/src/capstonenext/arch/SystemZ/SystemZMCTargetDesc.c
Line  | Count  | Source  | 
1  |  | /* Capstone Disassembly Engine, http://www.capstone-engine.org */  | 
2  |  | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */  | 
3  |  | /*    Rot127 <unisono@quyllur.org> 2022-2023 */  | 
4  |  | /* Automatically translated source file from LLVM. */  | 
5  |  |  | 
6  |  | /* LLVM-commit: <commit> */  | 
7  |  | /* LLVM-tag: <tag> */  | 
8  |  |  | 
9  |  | /* Only small edits allowed. */  | 
10  |  | /* For multiple similar edits, please create a Patch for the translator. */  | 
11  |  |  | 
12  |  | /* Capstone's C++ file translator: */  | 
13  |  | /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */  | 
14  |  |  | 
15  |  | //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//  | 
16  |  | //  | 
17  |  | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.  | 
18  |  | // See https://llvm.org/LICENSE.txt for license information.  | 
19  |  | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception  | 
20  |  | //  | 
21  |  | //===----------------------------------------------------------------------===//  | 
22  |  |  | 
23  |  | #include <stdio.h>  | 
24  |  | #include <string.h>  | 
25  |  | #include <stdlib.h>  | 
26  |  | #include <capstone/platform.h>  | 
27  |  |  | 
28  |  | #include "../../MCInst.h"  | 
29  |  | #include "../../MCRegisterInfo.h"  | 
30  |  | #include "SystemZMCTargetDesc.h"  | 
31  |  | #include "SystemZInstPrinter.h"  | 
32  |  |  | 
33  |  | #define GET_INSTRINFO_MC_DESC  | 
34  |  | #define ENABLE_INSTR_PREDICATE_VERIFIER  | 
35  |  | #include "SystemZGenInstrInfo.inc"  | 
36  |  |  | 
37  |  | #define GET_SUBTARGETINFO_MC_DESC  | 
38  |  | #include "SystemZGenSubtargetInfo.inc"  | 
39  |  |  | 
40  |  | #define GET_REGINFO_MC_DESC  | 
41  |  | #include "SystemZGenRegisterInfo.inc"  | 
42  |  | #define CONCAT(a, b) CONCAT_(a, b)  | 
43  |  | #define CONCAT_(a, b) a##_##b  | 
44  |  |  | 
45  |  | const unsigned SystemZMC_GR32Regs[16] = { | 
46  |  |   SystemZ_R0L,  SystemZ_R1L,  SystemZ_R2L,  SystemZ_R3L,  | 
47  |  |   SystemZ_R4L,  SystemZ_R5L,  SystemZ_R6L,  SystemZ_R7L,  | 
48  |  |   SystemZ_R8L,  SystemZ_R9L,  SystemZ_R10L, SystemZ_R11L,  | 
49  |  |   SystemZ_R12L, SystemZ_R13L, SystemZ_R14L, SystemZ_R15L  | 
50  |  | };  | 
51  |  |  | 
52  |  | const unsigned SystemZMC_GRH32Regs[16] = { | 
53  |  |   SystemZ_R0H,  SystemZ_R1H,  SystemZ_R2H,  SystemZ_R3H,  | 
54  |  |   SystemZ_R4H,  SystemZ_R5H,  SystemZ_R6H,  SystemZ_R7H,  | 
55  |  |   SystemZ_R8H,  SystemZ_R9H,  SystemZ_R10H, SystemZ_R11H,  | 
56  |  |   SystemZ_R12H, SystemZ_R13H, SystemZ_R14H, SystemZ_R15H  | 
57  |  | };  | 
58  |  |  | 
59  |  | const unsigned SystemZMC_GR64Regs[16] = { | 
60  |  |   SystemZ_R0D,  SystemZ_R1D,  SystemZ_R2D,  SystemZ_R3D,  | 
61  |  |   SystemZ_R4D,  SystemZ_R5D,  SystemZ_R6D,  SystemZ_R7D,  | 
62  |  |   SystemZ_R8D,  SystemZ_R9D,  SystemZ_R10D, SystemZ_R11D,  | 
63  |  |   SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D  | 
64  |  | };  | 
65  |  |  | 
66  |  | const unsigned SystemZMC_GR128Regs[16] = { SystemZ_R0Q,  0, SystemZ_R2Q,  0, | 
67  |  |              SystemZ_R4Q,  0, SystemZ_R6Q,  0,  | 
68  |  |              SystemZ_R8Q,  0, SystemZ_R10Q, 0,  | 
69  |  |              SystemZ_R12Q, 0, SystemZ_R14Q, 0 };  | 
70  |  |  | 
71  |  | const unsigned SystemZMC_FP32Regs[16] = { | 
72  |  |   SystemZ_F0S,  SystemZ_F1S,  SystemZ_F2S,  SystemZ_F3S,  | 
73  |  |   SystemZ_F4S,  SystemZ_F5S,  SystemZ_F6S,  SystemZ_F7S,  | 
74  |  |   SystemZ_F8S,  SystemZ_F9S,  SystemZ_F10S, SystemZ_F11S,  | 
75  |  |   SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S  | 
76  |  | };  | 
77  |  |  | 
78  |  | const unsigned SystemZMC_FP64Regs[16] = { | 
79  |  |   SystemZ_F0D,  SystemZ_F1D,  SystemZ_F2D,  SystemZ_F3D,  | 
80  |  |   SystemZ_F4D,  SystemZ_F5D,  SystemZ_F6D,  SystemZ_F7D,  | 
81  |  |   SystemZ_F8D,  SystemZ_F9D,  SystemZ_F10D, SystemZ_F11D,  | 
82  |  |   SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D  | 
83  |  | };  | 
84  |  |  | 
85  |  | const unsigned SystemZMC_FP128Regs[16] = { SystemZ_F0Q,  SystemZ_F1Q,  0, 0, | 
86  |  |              SystemZ_F4Q,  SystemZ_F5Q,  0, 0,  | 
87  |  |              SystemZ_F8Q,  SystemZ_F9Q,  0, 0,  | 
88  |  |              SystemZ_F12Q, SystemZ_F13Q, 0, 0 };  | 
89  |  |  | 
90  |  | const unsigned SystemZMC_VR32Regs[32] = { | 
91  |  |   SystemZ_F0S,  SystemZ_F1S,  SystemZ_F2S,  SystemZ_F3S,  SystemZ_F4S,  | 
92  |  |   SystemZ_F5S,  SystemZ_F6S,  SystemZ_F7S,  SystemZ_F8S,  SystemZ_F9S,  | 
93  |  |   SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S,  | 
94  |  |   SystemZ_F15S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S,  | 
95  |  |   SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S,  | 
96  |  |   SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S,  | 
97  |  |   SystemZ_F30S, SystemZ_F31S  | 
98  |  | };  | 
99  |  |  | 
100  |  | const unsigned SystemZMC_VR64Regs[32] = { | 
101  |  |   SystemZ_F0D,  SystemZ_F1D,  SystemZ_F2D,  SystemZ_F3D,  SystemZ_F4D,  | 
102  |  |   SystemZ_F5D,  SystemZ_F6D,  SystemZ_F7D,  SystemZ_F8D,  SystemZ_F9D,  | 
103  |  |   SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D,  | 
104  |  |   SystemZ_F15D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D,  | 
105  |  |   SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D,  | 
106  |  |   SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D,  | 
107  |  |   SystemZ_F30D, SystemZ_F31D  | 
108  |  | };  | 
109  |  |  | 
110  |  | const unsigned SystemZMC_VR128Regs[32] = { | 
111  |  |   SystemZ_V0,  SystemZ_V1,  SystemZ_V2,  SystemZ_V3,  SystemZ_V4,  | 
112  |  |   SystemZ_V5,  SystemZ_V6,  SystemZ_V7,  SystemZ_V8,  SystemZ_V9,  | 
113  |  |   SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14,  | 
114  |  |   SystemZ_V15, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19,  | 
115  |  |   SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24,  | 
116  |  |   SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29,  | 
117  |  |   SystemZ_V30, SystemZ_V31  | 
118  |  | };  | 
119  |  |  | 
120  |  | const unsigned SystemZMC_AR32Regs[16] = { SystemZ_A0,  SystemZ_A1,  SystemZ_A2, | 
121  |  |             SystemZ_A3,  SystemZ_A4,  SystemZ_A5,  | 
122  |  |             SystemZ_A6,  SystemZ_A7,  SystemZ_A8,  | 
123  |  |             SystemZ_A9,  SystemZ_A10, SystemZ_A11,  | 
124  |  |             SystemZ_A12, SystemZ_A13, SystemZ_A14,  | 
125  |  |             SystemZ_A15 };  | 
126  |  |  | 
127  |  | const unsigned SystemZMC_CR64Regs[16] = { SystemZ_C0,  SystemZ_C1,  SystemZ_C2, | 
128  |  |             SystemZ_C3,  SystemZ_C4,  SystemZ_C5,  | 
129  |  |             SystemZ_C6,  SystemZ_C7,  SystemZ_C8,  | 
130  |  |             SystemZ_C9,  SystemZ_C10, SystemZ_C11,  | 
131  |  |             SystemZ_C12, SystemZ_C13, SystemZ_C14,  | 
132  |  |             SystemZ_C15 };  | 
133  |  |  | 
134  |  | unsigned SystemZMC_getFirstReg(unsigned Reg)  | 
135  | 0  | { | 
136  | 0  |   static unsigned Map[NUM_TARGET_REGS];  | 
137  | 0  |   static bool Initialized = false;  | 
138  | 0  |   if (!Initialized) { | 
139  | 0  |     for (unsigned I = 0; I < 16; ++I) { | 
140  | 0  |       Map[SystemZMC_GR32Regs[I]] = I;  | 
141  | 0  |       Map[SystemZMC_GRH32Regs[I]] = I;  | 
142  | 0  |       Map[SystemZMC_GR64Regs[I]] = I;  | 
143  | 0  |       Map[SystemZMC_GR128Regs[I]] = I;  | 
144  | 0  |       Map[SystemZMC_FP128Regs[I]] = I;  | 
145  | 0  |       Map[SystemZMC_AR32Regs[I]] = I;  | 
146  | 0  |     }  | 
147  | 0  |     for (unsigned I = 0; I < 32; ++I) { | 
148  | 0  |       Map[SystemZMC_VR32Regs[I]] = I;  | 
149  | 0  |       Map[SystemZMC_VR64Regs[I]] = I;  | 
150  | 0  |       Map[SystemZMC_VR128Regs[I]] = I;  | 
151  | 0  |     }  | 
152  | 0  |   }  | 
153  | 0  |   CS_ASSERT((Reg < NUM_TARGET_REGS));  | 
154  | 0  |   return Map[Reg];  | 
155  | 0  | }  | 
156  |  |  | 
157  |  | // end namespace  |