/src/capstonev5/arch/RISCV/RISCVBaseInfo.h
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1 | | //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file contains small standalone enum definitions for the RISCV target |
11 | | // useful for the compiler back-end and the MC libraries. |
12 | | // |
13 | | //===----------------------------------------------------------------------===// |
14 | | #ifndef CS_RISCVBASEINFO_H |
15 | | #define CS_RISCVBASEINFO_H |
16 | | #include "../../cs_priv.h" |
17 | | |
18 | | //#include "RISCVMCTargetDesc.h" |
19 | | |
20 | | // RISCVII - This namespace holds all of the target specific flags that |
21 | | // instruction info tracks. All definitions must match RISCVInstrFormats.td. |
22 | | enum { |
23 | | IRISCVII_InstFormatPseudo = 0, |
24 | | IRISCVII_InstFormatR = 1, |
25 | | IRISCVII_InstFormatR4 = 2, |
26 | | IRISCVII_InstFormatI = 3, |
27 | | IRISCVII_InstFormatS = 4, |
28 | | IRISCVII_InstFormatB = 5, |
29 | | IRISCVII_InstFormatU = 6, |
30 | | IRISCVII_InstFormatJ = 7, |
31 | | IRISCVII_InstFormatCR = 8, |
32 | | IRISCVII_InstFormatCI = 9, |
33 | | IRISCVII_InstFormatCSS = 10, |
34 | | IRISCVII_InstFormatCIW = 11, |
35 | | IRISCVII_InstFormatCL = 12, |
36 | | IRISCVII_InstFormatCS = 13, |
37 | | IRISCVII_InstFormatCA = 14, |
38 | | IRISCVII_InstFormatCB = 15, |
39 | | IRISCVII_InstFormatCJ = 16, |
40 | | IRISCVII_InstFormatOther = 17, |
41 | | |
42 | | IRISCVII_InstFormatMask = 31 |
43 | | }; |
44 | | |
45 | | enum { |
46 | | RISCVII_MO_None, |
47 | | RISCVII_MO_LO, |
48 | | RISCVII_MO_HI, |
49 | | RISCVII_MO_PCREL_HI, |
50 | | }; |
51 | | |
52 | | // Describes the predecessor/successor bits used in the FENCE instruction. |
53 | | enum FenceField { |
54 | | RISCVFenceField_I = 8, |
55 | | RISCVFenceField_O = 4, |
56 | | RISCVFenceField_R = 2, |
57 | | RISCVFenceField_W = 1 |
58 | | }; |
59 | | |
60 | | // Describes the supported floating point rounding mode encodings. |
61 | | enum RoundingMode { |
62 | | RISCVFPRndMode_RNE = 0, |
63 | | RISCVFPRndMode_RTZ = 1, |
64 | | RISCVFPRndMode_RDN = 2, |
65 | | RISCVFPRndMode_RUP = 3, |
66 | | RISCVFPRndMode_RMM = 4, |
67 | | RISCVFPRndMode_DYN = 7, |
68 | | RISCVFPRndMode_Invalid |
69 | | }; |
70 | | |
71 | | inline static const char *roundingModeToString(enum RoundingMode RndMode) |
72 | 24.7k | { |
73 | 24.7k | switch (RndMode) { |
74 | 0 | default: |
75 | 0 | CS_ASSERT(0 && "Unknown floating point rounding mode"); |
76 | 6.60k | case RISCVFPRndMode_RNE: |
77 | 6.60k | return "rne"; |
78 | 5.65k | case RISCVFPRndMode_RTZ: |
79 | 5.65k | return "rtz"; |
80 | 3.43k | case RISCVFPRndMode_RDN: |
81 | 3.43k | return "rdn"; |
82 | 4.59k | case RISCVFPRndMode_RUP: |
83 | 4.59k | return "rup"; |
84 | 4.49k | case RISCVFPRndMode_RMM: |
85 | 4.49k | return "rmm"; |
86 | 0 | case RISCVFPRndMode_DYN: |
87 | 0 | return "dyn"; |
88 | 24.7k | } |
89 | 24.7k | } Unexecuted instantiation: RISCVDisassembler.c:roundingModeToString RISCVInstPrinter.c:roundingModeToString Line | Count | Source | 72 | 24.7k | { | 73 | 24.7k | switch (RndMode) { | 74 | 0 | default: | 75 | 0 | CS_ASSERT(0 && "Unknown floating point rounding mode"); | 76 | 6.60k | case RISCVFPRndMode_RNE: | 77 | 6.60k | return "rne"; | 78 | 5.65k | case RISCVFPRndMode_RTZ: | 79 | 5.65k | return "rtz"; | 80 | 3.43k | case RISCVFPRndMode_RDN: | 81 | 3.43k | return "rdn"; | 82 | 4.59k | case RISCVFPRndMode_RUP: | 83 | 4.59k | return "rup"; | 84 | 4.49k | case RISCVFPRndMode_RMM: | 85 | 4.49k | return "rmm"; | 86 | 0 | case RISCVFPRndMode_DYN: | 87 | 0 | return "dyn"; | 88 | 24.7k | } | 89 | 24.7k | } |
|
90 | | |
91 | | inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode) |
92 | 42.9k | { |
93 | 42.9k | switch (Mode) { |
94 | 29 | default: |
95 | 29 | return false; |
96 | 6.60k | case RISCVFPRndMode_RNE: |
97 | 12.2k | case RISCVFPRndMode_RTZ: |
98 | 15.6k | case RISCVFPRndMode_RDN: |
99 | 20.2k | case RISCVFPRndMode_RUP: |
100 | 24.7k | case RISCVFPRndMode_RMM: |
101 | 42.8k | case RISCVFPRndMode_DYN: |
102 | | return true; |
103 | 42.9k | } |
104 | 42.9k | } RISCVDisassembler.c:RISCVFPRndMode_isValidRoundingMode Line | Count | Source | 92 | 42.9k | { | 93 | 42.9k | switch (Mode) { | 94 | 29 | default: | 95 | 29 | return false; | 96 | 6.60k | case RISCVFPRndMode_RNE: | 97 | 12.2k | case RISCVFPRndMode_RTZ: | 98 | 15.6k | case RISCVFPRndMode_RDN: | 99 | 20.2k | case RISCVFPRndMode_RUP: | 100 | 24.7k | case RISCVFPRndMode_RMM: | 101 | 42.8k | case RISCVFPRndMode_DYN: | 102 | | return true; | 103 | 42.9k | } | 104 | 42.9k | } |
Unexecuted instantiation: RISCVInstPrinter.c:RISCVFPRndMode_isValidRoundingMode |
105 | | |
106 | | #endif |