/src/capstonenext/arch/TMS320C64x/TMS320C64xDisassembler.c

Source
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */

#ifdef CAPSTONE_HAS_TMS320C64X

#include <string.h>

#include "../../cs_priv.h"
#include "../../utils.h"

#include "TMS320C64xDisassembler.h"

#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../MCRegisterInfo.h"
#include "../../MCDisassembler.h"
#include "../../MathExtras.h"

static uint64_t getFeatureBits(int mode);

static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
                uint64_t Address, void *Decoder);

static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
               uint64_t Address,
               void *Decoder);

static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address,
        void *Decoder);

static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address,
         void *Decoder);

static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder);

static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder);

static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
               uint64_t Address, void *Decoder);

static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
           uint64_t Address, void *Decoder);

static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
           uint64_t Address, void *Decoder);

static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
               uint64_t Address, void *Decoder);

static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder);

static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address,
             void *Decoder);

static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address,
           void *Decoder);

static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address,
            void *Decoder);

#include "TMS320C64xGenDisassemblerTables.inc"

#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "TMS320C64xGenRegisterInfo.inc"

static const unsigned GPRegsDecoderTable[] = {
  TMS320C64x_A0,  TMS320C64x_A1,  TMS320C64x_A2,  TMS320C64x_A3,
  TMS320C64x_A4,  TMS320C64x_A5,  TMS320C64x_A6,  TMS320C64x_A7,
  TMS320C64x_A8,  TMS320C64x_A9,  TMS320C64x_A10, TMS320C64x_A11,
  TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15,
  TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19,
  TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23,
  TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27,
  TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31
};

static const unsigned ControlRegsDecoderTable[] = { TMS320C64x_AMR,
                TMS320C64x_CSR,
                TMS320C64x_ISR,
                TMS320C64x_ICR,
                TMS320C64x_IER,
                TMS320C64x_ISTP,
                TMS320C64x_IRP,
                TMS320C64x_NRP,
                ~0U,
                ~0U,
                TMS320C64x_TSCL,
                TMS320C64x_TSCH,
                ~0U,
                TMS320C64x_ILC,
                TMS320C64x_RILC,
                TMS320C64x_REP,
                TMS320C64x_PCE1,
                TMS320C64x_DNUM,
                ~0U,
                ~0U,
                ~0U,
                TMS320C64x_SSR,
                TMS320C64x_GPLYA,
                TMS320C64x_GPLYB,
                TMS320C64x_GFPGFR,
                TMS320C64x_DIER,
                TMS320C64x_TSR,
                TMS320C64x_ITSR,
                TMS320C64x_NTSR,
                TMS320C64x_ECR,
                ~0U,
                TMS320C64x_IERR };

static uint64_t getFeatureBits(int mode)
{
  // support everything
  return (uint64_t)-1;
}

static unsigned getReg(const unsigned *RegTable, unsigned RegNo)
{
  if (RegNo > 31)
    return ~0U;
  return RegTable[RegNo];
}

static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
                uint64_t Address, void *Decoder)
{
  unsigned Reg;

  if (RegNo > 31)
    return MCDisassembler_Fail;

  Reg = getReg(GPRegsDecoderTable, RegNo);
  if (Reg == ~0U)
    return MCDisassembler_Fail;
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
               uint64_t Address,
               void *Decoder)
{
  unsigned Reg;

  if (RegNo > 31)
    return MCDisassembler_Fail;

  Reg = getReg(ControlRegsDecoderTable, RegNo);
  if (Reg == ~0U)
    return MCDisassembler_Fail;
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address,
        void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 5 bit value */
  if (imm & (1 << (5 - 1)))
    imm |= ~((1 << 5) - 1);

  MCOperand_CreateImm0(Inst, imm);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address,
         void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 16 bit value */
  if (imm & (1 << (16 - 1)))
    imm |= ~((1 << 16) - 1);

  MCOperand_CreateImm0(Inst, imm);

  return MCDisassembler_Success;
}

static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 7 bit value */
  if (imm & (1 << (7 - 1)))
    imm |= ~((1 << 7) - 1);

  /* Address is relative to the address of the first instruction in the fetch packet */
  MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));

  return MCDisassembler_Success;
}

static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 10 bit value */
  if (imm & (1 << (10 - 1)))
    imm |= ~((1 << 10) - 1);

  /* Address is relative to the address of the first instruction in the fetch packet */
  MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));

  return MCDisassembler_Success;
}

static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 12 bit value */
  if (imm & (1 << (12 - 1)))
    imm |= ~((1 << 12) - 1);

  /* Address is relative to the address of the first instruction in the fetch packet */
  MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));

  return MCDisassembler_Success;
}

static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 21 bit value */
  if (imm & (1 << (21 - 1)))
    imm |= ~((1 << 21) - 1);

  /* Address is relative to the address of the first instruction in the fetch packet */
  MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));

  return MCDisassembler_Success;
}

static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder)
{
  return DecodeMemOperandSc(Inst, Val | (1 << 15), Address, Decoder);
}

static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
               uint64_t Address, void *Decoder)
{
  uint8_t scaled, base, offset, mode, unit;
  unsigned basereg, offsetreg;

  scaled = (Val >> 15) & 1;
  base = (Val >> 10) & 0x1f;
  offset = (Val >> 5) & 0x1f;
  mode = (Val >> 1) & 0xf;
  unit = Val & 1;

  if ((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31))
    base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
  // base cannot be a B register, because it was ANDed above with 0x1f.
  // And the TMS320C64X_REG_B0 > 31
  basereg = getReg(GPRegsDecoderTable, base);
  if (basereg == ~0U)
    return MCDisassembler_Fail;

  switch (mode) {
  case 0:
  case 1:
  case 8:
  case 9:
  case 10:
  case 11:
    MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) |
               (offset << 5) | (mode << 1) |
               unit);
    break;
  case 4:
  case 5:
  case 12:
  case 13:
  case 14:
  case 15:
    if ((offset >= TMS320C64X_REG_A0) &&
        (offset <= TMS320C64X_REG_A31))
      offset = (offset - TMS320C64X_REG_A0 +
          TMS320C64X_REG_B0);
    // offset cannot be a B register, because it was ANDed above with 0x1f.
    // And the TMS320C64X_REG_B0 > 31
    offsetreg = getReg(GPRegsDecoderTable, offset);
    if (offsetreg == ~0U)
      return MCDisassembler_Fail;
    MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) |
               (offsetreg << 5) |
               (mode << 1) | unit);
    break;
  default:
    return MCDisassembler_Fail;
  }

  return MCDisassembler_Success;
}

static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  uint16_t offset;
  unsigned basereg;

  if (Val & 1)
    basereg = TMS320C64X_REG_B15;
  else
    basereg = TMS320C64X_REG_B14;

  offset = (Val >> 1) & 0x7fff;
  MCOperand_CreateImm0(Inst, (offset << 7) | basereg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
           uint64_t Address, void *Decoder)
{
  unsigned Reg;

  if (RegNo > 31)
    return MCDisassembler_Fail;

  Reg = getReg(GPRegsDecoderTable, RegNo);
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
           uint64_t Address, void *Decoder)
{
  unsigned Reg;

  if (RegNo > 15)
    return MCDisassembler_Fail;

  Reg = getReg(GPRegsDecoderTable, RegNo << 1);
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
               uint64_t Address, void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
  case 7:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_INVALID;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_B0;
    break;
  case 2:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_B1;
    break;
  case 3:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_B2;
    break;
  case 4:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_A1;
    break;
  case 5:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_A2;
    break;
  case 6:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_A0;
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_INVALID;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.condition.zero = 1;
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address,
             void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;
  MCOperand *op;
  int i;

  /* This is pretty messy, probably we should find a better way */
  if (Val == 1) {
    for (i = 0; i < Inst->size; i++) {
      op = &Inst->Operands[i];
      if (op->Kind == kRegister) {
        if ((op->RegVal >= TMS320C64X_REG_A0) &&
            (op->RegVal <= TMS320C64X_REG_A31))
          op->RegVal = (op->RegVal -
                  TMS320C64X_REG_A0 +
                  TMS320C64X_REG_B0);
        else if ((op->RegVal >= TMS320C64X_REG_B0) &&
           (op->RegVal <= TMS320C64X_REG_B31))
          op->RegVal = (op->RegVal -
                  TMS320C64X_REG_B0 +
                  TMS320C64X_REG_A0);
      }
    }
  }

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.funit.side = 1;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.funit.side = 2;
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.funit.side = 0;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address,
           void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.parallel = 0;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.parallel = 1;
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.parallel = -1;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;
  MCOperand *op;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
    op = &Inst->Operands[0];
    if (op->Kind == kRegister) {
      if ((op->RegVal >= TMS320C64X_REG_A0) &&
          (op->RegVal <= TMS320C64X_REG_A31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
                TMS320C64X_REG_B0);
      else if ((op->RegVal >= TMS320C64X_REG_B0) &&
         (op->RegVal <= TMS320C64X_REG_B31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
                TMS320C64X_REG_A0);
    }
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;
  MCOperand *op;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
    op = &Inst->Operands[1];
    if (op->Kind == kRegister) {
      if ((op->RegVal >= TMS320C64X_REG_A0) &&
          (op->RegVal <= TMS320C64X_REG_A31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
                TMS320C64X_REG_B0);
      else if ((op->RegVal >= TMS320C64X_REG_B0) &&
         (op->RegVal <= TMS320C64X_REG_B31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
                TMS320C64X_REG_A0);
    }
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;
  MCOperand *op;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 2;
    op = &Inst->Operands[2];
    if (op->Kind == kRegister) {
      if ((op->RegVal >= TMS320C64X_REG_A0) &&
          (op->RegVal <= TMS320C64X_REG_A31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
                TMS320C64X_REG_B0);
      else if ((op->RegVal >= TMS320C64X_REG_B0) &&
         (op->RegVal <= TMS320C64X_REG_B31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
                TMS320C64X_REG_A0);
    }
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address,
            void *Decoder)
{
  MCOperand_CreateImm0(Inst, Val + 1);

  return MCDisassembler_Success;
}

#define GET_INSTRINFO_ENUM
#include "TMS320C64xGenInstrInfo.inc"

bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len,
             MCInst *MI, uint16_t *size, uint64_t address,
             void *info)
{
  uint32_t insn;
  DecodeStatus result;

  if (code_len < 4) {
    *size = 0;
    return MCDisassembler_Fail;
  }

  if (MI->flat_insn->detail)
    memset(MI->flat_insn->detail, 0,
           offsetof(cs_detail, tms320c64x) + sizeof(cs_tms320c64x));

  insn = readBytes32(MI, code);
  result =
    decodeInstruction_4(DecoderTable32, MI, insn, address, info, 0);

  if (result == MCDisassembler_Success) {
    *size = 4;
    return true;
  }

  MCInst_clear(MI);
  *size = 0;
  return false;
}

void TMS320C64x_init(MCRegisterInfo *MRI)
{
  MCRegisterInfo_InitMCRegisterInfo(MRI, TMS320C64xRegDesc, 90, 0, 0,
            TMS320C64xMCRegisterClasses, 7, 0, 0,
            TMS320C64xRegDiffLists, 0,
            TMS320C64xSubRegIdxLists, 1, 0);
}

#endif

Coverage Report

Created: 2025-11-09 07:00

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3
4		#ifdef CAPSTONE_HAS_TMS320C64X
5
6		#include <string.h>
7
8		#include "../../cs_priv.h"
9		#include "../../utils.h"
10
11		#include "TMS320C64xDisassembler.h"
12
13		#include "../../MCInst.h"
14		#include "../../MCInstrDesc.h"
15		#include "../../MCFixedLenDisassembler.h"
16		#include "../../MCRegisterInfo.h"
17		#include "../../MCDisassembler.h"
18		#include "../../MathExtras.h"
19
20		static uint64_t getFeatureBits(int mode);
21
22		static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
23		uint64_t Address, void *Decoder);
24
25		static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
26		uint64_t Address,
27		void *Decoder);
28
29		static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address,
30		void *Decoder);
31
32		static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address,
33		void *Decoder);
34
35		static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
36		uint64_t Address, void *Decoder);
37
38		static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
39		uint64_t Address, void *Decoder);
40
41		static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
42		uint64_t Address, void *Decoder);
43
44		static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
45		uint64_t Address, void *Decoder);
46
47		static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
48		uint64_t Address, void *Decoder);
49
50		static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
51		uint64_t Address, void *Decoder);
52
53		static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
54		uint64_t Address, void *Decoder);
55
56		static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
57		uint64_t Address, void *Decoder);
58
59		static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
60		uint64_t Address, void *Decoder);
61
62		static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
63		uint64_t Address, void *Decoder);
64
65		static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
66		uint64_t Address, void *Decoder);
67
68		static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address,
69		void *Decoder);
70
71		static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address,
72		void *Decoder);
73
74		static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
75		uint64_t Address, void *Decoder);
76
77		static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
78		uint64_t Address, void *Decoder);
79
80		static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
81		uint64_t Address, void *Decoder);
82
83		static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address,
84		void *Decoder);
85
86		#include "TMS320C64xGenDisassemblerTables.inc"
87
88		#define GET_REGINFO_ENUM
89		#define GET_REGINFO_MC_DESC
90		#include "TMS320C64xGenRegisterInfo.inc"
91
92		static const unsigned GPRegsDecoderTable[] = {
93		TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3,
94		TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7,
95		TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11,
96		TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15,
97		TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19,
98		TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23,
99		TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27,
100		TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31
101		};
102
103		static const unsigned ControlRegsDecoderTable[] = { TMS320C64x_AMR,
104		TMS320C64x_CSR,
105		TMS320C64x_ISR,
106		TMS320C64x_ICR,
107		TMS320C64x_IER,
108		TMS320C64x_ISTP,
109		TMS320C64x_IRP,
110		TMS320C64x_NRP,
111		~0U,
112		~0U,
113		TMS320C64x_TSCL,
114		TMS320C64x_TSCH,
115		~0U,
116		TMS320C64x_ILC,
117		TMS320C64x_RILC,
118		TMS320C64x_REP,
119		TMS320C64x_PCE1,
120		TMS320C64x_DNUM,
121		~0U,
122		~0U,
123		~0U,
124		TMS320C64x_SSR,
125		TMS320C64x_GPLYA,
126		TMS320C64x_GPLYB,
127		TMS320C64x_GFPGFR,
128		TMS320C64x_DIER,
129		TMS320C64x_TSR,
130		TMS320C64x_ITSR,
131		TMS320C64x_NTSR,
132		TMS320C64x_ECR,
133		~0U,
134		TMS320C64x_IERR };
135
136		static uint64_t getFeatureBits(int mode)
137	44.9k	{
138		// support everything
139	44.9k	return (uint64_t)-1;
140	44.9k	}
141
142		static unsigned getReg(const unsigned *RegTable, unsigned RegNo)
143	78.3k	{
144	78.3k	if (RegNo > 31)
145	22	return ~0U;
146	78.3k	return RegTable[RegNo];
147	78.3k	}
148
149		static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
150		uint64_t Address, void *Decoder)
151	54.9k	{
152	54.9k	unsigned Reg;
153
154	54.9k	if (RegNo > 31)
155	0	return MCDisassembler_Fail;
156
157	54.9k	Reg = getReg(GPRegsDecoderTable, RegNo);
158	54.9k	if (Reg == ~0U)
159	0	return MCDisassembler_Fail;
160	54.9k	MCOperand_CreateReg0(Inst, Reg);
161
162	54.9k	return MCDisassembler_Success;
163	54.9k	}
164
165		static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
166		uint64_t Address,
167		void *Decoder)
168	1.67k	{
169	1.67k	unsigned Reg;
170
171	1.67k	if (RegNo > 31)
172	0	return MCDisassembler_Fail;
173
174	1.67k	Reg = getReg(ControlRegsDecoderTable, RegNo);
175	1.67k	if (Reg == ~0U)
176	3	return MCDisassembler_Fail;
177	1.67k	MCOperand_CreateReg0(Inst, Reg);
178
179	1.67k	return MCDisassembler_Success;
180	1.67k	}
181
182		static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address,
183		void *Decoder)
184	8.57k	{
185	8.57k	int32_t imm;
186
187	8.57k	imm = Val;
188		/* Sign extend 5 bit value */
189	8.57k	if (imm & (1 << (5 - 1)))
190	3.27k	imm \|= ~((1 << 5) - 1);
191
192	8.57k	MCOperand_CreateImm0(Inst, imm);
193
194	8.57k	return MCDisassembler_Success;
195	8.57k	}
196
197		static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address,
198		void *Decoder)
199	2.12k	{
200	2.12k	int32_t imm;
201
202	2.12k	imm = Val;
203		/* Sign extend 16 bit value */
204	2.12k	if (imm & (1 << (16 - 1)))
205	1.53k	imm \|= ~((1 << 16) - 1);
206
207	2.12k	MCOperand_CreateImm0(Inst, imm);
208
209	2.12k	return MCDisassembler_Success;
210	2.12k	}
211
212		static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
213		uint64_t Address, void *Decoder)
214	670	{
215	670	int32_t imm;
216
217	670	imm = Val;
218		/* Sign extend 7 bit value */
219	670	if (imm & (1 << (7 - 1)))
220	563	imm \|= ~((1 << 7) - 1);
221
222		/* Address is relative to the address of the first instruction in the fetch packet */
223	670	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
224
225	670	return MCDisassembler_Success;
226	670	}
227
228		static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
229		uint64_t Address, void *Decoder)
230	893	{
231	893	int32_t imm;
232
233	893	imm = Val;
234		/* Sign extend 10 bit value */
235	893	if (imm & (1 << (10 - 1)))
236	224	imm \|= ~((1 << 10) - 1);
237
238		/* Address is relative to the address of the first instruction in the fetch packet */
239	893	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
240
241	893	return MCDisassembler_Success;
242	893	}
243
244		static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
245		uint64_t Address, void *Decoder)
246	1.11k	{
247	1.11k	int32_t imm;
248
249	1.11k	imm = Val;
250		/* Sign extend 12 bit value */
251	1.11k	if (imm & (1 << (12 - 1)))
252	477	imm \|= ~((1 << 12) - 1);
253
254		/* Address is relative to the address of the first instruction in the fetch packet */
255	1.11k	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
256
257	1.11k	return MCDisassembler_Success;
258	1.11k	}
259
260		static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
261		uint64_t Address, void *Decoder)
262	1.70k	{
263	1.70k	int32_t imm;
264
265	1.70k	imm = Val;
266		/* Sign extend 21 bit value */
267	1.70k	if (imm & (1 << (21 - 1)))
268	509	imm \|= ~((1 << 21) - 1);
269
270		/* Address is relative to the address of the first instruction in the fetch packet */
271	1.70k	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
272
273	1.70k	return MCDisassembler_Success;
274	1.70k	}
275
276		static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
277		uint64_t Address, void *Decoder)
278	3.60k	{
279	3.60k	return DecodeMemOperandSc(Inst, Val \| (1 << 15), Address, Decoder);
280	3.60k	}
281
282		static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
283		uint64_t Address, void *Decoder)
284	223	{
285	223	uint8_t scaled, base, offset, mode, unit;
286	223	unsigned basereg, offsetreg;
287
288	223	scaled = (Val >> 15) & 1;
289	223	base = (Val >> 10) & 0x1f;
290	223	offset = (Val >> 5) & 0x1f;
291	223	mode = (Val >> 1) & 0xf;
292	223	unit = Val & 1;
293
294	223	if ((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31))
295	0	base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
296		// base cannot be a B register, because it was ANDed above with 0x1f.
297		// And the TMS320C64X_REG_B0 > 31
298	223	basereg = getReg(GPRegsDecoderTable, base);
299	223	if (basereg == ~0U)
300	0	return MCDisassembler_Fail;
301
302	223	switch (mode) {
303	70	case 0:
304	120	case 1:
305	124	case 8:
306	128	case 9:
307	169	case 10:
308	194	case 11:
309	194	MCOperand_CreateImm0(Inst, (scaled << 19) \| (basereg << 12) \|
310	194	(offset << 5) \| (mode << 1) \|
311	194	unit);
312	194	break;
313	2	case 4:
314	3	case 5:
315	16	case 12:
316	16	case 13:
317	26	case 14:
318	29	case 15:
319	29	if ((offset >= TMS320C64X_REG_A0) &&
320	2	(offset <= TMS320C64X_REG_A31))
321	2	offset = (offset - TMS320C64X_REG_A0 +
322	2	TMS320C64X_REG_B0);
323		// offset cannot be a B register, because it was ANDed above with 0x1f.
324		// And the TMS320C64X_REG_B0 > 31
325	29	offsetreg = getReg(GPRegsDecoderTable, offset);
326	29	if (offsetreg == ~0U)
327	2	return MCDisassembler_Fail;
328	27	MCOperand_CreateImm0(Inst, (scaled << 19) \| (basereg << 12) \|
329	27	(offsetreg << 5) \|
330	27	(mode << 1) \| unit);
331	27	break;
332	0	default:
333	0	return MCDisassembler_Fail;
334	223	}
335
336	221	return MCDisassembler_Success;
337	223	}
338
339		static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
340		uint64_t Address, void *Decoder)
341	3.15k	{
342	3.15k	uint16_t offset;
343	3.15k	unsigned basereg;
344
345	3.15k	if (Val & 1)
346	1.82k	basereg = TMS320C64X_REG_B15;
347	1.32k	else
348	1.32k	basereg = TMS320C64X_REG_B14;
349
350	3.15k	offset = (Val >> 1) & 0x7fff;
351	3.15k	MCOperand_CreateImm0(Inst, (offset << 7) \| basereg);
352
353	3.15k	return MCDisassembler_Success;
354	3.15k	}
355
356		static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
357		uint64_t Address, void *Decoder)
358	14.4k	{
359	14.4k	unsigned Reg;
360
361	14.4k	if (RegNo > 31)
362	0	return MCDisassembler_Fail;
363
364	14.4k	Reg = getReg(GPRegsDecoderTable, RegNo);
365	14.4k	MCOperand_CreateReg0(Inst, Reg);
366
367	14.4k	return MCDisassembler_Success;
368	14.4k	}
369
370		static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
371		uint64_t Address, void *Decoder)
372	862	{
373	862	unsigned Reg;
374
375	862	if (RegNo > 15)
376	0	return MCDisassembler_Fail;
377
378	862	Reg = getReg(GPRegsDecoderTable, RegNo << 1);
379	862	MCOperand_CreateReg0(Inst, Reg);
380
381	862	return MCDisassembler_Success;
382	862	}
383
384		static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
385		uint64_t Address, void *Decoder)
386	44.7k	{
387	44.7k	DecodeStatus ret = MCDisassembler_Success;
388
389	44.7k	if (!Inst->flat_insn->detail)
390	0	return MCDisassembler_Success;
391
392	44.7k	switch (Val) {
393	9.35k	case 0:
394	14.5k	case 7:
395	14.5k	Inst->flat_insn->detail->tms320c64x.condition.reg =
396	14.5k	TMS320C64X_REG_INVALID;
397	14.5k	break;
398	6.08k	case 1:
399	6.08k	Inst->flat_insn->detail->tms320c64x.condition.reg =
400	6.08k	TMS320C64X_REG_B0;
401	6.08k	break;
402	5.43k	case 2:
403	5.43k	Inst->flat_insn->detail->tms320c64x.condition.reg =
404	5.43k	TMS320C64X_REG_B1;
405	5.43k	break;
406	4.63k	case 3:
407	4.63k	Inst->flat_insn->detail->tms320c64x.condition.reg =
408	4.63k	TMS320C64X_REG_B2;
409	4.63k	break;
410	3.87k	case 4:
411	3.87k	Inst->flat_insn->detail->tms320c64x.condition.reg =
412	3.87k	TMS320C64X_REG_A1;
413	3.87k	break;
414	6.63k	case 5:
415	6.63k	Inst->flat_insn->detail->tms320c64x.condition.reg =
416	6.63k	TMS320C64X_REG_A2;
417	6.63k	break;
418	3.53k	case 6:
419	3.53k	Inst->flat_insn->detail->tms320c64x.condition.reg =
420	3.53k	TMS320C64X_REG_A0;
421	3.53k	break;
422	0	default:
423	0	Inst->flat_insn->detail->tms320c64x.condition.reg =
424	0	TMS320C64X_REG_INVALID;
425	0	ret = MCDisassembler_Fail;
426	0	break;
427	44.7k	}
428
429	44.7k	return ret;
430	44.7k	}
431
432		static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
433		uint64_t Address, void *Decoder)
434	44.7k	{
435	44.7k	DecodeStatus ret = MCDisassembler_Success;
436
437	44.7k	if (!Inst->flat_insn->detail)
438	0	return MCDisassembler_Success;
439
440	44.7k	switch (Val) {
441	24.4k	case 0:
442	24.4k	Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
443	24.4k	break;
444	20.3k	case 1:
445	20.3k	Inst->flat_insn->detail->tms320c64x.condition.zero = 1;
446	20.3k	break;
447	0	default:
448	0	Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
449	0	ret = MCDisassembler_Fail;
450	0	break;
451	44.7k	}
452
453	44.7k	return ret;
454	44.7k	}
455
456		static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address,
457		void *Decoder)
458	44.7k	{
459	44.7k	DecodeStatus ret = MCDisassembler_Success;
460	44.7k	MCOperand *op;
461	44.7k	int i;
462
463		/* This is pretty messy, probably we should find a better way */
464	44.7k	if (Val == 1) {
465	65.5k	for (i = 0; i < Inst->size; i++) {
466	45.9k	op = &Inst->Operands[i];
467	45.9k	if (op->Kind == kRegister) {
468	32.3k	if ((op->RegVal >= TMS320C64X_REG_A0) &&
469	30.9k	(op->RegVal <= TMS320C64X_REG_A31))
470	28.9k	op->RegVal = (op->RegVal -
471	28.9k	TMS320C64X_REG_A0 +
472	28.9k	TMS320C64X_REG_B0);
473	3.43k	else if ((op->RegVal >= TMS320C64X_REG_B0) &&
474	2.04k	(op->RegVal <= TMS320C64X_REG_B31))
475	1.90k	op->RegVal = (op->RegVal -
476	1.90k	TMS320C64X_REG_B0 +
477	1.90k	TMS320C64X_REG_A0);
478	32.3k	}
479	45.9k	}
480	19.6k	}
481
482	44.7k	if (!Inst->flat_insn->detail)
483	0	return MCDisassembler_Success;
484
485	44.7k	switch (Val) {
486	25.0k	case 0:
487	25.0k	Inst->flat_insn->detail->tms320c64x.funit.side = 1;
488	25.0k	break;
489	19.6k	case 1:
490	19.6k	Inst->flat_insn->detail->tms320c64x.funit.side = 2;
491	19.6k	break;
492	0	default:
493	0	Inst->flat_insn->detail->tms320c64x.funit.side = 0;
494	0	ret = MCDisassembler_Fail;
495	0	break;
496	44.7k	}
497
498	44.7k	return ret;
499	44.7k	}
500
501		static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address,
502		void *Decoder)
503	44.7k	{
504	44.7k	DecodeStatus ret = MCDisassembler_Success;
505
506	44.7k	if (!Inst->flat_insn->detail)
507	0	return MCDisassembler_Success;
508
509	44.7k	switch (Val) {
510	23.2k	case 0:
511	23.2k	Inst->flat_insn->detail->tms320c64x.parallel = 0;
512	23.2k	break;
513	21.4k	case 1:
514	21.4k	Inst->flat_insn->detail->tms320c64x.parallel = 1;
515	21.4k	break;
516	0	default:
517	0	Inst->flat_insn->detail->tms320c64x.parallel = -1;
518	0	ret = MCDisassembler_Fail;
519	0	break;
520	44.7k	}
521
522	44.7k	return ret;
523	44.7k	}
524
525		static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
526		uint64_t Address, void *Decoder)
527	672	{
528	672	DecodeStatus ret = MCDisassembler_Success;
529	672	MCOperand *op;
530
531	672	if (!Inst->flat_insn->detail)
532	0	return MCDisassembler_Success;
533
534	672	switch (Val) {
535	344	case 0:
536	344	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
537	344	break;
538	328	case 1:
539	328	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
540	328	op = &Inst->Operands[0];
541	328	if (op->Kind == kRegister) {
542	328	if ((op->RegVal >= TMS320C64X_REG_A0) &&
543	328	(op->RegVal <= TMS320C64X_REG_A31))
544	328	op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
545	328	TMS320C64X_REG_B0);
546	0	else if ((op->RegVal >= TMS320C64X_REG_B0) &&
547	0	(op->RegVal <= TMS320C64X_REG_B31))
548	0	op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
549	0	TMS320C64X_REG_A0);
550	328	}
551	328	break;
552	0	default:
553	0	Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
554	0	ret = MCDisassembler_Fail;
555	0	break;
556	672	}
557
558	672	return ret;
559	672	}
560
561		static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
562		uint64_t Address, void *Decoder)
563	14.8k	{
564	14.8k	DecodeStatus ret = MCDisassembler_Success;
565	14.8k	MCOperand *op;
566
567	14.8k	if (!Inst->flat_insn->detail)
568	0	return MCDisassembler_Success;
569
570	14.8k	switch (Val) {
571	7.60k	case 0:
572	7.60k	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
573	7.60k	break;
574	7.26k	case 1:
575	7.26k	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
576	7.26k	op = &Inst->Operands[1];
577	7.26k	if (op->Kind == kRegister) {
578	5.06k	if ((op->RegVal >= TMS320C64X_REG_A0) &&
579	3.75k	(op->RegVal <= TMS320C64X_REG_A31))
580	3.68k	op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
581	3.68k	TMS320C64X_REG_B0);
582	1.38k	else if ((op->RegVal >= TMS320C64X_REG_B0) &&
583	73	(op->RegVal <= TMS320C64X_REG_B31))
584	0	op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
585	0	TMS320C64X_REG_A0);
586	5.06k	}
587	7.26k	break;
588	0	default:
589	0	Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
590	0	ret = MCDisassembler_Fail;
591	0	break;
592	14.8k	}
593
594	14.8k	return ret;
595	14.8k	}
596
597		static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
598		uint64_t Address, void *Decoder)
599	8.47k	{
600	8.47k	DecodeStatus ret = MCDisassembler_Success;
601	8.47k	MCOperand *op;
602
603	8.47k	if (!Inst->flat_insn->detail)
604	0	return MCDisassembler_Success;
605
606	8.47k	switch (Val) {
607	3.34k	case 0:
608	3.34k	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
609	3.34k	break;
610	5.12k	case 1:
611	5.12k	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 2;
612	5.12k	op = &Inst->Operands[2];
613	5.12k	if (op->Kind == kRegister) {
614	2.19k	if ((op->RegVal >= TMS320C64X_REG_A0) &&
615	2.05k	(op->RegVal <= TMS320C64X_REG_A31))
616	1.74k	op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
617	1.74k	TMS320C64X_REG_B0);
618	450	else if ((op->RegVal >= TMS320C64X_REG_B0) &&
619	314	(op->RegVal <= TMS320C64X_REG_B31))
620	229	op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
621	229	TMS320C64X_REG_A0);
622	2.19k	}
623	5.12k	break;
624	0	default:
625	0	Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
626	0	ret = MCDisassembler_Fail;
627	0	break;
628	8.47k	}
629
630	8.47k	return ret;
631	8.47k	}
632
633		static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address,
634		void *Decoder)
635	1.25k	{
636	1.25k	MCOperand_CreateImm0(Inst, Val + 1);
637
638	1.25k	return MCDisassembler_Success;
639	1.25k	}
640
641		#define GET_INSTRINFO_ENUM
642		#include "TMS320C64xGenInstrInfo.inc"
643
644		bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len,
645		MCInst MI, uint16_t size, uint64_t address,
646		void *info)
647	45.4k	{
648	45.4k	uint32_t insn;
649	45.4k	DecodeStatus result;
650
651	45.4k	if (code_len < 4) {
652	476	*size = 0;
653	476	return MCDisassembler_Fail;
654	476	}
655
656	44.9k	if (MI->flat_insn->detail)
657	44.9k	memset(MI->flat_insn->detail, 0,
658	44.9k	offsetof(cs_detail, tms320c64x) + sizeof(cs_tms320c64x));
659
660	44.9k	insn = readBytes32(MI, code);
661	44.9k	result =
662	44.9k	decodeInstruction_4(DecoderTable32, MI, insn, address, info, 0);
663
664	44.9k	if (result == MCDisassembler_Success) {
665	44.7k	*size = 4;
666	44.7k	return true;
667	44.7k	}
668
669	210	MCInst_clear(MI);
670	210	*size = 0;
671	210	return false;
672	44.9k	}
673
674		void TMS320C64x_init(MCRegisterInfo *MRI)
675	1.41k	{
676	1.41k	MCRegisterInfo_InitMCRegisterInfo(MRI, TMS320C64xRegDesc, 90, 0, 0,
677	1.41k	TMS320C64xMCRegisterClasses, 7, 0, 0,
678	1.41k	TMS320C64xRegDiffLists, 0,
679	1.41k	TMS320C64xSubRegIdxLists, 1, 0);
680	1.41k	}
681
682		#endif