/src/capstonenext/arch/TMS320C64x/TMS320C64xDisassembler.c

Source
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */

#ifdef CAPSTONE_HAS_TMS320C64X

#include <string.h>

#include "../../cs_priv.h"
#include "../../utils.h"

#include "TMS320C64xDisassembler.h"

#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../MCRegisterInfo.h"
#include "../../MCDisassembler.h"
#include "../../MathExtras.h"

static uint64_t getFeatureBits(int mode);

static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
                uint64_t Address, void *Decoder);

static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
               uint64_t Address,
               void *Decoder);

static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address,
        void *Decoder);

static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address,
         void *Decoder);

static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder);

static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder);

static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
               uint64_t Address, void *Decoder);

static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
           uint64_t Address, void *Decoder);

static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
           uint64_t Address, void *Decoder);

static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
               uint64_t Address, void *Decoder);

static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder);

static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address,
             void *Decoder);

static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address,
           void *Decoder);

static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder);

static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address,
            void *Decoder);

#include "TMS320C64xGenDisassemblerTables.inc"

#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "TMS320C64xGenRegisterInfo.inc"

static const unsigned GPRegsDecoderTable[] = {
  TMS320C64x_A0,  TMS320C64x_A1,  TMS320C64x_A2,  TMS320C64x_A3,
  TMS320C64x_A4,  TMS320C64x_A5,  TMS320C64x_A6,  TMS320C64x_A7,
  TMS320C64x_A8,  TMS320C64x_A9,  TMS320C64x_A10, TMS320C64x_A11,
  TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15,
  TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19,
  TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23,
  TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27,
  TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31
};

static const unsigned ControlRegsDecoderTable[] = { TMS320C64x_AMR,
                TMS320C64x_CSR,
                TMS320C64x_ISR,
                TMS320C64x_ICR,
                TMS320C64x_IER,
                TMS320C64x_ISTP,
                TMS320C64x_IRP,
                TMS320C64x_NRP,
                ~0U,
                ~0U,
                TMS320C64x_TSCL,
                TMS320C64x_TSCH,
                ~0U,
                TMS320C64x_ILC,
                TMS320C64x_RILC,
                TMS320C64x_REP,
                TMS320C64x_PCE1,
                TMS320C64x_DNUM,
                ~0U,
                ~0U,
                ~0U,
                TMS320C64x_SSR,
                TMS320C64x_GPLYA,
                TMS320C64x_GPLYB,
                TMS320C64x_GFPGFR,
                TMS320C64x_DIER,
                TMS320C64x_TSR,
                TMS320C64x_ITSR,
                TMS320C64x_NTSR,
                TMS320C64x_ECR,
                ~0U,
                TMS320C64x_IERR };

static uint64_t getFeatureBits(int mode)
{
  // support everything
  return (uint64_t)-1;
}

static unsigned getReg(const unsigned *RegTable, unsigned RegNo)
{
  if (RegNo > 31)
    return ~0U;
  return RegTable[RegNo];
}

static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
                uint64_t Address, void *Decoder)
{
  unsigned Reg;

  if (RegNo > 31)
    return MCDisassembler_Fail;

  Reg = getReg(GPRegsDecoderTable, RegNo);
  if (Reg == ~0U)
    return MCDisassembler_Fail;
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
               uint64_t Address,
               void *Decoder)
{
  unsigned Reg;

  if (RegNo > 31)
    return MCDisassembler_Fail;

  Reg = getReg(ControlRegsDecoderTable, RegNo);
  if (Reg == ~0U)
    return MCDisassembler_Fail;
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address,
        void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 5 bit value */
  if (imm & (1 << (5 - 1)))
    imm |= ~((1 << 5) - 1);

  MCOperand_CreateImm0(Inst, imm);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address,
         void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 16 bit value */
  if (imm & (1 << (16 - 1)))
    imm |= ~((1 << 16) - 1);

  MCOperand_CreateImm0(Inst, imm);

  return MCDisassembler_Success;
}

static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 7 bit value */
  if (imm & (1 << (7 - 1)))
    imm |= ~((1 << 7) - 1);

  /* Address is relative to the address of the first instruction in the fetch packet */
  MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));

  return MCDisassembler_Success;
}

static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 10 bit value */
  if (imm & (1 << (10 - 1)))
    imm |= ~((1 << 10) - 1);

  /* Address is relative to the address of the first instruction in the fetch packet */
  MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));

  return MCDisassembler_Success;
}

static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 12 bit value */
  if (imm & (1 << (12 - 1)))
    imm |= ~((1 << 12) - 1);

  /* Address is relative to the address of the first instruction in the fetch packet */
  MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));

  return MCDisassembler_Success;
}

static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  int32_t imm;

  imm = Val;
  /* Sign extend 21 bit value */
  if (imm & (1 << (21 - 1)))
    imm |= ~((1 << 21) - 1);

  /* Address is relative to the address of the first instruction in the fetch packet */
  MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));

  return MCDisassembler_Success;
}

static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder)
{
  return DecodeMemOperandSc(Inst, Val | (1 << 15), Address, Decoder);
}

static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
               uint64_t Address, void *Decoder)
{
  uint8_t scaled, base, offset, mode, unit;
  unsigned basereg, offsetreg;

  scaled = (Val >> 15) & 1;
  base = (Val >> 10) & 0x1f;
  offset = (Val >> 5) & 0x1f;
  mode = (Val >> 1) & 0xf;
  unit = Val & 1;

  if ((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31))
    base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
  // base cannot be a B register, because it was ANDed above with 0x1f.
  // And the TMS320C64X_REG_B0 > 31
  basereg = getReg(GPRegsDecoderTable, base);
  if (basereg == ~0U)
    return MCDisassembler_Fail;

  switch (mode) {
  case 0:
  case 1:
  case 8:
  case 9:
  case 10:
  case 11:
    MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) |
               (offset << 5) | (mode << 1) |
               unit);
    break;
  case 4:
  case 5:
  case 12:
  case 13:
  case 14:
  case 15:
    if ((offset >= TMS320C64X_REG_A0) &&
        (offset <= TMS320C64X_REG_A31))
      offset = (offset - TMS320C64X_REG_A0 +
          TMS320C64X_REG_B0);
    // offset cannot be a B register, because it was ANDed above with 0x1f.
    // And the TMS320C64X_REG_B0 > 31
    offsetreg = getReg(GPRegsDecoderTable, offset);
    if (offsetreg == ~0U)
      return MCDisassembler_Fail;
    MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) |
               (offsetreg << 5) |
               (mode << 1) | unit);
    break;
  default:
    return MCDisassembler_Fail;
  }

  return MCDisassembler_Success;
}

static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  uint16_t offset;
  unsigned basereg;

  if (Val & 1)
    basereg = TMS320C64X_REG_B15;
  else
    basereg = TMS320C64X_REG_B14;

  offset = (Val >> 1) & 0x7fff;
  MCOperand_CreateImm0(Inst, (offset << 7) | basereg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
           uint64_t Address, void *Decoder)
{
  unsigned Reg;

  if (RegNo > 31)
    return MCDisassembler_Fail;

  Reg = getReg(GPRegsDecoderTable, RegNo);
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
           uint64_t Address, void *Decoder)
{
  unsigned Reg;

  if (RegNo > 15)
    return MCDisassembler_Fail;

  Reg = getReg(GPRegsDecoderTable, RegNo << 1);
  MCOperand_CreateReg0(Inst, Reg);

  return MCDisassembler_Success;
}

static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
               uint64_t Address, void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
  case 7:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_INVALID;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_B0;
    break;
  case 2:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_B1;
    break;
  case 3:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_B2;
    break;
  case 4:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_A1;
    break;
  case 5:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_A2;
    break;
  case 6:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_A0;
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.condition.reg =
      TMS320C64X_REG_INVALID;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
             uint64_t Address, void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.condition.zero = 1;
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address,
             void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;
  MCOperand *op;
  int i;

  /* This is pretty messy, probably we should find a better way */
  if (Val == 1) {
    for (i = 0; i < Inst->size; i++) {
      op = &Inst->Operands[i];
      if (op->Kind == kRegister) {
        if ((op->RegVal >= TMS320C64X_REG_A0) &&
            (op->RegVal <= TMS320C64X_REG_A31))
          op->RegVal = (op->RegVal -
                  TMS320C64X_REG_A0 +
                  TMS320C64X_REG_B0);
        else if ((op->RegVal >= TMS320C64X_REG_B0) &&
           (op->RegVal <= TMS320C64X_REG_B31))
          op->RegVal = (op->RegVal -
                  TMS320C64X_REG_B0 +
                  TMS320C64X_REG_A0);
      }
    }
  }

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.funit.side = 1;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.funit.side = 2;
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.funit.side = 0;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address,
           void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.parallel = 0;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.parallel = 1;
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.parallel = -1;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;
  MCOperand *op;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
    op = &Inst->Operands[0];
    if (op->Kind == kRegister) {
      if ((op->RegVal >= TMS320C64X_REG_A0) &&
          (op->RegVal <= TMS320C64X_REG_A31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
                TMS320C64X_REG_B0);
      else if ((op->RegVal >= TMS320C64X_REG_B0) &&
         (op->RegVal <= TMS320C64X_REG_B31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
                TMS320C64X_REG_A0);
    }
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;
  MCOperand *op;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
    op = &Inst->Operands[1];
    if (op->Kind == kRegister) {
      if ((op->RegVal >= TMS320C64X_REG_A0) &&
          (op->RegVal <= TMS320C64X_REG_A31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
                TMS320C64X_REG_B0);
      else if ((op->RegVal >= TMS320C64X_REG_B0) &&
         (op->RegVal <= TMS320C64X_REG_B31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
                TMS320C64X_REG_A0);
    }
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
              uint64_t Address, void *Decoder)
{
  DecodeStatus ret = MCDisassembler_Success;
  MCOperand *op;

  if (!Inst->flat_insn->detail)
    return MCDisassembler_Success;

  switch (Val) {
  case 0:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
    break;
  case 1:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = 2;
    op = &Inst->Operands[2];
    if (op->Kind == kRegister) {
      if ((op->RegVal >= TMS320C64X_REG_A0) &&
          (op->RegVal <= TMS320C64X_REG_A31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
                TMS320C64X_REG_B0);
      else if ((op->RegVal >= TMS320C64X_REG_B0) &&
         (op->RegVal <= TMS320C64X_REG_B31))
        op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
                TMS320C64X_REG_A0);
    }
    break;
  default:
    Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
    ret = MCDisassembler_Fail;
    break;
  }

  return ret;
}

static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address,
            void *Decoder)
{
  MCOperand_CreateImm0(Inst, Val + 1);

  return MCDisassembler_Success;
}

#define GET_INSTRINFO_ENUM
#include "TMS320C64xGenInstrInfo.inc"

bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len,
             MCInst *MI, uint16_t *size, uint64_t address,
             void *info)
{
  uint32_t insn;
  DecodeStatus result;

  if (code_len < 4) {
    *size = 0;
    return MCDisassembler_Fail;
  }

  if (MI->flat_insn->detail)
    memset(MI->flat_insn->detail, 0,
           offsetof(cs_detail, tms320c64x) + sizeof(cs_tms320c64x));

  insn = readBytes32(MI, code);
  result =
    decodeInstruction_4(DecoderTable32, MI, insn, address, info, 0);

  if (result == MCDisassembler_Success) {
    *size = 4;
    return true;
  }

  MCInst_clear(MI);
  *size = 0;
  return false;
}

void TMS320C64x_init(MCRegisterInfo *MRI)
{
  MCRegisterInfo_InitMCRegisterInfo(MRI, TMS320C64xRegDesc, 90, 0, 0,
            TMS320C64xMCRegisterClasses, 7, 0, 0,
            TMS320C64xRegDiffLists, 0,
            TMS320C64xSubRegIdxLists, 1, 0);
}

#endif

Coverage Report

Created: 2025-11-24 06:12

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3
4		#ifdef CAPSTONE_HAS_TMS320C64X
5
6		#include <string.h>
7
8		#include "../../cs_priv.h"
9		#include "../../utils.h"
10
11		#include "TMS320C64xDisassembler.h"
12
13		#include "../../MCInst.h"
14		#include "../../MCInstrDesc.h"
15		#include "../../MCFixedLenDisassembler.h"
16		#include "../../MCRegisterInfo.h"
17		#include "../../MCDisassembler.h"
18		#include "../../MathExtras.h"
19
20		static uint64_t getFeatureBits(int mode);
21
22		static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
23		uint64_t Address, void *Decoder);
24
25		static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
26		uint64_t Address,
27		void *Decoder);
28
29		static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address,
30		void *Decoder);
31
32		static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address,
33		void *Decoder);
34
35		static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
36		uint64_t Address, void *Decoder);
37
38		static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
39		uint64_t Address, void *Decoder);
40
41		static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
42		uint64_t Address, void *Decoder);
43
44		static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
45		uint64_t Address, void *Decoder);
46
47		static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
48		uint64_t Address, void *Decoder);
49
50		static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
51		uint64_t Address, void *Decoder);
52
53		static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
54		uint64_t Address, void *Decoder);
55
56		static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
57		uint64_t Address, void *Decoder);
58
59		static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
60		uint64_t Address, void *Decoder);
61
62		static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
63		uint64_t Address, void *Decoder);
64
65		static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
66		uint64_t Address, void *Decoder);
67
68		static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address,
69		void *Decoder);
70
71		static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address,
72		void *Decoder);
73
74		static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
75		uint64_t Address, void *Decoder);
76
77		static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
78		uint64_t Address, void *Decoder);
79
80		static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
81		uint64_t Address, void *Decoder);
82
83		static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address,
84		void *Decoder);
85
86		#include "TMS320C64xGenDisassemblerTables.inc"
87
88		#define GET_REGINFO_ENUM
89		#define GET_REGINFO_MC_DESC
90		#include "TMS320C64xGenRegisterInfo.inc"
91
92		static const unsigned GPRegsDecoderTable[] = {
93		TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3,
94		TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7,
95		TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11,
96		TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15,
97		TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19,
98		TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23,
99		TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27,
100		TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31
101		};
102
103		static const unsigned ControlRegsDecoderTable[] = { TMS320C64x_AMR,
104		TMS320C64x_CSR,
105		TMS320C64x_ISR,
106		TMS320C64x_ICR,
107		TMS320C64x_IER,
108		TMS320C64x_ISTP,
109		TMS320C64x_IRP,
110		TMS320C64x_NRP,
111		~0U,
112		~0U,
113		TMS320C64x_TSCL,
114		TMS320C64x_TSCH,
115		~0U,
116		TMS320C64x_ILC,
117		TMS320C64x_RILC,
118		TMS320C64x_REP,
119		TMS320C64x_PCE1,
120		TMS320C64x_DNUM,
121		~0U,
122		~0U,
123		~0U,
124		TMS320C64x_SSR,
125		TMS320C64x_GPLYA,
126		TMS320C64x_GPLYB,
127		TMS320C64x_GFPGFR,
128		TMS320C64x_DIER,
129		TMS320C64x_TSR,
130		TMS320C64x_ITSR,
131		TMS320C64x_NTSR,
132		TMS320C64x_ECR,
133		~0U,
134		TMS320C64x_IERR };
135
136		static uint64_t getFeatureBits(int mode)
137	46.1k	{
138		// support everything
139	46.1k	return (uint64_t)-1;
140	46.1k	}
141
142		static unsigned getReg(const unsigned *RegTable, unsigned RegNo)
143	79.4k	{
144	79.4k	if (RegNo > 31)
145	19	return ~0U;
146	79.4k	return RegTable[RegNo];
147	79.4k	}
148
149		static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
150		uint64_t Address, void *Decoder)
151	54.6k	{
152	54.6k	unsigned Reg;
153
154	54.6k	if (RegNo > 31)
155	0	return MCDisassembler_Fail;
156
157	54.6k	Reg = getReg(GPRegsDecoderTable, RegNo);
158	54.6k	if (Reg == ~0U)
159	0	return MCDisassembler_Fail;
160	54.6k	MCOperand_CreateReg0(Inst, Reg);
161
162	54.6k	return MCDisassembler_Success;
163	54.6k	}
164
165		static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
166		uint64_t Address,
167		void *Decoder)
168	3.57k	{
169	3.57k	unsigned Reg;
170
171	3.57k	if (RegNo > 31)
172	0	return MCDisassembler_Fail;
173
174	3.57k	Reg = getReg(ControlRegsDecoderTable, RegNo);
175	3.57k	if (Reg == ~0U)
176	3	return MCDisassembler_Fail;
177	3.56k	MCOperand_CreateReg0(Inst, Reg);
178
179	3.56k	return MCDisassembler_Success;
180	3.57k	}
181
182		static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val, uint64_t Address,
183		void *Decoder)
184	6.85k	{
185	6.85k	int32_t imm;
186
187	6.85k	imm = Val;
188		/* Sign extend 5 bit value */
189	6.85k	if (imm & (1 << (5 - 1)))
190	3.42k	imm \|= ~((1 << 5) - 1);
191
192	6.85k	MCOperand_CreateImm0(Inst, imm);
193
194	6.85k	return MCDisassembler_Success;
195	6.85k	}
196
197		static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val, uint64_t Address,
198		void *Decoder)
199	2.14k	{
200	2.14k	int32_t imm;
201
202	2.14k	imm = Val;
203		/* Sign extend 16 bit value */
204	2.14k	if (imm & (1 << (16 - 1)))
205	1.51k	imm \|= ~((1 << 16) - 1);
206
207	2.14k	MCOperand_CreateImm0(Inst, imm);
208
209	2.14k	return MCDisassembler_Success;
210	2.14k	}
211
212		static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
213		uint64_t Address, void *Decoder)
214	494	{
215	494	int32_t imm;
216
217	494	imm = Val;
218		/* Sign extend 7 bit value */
219	494	if (imm & (1 << (7 - 1)))
220	378	imm \|= ~((1 << 7) - 1);
221
222		/* Address is relative to the address of the first instruction in the fetch packet */
223	494	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
224
225	494	return MCDisassembler_Success;
226	494	}
227
228		static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
229		uint64_t Address, void *Decoder)
230	650	{
231	650	int32_t imm;
232
233	650	imm = Val;
234		/* Sign extend 10 bit value */
235	650	if (imm & (1 << (10 - 1)))
236	101	imm \|= ~((1 << 10) - 1);
237
238		/* Address is relative to the address of the first instruction in the fetch packet */
239	650	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
240
241	650	return MCDisassembler_Success;
242	650	}
243
244		static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
245		uint64_t Address, void *Decoder)
246	1.17k	{
247	1.17k	int32_t imm;
248
249	1.17k	imm = Val;
250		/* Sign extend 12 bit value */
251	1.17k	if (imm & (1 << (12 - 1)))
252	547	imm \|= ~((1 << 12) - 1);
253
254		/* Address is relative to the address of the first instruction in the fetch packet */
255	1.17k	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
256
257	1.17k	return MCDisassembler_Success;
258	1.17k	}
259
260		static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
261		uint64_t Address, void *Decoder)
262	2.37k	{
263	2.37k	int32_t imm;
264
265	2.37k	imm = Val;
266		/* Sign extend 21 bit value */
267	2.37k	if (imm & (1 << (21 - 1)))
268	515	imm \|= ~((1 << 21) - 1);
269
270		/* Address is relative to the address of the first instruction in the fetch packet */
271	2.37k	MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
272
273	2.37k	return MCDisassembler_Success;
274	2.37k	}
275
276		static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
277		uint64_t Address, void *Decoder)
278	4.13k	{
279	4.13k	return DecodeMemOperandSc(Inst, Val \| (1 << 15), Address, Decoder);
280	4.13k	}
281
282		static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
283		uint64_t Address, void *Decoder)
284	4.55k	{
285	4.55k	uint8_t scaled, base, offset, mode, unit;
286	4.55k	unsigned basereg, offsetreg;
287
288	4.55k	scaled = (Val >> 15) & 1;
289	4.55k	base = (Val >> 10) & 0x1f;
290	4.55k	offset = (Val >> 5) & 0x1f;
291	4.55k	mode = (Val >> 1) & 0xf;
292	4.55k	unit = Val & 1;
293
294	4.55k	if ((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31))
295	12	base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
296		// base cannot be a B register, because it was ANDed above with 0x1f.
297		// And the TMS320C64X_REG_B0 > 31
298	4.55k	basereg = getReg(GPRegsDecoderTable, base);
299	4.55k	if (basereg == ~0U)
300	12	return MCDisassembler_Fail;
301
302	4.54k	switch (mode) {
303	871	case 0:
304	1.22k	case 1:
305	1.59k	case 8:
306	1.88k	case 9:
307	2.30k	case 10:
308	2.95k	case 11:
309	2.95k	MCOperand_CreateImm0(Inst, (scaled << 19) \| (basereg << 12) \|
310	2.95k	(offset << 5) \| (mode << 1) \|
311	2.95k	unit);
312	2.95k	break;
313	293	case 4:
314	669	case 5:
315	901	case 12:
316	999	case 13:
317	1.24k	case 14:
318	1.58k	case 15:
319	1.58k	if ((offset >= TMS320C64X_REG_A0) &&
320	5	(offset <= TMS320C64X_REG_A31))
321	5	offset = (offset - TMS320C64X_REG_A0 +
322	5	TMS320C64X_REG_B0);
323		// offset cannot be a B register, because it was ANDed above with 0x1f.
324		// And the TMS320C64X_REG_B0 > 31
325	1.58k	offsetreg = getReg(GPRegsDecoderTable, offset);
326	1.58k	if (offsetreg == ~0U)
327	5	return MCDisassembler_Fail;
328	1.57k	MCOperand_CreateImm0(Inst, (scaled << 19) \| (basereg << 12) \|
329	1.57k	(offsetreg << 5) \|
330	1.57k	(mode << 1) \| unit);
331	1.57k	break;
332	13	default:
333	13	return MCDisassembler_Fail;
334	4.54k	}
335
336	4.52k	return MCDisassembler_Success;
337	4.54k	}
338
339		static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
340		uint64_t Address, void *Decoder)
341	4.00k	{
342	4.00k	uint16_t offset;
343	4.00k	unsigned basereg;
344
345	4.00k	if (Val & 1)
346	1.73k	basereg = TMS320C64X_REG_B15;
347	2.26k	else
348	2.26k	basereg = TMS320C64X_REG_B14;
349
350	4.00k	offset = (Val >> 1) & 0x7fff;
351	4.00k	MCOperand_CreateImm0(Inst, (offset << 7) \| basereg);
352
353	4.00k	return MCDisassembler_Success;
354	4.00k	}
355
356		static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
357		uint64_t Address, void *Decoder)
358	13.6k	{
359	13.6k	unsigned Reg;
360
361	13.6k	if (RegNo > 31)
362	0	return MCDisassembler_Fail;
363
364	13.6k	Reg = getReg(GPRegsDecoderTable, RegNo);
365	13.6k	MCOperand_CreateReg0(Inst, Reg);
366
367	13.6k	return MCDisassembler_Success;
368	13.6k	}
369
370		static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
371		uint64_t Address, void *Decoder)
372	794	{
373	794	unsigned Reg;
374
375	794	if (RegNo > 15)
376	0	return MCDisassembler_Fail;
377
378	794	Reg = getReg(GPRegsDecoderTable, RegNo << 1);
379	794	MCOperand_CreateReg0(Inst, Reg);
380
381	794	return MCDisassembler_Success;
382	794	}
383
384		static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
385		uint64_t Address, void *Decoder)
386	45.9k	{
387	45.9k	DecodeStatus ret = MCDisassembler_Success;
388
389	45.9k	if (!Inst->flat_insn->detail)
390	0	return MCDisassembler_Success;
391
392	45.9k	switch (Val) {
393	10.3k	case 0:
394	17.6k	case 7:
395	17.6k	Inst->flat_insn->detail->tms320c64x.condition.reg =
396	17.6k	TMS320C64X_REG_INVALID;
397	17.6k	break;
398	5.90k	case 1:
399	5.90k	Inst->flat_insn->detail->tms320c64x.condition.reg =
400	5.90k	TMS320C64X_REG_B0;
401	5.90k	break;
402	4.79k	case 2:
403	4.79k	Inst->flat_insn->detail->tms320c64x.condition.reg =
404	4.79k	TMS320C64X_REG_B1;
405	4.79k	break;
406	4.66k	case 3:
407	4.66k	Inst->flat_insn->detail->tms320c64x.condition.reg =
408	4.66k	TMS320C64X_REG_B2;
409	4.66k	break;
410	5.16k	case 4:
411	5.16k	Inst->flat_insn->detail->tms320c64x.condition.reg =
412	5.16k	TMS320C64X_REG_A1;
413	5.16k	break;
414	4.35k	case 5:
415	4.35k	Inst->flat_insn->detail->tms320c64x.condition.reg =
416	4.35k	TMS320C64X_REG_A2;
417	4.35k	break;
418	3.47k	case 6:
419	3.47k	Inst->flat_insn->detail->tms320c64x.condition.reg =
420	3.47k	TMS320C64X_REG_A0;
421	3.47k	break;
422	0	default:
423	0	Inst->flat_insn->detail->tms320c64x.condition.reg =
424	0	TMS320C64X_REG_INVALID;
425	0	ret = MCDisassembler_Fail;
426	0	break;
427	45.9k	}
428
429	45.9k	return ret;
430	45.9k	}
431
432		static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
433		uint64_t Address, void *Decoder)
434	45.9k	{
435	45.9k	DecodeStatus ret = MCDisassembler_Success;
436
437	45.9k	if (!Inst->flat_insn->detail)
438	0	return MCDisassembler_Success;
439
440	45.9k	switch (Val) {
441	22.4k	case 0:
442	22.4k	Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
443	22.4k	break;
444	23.5k	case 1:
445	23.5k	Inst->flat_insn->detail->tms320c64x.condition.zero = 1;
446	23.5k	break;
447	0	default:
448	0	Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
449	0	ret = MCDisassembler_Fail;
450	0	break;
451	45.9k	}
452
453	45.9k	return ret;
454	45.9k	}
455
456		static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val, uint64_t Address,
457		void *Decoder)
458	45.9k	{
459	45.9k	DecodeStatus ret = MCDisassembler_Success;
460	45.9k	MCOperand *op;
461	45.9k	int i;
462
463		/* This is pretty messy, probably we should find a better way */
464	45.9k	if (Val == 1) {
465	73.4k	for (i = 0; i < Inst->size; i++) {
466	51.7k	op = &Inst->Operands[i];
467	51.7k	if (op->Kind == kRegister) {
468	37.8k	if ((op->RegVal >= TMS320C64X_REG_A0) &&
469	34.8k	(op->RegVal <= TMS320C64X_REG_A31))
470	31.3k	op->RegVal = (op->RegVal -
471	31.3k	TMS320C64X_REG_A0 +
472	31.3k	TMS320C64X_REG_B0);
473	6.52k	else if ((op->RegVal >= TMS320C64X_REG_B0) &&
474	3.46k	(op->RegVal <= TMS320C64X_REG_B31))
475	3.13k	op->RegVal = (op->RegVal -
476	3.13k	TMS320C64X_REG_B0 +
477	3.13k	TMS320C64X_REG_A0);
478	37.8k	}
479	51.7k	}
480	21.7k	}
481
482	45.9k	if (!Inst->flat_insn->detail)
483	0	return MCDisassembler_Success;
484
485	45.9k	switch (Val) {
486	24.2k	case 0:
487	24.2k	Inst->flat_insn->detail->tms320c64x.funit.side = 1;
488	24.2k	break;
489	21.7k	case 1:
490	21.7k	Inst->flat_insn->detail->tms320c64x.funit.side = 2;
491	21.7k	break;
492	0	default:
493	0	Inst->flat_insn->detail->tms320c64x.funit.side = 0;
494	0	ret = MCDisassembler_Fail;
495	0	break;
496	45.9k	}
497
498	45.9k	return ret;
499	45.9k	}
500
501		static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val, uint64_t Address,
502		void *Decoder)
503	45.9k	{
504	45.9k	DecodeStatus ret = MCDisassembler_Success;
505
506	45.9k	if (!Inst->flat_insn->detail)
507	0	return MCDisassembler_Success;
508
509	45.9k	switch (Val) {
510	24.0k	case 0:
511	24.0k	Inst->flat_insn->detail->tms320c64x.parallel = 0;
512	24.0k	break;
513	21.9k	case 1:
514	21.9k	Inst->flat_insn->detail->tms320c64x.parallel = 1;
515	21.9k	break;
516	0	default:
517	0	Inst->flat_insn->detail->tms320c64x.parallel = -1;
518	0	ret = MCDisassembler_Fail;
519	0	break;
520	45.9k	}
521
522	45.9k	return ret;
523	45.9k	}
524
525		static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
526		uint64_t Address, void *Decoder)
527	499	{
528	499	DecodeStatus ret = MCDisassembler_Success;
529	499	MCOperand *op;
530
531	499	if (!Inst->flat_insn->detail)
532	0	return MCDisassembler_Success;
533
534	499	switch (Val) {
535	256	case 0:
536	256	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
537	256	break;
538	243	case 1:
539	243	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
540	243	op = &Inst->Operands[0];
541	243	if (op->Kind == kRegister) {
542	243	if ((op->RegVal >= TMS320C64X_REG_A0) &&
543	243	(op->RegVal <= TMS320C64X_REG_A31))
544	243	op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
545	243	TMS320C64X_REG_B0);
546	0	else if ((op->RegVal >= TMS320C64X_REG_B0) &&
547	0	(op->RegVal <= TMS320C64X_REG_B31))
548	0	op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
549	0	TMS320C64X_REG_A0);
550	243	}
551	243	break;
552	0	default:
553	0	Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
554	0	ret = MCDisassembler_Fail;
555	0	break;
556	499	}
557
558	499	return ret;
559	499	}
560
561		static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
562		uint64_t Address, void *Decoder)
563	15.4k	{
564	15.4k	DecodeStatus ret = MCDisassembler_Success;
565	15.4k	MCOperand *op;
566
567	15.4k	if (!Inst->flat_insn->detail)
568	0	return MCDisassembler_Success;
569
570	15.4k	switch (Val) {
571	5.63k	case 0:
572	5.63k	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
573	5.63k	break;
574	9.80k	case 1:
575	9.80k	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
576	9.80k	op = &Inst->Operands[1];
577	9.80k	if (op->Kind == kRegister) {
578	9.02k	if ((op->RegVal >= TMS320C64X_REG_A0) &&
579	5.97k	(op->RegVal <= TMS320C64X_REG_A31))
580	5.65k	op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
581	5.65k	TMS320C64X_REG_B0);
582	3.37k	else if ((op->RegVal >= TMS320C64X_REG_B0) &&
583	326	(op->RegVal <= TMS320C64X_REG_B31))
584	0	op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
585	0	TMS320C64X_REG_A0);
586	9.02k	}
587	9.80k	break;
588	0	default:
589	0	Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
590	0	ret = MCDisassembler_Fail;
591	0	break;
592	15.4k	}
593
594	15.4k	return ret;
595	15.4k	}
596
597		static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
598		uint64_t Address, void *Decoder)
599	7.58k	{
600	7.58k	DecodeStatus ret = MCDisassembler_Success;
601	7.58k	MCOperand *op;
602
603	7.58k	if (!Inst->flat_insn->detail)
604	0	return MCDisassembler_Success;
605
606	7.58k	switch (Val) {
607	3.21k	case 0:
608	3.21k	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
609	3.21k	break;
610	4.36k	case 1:
611	4.36k	Inst->flat_insn->detail->tms320c64x.funit.crosspath = 2;
612	4.36k	op = &Inst->Operands[2];
613	4.36k	if (op->Kind == kRegister) {
614	1.03k	if ((op->RegVal >= TMS320C64X_REG_A0) &&
615	1.00k	(op->RegVal <= TMS320C64X_REG_A31))
616	1.00k	op->RegVal = (op->RegVal - TMS320C64X_REG_A0 +
617	1.00k	TMS320C64X_REG_B0);
618	36	else if ((op->RegVal >= TMS320C64X_REG_B0) &&
619	8	(op->RegVal <= TMS320C64X_REG_B31))
620	8	op->RegVal = (op->RegVal - TMS320C64X_REG_B0 +
621	8	TMS320C64X_REG_A0);
622	1.03k	}
623	4.36k	break;
624	0	default:
625	0	Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
626	0	ret = MCDisassembler_Fail;
627	0	break;
628	7.58k	}
629
630	7.58k	return ret;
631	7.58k	}
632
633		static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val, uint64_t Address,
634		void *Decoder)
635	1.10k	{
636	1.10k	MCOperand_CreateImm0(Inst, Val + 1);
637
638	1.10k	return MCDisassembler_Success;
639	1.10k	}
640
641		#define GET_INSTRINFO_ENUM
642		#include "TMS320C64xGenInstrInfo.inc"
643
644		bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len,
645		MCInst MI, uint16_t size, uint64_t address,
646		void *info)
647	46.6k	{
648	46.6k	uint32_t insn;
649	46.6k	DecodeStatus result;
650
651	46.6k	if (code_len < 4) {
652	506	*size = 0;
653	506	return MCDisassembler_Fail;
654	506	}
655
656	46.1k	if (MI->flat_insn->detail)
657	46.1k	memset(MI->flat_insn->detail, 0,
658	46.1k	offsetof(cs_detail, tms320c64x) + sizeof(cs_tms320c64x));
659
660	46.1k	insn = readBytes32(MI, code);
661	46.1k	result =
662	46.1k	decodeInstruction_4(DecoderTable32, MI, insn, address, info, 0);
663
664	46.1k	if (result == MCDisassembler_Success) {
665	45.9k	*size = 4;
666	45.9k	return true;
667	45.9k	}
668
669	197	MCInst_clear(MI);
670	197	*size = 0;
671	197	return false;
672	46.1k	}
673
674		void TMS320C64x_init(MCRegisterInfo *MRI)
675	1.34k	{
676	1.34k	MCRegisterInfo_InitMCRegisterInfo(MRI, TMS320C64xRegDesc, 90, 0, 0,
677	1.34k	TMS320C64xMCRegisterClasses, 7, 0, 0,
678	1.34k	TMS320C64xRegDiffLists, 0,
679	1.34k	TMS320C64xSubRegIdxLists, 1, 0);
680	1.34k	}
681
682		#endif