/src/capstonenext/arch/RISCV/RISCVGenSystemOperands.inc
Line | Count | Source |
1 | | /* Capstone Disassembly Engine, https://www.capstone-engine.org */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */ |
3 | | /* Rot127 <unisono@quyllur.org> 2022-2024 */ |
4 | | /* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */ |
5 | | |
6 | | /* LLVM-commit: <commit> */ |
7 | | /* LLVM-tag: <tag> */ |
8 | | |
9 | | /* Do not edit. */ |
10 | | |
11 | | /* Capstone's LLVM TableGen Backends: */ |
12 | | /* https://github.com/capstone-engine/llvm-capstone */ |
13 | | |
14 | | #ifdef GET_RISCVMaskedPseudosTable_DECL |
15 | | const RISCV_RISCVMaskedPseudoInfo *RISCV_getMaskedPseudoInfo(unsigned MaskedPseudo); |
16 | | const RISCV_RISCVMaskedPseudoInfo *RISCV_lookupMaskedIntrinsicByUnmasked(unsigned UnmaskedPseudo); |
17 | | #endif |
18 | | |
19 | | #ifdef GET_RISCVOpcodesList_DECL |
20 | | const RISCV_RISCVOpcode *RISCV_lookupRISCVOpcodeByValue(uint8_t Value); |
21 | | const RISCV_RISCVOpcode *RISCV_lookupRISCVOpcodeByName(const char * Name); |
22 | | #endif |
23 | | |
24 | | #ifdef GET_RISCVTuneInfoTable_DECL |
25 | | const RISCV_RISCVTuneInfo *RISCV_getRISCVTuneInfo(const char * Name); |
26 | | #endif |
27 | | |
28 | | #ifdef GET_RISCVVInversePseudosTable_DECL |
29 | | const RISCV_PseudoInfo *RISCV_getBaseInfo(unsigned BaseInstr, uint8_t VLMul, uint8_t SEW); |
30 | | #endif |
31 | | |
32 | | #ifdef GET_RISCVVLETable_DECL |
33 | | const RISCV_VLEPseudo *RISCV_getVLEPseudo(uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL); |
34 | | #endif |
35 | | |
36 | | #ifdef GET_RISCVVLSEGTable_DECL |
37 | | const RISCV_VLSEGPseudo *RISCV_getVLSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL); |
38 | | #endif |
39 | | |
40 | | #ifdef GET_RISCVVLXSEGTable_DECL |
41 | | const RISCV_VLXSEGPseudo *RISCV_getVLXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL); |
42 | | #endif |
43 | | |
44 | | #ifdef GET_RISCVVLXTable_DECL |
45 | | const RISCV_VLX_VSXPseudo *RISCV_getVLXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL); |
46 | | #endif |
47 | | |
48 | | #ifdef GET_RISCVVPseudosTable_DECL |
49 | | const RISCV_PseudoInfo *RISCV_getPseudoInfo(unsigned Pseudo); |
50 | | #endif |
51 | | |
52 | | #ifdef GET_RISCVVSETable_DECL |
53 | | const RISCV_VSEPseudo *RISCV_getVSEPseudo(uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL); |
54 | | #endif |
55 | | |
56 | | #ifdef GET_RISCVVSSEGTable_DECL |
57 | | const RISCV_VSSEGPseudo *RISCV_getVSSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL); |
58 | | #endif |
59 | | |
60 | | #ifdef GET_RISCVVSXSEGTable_DECL |
61 | | const RISCV_VSXSEGPseudo *RISCV_getVSXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL); |
62 | | #endif |
63 | | |
64 | | #ifdef GET_RISCVVSXTable_DECL |
65 | | const RISCV_VLX_VSXPseudo *RISCV_getVSXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL); |
66 | | #endif |
67 | | |
68 | | #ifdef GET_SysRegsList_DECL |
69 | | const RISCV_SysReg *RISCV_lookupSysRegByEncoding(uint16_t Encoding); |
70 | | const RISCV_SysReg *RISCV_lookupSysRegByAltName(const char * AltName); |
71 | | const RISCV_SysReg *RISCV_lookupSysRegByDeprecatedName(const char * DeprecatedName); |
72 | | const RISCV_SysReg *RISCV_lookupSysRegByName(const char * Name); |
73 | | #endif |
74 | | |
75 | | #ifdef GET_RISCVMaskedPseudosTable_IMPL |
76 | | static const RISCV_RISCVMaskedPseudoInfo RISCVMaskedPseudosTable[] = { |
77 | | { PseudoTHVdotVMAQASU_VV_M1_MASK, PseudoTHVdotVMAQASU_VV_M1, 0x3, false }, // 0 |
78 | | { PseudoTHVdotVMAQASU_VV_M2_MASK, PseudoTHVdotVMAQASU_VV_M2, 0x3, false }, // 1 |
79 | | { PseudoTHVdotVMAQASU_VV_M4_MASK, PseudoTHVdotVMAQASU_VV_M4, 0x3, false }, // 2 |
80 | | { PseudoTHVdotVMAQASU_VV_M8_MASK, PseudoTHVdotVMAQASU_VV_M8, 0x3, false }, // 3 |
81 | | { PseudoTHVdotVMAQASU_VV_MF2_MASK, PseudoTHVdotVMAQASU_VV_MF2, 0x3, false }, // 4 |
82 | | { PseudoTHVdotVMAQASU_VX_M1_MASK, PseudoTHVdotVMAQASU_VX_M1, 0x3, false }, // 5 |
83 | | { PseudoTHVdotVMAQASU_VX_M2_MASK, PseudoTHVdotVMAQASU_VX_M2, 0x3, false }, // 6 |
84 | | { PseudoTHVdotVMAQASU_VX_M4_MASK, PseudoTHVdotVMAQASU_VX_M4, 0x3, false }, // 7 |
85 | | { PseudoTHVdotVMAQASU_VX_M8_MASK, PseudoTHVdotVMAQASU_VX_M8, 0x3, false }, // 8 |
86 | | { PseudoTHVdotVMAQASU_VX_MF2_MASK, PseudoTHVdotVMAQASU_VX_MF2, 0x3, false }, // 9 |
87 | | { PseudoTHVdotVMAQAUS_VX_M1_MASK, PseudoTHVdotVMAQAUS_VX_M1, 0x3, false }, // 10 |
88 | | { PseudoTHVdotVMAQAUS_VX_M2_MASK, PseudoTHVdotVMAQAUS_VX_M2, 0x3, false }, // 11 |
89 | | { PseudoTHVdotVMAQAUS_VX_M4_MASK, PseudoTHVdotVMAQAUS_VX_M4, 0x3, false }, // 12 |
90 | | { PseudoTHVdotVMAQAUS_VX_M8_MASK, PseudoTHVdotVMAQAUS_VX_M8, 0x3, false }, // 13 |
91 | | { PseudoTHVdotVMAQAUS_VX_MF2_MASK, PseudoTHVdotVMAQAUS_VX_MF2, 0x3, false }, // 14 |
92 | | { PseudoTHVdotVMAQAU_VV_M1_MASK, PseudoTHVdotVMAQAU_VV_M1, 0x3, false }, // 15 |
93 | | { PseudoTHVdotVMAQAU_VV_M2_MASK, PseudoTHVdotVMAQAU_VV_M2, 0x3, false }, // 16 |
94 | | { PseudoTHVdotVMAQAU_VV_M4_MASK, PseudoTHVdotVMAQAU_VV_M4, 0x3, false }, // 17 |
95 | | { PseudoTHVdotVMAQAU_VV_M8_MASK, PseudoTHVdotVMAQAU_VV_M8, 0x3, false }, // 18 |
96 | | { PseudoTHVdotVMAQAU_VV_MF2_MASK, PseudoTHVdotVMAQAU_VV_MF2, 0x3, false }, // 19 |
97 | | { PseudoTHVdotVMAQAU_VX_M1_MASK, PseudoTHVdotVMAQAU_VX_M1, 0x3, false }, // 20 |
98 | | { PseudoTHVdotVMAQAU_VX_M2_MASK, PseudoTHVdotVMAQAU_VX_M2, 0x3, false }, // 21 |
99 | | { PseudoTHVdotVMAQAU_VX_M4_MASK, PseudoTHVdotVMAQAU_VX_M4, 0x3, false }, // 22 |
100 | | { PseudoTHVdotVMAQAU_VX_M8_MASK, PseudoTHVdotVMAQAU_VX_M8, 0x3, false }, // 23 |
101 | | { PseudoTHVdotVMAQAU_VX_MF2_MASK, PseudoTHVdotVMAQAU_VX_MF2, 0x3, false }, // 24 |
102 | | { PseudoTHVdotVMAQA_VV_M1_MASK, PseudoTHVdotVMAQA_VV_M1, 0x3, false }, // 25 |
103 | | { PseudoTHVdotVMAQA_VV_M2_MASK, PseudoTHVdotVMAQA_VV_M2, 0x3, false }, // 26 |
104 | | { PseudoTHVdotVMAQA_VV_M4_MASK, PseudoTHVdotVMAQA_VV_M4, 0x3, false }, // 27 |
105 | | { PseudoTHVdotVMAQA_VV_M8_MASK, PseudoTHVdotVMAQA_VV_M8, 0x3, false }, // 28 |
106 | | { PseudoTHVdotVMAQA_VV_MF2_MASK, PseudoTHVdotVMAQA_VV_MF2, 0x3, false }, // 29 |
107 | | { PseudoTHVdotVMAQA_VX_M1_MASK, PseudoTHVdotVMAQA_VX_M1, 0x3, false }, // 30 |
108 | | { PseudoTHVdotVMAQA_VX_M2_MASK, PseudoTHVdotVMAQA_VX_M2, 0x3, false }, // 31 |
109 | | { PseudoTHVdotVMAQA_VX_M4_MASK, PseudoTHVdotVMAQA_VX_M4, 0x3, false }, // 32 |
110 | | { PseudoTHVdotVMAQA_VX_M8_MASK, PseudoTHVdotVMAQA_VX_M8, 0x3, false }, // 33 |
111 | | { PseudoTHVdotVMAQA_VX_MF2_MASK, PseudoTHVdotVMAQA_VX_MF2, 0x3, false }, // 34 |
112 | | { PseudoVAADDU_VV_M1_MASK, PseudoVAADDU_VV_M1, 0x3, false }, // 35 |
113 | | { PseudoVAADDU_VV_M2_MASK, PseudoVAADDU_VV_M2, 0x3, false }, // 36 |
114 | | { PseudoVAADDU_VV_M4_MASK, PseudoVAADDU_VV_M4, 0x3, false }, // 37 |
115 | | { PseudoVAADDU_VV_M8_MASK, PseudoVAADDU_VV_M8, 0x3, false }, // 38 |
116 | | { PseudoVAADDU_VV_MF2_MASK, PseudoVAADDU_VV_MF2, 0x3, false }, // 39 |
117 | | { PseudoVAADDU_VV_MF4_MASK, PseudoVAADDU_VV_MF4, 0x3, false }, // 40 |
118 | | { PseudoVAADDU_VV_MF8_MASK, PseudoVAADDU_VV_MF8, 0x3, false }, // 41 |
119 | | { PseudoVAADDU_VX_M1_MASK, PseudoVAADDU_VX_M1, 0x3, false }, // 42 |
120 | | { PseudoVAADDU_VX_M2_MASK, PseudoVAADDU_VX_M2, 0x3, false }, // 43 |
121 | | { PseudoVAADDU_VX_M4_MASK, PseudoVAADDU_VX_M4, 0x3, false }, // 44 |
122 | | { PseudoVAADDU_VX_M8_MASK, PseudoVAADDU_VX_M8, 0x3, false }, // 45 |
123 | | { PseudoVAADDU_VX_MF2_MASK, PseudoVAADDU_VX_MF2, 0x3, false }, // 46 |
124 | | { PseudoVAADDU_VX_MF4_MASK, PseudoVAADDU_VX_MF4, 0x3, false }, // 47 |
125 | | { PseudoVAADDU_VX_MF8_MASK, PseudoVAADDU_VX_MF8, 0x3, false }, // 48 |
126 | | { PseudoVAADD_VV_M1_MASK, PseudoVAADD_VV_M1, 0x3, false }, // 49 |
127 | | { PseudoVAADD_VV_M2_MASK, PseudoVAADD_VV_M2, 0x3, false }, // 50 |
128 | | { PseudoVAADD_VV_M4_MASK, PseudoVAADD_VV_M4, 0x3, false }, // 51 |
129 | | { PseudoVAADD_VV_M8_MASK, PseudoVAADD_VV_M8, 0x3, false }, // 52 |
130 | | { PseudoVAADD_VV_MF2_MASK, PseudoVAADD_VV_MF2, 0x3, false }, // 53 |
131 | | { PseudoVAADD_VV_MF4_MASK, PseudoVAADD_VV_MF4, 0x3, false }, // 54 |
132 | | { PseudoVAADD_VV_MF8_MASK, PseudoVAADD_VV_MF8, 0x3, false }, // 55 |
133 | | { PseudoVAADD_VX_M1_MASK, PseudoVAADD_VX_M1, 0x3, false }, // 56 |
134 | | { PseudoVAADD_VX_M2_MASK, PseudoVAADD_VX_M2, 0x3, false }, // 57 |
135 | | { PseudoVAADD_VX_M4_MASK, PseudoVAADD_VX_M4, 0x3, false }, // 58 |
136 | | { PseudoVAADD_VX_M8_MASK, PseudoVAADD_VX_M8, 0x3, false }, // 59 |
137 | | { PseudoVAADD_VX_MF2_MASK, PseudoVAADD_VX_MF2, 0x3, false }, // 60 |
138 | | { PseudoVAADD_VX_MF4_MASK, PseudoVAADD_VX_MF4, 0x3, false }, // 61 |
139 | | { PseudoVAADD_VX_MF8_MASK, PseudoVAADD_VX_MF8, 0x3, false }, // 62 |
140 | | { PseudoVADD_VI_M1_MASK, PseudoVADD_VI_M1, 0x3, false }, // 63 |
141 | | { PseudoVADD_VI_M2_MASK, PseudoVADD_VI_M2, 0x3, false }, // 64 |
142 | | { PseudoVADD_VI_M4_MASK, PseudoVADD_VI_M4, 0x3, false }, // 65 |
143 | | { PseudoVADD_VI_M8_MASK, PseudoVADD_VI_M8, 0x3, false }, // 66 |
144 | | { PseudoVADD_VI_MF2_MASK, PseudoVADD_VI_MF2, 0x3, false }, // 67 |
145 | | { PseudoVADD_VI_MF4_MASK, PseudoVADD_VI_MF4, 0x3, false }, // 68 |
146 | | { PseudoVADD_VI_MF8_MASK, PseudoVADD_VI_MF8, 0x3, false }, // 69 |
147 | | { PseudoVADD_VV_M1_MASK, PseudoVADD_VV_M1, 0x3, false }, // 70 |
148 | | { PseudoVADD_VV_M2_MASK, PseudoVADD_VV_M2, 0x3, false }, // 71 |
149 | | { PseudoVADD_VV_M4_MASK, PseudoVADD_VV_M4, 0x3, false }, // 72 |
150 | | { PseudoVADD_VV_M8_MASK, PseudoVADD_VV_M8, 0x3, false }, // 73 |
151 | | { PseudoVADD_VV_MF2_MASK, PseudoVADD_VV_MF2, 0x3, false }, // 74 |
152 | | { PseudoVADD_VV_MF4_MASK, PseudoVADD_VV_MF4, 0x3, false }, // 75 |
153 | | { PseudoVADD_VV_MF8_MASK, PseudoVADD_VV_MF8, 0x3, false }, // 76 |
154 | | { PseudoVADD_VX_M1_MASK, PseudoVADD_VX_M1, 0x3, false }, // 77 |
155 | | { PseudoVADD_VX_M2_MASK, PseudoVADD_VX_M2, 0x3, false }, // 78 |
156 | | { PseudoVADD_VX_M4_MASK, PseudoVADD_VX_M4, 0x3, false }, // 79 |
157 | | { PseudoVADD_VX_M8_MASK, PseudoVADD_VX_M8, 0x3, false }, // 80 |
158 | | { PseudoVADD_VX_MF2_MASK, PseudoVADD_VX_MF2, 0x3, false }, // 81 |
159 | | { PseudoVADD_VX_MF4_MASK, PseudoVADD_VX_MF4, 0x3, false }, // 82 |
160 | | { PseudoVADD_VX_MF8_MASK, PseudoVADD_VX_MF8, 0x3, false }, // 83 |
161 | | { PseudoVANDN_VV_M1_MASK, PseudoVANDN_VV_M1, 0x3, false }, // 84 |
162 | | { PseudoVANDN_VV_M2_MASK, PseudoVANDN_VV_M2, 0x3, false }, // 85 |
163 | | { PseudoVANDN_VV_M4_MASK, PseudoVANDN_VV_M4, 0x3, false }, // 86 |
164 | | { PseudoVANDN_VV_M8_MASK, PseudoVANDN_VV_M8, 0x3, false }, // 87 |
165 | | { PseudoVANDN_VV_MF2_MASK, PseudoVANDN_VV_MF2, 0x3, false }, // 88 |
166 | | { PseudoVANDN_VV_MF4_MASK, PseudoVANDN_VV_MF4, 0x3, false }, // 89 |
167 | | { PseudoVANDN_VV_MF8_MASK, PseudoVANDN_VV_MF8, 0x3, false }, // 90 |
168 | | { PseudoVANDN_VX_M1_MASK, PseudoVANDN_VX_M1, 0x3, false }, // 91 |
169 | | { PseudoVANDN_VX_M2_MASK, PseudoVANDN_VX_M2, 0x3, false }, // 92 |
170 | | { PseudoVANDN_VX_M4_MASK, PseudoVANDN_VX_M4, 0x3, false }, // 93 |
171 | | { PseudoVANDN_VX_M8_MASK, PseudoVANDN_VX_M8, 0x3, false }, // 94 |
172 | | { PseudoVANDN_VX_MF2_MASK, PseudoVANDN_VX_MF2, 0x3, false }, // 95 |
173 | | { PseudoVANDN_VX_MF4_MASK, PseudoVANDN_VX_MF4, 0x3, false }, // 96 |
174 | | { PseudoVANDN_VX_MF8_MASK, PseudoVANDN_VX_MF8, 0x3, false }, // 97 |
175 | | { PseudoVAND_VI_M1_MASK, PseudoVAND_VI_M1, 0x3, false }, // 98 |
176 | | { PseudoVAND_VI_M2_MASK, PseudoVAND_VI_M2, 0x3, false }, // 99 |
177 | | { PseudoVAND_VI_M4_MASK, PseudoVAND_VI_M4, 0x3, false }, // 100 |
178 | | { PseudoVAND_VI_M8_MASK, PseudoVAND_VI_M8, 0x3, false }, // 101 |
179 | | { PseudoVAND_VI_MF2_MASK, PseudoVAND_VI_MF2, 0x3, false }, // 102 |
180 | | { PseudoVAND_VI_MF4_MASK, PseudoVAND_VI_MF4, 0x3, false }, // 103 |
181 | | { PseudoVAND_VI_MF8_MASK, PseudoVAND_VI_MF8, 0x3, false }, // 104 |
182 | | { PseudoVAND_VV_M1_MASK, PseudoVAND_VV_M1, 0x3, false }, // 105 |
183 | | { PseudoVAND_VV_M2_MASK, PseudoVAND_VV_M2, 0x3, false }, // 106 |
184 | | { PseudoVAND_VV_M4_MASK, PseudoVAND_VV_M4, 0x3, false }, // 107 |
185 | | { PseudoVAND_VV_M8_MASK, PseudoVAND_VV_M8, 0x3, false }, // 108 |
186 | | { PseudoVAND_VV_MF2_MASK, PseudoVAND_VV_MF2, 0x3, false }, // 109 |
187 | | { PseudoVAND_VV_MF4_MASK, PseudoVAND_VV_MF4, 0x3, false }, // 110 |
188 | | { PseudoVAND_VV_MF8_MASK, PseudoVAND_VV_MF8, 0x3, false }, // 111 |
189 | | { PseudoVAND_VX_M1_MASK, PseudoVAND_VX_M1, 0x3, false }, // 112 |
190 | | { PseudoVAND_VX_M2_MASK, PseudoVAND_VX_M2, 0x3, false }, // 113 |
191 | | { PseudoVAND_VX_M4_MASK, PseudoVAND_VX_M4, 0x3, false }, // 114 |
192 | | { PseudoVAND_VX_M8_MASK, PseudoVAND_VX_M8, 0x3, false }, // 115 |
193 | | { PseudoVAND_VX_MF2_MASK, PseudoVAND_VX_MF2, 0x3, false }, // 116 |
194 | | { PseudoVAND_VX_MF4_MASK, PseudoVAND_VX_MF4, 0x3, false }, // 117 |
195 | | { PseudoVAND_VX_MF8_MASK, PseudoVAND_VX_MF8, 0x3, false }, // 118 |
196 | | { PseudoVASUBU_VV_M1_MASK, PseudoVASUBU_VV_M1, 0x3, false }, // 119 |
197 | | { PseudoVASUBU_VV_M2_MASK, PseudoVASUBU_VV_M2, 0x3, false }, // 120 |
198 | | { PseudoVASUBU_VV_M4_MASK, PseudoVASUBU_VV_M4, 0x3, false }, // 121 |
199 | | { PseudoVASUBU_VV_M8_MASK, PseudoVASUBU_VV_M8, 0x3, false }, // 122 |
200 | | { PseudoVASUBU_VV_MF2_MASK, PseudoVASUBU_VV_MF2, 0x3, false }, // 123 |
201 | | { PseudoVASUBU_VV_MF4_MASK, PseudoVASUBU_VV_MF4, 0x3, false }, // 124 |
202 | | { PseudoVASUBU_VV_MF8_MASK, PseudoVASUBU_VV_MF8, 0x3, false }, // 125 |
203 | | { PseudoVASUBU_VX_M1_MASK, PseudoVASUBU_VX_M1, 0x3, false }, // 126 |
204 | | { PseudoVASUBU_VX_M2_MASK, PseudoVASUBU_VX_M2, 0x3, false }, // 127 |
205 | | { PseudoVASUBU_VX_M4_MASK, PseudoVASUBU_VX_M4, 0x3, false }, // 128 |
206 | | { PseudoVASUBU_VX_M8_MASK, PseudoVASUBU_VX_M8, 0x3, false }, // 129 |
207 | | { PseudoVASUBU_VX_MF2_MASK, PseudoVASUBU_VX_MF2, 0x3, false }, // 130 |
208 | | { PseudoVASUBU_VX_MF4_MASK, PseudoVASUBU_VX_MF4, 0x3, false }, // 131 |
209 | | { PseudoVASUBU_VX_MF8_MASK, PseudoVASUBU_VX_MF8, 0x3, false }, // 132 |
210 | | { PseudoVASUB_VV_M1_MASK, PseudoVASUB_VV_M1, 0x3, false }, // 133 |
211 | | { PseudoVASUB_VV_M2_MASK, PseudoVASUB_VV_M2, 0x3, false }, // 134 |
212 | | { PseudoVASUB_VV_M4_MASK, PseudoVASUB_VV_M4, 0x3, false }, // 135 |
213 | | { PseudoVASUB_VV_M8_MASK, PseudoVASUB_VV_M8, 0x3, false }, // 136 |
214 | | { PseudoVASUB_VV_MF2_MASK, PseudoVASUB_VV_MF2, 0x3, false }, // 137 |
215 | | { PseudoVASUB_VV_MF4_MASK, PseudoVASUB_VV_MF4, 0x3, false }, // 138 |
216 | | { PseudoVASUB_VV_MF8_MASK, PseudoVASUB_VV_MF8, 0x3, false }, // 139 |
217 | | { PseudoVASUB_VX_M1_MASK, PseudoVASUB_VX_M1, 0x3, false }, // 140 |
218 | | { PseudoVASUB_VX_M2_MASK, PseudoVASUB_VX_M2, 0x3, false }, // 141 |
219 | | { PseudoVASUB_VX_M4_MASK, PseudoVASUB_VX_M4, 0x3, false }, // 142 |
220 | | { PseudoVASUB_VX_M8_MASK, PseudoVASUB_VX_M8, 0x3, false }, // 143 |
221 | | { PseudoVASUB_VX_MF2_MASK, PseudoVASUB_VX_MF2, 0x3, false }, // 144 |
222 | | { PseudoVASUB_VX_MF4_MASK, PseudoVASUB_VX_MF4, 0x3, false }, // 145 |
223 | | { PseudoVASUB_VX_MF8_MASK, PseudoVASUB_VX_MF8, 0x3, false }, // 146 |
224 | | { PseudoVBREV8_V_M1_MASK, PseudoVBREV8_V_M1, 0x2, false }, // 147 |
225 | | { PseudoVBREV8_V_M2_MASK, PseudoVBREV8_V_M2, 0x2, false }, // 148 |
226 | | { PseudoVBREV8_V_M4_MASK, PseudoVBREV8_V_M4, 0x2, false }, // 149 |
227 | | { PseudoVBREV8_V_M8_MASK, PseudoVBREV8_V_M8, 0x2, false }, // 150 |
228 | | { PseudoVBREV8_V_MF2_MASK, PseudoVBREV8_V_MF2, 0x2, false }, // 151 |
229 | | { PseudoVBREV8_V_MF4_MASK, PseudoVBREV8_V_MF4, 0x2, false }, // 152 |
230 | | { PseudoVBREV8_V_MF8_MASK, PseudoVBREV8_V_MF8, 0x2, false }, // 153 |
231 | | { PseudoVBREV_V_M1_MASK, PseudoVBREV_V_M1, 0x2, false }, // 154 |
232 | | { PseudoVBREV_V_M2_MASK, PseudoVBREV_V_M2, 0x2, false }, // 155 |
233 | | { PseudoVBREV_V_M4_MASK, PseudoVBREV_V_M4, 0x2, false }, // 156 |
234 | | { PseudoVBREV_V_M8_MASK, PseudoVBREV_V_M8, 0x2, false }, // 157 |
235 | | { PseudoVBREV_V_MF2_MASK, PseudoVBREV_V_MF2, 0x2, false }, // 158 |
236 | | { PseudoVBREV_V_MF4_MASK, PseudoVBREV_V_MF4, 0x2, false }, // 159 |
237 | | { PseudoVBREV_V_MF8_MASK, PseudoVBREV_V_MF8, 0x2, false }, // 160 |
238 | | { PseudoVCLMULH_VV_M1_MASK, PseudoVCLMULH_VV_M1, 0x3, false }, // 161 |
239 | | { PseudoVCLMULH_VV_M2_MASK, PseudoVCLMULH_VV_M2, 0x3, false }, // 162 |
240 | | { PseudoVCLMULH_VV_M4_MASK, PseudoVCLMULH_VV_M4, 0x3, false }, // 163 |
241 | | { PseudoVCLMULH_VV_M8_MASK, PseudoVCLMULH_VV_M8, 0x3, false }, // 164 |
242 | | { PseudoVCLMULH_VV_MF2_MASK, PseudoVCLMULH_VV_MF2, 0x3, false }, // 165 |
243 | | { PseudoVCLMULH_VV_MF4_MASK, PseudoVCLMULH_VV_MF4, 0x3, false }, // 166 |
244 | | { PseudoVCLMULH_VV_MF8_MASK, PseudoVCLMULH_VV_MF8, 0x3, false }, // 167 |
245 | | { PseudoVCLMULH_VX_M1_MASK, PseudoVCLMULH_VX_M1, 0x3, false }, // 168 |
246 | | { PseudoVCLMULH_VX_M2_MASK, PseudoVCLMULH_VX_M2, 0x3, false }, // 169 |
247 | | { PseudoVCLMULH_VX_M4_MASK, PseudoVCLMULH_VX_M4, 0x3, false }, // 170 |
248 | | { PseudoVCLMULH_VX_M8_MASK, PseudoVCLMULH_VX_M8, 0x3, false }, // 171 |
249 | | { PseudoVCLMULH_VX_MF2_MASK, PseudoVCLMULH_VX_MF2, 0x3, false }, // 172 |
250 | | { PseudoVCLMULH_VX_MF4_MASK, PseudoVCLMULH_VX_MF4, 0x3, false }, // 173 |
251 | | { PseudoVCLMULH_VX_MF8_MASK, PseudoVCLMULH_VX_MF8, 0x3, false }, // 174 |
252 | | { PseudoVCLMUL_VV_M1_MASK, PseudoVCLMUL_VV_M1, 0x3, false }, // 175 |
253 | | { PseudoVCLMUL_VV_M2_MASK, PseudoVCLMUL_VV_M2, 0x3, false }, // 176 |
254 | | { PseudoVCLMUL_VV_M4_MASK, PseudoVCLMUL_VV_M4, 0x3, false }, // 177 |
255 | | { PseudoVCLMUL_VV_M8_MASK, PseudoVCLMUL_VV_M8, 0x3, false }, // 178 |
256 | | { PseudoVCLMUL_VV_MF2_MASK, PseudoVCLMUL_VV_MF2, 0x3, false }, // 179 |
257 | | { PseudoVCLMUL_VV_MF4_MASK, PseudoVCLMUL_VV_MF4, 0x3, false }, // 180 |
258 | | { PseudoVCLMUL_VV_MF8_MASK, PseudoVCLMUL_VV_MF8, 0x3, false }, // 181 |
259 | | { PseudoVCLMUL_VX_M1_MASK, PseudoVCLMUL_VX_M1, 0x3, false }, // 182 |
260 | | { PseudoVCLMUL_VX_M2_MASK, PseudoVCLMUL_VX_M2, 0x3, false }, // 183 |
261 | | { PseudoVCLMUL_VX_M4_MASK, PseudoVCLMUL_VX_M4, 0x3, false }, // 184 |
262 | | { PseudoVCLMUL_VX_M8_MASK, PseudoVCLMUL_VX_M8, 0x3, false }, // 185 |
263 | | { PseudoVCLMUL_VX_MF2_MASK, PseudoVCLMUL_VX_MF2, 0x3, false }, // 186 |
264 | | { PseudoVCLMUL_VX_MF4_MASK, PseudoVCLMUL_VX_MF4, 0x3, false }, // 187 |
265 | | { PseudoVCLMUL_VX_MF8_MASK, PseudoVCLMUL_VX_MF8, 0x3, false }, // 188 |
266 | | { PseudoVCLZ_V_M1_MASK, PseudoVCLZ_V_M1, 0x2, false }, // 189 |
267 | | { PseudoVCLZ_V_M2_MASK, PseudoVCLZ_V_M2, 0x2, false }, // 190 |
268 | | { PseudoVCLZ_V_M4_MASK, PseudoVCLZ_V_M4, 0x2, false }, // 191 |
269 | | { PseudoVCLZ_V_M8_MASK, PseudoVCLZ_V_M8, 0x2, false }, // 192 |
270 | | { PseudoVCLZ_V_MF2_MASK, PseudoVCLZ_V_MF2, 0x2, false }, // 193 |
271 | | { PseudoVCLZ_V_MF4_MASK, PseudoVCLZ_V_MF4, 0x2, false }, // 194 |
272 | | { PseudoVCLZ_V_MF8_MASK, PseudoVCLZ_V_MF8, 0x2, false }, // 195 |
273 | | { PseudoVCPOP_V_M1_MASK, PseudoVCPOP_V_M1, 0x2, false }, // 196 |
274 | | { PseudoVCPOP_V_M2_MASK, PseudoVCPOP_V_M2, 0x2, false }, // 197 |
275 | | { PseudoVCPOP_V_M4_MASK, PseudoVCPOP_V_M4, 0x2, false }, // 198 |
276 | | { PseudoVCPOP_V_M8_MASK, PseudoVCPOP_V_M8, 0x2, false }, // 199 |
277 | | { PseudoVCPOP_V_MF2_MASK, PseudoVCPOP_V_MF2, 0x2, false }, // 200 |
278 | | { PseudoVCPOP_V_MF4_MASK, PseudoVCPOP_V_MF4, 0x2, false }, // 201 |
279 | | { PseudoVCPOP_V_MF8_MASK, PseudoVCPOP_V_MF8, 0x2, false }, // 202 |
280 | | { PseudoVCTZ_V_M1_MASK, PseudoVCTZ_V_M1, 0x2, false }, // 203 |
281 | | { PseudoVCTZ_V_M2_MASK, PseudoVCTZ_V_M2, 0x2, false }, // 204 |
282 | | { PseudoVCTZ_V_M4_MASK, PseudoVCTZ_V_M4, 0x2, false }, // 205 |
283 | | { PseudoVCTZ_V_M8_MASK, PseudoVCTZ_V_M8, 0x2, false }, // 206 |
284 | | { PseudoVCTZ_V_MF2_MASK, PseudoVCTZ_V_MF2, 0x2, false }, // 207 |
285 | | { PseudoVCTZ_V_MF4_MASK, PseudoVCTZ_V_MF4, 0x2, false }, // 208 |
286 | | { PseudoVCTZ_V_MF8_MASK, PseudoVCTZ_V_MF8, 0x2, false }, // 209 |
287 | | { PseudoVDIVU_VV_M1_E16_MASK, PseudoVDIVU_VV_M1_E16, 0x3, false }, // 210 |
288 | | { PseudoVDIVU_VV_M1_E32_MASK, PseudoVDIVU_VV_M1_E32, 0x3, false }, // 211 |
289 | | { PseudoVDIVU_VV_M1_E64_MASK, PseudoVDIVU_VV_M1_E64, 0x3, false }, // 212 |
290 | | { PseudoVDIVU_VV_M1_E8_MASK, PseudoVDIVU_VV_M1_E8, 0x3, false }, // 213 |
291 | | { PseudoVDIVU_VV_M2_E16_MASK, PseudoVDIVU_VV_M2_E16, 0x3, false }, // 214 |
292 | | { PseudoVDIVU_VV_M2_E32_MASK, PseudoVDIVU_VV_M2_E32, 0x3, false }, // 215 |
293 | | { PseudoVDIVU_VV_M2_E64_MASK, PseudoVDIVU_VV_M2_E64, 0x3, false }, // 216 |
294 | | { PseudoVDIVU_VV_M2_E8_MASK, PseudoVDIVU_VV_M2_E8, 0x3, false }, // 217 |
295 | | { PseudoVDIVU_VV_M4_E16_MASK, PseudoVDIVU_VV_M4_E16, 0x3, false }, // 218 |
296 | | { PseudoVDIVU_VV_M4_E32_MASK, PseudoVDIVU_VV_M4_E32, 0x3, false }, // 219 |
297 | | { PseudoVDIVU_VV_M4_E64_MASK, PseudoVDIVU_VV_M4_E64, 0x3, false }, // 220 |
298 | | { PseudoVDIVU_VV_M4_E8_MASK, PseudoVDIVU_VV_M4_E8, 0x3, false }, // 221 |
299 | | { PseudoVDIVU_VV_M8_E16_MASK, PseudoVDIVU_VV_M8_E16, 0x3, false }, // 222 |
300 | | { PseudoVDIVU_VV_M8_E32_MASK, PseudoVDIVU_VV_M8_E32, 0x3, false }, // 223 |
301 | | { PseudoVDIVU_VV_M8_E64_MASK, PseudoVDIVU_VV_M8_E64, 0x3, false }, // 224 |
302 | | { PseudoVDIVU_VV_M8_E8_MASK, PseudoVDIVU_VV_M8_E8, 0x3, false }, // 225 |
303 | | { PseudoVDIVU_VV_MF2_E16_MASK, PseudoVDIVU_VV_MF2_E16, 0x3, false }, // 226 |
304 | | { PseudoVDIVU_VV_MF2_E32_MASK, PseudoVDIVU_VV_MF2_E32, 0x3, false }, // 227 |
305 | | { PseudoVDIVU_VV_MF2_E8_MASK, PseudoVDIVU_VV_MF2_E8, 0x3, false }, // 228 |
306 | | { PseudoVDIVU_VV_MF4_E16_MASK, PseudoVDIVU_VV_MF4_E16, 0x3, false }, // 229 |
307 | | { PseudoVDIVU_VV_MF4_E8_MASK, PseudoVDIVU_VV_MF4_E8, 0x3, false }, // 230 |
308 | | { PseudoVDIVU_VV_MF8_E8_MASK, PseudoVDIVU_VV_MF8_E8, 0x3, false }, // 231 |
309 | | { PseudoVDIVU_VX_M1_E16_MASK, PseudoVDIVU_VX_M1_E16, 0x3, false }, // 232 |
310 | | { PseudoVDIVU_VX_M1_E32_MASK, PseudoVDIVU_VX_M1_E32, 0x3, false }, // 233 |
311 | | { PseudoVDIVU_VX_M1_E64_MASK, PseudoVDIVU_VX_M1_E64, 0x3, false }, // 234 |
312 | | { PseudoVDIVU_VX_M1_E8_MASK, PseudoVDIVU_VX_M1_E8, 0x3, false }, // 235 |
313 | | { PseudoVDIVU_VX_M2_E16_MASK, PseudoVDIVU_VX_M2_E16, 0x3, false }, // 236 |
314 | | { PseudoVDIVU_VX_M2_E32_MASK, PseudoVDIVU_VX_M2_E32, 0x3, false }, // 237 |
315 | | { PseudoVDIVU_VX_M2_E64_MASK, PseudoVDIVU_VX_M2_E64, 0x3, false }, // 238 |
316 | | { PseudoVDIVU_VX_M2_E8_MASK, PseudoVDIVU_VX_M2_E8, 0x3, false }, // 239 |
317 | | { PseudoVDIVU_VX_M4_E16_MASK, PseudoVDIVU_VX_M4_E16, 0x3, false }, // 240 |
318 | | { PseudoVDIVU_VX_M4_E32_MASK, PseudoVDIVU_VX_M4_E32, 0x3, false }, // 241 |
319 | | { PseudoVDIVU_VX_M4_E64_MASK, PseudoVDIVU_VX_M4_E64, 0x3, false }, // 242 |
320 | | { PseudoVDIVU_VX_M4_E8_MASK, PseudoVDIVU_VX_M4_E8, 0x3, false }, // 243 |
321 | | { PseudoVDIVU_VX_M8_E16_MASK, PseudoVDIVU_VX_M8_E16, 0x3, false }, // 244 |
322 | | { PseudoVDIVU_VX_M8_E32_MASK, PseudoVDIVU_VX_M8_E32, 0x3, false }, // 245 |
323 | | { PseudoVDIVU_VX_M8_E64_MASK, PseudoVDIVU_VX_M8_E64, 0x3, false }, // 246 |
324 | | { PseudoVDIVU_VX_M8_E8_MASK, PseudoVDIVU_VX_M8_E8, 0x3, false }, // 247 |
325 | | { PseudoVDIVU_VX_MF2_E16_MASK, PseudoVDIVU_VX_MF2_E16, 0x3, false }, // 248 |
326 | | { PseudoVDIVU_VX_MF2_E32_MASK, PseudoVDIVU_VX_MF2_E32, 0x3, false }, // 249 |
327 | | { PseudoVDIVU_VX_MF2_E8_MASK, PseudoVDIVU_VX_MF2_E8, 0x3, false }, // 250 |
328 | | { PseudoVDIVU_VX_MF4_E16_MASK, PseudoVDIVU_VX_MF4_E16, 0x3, false }, // 251 |
329 | | { PseudoVDIVU_VX_MF4_E8_MASK, PseudoVDIVU_VX_MF4_E8, 0x3, false }, // 252 |
330 | | { PseudoVDIVU_VX_MF8_E8_MASK, PseudoVDIVU_VX_MF8_E8, 0x3, false }, // 253 |
331 | | { PseudoVDIV_VV_M1_E16_MASK, PseudoVDIV_VV_M1_E16, 0x3, false }, // 254 |
332 | | { PseudoVDIV_VV_M1_E32_MASK, PseudoVDIV_VV_M1_E32, 0x3, false }, // 255 |
333 | | { PseudoVDIV_VV_M1_E64_MASK, PseudoVDIV_VV_M1_E64, 0x3, false }, // 256 |
334 | | { PseudoVDIV_VV_M1_E8_MASK, PseudoVDIV_VV_M1_E8, 0x3, false }, // 257 |
335 | | { PseudoVDIV_VV_M2_E16_MASK, PseudoVDIV_VV_M2_E16, 0x3, false }, // 258 |
336 | | { PseudoVDIV_VV_M2_E32_MASK, PseudoVDIV_VV_M2_E32, 0x3, false }, // 259 |
337 | | { PseudoVDIV_VV_M2_E64_MASK, PseudoVDIV_VV_M2_E64, 0x3, false }, // 260 |
338 | | { PseudoVDIV_VV_M2_E8_MASK, PseudoVDIV_VV_M2_E8, 0x3, false }, // 261 |
339 | | { PseudoVDIV_VV_M4_E16_MASK, PseudoVDIV_VV_M4_E16, 0x3, false }, // 262 |
340 | | { PseudoVDIV_VV_M4_E32_MASK, PseudoVDIV_VV_M4_E32, 0x3, false }, // 263 |
341 | | { PseudoVDIV_VV_M4_E64_MASK, PseudoVDIV_VV_M4_E64, 0x3, false }, // 264 |
342 | | { PseudoVDIV_VV_M4_E8_MASK, PseudoVDIV_VV_M4_E8, 0x3, false }, // 265 |
343 | | { PseudoVDIV_VV_M8_E16_MASK, PseudoVDIV_VV_M8_E16, 0x3, false }, // 266 |
344 | | { PseudoVDIV_VV_M8_E32_MASK, PseudoVDIV_VV_M8_E32, 0x3, false }, // 267 |
345 | | { PseudoVDIV_VV_M8_E64_MASK, PseudoVDIV_VV_M8_E64, 0x3, false }, // 268 |
346 | | { PseudoVDIV_VV_M8_E8_MASK, PseudoVDIV_VV_M8_E8, 0x3, false }, // 269 |
347 | | { PseudoVDIV_VV_MF2_E16_MASK, PseudoVDIV_VV_MF2_E16, 0x3, false }, // 270 |
348 | | { PseudoVDIV_VV_MF2_E32_MASK, PseudoVDIV_VV_MF2_E32, 0x3, false }, // 271 |
349 | | { PseudoVDIV_VV_MF2_E8_MASK, PseudoVDIV_VV_MF2_E8, 0x3, false }, // 272 |
350 | | { PseudoVDIV_VV_MF4_E16_MASK, PseudoVDIV_VV_MF4_E16, 0x3, false }, // 273 |
351 | | { PseudoVDIV_VV_MF4_E8_MASK, PseudoVDIV_VV_MF4_E8, 0x3, false }, // 274 |
352 | | { PseudoVDIV_VV_MF8_E8_MASK, PseudoVDIV_VV_MF8_E8, 0x3, false }, // 275 |
353 | | { PseudoVDIV_VX_M1_E16_MASK, PseudoVDIV_VX_M1_E16, 0x3, false }, // 276 |
354 | | { PseudoVDIV_VX_M1_E32_MASK, PseudoVDIV_VX_M1_E32, 0x3, false }, // 277 |
355 | | { PseudoVDIV_VX_M1_E64_MASK, PseudoVDIV_VX_M1_E64, 0x3, false }, // 278 |
356 | | { PseudoVDIV_VX_M1_E8_MASK, PseudoVDIV_VX_M1_E8, 0x3, false }, // 279 |
357 | | { PseudoVDIV_VX_M2_E16_MASK, PseudoVDIV_VX_M2_E16, 0x3, false }, // 280 |
358 | | { PseudoVDIV_VX_M2_E32_MASK, PseudoVDIV_VX_M2_E32, 0x3, false }, // 281 |
359 | | { PseudoVDIV_VX_M2_E64_MASK, PseudoVDIV_VX_M2_E64, 0x3, false }, // 282 |
360 | | { PseudoVDIV_VX_M2_E8_MASK, PseudoVDIV_VX_M2_E8, 0x3, false }, // 283 |
361 | | { PseudoVDIV_VX_M4_E16_MASK, PseudoVDIV_VX_M4_E16, 0x3, false }, // 284 |
362 | | { PseudoVDIV_VX_M4_E32_MASK, PseudoVDIV_VX_M4_E32, 0x3, false }, // 285 |
363 | | { PseudoVDIV_VX_M4_E64_MASK, PseudoVDIV_VX_M4_E64, 0x3, false }, // 286 |
364 | | { PseudoVDIV_VX_M4_E8_MASK, PseudoVDIV_VX_M4_E8, 0x3, false }, // 287 |
365 | | { PseudoVDIV_VX_M8_E16_MASK, PseudoVDIV_VX_M8_E16, 0x3, false }, // 288 |
366 | | { PseudoVDIV_VX_M8_E32_MASK, PseudoVDIV_VX_M8_E32, 0x3, false }, // 289 |
367 | | { PseudoVDIV_VX_M8_E64_MASK, PseudoVDIV_VX_M8_E64, 0x3, false }, // 290 |
368 | | { PseudoVDIV_VX_M8_E8_MASK, PseudoVDIV_VX_M8_E8, 0x3, false }, // 291 |
369 | | { PseudoVDIV_VX_MF2_E16_MASK, PseudoVDIV_VX_MF2_E16, 0x3, false }, // 292 |
370 | | { PseudoVDIV_VX_MF2_E32_MASK, PseudoVDIV_VX_MF2_E32, 0x3, false }, // 293 |
371 | | { PseudoVDIV_VX_MF2_E8_MASK, PseudoVDIV_VX_MF2_E8, 0x3, false }, // 294 |
372 | | { PseudoVDIV_VX_MF4_E16_MASK, PseudoVDIV_VX_MF4_E16, 0x3, false }, // 295 |
373 | | { PseudoVDIV_VX_MF4_E8_MASK, PseudoVDIV_VX_MF4_E8, 0x3, false }, // 296 |
374 | | { PseudoVDIV_VX_MF8_E8_MASK, PseudoVDIV_VX_MF8_E8, 0x3, false }, // 297 |
375 | | { PseudoVFADD_VFPR16_M1_MASK, PseudoVFADD_VFPR16_M1, 0x3, false }, // 298 |
376 | | { PseudoVFADD_VFPR16_M2_MASK, PseudoVFADD_VFPR16_M2, 0x3, false }, // 299 |
377 | | { PseudoVFADD_VFPR16_M4_MASK, PseudoVFADD_VFPR16_M4, 0x3, false }, // 300 |
378 | | { PseudoVFADD_VFPR16_M8_MASK, PseudoVFADD_VFPR16_M8, 0x3, false }, // 301 |
379 | | { PseudoVFADD_VFPR16_MF2_MASK, PseudoVFADD_VFPR16_MF2, 0x3, false }, // 302 |
380 | | { PseudoVFADD_VFPR16_MF4_MASK, PseudoVFADD_VFPR16_MF4, 0x3, false }, // 303 |
381 | | { PseudoVFADD_VFPR32_M1_MASK, PseudoVFADD_VFPR32_M1, 0x3, false }, // 304 |
382 | | { PseudoVFADD_VFPR32_M2_MASK, PseudoVFADD_VFPR32_M2, 0x3, false }, // 305 |
383 | | { PseudoVFADD_VFPR32_M4_MASK, PseudoVFADD_VFPR32_M4, 0x3, false }, // 306 |
384 | | { PseudoVFADD_VFPR32_M8_MASK, PseudoVFADD_VFPR32_M8, 0x3, false }, // 307 |
385 | | { PseudoVFADD_VFPR32_MF2_MASK, PseudoVFADD_VFPR32_MF2, 0x3, false }, // 308 |
386 | | { PseudoVFADD_VFPR64_M1_MASK, PseudoVFADD_VFPR64_M1, 0x3, false }, // 309 |
387 | | { PseudoVFADD_VFPR64_M2_MASK, PseudoVFADD_VFPR64_M2, 0x3, false }, // 310 |
388 | | { PseudoVFADD_VFPR64_M4_MASK, PseudoVFADD_VFPR64_M4, 0x3, false }, // 311 |
389 | | { PseudoVFADD_VFPR64_M8_MASK, PseudoVFADD_VFPR64_M8, 0x3, false }, // 312 |
390 | | { PseudoVFADD_VV_M1_MASK, PseudoVFADD_VV_M1, 0x3, false }, // 313 |
391 | | { PseudoVFADD_VV_M2_MASK, PseudoVFADD_VV_M2, 0x3, false }, // 314 |
392 | | { PseudoVFADD_VV_M4_MASK, PseudoVFADD_VV_M4, 0x3, false }, // 315 |
393 | | { PseudoVFADD_VV_M8_MASK, PseudoVFADD_VV_M8, 0x3, false }, // 316 |
394 | | { PseudoVFADD_VV_MF2_MASK, PseudoVFADD_VV_MF2, 0x3, false }, // 317 |
395 | | { PseudoVFADD_VV_MF4_MASK, PseudoVFADD_VV_MF4, 0x3, false }, // 318 |
396 | | { PseudoVFCLASS_V_M1_MASK, PseudoVFCLASS_V_M1, 0x2, false }, // 319 |
397 | | { PseudoVFCLASS_V_M2_MASK, PseudoVFCLASS_V_M2, 0x2, false }, // 320 |
398 | | { PseudoVFCLASS_V_M4_MASK, PseudoVFCLASS_V_M4, 0x2, false }, // 321 |
399 | | { PseudoVFCLASS_V_M8_MASK, PseudoVFCLASS_V_M8, 0x2, false }, // 322 |
400 | | { PseudoVFCLASS_V_MF2_MASK, PseudoVFCLASS_V_MF2, 0x2, false }, // 323 |
401 | | { PseudoVFCLASS_V_MF4_MASK, PseudoVFCLASS_V_MF4, 0x2, false }, // 324 |
402 | | { PseudoVFCVT_F_XU_V_M1_MASK, PseudoVFCVT_F_XU_V_M1, 0x2, false }, // 325 |
403 | | { PseudoVFCVT_F_XU_V_M2_MASK, PseudoVFCVT_F_XU_V_M2, 0x2, false }, // 326 |
404 | | { PseudoVFCVT_F_XU_V_M4_MASK, PseudoVFCVT_F_XU_V_M4, 0x2, false }, // 327 |
405 | | { PseudoVFCVT_F_XU_V_M8_MASK, PseudoVFCVT_F_XU_V_M8, 0x2, false }, // 328 |
406 | | { PseudoVFCVT_F_XU_V_MF2_MASK, PseudoVFCVT_F_XU_V_MF2, 0x2, false }, // 329 |
407 | | { PseudoVFCVT_F_XU_V_MF4_MASK, PseudoVFCVT_F_XU_V_MF4, 0x2, false }, // 330 |
408 | | { PseudoVFCVT_F_X_V_M1_MASK, PseudoVFCVT_F_X_V_M1, 0x2, false }, // 331 |
409 | | { PseudoVFCVT_F_X_V_M2_MASK, PseudoVFCVT_F_X_V_M2, 0x2, false }, // 332 |
410 | | { PseudoVFCVT_F_X_V_M4_MASK, PseudoVFCVT_F_X_V_M4, 0x2, false }, // 333 |
411 | | { PseudoVFCVT_F_X_V_M8_MASK, PseudoVFCVT_F_X_V_M8, 0x2, false }, // 334 |
412 | | { PseudoVFCVT_F_X_V_MF2_MASK, PseudoVFCVT_F_X_V_MF2, 0x2, false }, // 335 |
413 | | { PseudoVFCVT_F_X_V_MF4_MASK, PseudoVFCVT_F_X_V_MF4, 0x2, false }, // 336 |
414 | | { PseudoVFCVT_RM_F_XU_V_M1_MASK, PseudoVFCVT_RM_F_XU_V_M1, 0x2, false }, // 337 |
415 | | { PseudoVFCVT_RM_F_XU_V_M2_MASK, PseudoVFCVT_RM_F_XU_V_M2, 0x2, false }, // 338 |
416 | | { PseudoVFCVT_RM_F_XU_V_M4_MASK, PseudoVFCVT_RM_F_XU_V_M4, 0x2, false }, // 339 |
417 | | { PseudoVFCVT_RM_F_XU_V_M8_MASK, PseudoVFCVT_RM_F_XU_V_M8, 0x2, false }, // 340 |
418 | | { PseudoVFCVT_RM_F_XU_V_MF2_MASK, PseudoVFCVT_RM_F_XU_V_MF2, 0x2, false }, // 341 |
419 | | { PseudoVFCVT_RM_F_XU_V_MF4_MASK, PseudoVFCVT_RM_F_XU_V_MF4, 0x2, false }, // 342 |
420 | | { PseudoVFCVT_RM_F_X_V_M1_MASK, PseudoVFCVT_RM_F_X_V_M1, 0x2, false }, // 343 |
421 | | { PseudoVFCVT_RM_F_X_V_M2_MASK, PseudoVFCVT_RM_F_X_V_M2, 0x2, false }, // 344 |
422 | | { PseudoVFCVT_RM_F_X_V_M4_MASK, PseudoVFCVT_RM_F_X_V_M4, 0x2, false }, // 345 |
423 | | { PseudoVFCVT_RM_F_X_V_M8_MASK, PseudoVFCVT_RM_F_X_V_M8, 0x2, false }, // 346 |
424 | | { PseudoVFCVT_RM_F_X_V_MF2_MASK, PseudoVFCVT_RM_F_X_V_MF2, 0x2, false }, // 347 |
425 | | { PseudoVFCVT_RM_F_X_V_MF4_MASK, PseudoVFCVT_RM_F_X_V_MF4, 0x2, false }, // 348 |
426 | | { PseudoVFCVT_RM_XU_F_V_M1_MASK, PseudoVFCVT_RM_XU_F_V_M1, 0x2, false }, // 349 |
427 | | { PseudoVFCVT_RM_XU_F_V_M2_MASK, PseudoVFCVT_RM_XU_F_V_M2, 0x2, false }, // 350 |
428 | | { PseudoVFCVT_RM_XU_F_V_M4_MASK, PseudoVFCVT_RM_XU_F_V_M4, 0x2, false }, // 351 |
429 | | { PseudoVFCVT_RM_XU_F_V_M8_MASK, PseudoVFCVT_RM_XU_F_V_M8, 0x2, false }, // 352 |
430 | | { PseudoVFCVT_RM_XU_F_V_MF2_MASK, PseudoVFCVT_RM_XU_F_V_MF2, 0x2, false }, // 353 |
431 | | { PseudoVFCVT_RM_XU_F_V_MF4_MASK, PseudoVFCVT_RM_XU_F_V_MF4, 0x2, false }, // 354 |
432 | | { PseudoVFCVT_RM_X_F_V_M1_MASK, PseudoVFCVT_RM_X_F_V_M1, 0x2, false }, // 355 |
433 | | { PseudoVFCVT_RM_X_F_V_M2_MASK, PseudoVFCVT_RM_X_F_V_M2, 0x2, false }, // 356 |
434 | | { PseudoVFCVT_RM_X_F_V_M4_MASK, PseudoVFCVT_RM_X_F_V_M4, 0x2, false }, // 357 |
435 | | { PseudoVFCVT_RM_X_F_V_M8_MASK, PseudoVFCVT_RM_X_F_V_M8, 0x2, false }, // 358 |
436 | | { PseudoVFCVT_RM_X_F_V_MF2_MASK, PseudoVFCVT_RM_X_F_V_MF2, 0x2, false }, // 359 |
437 | | { PseudoVFCVT_RM_X_F_V_MF4_MASK, PseudoVFCVT_RM_X_F_V_MF4, 0x2, false }, // 360 |
438 | | { PseudoVFCVT_RTZ_XU_F_V_M1_MASK, PseudoVFCVT_RTZ_XU_F_V_M1, 0x2, false }, // 361 |
439 | | { PseudoVFCVT_RTZ_XU_F_V_M2_MASK, PseudoVFCVT_RTZ_XU_F_V_M2, 0x2, false }, // 362 |
440 | | { PseudoVFCVT_RTZ_XU_F_V_M4_MASK, PseudoVFCVT_RTZ_XU_F_V_M4, 0x2, false }, // 363 |
441 | | { PseudoVFCVT_RTZ_XU_F_V_M8_MASK, PseudoVFCVT_RTZ_XU_F_V_M8, 0x2, false }, // 364 |
442 | | { PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, PseudoVFCVT_RTZ_XU_F_V_MF2, 0x2, false }, // 365 |
443 | | { PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, PseudoVFCVT_RTZ_XU_F_V_MF4, 0x2, false }, // 366 |
444 | | { PseudoVFCVT_RTZ_X_F_V_M1_MASK, PseudoVFCVT_RTZ_X_F_V_M1, 0x2, false }, // 367 |
445 | | { PseudoVFCVT_RTZ_X_F_V_M2_MASK, PseudoVFCVT_RTZ_X_F_V_M2, 0x2, false }, // 368 |
446 | | { PseudoVFCVT_RTZ_X_F_V_M4_MASK, PseudoVFCVT_RTZ_X_F_V_M4, 0x2, false }, // 369 |
447 | | { PseudoVFCVT_RTZ_X_F_V_M8_MASK, PseudoVFCVT_RTZ_X_F_V_M8, 0x2, false }, // 370 |
448 | | { PseudoVFCVT_RTZ_X_F_V_MF2_MASK, PseudoVFCVT_RTZ_X_F_V_MF2, 0x2, false }, // 371 |
449 | | { PseudoVFCVT_RTZ_X_F_V_MF4_MASK, PseudoVFCVT_RTZ_X_F_V_MF4, 0x2, false }, // 372 |
450 | | { PseudoVFCVT_XU_F_V_M1_MASK, PseudoVFCVT_XU_F_V_M1, 0x2, false }, // 373 |
451 | | { PseudoVFCVT_XU_F_V_M2_MASK, PseudoVFCVT_XU_F_V_M2, 0x2, false }, // 374 |
452 | | { PseudoVFCVT_XU_F_V_M4_MASK, PseudoVFCVT_XU_F_V_M4, 0x2, false }, // 375 |
453 | | { PseudoVFCVT_XU_F_V_M8_MASK, PseudoVFCVT_XU_F_V_M8, 0x2, false }, // 376 |
454 | | { PseudoVFCVT_XU_F_V_MF2_MASK, PseudoVFCVT_XU_F_V_MF2, 0x2, false }, // 377 |
455 | | { PseudoVFCVT_XU_F_V_MF4_MASK, PseudoVFCVT_XU_F_V_MF4, 0x2, false }, // 378 |
456 | | { PseudoVFCVT_X_F_V_M1_MASK, PseudoVFCVT_X_F_V_M1, 0x2, false }, // 379 |
457 | | { PseudoVFCVT_X_F_V_M2_MASK, PseudoVFCVT_X_F_V_M2, 0x2, false }, // 380 |
458 | | { PseudoVFCVT_X_F_V_M4_MASK, PseudoVFCVT_X_F_V_M4, 0x2, false }, // 381 |
459 | | { PseudoVFCVT_X_F_V_M8_MASK, PseudoVFCVT_X_F_V_M8, 0x2, false }, // 382 |
460 | | { PseudoVFCVT_X_F_V_MF2_MASK, PseudoVFCVT_X_F_V_MF2, 0x2, false }, // 383 |
461 | | { PseudoVFCVT_X_F_V_MF4_MASK, PseudoVFCVT_X_F_V_MF4, 0x2, false }, // 384 |
462 | | { PseudoVFDIV_VFPR16_M1_E16_MASK, PseudoVFDIV_VFPR16_M1_E16, 0x3, false }, // 385 |
463 | | { PseudoVFDIV_VFPR16_M2_E16_MASK, PseudoVFDIV_VFPR16_M2_E16, 0x3, false }, // 386 |
464 | | { PseudoVFDIV_VFPR16_M4_E16_MASK, PseudoVFDIV_VFPR16_M4_E16, 0x3, false }, // 387 |
465 | | { PseudoVFDIV_VFPR16_M8_E16_MASK, PseudoVFDIV_VFPR16_M8_E16, 0x3, false }, // 388 |
466 | | { PseudoVFDIV_VFPR16_MF2_E16_MASK, PseudoVFDIV_VFPR16_MF2_E16, 0x3, false }, // 389 |
467 | | { PseudoVFDIV_VFPR16_MF4_E16_MASK, PseudoVFDIV_VFPR16_MF4_E16, 0x3, false }, // 390 |
468 | | { PseudoVFDIV_VFPR32_M1_E32_MASK, PseudoVFDIV_VFPR32_M1_E32, 0x3, false }, // 391 |
469 | | { PseudoVFDIV_VFPR32_M2_E32_MASK, PseudoVFDIV_VFPR32_M2_E32, 0x3, false }, // 392 |
470 | | { PseudoVFDIV_VFPR32_M4_E32_MASK, PseudoVFDIV_VFPR32_M4_E32, 0x3, false }, // 393 |
471 | | { PseudoVFDIV_VFPR32_M8_E32_MASK, PseudoVFDIV_VFPR32_M8_E32, 0x3, false }, // 394 |
472 | | { PseudoVFDIV_VFPR32_MF2_E32_MASK, PseudoVFDIV_VFPR32_MF2_E32, 0x3, false }, // 395 |
473 | | { PseudoVFDIV_VFPR64_M1_E64_MASK, PseudoVFDIV_VFPR64_M1_E64, 0x3, false }, // 396 |
474 | | { PseudoVFDIV_VFPR64_M2_E64_MASK, PseudoVFDIV_VFPR64_M2_E64, 0x3, false }, // 397 |
475 | | { PseudoVFDIV_VFPR64_M4_E64_MASK, PseudoVFDIV_VFPR64_M4_E64, 0x3, false }, // 398 |
476 | | { PseudoVFDIV_VFPR64_M8_E64_MASK, PseudoVFDIV_VFPR64_M8_E64, 0x3, false }, // 399 |
477 | | { PseudoVFDIV_VV_M1_E16_MASK, PseudoVFDIV_VV_M1_E16, 0x3, false }, // 400 |
478 | | { PseudoVFDIV_VV_M1_E32_MASK, PseudoVFDIV_VV_M1_E32, 0x3, false }, // 401 |
479 | | { PseudoVFDIV_VV_M1_E64_MASK, PseudoVFDIV_VV_M1_E64, 0x3, false }, // 402 |
480 | | { PseudoVFDIV_VV_M2_E16_MASK, PseudoVFDIV_VV_M2_E16, 0x3, false }, // 403 |
481 | | { PseudoVFDIV_VV_M2_E32_MASK, PseudoVFDIV_VV_M2_E32, 0x3, false }, // 404 |
482 | | { PseudoVFDIV_VV_M2_E64_MASK, PseudoVFDIV_VV_M2_E64, 0x3, false }, // 405 |
483 | | { PseudoVFDIV_VV_M4_E16_MASK, PseudoVFDIV_VV_M4_E16, 0x3, false }, // 406 |
484 | | { PseudoVFDIV_VV_M4_E32_MASK, PseudoVFDIV_VV_M4_E32, 0x3, false }, // 407 |
485 | | { PseudoVFDIV_VV_M4_E64_MASK, PseudoVFDIV_VV_M4_E64, 0x3, false }, // 408 |
486 | | { PseudoVFDIV_VV_M8_E16_MASK, PseudoVFDIV_VV_M8_E16, 0x3, false }, // 409 |
487 | | { PseudoVFDIV_VV_M8_E32_MASK, PseudoVFDIV_VV_M8_E32, 0x3, false }, // 410 |
488 | | { PseudoVFDIV_VV_M8_E64_MASK, PseudoVFDIV_VV_M8_E64, 0x3, false }, // 411 |
489 | | { PseudoVFDIV_VV_MF2_E16_MASK, PseudoVFDIV_VV_MF2_E16, 0x3, false }, // 412 |
490 | | { PseudoVFDIV_VV_MF2_E32_MASK, PseudoVFDIV_VV_MF2_E32, 0x3, false }, // 413 |
491 | | { PseudoVFDIV_VV_MF4_E16_MASK, PseudoVFDIV_VV_MF4_E16, 0x3, false }, // 414 |
492 | | { PseudoVFMACC_VFPR16_M1_MASK, PseudoVFMACC_VFPR16_M1, 0x3, false }, // 415 |
493 | | { PseudoVFMACC_VFPR16_M2_MASK, PseudoVFMACC_VFPR16_M2, 0x3, false }, // 416 |
494 | | { PseudoVFMACC_VFPR16_M4_MASK, PseudoVFMACC_VFPR16_M4, 0x3, false }, // 417 |
495 | | { PseudoVFMACC_VFPR16_M8_MASK, PseudoVFMACC_VFPR16_M8, 0x3, false }, // 418 |
496 | | { PseudoVFMACC_VFPR16_MF2_MASK, PseudoVFMACC_VFPR16_MF2, 0x3, false }, // 419 |
497 | | { PseudoVFMACC_VFPR16_MF4_MASK, PseudoVFMACC_VFPR16_MF4, 0x3, false }, // 420 |
498 | | { PseudoVFMACC_VFPR32_M1_MASK, PseudoVFMACC_VFPR32_M1, 0x3, false }, // 421 |
499 | | { PseudoVFMACC_VFPR32_M2_MASK, PseudoVFMACC_VFPR32_M2, 0x3, false }, // 422 |
500 | | { PseudoVFMACC_VFPR32_M4_MASK, PseudoVFMACC_VFPR32_M4, 0x3, false }, // 423 |
501 | | { PseudoVFMACC_VFPR32_M8_MASK, PseudoVFMACC_VFPR32_M8, 0x3, false }, // 424 |
502 | | { PseudoVFMACC_VFPR32_MF2_MASK, PseudoVFMACC_VFPR32_MF2, 0x3, false }, // 425 |
503 | | { PseudoVFMACC_VFPR64_M1_MASK, PseudoVFMACC_VFPR64_M1, 0x3, false }, // 426 |
504 | | { PseudoVFMACC_VFPR64_M2_MASK, PseudoVFMACC_VFPR64_M2, 0x3, false }, // 427 |
505 | | { PseudoVFMACC_VFPR64_M4_MASK, PseudoVFMACC_VFPR64_M4, 0x3, false }, // 428 |
506 | | { PseudoVFMACC_VFPR64_M8_MASK, PseudoVFMACC_VFPR64_M8, 0x3, false }, // 429 |
507 | | { PseudoVFMACC_VV_M1_MASK, PseudoVFMACC_VV_M1, 0x3, false }, // 430 |
508 | | { PseudoVFMACC_VV_M2_MASK, PseudoVFMACC_VV_M2, 0x3, false }, // 431 |
509 | | { PseudoVFMACC_VV_M4_MASK, PseudoVFMACC_VV_M4, 0x3, false }, // 432 |
510 | | { PseudoVFMACC_VV_M8_MASK, PseudoVFMACC_VV_M8, 0x3, false }, // 433 |
511 | | { PseudoVFMACC_VV_MF2_MASK, PseudoVFMACC_VV_MF2, 0x3, false }, // 434 |
512 | | { PseudoVFMACC_VV_MF4_MASK, PseudoVFMACC_VV_MF4, 0x3, false }, // 435 |
513 | | { PseudoVFMADD_VFPR16_M1_MASK, PseudoVFMADD_VFPR16_M1, 0x3, false }, // 436 |
514 | | { PseudoVFMADD_VFPR16_M2_MASK, PseudoVFMADD_VFPR16_M2, 0x3, false }, // 437 |
515 | | { PseudoVFMADD_VFPR16_M4_MASK, PseudoVFMADD_VFPR16_M4, 0x3, false }, // 438 |
516 | | { PseudoVFMADD_VFPR16_M8_MASK, PseudoVFMADD_VFPR16_M8, 0x3, false }, // 439 |
517 | | { PseudoVFMADD_VFPR16_MF2_MASK, PseudoVFMADD_VFPR16_MF2, 0x3, false }, // 440 |
518 | | { PseudoVFMADD_VFPR16_MF4_MASK, PseudoVFMADD_VFPR16_MF4, 0x3, false }, // 441 |
519 | | { PseudoVFMADD_VFPR32_M1_MASK, PseudoVFMADD_VFPR32_M1, 0x3, false }, // 442 |
520 | | { PseudoVFMADD_VFPR32_M2_MASK, PseudoVFMADD_VFPR32_M2, 0x3, false }, // 443 |
521 | | { PseudoVFMADD_VFPR32_M4_MASK, PseudoVFMADD_VFPR32_M4, 0x3, false }, // 444 |
522 | | { PseudoVFMADD_VFPR32_M8_MASK, PseudoVFMADD_VFPR32_M8, 0x3, false }, // 445 |
523 | | { PseudoVFMADD_VFPR32_MF2_MASK, PseudoVFMADD_VFPR32_MF2, 0x3, false }, // 446 |
524 | | { PseudoVFMADD_VFPR64_M1_MASK, PseudoVFMADD_VFPR64_M1, 0x3, false }, // 447 |
525 | | { PseudoVFMADD_VFPR64_M2_MASK, PseudoVFMADD_VFPR64_M2, 0x3, false }, // 448 |
526 | | { PseudoVFMADD_VFPR64_M4_MASK, PseudoVFMADD_VFPR64_M4, 0x3, false }, // 449 |
527 | | { PseudoVFMADD_VFPR64_M8_MASK, PseudoVFMADD_VFPR64_M8, 0x3, false }, // 450 |
528 | | { PseudoVFMADD_VV_M1_MASK, PseudoVFMADD_VV_M1, 0x3, false }, // 451 |
529 | | { PseudoVFMADD_VV_M2_MASK, PseudoVFMADD_VV_M2, 0x3, false }, // 452 |
530 | | { PseudoVFMADD_VV_M4_MASK, PseudoVFMADD_VV_M4, 0x3, false }, // 453 |
531 | | { PseudoVFMADD_VV_M8_MASK, PseudoVFMADD_VV_M8, 0x3, false }, // 454 |
532 | | { PseudoVFMADD_VV_MF2_MASK, PseudoVFMADD_VV_MF2, 0x3, false }, // 455 |
533 | | { PseudoVFMADD_VV_MF4_MASK, PseudoVFMADD_VV_MF4, 0x3, false }, // 456 |
534 | | { PseudoVFMAX_VFPR16_M1_MASK, PseudoVFMAX_VFPR16_M1, 0x3, false }, // 457 |
535 | | { PseudoVFMAX_VFPR16_M2_MASK, PseudoVFMAX_VFPR16_M2, 0x3, false }, // 458 |
536 | | { PseudoVFMAX_VFPR16_M4_MASK, PseudoVFMAX_VFPR16_M4, 0x3, false }, // 459 |
537 | | { PseudoVFMAX_VFPR16_M8_MASK, PseudoVFMAX_VFPR16_M8, 0x3, false }, // 460 |
538 | | { PseudoVFMAX_VFPR16_MF2_MASK, PseudoVFMAX_VFPR16_MF2, 0x3, false }, // 461 |
539 | | { PseudoVFMAX_VFPR16_MF4_MASK, PseudoVFMAX_VFPR16_MF4, 0x3, false }, // 462 |
540 | | { PseudoVFMAX_VFPR32_M1_MASK, PseudoVFMAX_VFPR32_M1, 0x3, false }, // 463 |
541 | | { PseudoVFMAX_VFPR32_M2_MASK, PseudoVFMAX_VFPR32_M2, 0x3, false }, // 464 |
542 | | { PseudoVFMAX_VFPR32_M4_MASK, PseudoVFMAX_VFPR32_M4, 0x3, false }, // 465 |
543 | | { PseudoVFMAX_VFPR32_M8_MASK, PseudoVFMAX_VFPR32_M8, 0x3, false }, // 466 |
544 | | { PseudoVFMAX_VFPR32_MF2_MASK, PseudoVFMAX_VFPR32_MF2, 0x3, false }, // 467 |
545 | | { PseudoVFMAX_VFPR64_M1_MASK, PseudoVFMAX_VFPR64_M1, 0x3, false }, // 468 |
546 | | { PseudoVFMAX_VFPR64_M2_MASK, PseudoVFMAX_VFPR64_M2, 0x3, false }, // 469 |
547 | | { PseudoVFMAX_VFPR64_M4_MASK, PseudoVFMAX_VFPR64_M4, 0x3, false }, // 470 |
548 | | { PseudoVFMAX_VFPR64_M8_MASK, PseudoVFMAX_VFPR64_M8, 0x3, false }, // 471 |
549 | | { PseudoVFMAX_VV_M1_MASK, PseudoVFMAX_VV_M1, 0x3, false }, // 472 |
550 | | { PseudoVFMAX_VV_M2_MASK, PseudoVFMAX_VV_M2, 0x3, false }, // 473 |
551 | | { PseudoVFMAX_VV_M4_MASK, PseudoVFMAX_VV_M4, 0x3, false }, // 474 |
552 | | { PseudoVFMAX_VV_M8_MASK, PseudoVFMAX_VV_M8, 0x3, false }, // 475 |
553 | | { PseudoVFMAX_VV_MF2_MASK, PseudoVFMAX_VV_MF2, 0x3, false }, // 476 |
554 | | { PseudoVFMAX_VV_MF4_MASK, PseudoVFMAX_VV_MF4, 0x3, false }, // 477 |
555 | | { PseudoVFMIN_VFPR16_M1_MASK, PseudoVFMIN_VFPR16_M1, 0x3, false }, // 478 |
556 | | { PseudoVFMIN_VFPR16_M2_MASK, PseudoVFMIN_VFPR16_M2, 0x3, false }, // 479 |
557 | | { PseudoVFMIN_VFPR16_M4_MASK, PseudoVFMIN_VFPR16_M4, 0x3, false }, // 480 |
558 | | { PseudoVFMIN_VFPR16_M8_MASK, PseudoVFMIN_VFPR16_M8, 0x3, false }, // 481 |
559 | | { PseudoVFMIN_VFPR16_MF2_MASK, PseudoVFMIN_VFPR16_MF2, 0x3, false }, // 482 |
560 | | { PseudoVFMIN_VFPR16_MF4_MASK, PseudoVFMIN_VFPR16_MF4, 0x3, false }, // 483 |
561 | | { PseudoVFMIN_VFPR32_M1_MASK, PseudoVFMIN_VFPR32_M1, 0x3, false }, // 484 |
562 | | { PseudoVFMIN_VFPR32_M2_MASK, PseudoVFMIN_VFPR32_M2, 0x3, false }, // 485 |
563 | | { PseudoVFMIN_VFPR32_M4_MASK, PseudoVFMIN_VFPR32_M4, 0x3, false }, // 486 |
564 | | { PseudoVFMIN_VFPR32_M8_MASK, PseudoVFMIN_VFPR32_M8, 0x3, false }, // 487 |
565 | | { PseudoVFMIN_VFPR32_MF2_MASK, PseudoVFMIN_VFPR32_MF2, 0x3, false }, // 488 |
566 | | { PseudoVFMIN_VFPR64_M1_MASK, PseudoVFMIN_VFPR64_M1, 0x3, false }, // 489 |
567 | | { PseudoVFMIN_VFPR64_M2_MASK, PseudoVFMIN_VFPR64_M2, 0x3, false }, // 490 |
568 | | { PseudoVFMIN_VFPR64_M4_MASK, PseudoVFMIN_VFPR64_M4, 0x3, false }, // 491 |
569 | | { PseudoVFMIN_VFPR64_M8_MASK, PseudoVFMIN_VFPR64_M8, 0x3, false }, // 492 |
570 | | { PseudoVFMIN_VV_M1_MASK, PseudoVFMIN_VV_M1, 0x3, false }, // 493 |
571 | | { PseudoVFMIN_VV_M2_MASK, PseudoVFMIN_VV_M2, 0x3, false }, // 494 |
572 | | { PseudoVFMIN_VV_M4_MASK, PseudoVFMIN_VV_M4, 0x3, false }, // 495 |
573 | | { PseudoVFMIN_VV_M8_MASK, PseudoVFMIN_VV_M8, 0x3, false }, // 496 |
574 | | { PseudoVFMIN_VV_MF2_MASK, PseudoVFMIN_VV_MF2, 0x3, false }, // 497 |
575 | | { PseudoVFMIN_VV_MF4_MASK, PseudoVFMIN_VV_MF4, 0x3, false }, // 498 |
576 | | { PseudoVFMSAC_VFPR16_M1_MASK, PseudoVFMSAC_VFPR16_M1, 0x3, false }, // 499 |
577 | | { PseudoVFMSAC_VFPR16_M2_MASK, PseudoVFMSAC_VFPR16_M2, 0x3, false }, // 500 |
578 | | { PseudoVFMSAC_VFPR16_M4_MASK, PseudoVFMSAC_VFPR16_M4, 0x3, false }, // 501 |
579 | | { PseudoVFMSAC_VFPR16_M8_MASK, PseudoVFMSAC_VFPR16_M8, 0x3, false }, // 502 |
580 | | { PseudoVFMSAC_VFPR16_MF2_MASK, PseudoVFMSAC_VFPR16_MF2, 0x3, false }, // 503 |
581 | | { PseudoVFMSAC_VFPR16_MF4_MASK, PseudoVFMSAC_VFPR16_MF4, 0x3, false }, // 504 |
582 | | { PseudoVFMSAC_VFPR32_M1_MASK, PseudoVFMSAC_VFPR32_M1, 0x3, false }, // 505 |
583 | | { PseudoVFMSAC_VFPR32_M2_MASK, PseudoVFMSAC_VFPR32_M2, 0x3, false }, // 506 |
584 | | { PseudoVFMSAC_VFPR32_M4_MASK, PseudoVFMSAC_VFPR32_M4, 0x3, false }, // 507 |
585 | | { PseudoVFMSAC_VFPR32_M8_MASK, PseudoVFMSAC_VFPR32_M8, 0x3, false }, // 508 |
586 | | { PseudoVFMSAC_VFPR32_MF2_MASK, PseudoVFMSAC_VFPR32_MF2, 0x3, false }, // 509 |
587 | | { PseudoVFMSAC_VFPR64_M1_MASK, PseudoVFMSAC_VFPR64_M1, 0x3, false }, // 510 |
588 | | { PseudoVFMSAC_VFPR64_M2_MASK, PseudoVFMSAC_VFPR64_M2, 0x3, false }, // 511 |
589 | | { PseudoVFMSAC_VFPR64_M4_MASK, PseudoVFMSAC_VFPR64_M4, 0x3, false }, // 512 |
590 | | { PseudoVFMSAC_VFPR64_M8_MASK, PseudoVFMSAC_VFPR64_M8, 0x3, false }, // 513 |
591 | | { PseudoVFMSAC_VV_M1_MASK, PseudoVFMSAC_VV_M1, 0x3, false }, // 514 |
592 | | { PseudoVFMSAC_VV_M2_MASK, PseudoVFMSAC_VV_M2, 0x3, false }, // 515 |
593 | | { PseudoVFMSAC_VV_M4_MASK, PseudoVFMSAC_VV_M4, 0x3, false }, // 516 |
594 | | { PseudoVFMSAC_VV_M8_MASK, PseudoVFMSAC_VV_M8, 0x3, false }, // 517 |
595 | | { PseudoVFMSAC_VV_MF2_MASK, PseudoVFMSAC_VV_MF2, 0x3, false }, // 518 |
596 | | { PseudoVFMSAC_VV_MF4_MASK, PseudoVFMSAC_VV_MF4, 0x3, false }, // 519 |
597 | | { PseudoVFMSUB_VFPR16_M1_MASK, PseudoVFMSUB_VFPR16_M1, 0x3, false }, // 520 |
598 | | { PseudoVFMSUB_VFPR16_M2_MASK, PseudoVFMSUB_VFPR16_M2, 0x3, false }, // 521 |
599 | | { PseudoVFMSUB_VFPR16_M4_MASK, PseudoVFMSUB_VFPR16_M4, 0x3, false }, // 522 |
600 | | { PseudoVFMSUB_VFPR16_M8_MASK, PseudoVFMSUB_VFPR16_M8, 0x3, false }, // 523 |
601 | | { PseudoVFMSUB_VFPR16_MF2_MASK, PseudoVFMSUB_VFPR16_MF2, 0x3, false }, // 524 |
602 | | { PseudoVFMSUB_VFPR16_MF4_MASK, PseudoVFMSUB_VFPR16_MF4, 0x3, false }, // 525 |
603 | | { PseudoVFMSUB_VFPR32_M1_MASK, PseudoVFMSUB_VFPR32_M1, 0x3, false }, // 526 |
604 | | { PseudoVFMSUB_VFPR32_M2_MASK, PseudoVFMSUB_VFPR32_M2, 0x3, false }, // 527 |
605 | | { PseudoVFMSUB_VFPR32_M4_MASK, PseudoVFMSUB_VFPR32_M4, 0x3, false }, // 528 |
606 | | { PseudoVFMSUB_VFPR32_M8_MASK, PseudoVFMSUB_VFPR32_M8, 0x3, false }, // 529 |
607 | | { PseudoVFMSUB_VFPR32_MF2_MASK, PseudoVFMSUB_VFPR32_MF2, 0x3, false }, // 530 |
608 | | { PseudoVFMSUB_VFPR64_M1_MASK, PseudoVFMSUB_VFPR64_M1, 0x3, false }, // 531 |
609 | | { PseudoVFMSUB_VFPR64_M2_MASK, PseudoVFMSUB_VFPR64_M2, 0x3, false }, // 532 |
610 | | { PseudoVFMSUB_VFPR64_M4_MASK, PseudoVFMSUB_VFPR64_M4, 0x3, false }, // 533 |
611 | | { PseudoVFMSUB_VFPR64_M8_MASK, PseudoVFMSUB_VFPR64_M8, 0x3, false }, // 534 |
612 | | { PseudoVFMSUB_VV_M1_MASK, PseudoVFMSUB_VV_M1, 0x3, false }, // 535 |
613 | | { PseudoVFMSUB_VV_M2_MASK, PseudoVFMSUB_VV_M2, 0x3, false }, // 536 |
614 | | { PseudoVFMSUB_VV_M4_MASK, PseudoVFMSUB_VV_M4, 0x3, false }, // 537 |
615 | | { PseudoVFMSUB_VV_M8_MASK, PseudoVFMSUB_VV_M8, 0x3, false }, // 538 |
616 | | { PseudoVFMSUB_VV_MF2_MASK, PseudoVFMSUB_VV_MF2, 0x3, false }, // 539 |
617 | | { PseudoVFMSUB_VV_MF4_MASK, PseudoVFMSUB_VV_MF4, 0x3, false }, // 540 |
618 | | { PseudoVFMUL_VFPR16_M1_MASK, PseudoVFMUL_VFPR16_M1, 0x3, false }, // 541 |
619 | | { PseudoVFMUL_VFPR16_M2_MASK, PseudoVFMUL_VFPR16_M2, 0x3, false }, // 542 |
620 | | { PseudoVFMUL_VFPR16_M4_MASK, PseudoVFMUL_VFPR16_M4, 0x3, false }, // 543 |
621 | | { PseudoVFMUL_VFPR16_M8_MASK, PseudoVFMUL_VFPR16_M8, 0x3, false }, // 544 |
622 | | { PseudoVFMUL_VFPR16_MF2_MASK, PseudoVFMUL_VFPR16_MF2, 0x3, false }, // 545 |
623 | | { PseudoVFMUL_VFPR16_MF4_MASK, PseudoVFMUL_VFPR16_MF4, 0x3, false }, // 546 |
624 | | { PseudoVFMUL_VFPR32_M1_MASK, PseudoVFMUL_VFPR32_M1, 0x3, false }, // 547 |
625 | | { PseudoVFMUL_VFPR32_M2_MASK, PseudoVFMUL_VFPR32_M2, 0x3, false }, // 548 |
626 | | { PseudoVFMUL_VFPR32_M4_MASK, PseudoVFMUL_VFPR32_M4, 0x3, false }, // 549 |
627 | | { PseudoVFMUL_VFPR32_M8_MASK, PseudoVFMUL_VFPR32_M8, 0x3, false }, // 550 |
628 | | { PseudoVFMUL_VFPR32_MF2_MASK, PseudoVFMUL_VFPR32_MF2, 0x3, false }, // 551 |
629 | | { PseudoVFMUL_VFPR64_M1_MASK, PseudoVFMUL_VFPR64_M1, 0x3, false }, // 552 |
630 | | { PseudoVFMUL_VFPR64_M2_MASK, PseudoVFMUL_VFPR64_M2, 0x3, false }, // 553 |
631 | | { PseudoVFMUL_VFPR64_M4_MASK, PseudoVFMUL_VFPR64_M4, 0x3, false }, // 554 |
632 | | { PseudoVFMUL_VFPR64_M8_MASK, PseudoVFMUL_VFPR64_M8, 0x3, false }, // 555 |
633 | | { PseudoVFMUL_VV_M1_MASK, PseudoVFMUL_VV_M1, 0x3, false }, // 556 |
634 | | { PseudoVFMUL_VV_M2_MASK, PseudoVFMUL_VV_M2, 0x3, false }, // 557 |
635 | | { PseudoVFMUL_VV_M4_MASK, PseudoVFMUL_VV_M4, 0x3, false }, // 558 |
636 | | { PseudoVFMUL_VV_M8_MASK, PseudoVFMUL_VV_M8, 0x3, false }, // 559 |
637 | | { PseudoVFMUL_VV_MF2_MASK, PseudoVFMUL_VV_MF2, 0x3, false }, // 560 |
638 | | { PseudoVFMUL_VV_MF4_MASK, PseudoVFMUL_VV_MF4, 0x3, false }, // 561 |
639 | | { PseudoVFNCVTBF16_F_F_W_M1_MASK, PseudoVFNCVTBF16_F_F_W_M1, 0x2, false }, // 562 |
640 | | { PseudoVFNCVTBF16_F_F_W_M2_MASK, PseudoVFNCVTBF16_F_F_W_M2, 0x2, false }, // 563 |
641 | | { PseudoVFNCVTBF16_F_F_W_M4_MASK, PseudoVFNCVTBF16_F_F_W_M4, 0x2, false }, // 564 |
642 | | { PseudoVFNCVTBF16_F_F_W_MF2_MASK, PseudoVFNCVTBF16_F_F_W_MF2, 0x2, false }, // 565 |
643 | | { PseudoVFNCVTBF16_F_F_W_MF4_MASK, PseudoVFNCVTBF16_F_F_W_MF4, 0x2, false }, // 566 |
644 | | { PseudoVFNCVT_F_F_W_M1_MASK, PseudoVFNCVT_F_F_W_M1, 0x2, false }, // 567 |
645 | | { PseudoVFNCVT_F_F_W_M2_MASK, PseudoVFNCVT_F_F_W_M2, 0x2, false }, // 568 |
646 | | { PseudoVFNCVT_F_F_W_M4_MASK, PseudoVFNCVT_F_F_W_M4, 0x2, false }, // 569 |
647 | | { PseudoVFNCVT_F_F_W_MF2_MASK, PseudoVFNCVT_F_F_W_MF2, 0x2, false }, // 570 |
648 | | { PseudoVFNCVT_F_F_W_MF4_MASK, PseudoVFNCVT_F_F_W_MF4, 0x2, false }, // 571 |
649 | | { PseudoVFNCVT_F_XU_W_M1_MASK, PseudoVFNCVT_F_XU_W_M1, 0x2, false }, // 572 |
650 | | { PseudoVFNCVT_F_XU_W_M2_MASK, PseudoVFNCVT_F_XU_W_M2, 0x2, false }, // 573 |
651 | | { PseudoVFNCVT_F_XU_W_M4_MASK, PseudoVFNCVT_F_XU_W_M4, 0x2, false }, // 574 |
652 | | { PseudoVFNCVT_F_XU_W_MF2_MASK, PseudoVFNCVT_F_XU_W_MF2, 0x2, false }, // 575 |
653 | | { PseudoVFNCVT_F_XU_W_MF4_MASK, PseudoVFNCVT_F_XU_W_MF4, 0x2, false }, // 576 |
654 | | { PseudoVFNCVT_F_X_W_M1_MASK, PseudoVFNCVT_F_X_W_M1, 0x2, false }, // 577 |
655 | | { PseudoVFNCVT_F_X_W_M2_MASK, PseudoVFNCVT_F_X_W_M2, 0x2, false }, // 578 |
656 | | { PseudoVFNCVT_F_X_W_M4_MASK, PseudoVFNCVT_F_X_W_M4, 0x2, false }, // 579 |
657 | | { PseudoVFNCVT_F_X_W_MF2_MASK, PseudoVFNCVT_F_X_W_MF2, 0x2, false }, // 580 |
658 | | { PseudoVFNCVT_F_X_W_MF4_MASK, PseudoVFNCVT_F_X_W_MF4, 0x2, false }, // 581 |
659 | | { PseudoVFNCVT_RM_F_XU_W_M1_MASK, PseudoVFNCVT_RM_F_XU_W_M1, 0x2, false }, // 582 |
660 | | { PseudoVFNCVT_RM_F_XU_W_M2_MASK, PseudoVFNCVT_RM_F_XU_W_M2, 0x2, false }, // 583 |
661 | | { PseudoVFNCVT_RM_F_XU_W_M4_MASK, PseudoVFNCVT_RM_F_XU_W_M4, 0x2, false }, // 584 |
662 | | { PseudoVFNCVT_RM_F_XU_W_MF2_MASK, PseudoVFNCVT_RM_F_XU_W_MF2, 0x2, false }, // 585 |
663 | | { PseudoVFNCVT_RM_F_XU_W_MF4_MASK, PseudoVFNCVT_RM_F_XU_W_MF4, 0x2, false }, // 586 |
664 | | { PseudoVFNCVT_RM_F_X_W_M1_MASK, PseudoVFNCVT_RM_F_X_W_M1, 0x2, false }, // 587 |
665 | | { PseudoVFNCVT_RM_F_X_W_M2_MASK, PseudoVFNCVT_RM_F_X_W_M2, 0x2, false }, // 588 |
666 | | { PseudoVFNCVT_RM_F_X_W_M4_MASK, PseudoVFNCVT_RM_F_X_W_M4, 0x2, false }, // 589 |
667 | | { PseudoVFNCVT_RM_F_X_W_MF2_MASK, PseudoVFNCVT_RM_F_X_W_MF2, 0x2, false }, // 590 |
668 | | { PseudoVFNCVT_RM_F_X_W_MF4_MASK, PseudoVFNCVT_RM_F_X_W_MF4, 0x2, false }, // 591 |
669 | | { PseudoVFNCVT_RM_XU_F_W_M1_MASK, PseudoVFNCVT_RM_XU_F_W_M1, 0x2, false }, // 592 |
670 | | { PseudoVFNCVT_RM_XU_F_W_M2_MASK, PseudoVFNCVT_RM_XU_F_W_M2, 0x2, false }, // 593 |
671 | | { PseudoVFNCVT_RM_XU_F_W_M4_MASK, PseudoVFNCVT_RM_XU_F_W_M4, 0x2, false }, // 594 |
672 | | { PseudoVFNCVT_RM_XU_F_W_MF2_MASK, PseudoVFNCVT_RM_XU_F_W_MF2, 0x2, false }, // 595 |
673 | | { PseudoVFNCVT_RM_XU_F_W_MF4_MASK, PseudoVFNCVT_RM_XU_F_W_MF4, 0x2, false }, // 596 |
674 | | { PseudoVFNCVT_RM_XU_F_W_MF8_MASK, PseudoVFNCVT_RM_XU_F_W_MF8, 0x2, false }, // 597 |
675 | | { PseudoVFNCVT_RM_X_F_W_M1_MASK, PseudoVFNCVT_RM_X_F_W_M1, 0x2, false }, // 598 |
676 | | { PseudoVFNCVT_RM_X_F_W_M2_MASK, PseudoVFNCVT_RM_X_F_W_M2, 0x2, false }, // 599 |
677 | | { PseudoVFNCVT_RM_X_F_W_M4_MASK, PseudoVFNCVT_RM_X_F_W_M4, 0x2, false }, // 600 |
678 | | { PseudoVFNCVT_RM_X_F_W_MF2_MASK, PseudoVFNCVT_RM_X_F_W_MF2, 0x2, false }, // 601 |
679 | | { PseudoVFNCVT_RM_X_F_W_MF4_MASK, PseudoVFNCVT_RM_X_F_W_MF4, 0x2, false }, // 602 |
680 | | { PseudoVFNCVT_RM_X_F_W_MF8_MASK, PseudoVFNCVT_RM_X_F_W_MF8, 0x2, false }, // 603 |
681 | | { PseudoVFNCVT_ROD_F_F_W_M1_MASK, PseudoVFNCVT_ROD_F_F_W_M1, 0x2, false }, // 604 |
682 | | { PseudoVFNCVT_ROD_F_F_W_M2_MASK, PseudoVFNCVT_ROD_F_F_W_M2, 0x2, false }, // 605 |
683 | | { PseudoVFNCVT_ROD_F_F_W_M4_MASK, PseudoVFNCVT_ROD_F_F_W_M4, 0x2, false }, // 606 |
684 | | { PseudoVFNCVT_ROD_F_F_W_MF2_MASK, PseudoVFNCVT_ROD_F_F_W_MF2, 0x2, false }, // 607 |
685 | | { PseudoVFNCVT_ROD_F_F_W_MF4_MASK, PseudoVFNCVT_ROD_F_F_W_MF4, 0x2, false }, // 608 |
686 | | { PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, PseudoVFNCVT_RTZ_XU_F_W_M1, 0x2, false }, // 609 |
687 | | { PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, PseudoVFNCVT_RTZ_XU_F_W_M2, 0x2, false }, // 610 |
688 | | { PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, PseudoVFNCVT_RTZ_XU_F_W_M4, 0x2, false }, // 611 |
689 | | { PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF2, 0x2, false }, // 612 |
690 | | { PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF4, 0x2, false }, // 613 |
691 | | { PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, PseudoVFNCVT_RTZ_XU_F_W_MF8, 0x2, false }, // 614 |
692 | | { PseudoVFNCVT_RTZ_X_F_W_M1_MASK, PseudoVFNCVT_RTZ_X_F_W_M1, 0x2, false }, // 615 |
693 | | { PseudoVFNCVT_RTZ_X_F_W_M2_MASK, PseudoVFNCVT_RTZ_X_F_W_M2, 0x2, false }, // 616 |
694 | | { PseudoVFNCVT_RTZ_X_F_W_M4_MASK, PseudoVFNCVT_RTZ_X_F_W_M4, 0x2, false }, // 617 |
695 | | { PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, PseudoVFNCVT_RTZ_X_F_W_MF2, 0x2, false }, // 618 |
696 | | { PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, PseudoVFNCVT_RTZ_X_F_W_MF4, 0x2, false }, // 619 |
697 | | { PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, PseudoVFNCVT_RTZ_X_F_W_MF8, 0x2, false }, // 620 |
698 | | { PseudoVFNCVT_XU_F_W_M1_MASK, PseudoVFNCVT_XU_F_W_M1, 0x2, false }, // 621 |
699 | | { PseudoVFNCVT_XU_F_W_M2_MASK, PseudoVFNCVT_XU_F_W_M2, 0x2, false }, // 622 |
700 | | { PseudoVFNCVT_XU_F_W_M4_MASK, PseudoVFNCVT_XU_F_W_M4, 0x2, false }, // 623 |
701 | | { PseudoVFNCVT_XU_F_W_MF2_MASK, PseudoVFNCVT_XU_F_W_MF2, 0x2, false }, // 624 |
702 | | { PseudoVFNCVT_XU_F_W_MF4_MASK, PseudoVFNCVT_XU_F_W_MF4, 0x2, false }, // 625 |
703 | | { PseudoVFNCVT_XU_F_W_MF8_MASK, PseudoVFNCVT_XU_F_W_MF8, 0x2, false }, // 626 |
704 | | { PseudoVFNCVT_X_F_W_M1_MASK, PseudoVFNCVT_X_F_W_M1, 0x2, false }, // 627 |
705 | | { PseudoVFNCVT_X_F_W_M2_MASK, PseudoVFNCVT_X_F_W_M2, 0x2, false }, // 628 |
706 | | { PseudoVFNCVT_X_F_W_M4_MASK, PseudoVFNCVT_X_F_W_M4, 0x2, false }, // 629 |
707 | | { PseudoVFNCVT_X_F_W_MF2_MASK, PseudoVFNCVT_X_F_W_MF2, 0x2, false }, // 630 |
708 | | { PseudoVFNCVT_X_F_W_MF4_MASK, PseudoVFNCVT_X_F_W_MF4, 0x2, false }, // 631 |
709 | | { PseudoVFNCVT_X_F_W_MF8_MASK, PseudoVFNCVT_X_F_W_MF8, 0x2, false }, // 632 |
710 | | { PseudoVFNMACC_VFPR16_M1_MASK, PseudoVFNMACC_VFPR16_M1, 0x3, false }, // 633 |
711 | | { PseudoVFNMACC_VFPR16_M2_MASK, PseudoVFNMACC_VFPR16_M2, 0x3, false }, // 634 |
712 | | { PseudoVFNMACC_VFPR16_M4_MASK, PseudoVFNMACC_VFPR16_M4, 0x3, false }, // 635 |
713 | | { PseudoVFNMACC_VFPR16_M8_MASK, PseudoVFNMACC_VFPR16_M8, 0x3, false }, // 636 |
714 | | { PseudoVFNMACC_VFPR16_MF2_MASK, PseudoVFNMACC_VFPR16_MF2, 0x3, false }, // 637 |
715 | | { PseudoVFNMACC_VFPR16_MF4_MASK, PseudoVFNMACC_VFPR16_MF4, 0x3, false }, // 638 |
716 | | { PseudoVFNMACC_VFPR32_M1_MASK, PseudoVFNMACC_VFPR32_M1, 0x3, false }, // 639 |
717 | | { PseudoVFNMACC_VFPR32_M2_MASK, PseudoVFNMACC_VFPR32_M2, 0x3, false }, // 640 |
718 | | { PseudoVFNMACC_VFPR32_M4_MASK, PseudoVFNMACC_VFPR32_M4, 0x3, false }, // 641 |
719 | | { PseudoVFNMACC_VFPR32_M8_MASK, PseudoVFNMACC_VFPR32_M8, 0x3, false }, // 642 |
720 | | { PseudoVFNMACC_VFPR32_MF2_MASK, PseudoVFNMACC_VFPR32_MF2, 0x3, false }, // 643 |
721 | | { PseudoVFNMACC_VFPR64_M1_MASK, PseudoVFNMACC_VFPR64_M1, 0x3, false }, // 644 |
722 | | { PseudoVFNMACC_VFPR64_M2_MASK, PseudoVFNMACC_VFPR64_M2, 0x3, false }, // 645 |
723 | | { PseudoVFNMACC_VFPR64_M4_MASK, PseudoVFNMACC_VFPR64_M4, 0x3, false }, // 646 |
724 | | { PseudoVFNMACC_VFPR64_M8_MASK, PseudoVFNMACC_VFPR64_M8, 0x3, false }, // 647 |
725 | | { PseudoVFNMACC_VV_M1_MASK, PseudoVFNMACC_VV_M1, 0x3, false }, // 648 |
726 | | { PseudoVFNMACC_VV_M2_MASK, PseudoVFNMACC_VV_M2, 0x3, false }, // 649 |
727 | | { PseudoVFNMACC_VV_M4_MASK, PseudoVFNMACC_VV_M4, 0x3, false }, // 650 |
728 | | { PseudoVFNMACC_VV_M8_MASK, PseudoVFNMACC_VV_M8, 0x3, false }, // 651 |
729 | | { PseudoVFNMACC_VV_MF2_MASK, PseudoVFNMACC_VV_MF2, 0x3, false }, // 652 |
730 | | { PseudoVFNMACC_VV_MF4_MASK, PseudoVFNMACC_VV_MF4, 0x3, false }, // 653 |
731 | | { PseudoVFNMADD_VFPR16_M1_MASK, PseudoVFNMADD_VFPR16_M1, 0x3, false }, // 654 |
732 | | { PseudoVFNMADD_VFPR16_M2_MASK, PseudoVFNMADD_VFPR16_M2, 0x3, false }, // 655 |
733 | | { PseudoVFNMADD_VFPR16_M4_MASK, PseudoVFNMADD_VFPR16_M4, 0x3, false }, // 656 |
734 | | { PseudoVFNMADD_VFPR16_M8_MASK, PseudoVFNMADD_VFPR16_M8, 0x3, false }, // 657 |
735 | | { PseudoVFNMADD_VFPR16_MF2_MASK, PseudoVFNMADD_VFPR16_MF2, 0x3, false }, // 658 |
736 | | { PseudoVFNMADD_VFPR16_MF4_MASK, PseudoVFNMADD_VFPR16_MF4, 0x3, false }, // 659 |
737 | | { PseudoVFNMADD_VFPR32_M1_MASK, PseudoVFNMADD_VFPR32_M1, 0x3, false }, // 660 |
738 | | { PseudoVFNMADD_VFPR32_M2_MASK, PseudoVFNMADD_VFPR32_M2, 0x3, false }, // 661 |
739 | | { PseudoVFNMADD_VFPR32_M4_MASK, PseudoVFNMADD_VFPR32_M4, 0x3, false }, // 662 |
740 | | { PseudoVFNMADD_VFPR32_M8_MASK, PseudoVFNMADD_VFPR32_M8, 0x3, false }, // 663 |
741 | | { PseudoVFNMADD_VFPR32_MF2_MASK, PseudoVFNMADD_VFPR32_MF2, 0x3, false }, // 664 |
742 | | { PseudoVFNMADD_VFPR64_M1_MASK, PseudoVFNMADD_VFPR64_M1, 0x3, false }, // 665 |
743 | | { PseudoVFNMADD_VFPR64_M2_MASK, PseudoVFNMADD_VFPR64_M2, 0x3, false }, // 666 |
744 | | { PseudoVFNMADD_VFPR64_M4_MASK, PseudoVFNMADD_VFPR64_M4, 0x3, false }, // 667 |
745 | | { PseudoVFNMADD_VFPR64_M8_MASK, PseudoVFNMADD_VFPR64_M8, 0x3, false }, // 668 |
746 | | { PseudoVFNMADD_VV_M1_MASK, PseudoVFNMADD_VV_M1, 0x3, false }, // 669 |
747 | | { PseudoVFNMADD_VV_M2_MASK, PseudoVFNMADD_VV_M2, 0x3, false }, // 670 |
748 | | { PseudoVFNMADD_VV_M4_MASK, PseudoVFNMADD_VV_M4, 0x3, false }, // 671 |
749 | | { PseudoVFNMADD_VV_M8_MASK, PseudoVFNMADD_VV_M8, 0x3, false }, // 672 |
750 | | { PseudoVFNMADD_VV_MF2_MASK, PseudoVFNMADD_VV_MF2, 0x3, false }, // 673 |
751 | | { PseudoVFNMADD_VV_MF4_MASK, PseudoVFNMADD_VV_MF4, 0x3, false }, // 674 |
752 | | { PseudoVFNMSAC_VFPR16_M1_MASK, PseudoVFNMSAC_VFPR16_M1, 0x3, false }, // 675 |
753 | | { PseudoVFNMSAC_VFPR16_M2_MASK, PseudoVFNMSAC_VFPR16_M2, 0x3, false }, // 676 |
754 | | { PseudoVFNMSAC_VFPR16_M4_MASK, PseudoVFNMSAC_VFPR16_M4, 0x3, false }, // 677 |
755 | | { PseudoVFNMSAC_VFPR16_M8_MASK, PseudoVFNMSAC_VFPR16_M8, 0x3, false }, // 678 |
756 | | { PseudoVFNMSAC_VFPR16_MF2_MASK, PseudoVFNMSAC_VFPR16_MF2, 0x3, false }, // 679 |
757 | | { PseudoVFNMSAC_VFPR16_MF4_MASK, PseudoVFNMSAC_VFPR16_MF4, 0x3, false }, // 680 |
758 | | { PseudoVFNMSAC_VFPR32_M1_MASK, PseudoVFNMSAC_VFPR32_M1, 0x3, false }, // 681 |
759 | | { PseudoVFNMSAC_VFPR32_M2_MASK, PseudoVFNMSAC_VFPR32_M2, 0x3, false }, // 682 |
760 | | { PseudoVFNMSAC_VFPR32_M4_MASK, PseudoVFNMSAC_VFPR32_M4, 0x3, false }, // 683 |
761 | | { PseudoVFNMSAC_VFPR32_M8_MASK, PseudoVFNMSAC_VFPR32_M8, 0x3, false }, // 684 |
762 | | { PseudoVFNMSAC_VFPR32_MF2_MASK, PseudoVFNMSAC_VFPR32_MF2, 0x3, false }, // 685 |
763 | | { PseudoVFNMSAC_VFPR64_M1_MASK, PseudoVFNMSAC_VFPR64_M1, 0x3, false }, // 686 |
764 | | { PseudoVFNMSAC_VFPR64_M2_MASK, PseudoVFNMSAC_VFPR64_M2, 0x3, false }, // 687 |
765 | | { PseudoVFNMSAC_VFPR64_M4_MASK, PseudoVFNMSAC_VFPR64_M4, 0x3, false }, // 688 |
766 | | { PseudoVFNMSAC_VFPR64_M8_MASK, PseudoVFNMSAC_VFPR64_M8, 0x3, false }, // 689 |
767 | | { PseudoVFNMSAC_VV_M1_MASK, PseudoVFNMSAC_VV_M1, 0x3, false }, // 690 |
768 | | { PseudoVFNMSAC_VV_M2_MASK, PseudoVFNMSAC_VV_M2, 0x3, false }, // 691 |
769 | | { PseudoVFNMSAC_VV_M4_MASK, PseudoVFNMSAC_VV_M4, 0x3, false }, // 692 |
770 | | { PseudoVFNMSAC_VV_M8_MASK, PseudoVFNMSAC_VV_M8, 0x3, false }, // 693 |
771 | | { PseudoVFNMSAC_VV_MF2_MASK, PseudoVFNMSAC_VV_MF2, 0x3, false }, // 694 |
772 | | { PseudoVFNMSAC_VV_MF4_MASK, PseudoVFNMSAC_VV_MF4, 0x3, false }, // 695 |
773 | | { PseudoVFNMSUB_VFPR16_M1_MASK, PseudoVFNMSUB_VFPR16_M1, 0x3, false }, // 696 |
774 | | { PseudoVFNMSUB_VFPR16_M2_MASK, PseudoVFNMSUB_VFPR16_M2, 0x3, false }, // 697 |
775 | | { PseudoVFNMSUB_VFPR16_M4_MASK, PseudoVFNMSUB_VFPR16_M4, 0x3, false }, // 698 |
776 | | { PseudoVFNMSUB_VFPR16_M8_MASK, PseudoVFNMSUB_VFPR16_M8, 0x3, false }, // 699 |
777 | | { PseudoVFNMSUB_VFPR16_MF2_MASK, PseudoVFNMSUB_VFPR16_MF2, 0x3, false }, // 700 |
778 | | { PseudoVFNMSUB_VFPR16_MF4_MASK, PseudoVFNMSUB_VFPR16_MF4, 0x3, false }, // 701 |
779 | | { PseudoVFNMSUB_VFPR32_M1_MASK, PseudoVFNMSUB_VFPR32_M1, 0x3, false }, // 702 |
780 | | { PseudoVFNMSUB_VFPR32_M2_MASK, PseudoVFNMSUB_VFPR32_M2, 0x3, false }, // 703 |
781 | | { PseudoVFNMSUB_VFPR32_M4_MASK, PseudoVFNMSUB_VFPR32_M4, 0x3, false }, // 704 |
782 | | { PseudoVFNMSUB_VFPR32_M8_MASK, PseudoVFNMSUB_VFPR32_M8, 0x3, false }, // 705 |
783 | | { PseudoVFNMSUB_VFPR32_MF2_MASK, PseudoVFNMSUB_VFPR32_MF2, 0x3, false }, // 706 |
784 | | { PseudoVFNMSUB_VFPR64_M1_MASK, PseudoVFNMSUB_VFPR64_M1, 0x3, false }, // 707 |
785 | | { PseudoVFNMSUB_VFPR64_M2_MASK, PseudoVFNMSUB_VFPR64_M2, 0x3, false }, // 708 |
786 | | { PseudoVFNMSUB_VFPR64_M4_MASK, PseudoVFNMSUB_VFPR64_M4, 0x3, false }, // 709 |
787 | | { PseudoVFNMSUB_VFPR64_M8_MASK, PseudoVFNMSUB_VFPR64_M8, 0x3, false }, // 710 |
788 | | { PseudoVFNMSUB_VV_M1_MASK, PseudoVFNMSUB_VV_M1, 0x3, false }, // 711 |
789 | | { PseudoVFNMSUB_VV_M2_MASK, PseudoVFNMSUB_VV_M2, 0x3, false }, // 712 |
790 | | { PseudoVFNMSUB_VV_M4_MASK, PseudoVFNMSUB_VV_M4, 0x3, false }, // 713 |
791 | | { PseudoVFNMSUB_VV_M8_MASK, PseudoVFNMSUB_VV_M8, 0x3, false }, // 714 |
792 | | { PseudoVFNMSUB_VV_MF2_MASK, PseudoVFNMSUB_VV_MF2, 0x3, false }, // 715 |
793 | | { PseudoVFNMSUB_VV_MF4_MASK, PseudoVFNMSUB_VV_MF4, 0x3, false }, // 716 |
794 | | { PseudoVFNRCLIP_XU_F_QF_M1_MASK, PseudoVFNRCLIP_XU_F_QF_M1, 0x3, false }, // 717 |
795 | | { PseudoVFNRCLIP_XU_F_QF_M2_MASK, PseudoVFNRCLIP_XU_F_QF_M2, 0x3, false }, // 718 |
796 | | { PseudoVFNRCLIP_XU_F_QF_MF2_MASK, PseudoVFNRCLIP_XU_F_QF_MF2, 0x3, false }, // 719 |
797 | | { PseudoVFNRCLIP_XU_F_QF_MF4_MASK, PseudoVFNRCLIP_XU_F_QF_MF4, 0x3, false }, // 720 |
798 | | { PseudoVFNRCLIP_XU_F_QF_MF8_MASK, PseudoVFNRCLIP_XU_F_QF_MF8, 0x3, false }, // 721 |
799 | | { PseudoVFNRCLIP_X_F_QF_M1_MASK, PseudoVFNRCLIP_X_F_QF_M1, 0x3, false }, // 722 |
800 | | { PseudoVFNRCLIP_X_F_QF_M2_MASK, PseudoVFNRCLIP_X_F_QF_M2, 0x3, false }, // 723 |
801 | | { PseudoVFNRCLIP_X_F_QF_MF2_MASK, PseudoVFNRCLIP_X_F_QF_MF2, 0x3, false }, // 724 |
802 | | { PseudoVFNRCLIP_X_F_QF_MF4_MASK, PseudoVFNRCLIP_X_F_QF_MF4, 0x3, false }, // 725 |
803 | | { PseudoVFNRCLIP_X_F_QF_MF8_MASK, PseudoVFNRCLIP_X_F_QF_MF8, 0x3, false }, // 726 |
804 | | { PseudoVFRDIV_VFPR16_M1_E16_MASK, PseudoVFRDIV_VFPR16_M1_E16, 0x3, false }, // 727 |
805 | | { PseudoVFRDIV_VFPR16_M2_E16_MASK, PseudoVFRDIV_VFPR16_M2_E16, 0x3, false }, // 728 |
806 | | { PseudoVFRDIV_VFPR16_M4_E16_MASK, PseudoVFRDIV_VFPR16_M4_E16, 0x3, false }, // 729 |
807 | | { PseudoVFRDIV_VFPR16_M8_E16_MASK, PseudoVFRDIV_VFPR16_M8_E16, 0x3, false }, // 730 |
808 | | { PseudoVFRDIV_VFPR16_MF2_E16_MASK, PseudoVFRDIV_VFPR16_MF2_E16, 0x3, false }, // 731 |
809 | | { PseudoVFRDIV_VFPR16_MF4_E16_MASK, PseudoVFRDIV_VFPR16_MF4_E16, 0x3, false }, // 732 |
810 | | { PseudoVFRDIV_VFPR32_M1_E32_MASK, PseudoVFRDIV_VFPR32_M1_E32, 0x3, false }, // 733 |
811 | | { PseudoVFRDIV_VFPR32_M2_E32_MASK, PseudoVFRDIV_VFPR32_M2_E32, 0x3, false }, // 734 |
812 | | { PseudoVFRDIV_VFPR32_M4_E32_MASK, PseudoVFRDIV_VFPR32_M4_E32, 0x3, false }, // 735 |
813 | | { PseudoVFRDIV_VFPR32_M8_E32_MASK, PseudoVFRDIV_VFPR32_M8_E32, 0x3, false }, // 736 |
814 | | { PseudoVFRDIV_VFPR32_MF2_E32_MASK, PseudoVFRDIV_VFPR32_MF2_E32, 0x3, false }, // 737 |
815 | | { PseudoVFRDIV_VFPR64_M1_E64_MASK, PseudoVFRDIV_VFPR64_M1_E64, 0x3, false }, // 738 |
816 | | { PseudoVFRDIV_VFPR64_M2_E64_MASK, PseudoVFRDIV_VFPR64_M2_E64, 0x3, false }, // 739 |
817 | | { PseudoVFRDIV_VFPR64_M4_E64_MASK, PseudoVFRDIV_VFPR64_M4_E64, 0x3, false }, // 740 |
818 | | { PseudoVFRDIV_VFPR64_M8_E64_MASK, PseudoVFRDIV_VFPR64_M8_E64, 0x3, false }, // 741 |
819 | | { PseudoVFREC7_V_M1_MASK, PseudoVFREC7_V_M1, 0x2, false }, // 742 |
820 | | { PseudoVFREC7_V_M2_MASK, PseudoVFREC7_V_M2, 0x2, false }, // 743 |
821 | | { PseudoVFREC7_V_M4_MASK, PseudoVFREC7_V_M4, 0x2, false }, // 744 |
822 | | { PseudoVFREC7_V_M8_MASK, PseudoVFREC7_V_M8, 0x2, false }, // 745 |
823 | | { PseudoVFREC7_V_MF2_MASK, PseudoVFREC7_V_MF2, 0x2, false }, // 746 |
824 | | { PseudoVFREC7_V_MF4_MASK, PseudoVFREC7_V_MF4, 0x2, false }, // 747 |
825 | | { PseudoVFREDMAX_VS_M1_E16_MASK, PseudoVFREDMAX_VS_M1_E16, 0x3, true }, // 748 |
826 | | { PseudoVFREDMAX_VS_M1_E32_MASK, PseudoVFREDMAX_VS_M1_E32, 0x3, true }, // 749 |
827 | | { PseudoVFREDMAX_VS_M1_E64_MASK, PseudoVFREDMAX_VS_M1_E64, 0x3, true }, // 750 |
828 | | { PseudoVFREDMAX_VS_M2_E16_MASK, PseudoVFREDMAX_VS_M2_E16, 0x3, true }, // 751 |
829 | | { PseudoVFREDMAX_VS_M2_E32_MASK, PseudoVFREDMAX_VS_M2_E32, 0x3, true }, // 752 |
830 | | { PseudoVFREDMAX_VS_M2_E64_MASK, PseudoVFREDMAX_VS_M2_E64, 0x3, true }, // 753 |
831 | | { PseudoVFREDMAX_VS_M4_E16_MASK, PseudoVFREDMAX_VS_M4_E16, 0x3, true }, // 754 |
832 | | { PseudoVFREDMAX_VS_M4_E32_MASK, PseudoVFREDMAX_VS_M4_E32, 0x3, true }, // 755 |
833 | | { PseudoVFREDMAX_VS_M4_E64_MASK, PseudoVFREDMAX_VS_M4_E64, 0x3, true }, // 756 |
834 | | { PseudoVFREDMAX_VS_M8_E16_MASK, PseudoVFREDMAX_VS_M8_E16, 0x3, true }, // 757 |
835 | | { PseudoVFREDMAX_VS_M8_E32_MASK, PseudoVFREDMAX_VS_M8_E32, 0x3, true }, // 758 |
836 | | { PseudoVFREDMAX_VS_M8_E64_MASK, PseudoVFREDMAX_VS_M8_E64, 0x3, true }, // 759 |
837 | | { PseudoVFREDMAX_VS_MF2_E16_MASK, PseudoVFREDMAX_VS_MF2_E16, 0x3, true }, // 760 |
838 | | { PseudoVFREDMAX_VS_MF2_E32_MASK, PseudoVFREDMAX_VS_MF2_E32, 0x3, true }, // 761 |
839 | | { PseudoVFREDMAX_VS_MF4_E16_MASK, PseudoVFREDMAX_VS_MF4_E16, 0x3, true }, // 762 |
840 | | { PseudoVFREDMIN_VS_M1_E16_MASK, PseudoVFREDMIN_VS_M1_E16, 0x3, true }, // 763 |
841 | | { PseudoVFREDMIN_VS_M1_E32_MASK, PseudoVFREDMIN_VS_M1_E32, 0x3, true }, // 764 |
842 | | { PseudoVFREDMIN_VS_M1_E64_MASK, PseudoVFREDMIN_VS_M1_E64, 0x3, true }, // 765 |
843 | | { PseudoVFREDMIN_VS_M2_E16_MASK, PseudoVFREDMIN_VS_M2_E16, 0x3, true }, // 766 |
844 | | { PseudoVFREDMIN_VS_M2_E32_MASK, PseudoVFREDMIN_VS_M2_E32, 0x3, true }, // 767 |
845 | | { PseudoVFREDMIN_VS_M2_E64_MASK, PseudoVFREDMIN_VS_M2_E64, 0x3, true }, // 768 |
846 | | { PseudoVFREDMIN_VS_M4_E16_MASK, PseudoVFREDMIN_VS_M4_E16, 0x3, true }, // 769 |
847 | | { PseudoVFREDMIN_VS_M4_E32_MASK, PseudoVFREDMIN_VS_M4_E32, 0x3, true }, // 770 |
848 | | { PseudoVFREDMIN_VS_M4_E64_MASK, PseudoVFREDMIN_VS_M4_E64, 0x3, true }, // 771 |
849 | | { PseudoVFREDMIN_VS_M8_E16_MASK, PseudoVFREDMIN_VS_M8_E16, 0x3, true }, // 772 |
850 | | { PseudoVFREDMIN_VS_M8_E32_MASK, PseudoVFREDMIN_VS_M8_E32, 0x3, true }, // 773 |
851 | | { PseudoVFREDMIN_VS_M8_E64_MASK, PseudoVFREDMIN_VS_M8_E64, 0x3, true }, // 774 |
852 | | { PseudoVFREDMIN_VS_MF2_E16_MASK, PseudoVFREDMIN_VS_MF2_E16, 0x3, true }, // 775 |
853 | | { PseudoVFREDMIN_VS_MF2_E32_MASK, PseudoVFREDMIN_VS_MF2_E32, 0x3, true }, // 776 |
854 | | { PseudoVFREDMIN_VS_MF4_E16_MASK, PseudoVFREDMIN_VS_MF4_E16, 0x3, true }, // 777 |
855 | | { PseudoVFREDOSUM_VS_M1_E16_MASK, PseudoVFREDOSUM_VS_M1_E16, 0x3, true }, // 778 |
856 | | { PseudoVFREDOSUM_VS_M1_E32_MASK, PseudoVFREDOSUM_VS_M1_E32, 0x3, true }, // 779 |
857 | | { PseudoVFREDOSUM_VS_M1_E64_MASK, PseudoVFREDOSUM_VS_M1_E64, 0x3, true }, // 780 |
858 | | { PseudoVFREDOSUM_VS_M2_E16_MASK, PseudoVFREDOSUM_VS_M2_E16, 0x3, true }, // 781 |
859 | | { PseudoVFREDOSUM_VS_M2_E32_MASK, PseudoVFREDOSUM_VS_M2_E32, 0x3, true }, // 782 |
860 | | { PseudoVFREDOSUM_VS_M2_E64_MASK, PseudoVFREDOSUM_VS_M2_E64, 0x3, true }, // 783 |
861 | | { PseudoVFREDOSUM_VS_M4_E16_MASK, PseudoVFREDOSUM_VS_M4_E16, 0x3, true }, // 784 |
862 | | { PseudoVFREDOSUM_VS_M4_E32_MASK, PseudoVFREDOSUM_VS_M4_E32, 0x3, true }, // 785 |
863 | | { PseudoVFREDOSUM_VS_M4_E64_MASK, PseudoVFREDOSUM_VS_M4_E64, 0x3, true }, // 786 |
864 | | { PseudoVFREDOSUM_VS_M8_E16_MASK, PseudoVFREDOSUM_VS_M8_E16, 0x3, true }, // 787 |
865 | | { PseudoVFREDOSUM_VS_M8_E32_MASK, PseudoVFREDOSUM_VS_M8_E32, 0x3, true }, // 788 |
866 | | { PseudoVFREDOSUM_VS_M8_E64_MASK, PseudoVFREDOSUM_VS_M8_E64, 0x3, true }, // 789 |
867 | | { PseudoVFREDOSUM_VS_MF2_E16_MASK, PseudoVFREDOSUM_VS_MF2_E16, 0x3, true }, // 790 |
868 | | { PseudoVFREDOSUM_VS_MF2_E32_MASK, PseudoVFREDOSUM_VS_MF2_E32, 0x3, true }, // 791 |
869 | | { PseudoVFREDOSUM_VS_MF4_E16_MASK, PseudoVFREDOSUM_VS_MF4_E16, 0x3, true }, // 792 |
870 | | { PseudoVFREDUSUM_VS_M1_E16_MASK, PseudoVFREDUSUM_VS_M1_E16, 0x3, true }, // 793 |
871 | | { PseudoVFREDUSUM_VS_M1_E32_MASK, PseudoVFREDUSUM_VS_M1_E32, 0x3, true }, // 794 |
872 | | { PseudoVFREDUSUM_VS_M1_E64_MASK, PseudoVFREDUSUM_VS_M1_E64, 0x3, true }, // 795 |
873 | | { PseudoVFREDUSUM_VS_M2_E16_MASK, PseudoVFREDUSUM_VS_M2_E16, 0x3, true }, // 796 |
874 | | { PseudoVFREDUSUM_VS_M2_E32_MASK, PseudoVFREDUSUM_VS_M2_E32, 0x3, true }, // 797 |
875 | | { PseudoVFREDUSUM_VS_M2_E64_MASK, PseudoVFREDUSUM_VS_M2_E64, 0x3, true }, // 798 |
876 | | { PseudoVFREDUSUM_VS_M4_E16_MASK, PseudoVFREDUSUM_VS_M4_E16, 0x3, true }, // 799 |
877 | | { PseudoVFREDUSUM_VS_M4_E32_MASK, PseudoVFREDUSUM_VS_M4_E32, 0x3, true }, // 800 |
878 | | { PseudoVFREDUSUM_VS_M4_E64_MASK, PseudoVFREDUSUM_VS_M4_E64, 0x3, true }, // 801 |
879 | | { PseudoVFREDUSUM_VS_M8_E16_MASK, PseudoVFREDUSUM_VS_M8_E16, 0x3, true }, // 802 |
880 | | { PseudoVFREDUSUM_VS_M8_E32_MASK, PseudoVFREDUSUM_VS_M8_E32, 0x3, true }, // 803 |
881 | | { PseudoVFREDUSUM_VS_M8_E64_MASK, PseudoVFREDUSUM_VS_M8_E64, 0x3, true }, // 804 |
882 | | { PseudoVFREDUSUM_VS_MF2_E16_MASK, PseudoVFREDUSUM_VS_MF2_E16, 0x3, true }, // 805 |
883 | | { PseudoVFREDUSUM_VS_MF2_E32_MASK, PseudoVFREDUSUM_VS_MF2_E32, 0x3, true }, // 806 |
884 | | { PseudoVFREDUSUM_VS_MF4_E16_MASK, PseudoVFREDUSUM_VS_MF4_E16, 0x3, true }, // 807 |
885 | | { PseudoVFRSQRT7_V_M1_MASK, PseudoVFRSQRT7_V_M1, 0x2, false }, // 808 |
886 | | { PseudoVFRSQRT7_V_M2_MASK, PseudoVFRSQRT7_V_M2, 0x2, false }, // 809 |
887 | | { PseudoVFRSQRT7_V_M4_MASK, PseudoVFRSQRT7_V_M4, 0x2, false }, // 810 |
888 | | { PseudoVFRSQRT7_V_M8_MASK, PseudoVFRSQRT7_V_M8, 0x2, false }, // 811 |
889 | | { PseudoVFRSQRT7_V_MF2_MASK, PseudoVFRSQRT7_V_MF2, 0x2, false }, // 812 |
890 | | { PseudoVFRSQRT7_V_MF4_MASK, PseudoVFRSQRT7_V_MF4, 0x2, false }, // 813 |
891 | | { PseudoVFRSUB_VFPR16_M1_MASK, PseudoVFRSUB_VFPR16_M1, 0x3, false }, // 814 |
892 | | { PseudoVFRSUB_VFPR16_M2_MASK, PseudoVFRSUB_VFPR16_M2, 0x3, false }, // 815 |
893 | | { PseudoVFRSUB_VFPR16_M4_MASK, PseudoVFRSUB_VFPR16_M4, 0x3, false }, // 816 |
894 | | { PseudoVFRSUB_VFPR16_M8_MASK, PseudoVFRSUB_VFPR16_M8, 0x3, false }, // 817 |
895 | | { PseudoVFRSUB_VFPR16_MF2_MASK, PseudoVFRSUB_VFPR16_MF2, 0x3, false }, // 818 |
896 | | { PseudoVFRSUB_VFPR16_MF4_MASK, PseudoVFRSUB_VFPR16_MF4, 0x3, false }, // 819 |
897 | | { PseudoVFRSUB_VFPR32_M1_MASK, PseudoVFRSUB_VFPR32_M1, 0x3, false }, // 820 |
898 | | { PseudoVFRSUB_VFPR32_M2_MASK, PseudoVFRSUB_VFPR32_M2, 0x3, false }, // 821 |
899 | | { PseudoVFRSUB_VFPR32_M4_MASK, PseudoVFRSUB_VFPR32_M4, 0x3, false }, // 822 |
900 | | { PseudoVFRSUB_VFPR32_M8_MASK, PseudoVFRSUB_VFPR32_M8, 0x3, false }, // 823 |
901 | | { PseudoVFRSUB_VFPR32_MF2_MASK, PseudoVFRSUB_VFPR32_MF2, 0x3, false }, // 824 |
902 | | { PseudoVFRSUB_VFPR64_M1_MASK, PseudoVFRSUB_VFPR64_M1, 0x3, false }, // 825 |
903 | | { PseudoVFRSUB_VFPR64_M2_MASK, PseudoVFRSUB_VFPR64_M2, 0x3, false }, // 826 |
904 | | { PseudoVFRSUB_VFPR64_M4_MASK, PseudoVFRSUB_VFPR64_M4, 0x3, false }, // 827 |
905 | | { PseudoVFRSUB_VFPR64_M8_MASK, PseudoVFRSUB_VFPR64_M8, 0x3, false }, // 828 |
906 | | { PseudoVFSGNJN_VFPR16_M1_MASK, PseudoVFSGNJN_VFPR16_M1, 0x3, false }, // 829 |
907 | | { PseudoVFSGNJN_VFPR16_M2_MASK, PseudoVFSGNJN_VFPR16_M2, 0x3, false }, // 830 |
908 | | { PseudoVFSGNJN_VFPR16_M4_MASK, PseudoVFSGNJN_VFPR16_M4, 0x3, false }, // 831 |
909 | | { PseudoVFSGNJN_VFPR16_M8_MASK, PseudoVFSGNJN_VFPR16_M8, 0x3, false }, // 832 |
910 | | { PseudoVFSGNJN_VFPR16_MF2_MASK, PseudoVFSGNJN_VFPR16_MF2, 0x3, false }, // 833 |
911 | | { PseudoVFSGNJN_VFPR16_MF4_MASK, PseudoVFSGNJN_VFPR16_MF4, 0x3, false }, // 834 |
912 | | { PseudoVFSGNJN_VFPR32_M1_MASK, PseudoVFSGNJN_VFPR32_M1, 0x3, false }, // 835 |
913 | | { PseudoVFSGNJN_VFPR32_M2_MASK, PseudoVFSGNJN_VFPR32_M2, 0x3, false }, // 836 |
914 | | { PseudoVFSGNJN_VFPR32_M4_MASK, PseudoVFSGNJN_VFPR32_M4, 0x3, false }, // 837 |
915 | | { PseudoVFSGNJN_VFPR32_M8_MASK, PseudoVFSGNJN_VFPR32_M8, 0x3, false }, // 838 |
916 | | { PseudoVFSGNJN_VFPR32_MF2_MASK, PseudoVFSGNJN_VFPR32_MF2, 0x3, false }, // 839 |
917 | | { PseudoVFSGNJN_VFPR64_M1_MASK, PseudoVFSGNJN_VFPR64_M1, 0x3, false }, // 840 |
918 | | { PseudoVFSGNJN_VFPR64_M2_MASK, PseudoVFSGNJN_VFPR64_M2, 0x3, false }, // 841 |
919 | | { PseudoVFSGNJN_VFPR64_M4_MASK, PseudoVFSGNJN_VFPR64_M4, 0x3, false }, // 842 |
920 | | { PseudoVFSGNJN_VFPR64_M8_MASK, PseudoVFSGNJN_VFPR64_M8, 0x3, false }, // 843 |
921 | | { PseudoVFSGNJN_VV_M1_MASK, PseudoVFSGNJN_VV_M1, 0x3, false }, // 844 |
922 | | { PseudoVFSGNJN_VV_M2_MASK, PseudoVFSGNJN_VV_M2, 0x3, false }, // 845 |
923 | | { PseudoVFSGNJN_VV_M4_MASK, PseudoVFSGNJN_VV_M4, 0x3, false }, // 846 |
924 | | { PseudoVFSGNJN_VV_M8_MASK, PseudoVFSGNJN_VV_M8, 0x3, false }, // 847 |
925 | | { PseudoVFSGNJN_VV_MF2_MASK, PseudoVFSGNJN_VV_MF2, 0x3, false }, // 848 |
926 | | { PseudoVFSGNJN_VV_MF4_MASK, PseudoVFSGNJN_VV_MF4, 0x3, false }, // 849 |
927 | | { PseudoVFSGNJX_VFPR16_M1_MASK, PseudoVFSGNJX_VFPR16_M1, 0x3, false }, // 850 |
928 | | { PseudoVFSGNJX_VFPR16_M2_MASK, PseudoVFSGNJX_VFPR16_M2, 0x3, false }, // 851 |
929 | | { PseudoVFSGNJX_VFPR16_M4_MASK, PseudoVFSGNJX_VFPR16_M4, 0x3, false }, // 852 |
930 | | { PseudoVFSGNJX_VFPR16_M8_MASK, PseudoVFSGNJX_VFPR16_M8, 0x3, false }, // 853 |
931 | | { PseudoVFSGNJX_VFPR16_MF2_MASK, PseudoVFSGNJX_VFPR16_MF2, 0x3, false }, // 854 |
932 | | { PseudoVFSGNJX_VFPR16_MF4_MASK, PseudoVFSGNJX_VFPR16_MF4, 0x3, false }, // 855 |
933 | | { PseudoVFSGNJX_VFPR32_M1_MASK, PseudoVFSGNJX_VFPR32_M1, 0x3, false }, // 856 |
934 | | { PseudoVFSGNJX_VFPR32_M2_MASK, PseudoVFSGNJX_VFPR32_M2, 0x3, false }, // 857 |
935 | | { PseudoVFSGNJX_VFPR32_M4_MASK, PseudoVFSGNJX_VFPR32_M4, 0x3, false }, // 858 |
936 | | { PseudoVFSGNJX_VFPR32_M8_MASK, PseudoVFSGNJX_VFPR32_M8, 0x3, false }, // 859 |
937 | | { PseudoVFSGNJX_VFPR32_MF2_MASK, PseudoVFSGNJX_VFPR32_MF2, 0x3, false }, // 860 |
938 | | { PseudoVFSGNJX_VFPR64_M1_MASK, PseudoVFSGNJX_VFPR64_M1, 0x3, false }, // 861 |
939 | | { PseudoVFSGNJX_VFPR64_M2_MASK, PseudoVFSGNJX_VFPR64_M2, 0x3, false }, // 862 |
940 | | { PseudoVFSGNJX_VFPR64_M4_MASK, PseudoVFSGNJX_VFPR64_M4, 0x3, false }, // 863 |
941 | | { PseudoVFSGNJX_VFPR64_M8_MASK, PseudoVFSGNJX_VFPR64_M8, 0x3, false }, // 864 |
942 | | { PseudoVFSGNJX_VV_M1_MASK, PseudoVFSGNJX_VV_M1, 0x3, false }, // 865 |
943 | | { PseudoVFSGNJX_VV_M2_MASK, PseudoVFSGNJX_VV_M2, 0x3, false }, // 866 |
944 | | { PseudoVFSGNJX_VV_M4_MASK, PseudoVFSGNJX_VV_M4, 0x3, false }, // 867 |
945 | | { PseudoVFSGNJX_VV_M8_MASK, PseudoVFSGNJX_VV_M8, 0x3, false }, // 868 |
946 | | { PseudoVFSGNJX_VV_MF2_MASK, PseudoVFSGNJX_VV_MF2, 0x3, false }, // 869 |
947 | | { PseudoVFSGNJX_VV_MF4_MASK, PseudoVFSGNJX_VV_MF4, 0x3, false }, // 870 |
948 | | { PseudoVFSGNJ_VFPR16_M1_MASK, PseudoVFSGNJ_VFPR16_M1, 0x3, false }, // 871 |
949 | | { PseudoVFSGNJ_VFPR16_M2_MASK, PseudoVFSGNJ_VFPR16_M2, 0x3, false }, // 872 |
950 | | { PseudoVFSGNJ_VFPR16_M4_MASK, PseudoVFSGNJ_VFPR16_M4, 0x3, false }, // 873 |
951 | | { PseudoVFSGNJ_VFPR16_M8_MASK, PseudoVFSGNJ_VFPR16_M8, 0x3, false }, // 874 |
952 | | { PseudoVFSGNJ_VFPR16_MF2_MASK, PseudoVFSGNJ_VFPR16_MF2, 0x3, false }, // 875 |
953 | | { PseudoVFSGNJ_VFPR16_MF4_MASK, PseudoVFSGNJ_VFPR16_MF4, 0x3, false }, // 876 |
954 | | { PseudoVFSGNJ_VFPR32_M1_MASK, PseudoVFSGNJ_VFPR32_M1, 0x3, false }, // 877 |
955 | | { PseudoVFSGNJ_VFPR32_M2_MASK, PseudoVFSGNJ_VFPR32_M2, 0x3, false }, // 878 |
956 | | { PseudoVFSGNJ_VFPR32_M4_MASK, PseudoVFSGNJ_VFPR32_M4, 0x3, false }, // 879 |
957 | | { PseudoVFSGNJ_VFPR32_M8_MASK, PseudoVFSGNJ_VFPR32_M8, 0x3, false }, // 880 |
958 | | { PseudoVFSGNJ_VFPR32_MF2_MASK, PseudoVFSGNJ_VFPR32_MF2, 0x3, false }, // 881 |
959 | | { PseudoVFSGNJ_VFPR64_M1_MASK, PseudoVFSGNJ_VFPR64_M1, 0x3, false }, // 882 |
960 | | { PseudoVFSGNJ_VFPR64_M2_MASK, PseudoVFSGNJ_VFPR64_M2, 0x3, false }, // 883 |
961 | | { PseudoVFSGNJ_VFPR64_M4_MASK, PseudoVFSGNJ_VFPR64_M4, 0x3, false }, // 884 |
962 | | { PseudoVFSGNJ_VFPR64_M8_MASK, PseudoVFSGNJ_VFPR64_M8, 0x3, false }, // 885 |
963 | | { PseudoVFSGNJ_VV_M1_MASK, PseudoVFSGNJ_VV_M1, 0x3, false }, // 886 |
964 | | { PseudoVFSGNJ_VV_M2_MASK, PseudoVFSGNJ_VV_M2, 0x3, false }, // 887 |
965 | | { PseudoVFSGNJ_VV_M4_MASK, PseudoVFSGNJ_VV_M4, 0x3, false }, // 888 |
966 | | { PseudoVFSGNJ_VV_M8_MASK, PseudoVFSGNJ_VV_M8, 0x3, false }, // 889 |
967 | | { PseudoVFSGNJ_VV_MF2_MASK, PseudoVFSGNJ_VV_MF2, 0x3, false }, // 890 |
968 | | { PseudoVFSGNJ_VV_MF4_MASK, PseudoVFSGNJ_VV_MF4, 0x3, false }, // 891 |
969 | | { PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, PseudoVFSLIDE1DOWN_VFPR16_M1, 0x3, false }, // 892 |
970 | | { PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, PseudoVFSLIDE1DOWN_VFPR16_M2, 0x3, false }, // 893 |
971 | | { PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, PseudoVFSLIDE1DOWN_VFPR16_M4, 0x3, false }, // 894 |
972 | | { PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, PseudoVFSLIDE1DOWN_VFPR16_M8, 0x3, false }, // 895 |
973 | | { PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, PseudoVFSLIDE1DOWN_VFPR16_MF2, 0x3, false }, // 896 |
974 | | { PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, PseudoVFSLIDE1DOWN_VFPR16_MF4, 0x3, false }, // 897 |
975 | | { PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, PseudoVFSLIDE1DOWN_VFPR32_M1, 0x3, false }, // 898 |
976 | | { PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, PseudoVFSLIDE1DOWN_VFPR32_M2, 0x3, false }, // 899 |
977 | | { PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, PseudoVFSLIDE1DOWN_VFPR32_M4, 0x3, false }, // 900 |
978 | | { PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, PseudoVFSLIDE1DOWN_VFPR32_M8, 0x3, false }, // 901 |
979 | | { PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, PseudoVFSLIDE1DOWN_VFPR32_MF2, 0x3, false }, // 902 |
980 | | { PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, PseudoVFSLIDE1DOWN_VFPR64_M1, 0x3, false }, // 903 |
981 | | { PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, PseudoVFSLIDE1DOWN_VFPR64_M2, 0x3, false }, // 904 |
982 | | { PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, PseudoVFSLIDE1DOWN_VFPR64_M4, 0x3, false }, // 905 |
983 | | { PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, PseudoVFSLIDE1DOWN_VFPR64_M8, 0x3, false }, // 906 |
984 | | { PseudoVFSLIDE1UP_VFPR16_M1_MASK, PseudoVFSLIDE1UP_VFPR16_M1, 0x3, false }, // 907 |
985 | | { PseudoVFSLIDE1UP_VFPR16_M2_MASK, PseudoVFSLIDE1UP_VFPR16_M2, 0x3, false }, // 908 |
986 | | { PseudoVFSLIDE1UP_VFPR16_M4_MASK, PseudoVFSLIDE1UP_VFPR16_M4, 0x3, false }, // 909 |
987 | | { PseudoVFSLIDE1UP_VFPR16_M8_MASK, PseudoVFSLIDE1UP_VFPR16_M8, 0x3, false }, // 910 |
988 | | { PseudoVFSLIDE1UP_VFPR16_MF2_MASK, PseudoVFSLIDE1UP_VFPR16_MF2, 0x3, false }, // 911 |
989 | | { PseudoVFSLIDE1UP_VFPR16_MF4_MASK, PseudoVFSLIDE1UP_VFPR16_MF4, 0x3, false }, // 912 |
990 | | { PseudoVFSLIDE1UP_VFPR32_M1_MASK, PseudoVFSLIDE1UP_VFPR32_M1, 0x3, false }, // 913 |
991 | | { PseudoVFSLIDE1UP_VFPR32_M2_MASK, PseudoVFSLIDE1UP_VFPR32_M2, 0x3, false }, // 914 |
992 | | { PseudoVFSLIDE1UP_VFPR32_M4_MASK, PseudoVFSLIDE1UP_VFPR32_M4, 0x3, false }, // 915 |
993 | | { PseudoVFSLIDE1UP_VFPR32_M8_MASK, PseudoVFSLIDE1UP_VFPR32_M8, 0x3, false }, // 916 |
994 | | { PseudoVFSLIDE1UP_VFPR32_MF2_MASK, PseudoVFSLIDE1UP_VFPR32_MF2, 0x3, false }, // 917 |
995 | | { PseudoVFSLIDE1UP_VFPR64_M1_MASK, PseudoVFSLIDE1UP_VFPR64_M1, 0x3, false }, // 918 |
996 | | { PseudoVFSLIDE1UP_VFPR64_M2_MASK, PseudoVFSLIDE1UP_VFPR64_M2, 0x3, false }, // 919 |
997 | | { PseudoVFSLIDE1UP_VFPR64_M4_MASK, PseudoVFSLIDE1UP_VFPR64_M4, 0x3, false }, // 920 |
998 | | { PseudoVFSLIDE1UP_VFPR64_M8_MASK, PseudoVFSLIDE1UP_VFPR64_M8, 0x3, false }, // 921 |
999 | | { PseudoVFSQRT_V_M1_E16_MASK, PseudoVFSQRT_V_M1_E16, 0x2, false }, // 922 |
1000 | | { PseudoVFSQRT_V_M1_E32_MASK, PseudoVFSQRT_V_M1_E32, 0x2, false }, // 923 |
1001 | | { PseudoVFSQRT_V_M1_E64_MASK, PseudoVFSQRT_V_M1_E64, 0x2, false }, // 924 |
1002 | | { PseudoVFSQRT_V_M2_E16_MASK, PseudoVFSQRT_V_M2_E16, 0x2, false }, // 925 |
1003 | | { PseudoVFSQRT_V_M2_E32_MASK, PseudoVFSQRT_V_M2_E32, 0x2, false }, // 926 |
1004 | | { PseudoVFSQRT_V_M2_E64_MASK, PseudoVFSQRT_V_M2_E64, 0x2, false }, // 927 |
1005 | | { PseudoVFSQRT_V_M4_E16_MASK, PseudoVFSQRT_V_M4_E16, 0x2, false }, // 928 |
1006 | | { PseudoVFSQRT_V_M4_E32_MASK, PseudoVFSQRT_V_M4_E32, 0x2, false }, // 929 |
1007 | | { PseudoVFSQRT_V_M4_E64_MASK, PseudoVFSQRT_V_M4_E64, 0x2, false }, // 930 |
1008 | | { PseudoVFSQRT_V_M8_E16_MASK, PseudoVFSQRT_V_M8_E16, 0x2, false }, // 931 |
1009 | | { PseudoVFSQRT_V_M8_E32_MASK, PseudoVFSQRT_V_M8_E32, 0x2, false }, // 932 |
1010 | | { PseudoVFSQRT_V_M8_E64_MASK, PseudoVFSQRT_V_M8_E64, 0x2, false }, // 933 |
1011 | | { PseudoVFSQRT_V_MF2_E16_MASK, PseudoVFSQRT_V_MF2_E16, 0x2, false }, // 934 |
1012 | | { PseudoVFSQRT_V_MF2_E32_MASK, PseudoVFSQRT_V_MF2_E32, 0x2, false }, // 935 |
1013 | | { PseudoVFSQRT_V_MF4_E16_MASK, PseudoVFSQRT_V_MF4_E16, 0x2, false }, // 936 |
1014 | | { PseudoVFSUB_VFPR16_M1_MASK, PseudoVFSUB_VFPR16_M1, 0x3, false }, // 937 |
1015 | | { PseudoVFSUB_VFPR16_M2_MASK, PseudoVFSUB_VFPR16_M2, 0x3, false }, // 938 |
1016 | | { PseudoVFSUB_VFPR16_M4_MASK, PseudoVFSUB_VFPR16_M4, 0x3, false }, // 939 |
1017 | | { PseudoVFSUB_VFPR16_M8_MASK, PseudoVFSUB_VFPR16_M8, 0x3, false }, // 940 |
1018 | | { PseudoVFSUB_VFPR16_MF2_MASK, PseudoVFSUB_VFPR16_MF2, 0x3, false }, // 941 |
1019 | | { PseudoVFSUB_VFPR16_MF4_MASK, PseudoVFSUB_VFPR16_MF4, 0x3, false }, // 942 |
1020 | | { PseudoVFSUB_VFPR32_M1_MASK, PseudoVFSUB_VFPR32_M1, 0x3, false }, // 943 |
1021 | | { PseudoVFSUB_VFPR32_M2_MASK, PseudoVFSUB_VFPR32_M2, 0x3, false }, // 944 |
1022 | | { PseudoVFSUB_VFPR32_M4_MASK, PseudoVFSUB_VFPR32_M4, 0x3, false }, // 945 |
1023 | | { PseudoVFSUB_VFPR32_M8_MASK, PseudoVFSUB_VFPR32_M8, 0x3, false }, // 946 |
1024 | | { PseudoVFSUB_VFPR32_MF2_MASK, PseudoVFSUB_VFPR32_MF2, 0x3, false }, // 947 |
1025 | | { PseudoVFSUB_VFPR64_M1_MASK, PseudoVFSUB_VFPR64_M1, 0x3, false }, // 948 |
1026 | | { PseudoVFSUB_VFPR64_M2_MASK, PseudoVFSUB_VFPR64_M2, 0x3, false }, // 949 |
1027 | | { PseudoVFSUB_VFPR64_M4_MASK, PseudoVFSUB_VFPR64_M4, 0x3, false }, // 950 |
1028 | | { PseudoVFSUB_VFPR64_M8_MASK, PseudoVFSUB_VFPR64_M8, 0x3, false }, // 951 |
1029 | | { PseudoVFSUB_VV_M1_MASK, PseudoVFSUB_VV_M1, 0x3, false }, // 952 |
1030 | | { PseudoVFSUB_VV_M2_MASK, PseudoVFSUB_VV_M2, 0x3, false }, // 953 |
1031 | | { PseudoVFSUB_VV_M4_MASK, PseudoVFSUB_VV_M4, 0x3, false }, // 954 |
1032 | | { PseudoVFSUB_VV_M8_MASK, PseudoVFSUB_VV_M8, 0x3, false }, // 955 |
1033 | | { PseudoVFSUB_VV_MF2_MASK, PseudoVFSUB_VV_MF2, 0x3, false }, // 956 |
1034 | | { PseudoVFSUB_VV_MF4_MASK, PseudoVFSUB_VV_MF4, 0x3, false }, // 957 |
1035 | | { PseudoVFWADD_VFPR16_M1_MASK, PseudoVFWADD_VFPR16_M1, 0x3, false }, // 958 |
1036 | | { PseudoVFWADD_VFPR16_M2_MASK, PseudoVFWADD_VFPR16_M2, 0x3, false }, // 959 |
1037 | | { PseudoVFWADD_VFPR16_M4_MASK, PseudoVFWADD_VFPR16_M4, 0x3, false }, // 960 |
1038 | | { PseudoVFWADD_VFPR16_MF2_MASK, PseudoVFWADD_VFPR16_MF2, 0x3, false }, // 961 |
1039 | | { PseudoVFWADD_VFPR16_MF4_MASK, PseudoVFWADD_VFPR16_MF4, 0x3, false }, // 962 |
1040 | | { PseudoVFWADD_VFPR32_M1_MASK, PseudoVFWADD_VFPR32_M1, 0x3, false }, // 963 |
1041 | | { PseudoVFWADD_VFPR32_M2_MASK, PseudoVFWADD_VFPR32_M2, 0x3, false }, // 964 |
1042 | | { PseudoVFWADD_VFPR32_M4_MASK, PseudoVFWADD_VFPR32_M4, 0x3, false }, // 965 |
1043 | | { PseudoVFWADD_VFPR32_MF2_MASK, PseudoVFWADD_VFPR32_MF2, 0x3, false }, // 966 |
1044 | | { PseudoVFWADD_VV_M1_MASK, PseudoVFWADD_VV_M1, 0x3, false }, // 967 |
1045 | | { PseudoVFWADD_VV_M2_MASK, PseudoVFWADD_VV_M2, 0x3, false }, // 968 |
1046 | | { PseudoVFWADD_VV_M4_MASK, PseudoVFWADD_VV_M4, 0x3, false }, // 969 |
1047 | | { PseudoVFWADD_VV_MF2_MASK, PseudoVFWADD_VV_MF2, 0x3, false }, // 970 |
1048 | | { PseudoVFWADD_VV_MF4_MASK, PseudoVFWADD_VV_MF4, 0x3, false }, // 971 |
1049 | | { PseudoVFWADD_WFPR16_M1_MASK, PseudoVFWADD_WFPR16_M1, 0x3, false }, // 972 |
1050 | | { PseudoVFWADD_WFPR16_M2_MASK, PseudoVFWADD_WFPR16_M2, 0x3, false }, // 973 |
1051 | | { PseudoVFWADD_WFPR16_M4_MASK, PseudoVFWADD_WFPR16_M4, 0x3, false }, // 974 |
1052 | | { PseudoVFWADD_WFPR16_MF2_MASK, PseudoVFWADD_WFPR16_MF2, 0x3, false }, // 975 |
1053 | | { PseudoVFWADD_WFPR16_MF4_MASK, PseudoVFWADD_WFPR16_MF4, 0x3, false }, // 976 |
1054 | | { PseudoVFWADD_WFPR32_M1_MASK, PseudoVFWADD_WFPR32_M1, 0x3, false }, // 977 |
1055 | | { PseudoVFWADD_WFPR32_M2_MASK, PseudoVFWADD_WFPR32_M2, 0x3, false }, // 978 |
1056 | | { PseudoVFWADD_WFPR32_M4_MASK, PseudoVFWADD_WFPR32_M4, 0x3, false }, // 979 |
1057 | | { PseudoVFWADD_WFPR32_MF2_MASK, PseudoVFWADD_WFPR32_MF2, 0x3, false }, // 980 |
1058 | | { PseudoVFWADD_WV_M1_MASK, PseudoVFWADD_WV_M1, 0x3, false }, // 981 |
1059 | | { PseudoVFWADD_WV_M2_MASK, PseudoVFWADD_WV_M2, 0x3, false }, // 982 |
1060 | | { PseudoVFWADD_WV_M4_MASK, PseudoVFWADD_WV_M4, 0x3, false }, // 983 |
1061 | | { PseudoVFWADD_WV_MF2_MASK, PseudoVFWADD_WV_MF2, 0x3, false }, // 984 |
1062 | | { PseudoVFWADD_WV_MF4_MASK, PseudoVFWADD_WV_MF4, 0x3, false }, // 985 |
1063 | | { PseudoVFWCVTBF16_F_F_V_M1_MASK, PseudoVFWCVTBF16_F_F_V_M1, 0x2, false }, // 986 |
1064 | | { PseudoVFWCVTBF16_F_F_V_M2_MASK, PseudoVFWCVTBF16_F_F_V_M2, 0x2, false }, // 987 |
1065 | | { PseudoVFWCVTBF16_F_F_V_M4_MASK, PseudoVFWCVTBF16_F_F_V_M4, 0x2, false }, // 988 |
1066 | | { PseudoVFWCVTBF16_F_F_V_MF2_MASK, PseudoVFWCVTBF16_F_F_V_MF2, 0x2, false }, // 989 |
1067 | | { PseudoVFWCVTBF16_F_F_V_MF4_MASK, PseudoVFWCVTBF16_F_F_V_MF4, 0x2, false }, // 990 |
1068 | | { PseudoVFWCVT_F_F_V_M1_MASK, PseudoVFWCVT_F_F_V_M1, 0x2, false }, // 991 |
1069 | | { PseudoVFWCVT_F_F_V_M2_MASK, PseudoVFWCVT_F_F_V_M2, 0x2, false }, // 992 |
1070 | | { PseudoVFWCVT_F_F_V_M4_MASK, PseudoVFWCVT_F_F_V_M4, 0x2, false }, // 993 |
1071 | | { PseudoVFWCVT_F_F_V_MF2_MASK, PseudoVFWCVT_F_F_V_MF2, 0x2, false }, // 994 |
1072 | | { PseudoVFWCVT_F_F_V_MF4_MASK, PseudoVFWCVT_F_F_V_MF4, 0x2, false }, // 995 |
1073 | | { PseudoVFWCVT_F_XU_V_M1_MASK, PseudoVFWCVT_F_XU_V_M1, 0x2, false }, // 996 |
1074 | | { PseudoVFWCVT_F_XU_V_M2_MASK, PseudoVFWCVT_F_XU_V_M2, 0x2, false }, // 997 |
1075 | | { PseudoVFWCVT_F_XU_V_M4_MASK, PseudoVFWCVT_F_XU_V_M4, 0x2, false }, // 998 |
1076 | | { PseudoVFWCVT_F_XU_V_MF2_MASK, PseudoVFWCVT_F_XU_V_MF2, 0x2, false }, // 999 |
1077 | | { PseudoVFWCVT_F_XU_V_MF4_MASK, PseudoVFWCVT_F_XU_V_MF4, 0x2, false }, // 1000 |
1078 | | { PseudoVFWCVT_F_XU_V_MF8_MASK, PseudoVFWCVT_F_XU_V_MF8, 0x2, false }, // 1001 |
1079 | | { PseudoVFWCVT_F_X_V_M1_MASK, PseudoVFWCVT_F_X_V_M1, 0x2, false }, // 1002 |
1080 | | { PseudoVFWCVT_F_X_V_M2_MASK, PseudoVFWCVT_F_X_V_M2, 0x2, false }, // 1003 |
1081 | | { PseudoVFWCVT_F_X_V_M4_MASK, PseudoVFWCVT_F_X_V_M4, 0x2, false }, // 1004 |
1082 | | { PseudoVFWCVT_F_X_V_MF2_MASK, PseudoVFWCVT_F_X_V_MF2, 0x2, false }, // 1005 |
1083 | | { PseudoVFWCVT_F_X_V_MF4_MASK, PseudoVFWCVT_F_X_V_MF4, 0x2, false }, // 1006 |
1084 | | { PseudoVFWCVT_F_X_V_MF8_MASK, PseudoVFWCVT_F_X_V_MF8, 0x2, false }, // 1007 |
1085 | | { PseudoVFWCVT_RM_XU_F_V_M1_MASK, PseudoVFWCVT_RM_XU_F_V_M1, 0x2, false }, // 1008 |
1086 | | { PseudoVFWCVT_RM_XU_F_V_M2_MASK, PseudoVFWCVT_RM_XU_F_V_M2, 0x2, false }, // 1009 |
1087 | | { PseudoVFWCVT_RM_XU_F_V_M4_MASK, PseudoVFWCVT_RM_XU_F_V_M4, 0x2, false }, // 1010 |
1088 | | { PseudoVFWCVT_RM_XU_F_V_MF2_MASK, PseudoVFWCVT_RM_XU_F_V_MF2, 0x2, false }, // 1011 |
1089 | | { PseudoVFWCVT_RM_XU_F_V_MF4_MASK, PseudoVFWCVT_RM_XU_F_V_MF4, 0x2, false }, // 1012 |
1090 | | { PseudoVFWCVT_RM_X_F_V_M1_MASK, PseudoVFWCVT_RM_X_F_V_M1, 0x2, false }, // 1013 |
1091 | | { PseudoVFWCVT_RM_X_F_V_M2_MASK, PseudoVFWCVT_RM_X_F_V_M2, 0x2, false }, // 1014 |
1092 | | { PseudoVFWCVT_RM_X_F_V_M4_MASK, PseudoVFWCVT_RM_X_F_V_M4, 0x2, false }, // 1015 |
1093 | | { PseudoVFWCVT_RM_X_F_V_MF2_MASK, PseudoVFWCVT_RM_X_F_V_MF2, 0x2, false }, // 1016 |
1094 | | { PseudoVFWCVT_RM_X_F_V_MF4_MASK, PseudoVFWCVT_RM_X_F_V_MF4, 0x2, false }, // 1017 |
1095 | | { PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, PseudoVFWCVT_RTZ_XU_F_V_M1, 0x2, false }, // 1018 |
1096 | | { PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, PseudoVFWCVT_RTZ_XU_F_V_M2, 0x2, false }, // 1019 |
1097 | | { PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, PseudoVFWCVT_RTZ_XU_F_V_M4, 0x2, false }, // 1020 |
1098 | | { PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, PseudoVFWCVT_RTZ_XU_F_V_MF2, 0x2, false }, // 1021 |
1099 | | { PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, PseudoVFWCVT_RTZ_XU_F_V_MF4, 0x2, false }, // 1022 |
1100 | | { PseudoVFWCVT_RTZ_X_F_V_M1_MASK, PseudoVFWCVT_RTZ_X_F_V_M1, 0x2, false }, // 1023 |
1101 | | { PseudoVFWCVT_RTZ_X_F_V_M2_MASK, PseudoVFWCVT_RTZ_X_F_V_M2, 0x2, false }, // 1024 |
1102 | | { PseudoVFWCVT_RTZ_X_F_V_M4_MASK, PseudoVFWCVT_RTZ_X_F_V_M4, 0x2, false }, // 1025 |
1103 | | { PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, PseudoVFWCVT_RTZ_X_F_V_MF2, 0x2, false }, // 1026 |
1104 | | { PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, PseudoVFWCVT_RTZ_X_F_V_MF4, 0x2, false }, // 1027 |
1105 | | { PseudoVFWCVT_XU_F_V_M1_MASK, PseudoVFWCVT_XU_F_V_M1, 0x2, false }, // 1028 |
1106 | | { PseudoVFWCVT_XU_F_V_M2_MASK, PseudoVFWCVT_XU_F_V_M2, 0x2, false }, // 1029 |
1107 | | { PseudoVFWCVT_XU_F_V_M4_MASK, PseudoVFWCVT_XU_F_V_M4, 0x2, false }, // 1030 |
1108 | | { PseudoVFWCVT_XU_F_V_MF2_MASK, PseudoVFWCVT_XU_F_V_MF2, 0x2, false }, // 1031 |
1109 | | { PseudoVFWCVT_XU_F_V_MF4_MASK, PseudoVFWCVT_XU_F_V_MF4, 0x2, false }, // 1032 |
1110 | | { PseudoVFWCVT_X_F_V_M1_MASK, PseudoVFWCVT_X_F_V_M1, 0x2, false }, // 1033 |
1111 | | { PseudoVFWCVT_X_F_V_M2_MASK, PseudoVFWCVT_X_F_V_M2, 0x2, false }, // 1034 |
1112 | | { PseudoVFWCVT_X_F_V_M4_MASK, PseudoVFWCVT_X_F_V_M4, 0x2, false }, // 1035 |
1113 | | { PseudoVFWCVT_X_F_V_MF2_MASK, PseudoVFWCVT_X_F_V_MF2, 0x2, false }, // 1036 |
1114 | | { PseudoVFWCVT_X_F_V_MF4_MASK, PseudoVFWCVT_X_F_V_MF4, 0x2, false }, // 1037 |
1115 | | { PseudoVFWMACCBF16_VFPR16_M1_MASK, PseudoVFWMACCBF16_VFPR16_M1, 0x3, false }, // 1038 |
1116 | | { PseudoVFWMACCBF16_VFPR16_M2_MASK, PseudoVFWMACCBF16_VFPR16_M2, 0x3, false }, // 1039 |
1117 | | { PseudoVFWMACCBF16_VFPR16_M4_MASK, PseudoVFWMACCBF16_VFPR16_M4, 0x3, false }, // 1040 |
1118 | | { PseudoVFWMACCBF16_VFPR16_MF2_MASK, PseudoVFWMACCBF16_VFPR16_MF2, 0x3, false }, // 1041 |
1119 | | { PseudoVFWMACCBF16_VFPR16_MF4_MASK, PseudoVFWMACCBF16_VFPR16_MF4, 0x3, false }, // 1042 |
1120 | | { PseudoVFWMACCBF16_VV_M1_MASK, PseudoVFWMACCBF16_VV_M1, 0x3, false }, // 1043 |
1121 | | { PseudoVFWMACCBF16_VV_M2_MASK, PseudoVFWMACCBF16_VV_M2, 0x3, false }, // 1044 |
1122 | | { PseudoVFWMACCBF16_VV_M4_MASK, PseudoVFWMACCBF16_VV_M4, 0x3, false }, // 1045 |
1123 | | { PseudoVFWMACCBF16_VV_MF2_MASK, PseudoVFWMACCBF16_VV_MF2, 0x3, false }, // 1046 |
1124 | | { PseudoVFWMACCBF16_VV_MF4_MASK, PseudoVFWMACCBF16_VV_MF4, 0x3, false }, // 1047 |
1125 | | { PseudoVFWMACC_VFPR16_M1_MASK, PseudoVFWMACC_VFPR16_M1, 0x3, false }, // 1048 |
1126 | | { PseudoVFWMACC_VFPR16_M2_MASK, PseudoVFWMACC_VFPR16_M2, 0x3, false }, // 1049 |
1127 | | { PseudoVFWMACC_VFPR16_M4_MASK, PseudoVFWMACC_VFPR16_M4, 0x3, false }, // 1050 |
1128 | | { PseudoVFWMACC_VFPR16_MF2_MASK, PseudoVFWMACC_VFPR16_MF2, 0x3, false }, // 1051 |
1129 | | { PseudoVFWMACC_VFPR16_MF4_MASK, PseudoVFWMACC_VFPR16_MF4, 0x3, false }, // 1052 |
1130 | | { PseudoVFWMACC_VFPR32_M1_MASK, PseudoVFWMACC_VFPR32_M1, 0x3, false }, // 1053 |
1131 | | { PseudoVFWMACC_VFPR32_M2_MASK, PseudoVFWMACC_VFPR32_M2, 0x3, false }, // 1054 |
1132 | | { PseudoVFWMACC_VFPR32_M4_MASK, PseudoVFWMACC_VFPR32_M4, 0x3, false }, // 1055 |
1133 | | { PseudoVFWMACC_VFPR32_MF2_MASK, PseudoVFWMACC_VFPR32_MF2, 0x3, false }, // 1056 |
1134 | | { PseudoVFWMACC_VV_M1_MASK, PseudoVFWMACC_VV_M1, 0x3, false }, // 1057 |
1135 | | { PseudoVFWMACC_VV_M2_MASK, PseudoVFWMACC_VV_M2, 0x3, false }, // 1058 |
1136 | | { PseudoVFWMACC_VV_M4_MASK, PseudoVFWMACC_VV_M4, 0x3, false }, // 1059 |
1137 | | { PseudoVFWMACC_VV_MF2_MASK, PseudoVFWMACC_VV_MF2, 0x3, false }, // 1060 |
1138 | | { PseudoVFWMACC_VV_MF4_MASK, PseudoVFWMACC_VV_MF4, 0x3, false }, // 1061 |
1139 | | { PseudoVFWMSAC_VFPR16_M1_MASK, PseudoVFWMSAC_VFPR16_M1, 0x3, false }, // 1062 |
1140 | | { PseudoVFWMSAC_VFPR16_M2_MASK, PseudoVFWMSAC_VFPR16_M2, 0x3, false }, // 1063 |
1141 | | { PseudoVFWMSAC_VFPR16_M4_MASK, PseudoVFWMSAC_VFPR16_M4, 0x3, false }, // 1064 |
1142 | | { PseudoVFWMSAC_VFPR16_MF2_MASK, PseudoVFWMSAC_VFPR16_MF2, 0x3, false }, // 1065 |
1143 | | { PseudoVFWMSAC_VFPR16_MF4_MASK, PseudoVFWMSAC_VFPR16_MF4, 0x3, false }, // 1066 |
1144 | | { PseudoVFWMSAC_VFPR32_M1_MASK, PseudoVFWMSAC_VFPR32_M1, 0x3, false }, // 1067 |
1145 | | { PseudoVFWMSAC_VFPR32_M2_MASK, PseudoVFWMSAC_VFPR32_M2, 0x3, false }, // 1068 |
1146 | | { PseudoVFWMSAC_VFPR32_M4_MASK, PseudoVFWMSAC_VFPR32_M4, 0x3, false }, // 1069 |
1147 | | { PseudoVFWMSAC_VFPR32_MF2_MASK, PseudoVFWMSAC_VFPR32_MF2, 0x3, false }, // 1070 |
1148 | | { PseudoVFWMSAC_VV_M1_MASK, PseudoVFWMSAC_VV_M1, 0x3, false }, // 1071 |
1149 | | { PseudoVFWMSAC_VV_M2_MASK, PseudoVFWMSAC_VV_M2, 0x3, false }, // 1072 |
1150 | | { PseudoVFWMSAC_VV_M4_MASK, PseudoVFWMSAC_VV_M4, 0x3, false }, // 1073 |
1151 | | { PseudoVFWMSAC_VV_MF2_MASK, PseudoVFWMSAC_VV_MF2, 0x3, false }, // 1074 |
1152 | | { PseudoVFWMSAC_VV_MF4_MASK, PseudoVFWMSAC_VV_MF4, 0x3, false }, // 1075 |
1153 | | { PseudoVFWMUL_VFPR16_M1_MASK, PseudoVFWMUL_VFPR16_M1, 0x3, false }, // 1076 |
1154 | | { PseudoVFWMUL_VFPR16_M2_MASK, PseudoVFWMUL_VFPR16_M2, 0x3, false }, // 1077 |
1155 | | { PseudoVFWMUL_VFPR16_M4_MASK, PseudoVFWMUL_VFPR16_M4, 0x3, false }, // 1078 |
1156 | | { PseudoVFWMUL_VFPR16_MF2_MASK, PseudoVFWMUL_VFPR16_MF2, 0x3, false }, // 1079 |
1157 | | { PseudoVFWMUL_VFPR16_MF4_MASK, PseudoVFWMUL_VFPR16_MF4, 0x3, false }, // 1080 |
1158 | | { PseudoVFWMUL_VFPR32_M1_MASK, PseudoVFWMUL_VFPR32_M1, 0x3, false }, // 1081 |
1159 | | { PseudoVFWMUL_VFPR32_M2_MASK, PseudoVFWMUL_VFPR32_M2, 0x3, false }, // 1082 |
1160 | | { PseudoVFWMUL_VFPR32_M4_MASK, PseudoVFWMUL_VFPR32_M4, 0x3, false }, // 1083 |
1161 | | { PseudoVFWMUL_VFPR32_MF2_MASK, PseudoVFWMUL_VFPR32_MF2, 0x3, false }, // 1084 |
1162 | | { PseudoVFWMUL_VV_M1_MASK, PseudoVFWMUL_VV_M1, 0x3, false }, // 1085 |
1163 | | { PseudoVFWMUL_VV_M2_MASK, PseudoVFWMUL_VV_M2, 0x3, false }, // 1086 |
1164 | | { PseudoVFWMUL_VV_M4_MASK, PseudoVFWMUL_VV_M4, 0x3, false }, // 1087 |
1165 | | { PseudoVFWMUL_VV_MF2_MASK, PseudoVFWMUL_VV_MF2, 0x3, false }, // 1088 |
1166 | | { PseudoVFWMUL_VV_MF4_MASK, PseudoVFWMUL_VV_MF4, 0x3, false }, // 1089 |
1167 | | { PseudoVFWNMACC_VFPR16_M1_MASK, PseudoVFWNMACC_VFPR16_M1, 0x3, false }, // 1090 |
1168 | | { PseudoVFWNMACC_VFPR16_M2_MASK, PseudoVFWNMACC_VFPR16_M2, 0x3, false }, // 1091 |
1169 | | { PseudoVFWNMACC_VFPR16_M4_MASK, PseudoVFWNMACC_VFPR16_M4, 0x3, false }, // 1092 |
1170 | | { PseudoVFWNMACC_VFPR16_MF2_MASK, PseudoVFWNMACC_VFPR16_MF2, 0x3, false }, // 1093 |
1171 | | { PseudoVFWNMACC_VFPR16_MF4_MASK, PseudoVFWNMACC_VFPR16_MF4, 0x3, false }, // 1094 |
1172 | | { PseudoVFWNMACC_VFPR32_M1_MASK, PseudoVFWNMACC_VFPR32_M1, 0x3, false }, // 1095 |
1173 | | { PseudoVFWNMACC_VFPR32_M2_MASK, PseudoVFWNMACC_VFPR32_M2, 0x3, false }, // 1096 |
1174 | | { PseudoVFWNMACC_VFPR32_M4_MASK, PseudoVFWNMACC_VFPR32_M4, 0x3, false }, // 1097 |
1175 | | { PseudoVFWNMACC_VFPR32_MF2_MASK, PseudoVFWNMACC_VFPR32_MF2, 0x3, false }, // 1098 |
1176 | | { PseudoVFWNMACC_VV_M1_MASK, PseudoVFWNMACC_VV_M1, 0x3, false }, // 1099 |
1177 | | { PseudoVFWNMACC_VV_M2_MASK, PseudoVFWNMACC_VV_M2, 0x3, false }, // 1100 |
1178 | | { PseudoVFWNMACC_VV_M4_MASK, PseudoVFWNMACC_VV_M4, 0x3, false }, // 1101 |
1179 | | { PseudoVFWNMACC_VV_MF2_MASK, PseudoVFWNMACC_VV_MF2, 0x3, false }, // 1102 |
1180 | | { PseudoVFWNMACC_VV_MF4_MASK, PseudoVFWNMACC_VV_MF4, 0x3, false }, // 1103 |
1181 | | { PseudoVFWNMSAC_VFPR16_M1_MASK, PseudoVFWNMSAC_VFPR16_M1, 0x3, false }, // 1104 |
1182 | | { PseudoVFWNMSAC_VFPR16_M2_MASK, PseudoVFWNMSAC_VFPR16_M2, 0x3, false }, // 1105 |
1183 | | { PseudoVFWNMSAC_VFPR16_M4_MASK, PseudoVFWNMSAC_VFPR16_M4, 0x3, false }, // 1106 |
1184 | | { PseudoVFWNMSAC_VFPR16_MF2_MASK, PseudoVFWNMSAC_VFPR16_MF2, 0x3, false }, // 1107 |
1185 | | { PseudoVFWNMSAC_VFPR16_MF4_MASK, PseudoVFWNMSAC_VFPR16_MF4, 0x3, false }, // 1108 |
1186 | | { PseudoVFWNMSAC_VFPR32_M1_MASK, PseudoVFWNMSAC_VFPR32_M1, 0x3, false }, // 1109 |
1187 | | { PseudoVFWNMSAC_VFPR32_M2_MASK, PseudoVFWNMSAC_VFPR32_M2, 0x3, false }, // 1110 |
1188 | | { PseudoVFWNMSAC_VFPR32_M4_MASK, PseudoVFWNMSAC_VFPR32_M4, 0x3, false }, // 1111 |
1189 | | { PseudoVFWNMSAC_VFPR32_MF2_MASK, PseudoVFWNMSAC_VFPR32_MF2, 0x3, false }, // 1112 |
1190 | | { PseudoVFWNMSAC_VV_M1_MASK, PseudoVFWNMSAC_VV_M1, 0x3, false }, // 1113 |
1191 | | { PseudoVFWNMSAC_VV_M2_MASK, PseudoVFWNMSAC_VV_M2, 0x3, false }, // 1114 |
1192 | | { PseudoVFWNMSAC_VV_M4_MASK, PseudoVFWNMSAC_VV_M4, 0x3, false }, // 1115 |
1193 | | { PseudoVFWNMSAC_VV_MF2_MASK, PseudoVFWNMSAC_VV_MF2, 0x3, false }, // 1116 |
1194 | | { PseudoVFWNMSAC_VV_MF4_MASK, PseudoVFWNMSAC_VV_MF4, 0x3, false }, // 1117 |
1195 | | { PseudoVFWREDOSUM_VS_M1_E16_MASK, PseudoVFWREDOSUM_VS_M1_E16, 0x3, true }, // 1118 |
1196 | | { PseudoVFWREDOSUM_VS_M1_E32_MASK, PseudoVFWREDOSUM_VS_M1_E32, 0x3, true }, // 1119 |
1197 | | { PseudoVFWREDOSUM_VS_M2_E16_MASK, PseudoVFWREDOSUM_VS_M2_E16, 0x3, true }, // 1120 |
1198 | | { PseudoVFWREDOSUM_VS_M2_E32_MASK, PseudoVFWREDOSUM_VS_M2_E32, 0x3, true }, // 1121 |
1199 | | { PseudoVFWREDOSUM_VS_M4_E16_MASK, PseudoVFWREDOSUM_VS_M4_E16, 0x3, true }, // 1122 |
1200 | | { PseudoVFWREDOSUM_VS_M4_E32_MASK, PseudoVFWREDOSUM_VS_M4_E32, 0x3, true }, // 1123 |
1201 | | { PseudoVFWREDOSUM_VS_M8_E16_MASK, PseudoVFWREDOSUM_VS_M8_E16, 0x3, true }, // 1124 |
1202 | | { PseudoVFWREDOSUM_VS_M8_E32_MASK, PseudoVFWREDOSUM_VS_M8_E32, 0x3, true }, // 1125 |
1203 | | { PseudoVFWREDOSUM_VS_MF2_E16_MASK, PseudoVFWREDOSUM_VS_MF2_E16, 0x3, true }, // 1126 |
1204 | | { PseudoVFWREDOSUM_VS_MF2_E32_MASK, PseudoVFWREDOSUM_VS_MF2_E32, 0x3, true }, // 1127 |
1205 | | { PseudoVFWREDOSUM_VS_MF4_E16_MASK, PseudoVFWREDOSUM_VS_MF4_E16, 0x3, true }, // 1128 |
1206 | | { PseudoVFWREDUSUM_VS_M1_E16_MASK, PseudoVFWREDUSUM_VS_M1_E16, 0x3, true }, // 1129 |
1207 | | { PseudoVFWREDUSUM_VS_M1_E32_MASK, PseudoVFWREDUSUM_VS_M1_E32, 0x3, true }, // 1130 |
1208 | | { PseudoVFWREDUSUM_VS_M2_E16_MASK, PseudoVFWREDUSUM_VS_M2_E16, 0x3, true }, // 1131 |
1209 | | { PseudoVFWREDUSUM_VS_M2_E32_MASK, PseudoVFWREDUSUM_VS_M2_E32, 0x3, true }, // 1132 |
1210 | | { PseudoVFWREDUSUM_VS_M4_E16_MASK, PseudoVFWREDUSUM_VS_M4_E16, 0x3, true }, // 1133 |
1211 | | { PseudoVFWREDUSUM_VS_M4_E32_MASK, PseudoVFWREDUSUM_VS_M4_E32, 0x3, true }, // 1134 |
1212 | | { PseudoVFWREDUSUM_VS_M8_E16_MASK, PseudoVFWREDUSUM_VS_M8_E16, 0x3, true }, // 1135 |
1213 | | { PseudoVFWREDUSUM_VS_M8_E32_MASK, PseudoVFWREDUSUM_VS_M8_E32, 0x3, true }, // 1136 |
1214 | | { PseudoVFWREDUSUM_VS_MF2_E16_MASK, PseudoVFWREDUSUM_VS_MF2_E16, 0x3, true }, // 1137 |
1215 | | { PseudoVFWREDUSUM_VS_MF2_E32_MASK, PseudoVFWREDUSUM_VS_MF2_E32, 0x3, true }, // 1138 |
1216 | | { PseudoVFWREDUSUM_VS_MF4_E16_MASK, PseudoVFWREDUSUM_VS_MF4_E16, 0x3, true }, // 1139 |
1217 | | { PseudoVFWSUB_VFPR16_M1_MASK, PseudoVFWSUB_VFPR16_M1, 0x3, false }, // 1140 |
1218 | | { PseudoVFWSUB_VFPR16_M2_MASK, PseudoVFWSUB_VFPR16_M2, 0x3, false }, // 1141 |
1219 | | { PseudoVFWSUB_VFPR16_M4_MASK, PseudoVFWSUB_VFPR16_M4, 0x3, false }, // 1142 |
1220 | | { PseudoVFWSUB_VFPR16_MF2_MASK, PseudoVFWSUB_VFPR16_MF2, 0x3, false }, // 1143 |
1221 | | { PseudoVFWSUB_VFPR16_MF4_MASK, PseudoVFWSUB_VFPR16_MF4, 0x3, false }, // 1144 |
1222 | | { PseudoVFWSUB_VFPR32_M1_MASK, PseudoVFWSUB_VFPR32_M1, 0x3, false }, // 1145 |
1223 | | { PseudoVFWSUB_VFPR32_M2_MASK, PseudoVFWSUB_VFPR32_M2, 0x3, false }, // 1146 |
1224 | | { PseudoVFWSUB_VFPR32_M4_MASK, PseudoVFWSUB_VFPR32_M4, 0x3, false }, // 1147 |
1225 | | { PseudoVFWSUB_VFPR32_MF2_MASK, PseudoVFWSUB_VFPR32_MF2, 0x3, false }, // 1148 |
1226 | | { PseudoVFWSUB_VV_M1_MASK, PseudoVFWSUB_VV_M1, 0x3, false }, // 1149 |
1227 | | { PseudoVFWSUB_VV_M2_MASK, PseudoVFWSUB_VV_M2, 0x3, false }, // 1150 |
1228 | | { PseudoVFWSUB_VV_M4_MASK, PseudoVFWSUB_VV_M4, 0x3, false }, // 1151 |
1229 | | { PseudoVFWSUB_VV_MF2_MASK, PseudoVFWSUB_VV_MF2, 0x3, false }, // 1152 |
1230 | | { PseudoVFWSUB_VV_MF4_MASK, PseudoVFWSUB_VV_MF4, 0x3, false }, // 1153 |
1231 | | { PseudoVFWSUB_WFPR16_M1_MASK, PseudoVFWSUB_WFPR16_M1, 0x3, false }, // 1154 |
1232 | | { PseudoVFWSUB_WFPR16_M2_MASK, PseudoVFWSUB_WFPR16_M2, 0x3, false }, // 1155 |
1233 | | { PseudoVFWSUB_WFPR16_M4_MASK, PseudoVFWSUB_WFPR16_M4, 0x3, false }, // 1156 |
1234 | | { PseudoVFWSUB_WFPR16_MF2_MASK, PseudoVFWSUB_WFPR16_MF2, 0x3, false }, // 1157 |
1235 | | { PseudoVFWSUB_WFPR16_MF4_MASK, PseudoVFWSUB_WFPR16_MF4, 0x3, false }, // 1158 |
1236 | | { PseudoVFWSUB_WFPR32_M1_MASK, PseudoVFWSUB_WFPR32_M1, 0x3, false }, // 1159 |
1237 | | { PseudoVFWSUB_WFPR32_M2_MASK, PseudoVFWSUB_WFPR32_M2, 0x3, false }, // 1160 |
1238 | | { PseudoVFWSUB_WFPR32_M4_MASK, PseudoVFWSUB_WFPR32_M4, 0x3, false }, // 1161 |
1239 | | { PseudoVFWSUB_WFPR32_MF2_MASK, PseudoVFWSUB_WFPR32_MF2, 0x3, false }, // 1162 |
1240 | | { PseudoVFWSUB_WV_M1_MASK, PseudoVFWSUB_WV_M1, 0x3, false }, // 1163 |
1241 | | { PseudoVFWSUB_WV_M2_MASK, PseudoVFWSUB_WV_M2, 0x3, false }, // 1164 |
1242 | | { PseudoVFWSUB_WV_M4_MASK, PseudoVFWSUB_WV_M4, 0x3, false }, // 1165 |
1243 | | { PseudoVFWSUB_WV_MF2_MASK, PseudoVFWSUB_WV_MF2, 0x3, false }, // 1166 |
1244 | | { PseudoVFWSUB_WV_MF4_MASK, PseudoVFWSUB_WV_MF4, 0x3, false }, // 1167 |
1245 | | { PseudoVID_V_M1_MASK, PseudoVID_V_M1, 0x1, false }, // 1168 |
1246 | | { PseudoVID_V_M2_MASK, PseudoVID_V_M2, 0x1, false }, // 1169 |
1247 | | { PseudoVID_V_M4_MASK, PseudoVID_V_M4, 0x1, false }, // 1170 |
1248 | | { PseudoVID_V_M8_MASK, PseudoVID_V_M8, 0x1, false }, // 1171 |
1249 | | { PseudoVID_V_MF2_MASK, PseudoVID_V_MF2, 0x1, false }, // 1172 |
1250 | | { PseudoVID_V_MF4_MASK, PseudoVID_V_MF4, 0x1, false }, // 1173 |
1251 | | { PseudoVID_V_MF8_MASK, PseudoVID_V_MF8, 0x1, false }, // 1174 |
1252 | | { PseudoVIOTA_M_M1_MASK, PseudoVIOTA_M_M1, 0x2, true }, // 1175 |
1253 | | { PseudoVIOTA_M_M2_MASK, PseudoVIOTA_M_M2, 0x2, true }, // 1176 |
1254 | | { PseudoVIOTA_M_M4_MASK, PseudoVIOTA_M_M4, 0x2, true }, // 1177 |
1255 | | { PseudoVIOTA_M_M8_MASK, PseudoVIOTA_M_M8, 0x2, true }, // 1178 |
1256 | | { PseudoVIOTA_M_MF2_MASK, PseudoVIOTA_M_MF2, 0x2, true }, // 1179 |
1257 | | { PseudoVIOTA_M_MF4_MASK, PseudoVIOTA_M_MF4, 0x2, true }, // 1180 |
1258 | | { PseudoVIOTA_M_MF8_MASK, PseudoVIOTA_M_MF8, 0x2, true }, // 1181 |
1259 | | { PseudoVLE16FF_V_M1_MASK, PseudoVLE16FF_V_M1, 0x2, false }, // 1182 |
1260 | | { PseudoVLE16FF_V_M2_MASK, PseudoVLE16FF_V_M2, 0x2, false }, // 1183 |
1261 | | { PseudoVLE16FF_V_M4_MASK, PseudoVLE16FF_V_M4, 0x2, false }, // 1184 |
1262 | | { PseudoVLE16FF_V_M8_MASK, PseudoVLE16FF_V_M8, 0x2, false }, // 1185 |
1263 | | { PseudoVLE16FF_V_MF2_MASK, PseudoVLE16FF_V_MF2, 0x2, false }, // 1186 |
1264 | | { PseudoVLE16FF_V_MF4_MASK, PseudoVLE16FF_V_MF4, 0x2, false }, // 1187 |
1265 | | { PseudoVLE16_V_M1_MASK, PseudoVLE16_V_M1, 0x2, false }, // 1188 |
1266 | | { PseudoVLE16_V_M2_MASK, PseudoVLE16_V_M2, 0x2, false }, // 1189 |
1267 | | { PseudoVLE16_V_M4_MASK, PseudoVLE16_V_M4, 0x2, false }, // 1190 |
1268 | | { PseudoVLE16_V_M8_MASK, PseudoVLE16_V_M8, 0x2, false }, // 1191 |
1269 | | { PseudoVLE16_V_MF2_MASK, PseudoVLE16_V_MF2, 0x2, false }, // 1192 |
1270 | | { PseudoVLE16_V_MF4_MASK, PseudoVLE16_V_MF4, 0x2, false }, // 1193 |
1271 | | { PseudoVLE32FF_V_M1_MASK, PseudoVLE32FF_V_M1, 0x2, false }, // 1194 |
1272 | | { PseudoVLE32FF_V_M2_MASK, PseudoVLE32FF_V_M2, 0x2, false }, // 1195 |
1273 | | { PseudoVLE32FF_V_M4_MASK, PseudoVLE32FF_V_M4, 0x2, false }, // 1196 |
1274 | | { PseudoVLE32FF_V_M8_MASK, PseudoVLE32FF_V_M8, 0x2, false }, // 1197 |
1275 | | { PseudoVLE32FF_V_MF2_MASK, PseudoVLE32FF_V_MF2, 0x2, false }, // 1198 |
1276 | | { PseudoVLE32_V_M1_MASK, PseudoVLE32_V_M1, 0x2, false }, // 1199 |
1277 | | { PseudoVLE32_V_M2_MASK, PseudoVLE32_V_M2, 0x2, false }, // 1200 |
1278 | | { PseudoVLE32_V_M4_MASK, PseudoVLE32_V_M4, 0x2, false }, // 1201 |
1279 | | { PseudoVLE32_V_M8_MASK, PseudoVLE32_V_M8, 0x2, false }, // 1202 |
1280 | | { PseudoVLE32_V_MF2_MASK, PseudoVLE32_V_MF2, 0x2, false }, // 1203 |
1281 | | { PseudoVLE64FF_V_M1_MASK, PseudoVLE64FF_V_M1, 0x2, false }, // 1204 |
1282 | | { PseudoVLE64FF_V_M2_MASK, PseudoVLE64FF_V_M2, 0x2, false }, // 1205 |
1283 | | { PseudoVLE64FF_V_M4_MASK, PseudoVLE64FF_V_M4, 0x2, false }, // 1206 |
1284 | | { PseudoVLE64FF_V_M8_MASK, PseudoVLE64FF_V_M8, 0x2, false }, // 1207 |
1285 | | { PseudoVLE64_V_M1_MASK, PseudoVLE64_V_M1, 0x2, false }, // 1208 |
1286 | | { PseudoVLE64_V_M2_MASK, PseudoVLE64_V_M2, 0x2, false }, // 1209 |
1287 | | { PseudoVLE64_V_M4_MASK, PseudoVLE64_V_M4, 0x2, false }, // 1210 |
1288 | | { PseudoVLE64_V_M8_MASK, PseudoVLE64_V_M8, 0x2, false }, // 1211 |
1289 | | { PseudoVLE8FF_V_M1_MASK, PseudoVLE8FF_V_M1, 0x2, false }, // 1212 |
1290 | | { PseudoVLE8FF_V_M2_MASK, PseudoVLE8FF_V_M2, 0x2, false }, // 1213 |
1291 | | { PseudoVLE8FF_V_M4_MASK, PseudoVLE8FF_V_M4, 0x2, false }, // 1214 |
1292 | | { PseudoVLE8FF_V_M8_MASK, PseudoVLE8FF_V_M8, 0x2, false }, // 1215 |
1293 | | { PseudoVLE8FF_V_MF2_MASK, PseudoVLE8FF_V_MF2, 0x2, false }, // 1216 |
1294 | | { PseudoVLE8FF_V_MF4_MASK, PseudoVLE8FF_V_MF4, 0x2, false }, // 1217 |
1295 | | { PseudoVLE8FF_V_MF8_MASK, PseudoVLE8FF_V_MF8, 0x2, false }, // 1218 |
1296 | | { PseudoVLE8_V_M1_MASK, PseudoVLE8_V_M1, 0x2, false }, // 1219 |
1297 | | { PseudoVLE8_V_M2_MASK, PseudoVLE8_V_M2, 0x2, false }, // 1220 |
1298 | | { PseudoVLE8_V_M4_MASK, PseudoVLE8_V_M4, 0x2, false }, // 1221 |
1299 | | { PseudoVLE8_V_M8_MASK, PseudoVLE8_V_M8, 0x2, false }, // 1222 |
1300 | | { PseudoVLE8_V_MF2_MASK, PseudoVLE8_V_MF2, 0x2, false }, // 1223 |
1301 | | { PseudoVLE8_V_MF4_MASK, PseudoVLE8_V_MF4, 0x2, false }, // 1224 |
1302 | | { PseudoVLE8_V_MF8_MASK, PseudoVLE8_V_MF8, 0x2, false }, // 1225 |
1303 | | { PseudoVLOXEI16_V_M1_M1_MASK, PseudoVLOXEI16_V_M1_M1, 0x3, false }, // 1226 |
1304 | | { PseudoVLOXEI16_V_M1_M2_MASK, PseudoVLOXEI16_V_M1_M2, 0x3, false }, // 1227 |
1305 | | { PseudoVLOXEI16_V_M1_M4_MASK, PseudoVLOXEI16_V_M1_M4, 0x3, false }, // 1228 |
1306 | | { PseudoVLOXEI16_V_M1_MF2_MASK, PseudoVLOXEI16_V_M1_MF2, 0x3, false }, // 1229 |
1307 | | { PseudoVLOXEI16_V_M2_M1_MASK, PseudoVLOXEI16_V_M2_M1, 0x3, false }, // 1230 |
1308 | | { PseudoVLOXEI16_V_M2_M2_MASK, PseudoVLOXEI16_V_M2_M2, 0x3, false }, // 1231 |
1309 | | { PseudoVLOXEI16_V_M2_M4_MASK, PseudoVLOXEI16_V_M2_M4, 0x3, false }, // 1232 |
1310 | | { PseudoVLOXEI16_V_M2_M8_MASK, PseudoVLOXEI16_V_M2_M8, 0x3, false }, // 1233 |
1311 | | { PseudoVLOXEI16_V_M4_M2_MASK, PseudoVLOXEI16_V_M4_M2, 0x3, false }, // 1234 |
1312 | | { PseudoVLOXEI16_V_M4_M4_MASK, PseudoVLOXEI16_V_M4_M4, 0x3, false }, // 1235 |
1313 | | { PseudoVLOXEI16_V_M4_M8_MASK, PseudoVLOXEI16_V_M4_M8, 0x3, false }, // 1236 |
1314 | | { PseudoVLOXEI16_V_M8_M4_MASK, PseudoVLOXEI16_V_M8_M4, 0x3, false }, // 1237 |
1315 | | { PseudoVLOXEI16_V_M8_M8_MASK, PseudoVLOXEI16_V_M8_M8, 0x3, false }, // 1238 |
1316 | | { PseudoVLOXEI16_V_MF2_M1_MASK, PseudoVLOXEI16_V_MF2_M1, 0x3, false }, // 1239 |
1317 | | { PseudoVLOXEI16_V_MF2_M2_MASK, PseudoVLOXEI16_V_MF2_M2, 0x3, false }, // 1240 |
1318 | | { PseudoVLOXEI16_V_MF2_MF2_MASK, PseudoVLOXEI16_V_MF2_MF2, 0x3, false }, // 1241 |
1319 | | { PseudoVLOXEI16_V_MF2_MF4_MASK, PseudoVLOXEI16_V_MF2_MF4, 0x3, false }, // 1242 |
1320 | | { PseudoVLOXEI16_V_MF4_M1_MASK, PseudoVLOXEI16_V_MF4_M1, 0x3, false }, // 1243 |
1321 | | { PseudoVLOXEI16_V_MF4_MF2_MASK, PseudoVLOXEI16_V_MF4_MF2, 0x3, false }, // 1244 |
1322 | | { PseudoVLOXEI16_V_MF4_MF4_MASK, PseudoVLOXEI16_V_MF4_MF4, 0x3, false }, // 1245 |
1323 | | { PseudoVLOXEI16_V_MF4_MF8_MASK, PseudoVLOXEI16_V_MF4_MF8, 0x3, false }, // 1246 |
1324 | | { PseudoVLOXEI32_V_M1_M1_MASK, PseudoVLOXEI32_V_M1_M1, 0x3, false }, // 1247 |
1325 | | { PseudoVLOXEI32_V_M1_M2_MASK, PseudoVLOXEI32_V_M1_M2, 0x3, false }, // 1248 |
1326 | | { PseudoVLOXEI32_V_M1_MF2_MASK, PseudoVLOXEI32_V_M1_MF2, 0x3, false }, // 1249 |
1327 | | { PseudoVLOXEI32_V_M1_MF4_MASK, PseudoVLOXEI32_V_M1_MF4, 0x3, false }, // 1250 |
1328 | | { PseudoVLOXEI32_V_M2_M1_MASK, PseudoVLOXEI32_V_M2_M1, 0x3, false }, // 1251 |
1329 | | { PseudoVLOXEI32_V_M2_M2_MASK, PseudoVLOXEI32_V_M2_M2, 0x3, false }, // 1252 |
1330 | | { PseudoVLOXEI32_V_M2_M4_MASK, PseudoVLOXEI32_V_M2_M4, 0x3, false }, // 1253 |
1331 | | { PseudoVLOXEI32_V_M2_MF2_MASK, PseudoVLOXEI32_V_M2_MF2, 0x3, false }, // 1254 |
1332 | | { PseudoVLOXEI32_V_M4_M1_MASK, PseudoVLOXEI32_V_M4_M1, 0x3, false }, // 1255 |
1333 | | { PseudoVLOXEI32_V_M4_M2_MASK, PseudoVLOXEI32_V_M4_M2, 0x3, false }, // 1256 |
1334 | | { PseudoVLOXEI32_V_M4_M4_MASK, PseudoVLOXEI32_V_M4_M4, 0x3, false }, // 1257 |
1335 | | { PseudoVLOXEI32_V_M4_M8_MASK, PseudoVLOXEI32_V_M4_M8, 0x3, false }, // 1258 |
1336 | | { PseudoVLOXEI32_V_M8_M2_MASK, PseudoVLOXEI32_V_M8_M2, 0x3, false }, // 1259 |
1337 | | { PseudoVLOXEI32_V_M8_M4_MASK, PseudoVLOXEI32_V_M8_M4, 0x3, false }, // 1260 |
1338 | | { PseudoVLOXEI32_V_M8_M8_MASK, PseudoVLOXEI32_V_M8_M8, 0x3, false }, // 1261 |
1339 | | { PseudoVLOXEI32_V_MF2_M1_MASK, PseudoVLOXEI32_V_MF2_M1, 0x3, false }, // 1262 |
1340 | | { PseudoVLOXEI32_V_MF2_MF2_MASK, PseudoVLOXEI32_V_MF2_MF2, 0x3, false }, // 1263 |
1341 | | { PseudoVLOXEI32_V_MF2_MF4_MASK, PseudoVLOXEI32_V_MF2_MF4, 0x3, false }, // 1264 |
1342 | | { PseudoVLOXEI32_V_MF2_MF8_MASK, PseudoVLOXEI32_V_MF2_MF8, 0x3, false }, // 1265 |
1343 | | { PseudoVLOXEI64_V_M1_M1_MASK, PseudoVLOXEI64_V_M1_M1, 0x3, false }, // 1266 |
1344 | | { PseudoVLOXEI64_V_M1_MF2_MASK, PseudoVLOXEI64_V_M1_MF2, 0x3, false }, // 1267 |
1345 | | { PseudoVLOXEI64_V_M1_MF4_MASK, PseudoVLOXEI64_V_M1_MF4, 0x3, false }, // 1268 |
1346 | | { PseudoVLOXEI64_V_M1_MF8_MASK, PseudoVLOXEI64_V_M1_MF8, 0x3, false }, // 1269 |
1347 | | { PseudoVLOXEI64_V_M2_M1_MASK, PseudoVLOXEI64_V_M2_M1, 0x3, false }, // 1270 |
1348 | | { PseudoVLOXEI64_V_M2_M2_MASK, PseudoVLOXEI64_V_M2_M2, 0x3, false }, // 1271 |
1349 | | { PseudoVLOXEI64_V_M2_MF2_MASK, PseudoVLOXEI64_V_M2_MF2, 0x3, false }, // 1272 |
1350 | | { PseudoVLOXEI64_V_M2_MF4_MASK, PseudoVLOXEI64_V_M2_MF4, 0x3, false }, // 1273 |
1351 | | { PseudoVLOXEI64_V_M4_M1_MASK, PseudoVLOXEI64_V_M4_M1, 0x3, false }, // 1274 |
1352 | | { PseudoVLOXEI64_V_M4_M2_MASK, PseudoVLOXEI64_V_M4_M2, 0x3, false }, // 1275 |
1353 | | { PseudoVLOXEI64_V_M4_M4_MASK, PseudoVLOXEI64_V_M4_M4, 0x3, false }, // 1276 |
1354 | | { PseudoVLOXEI64_V_M4_MF2_MASK, PseudoVLOXEI64_V_M4_MF2, 0x3, false }, // 1277 |
1355 | | { PseudoVLOXEI64_V_M8_M1_MASK, PseudoVLOXEI64_V_M8_M1, 0x3, false }, // 1278 |
1356 | | { PseudoVLOXEI64_V_M8_M2_MASK, PseudoVLOXEI64_V_M8_M2, 0x3, false }, // 1279 |
1357 | | { PseudoVLOXEI64_V_M8_M4_MASK, PseudoVLOXEI64_V_M8_M4, 0x3, false }, // 1280 |
1358 | | { PseudoVLOXEI64_V_M8_M8_MASK, PseudoVLOXEI64_V_M8_M8, 0x3, false }, // 1281 |
1359 | | { PseudoVLOXEI8_V_M1_M1_MASK, PseudoVLOXEI8_V_M1_M1, 0x3, false }, // 1282 |
1360 | | { PseudoVLOXEI8_V_M1_M2_MASK, PseudoVLOXEI8_V_M1_M2, 0x3, false }, // 1283 |
1361 | | { PseudoVLOXEI8_V_M1_M4_MASK, PseudoVLOXEI8_V_M1_M4, 0x3, false }, // 1284 |
1362 | | { PseudoVLOXEI8_V_M1_M8_MASK, PseudoVLOXEI8_V_M1_M8, 0x3, false }, // 1285 |
1363 | | { PseudoVLOXEI8_V_M2_M2_MASK, PseudoVLOXEI8_V_M2_M2, 0x3, false }, // 1286 |
1364 | | { PseudoVLOXEI8_V_M2_M4_MASK, PseudoVLOXEI8_V_M2_M4, 0x3, false }, // 1287 |
1365 | | { PseudoVLOXEI8_V_M2_M8_MASK, PseudoVLOXEI8_V_M2_M8, 0x3, false }, // 1288 |
1366 | | { PseudoVLOXEI8_V_M4_M4_MASK, PseudoVLOXEI8_V_M4_M4, 0x3, false }, // 1289 |
1367 | | { PseudoVLOXEI8_V_M4_M8_MASK, PseudoVLOXEI8_V_M4_M8, 0x3, false }, // 1290 |
1368 | | { PseudoVLOXEI8_V_M8_M8_MASK, PseudoVLOXEI8_V_M8_M8, 0x3, false }, // 1291 |
1369 | | { PseudoVLOXEI8_V_MF2_M1_MASK, PseudoVLOXEI8_V_MF2_M1, 0x3, false }, // 1292 |
1370 | | { PseudoVLOXEI8_V_MF2_M2_MASK, PseudoVLOXEI8_V_MF2_M2, 0x3, false }, // 1293 |
1371 | | { PseudoVLOXEI8_V_MF2_M4_MASK, PseudoVLOXEI8_V_MF2_M4, 0x3, false }, // 1294 |
1372 | | { PseudoVLOXEI8_V_MF2_MF2_MASK, PseudoVLOXEI8_V_MF2_MF2, 0x3, false }, // 1295 |
1373 | | { PseudoVLOXEI8_V_MF4_M1_MASK, PseudoVLOXEI8_V_MF4_M1, 0x3, false }, // 1296 |
1374 | | { PseudoVLOXEI8_V_MF4_M2_MASK, PseudoVLOXEI8_V_MF4_M2, 0x3, false }, // 1297 |
1375 | | { PseudoVLOXEI8_V_MF4_MF2_MASK, PseudoVLOXEI8_V_MF4_MF2, 0x3, false }, // 1298 |
1376 | | { PseudoVLOXEI8_V_MF4_MF4_MASK, PseudoVLOXEI8_V_MF4_MF4, 0x3, false }, // 1299 |
1377 | | { PseudoVLOXEI8_V_MF8_M1_MASK, PseudoVLOXEI8_V_MF8_M1, 0x3, false }, // 1300 |
1378 | | { PseudoVLOXEI8_V_MF8_MF2_MASK, PseudoVLOXEI8_V_MF8_MF2, 0x3, false }, // 1301 |
1379 | | { PseudoVLOXEI8_V_MF8_MF4_MASK, PseudoVLOXEI8_V_MF8_MF4, 0x3, false }, // 1302 |
1380 | | { PseudoVLOXEI8_V_MF8_MF8_MASK, PseudoVLOXEI8_V_MF8_MF8, 0x3, false }, // 1303 |
1381 | | { PseudoVLSE16_V_M1_MASK, PseudoVLSE16_V_M1, 0x3, false }, // 1304 |
1382 | | { PseudoVLSE16_V_M2_MASK, PseudoVLSE16_V_M2, 0x3, false }, // 1305 |
1383 | | { PseudoVLSE16_V_M4_MASK, PseudoVLSE16_V_M4, 0x3, false }, // 1306 |
1384 | | { PseudoVLSE16_V_M8_MASK, PseudoVLSE16_V_M8, 0x3, false }, // 1307 |
1385 | | { PseudoVLSE16_V_MF2_MASK, PseudoVLSE16_V_MF2, 0x3, false }, // 1308 |
1386 | | { PseudoVLSE16_V_MF4_MASK, PseudoVLSE16_V_MF4, 0x3, false }, // 1309 |
1387 | | { PseudoVLSE32_V_M1_MASK, PseudoVLSE32_V_M1, 0x3, false }, // 1310 |
1388 | | { PseudoVLSE32_V_M2_MASK, PseudoVLSE32_V_M2, 0x3, false }, // 1311 |
1389 | | { PseudoVLSE32_V_M4_MASK, PseudoVLSE32_V_M4, 0x3, false }, // 1312 |
1390 | | { PseudoVLSE32_V_M8_MASK, PseudoVLSE32_V_M8, 0x3, false }, // 1313 |
1391 | | { PseudoVLSE32_V_MF2_MASK, PseudoVLSE32_V_MF2, 0x3, false }, // 1314 |
1392 | | { PseudoVLSE64_V_M1_MASK, PseudoVLSE64_V_M1, 0x3, false }, // 1315 |
1393 | | { PseudoVLSE64_V_M2_MASK, PseudoVLSE64_V_M2, 0x3, false }, // 1316 |
1394 | | { PseudoVLSE64_V_M4_MASK, PseudoVLSE64_V_M4, 0x3, false }, // 1317 |
1395 | | { PseudoVLSE64_V_M8_MASK, PseudoVLSE64_V_M8, 0x3, false }, // 1318 |
1396 | | { PseudoVLSE8_V_M1_MASK, PseudoVLSE8_V_M1, 0x3, false }, // 1319 |
1397 | | { PseudoVLSE8_V_M2_MASK, PseudoVLSE8_V_M2, 0x3, false }, // 1320 |
1398 | | { PseudoVLSE8_V_M4_MASK, PseudoVLSE8_V_M4, 0x3, false }, // 1321 |
1399 | | { PseudoVLSE8_V_M8_MASK, PseudoVLSE8_V_M8, 0x3, false }, // 1322 |
1400 | | { PseudoVLSE8_V_MF2_MASK, PseudoVLSE8_V_MF2, 0x3, false }, // 1323 |
1401 | | { PseudoVLSE8_V_MF4_MASK, PseudoVLSE8_V_MF4, 0x3, false }, // 1324 |
1402 | | { PseudoVLSE8_V_MF8_MASK, PseudoVLSE8_V_MF8, 0x3, false }, // 1325 |
1403 | | { PseudoVLUXEI16_V_M1_M1_MASK, PseudoVLUXEI16_V_M1_M1, 0x3, false }, // 1326 |
1404 | | { PseudoVLUXEI16_V_M1_M2_MASK, PseudoVLUXEI16_V_M1_M2, 0x3, false }, // 1327 |
1405 | | { PseudoVLUXEI16_V_M1_M4_MASK, PseudoVLUXEI16_V_M1_M4, 0x3, false }, // 1328 |
1406 | | { PseudoVLUXEI16_V_M1_MF2_MASK, PseudoVLUXEI16_V_M1_MF2, 0x3, false }, // 1329 |
1407 | | { PseudoVLUXEI16_V_M2_M1_MASK, PseudoVLUXEI16_V_M2_M1, 0x3, false }, // 1330 |
1408 | | { PseudoVLUXEI16_V_M2_M2_MASK, PseudoVLUXEI16_V_M2_M2, 0x3, false }, // 1331 |
1409 | | { PseudoVLUXEI16_V_M2_M4_MASK, PseudoVLUXEI16_V_M2_M4, 0x3, false }, // 1332 |
1410 | | { PseudoVLUXEI16_V_M2_M8_MASK, PseudoVLUXEI16_V_M2_M8, 0x3, false }, // 1333 |
1411 | | { PseudoVLUXEI16_V_M4_M2_MASK, PseudoVLUXEI16_V_M4_M2, 0x3, false }, // 1334 |
1412 | | { PseudoVLUXEI16_V_M4_M4_MASK, PseudoVLUXEI16_V_M4_M4, 0x3, false }, // 1335 |
1413 | | { PseudoVLUXEI16_V_M4_M8_MASK, PseudoVLUXEI16_V_M4_M8, 0x3, false }, // 1336 |
1414 | | { PseudoVLUXEI16_V_M8_M4_MASK, PseudoVLUXEI16_V_M8_M4, 0x3, false }, // 1337 |
1415 | | { PseudoVLUXEI16_V_M8_M8_MASK, PseudoVLUXEI16_V_M8_M8, 0x3, false }, // 1338 |
1416 | | { PseudoVLUXEI16_V_MF2_M1_MASK, PseudoVLUXEI16_V_MF2_M1, 0x3, false }, // 1339 |
1417 | | { PseudoVLUXEI16_V_MF2_M2_MASK, PseudoVLUXEI16_V_MF2_M2, 0x3, false }, // 1340 |
1418 | | { PseudoVLUXEI16_V_MF2_MF2_MASK, PseudoVLUXEI16_V_MF2_MF2, 0x3, false }, // 1341 |
1419 | | { PseudoVLUXEI16_V_MF2_MF4_MASK, PseudoVLUXEI16_V_MF2_MF4, 0x3, false }, // 1342 |
1420 | | { PseudoVLUXEI16_V_MF4_M1_MASK, PseudoVLUXEI16_V_MF4_M1, 0x3, false }, // 1343 |
1421 | | { PseudoVLUXEI16_V_MF4_MF2_MASK, PseudoVLUXEI16_V_MF4_MF2, 0x3, false }, // 1344 |
1422 | | { PseudoVLUXEI16_V_MF4_MF4_MASK, PseudoVLUXEI16_V_MF4_MF4, 0x3, false }, // 1345 |
1423 | | { PseudoVLUXEI16_V_MF4_MF8_MASK, PseudoVLUXEI16_V_MF4_MF8, 0x3, false }, // 1346 |
1424 | | { PseudoVLUXEI32_V_M1_M1_MASK, PseudoVLUXEI32_V_M1_M1, 0x3, false }, // 1347 |
1425 | | { PseudoVLUXEI32_V_M1_M2_MASK, PseudoVLUXEI32_V_M1_M2, 0x3, false }, // 1348 |
1426 | | { PseudoVLUXEI32_V_M1_MF2_MASK, PseudoVLUXEI32_V_M1_MF2, 0x3, false }, // 1349 |
1427 | | { PseudoVLUXEI32_V_M1_MF4_MASK, PseudoVLUXEI32_V_M1_MF4, 0x3, false }, // 1350 |
1428 | | { PseudoVLUXEI32_V_M2_M1_MASK, PseudoVLUXEI32_V_M2_M1, 0x3, false }, // 1351 |
1429 | | { PseudoVLUXEI32_V_M2_M2_MASK, PseudoVLUXEI32_V_M2_M2, 0x3, false }, // 1352 |
1430 | | { PseudoVLUXEI32_V_M2_M4_MASK, PseudoVLUXEI32_V_M2_M4, 0x3, false }, // 1353 |
1431 | | { PseudoVLUXEI32_V_M2_MF2_MASK, PseudoVLUXEI32_V_M2_MF2, 0x3, false }, // 1354 |
1432 | | { PseudoVLUXEI32_V_M4_M1_MASK, PseudoVLUXEI32_V_M4_M1, 0x3, false }, // 1355 |
1433 | | { PseudoVLUXEI32_V_M4_M2_MASK, PseudoVLUXEI32_V_M4_M2, 0x3, false }, // 1356 |
1434 | | { PseudoVLUXEI32_V_M4_M4_MASK, PseudoVLUXEI32_V_M4_M4, 0x3, false }, // 1357 |
1435 | | { PseudoVLUXEI32_V_M4_M8_MASK, PseudoVLUXEI32_V_M4_M8, 0x3, false }, // 1358 |
1436 | | { PseudoVLUXEI32_V_M8_M2_MASK, PseudoVLUXEI32_V_M8_M2, 0x3, false }, // 1359 |
1437 | | { PseudoVLUXEI32_V_M8_M4_MASK, PseudoVLUXEI32_V_M8_M4, 0x3, false }, // 1360 |
1438 | | { PseudoVLUXEI32_V_M8_M8_MASK, PseudoVLUXEI32_V_M8_M8, 0x3, false }, // 1361 |
1439 | | { PseudoVLUXEI32_V_MF2_M1_MASK, PseudoVLUXEI32_V_MF2_M1, 0x3, false }, // 1362 |
1440 | | { PseudoVLUXEI32_V_MF2_MF2_MASK, PseudoVLUXEI32_V_MF2_MF2, 0x3, false }, // 1363 |
1441 | | { PseudoVLUXEI32_V_MF2_MF4_MASK, PseudoVLUXEI32_V_MF2_MF4, 0x3, false }, // 1364 |
1442 | | { PseudoVLUXEI32_V_MF2_MF8_MASK, PseudoVLUXEI32_V_MF2_MF8, 0x3, false }, // 1365 |
1443 | | { PseudoVLUXEI64_V_M1_M1_MASK, PseudoVLUXEI64_V_M1_M1, 0x3, false }, // 1366 |
1444 | | { PseudoVLUXEI64_V_M1_MF2_MASK, PseudoVLUXEI64_V_M1_MF2, 0x3, false }, // 1367 |
1445 | | { PseudoVLUXEI64_V_M1_MF4_MASK, PseudoVLUXEI64_V_M1_MF4, 0x3, false }, // 1368 |
1446 | | { PseudoVLUXEI64_V_M1_MF8_MASK, PseudoVLUXEI64_V_M1_MF8, 0x3, false }, // 1369 |
1447 | | { PseudoVLUXEI64_V_M2_M1_MASK, PseudoVLUXEI64_V_M2_M1, 0x3, false }, // 1370 |
1448 | | { PseudoVLUXEI64_V_M2_M2_MASK, PseudoVLUXEI64_V_M2_M2, 0x3, false }, // 1371 |
1449 | | { PseudoVLUXEI64_V_M2_MF2_MASK, PseudoVLUXEI64_V_M2_MF2, 0x3, false }, // 1372 |
1450 | | { PseudoVLUXEI64_V_M2_MF4_MASK, PseudoVLUXEI64_V_M2_MF4, 0x3, false }, // 1373 |
1451 | | { PseudoVLUXEI64_V_M4_M1_MASK, PseudoVLUXEI64_V_M4_M1, 0x3, false }, // 1374 |
1452 | | { PseudoVLUXEI64_V_M4_M2_MASK, PseudoVLUXEI64_V_M4_M2, 0x3, false }, // 1375 |
1453 | | { PseudoVLUXEI64_V_M4_M4_MASK, PseudoVLUXEI64_V_M4_M4, 0x3, false }, // 1376 |
1454 | | { PseudoVLUXEI64_V_M4_MF2_MASK, PseudoVLUXEI64_V_M4_MF2, 0x3, false }, // 1377 |
1455 | | { PseudoVLUXEI64_V_M8_M1_MASK, PseudoVLUXEI64_V_M8_M1, 0x3, false }, // 1378 |
1456 | | { PseudoVLUXEI64_V_M8_M2_MASK, PseudoVLUXEI64_V_M8_M2, 0x3, false }, // 1379 |
1457 | | { PseudoVLUXEI64_V_M8_M4_MASK, PseudoVLUXEI64_V_M8_M4, 0x3, false }, // 1380 |
1458 | | { PseudoVLUXEI64_V_M8_M8_MASK, PseudoVLUXEI64_V_M8_M8, 0x3, false }, // 1381 |
1459 | | { PseudoVLUXEI8_V_M1_M1_MASK, PseudoVLUXEI8_V_M1_M1, 0x3, false }, // 1382 |
1460 | | { PseudoVLUXEI8_V_M1_M2_MASK, PseudoVLUXEI8_V_M1_M2, 0x3, false }, // 1383 |
1461 | | { PseudoVLUXEI8_V_M1_M4_MASK, PseudoVLUXEI8_V_M1_M4, 0x3, false }, // 1384 |
1462 | | { PseudoVLUXEI8_V_M1_M8_MASK, PseudoVLUXEI8_V_M1_M8, 0x3, false }, // 1385 |
1463 | | { PseudoVLUXEI8_V_M2_M2_MASK, PseudoVLUXEI8_V_M2_M2, 0x3, false }, // 1386 |
1464 | | { PseudoVLUXEI8_V_M2_M4_MASK, PseudoVLUXEI8_V_M2_M4, 0x3, false }, // 1387 |
1465 | | { PseudoVLUXEI8_V_M2_M8_MASK, PseudoVLUXEI8_V_M2_M8, 0x3, false }, // 1388 |
1466 | | { PseudoVLUXEI8_V_M4_M4_MASK, PseudoVLUXEI8_V_M4_M4, 0x3, false }, // 1389 |
1467 | | { PseudoVLUXEI8_V_M4_M8_MASK, PseudoVLUXEI8_V_M4_M8, 0x3, false }, // 1390 |
1468 | | { PseudoVLUXEI8_V_M8_M8_MASK, PseudoVLUXEI8_V_M8_M8, 0x3, false }, // 1391 |
1469 | | { PseudoVLUXEI8_V_MF2_M1_MASK, PseudoVLUXEI8_V_MF2_M1, 0x3, false }, // 1392 |
1470 | | { PseudoVLUXEI8_V_MF2_M2_MASK, PseudoVLUXEI8_V_MF2_M2, 0x3, false }, // 1393 |
1471 | | { PseudoVLUXEI8_V_MF2_M4_MASK, PseudoVLUXEI8_V_MF2_M4, 0x3, false }, // 1394 |
1472 | | { PseudoVLUXEI8_V_MF2_MF2_MASK, PseudoVLUXEI8_V_MF2_MF2, 0x3, false }, // 1395 |
1473 | | { PseudoVLUXEI8_V_MF4_M1_MASK, PseudoVLUXEI8_V_MF4_M1, 0x3, false }, // 1396 |
1474 | | { PseudoVLUXEI8_V_MF4_M2_MASK, PseudoVLUXEI8_V_MF4_M2, 0x3, false }, // 1397 |
1475 | | { PseudoVLUXEI8_V_MF4_MF2_MASK, PseudoVLUXEI8_V_MF4_MF2, 0x3, false }, // 1398 |
1476 | | { PseudoVLUXEI8_V_MF4_MF4_MASK, PseudoVLUXEI8_V_MF4_MF4, 0x3, false }, // 1399 |
1477 | | { PseudoVLUXEI8_V_MF8_M1_MASK, PseudoVLUXEI8_V_MF8_M1, 0x3, false }, // 1400 |
1478 | | { PseudoVLUXEI8_V_MF8_MF2_MASK, PseudoVLUXEI8_V_MF8_MF2, 0x3, false }, // 1401 |
1479 | | { PseudoVLUXEI8_V_MF8_MF4_MASK, PseudoVLUXEI8_V_MF8_MF4, 0x3, false }, // 1402 |
1480 | | { PseudoVLUXEI8_V_MF8_MF8_MASK, PseudoVLUXEI8_V_MF8_MF8, 0x3, false }, // 1403 |
1481 | | { PseudoVMACC_VV_M1_MASK, PseudoVMACC_VV_M1, 0x3, false }, // 1404 |
1482 | | { PseudoVMACC_VV_M2_MASK, PseudoVMACC_VV_M2, 0x3, false }, // 1405 |
1483 | | { PseudoVMACC_VV_M4_MASK, PseudoVMACC_VV_M4, 0x3, false }, // 1406 |
1484 | | { PseudoVMACC_VV_M8_MASK, PseudoVMACC_VV_M8, 0x3, false }, // 1407 |
1485 | | { PseudoVMACC_VV_MF2_MASK, PseudoVMACC_VV_MF2, 0x3, false }, // 1408 |
1486 | | { PseudoVMACC_VV_MF4_MASK, PseudoVMACC_VV_MF4, 0x3, false }, // 1409 |
1487 | | { PseudoVMACC_VV_MF8_MASK, PseudoVMACC_VV_MF8, 0x3, false }, // 1410 |
1488 | | { PseudoVMACC_VX_M1_MASK, PseudoVMACC_VX_M1, 0x3, false }, // 1411 |
1489 | | { PseudoVMACC_VX_M2_MASK, PseudoVMACC_VX_M2, 0x3, false }, // 1412 |
1490 | | { PseudoVMACC_VX_M4_MASK, PseudoVMACC_VX_M4, 0x3, false }, // 1413 |
1491 | | { PseudoVMACC_VX_M8_MASK, PseudoVMACC_VX_M8, 0x3, false }, // 1414 |
1492 | | { PseudoVMACC_VX_MF2_MASK, PseudoVMACC_VX_MF2, 0x3, false }, // 1415 |
1493 | | { PseudoVMACC_VX_MF4_MASK, PseudoVMACC_VX_MF4, 0x3, false }, // 1416 |
1494 | | { PseudoVMACC_VX_MF8_MASK, PseudoVMACC_VX_MF8, 0x3, false }, // 1417 |
1495 | | { PseudoVMADD_VV_M1_MASK, PseudoVMADD_VV_M1, 0x3, false }, // 1418 |
1496 | | { PseudoVMADD_VV_M2_MASK, PseudoVMADD_VV_M2, 0x3, false }, // 1419 |
1497 | | { PseudoVMADD_VV_M4_MASK, PseudoVMADD_VV_M4, 0x3, false }, // 1420 |
1498 | | { PseudoVMADD_VV_M8_MASK, PseudoVMADD_VV_M8, 0x3, false }, // 1421 |
1499 | | { PseudoVMADD_VV_MF2_MASK, PseudoVMADD_VV_MF2, 0x3, false }, // 1422 |
1500 | | { PseudoVMADD_VV_MF4_MASK, PseudoVMADD_VV_MF4, 0x3, false }, // 1423 |
1501 | | { PseudoVMADD_VV_MF8_MASK, PseudoVMADD_VV_MF8, 0x3, false }, // 1424 |
1502 | | { PseudoVMADD_VX_M1_MASK, PseudoVMADD_VX_M1, 0x3, false }, // 1425 |
1503 | | { PseudoVMADD_VX_M2_MASK, PseudoVMADD_VX_M2, 0x3, false }, // 1426 |
1504 | | { PseudoVMADD_VX_M4_MASK, PseudoVMADD_VX_M4, 0x3, false }, // 1427 |
1505 | | { PseudoVMADD_VX_M8_MASK, PseudoVMADD_VX_M8, 0x3, false }, // 1428 |
1506 | | { PseudoVMADD_VX_MF2_MASK, PseudoVMADD_VX_MF2, 0x3, false }, // 1429 |
1507 | | { PseudoVMADD_VX_MF4_MASK, PseudoVMADD_VX_MF4, 0x3, false }, // 1430 |
1508 | | { PseudoVMADD_VX_MF8_MASK, PseudoVMADD_VX_MF8, 0x3, false }, // 1431 |
1509 | | { PseudoVMAXU_VV_M1_MASK, PseudoVMAXU_VV_M1, 0x3, false }, // 1432 |
1510 | | { PseudoVMAXU_VV_M2_MASK, PseudoVMAXU_VV_M2, 0x3, false }, // 1433 |
1511 | | { PseudoVMAXU_VV_M4_MASK, PseudoVMAXU_VV_M4, 0x3, false }, // 1434 |
1512 | | { PseudoVMAXU_VV_M8_MASK, PseudoVMAXU_VV_M8, 0x3, false }, // 1435 |
1513 | | { PseudoVMAXU_VV_MF2_MASK, PseudoVMAXU_VV_MF2, 0x3, false }, // 1436 |
1514 | | { PseudoVMAXU_VV_MF4_MASK, PseudoVMAXU_VV_MF4, 0x3, false }, // 1437 |
1515 | | { PseudoVMAXU_VV_MF8_MASK, PseudoVMAXU_VV_MF8, 0x3, false }, // 1438 |
1516 | | { PseudoVMAXU_VX_M1_MASK, PseudoVMAXU_VX_M1, 0x3, false }, // 1439 |
1517 | | { PseudoVMAXU_VX_M2_MASK, PseudoVMAXU_VX_M2, 0x3, false }, // 1440 |
1518 | | { PseudoVMAXU_VX_M4_MASK, PseudoVMAXU_VX_M4, 0x3, false }, // 1441 |
1519 | | { PseudoVMAXU_VX_M8_MASK, PseudoVMAXU_VX_M8, 0x3, false }, // 1442 |
1520 | | { PseudoVMAXU_VX_MF2_MASK, PseudoVMAXU_VX_MF2, 0x3, false }, // 1443 |
1521 | | { PseudoVMAXU_VX_MF4_MASK, PseudoVMAXU_VX_MF4, 0x3, false }, // 1444 |
1522 | | { PseudoVMAXU_VX_MF8_MASK, PseudoVMAXU_VX_MF8, 0x3, false }, // 1445 |
1523 | | { PseudoVMAX_VV_M1_MASK, PseudoVMAX_VV_M1, 0x3, false }, // 1446 |
1524 | | { PseudoVMAX_VV_M2_MASK, PseudoVMAX_VV_M2, 0x3, false }, // 1447 |
1525 | | { PseudoVMAX_VV_M4_MASK, PseudoVMAX_VV_M4, 0x3, false }, // 1448 |
1526 | | { PseudoVMAX_VV_M8_MASK, PseudoVMAX_VV_M8, 0x3, false }, // 1449 |
1527 | | { PseudoVMAX_VV_MF2_MASK, PseudoVMAX_VV_MF2, 0x3, false }, // 1450 |
1528 | | { PseudoVMAX_VV_MF4_MASK, PseudoVMAX_VV_MF4, 0x3, false }, // 1451 |
1529 | | { PseudoVMAX_VV_MF8_MASK, PseudoVMAX_VV_MF8, 0x3, false }, // 1452 |
1530 | | { PseudoVMAX_VX_M1_MASK, PseudoVMAX_VX_M1, 0x3, false }, // 1453 |
1531 | | { PseudoVMAX_VX_M2_MASK, PseudoVMAX_VX_M2, 0x3, false }, // 1454 |
1532 | | { PseudoVMAX_VX_M4_MASK, PseudoVMAX_VX_M4, 0x3, false }, // 1455 |
1533 | | { PseudoVMAX_VX_M8_MASK, PseudoVMAX_VX_M8, 0x3, false }, // 1456 |
1534 | | { PseudoVMAX_VX_MF2_MASK, PseudoVMAX_VX_MF2, 0x3, false }, // 1457 |
1535 | | { PseudoVMAX_VX_MF4_MASK, PseudoVMAX_VX_MF4, 0x3, false }, // 1458 |
1536 | | { PseudoVMAX_VX_MF8_MASK, PseudoVMAX_VX_MF8, 0x3, false }, // 1459 |
1537 | | { PseudoVMFEQ_VFPR16_M1_MASK, PseudoVMFEQ_VFPR16_M1, 0x3, false }, // 1460 |
1538 | | { PseudoVMFEQ_VFPR16_M2_MASK, PseudoVMFEQ_VFPR16_M2, 0x3, false }, // 1461 |
1539 | | { PseudoVMFEQ_VFPR16_M4_MASK, PseudoVMFEQ_VFPR16_M4, 0x3, false }, // 1462 |
1540 | | { PseudoVMFEQ_VFPR16_M8_MASK, PseudoVMFEQ_VFPR16_M8, 0x3, false }, // 1463 |
1541 | | { PseudoVMFEQ_VFPR16_MF2_MASK, PseudoVMFEQ_VFPR16_MF2, 0x3, false }, // 1464 |
1542 | | { PseudoVMFEQ_VFPR16_MF4_MASK, PseudoVMFEQ_VFPR16_MF4, 0x3, false }, // 1465 |
1543 | | { PseudoVMFEQ_VFPR32_M1_MASK, PseudoVMFEQ_VFPR32_M1, 0x3, false }, // 1466 |
1544 | | { PseudoVMFEQ_VFPR32_M2_MASK, PseudoVMFEQ_VFPR32_M2, 0x3, false }, // 1467 |
1545 | | { PseudoVMFEQ_VFPR32_M4_MASK, PseudoVMFEQ_VFPR32_M4, 0x3, false }, // 1468 |
1546 | | { PseudoVMFEQ_VFPR32_M8_MASK, PseudoVMFEQ_VFPR32_M8, 0x3, false }, // 1469 |
1547 | | { PseudoVMFEQ_VFPR32_MF2_MASK, PseudoVMFEQ_VFPR32_MF2, 0x3, false }, // 1470 |
1548 | | { PseudoVMFEQ_VFPR64_M1_MASK, PseudoVMFEQ_VFPR64_M1, 0x3, false }, // 1471 |
1549 | | { PseudoVMFEQ_VFPR64_M2_MASK, PseudoVMFEQ_VFPR64_M2, 0x3, false }, // 1472 |
1550 | | { PseudoVMFEQ_VFPR64_M4_MASK, PseudoVMFEQ_VFPR64_M4, 0x3, false }, // 1473 |
1551 | | { PseudoVMFEQ_VFPR64_M8_MASK, PseudoVMFEQ_VFPR64_M8, 0x3, false }, // 1474 |
1552 | | { PseudoVMFEQ_VV_M1_MASK, PseudoVMFEQ_VV_M1, 0x3, false }, // 1475 |
1553 | | { PseudoVMFEQ_VV_M2_MASK, PseudoVMFEQ_VV_M2, 0x3, false }, // 1476 |
1554 | | { PseudoVMFEQ_VV_M4_MASK, PseudoVMFEQ_VV_M4, 0x3, false }, // 1477 |
1555 | | { PseudoVMFEQ_VV_M8_MASK, PseudoVMFEQ_VV_M8, 0x3, false }, // 1478 |
1556 | | { PseudoVMFEQ_VV_MF2_MASK, PseudoVMFEQ_VV_MF2, 0x3, false }, // 1479 |
1557 | | { PseudoVMFEQ_VV_MF4_MASK, PseudoVMFEQ_VV_MF4, 0x3, false }, // 1480 |
1558 | | { PseudoVMFGE_VFPR16_M1_MASK, PseudoVMFGE_VFPR16_M1, 0x3, false }, // 1481 |
1559 | | { PseudoVMFGE_VFPR16_M2_MASK, PseudoVMFGE_VFPR16_M2, 0x3, false }, // 1482 |
1560 | | { PseudoVMFGE_VFPR16_M4_MASK, PseudoVMFGE_VFPR16_M4, 0x3, false }, // 1483 |
1561 | | { PseudoVMFGE_VFPR16_M8_MASK, PseudoVMFGE_VFPR16_M8, 0x3, false }, // 1484 |
1562 | | { PseudoVMFGE_VFPR16_MF2_MASK, PseudoVMFGE_VFPR16_MF2, 0x3, false }, // 1485 |
1563 | | { PseudoVMFGE_VFPR16_MF4_MASK, PseudoVMFGE_VFPR16_MF4, 0x3, false }, // 1486 |
1564 | | { PseudoVMFGE_VFPR32_M1_MASK, PseudoVMFGE_VFPR32_M1, 0x3, false }, // 1487 |
1565 | | { PseudoVMFGE_VFPR32_M2_MASK, PseudoVMFGE_VFPR32_M2, 0x3, false }, // 1488 |
1566 | | { PseudoVMFGE_VFPR32_M4_MASK, PseudoVMFGE_VFPR32_M4, 0x3, false }, // 1489 |
1567 | | { PseudoVMFGE_VFPR32_M8_MASK, PseudoVMFGE_VFPR32_M8, 0x3, false }, // 1490 |
1568 | | { PseudoVMFGE_VFPR32_MF2_MASK, PseudoVMFGE_VFPR32_MF2, 0x3, false }, // 1491 |
1569 | | { PseudoVMFGE_VFPR64_M1_MASK, PseudoVMFGE_VFPR64_M1, 0x3, false }, // 1492 |
1570 | | { PseudoVMFGE_VFPR64_M2_MASK, PseudoVMFGE_VFPR64_M2, 0x3, false }, // 1493 |
1571 | | { PseudoVMFGE_VFPR64_M4_MASK, PseudoVMFGE_VFPR64_M4, 0x3, false }, // 1494 |
1572 | | { PseudoVMFGE_VFPR64_M8_MASK, PseudoVMFGE_VFPR64_M8, 0x3, false }, // 1495 |
1573 | | { PseudoVMFGT_VFPR16_M1_MASK, PseudoVMFGT_VFPR16_M1, 0x3, false }, // 1496 |
1574 | | { PseudoVMFGT_VFPR16_M2_MASK, PseudoVMFGT_VFPR16_M2, 0x3, false }, // 1497 |
1575 | | { PseudoVMFGT_VFPR16_M4_MASK, PseudoVMFGT_VFPR16_M4, 0x3, false }, // 1498 |
1576 | | { PseudoVMFGT_VFPR16_M8_MASK, PseudoVMFGT_VFPR16_M8, 0x3, false }, // 1499 |
1577 | | { PseudoVMFGT_VFPR16_MF2_MASK, PseudoVMFGT_VFPR16_MF2, 0x3, false }, // 1500 |
1578 | | { PseudoVMFGT_VFPR16_MF4_MASK, PseudoVMFGT_VFPR16_MF4, 0x3, false }, // 1501 |
1579 | | { PseudoVMFGT_VFPR32_M1_MASK, PseudoVMFGT_VFPR32_M1, 0x3, false }, // 1502 |
1580 | | { PseudoVMFGT_VFPR32_M2_MASK, PseudoVMFGT_VFPR32_M2, 0x3, false }, // 1503 |
1581 | | { PseudoVMFGT_VFPR32_M4_MASK, PseudoVMFGT_VFPR32_M4, 0x3, false }, // 1504 |
1582 | | { PseudoVMFGT_VFPR32_M8_MASK, PseudoVMFGT_VFPR32_M8, 0x3, false }, // 1505 |
1583 | | { PseudoVMFGT_VFPR32_MF2_MASK, PseudoVMFGT_VFPR32_MF2, 0x3, false }, // 1506 |
1584 | | { PseudoVMFGT_VFPR64_M1_MASK, PseudoVMFGT_VFPR64_M1, 0x3, false }, // 1507 |
1585 | | { PseudoVMFGT_VFPR64_M2_MASK, PseudoVMFGT_VFPR64_M2, 0x3, false }, // 1508 |
1586 | | { PseudoVMFGT_VFPR64_M4_MASK, PseudoVMFGT_VFPR64_M4, 0x3, false }, // 1509 |
1587 | | { PseudoVMFGT_VFPR64_M8_MASK, PseudoVMFGT_VFPR64_M8, 0x3, false }, // 1510 |
1588 | | { PseudoVMFLE_VFPR16_M1_MASK, PseudoVMFLE_VFPR16_M1, 0x3, false }, // 1511 |
1589 | | { PseudoVMFLE_VFPR16_M2_MASK, PseudoVMFLE_VFPR16_M2, 0x3, false }, // 1512 |
1590 | | { PseudoVMFLE_VFPR16_M4_MASK, PseudoVMFLE_VFPR16_M4, 0x3, false }, // 1513 |
1591 | | { PseudoVMFLE_VFPR16_M8_MASK, PseudoVMFLE_VFPR16_M8, 0x3, false }, // 1514 |
1592 | | { PseudoVMFLE_VFPR16_MF2_MASK, PseudoVMFLE_VFPR16_MF2, 0x3, false }, // 1515 |
1593 | | { PseudoVMFLE_VFPR16_MF4_MASK, PseudoVMFLE_VFPR16_MF4, 0x3, false }, // 1516 |
1594 | | { PseudoVMFLE_VFPR32_M1_MASK, PseudoVMFLE_VFPR32_M1, 0x3, false }, // 1517 |
1595 | | { PseudoVMFLE_VFPR32_M2_MASK, PseudoVMFLE_VFPR32_M2, 0x3, false }, // 1518 |
1596 | | { PseudoVMFLE_VFPR32_M4_MASK, PseudoVMFLE_VFPR32_M4, 0x3, false }, // 1519 |
1597 | | { PseudoVMFLE_VFPR32_M8_MASK, PseudoVMFLE_VFPR32_M8, 0x3, false }, // 1520 |
1598 | | { PseudoVMFLE_VFPR32_MF2_MASK, PseudoVMFLE_VFPR32_MF2, 0x3, false }, // 1521 |
1599 | | { PseudoVMFLE_VFPR64_M1_MASK, PseudoVMFLE_VFPR64_M1, 0x3, false }, // 1522 |
1600 | | { PseudoVMFLE_VFPR64_M2_MASK, PseudoVMFLE_VFPR64_M2, 0x3, false }, // 1523 |
1601 | | { PseudoVMFLE_VFPR64_M4_MASK, PseudoVMFLE_VFPR64_M4, 0x3, false }, // 1524 |
1602 | | { PseudoVMFLE_VFPR64_M8_MASK, PseudoVMFLE_VFPR64_M8, 0x3, false }, // 1525 |
1603 | | { PseudoVMFLE_VV_M1_MASK, PseudoVMFLE_VV_M1, 0x3, false }, // 1526 |
1604 | | { PseudoVMFLE_VV_M2_MASK, PseudoVMFLE_VV_M2, 0x3, false }, // 1527 |
1605 | | { PseudoVMFLE_VV_M4_MASK, PseudoVMFLE_VV_M4, 0x3, false }, // 1528 |
1606 | | { PseudoVMFLE_VV_M8_MASK, PseudoVMFLE_VV_M8, 0x3, false }, // 1529 |
1607 | | { PseudoVMFLE_VV_MF2_MASK, PseudoVMFLE_VV_MF2, 0x3, false }, // 1530 |
1608 | | { PseudoVMFLE_VV_MF4_MASK, PseudoVMFLE_VV_MF4, 0x3, false }, // 1531 |
1609 | | { PseudoVMFLT_VFPR16_M1_MASK, PseudoVMFLT_VFPR16_M1, 0x3, false }, // 1532 |
1610 | | { PseudoVMFLT_VFPR16_M2_MASK, PseudoVMFLT_VFPR16_M2, 0x3, false }, // 1533 |
1611 | | { PseudoVMFLT_VFPR16_M4_MASK, PseudoVMFLT_VFPR16_M4, 0x3, false }, // 1534 |
1612 | | { PseudoVMFLT_VFPR16_M8_MASK, PseudoVMFLT_VFPR16_M8, 0x3, false }, // 1535 |
1613 | | { PseudoVMFLT_VFPR16_MF2_MASK, PseudoVMFLT_VFPR16_MF2, 0x3, false }, // 1536 |
1614 | | { PseudoVMFLT_VFPR16_MF4_MASK, PseudoVMFLT_VFPR16_MF4, 0x3, false }, // 1537 |
1615 | | { PseudoVMFLT_VFPR32_M1_MASK, PseudoVMFLT_VFPR32_M1, 0x3, false }, // 1538 |
1616 | | { PseudoVMFLT_VFPR32_M2_MASK, PseudoVMFLT_VFPR32_M2, 0x3, false }, // 1539 |
1617 | | { PseudoVMFLT_VFPR32_M4_MASK, PseudoVMFLT_VFPR32_M4, 0x3, false }, // 1540 |
1618 | | { PseudoVMFLT_VFPR32_M8_MASK, PseudoVMFLT_VFPR32_M8, 0x3, false }, // 1541 |
1619 | | { PseudoVMFLT_VFPR32_MF2_MASK, PseudoVMFLT_VFPR32_MF2, 0x3, false }, // 1542 |
1620 | | { PseudoVMFLT_VFPR64_M1_MASK, PseudoVMFLT_VFPR64_M1, 0x3, false }, // 1543 |
1621 | | { PseudoVMFLT_VFPR64_M2_MASK, PseudoVMFLT_VFPR64_M2, 0x3, false }, // 1544 |
1622 | | { PseudoVMFLT_VFPR64_M4_MASK, PseudoVMFLT_VFPR64_M4, 0x3, false }, // 1545 |
1623 | | { PseudoVMFLT_VFPR64_M8_MASK, PseudoVMFLT_VFPR64_M8, 0x3, false }, // 1546 |
1624 | | { PseudoVMFLT_VV_M1_MASK, PseudoVMFLT_VV_M1, 0x3, false }, // 1547 |
1625 | | { PseudoVMFLT_VV_M2_MASK, PseudoVMFLT_VV_M2, 0x3, false }, // 1548 |
1626 | | { PseudoVMFLT_VV_M4_MASK, PseudoVMFLT_VV_M4, 0x3, false }, // 1549 |
1627 | | { PseudoVMFLT_VV_M8_MASK, PseudoVMFLT_VV_M8, 0x3, false }, // 1550 |
1628 | | { PseudoVMFLT_VV_MF2_MASK, PseudoVMFLT_VV_MF2, 0x3, false }, // 1551 |
1629 | | { PseudoVMFLT_VV_MF4_MASK, PseudoVMFLT_VV_MF4, 0x3, false }, // 1552 |
1630 | | { PseudoVMFNE_VFPR16_M1_MASK, PseudoVMFNE_VFPR16_M1, 0x3, false }, // 1553 |
1631 | | { PseudoVMFNE_VFPR16_M2_MASK, PseudoVMFNE_VFPR16_M2, 0x3, false }, // 1554 |
1632 | | { PseudoVMFNE_VFPR16_M4_MASK, PseudoVMFNE_VFPR16_M4, 0x3, false }, // 1555 |
1633 | | { PseudoVMFNE_VFPR16_M8_MASK, PseudoVMFNE_VFPR16_M8, 0x3, false }, // 1556 |
1634 | | { PseudoVMFNE_VFPR16_MF2_MASK, PseudoVMFNE_VFPR16_MF2, 0x3, false }, // 1557 |
1635 | | { PseudoVMFNE_VFPR16_MF4_MASK, PseudoVMFNE_VFPR16_MF4, 0x3, false }, // 1558 |
1636 | | { PseudoVMFNE_VFPR32_M1_MASK, PseudoVMFNE_VFPR32_M1, 0x3, false }, // 1559 |
1637 | | { PseudoVMFNE_VFPR32_M2_MASK, PseudoVMFNE_VFPR32_M2, 0x3, false }, // 1560 |
1638 | | { PseudoVMFNE_VFPR32_M4_MASK, PseudoVMFNE_VFPR32_M4, 0x3, false }, // 1561 |
1639 | | { PseudoVMFNE_VFPR32_M8_MASK, PseudoVMFNE_VFPR32_M8, 0x3, false }, // 1562 |
1640 | | { PseudoVMFNE_VFPR32_MF2_MASK, PseudoVMFNE_VFPR32_MF2, 0x3, false }, // 1563 |
1641 | | { PseudoVMFNE_VFPR64_M1_MASK, PseudoVMFNE_VFPR64_M1, 0x3, false }, // 1564 |
1642 | | { PseudoVMFNE_VFPR64_M2_MASK, PseudoVMFNE_VFPR64_M2, 0x3, false }, // 1565 |
1643 | | { PseudoVMFNE_VFPR64_M4_MASK, PseudoVMFNE_VFPR64_M4, 0x3, false }, // 1566 |
1644 | | { PseudoVMFNE_VFPR64_M8_MASK, PseudoVMFNE_VFPR64_M8, 0x3, false }, // 1567 |
1645 | | { PseudoVMFNE_VV_M1_MASK, PseudoVMFNE_VV_M1, 0x3, false }, // 1568 |
1646 | | { PseudoVMFNE_VV_M2_MASK, PseudoVMFNE_VV_M2, 0x3, false }, // 1569 |
1647 | | { PseudoVMFNE_VV_M4_MASK, PseudoVMFNE_VV_M4, 0x3, false }, // 1570 |
1648 | | { PseudoVMFNE_VV_M8_MASK, PseudoVMFNE_VV_M8, 0x3, false }, // 1571 |
1649 | | { PseudoVMFNE_VV_MF2_MASK, PseudoVMFNE_VV_MF2, 0x3, false }, // 1572 |
1650 | | { PseudoVMFNE_VV_MF4_MASK, PseudoVMFNE_VV_MF4, 0x3, false }, // 1573 |
1651 | | { PseudoVMINU_VV_M1_MASK, PseudoVMINU_VV_M1, 0x3, false }, // 1574 |
1652 | | { PseudoVMINU_VV_M2_MASK, PseudoVMINU_VV_M2, 0x3, false }, // 1575 |
1653 | | { PseudoVMINU_VV_M4_MASK, PseudoVMINU_VV_M4, 0x3, false }, // 1576 |
1654 | | { PseudoVMINU_VV_M8_MASK, PseudoVMINU_VV_M8, 0x3, false }, // 1577 |
1655 | | { PseudoVMINU_VV_MF2_MASK, PseudoVMINU_VV_MF2, 0x3, false }, // 1578 |
1656 | | { PseudoVMINU_VV_MF4_MASK, PseudoVMINU_VV_MF4, 0x3, false }, // 1579 |
1657 | | { PseudoVMINU_VV_MF8_MASK, PseudoVMINU_VV_MF8, 0x3, false }, // 1580 |
1658 | | { PseudoVMINU_VX_M1_MASK, PseudoVMINU_VX_M1, 0x3, false }, // 1581 |
1659 | | { PseudoVMINU_VX_M2_MASK, PseudoVMINU_VX_M2, 0x3, false }, // 1582 |
1660 | | { PseudoVMINU_VX_M4_MASK, PseudoVMINU_VX_M4, 0x3, false }, // 1583 |
1661 | | { PseudoVMINU_VX_M8_MASK, PseudoVMINU_VX_M8, 0x3, false }, // 1584 |
1662 | | { PseudoVMINU_VX_MF2_MASK, PseudoVMINU_VX_MF2, 0x3, false }, // 1585 |
1663 | | { PseudoVMINU_VX_MF4_MASK, PseudoVMINU_VX_MF4, 0x3, false }, // 1586 |
1664 | | { PseudoVMINU_VX_MF8_MASK, PseudoVMINU_VX_MF8, 0x3, false }, // 1587 |
1665 | | { PseudoVMIN_VV_M1_MASK, PseudoVMIN_VV_M1, 0x3, false }, // 1588 |
1666 | | { PseudoVMIN_VV_M2_MASK, PseudoVMIN_VV_M2, 0x3, false }, // 1589 |
1667 | | { PseudoVMIN_VV_M4_MASK, PseudoVMIN_VV_M4, 0x3, false }, // 1590 |
1668 | | { PseudoVMIN_VV_M8_MASK, PseudoVMIN_VV_M8, 0x3, false }, // 1591 |
1669 | | { PseudoVMIN_VV_MF2_MASK, PseudoVMIN_VV_MF2, 0x3, false }, // 1592 |
1670 | | { PseudoVMIN_VV_MF4_MASK, PseudoVMIN_VV_MF4, 0x3, false }, // 1593 |
1671 | | { PseudoVMIN_VV_MF8_MASK, PseudoVMIN_VV_MF8, 0x3, false }, // 1594 |
1672 | | { PseudoVMIN_VX_M1_MASK, PseudoVMIN_VX_M1, 0x3, false }, // 1595 |
1673 | | { PseudoVMIN_VX_M2_MASK, PseudoVMIN_VX_M2, 0x3, false }, // 1596 |
1674 | | { PseudoVMIN_VX_M4_MASK, PseudoVMIN_VX_M4, 0x3, false }, // 1597 |
1675 | | { PseudoVMIN_VX_M8_MASK, PseudoVMIN_VX_M8, 0x3, false }, // 1598 |
1676 | | { PseudoVMIN_VX_MF2_MASK, PseudoVMIN_VX_MF2, 0x3, false }, // 1599 |
1677 | | { PseudoVMIN_VX_MF4_MASK, PseudoVMIN_VX_MF4, 0x3, false }, // 1600 |
1678 | | { PseudoVMIN_VX_MF8_MASK, PseudoVMIN_VX_MF8, 0x3, false }, // 1601 |
1679 | | { PseudoVMSEQ_VI_M1_MASK, PseudoVMSEQ_VI_M1, 0x3, false }, // 1602 |
1680 | | { PseudoVMSEQ_VI_M2_MASK, PseudoVMSEQ_VI_M2, 0x3, false }, // 1603 |
1681 | | { PseudoVMSEQ_VI_M4_MASK, PseudoVMSEQ_VI_M4, 0x3, false }, // 1604 |
1682 | | { PseudoVMSEQ_VI_M8_MASK, PseudoVMSEQ_VI_M8, 0x3, false }, // 1605 |
1683 | | { PseudoVMSEQ_VI_MF2_MASK, PseudoVMSEQ_VI_MF2, 0x3, false }, // 1606 |
1684 | | { PseudoVMSEQ_VI_MF4_MASK, PseudoVMSEQ_VI_MF4, 0x3, false }, // 1607 |
1685 | | { PseudoVMSEQ_VI_MF8_MASK, PseudoVMSEQ_VI_MF8, 0x3, false }, // 1608 |
1686 | | { PseudoVMSEQ_VV_M1_MASK, PseudoVMSEQ_VV_M1, 0x3, false }, // 1609 |
1687 | | { PseudoVMSEQ_VV_M2_MASK, PseudoVMSEQ_VV_M2, 0x3, false }, // 1610 |
1688 | | { PseudoVMSEQ_VV_M4_MASK, PseudoVMSEQ_VV_M4, 0x3, false }, // 1611 |
1689 | | { PseudoVMSEQ_VV_M8_MASK, PseudoVMSEQ_VV_M8, 0x3, false }, // 1612 |
1690 | | { PseudoVMSEQ_VV_MF2_MASK, PseudoVMSEQ_VV_MF2, 0x3, false }, // 1613 |
1691 | | { PseudoVMSEQ_VV_MF4_MASK, PseudoVMSEQ_VV_MF4, 0x3, false }, // 1614 |
1692 | | { PseudoVMSEQ_VV_MF8_MASK, PseudoVMSEQ_VV_MF8, 0x3, false }, // 1615 |
1693 | | { PseudoVMSEQ_VX_M1_MASK, PseudoVMSEQ_VX_M1, 0x3, false }, // 1616 |
1694 | | { PseudoVMSEQ_VX_M2_MASK, PseudoVMSEQ_VX_M2, 0x3, false }, // 1617 |
1695 | | { PseudoVMSEQ_VX_M4_MASK, PseudoVMSEQ_VX_M4, 0x3, false }, // 1618 |
1696 | | { PseudoVMSEQ_VX_M8_MASK, PseudoVMSEQ_VX_M8, 0x3, false }, // 1619 |
1697 | | { PseudoVMSEQ_VX_MF2_MASK, PseudoVMSEQ_VX_MF2, 0x3, false }, // 1620 |
1698 | | { PseudoVMSEQ_VX_MF4_MASK, PseudoVMSEQ_VX_MF4, 0x3, false }, // 1621 |
1699 | | { PseudoVMSEQ_VX_MF8_MASK, PseudoVMSEQ_VX_MF8, 0x3, false }, // 1622 |
1700 | | { PseudoVMSGTU_VI_M1_MASK, PseudoVMSGTU_VI_M1, 0x3, false }, // 1623 |
1701 | | { PseudoVMSGTU_VI_M2_MASK, PseudoVMSGTU_VI_M2, 0x3, false }, // 1624 |
1702 | | { PseudoVMSGTU_VI_M4_MASK, PseudoVMSGTU_VI_M4, 0x3, false }, // 1625 |
1703 | | { PseudoVMSGTU_VI_M8_MASK, PseudoVMSGTU_VI_M8, 0x3, false }, // 1626 |
1704 | | { PseudoVMSGTU_VI_MF2_MASK, PseudoVMSGTU_VI_MF2, 0x3, false }, // 1627 |
1705 | | { PseudoVMSGTU_VI_MF4_MASK, PseudoVMSGTU_VI_MF4, 0x3, false }, // 1628 |
1706 | | { PseudoVMSGTU_VI_MF8_MASK, PseudoVMSGTU_VI_MF8, 0x3, false }, // 1629 |
1707 | | { PseudoVMSGTU_VX_M1_MASK, PseudoVMSGTU_VX_M1, 0x3, false }, // 1630 |
1708 | | { PseudoVMSGTU_VX_M2_MASK, PseudoVMSGTU_VX_M2, 0x3, false }, // 1631 |
1709 | | { PseudoVMSGTU_VX_M4_MASK, PseudoVMSGTU_VX_M4, 0x3, false }, // 1632 |
1710 | | { PseudoVMSGTU_VX_M8_MASK, PseudoVMSGTU_VX_M8, 0x3, false }, // 1633 |
1711 | | { PseudoVMSGTU_VX_MF2_MASK, PseudoVMSGTU_VX_MF2, 0x3, false }, // 1634 |
1712 | | { PseudoVMSGTU_VX_MF4_MASK, PseudoVMSGTU_VX_MF4, 0x3, false }, // 1635 |
1713 | | { PseudoVMSGTU_VX_MF8_MASK, PseudoVMSGTU_VX_MF8, 0x3, false }, // 1636 |
1714 | | { PseudoVMSGT_VI_M1_MASK, PseudoVMSGT_VI_M1, 0x3, false }, // 1637 |
1715 | | { PseudoVMSGT_VI_M2_MASK, PseudoVMSGT_VI_M2, 0x3, false }, // 1638 |
1716 | | { PseudoVMSGT_VI_M4_MASK, PseudoVMSGT_VI_M4, 0x3, false }, // 1639 |
1717 | | { PseudoVMSGT_VI_M8_MASK, PseudoVMSGT_VI_M8, 0x3, false }, // 1640 |
1718 | | { PseudoVMSGT_VI_MF2_MASK, PseudoVMSGT_VI_MF2, 0x3, false }, // 1641 |
1719 | | { PseudoVMSGT_VI_MF4_MASK, PseudoVMSGT_VI_MF4, 0x3, false }, // 1642 |
1720 | | { PseudoVMSGT_VI_MF8_MASK, PseudoVMSGT_VI_MF8, 0x3, false }, // 1643 |
1721 | | { PseudoVMSGT_VX_M1_MASK, PseudoVMSGT_VX_M1, 0x3, false }, // 1644 |
1722 | | { PseudoVMSGT_VX_M2_MASK, PseudoVMSGT_VX_M2, 0x3, false }, // 1645 |
1723 | | { PseudoVMSGT_VX_M4_MASK, PseudoVMSGT_VX_M4, 0x3, false }, // 1646 |
1724 | | { PseudoVMSGT_VX_M8_MASK, PseudoVMSGT_VX_M8, 0x3, false }, // 1647 |
1725 | | { PseudoVMSGT_VX_MF2_MASK, PseudoVMSGT_VX_MF2, 0x3, false }, // 1648 |
1726 | | { PseudoVMSGT_VX_MF4_MASK, PseudoVMSGT_VX_MF4, 0x3, false }, // 1649 |
1727 | | { PseudoVMSGT_VX_MF8_MASK, PseudoVMSGT_VX_MF8, 0x3, false }, // 1650 |
1728 | | { PseudoVMSLEU_VI_M1_MASK, PseudoVMSLEU_VI_M1, 0x3, false }, // 1651 |
1729 | | { PseudoVMSLEU_VI_M2_MASK, PseudoVMSLEU_VI_M2, 0x3, false }, // 1652 |
1730 | | { PseudoVMSLEU_VI_M4_MASK, PseudoVMSLEU_VI_M4, 0x3, false }, // 1653 |
1731 | | { PseudoVMSLEU_VI_M8_MASK, PseudoVMSLEU_VI_M8, 0x3, false }, // 1654 |
1732 | | { PseudoVMSLEU_VI_MF2_MASK, PseudoVMSLEU_VI_MF2, 0x3, false }, // 1655 |
1733 | | { PseudoVMSLEU_VI_MF4_MASK, PseudoVMSLEU_VI_MF4, 0x3, false }, // 1656 |
1734 | | { PseudoVMSLEU_VI_MF8_MASK, PseudoVMSLEU_VI_MF8, 0x3, false }, // 1657 |
1735 | | { PseudoVMSLEU_VV_M1_MASK, PseudoVMSLEU_VV_M1, 0x3, false }, // 1658 |
1736 | | { PseudoVMSLEU_VV_M2_MASK, PseudoVMSLEU_VV_M2, 0x3, false }, // 1659 |
1737 | | { PseudoVMSLEU_VV_M4_MASK, PseudoVMSLEU_VV_M4, 0x3, false }, // 1660 |
1738 | | { PseudoVMSLEU_VV_M8_MASK, PseudoVMSLEU_VV_M8, 0x3, false }, // 1661 |
1739 | | { PseudoVMSLEU_VV_MF2_MASK, PseudoVMSLEU_VV_MF2, 0x3, false }, // 1662 |
1740 | | { PseudoVMSLEU_VV_MF4_MASK, PseudoVMSLEU_VV_MF4, 0x3, false }, // 1663 |
1741 | | { PseudoVMSLEU_VV_MF8_MASK, PseudoVMSLEU_VV_MF8, 0x3, false }, // 1664 |
1742 | | { PseudoVMSLEU_VX_M1_MASK, PseudoVMSLEU_VX_M1, 0x3, false }, // 1665 |
1743 | | { PseudoVMSLEU_VX_M2_MASK, PseudoVMSLEU_VX_M2, 0x3, false }, // 1666 |
1744 | | { PseudoVMSLEU_VX_M4_MASK, PseudoVMSLEU_VX_M4, 0x3, false }, // 1667 |
1745 | | { PseudoVMSLEU_VX_M8_MASK, PseudoVMSLEU_VX_M8, 0x3, false }, // 1668 |
1746 | | { PseudoVMSLEU_VX_MF2_MASK, PseudoVMSLEU_VX_MF2, 0x3, false }, // 1669 |
1747 | | { PseudoVMSLEU_VX_MF4_MASK, PseudoVMSLEU_VX_MF4, 0x3, false }, // 1670 |
1748 | | { PseudoVMSLEU_VX_MF8_MASK, PseudoVMSLEU_VX_MF8, 0x3, false }, // 1671 |
1749 | | { PseudoVMSLE_VI_M1_MASK, PseudoVMSLE_VI_M1, 0x3, false }, // 1672 |
1750 | | { PseudoVMSLE_VI_M2_MASK, PseudoVMSLE_VI_M2, 0x3, false }, // 1673 |
1751 | | { PseudoVMSLE_VI_M4_MASK, PseudoVMSLE_VI_M4, 0x3, false }, // 1674 |
1752 | | { PseudoVMSLE_VI_M8_MASK, PseudoVMSLE_VI_M8, 0x3, false }, // 1675 |
1753 | | { PseudoVMSLE_VI_MF2_MASK, PseudoVMSLE_VI_MF2, 0x3, false }, // 1676 |
1754 | | { PseudoVMSLE_VI_MF4_MASK, PseudoVMSLE_VI_MF4, 0x3, false }, // 1677 |
1755 | | { PseudoVMSLE_VI_MF8_MASK, PseudoVMSLE_VI_MF8, 0x3, false }, // 1678 |
1756 | | { PseudoVMSLE_VV_M1_MASK, PseudoVMSLE_VV_M1, 0x3, false }, // 1679 |
1757 | | { PseudoVMSLE_VV_M2_MASK, PseudoVMSLE_VV_M2, 0x3, false }, // 1680 |
1758 | | { PseudoVMSLE_VV_M4_MASK, PseudoVMSLE_VV_M4, 0x3, false }, // 1681 |
1759 | | { PseudoVMSLE_VV_M8_MASK, PseudoVMSLE_VV_M8, 0x3, false }, // 1682 |
1760 | | { PseudoVMSLE_VV_MF2_MASK, PseudoVMSLE_VV_MF2, 0x3, false }, // 1683 |
1761 | | { PseudoVMSLE_VV_MF4_MASK, PseudoVMSLE_VV_MF4, 0x3, false }, // 1684 |
1762 | | { PseudoVMSLE_VV_MF8_MASK, PseudoVMSLE_VV_MF8, 0x3, false }, // 1685 |
1763 | | { PseudoVMSLE_VX_M1_MASK, PseudoVMSLE_VX_M1, 0x3, false }, // 1686 |
1764 | | { PseudoVMSLE_VX_M2_MASK, PseudoVMSLE_VX_M2, 0x3, false }, // 1687 |
1765 | | { PseudoVMSLE_VX_M4_MASK, PseudoVMSLE_VX_M4, 0x3, false }, // 1688 |
1766 | | { PseudoVMSLE_VX_M8_MASK, PseudoVMSLE_VX_M8, 0x3, false }, // 1689 |
1767 | | { PseudoVMSLE_VX_MF2_MASK, PseudoVMSLE_VX_MF2, 0x3, false }, // 1690 |
1768 | | { PseudoVMSLE_VX_MF4_MASK, PseudoVMSLE_VX_MF4, 0x3, false }, // 1691 |
1769 | | { PseudoVMSLE_VX_MF8_MASK, PseudoVMSLE_VX_MF8, 0x3, false }, // 1692 |
1770 | | { PseudoVMSLTU_VV_M1_MASK, PseudoVMSLTU_VV_M1, 0x3, false }, // 1693 |
1771 | | { PseudoVMSLTU_VV_M2_MASK, PseudoVMSLTU_VV_M2, 0x3, false }, // 1694 |
1772 | | { PseudoVMSLTU_VV_M4_MASK, PseudoVMSLTU_VV_M4, 0x3, false }, // 1695 |
1773 | | { PseudoVMSLTU_VV_M8_MASK, PseudoVMSLTU_VV_M8, 0x3, false }, // 1696 |
1774 | | { PseudoVMSLTU_VV_MF2_MASK, PseudoVMSLTU_VV_MF2, 0x3, false }, // 1697 |
1775 | | { PseudoVMSLTU_VV_MF4_MASK, PseudoVMSLTU_VV_MF4, 0x3, false }, // 1698 |
1776 | | { PseudoVMSLTU_VV_MF8_MASK, PseudoVMSLTU_VV_MF8, 0x3, false }, // 1699 |
1777 | | { PseudoVMSLTU_VX_M1_MASK, PseudoVMSLTU_VX_M1, 0x3, false }, // 1700 |
1778 | | { PseudoVMSLTU_VX_M2_MASK, PseudoVMSLTU_VX_M2, 0x3, false }, // 1701 |
1779 | | { PseudoVMSLTU_VX_M4_MASK, PseudoVMSLTU_VX_M4, 0x3, false }, // 1702 |
1780 | | { PseudoVMSLTU_VX_M8_MASK, PseudoVMSLTU_VX_M8, 0x3, false }, // 1703 |
1781 | | { PseudoVMSLTU_VX_MF2_MASK, PseudoVMSLTU_VX_MF2, 0x3, false }, // 1704 |
1782 | | { PseudoVMSLTU_VX_MF4_MASK, PseudoVMSLTU_VX_MF4, 0x3, false }, // 1705 |
1783 | | { PseudoVMSLTU_VX_MF8_MASK, PseudoVMSLTU_VX_MF8, 0x3, false }, // 1706 |
1784 | | { PseudoVMSLT_VV_M1_MASK, PseudoVMSLT_VV_M1, 0x3, false }, // 1707 |
1785 | | { PseudoVMSLT_VV_M2_MASK, PseudoVMSLT_VV_M2, 0x3, false }, // 1708 |
1786 | | { PseudoVMSLT_VV_M4_MASK, PseudoVMSLT_VV_M4, 0x3, false }, // 1709 |
1787 | | { PseudoVMSLT_VV_M8_MASK, PseudoVMSLT_VV_M8, 0x3, false }, // 1710 |
1788 | | { PseudoVMSLT_VV_MF2_MASK, PseudoVMSLT_VV_MF2, 0x3, false }, // 1711 |
1789 | | { PseudoVMSLT_VV_MF4_MASK, PseudoVMSLT_VV_MF4, 0x3, false }, // 1712 |
1790 | | { PseudoVMSLT_VV_MF8_MASK, PseudoVMSLT_VV_MF8, 0x3, false }, // 1713 |
1791 | | { PseudoVMSLT_VX_M1_MASK, PseudoVMSLT_VX_M1, 0x3, false }, // 1714 |
1792 | | { PseudoVMSLT_VX_M2_MASK, PseudoVMSLT_VX_M2, 0x3, false }, // 1715 |
1793 | | { PseudoVMSLT_VX_M4_MASK, PseudoVMSLT_VX_M4, 0x3, false }, // 1716 |
1794 | | { PseudoVMSLT_VX_M8_MASK, PseudoVMSLT_VX_M8, 0x3, false }, // 1717 |
1795 | | { PseudoVMSLT_VX_MF2_MASK, PseudoVMSLT_VX_MF2, 0x3, false }, // 1718 |
1796 | | { PseudoVMSLT_VX_MF4_MASK, PseudoVMSLT_VX_MF4, 0x3, false }, // 1719 |
1797 | | { PseudoVMSLT_VX_MF8_MASK, PseudoVMSLT_VX_MF8, 0x3, false }, // 1720 |
1798 | | { PseudoVMSNE_VI_M1_MASK, PseudoVMSNE_VI_M1, 0x3, false }, // 1721 |
1799 | | { PseudoVMSNE_VI_M2_MASK, PseudoVMSNE_VI_M2, 0x3, false }, // 1722 |
1800 | | { PseudoVMSNE_VI_M4_MASK, PseudoVMSNE_VI_M4, 0x3, false }, // 1723 |
1801 | | { PseudoVMSNE_VI_M8_MASK, PseudoVMSNE_VI_M8, 0x3, false }, // 1724 |
1802 | | { PseudoVMSNE_VI_MF2_MASK, PseudoVMSNE_VI_MF2, 0x3, false }, // 1725 |
1803 | | { PseudoVMSNE_VI_MF4_MASK, PseudoVMSNE_VI_MF4, 0x3, false }, // 1726 |
1804 | | { PseudoVMSNE_VI_MF8_MASK, PseudoVMSNE_VI_MF8, 0x3, false }, // 1727 |
1805 | | { PseudoVMSNE_VV_M1_MASK, PseudoVMSNE_VV_M1, 0x3, false }, // 1728 |
1806 | | { PseudoVMSNE_VV_M2_MASK, PseudoVMSNE_VV_M2, 0x3, false }, // 1729 |
1807 | | { PseudoVMSNE_VV_M4_MASK, PseudoVMSNE_VV_M4, 0x3, false }, // 1730 |
1808 | | { PseudoVMSNE_VV_M8_MASK, PseudoVMSNE_VV_M8, 0x3, false }, // 1731 |
1809 | | { PseudoVMSNE_VV_MF2_MASK, PseudoVMSNE_VV_MF2, 0x3, false }, // 1732 |
1810 | | { PseudoVMSNE_VV_MF4_MASK, PseudoVMSNE_VV_MF4, 0x3, false }, // 1733 |
1811 | | { PseudoVMSNE_VV_MF8_MASK, PseudoVMSNE_VV_MF8, 0x3, false }, // 1734 |
1812 | | { PseudoVMSNE_VX_M1_MASK, PseudoVMSNE_VX_M1, 0x3, false }, // 1735 |
1813 | | { PseudoVMSNE_VX_M2_MASK, PseudoVMSNE_VX_M2, 0x3, false }, // 1736 |
1814 | | { PseudoVMSNE_VX_M4_MASK, PseudoVMSNE_VX_M4, 0x3, false }, // 1737 |
1815 | | { PseudoVMSNE_VX_M8_MASK, PseudoVMSNE_VX_M8, 0x3, false }, // 1738 |
1816 | | { PseudoVMSNE_VX_MF2_MASK, PseudoVMSNE_VX_MF2, 0x3, false }, // 1739 |
1817 | | { PseudoVMSNE_VX_MF4_MASK, PseudoVMSNE_VX_MF4, 0x3, false }, // 1740 |
1818 | | { PseudoVMSNE_VX_MF8_MASK, PseudoVMSNE_VX_MF8, 0x3, false }, // 1741 |
1819 | | { PseudoVMULHSU_VV_M1_MASK, PseudoVMULHSU_VV_M1, 0x3, false }, // 1742 |
1820 | | { PseudoVMULHSU_VV_M2_MASK, PseudoVMULHSU_VV_M2, 0x3, false }, // 1743 |
1821 | | { PseudoVMULHSU_VV_M4_MASK, PseudoVMULHSU_VV_M4, 0x3, false }, // 1744 |
1822 | | { PseudoVMULHSU_VV_M8_MASK, PseudoVMULHSU_VV_M8, 0x3, false }, // 1745 |
1823 | | { PseudoVMULHSU_VV_MF2_MASK, PseudoVMULHSU_VV_MF2, 0x3, false }, // 1746 |
1824 | | { PseudoVMULHSU_VV_MF4_MASK, PseudoVMULHSU_VV_MF4, 0x3, false }, // 1747 |
1825 | | { PseudoVMULHSU_VV_MF8_MASK, PseudoVMULHSU_VV_MF8, 0x3, false }, // 1748 |
1826 | | { PseudoVMULHSU_VX_M1_MASK, PseudoVMULHSU_VX_M1, 0x3, false }, // 1749 |
1827 | | { PseudoVMULHSU_VX_M2_MASK, PseudoVMULHSU_VX_M2, 0x3, false }, // 1750 |
1828 | | { PseudoVMULHSU_VX_M4_MASK, PseudoVMULHSU_VX_M4, 0x3, false }, // 1751 |
1829 | | { PseudoVMULHSU_VX_M8_MASK, PseudoVMULHSU_VX_M8, 0x3, false }, // 1752 |
1830 | | { PseudoVMULHSU_VX_MF2_MASK, PseudoVMULHSU_VX_MF2, 0x3, false }, // 1753 |
1831 | | { PseudoVMULHSU_VX_MF4_MASK, PseudoVMULHSU_VX_MF4, 0x3, false }, // 1754 |
1832 | | { PseudoVMULHSU_VX_MF8_MASK, PseudoVMULHSU_VX_MF8, 0x3, false }, // 1755 |
1833 | | { PseudoVMULHU_VV_M1_MASK, PseudoVMULHU_VV_M1, 0x3, false }, // 1756 |
1834 | | { PseudoVMULHU_VV_M2_MASK, PseudoVMULHU_VV_M2, 0x3, false }, // 1757 |
1835 | | { PseudoVMULHU_VV_M4_MASK, PseudoVMULHU_VV_M4, 0x3, false }, // 1758 |
1836 | | { PseudoVMULHU_VV_M8_MASK, PseudoVMULHU_VV_M8, 0x3, false }, // 1759 |
1837 | | { PseudoVMULHU_VV_MF2_MASK, PseudoVMULHU_VV_MF2, 0x3, false }, // 1760 |
1838 | | { PseudoVMULHU_VV_MF4_MASK, PseudoVMULHU_VV_MF4, 0x3, false }, // 1761 |
1839 | | { PseudoVMULHU_VV_MF8_MASK, PseudoVMULHU_VV_MF8, 0x3, false }, // 1762 |
1840 | | { PseudoVMULHU_VX_M1_MASK, PseudoVMULHU_VX_M1, 0x3, false }, // 1763 |
1841 | | { PseudoVMULHU_VX_M2_MASK, PseudoVMULHU_VX_M2, 0x3, false }, // 1764 |
1842 | | { PseudoVMULHU_VX_M4_MASK, PseudoVMULHU_VX_M4, 0x3, false }, // 1765 |
1843 | | { PseudoVMULHU_VX_M8_MASK, PseudoVMULHU_VX_M8, 0x3, false }, // 1766 |
1844 | | { PseudoVMULHU_VX_MF2_MASK, PseudoVMULHU_VX_MF2, 0x3, false }, // 1767 |
1845 | | { PseudoVMULHU_VX_MF4_MASK, PseudoVMULHU_VX_MF4, 0x3, false }, // 1768 |
1846 | | { PseudoVMULHU_VX_MF8_MASK, PseudoVMULHU_VX_MF8, 0x3, false }, // 1769 |
1847 | | { PseudoVMULH_VV_M1_MASK, PseudoVMULH_VV_M1, 0x3, false }, // 1770 |
1848 | | { PseudoVMULH_VV_M2_MASK, PseudoVMULH_VV_M2, 0x3, false }, // 1771 |
1849 | | { PseudoVMULH_VV_M4_MASK, PseudoVMULH_VV_M4, 0x3, false }, // 1772 |
1850 | | { PseudoVMULH_VV_M8_MASK, PseudoVMULH_VV_M8, 0x3, false }, // 1773 |
1851 | | { PseudoVMULH_VV_MF2_MASK, PseudoVMULH_VV_MF2, 0x3, false }, // 1774 |
1852 | | { PseudoVMULH_VV_MF4_MASK, PseudoVMULH_VV_MF4, 0x3, false }, // 1775 |
1853 | | { PseudoVMULH_VV_MF8_MASK, PseudoVMULH_VV_MF8, 0x3, false }, // 1776 |
1854 | | { PseudoVMULH_VX_M1_MASK, PseudoVMULH_VX_M1, 0x3, false }, // 1777 |
1855 | | { PseudoVMULH_VX_M2_MASK, PseudoVMULH_VX_M2, 0x3, false }, // 1778 |
1856 | | { PseudoVMULH_VX_M4_MASK, PseudoVMULH_VX_M4, 0x3, false }, // 1779 |
1857 | | { PseudoVMULH_VX_M8_MASK, PseudoVMULH_VX_M8, 0x3, false }, // 1780 |
1858 | | { PseudoVMULH_VX_MF2_MASK, PseudoVMULH_VX_MF2, 0x3, false }, // 1781 |
1859 | | { PseudoVMULH_VX_MF4_MASK, PseudoVMULH_VX_MF4, 0x3, false }, // 1782 |
1860 | | { PseudoVMULH_VX_MF8_MASK, PseudoVMULH_VX_MF8, 0x3, false }, // 1783 |
1861 | | { PseudoVMUL_VV_M1_MASK, PseudoVMUL_VV_M1, 0x3, false }, // 1784 |
1862 | | { PseudoVMUL_VV_M2_MASK, PseudoVMUL_VV_M2, 0x3, false }, // 1785 |
1863 | | { PseudoVMUL_VV_M4_MASK, PseudoVMUL_VV_M4, 0x3, false }, // 1786 |
1864 | | { PseudoVMUL_VV_M8_MASK, PseudoVMUL_VV_M8, 0x3, false }, // 1787 |
1865 | | { PseudoVMUL_VV_MF2_MASK, PseudoVMUL_VV_MF2, 0x3, false }, // 1788 |
1866 | | { PseudoVMUL_VV_MF4_MASK, PseudoVMUL_VV_MF4, 0x3, false }, // 1789 |
1867 | | { PseudoVMUL_VV_MF8_MASK, PseudoVMUL_VV_MF8, 0x3, false }, // 1790 |
1868 | | { PseudoVMUL_VX_M1_MASK, PseudoVMUL_VX_M1, 0x3, false }, // 1791 |
1869 | | { PseudoVMUL_VX_M2_MASK, PseudoVMUL_VX_M2, 0x3, false }, // 1792 |
1870 | | { PseudoVMUL_VX_M4_MASK, PseudoVMUL_VX_M4, 0x3, false }, // 1793 |
1871 | | { PseudoVMUL_VX_M8_MASK, PseudoVMUL_VX_M8, 0x3, false }, // 1794 |
1872 | | { PseudoVMUL_VX_MF2_MASK, PseudoVMUL_VX_MF2, 0x3, false }, // 1795 |
1873 | | { PseudoVMUL_VX_MF4_MASK, PseudoVMUL_VX_MF4, 0x3, false }, // 1796 |
1874 | | { PseudoVMUL_VX_MF8_MASK, PseudoVMUL_VX_MF8, 0x3, false }, // 1797 |
1875 | | { PseudoVNCLIPU_WI_M1_MASK, PseudoVNCLIPU_WI_M1, 0x3, false }, // 1798 |
1876 | | { PseudoVNCLIPU_WI_M2_MASK, PseudoVNCLIPU_WI_M2, 0x3, false }, // 1799 |
1877 | | { PseudoVNCLIPU_WI_M4_MASK, PseudoVNCLIPU_WI_M4, 0x3, false }, // 1800 |
1878 | | { PseudoVNCLIPU_WI_MF2_MASK, PseudoVNCLIPU_WI_MF2, 0x3, false }, // 1801 |
1879 | | { PseudoVNCLIPU_WI_MF4_MASK, PseudoVNCLIPU_WI_MF4, 0x3, false }, // 1802 |
1880 | | { PseudoVNCLIPU_WI_MF8_MASK, PseudoVNCLIPU_WI_MF8, 0x3, false }, // 1803 |
1881 | | { PseudoVNCLIPU_WV_M1_MASK, PseudoVNCLIPU_WV_M1, 0x3, false }, // 1804 |
1882 | | { PseudoVNCLIPU_WV_M2_MASK, PseudoVNCLIPU_WV_M2, 0x3, false }, // 1805 |
1883 | | { PseudoVNCLIPU_WV_M4_MASK, PseudoVNCLIPU_WV_M4, 0x3, false }, // 1806 |
1884 | | { PseudoVNCLIPU_WV_MF2_MASK, PseudoVNCLIPU_WV_MF2, 0x3, false }, // 1807 |
1885 | | { PseudoVNCLIPU_WV_MF4_MASK, PseudoVNCLIPU_WV_MF4, 0x3, false }, // 1808 |
1886 | | { PseudoVNCLIPU_WV_MF8_MASK, PseudoVNCLIPU_WV_MF8, 0x3, false }, // 1809 |
1887 | | { PseudoVNCLIPU_WX_M1_MASK, PseudoVNCLIPU_WX_M1, 0x3, false }, // 1810 |
1888 | | { PseudoVNCLIPU_WX_M2_MASK, PseudoVNCLIPU_WX_M2, 0x3, false }, // 1811 |
1889 | | { PseudoVNCLIPU_WX_M4_MASK, PseudoVNCLIPU_WX_M4, 0x3, false }, // 1812 |
1890 | | { PseudoVNCLIPU_WX_MF2_MASK, PseudoVNCLIPU_WX_MF2, 0x3, false }, // 1813 |
1891 | | { PseudoVNCLIPU_WX_MF4_MASK, PseudoVNCLIPU_WX_MF4, 0x3, false }, // 1814 |
1892 | | { PseudoVNCLIPU_WX_MF8_MASK, PseudoVNCLIPU_WX_MF8, 0x3, false }, // 1815 |
1893 | | { PseudoVNCLIP_WI_M1_MASK, PseudoVNCLIP_WI_M1, 0x3, false }, // 1816 |
1894 | | { PseudoVNCLIP_WI_M2_MASK, PseudoVNCLIP_WI_M2, 0x3, false }, // 1817 |
1895 | | { PseudoVNCLIP_WI_M4_MASK, PseudoVNCLIP_WI_M4, 0x3, false }, // 1818 |
1896 | | { PseudoVNCLIP_WI_MF2_MASK, PseudoVNCLIP_WI_MF2, 0x3, false }, // 1819 |
1897 | | { PseudoVNCLIP_WI_MF4_MASK, PseudoVNCLIP_WI_MF4, 0x3, false }, // 1820 |
1898 | | { PseudoVNCLIP_WI_MF8_MASK, PseudoVNCLIP_WI_MF8, 0x3, false }, // 1821 |
1899 | | { PseudoVNCLIP_WV_M1_MASK, PseudoVNCLIP_WV_M1, 0x3, false }, // 1822 |
1900 | | { PseudoVNCLIP_WV_M2_MASK, PseudoVNCLIP_WV_M2, 0x3, false }, // 1823 |
1901 | | { PseudoVNCLIP_WV_M4_MASK, PseudoVNCLIP_WV_M4, 0x3, false }, // 1824 |
1902 | | { PseudoVNCLIP_WV_MF2_MASK, PseudoVNCLIP_WV_MF2, 0x3, false }, // 1825 |
1903 | | { PseudoVNCLIP_WV_MF4_MASK, PseudoVNCLIP_WV_MF4, 0x3, false }, // 1826 |
1904 | | { PseudoVNCLIP_WV_MF8_MASK, PseudoVNCLIP_WV_MF8, 0x3, false }, // 1827 |
1905 | | { PseudoVNCLIP_WX_M1_MASK, PseudoVNCLIP_WX_M1, 0x3, false }, // 1828 |
1906 | | { PseudoVNCLIP_WX_M2_MASK, PseudoVNCLIP_WX_M2, 0x3, false }, // 1829 |
1907 | | { PseudoVNCLIP_WX_M4_MASK, PseudoVNCLIP_WX_M4, 0x3, false }, // 1830 |
1908 | | { PseudoVNCLIP_WX_MF2_MASK, PseudoVNCLIP_WX_MF2, 0x3, false }, // 1831 |
1909 | | { PseudoVNCLIP_WX_MF4_MASK, PseudoVNCLIP_WX_MF4, 0x3, false }, // 1832 |
1910 | | { PseudoVNCLIP_WX_MF8_MASK, PseudoVNCLIP_WX_MF8, 0x3, false }, // 1833 |
1911 | | { PseudoVNMSAC_VV_M1_MASK, PseudoVNMSAC_VV_M1, 0x3, false }, // 1834 |
1912 | | { PseudoVNMSAC_VV_M2_MASK, PseudoVNMSAC_VV_M2, 0x3, false }, // 1835 |
1913 | | { PseudoVNMSAC_VV_M4_MASK, PseudoVNMSAC_VV_M4, 0x3, false }, // 1836 |
1914 | | { PseudoVNMSAC_VV_M8_MASK, PseudoVNMSAC_VV_M8, 0x3, false }, // 1837 |
1915 | | { PseudoVNMSAC_VV_MF2_MASK, PseudoVNMSAC_VV_MF2, 0x3, false }, // 1838 |
1916 | | { PseudoVNMSAC_VV_MF4_MASK, PseudoVNMSAC_VV_MF4, 0x3, false }, // 1839 |
1917 | | { PseudoVNMSAC_VV_MF8_MASK, PseudoVNMSAC_VV_MF8, 0x3, false }, // 1840 |
1918 | | { PseudoVNMSAC_VX_M1_MASK, PseudoVNMSAC_VX_M1, 0x3, false }, // 1841 |
1919 | | { PseudoVNMSAC_VX_M2_MASK, PseudoVNMSAC_VX_M2, 0x3, false }, // 1842 |
1920 | | { PseudoVNMSAC_VX_M4_MASK, PseudoVNMSAC_VX_M4, 0x3, false }, // 1843 |
1921 | | { PseudoVNMSAC_VX_M8_MASK, PseudoVNMSAC_VX_M8, 0x3, false }, // 1844 |
1922 | | { PseudoVNMSAC_VX_MF2_MASK, PseudoVNMSAC_VX_MF2, 0x3, false }, // 1845 |
1923 | | { PseudoVNMSAC_VX_MF4_MASK, PseudoVNMSAC_VX_MF4, 0x3, false }, // 1846 |
1924 | | { PseudoVNMSAC_VX_MF8_MASK, PseudoVNMSAC_VX_MF8, 0x3, false }, // 1847 |
1925 | | { PseudoVNMSUB_VV_M1_MASK, PseudoVNMSUB_VV_M1, 0x3, false }, // 1848 |
1926 | | { PseudoVNMSUB_VV_M2_MASK, PseudoVNMSUB_VV_M2, 0x3, false }, // 1849 |
1927 | | { PseudoVNMSUB_VV_M4_MASK, PseudoVNMSUB_VV_M4, 0x3, false }, // 1850 |
1928 | | { PseudoVNMSUB_VV_M8_MASK, PseudoVNMSUB_VV_M8, 0x3, false }, // 1851 |
1929 | | { PseudoVNMSUB_VV_MF2_MASK, PseudoVNMSUB_VV_MF2, 0x3, false }, // 1852 |
1930 | | { PseudoVNMSUB_VV_MF4_MASK, PseudoVNMSUB_VV_MF4, 0x3, false }, // 1853 |
1931 | | { PseudoVNMSUB_VV_MF8_MASK, PseudoVNMSUB_VV_MF8, 0x3, false }, // 1854 |
1932 | | { PseudoVNMSUB_VX_M1_MASK, PseudoVNMSUB_VX_M1, 0x3, false }, // 1855 |
1933 | | { PseudoVNMSUB_VX_M2_MASK, PseudoVNMSUB_VX_M2, 0x3, false }, // 1856 |
1934 | | { PseudoVNMSUB_VX_M4_MASK, PseudoVNMSUB_VX_M4, 0x3, false }, // 1857 |
1935 | | { PseudoVNMSUB_VX_M8_MASK, PseudoVNMSUB_VX_M8, 0x3, false }, // 1858 |
1936 | | { PseudoVNMSUB_VX_MF2_MASK, PseudoVNMSUB_VX_MF2, 0x3, false }, // 1859 |
1937 | | { PseudoVNMSUB_VX_MF4_MASK, PseudoVNMSUB_VX_MF4, 0x3, false }, // 1860 |
1938 | | { PseudoVNMSUB_VX_MF8_MASK, PseudoVNMSUB_VX_MF8, 0x3, false }, // 1861 |
1939 | | { PseudoVNSRA_WI_M1_MASK, PseudoVNSRA_WI_M1, 0x3, false }, // 1862 |
1940 | | { PseudoVNSRA_WI_M2_MASK, PseudoVNSRA_WI_M2, 0x3, false }, // 1863 |
1941 | | { PseudoVNSRA_WI_M4_MASK, PseudoVNSRA_WI_M4, 0x3, false }, // 1864 |
1942 | | { PseudoVNSRA_WI_MF2_MASK, PseudoVNSRA_WI_MF2, 0x3, false }, // 1865 |
1943 | | { PseudoVNSRA_WI_MF4_MASK, PseudoVNSRA_WI_MF4, 0x3, false }, // 1866 |
1944 | | { PseudoVNSRA_WI_MF8_MASK, PseudoVNSRA_WI_MF8, 0x3, false }, // 1867 |
1945 | | { PseudoVNSRA_WV_M1_MASK, PseudoVNSRA_WV_M1, 0x3, false }, // 1868 |
1946 | | { PseudoVNSRA_WV_M2_MASK, PseudoVNSRA_WV_M2, 0x3, false }, // 1869 |
1947 | | { PseudoVNSRA_WV_M4_MASK, PseudoVNSRA_WV_M4, 0x3, false }, // 1870 |
1948 | | { PseudoVNSRA_WV_MF2_MASK, PseudoVNSRA_WV_MF2, 0x3, false }, // 1871 |
1949 | | { PseudoVNSRA_WV_MF4_MASK, PseudoVNSRA_WV_MF4, 0x3, false }, // 1872 |
1950 | | { PseudoVNSRA_WV_MF8_MASK, PseudoVNSRA_WV_MF8, 0x3, false }, // 1873 |
1951 | | { PseudoVNSRA_WX_M1_MASK, PseudoVNSRA_WX_M1, 0x3, false }, // 1874 |
1952 | | { PseudoVNSRA_WX_M2_MASK, PseudoVNSRA_WX_M2, 0x3, false }, // 1875 |
1953 | | { PseudoVNSRA_WX_M4_MASK, PseudoVNSRA_WX_M4, 0x3, false }, // 1876 |
1954 | | { PseudoVNSRA_WX_MF2_MASK, PseudoVNSRA_WX_MF2, 0x3, false }, // 1877 |
1955 | | { PseudoVNSRA_WX_MF4_MASK, PseudoVNSRA_WX_MF4, 0x3, false }, // 1878 |
1956 | | { PseudoVNSRA_WX_MF8_MASK, PseudoVNSRA_WX_MF8, 0x3, false }, // 1879 |
1957 | | { PseudoVNSRL_WI_M1_MASK, PseudoVNSRL_WI_M1, 0x3, false }, // 1880 |
1958 | | { PseudoVNSRL_WI_M2_MASK, PseudoVNSRL_WI_M2, 0x3, false }, // 1881 |
1959 | | { PseudoVNSRL_WI_M4_MASK, PseudoVNSRL_WI_M4, 0x3, false }, // 1882 |
1960 | | { PseudoVNSRL_WI_MF2_MASK, PseudoVNSRL_WI_MF2, 0x3, false }, // 1883 |
1961 | | { PseudoVNSRL_WI_MF4_MASK, PseudoVNSRL_WI_MF4, 0x3, false }, // 1884 |
1962 | | { PseudoVNSRL_WI_MF8_MASK, PseudoVNSRL_WI_MF8, 0x3, false }, // 1885 |
1963 | | { PseudoVNSRL_WV_M1_MASK, PseudoVNSRL_WV_M1, 0x3, false }, // 1886 |
1964 | | { PseudoVNSRL_WV_M2_MASK, PseudoVNSRL_WV_M2, 0x3, false }, // 1887 |
1965 | | { PseudoVNSRL_WV_M4_MASK, PseudoVNSRL_WV_M4, 0x3, false }, // 1888 |
1966 | | { PseudoVNSRL_WV_MF2_MASK, PseudoVNSRL_WV_MF2, 0x3, false }, // 1889 |
1967 | | { PseudoVNSRL_WV_MF4_MASK, PseudoVNSRL_WV_MF4, 0x3, false }, // 1890 |
1968 | | { PseudoVNSRL_WV_MF8_MASK, PseudoVNSRL_WV_MF8, 0x3, false }, // 1891 |
1969 | | { PseudoVNSRL_WX_M1_MASK, PseudoVNSRL_WX_M1, 0x3, false }, // 1892 |
1970 | | { PseudoVNSRL_WX_M2_MASK, PseudoVNSRL_WX_M2, 0x3, false }, // 1893 |
1971 | | { PseudoVNSRL_WX_M4_MASK, PseudoVNSRL_WX_M4, 0x3, false }, // 1894 |
1972 | | { PseudoVNSRL_WX_MF2_MASK, PseudoVNSRL_WX_MF2, 0x3, false }, // 1895 |
1973 | | { PseudoVNSRL_WX_MF4_MASK, PseudoVNSRL_WX_MF4, 0x3, false }, // 1896 |
1974 | | { PseudoVNSRL_WX_MF8_MASK, PseudoVNSRL_WX_MF8, 0x3, false }, // 1897 |
1975 | | { PseudoVOR_VI_M1_MASK, PseudoVOR_VI_M1, 0x3, false }, // 1898 |
1976 | | { PseudoVOR_VI_M2_MASK, PseudoVOR_VI_M2, 0x3, false }, // 1899 |
1977 | | { PseudoVOR_VI_M4_MASK, PseudoVOR_VI_M4, 0x3, false }, // 1900 |
1978 | | { PseudoVOR_VI_M8_MASK, PseudoVOR_VI_M8, 0x3, false }, // 1901 |
1979 | | { PseudoVOR_VI_MF2_MASK, PseudoVOR_VI_MF2, 0x3, false }, // 1902 |
1980 | | { PseudoVOR_VI_MF4_MASK, PseudoVOR_VI_MF4, 0x3, false }, // 1903 |
1981 | | { PseudoVOR_VI_MF8_MASK, PseudoVOR_VI_MF8, 0x3, false }, // 1904 |
1982 | | { PseudoVOR_VV_M1_MASK, PseudoVOR_VV_M1, 0x3, false }, // 1905 |
1983 | | { PseudoVOR_VV_M2_MASK, PseudoVOR_VV_M2, 0x3, false }, // 1906 |
1984 | | { PseudoVOR_VV_M4_MASK, PseudoVOR_VV_M4, 0x3, false }, // 1907 |
1985 | | { PseudoVOR_VV_M8_MASK, PseudoVOR_VV_M8, 0x3, false }, // 1908 |
1986 | | { PseudoVOR_VV_MF2_MASK, PseudoVOR_VV_MF2, 0x3, false }, // 1909 |
1987 | | { PseudoVOR_VV_MF4_MASK, PseudoVOR_VV_MF4, 0x3, false }, // 1910 |
1988 | | { PseudoVOR_VV_MF8_MASK, PseudoVOR_VV_MF8, 0x3, false }, // 1911 |
1989 | | { PseudoVOR_VX_M1_MASK, PseudoVOR_VX_M1, 0x3, false }, // 1912 |
1990 | | { PseudoVOR_VX_M2_MASK, PseudoVOR_VX_M2, 0x3, false }, // 1913 |
1991 | | { PseudoVOR_VX_M4_MASK, PseudoVOR_VX_M4, 0x3, false }, // 1914 |
1992 | | { PseudoVOR_VX_M8_MASK, PseudoVOR_VX_M8, 0x3, false }, // 1915 |
1993 | | { PseudoVOR_VX_MF2_MASK, PseudoVOR_VX_MF2, 0x3, false }, // 1916 |
1994 | | { PseudoVOR_VX_MF4_MASK, PseudoVOR_VX_MF4, 0x3, false }, // 1917 |
1995 | | { PseudoVOR_VX_MF8_MASK, PseudoVOR_VX_MF8, 0x3, false }, // 1918 |
1996 | | { PseudoVREDAND_VS_M1_E16_MASK, PseudoVREDAND_VS_M1_E16, 0x3, true }, // 1919 |
1997 | | { PseudoVREDAND_VS_M1_E32_MASK, PseudoVREDAND_VS_M1_E32, 0x3, true }, // 1920 |
1998 | | { PseudoVREDAND_VS_M1_E64_MASK, PseudoVREDAND_VS_M1_E64, 0x3, true }, // 1921 |
1999 | | { PseudoVREDAND_VS_M1_E8_MASK, PseudoVREDAND_VS_M1_E8, 0x3, true }, // 1922 |
2000 | | { PseudoVREDAND_VS_M2_E16_MASK, PseudoVREDAND_VS_M2_E16, 0x3, true }, // 1923 |
2001 | | { PseudoVREDAND_VS_M2_E32_MASK, PseudoVREDAND_VS_M2_E32, 0x3, true }, // 1924 |
2002 | | { PseudoVREDAND_VS_M2_E64_MASK, PseudoVREDAND_VS_M2_E64, 0x3, true }, // 1925 |
2003 | | { PseudoVREDAND_VS_M2_E8_MASK, PseudoVREDAND_VS_M2_E8, 0x3, true }, // 1926 |
2004 | | { PseudoVREDAND_VS_M4_E16_MASK, PseudoVREDAND_VS_M4_E16, 0x3, true }, // 1927 |
2005 | | { PseudoVREDAND_VS_M4_E32_MASK, PseudoVREDAND_VS_M4_E32, 0x3, true }, // 1928 |
2006 | | { PseudoVREDAND_VS_M4_E64_MASK, PseudoVREDAND_VS_M4_E64, 0x3, true }, // 1929 |
2007 | | { PseudoVREDAND_VS_M4_E8_MASK, PseudoVREDAND_VS_M4_E8, 0x3, true }, // 1930 |
2008 | | { PseudoVREDAND_VS_M8_E16_MASK, PseudoVREDAND_VS_M8_E16, 0x3, true }, // 1931 |
2009 | | { PseudoVREDAND_VS_M8_E32_MASK, PseudoVREDAND_VS_M8_E32, 0x3, true }, // 1932 |
2010 | | { PseudoVREDAND_VS_M8_E64_MASK, PseudoVREDAND_VS_M8_E64, 0x3, true }, // 1933 |
2011 | | { PseudoVREDAND_VS_M8_E8_MASK, PseudoVREDAND_VS_M8_E8, 0x3, true }, // 1934 |
2012 | | { PseudoVREDAND_VS_MF2_E16_MASK, PseudoVREDAND_VS_MF2_E16, 0x3, true }, // 1935 |
2013 | | { PseudoVREDAND_VS_MF2_E32_MASK, PseudoVREDAND_VS_MF2_E32, 0x3, true }, // 1936 |
2014 | | { PseudoVREDAND_VS_MF2_E8_MASK, PseudoVREDAND_VS_MF2_E8, 0x3, true }, // 1937 |
2015 | | { PseudoVREDAND_VS_MF4_E16_MASK, PseudoVREDAND_VS_MF4_E16, 0x3, true }, // 1938 |
2016 | | { PseudoVREDAND_VS_MF4_E8_MASK, PseudoVREDAND_VS_MF4_E8, 0x3, true }, // 1939 |
2017 | | { PseudoVREDAND_VS_MF8_E8_MASK, PseudoVREDAND_VS_MF8_E8, 0x3, true }, // 1940 |
2018 | | { PseudoVREDMAXU_VS_M1_E16_MASK, PseudoVREDMAXU_VS_M1_E16, 0x3, true }, // 1941 |
2019 | | { PseudoVREDMAXU_VS_M1_E32_MASK, PseudoVREDMAXU_VS_M1_E32, 0x3, true }, // 1942 |
2020 | | { PseudoVREDMAXU_VS_M1_E64_MASK, PseudoVREDMAXU_VS_M1_E64, 0x3, true }, // 1943 |
2021 | | { PseudoVREDMAXU_VS_M1_E8_MASK, PseudoVREDMAXU_VS_M1_E8, 0x3, true }, // 1944 |
2022 | | { PseudoVREDMAXU_VS_M2_E16_MASK, PseudoVREDMAXU_VS_M2_E16, 0x3, true }, // 1945 |
2023 | | { PseudoVREDMAXU_VS_M2_E32_MASK, PseudoVREDMAXU_VS_M2_E32, 0x3, true }, // 1946 |
2024 | | { PseudoVREDMAXU_VS_M2_E64_MASK, PseudoVREDMAXU_VS_M2_E64, 0x3, true }, // 1947 |
2025 | | { PseudoVREDMAXU_VS_M2_E8_MASK, PseudoVREDMAXU_VS_M2_E8, 0x3, true }, // 1948 |
2026 | | { PseudoVREDMAXU_VS_M4_E16_MASK, PseudoVREDMAXU_VS_M4_E16, 0x3, true }, // 1949 |
2027 | | { PseudoVREDMAXU_VS_M4_E32_MASK, PseudoVREDMAXU_VS_M4_E32, 0x3, true }, // 1950 |
2028 | | { PseudoVREDMAXU_VS_M4_E64_MASK, PseudoVREDMAXU_VS_M4_E64, 0x3, true }, // 1951 |
2029 | | { PseudoVREDMAXU_VS_M4_E8_MASK, PseudoVREDMAXU_VS_M4_E8, 0x3, true }, // 1952 |
2030 | | { PseudoVREDMAXU_VS_M8_E16_MASK, PseudoVREDMAXU_VS_M8_E16, 0x3, true }, // 1953 |
2031 | | { PseudoVREDMAXU_VS_M8_E32_MASK, PseudoVREDMAXU_VS_M8_E32, 0x3, true }, // 1954 |
2032 | | { PseudoVREDMAXU_VS_M8_E64_MASK, PseudoVREDMAXU_VS_M8_E64, 0x3, true }, // 1955 |
2033 | | { PseudoVREDMAXU_VS_M8_E8_MASK, PseudoVREDMAXU_VS_M8_E8, 0x3, true }, // 1956 |
2034 | | { PseudoVREDMAXU_VS_MF2_E16_MASK, PseudoVREDMAXU_VS_MF2_E16, 0x3, true }, // 1957 |
2035 | | { PseudoVREDMAXU_VS_MF2_E32_MASK, PseudoVREDMAXU_VS_MF2_E32, 0x3, true }, // 1958 |
2036 | | { PseudoVREDMAXU_VS_MF2_E8_MASK, PseudoVREDMAXU_VS_MF2_E8, 0x3, true }, // 1959 |
2037 | | { PseudoVREDMAXU_VS_MF4_E16_MASK, PseudoVREDMAXU_VS_MF4_E16, 0x3, true }, // 1960 |
2038 | | { PseudoVREDMAXU_VS_MF4_E8_MASK, PseudoVREDMAXU_VS_MF4_E8, 0x3, true }, // 1961 |
2039 | | { PseudoVREDMAXU_VS_MF8_E8_MASK, PseudoVREDMAXU_VS_MF8_E8, 0x3, true }, // 1962 |
2040 | | { PseudoVREDMAX_VS_M1_E16_MASK, PseudoVREDMAX_VS_M1_E16, 0x3, true }, // 1963 |
2041 | | { PseudoVREDMAX_VS_M1_E32_MASK, PseudoVREDMAX_VS_M1_E32, 0x3, true }, // 1964 |
2042 | | { PseudoVREDMAX_VS_M1_E64_MASK, PseudoVREDMAX_VS_M1_E64, 0x3, true }, // 1965 |
2043 | | { PseudoVREDMAX_VS_M1_E8_MASK, PseudoVREDMAX_VS_M1_E8, 0x3, true }, // 1966 |
2044 | | { PseudoVREDMAX_VS_M2_E16_MASK, PseudoVREDMAX_VS_M2_E16, 0x3, true }, // 1967 |
2045 | | { PseudoVREDMAX_VS_M2_E32_MASK, PseudoVREDMAX_VS_M2_E32, 0x3, true }, // 1968 |
2046 | | { PseudoVREDMAX_VS_M2_E64_MASK, PseudoVREDMAX_VS_M2_E64, 0x3, true }, // 1969 |
2047 | | { PseudoVREDMAX_VS_M2_E8_MASK, PseudoVREDMAX_VS_M2_E8, 0x3, true }, // 1970 |
2048 | | { PseudoVREDMAX_VS_M4_E16_MASK, PseudoVREDMAX_VS_M4_E16, 0x3, true }, // 1971 |
2049 | | { PseudoVREDMAX_VS_M4_E32_MASK, PseudoVREDMAX_VS_M4_E32, 0x3, true }, // 1972 |
2050 | | { PseudoVREDMAX_VS_M4_E64_MASK, PseudoVREDMAX_VS_M4_E64, 0x3, true }, // 1973 |
2051 | | { PseudoVREDMAX_VS_M4_E8_MASK, PseudoVREDMAX_VS_M4_E8, 0x3, true }, // 1974 |
2052 | | { PseudoVREDMAX_VS_M8_E16_MASK, PseudoVREDMAX_VS_M8_E16, 0x3, true }, // 1975 |
2053 | | { PseudoVREDMAX_VS_M8_E32_MASK, PseudoVREDMAX_VS_M8_E32, 0x3, true }, // 1976 |
2054 | | { PseudoVREDMAX_VS_M8_E64_MASK, PseudoVREDMAX_VS_M8_E64, 0x3, true }, // 1977 |
2055 | | { PseudoVREDMAX_VS_M8_E8_MASK, PseudoVREDMAX_VS_M8_E8, 0x3, true }, // 1978 |
2056 | | { PseudoVREDMAX_VS_MF2_E16_MASK, PseudoVREDMAX_VS_MF2_E16, 0x3, true }, // 1979 |
2057 | | { PseudoVREDMAX_VS_MF2_E32_MASK, PseudoVREDMAX_VS_MF2_E32, 0x3, true }, // 1980 |
2058 | | { PseudoVREDMAX_VS_MF2_E8_MASK, PseudoVREDMAX_VS_MF2_E8, 0x3, true }, // 1981 |
2059 | | { PseudoVREDMAX_VS_MF4_E16_MASK, PseudoVREDMAX_VS_MF4_E16, 0x3, true }, // 1982 |
2060 | | { PseudoVREDMAX_VS_MF4_E8_MASK, PseudoVREDMAX_VS_MF4_E8, 0x3, true }, // 1983 |
2061 | | { PseudoVREDMAX_VS_MF8_E8_MASK, PseudoVREDMAX_VS_MF8_E8, 0x3, true }, // 1984 |
2062 | | { PseudoVREDMINU_VS_M1_E16_MASK, PseudoVREDMINU_VS_M1_E16, 0x3, true }, // 1985 |
2063 | | { PseudoVREDMINU_VS_M1_E32_MASK, PseudoVREDMINU_VS_M1_E32, 0x3, true }, // 1986 |
2064 | | { PseudoVREDMINU_VS_M1_E64_MASK, PseudoVREDMINU_VS_M1_E64, 0x3, true }, // 1987 |
2065 | | { PseudoVREDMINU_VS_M1_E8_MASK, PseudoVREDMINU_VS_M1_E8, 0x3, true }, // 1988 |
2066 | | { PseudoVREDMINU_VS_M2_E16_MASK, PseudoVREDMINU_VS_M2_E16, 0x3, true }, // 1989 |
2067 | | { PseudoVREDMINU_VS_M2_E32_MASK, PseudoVREDMINU_VS_M2_E32, 0x3, true }, // 1990 |
2068 | | { PseudoVREDMINU_VS_M2_E64_MASK, PseudoVREDMINU_VS_M2_E64, 0x3, true }, // 1991 |
2069 | | { PseudoVREDMINU_VS_M2_E8_MASK, PseudoVREDMINU_VS_M2_E8, 0x3, true }, // 1992 |
2070 | | { PseudoVREDMINU_VS_M4_E16_MASK, PseudoVREDMINU_VS_M4_E16, 0x3, true }, // 1993 |
2071 | | { PseudoVREDMINU_VS_M4_E32_MASK, PseudoVREDMINU_VS_M4_E32, 0x3, true }, // 1994 |
2072 | | { PseudoVREDMINU_VS_M4_E64_MASK, PseudoVREDMINU_VS_M4_E64, 0x3, true }, // 1995 |
2073 | | { PseudoVREDMINU_VS_M4_E8_MASK, PseudoVREDMINU_VS_M4_E8, 0x3, true }, // 1996 |
2074 | | { PseudoVREDMINU_VS_M8_E16_MASK, PseudoVREDMINU_VS_M8_E16, 0x3, true }, // 1997 |
2075 | | { PseudoVREDMINU_VS_M8_E32_MASK, PseudoVREDMINU_VS_M8_E32, 0x3, true }, // 1998 |
2076 | | { PseudoVREDMINU_VS_M8_E64_MASK, PseudoVREDMINU_VS_M8_E64, 0x3, true }, // 1999 |
2077 | | { PseudoVREDMINU_VS_M8_E8_MASK, PseudoVREDMINU_VS_M8_E8, 0x3, true }, // 2000 |
2078 | | { PseudoVREDMINU_VS_MF2_E16_MASK, PseudoVREDMINU_VS_MF2_E16, 0x3, true }, // 2001 |
2079 | | { PseudoVREDMINU_VS_MF2_E32_MASK, PseudoVREDMINU_VS_MF2_E32, 0x3, true }, // 2002 |
2080 | | { PseudoVREDMINU_VS_MF2_E8_MASK, PseudoVREDMINU_VS_MF2_E8, 0x3, true }, // 2003 |
2081 | | { PseudoVREDMINU_VS_MF4_E16_MASK, PseudoVREDMINU_VS_MF4_E16, 0x3, true }, // 2004 |
2082 | | { PseudoVREDMINU_VS_MF4_E8_MASK, PseudoVREDMINU_VS_MF4_E8, 0x3, true }, // 2005 |
2083 | | { PseudoVREDMINU_VS_MF8_E8_MASK, PseudoVREDMINU_VS_MF8_E8, 0x3, true }, // 2006 |
2084 | | { PseudoVREDMIN_VS_M1_E16_MASK, PseudoVREDMIN_VS_M1_E16, 0x3, true }, // 2007 |
2085 | | { PseudoVREDMIN_VS_M1_E32_MASK, PseudoVREDMIN_VS_M1_E32, 0x3, true }, // 2008 |
2086 | | { PseudoVREDMIN_VS_M1_E64_MASK, PseudoVREDMIN_VS_M1_E64, 0x3, true }, // 2009 |
2087 | | { PseudoVREDMIN_VS_M1_E8_MASK, PseudoVREDMIN_VS_M1_E8, 0x3, true }, // 2010 |
2088 | | { PseudoVREDMIN_VS_M2_E16_MASK, PseudoVREDMIN_VS_M2_E16, 0x3, true }, // 2011 |
2089 | | { PseudoVREDMIN_VS_M2_E32_MASK, PseudoVREDMIN_VS_M2_E32, 0x3, true }, // 2012 |
2090 | | { PseudoVREDMIN_VS_M2_E64_MASK, PseudoVREDMIN_VS_M2_E64, 0x3, true }, // 2013 |
2091 | | { PseudoVREDMIN_VS_M2_E8_MASK, PseudoVREDMIN_VS_M2_E8, 0x3, true }, // 2014 |
2092 | | { PseudoVREDMIN_VS_M4_E16_MASK, PseudoVREDMIN_VS_M4_E16, 0x3, true }, // 2015 |
2093 | | { PseudoVREDMIN_VS_M4_E32_MASK, PseudoVREDMIN_VS_M4_E32, 0x3, true }, // 2016 |
2094 | | { PseudoVREDMIN_VS_M4_E64_MASK, PseudoVREDMIN_VS_M4_E64, 0x3, true }, // 2017 |
2095 | | { PseudoVREDMIN_VS_M4_E8_MASK, PseudoVREDMIN_VS_M4_E8, 0x3, true }, // 2018 |
2096 | | { PseudoVREDMIN_VS_M8_E16_MASK, PseudoVREDMIN_VS_M8_E16, 0x3, true }, // 2019 |
2097 | | { PseudoVREDMIN_VS_M8_E32_MASK, PseudoVREDMIN_VS_M8_E32, 0x3, true }, // 2020 |
2098 | | { PseudoVREDMIN_VS_M8_E64_MASK, PseudoVREDMIN_VS_M8_E64, 0x3, true }, // 2021 |
2099 | | { PseudoVREDMIN_VS_M8_E8_MASK, PseudoVREDMIN_VS_M8_E8, 0x3, true }, // 2022 |
2100 | | { PseudoVREDMIN_VS_MF2_E16_MASK, PseudoVREDMIN_VS_MF2_E16, 0x3, true }, // 2023 |
2101 | | { PseudoVREDMIN_VS_MF2_E32_MASK, PseudoVREDMIN_VS_MF2_E32, 0x3, true }, // 2024 |
2102 | | { PseudoVREDMIN_VS_MF2_E8_MASK, PseudoVREDMIN_VS_MF2_E8, 0x3, true }, // 2025 |
2103 | | { PseudoVREDMIN_VS_MF4_E16_MASK, PseudoVREDMIN_VS_MF4_E16, 0x3, true }, // 2026 |
2104 | | { PseudoVREDMIN_VS_MF4_E8_MASK, PseudoVREDMIN_VS_MF4_E8, 0x3, true }, // 2027 |
2105 | | { PseudoVREDMIN_VS_MF8_E8_MASK, PseudoVREDMIN_VS_MF8_E8, 0x3, true }, // 2028 |
2106 | | { PseudoVREDOR_VS_M1_E16_MASK, PseudoVREDOR_VS_M1_E16, 0x3, true }, // 2029 |
2107 | | { PseudoVREDOR_VS_M1_E32_MASK, PseudoVREDOR_VS_M1_E32, 0x3, true }, // 2030 |
2108 | | { PseudoVREDOR_VS_M1_E64_MASK, PseudoVREDOR_VS_M1_E64, 0x3, true }, // 2031 |
2109 | | { PseudoVREDOR_VS_M1_E8_MASK, PseudoVREDOR_VS_M1_E8, 0x3, true }, // 2032 |
2110 | | { PseudoVREDOR_VS_M2_E16_MASK, PseudoVREDOR_VS_M2_E16, 0x3, true }, // 2033 |
2111 | | { PseudoVREDOR_VS_M2_E32_MASK, PseudoVREDOR_VS_M2_E32, 0x3, true }, // 2034 |
2112 | | { PseudoVREDOR_VS_M2_E64_MASK, PseudoVREDOR_VS_M2_E64, 0x3, true }, // 2035 |
2113 | | { PseudoVREDOR_VS_M2_E8_MASK, PseudoVREDOR_VS_M2_E8, 0x3, true }, // 2036 |
2114 | | { PseudoVREDOR_VS_M4_E16_MASK, PseudoVREDOR_VS_M4_E16, 0x3, true }, // 2037 |
2115 | | { PseudoVREDOR_VS_M4_E32_MASK, PseudoVREDOR_VS_M4_E32, 0x3, true }, // 2038 |
2116 | | { PseudoVREDOR_VS_M4_E64_MASK, PseudoVREDOR_VS_M4_E64, 0x3, true }, // 2039 |
2117 | | { PseudoVREDOR_VS_M4_E8_MASK, PseudoVREDOR_VS_M4_E8, 0x3, true }, // 2040 |
2118 | | { PseudoVREDOR_VS_M8_E16_MASK, PseudoVREDOR_VS_M8_E16, 0x3, true }, // 2041 |
2119 | | { PseudoVREDOR_VS_M8_E32_MASK, PseudoVREDOR_VS_M8_E32, 0x3, true }, // 2042 |
2120 | | { PseudoVREDOR_VS_M8_E64_MASK, PseudoVREDOR_VS_M8_E64, 0x3, true }, // 2043 |
2121 | | { PseudoVREDOR_VS_M8_E8_MASK, PseudoVREDOR_VS_M8_E8, 0x3, true }, // 2044 |
2122 | | { PseudoVREDOR_VS_MF2_E16_MASK, PseudoVREDOR_VS_MF2_E16, 0x3, true }, // 2045 |
2123 | | { PseudoVREDOR_VS_MF2_E32_MASK, PseudoVREDOR_VS_MF2_E32, 0x3, true }, // 2046 |
2124 | | { PseudoVREDOR_VS_MF2_E8_MASK, PseudoVREDOR_VS_MF2_E8, 0x3, true }, // 2047 |
2125 | | { PseudoVREDOR_VS_MF4_E16_MASK, PseudoVREDOR_VS_MF4_E16, 0x3, true }, // 2048 |
2126 | | { PseudoVREDOR_VS_MF4_E8_MASK, PseudoVREDOR_VS_MF4_E8, 0x3, true }, // 2049 |
2127 | | { PseudoVREDOR_VS_MF8_E8_MASK, PseudoVREDOR_VS_MF8_E8, 0x3, true }, // 2050 |
2128 | | { PseudoVREDSUM_VS_M1_E16_MASK, PseudoVREDSUM_VS_M1_E16, 0x3, true }, // 2051 |
2129 | | { PseudoVREDSUM_VS_M1_E32_MASK, PseudoVREDSUM_VS_M1_E32, 0x3, true }, // 2052 |
2130 | | { PseudoVREDSUM_VS_M1_E64_MASK, PseudoVREDSUM_VS_M1_E64, 0x3, true }, // 2053 |
2131 | | { PseudoVREDSUM_VS_M1_E8_MASK, PseudoVREDSUM_VS_M1_E8, 0x3, true }, // 2054 |
2132 | | { PseudoVREDSUM_VS_M2_E16_MASK, PseudoVREDSUM_VS_M2_E16, 0x3, true }, // 2055 |
2133 | | { PseudoVREDSUM_VS_M2_E32_MASK, PseudoVREDSUM_VS_M2_E32, 0x3, true }, // 2056 |
2134 | | { PseudoVREDSUM_VS_M2_E64_MASK, PseudoVREDSUM_VS_M2_E64, 0x3, true }, // 2057 |
2135 | | { PseudoVREDSUM_VS_M2_E8_MASK, PseudoVREDSUM_VS_M2_E8, 0x3, true }, // 2058 |
2136 | | { PseudoVREDSUM_VS_M4_E16_MASK, PseudoVREDSUM_VS_M4_E16, 0x3, true }, // 2059 |
2137 | | { PseudoVREDSUM_VS_M4_E32_MASK, PseudoVREDSUM_VS_M4_E32, 0x3, true }, // 2060 |
2138 | | { PseudoVREDSUM_VS_M4_E64_MASK, PseudoVREDSUM_VS_M4_E64, 0x3, true }, // 2061 |
2139 | | { PseudoVREDSUM_VS_M4_E8_MASK, PseudoVREDSUM_VS_M4_E8, 0x3, true }, // 2062 |
2140 | | { PseudoVREDSUM_VS_M8_E16_MASK, PseudoVREDSUM_VS_M8_E16, 0x3, true }, // 2063 |
2141 | | { PseudoVREDSUM_VS_M8_E32_MASK, PseudoVREDSUM_VS_M8_E32, 0x3, true }, // 2064 |
2142 | | { PseudoVREDSUM_VS_M8_E64_MASK, PseudoVREDSUM_VS_M8_E64, 0x3, true }, // 2065 |
2143 | | { PseudoVREDSUM_VS_M8_E8_MASK, PseudoVREDSUM_VS_M8_E8, 0x3, true }, // 2066 |
2144 | | { PseudoVREDSUM_VS_MF2_E16_MASK, PseudoVREDSUM_VS_MF2_E16, 0x3, true }, // 2067 |
2145 | | { PseudoVREDSUM_VS_MF2_E32_MASK, PseudoVREDSUM_VS_MF2_E32, 0x3, true }, // 2068 |
2146 | | { PseudoVREDSUM_VS_MF2_E8_MASK, PseudoVREDSUM_VS_MF2_E8, 0x3, true }, // 2069 |
2147 | | { PseudoVREDSUM_VS_MF4_E16_MASK, PseudoVREDSUM_VS_MF4_E16, 0x3, true }, // 2070 |
2148 | | { PseudoVREDSUM_VS_MF4_E8_MASK, PseudoVREDSUM_VS_MF4_E8, 0x3, true }, // 2071 |
2149 | | { PseudoVREDSUM_VS_MF8_E8_MASK, PseudoVREDSUM_VS_MF8_E8, 0x3, true }, // 2072 |
2150 | | { PseudoVREDXOR_VS_M1_E16_MASK, PseudoVREDXOR_VS_M1_E16, 0x3, true }, // 2073 |
2151 | | { PseudoVREDXOR_VS_M1_E32_MASK, PseudoVREDXOR_VS_M1_E32, 0x3, true }, // 2074 |
2152 | | { PseudoVREDXOR_VS_M1_E64_MASK, PseudoVREDXOR_VS_M1_E64, 0x3, true }, // 2075 |
2153 | | { PseudoVREDXOR_VS_M1_E8_MASK, PseudoVREDXOR_VS_M1_E8, 0x3, true }, // 2076 |
2154 | | { PseudoVREDXOR_VS_M2_E16_MASK, PseudoVREDXOR_VS_M2_E16, 0x3, true }, // 2077 |
2155 | | { PseudoVREDXOR_VS_M2_E32_MASK, PseudoVREDXOR_VS_M2_E32, 0x3, true }, // 2078 |
2156 | | { PseudoVREDXOR_VS_M2_E64_MASK, PseudoVREDXOR_VS_M2_E64, 0x3, true }, // 2079 |
2157 | | { PseudoVREDXOR_VS_M2_E8_MASK, PseudoVREDXOR_VS_M2_E8, 0x3, true }, // 2080 |
2158 | | { PseudoVREDXOR_VS_M4_E16_MASK, PseudoVREDXOR_VS_M4_E16, 0x3, true }, // 2081 |
2159 | | { PseudoVREDXOR_VS_M4_E32_MASK, PseudoVREDXOR_VS_M4_E32, 0x3, true }, // 2082 |
2160 | | { PseudoVREDXOR_VS_M4_E64_MASK, PseudoVREDXOR_VS_M4_E64, 0x3, true }, // 2083 |
2161 | | { PseudoVREDXOR_VS_M4_E8_MASK, PseudoVREDXOR_VS_M4_E8, 0x3, true }, // 2084 |
2162 | | { PseudoVREDXOR_VS_M8_E16_MASK, PseudoVREDXOR_VS_M8_E16, 0x3, true }, // 2085 |
2163 | | { PseudoVREDXOR_VS_M8_E32_MASK, PseudoVREDXOR_VS_M8_E32, 0x3, true }, // 2086 |
2164 | | { PseudoVREDXOR_VS_M8_E64_MASK, PseudoVREDXOR_VS_M8_E64, 0x3, true }, // 2087 |
2165 | | { PseudoVREDXOR_VS_M8_E8_MASK, PseudoVREDXOR_VS_M8_E8, 0x3, true }, // 2088 |
2166 | | { PseudoVREDXOR_VS_MF2_E16_MASK, PseudoVREDXOR_VS_MF2_E16, 0x3, true }, // 2089 |
2167 | | { PseudoVREDXOR_VS_MF2_E32_MASK, PseudoVREDXOR_VS_MF2_E32, 0x3, true }, // 2090 |
2168 | | { PseudoVREDXOR_VS_MF2_E8_MASK, PseudoVREDXOR_VS_MF2_E8, 0x3, true }, // 2091 |
2169 | | { PseudoVREDXOR_VS_MF4_E16_MASK, PseudoVREDXOR_VS_MF4_E16, 0x3, true }, // 2092 |
2170 | | { PseudoVREDXOR_VS_MF4_E8_MASK, PseudoVREDXOR_VS_MF4_E8, 0x3, true }, // 2093 |
2171 | | { PseudoVREDXOR_VS_MF8_E8_MASK, PseudoVREDXOR_VS_MF8_E8, 0x3, true }, // 2094 |
2172 | | { PseudoVREMU_VV_M1_E16_MASK, PseudoVREMU_VV_M1_E16, 0x3, false }, // 2095 |
2173 | | { PseudoVREMU_VV_M1_E32_MASK, PseudoVREMU_VV_M1_E32, 0x3, false }, // 2096 |
2174 | | { PseudoVREMU_VV_M1_E64_MASK, PseudoVREMU_VV_M1_E64, 0x3, false }, // 2097 |
2175 | | { PseudoVREMU_VV_M1_E8_MASK, PseudoVREMU_VV_M1_E8, 0x3, false }, // 2098 |
2176 | | { PseudoVREMU_VV_M2_E16_MASK, PseudoVREMU_VV_M2_E16, 0x3, false }, // 2099 |
2177 | | { PseudoVREMU_VV_M2_E32_MASK, PseudoVREMU_VV_M2_E32, 0x3, false }, // 2100 |
2178 | | { PseudoVREMU_VV_M2_E64_MASK, PseudoVREMU_VV_M2_E64, 0x3, false }, // 2101 |
2179 | | { PseudoVREMU_VV_M2_E8_MASK, PseudoVREMU_VV_M2_E8, 0x3, false }, // 2102 |
2180 | | { PseudoVREMU_VV_M4_E16_MASK, PseudoVREMU_VV_M4_E16, 0x3, false }, // 2103 |
2181 | | { PseudoVREMU_VV_M4_E32_MASK, PseudoVREMU_VV_M4_E32, 0x3, false }, // 2104 |
2182 | | { PseudoVREMU_VV_M4_E64_MASK, PseudoVREMU_VV_M4_E64, 0x3, false }, // 2105 |
2183 | | { PseudoVREMU_VV_M4_E8_MASK, PseudoVREMU_VV_M4_E8, 0x3, false }, // 2106 |
2184 | | { PseudoVREMU_VV_M8_E16_MASK, PseudoVREMU_VV_M8_E16, 0x3, false }, // 2107 |
2185 | | { PseudoVREMU_VV_M8_E32_MASK, PseudoVREMU_VV_M8_E32, 0x3, false }, // 2108 |
2186 | | { PseudoVREMU_VV_M8_E64_MASK, PseudoVREMU_VV_M8_E64, 0x3, false }, // 2109 |
2187 | | { PseudoVREMU_VV_M8_E8_MASK, PseudoVREMU_VV_M8_E8, 0x3, false }, // 2110 |
2188 | | { PseudoVREMU_VV_MF2_E16_MASK, PseudoVREMU_VV_MF2_E16, 0x3, false }, // 2111 |
2189 | | { PseudoVREMU_VV_MF2_E32_MASK, PseudoVREMU_VV_MF2_E32, 0x3, false }, // 2112 |
2190 | | { PseudoVREMU_VV_MF2_E8_MASK, PseudoVREMU_VV_MF2_E8, 0x3, false }, // 2113 |
2191 | | { PseudoVREMU_VV_MF4_E16_MASK, PseudoVREMU_VV_MF4_E16, 0x3, false }, // 2114 |
2192 | | { PseudoVREMU_VV_MF4_E8_MASK, PseudoVREMU_VV_MF4_E8, 0x3, false }, // 2115 |
2193 | | { PseudoVREMU_VV_MF8_E8_MASK, PseudoVREMU_VV_MF8_E8, 0x3, false }, // 2116 |
2194 | | { PseudoVREMU_VX_M1_E16_MASK, PseudoVREMU_VX_M1_E16, 0x3, false }, // 2117 |
2195 | | { PseudoVREMU_VX_M1_E32_MASK, PseudoVREMU_VX_M1_E32, 0x3, false }, // 2118 |
2196 | | { PseudoVREMU_VX_M1_E64_MASK, PseudoVREMU_VX_M1_E64, 0x3, false }, // 2119 |
2197 | | { PseudoVREMU_VX_M1_E8_MASK, PseudoVREMU_VX_M1_E8, 0x3, false }, // 2120 |
2198 | | { PseudoVREMU_VX_M2_E16_MASK, PseudoVREMU_VX_M2_E16, 0x3, false }, // 2121 |
2199 | | { PseudoVREMU_VX_M2_E32_MASK, PseudoVREMU_VX_M2_E32, 0x3, false }, // 2122 |
2200 | | { PseudoVREMU_VX_M2_E64_MASK, PseudoVREMU_VX_M2_E64, 0x3, false }, // 2123 |
2201 | | { PseudoVREMU_VX_M2_E8_MASK, PseudoVREMU_VX_M2_E8, 0x3, false }, // 2124 |
2202 | | { PseudoVREMU_VX_M4_E16_MASK, PseudoVREMU_VX_M4_E16, 0x3, false }, // 2125 |
2203 | | { PseudoVREMU_VX_M4_E32_MASK, PseudoVREMU_VX_M4_E32, 0x3, false }, // 2126 |
2204 | | { PseudoVREMU_VX_M4_E64_MASK, PseudoVREMU_VX_M4_E64, 0x3, false }, // 2127 |
2205 | | { PseudoVREMU_VX_M4_E8_MASK, PseudoVREMU_VX_M4_E8, 0x3, false }, // 2128 |
2206 | | { PseudoVREMU_VX_M8_E16_MASK, PseudoVREMU_VX_M8_E16, 0x3, false }, // 2129 |
2207 | | { PseudoVREMU_VX_M8_E32_MASK, PseudoVREMU_VX_M8_E32, 0x3, false }, // 2130 |
2208 | | { PseudoVREMU_VX_M8_E64_MASK, PseudoVREMU_VX_M8_E64, 0x3, false }, // 2131 |
2209 | | { PseudoVREMU_VX_M8_E8_MASK, PseudoVREMU_VX_M8_E8, 0x3, false }, // 2132 |
2210 | | { PseudoVREMU_VX_MF2_E16_MASK, PseudoVREMU_VX_MF2_E16, 0x3, false }, // 2133 |
2211 | | { PseudoVREMU_VX_MF2_E32_MASK, PseudoVREMU_VX_MF2_E32, 0x3, false }, // 2134 |
2212 | | { PseudoVREMU_VX_MF2_E8_MASK, PseudoVREMU_VX_MF2_E8, 0x3, false }, // 2135 |
2213 | | { PseudoVREMU_VX_MF4_E16_MASK, PseudoVREMU_VX_MF4_E16, 0x3, false }, // 2136 |
2214 | | { PseudoVREMU_VX_MF4_E8_MASK, PseudoVREMU_VX_MF4_E8, 0x3, false }, // 2137 |
2215 | | { PseudoVREMU_VX_MF8_E8_MASK, PseudoVREMU_VX_MF8_E8, 0x3, false }, // 2138 |
2216 | | { PseudoVREM_VV_M1_E16_MASK, PseudoVREM_VV_M1_E16, 0x3, false }, // 2139 |
2217 | | { PseudoVREM_VV_M1_E32_MASK, PseudoVREM_VV_M1_E32, 0x3, false }, // 2140 |
2218 | | { PseudoVREM_VV_M1_E64_MASK, PseudoVREM_VV_M1_E64, 0x3, false }, // 2141 |
2219 | | { PseudoVREM_VV_M1_E8_MASK, PseudoVREM_VV_M1_E8, 0x3, false }, // 2142 |
2220 | | { PseudoVREM_VV_M2_E16_MASK, PseudoVREM_VV_M2_E16, 0x3, false }, // 2143 |
2221 | | { PseudoVREM_VV_M2_E32_MASK, PseudoVREM_VV_M2_E32, 0x3, false }, // 2144 |
2222 | | { PseudoVREM_VV_M2_E64_MASK, PseudoVREM_VV_M2_E64, 0x3, false }, // 2145 |
2223 | | { PseudoVREM_VV_M2_E8_MASK, PseudoVREM_VV_M2_E8, 0x3, false }, // 2146 |
2224 | | { PseudoVREM_VV_M4_E16_MASK, PseudoVREM_VV_M4_E16, 0x3, false }, // 2147 |
2225 | | { PseudoVREM_VV_M4_E32_MASK, PseudoVREM_VV_M4_E32, 0x3, false }, // 2148 |
2226 | | { PseudoVREM_VV_M4_E64_MASK, PseudoVREM_VV_M4_E64, 0x3, false }, // 2149 |
2227 | | { PseudoVREM_VV_M4_E8_MASK, PseudoVREM_VV_M4_E8, 0x3, false }, // 2150 |
2228 | | { PseudoVREM_VV_M8_E16_MASK, PseudoVREM_VV_M8_E16, 0x3, false }, // 2151 |
2229 | | { PseudoVREM_VV_M8_E32_MASK, PseudoVREM_VV_M8_E32, 0x3, false }, // 2152 |
2230 | | { PseudoVREM_VV_M8_E64_MASK, PseudoVREM_VV_M8_E64, 0x3, false }, // 2153 |
2231 | | { PseudoVREM_VV_M8_E8_MASK, PseudoVREM_VV_M8_E8, 0x3, false }, // 2154 |
2232 | | { PseudoVREM_VV_MF2_E16_MASK, PseudoVREM_VV_MF2_E16, 0x3, false }, // 2155 |
2233 | | { PseudoVREM_VV_MF2_E32_MASK, PseudoVREM_VV_MF2_E32, 0x3, false }, // 2156 |
2234 | | { PseudoVREM_VV_MF2_E8_MASK, PseudoVREM_VV_MF2_E8, 0x3, false }, // 2157 |
2235 | | { PseudoVREM_VV_MF4_E16_MASK, PseudoVREM_VV_MF4_E16, 0x3, false }, // 2158 |
2236 | | { PseudoVREM_VV_MF4_E8_MASK, PseudoVREM_VV_MF4_E8, 0x3, false }, // 2159 |
2237 | | { PseudoVREM_VV_MF8_E8_MASK, PseudoVREM_VV_MF8_E8, 0x3, false }, // 2160 |
2238 | | { PseudoVREM_VX_M1_E16_MASK, PseudoVREM_VX_M1_E16, 0x3, false }, // 2161 |
2239 | | { PseudoVREM_VX_M1_E32_MASK, PseudoVREM_VX_M1_E32, 0x3, false }, // 2162 |
2240 | | { PseudoVREM_VX_M1_E64_MASK, PseudoVREM_VX_M1_E64, 0x3, false }, // 2163 |
2241 | | { PseudoVREM_VX_M1_E8_MASK, PseudoVREM_VX_M1_E8, 0x3, false }, // 2164 |
2242 | | { PseudoVREM_VX_M2_E16_MASK, PseudoVREM_VX_M2_E16, 0x3, false }, // 2165 |
2243 | | { PseudoVREM_VX_M2_E32_MASK, PseudoVREM_VX_M2_E32, 0x3, false }, // 2166 |
2244 | | { PseudoVREM_VX_M2_E64_MASK, PseudoVREM_VX_M2_E64, 0x3, false }, // 2167 |
2245 | | { PseudoVREM_VX_M2_E8_MASK, PseudoVREM_VX_M2_E8, 0x3, false }, // 2168 |
2246 | | { PseudoVREM_VX_M4_E16_MASK, PseudoVREM_VX_M4_E16, 0x3, false }, // 2169 |
2247 | | { PseudoVREM_VX_M4_E32_MASK, PseudoVREM_VX_M4_E32, 0x3, false }, // 2170 |
2248 | | { PseudoVREM_VX_M4_E64_MASK, PseudoVREM_VX_M4_E64, 0x3, false }, // 2171 |
2249 | | { PseudoVREM_VX_M4_E8_MASK, PseudoVREM_VX_M4_E8, 0x3, false }, // 2172 |
2250 | | { PseudoVREM_VX_M8_E16_MASK, PseudoVREM_VX_M8_E16, 0x3, false }, // 2173 |
2251 | | { PseudoVREM_VX_M8_E32_MASK, PseudoVREM_VX_M8_E32, 0x3, false }, // 2174 |
2252 | | { PseudoVREM_VX_M8_E64_MASK, PseudoVREM_VX_M8_E64, 0x3, false }, // 2175 |
2253 | | { PseudoVREM_VX_M8_E8_MASK, PseudoVREM_VX_M8_E8, 0x3, false }, // 2176 |
2254 | | { PseudoVREM_VX_MF2_E16_MASK, PseudoVREM_VX_MF2_E16, 0x3, false }, // 2177 |
2255 | | { PseudoVREM_VX_MF2_E32_MASK, PseudoVREM_VX_MF2_E32, 0x3, false }, // 2178 |
2256 | | { PseudoVREM_VX_MF2_E8_MASK, PseudoVREM_VX_MF2_E8, 0x3, false }, // 2179 |
2257 | | { PseudoVREM_VX_MF4_E16_MASK, PseudoVREM_VX_MF4_E16, 0x3, false }, // 2180 |
2258 | | { PseudoVREM_VX_MF4_E8_MASK, PseudoVREM_VX_MF4_E8, 0x3, false }, // 2181 |
2259 | | { PseudoVREM_VX_MF8_E8_MASK, PseudoVREM_VX_MF8_E8, 0x3, false }, // 2182 |
2260 | | { PseudoVREV8_V_M1_MASK, PseudoVREV8_V_M1, 0x2, false }, // 2183 |
2261 | | { PseudoVREV8_V_M2_MASK, PseudoVREV8_V_M2, 0x2, false }, // 2184 |
2262 | | { PseudoVREV8_V_M4_MASK, PseudoVREV8_V_M4, 0x2, false }, // 2185 |
2263 | | { PseudoVREV8_V_M8_MASK, PseudoVREV8_V_M8, 0x2, false }, // 2186 |
2264 | | { PseudoVREV8_V_MF2_MASK, PseudoVREV8_V_MF2, 0x2, false }, // 2187 |
2265 | | { PseudoVREV8_V_MF4_MASK, PseudoVREV8_V_MF4, 0x2, false }, // 2188 |
2266 | | { PseudoVREV8_V_MF8_MASK, PseudoVREV8_V_MF8, 0x2, false }, // 2189 |
2267 | | { PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, PseudoVRGATHEREI16_VV_M1_E16_M1, 0x3, false }, // 2190 |
2268 | | { PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, PseudoVRGATHEREI16_VV_M1_E16_M2, 0x3, false }, // 2191 |
2269 | | { PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E16_MF2, 0x3, false }, // 2192 |
2270 | | { PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E16_MF4, 0x3, false }, // 2193 |
2271 | | { PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, PseudoVRGATHEREI16_VV_M1_E32_M1, 0x3, false }, // 2194 |
2272 | | { PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, PseudoVRGATHEREI16_VV_M1_E32_M2, 0x3, false }, // 2195 |
2273 | | { PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E32_MF2, 0x3, false }, // 2196 |
2274 | | { PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E32_MF4, 0x3, false }, // 2197 |
2275 | | { PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, PseudoVRGATHEREI16_VV_M1_E64_M1, 0x3, false }, // 2198 |
2276 | | { PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, PseudoVRGATHEREI16_VV_M1_E64_M2, 0x3, false }, // 2199 |
2277 | | { PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E64_MF2, 0x3, false }, // 2200 |
2278 | | { PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E64_MF4, 0x3, false }, // 2201 |
2279 | | { PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, PseudoVRGATHEREI16_VV_M1_E8_M1, 0x3, false }, // 2202 |
2280 | | { PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, PseudoVRGATHEREI16_VV_M1_E8_M2, 0x3, false }, // 2203 |
2281 | | { PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, PseudoVRGATHEREI16_VV_M1_E8_MF2, 0x3, false }, // 2204 |
2282 | | { PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, PseudoVRGATHEREI16_VV_M1_E8_MF4, 0x3, false }, // 2205 |
2283 | | { PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, PseudoVRGATHEREI16_VV_M2_E16_M1, 0x3, false }, // 2206 |
2284 | | { PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, PseudoVRGATHEREI16_VV_M2_E16_M2, 0x3, false }, // 2207 |
2285 | | { PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, PseudoVRGATHEREI16_VV_M2_E16_M4, 0x3, false }, // 2208 |
2286 | | { PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E16_MF2, 0x3, false }, // 2209 |
2287 | | { PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, PseudoVRGATHEREI16_VV_M2_E32_M1, 0x3, false }, // 2210 |
2288 | | { PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, PseudoVRGATHEREI16_VV_M2_E32_M2, 0x3, false }, // 2211 |
2289 | | { PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, PseudoVRGATHEREI16_VV_M2_E32_M4, 0x3, false }, // 2212 |
2290 | | { PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E32_MF2, 0x3, false }, // 2213 |
2291 | | { PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, PseudoVRGATHEREI16_VV_M2_E64_M1, 0x3, false }, // 2214 |
2292 | | { PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, PseudoVRGATHEREI16_VV_M2_E64_M2, 0x3, false }, // 2215 |
2293 | | { PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, PseudoVRGATHEREI16_VV_M2_E64_M4, 0x3, false }, // 2216 |
2294 | | { PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E64_MF2, 0x3, false }, // 2217 |
2295 | | { PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, PseudoVRGATHEREI16_VV_M2_E8_M1, 0x3, false }, // 2218 |
2296 | | { PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, PseudoVRGATHEREI16_VV_M2_E8_M2, 0x3, false }, // 2219 |
2297 | | { PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, PseudoVRGATHEREI16_VV_M2_E8_M4, 0x3, false }, // 2220 |
2298 | | { PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, PseudoVRGATHEREI16_VV_M2_E8_MF2, 0x3, false }, // 2221 |
2299 | | { PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, PseudoVRGATHEREI16_VV_M4_E16_M1, 0x3, false }, // 2222 |
2300 | | { PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, PseudoVRGATHEREI16_VV_M4_E16_M2, 0x3, false }, // 2223 |
2301 | | { PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, PseudoVRGATHEREI16_VV_M4_E16_M4, 0x3, false }, // 2224 |
2302 | | { PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, PseudoVRGATHEREI16_VV_M4_E16_M8, 0x3, false }, // 2225 |
2303 | | { PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, PseudoVRGATHEREI16_VV_M4_E32_M1, 0x3, false }, // 2226 |
2304 | | { PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, PseudoVRGATHEREI16_VV_M4_E32_M2, 0x3, false }, // 2227 |
2305 | | { PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, PseudoVRGATHEREI16_VV_M4_E32_M4, 0x3, false }, // 2228 |
2306 | | { PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, PseudoVRGATHEREI16_VV_M4_E32_M8, 0x3, false }, // 2229 |
2307 | | { PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, PseudoVRGATHEREI16_VV_M4_E64_M1, 0x3, false }, // 2230 |
2308 | | { PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, PseudoVRGATHEREI16_VV_M4_E64_M2, 0x3, false }, // 2231 |
2309 | | { PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, PseudoVRGATHEREI16_VV_M4_E64_M4, 0x3, false }, // 2232 |
2310 | | { PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, PseudoVRGATHEREI16_VV_M4_E64_M8, 0x3, false }, // 2233 |
2311 | | { PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, PseudoVRGATHEREI16_VV_M4_E8_M1, 0x3, false }, // 2234 |
2312 | | { PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, PseudoVRGATHEREI16_VV_M4_E8_M2, 0x3, false }, // 2235 |
2313 | | { PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, PseudoVRGATHEREI16_VV_M4_E8_M4, 0x3, false }, // 2236 |
2314 | | { PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, PseudoVRGATHEREI16_VV_M4_E8_M8, 0x3, false }, // 2237 |
2315 | | { PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, PseudoVRGATHEREI16_VV_M8_E16_M2, 0x3, false }, // 2238 |
2316 | | { PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, PseudoVRGATHEREI16_VV_M8_E16_M4, 0x3, false }, // 2239 |
2317 | | { PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, PseudoVRGATHEREI16_VV_M8_E16_M8, 0x3, false }, // 2240 |
2318 | | { PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, PseudoVRGATHEREI16_VV_M8_E32_M2, 0x3, false }, // 2241 |
2319 | | { PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, PseudoVRGATHEREI16_VV_M8_E32_M4, 0x3, false }, // 2242 |
2320 | | { PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, PseudoVRGATHEREI16_VV_M8_E32_M8, 0x3, false }, // 2243 |
2321 | | { PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, PseudoVRGATHEREI16_VV_M8_E64_M2, 0x3, false }, // 2244 |
2322 | | { PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, PseudoVRGATHEREI16_VV_M8_E64_M4, 0x3, false }, // 2245 |
2323 | | { PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, PseudoVRGATHEREI16_VV_M8_E64_M8, 0x3, false }, // 2246 |
2324 | | { PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, PseudoVRGATHEREI16_VV_M8_E8_M2, 0x3, false }, // 2247 |
2325 | | { PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, PseudoVRGATHEREI16_VV_M8_E8_M4, 0x3, false }, // 2248 |
2326 | | { PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, PseudoVRGATHEREI16_VV_M8_E8_M8, 0x3, false }, // 2249 |
2327 | | { PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E16_M1, 0x3, false }, // 2250 |
2328 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF2, 0x3, false }, // 2251 |
2329 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF4, 0x3, false }, // 2252 |
2330 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E16_MF8, 0x3, false }, // 2253 |
2331 | | { PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E32_M1, 0x3, false }, // 2254 |
2332 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF2, 0x3, false }, // 2255 |
2333 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF4, 0x3, false }, // 2256 |
2334 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E32_MF8, 0x3, false }, // 2257 |
2335 | | { PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, PseudoVRGATHEREI16_VV_MF2_E8_M1, 0x3, false }, // 2258 |
2336 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF2, 0x3, false }, // 2259 |
2337 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF4, 0x3, false }, // 2260 |
2338 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF2_E8_MF8, 0x3, false }, // 2261 |
2339 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF2, 0x3, false }, // 2262 |
2340 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF4, 0x3, false }, // 2263 |
2341 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, PseudoVRGATHEREI16_VV_MF4_E16_MF8, 0x3, false }, // 2264 |
2342 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF2, 0x3, false }, // 2265 |
2343 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF4, 0x3, false }, // 2266 |
2344 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF4_E8_MF8, 0x3, false }, // 2267 |
2345 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, PseudoVRGATHEREI16_VV_MF8_E8_MF4, 0x3, false }, // 2268 |
2346 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, PseudoVRGATHEREI16_VV_MF8_E8_MF8, 0x3, false }, // 2269 |
2347 | | { PseudoVRGATHER_VI_M1_MASK, PseudoVRGATHER_VI_M1, 0x3, false }, // 2270 |
2348 | | { PseudoVRGATHER_VI_M2_MASK, PseudoVRGATHER_VI_M2, 0x3, false }, // 2271 |
2349 | | { PseudoVRGATHER_VI_M4_MASK, PseudoVRGATHER_VI_M4, 0x3, false }, // 2272 |
2350 | | { PseudoVRGATHER_VI_M8_MASK, PseudoVRGATHER_VI_M8, 0x3, false }, // 2273 |
2351 | | { PseudoVRGATHER_VI_MF2_MASK, PseudoVRGATHER_VI_MF2, 0x3, false }, // 2274 |
2352 | | { PseudoVRGATHER_VI_MF4_MASK, PseudoVRGATHER_VI_MF4, 0x3, false }, // 2275 |
2353 | | { PseudoVRGATHER_VI_MF8_MASK, PseudoVRGATHER_VI_MF8, 0x3, false }, // 2276 |
2354 | | { PseudoVRGATHER_VV_M1_E16_MASK, PseudoVRGATHER_VV_M1_E16, 0x3, false }, // 2277 |
2355 | | { PseudoVRGATHER_VV_M1_E32_MASK, PseudoVRGATHER_VV_M1_E32, 0x3, false }, // 2278 |
2356 | | { PseudoVRGATHER_VV_M1_E64_MASK, PseudoVRGATHER_VV_M1_E64, 0x3, false }, // 2279 |
2357 | | { PseudoVRGATHER_VV_M1_E8_MASK, PseudoVRGATHER_VV_M1_E8, 0x3, false }, // 2280 |
2358 | | { PseudoVRGATHER_VV_M2_E16_MASK, PseudoVRGATHER_VV_M2_E16, 0x3, false }, // 2281 |
2359 | | { PseudoVRGATHER_VV_M2_E32_MASK, PseudoVRGATHER_VV_M2_E32, 0x3, false }, // 2282 |
2360 | | { PseudoVRGATHER_VV_M2_E64_MASK, PseudoVRGATHER_VV_M2_E64, 0x3, false }, // 2283 |
2361 | | { PseudoVRGATHER_VV_M2_E8_MASK, PseudoVRGATHER_VV_M2_E8, 0x3, false }, // 2284 |
2362 | | { PseudoVRGATHER_VV_M4_E16_MASK, PseudoVRGATHER_VV_M4_E16, 0x3, false }, // 2285 |
2363 | | { PseudoVRGATHER_VV_M4_E32_MASK, PseudoVRGATHER_VV_M4_E32, 0x3, false }, // 2286 |
2364 | | { PseudoVRGATHER_VV_M4_E64_MASK, PseudoVRGATHER_VV_M4_E64, 0x3, false }, // 2287 |
2365 | | { PseudoVRGATHER_VV_M4_E8_MASK, PseudoVRGATHER_VV_M4_E8, 0x3, false }, // 2288 |
2366 | | { PseudoVRGATHER_VV_M8_E16_MASK, PseudoVRGATHER_VV_M8_E16, 0x3, false }, // 2289 |
2367 | | { PseudoVRGATHER_VV_M8_E32_MASK, PseudoVRGATHER_VV_M8_E32, 0x3, false }, // 2290 |
2368 | | { PseudoVRGATHER_VV_M8_E64_MASK, PseudoVRGATHER_VV_M8_E64, 0x3, false }, // 2291 |
2369 | | { PseudoVRGATHER_VV_M8_E8_MASK, PseudoVRGATHER_VV_M8_E8, 0x3, false }, // 2292 |
2370 | | { PseudoVRGATHER_VV_MF2_E16_MASK, PseudoVRGATHER_VV_MF2_E16, 0x3, false }, // 2293 |
2371 | | { PseudoVRGATHER_VV_MF2_E32_MASK, PseudoVRGATHER_VV_MF2_E32, 0x3, false }, // 2294 |
2372 | | { PseudoVRGATHER_VV_MF2_E8_MASK, PseudoVRGATHER_VV_MF2_E8, 0x3, false }, // 2295 |
2373 | | { PseudoVRGATHER_VV_MF4_E16_MASK, PseudoVRGATHER_VV_MF4_E16, 0x3, false }, // 2296 |
2374 | | { PseudoVRGATHER_VV_MF4_E8_MASK, PseudoVRGATHER_VV_MF4_E8, 0x3, false }, // 2297 |
2375 | | { PseudoVRGATHER_VV_MF8_E8_MASK, PseudoVRGATHER_VV_MF8_E8, 0x3, false }, // 2298 |
2376 | | { PseudoVRGATHER_VX_M1_MASK, PseudoVRGATHER_VX_M1, 0x3, false }, // 2299 |
2377 | | { PseudoVRGATHER_VX_M2_MASK, PseudoVRGATHER_VX_M2, 0x3, false }, // 2300 |
2378 | | { PseudoVRGATHER_VX_M4_MASK, PseudoVRGATHER_VX_M4, 0x3, false }, // 2301 |
2379 | | { PseudoVRGATHER_VX_M8_MASK, PseudoVRGATHER_VX_M8, 0x3, false }, // 2302 |
2380 | | { PseudoVRGATHER_VX_MF2_MASK, PseudoVRGATHER_VX_MF2, 0x3, false }, // 2303 |
2381 | | { PseudoVRGATHER_VX_MF4_MASK, PseudoVRGATHER_VX_MF4, 0x3, false }, // 2304 |
2382 | | { PseudoVRGATHER_VX_MF8_MASK, PseudoVRGATHER_VX_MF8, 0x3, false }, // 2305 |
2383 | | { PseudoVROL_VV_M1_MASK, PseudoVROL_VV_M1, 0x3, false }, // 2306 |
2384 | | { PseudoVROL_VV_M2_MASK, PseudoVROL_VV_M2, 0x3, false }, // 2307 |
2385 | | { PseudoVROL_VV_M4_MASK, PseudoVROL_VV_M4, 0x3, false }, // 2308 |
2386 | | { PseudoVROL_VV_M8_MASK, PseudoVROL_VV_M8, 0x3, false }, // 2309 |
2387 | | { PseudoVROL_VV_MF2_MASK, PseudoVROL_VV_MF2, 0x3, false }, // 2310 |
2388 | | { PseudoVROL_VV_MF4_MASK, PseudoVROL_VV_MF4, 0x3, false }, // 2311 |
2389 | | { PseudoVROL_VV_MF8_MASK, PseudoVROL_VV_MF8, 0x3, false }, // 2312 |
2390 | | { PseudoVROL_VX_M1_MASK, PseudoVROL_VX_M1, 0x3, false }, // 2313 |
2391 | | { PseudoVROL_VX_M2_MASK, PseudoVROL_VX_M2, 0x3, false }, // 2314 |
2392 | | { PseudoVROL_VX_M4_MASK, PseudoVROL_VX_M4, 0x3, false }, // 2315 |
2393 | | { PseudoVROL_VX_M8_MASK, PseudoVROL_VX_M8, 0x3, false }, // 2316 |
2394 | | { PseudoVROL_VX_MF2_MASK, PseudoVROL_VX_MF2, 0x3, false }, // 2317 |
2395 | | { PseudoVROL_VX_MF4_MASK, PseudoVROL_VX_MF4, 0x3, false }, // 2318 |
2396 | | { PseudoVROL_VX_MF8_MASK, PseudoVROL_VX_MF8, 0x3, false }, // 2319 |
2397 | | { PseudoVROR_VI_M1_MASK, PseudoVROR_VI_M1, 0x3, false }, // 2320 |
2398 | | { PseudoVROR_VI_M2_MASK, PseudoVROR_VI_M2, 0x3, false }, // 2321 |
2399 | | { PseudoVROR_VI_M4_MASK, PseudoVROR_VI_M4, 0x3, false }, // 2322 |
2400 | | { PseudoVROR_VI_M8_MASK, PseudoVROR_VI_M8, 0x3, false }, // 2323 |
2401 | | { PseudoVROR_VI_MF2_MASK, PseudoVROR_VI_MF2, 0x3, false }, // 2324 |
2402 | | { PseudoVROR_VI_MF4_MASK, PseudoVROR_VI_MF4, 0x3, false }, // 2325 |
2403 | | { PseudoVROR_VI_MF8_MASK, PseudoVROR_VI_MF8, 0x3, false }, // 2326 |
2404 | | { PseudoVROR_VV_M1_MASK, PseudoVROR_VV_M1, 0x3, false }, // 2327 |
2405 | | { PseudoVROR_VV_M2_MASK, PseudoVROR_VV_M2, 0x3, false }, // 2328 |
2406 | | { PseudoVROR_VV_M4_MASK, PseudoVROR_VV_M4, 0x3, false }, // 2329 |
2407 | | { PseudoVROR_VV_M8_MASK, PseudoVROR_VV_M8, 0x3, false }, // 2330 |
2408 | | { PseudoVROR_VV_MF2_MASK, PseudoVROR_VV_MF2, 0x3, false }, // 2331 |
2409 | | { PseudoVROR_VV_MF4_MASK, PseudoVROR_VV_MF4, 0x3, false }, // 2332 |
2410 | | { PseudoVROR_VV_MF8_MASK, PseudoVROR_VV_MF8, 0x3, false }, // 2333 |
2411 | | { PseudoVROR_VX_M1_MASK, PseudoVROR_VX_M1, 0x3, false }, // 2334 |
2412 | | { PseudoVROR_VX_M2_MASK, PseudoVROR_VX_M2, 0x3, false }, // 2335 |
2413 | | { PseudoVROR_VX_M4_MASK, PseudoVROR_VX_M4, 0x3, false }, // 2336 |
2414 | | { PseudoVROR_VX_M8_MASK, PseudoVROR_VX_M8, 0x3, false }, // 2337 |
2415 | | { PseudoVROR_VX_MF2_MASK, PseudoVROR_VX_MF2, 0x3, false }, // 2338 |
2416 | | { PseudoVROR_VX_MF4_MASK, PseudoVROR_VX_MF4, 0x3, false }, // 2339 |
2417 | | { PseudoVROR_VX_MF8_MASK, PseudoVROR_VX_MF8, 0x3, false }, // 2340 |
2418 | | { PseudoVRSUB_VI_M1_MASK, PseudoVRSUB_VI_M1, 0x3, false }, // 2341 |
2419 | | { PseudoVRSUB_VI_M2_MASK, PseudoVRSUB_VI_M2, 0x3, false }, // 2342 |
2420 | | { PseudoVRSUB_VI_M4_MASK, PseudoVRSUB_VI_M4, 0x3, false }, // 2343 |
2421 | | { PseudoVRSUB_VI_M8_MASK, PseudoVRSUB_VI_M8, 0x3, false }, // 2344 |
2422 | | { PseudoVRSUB_VI_MF2_MASK, PseudoVRSUB_VI_MF2, 0x3, false }, // 2345 |
2423 | | { PseudoVRSUB_VI_MF4_MASK, PseudoVRSUB_VI_MF4, 0x3, false }, // 2346 |
2424 | | { PseudoVRSUB_VI_MF8_MASK, PseudoVRSUB_VI_MF8, 0x3, false }, // 2347 |
2425 | | { PseudoVRSUB_VX_M1_MASK, PseudoVRSUB_VX_M1, 0x3, false }, // 2348 |
2426 | | { PseudoVRSUB_VX_M2_MASK, PseudoVRSUB_VX_M2, 0x3, false }, // 2349 |
2427 | | { PseudoVRSUB_VX_M4_MASK, PseudoVRSUB_VX_M4, 0x3, false }, // 2350 |
2428 | | { PseudoVRSUB_VX_M8_MASK, PseudoVRSUB_VX_M8, 0x3, false }, // 2351 |
2429 | | { PseudoVRSUB_VX_MF2_MASK, PseudoVRSUB_VX_MF2, 0x3, false }, // 2352 |
2430 | | { PseudoVRSUB_VX_MF4_MASK, PseudoVRSUB_VX_MF4, 0x3, false }, // 2353 |
2431 | | { PseudoVRSUB_VX_MF8_MASK, PseudoVRSUB_VX_MF8, 0x3, false }, // 2354 |
2432 | | { PseudoVSADDU_VI_M1_MASK, PseudoVSADDU_VI_M1, 0x3, false }, // 2355 |
2433 | | { PseudoVSADDU_VI_M2_MASK, PseudoVSADDU_VI_M2, 0x3, false }, // 2356 |
2434 | | { PseudoVSADDU_VI_M4_MASK, PseudoVSADDU_VI_M4, 0x3, false }, // 2357 |
2435 | | { PseudoVSADDU_VI_M8_MASK, PseudoVSADDU_VI_M8, 0x3, false }, // 2358 |
2436 | | { PseudoVSADDU_VI_MF2_MASK, PseudoVSADDU_VI_MF2, 0x3, false }, // 2359 |
2437 | | { PseudoVSADDU_VI_MF4_MASK, PseudoVSADDU_VI_MF4, 0x3, false }, // 2360 |
2438 | | { PseudoVSADDU_VI_MF8_MASK, PseudoVSADDU_VI_MF8, 0x3, false }, // 2361 |
2439 | | { PseudoVSADDU_VV_M1_MASK, PseudoVSADDU_VV_M1, 0x3, false }, // 2362 |
2440 | | { PseudoVSADDU_VV_M2_MASK, PseudoVSADDU_VV_M2, 0x3, false }, // 2363 |
2441 | | { PseudoVSADDU_VV_M4_MASK, PseudoVSADDU_VV_M4, 0x3, false }, // 2364 |
2442 | | { PseudoVSADDU_VV_M8_MASK, PseudoVSADDU_VV_M8, 0x3, false }, // 2365 |
2443 | | { PseudoVSADDU_VV_MF2_MASK, PseudoVSADDU_VV_MF2, 0x3, false }, // 2366 |
2444 | | { PseudoVSADDU_VV_MF4_MASK, PseudoVSADDU_VV_MF4, 0x3, false }, // 2367 |
2445 | | { PseudoVSADDU_VV_MF8_MASK, PseudoVSADDU_VV_MF8, 0x3, false }, // 2368 |
2446 | | { PseudoVSADDU_VX_M1_MASK, PseudoVSADDU_VX_M1, 0x3, false }, // 2369 |
2447 | | { PseudoVSADDU_VX_M2_MASK, PseudoVSADDU_VX_M2, 0x3, false }, // 2370 |
2448 | | { PseudoVSADDU_VX_M4_MASK, PseudoVSADDU_VX_M4, 0x3, false }, // 2371 |
2449 | | { PseudoVSADDU_VX_M8_MASK, PseudoVSADDU_VX_M8, 0x3, false }, // 2372 |
2450 | | { PseudoVSADDU_VX_MF2_MASK, PseudoVSADDU_VX_MF2, 0x3, false }, // 2373 |
2451 | | { PseudoVSADDU_VX_MF4_MASK, PseudoVSADDU_VX_MF4, 0x3, false }, // 2374 |
2452 | | { PseudoVSADDU_VX_MF8_MASK, PseudoVSADDU_VX_MF8, 0x3, false }, // 2375 |
2453 | | { PseudoVSADD_VI_M1_MASK, PseudoVSADD_VI_M1, 0x3, false }, // 2376 |
2454 | | { PseudoVSADD_VI_M2_MASK, PseudoVSADD_VI_M2, 0x3, false }, // 2377 |
2455 | | { PseudoVSADD_VI_M4_MASK, PseudoVSADD_VI_M4, 0x3, false }, // 2378 |
2456 | | { PseudoVSADD_VI_M8_MASK, PseudoVSADD_VI_M8, 0x3, false }, // 2379 |
2457 | | { PseudoVSADD_VI_MF2_MASK, PseudoVSADD_VI_MF2, 0x3, false }, // 2380 |
2458 | | { PseudoVSADD_VI_MF4_MASK, PseudoVSADD_VI_MF4, 0x3, false }, // 2381 |
2459 | | { PseudoVSADD_VI_MF8_MASK, PseudoVSADD_VI_MF8, 0x3, false }, // 2382 |
2460 | | { PseudoVSADD_VV_M1_MASK, PseudoVSADD_VV_M1, 0x3, false }, // 2383 |
2461 | | { PseudoVSADD_VV_M2_MASK, PseudoVSADD_VV_M2, 0x3, false }, // 2384 |
2462 | | { PseudoVSADD_VV_M4_MASK, PseudoVSADD_VV_M4, 0x3, false }, // 2385 |
2463 | | { PseudoVSADD_VV_M8_MASK, PseudoVSADD_VV_M8, 0x3, false }, // 2386 |
2464 | | { PseudoVSADD_VV_MF2_MASK, PseudoVSADD_VV_MF2, 0x3, false }, // 2387 |
2465 | | { PseudoVSADD_VV_MF4_MASK, PseudoVSADD_VV_MF4, 0x3, false }, // 2388 |
2466 | | { PseudoVSADD_VV_MF8_MASK, PseudoVSADD_VV_MF8, 0x3, false }, // 2389 |
2467 | | { PseudoVSADD_VX_M1_MASK, PseudoVSADD_VX_M1, 0x3, false }, // 2390 |
2468 | | { PseudoVSADD_VX_M2_MASK, PseudoVSADD_VX_M2, 0x3, false }, // 2391 |
2469 | | { PseudoVSADD_VX_M4_MASK, PseudoVSADD_VX_M4, 0x3, false }, // 2392 |
2470 | | { PseudoVSADD_VX_M8_MASK, PseudoVSADD_VX_M8, 0x3, false }, // 2393 |
2471 | | { PseudoVSADD_VX_MF2_MASK, PseudoVSADD_VX_MF2, 0x3, false }, // 2394 |
2472 | | { PseudoVSADD_VX_MF4_MASK, PseudoVSADD_VX_MF4, 0x3, false }, // 2395 |
2473 | | { PseudoVSADD_VX_MF8_MASK, PseudoVSADD_VX_MF8, 0x3, false }, // 2396 |
2474 | | { PseudoVSEXT_VF2_M1_MASK, PseudoVSEXT_VF2_M1, 0x2, false }, // 2397 |
2475 | | { PseudoVSEXT_VF2_M2_MASK, PseudoVSEXT_VF2_M2, 0x2, false }, // 2398 |
2476 | | { PseudoVSEXT_VF2_M4_MASK, PseudoVSEXT_VF2_M4, 0x2, false }, // 2399 |
2477 | | { PseudoVSEXT_VF2_M8_MASK, PseudoVSEXT_VF2_M8, 0x2, false }, // 2400 |
2478 | | { PseudoVSEXT_VF2_MF2_MASK, PseudoVSEXT_VF2_MF2, 0x2, false }, // 2401 |
2479 | | { PseudoVSEXT_VF2_MF4_MASK, PseudoVSEXT_VF2_MF4, 0x2, false }, // 2402 |
2480 | | { PseudoVSEXT_VF4_M1_MASK, PseudoVSEXT_VF4_M1, 0x2, false }, // 2403 |
2481 | | { PseudoVSEXT_VF4_M2_MASK, PseudoVSEXT_VF4_M2, 0x2, false }, // 2404 |
2482 | | { PseudoVSEXT_VF4_M4_MASK, PseudoVSEXT_VF4_M4, 0x2, false }, // 2405 |
2483 | | { PseudoVSEXT_VF4_M8_MASK, PseudoVSEXT_VF4_M8, 0x2, false }, // 2406 |
2484 | | { PseudoVSEXT_VF4_MF2_MASK, PseudoVSEXT_VF4_MF2, 0x2, false }, // 2407 |
2485 | | { PseudoVSEXT_VF8_M1_MASK, PseudoVSEXT_VF8_M1, 0x2, false }, // 2408 |
2486 | | { PseudoVSEXT_VF8_M2_MASK, PseudoVSEXT_VF8_M2, 0x2, false }, // 2409 |
2487 | | { PseudoVSEXT_VF8_M4_MASK, PseudoVSEXT_VF8_M4, 0x2, false }, // 2410 |
2488 | | { PseudoVSEXT_VF8_M8_MASK, PseudoVSEXT_VF8_M8, 0x2, false }, // 2411 |
2489 | | { PseudoVSLIDE1DOWN_VX_M1_MASK, PseudoVSLIDE1DOWN_VX_M1, 0x3, false }, // 2412 |
2490 | | { PseudoVSLIDE1DOWN_VX_M2_MASK, PseudoVSLIDE1DOWN_VX_M2, 0x3, false }, // 2413 |
2491 | | { PseudoVSLIDE1DOWN_VX_M4_MASK, PseudoVSLIDE1DOWN_VX_M4, 0x3, false }, // 2414 |
2492 | | { PseudoVSLIDE1DOWN_VX_M8_MASK, PseudoVSLIDE1DOWN_VX_M8, 0x3, false }, // 2415 |
2493 | | { PseudoVSLIDE1DOWN_VX_MF2_MASK, PseudoVSLIDE1DOWN_VX_MF2, 0x3, false }, // 2416 |
2494 | | { PseudoVSLIDE1DOWN_VX_MF4_MASK, PseudoVSLIDE1DOWN_VX_MF4, 0x3, false }, // 2417 |
2495 | | { PseudoVSLIDE1DOWN_VX_MF8_MASK, PseudoVSLIDE1DOWN_VX_MF8, 0x3, false }, // 2418 |
2496 | | { PseudoVSLIDE1UP_VX_M1_MASK, PseudoVSLIDE1UP_VX_M1, 0x3, false }, // 2419 |
2497 | | { PseudoVSLIDE1UP_VX_M2_MASK, PseudoVSLIDE1UP_VX_M2, 0x3, false }, // 2420 |
2498 | | { PseudoVSLIDE1UP_VX_M4_MASK, PseudoVSLIDE1UP_VX_M4, 0x3, false }, // 2421 |
2499 | | { PseudoVSLIDE1UP_VX_M8_MASK, PseudoVSLIDE1UP_VX_M8, 0x3, false }, // 2422 |
2500 | | { PseudoVSLIDE1UP_VX_MF2_MASK, PseudoVSLIDE1UP_VX_MF2, 0x3, false }, // 2423 |
2501 | | { PseudoVSLIDE1UP_VX_MF4_MASK, PseudoVSLIDE1UP_VX_MF4, 0x3, false }, // 2424 |
2502 | | { PseudoVSLIDE1UP_VX_MF8_MASK, PseudoVSLIDE1UP_VX_MF8, 0x3, false }, // 2425 |
2503 | | { PseudoVSLIDEDOWN_VI_M1_MASK, PseudoVSLIDEDOWN_VI_M1, 0x3, false }, // 2426 |
2504 | | { PseudoVSLIDEDOWN_VI_M2_MASK, PseudoVSLIDEDOWN_VI_M2, 0x3, false }, // 2427 |
2505 | | { PseudoVSLIDEDOWN_VI_M4_MASK, PseudoVSLIDEDOWN_VI_M4, 0x3, false }, // 2428 |
2506 | | { PseudoVSLIDEDOWN_VI_M8_MASK, PseudoVSLIDEDOWN_VI_M8, 0x3, false }, // 2429 |
2507 | | { PseudoVSLIDEDOWN_VI_MF2_MASK, PseudoVSLIDEDOWN_VI_MF2, 0x3, false }, // 2430 |
2508 | | { PseudoVSLIDEDOWN_VI_MF4_MASK, PseudoVSLIDEDOWN_VI_MF4, 0x3, false }, // 2431 |
2509 | | { PseudoVSLIDEDOWN_VI_MF8_MASK, PseudoVSLIDEDOWN_VI_MF8, 0x3, false }, // 2432 |
2510 | | { PseudoVSLIDEDOWN_VX_M1_MASK, PseudoVSLIDEDOWN_VX_M1, 0x3, false }, // 2433 |
2511 | | { PseudoVSLIDEDOWN_VX_M2_MASK, PseudoVSLIDEDOWN_VX_M2, 0x3, false }, // 2434 |
2512 | | { PseudoVSLIDEDOWN_VX_M4_MASK, PseudoVSLIDEDOWN_VX_M4, 0x3, false }, // 2435 |
2513 | | { PseudoVSLIDEDOWN_VX_M8_MASK, PseudoVSLIDEDOWN_VX_M8, 0x3, false }, // 2436 |
2514 | | { PseudoVSLIDEDOWN_VX_MF2_MASK, PseudoVSLIDEDOWN_VX_MF2, 0x3, false }, // 2437 |
2515 | | { PseudoVSLIDEDOWN_VX_MF4_MASK, PseudoVSLIDEDOWN_VX_MF4, 0x3, false }, // 2438 |
2516 | | { PseudoVSLIDEDOWN_VX_MF8_MASK, PseudoVSLIDEDOWN_VX_MF8, 0x3, false }, // 2439 |
2517 | | { PseudoVSLIDEUP_VI_M1_MASK, PseudoVSLIDEUP_VI_M1, 0x3, false }, // 2440 |
2518 | | { PseudoVSLIDEUP_VI_M2_MASK, PseudoVSLIDEUP_VI_M2, 0x3, false }, // 2441 |
2519 | | { PseudoVSLIDEUP_VI_M4_MASK, PseudoVSLIDEUP_VI_M4, 0x3, false }, // 2442 |
2520 | | { PseudoVSLIDEUP_VI_M8_MASK, PseudoVSLIDEUP_VI_M8, 0x3, false }, // 2443 |
2521 | | { PseudoVSLIDEUP_VI_MF2_MASK, PseudoVSLIDEUP_VI_MF2, 0x3, false }, // 2444 |
2522 | | { PseudoVSLIDEUP_VI_MF4_MASK, PseudoVSLIDEUP_VI_MF4, 0x3, false }, // 2445 |
2523 | | { PseudoVSLIDEUP_VI_MF8_MASK, PseudoVSLIDEUP_VI_MF8, 0x3, false }, // 2446 |
2524 | | { PseudoVSLIDEUP_VX_M1_MASK, PseudoVSLIDEUP_VX_M1, 0x3, false }, // 2447 |
2525 | | { PseudoVSLIDEUP_VX_M2_MASK, PseudoVSLIDEUP_VX_M2, 0x3, false }, // 2448 |
2526 | | { PseudoVSLIDEUP_VX_M4_MASK, PseudoVSLIDEUP_VX_M4, 0x3, false }, // 2449 |
2527 | | { PseudoVSLIDEUP_VX_M8_MASK, PseudoVSLIDEUP_VX_M8, 0x3, false }, // 2450 |
2528 | | { PseudoVSLIDEUP_VX_MF2_MASK, PseudoVSLIDEUP_VX_MF2, 0x3, false }, // 2451 |
2529 | | { PseudoVSLIDEUP_VX_MF4_MASK, PseudoVSLIDEUP_VX_MF4, 0x3, false }, // 2452 |
2530 | | { PseudoVSLIDEUP_VX_MF8_MASK, PseudoVSLIDEUP_VX_MF8, 0x3, false }, // 2453 |
2531 | | { PseudoVSLL_VI_M1_MASK, PseudoVSLL_VI_M1, 0x3, false }, // 2454 |
2532 | | { PseudoVSLL_VI_M2_MASK, PseudoVSLL_VI_M2, 0x3, false }, // 2455 |
2533 | | { PseudoVSLL_VI_M4_MASK, PseudoVSLL_VI_M4, 0x3, false }, // 2456 |
2534 | | { PseudoVSLL_VI_M8_MASK, PseudoVSLL_VI_M8, 0x3, false }, // 2457 |
2535 | | { PseudoVSLL_VI_MF2_MASK, PseudoVSLL_VI_MF2, 0x3, false }, // 2458 |
2536 | | { PseudoVSLL_VI_MF4_MASK, PseudoVSLL_VI_MF4, 0x3, false }, // 2459 |
2537 | | { PseudoVSLL_VI_MF8_MASK, PseudoVSLL_VI_MF8, 0x3, false }, // 2460 |
2538 | | { PseudoVSLL_VV_M1_MASK, PseudoVSLL_VV_M1, 0x3, false }, // 2461 |
2539 | | { PseudoVSLL_VV_M2_MASK, PseudoVSLL_VV_M2, 0x3, false }, // 2462 |
2540 | | { PseudoVSLL_VV_M4_MASK, PseudoVSLL_VV_M4, 0x3, false }, // 2463 |
2541 | | { PseudoVSLL_VV_M8_MASK, PseudoVSLL_VV_M8, 0x3, false }, // 2464 |
2542 | | { PseudoVSLL_VV_MF2_MASK, PseudoVSLL_VV_MF2, 0x3, false }, // 2465 |
2543 | | { PseudoVSLL_VV_MF4_MASK, PseudoVSLL_VV_MF4, 0x3, false }, // 2466 |
2544 | | { PseudoVSLL_VV_MF8_MASK, PseudoVSLL_VV_MF8, 0x3, false }, // 2467 |
2545 | | { PseudoVSLL_VX_M1_MASK, PseudoVSLL_VX_M1, 0x3, false }, // 2468 |
2546 | | { PseudoVSLL_VX_M2_MASK, PseudoVSLL_VX_M2, 0x3, false }, // 2469 |
2547 | | { PseudoVSLL_VX_M4_MASK, PseudoVSLL_VX_M4, 0x3, false }, // 2470 |
2548 | | { PseudoVSLL_VX_M8_MASK, PseudoVSLL_VX_M8, 0x3, false }, // 2471 |
2549 | | { PseudoVSLL_VX_MF2_MASK, PseudoVSLL_VX_MF2, 0x3, false }, // 2472 |
2550 | | { PseudoVSLL_VX_MF4_MASK, PseudoVSLL_VX_MF4, 0x3, false }, // 2473 |
2551 | | { PseudoVSLL_VX_MF8_MASK, PseudoVSLL_VX_MF8, 0x3, false }, // 2474 |
2552 | | { PseudoVSMUL_VV_M1_MASK, PseudoVSMUL_VV_M1, 0x3, false }, // 2475 |
2553 | | { PseudoVSMUL_VV_M2_MASK, PseudoVSMUL_VV_M2, 0x3, false }, // 2476 |
2554 | | { PseudoVSMUL_VV_M4_MASK, PseudoVSMUL_VV_M4, 0x3, false }, // 2477 |
2555 | | { PseudoVSMUL_VV_M8_MASK, PseudoVSMUL_VV_M8, 0x3, false }, // 2478 |
2556 | | { PseudoVSMUL_VV_MF2_MASK, PseudoVSMUL_VV_MF2, 0x3, false }, // 2479 |
2557 | | { PseudoVSMUL_VV_MF4_MASK, PseudoVSMUL_VV_MF4, 0x3, false }, // 2480 |
2558 | | { PseudoVSMUL_VV_MF8_MASK, PseudoVSMUL_VV_MF8, 0x3, false }, // 2481 |
2559 | | { PseudoVSMUL_VX_M1_MASK, PseudoVSMUL_VX_M1, 0x3, false }, // 2482 |
2560 | | { PseudoVSMUL_VX_M2_MASK, PseudoVSMUL_VX_M2, 0x3, false }, // 2483 |
2561 | | { PseudoVSMUL_VX_M4_MASK, PseudoVSMUL_VX_M4, 0x3, false }, // 2484 |
2562 | | { PseudoVSMUL_VX_M8_MASK, PseudoVSMUL_VX_M8, 0x3, false }, // 2485 |
2563 | | { PseudoVSMUL_VX_MF2_MASK, PseudoVSMUL_VX_MF2, 0x3, false }, // 2486 |
2564 | | { PseudoVSMUL_VX_MF4_MASK, PseudoVSMUL_VX_MF4, 0x3, false }, // 2487 |
2565 | | { PseudoVSMUL_VX_MF8_MASK, PseudoVSMUL_VX_MF8, 0x3, false }, // 2488 |
2566 | | { PseudoVSRA_VI_M1_MASK, PseudoVSRA_VI_M1, 0x3, false }, // 2489 |
2567 | | { PseudoVSRA_VI_M2_MASK, PseudoVSRA_VI_M2, 0x3, false }, // 2490 |
2568 | | { PseudoVSRA_VI_M4_MASK, PseudoVSRA_VI_M4, 0x3, false }, // 2491 |
2569 | | { PseudoVSRA_VI_M8_MASK, PseudoVSRA_VI_M8, 0x3, false }, // 2492 |
2570 | | { PseudoVSRA_VI_MF2_MASK, PseudoVSRA_VI_MF2, 0x3, false }, // 2493 |
2571 | | { PseudoVSRA_VI_MF4_MASK, PseudoVSRA_VI_MF4, 0x3, false }, // 2494 |
2572 | | { PseudoVSRA_VI_MF8_MASK, PseudoVSRA_VI_MF8, 0x3, false }, // 2495 |
2573 | | { PseudoVSRA_VV_M1_MASK, PseudoVSRA_VV_M1, 0x3, false }, // 2496 |
2574 | | { PseudoVSRA_VV_M2_MASK, PseudoVSRA_VV_M2, 0x3, false }, // 2497 |
2575 | | { PseudoVSRA_VV_M4_MASK, PseudoVSRA_VV_M4, 0x3, false }, // 2498 |
2576 | | { PseudoVSRA_VV_M8_MASK, PseudoVSRA_VV_M8, 0x3, false }, // 2499 |
2577 | | { PseudoVSRA_VV_MF2_MASK, PseudoVSRA_VV_MF2, 0x3, false }, // 2500 |
2578 | | { PseudoVSRA_VV_MF4_MASK, PseudoVSRA_VV_MF4, 0x3, false }, // 2501 |
2579 | | { PseudoVSRA_VV_MF8_MASK, PseudoVSRA_VV_MF8, 0x3, false }, // 2502 |
2580 | | { PseudoVSRA_VX_M1_MASK, PseudoVSRA_VX_M1, 0x3, false }, // 2503 |
2581 | | { PseudoVSRA_VX_M2_MASK, PseudoVSRA_VX_M2, 0x3, false }, // 2504 |
2582 | | { PseudoVSRA_VX_M4_MASK, PseudoVSRA_VX_M4, 0x3, false }, // 2505 |
2583 | | { PseudoVSRA_VX_M8_MASK, PseudoVSRA_VX_M8, 0x3, false }, // 2506 |
2584 | | { PseudoVSRA_VX_MF2_MASK, PseudoVSRA_VX_MF2, 0x3, false }, // 2507 |
2585 | | { PseudoVSRA_VX_MF4_MASK, PseudoVSRA_VX_MF4, 0x3, false }, // 2508 |
2586 | | { PseudoVSRA_VX_MF8_MASK, PseudoVSRA_VX_MF8, 0x3, false }, // 2509 |
2587 | | { PseudoVSRL_VI_M1_MASK, PseudoVSRL_VI_M1, 0x3, false }, // 2510 |
2588 | | { PseudoVSRL_VI_M2_MASK, PseudoVSRL_VI_M2, 0x3, false }, // 2511 |
2589 | | { PseudoVSRL_VI_M4_MASK, PseudoVSRL_VI_M4, 0x3, false }, // 2512 |
2590 | | { PseudoVSRL_VI_M8_MASK, PseudoVSRL_VI_M8, 0x3, false }, // 2513 |
2591 | | { PseudoVSRL_VI_MF2_MASK, PseudoVSRL_VI_MF2, 0x3, false }, // 2514 |
2592 | | { PseudoVSRL_VI_MF4_MASK, PseudoVSRL_VI_MF4, 0x3, false }, // 2515 |
2593 | | { PseudoVSRL_VI_MF8_MASK, PseudoVSRL_VI_MF8, 0x3, false }, // 2516 |
2594 | | { PseudoVSRL_VV_M1_MASK, PseudoVSRL_VV_M1, 0x3, false }, // 2517 |
2595 | | { PseudoVSRL_VV_M2_MASK, PseudoVSRL_VV_M2, 0x3, false }, // 2518 |
2596 | | { PseudoVSRL_VV_M4_MASK, PseudoVSRL_VV_M4, 0x3, false }, // 2519 |
2597 | | { PseudoVSRL_VV_M8_MASK, PseudoVSRL_VV_M8, 0x3, false }, // 2520 |
2598 | | { PseudoVSRL_VV_MF2_MASK, PseudoVSRL_VV_MF2, 0x3, false }, // 2521 |
2599 | | { PseudoVSRL_VV_MF4_MASK, PseudoVSRL_VV_MF4, 0x3, false }, // 2522 |
2600 | | { PseudoVSRL_VV_MF8_MASK, PseudoVSRL_VV_MF8, 0x3, false }, // 2523 |
2601 | | { PseudoVSRL_VX_M1_MASK, PseudoVSRL_VX_M1, 0x3, false }, // 2524 |
2602 | | { PseudoVSRL_VX_M2_MASK, PseudoVSRL_VX_M2, 0x3, false }, // 2525 |
2603 | | { PseudoVSRL_VX_M4_MASK, PseudoVSRL_VX_M4, 0x3, false }, // 2526 |
2604 | | { PseudoVSRL_VX_M8_MASK, PseudoVSRL_VX_M8, 0x3, false }, // 2527 |
2605 | | { PseudoVSRL_VX_MF2_MASK, PseudoVSRL_VX_MF2, 0x3, false }, // 2528 |
2606 | | { PseudoVSRL_VX_MF4_MASK, PseudoVSRL_VX_MF4, 0x3, false }, // 2529 |
2607 | | { PseudoVSRL_VX_MF8_MASK, PseudoVSRL_VX_MF8, 0x3, false }, // 2530 |
2608 | | { PseudoVSSRA_VI_M1_MASK, PseudoVSSRA_VI_M1, 0x3, false }, // 2531 |
2609 | | { PseudoVSSRA_VI_M2_MASK, PseudoVSSRA_VI_M2, 0x3, false }, // 2532 |
2610 | | { PseudoVSSRA_VI_M4_MASK, PseudoVSSRA_VI_M4, 0x3, false }, // 2533 |
2611 | | { PseudoVSSRA_VI_M8_MASK, PseudoVSSRA_VI_M8, 0x3, false }, // 2534 |
2612 | | { PseudoVSSRA_VI_MF2_MASK, PseudoVSSRA_VI_MF2, 0x3, false }, // 2535 |
2613 | | { PseudoVSSRA_VI_MF4_MASK, PseudoVSSRA_VI_MF4, 0x3, false }, // 2536 |
2614 | | { PseudoVSSRA_VI_MF8_MASK, PseudoVSSRA_VI_MF8, 0x3, false }, // 2537 |
2615 | | { PseudoVSSRA_VV_M1_MASK, PseudoVSSRA_VV_M1, 0x3, false }, // 2538 |
2616 | | { PseudoVSSRA_VV_M2_MASK, PseudoVSSRA_VV_M2, 0x3, false }, // 2539 |
2617 | | { PseudoVSSRA_VV_M4_MASK, PseudoVSSRA_VV_M4, 0x3, false }, // 2540 |
2618 | | { PseudoVSSRA_VV_M8_MASK, PseudoVSSRA_VV_M8, 0x3, false }, // 2541 |
2619 | | { PseudoVSSRA_VV_MF2_MASK, PseudoVSSRA_VV_MF2, 0x3, false }, // 2542 |
2620 | | { PseudoVSSRA_VV_MF4_MASK, PseudoVSSRA_VV_MF4, 0x3, false }, // 2543 |
2621 | | { PseudoVSSRA_VV_MF8_MASK, PseudoVSSRA_VV_MF8, 0x3, false }, // 2544 |
2622 | | { PseudoVSSRA_VX_M1_MASK, PseudoVSSRA_VX_M1, 0x3, false }, // 2545 |
2623 | | { PseudoVSSRA_VX_M2_MASK, PseudoVSSRA_VX_M2, 0x3, false }, // 2546 |
2624 | | { PseudoVSSRA_VX_M4_MASK, PseudoVSSRA_VX_M4, 0x3, false }, // 2547 |
2625 | | { PseudoVSSRA_VX_M8_MASK, PseudoVSSRA_VX_M8, 0x3, false }, // 2548 |
2626 | | { PseudoVSSRA_VX_MF2_MASK, PseudoVSSRA_VX_MF2, 0x3, false }, // 2549 |
2627 | | { PseudoVSSRA_VX_MF4_MASK, PseudoVSSRA_VX_MF4, 0x3, false }, // 2550 |
2628 | | { PseudoVSSRA_VX_MF8_MASK, PseudoVSSRA_VX_MF8, 0x3, false }, // 2551 |
2629 | | { PseudoVSSRL_VI_M1_MASK, PseudoVSSRL_VI_M1, 0x3, false }, // 2552 |
2630 | | { PseudoVSSRL_VI_M2_MASK, PseudoVSSRL_VI_M2, 0x3, false }, // 2553 |
2631 | | { PseudoVSSRL_VI_M4_MASK, PseudoVSSRL_VI_M4, 0x3, false }, // 2554 |
2632 | | { PseudoVSSRL_VI_M8_MASK, PseudoVSSRL_VI_M8, 0x3, false }, // 2555 |
2633 | | { PseudoVSSRL_VI_MF2_MASK, PseudoVSSRL_VI_MF2, 0x3, false }, // 2556 |
2634 | | { PseudoVSSRL_VI_MF4_MASK, PseudoVSSRL_VI_MF4, 0x3, false }, // 2557 |
2635 | | { PseudoVSSRL_VI_MF8_MASK, PseudoVSSRL_VI_MF8, 0x3, false }, // 2558 |
2636 | | { PseudoVSSRL_VV_M1_MASK, PseudoVSSRL_VV_M1, 0x3, false }, // 2559 |
2637 | | { PseudoVSSRL_VV_M2_MASK, PseudoVSSRL_VV_M2, 0x3, false }, // 2560 |
2638 | | { PseudoVSSRL_VV_M4_MASK, PseudoVSSRL_VV_M4, 0x3, false }, // 2561 |
2639 | | { PseudoVSSRL_VV_M8_MASK, PseudoVSSRL_VV_M8, 0x3, false }, // 2562 |
2640 | | { PseudoVSSRL_VV_MF2_MASK, PseudoVSSRL_VV_MF2, 0x3, false }, // 2563 |
2641 | | { PseudoVSSRL_VV_MF4_MASK, PseudoVSSRL_VV_MF4, 0x3, false }, // 2564 |
2642 | | { PseudoVSSRL_VV_MF8_MASK, PseudoVSSRL_VV_MF8, 0x3, false }, // 2565 |
2643 | | { PseudoVSSRL_VX_M1_MASK, PseudoVSSRL_VX_M1, 0x3, false }, // 2566 |
2644 | | { PseudoVSSRL_VX_M2_MASK, PseudoVSSRL_VX_M2, 0x3, false }, // 2567 |
2645 | | { PseudoVSSRL_VX_M4_MASK, PseudoVSSRL_VX_M4, 0x3, false }, // 2568 |
2646 | | { PseudoVSSRL_VX_M8_MASK, PseudoVSSRL_VX_M8, 0x3, false }, // 2569 |
2647 | | { PseudoVSSRL_VX_MF2_MASK, PseudoVSSRL_VX_MF2, 0x3, false }, // 2570 |
2648 | | { PseudoVSSRL_VX_MF4_MASK, PseudoVSSRL_VX_MF4, 0x3, false }, // 2571 |
2649 | | { PseudoVSSRL_VX_MF8_MASK, PseudoVSSRL_VX_MF8, 0x3, false }, // 2572 |
2650 | | { PseudoVSSUBU_VV_M1_MASK, PseudoVSSUBU_VV_M1, 0x3, false }, // 2573 |
2651 | | { PseudoVSSUBU_VV_M2_MASK, PseudoVSSUBU_VV_M2, 0x3, false }, // 2574 |
2652 | | { PseudoVSSUBU_VV_M4_MASK, PseudoVSSUBU_VV_M4, 0x3, false }, // 2575 |
2653 | | { PseudoVSSUBU_VV_M8_MASK, PseudoVSSUBU_VV_M8, 0x3, false }, // 2576 |
2654 | | { PseudoVSSUBU_VV_MF2_MASK, PseudoVSSUBU_VV_MF2, 0x3, false }, // 2577 |
2655 | | { PseudoVSSUBU_VV_MF4_MASK, PseudoVSSUBU_VV_MF4, 0x3, false }, // 2578 |
2656 | | { PseudoVSSUBU_VV_MF8_MASK, PseudoVSSUBU_VV_MF8, 0x3, false }, // 2579 |
2657 | | { PseudoVSSUBU_VX_M1_MASK, PseudoVSSUBU_VX_M1, 0x3, false }, // 2580 |
2658 | | { PseudoVSSUBU_VX_M2_MASK, PseudoVSSUBU_VX_M2, 0x3, false }, // 2581 |
2659 | | { PseudoVSSUBU_VX_M4_MASK, PseudoVSSUBU_VX_M4, 0x3, false }, // 2582 |
2660 | | { PseudoVSSUBU_VX_M8_MASK, PseudoVSSUBU_VX_M8, 0x3, false }, // 2583 |
2661 | | { PseudoVSSUBU_VX_MF2_MASK, PseudoVSSUBU_VX_MF2, 0x3, false }, // 2584 |
2662 | | { PseudoVSSUBU_VX_MF4_MASK, PseudoVSSUBU_VX_MF4, 0x3, false }, // 2585 |
2663 | | { PseudoVSSUBU_VX_MF8_MASK, PseudoVSSUBU_VX_MF8, 0x3, false }, // 2586 |
2664 | | { PseudoVSSUB_VV_M1_MASK, PseudoVSSUB_VV_M1, 0x3, false }, // 2587 |
2665 | | { PseudoVSSUB_VV_M2_MASK, PseudoVSSUB_VV_M2, 0x3, false }, // 2588 |
2666 | | { PseudoVSSUB_VV_M4_MASK, PseudoVSSUB_VV_M4, 0x3, false }, // 2589 |
2667 | | { PseudoVSSUB_VV_M8_MASK, PseudoVSSUB_VV_M8, 0x3, false }, // 2590 |
2668 | | { PseudoVSSUB_VV_MF2_MASK, PseudoVSSUB_VV_MF2, 0x3, false }, // 2591 |
2669 | | { PseudoVSSUB_VV_MF4_MASK, PseudoVSSUB_VV_MF4, 0x3, false }, // 2592 |
2670 | | { PseudoVSSUB_VV_MF8_MASK, PseudoVSSUB_VV_MF8, 0x3, false }, // 2593 |
2671 | | { PseudoVSSUB_VX_M1_MASK, PseudoVSSUB_VX_M1, 0x3, false }, // 2594 |
2672 | | { PseudoVSSUB_VX_M2_MASK, PseudoVSSUB_VX_M2, 0x3, false }, // 2595 |
2673 | | { PseudoVSSUB_VX_M4_MASK, PseudoVSSUB_VX_M4, 0x3, false }, // 2596 |
2674 | | { PseudoVSSUB_VX_M8_MASK, PseudoVSSUB_VX_M8, 0x3, false }, // 2597 |
2675 | | { PseudoVSSUB_VX_MF2_MASK, PseudoVSSUB_VX_MF2, 0x3, false }, // 2598 |
2676 | | { PseudoVSSUB_VX_MF4_MASK, PseudoVSSUB_VX_MF4, 0x3, false }, // 2599 |
2677 | | { PseudoVSSUB_VX_MF8_MASK, PseudoVSSUB_VX_MF8, 0x3, false }, // 2600 |
2678 | | { PseudoVSUB_VV_M1_MASK, PseudoVSUB_VV_M1, 0x3, false }, // 2601 |
2679 | | { PseudoVSUB_VV_M2_MASK, PseudoVSUB_VV_M2, 0x3, false }, // 2602 |
2680 | | { PseudoVSUB_VV_M4_MASK, PseudoVSUB_VV_M4, 0x3, false }, // 2603 |
2681 | | { PseudoVSUB_VV_M8_MASK, PseudoVSUB_VV_M8, 0x3, false }, // 2604 |
2682 | | { PseudoVSUB_VV_MF2_MASK, PseudoVSUB_VV_MF2, 0x3, false }, // 2605 |
2683 | | { PseudoVSUB_VV_MF4_MASK, PseudoVSUB_VV_MF4, 0x3, false }, // 2606 |
2684 | | { PseudoVSUB_VV_MF8_MASK, PseudoVSUB_VV_MF8, 0x3, false }, // 2607 |
2685 | | { PseudoVSUB_VX_M1_MASK, PseudoVSUB_VX_M1, 0x3, false }, // 2608 |
2686 | | { PseudoVSUB_VX_M2_MASK, PseudoVSUB_VX_M2, 0x3, false }, // 2609 |
2687 | | { PseudoVSUB_VX_M4_MASK, PseudoVSUB_VX_M4, 0x3, false }, // 2610 |
2688 | | { PseudoVSUB_VX_M8_MASK, PseudoVSUB_VX_M8, 0x3, false }, // 2611 |
2689 | | { PseudoVSUB_VX_MF2_MASK, PseudoVSUB_VX_MF2, 0x3, false }, // 2612 |
2690 | | { PseudoVSUB_VX_MF4_MASK, PseudoVSUB_VX_MF4, 0x3, false }, // 2613 |
2691 | | { PseudoVSUB_VX_MF8_MASK, PseudoVSUB_VX_MF8, 0x3, false }, // 2614 |
2692 | | { PseudoVWADDU_VV_M1_MASK, PseudoVWADDU_VV_M1, 0x3, false }, // 2615 |
2693 | | { PseudoVWADDU_VV_M2_MASK, PseudoVWADDU_VV_M2, 0x3, false }, // 2616 |
2694 | | { PseudoVWADDU_VV_M4_MASK, PseudoVWADDU_VV_M4, 0x3, false }, // 2617 |
2695 | | { PseudoVWADDU_VV_MF2_MASK, PseudoVWADDU_VV_MF2, 0x3, false }, // 2618 |
2696 | | { PseudoVWADDU_VV_MF4_MASK, PseudoVWADDU_VV_MF4, 0x3, false }, // 2619 |
2697 | | { PseudoVWADDU_VV_MF8_MASK, PseudoVWADDU_VV_MF8, 0x3, false }, // 2620 |
2698 | | { PseudoVWADDU_VX_M1_MASK, PseudoVWADDU_VX_M1, 0x3, false }, // 2621 |
2699 | | { PseudoVWADDU_VX_M2_MASK, PseudoVWADDU_VX_M2, 0x3, false }, // 2622 |
2700 | | { PseudoVWADDU_VX_M4_MASK, PseudoVWADDU_VX_M4, 0x3, false }, // 2623 |
2701 | | { PseudoVWADDU_VX_MF2_MASK, PseudoVWADDU_VX_MF2, 0x3, false }, // 2624 |
2702 | | { PseudoVWADDU_VX_MF4_MASK, PseudoVWADDU_VX_MF4, 0x3, false }, // 2625 |
2703 | | { PseudoVWADDU_VX_MF8_MASK, PseudoVWADDU_VX_MF8, 0x3, false }, // 2626 |
2704 | | { PseudoVWADDU_WV_M1_MASK, PseudoVWADDU_WV_M1, 0x3, false }, // 2627 |
2705 | | { PseudoVWADDU_WV_M2_MASK, PseudoVWADDU_WV_M2, 0x3, false }, // 2628 |
2706 | | { PseudoVWADDU_WV_M4_MASK, PseudoVWADDU_WV_M4, 0x3, false }, // 2629 |
2707 | | { PseudoVWADDU_WV_MF2_MASK, PseudoVWADDU_WV_MF2, 0x3, false }, // 2630 |
2708 | | { PseudoVWADDU_WV_MF4_MASK, PseudoVWADDU_WV_MF4, 0x3, false }, // 2631 |
2709 | | { PseudoVWADDU_WV_MF8_MASK, PseudoVWADDU_WV_MF8, 0x3, false }, // 2632 |
2710 | | { PseudoVWADDU_WX_M1_MASK, PseudoVWADDU_WX_M1, 0x3, false }, // 2633 |
2711 | | { PseudoVWADDU_WX_M2_MASK, PseudoVWADDU_WX_M2, 0x3, false }, // 2634 |
2712 | | { PseudoVWADDU_WX_M4_MASK, PseudoVWADDU_WX_M4, 0x3, false }, // 2635 |
2713 | | { PseudoVWADDU_WX_MF2_MASK, PseudoVWADDU_WX_MF2, 0x3, false }, // 2636 |
2714 | | { PseudoVWADDU_WX_MF4_MASK, PseudoVWADDU_WX_MF4, 0x3, false }, // 2637 |
2715 | | { PseudoVWADDU_WX_MF8_MASK, PseudoVWADDU_WX_MF8, 0x3, false }, // 2638 |
2716 | | { PseudoVWADD_VV_M1_MASK, PseudoVWADD_VV_M1, 0x3, false }, // 2639 |
2717 | | { PseudoVWADD_VV_M2_MASK, PseudoVWADD_VV_M2, 0x3, false }, // 2640 |
2718 | | { PseudoVWADD_VV_M4_MASK, PseudoVWADD_VV_M4, 0x3, false }, // 2641 |
2719 | | { PseudoVWADD_VV_MF2_MASK, PseudoVWADD_VV_MF2, 0x3, false }, // 2642 |
2720 | | { PseudoVWADD_VV_MF4_MASK, PseudoVWADD_VV_MF4, 0x3, false }, // 2643 |
2721 | | { PseudoVWADD_VV_MF8_MASK, PseudoVWADD_VV_MF8, 0x3, false }, // 2644 |
2722 | | { PseudoVWADD_VX_M1_MASK, PseudoVWADD_VX_M1, 0x3, false }, // 2645 |
2723 | | { PseudoVWADD_VX_M2_MASK, PseudoVWADD_VX_M2, 0x3, false }, // 2646 |
2724 | | { PseudoVWADD_VX_M4_MASK, PseudoVWADD_VX_M4, 0x3, false }, // 2647 |
2725 | | { PseudoVWADD_VX_MF2_MASK, PseudoVWADD_VX_MF2, 0x3, false }, // 2648 |
2726 | | { PseudoVWADD_VX_MF4_MASK, PseudoVWADD_VX_MF4, 0x3, false }, // 2649 |
2727 | | { PseudoVWADD_VX_MF8_MASK, PseudoVWADD_VX_MF8, 0x3, false }, // 2650 |
2728 | | { PseudoVWADD_WV_M1_MASK, PseudoVWADD_WV_M1, 0x3, false }, // 2651 |
2729 | | { PseudoVWADD_WV_M2_MASK, PseudoVWADD_WV_M2, 0x3, false }, // 2652 |
2730 | | { PseudoVWADD_WV_M4_MASK, PseudoVWADD_WV_M4, 0x3, false }, // 2653 |
2731 | | { PseudoVWADD_WV_MF2_MASK, PseudoVWADD_WV_MF2, 0x3, false }, // 2654 |
2732 | | { PseudoVWADD_WV_MF4_MASK, PseudoVWADD_WV_MF4, 0x3, false }, // 2655 |
2733 | | { PseudoVWADD_WV_MF8_MASK, PseudoVWADD_WV_MF8, 0x3, false }, // 2656 |
2734 | | { PseudoVWADD_WX_M1_MASK, PseudoVWADD_WX_M1, 0x3, false }, // 2657 |
2735 | | { PseudoVWADD_WX_M2_MASK, PseudoVWADD_WX_M2, 0x3, false }, // 2658 |
2736 | | { PseudoVWADD_WX_M4_MASK, PseudoVWADD_WX_M4, 0x3, false }, // 2659 |
2737 | | { PseudoVWADD_WX_MF2_MASK, PseudoVWADD_WX_MF2, 0x3, false }, // 2660 |
2738 | | { PseudoVWADD_WX_MF4_MASK, PseudoVWADD_WX_MF4, 0x3, false }, // 2661 |
2739 | | { PseudoVWADD_WX_MF8_MASK, PseudoVWADD_WX_MF8, 0x3, false }, // 2662 |
2740 | | { PseudoVWMACCSU_VV_M1_MASK, PseudoVWMACCSU_VV_M1, 0x3, false }, // 2663 |
2741 | | { PseudoVWMACCSU_VV_M2_MASK, PseudoVWMACCSU_VV_M2, 0x3, false }, // 2664 |
2742 | | { PseudoVWMACCSU_VV_M4_MASK, PseudoVWMACCSU_VV_M4, 0x3, false }, // 2665 |
2743 | | { PseudoVWMACCSU_VV_MF2_MASK, PseudoVWMACCSU_VV_MF2, 0x3, false }, // 2666 |
2744 | | { PseudoVWMACCSU_VV_MF4_MASK, PseudoVWMACCSU_VV_MF4, 0x3, false }, // 2667 |
2745 | | { PseudoVWMACCSU_VV_MF8_MASK, PseudoVWMACCSU_VV_MF8, 0x3, false }, // 2668 |
2746 | | { PseudoVWMACCSU_VX_M1_MASK, PseudoVWMACCSU_VX_M1, 0x3, false }, // 2669 |
2747 | | { PseudoVWMACCSU_VX_M2_MASK, PseudoVWMACCSU_VX_M2, 0x3, false }, // 2670 |
2748 | | { PseudoVWMACCSU_VX_M4_MASK, PseudoVWMACCSU_VX_M4, 0x3, false }, // 2671 |
2749 | | { PseudoVWMACCSU_VX_MF2_MASK, PseudoVWMACCSU_VX_MF2, 0x3, false }, // 2672 |
2750 | | { PseudoVWMACCSU_VX_MF4_MASK, PseudoVWMACCSU_VX_MF4, 0x3, false }, // 2673 |
2751 | | { PseudoVWMACCSU_VX_MF8_MASK, PseudoVWMACCSU_VX_MF8, 0x3, false }, // 2674 |
2752 | | { PseudoVWMACCUS_VX_M1_MASK, PseudoVWMACCUS_VX_M1, 0x3, false }, // 2675 |
2753 | | { PseudoVWMACCUS_VX_M2_MASK, PseudoVWMACCUS_VX_M2, 0x3, false }, // 2676 |
2754 | | { PseudoVWMACCUS_VX_M4_MASK, PseudoVWMACCUS_VX_M4, 0x3, false }, // 2677 |
2755 | | { PseudoVWMACCUS_VX_MF2_MASK, PseudoVWMACCUS_VX_MF2, 0x3, false }, // 2678 |
2756 | | { PseudoVWMACCUS_VX_MF4_MASK, PseudoVWMACCUS_VX_MF4, 0x3, false }, // 2679 |
2757 | | { PseudoVWMACCUS_VX_MF8_MASK, PseudoVWMACCUS_VX_MF8, 0x3, false }, // 2680 |
2758 | | { PseudoVWMACCU_VV_M1_MASK, PseudoVWMACCU_VV_M1, 0x3, false }, // 2681 |
2759 | | { PseudoVWMACCU_VV_M2_MASK, PseudoVWMACCU_VV_M2, 0x3, false }, // 2682 |
2760 | | { PseudoVWMACCU_VV_M4_MASK, PseudoVWMACCU_VV_M4, 0x3, false }, // 2683 |
2761 | | { PseudoVWMACCU_VV_MF2_MASK, PseudoVWMACCU_VV_MF2, 0x3, false }, // 2684 |
2762 | | { PseudoVWMACCU_VV_MF4_MASK, PseudoVWMACCU_VV_MF4, 0x3, false }, // 2685 |
2763 | | { PseudoVWMACCU_VV_MF8_MASK, PseudoVWMACCU_VV_MF8, 0x3, false }, // 2686 |
2764 | | { PseudoVWMACCU_VX_M1_MASK, PseudoVWMACCU_VX_M1, 0x3, false }, // 2687 |
2765 | | { PseudoVWMACCU_VX_M2_MASK, PseudoVWMACCU_VX_M2, 0x3, false }, // 2688 |
2766 | | { PseudoVWMACCU_VX_M4_MASK, PseudoVWMACCU_VX_M4, 0x3, false }, // 2689 |
2767 | | { PseudoVWMACCU_VX_MF2_MASK, PseudoVWMACCU_VX_MF2, 0x3, false }, // 2690 |
2768 | | { PseudoVWMACCU_VX_MF4_MASK, PseudoVWMACCU_VX_MF4, 0x3, false }, // 2691 |
2769 | | { PseudoVWMACCU_VX_MF8_MASK, PseudoVWMACCU_VX_MF8, 0x3, false }, // 2692 |
2770 | | { PseudoVWMACC_VV_M1_MASK, PseudoVWMACC_VV_M1, 0x3, false }, // 2693 |
2771 | | { PseudoVWMACC_VV_M2_MASK, PseudoVWMACC_VV_M2, 0x3, false }, // 2694 |
2772 | | { PseudoVWMACC_VV_M4_MASK, PseudoVWMACC_VV_M4, 0x3, false }, // 2695 |
2773 | | { PseudoVWMACC_VV_MF2_MASK, PseudoVWMACC_VV_MF2, 0x3, false }, // 2696 |
2774 | | { PseudoVWMACC_VV_MF4_MASK, PseudoVWMACC_VV_MF4, 0x3, false }, // 2697 |
2775 | | { PseudoVWMACC_VV_MF8_MASK, PseudoVWMACC_VV_MF8, 0x3, false }, // 2698 |
2776 | | { PseudoVWMACC_VX_M1_MASK, PseudoVWMACC_VX_M1, 0x3, false }, // 2699 |
2777 | | { PseudoVWMACC_VX_M2_MASK, PseudoVWMACC_VX_M2, 0x3, false }, // 2700 |
2778 | | { PseudoVWMACC_VX_M4_MASK, PseudoVWMACC_VX_M4, 0x3, false }, // 2701 |
2779 | | { PseudoVWMACC_VX_MF2_MASK, PseudoVWMACC_VX_MF2, 0x3, false }, // 2702 |
2780 | | { PseudoVWMACC_VX_MF4_MASK, PseudoVWMACC_VX_MF4, 0x3, false }, // 2703 |
2781 | | { PseudoVWMACC_VX_MF8_MASK, PseudoVWMACC_VX_MF8, 0x3, false }, // 2704 |
2782 | | { PseudoVWMULSU_VV_M1_MASK, PseudoVWMULSU_VV_M1, 0x3, false }, // 2705 |
2783 | | { PseudoVWMULSU_VV_M2_MASK, PseudoVWMULSU_VV_M2, 0x3, false }, // 2706 |
2784 | | { PseudoVWMULSU_VV_M4_MASK, PseudoVWMULSU_VV_M4, 0x3, false }, // 2707 |
2785 | | { PseudoVWMULSU_VV_MF2_MASK, PseudoVWMULSU_VV_MF2, 0x3, false }, // 2708 |
2786 | | { PseudoVWMULSU_VV_MF4_MASK, PseudoVWMULSU_VV_MF4, 0x3, false }, // 2709 |
2787 | | { PseudoVWMULSU_VV_MF8_MASK, PseudoVWMULSU_VV_MF8, 0x3, false }, // 2710 |
2788 | | { PseudoVWMULSU_VX_M1_MASK, PseudoVWMULSU_VX_M1, 0x3, false }, // 2711 |
2789 | | { PseudoVWMULSU_VX_M2_MASK, PseudoVWMULSU_VX_M2, 0x3, false }, // 2712 |
2790 | | { PseudoVWMULSU_VX_M4_MASK, PseudoVWMULSU_VX_M4, 0x3, false }, // 2713 |
2791 | | { PseudoVWMULSU_VX_MF2_MASK, PseudoVWMULSU_VX_MF2, 0x3, false }, // 2714 |
2792 | | { PseudoVWMULSU_VX_MF4_MASK, PseudoVWMULSU_VX_MF4, 0x3, false }, // 2715 |
2793 | | { PseudoVWMULSU_VX_MF8_MASK, PseudoVWMULSU_VX_MF8, 0x3, false }, // 2716 |
2794 | | { PseudoVWMULU_VV_M1_MASK, PseudoVWMULU_VV_M1, 0x3, false }, // 2717 |
2795 | | { PseudoVWMULU_VV_M2_MASK, PseudoVWMULU_VV_M2, 0x3, false }, // 2718 |
2796 | | { PseudoVWMULU_VV_M4_MASK, PseudoVWMULU_VV_M4, 0x3, false }, // 2719 |
2797 | | { PseudoVWMULU_VV_MF2_MASK, PseudoVWMULU_VV_MF2, 0x3, false }, // 2720 |
2798 | | { PseudoVWMULU_VV_MF4_MASK, PseudoVWMULU_VV_MF4, 0x3, false }, // 2721 |
2799 | | { PseudoVWMULU_VV_MF8_MASK, PseudoVWMULU_VV_MF8, 0x3, false }, // 2722 |
2800 | | { PseudoVWMULU_VX_M1_MASK, PseudoVWMULU_VX_M1, 0x3, false }, // 2723 |
2801 | | { PseudoVWMULU_VX_M2_MASK, PseudoVWMULU_VX_M2, 0x3, false }, // 2724 |
2802 | | { PseudoVWMULU_VX_M4_MASK, PseudoVWMULU_VX_M4, 0x3, false }, // 2725 |
2803 | | { PseudoVWMULU_VX_MF2_MASK, PseudoVWMULU_VX_MF2, 0x3, false }, // 2726 |
2804 | | { PseudoVWMULU_VX_MF4_MASK, PseudoVWMULU_VX_MF4, 0x3, false }, // 2727 |
2805 | | { PseudoVWMULU_VX_MF8_MASK, PseudoVWMULU_VX_MF8, 0x3, false }, // 2728 |
2806 | | { PseudoVWMUL_VV_M1_MASK, PseudoVWMUL_VV_M1, 0x3, false }, // 2729 |
2807 | | { PseudoVWMUL_VV_M2_MASK, PseudoVWMUL_VV_M2, 0x3, false }, // 2730 |
2808 | | { PseudoVWMUL_VV_M4_MASK, PseudoVWMUL_VV_M4, 0x3, false }, // 2731 |
2809 | | { PseudoVWMUL_VV_MF2_MASK, PseudoVWMUL_VV_MF2, 0x3, false }, // 2732 |
2810 | | { PseudoVWMUL_VV_MF4_MASK, PseudoVWMUL_VV_MF4, 0x3, false }, // 2733 |
2811 | | { PseudoVWMUL_VV_MF8_MASK, PseudoVWMUL_VV_MF8, 0x3, false }, // 2734 |
2812 | | { PseudoVWMUL_VX_M1_MASK, PseudoVWMUL_VX_M1, 0x3, false }, // 2735 |
2813 | | { PseudoVWMUL_VX_M2_MASK, PseudoVWMUL_VX_M2, 0x3, false }, // 2736 |
2814 | | { PseudoVWMUL_VX_M4_MASK, PseudoVWMUL_VX_M4, 0x3, false }, // 2737 |
2815 | | { PseudoVWMUL_VX_MF2_MASK, PseudoVWMUL_VX_MF2, 0x3, false }, // 2738 |
2816 | | { PseudoVWMUL_VX_MF4_MASK, PseudoVWMUL_VX_MF4, 0x3, false }, // 2739 |
2817 | | { PseudoVWMUL_VX_MF8_MASK, PseudoVWMUL_VX_MF8, 0x3, false }, // 2740 |
2818 | | { PseudoVWREDSUMU_VS_M1_E16_MASK, PseudoVWREDSUMU_VS_M1_E16, 0x3, true }, // 2741 |
2819 | | { PseudoVWREDSUMU_VS_M1_E32_MASK, PseudoVWREDSUMU_VS_M1_E32, 0x3, true }, // 2742 |
2820 | | { PseudoVWREDSUMU_VS_M1_E8_MASK, PseudoVWREDSUMU_VS_M1_E8, 0x3, true }, // 2743 |
2821 | | { PseudoVWREDSUMU_VS_M2_E16_MASK, PseudoVWREDSUMU_VS_M2_E16, 0x3, true }, // 2744 |
2822 | | { PseudoVWREDSUMU_VS_M2_E32_MASK, PseudoVWREDSUMU_VS_M2_E32, 0x3, true }, // 2745 |
2823 | | { PseudoVWREDSUMU_VS_M2_E8_MASK, PseudoVWREDSUMU_VS_M2_E8, 0x3, true }, // 2746 |
2824 | | { PseudoVWREDSUMU_VS_M4_E16_MASK, PseudoVWREDSUMU_VS_M4_E16, 0x3, true }, // 2747 |
2825 | | { PseudoVWREDSUMU_VS_M4_E32_MASK, PseudoVWREDSUMU_VS_M4_E32, 0x3, true }, // 2748 |
2826 | | { PseudoVWREDSUMU_VS_M4_E8_MASK, PseudoVWREDSUMU_VS_M4_E8, 0x3, true }, // 2749 |
2827 | | { PseudoVWREDSUMU_VS_M8_E16_MASK, PseudoVWREDSUMU_VS_M8_E16, 0x3, true }, // 2750 |
2828 | | { PseudoVWREDSUMU_VS_M8_E32_MASK, PseudoVWREDSUMU_VS_M8_E32, 0x3, true }, // 2751 |
2829 | | { PseudoVWREDSUMU_VS_M8_E8_MASK, PseudoVWREDSUMU_VS_M8_E8, 0x3, true }, // 2752 |
2830 | | { PseudoVWREDSUMU_VS_MF2_E16_MASK, PseudoVWREDSUMU_VS_MF2_E16, 0x3, true }, // 2753 |
2831 | | { PseudoVWREDSUMU_VS_MF2_E32_MASK, PseudoVWREDSUMU_VS_MF2_E32, 0x3, true }, // 2754 |
2832 | | { PseudoVWREDSUMU_VS_MF2_E8_MASK, PseudoVWREDSUMU_VS_MF2_E8, 0x3, true }, // 2755 |
2833 | | { PseudoVWREDSUMU_VS_MF4_E16_MASK, PseudoVWREDSUMU_VS_MF4_E16, 0x3, true }, // 2756 |
2834 | | { PseudoVWREDSUMU_VS_MF4_E8_MASK, PseudoVWREDSUMU_VS_MF4_E8, 0x3, true }, // 2757 |
2835 | | { PseudoVWREDSUMU_VS_MF8_E8_MASK, PseudoVWREDSUMU_VS_MF8_E8, 0x3, true }, // 2758 |
2836 | | { PseudoVWREDSUM_VS_M1_E16_MASK, PseudoVWREDSUM_VS_M1_E16, 0x3, true }, // 2759 |
2837 | | { PseudoVWREDSUM_VS_M1_E32_MASK, PseudoVWREDSUM_VS_M1_E32, 0x3, true }, // 2760 |
2838 | | { PseudoVWREDSUM_VS_M1_E8_MASK, PseudoVWREDSUM_VS_M1_E8, 0x3, true }, // 2761 |
2839 | | { PseudoVWREDSUM_VS_M2_E16_MASK, PseudoVWREDSUM_VS_M2_E16, 0x3, true }, // 2762 |
2840 | | { PseudoVWREDSUM_VS_M2_E32_MASK, PseudoVWREDSUM_VS_M2_E32, 0x3, true }, // 2763 |
2841 | | { PseudoVWREDSUM_VS_M2_E8_MASK, PseudoVWREDSUM_VS_M2_E8, 0x3, true }, // 2764 |
2842 | | { PseudoVWREDSUM_VS_M4_E16_MASK, PseudoVWREDSUM_VS_M4_E16, 0x3, true }, // 2765 |
2843 | | { PseudoVWREDSUM_VS_M4_E32_MASK, PseudoVWREDSUM_VS_M4_E32, 0x3, true }, // 2766 |
2844 | | { PseudoVWREDSUM_VS_M4_E8_MASK, PseudoVWREDSUM_VS_M4_E8, 0x3, true }, // 2767 |
2845 | | { PseudoVWREDSUM_VS_M8_E16_MASK, PseudoVWREDSUM_VS_M8_E16, 0x3, true }, // 2768 |
2846 | | { PseudoVWREDSUM_VS_M8_E32_MASK, PseudoVWREDSUM_VS_M8_E32, 0x3, true }, // 2769 |
2847 | | { PseudoVWREDSUM_VS_M8_E8_MASK, PseudoVWREDSUM_VS_M8_E8, 0x3, true }, // 2770 |
2848 | | { PseudoVWREDSUM_VS_MF2_E16_MASK, PseudoVWREDSUM_VS_MF2_E16, 0x3, true }, // 2771 |
2849 | | { PseudoVWREDSUM_VS_MF2_E32_MASK, PseudoVWREDSUM_VS_MF2_E32, 0x3, true }, // 2772 |
2850 | | { PseudoVWREDSUM_VS_MF2_E8_MASK, PseudoVWREDSUM_VS_MF2_E8, 0x3, true }, // 2773 |
2851 | | { PseudoVWREDSUM_VS_MF4_E16_MASK, PseudoVWREDSUM_VS_MF4_E16, 0x3, true }, // 2774 |
2852 | | { PseudoVWREDSUM_VS_MF4_E8_MASK, PseudoVWREDSUM_VS_MF4_E8, 0x3, true }, // 2775 |
2853 | | { PseudoVWREDSUM_VS_MF8_E8_MASK, PseudoVWREDSUM_VS_MF8_E8, 0x3, true }, // 2776 |
2854 | | { PseudoVWSLL_VI_M1_MASK, PseudoVWSLL_VI_M1, 0x3, false }, // 2777 |
2855 | | { PseudoVWSLL_VI_M2_MASK, PseudoVWSLL_VI_M2, 0x3, false }, // 2778 |
2856 | | { PseudoVWSLL_VI_M4_MASK, PseudoVWSLL_VI_M4, 0x3, false }, // 2779 |
2857 | | { PseudoVWSLL_VI_MF2_MASK, PseudoVWSLL_VI_MF2, 0x3, false }, // 2780 |
2858 | | { PseudoVWSLL_VI_MF4_MASK, PseudoVWSLL_VI_MF4, 0x3, false }, // 2781 |
2859 | | { PseudoVWSLL_VI_MF8_MASK, PseudoVWSLL_VI_MF8, 0x3, false }, // 2782 |
2860 | | { PseudoVWSLL_VV_M1_MASK, PseudoVWSLL_VV_M1, 0x3, false }, // 2783 |
2861 | | { PseudoVWSLL_VV_M2_MASK, PseudoVWSLL_VV_M2, 0x3, false }, // 2784 |
2862 | | { PseudoVWSLL_VV_M4_MASK, PseudoVWSLL_VV_M4, 0x3, false }, // 2785 |
2863 | | { PseudoVWSLL_VV_MF2_MASK, PseudoVWSLL_VV_MF2, 0x3, false }, // 2786 |
2864 | | { PseudoVWSLL_VV_MF4_MASK, PseudoVWSLL_VV_MF4, 0x3, false }, // 2787 |
2865 | | { PseudoVWSLL_VV_MF8_MASK, PseudoVWSLL_VV_MF8, 0x3, false }, // 2788 |
2866 | | { PseudoVWSLL_VX_M1_MASK, PseudoVWSLL_VX_M1, 0x3, false }, // 2789 |
2867 | | { PseudoVWSLL_VX_M2_MASK, PseudoVWSLL_VX_M2, 0x3, false }, // 2790 |
2868 | | { PseudoVWSLL_VX_M4_MASK, PseudoVWSLL_VX_M4, 0x3, false }, // 2791 |
2869 | | { PseudoVWSLL_VX_MF2_MASK, PseudoVWSLL_VX_MF2, 0x3, false }, // 2792 |
2870 | | { PseudoVWSLL_VX_MF4_MASK, PseudoVWSLL_VX_MF4, 0x3, false }, // 2793 |
2871 | | { PseudoVWSLL_VX_MF8_MASK, PseudoVWSLL_VX_MF8, 0x3, false }, // 2794 |
2872 | | { PseudoVWSUBU_VV_M1_MASK, PseudoVWSUBU_VV_M1, 0x3, false }, // 2795 |
2873 | | { PseudoVWSUBU_VV_M2_MASK, PseudoVWSUBU_VV_M2, 0x3, false }, // 2796 |
2874 | | { PseudoVWSUBU_VV_M4_MASK, PseudoVWSUBU_VV_M4, 0x3, false }, // 2797 |
2875 | | { PseudoVWSUBU_VV_MF2_MASK, PseudoVWSUBU_VV_MF2, 0x3, false }, // 2798 |
2876 | | { PseudoVWSUBU_VV_MF4_MASK, PseudoVWSUBU_VV_MF4, 0x3, false }, // 2799 |
2877 | | { PseudoVWSUBU_VV_MF8_MASK, PseudoVWSUBU_VV_MF8, 0x3, false }, // 2800 |
2878 | | { PseudoVWSUBU_VX_M1_MASK, PseudoVWSUBU_VX_M1, 0x3, false }, // 2801 |
2879 | | { PseudoVWSUBU_VX_M2_MASK, PseudoVWSUBU_VX_M2, 0x3, false }, // 2802 |
2880 | | { PseudoVWSUBU_VX_M4_MASK, PseudoVWSUBU_VX_M4, 0x3, false }, // 2803 |
2881 | | { PseudoVWSUBU_VX_MF2_MASK, PseudoVWSUBU_VX_MF2, 0x3, false }, // 2804 |
2882 | | { PseudoVWSUBU_VX_MF4_MASK, PseudoVWSUBU_VX_MF4, 0x3, false }, // 2805 |
2883 | | { PseudoVWSUBU_VX_MF8_MASK, PseudoVWSUBU_VX_MF8, 0x3, false }, // 2806 |
2884 | | { PseudoVWSUBU_WV_M1_MASK, PseudoVWSUBU_WV_M1, 0x3, false }, // 2807 |
2885 | | { PseudoVWSUBU_WV_M2_MASK, PseudoVWSUBU_WV_M2, 0x3, false }, // 2808 |
2886 | | { PseudoVWSUBU_WV_M4_MASK, PseudoVWSUBU_WV_M4, 0x3, false }, // 2809 |
2887 | | { PseudoVWSUBU_WV_MF2_MASK, PseudoVWSUBU_WV_MF2, 0x3, false }, // 2810 |
2888 | | { PseudoVWSUBU_WV_MF4_MASK, PseudoVWSUBU_WV_MF4, 0x3, false }, // 2811 |
2889 | | { PseudoVWSUBU_WV_MF8_MASK, PseudoVWSUBU_WV_MF8, 0x3, false }, // 2812 |
2890 | | { PseudoVWSUBU_WX_M1_MASK, PseudoVWSUBU_WX_M1, 0x3, false }, // 2813 |
2891 | | { PseudoVWSUBU_WX_M2_MASK, PseudoVWSUBU_WX_M2, 0x3, false }, // 2814 |
2892 | | { PseudoVWSUBU_WX_M4_MASK, PseudoVWSUBU_WX_M4, 0x3, false }, // 2815 |
2893 | | { PseudoVWSUBU_WX_MF2_MASK, PseudoVWSUBU_WX_MF2, 0x3, false }, // 2816 |
2894 | | { PseudoVWSUBU_WX_MF4_MASK, PseudoVWSUBU_WX_MF4, 0x3, false }, // 2817 |
2895 | | { PseudoVWSUBU_WX_MF8_MASK, PseudoVWSUBU_WX_MF8, 0x3, false }, // 2818 |
2896 | | { PseudoVWSUB_VV_M1_MASK, PseudoVWSUB_VV_M1, 0x3, false }, // 2819 |
2897 | | { PseudoVWSUB_VV_M2_MASK, PseudoVWSUB_VV_M2, 0x3, false }, // 2820 |
2898 | | { PseudoVWSUB_VV_M4_MASK, PseudoVWSUB_VV_M4, 0x3, false }, // 2821 |
2899 | | { PseudoVWSUB_VV_MF2_MASK, PseudoVWSUB_VV_MF2, 0x3, false }, // 2822 |
2900 | | { PseudoVWSUB_VV_MF4_MASK, PseudoVWSUB_VV_MF4, 0x3, false }, // 2823 |
2901 | | { PseudoVWSUB_VV_MF8_MASK, PseudoVWSUB_VV_MF8, 0x3, false }, // 2824 |
2902 | | { PseudoVWSUB_VX_M1_MASK, PseudoVWSUB_VX_M1, 0x3, false }, // 2825 |
2903 | | { PseudoVWSUB_VX_M2_MASK, PseudoVWSUB_VX_M2, 0x3, false }, // 2826 |
2904 | | { PseudoVWSUB_VX_M4_MASK, PseudoVWSUB_VX_M4, 0x3, false }, // 2827 |
2905 | | { PseudoVWSUB_VX_MF2_MASK, PseudoVWSUB_VX_MF2, 0x3, false }, // 2828 |
2906 | | { PseudoVWSUB_VX_MF4_MASK, PseudoVWSUB_VX_MF4, 0x3, false }, // 2829 |
2907 | | { PseudoVWSUB_VX_MF8_MASK, PseudoVWSUB_VX_MF8, 0x3, false }, // 2830 |
2908 | | { PseudoVWSUB_WV_M1_MASK, PseudoVWSUB_WV_M1, 0x3, false }, // 2831 |
2909 | | { PseudoVWSUB_WV_M2_MASK, PseudoVWSUB_WV_M2, 0x3, false }, // 2832 |
2910 | | { PseudoVWSUB_WV_M4_MASK, PseudoVWSUB_WV_M4, 0x3, false }, // 2833 |
2911 | | { PseudoVWSUB_WV_MF2_MASK, PseudoVWSUB_WV_MF2, 0x3, false }, // 2834 |
2912 | | { PseudoVWSUB_WV_MF4_MASK, PseudoVWSUB_WV_MF4, 0x3, false }, // 2835 |
2913 | | { PseudoVWSUB_WV_MF8_MASK, PseudoVWSUB_WV_MF8, 0x3, false }, // 2836 |
2914 | | { PseudoVWSUB_WX_M1_MASK, PseudoVWSUB_WX_M1, 0x3, false }, // 2837 |
2915 | | { PseudoVWSUB_WX_M2_MASK, PseudoVWSUB_WX_M2, 0x3, false }, // 2838 |
2916 | | { PseudoVWSUB_WX_M4_MASK, PseudoVWSUB_WX_M4, 0x3, false }, // 2839 |
2917 | | { PseudoVWSUB_WX_MF2_MASK, PseudoVWSUB_WX_MF2, 0x3, false }, // 2840 |
2918 | | { PseudoVWSUB_WX_MF4_MASK, PseudoVWSUB_WX_MF4, 0x3, false }, // 2841 |
2919 | | { PseudoVWSUB_WX_MF8_MASK, PseudoVWSUB_WX_MF8, 0x3, false }, // 2842 |
2920 | | { PseudoVXOR_VI_M1_MASK, PseudoVXOR_VI_M1, 0x3, false }, // 2843 |
2921 | | { PseudoVXOR_VI_M2_MASK, PseudoVXOR_VI_M2, 0x3, false }, // 2844 |
2922 | | { PseudoVXOR_VI_M4_MASK, PseudoVXOR_VI_M4, 0x3, false }, // 2845 |
2923 | | { PseudoVXOR_VI_M8_MASK, PseudoVXOR_VI_M8, 0x3, false }, // 2846 |
2924 | | { PseudoVXOR_VI_MF2_MASK, PseudoVXOR_VI_MF2, 0x3, false }, // 2847 |
2925 | | { PseudoVXOR_VI_MF4_MASK, PseudoVXOR_VI_MF4, 0x3, false }, // 2848 |
2926 | | { PseudoVXOR_VI_MF8_MASK, PseudoVXOR_VI_MF8, 0x3, false }, // 2849 |
2927 | | { PseudoVXOR_VV_M1_MASK, PseudoVXOR_VV_M1, 0x3, false }, // 2850 |
2928 | | { PseudoVXOR_VV_M2_MASK, PseudoVXOR_VV_M2, 0x3, false }, // 2851 |
2929 | | { PseudoVXOR_VV_M4_MASK, PseudoVXOR_VV_M4, 0x3, false }, // 2852 |
2930 | | { PseudoVXOR_VV_M8_MASK, PseudoVXOR_VV_M8, 0x3, false }, // 2853 |
2931 | | { PseudoVXOR_VV_MF2_MASK, PseudoVXOR_VV_MF2, 0x3, false }, // 2854 |
2932 | | { PseudoVXOR_VV_MF4_MASK, PseudoVXOR_VV_MF4, 0x3, false }, // 2855 |
2933 | | { PseudoVXOR_VV_MF8_MASK, PseudoVXOR_VV_MF8, 0x3, false }, // 2856 |
2934 | | { PseudoVXOR_VX_M1_MASK, PseudoVXOR_VX_M1, 0x3, false }, // 2857 |
2935 | | { PseudoVXOR_VX_M2_MASK, PseudoVXOR_VX_M2, 0x3, false }, // 2858 |
2936 | | { PseudoVXOR_VX_M4_MASK, PseudoVXOR_VX_M4, 0x3, false }, // 2859 |
2937 | | { PseudoVXOR_VX_M8_MASK, PseudoVXOR_VX_M8, 0x3, false }, // 2860 |
2938 | | { PseudoVXOR_VX_MF2_MASK, PseudoVXOR_VX_MF2, 0x3, false }, // 2861 |
2939 | | { PseudoVXOR_VX_MF4_MASK, PseudoVXOR_VX_MF4, 0x3, false }, // 2862 |
2940 | | { PseudoVXOR_VX_MF8_MASK, PseudoVXOR_VX_MF8, 0x3, false }, // 2863 |
2941 | | { PseudoVZEXT_VF2_M1_MASK, PseudoVZEXT_VF2_M1, 0x2, false }, // 2864 |
2942 | | { PseudoVZEXT_VF2_M2_MASK, PseudoVZEXT_VF2_M2, 0x2, false }, // 2865 |
2943 | | { PseudoVZEXT_VF2_M4_MASK, PseudoVZEXT_VF2_M4, 0x2, false }, // 2866 |
2944 | | { PseudoVZEXT_VF2_M8_MASK, PseudoVZEXT_VF2_M8, 0x2, false }, // 2867 |
2945 | | { PseudoVZEXT_VF2_MF2_MASK, PseudoVZEXT_VF2_MF2, 0x2, false }, // 2868 |
2946 | | { PseudoVZEXT_VF2_MF4_MASK, PseudoVZEXT_VF2_MF4, 0x2, false }, // 2869 |
2947 | | { PseudoVZEXT_VF4_M1_MASK, PseudoVZEXT_VF4_M1, 0x2, false }, // 2870 |
2948 | | { PseudoVZEXT_VF4_M2_MASK, PseudoVZEXT_VF4_M2, 0x2, false }, // 2871 |
2949 | | { PseudoVZEXT_VF4_M4_MASK, PseudoVZEXT_VF4_M4, 0x2, false }, // 2872 |
2950 | | { PseudoVZEXT_VF4_M8_MASK, PseudoVZEXT_VF4_M8, 0x2, false }, // 2873 |
2951 | | { PseudoVZEXT_VF4_MF2_MASK, PseudoVZEXT_VF4_MF2, 0x2, false }, // 2874 |
2952 | | { PseudoVZEXT_VF8_M1_MASK, PseudoVZEXT_VF8_M1, 0x2, false }, // 2875 |
2953 | | { PseudoVZEXT_VF8_M2_MASK, PseudoVZEXT_VF8_M2, 0x2, false }, // 2876 |
2954 | | { PseudoVZEXT_VF8_M4_MASK, PseudoVZEXT_VF8_M4, 0x2, false }, // 2877 |
2955 | | { PseudoVZEXT_VF8_M8_MASK, PseudoVZEXT_VF8_M8, 0x2, false }, // 2878 |
2956 | | }; |
2957 | | |
2958 | | const RISCV_RISCVMaskedPseudoInfo *RISCV_getMaskedPseudoInfo(unsigned MaskedPseudo) { |
2959 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), MaskedPseudo); |
2960 | | if (i == -1) |
2961 | | return NULL; |
2962 | | else |
2963 | | return &RISCVMaskedPseudosTable[Index[i].index]; |
2964 | | } |
2965 | | |
2966 | | const RISCV_RISCVMaskedPseudoInfo *RISCV_lookupMaskedIntrinsicByUnmasked(unsigned UnmaskedPseudo) { |
2967 | | static const struct IndexType Index[] = { |
2968 | | { PseudoTHVdotVMAQASU_VV_M1, 0 }, |
2969 | | { PseudoTHVdotVMAQASU_VV_M2, 1 }, |
2970 | | { PseudoTHVdotVMAQASU_VV_M4, 2 }, |
2971 | | { PseudoTHVdotVMAQASU_VV_M8, 3 }, |
2972 | | { PseudoTHVdotVMAQASU_VV_MF2, 4 }, |
2973 | | { PseudoTHVdotVMAQASU_VX_M1, 5 }, |
2974 | | { PseudoTHVdotVMAQASU_VX_M2, 6 }, |
2975 | | { PseudoTHVdotVMAQASU_VX_M4, 7 }, |
2976 | | { PseudoTHVdotVMAQASU_VX_M8, 8 }, |
2977 | | { PseudoTHVdotVMAQASU_VX_MF2, 9 }, |
2978 | | { PseudoTHVdotVMAQAUS_VX_M1, 10 }, |
2979 | | { PseudoTHVdotVMAQAUS_VX_M2, 11 }, |
2980 | | { PseudoTHVdotVMAQAUS_VX_M4, 12 }, |
2981 | | { PseudoTHVdotVMAQAUS_VX_M8, 13 }, |
2982 | | { PseudoTHVdotVMAQAUS_VX_MF2, 14 }, |
2983 | | { PseudoTHVdotVMAQAU_VV_M1, 15 }, |
2984 | | { PseudoTHVdotVMAQAU_VV_M2, 16 }, |
2985 | | { PseudoTHVdotVMAQAU_VV_M4, 17 }, |
2986 | | { PseudoTHVdotVMAQAU_VV_M8, 18 }, |
2987 | | { PseudoTHVdotVMAQAU_VV_MF2, 19 }, |
2988 | | { PseudoTHVdotVMAQAU_VX_M1, 20 }, |
2989 | | { PseudoTHVdotVMAQAU_VX_M2, 21 }, |
2990 | | { PseudoTHVdotVMAQAU_VX_M4, 22 }, |
2991 | | { PseudoTHVdotVMAQAU_VX_M8, 23 }, |
2992 | | { PseudoTHVdotVMAQAU_VX_MF2, 24 }, |
2993 | | { PseudoTHVdotVMAQA_VV_M1, 25 }, |
2994 | | { PseudoTHVdotVMAQA_VV_M2, 26 }, |
2995 | | { PseudoTHVdotVMAQA_VV_M4, 27 }, |
2996 | | { PseudoTHVdotVMAQA_VV_M8, 28 }, |
2997 | | { PseudoTHVdotVMAQA_VV_MF2, 29 }, |
2998 | | { PseudoTHVdotVMAQA_VX_M1, 30 }, |
2999 | | { PseudoTHVdotVMAQA_VX_M2, 31 }, |
3000 | | { PseudoTHVdotVMAQA_VX_M4, 32 }, |
3001 | | { PseudoTHVdotVMAQA_VX_M8, 33 }, |
3002 | | { PseudoTHVdotVMAQA_VX_MF2, 34 }, |
3003 | | { PseudoVAADDU_VV_M1, 35 }, |
3004 | | { PseudoVAADDU_VV_M2, 36 }, |
3005 | | { PseudoVAADDU_VV_M4, 37 }, |
3006 | | { PseudoVAADDU_VV_M8, 38 }, |
3007 | | { PseudoVAADDU_VV_MF2, 39 }, |
3008 | | { PseudoVAADDU_VV_MF4, 40 }, |
3009 | | { PseudoVAADDU_VV_MF8, 41 }, |
3010 | | { PseudoVAADDU_VX_M1, 42 }, |
3011 | | { PseudoVAADDU_VX_M2, 43 }, |
3012 | | { PseudoVAADDU_VX_M4, 44 }, |
3013 | | { PseudoVAADDU_VX_M8, 45 }, |
3014 | | { PseudoVAADDU_VX_MF2, 46 }, |
3015 | | { PseudoVAADDU_VX_MF4, 47 }, |
3016 | | { PseudoVAADDU_VX_MF8, 48 }, |
3017 | | { PseudoVAADD_VV_M1, 49 }, |
3018 | | { PseudoVAADD_VV_M2, 50 }, |
3019 | | { PseudoVAADD_VV_M4, 51 }, |
3020 | | { PseudoVAADD_VV_M8, 52 }, |
3021 | | { PseudoVAADD_VV_MF2, 53 }, |
3022 | | { PseudoVAADD_VV_MF4, 54 }, |
3023 | | { PseudoVAADD_VV_MF8, 55 }, |
3024 | | { PseudoVAADD_VX_M1, 56 }, |
3025 | | { PseudoVAADD_VX_M2, 57 }, |
3026 | | { PseudoVAADD_VX_M4, 58 }, |
3027 | | { PseudoVAADD_VX_M8, 59 }, |
3028 | | { PseudoVAADD_VX_MF2, 60 }, |
3029 | | { PseudoVAADD_VX_MF4, 61 }, |
3030 | | { PseudoVAADD_VX_MF8, 62 }, |
3031 | | { PseudoVADD_VI_M1, 63 }, |
3032 | | { PseudoVADD_VI_M2, 64 }, |
3033 | | { PseudoVADD_VI_M4, 65 }, |
3034 | | { PseudoVADD_VI_M8, 66 }, |
3035 | | { PseudoVADD_VI_MF2, 67 }, |
3036 | | { PseudoVADD_VI_MF4, 68 }, |
3037 | | { PseudoVADD_VI_MF8, 69 }, |
3038 | | { PseudoVADD_VV_M1, 70 }, |
3039 | | { PseudoVADD_VV_M2, 71 }, |
3040 | | { PseudoVADD_VV_M4, 72 }, |
3041 | | { PseudoVADD_VV_M8, 73 }, |
3042 | | { PseudoVADD_VV_MF2, 74 }, |
3043 | | { PseudoVADD_VV_MF4, 75 }, |
3044 | | { PseudoVADD_VV_MF8, 76 }, |
3045 | | { PseudoVADD_VX_M1, 77 }, |
3046 | | { PseudoVADD_VX_M2, 78 }, |
3047 | | { PseudoVADD_VX_M4, 79 }, |
3048 | | { PseudoVADD_VX_M8, 80 }, |
3049 | | { PseudoVADD_VX_MF2, 81 }, |
3050 | | { PseudoVADD_VX_MF4, 82 }, |
3051 | | { PseudoVADD_VX_MF8, 83 }, |
3052 | | { PseudoVANDN_VV_M1, 84 }, |
3053 | | { PseudoVANDN_VV_M2, 85 }, |
3054 | | { PseudoVANDN_VV_M4, 86 }, |
3055 | | { PseudoVANDN_VV_M8, 87 }, |
3056 | | { PseudoVANDN_VV_MF2, 88 }, |
3057 | | { PseudoVANDN_VV_MF4, 89 }, |
3058 | | { PseudoVANDN_VV_MF8, 90 }, |
3059 | | { PseudoVANDN_VX_M1, 91 }, |
3060 | | { PseudoVANDN_VX_M2, 92 }, |
3061 | | { PseudoVANDN_VX_M4, 93 }, |
3062 | | { PseudoVANDN_VX_M8, 94 }, |
3063 | | { PseudoVANDN_VX_MF2, 95 }, |
3064 | | { PseudoVANDN_VX_MF4, 96 }, |
3065 | | { PseudoVANDN_VX_MF8, 97 }, |
3066 | | { PseudoVAND_VI_M1, 98 }, |
3067 | | { PseudoVAND_VI_M2, 99 }, |
3068 | | { PseudoVAND_VI_M4, 100 }, |
3069 | | { PseudoVAND_VI_M8, 101 }, |
3070 | | { PseudoVAND_VI_MF2, 102 }, |
3071 | | { PseudoVAND_VI_MF4, 103 }, |
3072 | | { PseudoVAND_VI_MF8, 104 }, |
3073 | | { PseudoVAND_VV_M1, 105 }, |
3074 | | { PseudoVAND_VV_M2, 106 }, |
3075 | | { PseudoVAND_VV_M4, 107 }, |
3076 | | { PseudoVAND_VV_M8, 108 }, |
3077 | | { PseudoVAND_VV_MF2, 109 }, |
3078 | | { PseudoVAND_VV_MF4, 110 }, |
3079 | | { PseudoVAND_VV_MF8, 111 }, |
3080 | | { PseudoVAND_VX_M1, 112 }, |
3081 | | { PseudoVAND_VX_M2, 113 }, |
3082 | | { PseudoVAND_VX_M4, 114 }, |
3083 | | { PseudoVAND_VX_M8, 115 }, |
3084 | | { PseudoVAND_VX_MF2, 116 }, |
3085 | | { PseudoVAND_VX_MF4, 117 }, |
3086 | | { PseudoVAND_VX_MF8, 118 }, |
3087 | | { PseudoVASUBU_VV_M1, 119 }, |
3088 | | { PseudoVASUBU_VV_M2, 120 }, |
3089 | | { PseudoVASUBU_VV_M4, 121 }, |
3090 | | { PseudoVASUBU_VV_M8, 122 }, |
3091 | | { PseudoVASUBU_VV_MF2, 123 }, |
3092 | | { PseudoVASUBU_VV_MF4, 124 }, |
3093 | | { PseudoVASUBU_VV_MF8, 125 }, |
3094 | | { PseudoVASUBU_VX_M1, 126 }, |
3095 | | { PseudoVASUBU_VX_M2, 127 }, |
3096 | | { PseudoVASUBU_VX_M4, 128 }, |
3097 | | { PseudoVASUBU_VX_M8, 129 }, |
3098 | | { PseudoVASUBU_VX_MF2, 130 }, |
3099 | | { PseudoVASUBU_VX_MF4, 131 }, |
3100 | | { PseudoVASUBU_VX_MF8, 132 }, |
3101 | | { PseudoVASUB_VV_M1, 133 }, |
3102 | | { PseudoVASUB_VV_M2, 134 }, |
3103 | | { PseudoVASUB_VV_M4, 135 }, |
3104 | | { PseudoVASUB_VV_M8, 136 }, |
3105 | | { PseudoVASUB_VV_MF2, 137 }, |
3106 | | { PseudoVASUB_VV_MF4, 138 }, |
3107 | | { PseudoVASUB_VV_MF8, 139 }, |
3108 | | { PseudoVASUB_VX_M1, 140 }, |
3109 | | { PseudoVASUB_VX_M2, 141 }, |
3110 | | { PseudoVASUB_VX_M4, 142 }, |
3111 | | { PseudoVASUB_VX_M8, 143 }, |
3112 | | { PseudoVASUB_VX_MF2, 144 }, |
3113 | | { PseudoVASUB_VX_MF4, 145 }, |
3114 | | { PseudoVASUB_VX_MF8, 146 }, |
3115 | | { PseudoVBREV8_V_M1, 147 }, |
3116 | | { PseudoVBREV8_V_M2, 148 }, |
3117 | | { PseudoVBREV8_V_M4, 149 }, |
3118 | | { PseudoVBREV8_V_M8, 150 }, |
3119 | | { PseudoVBREV8_V_MF2, 151 }, |
3120 | | { PseudoVBREV8_V_MF4, 152 }, |
3121 | | { PseudoVBREV8_V_MF8, 153 }, |
3122 | | { PseudoVBREV_V_M1, 154 }, |
3123 | | { PseudoVBREV_V_M2, 155 }, |
3124 | | { PseudoVBREV_V_M4, 156 }, |
3125 | | { PseudoVBREV_V_M8, 157 }, |
3126 | | { PseudoVBREV_V_MF2, 158 }, |
3127 | | { PseudoVBREV_V_MF4, 159 }, |
3128 | | { PseudoVBREV_V_MF8, 160 }, |
3129 | | { PseudoVCLMULH_VV_M1, 161 }, |
3130 | | { PseudoVCLMULH_VV_M2, 162 }, |
3131 | | { PseudoVCLMULH_VV_M4, 163 }, |
3132 | | { PseudoVCLMULH_VV_M8, 164 }, |
3133 | | { PseudoVCLMULH_VV_MF2, 165 }, |
3134 | | { PseudoVCLMULH_VV_MF4, 166 }, |
3135 | | { PseudoVCLMULH_VV_MF8, 167 }, |
3136 | | { PseudoVCLMULH_VX_M1, 168 }, |
3137 | | { PseudoVCLMULH_VX_M2, 169 }, |
3138 | | { PseudoVCLMULH_VX_M4, 170 }, |
3139 | | { PseudoVCLMULH_VX_M8, 171 }, |
3140 | | { PseudoVCLMULH_VX_MF2, 172 }, |
3141 | | { PseudoVCLMULH_VX_MF4, 173 }, |
3142 | | { PseudoVCLMULH_VX_MF8, 174 }, |
3143 | | { PseudoVCLMUL_VV_M1, 175 }, |
3144 | | { PseudoVCLMUL_VV_M2, 176 }, |
3145 | | { PseudoVCLMUL_VV_M4, 177 }, |
3146 | | { PseudoVCLMUL_VV_M8, 178 }, |
3147 | | { PseudoVCLMUL_VV_MF2, 179 }, |
3148 | | { PseudoVCLMUL_VV_MF4, 180 }, |
3149 | | { PseudoVCLMUL_VV_MF8, 181 }, |
3150 | | { PseudoVCLMUL_VX_M1, 182 }, |
3151 | | { PseudoVCLMUL_VX_M2, 183 }, |
3152 | | { PseudoVCLMUL_VX_M4, 184 }, |
3153 | | { PseudoVCLMUL_VX_M8, 185 }, |
3154 | | { PseudoVCLMUL_VX_MF2, 186 }, |
3155 | | { PseudoVCLMUL_VX_MF4, 187 }, |
3156 | | { PseudoVCLMUL_VX_MF8, 188 }, |
3157 | | { PseudoVCLZ_V_M1, 189 }, |
3158 | | { PseudoVCLZ_V_M2, 190 }, |
3159 | | { PseudoVCLZ_V_M4, 191 }, |
3160 | | { PseudoVCLZ_V_M8, 192 }, |
3161 | | { PseudoVCLZ_V_MF2, 193 }, |
3162 | | { PseudoVCLZ_V_MF4, 194 }, |
3163 | | { PseudoVCLZ_V_MF8, 195 }, |
3164 | | { PseudoVCPOP_V_M1, 196 }, |
3165 | | { PseudoVCPOP_V_M2, 197 }, |
3166 | | { PseudoVCPOP_V_M4, 198 }, |
3167 | | { PseudoVCPOP_V_M8, 199 }, |
3168 | | { PseudoVCPOP_V_MF2, 200 }, |
3169 | | { PseudoVCPOP_V_MF4, 201 }, |
3170 | | { PseudoVCPOP_V_MF8, 202 }, |
3171 | | { PseudoVCTZ_V_M1, 203 }, |
3172 | | { PseudoVCTZ_V_M2, 204 }, |
3173 | | { PseudoVCTZ_V_M4, 205 }, |
3174 | | { PseudoVCTZ_V_M8, 206 }, |
3175 | | { PseudoVCTZ_V_MF2, 207 }, |
3176 | | { PseudoVCTZ_V_MF4, 208 }, |
3177 | | { PseudoVCTZ_V_MF8, 209 }, |
3178 | | { PseudoVDIVU_VV_M1_E16, 210 }, |
3179 | | { PseudoVDIVU_VV_M1_E32, 211 }, |
3180 | | { PseudoVDIVU_VV_M1_E64, 212 }, |
3181 | | { PseudoVDIVU_VV_M1_E8, 213 }, |
3182 | | { PseudoVDIVU_VV_M2_E16, 214 }, |
3183 | | { PseudoVDIVU_VV_M2_E32, 215 }, |
3184 | | { PseudoVDIVU_VV_M2_E64, 216 }, |
3185 | | { PseudoVDIVU_VV_M2_E8, 217 }, |
3186 | | { PseudoVDIVU_VV_M4_E16, 218 }, |
3187 | | { PseudoVDIVU_VV_M4_E32, 219 }, |
3188 | | { PseudoVDIVU_VV_M4_E64, 220 }, |
3189 | | { PseudoVDIVU_VV_M4_E8, 221 }, |
3190 | | { PseudoVDIVU_VV_M8_E16, 222 }, |
3191 | | { PseudoVDIVU_VV_M8_E32, 223 }, |
3192 | | { PseudoVDIVU_VV_M8_E64, 224 }, |
3193 | | { PseudoVDIVU_VV_M8_E8, 225 }, |
3194 | | { PseudoVDIVU_VV_MF2_E16, 226 }, |
3195 | | { PseudoVDIVU_VV_MF2_E32, 227 }, |
3196 | | { PseudoVDIVU_VV_MF2_E8, 228 }, |
3197 | | { PseudoVDIVU_VV_MF4_E16, 229 }, |
3198 | | { PseudoVDIVU_VV_MF4_E8, 230 }, |
3199 | | { PseudoVDIVU_VV_MF8_E8, 231 }, |
3200 | | { PseudoVDIVU_VX_M1_E16, 232 }, |
3201 | | { PseudoVDIVU_VX_M1_E32, 233 }, |
3202 | | { PseudoVDIVU_VX_M1_E64, 234 }, |
3203 | | { PseudoVDIVU_VX_M1_E8, 235 }, |
3204 | | { PseudoVDIVU_VX_M2_E16, 236 }, |
3205 | | { PseudoVDIVU_VX_M2_E32, 237 }, |
3206 | | { PseudoVDIVU_VX_M2_E64, 238 }, |
3207 | | { PseudoVDIVU_VX_M2_E8, 239 }, |
3208 | | { PseudoVDIVU_VX_M4_E16, 240 }, |
3209 | | { PseudoVDIVU_VX_M4_E32, 241 }, |
3210 | | { PseudoVDIVU_VX_M4_E64, 242 }, |
3211 | | { PseudoVDIVU_VX_M4_E8, 243 }, |
3212 | | { PseudoVDIVU_VX_M8_E16, 244 }, |
3213 | | { PseudoVDIVU_VX_M8_E32, 245 }, |
3214 | | { PseudoVDIVU_VX_M8_E64, 246 }, |
3215 | | { PseudoVDIVU_VX_M8_E8, 247 }, |
3216 | | { PseudoVDIVU_VX_MF2_E16, 248 }, |
3217 | | { PseudoVDIVU_VX_MF2_E32, 249 }, |
3218 | | { PseudoVDIVU_VX_MF2_E8, 250 }, |
3219 | | { PseudoVDIVU_VX_MF4_E16, 251 }, |
3220 | | { PseudoVDIVU_VX_MF4_E8, 252 }, |
3221 | | { PseudoVDIVU_VX_MF8_E8, 253 }, |
3222 | | { PseudoVDIV_VV_M1_E16, 254 }, |
3223 | | { PseudoVDIV_VV_M1_E32, 255 }, |
3224 | | { PseudoVDIV_VV_M1_E64, 256 }, |
3225 | | { PseudoVDIV_VV_M1_E8, 257 }, |
3226 | | { PseudoVDIV_VV_M2_E16, 258 }, |
3227 | | { PseudoVDIV_VV_M2_E32, 259 }, |
3228 | | { PseudoVDIV_VV_M2_E64, 260 }, |
3229 | | { PseudoVDIV_VV_M2_E8, 261 }, |
3230 | | { PseudoVDIV_VV_M4_E16, 262 }, |
3231 | | { PseudoVDIV_VV_M4_E32, 263 }, |
3232 | | { PseudoVDIV_VV_M4_E64, 264 }, |
3233 | | { PseudoVDIV_VV_M4_E8, 265 }, |
3234 | | { PseudoVDIV_VV_M8_E16, 266 }, |
3235 | | { PseudoVDIV_VV_M8_E32, 267 }, |
3236 | | { PseudoVDIV_VV_M8_E64, 268 }, |
3237 | | { PseudoVDIV_VV_M8_E8, 269 }, |
3238 | | { PseudoVDIV_VV_MF2_E16, 270 }, |
3239 | | { PseudoVDIV_VV_MF2_E32, 271 }, |
3240 | | { PseudoVDIV_VV_MF2_E8, 272 }, |
3241 | | { PseudoVDIV_VV_MF4_E16, 273 }, |
3242 | | { PseudoVDIV_VV_MF4_E8, 274 }, |
3243 | | { PseudoVDIV_VV_MF8_E8, 275 }, |
3244 | | { PseudoVDIV_VX_M1_E16, 276 }, |
3245 | | { PseudoVDIV_VX_M1_E32, 277 }, |
3246 | | { PseudoVDIV_VX_M1_E64, 278 }, |
3247 | | { PseudoVDIV_VX_M1_E8, 279 }, |
3248 | | { PseudoVDIV_VX_M2_E16, 280 }, |
3249 | | { PseudoVDIV_VX_M2_E32, 281 }, |
3250 | | { PseudoVDIV_VX_M2_E64, 282 }, |
3251 | | { PseudoVDIV_VX_M2_E8, 283 }, |
3252 | | { PseudoVDIV_VX_M4_E16, 284 }, |
3253 | | { PseudoVDIV_VX_M4_E32, 285 }, |
3254 | | { PseudoVDIV_VX_M4_E64, 286 }, |
3255 | | { PseudoVDIV_VX_M4_E8, 287 }, |
3256 | | { PseudoVDIV_VX_M8_E16, 288 }, |
3257 | | { PseudoVDIV_VX_M8_E32, 289 }, |
3258 | | { PseudoVDIV_VX_M8_E64, 290 }, |
3259 | | { PseudoVDIV_VX_M8_E8, 291 }, |
3260 | | { PseudoVDIV_VX_MF2_E16, 292 }, |
3261 | | { PseudoVDIV_VX_MF2_E32, 293 }, |
3262 | | { PseudoVDIV_VX_MF2_E8, 294 }, |
3263 | | { PseudoVDIV_VX_MF4_E16, 295 }, |
3264 | | { PseudoVDIV_VX_MF4_E8, 296 }, |
3265 | | { PseudoVDIV_VX_MF8_E8, 297 }, |
3266 | | { PseudoVFADD_VFPR16_M1, 298 }, |
3267 | | { PseudoVFADD_VFPR16_M2, 299 }, |
3268 | | { PseudoVFADD_VFPR16_M4, 300 }, |
3269 | | { PseudoVFADD_VFPR16_M8, 301 }, |
3270 | | { PseudoVFADD_VFPR16_MF2, 302 }, |
3271 | | { PseudoVFADD_VFPR16_MF4, 303 }, |
3272 | | { PseudoVFADD_VFPR32_M1, 304 }, |
3273 | | { PseudoVFADD_VFPR32_M2, 305 }, |
3274 | | { PseudoVFADD_VFPR32_M4, 306 }, |
3275 | | { PseudoVFADD_VFPR32_M8, 307 }, |
3276 | | { PseudoVFADD_VFPR32_MF2, 308 }, |
3277 | | { PseudoVFADD_VFPR64_M1, 309 }, |
3278 | | { PseudoVFADD_VFPR64_M2, 310 }, |
3279 | | { PseudoVFADD_VFPR64_M4, 311 }, |
3280 | | { PseudoVFADD_VFPR64_M8, 312 }, |
3281 | | { PseudoVFADD_VV_M1, 313 }, |
3282 | | { PseudoVFADD_VV_M2, 314 }, |
3283 | | { PseudoVFADD_VV_M4, 315 }, |
3284 | | { PseudoVFADD_VV_M8, 316 }, |
3285 | | { PseudoVFADD_VV_MF2, 317 }, |
3286 | | { PseudoVFADD_VV_MF4, 318 }, |
3287 | | { PseudoVFCLASS_V_M1, 319 }, |
3288 | | { PseudoVFCLASS_V_M2, 320 }, |
3289 | | { PseudoVFCLASS_V_M4, 321 }, |
3290 | | { PseudoVFCLASS_V_M8, 322 }, |
3291 | | { PseudoVFCLASS_V_MF2, 323 }, |
3292 | | { PseudoVFCLASS_V_MF4, 324 }, |
3293 | | { PseudoVFCVT_F_XU_V_M1, 325 }, |
3294 | | { PseudoVFCVT_F_XU_V_M2, 326 }, |
3295 | | { PseudoVFCVT_F_XU_V_M4, 327 }, |
3296 | | { PseudoVFCVT_F_XU_V_M8, 328 }, |
3297 | | { PseudoVFCVT_F_XU_V_MF2, 329 }, |
3298 | | { PseudoVFCVT_F_XU_V_MF4, 330 }, |
3299 | | { PseudoVFCVT_F_X_V_M1, 331 }, |
3300 | | { PseudoVFCVT_F_X_V_M2, 332 }, |
3301 | | { PseudoVFCVT_F_X_V_M4, 333 }, |
3302 | | { PseudoVFCVT_F_X_V_M8, 334 }, |
3303 | | { PseudoVFCVT_F_X_V_MF2, 335 }, |
3304 | | { PseudoVFCVT_F_X_V_MF4, 336 }, |
3305 | | { PseudoVFCVT_RM_F_XU_V_M1, 337 }, |
3306 | | { PseudoVFCVT_RM_F_XU_V_M2, 338 }, |
3307 | | { PseudoVFCVT_RM_F_XU_V_M4, 339 }, |
3308 | | { PseudoVFCVT_RM_F_XU_V_M8, 340 }, |
3309 | | { PseudoVFCVT_RM_F_XU_V_MF2, 341 }, |
3310 | | { PseudoVFCVT_RM_F_XU_V_MF4, 342 }, |
3311 | | { PseudoVFCVT_RM_F_X_V_M1, 343 }, |
3312 | | { PseudoVFCVT_RM_F_X_V_M2, 344 }, |
3313 | | { PseudoVFCVT_RM_F_X_V_M4, 345 }, |
3314 | | { PseudoVFCVT_RM_F_X_V_M8, 346 }, |
3315 | | { PseudoVFCVT_RM_F_X_V_MF2, 347 }, |
3316 | | { PseudoVFCVT_RM_F_X_V_MF4, 348 }, |
3317 | | { PseudoVFCVT_RM_XU_F_V_M1, 349 }, |
3318 | | { PseudoVFCVT_RM_XU_F_V_M2, 350 }, |
3319 | | { PseudoVFCVT_RM_XU_F_V_M4, 351 }, |
3320 | | { PseudoVFCVT_RM_XU_F_V_M8, 352 }, |
3321 | | { PseudoVFCVT_RM_XU_F_V_MF2, 353 }, |
3322 | | { PseudoVFCVT_RM_XU_F_V_MF4, 354 }, |
3323 | | { PseudoVFCVT_RM_X_F_V_M1, 355 }, |
3324 | | { PseudoVFCVT_RM_X_F_V_M2, 356 }, |
3325 | | { PseudoVFCVT_RM_X_F_V_M4, 357 }, |
3326 | | { PseudoVFCVT_RM_X_F_V_M8, 358 }, |
3327 | | { PseudoVFCVT_RM_X_F_V_MF2, 359 }, |
3328 | | { PseudoVFCVT_RM_X_F_V_MF4, 360 }, |
3329 | | { PseudoVFCVT_RTZ_XU_F_V_M1, 361 }, |
3330 | | { PseudoVFCVT_RTZ_XU_F_V_M2, 362 }, |
3331 | | { PseudoVFCVT_RTZ_XU_F_V_M4, 363 }, |
3332 | | { PseudoVFCVT_RTZ_XU_F_V_M8, 364 }, |
3333 | | { PseudoVFCVT_RTZ_XU_F_V_MF2, 365 }, |
3334 | | { PseudoVFCVT_RTZ_XU_F_V_MF4, 366 }, |
3335 | | { PseudoVFCVT_RTZ_X_F_V_M1, 367 }, |
3336 | | { PseudoVFCVT_RTZ_X_F_V_M2, 368 }, |
3337 | | { PseudoVFCVT_RTZ_X_F_V_M4, 369 }, |
3338 | | { PseudoVFCVT_RTZ_X_F_V_M8, 370 }, |
3339 | | { PseudoVFCVT_RTZ_X_F_V_MF2, 371 }, |
3340 | | { PseudoVFCVT_RTZ_X_F_V_MF4, 372 }, |
3341 | | { PseudoVFCVT_XU_F_V_M1, 373 }, |
3342 | | { PseudoVFCVT_XU_F_V_M2, 374 }, |
3343 | | { PseudoVFCVT_XU_F_V_M4, 375 }, |
3344 | | { PseudoVFCVT_XU_F_V_M8, 376 }, |
3345 | | { PseudoVFCVT_XU_F_V_MF2, 377 }, |
3346 | | { PseudoVFCVT_XU_F_V_MF4, 378 }, |
3347 | | { PseudoVFCVT_X_F_V_M1, 379 }, |
3348 | | { PseudoVFCVT_X_F_V_M2, 380 }, |
3349 | | { PseudoVFCVT_X_F_V_M4, 381 }, |
3350 | | { PseudoVFCVT_X_F_V_M8, 382 }, |
3351 | | { PseudoVFCVT_X_F_V_MF2, 383 }, |
3352 | | { PseudoVFCVT_X_F_V_MF4, 384 }, |
3353 | | { PseudoVFDIV_VFPR16_M1_E16, 385 }, |
3354 | | { PseudoVFDIV_VFPR16_M2_E16, 386 }, |
3355 | | { PseudoVFDIV_VFPR16_M4_E16, 387 }, |
3356 | | { PseudoVFDIV_VFPR16_M8_E16, 388 }, |
3357 | | { PseudoVFDIV_VFPR16_MF2_E16, 389 }, |
3358 | | { PseudoVFDIV_VFPR16_MF4_E16, 390 }, |
3359 | | { PseudoVFDIV_VFPR32_M1_E32, 391 }, |
3360 | | { PseudoVFDIV_VFPR32_M2_E32, 392 }, |
3361 | | { PseudoVFDIV_VFPR32_M4_E32, 393 }, |
3362 | | { PseudoVFDIV_VFPR32_M8_E32, 394 }, |
3363 | | { PseudoVFDIV_VFPR32_MF2_E32, 395 }, |
3364 | | { PseudoVFDIV_VFPR64_M1_E64, 396 }, |
3365 | | { PseudoVFDIV_VFPR64_M2_E64, 397 }, |
3366 | | { PseudoVFDIV_VFPR64_M4_E64, 398 }, |
3367 | | { PseudoVFDIV_VFPR64_M8_E64, 399 }, |
3368 | | { PseudoVFDIV_VV_M1_E16, 400 }, |
3369 | | { PseudoVFDIV_VV_M1_E32, 401 }, |
3370 | | { PseudoVFDIV_VV_M1_E64, 402 }, |
3371 | | { PseudoVFDIV_VV_M2_E16, 403 }, |
3372 | | { PseudoVFDIV_VV_M2_E32, 404 }, |
3373 | | { PseudoVFDIV_VV_M2_E64, 405 }, |
3374 | | { PseudoVFDIV_VV_M4_E16, 406 }, |
3375 | | { PseudoVFDIV_VV_M4_E32, 407 }, |
3376 | | { PseudoVFDIV_VV_M4_E64, 408 }, |
3377 | | { PseudoVFDIV_VV_M8_E16, 409 }, |
3378 | | { PseudoVFDIV_VV_M8_E32, 410 }, |
3379 | | { PseudoVFDIV_VV_M8_E64, 411 }, |
3380 | | { PseudoVFDIV_VV_MF2_E16, 412 }, |
3381 | | { PseudoVFDIV_VV_MF2_E32, 413 }, |
3382 | | { PseudoVFDIV_VV_MF4_E16, 414 }, |
3383 | | { PseudoVFMACC_VFPR16_M1, 415 }, |
3384 | | { PseudoVFMACC_VFPR16_M2, 416 }, |
3385 | | { PseudoVFMACC_VFPR16_M4, 417 }, |
3386 | | { PseudoVFMACC_VFPR16_M8, 418 }, |
3387 | | { PseudoVFMACC_VFPR16_MF2, 419 }, |
3388 | | { PseudoVFMACC_VFPR16_MF4, 420 }, |
3389 | | { PseudoVFMACC_VFPR32_M1, 421 }, |
3390 | | { PseudoVFMACC_VFPR32_M2, 422 }, |
3391 | | { PseudoVFMACC_VFPR32_M4, 423 }, |
3392 | | { PseudoVFMACC_VFPR32_M8, 424 }, |
3393 | | { PseudoVFMACC_VFPR32_MF2, 425 }, |
3394 | | { PseudoVFMACC_VFPR64_M1, 426 }, |
3395 | | { PseudoVFMACC_VFPR64_M2, 427 }, |
3396 | | { PseudoVFMACC_VFPR64_M4, 428 }, |
3397 | | { PseudoVFMACC_VFPR64_M8, 429 }, |
3398 | | { PseudoVFMACC_VV_M1, 430 }, |
3399 | | { PseudoVFMACC_VV_M2, 431 }, |
3400 | | { PseudoVFMACC_VV_M4, 432 }, |
3401 | | { PseudoVFMACC_VV_M8, 433 }, |
3402 | | { PseudoVFMACC_VV_MF2, 434 }, |
3403 | | { PseudoVFMACC_VV_MF4, 435 }, |
3404 | | { PseudoVFMADD_VFPR16_M1, 436 }, |
3405 | | { PseudoVFMADD_VFPR16_M2, 437 }, |
3406 | | { PseudoVFMADD_VFPR16_M4, 438 }, |
3407 | | { PseudoVFMADD_VFPR16_M8, 439 }, |
3408 | | { PseudoVFMADD_VFPR16_MF2, 440 }, |
3409 | | { PseudoVFMADD_VFPR16_MF4, 441 }, |
3410 | | { PseudoVFMADD_VFPR32_M1, 442 }, |
3411 | | { PseudoVFMADD_VFPR32_M2, 443 }, |
3412 | | { PseudoVFMADD_VFPR32_M4, 444 }, |
3413 | | { PseudoVFMADD_VFPR32_M8, 445 }, |
3414 | | { PseudoVFMADD_VFPR32_MF2, 446 }, |
3415 | | { PseudoVFMADD_VFPR64_M1, 447 }, |
3416 | | { PseudoVFMADD_VFPR64_M2, 448 }, |
3417 | | { PseudoVFMADD_VFPR64_M4, 449 }, |
3418 | | { PseudoVFMADD_VFPR64_M8, 450 }, |
3419 | | { PseudoVFMADD_VV_M1, 451 }, |
3420 | | { PseudoVFMADD_VV_M2, 452 }, |
3421 | | { PseudoVFMADD_VV_M4, 453 }, |
3422 | | { PseudoVFMADD_VV_M8, 454 }, |
3423 | | { PseudoVFMADD_VV_MF2, 455 }, |
3424 | | { PseudoVFMADD_VV_MF4, 456 }, |
3425 | | { PseudoVFMAX_VFPR16_M1, 457 }, |
3426 | | { PseudoVFMAX_VFPR16_M2, 458 }, |
3427 | | { PseudoVFMAX_VFPR16_M4, 459 }, |
3428 | | { PseudoVFMAX_VFPR16_M8, 460 }, |
3429 | | { PseudoVFMAX_VFPR16_MF2, 461 }, |
3430 | | { PseudoVFMAX_VFPR16_MF4, 462 }, |
3431 | | { PseudoVFMAX_VFPR32_M1, 463 }, |
3432 | | { PseudoVFMAX_VFPR32_M2, 464 }, |
3433 | | { PseudoVFMAX_VFPR32_M4, 465 }, |
3434 | | { PseudoVFMAX_VFPR32_M8, 466 }, |
3435 | | { PseudoVFMAX_VFPR32_MF2, 467 }, |
3436 | | { PseudoVFMAX_VFPR64_M1, 468 }, |
3437 | | { PseudoVFMAX_VFPR64_M2, 469 }, |
3438 | | { PseudoVFMAX_VFPR64_M4, 470 }, |
3439 | | { PseudoVFMAX_VFPR64_M8, 471 }, |
3440 | | { PseudoVFMAX_VV_M1, 472 }, |
3441 | | { PseudoVFMAX_VV_M2, 473 }, |
3442 | | { PseudoVFMAX_VV_M4, 474 }, |
3443 | | { PseudoVFMAX_VV_M8, 475 }, |
3444 | | { PseudoVFMAX_VV_MF2, 476 }, |
3445 | | { PseudoVFMAX_VV_MF4, 477 }, |
3446 | | { PseudoVFMIN_VFPR16_M1, 478 }, |
3447 | | { PseudoVFMIN_VFPR16_M2, 479 }, |
3448 | | { PseudoVFMIN_VFPR16_M4, 480 }, |
3449 | | { PseudoVFMIN_VFPR16_M8, 481 }, |
3450 | | { PseudoVFMIN_VFPR16_MF2, 482 }, |
3451 | | { PseudoVFMIN_VFPR16_MF4, 483 }, |
3452 | | { PseudoVFMIN_VFPR32_M1, 484 }, |
3453 | | { PseudoVFMIN_VFPR32_M2, 485 }, |
3454 | | { PseudoVFMIN_VFPR32_M4, 486 }, |
3455 | | { PseudoVFMIN_VFPR32_M8, 487 }, |
3456 | | { PseudoVFMIN_VFPR32_MF2, 488 }, |
3457 | | { PseudoVFMIN_VFPR64_M1, 489 }, |
3458 | | { PseudoVFMIN_VFPR64_M2, 490 }, |
3459 | | { PseudoVFMIN_VFPR64_M4, 491 }, |
3460 | | { PseudoVFMIN_VFPR64_M8, 492 }, |
3461 | | { PseudoVFMIN_VV_M1, 493 }, |
3462 | | { PseudoVFMIN_VV_M2, 494 }, |
3463 | | { PseudoVFMIN_VV_M4, 495 }, |
3464 | | { PseudoVFMIN_VV_M8, 496 }, |
3465 | | { PseudoVFMIN_VV_MF2, 497 }, |
3466 | | { PseudoVFMIN_VV_MF4, 498 }, |
3467 | | { PseudoVFMSAC_VFPR16_M1, 499 }, |
3468 | | { PseudoVFMSAC_VFPR16_M2, 500 }, |
3469 | | { PseudoVFMSAC_VFPR16_M4, 501 }, |
3470 | | { PseudoVFMSAC_VFPR16_M8, 502 }, |
3471 | | { PseudoVFMSAC_VFPR16_MF2, 503 }, |
3472 | | { PseudoVFMSAC_VFPR16_MF4, 504 }, |
3473 | | { PseudoVFMSAC_VFPR32_M1, 505 }, |
3474 | | { PseudoVFMSAC_VFPR32_M2, 506 }, |
3475 | | { PseudoVFMSAC_VFPR32_M4, 507 }, |
3476 | | { PseudoVFMSAC_VFPR32_M8, 508 }, |
3477 | | { PseudoVFMSAC_VFPR32_MF2, 509 }, |
3478 | | { PseudoVFMSAC_VFPR64_M1, 510 }, |
3479 | | { PseudoVFMSAC_VFPR64_M2, 511 }, |
3480 | | { PseudoVFMSAC_VFPR64_M4, 512 }, |
3481 | | { PseudoVFMSAC_VFPR64_M8, 513 }, |
3482 | | { PseudoVFMSAC_VV_M1, 514 }, |
3483 | | { PseudoVFMSAC_VV_M2, 515 }, |
3484 | | { PseudoVFMSAC_VV_M4, 516 }, |
3485 | | { PseudoVFMSAC_VV_M8, 517 }, |
3486 | | { PseudoVFMSAC_VV_MF2, 518 }, |
3487 | | { PseudoVFMSAC_VV_MF4, 519 }, |
3488 | | { PseudoVFMSUB_VFPR16_M1, 520 }, |
3489 | | { PseudoVFMSUB_VFPR16_M2, 521 }, |
3490 | | { PseudoVFMSUB_VFPR16_M4, 522 }, |
3491 | | { PseudoVFMSUB_VFPR16_M8, 523 }, |
3492 | | { PseudoVFMSUB_VFPR16_MF2, 524 }, |
3493 | | { PseudoVFMSUB_VFPR16_MF4, 525 }, |
3494 | | { PseudoVFMSUB_VFPR32_M1, 526 }, |
3495 | | { PseudoVFMSUB_VFPR32_M2, 527 }, |
3496 | | { PseudoVFMSUB_VFPR32_M4, 528 }, |
3497 | | { PseudoVFMSUB_VFPR32_M8, 529 }, |
3498 | | { PseudoVFMSUB_VFPR32_MF2, 530 }, |
3499 | | { PseudoVFMSUB_VFPR64_M1, 531 }, |
3500 | | { PseudoVFMSUB_VFPR64_M2, 532 }, |
3501 | | { PseudoVFMSUB_VFPR64_M4, 533 }, |
3502 | | { PseudoVFMSUB_VFPR64_M8, 534 }, |
3503 | | { PseudoVFMSUB_VV_M1, 535 }, |
3504 | | { PseudoVFMSUB_VV_M2, 536 }, |
3505 | | { PseudoVFMSUB_VV_M4, 537 }, |
3506 | | { PseudoVFMSUB_VV_M8, 538 }, |
3507 | | { PseudoVFMSUB_VV_MF2, 539 }, |
3508 | | { PseudoVFMSUB_VV_MF4, 540 }, |
3509 | | { PseudoVFMUL_VFPR16_M1, 541 }, |
3510 | | { PseudoVFMUL_VFPR16_M2, 542 }, |
3511 | | { PseudoVFMUL_VFPR16_M4, 543 }, |
3512 | | { PseudoVFMUL_VFPR16_M8, 544 }, |
3513 | | { PseudoVFMUL_VFPR16_MF2, 545 }, |
3514 | | { PseudoVFMUL_VFPR16_MF4, 546 }, |
3515 | | { PseudoVFMUL_VFPR32_M1, 547 }, |
3516 | | { PseudoVFMUL_VFPR32_M2, 548 }, |
3517 | | { PseudoVFMUL_VFPR32_M4, 549 }, |
3518 | | { PseudoVFMUL_VFPR32_M8, 550 }, |
3519 | | { PseudoVFMUL_VFPR32_MF2, 551 }, |
3520 | | { PseudoVFMUL_VFPR64_M1, 552 }, |
3521 | | { PseudoVFMUL_VFPR64_M2, 553 }, |
3522 | | { PseudoVFMUL_VFPR64_M4, 554 }, |
3523 | | { PseudoVFMUL_VFPR64_M8, 555 }, |
3524 | | { PseudoVFMUL_VV_M1, 556 }, |
3525 | | { PseudoVFMUL_VV_M2, 557 }, |
3526 | | { PseudoVFMUL_VV_M4, 558 }, |
3527 | | { PseudoVFMUL_VV_M8, 559 }, |
3528 | | { PseudoVFMUL_VV_MF2, 560 }, |
3529 | | { PseudoVFMUL_VV_MF4, 561 }, |
3530 | | { PseudoVFNCVTBF16_F_F_W_M1, 562 }, |
3531 | | { PseudoVFNCVTBF16_F_F_W_M2, 563 }, |
3532 | | { PseudoVFNCVTBF16_F_F_W_M4, 564 }, |
3533 | | { PseudoVFNCVTBF16_F_F_W_MF2, 565 }, |
3534 | | { PseudoVFNCVTBF16_F_F_W_MF4, 566 }, |
3535 | | { PseudoVFNCVT_F_F_W_M1, 567 }, |
3536 | | { PseudoVFNCVT_F_F_W_M2, 568 }, |
3537 | | { PseudoVFNCVT_F_F_W_M4, 569 }, |
3538 | | { PseudoVFNCVT_F_F_W_MF2, 570 }, |
3539 | | { PseudoVFNCVT_F_F_W_MF4, 571 }, |
3540 | | { PseudoVFNCVT_F_XU_W_M1, 572 }, |
3541 | | { PseudoVFNCVT_F_XU_W_M2, 573 }, |
3542 | | { PseudoVFNCVT_F_XU_W_M4, 574 }, |
3543 | | { PseudoVFNCVT_F_XU_W_MF2, 575 }, |
3544 | | { PseudoVFNCVT_F_XU_W_MF4, 576 }, |
3545 | | { PseudoVFNCVT_F_X_W_M1, 577 }, |
3546 | | { PseudoVFNCVT_F_X_W_M2, 578 }, |
3547 | | { PseudoVFNCVT_F_X_W_M4, 579 }, |
3548 | | { PseudoVFNCVT_F_X_W_MF2, 580 }, |
3549 | | { PseudoVFNCVT_F_X_W_MF4, 581 }, |
3550 | | { PseudoVFNCVT_RM_F_XU_W_M1, 582 }, |
3551 | | { PseudoVFNCVT_RM_F_XU_W_M2, 583 }, |
3552 | | { PseudoVFNCVT_RM_F_XU_W_M4, 584 }, |
3553 | | { PseudoVFNCVT_RM_F_XU_W_MF2, 585 }, |
3554 | | { PseudoVFNCVT_RM_F_XU_W_MF4, 586 }, |
3555 | | { PseudoVFNCVT_RM_F_X_W_M1, 587 }, |
3556 | | { PseudoVFNCVT_RM_F_X_W_M2, 588 }, |
3557 | | { PseudoVFNCVT_RM_F_X_W_M4, 589 }, |
3558 | | { PseudoVFNCVT_RM_F_X_W_MF2, 590 }, |
3559 | | { PseudoVFNCVT_RM_F_X_W_MF4, 591 }, |
3560 | | { PseudoVFNCVT_RM_XU_F_W_M1, 592 }, |
3561 | | { PseudoVFNCVT_RM_XU_F_W_M2, 593 }, |
3562 | | { PseudoVFNCVT_RM_XU_F_W_M4, 594 }, |
3563 | | { PseudoVFNCVT_RM_XU_F_W_MF2, 595 }, |
3564 | | { PseudoVFNCVT_RM_XU_F_W_MF4, 596 }, |
3565 | | { PseudoVFNCVT_RM_XU_F_W_MF8, 597 }, |
3566 | | { PseudoVFNCVT_RM_X_F_W_M1, 598 }, |
3567 | | { PseudoVFNCVT_RM_X_F_W_M2, 599 }, |
3568 | | { PseudoVFNCVT_RM_X_F_W_M4, 600 }, |
3569 | | { PseudoVFNCVT_RM_X_F_W_MF2, 601 }, |
3570 | | { PseudoVFNCVT_RM_X_F_W_MF4, 602 }, |
3571 | | { PseudoVFNCVT_RM_X_F_W_MF8, 603 }, |
3572 | | { PseudoVFNCVT_ROD_F_F_W_M1, 604 }, |
3573 | | { PseudoVFNCVT_ROD_F_F_W_M2, 605 }, |
3574 | | { PseudoVFNCVT_ROD_F_F_W_M4, 606 }, |
3575 | | { PseudoVFNCVT_ROD_F_F_W_MF2, 607 }, |
3576 | | { PseudoVFNCVT_ROD_F_F_W_MF4, 608 }, |
3577 | | { PseudoVFNCVT_RTZ_XU_F_W_M1, 609 }, |
3578 | | { PseudoVFNCVT_RTZ_XU_F_W_M2, 610 }, |
3579 | | { PseudoVFNCVT_RTZ_XU_F_W_M4, 611 }, |
3580 | | { PseudoVFNCVT_RTZ_XU_F_W_MF2, 612 }, |
3581 | | { PseudoVFNCVT_RTZ_XU_F_W_MF4, 613 }, |
3582 | | { PseudoVFNCVT_RTZ_XU_F_W_MF8, 614 }, |
3583 | | { PseudoVFNCVT_RTZ_X_F_W_M1, 615 }, |
3584 | | { PseudoVFNCVT_RTZ_X_F_W_M2, 616 }, |
3585 | | { PseudoVFNCVT_RTZ_X_F_W_M4, 617 }, |
3586 | | { PseudoVFNCVT_RTZ_X_F_W_MF2, 618 }, |
3587 | | { PseudoVFNCVT_RTZ_X_F_W_MF4, 619 }, |
3588 | | { PseudoVFNCVT_RTZ_X_F_W_MF8, 620 }, |
3589 | | { PseudoVFNCVT_XU_F_W_M1, 621 }, |
3590 | | { PseudoVFNCVT_XU_F_W_M2, 622 }, |
3591 | | { PseudoVFNCVT_XU_F_W_M4, 623 }, |
3592 | | { PseudoVFNCVT_XU_F_W_MF2, 624 }, |
3593 | | { PseudoVFNCVT_XU_F_W_MF4, 625 }, |
3594 | | { PseudoVFNCVT_XU_F_W_MF8, 626 }, |
3595 | | { PseudoVFNCVT_X_F_W_M1, 627 }, |
3596 | | { PseudoVFNCVT_X_F_W_M2, 628 }, |
3597 | | { PseudoVFNCVT_X_F_W_M4, 629 }, |
3598 | | { PseudoVFNCVT_X_F_W_MF2, 630 }, |
3599 | | { PseudoVFNCVT_X_F_W_MF4, 631 }, |
3600 | | { PseudoVFNCVT_X_F_W_MF8, 632 }, |
3601 | | { PseudoVFNMACC_VFPR16_M1, 633 }, |
3602 | | { PseudoVFNMACC_VFPR16_M2, 634 }, |
3603 | | { PseudoVFNMACC_VFPR16_M4, 635 }, |
3604 | | { PseudoVFNMACC_VFPR16_M8, 636 }, |
3605 | | { PseudoVFNMACC_VFPR16_MF2, 637 }, |
3606 | | { PseudoVFNMACC_VFPR16_MF4, 638 }, |
3607 | | { PseudoVFNMACC_VFPR32_M1, 639 }, |
3608 | | { PseudoVFNMACC_VFPR32_M2, 640 }, |
3609 | | { PseudoVFNMACC_VFPR32_M4, 641 }, |
3610 | | { PseudoVFNMACC_VFPR32_M8, 642 }, |
3611 | | { PseudoVFNMACC_VFPR32_MF2, 643 }, |
3612 | | { PseudoVFNMACC_VFPR64_M1, 644 }, |
3613 | | { PseudoVFNMACC_VFPR64_M2, 645 }, |
3614 | | { PseudoVFNMACC_VFPR64_M4, 646 }, |
3615 | | { PseudoVFNMACC_VFPR64_M8, 647 }, |
3616 | | { PseudoVFNMACC_VV_M1, 648 }, |
3617 | | { PseudoVFNMACC_VV_M2, 649 }, |
3618 | | { PseudoVFNMACC_VV_M4, 650 }, |
3619 | | { PseudoVFNMACC_VV_M8, 651 }, |
3620 | | { PseudoVFNMACC_VV_MF2, 652 }, |
3621 | | { PseudoVFNMACC_VV_MF4, 653 }, |
3622 | | { PseudoVFNMADD_VFPR16_M1, 654 }, |
3623 | | { PseudoVFNMADD_VFPR16_M2, 655 }, |
3624 | | { PseudoVFNMADD_VFPR16_M4, 656 }, |
3625 | | { PseudoVFNMADD_VFPR16_M8, 657 }, |
3626 | | { PseudoVFNMADD_VFPR16_MF2, 658 }, |
3627 | | { PseudoVFNMADD_VFPR16_MF4, 659 }, |
3628 | | { PseudoVFNMADD_VFPR32_M1, 660 }, |
3629 | | { PseudoVFNMADD_VFPR32_M2, 661 }, |
3630 | | { PseudoVFNMADD_VFPR32_M4, 662 }, |
3631 | | { PseudoVFNMADD_VFPR32_M8, 663 }, |
3632 | | { PseudoVFNMADD_VFPR32_MF2, 664 }, |
3633 | | { PseudoVFNMADD_VFPR64_M1, 665 }, |
3634 | | { PseudoVFNMADD_VFPR64_M2, 666 }, |
3635 | | { PseudoVFNMADD_VFPR64_M4, 667 }, |
3636 | | { PseudoVFNMADD_VFPR64_M8, 668 }, |
3637 | | { PseudoVFNMADD_VV_M1, 669 }, |
3638 | | { PseudoVFNMADD_VV_M2, 670 }, |
3639 | | { PseudoVFNMADD_VV_M4, 671 }, |
3640 | | { PseudoVFNMADD_VV_M8, 672 }, |
3641 | | { PseudoVFNMADD_VV_MF2, 673 }, |
3642 | | { PseudoVFNMADD_VV_MF4, 674 }, |
3643 | | { PseudoVFNMSAC_VFPR16_M1, 675 }, |
3644 | | { PseudoVFNMSAC_VFPR16_M2, 676 }, |
3645 | | { PseudoVFNMSAC_VFPR16_M4, 677 }, |
3646 | | { PseudoVFNMSAC_VFPR16_M8, 678 }, |
3647 | | { PseudoVFNMSAC_VFPR16_MF2, 679 }, |
3648 | | { PseudoVFNMSAC_VFPR16_MF4, 680 }, |
3649 | | { PseudoVFNMSAC_VFPR32_M1, 681 }, |
3650 | | { PseudoVFNMSAC_VFPR32_M2, 682 }, |
3651 | | { PseudoVFNMSAC_VFPR32_M4, 683 }, |
3652 | | { PseudoVFNMSAC_VFPR32_M8, 684 }, |
3653 | | { PseudoVFNMSAC_VFPR32_MF2, 685 }, |
3654 | | { PseudoVFNMSAC_VFPR64_M1, 686 }, |
3655 | | { PseudoVFNMSAC_VFPR64_M2, 687 }, |
3656 | | { PseudoVFNMSAC_VFPR64_M4, 688 }, |
3657 | | { PseudoVFNMSAC_VFPR64_M8, 689 }, |
3658 | | { PseudoVFNMSAC_VV_M1, 690 }, |
3659 | | { PseudoVFNMSAC_VV_M2, 691 }, |
3660 | | { PseudoVFNMSAC_VV_M4, 692 }, |
3661 | | { PseudoVFNMSAC_VV_M8, 693 }, |
3662 | | { PseudoVFNMSAC_VV_MF2, 694 }, |
3663 | | { PseudoVFNMSAC_VV_MF4, 695 }, |
3664 | | { PseudoVFNMSUB_VFPR16_M1, 696 }, |
3665 | | { PseudoVFNMSUB_VFPR16_M2, 697 }, |
3666 | | { PseudoVFNMSUB_VFPR16_M4, 698 }, |
3667 | | { PseudoVFNMSUB_VFPR16_M8, 699 }, |
3668 | | { PseudoVFNMSUB_VFPR16_MF2, 700 }, |
3669 | | { PseudoVFNMSUB_VFPR16_MF4, 701 }, |
3670 | | { PseudoVFNMSUB_VFPR32_M1, 702 }, |
3671 | | { PseudoVFNMSUB_VFPR32_M2, 703 }, |
3672 | | { PseudoVFNMSUB_VFPR32_M4, 704 }, |
3673 | | { PseudoVFNMSUB_VFPR32_M8, 705 }, |
3674 | | { PseudoVFNMSUB_VFPR32_MF2, 706 }, |
3675 | | { PseudoVFNMSUB_VFPR64_M1, 707 }, |
3676 | | { PseudoVFNMSUB_VFPR64_M2, 708 }, |
3677 | | { PseudoVFNMSUB_VFPR64_M4, 709 }, |
3678 | | { PseudoVFNMSUB_VFPR64_M8, 710 }, |
3679 | | { PseudoVFNMSUB_VV_M1, 711 }, |
3680 | | { PseudoVFNMSUB_VV_M2, 712 }, |
3681 | | { PseudoVFNMSUB_VV_M4, 713 }, |
3682 | | { PseudoVFNMSUB_VV_M8, 714 }, |
3683 | | { PseudoVFNMSUB_VV_MF2, 715 }, |
3684 | | { PseudoVFNMSUB_VV_MF4, 716 }, |
3685 | | { PseudoVFNRCLIP_XU_F_QF_M1, 717 }, |
3686 | | { PseudoVFNRCLIP_XU_F_QF_M2, 718 }, |
3687 | | { PseudoVFNRCLIP_XU_F_QF_MF2, 719 }, |
3688 | | { PseudoVFNRCLIP_XU_F_QF_MF4, 720 }, |
3689 | | { PseudoVFNRCLIP_XU_F_QF_MF8, 721 }, |
3690 | | { PseudoVFNRCLIP_X_F_QF_M1, 722 }, |
3691 | | { PseudoVFNRCLIP_X_F_QF_M2, 723 }, |
3692 | | { PseudoVFNRCLIP_X_F_QF_MF2, 724 }, |
3693 | | { PseudoVFNRCLIP_X_F_QF_MF4, 725 }, |
3694 | | { PseudoVFNRCLIP_X_F_QF_MF8, 726 }, |
3695 | | { PseudoVFRDIV_VFPR16_M1_E16, 727 }, |
3696 | | { PseudoVFRDIV_VFPR16_M2_E16, 728 }, |
3697 | | { PseudoVFRDIV_VFPR16_M4_E16, 729 }, |
3698 | | { PseudoVFRDIV_VFPR16_M8_E16, 730 }, |
3699 | | { PseudoVFRDIV_VFPR16_MF2_E16, 731 }, |
3700 | | { PseudoVFRDIV_VFPR16_MF4_E16, 732 }, |
3701 | | { PseudoVFRDIV_VFPR32_M1_E32, 733 }, |
3702 | | { PseudoVFRDIV_VFPR32_M2_E32, 734 }, |
3703 | | { PseudoVFRDIV_VFPR32_M4_E32, 735 }, |
3704 | | { PseudoVFRDIV_VFPR32_M8_E32, 736 }, |
3705 | | { PseudoVFRDIV_VFPR32_MF2_E32, 737 }, |
3706 | | { PseudoVFRDIV_VFPR64_M1_E64, 738 }, |
3707 | | { PseudoVFRDIV_VFPR64_M2_E64, 739 }, |
3708 | | { PseudoVFRDIV_VFPR64_M4_E64, 740 }, |
3709 | | { PseudoVFRDIV_VFPR64_M8_E64, 741 }, |
3710 | | { PseudoVFREC7_V_M1, 742 }, |
3711 | | { PseudoVFREC7_V_M2, 743 }, |
3712 | | { PseudoVFREC7_V_M4, 744 }, |
3713 | | { PseudoVFREC7_V_M8, 745 }, |
3714 | | { PseudoVFREC7_V_MF2, 746 }, |
3715 | | { PseudoVFREC7_V_MF4, 747 }, |
3716 | | { PseudoVFREDMAX_VS_M1_E16, 748 }, |
3717 | | { PseudoVFREDMAX_VS_M1_E32, 749 }, |
3718 | | { PseudoVFREDMAX_VS_M1_E64, 750 }, |
3719 | | { PseudoVFREDMAX_VS_M2_E16, 751 }, |
3720 | | { PseudoVFREDMAX_VS_M2_E32, 752 }, |
3721 | | { PseudoVFREDMAX_VS_M2_E64, 753 }, |
3722 | | { PseudoVFREDMAX_VS_M4_E16, 754 }, |
3723 | | { PseudoVFREDMAX_VS_M4_E32, 755 }, |
3724 | | { PseudoVFREDMAX_VS_M4_E64, 756 }, |
3725 | | { PseudoVFREDMAX_VS_M8_E16, 757 }, |
3726 | | { PseudoVFREDMAX_VS_M8_E32, 758 }, |
3727 | | { PseudoVFREDMAX_VS_M8_E64, 759 }, |
3728 | | { PseudoVFREDMAX_VS_MF2_E16, 760 }, |
3729 | | { PseudoVFREDMAX_VS_MF2_E32, 761 }, |
3730 | | { PseudoVFREDMAX_VS_MF4_E16, 762 }, |
3731 | | { PseudoVFREDMIN_VS_M1_E16, 763 }, |
3732 | | { PseudoVFREDMIN_VS_M1_E32, 764 }, |
3733 | | { PseudoVFREDMIN_VS_M1_E64, 765 }, |
3734 | | { PseudoVFREDMIN_VS_M2_E16, 766 }, |
3735 | | { PseudoVFREDMIN_VS_M2_E32, 767 }, |
3736 | | { PseudoVFREDMIN_VS_M2_E64, 768 }, |
3737 | | { PseudoVFREDMIN_VS_M4_E16, 769 }, |
3738 | | { PseudoVFREDMIN_VS_M4_E32, 770 }, |
3739 | | { PseudoVFREDMIN_VS_M4_E64, 771 }, |
3740 | | { PseudoVFREDMIN_VS_M8_E16, 772 }, |
3741 | | { PseudoVFREDMIN_VS_M8_E32, 773 }, |
3742 | | { PseudoVFREDMIN_VS_M8_E64, 774 }, |
3743 | | { PseudoVFREDMIN_VS_MF2_E16, 775 }, |
3744 | | { PseudoVFREDMIN_VS_MF2_E32, 776 }, |
3745 | | { PseudoVFREDMIN_VS_MF4_E16, 777 }, |
3746 | | { PseudoVFREDOSUM_VS_M1_E16, 778 }, |
3747 | | { PseudoVFREDOSUM_VS_M1_E32, 779 }, |
3748 | | { PseudoVFREDOSUM_VS_M1_E64, 780 }, |
3749 | | { PseudoVFREDOSUM_VS_M2_E16, 781 }, |
3750 | | { PseudoVFREDOSUM_VS_M2_E32, 782 }, |
3751 | | { PseudoVFREDOSUM_VS_M2_E64, 783 }, |
3752 | | { PseudoVFREDOSUM_VS_M4_E16, 784 }, |
3753 | | { PseudoVFREDOSUM_VS_M4_E32, 785 }, |
3754 | | { PseudoVFREDOSUM_VS_M4_E64, 786 }, |
3755 | | { PseudoVFREDOSUM_VS_M8_E16, 787 }, |
3756 | | { PseudoVFREDOSUM_VS_M8_E32, 788 }, |
3757 | | { PseudoVFREDOSUM_VS_M8_E64, 789 }, |
3758 | | { PseudoVFREDOSUM_VS_MF2_E16, 790 }, |
3759 | | { PseudoVFREDOSUM_VS_MF2_E32, 791 }, |
3760 | | { PseudoVFREDOSUM_VS_MF4_E16, 792 }, |
3761 | | { PseudoVFREDUSUM_VS_M1_E16, 793 }, |
3762 | | { PseudoVFREDUSUM_VS_M1_E32, 794 }, |
3763 | | { PseudoVFREDUSUM_VS_M1_E64, 795 }, |
3764 | | { PseudoVFREDUSUM_VS_M2_E16, 796 }, |
3765 | | { PseudoVFREDUSUM_VS_M2_E32, 797 }, |
3766 | | { PseudoVFREDUSUM_VS_M2_E64, 798 }, |
3767 | | { PseudoVFREDUSUM_VS_M4_E16, 799 }, |
3768 | | { PseudoVFREDUSUM_VS_M4_E32, 800 }, |
3769 | | { PseudoVFREDUSUM_VS_M4_E64, 801 }, |
3770 | | { PseudoVFREDUSUM_VS_M8_E16, 802 }, |
3771 | | { PseudoVFREDUSUM_VS_M8_E32, 803 }, |
3772 | | { PseudoVFREDUSUM_VS_M8_E64, 804 }, |
3773 | | { PseudoVFREDUSUM_VS_MF2_E16, 805 }, |
3774 | | { PseudoVFREDUSUM_VS_MF2_E32, 806 }, |
3775 | | { PseudoVFREDUSUM_VS_MF4_E16, 807 }, |
3776 | | { PseudoVFRSQRT7_V_M1, 808 }, |
3777 | | { PseudoVFRSQRT7_V_M2, 809 }, |
3778 | | { PseudoVFRSQRT7_V_M4, 810 }, |
3779 | | { PseudoVFRSQRT7_V_M8, 811 }, |
3780 | | { PseudoVFRSQRT7_V_MF2, 812 }, |
3781 | | { PseudoVFRSQRT7_V_MF4, 813 }, |
3782 | | { PseudoVFRSUB_VFPR16_M1, 814 }, |
3783 | | { PseudoVFRSUB_VFPR16_M2, 815 }, |
3784 | | { PseudoVFRSUB_VFPR16_M4, 816 }, |
3785 | | { PseudoVFRSUB_VFPR16_M8, 817 }, |
3786 | | { PseudoVFRSUB_VFPR16_MF2, 818 }, |
3787 | | { PseudoVFRSUB_VFPR16_MF4, 819 }, |
3788 | | { PseudoVFRSUB_VFPR32_M1, 820 }, |
3789 | | { PseudoVFRSUB_VFPR32_M2, 821 }, |
3790 | | { PseudoVFRSUB_VFPR32_M4, 822 }, |
3791 | | { PseudoVFRSUB_VFPR32_M8, 823 }, |
3792 | | { PseudoVFRSUB_VFPR32_MF2, 824 }, |
3793 | | { PseudoVFRSUB_VFPR64_M1, 825 }, |
3794 | | { PseudoVFRSUB_VFPR64_M2, 826 }, |
3795 | | { PseudoVFRSUB_VFPR64_M4, 827 }, |
3796 | | { PseudoVFRSUB_VFPR64_M8, 828 }, |
3797 | | { PseudoVFSGNJN_VFPR16_M1, 829 }, |
3798 | | { PseudoVFSGNJN_VFPR16_M2, 830 }, |
3799 | | { PseudoVFSGNJN_VFPR16_M4, 831 }, |
3800 | | { PseudoVFSGNJN_VFPR16_M8, 832 }, |
3801 | | { PseudoVFSGNJN_VFPR16_MF2, 833 }, |
3802 | | { PseudoVFSGNJN_VFPR16_MF4, 834 }, |
3803 | | { PseudoVFSGNJN_VFPR32_M1, 835 }, |
3804 | | { PseudoVFSGNJN_VFPR32_M2, 836 }, |
3805 | | { PseudoVFSGNJN_VFPR32_M4, 837 }, |
3806 | | { PseudoVFSGNJN_VFPR32_M8, 838 }, |
3807 | | { PseudoVFSGNJN_VFPR32_MF2, 839 }, |
3808 | | { PseudoVFSGNJN_VFPR64_M1, 840 }, |
3809 | | { PseudoVFSGNJN_VFPR64_M2, 841 }, |
3810 | | { PseudoVFSGNJN_VFPR64_M4, 842 }, |
3811 | | { PseudoVFSGNJN_VFPR64_M8, 843 }, |
3812 | | { PseudoVFSGNJN_VV_M1, 844 }, |
3813 | | { PseudoVFSGNJN_VV_M2, 845 }, |
3814 | | { PseudoVFSGNJN_VV_M4, 846 }, |
3815 | | { PseudoVFSGNJN_VV_M8, 847 }, |
3816 | | { PseudoVFSGNJN_VV_MF2, 848 }, |
3817 | | { PseudoVFSGNJN_VV_MF4, 849 }, |
3818 | | { PseudoVFSGNJX_VFPR16_M1, 850 }, |
3819 | | { PseudoVFSGNJX_VFPR16_M2, 851 }, |
3820 | | { PseudoVFSGNJX_VFPR16_M4, 852 }, |
3821 | | { PseudoVFSGNJX_VFPR16_M8, 853 }, |
3822 | | { PseudoVFSGNJX_VFPR16_MF2, 854 }, |
3823 | | { PseudoVFSGNJX_VFPR16_MF4, 855 }, |
3824 | | { PseudoVFSGNJX_VFPR32_M1, 856 }, |
3825 | | { PseudoVFSGNJX_VFPR32_M2, 857 }, |
3826 | | { PseudoVFSGNJX_VFPR32_M4, 858 }, |
3827 | | { PseudoVFSGNJX_VFPR32_M8, 859 }, |
3828 | | { PseudoVFSGNJX_VFPR32_MF2, 860 }, |
3829 | | { PseudoVFSGNJX_VFPR64_M1, 861 }, |
3830 | | { PseudoVFSGNJX_VFPR64_M2, 862 }, |
3831 | | { PseudoVFSGNJX_VFPR64_M4, 863 }, |
3832 | | { PseudoVFSGNJX_VFPR64_M8, 864 }, |
3833 | | { PseudoVFSGNJX_VV_M1, 865 }, |
3834 | | { PseudoVFSGNJX_VV_M2, 866 }, |
3835 | | { PseudoVFSGNJX_VV_M4, 867 }, |
3836 | | { PseudoVFSGNJX_VV_M8, 868 }, |
3837 | | { PseudoVFSGNJX_VV_MF2, 869 }, |
3838 | | { PseudoVFSGNJX_VV_MF4, 870 }, |
3839 | | { PseudoVFSGNJ_VFPR16_M1, 871 }, |
3840 | | { PseudoVFSGNJ_VFPR16_M2, 872 }, |
3841 | | { PseudoVFSGNJ_VFPR16_M4, 873 }, |
3842 | | { PseudoVFSGNJ_VFPR16_M8, 874 }, |
3843 | | { PseudoVFSGNJ_VFPR16_MF2, 875 }, |
3844 | | { PseudoVFSGNJ_VFPR16_MF4, 876 }, |
3845 | | { PseudoVFSGNJ_VFPR32_M1, 877 }, |
3846 | | { PseudoVFSGNJ_VFPR32_M2, 878 }, |
3847 | | { PseudoVFSGNJ_VFPR32_M4, 879 }, |
3848 | | { PseudoVFSGNJ_VFPR32_M8, 880 }, |
3849 | | { PseudoVFSGNJ_VFPR32_MF2, 881 }, |
3850 | | { PseudoVFSGNJ_VFPR64_M1, 882 }, |
3851 | | { PseudoVFSGNJ_VFPR64_M2, 883 }, |
3852 | | { PseudoVFSGNJ_VFPR64_M4, 884 }, |
3853 | | { PseudoVFSGNJ_VFPR64_M8, 885 }, |
3854 | | { PseudoVFSGNJ_VV_M1, 886 }, |
3855 | | { PseudoVFSGNJ_VV_M2, 887 }, |
3856 | | { PseudoVFSGNJ_VV_M4, 888 }, |
3857 | | { PseudoVFSGNJ_VV_M8, 889 }, |
3858 | | { PseudoVFSGNJ_VV_MF2, 890 }, |
3859 | | { PseudoVFSGNJ_VV_MF4, 891 }, |
3860 | | { PseudoVFSLIDE1DOWN_VFPR16_M1, 892 }, |
3861 | | { PseudoVFSLIDE1DOWN_VFPR16_M2, 893 }, |
3862 | | { PseudoVFSLIDE1DOWN_VFPR16_M4, 894 }, |
3863 | | { PseudoVFSLIDE1DOWN_VFPR16_M8, 895 }, |
3864 | | { PseudoVFSLIDE1DOWN_VFPR16_MF2, 896 }, |
3865 | | { PseudoVFSLIDE1DOWN_VFPR16_MF4, 897 }, |
3866 | | { PseudoVFSLIDE1DOWN_VFPR32_M1, 898 }, |
3867 | | { PseudoVFSLIDE1DOWN_VFPR32_M2, 899 }, |
3868 | | { PseudoVFSLIDE1DOWN_VFPR32_M4, 900 }, |
3869 | | { PseudoVFSLIDE1DOWN_VFPR32_M8, 901 }, |
3870 | | { PseudoVFSLIDE1DOWN_VFPR32_MF2, 902 }, |
3871 | | { PseudoVFSLIDE1DOWN_VFPR64_M1, 903 }, |
3872 | | { PseudoVFSLIDE1DOWN_VFPR64_M2, 904 }, |
3873 | | { PseudoVFSLIDE1DOWN_VFPR64_M4, 905 }, |
3874 | | { PseudoVFSLIDE1DOWN_VFPR64_M8, 906 }, |
3875 | | { PseudoVFSLIDE1UP_VFPR16_M1, 907 }, |
3876 | | { PseudoVFSLIDE1UP_VFPR16_M2, 908 }, |
3877 | | { PseudoVFSLIDE1UP_VFPR16_M4, 909 }, |
3878 | | { PseudoVFSLIDE1UP_VFPR16_M8, 910 }, |
3879 | | { PseudoVFSLIDE1UP_VFPR16_MF2, 911 }, |
3880 | | { PseudoVFSLIDE1UP_VFPR16_MF4, 912 }, |
3881 | | { PseudoVFSLIDE1UP_VFPR32_M1, 913 }, |
3882 | | { PseudoVFSLIDE1UP_VFPR32_M2, 914 }, |
3883 | | { PseudoVFSLIDE1UP_VFPR32_M4, 915 }, |
3884 | | { PseudoVFSLIDE1UP_VFPR32_M8, 916 }, |
3885 | | { PseudoVFSLIDE1UP_VFPR32_MF2, 917 }, |
3886 | | { PseudoVFSLIDE1UP_VFPR64_M1, 918 }, |
3887 | | { PseudoVFSLIDE1UP_VFPR64_M2, 919 }, |
3888 | | { PseudoVFSLIDE1UP_VFPR64_M4, 920 }, |
3889 | | { PseudoVFSLIDE1UP_VFPR64_M8, 921 }, |
3890 | | { PseudoVFSQRT_V_M1_E16, 922 }, |
3891 | | { PseudoVFSQRT_V_M1_E32, 923 }, |
3892 | | { PseudoVFSQRT_V_M1_E64, 924 }, |
3893 | | { PseudoVFSQRT_V_M2_E16, 925 }, |
3894 | | { PseudoVFSQRT_V_M2_E32, 926 }, |
3895 | | { PseudoVFSQRT_V_M2_E64, 927 }, |
3896 | | { PseudoVFSQRT_V_M4_E16, 928 }, |
3897 | | { PseudoVFSQRT_V_M4_E32, 929 }, |
3898 | | { PseudoVFSQRT_V_M4_E64, 930 }, |
3899 | | { PseudoVFSQRT_V_M8_E16, 931 }, |
3900 | | { PseudoVFSQRT_V_M8_E32, 932 }, |
3901 | | { PseudoVFSQRT_V_M8_E64, 933 }, |
3902 | | { PseudoVFSQRT_V_MF2_E16, 934 }, |
3903 | | { PseudoVFSQRT_V_MF2_E32, 935 }, |
3904 | | { PseudoVFSQRT_V_MF4_E16, 936 }, |
3905 | | { PseudoVFSUB_VFPR16_M1, 937 }, |
3906 | | { PseudoVFSUB_VFPR16_M2, 938 }, |
3907 | | { PseudoVFSUB_VFPR16_M4, 939 }, |
3908 | | { PseudoVFSUB_VFPR16_M8, 940 }, |
3909 | | { PseudoVFSUB_VFPR16_MF2, 941 }, |
3910 | | { PseudoVFSUB_VFPR16_MF4, 942 }, |
3911 | | { PseudoVFSUB_VFPR32_M1, 943 }, |
3912 | | { PseudoVFSUB_VFPR32_M2, 944 }, |
3913 | | { PseudoVFSUB_VFPR32_M4, 945 }, |
3914 | | { PseudoVFSUB_VFPR32_M8, 946 }, |
3915 | | { PseudoVFSUB_VFPR32_MF2, 947 }, |
3916 | | { PseudoVFSUB_VFPR64_M1, 948 }, |
3917 | | { PseudoVFSUB_VFPR64_M2, 949 }, |
3918 | | { PseudoVFSUB_VFPR64_M4, 950 }, |
3919 | | { PseudoVFSUB_VFPR64_M8, 951 }, |
3920 | | { PseudoVFSUB_VV_M1, 952 }, |
3921 | | { PseudoVFSUB_VV_M2, 953 }, |
3922 | | { PseudoVFSUB_VV_M4, 954 }, |
3923 | | { PseudoVFSUB_VV_M8, 955 }, |
3924 | | { PseudoVFSUB_VV_MF2, 956 }, |
3925 | | { PseudoVFSUB_VV_MF4, 957 }, |
3926 | | { PseudoVFWADD_VFPR16_M1, 958 }, |
3927 | | { PseudoVFWADD_VFPR16_M2, 959 }, |
3928 | | { PseudoVFWADD_VFPR16_M4, 960 }, |
3929 | | { PseudoVFWADD_VFPR16_MF2, 961 }, |
3930 | | { PseudoVFWADD_VFPR16_MF4, 962 }, |
3931 | | { PseudoVFWADD_VFPR32_M1, 963 }, |
3932 | | { PseudoVFWADD_VFPR32_M2, 964 }, |
3933 | | { PseudoVFWADD_VFPR32_M4, 965 }, |
3934 | | { PseudoVFWADD_VFPR32_MF2, 966 }, |
3935 | | { PseudoVFWADD_VV_M1, 967 }, |
3936 | | { PseudoVFWADD_VV_M2, 968 }, |
3937 | | { PseudoVFWADD_VV_M4, 969 }, |
3938 | | { PseudoVFWADD_VV_MF2, 970 }, |
3939 | | { PseudoVFWADD_VV_MF4, 971 }, |
3940 | | { PseudoVFWADD_WFPR16_M1, 972 }, |
3941 | | { PseudoVFWADD_WFPR16_M2, 973 }, |
3942 | | { PseudoVFWADD_WFPR16_M4, 974 }, |
3943 | | { PseudoVFWADD_WFPR16_MF2, 975 }, |
3944 | | { PseudoVFWADD_WFPR16_MF4, 976 }, |
3945 | | { PseudoVFWADD_WFPR32_M1, 977 }, |
3946 | | { PseudoVFWADD_WFPR32_M2, 978 }, |
3947 | | { PseudoVFWADD_WFPR32_M4, 979 }, |
3948 | | { PseudoVFWADD_WFPR32_MF2, 980 }, |
3949 | | { PseudoVFWADD_WV_M1, 981 }, |
3950 | | { PseudoVFWADD_WV_M2, 982 }, |
3951 | | { PseudoVFWADD_WV_M4, 983 }, |
3952 | | { PseudoVFWADD_WV_MF2, 984 }, |
3953 | | { PseudoVFWADD_WV_MF4, 985 }, |
3954 | | { PseudoVFWCVTBF16_F_F_V_M1, 986 }, |
3955 | | { PseudoVFWCVTBF16_F_F_V_M2, 987 }, |
3956 | | { PseudoVFWCVTBF16_F_F_V_M4, 988 }, |
3957 | | { PseudoVFWCVTBF16_F_F_V_MF2, 989 }, |
3958 | | { PseudoVFWCVTBF16_F_F_V_MF4, 990 }, |
3959 | | { PseudoVFWCVT_F_F_V_M1, 991 }, |
3960 | | { PseudoVFWCVT_F_F_V_M2, 992 }, |
3961 | | { PseudoVFWCVT_F_F_V_M4, 993 }, |
3962 | | { PseudoVFWCVT_F_F_V_MF2, 994 }, |
3963 | | { PseudoVFWCVT_F_F_V_MF4, 995 }, |
3964 | | { PseudoVFWCVT_F_XU_V_M1, 996 }, |
3965 | | { PseudoVFWCVT_F_XU_V_M2, 997 }, |
3966 | | { PseudoVFWCVT_F_XU_V_M4, 998 }, |
3967 | | { PseudoVFWCVT_F_XU_V_MF2, 999 }, |
3968 | | { PseudoVFWCVT_F_XU_V_MF4, 1000 }, |
3969 | | { PseudoVFWCVT_F_XU_V_MF8, 1001 }, |
3970 | | { PseudoVFWCVT_F_X_V_M1, 1002 }, |
3971 | | { PseudoVFWCVT_F_X_V_M2, 1003 }, |
3972 | | { PseudoVFWCVT_F_X_V_M4, 1004 }, |
3973 | | { PseudoVFWCVT_F_X_V_MF2, 1005 }, |
3974 | | { PseudoVFWCVT_F_X_V_MF4, 1006 }, |
3975 | | { PseudoVFWCVT_F_X_V_MF8, 1007 }, |
3976 | | { PseudoVFWCVT_RM_XU_F_V_M1, 1008 }, |
3977 | | { PseudoVFWCVT_RM_XU_F_V_M2, 1009 }, |
3978 | | { PseudoVFWCVT_RM_XU_F_V_M4, 1010 }, |
3979 | | { PseudoVFWCVT_RM_XU_F_V_MF2, 1011 }, |
3980 | | { PseudoVFWCVT_RM_XU_F_V_MF4, 1012 }, |
3981 | | { PseudoVFWCVT_RM_X_F_V_M1, 1013 }, |
3982 | | { PseudoVFWCVT_RM_X_F_V_M2, 1014 }, |
3983 | | { PseudoVFWCVT_RM_X_F_V_M4, 1015 }, |
3984 | | { PseudoVFWCVT_RM_X_F_V_MF2, 1016 }, |
3985 | | { PseudoVFWCVT_RM_X_F_V_MF4, 1017 }, |
3986 | | { PseudoVFWCVT_RTZ_XU_F_V_M1, 1018 }, |
3987 | | { PseudoVFWCVT_RTZ_XU_F_V_M2, 1019 }, |
3988 | | { PseudoVFWCVT_RTZ_XU_F_V_M4, 1020 }, |
3989 | | { PseudoVFWCVT_RTZ_XU_F_V_MF2, 1021 }, |
3990 | | { PseudoVFWCVT_RTZ_XU_F_V_MF4, 1022 }, |
3991 | | { PseudoVFWCVT_RTZ_X_F_V_M1, 1023 }, |
3992 | | { PseudoVFWCVT_RTZ_X_F_V_M2, 1024 }, |
3993 | | { PseudoVFWCVT_RTZ_X_F_V_M4, 1025 }, |
3994 | | { PseudoVFWCVT_RTZ_X_F_V_MF2, 1026 }, |
3995 | | { PseudoVFWCVT_RTZ_X_F_V_MF4, 1027 }, |
3996 | | { PseudoVFWCVT_XU_F_V_M1, 1028 }, |
3997 | | { PseudoVFWCVT_XU_F_V_M2, 1029 }, |
3998 | | { PseudoVFWCVT_XU_F_V_M4, 1030 }, |
3999 | | { PseudoVFWCVT_XU_F_V_MF2, 1031 }, |
4000 | | { PseudoVFWCVT_XU_F_V_MF4, 1032 }, |
4001 | | { PseudoVFWCVT_X_F_V_M1, 1033 }, |
4002 | | { PseudoVFWCVT_X_F_V_M2, 1034 }, |
4003 | | { PseudoVFWCVT_X_F_V_M4, 1035 }, |
4004 | | { PseudoVFWCVT_X_F_V_MF2, 1036 }, |
4005 | | { PseudoVFWCVT_X_F_V_MF4, 1037 }, |
4006 | | { PseudoVFWMACCBF16_VFPR16_M1, 1038 }, |
4007 | | { PseudoVFWMACCBF16_VFPR16_M2, 1039 }, |
4008 | | { PseudoVFWMACCBF16_VFPR16_M4, 1040 }, |
4009 | | { PseudoVFWMACCBF16_VFPR16_MF2, 1041 }, |
4010 | | { PseudoVFWMACCBF16_VFPR16_MF4, 1042 }, |
4011 | | { PseudoVFWMACCBF16_VV_M1, 1043 }, |
4012 | | { PseudoVFWMACCBF16_VV_M2, 1044 }, |
4013 | | { PseudoVFWMACCBF16_VV_M4, 1045 }, |
4014 | | { PseudoVFWMACCBF16_VV_MF2, 1046 }, |
4015 | | { PseudoVFWMACCBF16_VV_MF4, 1047 }, |
4016 | | { PseudoVFWMACC_VFPR16_M1, 1048 }, |
4017 | | { PseudoVFWMACC_VFPR16_M2, 1049 }, |
4018 | | { PseudoVFWMACC_VFPR16_M4, 1050 }, |
4019 | | { PseudoVFWMACC_VFPR16_MF2, 1051 }, |
4020 | | { PseudoVFWMACC_VFPR16_MF4, 1052 }, |
4021 | | { PseudoVFWMACC_VFPR32_M1, 1053 }, |
4022 | | { PseudoVFWMACC_VFPR32_M2, 1054 }, |
4023 | | { PseudoVFWMACC_VFPR32_M4, 1055 }, |
4024 | | { PseudoVFWMACC_VFPR32_MF2, 1056 }, |
4025 | | { PseudoVFWMACC_VV_M1, 1057 }, |
4026 | | { PseudoVFWMACC_VV_M2, 1058 }, |
4027 | | { PseudoVFWMACC_VV_M4, 1059 }, |
4028 | | { PseudoVFWMACC_VV_MF2, 1060 }, |
4029 | | { PseudoVFWMACC_VV_MF4, 1061 }, |
4030 | | { PseudoVFWMSAC_VFPR16_M1, 1062 }, |
4031 | | { PseudoVFWMSAC_VFPR16_M2, 1063 }, |
4032 | | { PseudoVFWMSAC_VFPR16_M4, 1064 }, |
4033 | | { PseudoVFWMSAC_VFPR16_MF2, 1065 }, |
4034 | | { PseudoVFWMSAC_VFPR16_MF4, 1066 }, |
4035 | | { PseudoVFWMSAC_VFPR32_M1, 1067 }, |
4036 | | { PseudoVFWMSAC_VFPR32_M2, 1068 }, |
4037 | | { PseudoVFWMSAC_VFPR32_M4, 1069 }, |
4038 | | { PseudoVFWMSAC_VFPR32_MF2, 1070 }, |
4039 | | { PseudoVFWMSAC_VV_M1, 1071 }, |
4040 | | { PseudoVFWMSAC_VV_M2, 1072 }, |
4041 | | { PseudoVFWMSAC_VV_M4, 1073 }, |
4042 | | { PseudoVFWMSAC_VV_MF2, 1074 }, |
4043 | | { PseudoVFWMSAC_VV_MF4, 1075 }, |
4044 | | { PseudoVFWMUL_VFPR16_M1, 1076 }, |
4045 | | { PseudoVFWMUL_VFPR16_M2, 1077 }, |
4046 | | { PseudoVFWMUL_VFPR16_M4, 1078 }, |
4047 | | { PseudoVFWMUL_VFPR16_MF2, 1079 }, |
4048 | | { PseudoVFWMUL_VFPR16_MF4, 1080 }, |
4049 | | { PseudoVFWMUL_VFPR32_M1, 1081 }, |
4050 | | { PseudoVFWMUL_VFPR32_M2, 1082 }, |
4051 | | { PseudoVFWMUL_VFPR32_M4, 1083 }, |
4052 | | { PseudoVFWMUL_VFPR32_MF2, 1084 }, |
4053 | | { PseudoVFWMUL_VV_M1, 1085 }, |
4054 | | { PseudoVFWMUL_VV_M2, 1086 }, |
4055 | | { PseudoVFWMUL_VV_M4, 1087 }, |
4056 | | { PseudoVFWMUL_VV_MF2, 1088 }, |
4057 | | { PseudoVFWMUL_VV_MF4, 1089 }, |
4058 | | { PseudoVFWNMACC_VFPR16_M1, 1090 }, |
4059 | | { PseudoVFWNMACC_VFPR16_M2, 1091 }, |
4060 | | { PseudoVFWNMACC_VFPR16_M4, 1092 }, |
4061 | | { PseudoVFWNMACC_VFPR16_MF2, 1093 }, |
4062 | | { PseudoVFWNMACC_VFPR16_MF4, 1094 }, |
4063 | | { PseudoVFWNMACC_VFPR32_M1, 1095 }, |
4064 | | { PseudoVFWNMACC_VFPR32_M2, 1096 }, |
4065 | | { PseudoVFWNMACC_VFPR32_M4, 1097 }, |
4066 | | { PseudoVFWNMACC_VFPR32_MF2, 1098 }, |
4067 | | { PseudoVFWNMACC_VV_M1, 1099 }, |
4068 | | { PseudoVFWNMACC_VV_M2, 1100 }, |
4069 | | { PseudoVFWNMACC_VV_M4, 1101 }, |
4070 | | { PseudoVFWNMACC_VV_MF2, 1102 }, |
4071 | | { PseudoVFWNMACC_VV_MF4, 1103 }, |
4072 | | { PseudoVFWNMSAC_VFPR16_M1, 1104 }, |
4073 | | { PseudoVFWNMSAC_VFPR16_M2, 1105 }, |
4074 | | { PseudoVFWNMSAC_VFPR16_M4, 1106 }, |
4075 | | { PseudoVFWNMSAC_VFPR16_MF2, 1107 }, |
4076 | | { PseudoVFWNMSAC_VFPR16_MF4, 1108 }, |
4077 | | { PseudoVFWNMSAC_VFPR32_M1, 1109 }, |
4078 | | { PseudoVFWNMSAC_VFPR32_M2, 1110 }, |
4079 | | { PseudoVFWNMSAC_VFPR32_M4, 1111 }, |
4080 | | { PseudoVFWNMSAC_VFPR32_MF2, 1112 }, |
4081 | | { PseudoVFWNMSAC_VV_M1, 1113 }, |
4082 | | { PseudoVFWNMSAC_VV_M2, 1114 }, |
4083 | | { PseudoVFWNMSAC_VV_M4, 1115 }, |
4084 | | { PseudoVFWNMSAC_VV_MF2, 1116 }, |
4085 | | { PseudoVFWNMSAC_VV_MF4, 1117 }, |
4086 | | { PseudoVFWREDOSUM_VS_M1_E16, 1118 }, |
4087 | | { PseudoVFWREDOSUM_VS_M1_E32, 1119 }, |
4088 | | { PseudoVFWREDOSUM_VS_M2_E16, 1120 }, |
4089 | | { PseudoVFWREDOSUM_VS_M2_E32, 1121 }, |
4090 | | { PseudoVFWREDOSUM_VS_M4_E16, 1122 }, |
4091 | | { PseudoVFWREDOSUM_VS_M4_E32, 1123 }, |
4092 | | { PseudoVFWREDOSUM_VS_M8_E16, 1124 }, |
4093 | | { PseudoVFWREDOSUM_VS_M8_E32, 1125 }, |
4094 | | { PseudoVFWREDOSUM_VS_MF2_E16, 1126 }, |
4095 | | { PseudoVFWREDOSUM_VS_MF2_E32, 1127 }, |
4096 | | { PseudoVFWREDOSUM_VS_MF4_E16, 1128 }, |
4097 | | { PseudoVFWREDUSUM_VS_M1_E16, 1129 }, |
4098 | | { PseudoVFWREDUSUM_VS_M1_E32, 1130 }, |
4099 | | { PseudoVFWREDUSUM_VS_M2_E16, 1131 }, |
4100 | | { PseudoVFWREDUSUM_VS_M2_E32, 1132 }, |
4101 | | { PseudoVFWREDUSUM_VS_M4_E16, 1133 }, |
4102 | | { PseudoVFWREDUSUM_VS_M4_E32, 1134 }, |
4103 | | { PseudoVFWREDUSUM_VS_M8_E16, 1135 }, |
4104 | | { PseudoVFWREDUSUM_VS_M8_E32, 1136 }, |
4105 | | { PseudoVFWREDUSUM_VS_MF2_E16, 1137 }, |
4106 | | { PseudoVFWREDUSUM_VS_MF2_E32, 1138 }, |
4107 | | { PseudoVFWREDUSUM_VS_MF4_E16, 1139 }, |
4108 | | { PseudoVFWSUB_VFPR16_M1, 1140 }, |
4109 | | { PseudoVFWSUB_VFPR16_M2, 1141 }, |
4110 | | { PseudoVFWSUB_VFPR16_M4, 1142 }, |
4111 | | { PseudoVFWSUB_VFPR16_MF2, 1143 }, |
4112 | | { PseudoVFWSUB_VFPR16_MF4, 1144 }, |
4113 | | { PseudoVFWSUB_VFPR32_M1, 1145 }, |
4114 | | { PseudoVFWSUB_VFPR32_M2, 1146 }, |
4115 | | { PseudoVFWSUB_VFPR32_M4, 1147 }, |
4116 | | { PseudoVFWSUB_VFPR32_MF2, 1148 }, |
4117 | | { PseudoVFWSUB_VV_M1, 1149 }, |
4118 | | { PseudoVFWSUB_VV_M2, 1150 }, |
4119 | | { PseudoVFWSUB_VV_M4, 1151 }, |
4120 | | { PseudoVFWSUB_VV_MF2, 1152 }, |
4121 | | { PseudoVFWSUB_VV_MF4, 1153 }, |
4122 | | { PseudoVFWSUB_WFPR16_M1, 1154 }, |
4123 | | { PseudoVFWSUB_WFPR16_M2, 1155 }, |
4124 | | { PseudoVFWSUB_WFPR16_M4, 1156 }, |
4125 | | { PseudoVFWSUB_WFPR16_MF2, 1157 }, |
4126 | | { PseudoVFWSUB_WFPR16_MF4, 1158 }, |
4127 | | { PseudoVFWSUB_WFPR32_M1, 1159 }, |
4128 | | { PseudoVFWSUB_WFPR32_M2, 1160 }, |
4129 | | { PseudoVFWSUB_WFPR32_M4, 1161 }, |
4130 | | { PseudoVFWSUB_WFPR32_MF2, 1162 }, |
4131 | | { PseudoVFWSUB_WV_M1, 1163 }, |
4132 | | { PseudoVFWSUB_WV_M2, 1164 }, |
4133 | | { PseudoVFWSUB_WV_M4, 1165 }, |
4134 | | { PseudoVFWSUB_WV_MF2, 1166 }, |
4135 | | { PseudoVFWSUB_WV_MF4, 1167 }, |
4136 | | { PseudoVID_V_M1, 1168 }, |
4137 | | { PseudoVID_V_M2, 1169 }, |
4138 | | { PseudoVID_V_M4, 1170 }, |
4139 | | { PseudoVID_V_M8, 1171 }, |
4140 | | { PseudoVID_V_MF2, 1172 }, |
4141 | | { PseudoVID_V_MF4, 1173 }, |
4142 | | { PseudoVID_V_MF8, 1174 }, |
4143 | | { PseudoVIOTA_M_M1, 1175 }, |
4144 | | { PseudoVIOTA_M_M2, 1176 }, |
4145 | | { PseudoVIOTA_M_M4, 1177 }, |
4146 | | { PseudoVIOTA_M_M8, 1178 }, |
4147 | | { PseudoVIOTA_M_MF2, 1179 }, |
4148 | | { PseudoVIOTA_M_MF4, 1180 }, |
4149 | | { PseudoVIOTA_M_MF8, 1181 }, |
4150 | | { PseudoVLE16FF_V_M1, 1182 }, |
4151 | | { PseudoVLE16FF_V_M2, 1183 }, |
4152 | | { PseudoVLE16FF_V_M4, 1184 }, |
4153 | | { PseudoVLE16FF_V_M8, 1185 }, |
4154 | | { PseudoVLE16FF_V_MF2, 1186 }, |
4155 | | { PseudoVLE16FF_V_MF4, 1187 }, |
4156 | | { PseudoVLE16_V_M1, 1188 }, |
4157 | | { PseudoVLE16_V_M2, 1189 }, |
4158 | | { PseudoVLE16_V_M4, 1190 }, |
4159 | | { PseudoVLE16_V_M8, 1191 }, |
4160 | | { PseudoVLE16_V_MF2, 1192 }, |
4161 | | { PseudoVLE16_V_MF4, 1193 }, |
4162 | | { PseudoVLE32FF_V_M1, 1194 }, |
4163 | | { PseudoVLE32FF_V_M2, 1195 }, |
4164 | | { PseudoVLE32FF_V_M4, 1196 }, |
4165 | | { PseudoVLE32FF_V_M8, 1197 }, |
4166 | | { PseudoVLE32FF_V_MF2, 1198 }, |
4167 | | { PseudoVLE32_V_M1, 1199 }, |
4168 | | { PseudoVLE32_V_M2, 1200 }, |
4169 | | { PseudoVLE32_V_M4, 1201 }, |
4170 | | { PseudoVLE32_V_M8, 1202 }, |
4171 | | { PseudoVLE32_V_MF2, 1203 }, |
4172 | | { PseudoVLE64FF_V_M1, 1204 }, |
4173 | | { PseudoVLE64FF_V_M2, 1205 }, |
4174 | | { PseudoVLE64FF_V_M4, 1206 }, |
4175 | | { PseudoVLE64FF_V_M8, 1207 }, |
4176 | | { PseudoVLE64_V_M1, 1208 }, |
4177 | | { PseudoVLE64_V_M2, 1209 }, |
4178 | | { PseudoVLE64_V_M4, 1210 }, |
4179 | | { PseudoVLE64_V_M8, 1211 }, |
4180 | | { PseudoVLE8FF_V_M1, 1212 }, |
4181 | | { PseudoVLE8FF_V_M2, 1213 }, |
4182 | | { PseudoVLE8FF_V_M4, 1214 }, |
4183 | | { PseudoVLE8FF_V_M8, 1215 }, |
4184 | | { PseudoVLE8FF_V_MF2, 1216 }, |
4185 | | { PseudoVLE8FF_V_MF4, 1217 }, |
4186 | | { PseudoVLE8FF_V_MF8, 1218 }, |
4187 | | { PseudoVLE8_V_M1, 1219 }, |
4188 | | { PseudoVLE8_V_M2, 1220 }, |
4189 | | { PseudoVLE8_V_M4, 1221 }, |
4190 | | { PseudoVLE8_V_M8, 1222 }, |
4191 | | { PseudoVLE8_V_MF2, 1223 }, |
4192 | | { PseudoVLE8_V_MF4, 1224 }, |
4193 | | { PseudoVLE8_V_MF8, 1225 }, |
4194 | | { PseudoVLOXEI16_V_M1_M1, 1226 }, |
4195 | | { PseudoVLOXEI16_V_M1_M2, 1227 }, |
4196 | | { PseudoVLOXEI16_V_M1_M4, 1228 }, |
4197 | | { PseudoVLOXEI16_V_M1_MF2, 1229 }, |
4198 | | { PseudoVLOXEI16_V_M2_M1, 1230 }, |
4199 | | { PseudoVLOXEI16_V_M2_M2, 1231 }, |
4200 | | { PseudoVLOXEI16_V_M2_M4, 1232 }, |
4201 | | { PseudoVLOXEI16_V_M2_M8, 1233 }, |
4202 | | { PseudoVLOXEI16_V_M4_M2, 1234 }, |
4203 | | { PseudoVLOXEI16_V_M4_M4, 1235 }, |
4204 | | { PseudoVLOXEI16_V_M4_M8, 1236 }, |
4205 | | { PseudoVLOXEI16_V_M8_M4, 1237 }, |
4206 | | { PseudoVLOXEI16_V_M8_M8, 1238 }, |
4207 | | { PseudoVLOXEI16_V_MF2_M1, 1239 }, |
4208 | | { PseudoVLOXEI16_V_MF2_M2, 1240 }, |
4209 | | { PseudoVLOXEI16_V_MF2_MF2, 1241 }, |
4210 | | { PseudoVLOXEI16_V_MF2_MF4, 1242 }, |
4211 | | { PseudoVLOXEI16_V_MF4_M1, 1243 }, |
4212 | | { PseudoVLOXEI16_V_MF4_MF2, 1244 }, |
4213 | | { PseudoVLOXEI16_V_MF4_MF4, 1245 }, |
4214 | | { PseudoVLOXEI16_V_MF4_MF8, 1246 }, |
4215 | | { PseudoVLOXEI32_V_M1_M1, 1247 }, |
4216 | | { PseudoVLOXEI32_V_M1_M2, 1248 }, |
4217 | | { PseudoVLOXEI32_V_M1_MF2, 1249 }, |
4218 | | { PseudoVLOXEI32_V_M1_MF4, 1250 }, |
4219 | | { PseudoVLOXEI32_V_M2_M1, 1251 }, |
4220 | | { PseudoVLOXEI32_V_M2_M2, 1252 }, |
4221 | | { PseudoVLOXEI32_V_M2_M4, 1253 }, |
4222 | | { PseudoVLOXEI32_V_M2_MF2, 1254 }, |
4223 | | { PseudoVLOXEI32_V_M4_M1, 1255 }, |
4224 | | { PseudoVLOXEI32_V_M4_M2, 1256 }, |
4225 | | { PseudoVLOXEI32_V_M4_M4, 1257 }, |
4226 | | { PseudoVLOXEI32_V_M4_M8, 1258 }, |
4227 | | { PseudoVLOXEI32_V_M8_M2, 1259 }, |
4228 | | { PseudoVLOXEI32_V_M8_M4, 1260 }, |
4229 | | { PseudoVLOXEI32_V_M8_M8, 1261 }, |
4230 | | { PseudoVLOXEI32_V_MF2_M1, 1262 }, |
4231 | | { PseudoVLOXEI32_V_MF2_MF2, 1263 }, |
4232 | | { PseudoVLOXEI32_V_MF2_MF4, 1264 }, |
4233 | | { PseudoVLOXEI32_V_MF2_MF8, 1265 }, |
4234 | | { PseudoVLOXEI64_V_M1_M1, 1266 }, |
4235 | | { PseudoVLOXEI64_V_M1_MF2, 1267 }, |
4236 | | { PseudoVLOXEI64_V_M1_MF4, 1268 }, |
4237 | | { PseudoVLOXEI64_V_M1_MF8, 1269 }, |
4238 | | { PseudoVLOXEI64_V_M2_M1, 1270 }, |
4239 | | { PseudoVLOXEI64_V_M2_M2, 1271 }, |
4240 | | { PseudoVLOXEI64_V_M2_MF2, 1272 }, |
4241 | | { PseudoVLOXEI64_V_M2_MF4, 1273 }, |
4242 | | { PseudoVLOXEI64_V_M4_M1, 1274 }, |
4243 | | { PseudoVLOXEI64_V_M4_M2, 1275 }, |
4244 | | { PseudoVLOXEI64_V_M4_M4, 1276 }, |
4245 | | { PseudoVLOXEI64_V_M4_MF2, 1277 }, |
4246 | | { PseudoVLOXEI64_V_M8_M1, 1278 }, |
4247 | | { PseudoVLOXEI64_V_M8_M2, 1279 }, |
4248 | | { PseudoVLOXEI64_V_M8_M4, 1280 }, |
4249 | | { PseudoVLOXEI64_V_M8_M8, 1281 }, |
4250 | | { PseudoVLOXEI8_V_M1_M1, 1282 }, |
4251 | | { PseudoVLOXEI8_V_M1_M2, 1283 }, |
4252 | | { PseudoVLOXEI8_V_M1_M4, 1284 }, |
4253 | | { PseudoVLOXEI8_V_M1_M8, 1285 }, |
4254 | | { PseudoVLOXEI8_V_M2_M2, 1286 }, |
4255 | | { PseudoVLOXEI8_V_M2_M4, 1287 }, |
4256 | | { PseudoVLOXEI8_V_M2_M8, 1288 }, |
4257 | | { PseudoVLOXEI8_V_M4_M4, 1289 }, |
4258 | | { PseudoVLOXEI8_V_M4_M8, 1290 }, |
4259 | | { PseudoVLOXEI8_V_M8_M8, 1291 }, |
4260 | | { PseudoVLOXEI8_V_MF2_M1, 1292 }, |
4261 | | { PseudoVLOXEI8_V_MF2_M2, 1293 }, |
4262 | | { PseudoVLOXEI8_V_MF2_M4, 1294 }, |
4263 | | { PseudoVLOXEI8_V_MF2_MF2, 1295 }, |
4264 | | { PseudoVLOXEI8_V_MF4_M1, 1296 }, |
4265 | | { PseudoVLOXEI8_V_MF4_M2, 1297 }, |
4266 | | { PseudoVLOXEI8_V_MF4_MF2, 1298 }, |
4267 | | { PseudoVLOXEI8_V_MF4_MF4, 1299 }, |
4268 | | { PseudoVLOXEI8_V_MF8_M1, 1300 }, |
4269 | | { PseudoVLOXEI8_V_MF8_MF2, 1301 }, |
4270 | | { PseudoVLOXEI8_V_MF8_MF4, 1302 }, |
4271 | | { PseudoVLOXEI8_V_MF8_MF8, 1303 }, |
4272 | | { PseudoVLSE16_V_M1, 1304 }, |
4273 | | { PseudoVLSE16_V_M2, 1305 }, |
4274 | | { PseudoVLSE16_V_M4, 1306 }, |
4275 | | { PseudoVLSE16_V_M8, 1307 }, |
4276 | | { PseudoVLSE16_V_MF2, 1308 }, |
4277 | | { PseudoVLSE16_V_MF4, 1309 }, |
4278 | | { PseudoVLSE32_V_M1, 1310 }, |
4279 | | { PseudoVLSE32_V_M2, 1311 }, |
4280 | | { PseudoVLSE32_V_M4, 1312 }, |
4281 | | { PseudoVLSE32_V_M8, 1313 }, |
4282 | | { PseudoVLSE32_V_MF2, 1314 }, |
4283 | | { PseudoVLSE64_V_M1, 1315 }, |
4284 | | { PseudoVLSE64_V_M2, 1316 }, |
4285 | | { PseudoVLSE64_V_M4, 1317 }, |
4286 | | { PseudoVLSE64_V_M8, 1318 }, |
4287 | | { PseudoVLSE8_V_M1, 1319 }, |
4288 | | { PseudoVLSE8_V_M2, 1320 }, |
4289 | | { PseudoVLSE8_V_M4, 1321 }, |
4290 | | { PseudoVLSE8_V_M8, 1322 }, |
4291 | | { PseudoVLSE8_V_MF2, 1323 }, |
4292 | | { PseudoVLSE8_V_MF4, 1324 }, |
4293 | | { PseudoVLSE8_V_MF8, 1325 }, |
4294 | | { PseudoVLUXEI16_V_M1_M1, 1326 }, |
4295 | | { PseudoVLUXEI16_V_M1_M2, 1327 }, |
4296 | | { PseudoVLUXEI16_V_M1_M4, 1328 }, |
4297 | | { PseudoVLUXEI16_V_M1_MF2, 1329 }, |
4298 | | { PseudoVLUXEI16_V_M2_M1, 1330 }, |
4299 | | { PseudoVLUXEI16_V_M2_M2, 1331 }, |
4300 | | { PseudoVLUXEI16_V_M2_M4, 1332 }, |
4301 | | { PseudoVLUXEI16_V_M2_M8, 1333 }, |
4302 | | { PseudoVLUXEI16_V_M4_M2, 1334 }, |
4303 | | { PseudoVLUXEI16_V_M4_M4, 1335 }, |
4304 | | { PseudoVLUXEI16_V_M4_M8, 1336 }, |
4305 | | { PseudoVLUXEI16_V_M8_M4, 1337 }, |
4306 | | { PseudoVLUXEI16_V_M8_M8, 1338 }, |
4307 | | { PseudoVLUXEI16_V_MF2_M1, 1339 }, |
4308 | | { PseudoVLUXEI16_V_MF2_M2, 1340 }, |
4309 | | { PseudoVLUXEI16_V_MF2_MF2, 1341 }, |
4310 | | { PseudoVLUXEI16_V_MF2_MF4, 1342 }, |
4311 | | { PseudoVLUXEI16_V_MF4_M1, 1343 }, |
4312 | | { PseudoVLUXEI16_V_MF4_MF2, 1344 }, |
4313 | | { PseudoVLUXEI16_V_MF4_MF4, 1345 }, |
4314 | | { PseudoVLUXEI16_V_MF4_MF8, 1346 }, |
4315 | | { PseudoVLUXEI32_V_M1_M1, 1347 }, |
4316 | | { PseudoVLUXEI32_V_M1_M2, 1348 }, |
4317 | | { PseudoVLUXEI32_V_M1_MF2, 1349 }, |
4318 | | { PseudoVLUXEI32_V_M1_MF4, 1350 }, |
4319 | | { PseudoVLUXEI32_V_M2_M1, 1351 }, |
4320 | | { PseudoVLUXEI32_V_M2_M2, 1352 }, |
4321 | | { PseudoVLUXEI32_V_M2_M4, 1353 }, |
4322 | | { PseudoVLUXEI32_V_M2_MF2, 1354 }, |
4323 | | { PseudoVLUXEI32_V_M4_M1, 1355 }, |
4324 | | { PseudoVLUXEI32_V_M4_M2, 1356 }, |
4325 | | { PseudoVLUXEI32_V_M4_M4, 1357 }, |
4326 | | { PseudoVLUXEI32_V_M4_M8, 1358 }, |
4327 | | { PseudoVLUXEI32_V_M8_M2, 1359 }, |
4328 | | { PseudoVLUXEI32_V_M8_M4, 1360 }, |
4329 | | { PseudoVLUXEI32_V_M8_M8, 1361 }, |
4330 | | { PseudoVLUXEI32_V_MF2_M1, 1362 }, |
4331 | | { PseudoVLUXEI32_V_MF2_MF2, 1363 }, |
4332 | | { PseudoVLUXEI32_V_MF2_MF4, 1364 }, |
4333 | | { PseudoVLUXEI32_V_MF2_MF8, 1365 }, |
4334 | | { PseudoVLUXEI64_V_M1_M1, 1366 }, |
4335 | | { PseudoVLUXEI64_V_M1_MF2, 1367 }, |
4336 | | { PseudoVLUXEI64_V_M1_MF4, 1368 }, |
4337 | | { PseudoVLUXEI64_V_M1_MF8, 1369 }, |
4338 | | { PseudoVLUXEI64_V_M2_M1, 1370 }, |
4339 | | { PseudoVLUXEI64_V_M2_M2, 1371 }, |
4340 | | { PseudoVLUXEI64_V_M2_MF2, 1372 }, |
4341 | | { PseudoVLUXEI64_V_M2_MF4, 1373 }, |
4342 | | { PseudoVLUXEI64_V_M4_M1, 1374 }, |
4343 | | { PseudoVLUXEI64_V_M4_M2, 1375 }, |
4344 | | { PseudoVLUXEI64_V_M4_M4, 1376 }, |
4345 | | { PseudoVLUXEI64_V_M4_MF2, 1377 }, |
4346 | | { PseudoVLUXEI64_V_M8_M1, 1378 }, |
4347 | | { PseudoVLUXEI64_V_M8_M2, 1379 }, |
4348 | | { PseudoVLUXEI64_V_M8_M4, 1380 }, |
4349 | | { PseudoVLUXEI64_V_M8_M8, 1381 }, |
4350 | | { PseudoVLUXEI8_V_M1_M1, 1382 }, |
4351 | | { PseudoVLUXEI8_V_M1_M2, 1383 }, |
4352 | | { PseudoVLUXEI8_V_M1_M4, 1384 }, |
4353 | | { PseudoVLUXEI8_V_M1_M8, 1385 }, |
4354 | | { PseudoVLUXEI8_V_M2_M2, 1386 }, |
4355 | | { PseudoVLUXEI8_V_M2_M4, 1387 }, |
4356 | | { PseudoVLUXEI8_V_M2_M8, 1388 }, |
4357 | | { PseudoVLUXEI8_V_M4_M4, 1389 }, |
4358 | | { PseudoVLUXEI8_V_M4_M8, 1390 }, |
4359 | | { PseudoVLUXEI8_V_M8_M8, 1391 }, |
4360 | | { PseudoVLUXEI8_V_MF2_M1, 1392 }, |
4361 | | { PseudoVLUXEI8_V_MF2_M2, 1393 }, |
4362 | | { PseudoVLUXEI8_V_MF2_M4, 1394 }, |
4363 | | { PseudoVLUXEI8_V_MF2_MF2, 1395 }, |
4364 | | { PseudoVLUXEI8_V_MF4_M1, 1396 }, |
4365 | | { PseudoVLUXEI8_V_MF4_M2, 1397 }, |
4366 | | { PseudoVLUXEI8_V_MF4_MF2, 1398 }, |
4367 | | { PseudoVLUXEI8_V_MF4_MF4, 1399 }, |
4368 | | { PseudoVLUXEI8_V_MF8_M1, 1400 }, |
4369 | | { PseudoVLUXEI8_V_MF8_MF2, 1401 }, |
4370 | | { PseudoVLUXEI8_V_MF8_MF4, 1402 }, |
4371 | | { PseudoVLUXEI8_V_MF8_MF8, 1403 }, |
4372 | | { PseudoVMACC_VV_M1, 1404 }, |
4373 | | { PseudoVMACC_VV_M2, 1405 }, |
4374 | | { PseudoVMACC_VV_M4, 1406 }, |
4375 | | { PseudoVMACC_VV_M8, 1407 }, |
4376 | | { PseudoVMACC_VV_MF2, 1408 }, |
4377 | | { PseudoVMACC_VV_MF4, 1409 }, |
4378 | | { PseudoVMACC_VV_MF8, 1410 }, |
4379 | | { PseudoVMACC_VX_M1, 1411 }, |
4380 | | { PseudoVMACC_VX_M2, 1412 }, |
4381 | | { PseudoVMACC_VX_M4, 1413 }, |
4382 | | { PseudoVMACC_VX_M8, 1414 }, |
4383 | | { PseudoVMACC_VX_MF2, 1415 }, |
4384 | | { PseudoVMACC_VX_MF4, 1416 }, |
4385 | | { PseudoVMACC_VX_MF8, 1417 }, |
4386 | | { PseudoVMADD_VV_M1, 1418 }, |
4387 | | { PseudoVMADD_VV_M2, 1419 }, |
4388 | | { PseudoVMADD_VV_M4, 1420 }, |
4389 | | { PseudoVMADD_VV_M8, 1421 }, |
4390 | | { PseudoVMADD_VV_MF2, 1422 }, |
4391 | | { PseudoVMADD_VV_MF4, 1423 }, |
4392 | | { PseudoVMADD_VV_MF8, 1424 }, |
4393 | | { PseudoVMADD_VX_M1, 1425 }, |
4394 | | { PseudoVMADD_VX_M2, 1426 }, |
4395 | | { PseudoVMADD_VX_M4, 1427 }, |
4396 | | { PseudoVMADD_VX_M8, 1428 }, |
4397 | | { PseudoVMADD_VX_MF2, 1429 }, |
4398 | | { PseudoVMADD_VX_MF4, 1430 }, |
4399 | | { PseudoVMADD_VX_MF8, 1431 }, |
4400 | | { PseudoVMAXU_VV_M1, 1432 }, |
4401 | | { PseudoVMAXU_VV_M2, 1433 }, |
4402 | | { PseudoVMAXU_VV_M4, 1434 }, |
4403 | | { PseudoVMAXU_VV_M8, 1435 }, |
4404 | | { PseudoVMAXU_VV_MF2, 1436 }, |
4405 | | { PseudoVMAXU_VV_MF4, 1437 }, |
4406 | | { PseudoVMAXU_VV_MF8, 1438 }, |
4407 | | { PseudoVMAXU_VX_M1, 1439 }, |
4408 | | { PseudoVMAXU_VX_M2, 1440 }, |
4409 | | { PseudoVMAXU_VX_M4, 1441 }, |
4410 | | { PseudoVMAXU_VX_M8, 1442 }, |
4411 | | { PseudoVMAXU_VX_MF2, 1443 }, |
4412 | | { PseudoVMAXU_VX_MF4, 1444 }, |
4413 | | { PseudoVMAXU_VX_MF8, 1445 }, |
4414 | | { PseudoVMAX_VV_M1, 1446 }, |
4415 | | { PseudoVMAX_VV_M2, 1447 }, |
4416 | | { PseudoVMAX_VV_M4, 1448 }, |
4417 | | { PseudoVMAX_VV_M8, 1449 }, |
4418 | | { PseudoVMAX_VV_MF2, 1450 }, |
4419 | | { PseudoVMAX_VV_MF4, 1451 }, |
4420 | | { PseudoVMAX_VV_MF8, 1452 }, |
4421 | | { PseudoVMAX_VX_M1, 1453 }, |
4422 | | { PseudoVMAX_VX_M2, 1454 }, |
4423 | | { PseudoVMAX_VX_M4, 1455 }, |
4424 | | { PseudoVMAX_VX_M8, 1456 }, |
4425 | | { PseudoVMAX_VX_MF2, 1457 }, |
4426 | | { PseudoVMAX_VX_MF4, 1458 }, |
4427 | | { PseudoVMAX_VX_MF8, 1459 }, |
4428 | | { PseudoVMFEQ_VFPR16_M1, 1460 }, |
4429 | | { PseudoVMFEQ_VFPR16_M2, 1461 }, |
4430 | | { PseudoVMFEQ_VFPR16_M4, 1462 }, |
4431 | | { PseudoVMFEQ_VFPR16_M8, 1463 }, |
4432 | | { PseudoVMFEQ_VFPR16_MF2, 1464 }, |
4433 | | { PseudoVMFEQ_VFPR16_MF4, 1465 }, |
4434 | | { PseudoVMFEQ_VFPR32_M1, 1466 }, |
4435 | | { PseudoVMFEQ_VFPR32_M2, 1467 }, |
4436 | | { PseudoVMFEQ_VFPR32_M4, 1468 }, |
4437 | | { PseudoVMFEQ_VFPR32_M8, 1469 }, |
4438 | | { PseudoVMFEQ_VFPR32_MF2, 1470 }, |
4439 | | { PseudoVMFEQ_VFPR64_M1, 1471 }, |
4440 | | { PseudoVMFEQ_VFPR64_M2, 1472 }, |
4441 | | { PseudoVMFEQ_VFPR64_M4, 1473 }, |
4442 | | { PseudoVMFEQ_VFPR64_M8, 1474 }, |
4443 | | { PseudoVMFEQ_VV_M1, 1475 }, |
4444 | | { PseudoVMFEQ_VV_M2, 1476 }, |
4445 | | { PseudoVMFEQ_VV_M4, 1477 }, |
4446 | | { PseudoVMFEQ_VV_M8, 1478 }, |
4447 | | { PseudoVMFEQ_VV_MF2, 1479 }, |
4448 | | { PseudoVMFEQ_VV_MF4, 1480 }, |
4449 | | { PseudoVMFGE_VFPR16_M1, 1481 }, |
4450 | | { PseudoVMFGE_VFPR16_M2, 1482 }, |
4451 | | { PseudoVMFGE_VFPR16_M4, 1483 }, |
4452 | | { PseudoVMFGE_VFPR16_M8, 1484 }, |
4453 | | { PseudoVMFGE_VFPR16_MF2, 1485 }, |
4454 | | { PseudoVMFGE_VFPR16_MF4, 1486 }, |
4455 | | { PseudoVMFGE_VFPR32_M1, 1487 }, |
4456 | | { PseudoVMFGE_VFPR32_M2, 1488 }, |
4457 | | { PseudoVMFGE_VFPR32_M4, 1489 }, |
4458 | | { PseudoVMFGE_VFPR32_M8, 1490 }, |
4459 | | { PseudoVMFGE_VFPR32_MF2, 1491 }, |
4460 | | { PseudoVMFGE_VFPR64_M1, 1492 }, |
4461 | | { PseudoVMFGE_VFPR64_M2, 1493 }, |
4462 | | { PseudoVMFGE_VFPR64_M4, 1494 }, |
4463 | | { PseudoVMFGE_VFPR64_M8, 1495 }, |
4464 | | { PseudoVMFGT_VFPR16_M1, 1496 }, |
4465 | | { PseudoVMFGT_VFPR16_M2, 1497 }, |
4466 | | { PseudoVMFGT_VFPR16_M4, 1498 }, |
4467 | | { PseudoVMFGT_VFPR16_M8, 1499 }, |
4468 | | { PseudoVMFGT_VFPR16_MF2, 1500 }, |
4469 | | { PseudoVMFGT_VFPR16_MF4, 1501 }, |
4470 | | { PseudoVMFGT_VFPR32_M1, 1502 }, |
4471 | | { PseudoVMFGT_VFPR32_M2, 1503 }, |
4472 | | { PseudoVMFGT_VFPR32_M4, 1504 }, |
4473 | | { PseudoVMFGT_VFPR32_M8, 1505 }, |
4474 | | { PseudoVMFGT_VFPR32_MF2, 1506 }, |
4475 | | { PseudoVMFGT_VFPR64_M1, 1507 }, |
4476 | | { PseudoVMFGT_VFPR64_M2, 1508 }, |
4477 | | { PseudoVMFGT_VFPR64_M4, 1509 }, |
4478 | | { PseudoVMFGT_VFPR64_M8, 1510 }, |
4479 | | { PseudoVMFLE_VFPR16_M1, 1511 }, |
4480 | | { PseudoVMFLE_VFPR16_M2, 1512 }, |
4481 | | { PseudoVMFLE_VFPR16_M4, 1513 }, |
4482 | | { PseudoVMFLE_VFPR16_M8, 1514 }, |
4483 | | { PseudoVMFLE_VFPR16_MF2, 1515 }, |
4484 | | { PseudoVMFLE_VFPR16_MF4, 1516 }, |
4485 | | { PseudoVMFLE_VFPR32_M1, 1517 }, |
4486 | | { PseudoVMFLE_VFPR32_M2, 1518 }, |
4487 | | { PseudoVMFLE_VFPR32_M4, 1519 }, |
4488 | | { PseudoVMFLE_VFPR32_M8, 1520 }, |
4489 | | { PseudoVMFLE_VFPR32_MF2, 1521 }, |
4490 | | { PseudoVMFLE_VFPR64_M1, 1522 }, |
4491 | | { PseudoVMFLE_VFPR64_M2, 1523 }, |
4492 | | { PseudoVMFLE_VFPR64_M4, 1524 }, |
4493 | | { PseudoVMFLE_VFPR64_M8, 1525 }, |
4494 | | { PseudoVMFLE_VV_M1, 1526 }, |
4495 | | { PseudoVMFLE_VV_M2, 1527 }, |
4496 | | { PseudoVMFLE_VV_M4, 1528 }, |
4497 | | { PseudoVMFLE_VV_M8, 1529 }, |
4498 | | { PseudoVMFLE_VV_MF2, 1530 }, |
4499 | | { PseudoVMFLE_VV_MF4, 1531 }, |
4500 | | { PseudoVMFLT_VFPR16_M1, 1532 }, |
4501 | | { PseudoVMFLT_VFPR16_M2, 1533 }, |
4502 | | { PseudoVMFLT_VFPR16_M4, 1534 }, |
4503 | | { PseudoVMFLT_VFPR16_M8, 1535 }, |
4504 | | { PseudoVMFLT_VFPR16_MF2, 1536 }, |
4505 | | { PseudoVMFLT_VFPR16_MF4, 1537 }, |
4506 | | { PseudoVMFLT_VFPR32_M1, 1538 }, |
4507 | | { PseudoVMFLT_VFPR32_M2, 1539 }, |
4508 | | { PseudoVMFLT_VFPR32_M4, 1540 }, |
4509 | | { PseudoVMFLT_VFPR32_M8, 1541 }, |
4510 | | { PseudoVMFLT_VFPR32_MF2, 1542 }, |
4511 | | { PseudoVMFLT_VFPR64_M1, 1543 }, |
4512 | | { PseudoVMFLT_VFPR64_M2, 1544 }, |
4513 | | { PseudoVMFLT_VFPR64_M4, 1545 }, |
4514 | | { PseudoVMFLT_VFPR64_M8, 1546 }, |
4515 | | { PseudoVMFLT_VV_M1, 1547 }, |
4516 | | { PseudoVMFLT_VV_M2, 1548 }, |
4517 | | { PseudoVMFLT_VV_M4, 1549 }, |
4518 | | { PseudoVMFLT_VV_M8, 1550 }, |
4519 | | { PseudoVMFLT_VV_MF2, 1551 }, |
4520 | | { PseudoVMFLT_VV_MF4, 1552 }, |
4521 | | { PseudoVMFNE_VFPR16_M1, 1553 }, |
4522 | | { PseudoVMFNE_VFPR16_M2, 1554 }, |
4523 | | { PseudoVMFNE_VFPR16_M4, 1555 }, |
4524 | | { PseudoVMFNE_VFPR16_M8, 1556 }, |
4525 | | { PseudoVMFNE_VFPR16_MF2, 1557 }, |
4526 | | { PseudoVMFNE_VFPR16_MF4, 1558 }, |
4527 | | { PseudoVMFNE_VFPR32_M1, 1559 }, |
4528 | | { PseudoVMFNE_VFPR32_M2, 1560 }, |
4529 | | { PseudoVMFNE_VFPR32_M4, 1561 }, |
4530 | | { PseudoVMFNE_VFPR32_M8, 1562 }, |
4531 | | { PseudoVMFNE_VFPR32_MF2, 1563 }, |
4532 | | { PseudoVMFNE_VFPR64_M1, 1564 }, |
4533 | | { PseudoVMFNE_VFPR64_M2, 1565 }, |
4534 | | { PseudoVMFNE_VFPR64_M4, 1566 }, |
4535 | | { PseudoVMFNE_VFPR64_M8, 1567 }, |
4536 | | { PseudoVMFNE_VV_M1, 1568 }, |
4537 | | { PseudoVMFNE_VV_M2, 1569 }, |
4538 | | { PseudoVMFNE_VV_M4, 1570 }, |
4539 | | { PseudoVMFNE_VV_M8, 1571 }, |
4540 | | { PseudoVMFNE_VV_MF2, 1572 }, |
4541 | | { PseudoVMFNE_VV_MF4, 1573 }, |
4542 | | { PseudoVMINU_VV_M1, 1574 }, |
4543 | | { PseudoVMINU_VV_M2, 1575 }, |
4544 | | { PseudoVMINU_VV_M4, 1576 }, |
4545 | | { PseudoVMINU_VV_M8, 1577 }, |
4546 | | { PseudoVMINU_VV_MF2, 1578 }, |
4547 | | { PseudoVMINU_VV_MF4, 1579 }, |
4548 | | { PseudoVMINU_VV_MF8, 1580 }, |
4549 | | { PseudoVMINU_VX_M1, 1581 }, |
4550 | | { PseudoVMINU_VX_M2, 1582 }, |
4551 | | { PseudoVMINU_VX_M4, 1583 }, |
4552 | | { PseudoVMINU_VX_M8, 1584 }, |
4553 | | { PseudoVMINU_VX_MF2, 1585 }, |
4554 | | { PseudoVMINU_VX_MF4, 1586 }, |
4555 | | { PseudoVMINU_VX_MF8, 1587 }, |
4556 | | { PseudoVMIN_VV_M1, 1588 }, |
4557 | | { PseudoVMIN_VV_M2, 1589 }, |
4558 | | { PseudoVMIN_VV_M4, 1590 }, |
4559 | | { PseudoVMIN_VV_M8, 1591 }, |
4560 | | { PseudoVMIN_VV_MF2, 1592 }, |
4561 | | { PseudoVMIN_VV_MF4, 1593 }, |
4562 | | { PseudoVMIN_VV_MF8, 1594 }, |
4563 | | { PseudoVMIN_VX_M1, 1595 }, |
4564 | | { PseudoVMIN_VX_M2, 1596 }, |
4565 | | { PseudoVMIN_VX_M4, 1597 }, |
4566 | | { PseudoVMIN_VX_M8, 1598 }, |
4567 | | { PseudoVMIN_VX_MF2, 1599 }, |
4568 | | { PseudoVMIN_VX_MF4, 1600 }, |
4569 | | { PseudoVMIN_VX_MF8, 1601 }, |
4570 | | { PseudoVMSEQ_VI_M1, 1602 }, |
4571 | | { PseudoVMSEQ_VI_M2, 1603 }, |
4572 | | { PseudoVMSEQ_VI_M4, 1604 }, |
4573 | | { PseudoVMSEQ_VI_M8, 1605 }, |
4574 | | { PseudoVMSEQ_VI_MF2, 1606 }, |
4575 | | { PseudoVMSEQ_VI_MF4, 1607 }, |
4576 | | { PseudoVMSEQ_VI_MF8, 1608 }, |
4577 | | { PseudoVMSEQ_VV_M1, 1609 }, |
4578 | | { PseudoVMSEQ_VV_M2, 1610 }, |
4579 | | { PseudoVMSEQ_VV_M4, 1611 }, |
4580 | | { PseudoVMSEQ_VV_M8, 1612 }, |
4581 | | { PseudoVMSEQ_VV_MF2, 1613 }, |
4582 | | { PseudoVMSEQ_VV_MF4, 1614 }, |
4583 | | { PseudoVMSEQ_VV_MF8, 1615 }, |
4584 | | { PseudoVMSEQ_VX_M1, 1616 }, |
4585 | | { PseudoVMSEQ_VX_M2, 1617 }, |
4586 | | { PseudoVMSEQ_VX_M4, 1618 }, |
4587 | | { PseudoVMSEQ_VX_M8, 1619 }, |
4588 | | { PseudoVMSEQ_VX_MF2, 1620 }, |
4589 | | { PseudoVMSEQ_VX_MF4, 1621 }, |
4590 | | { PseudoVMSEQ_VX_MF8, 1622 }, |
4591 | | { PseudoVMSGTU_VI_M1, 1623 }, |
4592 | | { PseudoVMSGTU_VI_M2, 1624 }, |
4593 | | { PseudoVMSGTU_VI_M4, 1625 }, |
4594 | | { PseudoVMSGTU_VI_M8, 1626 }, |
4595 | | { PseudoVMSGTU_VI_MF2, 1627 }, |
4596 | | { PseudoVMSGTU_VI_MF4, 1628 }, |
4597 | | { PseudoVMSGTU_VI_MF8, 1629 }, |
4598 | | { PseudoVMSGTU_VX_M1, 1630 }, |
4599 | | { PseudoVMSGTU_VX_M2, 1631 }, |
4600 | | { PseudoVMSGTU_VX_M4, 1632 }, |
4601 | | { PseudoVMSGTU_VX_M8, 1633 }, |
4602 | | { PseudoVMSGTU_VX_MF2, 1634 }, |
4603 | | { PseudoVMSGTU_VX_MF4, 1635 }, |
4604 | | { PseudoVMSGTU_VX_MF8, 1636 }, |
4605 | | { PseudoVMSGT_VI_M1, 1637 }, |
4606 | | { PseudoVMSGT_VI_M2, 1638 }, |
4607 | | { PseudoVMSGT_VI_M4, 1639 }, |
4608 | | { PseudoVMSGT_VI_M8, 1640 }, |
4609 | | { PseudoVMSGT_VI_MF2, 1641 }, |
4610 | | { PseudoVMSGT_VI_MF4, 1642 }, |
4611 | | { PseudoVMSGT_VI_MF8, 1643 }, |
4612 | | { PseudoVMSGT_VX_M1, 1644 }, |
4613 | | { PseudoVMSGT_VX_M2, 1645 }, |
4614 | | { PseudoVMSGT_VX_M4, 1646 }, |
4615 | | { PseudoVMSGT_VX_M8, 1647 }, |
4616 | | { PseudoVMSGT_VX_MF2, 1648 }, |
4617 | | { PseudoVMSGT_VX_MF4, 1649 }, |
4618 | | { PseudoVMSGT_VX_MF8, 1650 }, |
4619 | | { PseudoVMSLEU_VI_M1, 1651 }, |
4620 | | { PseudoVMSLEU_VI_M2, 1652 }, |
4621 | | { PseudoVMSLEU_VI_M4, 1653 }, |
4622 | | { PseudoVMSLEU_VI_M8, 1654 }, |
4623 | | { PseudoVMSLEU_VI_MF2, 1655 }, |
4624 | | { PseudoVMSLEU_VI_MF4, 1656 }, |
4625 | | { PseudoVMSLEU_VI_MF8, 1657 }, |
4626 | | { PseudoVMSLEU_VV_M1, 1658 }, |
4627 | | { PseudoVMSLEU_VV_M2, 1659 }, |
4628 | | { PseudoVMSLEU_VV_M4, 1660 }, |
4629 | | { PseudoVMSLEU_VV_M8, 1661 }, |
4630 | | { PseudoVMSLEU_VV_MF2, 1662 }, |
4631 | | { PseudoVMSLEU_VV_MF4, 1663 }, |
4632 | | { PseudoVMSLEU_VV_MF8, 1664 }, |
4633 | | { PseudoVMSLEU_VX_M1, 1665 }, |
4634 | | { PseudoVMSLEU_VX_M2, 1666 }, |
4635 | | { PseudoVMSLEU_VX_M4, 1667 }, |
4636 | | { PseudoVMSLEU_VX_M8, 1668 }, |
4637 | | { PseudoVMSLEU_VX_MF2, 1669 }, |
4638 | | { PseudoVMSLEU_VX_MF4, 1670 }, |
4639 | | { PseudoVMSLEU_VX_MF8, 1671 }, |
4640 | | { PseudoVMSLE_VI_M1, 1672 }, |
4641 | | { PseudoVMSLE_VI_M2, 1673 }, |
4642 | | { PseudoVMSLE_VI_M4, 1674 }, |
4643 | | { PseudoVMSLE_VI_M8, 1675 }, |
4644 | | { PseudoVMSLE_VI_MF2, 1676 }, |
4645 | | { PseudoVMSLE_VI_MF4, 1677 }, |
4646 | | { PseudoVMSLE_VI_MF8, 1678 }, |
4647 | | { PseudoVMSLE_VV_M1, 1679 }, |
4648 | | { PseudoVMSLE_VV_M2, 1680 }, |
4649 | | { PseudoVMSLE_VV_M4, 1681 }, |
4650 | | { PseudoVMSLE_VV_M8, 1682 }, |
4651 | | { PseudoVMSLE_VV_MF2, 1683 }, |
4652 | | { PseudoVMSLE_VV_MF4, 1684 }, |
4653 | | { PseudoVMSLE_VV_MF8, 1685 }, |
4654 | | { PseudoVMSLE_VX_M1, 1686 }, |
4655 | | { PseudoVMSLE_VX_M2, 1687 }, |
4656 | | { PseudoVMSLE_VX_M4, 1688 }, |
4657 | | { PseudoVMSLE_VX_M8, 1689 }, |
4658 | | { PseudoVMSLE_VX_MF2, 1690 }, |
4659 | | { PseudoVMSLE_VX_MF4, 1691 }, |
4660 | | { PseudoVMSLE_VX_MF8, 1692 }, |
4661 | | { PseudoVMSLTU_VV_M1, 1693 }, |
4662 | | { PseudoVMSLTU_VV_M2, 1694 }, |
4663 | | { PseudoVMSLTU_VV_M4, 1695 }, |
4664 | | { PseudoVMSLTU_VV_M8, 1696 }, |
4665 | | { PseudoVMSLTU_VV_MF2, 1697 }, |
4666 | | { PseudoVMSLTU_VV_MF4, 1698 }, |
4667 | | { PseudoVMSLTU_VV_MF8, 1699 }, |
4668 | | { PseudoVMSLTU_VX_M1, 1700 }, |
4669 | | { PseudoVMSLTU_VX_M2, 1701 }, |
4670 | | { PseudoVMSLTU_VX_M4, 1702 }, |
4671 | | { PseudoVMSLTU_VX_M8, 1703 }, |
4672 | | { PseudoVMSLTU_VX_MF2, 1704 }, |
4673 | | { PseudoVMSLTU_VX_MF4, 1705 }, |
4674 | | { PseudoVMSLTU_VX_MF8, 1706 }, |
4675 | | { PseudoVMSLT_VV_M1, 1707 }, |
4676 | | { PseudoVMSLT_VV_M2, 1708 }, |
4677 | | { PseudoVMSLT_VV_M4, 1709 }, |
4678 | | { PseudoVMSLT_VV_M8, 1710 }, |
4679 | | { PseudoVMSLT_VV_MF2, 1711 }, |
4680 | | { PseudoVMSLT_VV_MF4, 1712 }, |
4681 | | { PseudoVMSLT_VV_MF8, 1713 }, |
4682 | | { PseudoVMSLT_VX_M1, 1714 }, |
4683 | | { PseudoVMSLT_VX_M2, 1715 }, |
4684 | | { PseudoVMSLT_VX_M4, 1716 }, |
4685 | | { PseudoVMSLT_VX_M8, 1717 }, |
4686 | | { PseudoVMSLT_VX_MF2, 1718 }, |
4687 | | { PseudoVMSLT_VX_MF4, 1719 }, |
4688 | | { PseudoVMSLT_VX_MF8, 1720 }, |
4689 | | { PseudoVMSNE_VI_M1, 1721 }, |
4690 | | { PseudoVMSNE_VI_M2, 1722 }, |
4691 | | { PseudoVMSNE_VI_M4, 1723 }, |
4692 | | { PseudoVMSNE_VI_M8, 1724 }, |
4693 | | { PseudoVMSNE_VI_MF2, 1725 }, |
4694 | | { PseudoVMSNE_VI_MF4, 1726 }, |
4695 | | { PseudoVMSNE_VI_MF8, 1727 }, |
4696 | | { PseudoVMSNE_VV_M1, 1728 }, |
4697 | | { PseudoVMSNE_VV_M2, 1729 }, |
4698 | | { PseudoVMSNE_VV_M4, 1730 }, |
4699 | | { PseudoVMSNE_VV_M8, 1731 }, |
4700 | | { PseudoVMSNE_VV_MF2, 1732 }, |
4701 | | { PseudoVMSNE_VV_MF4, 1733 }, |
4702 | | { PseudoVMSNE_VV_MF8, 1734 }, |
4703 | | { PseudoVMSNE_VX_M1, 1735 }, |
4704 | | { PseudoVMSNE_VX_M2, 1736 }, |
4705 | | { PseudoVMSNE_VX_M4, 1737 }, |
4706 | | { PseudoVMSNE_VX_M8, 1738 }, |
4707 | | { PseudoVMSNE_VX_MF2, 1739 }, |
4708 | | { PseudoVMSNE_VX_MF4, 1740 }, |
4709 | | { PseudoVMSNE_VX_MF8, 1741 }, |
4710 | | { PseudoVMULHSU_VV_M1, 1742 }, |
4711 | | { PseudoVMULHSU_VV_M2, 1743 }, |
4712 | | { PseudoVMULHSU_VV_M4, 1744 }, |
4713 | | { PseudoVMULHSU_VV_M8, 1745 }, |
4714 | | { PseudoVMULHSU_VV_MF2, 1746 }, |
4715 | | { PseudoVMULHSU_VV_MF4, 1747 }, |
4716 | | { PseudoVMULHSU_VV_MF8, 1748 }, |
4717 | | { PseudoVMULHSU_VX_M1, 1749 }, |
4718 | | { PseudoVMULHSU_VX_M2, 1750 }, |
4719 | | { PseudoVMULHSU_VX_M4, 1751 }, |
4720 | | { PseudoVMULHSU_VX_M8, 1752 }, |
4721 | | { PseudoVMULHSU_VX_MF2, 1753 }, |
4722 | | { PseudoVMULHSU_VX_MF4, 1754 }, |
4723 | | { PseudoVMULHSU_VX_MF8, 1755 }, |
4724 | | { PseudoVMULHU_VV_M1, 1756 }, |
4725 | | { PseudoVMULHU_VV_M2, 1757 }, |
4726 | | { PseudoVMULHU_VV_M4, 1758 }, |
4727 | | { PseudoVMULHU_VV_M8, 1759 }, |
4728 | | { PseudoVMULHU_VV_MF2, 1760 }, |
4729 | | { PseudoVMULHU_VV_MF4, 1761 }, |
4730 | | { PseudoVMULHU_VV_MF8, 1762 }, |
4731 | | { PseudoVMULHU_VX_M1, 1763 }, |
4732 | | { PseudoVMULHU_VX_M2, 1764 }, |
4733 | | { PseudoVMULHU_VX_M4, 1765 }, |
4734 | | { PseudoVMULHU_VX_M8, 1766 }, |
4735 | | { PseudoVMULHU_VX_MF2, 1767 }, |
4736 | | { PseudoVMULHU_VX_MF4, 1768 }, |
4737 | | { PseudoVMULHU_VX_MF8, 1769 }, |
4738 | | { PseudoVMULH_VV_M1, 1770 }, |
4739 | | { PseudoVMULH_VV_M2, 1771 }, |
4740 | | { PseudoVMULH_VV_M4, 1772 }, |
4741 | | { PseudoVMULH_VV_M8, 1773 }, |
4742 | | { PseudoVMULH_VV_MF2, 1774 }, |
4743 | | { PseudoVMULH_VV_MF4, 1775 }, |
4744 | | { PseudoVMULH_VV_MF8, 1776 }, |
4745 | | { PseudoVMULH_VX_M1, 1777 }, |
4746 | | { PseudoVMULH_VX_M2, 1778 }, |
4747 | | { PseudoVMULH_VX_M4, 1779 }, |
4748 | | { PseudoVMULH_VX_M8, 1780 }, |
4749 | | { PseudoVMULH_VX_MF2, 1781 }, |
4750 | | { PseudoVMULH_VX_MF4, 1782 }, |
4751 | | { PseudoVMULH_VX_MF8, 1783 }, |
4752 | | { PseudoVMUL_VV_M1, 1784 }, |
4753 | | { PseudoVMUL_VV_M2, 1785 }, |
4754 | | { PseudoVMUL_VV_M4, 1786 }, |
4755 | | { PseudoVMUL_VV_M8, 1787 }, |
4756 | | { PseudoVMUL_VV_MF2, 1788 }, |
4757 | | { PseudoVMUL_VV_MF4, 1789 }, |
4758 | | { PseudoVMUL_VV_MF8, 1790 }, |
4759 | | { PseudoVMUL_VX_M1, 1791 }, |
4760 | | { PseudoVMUL_VX_M2, 1792 }, |
4761 | | { PseudoVMUL_VX_M4, 1793 }, |
4762 | | { PseudoVMUL_VX_M8, 1794 }, |
4763 | | { PseudoVMUL_VX_MF2, 1795 }, |
4764 | | { PseudoVMUL_VX_MF4, 1796 }, |
4765 | | { PseudoVMUL_VX_MF8, 1797 }, |
4766 | | { PseudoVNCLIPU_WI_M1, 1798 }, |
4767 | | { PseudoVNCLIPU_WI_M2, 1799 }, |
4768 | | { PseudoVNCLIPU_WI_M4, 1800 }, |
4769 | | { PseudoVNCLIPU_WI_MF2, 1801 }, |
4770 | | { PseudoVNCLIPU_WI_MF4, 1802 }, |
4771 | | { PseudoVNCLIPU_WI_MF8, 1803 }, |
4772 | | { PseudoVNCLIPU_WV_M1, 1804 }, |
4773 | | { PseudoVNCLIPU_WV_M2, 1805 }, |
4774 | | { PseudoVNCLIPU_WV_M4, 1806 }, |
4775 | | { PseudoVNCLIPU_WV_MF2, 1807 }, |
4776 | | { PseudoVNCLIPU_WV_MF4, 1808 }, |
4777 | | { PseudoVNCLIPU_WV_MF8, 1809 }, |
4778 | | { PseudoVNCLIPU_WX_M1, 1810 }, |
4779 | | { PseudoVNCLIPU_WX_M2, 1811 }, |
4780 | | { PseudoVNCLIPU_WX_M4, 1812 }, |
4781 | | { PseudoVNCLIPU_WX_MF2, 1813 }, |
4782 | | { PseudoVNCLIPU_WX_MF4, 1814 }, |
4783 | | { PseudoVNCLIPU_WX_MF8, 1815 }, |
4784 | | { PseudoVNCLIP_WI_M1, 1816 }, |
4785 | | { PseudoVNCLIP_WI_M2, 1817 }, |
4786 | | { PseudoVNCLIP_WI_M4, 1818 }, |
4787 | | { PseudoVNCLIP_WI_MF2, 1819 }, |
4788 | | { PseudoVNCLIP_WI_MF4, 1820 }, |
4789 | | { PseudoVNCLIP_WI_MF8, 1821 }, |
4790 | | { PseudoVNCLIP_WV_M1, 1822 }, |
4791 | | { PseudoVNCLIP_WV_M2, 1823 }, |
4792 | | { PseudoVNCLIP_WV_M4, 1824 }, |
4793 | | { PseudoVNCLIP_WV_MF2, 1825 }, |
4794 | | { PseudoVNCLIP_WV_MF4, 1826 }, |
4795 | | { PseudoVNCLIP_WV_MF8, 1827 }, |
4796 | | { PseudoVNCLIP_WX_M1, 1828 }, |
4797 | | { PseudoVNCLIP_WX_M2, 1829 }, |
4798 | | { PseudoVNCLIP_WX_M4, 1830 }, |
4799 | | { PseudoVNCLIP_WX_MF2, 1831 }, |
4800 | | { PseudoVNCLIP_WX_MF4, 1832 }, |
4801 | | { PseudoVNCLIP_WX_MF8, 1833 }, |
4802 | | { PseudoVNMSAC_VV_M1, 1834 }, |
4803 | | { PseudoVNMSAC_VV_M2, 1835 }, |
4804 | | { PseudoVNMSAC_VV_M4, 1836 }, |
4805 | | { PseudoVNMSAC_VV_M8, 1837 }, |
4806 | | { PseudoVNMSAC_VV_MF2, 1838 }, |
4807 | | { PseudoVNMSAC_VV_MF4, 1839 }, |
4808 | | { PseudoVNMSAC_VV_MF8, 1840 }, |
4809 | | { PseudoVNMSAC_VX_M1, 1841 }, |
4810 | | { PseudoVNMSAC_VX_M2, 1842 }, |
4811 | | { PseudoVNMSAC_VX_M4, 1843 }, |
4812 | | { PseudoVNMSAC_VX_M8, 1844 }, |
4813 | | { PseudoVNMSAC_VX_MF2, 1845 }, |
4814 | | { PseudoVNMSAC_VX_MF4, 1846 }, |
4815 | | { PseudoVNMSAC_VX_MF8, 1847 }, |
4816 | | { PseudoVNMSUB_VV_M1, 1848 }, |
4817 | | { PseudoVNMSUB_VV_M2, 1849 }, |
4818 | | { PseudoVNMSUB_VV_M4, 1850 }, |
4819 | | { PseudoVNMSUB_VV_M8, 1851 }, |
4820 | | { PseudoVNMSUB_VV_MF2, 1852 }, |
4821 | | { PseudoVNMSUB_VV_MF4, 1853 }, |
4822 | | { PseudoVNMSUB_VV_MF8, 1854 }, |
4823 | | { PseudoVNMSUB_VX_M1, 1855 }, |
4824 | | { PseudoVNMSUB_VX_M2, 1856 }, |
4825 | | { PseudoVNMSUB_VX_M4, 1857 }, |
4826 | | { PseudoVNMSUB_VX_M8, 1858 }, |
4827 | | { PseudoVNMSUB_VX_MF2, 1859 }, |
4828 | | { PseudoVNMSUB_VX_MF4, 1860 }, |
4829 | | { PseudoVNMSUB_VX_MF8, 1861 }, |
4830 | | { PseudoVNSRA_WI_M1, 1862 }, |
4831 | | { PseudoVNSRA_WI_M2, 1863 }, |
4832 | | { PseudoVNSRA_WI_M4, 1864 }, |
4833 | | { PseudoVNSRA_WI_MF2, 1865 }, |
4834 | | { PseudoVNSRA_WI_MF4, 1866 }, |
4835 | | { PseudoVNSRA_WI_MF8, 1867 }, |
4836 | | { PseudoVNSRA_WV_M1, 1868 }, |
4837 | | { PseudoVNSRA_WV_M2, 1869 }, |
4838 | | { PseudoVNSRA_WV_M4, 1870 }, |
4839 | | { PseudoVNSRA_WV_MF2, 1871 }, |
4840 | | { PseudoVNSRA_WV_MF4, 1872 }, |
4841 | | { PseudoVNSRA_WV_MF8, 1873 }, |
4842 | | { PseudoVNSRA_WX_M1, 1874 }, |
4843 | | { PseudoVNSRA_WX_M2, 1875 }, |
4844 | | { PseudoVNSRA_WX_M4, 1876 }, |
4845 | | { PseudoVNSRA_WX_MF2, 1877 }, |
4846 | | { PseudoVNSRA_WX_MF4, 1878 }, |
4847 | | { PseudoVNSRA_WX_MF8, 1879 }, |
4848 | | { PseudoVNSRL_WI_M1, 1880 }, |
4849 | | { PseudoVNSRL_WI_M2, 1881 }, |
4850 | | { PseudoVNSRL_WI_M4, 1882 }, |
4851 | | { PseudoVNSRL_WI_MF2, 1883 }, |
4852 | | { PseudoVNSRL_WI_MF4, 1884 }, |
4853 | | { PseudoVNSRL_WI_MF8, 1885 }, |
4854 | | { PseudoVNSRL_WV_M1, 1886 }, |
4855 | | { PseudoVNSRL_WV_M2, 1887 }, |
4856 | | { PseudoVNSRL_WV_M4, 1888 }, |
4857 | | { PseudoVNSRL_WV_MF2, 1889 }, |
4858 | | { PseudoVNSRL_WV_MF4, 1890 }, |
4859 | | { PseudoVNSRL_WV_MF8, 1891 }, |
4860 | | { PseudoVNSRL_WX_M1, 1892 }, |
4861 | | { PseudoVNSRL_WX_M2, 1893 }, |
4862 | | { PseudoVNSRL_WX_M4, 1894 }, |
4863 | | { PseudoVNSRL_WX_MF2, 1895 }, |
4864 | | { PseudoVNSRL_WX_MF4, 1896 }, |
4865 | | { PseudoVNSRL_WX_MF8, 1897 }, |
4866 | | { PseudoVOR_VI_M1, 1898 }, |
4867 | | { PseudoVOR_VI_M2, 1899 }, |
4868 | | { PseudoVOR_VI_M4, 1900 }, |
4869 | | { PseudoVOR_VI_M8, 1901 }, |
4870 | | { PseudoVOR_VI_MF2, 1902 }, |
4871 | | { PseudoVOR_VI_MF4, 1903 }, |
4872 | | { PseudoVOR_VI_MF8, 1904 }, |
4873 | | { PseudoVOR_VV_M1, 1905 }, |
4874 | | { PseudoVOR_VV_M2, 1906 }, |
4875 | | { PseudoVOR_VV_M4, 1907 }, |
4876 | | { PseudoVOR_VV_M8, 1908 }, |
4877 | | { PseudoVOR_VV_MF2, 1909 }, |
4878 | | { PseudoVOR_VV_MF4, 1910 }, |
4879 | | { PseudoVOR_VV_MF8, 1911 }, |
4880 | | { PseudoVOR_VX_M1, 1912 }, |
4881 | | { PseudoVOR_VX_M2, 1913 }, |
4882 | | { PseudoVOR_VX_M4, 1914 }, |
4883 | | { PseudoVOR_VX_M8, 1915 }, |
4884 | | { PseudoVOR_VX_MF2, 1916 }, |
4885 | | { PseudoVOR_VX_MF4, 1917 }, |
4886 | | { PseudoVOR_VX_MF8, 1918 }, |
4887 | | { PseudoVREDAND_VS_M1_E16, 1919 }, |
4888 | | { PseudoVREDAND_VS_M1_E32, 1920 }, |
4889 | | { PseudoVREDAND_VS_M1_E64, 1921 }, |
4890 | | { PseudoVREDAND_VS_M1_E8, 1922 }, |
4891 | | { PseudoVREDAND_VS_M2_E16, 1923 }, |
4892 | | { PseudoVREDAND_VS_M2_E32, 1924 }, |
4893 | | { PseudoVREDAND_VS_M2_E64, 1925 }, |
4894 | | { PseudoVREDAND_VS_M2_E8, 1926 }, |
4895 | | { PseudoVREDAND_VS_M4_E16, 1927 }, |
4896 | | { PseudoVREDAND_VS_M4_E32, 1928 }, |
4897 | | { PseudoVREDAND_VS_M4_E64, 1929 }, |
4898 | | { PseudoVREDAND_VS_M4_E8, 1930 }, |
4899 | | { PseudoVREDAND_VS_M8_E16, 1931 }, |
4900 | | { PseudoVREDAND_VS_M8_E32, 1932 }, |
4901 | | { PseudoVREDAND_VS_M8_E64, 1933 }, |
4902 | | { PseudoVREDAND_VS_M8_E8, 1934 }, |
4903 | | { PseudoVREDAND_VS_MF2_E16, 1935 }, |
4904 | | { PseudoVREDAND_VS_MF2_E32, 1936 }, |
4905 | | { PseudoVREDAND_VS_MF2_E8, 1937 }, |
4906 | | { PseudoVREDAND_VS_MF4_E16, 1938 }, |
4907 | | { PseudoVREDAND_VS_MF4_E8, 1939 }, |
4908 | | { PseudoVREDAND_VS_MF8_E8, 1940 }, |
4909 | | { PseudoVREDMAXU_VS_M1_E16, 1941 }, |
4910 | | { PseudoVREDMAXU_VS_M1_E32, 1942 }, |
4911 | | { PseudoVREDMAXU_VS_M1_E64, 1943 }, |
4912 | | { PseudoVREDMAXU_VS_M1_E8, 1944 }, |
4913 | | { PseudoVREDMAXU_VS_M2_E16, 1945 }, |
4914 | | { PseudoVREDMAXU_VS_M2_E32, 1946 }, |
4915 | | { PseudoVREDMAXU_VS_M2_E64, 1947 }, |
4916 | | { PseudoVREDMAXU_VS_M2_E8, 1948 }, |
4917 | | { PseudoVREDMAXU_VS_M4_E16, 1949 }, |
4918 | | { PseudoVREDMAXU_VS_M4_E32, 1950 }, |
4919 | | { PseudoVREDMAXU_VS_M4_E64, 1951 }, |
4920 | | { PseudoVREDMAXU_VS_M4_E8, 1952 }, |
4921 | | { PseudoVREDMAXU_VS_M8_E16, 1953 }, |
4922 | | { PseudoVREDMAXU_VS_M8_E32, 1954 }, |
4923 | | { PseudoVREDMAXU_VS_M8_E64, 1955 }, |
4924 | | { PseudoVREDMAXU_VS_M8_E8, 1956 }, |
4925 | | { PseudoVREDMAXU_VS_MF2_E16, 1957 }, |
4926 | | { PseudoVREDMAXU_VS_MF2_E32, 1958 }, |
4927 | | { PseudoVREDMAXU_VS_MF2_E8, 1959 }, |
4928 | | { PseudoVREDMAXU_VS_MF4_E16, 1960 }, |
4929 | | { PseudoVREDMAXU_VS_MF4_E8, 1961 }, |
4930 | | { PseudoVREDMAXU_VS_MF8_E8, 1962 }, |
4931 | | { PseudoVREDMAX_VS_M1_E16, 1963 }, |
4932 | | { PseudoVREDMAX_VS_M1_E32, 1964 }, |
4933 | | { PseudoVREDMAX_VS_M1_E64, 1965 }, |
4934 | | { PseudoVREDMAX_VS_M1_E8, 1966 }, |
4935 | | { PseudoVREDMAX_VS_M2_E16, 1967 }, |
4936 | | { PseudoVREDMAX_VS_M2_E32, 1968 }, |
4937 | | { PseudoVREDMAX_VS_M2_E64, 1969 }, |
4938 | | { PseudoVREDMAX_VS_M2_E8, 1970 }, |
4939 | | { PseudoVREDMAX_VS_M4_E16, 1971 }, |
4940 | | { PseudoVREDMAX_VS_M4_E32, 1972 }, |
4941 | | { PseudoVREDMAX_VS_M4_E64, 1973 }, |
4942 | | { PseudoVREDMAX_VS_M4_E8, 1974 }, |
4943 | | { PseudoVREDMAX_VS_M8_E16, 1975 }, |
4944 | | { PseudoVREDMAX_VS_M8_E32, 1976 }, |
4945 | | { PseudoVREDMAX_VS_M8_E64, 1977 }, |
4946 | | { PseudoVREDMAX_VS_M8_E8, 1978 }, |
4947 | | { PseudoVREDMAX_VS_MF2_E16, 1979 }, |
4948 | | { PseudoVREDMAX_VS_MF2_E32, 1980 }, |
4949 | | { PseudoVREDMAX_VS_MF2_E8, 1981 }, |
4950 | | { PseudoVREDMAX_VS_MF4_E16, 1982 }, |
4951 | | { PseudoVREDMAX_VS_MF4_E8, 1983 }, |
4952 | | { PseudoVREDMAX_VS_MF8_E8, 1984 }, |
4953 | | { PseudoVREDMINU_VS_M1_E16, 1985 }, |
4954 | | { PseudoVREDMINU_VS_M1_E32, 1986 }, |
4955 | | { PseudoVREDMINU_VS_M1_E64, 1987 }, |
4956 | | { PseudoVREDMINU_VS_M1_E8, 1988 }, |
4957 | | { PseudoVREDMINU_VS_M2_E16, 1989 }, |
4958 | | { PseudoVREDMINU_VS_M2_E32, 1990 }, |
4959 | | { PseudoVREDMINU_VS_M2_E64, 1991 }, |
4960 | | { PseudoVREDMINU_VS_M2_E8, 1992 }, |
4961 | | { PseudoVREDMINU_VS_M4_E16, 1993 }, |
4962 | | { PseudoVREDMINU_VS_M4_E32, 1994 }, |
4963 | | { PseudoVREDMINU_VS_M4_E64, 1995 }, |
4964 | | { PseudoVREDMINU_VS_M4_E8, 1996 }, |
4965 | | { PseudoVREDMINU_VS_M8_E16, 1997 }, |
4966 | | { PseudoVREDMINU_VS_M8_E32, 1998 }, |
4967 | | { PseudoVREDMINU_VS_M8_E64, 1999 }, |
4968 | | { PseudoVREDMINU_VS_M8_E8, 2000 }, |
4969 | | { PseudoVREDMINU_VS_MF2_E16, 2001 }, |
4970 | | { PseudoVREDMINU_VS_MF2_E32, 2002 }, |
4971 | | { PseudoVREDMINU_VS_MF2_E8, 2003 }, |
4972 | | { PseudoVREDMINU_VS_MF4_E16, 2004 }, |
4973 | | { PseudoVREDMINU_VS_MF4_E8, 2005 }, |
4974 | | { PseudoVREDMINU_VS_MF8_E8, 2006 }, |
4975 | | { PseudoVREDMIN_VS_M1_E16, 2007 }, |
4976 | | { PseudoVREDMIN_VS_M1_E32, 2008 }, |
4977 | | { PseudoVREDMIN_VS_M1_E64, 2009 }, |
4978 | | { PseudoVREDMIN_VS_M1_E8, 2010 }, |
4979 | | { PseudoVREDMIN_VS_M2_E16, 2011 }, |
4980 | | { PseudoVREDMIN_VS_M2_E32, 2012 }, |
4981 | | { PseudoVREDMIN_VS_M2_E64, 2013 }, |
4982 | | { PseudoVREDMIN_VS_M2_E8, 2014 }, |
4983 | | { PseudoVREDMIN_VS_M4_E16, 2015 }, |
4984 | | { PseudoVREDMIN_VS_M4_E32, 2016 }, |
4985 | | { PseudoVREDMIN_VS_M4_E64, 2017 }, |
4986 | | { PseudoVREDMIN_VS_M4_E8, 2018 }, |
4987 | | { PseudoVREDMIN_VS_M8_E16, 2019 }, |
4988 | | { PseudoVREDMIN_VS_M8_E32, 2020 }, |
4989 | | { PseudoVREDMIN_VS_M8_E64, 2021 }, |
4990 | | { PseudoVREDMIN_VS_M8_E8, 2022 }, |
4991 | | { PseudoVREDMIN_VS_MF2_E16, 2023 }, |
4992 | | { PseudoVREDMIN_VS_MF2_E32, 2024 }, |
4993 | | { PseudoVREDMIN_VS_MF2_E8, 2025 }, |
4994 | | { PseudoVREDMIN_VS_MF4_E16, 2026 }, |
4995 | | { PseudoVREDMIN_VS_MF4_E8, 2027 }, |
4996 | | { PseudoVREDMIN_VS_MF8_E8, 2028 }, |
4997 | | { PseudoVREDOR_VS_M1_E16, 2029 }, |
4998 | | { PseudoVREDOR_VS_M1_E32, 2030 }, |
4999 | | { PseudoVREDOR_VS_M1_E64, 2031 }, |
5000 | | { PseudoVREDOR_VS_M1_E8, 2032 }, |
5001 | | { PseudoVREDOR_VS_M2_E16, 2033 }, |
5002 | | { PseudoVREDOR_VS_M2_E32, 2034 }, |
5003 | | { PseudoVREDOR_VS_M2_E64, 2035 }, |
5004 | | { PseudoVREDOR_VS_M2_E8, 2036 }, |
5005 | | { PseudoVREDOR_VS_M4_E16, 2037 }, |
5006 | | { PseudoVREDOR_VS_M4_E32, 2038 }, |
5007 | | { PseudoVREDOR_VS_M4_E64, 2039 }, |
5008 | | { PseudoVREDOR_VS_M4_E8, 2040 }, |
5009 | | { PseudoVREDOR_VS_M8_E16, 2041 }, |
5010 | | { PseudoVREDOR_VS_M8_E32, 2042 }, |
5011 | | { PseudoVREDOR_VS_M8_E64, 2043 }, |
5012 | | { PseudoVREDOR_VS_M8_E8, 2044 }, |
5013 | | { PseudoVREDOR_VS_MF2_E16, 2045 }, |
5014 | | { PseudoVREDOR_VS_MF2_E32, 2046 }, |
5015 | | { PseudoVREDOR_VS_MF2_E8, 2047 }, |
5016 | | { PseudoVREDOR_VS_MF4_E16, 2048 }, |
5017 | | { PseudoVREDOR_VS_MF4_E8, 2049 }, |
5018 | | { PseudoVREDOR_VS_MF8_E8, 2050 }, |
5019 | | { PseudoVREDSUM_VS_M1_E16, 2051 }, |
5020 | | { PseudoVREDSUM_VS_M1_E32, 2052 }, |
5021 | | { PseudoVREDSUM_VS_M1_E64, 2053 }, |
5022 | | { PseudoVREDSUM_VS_M1_E8, 2054 }, |
5023 | | { PseudoVREDSUM_VS_M2_E16, 2055 }, |
5024 | | { PseudoVREDSUM_VS_M2_E32, 2056 }, |
5025 | | { PseudoVREDSUM_VS_M2_E64, 2057 }, |
5026 | | { PseudoVREDSUM_VS_M2_E8, 2058 }, |
5027 | | { PseudoVREDSUM_VS_M4_E16, 2059 }, |
5028 | | { PseudoVREDSUM_VS_M4_E32, 2060 }, |
5029 | | { PseudoVREDSUM_VS_M4_E64, 2061 }, |
5030 | | { PseudoVREDSUM_VS_M4_E8, 2062 }, |
5031 | | { PseudoVREDSUM_VS_M8_E16, 2063 }, |
5032 | | { PseudoVREDSUM_VS_M8_E32, 2064 }, |
5033 | | { PseudoVREDSUM_VS_M8_E64, 2065 }, |
5034 | | { PseudoVREDSUM_VS_M8_E8, 2066 }, |
5035 | | { PseudoVREDSUM_VS_MF2_E16, 2067 }, |
5036 | | { PseudoVREDSUM_VS_MF2_E32, 2068 }, |
5037 | | { PseudoVREDSUM_VS_MF2_E8, 2069 }, |
5038 | | { PseudoVREDSUM_VS_MF4_E16, 2070 }, |
5039 | | { PseudoVREDSUM_VS_MF4_E8, 2071 }, |
5040 | | { PseudoVREDSUM_VS_MF8_E8, 2072 }, |
5041 | | { PseudoVREDXOR_VS_M1_E16, 2073 }, |
5042 | | { PseudoVREDXOR_VS_M1_E32, 2074 }, |
5043 | | { PseudoVREDXOR_VS_M1_E64, 2075 }, |
5044 | | { PseudoVREDXOR_VS_M1_E8, 2076 }, |
5045 | | { PseudoVREDXOR_VS_M2_E16, 2077 }, |
5046 | | { PseudoVREDXOR_VS_M2_E32, 2078 }, |
5047 | | { PseudoVREDXOR_VS_M2_E64, 2079 }, |
5048 | | { PseudoVREDXOR_VS_M2_E8, 2080 }, |
5049 | | { PseudoVREDXOR_VS_M4_E16, 2081 }, |
5050 | | { PseudoVREDXOR_VS_M4_E32, 2082 }, |
5051 | | { PseudoVREDXOR_VS_M4_E64, 2083 }, |
5052 | | { PseudoVREDXOR_VS_M4_E8, 2084 }, |
5053 | | { PseudoVREDXOR_VS_M8_E16, 2085 }, |
5054 | | { PseudoVREDXOR_VS_M8_E32, 2086 }, |
5055 | | { PseudoVREDXOR_VS_M8_E64, 2087 }, |
5056 | | { PseudoVREDXOR_VS_M8_E8, 2088 }, |
5057 | | { PseudoVREDXOR_VS_MF2_E16, 2089 }, |
5058 | | { PseudoVREDXOR_VS_MF2_E32, 2090 }, |
5059 | | { PseudoVREDXOR_VS_MF2_E8, 2091 }, |
5060 | | { PseudoVREDXOR_VS_MF4_E16, 2092 }, |
5061 | | { PseudoVREDXOR_VS_MF4_E8, 2093 }, |
5062 | | { PseudoVREDXOR_VS_MF8_E8, 2094 }, |
5063 | | { PseudoVREMU_VV_M1_E16, 2095 }, |
5064 | | { PseudoVREMU_VV_M1_E32, 2096 }, |
5065 | | { PseudoVREMU_VV_M1_E64, 2097 }, |
5066 | | { PseudoVREMU_VV_M1_E8, 2098 }, |
5067 | | { PseudoVREMU_VV_M2_E16, 2099 }, |
5068 | | { PseudoVREMU_VV_M2_E32, 2100 }, |
5069 | | { PseudoVREMU_VV_M2_E64, 2101 }, |
5070 | | { PseudoVREMU_VV_M2_E8, 2102 }, |
5071 | | { PseudoVREMU_VV_M4_E16, 2103 }, |
5072 | | { PseudoVREMU_VV_M4_E32, 2104 }, |
5073 | | { PseudoVREMU_VV_M4_E64, 2105 }, |
5074 | | { PseudoVREMU_VV_M4_E8, 2106 }, |
5075 | | { PseudoVREMU_VV_M8_E16, 2107 }, |
5076 | | { PseudoVREMU_VV_M8_E32, 2108 }, |
5077 | | { PseudoVREMU_VV_M8_E64, 2109 }, |
5078 | | { PseudoVREMU_VV_M8_E8, 2110 }, |
5079 | | { PseudoVREMU_VV_MF2_E16, 2111 }, |
5080 | | { PseudoVREMU_VV_MF2_E32, 2112 }, |
5081 | | { PseudoVREMU_VV_MF2_E8, 2113 }, |
5082 | | { PseudoVREMU_VV_MF4_E16, 2114 }, |
5083 | | { PseudoVREMU_VV_MF4_E8, 2115 }, |
5084 | | { PseudoVREMU_VV_MF8_E8, 2116 }, |
5085 | | { PseudoVREMU_VX_M1_E16, 2117 }, |
5086 | | { PseudoVREMU_VX_M1_E32, 2118 }, |
5087 | | { PseudoVREMU_VX_M1_E64, 2119 }, |
5088 | | { PseudoVREMU_VX_M1_E8, 2120 }, |
5089 | | { PseudoVREMU_VX_M2_E16, 2121 }, |
5090 | | { PseudoVREMU_VX_M2_E32, 2122 }, |
5091 | | { PseudoVREMU_VX_M2_E64, 2123 }, |
5092 | | { PseudoVREMU_VX_M2_E8, 2124 }, |
5093 | | { PseudoVREMU_VX_M4_E16, 2125 }, |
5094 | | { PseudoVREMU_VX_M4_E32, 2126 }, |
5095 | | { PseudoVREMU_VX_M4_E64, 2127 }, |
5096 | | { PseudoVREMU_VX_M4_E8, 2128 }, |
5097 | | { PseudoVREMU_VX_M8_E16, 2129 }, |
5098 | | { PseudoVREMU_VX_M8_E32, 2130 }, |
5099 | | { PseudoVREMU_VX_M8_E64, 2131 }, |
5100 | | { PseudoVREMU_VX_M8_E8, 2132 }, |
5101 | | { PseudoVREMU_VX_MF2_E16, 2133 }, |
5102 | | { PseudoVREMU_VX_MF2_E32, 2134 }, |
5103 | | { PseudoVREMU_VX_MF2_E8, 2135 }, |
5104 | | { PseudoVREMU_VX_MF4_E16, 2136 }, |
5105 | | { PseudoVREMU_VX_MF4_E8, 2137 }, |
5106 | | { PseudoVREMU_VX_MF8_E8, 2138 }, |
5107 | | { PseudoVREM_VV_M1_E16, 2139 }, |
5108 | | { PseudoVREM_VV_M1_E32, 2140 }, |
5109 | | { PseudoVREM_VV_M1_E64, 2141 }, |
5110 | | { PseudoVREM_VV_M1_E8, 2142 }, |
5111 | | { PseudoVREM_VV_M2_E16, 2143 }, |
5112 | | { PseudoVREM_VV_M2_E32, 2144 }, |
5113 | | { PseudoVREM_VV_M2_E64, 2145 }, |
5114 | | { PseudoVREM_VV_M2_E8, 2146 }, |
5115 | | { PseudoVREM_VV_M4_E16, 2147 }, |
5116 | | { PseudoVREM_VV_M4_E32, 2148 }, |
5117 | | { PseudoVREM_VV_M4_E64, 2149 }, |
5118 | | { PseudoVREM_VV_M4_E8, 2150 }, |
5119 | | { PseudoVREM_VV_M8_E16, 2151 }, |
5120 | | { PseudoVREM_VV_M8_E32, 2152 }, |
5121 | | { PseudoVREM_VV_M8_E64, 2153 }, |
5122 | | { PseudoVREM_VV_M8_E8, 2154 }, |
5123 | | { PseudoVREM_VV_MF2_E16, 2155 }, |
5124 | | { PseudoVREM_VV_MF2_E32, 2156 }, |
5125 | | { PseudoVREM_VV_MF2_E8, 2157 }, |
5126 | | { PseudoVREM_VV_MF4_E16, 2158 }, |
5127 | | { PseudoVREM_VV_MF4_E8, 2159 }, |
5128 | | { PseudoVREM_VV_MF8_E8, 2160 }, |
5129 | | { PseudoVREM_VX_M1_E16, 2161 }, |
5130 | | { PseudoVREM_VX_M1_E32, 2162 }, |
5131 | | { PseudoVREM_VX_M1_E64, 2163 }, |
5132 | | { PseudoVREM_VX_M1_E8, 2164 }, |
5133 | | { PseudoVREM_VX_M2_E16, 2165 }, |
5134 | | { PseudoVREM_VX_M2_E32, 2166 }, |
5135 | | { PseudoVREM_VX_M2_E64, 2167 }, |
5136 | | { PseudoVREM_VX_M2_E8, 2168 }, |
5137 | | { PseudoVREM_VX_M4_E16, 2169 }, |
5138 | | { PseudoVREM_VX_M4_E32, 2170 }, |
5139 | | { PseudoVREM_VX_M4_E64, 2171 }, |
5140 | | { PseudoVREM_VX_M4_E8, 2172 }, |
5141 | | { PseudoVREM_VX_M8_E16, 2173 }, |
5142 | | { PseudoVREM_VX_M8_E32, 2174 }, |
5143 | | { PseudoVREM_VX_M8_E64, 2175 }, |
5144 | | { PseudoVREM_VX_M8_E8, 2176 }, |
5145 | | { PseudoVREM_VX_MF2_E16, 2177 }, |
5146 | | { PseudoVREM_VX_MF2_E32, 2178 }, |
5147 | | { PseudoVREM_VX_MF2_E8, 2179 }, |
5148 | | { PseudoVREM_VX_MF4_E16, 2180 }, |
5149 | | { PseudoVREM_VX_MF4_E8, 2181 }, |
5150 | | { PseudoVREM_VX_MF8_E8, 2182 }, |
5151 | | { PseudoVREV8_V_M1, 2183 }, |
5152 | | { PseudoVREV8_V_M2, 2184 }, |
5153 | | { PseudoVREV8_V_M4, 2185 }, |
5154 | | { PseudoVREV8_V_M8, 2186 }, |
5155 | | { PseudoVREV8_V_MF2, 2187 }, |
5156 | | { PseudoVREV8_V_MF4, 2188 }, |
5157 | | { PseudoVREV8_V_MF8, 2189 }, |
5158 | | { PseudoVRGATHEREI16_VV_M1_E16_M1, 2190 }, |
5159 | | { PseudoVRGATHEREI16_VV_M1_E16_M2, 2191 }, |
5160 | | { PseudoVRGATHEREI16_VV_M1_E16_MF2, 2192 }, |
5161 | | { PseudoVRGATHEREI16_VV_M1_E16_MF4, 2193 }, |
5162 | | { PseudoVRGATHEREI16_VV_M1_E32_M1, 2194 }, |
5163 | | { PseudoVRGATHEREI16_VV_M1_E32_M2, 2195 }, |
5164 | | { PseudoVRGATHEREI16_VV_M1_E32_MF2, 2196 }, |
5165 | | { PseudoVRGATHEREI16_VV_M1_E32_MF4, 2197 }, |
5166 | | { PseudoVRGATHEREI16_VV_M1_E64_M1, 2198 }, |
5167 | | { PseudoVRGATHEREI16_VV_M1_E64_M2, 2199 }, |
5168 | | { PseudoVRGATHEREI16_VV_M1_E64_MF2, 2200 }, |
5169 | | { PseudoVRGATHEREI16_VV_M1_E64_MF4, 2201 }, |
5170 | | { PseudoVRGATHEREI16_VV_M1_E8_M1, 2202 }, |
5171 | | { PseudoVRGATHEREI16_VV_M1_E8_M2, 2203 }, |
5172 | | { PseudoVRGATHEREI16_VV_M1_E8_MF2, 2204 }, |
5173 | | { PseudoVRGATHEREI16_VV_M1_E8_MF4, 2205 }, |
5174 | | { PseudoVRGATHEREI16_VV_M2_E16_M1, 2206 }, |
5175 | | { PseudoVRGATHEREI16_VV_M2_E16_M2, 2207 }, |
5176 | | { PseudoVRGATHEREI16_VV_M2_E16_M4, 2208 }, |
5177 | | { PseudoVRGATHEREI16_VV_M2_E16_MF2, 2209 }, |
5178 | | { PseudoVRGATHEREI16_VV_M2_E32_M1, 2210 }, |
5179 | | { PseudoVRGATHEREI16_VV_M2_E32_M2, 2211 }, |
5180 | | { PseudoVRGATHEREI16_VV_M2_E32_M4, 2212 }, |
5181 | | { PseudoVRGATHEREI16_VV_M2_E32_MF2, 2213 }, |
5182 | | { PseudoVRGATHEREI16_VV_M2_E64_M1, 2214 }, |
5183 | | { PseudoVRGATHEREI16_VV_M2_E64_M2, 2215 }, |
5184 | | { PseudoVRGATHEREI16_VV_M2_E64_M4, 2216 }, |
5185 | | { PseudoVRGATHEREI16_VV_M2_E64_MF2, 2217 }, |
5186 | | { PseudoVRGATHEREI16_VV_M2_E8_M1, 2218 }, |
5187 | | { PseudoVRGATHEREI16_VV_M2_E8_M2, 2219 }, |
5188 | | { PseudoVRGATHEREI16_VV_M2_E8_M4, 2220 }, |
5189 | | { PseudoVRGATHEREI16_VV_M2_E8_MF2, 2221 }, |
5190 | | { PseudoVRGATHEREI16_VV_M4_E16_M1, 2222 }, |
5191 | | { PseudoVRGATHEREI16_VV_M4_E16_M2, 2223 }, |
5192 | | { PseudoVRGATHEREI16_VV_M4_E16_M4, 2224 }, |
5193 | | { PseudoVRGATHEREI16_VV_M4_E16_M8, 2225 }, |
5194 | | { PseudoVRGATHEREI16_VV_M4_E32_M1, 2226 }, |
5195 | | { PseudoVRGATHEREI16_VV_M4_E32_M2, 2227 }, |
5196 | | { PseudoVRGATHEREI16_VV_M4_E32_M4, 2228 }, |
5197 | | { PseudoVRGATHEREI16_VV_M4_E32_M8, 2229 }, |
5198 | | { PseudoVRGATHEREI16_VV_M4_E64_M1, 2230 }, |
5199 | | { PseudoVRGATHEREI16_VV_M4_E64_M2, 2231 }, |
5200 | | { PseudoVRGATHEREI16_VV_M4_E64_M4, 2232 }, |
5201 | | { PseudoVRGATHEREI16_VV_M4_E64_M8, 2233 }, |
5202 | | { PseudoVRGATHEREI16_VV_M4_E8_M1, 2234 }, |
5203 | | { PseudoVRGATHEREI16_VV_M4_E8_M2, 2235 }, |
5204 | | { PseudoVRGATHEREI16_VV_M4_E8_M4, 2236 }, |
5205 | | { PseudoVRGATHEREI16_VV_M4_E8_M8, 2237 }, |
5206 | | { PseudoVRGATHEREI16_VV_M8_E16_M2, 2238 }, |
5207 | | { PseudoVRGATHEREI16_VV_M8_E16_M4, 2239 }, |
5208 | | { PseudoVRGATHEREI16_VV_M8_E16_M8, 2240 }, |
5209 | | { PseudoVRGATHEREI16_VV_M8_E32_M2, 2241 }, |
5210 | | { PseudoVRGATHEREI16_VV_M8_E32_M4, 2242 }, |
5211 | | { PseudoVRGATHEREI16_VV_M8_E32_M8, 2243 }, |
5212 | | { PseudoVRGATHEREI16_VV_M8_E64_M2, 2244 }, |
5213 | | { PseudoVRGATHEREI16_VV_M8_E64_M4, 2245 }, |
5214 | | { PseudoVRGATHEREI16_VV_M8_E64_M8, 2246 }, |
5215 | | { PseudoVRGATHEREI16_VV_M8_E8_M2, 2247 }, |
5216 | | { PseudoVRGATHEREI16_VV_M8_E8_M4, 2248 }, |
5217 | | { PseudoVRGATHEREI16_VV_M8_E8_M8, 2249 }, |
5218 | | { PseudoVRGATHEREI16_VV_MF2_E16_M1, 2250 }, |
5219 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF2, 2251 }, |
5220 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF4, 2252 }, |
5221 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF8, 2253 }, |
5222 | | { PseudoVRGATHEREI16_VV_MF2_E32_M1, 2254 }, |
5223 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF2, 2255 }, |
5224 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF4, 2256 }, |
5225 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF8, 2257 }, |
5226 | | { PseudoVRGATHEREI16_VV_MF2_E8_M1, 2258 }, |
5227 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF2, 2259 }, |
5228 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF4, 2260 }, |
5229 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF8, 2261 }, |
5230 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF2, 2262 }, |
5231 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF4, 2263 }, |
5232 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF8, 2264 }, |
5233 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF2, 2265 }, |
5234 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF4, 2266 }, |
5235 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF8, 2267 }, |
5236 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF4, 2268 }, |
5237 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF8, 2269 }, |
5238 | | { PseudoVRGATHER_VI_M1, 2270 }, |
5239 | | { PseudoVRGATHER_VI_M2, 2271 }, |
5240 | | { PseudoVRGATHER_VI_M4, 2272 }, |
5241 | | { PseudoVRGATHER_VI_M8, 2273 }, |
5242 | | { PseudoVRGATHER_VI_MF2, 2274 }, |
5243 | | { PseudoVRGATHER_VI_MF4, 2275 }, |
5244 | | { PseudoVRGATHER_VI_MF8, 2276 }, |
5245 | | { PseudoVRGATHER_VV_M1_E16, 2277 }, |
5246 | | { PseudoVRGATHER_VV_M1_E32, 2278 }, |
5247 | | { PseudoVRGATHER_VV_M1_E64, 2279 }, |
5248 | | { PseudoVRGATHER_VV_M1_E8, 2280 }, |
5249 | | { PseudoVRGATHER_VV_M2_E16, 2281 }, |
5250 | | { PseudoVRGATHER_VV_M2_E32, 2282 }, |
5251 | | { PseudoVRGATHER_VV_M2_E64, 2283 }, |
5252 | | { PseudoVRGATHER_VV_M2_E8, 2284 }, |
5253 | | { PseudoVRGATHER_VV_M4_E16, 2285 }, |
5254 | | { PseudoVRGATHER_VV_M4_E32, 2286 }, |
5255 | | { PseudoVRGATHER_VV_M4_E64, 2287 }, |
5256 | | { PseudoVRGATHER_VV_M4_E8, 2288 }, |
5257 | | { PseudoVRGATHER_VV_M8_E16, 2289 }, |
5258 | | { PseudoVRGATHER_VV_M8_E32, 2290 }, |
5259 | | { PseudoVRGATHER_VV_M8_E64, 2291 }, |
5260 | | { PseudoVRGATHER_VV_M8_E8, 2292 }, |
5261 | | { PseudoVRGATHER_VV_MF2_E16, 2293 }, |
5262 | | { PseudoVRGATHER_VV_MF2_E32, 2294 }, |
5263 | | { PseudoVRGATHER_VV_MF2_E8, 2295 }, |
5264 | | { PseudoVRGATHER_VV_MF4_E16, 2296 }, |
5265 | | { PseudoVRGATHER_VV_MF4_E8, 2297 }, |
5266 | | { PseudoVRGATHER_VV_MF8_E8, 2298 }, |
5267 | | { PseudoVRGATHER_VX_M1, 2299 }, |
5268 | | { PseudoVRGATHER_VX_M2, 2300 }, |
5269 | | { PseudoVRGATHER_VX_M4, 2301 }, |
5270 | | { PseudoVRGATHER_VX_M8, 2302 }, |
5271 | | { PseudoVRGATHER_VX_MF2, 2303 }, |
5272 | | { PseudoVRGATHER_VX_MF4, 2304 }, |
5273 | | { PseudoVRGATHER_VX_MF8, 2305 }, |
5274 | | { PseudoVROL_VV_M1, 2306 }, |
5275 | | { PseudoVROL_VV_M2, 2307 }, |
5276 | | { PseudoVROL_VV_M4, 2308 }, |
5277 | | { PseudoVROL_VV_M8, 2309 }, |
5278 | | { PseudoVROL_VV_MF2, 2310 }, |
5279 | | { PseudoVROL_VV_MF4, 2311 }, |
5280 | | { PseudoVROL_VV_MF8, 2312 }, |
5281 | | { PseudoVROL_VX_M1, 2313 }, |
5282 | | { PseudoVROL_VX_M2, 2314 }, |
5283 | | { PseudoVROL_VX_M4, 2315 }, |
5284 | | { PseudoVROL_VX_M8, 2316 }, |
5285 | | { PseudoVROL_VX_MF2, 2317 }, |
5286 | | { PseudoVROL_VX_MF4, 2318 }, |
5287 | | { PseudoVROL_VX_MF8, 2319 }, |
5288 | | { PseudoVROR_VI_M1, 2320 }, |
5289 | | { PseudoVROR_VI_M2, 2321 }, |
5290 | | { PseudoVROR_VI_M4, 2322 }, |
5291 | | { PseudoVROR_VI_M8, 2323 }, |
5292 | | { PseudoVROR_VI_MF2, 2324 }, |
5293 | | { PseudoVROR_VI_MF4, 2325 }, |
5294 | | { PseudoVROR_VI_MF8, 2326 }, |
5295 | | { PseudoVROR_VV_M1, 2327 }, |
5296 | | { PseudoVROR_VV_M2, 2328 }, |
5297 | | { PseudoVROR_VV_M4, 2329 }, |
5298 | | { PseudoVROR_VV_M8, 2330 }, |
5299 | | { PseudoVROR_VV_MF2, 2331 }, |
5300 | | { PseudoVROR_VV_MF4, 2332 }, |
5301 | | { PseudoVROR_VV_MF8, 2333 }, |
5302 | | { PseudoVROR_VX_M1, 2334 }, |
5303 | | { PseudoVROR_VX_M2, 2335 }, |
5304 | | { PseudoVROR_VX_M4, 2336 }, |
5305 | | { PseudoVROR_VX_M8, 2337 }, |
5306 | | { PseudoVROR_VX_MF2, 2338 }, |
5307 | | { PseudoVROR_VX_MF4, 2339 }, |
5308 | | { PseudoVROR_VX_MF8, 2340 }, |
5309 | | { PseudoVRSUB_VI_M1, 2341 }, |
5310 | | { PseudoVRSUB_VI_M2, 2342 }, |
5311 | | { PseudoVRSUB_VI_M4, 2343 }, |
5312 | | { PseudoVRSUB_VI_M8, 2344 }, |
5313 | | { PseudoVRSUB_VI_MF2, 2345 }, |
5314 | | { PseudoVRSUB_VI_MF4, 2346 }, |
5315 | | { PseudoVRSUB_VI_MF8, 2347 }, |
5316 | | { PseudoVRSUB_VX_M1, 2348 }, |
5317 | | { PseudoVRSUB_VX_M2, 2349 }, |
5318 | | { PseudoVRSUB_VX_M4, 2350 }, |
5319 | | { PseudoVRSUB_VX_M8, 2351 }, |
5320 | | { PseudoVRSUB_VX_MF2, 2352 }, |
5321 | | { PseudoVRSUB_VX_MF4, 2353 }, |
5322 | | { PseudoVRSUB_VX_MF8, 2354 }, |
5323 | | { PseudoVSADDU_VI_M1, 2355 }, |
5324 | | { PseudoVSADDU_VI_M2, 2356 }, |
5325 | | { PseudoVSADDU_VI_M4, 2357 }, |
5326 | | { PseudoVSADDU_VI_M8, 2358 }, |
5327 | | { PseudoVSADDU_VI_MF2, 2359 }, |
5328 | | { PseudoVSADDU_VI_MF4, 2360 }, |
5329 | | { PseudoVSADDU_VI_MF8, 2361 }, |
5330 | | { PseudoVSADDU_VV_M1, 2362 }, |
5331 | | { PseudoVSADDU_VV_M2, 2363 }, |
5332 | | { PseudoVSADDU_VV_M4, 2364 }, |
5333 | | { PseudoVSADDU_VV_M8, 2365 }, |
5334 | | { PseudoVSADDU_VV_MF2, 2366 }, |
5335 | | { PseudoVSADDU_VV_MF4, 2367 }, |
5336 | | { PseudoVSADDU_VV_MF8, 2368 }, |
5337 | | { PseudoVSADDU_VX_M1, 2369 }, |
5338 | | { PseudoVSADDU_VX_M2, 2370 }, |
5339 | | { PseudoVSADDU_VX_M4, 2371 }, |
5340 | | { PseudoVSADDU_VX_M8, 2372 }, |
5341 | | { PseudoVSADDU_VX_MF2, 2373 }, |
5342 | | { PseudoVSADDU_VX_MF4, 2374 }, |
5343 | | { PseudoVSADDU_VX_MF8, 2375 }, |
5344 | | { PseudoVSADD_VI_M1, 2376 }, |
5345 | | { PseudoVSADD_VI_M2, 2377 }, |
5346 | | { PseudoVSADD_VI_M4, 2378 }, |
5347 | | { PseudoVSADD_VI_M8, 2379 }, |
5348 | | { PseudoVSADD_VI_MF2, 2380 }, |
5349 | | { PseudoVSADD_VI_MF4, 2381 }, |
5350 | | { PseudoVSADD_VI_MF8, 2382 }, |
5351 | | { PseudoVSADD_VV_M1, 2383 }, |
5352 | | { PseudoVSADD_VV_M2, 2384 }, |
5353 | | { PseudoVSADD_VV_M4, 2385 }, |
5354 | | { PseudoVSADD_VV_M8, 2386 }, |
5355 | | { PseudoVSADD_VV_MF2, 2387 }, |
5356 | | { PseudoVSADD_VV_MF4, 2388 }, |
5357 | | { PseudoVSADD_VV_MF8, 2389 }, |
5358 | | { PseudoVSADD_VX_M1, 2390 }, |
5359 | | { PseudoVSADD_VX_M2, 2391 }, |
5360 | | { PseudoVSADD_VX_M4, 2392 }, |
5361 | | { PseudoVSADD_VX_M8, 2393 }, |
5362 | | { PseudoVSADD_VX_MF2, 2394 }, |
5363 | | { PseudoVSADD_VX_MF4, 2395 }, |
5364 | | { PseudoVSADD_VX_MF8, 2396 }, |
5365 | | { PseudoVSEXT_VF2_M1, 2397 }, |
5366 | | { PseudoVSEXT_VF2_M2, 2398 }, |
5367 | | { PseudoVSEXT_VF2_M4, 2399 }, |
5368 | | { PseudoVSEXT_VF2_M8, 2400 }, |
5369 | | { PseudoVSEXT_VF2_MF2, 2401 }, |
5370 | | { PseudoVSEXT_VF2_MF4, 2402 }, |
5371 | | { PseudoVSEXT_VF4_M1, 2403 }, |
5372 | | { PseudoVSEXT_VF4_M2, 2404 }, |
5373 | | { PseudoVSEXT_VF4_M4, 2405 }, |
5374 | | { PseudoVSEXT_VF4_M8, 2406 }, |
5375 | | { PseudoVSEXT_VF4_MF2, 2407 }, |
5376 | | { PseudoVSEXT_VF8_M1, 2408 }, |
5377 | | { PseudoVSEXT_VF8_M2, 2409 }, |
5378 | | { PseudoVSEXT_VF8_M4, 2410 }, |
5379 | | { PseudoVSEXT_VF8_M8, 2411 }, |
5380 | | { PseudoVSLIDE1DOWN_VX_M1, 2412 }, |
5381 | | { PseudoVSLIDE1DOWN_VX_M2, 2413 }, |
5382 | | { PseudoVSLIDE1DOWN_VX_M4, 2414 }, |
5383 | | { PseudoVSLIDE1DOWN_VX_M8, 2415 }, |
5384 | | { PseudoVSLIDE1DOWN_VX_MF2, 2416 }, |
5385 | | { PseudoVSLIDE1DOWN_VX_MF4, 2417 }, |
5386 | | { PseudoVSLIDE1DOWN_VX_MF8, 2418 }, |
5387 | | { PseudoVSLIDE1UP_VX_M1, 2419 }, |
5388 | | { PseudoVSLIDE1UP_VX_M2, 2420 }, |
5389 | | { PseudoVSLIDE1UP_VX_M4, 2421 }, |
5390 | | { PseudoVSLIDE1UP_VX_M8, 2422 }, |
5391 | | { PseudoVSLIDE1UP_VX_MF2, 2423 }, |
5392 | | { PseudoVSLIDE1UP_VX_MF4, 2424 }, |
5393 | | { PseudoVSLIDE1UP_VX_MF8, 2425 }, |
5394 | | { PseudoVSLIDEDOWN_VI_M1, 2426 }, |
5395 | | { PseudoVSLIDEDOWN_VI_M2, 2427 }, |
5396 | | { PseudoVSLIDEDOWN_VI_M4, 2428 }, |
5397 | | { PseudoVSLIDEDOWN_VI_M8, 2429 }, |
5398 | | { PseudoVSLIDEDOWN_VI_MF2, 2430 }, |
5399 | | { PseudoVSLIDEDOWN_VI_MF4, 2431 }, |
5400 | | { PseudoVSLIDEDOWN_VI_MF8, 2432 }, |
5401 | | { PseudoVSLIDEDOWN_VX_M1, 2433 }, |
5402 | | { PseudoVSLIDEDOWN_VX_M2, 2434 }, |
5403 | | { PseudoVSLIDEDOWN_VX_M4, 2435 }, |
5404 | | { PseudoVSLIDEDOWN_VX_M8, 2436 }, |
5405 | | { PseudoVSLIDEDOWN_VX_MF2, 2437 }, |
5406 | | { PseudoVSLIDEDOWN_VX_MF4, 2438 }, |
5407 | | { PseudoVSLIDEDOWN_VX_MF8, 2439 }, |
5408 | | { PseudoVSLIDEUP_VI_M1, 2440 }, |
5409 | | { PseudoVSLIDEUP_VI_M2, 2441 }, |
5410 | | { PseudoVSLIDEUP_VI_M4, 2442 }, |
5411 | | { PseudoVSLIDEUP_VI_M8, 2443 }, |
5412 | | { PseudoVSLIDEUP_VI_MF2, 2444 }, |
5413 | | { PseudoVSLIDEUP_VI_MF4, 2445 }, |
5414 | | { PseudoVSLIDEUP_VI_MF8, 2446 }, |
5415 | | { PseudoVSLIDEUP_VX_M1, 2447 }, |
5416 | | { PseudoVSLIDEUP_VX_M2, 2448 }, |
5417 | | { PseudoVSLIDEUP_VX_M4, 2449 }, |
5418 | | { PseudoVSLIDEUP_VX_M8, 2450 }, |
5419 | | { PseudoVSLIDEUP_VX_MF2, 2451 }, |
5420 | | { PseudoVSLIDEUP_VX_MF4, 2452 }, |
5421 | | { PseudoVSLIDEUP_VX_MF8, 2453 }, |
5422 | | { PseudoVSLL_VI_M1, 2454 }, |
5423 | | { PseudoVSLL_VI_M2, 2455 }, |
5424 | | { PseudoVSLL_VI_M4, 2456 }, |
5425 | | { PseudoVSLL_VI_M8, 2457 }, |
5426 | | { PseudoVSLL_VI_MF2, 2458 }, |
5427 | | { PseudoVSLL_VI_MF4, 2459 }, |
5428 | | { PseudoVSLL_VI_MF8, 2460 }, |
5429 | | { PseudoVSLL_VV_M1, 2461 }, |
5430 | | { PseudoVSLL_VV_M2, 2462 }, |
5431 | | { PseudoVSLL_VV_M4, 2463 }, |
5432 | | { PseudoVSLL_VV_M8, 2464 }, |
5433 | | { PseudoVSLL_VV_MF2, 2465 }, |
5434 | | { PseudoVSLL_VV_MF4, 2466 }, |
5435 | | { PseudoVSLL_VV_MF8, 2467 }, |
5436 | | { PseudoVSLL_VX_M1, 2468 }, |
5437 | | { PseudoVSLL_VX_M2, 2469 }, |
5438 | | { PseudoVSLL_VX_M4, 2470 }, |
5439 | | { PseudoVSLL_VX_M8, 2471 }, |
5440 | | { PseudoVSLL_VX_MF2, 2472 }, |
5441 | | { PseudoVSLL_VX_MF4, 2473 }, |
5442 | | { PseudoVSLL_VX_MF8, 2474 }, |
5443 | | { PseudoVSMUL_VV_M1, 2475 }, |
5444 | | { PseudoVSMUL_VV_M2, 2476 }, |
5445 | | { PseudoVSMUL_VV_M4, 2477 }, |
5446 | | { PseudoVSMUL_VV_M8, 2478 }, |
5447 | | { PseudoVSMUL_VV_MF2, 2479 }, |
5448 | | { PseudoVSMUL_VV_MF4, 2480 }, |
5449 | | { PseudoVSMUL_VV_MF8, 2481 }, |
5450 | | { PseudoVSMUL_VX_M1, 2482 }, |
5451 | | { PseudoVSMUL_VX_M2, 2483 }, |
5452 | | { PseudoVSMUL_VX_M4, 2484 }, |
5453 | | { PseudoVSMUL_VX_M8, 2485 }, |
5454 | | { PseudoVSMUL_VX_MF2, 2486 }, |
5455 | | { PseudoVSMUL_VX_MF4, 2487 }, |
5456 | | { PseudoVSMUL_VX_MF8, 2488 }, |
5457 | | { PseudoVSRA_VI_M1, 2489 }, |
5458 | | { PseudoVSRA_VI_M2, 2490 }, |
5459 | | { PseudoVSRA_VI_M4, 2491 }, |
5460 | | { PseudoVSRA_VI_M8, 2492 }, |
5461 | | { PseudoVSRA_VI_MF2, 2493 }, |
5462 | | { PseudoVSRA_VI_MF4, 2494 }, |
5463 | | { PseudoVSRA_VI_MF8, 2495 }, |
5464 | | { PseudoVSRA_VV_M1, 2496 }, |
5465 | | { PseudoVSRA_VV_M2, 2497 }, |
5466 | | { PseudoVSRA_VV_M4, 2498 }, |
5467 | | { PseudoVSRA_VV_M8, 2499 }, |
5468 | | { PseudoVSRA_VV_MF2, 2500 }, |
5469 | | { PseudoVSRA_VV_MF4, 2501 }, |
5470 | | { PseudoVSRA_VV_MF8, 2502 }, |
5471 | | { PseudoVSRA_VX_M1, 2503 }, |
5472 | | { PseudoVSRA_VX_M2, 2504 }, |
5473 | | { PseudoVSRA_VX_M4, 2505 }, |
5474 | | { PseudoVSRA_VX_M8, 2506 }, |
5475 | | { PseudoVSRA_VX_MF2, 2507 }, |
5476 | | { PseudoVSRA_VX_MF4, 2508 }, |
5477 | | { PseudoVSRA_VX_MF8, 2509 }, |
5478 | | { PseudoVSRL_VI_M1, 2510 }, |
5479 | | { PseudoVSRL_VI_M2, 2511 }, |
5480 | | { PseudoVSRL_VI_M4, 2512 }, |
5481 | | { PseudoVSRL_VI_M8, 2513 }, |
5482 | | { PseudoVSRL_VI_MF2, 2514 }, |
5483 | | { PseudoVSRL_VI_MF4, 2515 }, |
5484 | | { PseudoVSRL_VI_MF8, 2516 }, |
5485 | | { PseudoVSRL_VV_M1, 2517 }, |
5486 | | { PseudoVSRL_VV_M2, 2518 }, |
5487 | | { PseudoVSRL_VV_M4, 2519 }, |
5488 | | { PseudoVSRL_VV_M8, 2520 }, |
5489 | | { PseudoVSRL_VV_MF2, 2521 }, |
5490 | | { PseudoVSRL_VV_MF4, 2522 }, |
5491 | | { PseudoVSRL_VV_MF8, 2523 }, |
5492 | | { PseudoVSRL_VX_M1, 2524 }, |
5493 | | { PseudoVSRL_VX_M2, 2525 }, |
5494 | | { PseudoVSRL_VX_M4, 2526 }, |
5495 | | { PseudoVSRL_VX_M8, 2527 }, |
5496 | | { PseudoVSRL_VX_MF2, 2528 }, |
5497 | | { PseudoVSRL_VX_MF4, 2529 }, |
5498 | | { PseudoVSRL_VX_MF8, 2530 }, |
5499 | | { PseudoVSSRA_VI_M1, 2531 }, |
5500 | | { PseudoVSSRA_VI_M2, 2532 }, |
5501 | | { PseudoVSSRA_VI_M4, 2533 }, |
5502 | | { PseudoVSSRA_VI_M8, 2534 }, |
5503 | | { PseudoVSSRA_VI_MF2, 2535 }, |
5504 | | { PseudoVSSRA_VI_MF4, 2536 }, |
5505 | | { PseudoVSSRA_VI_MF8, 2537 }, |
5506 | | { PseudoVSSRA_VV_M1, 2538 }, |
5507 | | { PseudoVSSRA_VV_M2, 2539 }, |
5508 | | { PseudoVSSRA_VV_M4, 2540 }, |
5509 | | { PseudoVSSRA_VV_M8, 2541 }, |
5510 | | { PseudoVSSRA_VV_MF2, 2542 }, |
5511 | | { PseudoVSSRA_VV_MF4, 2543 }, |
5512 | | { PseudoVSSRA_VV_MF8, 2544 }, |
5513 | | { PseudoVSSRA_VX_M1, 2545 }, |
5514 | | { PseudoVSSRA_VX_M2, 2546 }, |
5515 | | { PseudoVSSRA_VX_M4, 2547 }, |
5516 | | { PseudoVSSRA_VX_M8, 2548 }, |
5517 | | { PseudoVSSRA_VX_MF2, 2549 }, |
5518 | | { PseudoVSSRA_VX_MF4, 2550 }, |
5519 | | { PseudoVSSRA_VX_MF8, 2551 }, |
5520 | | { PseudoVSSRL_VI_M1, 2552 }, |
5521 | | { PseudoVSSRL_VI_M2, 2553 }, |
5522 | | { PseudoVSSRL_VI_M4, 2554 }, |
5523 | | { PseudoVSSRL_VI_M8, 2555 }, |
5524 | | { PseudoVSSRL_VI_MF2, 2556 }, |
5525 | | { PseudoVSSRL_VI_MF4, 2557 }, |
5526 | | { PseudoVSSRL_VI_MF8, 2558 }, |
5527 | | { PseudoVSSRL_VV_M1, 2559 }, |
5528 | | { PseudoVSSRL_VV_M2, 2560 }, |
5529 | | { PseudoVSSRL_VV_M4, 2561 }, |
5530 | | { PseudoVSSRL_VV_M8, 2562 }, |
5531 | | { PseudoVSSRL_VV_MF2, 2563 }, |
5532 | | { PseudoVSSRL_VV_MF4, 2564 }, |
5533 | | { PseudoVSSRL_VV_MF8, 2565 }, |
5534 | | { PseudoVSSRL_VX_M1, 2566 }, |
5535 | | { PseudoVSSRL_VX_M2, 2567 }, |
5536 | | { PseudoVSSRL_VX_M4, 2568 }, |
5537 | | { PseudoVSSRL_VX_M8, 2569 }, |
5538 | | { PseudoVSSRL_VX_MF2, 2570 }, |
5539 | | { PseudoVSSRL_VX_MF4, 2571 }, |
5540 | | { PseudoVSSRL_VX_MF8, 2572 }, |
5541 | | { PseudoVSSUBU_VV_M1, 2573 }, |
5542 | | { PseudoVSSUBU_VV_M2, 2574 }, |
5543 | | { PseudoVSSUBU_VV_M4, 2575 }, |
5544 | | { PseudoVSSUBU_VV_M8, 2576 }, |
5545 | | { PseudoVSSUBU_VV_MF2, 2577 }, |
5546 | | { PseudoVSSUBU_VV_MF4, 2578 }, |
5547 | | { PseudoVSSUBU_VV_MF8, 2579 }, |
5548 | | { PseudoVSSUBU_VX_M1, 2580 }, |
5549 | | { PseudoVSSUBU_VX_M2, 2581 }, |
5550 | | { PseudoVSSUBU_VX_M4, 2582 }, |
5551 | | { PseudoVSSUBU_VX_M8, 2583 }, |
5552 | | { PseudoVSSUBU_VX_MF2, 2584 }, |
5553 | | { PseudoVSSUBU_VX_MF4, 2585 }, |
5554 | | { PseudoVSSUBU_VX_MF8, 2586 }, |
5555 | | { PseudoVSSUB_VV_M1, 2587 }, |
5556 | | { PseudoVSSUB_VV_M2, 2588 }, |
5557 | | { PseudoVSSUB_VV_M4, 2589 }, |
5558 | | { PseudoVSSUB_VV_M8, 2590 }, |
5559 | | { PseudoVSSUB_VV_MF2, 2591 }, |
5560 | | { PseudoVSSUB_VV_MF4, 2592 }, |
5561 | | { PseudoVSSUB_VV_MF8, 2593 }, |
5562 | | { PseudoVSSUB_VX_M1, 2594 }, |
5563 | | { PseudoVSSUB_VX_M2, 2595 }, |
5564 | | { PseudoVSSUB_VX_M4, 2596 }, |
5565 | | { PseudoVSSUB_VX_M8, 2597 }, |
5566 | | { PseudoVSSUB_VX_MF2, 2598 }, |
5567 | | { PseudoVSSUB_VX_MF4, 2599 }, |
5568 | | { PseudoVSSUB_VX_MF8, 2600 }, |
5569 | | { PseudoVSUB_VV_M1, 2601 }, |
5570 | | { PseudoVSUB_VV_M2, 2602 }, |
5571 | | { PseudoVSUB_VV_M4, 2603 }, |
5572 | | { PseudoVSUB_VV_M8, 2604 }, |
5573 | | { PseudoVSUB_VV_MF2, 2605 }, |
5574 | | { PseudoVSUB_VV_MF4, 2606 }, |
5575 | | { PseudoVSUB_VV_MF8, 2607 }, |
5576 | | { PseudoVSUB_VX_M1, 2608 }, |
5577 | | { PseudoVSUB_VX_M2, 2609 }, |
5578 | | { PseudoVSUB_VX_M4, 2610 }, |
5579 | | { PseudoVSUB_VX_M8, 2611 }, |
5580 | | { PseudoVSUB_VX_MF2, 2612 }, |
5581 | | { PseudoVSUB_VX_MF4, 2613 }, |
5582 | | { PseudoVSUB_VX_MF8, 2614 }, |
5583 | | { PseudoVWADDU_VV_M1, 2615 }, |
5584 | | { PseudoVWADDU_VV_M2, 2616 }, |
5585 | | { PseudoVWADDU_VV_M4, 2617 }, |
5586 | | { PseudoVWADDU_VV_MF2, 2618 }, |
5587 | | { PseudoVWADDU_VV_MF4, 2619 }, |
5588 | | { PseudoVWADDU_VV_MF8, 2620 }, |
5589 | | { PseudoVWADDU_VX_M1, 2621 }, |
5590 | | { PseudoVWADDU_VX_M2, 2622 }, |
5591 | | { PseudoVWADDU_VX_M4, 2623 }, |
5592 | | { PseudoVWADDU_VX_MF2, 2624 }, |
5593 | | { PseudoVWADDU_VX_MF4, 2625 }, |
5594 | | { PseudoVWADDU_VX_MF8, 2626 }, |
5595 | | { PseudoVWADDU_WV_M1, 2627 }, |
5596 | | { PseudoVWADDU_WV_M2, 2628 }, |
5597 | | { PseudoVWADDU_WV_M4, 2629 }, |
5598 | | { PseudoVWADDU_WV_MF2, 2630 }, |
5599 | | { PseudoVWADDU_WV_MF4, 2631 }, |
5600 | | { PseudoVWADDU_WV_MF8, 2632 }, |
5601 | | { PseudoVWADDU_WX_M1, 2633 }, |
5602 | | { PseudoVWADDU_WX_M2, 2634 }, |
5603 | | { PseudoVWADDU_WX_M4, 2635 }, |
5604 | | { PseudoVWADDU_WX_MF2, 2636 }, |
5605 | | { PseudoVWADDU_WX_MF4, 2637 }, |
5606 | | { PseudoVWADDU_WX_MF8, 2638 }, |
5607 | | { PseudoVWADD_VV_M1, 2639 }, |
5608 | | { PseudoVWADD_VV_M2, 2640 }, |
5609 | | { PseudoVWADD_VV_M4, 2641 }, |
5610 | | { PseudoVWADD_VV_MF2, 2642 }, |
5611 | | { PseudoVWADD_VV_MF4, 2643 }, |
5612 | | { PseudoVWADD_VV_MF8, 2644 }, |
5613 | | { PseudoVWADD_VX_M1, 2645 }, |
5614 | | { PseudoVWADD_VX_M2, 2646 }, |
5615 | | { PseudoVWADD_VX_M4, 2647 }, |
5616 | | { PseudoVWADD_VX_MF2, 2648 }, |
5617 | | { PseudoVWADD_VX_MF4, 2649 }, |
5618 | | { PseudoVWADD_VX_MF8, 2650 }, |
5619 | | { PseudoVWADD_WV_M1, 2651 }, |
5620 | | { PseudoVWADD_WV_M2, 2652 }, |
5621 | | { PseudoVWADD_WV_M4, 2653 }, |
5622 | | { PseudoVWADD_WV_MF2, 2654 }, |
5623 | | { PseudoVWADD_WV_MF4, 2655 }, |
5624 | | { PseudoVWADD_WV_MF8, 2656 }, |
5625 | | { PseudoVWADD_WX_M1, 2657 }, |
5626 | | { PseudoVWADD_WX_M2, 2658 }, |
5627 | | { PseudoVWADD_WX_M4, 2659 }, |
5628 | | { PseudoVWADD_WX_MF2, 2660 }, |
5629 | | { PseudoVWADD_WX_MF4, 2661 }, |
5630 | | { PseudoVWADD_WX_MF8, 2662 }, |
5631 | | { PseudoVWMACCSU_VV_M1, 2663 }, |
5632 | | { PseudoVWMACCSU_VV_M2, 2664 }, |
5633 | | { PseudoVWMACCSU_VV_M4, 2665 }, |
5634 | | { PseudoVWMACCSU_VV_MF2, 2666 }, |
5635 | | { PseudoVWMACCSU_VV_MF4, 2667 }, |
5636 | | { PseudoVWMACCSU_VV_MF8, 2668 }, |
5637 | | { PseudoVWMACCSU_VX_M1, 2669 }, |
5638 | | { PseudoVWMACCSU_VX_M2, 2670 }, |
5639 | | { PseudoVWMACCSU_VX_M4, 2671 }, |
5640 | | { PseudoVWMACCSU_VX_MF2, 2672 }, |
5641 | | { PseudoVWMACCSU_VX_MF4, 2673 }, |
5642 | | { PseudoVWMACCSU_VX_MF8, 2674 }, |
5643 | | { PseudoVWMACCUS_VX_M1, 2675 }, |
5644 | | { PseudoVWMACCUS_VX_M2, 2676 }, |
5645 | | { PseudoVWMACCUS_VX_M4, 2677 }, |
5646 | | { PseudoVWMACCUS_VX_MF2, 2678 }, |
5647 | | { PseudoVWMACCUS_VX_MF4, 2679 }, |
5648 | | { PseudoVWMACCUS_VX_MF8, 2680 }, |
5649 | | { PseudoVWMACCU_VV_M1, 2681 }, |
5650 | | { PseudoVWMACCU_VV_M2, 2682 }, |
5651 | | { PseudoVWMACCU_VV_M4, 2683 }, |
5652 | | { PseudoVWMACCU_VV_MF2, 2684 }, |
5653 | | { PseudoVWMACCU_VV_MF4, 2685 }, |
5654 | | { PseudoVWMACCU_VV_MF8, 2686 }, |
5655 | | { PseudoVWMACCU_VX_M1, 2687 }, |
5656 | | { PseudoVWMACCU_VX_M2, 2688 }, |
5657 | | { PseudoVWMACCU_VX_M4, 2689 }, |
5658 | | { PseudoVWMACCU_VX_MF2, 2690 }, |
5659 | | { PseudoVWMACCU_VX_MF4, 2691 }, |
5660 | | { PseudoVWMACCU_VX_MF8, 2692 }, |
5661 | | { PseudoVWMACC_VV_M1, 2693 }, |
5662 | | { PseudoVWMACC_VV_M2, 2694 }, |
5663 | | { PseudoVWMACC_VV_M4, 2695 }, |
5664 | | { PseudoVWMACC_VV_MF2, 2696 }, |
5665 | | { PseudoVWMACC_VV_MF4, 2697 }, |
5666 | | { PseudoVWMACC_VV_MF8, 2698 }, |
5667 | | { PseudoVWMACC_VX_M1, 2699 }, |
5668 | | { PseudoVWMACC_VX_M2, 2700 }, |
5669 | | { PseudoVWMACC_VX_M4, 2701 }, |
5670 | | { PseudoVWMACC_VX_MF2, 2702 }, |
5671 | | { PseudoVWMACC_VX_MF4, 2703 }, |
5672 | | { PseudoVWMACC_VX_MF8, 2704 }, |
5673 | | { PseudoVWMULSU_VV_M1, 2705 }, |
5674 | | { PseudoVWMULSU_VV_M2, 2706 }, |
5675 | | { PseudoVWMULSU_VV_M4, 2707 }, |
5676 | | { PseudoVWMULSU_VV_MF2, 2708 }, |
5677 | | { PseudoVWMULSU_VV_MF4, 2709 }, |
5678 | | { PseudoVWMULSU_VV_MF8, 2710 }, |
5679 | | { PseudoVWMULSU_VX_M1, 2711 }, |
5680 | | { PseudoVWMULSU_VX_M2, 2712 }, |
5681 | | { PseudoVWMULSU_VX_M4, 2713 }, |
5682 | | { PseudoVWMULSU_VX_MF2, 2714 }, |
5683 | | { PseudoVWMULSU_VX_MF4, 2715 }, |
5684 | | { PseudoVWMULSU_VX_MF8, 2716 }, |
5685 | | { PseudoVWMULU_VV_M1, 2717 }, |
5686 | | { PseudoVWMULU_VV_M2, 2718 }, |
5687 | | { PseudoVWMULU_VV_M4, 2719 }, |
5688 | | { PseudoVWMULU_VV_MF2, 2720 }, |
5689 | | { PseudoVWMULU_VV_MF4, 2721 }, |
5690 | | { PseudoVWMULU_VV_MF8, 2722 }, |
5691 | | { PseudoVWMULU_VX_M1, 2723 }, |
5692 | | { PseudoVWMULU_VX_M2, 2724 }, |
5693 | | { PseudoVWMULU_VX_M4, 2725 }, |
5694 | | { PseudoVWMULU_VX_MF2, 2726 }, |
5695 | | { PseudoVWMULU_VX_MF4, 2727 }, |
5696 | | { PseudoVWMULU_VX_MF8, 2728 }, |
5697 | | { PseudoVWMUL_VV_M1, 2729 }, |
5698 | | { PseudoVWMUL_VV_M2, 2730 }, |
5699 | | { PseudoVWMUL_VV_M4, 2731 }, |
5700 | | { PseudoVWMUL_VV_MF2, 2732 }, |
5701 | | { PseudoVWMUL_VV_MF4, 2733 }, |
5702 | | { PseudoVWMUL_VV_MF8, 2734 }, |
5703 | | { PseudoVWMUL_VX_M1, 2735 }, |
5704 | | { PseudoVWMUL_VX_M2, 2736 }, |
5705 | | { PseudoVWMUL_VX_M4, 2737 }, |
5706 | | { PseudoVWMUL_VX_MF2, 2738 }, |
5707 | | { PseudoVWMUL_VX_MF4, 2739 }, |
5708 | | { PseudoVWMUL_VX_MF8, 2740 }, |
5709 | | { PseudoVWREDSUMU_VS_M1_E16, 2741 }, |
5710 | | { PseudoVWREDSUMU_VS_M1_E32, 2742 }, |
5711 | | { PseudoVWREDSUMU_VS_M1_E8, 2743 }, |
5712 | | { PseudoVWREDSUMU_VS_M2_E16, 2744 }, |
5713 | | { PseudoVWREDSUMU_VS_M2_E32, 2745 }, |
5714 | | { PseudoVWREDSUMU_VS_M2_E8, 2746 }, |
5715 | | { PseudoVWREDSUMU_VS_M4_E16, 2747 }, |
5716 | | { PseudoVWREDSUMU_VS_M4_E32, 2748 }, |
5717 | | { PseudoVWREDSUMU_VS_M4_E8, 2749 }, |
5718 | | { PseudoVWREDSUMU_VS_M8_E16, 2750 }, |
5719 | | { PseudoVWREDSUMU_VS_M8_E32, 2751 }, |
5720 | | { PseudoVWREDSUMU_VS_M8_E8, 2752 }, |
5721 | | { PseudoVWREDSUMU_VS_MF2_E16, 2753 }, |
5722 | | { PseudoVWREDSUMU_VS_MF2_E32, 2754 }, |
5723 | | { PseudoVWREDSUMU_VS_MF2_E8, 2755 }, |
5724 | | { PseudoVWREDSUMU_VS_MF4_E16, 2756 }, |
5725 | | { PseudoVWREDSUMU_VS_MF4_E8, 2757 }, |
5726 | | { PseudoVWREDSUMU_VS_MF8_E8, 2758 }, |
5727 | | { PseudoVWREDSUM_VS_M1_E16, 2759 }, |
5728 | | { PseudoVWREDSUM_VS_M1_E32, 2760 }, |
5729 | | { PseudoVWREDSUM_VS_M1_E8, 2761 }, |
5730 | | { PseudoVWREDSUM_VS_M2_E16, 2762 }, |
5731 | | { PseudoVWREDSUM_VS_M2_E32, 2763 }, |
5732 | | { PseudoVWREDSUM_VS_M2_E8, 2764 }, |
5733 | | { PseudoVWREDSUM_VS_M4_E16, 2765 }, |
5734 | | { PseudoVWREDSUM_VS_M4_E32, 2766 }, |
5735 | | { PseudoVWREDSUM_VS_M4_E8, 2767 }, |
5736 | | { PseudoVWREDSUM_VS_M8_E16, 2768 }, |
5737 | | { PseudoVWREDSUM_VS_M8_E32, 2769 }, |
5738 | | { PseudoVWREDSUM_VS_M8_E8, 2770 }, |
5739 | | { PseudoVWREDSUM_VS_MF2_E16, 2771 }, |
5740 | | { PseudoVWREDSUM_VS_MF2_E32, 2772 }, |
5741 | | { PseudoVWREDSUM_VS_MF2_E8, 2773 }, |
5742 | | { PseudoVWREDSUM_VS_MF4_E16, 2774 }, |
5743 | | { PseudoVWREDSUM_VS_MF4_E8, 2775 }, |
5744 | | { PseudoVWREDSUM_VS_MF8_E8, 2776 }, |
5745 | | { PseudoVWSLL_VI_M1, 2777 }, |
5746 | | { PseudoVWSLL_VI_M2, 2778 }, |
5747 | | { PseudoVWSLL_VI_M4, 2779 }, |
5748 | | { PseudoVWSLL_VI_MF2, 2780 }, |
5749 | | { PseudoVWSLL_VI_MF4, 2781 }, |
5750 | | { PseudoVWSLL_VI_MF8, 2782 }, |
5751 | | { PseudoVWSLL_VV_M1, 2783 }, |
5752 | | { PseudoVWSLL_VV_M2, 2784 }, |
5753 | | { PseudoVWSLL_VV_M4, 2785 }, |
5754 | | { PseudoVWSLL_VV_MF2, 2786 }, |
5755 | | { PseudoVWSLL_VV_MF4, 2787 }, |
5756 | | { PseudoVWSLL_VV_MF8, 2788 }, |
5757 | | { PseudoVWSLL_VX_M1, 2789 }, |
5758 | | { PseudoVWSLL_VX_M2, 2790 }, |
5759 | | { PseudoVWSLL_VX_M4, 2791 }, |
5760 | | { PseudoVWSLL_VX_MF2, 2792 }, |
5761 | | { PseudoVWSLL_VX_MF4, 2793 }, |
5762 | | { PseudoVWSLL_VX_MF8, 2794 }, |
5763 | | { PseudoVWSUBU_VV_M1, 2795 }, |
5764 | | { PseudoVWSUBU_VV_M2, 2796 }, |
5765 | | { PseudoVWSUBU_VV_M4, 2797 }, |
5766 | | { PseudoVWSUBU_VV_MF2, 2798 }, |
5767 | | { PseudoVWSUBU_VV_MF4, 2799 }, |
5768 | | { PseudoVWSUBU_VV_MF8, 2800 }, |
5769 | | { PseudoVWSUBU_VX_M1, 2801 }, |
5770 | | { PseudoVWSUBU_VX_M2, 2802 }, |
5771 | | { PseudoVWSUBU_VX_M4, 2803 }, |
5772 | | { PseudoVWSUBU_VX_MF2, 2804 }, |
5773 | | { PseudoVWSUBU_VX_MF4, 2805 }, |
5774 | | { PseudoVWSUBU_VX_MF8, 2806 }, |
5775 | | { PseudoVWSUBU_WV_M1, 2807 }, |
5776 | | { PseudoVWSUBU_WV_M2, 2808 }, |
5777 | | { PseudoVWSUBU_WV_M4, 2809 }, |
5778 | | { PseudoVWSUBU_WV_MF2, 2810 }, |
5779 | | { PseudoVWSUBU_WV_MF4, 2811 }, |
5780 | | { PseudoVWSUBU_WV_MF8, 2812 }, |
5781 | | { PseudoVWSUBU_WX_M1, 2813 }, |
5782 | | { PseudoVWSUBU_WX_M2, 2814 }, |
5783 | | { PseudoVWSUBU_WX_M4, 2815 }, |
5784 | | { PseudoVWSUBU_WX_MF2, 2816 }, |
5785 | | { PseudoVWSUBU_WX_MF4, 2817 }, |
5786 | | { PseudoVWSUBU_WX_MF8, 2818 }, |
5787 | | { PseudoVWSUB_VV_M1, 2819 }, |
5788 | | { PseudoVWSUB_VV_M2, 2820 }, |
5789 | | { PseudoVWSUB_VV_M4, 2821 }, |
5790 | | { PseudoVWSUB_VV_MF2, 2822 }, |
5791 | | { PseudoVWSUB_VV_MF4, 2823 }, |
5792 | | { PseudoVWSUB_VV_MF8, 2824 }, |
5793 | | { PseudoVWSUB_VX_M1, 2825 }, |
5794 | | { PseudoVWSUB_VX_M2, 2826 }, |
5795 | | { PseudoVWSUB_VX_M4, 2827 }, |
5796 | | { PseudoVWSUB_VX_MF2, 2828 }, |
5797 | | { PseudoVWSUB_VX_MF4, 2829 }, |
5798 | | { PseudoVWSUB_VX_MF8, 2830 }, |
5799 | | { PseudoVWSUB_WV_M1, 2831 }, |
5800 | | { PseudoVWSUB_WV_M2, 2832 }, |
5801 | | { PseudoVWSUB_WV_M4, 2833 }, |
5802 | | { PseudoVWSUB_WV_MF2, 2834 }, |
5803 | | { PseudoVWSUB_WV_MF4, 2835 }, |
5804 | | { PseudoVWSUB_WV_MF8, 2836 }, |
5805 | | { PseudoVWSUB_WX_M1, 2837 }, |
5806 | | { PseudoVWSUB_WX_M2, 2838 }, |
5807 | | { PseudoVWSUB_WX_M4, 2839 }, |
5808 | | { PseudoVWSUB_WX_MF2, 2840 }, |
5809 | | { PseudoVWSUB_WX_MF4, 2841 }, |
5810 | | { PseudoVWSUB_WX_MF8, 2842 }, |
5811 | | { PseudoVXOR_VI_M1, 2843 }, |
5812 | | { PseudoVXOR_VI_M2, 2844 }, |
5813 | | { PseudoVXOR_VI_M4, 2845 }, |
5814 | | { PseudoVXOR_VI_M8, 2846 }, |
5815 | | { PseudoVXOR_VI_MF2, 2847 }, |
5816 | | { PseudoVXOR_VI_MF4, 2848 }, |
5817 | | { PseudoVXOR_VI_MF8, 2849 }, |
5818 | | { PseudoVXOR_VV_M1, 2850 }, |
5819 | | { PseudoVXOR_VV_M2, 2851 }, |
5820 | | { PseudoVXOR_VV_M4, 2852 }, |
5821 | | { PseudoVXOR_VV_M8, 2853 }, |
5822 | | { PseudoVXOR_VV_MF2, 2854 }, |
5823 | | { PseudoVXOR_VV_MF4, 2855 }, |
5824 | | { PseudoVXOR_VV_MF8, 2856 }, |
5825 | | { PseudoVXOR_VX_M1, 2857 }, |
5826 | | { PseudoVXOR_VX_M2, 2858 }, |
5827 | | { PseudoVXOR_VX_M4, 2859 }, |
5828 | | { PseudoVXOR_VX_M8, 2860 }, |
5829 | | { PseudoVXOR_VX_MF2, 2861 }, |
5830 | | { PseudoVXOR_VX_MF4, 2862 }, |
5831 | | { PseudoVXOR_VX_MF8, 2863 }, |
5832 | | { PseudoVZEXT_VF2_M1, 2864 }, |
5833 | | { PseudoVZEXT_VF2_M2, 2865 }, |
5834 | | { PseudoVZEXT_VF2_M4, 2866 }, |
5835 | | { PseudoVZEXT_VF2_M8, 2867 }, |
5836 | | { PseudoVZEXT_VF2_MF2, 2868 }, |
5837 | | { PseudoVZEXT_VF2_MF4, 2869 }, |
5838 | | { PseudoVZEXT_VF4_M1, 2870 }, |
5839 | | { PseudoVZEXT_VF4_M2, 2871 }, |
5840 | | { PseudoVZEXT_VF4_M4, 2872 }, |
5841 | | { PseudoVZEXT_VF4_M8, 2873 }, |
5842 | | { PseudoVZEXT_VF4_MF2, 2874 }, |
5843 | | { PseudoVZEXT_VF8_M1, 2875 }, |
5844 | | { PseudoVZEXT_VF8_M2, 2876 }, |
5845 | | { PseudoVZEXT_VF8_M4, 2877 }, |
5846 | | { PseudoVZEXT_VF8_M8, 2878 }, |
5847 | | }; |
5848 | | |
5849 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), UnmaskedPseudo); |
5850 | | if (i == -1) |
5851 | | return NULL; |
5852 | | else |
5853 | | return &RISCVMaskedPseudosTable[Index[i].index]; |
5854 | | } |
5855 | | |
5856 | | #endif |
5857 | | |
5858 | | #ifdef GET_RISCVOpcodesList_IMPL |
5859 | | static const RISCV_RISCVOpcode RISCVOpcodesList[] = { |
5860 | | { "LOAD", { .raw_val = RISCV_RISCVOPCODE_LOAD }, 0x3 }, // 0 |
5861 | | { "LOAD_FP", { .raw_val = RISCV_RISCVOPCODE_LOAD_FP }, 0x7 }, // 1 |
5862 | | { "CUSTOM_0", { .raw_val = RISCV_RISCVOPCODE_CUSTOM_0 }, 0xB }, // 2 |
5863 | | { "MISC_MEM", { .raw_val = RISCV_RISCVOPCODE_MISC_MEM }, 0xF }, // 3 |
5864 | | { "OP_IMM", { .raw_val = RISCV_RISCVOPCODE_OP_IMM }, 0x13 }, // 4 |
5865 | | { "AUIPC", { .raw_val = RISCV_RISCVOPCODE_AUIPC }, 0x17 }, // 5 |
5866 | | { "OP_IMM_32", { .raw_val = RISCV_RISCVOPCODE_OP_IMM_32 }, 0x1B }, // 6 |
5867 | | { "STORE", { .raw_val = RISCV_RISCVOPCODE_STORE }, 0x23 }, // 7 |
5868 | | { "STORE_FP", { .raw_val = RISCV_RISCVOPCODE_STORE_FP }, 0x27 }, // 8 |
5869 | | { "CUSTOM_1", { .raw_val = RISCV_RISCVOPCODE_CUSTOM_1 }, 0x2B }, // 9 |
5870 | | { "AMO", { .raw_val = RISCV_RISCVOPCODE_AMO }, 0x2F }, // 10 |
5871 | | { "OP", { .raw_val = RISCV_RISCVOPCODE_OP }, 0x33 }, // 11 |
5872 | | { "LUI", { .raw_val = RISCV_RISCVOPCODE_LUI }, 0x37 }, // 12 |
5873 | | { "OP_32", { .raw_val = RISCV_RISCVOPCODE_OP_32 }, 0x3B }, // 13 |
5874 | | { "MADD", { .raw_val = RISCV_RISCVOPCODE_MADD }, 0x43 }, // 14 |
5875 | | { "MSUB", { .raw_val = RISCV_RISCVOPCODE_MSUB }, 0x47 }, // 15 |
5876 | | { "NMSUB", { .raw_val = RISCV_RISCVOPCODE_NMSUB }, 0x4B }, // 16 |
5877 | | { "NMADD", { .raw_val = RISCV_RISCVOPCODE_NMADD }, 0x4F }, // 17 |
5878 | | { "OP_FP", { .raw_val = RISCV_RISCVOPCODE_OP_FP }, 0x53 }, // 18 |
5879 | | { "OP_V", { .raw_val = RISCV_RISCVOPCODE_OP_V }, 0x57 }, // 19 |
5880 | | { "CUSTOM_2", { .raw_val = RISCV_RISCVOPCODE_CUSTOM_2 }, 0x5B }, // 20 |
5881 | | { "BRANCH", { .raw_val = RISCV_RISCVOPCODE_BRANCH }, 0x63 }, // 21 |
5882 | | { "JALR", { .raw_val = RISCV_RISCVOPCODE_JALR }, 0x67 }, // 22 |
5883 | | { "JAL", { .raw_val = RISCV_RISCVOPCODE_JAL }, 0x6F }, // 23 |
5884 | | { "SYSTEM", { .raw_val = RISCV_RISCVOPCODE_SYSTEM }, 0x73 }, // 24 |
5885 | | { "OP_P", { .raw_val = RISCV_RISCVOPCODE_OP_P }, 0x77 }, // 25 |
5886 | | { "CUSTOM_3", { .raw_val = RISCV_RISCVOPCODE_CUSTOM_3 }, 0x7B }, // 26 |
5887 | | }; |
5888 | | |
5889 | | const RISCV_RISCVOpcode *RISCV_lookupRISCVOpcodeByValue(uint8_t Value) { |
5890 | | static const struct IndexType Index[] = { |
5891 | | {3,0}, |
5892 | | {7,1}, |
5893 | | {11,2}, |
5894 | | {15,3}, |
5895 | | {19,4}, |
5896 | | {23,5}, |
5897 | | {27,6}, |
5898 | | {35,7}, |
5899 | | {39,8}, |
5900 | | {43,9}, |
5901 | | {47,10}, |
5902 | | {51,11}, |
5903 | | {55,12}, |
5904 | | {59,13}, |
5905 | | {67,14}, |
5906 | | {71,15}, |
5907 | | {75,16}, |
5908 | | {79,17}, |
5909 | | {83,18}, |
5910 | | {87,19}, |
5911 | | {91,20}, |
5912 | | {99,21}, |
5913 | | {103,22}, |
5914 | | {111,23}, |
5915 | | {115,24}, |
5916 | | {119,25}, |
5917 | | {123,26}, |
5918 | | }; |
5919 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Value); |
5920 | | if (i == -1) |
5921 | | return NULL; |
5922 | | else |
5923 | | return &RISCVOpcodesList[Index[i].index]; |
5924 | | } |
5925 | | |
5926 | | const RISCV_RISCVOpcode *RISCV_lookupRISCVOpcodeByName(const char * Name) { |
5927 | | static const struct IndexTypeStr Index[] = { |
5928 | | { "AMO", 10 }, |
5929 | | { "AUIPC", 5 }, |
5930 | | { "BRANCH", 21 }, |
5931 | | { "CUSTOM_0", 2 }, |
5932 | | { "CUSTOM_1", 9 }, |
5933 | | { "CUSTOM_2", 20 }, |
5934 | | { "CUSTOM_3", 26 }, |
5935 | | { "JAL", 23 }, |
5936 | | { "JALR", 22 }, |
5937 | | { "LOAD", 0 }, |
5938 | | { "LOAD_FP", 1 }, |
5939 | | { "LUI", 12 }, |
5940 | | { "MADD", 14 }, |
5941 | | { "MISC_MEM", 3 }, |
5942 | | { "MSUB", 15 }, |
5943 | | { "NMADD", 17 }, |
5944 | | { "NMSUB", 16 }, |
5945 | | { "OP", 11 }, |
5946 | | { "OP_32", 13 }, |
5947 | | { "OP_FP", 18 }, |
5948 | | { "OP_IMM", 4 }, |
5949 | | { "OP_IMM_32", 6 }, |
5950 | | { "OP_P", 25 }, |
5951 | | { "OP_V", 19 }, |
5952 | | { "STORE", 7 }, |
5953 | | { "STORE_FP", 8 }, |
5954 | | { "SYSTEM", 24 }, |
5955 | | }; |
5956 | | |
5957 | | unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name); |
5958 | | if (i == -1) |
5959 | | return NULL; |
5960 | | else |
5961 | | return &RISCVOpcodesList[Index[i].index]; |
5962 | | } |
5963 | | |
5964 | | #endif |
5965 | | |
5966 | | #ifdef GET_RISCVTuneInfoTable_IMPL |
5967 | | static const RISCV_RISCVTuneInfo RISCVTuneInfoTable[] = { |
5968 | | { "generic", { .raw_val = RISCV_RISCVTUNEINFO_GENERIC }, 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5 }, // 0 |
5969 | | { "generic-rv32", { .raw_val = RISCV_RISCVTUNEINFO_GENERIC-RV32 }, 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5 }, // 1 |
5970 | | { "generic-rv64", { .raw_val = RISCV_RISCVTUNEINFO_GENERIC-RV64 }, 0x1, 0x1, 0x0, 0x0, 0x1, 0xFFFFFFFF, 0x5 }, // 2 |
5971 | | }; |
5972 | | |
5973 | | const RISCV_RISCVTuneInfo *RISCV_getRISCVTuneInfo(const char * Name) { |
5974 | | static const struct IndexTypeStr Index[] = { |
5975 | | { "GENERIC", 0 }, |
5976 | | { "GENERIC-RV32", 1 }, |
5977 | | { "GENERIC-RV64", 2 }, |
5978 | | }; |
5979 | | |
5980 | | unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name); |
5981 | | if (i == -1) |
5982 | | return NULL; |
5983 | | else |
5984 | | return &RISCVTuneInfoTable[Index[i].index]; |
5985 | | } |
5986 | | |
5987 | | #endif |
5988 | | |
5989 | | #ifdef GET_RISCVVInversePseudosTable_IMPL |
5990 | | static const RISCV_PseudoInfo RISCVVInversePseudosTable[] = { |
5991 | | { PseudoTHVdotVMAQASU_VV_M1, THVdotVMAQASU_VV, 0x0, 0x0 }, // 0 |
5992 | | { PseudoTHVdotVMAQASU_VV_M1_MASK, THVdotVMAQASU_VV, 0x0, 0x0 }, // 1 |
5993 | | { PseudoTHVdotVMAQASU_VV_M2, THVdotVMAQASU_VV, 0x1, 0x0 }, // 2 |
5994 | | { PseudoTHVdotVMAQASU_VV_M2_MASK, THVdotVMAQASU_VV, 0x1, 0x0 }, // 3 |
5995 | | { PseudoTHVdotVMAQASU_VV_M4, THVdotVMAQASU_VV, 0x2, 0x0 }, // 4 |
5996 | | { PseudoTHVdotVMAQASU_VV_M4_MASK, THVdotVMAQASU_VV, 0x2, 0x0 }, // 5 |
5997 | | { PseudoTHVdotVMAQASU_VV_M8, THVdotVMAQASU_VV, 0x3, 0x0 }, // 6 |
5998 | | { PseudoTHVdotVMAQASU_VV_M8_MASK, THVdotVMAQASU_VV, 0x3, 0x0 }, // 7 |
5999 | | { PseudoTHVdotVMAQASU_VV_MF2, THVdotVMAQASU_VV, 0x7, 0x0 }, // 8 |
6000 | | { PseudoTHVdotVMAQASU_VV_MF2_MASK, THVdotVMAQASU_VV, 0x7, 0x0 }, // 9 |
6001 | | { PseudoTHVdotVMAQASU_VX_M1, THVdotVMAQASU_VX, 0x0, 0x0 }, // 10 |
6002 | | { PseudoTHVdotVMAQASU_VX_M1_MASK, THVdotVMAQASU_VX, 0x0, 0x0 }, // 11 |
6003 | | { PseudoTHVdotVMAQASU_VX_M2, THVdotVMAQASU_VX, 0x1, 0x0 }, // 12 |
6004 | | { PseudoTHVdotVMAQASU_VX_M2_MASK, THVdotVMAQASU_VX, 0x1, 0x0 }, // 13 |
6005 | | { PseudoTHVdotVMAQASU_VX_M4, THVdotVMAQASU_VX, 0x2, 0x0 }, // 14 |
6006 | | { PseudoTHVdotVMAQASU_VX_M4_MASK, THVdotVMAQASU_VX, 0x2, 0x0 }, // 15 |
6007 | | { PseudoTHVdotVMAQASU_VX_M8, THVdotVMAQASU_VX, 0x3, 0x0 }, // 16 |
6008 | | { PseudoTHVdotVMAQASU_VX_M8_MASK, THVdotVMAQASU_VX, 0x3, 0x0 }, // 17 |
6009 | | { PseudoTHVdotVMAQASU_VX_MF2, THVdotVMAQASU_VX, 0x7, 0x0 }, // 18 |
6010 | | { PseudoTHVdotVMAQASU_VX_MF2_MASK, THVdotVMAQASU_VX, 0x7, 0x0 }, // 19 |
6011 | | { PseudoTHVdotVMAQAUS_VX_M1, THVdotVMAQAUS_VX, 0x0, 0x0 }, // 20 |
6012 | | { PseudoTHVdotVMAQAUS_VX_M1_MASK, THVdotVMAQAUS_VX, 0x0, 0x0 }, // 21 |
6013 | | { PseudoTHVdotVMAQAUS_VX_M2, THVdotVMAQAUS_VX, 0x1, 0x0 }, // 22 |
6014 | | { PseudoTHVdotVMAQAUS_VX_M2_MASK, THVdotVMAQAUS_VX, 0x1, 0x0 }, // 23 |
6015 | | { PseudoTHVdotVMAQAUS_VX_M4, THVdotVMAQAUS_VX, 0x2, 0x0 }, // 24 |
6016 | | { PseudoTHVdotVMAQAUS_VX_M4_MASK, THVdotVMAQAUS_VX, 0x2, 0x0 }, // 25 |
6017 | | { PseudoTHVdotVMAQAUS_VX_M8, THVdotVMAQAUS_VX, 0x3, 0x0 }, // 26 |
6018 | | { PseudoTHVdotVMAQAUS_VX_M8_MASK, THVdotVMAQAUS_VX, 0x3, 0x0 }, // 27 |
6019 | | { PseudoTHVdotVMAQAUS_VX_MF2, THVdotVMAQAUS_VX, 0x7, 0x0 }, // 28 |
6020 | | { PseudoTHVdotVMAQAUS_VX_MF2_MASK, THVdotVMAQAUS_VX, 0x7, 0x0 }, // 29 |
6021 | | { PseudoTHVdotVMAQAU_VV_M1, THVdotVMAQAU_VV, 0x0, 0x0 }, // 30 |
6022 | | { PseudoTHVdotVMAQAU_VV_M1_MASK, THVdotVMAQAU_VV, 0x0, 0x0 }, // 31 |
6023 | | { PseudoTHVdotVMAQAU_VV_M2, THVdotVMAQAU_VV, 0x1, 0x0 }, // 32 |
6024 | | { PseudoTHVdotVMAQAU_VV_M2_MASK, THVdotVMAQAU_VV, 0x1, 0x0 }, // 33 |
6025 | | { PseudoTHVdotVMAQAU_VV_M4, THVdotVMAQAU_VV, 0x2, 0x0 }, // 34 |
6026 | | { PseudoTHVdotVMAQAU_VV_M4_MASK, THVdotVMAQAU_VV, 0x2, 0x0 }, // 35 |
6027 | | { PseudoTHVdotVMAQAU_VV_M8, THVdotVMAQAU_VV, 0x3, 0x0 }, // 36 |
6028 | | { PseudoTHVdotVMAQAU_VV_M8_MASK, THVdotVMAQAU_VV, 0x3, 0x0 }, // 37 |
6029 | | { PseudoTHVdotVMAQAU_VV_MF2, THVdotVMAQAU_VV, 0x7, 0x0 }, // 38 |
6030 | | { PseudoTHVdotVMAQAU_VV_MF2_MASK, THVdotVMAQAU_VV, 0x7, 0x0 }, // 39 |
6031 | | { PseudoTHVdotVMAQAU_VX_M1, THVdotVMAQAU_VX, 0x0, 0x0 }, // 40 |
6032 | | { PseudoTHVdotVMAQAU_VX_M1_MASK, THVdotVMAQAU_VX, 0x0, 0x0 }, // 41 |
6033 | | { PseudoTHVdotVMAQAU_VX_M2, THVdotVMAQAU_VX, 0x1, 0x0 }, // 42 |
6034 | | { PseudoTHVdotVMAQAU_VX_M2_MASK, THVdotVMAQAU_VX, 0x1, 0x0 }, // 43 |
6035 | | { PseudoTHVdotVMAQAU_VX_M4, THVdotVMAQAU_VX, 0x2, 0x0 }, // 44 |
6036 | | { PseudoTHVdotVMAQAU_VX_M4_MASK, THVdotVMAQAU_VX, 0x2, 0x0 }, // 45 |
6037 | | { PseudoTHVdotVMAQAU_VX_M8, THVdotVMAQAU_VX, 0x3, 0x0 }, // 46 |
6038 | | { PseudoTHVdotVMAQAU_VX_M8_MASK, THVdotVMAQAU_VX, 0x3, 0x0 }, // 47 |
6039 | | { PseudoTHVdotVMAQAU_VX_MF2, THVdotVMAQAU_VX, 0x7, 0x0 }, // 48 |
6040 | | { PseudoTHVdotVMAQAU_VX_MF2_MASK, THVdotVMAQAU_VX, 0x7, 0x0 }, // 49 |
6041 | | { PseudoTHVdotVMAQA_VV_M1, THVdotVMAQA_VV, 0x0, 0x0 }, // 50 |
6042 | | { PseudoTHVdotVMAQA_VV_M1_MASK, THVdotVMAQA_VV, 0x0, 0x0 }, // 51 |
6043 | | { PseudoTHVdotVMAQA_VV_M2, THVdotVMAQA_VV, 0x1, 0x0 }, // 52 |
6044 | | { PseudoTHVdotVMAQA_VV_M2_MASK, THVdotVMAQA_VV, 0x1, 0x0 }, // 53 |
6045 | | { PseudoTHVdotVMAQA_VV_M4, THVdotVMAQA_VV, 0x2, 0x0 }, // 54 |
6046 | | { PseudoTHVdotVMAQA_VV_M4_MASK, THVdotVMAQA_VV, 0x2, 0x0 }, // 55 |
6047 | | { PseudoTHVdotVMAQA_VV_M8, THVdotVMAQA_VV, 0x3, 0x0 }, // 56 |
6048 | | { PseudoTHVdotVMAQA_VV_M8_MASK, THVdotVMAQA_VV, 0x3, 0x0 }, // 57 |
6049 | | { PseudoTHVdotVMAQA_VV_MF2, THVdotVMAQA_VV, 0x7, 0x0 }, // 58 |
6050 | | { PseudoTHVdotVMAQA_VV_MF2_MASK, THVdotVMAQA_VV, 0x7, 0x0 }, // 59 |
6051 | | { PseudoTHVdotVMAQA_VX_M1, THVdotVMAQA_VX, 0x0, 0x0 }, // 60 |
6052 | | { PseudoTHVdotVMAQA_VX_M1_MASK, THVdotVMAQA_VX, 0x0, 0x0 }, // 61 |
6053 | | { PseudoTHVdotVMAQA_VX_M2, THVdotVMAQA_VX, 0x1, 0x0 }, // 62 |
6054 | | { PseudoTHVdotVMAQA_VX_M2_MASK, THVdotVMAQA_VX, 0x1, 0x0 }, // 63 |
6055 | | { PseudoTHVdotVMAQA_VX_M4, THVdotVMAQA_VX, 0x2, 0x0 }, // 64 |
6056 | | { PseudoTHVdotVMAQA_VX_M4_MASK, THVdotVMAQA_VX, 0x2, 0x0 }, // 65 |
6057 | | { PseudoTHVdotVMAQA_VX_M8, THVdotVMAQA_VX, 0x3, 0x0 }, // 66 |
6058 | | { PseudoTHVdotVMAQA_VX_M8_MASK, THVdotVMAQA_VX, 0x3, 0x0 }, // 67 |
6059 | | { PseudoTHVdotVMAQA_VX_MF2, THVdotVMAQA_VX, 0x7, 0x0 }, // 68 |
6060 | | { PseudoTHVdotVMAQA_VX_MF2_MASK, THVdotVMAQA_VX, 0x7, 0x0 }, // 69 |
6061 | | { PseudoVAADDU_VV_M1, VAADDU_VV, 0x0, 0x0 }, // 70 |
6062 | | { PseudoVAADDU_VV_M1_MASK, VAADDU_VV, 0x0, 0x0 }, // 71 |
6063 | | { PseudoVAADDU_VV_M2, VAADDU_VV, 0x1, 0x0 }, // 72 |
6064 | | { PseudoVAADDU_VV_M2_MASK, VAADDU_VV, 0x1, 0x0 }, // 73 |
6065 | | { PseudoVAADDU_VV_M4, VAADDU_VV, 0x2, 0x0 }, // 74 |
6066 | | { PseudoVAADDU_VV_M4_MASK, VAADDU_VV, 0x2, 0x0 }, // 75 |
6067 | | { PseudoVAADDU_VV_M8, VAADDU_VV, 0x3, 0x0 }, // 76 |
6068 | | { PseudoVAADDU_VV_M8_MASK, VAADDU_VV, 0x3, 0x0 }, // 77 |
6069 | | { PseudoVAADDU_VV_MF8, VAADDU_VV, 0x5, 0x0 }, // 78 |
6070 | | { PseudoVAADDU_VV_MF8_MASK, VAADDU_VV, 0x5, 0x0 }, // 79 |
6071 | | { PseudoVAADDU_VV_MF4, VAADDU_VV, 0x6, 0x0 }, // 80 |
6072 | | { PseudoVAADDU_VV_MF4_MASK, VAADDU_VV, 0x6, 0x0 }, // 81 |
6073 | | { PseudoVAADDU_VV_MF2, VAADDU_VV, 0x7, 0x0 }, // 82 |
6074 | | { PseudoVAADDU_VV_MF2_MASK, VAADDU_VV, 0x7, 0x0 }, // 83 |
6075 | | { PseudoVAADDU_VX_M1, VAADDU_VX, 0x0, 0x0 }, // 84 |
6076 | | { PseudoVAADDU_VX_M1_MASK, VAADDU_VX, 0x0, 0x0 }, // 85 |
6077 | | { PseudoVAADDU_VX_M2, VAADDU_VX, 0x1, 0x0 }, // 86 |
6078 | | { PseudoVAADDU_VX_M2_MASK, VAADDU_VX, 0x1, 0x0 }, // 87 |
6079 | | { PseudoVAADDU_VX_M4, VAADDU_VX, 0x2, 0x0 }, // 88 |
6080 | | { PseudoVAADDU_VX_M4_MASK, VAADDU_VX, 0x2, 0x0 }, // 89 |
6081 | | { PseudoVAADDU_VX_M8, VAADDU_VX, 0x3, 0x0 }, // 90 |
6082 | | { PseudoVAADDU_VX_M8_MASK, VAADDU_VX, 0x3, 0x0 }, // 91 |
6083 | | { PseudoVAADDU_VX_MF8, VAADDU_VX, 0x5, 0x0 }, // 92 |
6084 | | { PseudoVAADDU_VX_MF8_MASK, VAADDU_VX, 0x5, 0x0 }, // 93 |
6085 | | { PseudoVAADDU_VX_MF4, VAADDU_VX, 0x6, 0x0 }, // 94 |
6086 | | { PseudoVAADDU_VX_MF4_MASK, VAADDU_VX, 0x6, 0x0 }, // 95 |
6087 | | { PseudoVAADDU_VX_MF2, VAADDU_VX, 0x7, 0x0 }, // 96 |
6088 | | { PseudoVAADDU_VX_MF2_MASK, VAADDU_VX, 0x7, 0x0 }, // 97 |
6089 | | { PseudoVAADD_VV_M1, VAADD_VV, 0x0, 0x0 }, // 98 |
6090 | | { PseudoVAADD_VV_M1_MASK, VAADD_VV, 0x0, 0x0 }, // 99 |
6091 | | { PseudoVAADD_VV_M2, VAADD_VV, 0x1, 0x0 }, // 100 |
6092 | | { PseudoVAADD_VV_M2_MASK, VAADD_VV, 0x1, 0x0 }, // 101 |
6093 | | { PseudoVAADD_VV_M4, VAADD_VV, 0x2, 0x0 }, // 102 |
6094 | | { PseudoVAADD_VV_M4_MASK, VAADD_VV, 0x2, 0x0 }, // 103 |
6095 | | { PseudoVAADD_VV_M8, VAADD_VV, 0x3, 0x0 }, // 104 |
6096 | | { PseudoVAADD_VV_M8_MASK, VAADD_VV, 0x3, 0x0 }, // 105 |
6097 | | { PseudoVAADD_VV_MF8, VAADD_VV, 0x5, 0x0 }, // 106 |
6098 | | { PseudoVAADD_VV_MF8_MASK, VAADD_VV, 0x5, 0x0 }, // 107 |
6099 | | { PseudoVAADD_VV_MF4, VAADD_VV, 0x6, 0x0 }, // 108 |
6100 | | { PseudoVAADD_VV_MF4_MASK, VAADD_VV, 0x6, 0x0 }, // 109 |
6101 | | { PseudoVAADD_VV_MF2, VAADD_VV, 0x7, 0x0 }, // 110 |
6102 | | { PseudoVAADD_VV_MF2_MASK, VAADD_VV, 0x7, 0x0 }, // 111 |
6103 | | { PseudoVAADD_VX_M1, VAADD_VX, 0x0, 0x0 }, // 112 |
6104 | | { PseudoVAADD_VX_M1_MASK, VAADD_VX, 0x0, 0x0 }, // 113 |
6105 | | { PseudoVAADD_VX_M2, VAADD_VX, 0x1, 0x0 }, // 114 |
6106 | | { PseudoVAADD_VX_M2_MASK, VAADD_VX, 0x1, 0x0 }, // 115 |
6107 | | { PseudoVAADD_VX_M4, VAADD_VX, 0x2, 0x0 }, // 116 |
6108 | | { PseudoVAADD_VX_M4_MASK, VAADD_VX, 0x2, 0x0 }, // 117 |
6109 | | { PseudoVAADD_VX_M8, VAADD_VX, 0x3, 0x0 }, // 118 |
6110 | | { PseudoVAADD_VX_M8_MASK, VAADD_VX, 0x3, 0x0 }, // 119 |
6111 | | { PseudoVAADD_VX_MF8, VAADD_VX, 0x5, 0x0 }, // 120 |
6112 | | { PseudoVAADD_VX_MF8_MASK, VAADD_VX, 0x5, 0x0 }, // 121 |
6113 | | { PseudoVAADD_VX_MF4, VAADD_VX, 0x6, 0x0 }, // 122 |
6114 | | { PseudoVAADD_VX_MF4_MASK, VAADD_VX, 0x6, 0x0 }, // 123 |
6115 | | { PseudoVAADD_VX_MF2, VAADD_VX, 0x7, 0x0 }, // 124 |
6116 | | { PseudoVAADD_VX_MF2_MASK, VAADD_VX, 0x7, 0x0 }, // 125 |
6117 | | { PseudoVADC_VIM_M1, VADC_VIM, 0x0, 0x0 }, // 126 |
6118 | | { PseudoVADC_VIM_M2, VADC_VIM, 0x1, 0x0 }, // 127 |
6119 | | { PseudoVADC_VIM_M4, VADC_VIM, 0x2, 0x0 }, // 128 |
6120 | | { PseudoVADC_VIM_M8, VADC_VIM, 0x3, 0x0 }, // 129 |
6121 | | { PseudoVADC_VIM_MF8, VADC_VIM, 0x5, 0x0 }, // 130 |
6122 | | { PseudoVADC_VIM_MF4, VADC_VIM, 0x6, 0x0 }, // 131 |
6123 | | { PseudoVADC_VIM_MF2, VADC_VIM, 0x7, 0x0 }, // 132 |
6124 | | { PseudoVADC_VVM_M1, VADC_VVM, 0x0, 0x0 }, // 133 |
6125 | | { PseudoVADC_VVM_M2, VADC_VVM, 0x1, 0x0 }, // 134 |
6126 | | { PseudoVADC_VVM_M4, VADC_VVM, 0x2, 0x0 }, // 135 |
6127 | | { PseudoVADC_VVM_M8, VADC_VVM, 0x3, 0x0 }, // 136 |
6128 | | { PseudoVADC_VVM_MF8, VADC_VVM, 0x5, 0x0 }, // 137 |
6129 | | { PseudoVADC_VVM_MF4, VADC_VVM, 0x6, 0x0 }, // 138 |
6130 | | { PseudoVADC_VVM_MF2, VADC_VVM, 0x7, 0x0 }, // 139 |
6131 | | { PseudoVADC_VXM_M1, VADC_VXM, 0x0, 0x0 }, // 140 |
6132 | | { PseudoVADC_VXM_M2, VADC_VXM, 0x1, 0x0 }, // 141 |
6133 | | { PseudoVADC_VXM_M4, VADC_VXM, 0x2, 0x0 }, // 142 |
6134 | | { PseudoVADC_VXM_M8, VADC_VXM, 0x3, 0x0 }, // 143 |
6135 | | { PseudoVADC_VXM_MF8, VADC_VXM, 0x5, 0x0 }, // 144 |
6136 | | { PseudoVADC_VXM_MF4, VADC_VXM, 0x6, 0x0 }, // 145 |
6137 | | { PseudoVADC_VXM_MF2, VADC_VXM, 0x7, 0x0 }, // 146 |
6138 | | { PseudoVADD_VI_M1, VADD_VI, 0x0, 0x0 }, // 147 |
6139 | | { PseudoVADD_VI_M1_MASK, VADD_VI, 0x0, 0x0 }, // 148 |
6140 | | { PseudoVADD_VI_M2, VADD_VI, 0x1, 0x0 }, // 149 |
6141 | | { PseudoVADD_VI_M2_MASK, VADD_VI, 0x1, 0x0 }, // 150 |
6142 | | { PseudoVADD_VI_M4, VADD_VI, 0x2, 0x0 }, // 151 |
6143 | | { PseudoVADD_VI_M4_MASK, VADD_VI, 0x2, 0x0 }, // 152 |
6144 | | { PseudoVADD_VI_M8, VADD_VI, 0x3, 0x0 }, // 153 |
6145 | | { PseudoVADD_VI_M8_MASK, VADD_VI, 0x3, 0x0 }, // 154 |
6146 | | { PseudoVADD_VI_MF8, VADD_VI, 0x5, 0x0 }, // 155 |
6147 | | { PseudoVADD_VI_MF8_MASK, VADD_VI, 0x5, 0x0 }, // 156 |
6148 | | { PseudoVADD_VI_MF4, VADD_VI, 0x6, 0x0 }, // 157 |
6149 | | { PseudoVADD_VI_MF4_MASK, VADD_VI, 0x6, 0x0 }, // 158 |
6150 | | { PseudoVADD_VI_MF2, VADD_VI, 0x7, 0x0 }, // 159 |
6151 | | { PseudoVADD_VI_MF2_MASK, VADD_VI, 0x7, 0x0 }, // 160 |
6152 | | { PseudoVADD_VV_M1, VADD_VV, 0x0, 0x0 }, // 161 |
6153 | | { PseudoVADD_VV_M1_MASK, VADD_VV, 0x0, 0x0 }, // 162 |
6154 | | { PseudoVADD_VV_M2, VADD_VV, 0x1, 0x0 }, // 163 |
6155 | | { PseudoVADD_VV_M2_MASK, VADD_VV, 0x1, 0x0 }, // 164 |
6156 | | { PseudoVADD_VV_M4, VADD_VV, 0x2, 0x0 }, // 165 |
6157 | | { PseudoVADD_VV_M4_MASK, VADD_VV, 0x2, 0x0 }, // 166 |
6158 | | { PseudoVADD_VV_M8, VADD_VV, 0x3, 0x0 }, // 167 |
6159 | | { PseudoVADD_VV_M8_MASK, VADD_VV, 0x3, 0x0 }, // 168 |
6160 | | { PseudoVADD_VV_MF8, VADD_VV, 0x5, 0x0 }, // 169 |
6161 | | { PseudoVADD_VV_MF8_MASK, VADD_VV, 0x5, 0x0 }, // 170 |
6162 | | { PseudoVADD_VV_MF4, VADD_VV, 0x6, 0x0 }, // 171 |
6163 | | { PseudoVADD_VV_MF4_MASK, VADD_VV, 0x6, 0x0 }, // 172 |
6164 | | { PseudoVADD_VV_MF2, VADD_VV, 0x7, 0x0 }, // 173 |
6165 | | { PseudoVADD_VV_MF2_MASK, VADD_VV, 0x7, 0x0 }, // 174 |
6166 | | { PseudoVADD_VX_M1, VADD_VX, 0x0, 0x0 }, // 175 |
6167 | | { PseudoVADD_VX_M1_MASK, VADD_VX, 0x0, 0x0 }, // 176 |
6168 | | { PseudoVADD_VX_M2, VADD_VX, 0x1, 0x0 }, // 177 |
6169 | | { PseudoVADD_VX_M2_MASK, VADD_VX, 0x1, 0x0 }, // 178 |
6170 | | { PseudoVADD_VX_M4, VADD_VX, 0x2, 0x0 }, // 179 |
6171 | | { PseudoVADD_VX_M4_MASK, VADD_VX, 0x2, 0x0 }, // 180 |
6172 | | { PseudoVADD_VX_M8, VADD_VX, 0x3, 0x0 }, // 181 |
6173 | | { PseudoVADD_VX_M8_MASK, VADD_VX, 0x3, 0x0 }, // 182 |
6174 | | { PseudoVADD_VX_MF8, VADD_VX, 0x5, 0x0 }, // 183 |
6175 | | { PseudoVADD_VX_MF8_MASK, VADD_VX, 0x5, 0x0 }, // 184 |
6176 | | { PseudoVADD_VX_MF4, VADD_VX, 0x6, 0x0 }, // 185 |
6177 | | { PseudoVADD_VX_MF4_MASK, VADD_VX, 0x6, 0x0 }, // 186 |
6178 | | { PseudoVADD_VX_MF2, VADD_VX, 0x7, 0x0 }, // 187 |
6179 | | { PseudoVADD_VX_MF2_MASK, VADD_VX, 0x7, 0x0 }, // 188 |
6180 | | { PseudoVAESDF_VS_M1_M1, VAESDF_VS, 0x0, 0x0 }, // 189 |
6181 | | { PseudoVAESDF_VS_M1_MF2, VAESDF_VS, 0x0, 0x0 }, // 190 |
6182 | | { PseudoVAESDF_VS_M1_MF4, VAESDF_VS, 0x0, 0x0 }, // 191 |
6183 | | { PseudoVAESDF_VS_M1_MF8, VAESDF_VS, 0x0, 0x0 }, // 192 |
6184 | | { PseudoVAESDF_VS_M2_M1, VAESDF_VS, 0x1, 0x0 }, // 193 |
6185 | | { PseudoVAESDF_VS_M2_M2, VAESDF_VS, 0x1, 0x0 }, // 194 |
6186 | | { PseudoVAESDF_VS_M2_MF2, VAESDF_VS, 0x1, 0x0 }, // 195 |
6187 | | { PseudoVAESDF_VS_M2_MF4, VAESDF_VS, 0x1, 0x0 }, // 196 |
6188 | | { PseudoVAESDF_VS_M2_MF8, VAESDF_VS, 0x1, 0x0 }, // 197 |
6189 | | { PseudoVAESDF_VS_M4_M1, VAESDF_VS, 0x2, 0x0 }, // 198 |
6190 | | { PseudoVAESDF_VS_M4_M2, VAESDF_VS, 0x2, 0x0 }, // 199 |
6191 | | { PseudoVAESDF_VS_M4_M4, VAESDF_VS, 0x2, 0x0 }, // 200 |
6192 | | { PseudoVAESDF_VS_M4_MF2, VAESDF_VS, 0x2, 0x0 }, // 201 |
6193 | | { PseudoVAESDF_VS_M4_MF4, VAESDF_VS, 0x2, 0x0 }, // 202 |
6194 | | { PseudoVAESDF_VS_M4_MF8, VAESDF_VS, 0x2, 0x0 }, // 203 |
6195 | | { PseudoVAESDF_VS_M8_M1, VAESDF_VS, 0x3, 0x0 }, // 204 |
6196 | | { PseudoVAESDF_VS_M8_M2, VAESDF_VS, 0x3, 0x0 }, // 205 |
6197 | | { PseudoVAESDF_VS_M8_M4, VAESDF_VS, 0x3, 0x0 }, // 206 |
6198 | | { PseudoVAESDF_VS_M8_MF2, VAESDF_VS, 0x3, 0x0 }, // 207 |
6199 | | { PseudoVAESDF_VS_M8_MF4, VAESDF_VS, 0x3, 0x0 }, // 208 |
6200 | | { PseudoVAESDF_VS_M8_MF8, VAESDF_VS, 0x3, 0x0 }, // 209 |
6201 | | { PseudoVAESDF_VS_MF2_MF2, VAESDF_VS, 0x7, 0x0 }, // 210 |
6202 | | { PseudoVAESDF_VS_MF2_MF4, VAESDF_VS, 0x7, 0x0 }, // 211 |
6203 | | { PseudoVAESDF_VS_MF2_MF8, VAESDF_VS, 0x7, 0x0 }, // 212 |
6204 | | { PseudoVAESDF_VV_M1, VAESDF_VV, 0x0, 0x0 }, // 213 |
6205 | | { PseudoVAESDF_VV_M2, VAESDF_VV, 0x1, 0x0 }, // 214 |
6206 | | { PseudoVAESDF_VV_M4, VAESDF_VV, 0x2, 0x0 }, // 215 |
6207 | | { PseudoVAESDF_VV_M8, VAESDF_VV, 0x3, 0x0 }, // 216 |
6208 | | { PseudoVAESDF_VV_MF2, VAESDF_VV, 0x7, 0x0 }, // 217 |
6209 | | { PseudoVAESDM_VS_M1_M1, VAESDM_VS, 0x0, 0x0 }, // 218 |
6210 | | { PseudoVAESDM_VS_M1_MF2, VAESDM_VS, 0x0, 0x0 }, // 219 |
6211 | | { PseudoVAESDM_VS_M1_MF4, VAESDM_VS, 0x0, 0x0 }, // 220 |
6212 | | { PseudoVAESDM_VS_M1_MF8, VAESDM_VS, 0x0, 0x0 }, // 221 |
6213 | | { PseudoVAESDM_VS_M2_M1, VAESDM_VS, 0x1, 0x0 }, // 222 |
6214 | | { PseudoVAESDM_VS_M2_M2, VAESDM_VS, 0x1, 0x0 }, // 223 |
6215 | | { PseudoVAESDM_VS_M2_MF2, VAESDM_VS, 0x1, 0x0 }, // 224 |
6216 | | { PseudoVAESDM_VS_M2_MF4, VAESDM_VS, 0x1, 0x0 }, // 225 |
6217 | | { PseudoVAESDM_VS_M2_MF8, VAESDM_VS, 0x1, 0x0 }, // 226 |
6218 | | { PseudoVAESDM_VS_M4_M1, VAESDM_VS, 0x2, 0x0 }, // 227 |
6219 | | { PseudoVAESDM_VS_M4_M2, VAESDM_VS, 0x2, 0x0 }, // 228 |
6220 | | { PseudoVAESDM_VS_M4_M4, VAESDM_VS, 0x2, 0x0 }, // 229 |
6221 | | { PseudoVAESDM_VS_M4_MF2, VAESDM_VS, 0x2, 0x0 }, // 230 |
6222 | | { PseudoVAESDM_VS_M4_MF4, VAESDM_VS, 0x2, 0x0 }, // 231 |
6223 | | { PseudoVAESDM_VS_M4_MF8, VAESDM_VS, 0x2, 0x0 }, // 232 |
6224 | | { PseudoVAESDM_VS_M8_M1, VAESDM_VS, 0x3, 0x0 }, // 233 |
6225 | | { PseudoVAESDM_VS_M8_M2, VAESDM_VS, 0x3, 0x0 }, // 234 |
6226 | | { PseudoVAESDM_VS_M8_M4, VAESDM_VS, 0x3, 0x0 }, // 235 |
6227 | | { PseudoVAESDM_VS_M8_MF2, VAESDM_VS, 0x3, 0x0 }, // 236 |
6228 | | { PseudoVAESDM_VS_M8_MF4, VAESDM_VS, 0x3, 0x0 }, // 237 |
6229 | | { PseudoVAESDM_VS_M8_MF8, VAESDM_VS, 0x3, 0x0 }, // 238 |
6230 | | { PseudoVAESDM_VS_MF2_MF2, VAESDM_VS, 0x7, 0x0 }, // 239 |
6231 | | { PseudoVAESDM_VS_MF2_MF4, VAESDM_VS, 0x7, 0x0 }, // 240 |
6232 | | { PseudoVAESDM_VS_MF2_MF8, VAESDM_VS, 0x7, 0x0 }, // 241 |
6233 | | { PseudoVAESDM_VV_M1, VAESDM_VV, 0x0, 0x0 }, // 242 |
6234 | | { PseudoVAESDM_VV_M2, VAESDM_VV, 0x1, 0x0 }, // 243 |
6235 | | { PseudoVAESDM_VV_M4, VAESDM_VV, 0x2, 0x0 }, // 244 |
6236 | | { PseudoVAESDM_VV_M8, VAESDM_VV, 0x3, 0x0 }, // 245 |
6237 | | { PseudoVAESDM_VV_MF2, VAESDM_VV, 0x7, 0x0 }, // 246 |
6238 | | { PseudoVAESEF_VS_M1_M1, VAESEF_VS, 0x0, 0x0 }, // 247 |
6239 | | { PseudoVAESEF_VS_M1_MF2, VAESEF_VS, 0x0, 0x0 }, // 248 |
6240 | | { PseudoVAESEF_VS_M1_MF4, VAESEF_VS, 0x0, 0x0 }, // 249 |
6241 | | { PseudoVAESEF_VS_M1_MF8, VAESEF_VS, 0x0, 0x0 }, // 250 |
6242 | | { PseudoVAESEF_VS_M2_M1, VAESEF_VS, 0x1, 0x0 }, // 251 |
6243 | | { PseudoVAESEF_VS_M2_M2, VAESEF_VS, 0x1, 0x0 }, // 252 |
6244 | | { PseudoVAESEF_VS_M2_MF2, VAESEF_VS, 0x1, 0x0 }, // 253 |
6245 | | { PseudoVAESEF_VS_M2_MF4, VAESEF_VS, 0x1, 0x0 }, // 254 |
6246 | | { PseudoVAESEF_VS_M2_MF8, VAESEF_VS, 0x1, 0x0 }, // 255 |
6247 | | { PseudoVAESEF_VS_M4_M1, VAESEF_VS, 0x2, 0x0 }, // 256 |
6248 | | { PseudoVAESEF_VS_M4_M2, VAESEF_VS, 0x2, 0x0 }, // 257 |
6249 | | { PseudoVAESEF_VS_M4_M4, VAESEF_VS, 0x2, 0x0 }, // 258 |
6250 | | { PseudoVAESEF_VS_M4_MF2, VAESEF_VS, 0x2, 0x0 }, // 259 |
6251 | | { PseudoVAESEF_VS_M4_MF4, VAESEF_VS, 0x2, 0x0 }, // 260 |
6252 | | { PseudoVAESEF_VS_M4_MF8, VAESEF_VS, 0x2, 0x0 }, // 261 |
6253 | | { PseudoVAESEF_VS_M8_M1, VAESEF_VS, 0x3, 0x0 }, // 262 |
6254 | | { PseudoVAESEF_VS_M8_M2, VAESEF_VS, 0x3, 0x0 }, // 263 |
6255 | | { PseudoVAESEF_VS_M8_M4, VAESEF_VS, 0x3, 0x0 }, // 264 |
6256 | | { PseudoVAESEF_VS_M8_MF2, VAESEF_VS, 0x3, 0x0 }, // 265 |
6257 | | { PseudoVAESEF_VS_M8_MF4, VAESEF_VS, 0x3, 0x0 }, // 266 |
6258 | | { PseudoVAESEF_VS_M8_MF8, VAESEF_VS, 0x3, 0x0 }, // 267 |
6259 | | { PseudoVAESEF_VS_MF2_MF2, VAESEF_VS, 0x7, 0x0 }, // 268 |
6260 | | { PseudoVAESEF_VS_MF2_MF4, VAESEF_VS, 0x7, 0x0 }, // 269 |
6261 | | { PseudoVAESEF_VS_MF2_MF8, VAESEF_VS, 0x7, 0x0 }, // 270 |
6262 | | { PseudoVAESEF_VV_M1, VAESEF_VV, 0x0, 0x0 }, // 271 |
6263 | | { PseudoVAESEF_VV_M2, VAESEF_VV, 0x1, 0x0 }, // 272 |
6264 | | { PseudoVAESEF_VV_M4, VAESEF_VV, 0x2, 0x0 }, // 273 |
6265 | | { PseudoVAESEF_VV_M8, VAESEF_VV, 0x3, 0x0 }, // 274 |
6266 | | { PseudoVAESEF_VV_MF2, VAESEF_VV, 0x7, 0x0 }, // 275 |
6267 | | { PseudoVAESEM_VS_M1_M1, VAESEM_VS, 0x0, 0x0 }, // 276 |
6268 | | { PseudoVAESEM_VS_M1_MF2, VAESEM_VS, 0x0, 0x0 }, // 277 |
6269 | | { PseudoVAESEM_VS_M1_MF4, VAESEM_VS, 0x0, 0x0 }, // 278 |
6270 | | { PseudoVAESEM_VS_M1_MF8, VAESEM_VS, 0x0, 0x0 }, // 279 |
6271 | | { PseudoVAESEM_VS_M2_M1, VAESEM_VS, 0x1, 0x0 }, // 280 |
6272 | | { PseudoVAESEM_VS_M2_M2, VAESEM_VS, 0x1, 0x0 }, // 281 |
6273 | | { PseudoVAESEM_VS_M2_MF2, VAESEM_VS, 0x1, 0x0 }, // 282 |
6274 | | { PseudoVAESEM_VS_M2_MF4, VAESEM_VS, 0x1, 0x0 }, // 283 |
6275 | | { PseudoVAESEM_VS_M2_MF8, VAESEM_VS, 0x1, 0x0 }, // 284 |
6276 | | { PseudoVAESEM_VS_M4_M1, VAESEM_VS, 0x2, 0x0 }, // 285 |
6277 | | { PseudoVAESEM_VS_M4_M2, VAESEM_VS, 0x2, 0x0 }, // 286 |
6278 | | { PseudoVAESEM_VS_M4_M4, VAESEM_VS, 0x2, 0x0 }, // 287 |
6279 | | { PseudoVAESEM_VS_M4_MF2, VAESEM_VS, 0x2, 0x0 }, // 288 |
6280 | | { PseudoVAESEM_VS_M4_MF4, VAESEM_VS, 0x2, 0x0 }, // 289 |
6281 | | { PseudoVAESEM_VS_M4_MF8, VAESEM_VS, 0x2, 0x0 }, // 290 |
6282 | | { PseudoVAESEM_VS_M8_M1, VAESEM_VS, 0x3, 0x0 }, // 291 |
6283 | | { PseudoVAESEM_VS_M8_M2, VAESEM_VS, 0x3, 0x0 }, // 292 |
6284 | | { PseudoVAESEM_VS_M8_M4, VAESEM_VS, 0x3, 0x0 }, // 293 |
6285 | | { PseudoVAESEM_VS_M8_MF2, VAESEM_VS, 0x3, 0x0 }, // 294 |
6286 | | { PseudoVAESEM_VS_M8_MF4, VAESEM_VS, 0x3, 0x0 }, // 295 |
6287 | | { PseudoVAESEM_VS_M8_MF8, VAESEM_VS, 0x3, 0x0 }, // 296 |
6288 | | { PseudoVAESEM_VS_MF2_MF2, VAESEM_VS, 0x7, 0x0 }, // 297 |
6289 | | { PseudoVAESEM_VS_MF2_MF4, VAESEM_VS, 0x7, 0x0 }, // 298 |
6290 | | { PseudoVAESEM_VS_MF2_MF8, VAESEM_VS, 0x7, 0x0 }, // 299 |
6291 | | { PseudoVAESEM_VV_M1, VAESEM_VV, 0x0, 0x0 }, // 300 |
6292 | | { PseudoVAESEM_VV_M2, VAESEM_VV, 0x1, 0x0 }, // 301 |
6293 | | { PseudoVAESEM_VV_M4, VAESEM_VV, 0x2, 0x0 }, // 302 |
6294 | | { PseudoVAESEM_VV_M8, VAESEM_VV, 0x3, 0x0 }, // 303 |
6295 | | { PseudoVAESEM_VV_MF2, VAESEM_VV, 0x7, 0x0 }, // 304 |
6296 | | { PseudoVAESKF1_VI_M1, VAESKF1_VI, 0x0, 0x0 }, // 305 |
6297 | | { PseudoVAESKF1_VI_M2, VAESKF1_VI, 0x1, 0x0 }, // 306 |
6298 | | { PseudoVAESKF1_VI_M4, VAESKF1_VI, 0x2, 0x0 }, // 307 |
6299 | | { PseudoVAESKF1_VI_M8, VAESKF1_VI, 0x3, 0x0 }, // 308 |
6300 | | { PseudoVAESKF1_VI_MF2, VAESKF1_VI, 0x7, 0x0 }, // 309 |
6301 | | { PseudoVAESKF2_VI_M1, VAESKF2_VI, 0x0, 0x0 }, // 310 |
6302 | | { PseudoVAESKF2_VI_M2, VAESKF2_VI, 0x1, 0x0 }, // 311 |
6303 | | { PseudoVAESKF2_VI_M4, VAESKF2_VI, 0x2, 0x0 }, // 312 |
6304 | | { PseudoVAESKF2_VI_M8, VAESKF2_VI, 0x3, 0x0 }, // 313 |
6305 | | { PseudoVAESKF2_VI_MF2, VAESKF2_VI, 0x7, 0x0 }, // 314 |
6306 | | { PseudoVAESZ_VS_M1_M1, VAESZ_VS, 0x0, 0x0 }, // 315 |
6307 | | { PseudoVAESZ_VS_M1_MF2, VAESZ_VS, 0x0, 0x0 }, // 316 |
6308 | | { PseudoVAESZ_VS_M1_MF4, VAESZ_VS, 0x0, 0x0 }, // 317 |
6309 | | { PseudoVAESZ_VS_M1_MF8, VAESZ_VS, 0x0, 0x0 }, // 318 |
6310 | | { PseudoVAESZ_VS_M2_M1, VAESZ_VS, 0x1, 0x0 }, // 319 |
6311 | | { PseudoVAESZ_VS_M2_M2, VAESZ_VS, 0x1, 0x0 }, // 320 |
6312 | | { PseudoVAESZ_VS_M2_MF2, VAESZ_VS, 0x1, 0x0 }, // 321 |
6313 | | { PseudoVAESZ_VS_M2_MF4, VAESZ_VS, 0x1, 0x0 }, // 322 |
6314 | | { PseudoVAESZ_VS_M2_MF8, VAESZ_VS, 0x1, 0x0 }, // 323 |
6315 | | { PseudoVAESZ_VS_M4_M1, VAESZ_VS, 0x2, 0x0 }, // 324 |
6316 | | { PseudoVAESZ_VS_M4_M2, VAESZ_VS, 0x2, 0x0 }, // 325 |
6317 | | { PseudoVAESZ_VS_M4_M4, VAESZ_VS, 0x2, 0x0 }, // 326 |
6318 | | { PseudoVAESZ_VS_M4_MF2, VAESZ_VS, 0x2, 0x0 }, // 327 |
6319 | | { PseudoVAESZ_VS_M4_MF4, VAESZ_VS, 0x2, 0x0 }, // 328 |
6320 | | { PseudoVAESZ_VS_M4_MF8, VAESZ_VS, 0x2, 0x0 }, // 329 |
6321 | | { PseudoVAESZ_VS_M8_M1, VAESZ_VS, 0x3, 0x0 }, // 330 |
6322 | | { PseudoVAESZ_VS_M8_M2, VAESZ_VS, 0x3, 0x0 }, // 331 |
6323 | | { PseudoVAESZ_VS_M8_M4, VAESZ_VS, 0x3, 0x0 }, // 332 |
6324 | | { PseudoVAESZ_VS_M8_MF2, VAESZ_VS, 0x3, 0x0 }, // 333 |
6325 | | { PseudoVAESZ_VS_M8_MF4, VAESZ_VS, 0x3, 0x0 }, // 334 |
6326 | | { PseudoVAESZ_VS_M8_MF8, VAESZ_VS, 0x3, 0x0 }, // 335 |
6327 | | { PseudoVAESZ_VS_MF2_MF2, VAESZ_VS, 0x7, 0x0 }, // 336 |
6328 | | { PseudoVAESZ_VS_MF2_MF4, VAESZ_VS, 0x7, 0x0 }, // 337 |
6329 | | { PseudoVAESZ_VS_MF2_MF8, VAESZ_VS, 0x7, 0x0 }, // 338 |
6330 | | { PseudoVANDN_VV_M1, VANDN_VV, 0x0, 0x0 }, // 339 |
6331 | | { PseudoVANDN_VV_M1_MASK, VANDN_VV, 0x0, 0x0 }, // 340 |
6332 | | { PseudoVANDN_VV_M2, VANDN_VV, 0x1, 0x0 }, // 341 |
6333 | | { PseudoVANDN_VV_M2_MASK, VANDN_VV, 0x1, 0x0 }, // 342 |
6334 | | { PseudoVANDN_VV_M4, VANDN_VV, 0x2, 0x0 }, // 343 |
6335 | | { PseudoVANDN_VV_M4_MASK, VANDN_VV, 0x2, 0x0 }, // 344 |
6336 | | { PseudoVANDN_VV_M8, VANDN_VV, 0x3, 0x0 }, // 345 |
6337 | | { PseudoVANDN_VV_M8_MASK, VANDN_VV, 0x3, 0x0 }, // 346 |
6338 | | { PseudoVANDN_VV_MF8, VANDN_VV, 0x5, 0x0 }, // 347 |
6339 | | { PseudoVANDN_VV_MF8_MASK, VANDN_VV, 0x5, 0x0 }, // 348 |
6340 | | { PseudoVANDN_VV_MF4, VANDN_VV, 0x6, 0x0 }, // 349 |
6341 | | { PseudoVANDN_VV_MF4_MASK, VANDN_VV, 0x6, 0x0 }, // 350 |
6342 | | { PseudoVANDN_VV_MF2, VANDN_VV, 0x7, 0x0 }, // 351 |
6343 | | { PseudoVANDN_VV_MF2_MASK, VANDN_VV, 0x7, 0x0 }, // 352 |
6344 | | { PseudoVANDN_VX_M1, VANDN_VX, 0x0, 0x0 }, // 353 |
6345 | | { PseudoVANDN_VX_M1_MASK, VANDN_VX, 0x0, 0x0 }, // 354 |
6346 | | { PseudoVANDN_VX_M2, VANDN_VX, 0x1, 0x0 }, // 355 |
6347 | | { PseudoVANDN_VX_M2_MASK, VANDN_VX, 0x1, 0x0 }, // 356 |
6348 | | { PseudoVANDN_VX_M4, VANDN_VX, 0x2, 0x0 }, // 357 |
6349 | | { PseudoVANDN_VX_M4_MASK, VANDN_VX, 0x2, 0x0 }, // 358 |
6350 | | { PseudoVANDN_VX_M8, VANDN_VX, 0x3, 0x0 }, // 359 |
6351 | | { PseudoVANDN_VX_M8_MASK, VANDN_VX, 0x3, 0x0 }, // 360 |
6352 | | { PseudoVANDN_VX_MF8, VANDN_VX, 0x5, 0x0 }, // 361 |
6353 | | { PseudoVANDN_VX_MF8_MASK, VANDN_VX, 0x5, 0x0 }, // 362 |
6354 | | { PseudoVANDN_VX_MF4, VANDN_VX, 0x6, 0x0 }, // 363 |
6355 | | { PseudoVANDN_VX_MF4_MASK, VANDN_VX, 0x6, 0x0 }, // 364 |
6356 | | { PseudoVANDN_VX_MF2, VANDN_VX, 0x7, 0x0 }, // 365 |
6357 | | { PseudoVANDN_VX_MF2_MASK, VANDN_VX, 0x7, 0x0 }, // 366 |
6358 | | { PseudoVAND_VI_M1, VAND_VI, 0x0, 0x0 }, // 367 |
6359 | | { PseudoVAND_VI_M1_MASK, VAND_VI, 0x0, 0x0 }, // 368 |
6360 | | { PseudoVAND_VI_M2, VAND_VI, 0x1, 0x0 }, // 369 |
6361 | | { PseudoVAND_VI_M2_MASK, VAND_VI, 0x1, 0x0 }, // 370 |
6362 | | { PseudoVAND_VI_M4, VAND_VI, 0x2, 0x0 }, // 371 |
6363 | | { PseudoVAND_VI_M4_MASK, VAND_VI, 0x2, 0x0 }, // 372 |
6364 | | { PseudoVAND_VI_M8, VAND_VI, 0x3, 0x0 }, // 373 |
6365 | | { PseudoVAND_VI_M8_MASK, VAND_VI, 0x3, 0x0 }, // 374 |
6366 | | { PseudoVAND_VI_MF8, VAND_VI, 0x5, 0x0 }, // 375 |
6367 | | { PseudoVAND_VI_MF8_MASK, VAND_VI, 0x5, 0x0 }, // 376 |
6368 | | { PseudoVAND_VI_MF4, VAND_VI, 0x6, 0x0 }, // 377 |
6369 | | { PseudoVAND_VI_MF4_MASK, VAND_VI, 0x6, 0x0 }, // 378 |
6370 | | { PseudoVAND_VI_MF2, VAND_VI, 0x7, 0x0 }, // 379 |
6371 | | { PseudoVAND_VI_MF2_MASK, VAND_VI, 0x7, 0x0 }, // 380 |
6372 | | { PseudoVAND_VV_M1, VAND_VV, 0x0, 0x0 }, // 381 |
6373 | | { PseudoVAND_VV_M1_MASK, VAND_VV, 0x0, 0x0 }, // 382 |
6374 | | { PseudoVAND_VV_M2, VAND_VV, 0x1, 0x0 }, // 383 |
6375 | | { PseudoVAND_VV_M2_MASK, VAND_VV, 0x1, 0x0 }, // 384 |
6376 | | { PseudoVAND_VV_M4, VAND_VV, 0x2, 0x0 }, // 385 |
6377 | | { PseudoVAND_VV_M4_MASK, VAND_VV, 0x2, 0x0 }, // 386 |
6378 | | { PseudoVAND_VV_M8, VAND_VV, 0x3, 0x0 }, // 387 |
6379 | | { PseudoVAND_VV_M8_MASK, VAND_VV, 0x3, 0x0 }, // 388 |
6380 | | { PseudoVAND_VV_MF8, VAND_VV, 0x5, 0x0 }, // 389 |
6381 | | { PseudoVAND_VV_MF8_MASK, VAND_VV, 0x5, 0x0 }, // 390 |
6382 | | { PseudoVAND_VV_MF4, VAND_VV, 0x6, 0x0 }, // 391 |
6383 | | { PseudoVAND_VV_MF4_MASK, VAND_VV, 0x6, 0x0 }, // 392 |
6384 | | { PseudoVAND_VV_MF2, VAND_VV, 0x7, 0x0 }, // 393 |
6385 | | { PseudoVAND_VV_MF2_MASK, VAND_VV, 0x7, 0x0 }, // 394 |
6386 | | { PseudoVAND_VX_M1, VAND_VX, 0x0, 0x0 }, // 395 |
6387 | | { PseudoVAND_VX_M1_MASK, VAND_VX, 0x0, 0x0 }, // 396 |
6388 | | { PseudoVAND_VX_M2, VAND_VX, 0x1, 0x0 }, // 397 |
6389 | | { PseudoVAND_VX_M2_MASK, VAND_VX, 0x1, 0x0 }, // 398 |
6390 | | { PseudoVAND_VX_M4, VAND_VX, 0x2, 0x0 }, // 399 |
6391 | | { PseudoVAND_VX_M4_MASK, VAND_VX, 0x2, 0x0 }, // 400 |
6392 | | { PseudoVAND_VX_M8, VAND_VX, 0x3, 0x0 }, // 401 |
6393 | | { PseudoVAND_VX_M8_MASK, VAND_VX, 0x3, 0x0 }, // 402 |
6394 | | { PseudoVAND_VX_MF8, VAND_VX, 0x5, 0x0 }, // 403 |
6395 | | { PseudoVAND_VX_MF8_MASK, VAND_VX, 0x5, 0x0 }, // 404 |
6396 | | { PseudoVAND_VX_MF4, VAND_VX, 0x6, 0x0 }, // 405 |
6397 | | { PseudoVAND_VX_MF4_MASK, VAND_VX, 0x6, 0x0 }, // 406 |
6398 | | { PseudoVAND_VX_MF2, VAND_VX, 0x7, 0x0 }, // 407 |
6399 | | { PseudoVAND_VX_MF2_MASK, VAND_VX, 0x7, 0x0 }, // 408 |
6400 | | { PseudoVASUBU_VV_M1, VASUBU_VV, 0x0, 0x0 }, // 409 |
6401 | | { PseudoVASUBU_VV_M1_MASK, VASUBU_VV, 0x0, 0x0 }, // 410 |
6402 | | { PseudoVASUBU_VV_M2, VASUBU_VV, 0x1, 0x0 }, // 411 |
6403 | | { PseudoVASUBU_VV_M2_MASK, VASUBU_VV, 0x1, 0x0 }, // 412 |
6404 | | { PseudoVASUBU_VV_M4, VASUBU_VV, 0x2, 0x0 }, // 413 |
6405 | | { PseudoVASUBU_VV_M4_MASK, VASUBU_VV, 0x2, 0x0 }, // 414 |
6406 | | { PseudoVASUBU_VV_M8, VASUBU_VV, 0x3, 0x0 }, // 415 |
6407 | | { PseudoVASUBU_VV_M8_MASK, VASUBU_VV, 0x3, 0x0 }, // 416 |
6408 | | { PseudoVASUBU_VV_MF8, VASUBU_VV, 0x5, 0x0 }, // 417 |
6409 | | { PseudoVASUBU_VV_MF8_MASK, VASUBU_VV, 0x5, 0x0 }, // 418 |
6410 | | { PseudoVASUBU_VV_MF4, VASUBU_VV, 0x6, 0x0 }, // 419 |
6411 | | { PseudoVASUBU_VV_MF4_MASK, VASUBU_VV, 0x6, 0x0 }, // 420 |
6412 | | { PseudoVASUBU_VV_MF2, VASUBU_VV, 0x7, 0x0 }, // 421 |
6413 | | { PseudoVASUBU_VV_MF2_MASK, VASUBU_VV, 0x7, 0x0 }, // 422 |
6414 | | { PseudoVASUBU_VX_M1, VASUBU_VX, 0x0, 0x0 }, // 423 |
6415 | | { PseudoVASUBU_VX_M1_MASK, VASUBU_VX, 0x0, 0x0 }, // 424 |
6416 | | { PseudoVASUBU_VX_M2, VASUBU_VX, 0x1, 0x0 }, // 425 |
6417 | | { PseudoVASUBU_VX_M2_MASK, VASUBU_VX, 0x1, 0x0 }, // 426 |
6418 | | { PseudoVASUBU_VX_M4, VASUBU_VX, 0x2, 0x0 }, // 427 |
6419 | | { PseudoVASUBU_VX_M4_MASK, VASUBU_VX, 0x2, 0x0 }, // 428 |
6420 | | { PseudoVASUBU_VX_M8, VASUBU_VX, 0x3, 0x0 }, // 429 |
6421 | | { PseudoVASUBU_VX_M8_MASK, VASUBU_VX, 0x3, 0x0 }, // 430 |
6422 | | { PseudoVASUBU_VX_MF8, VASUBU_VX, 0x5, 0x0 }, // 431 |
6423 | | { PseudoVASUBU_VX_MF8_MASK, VASUBU_VX, 0x5, 0x0 }, // 432 |
6424 | | { PseudoVASUBU_VX_MF4, VASUBU_VX, 0x6, 0x0 }, // 433 |
6425 | | { PseudoVASUBU_VX_MF4_MASK, VASUBU_VX, 0x6, 0x0 }, // 434 |
6426 | | { PseudoVASUBU_VX_MF2, VASUBU_VX, 0x7, 0x0 }, // 435 |
6427 | | { PseudoVASUBU_VX_MF2_MASK, VASUBU_VX, 0x7, 0x0 }, // 436 |
6428 | | { PseudoVASUB_VV_M1, VASUB_VV, 0x0, 0x0 }, // 437 |
6429 | | { PseudoVASUB_VV_M1_MASK, VASUB_VV, 0x0, 0x0 }, // 438 |
6430 | | { PseudoVASUB_VV_M2, VASUB_VV, 0x1, 0x0 }, // 439 |
6431 | | { PseudoVASUB_VV_M2_MASK, VASUB_VV, 0x1, 0x0 }, // 440 |
6432 | | { PseudoVASUB_VV_M4, VASUB_VV, 0x2, 0x0 }, // 441 |
6433 | | { PseudoVASUB_VV_M4_MASK, VASUB_VV, 0x2, 0x0 }, // 442 |
6434 | | { PseudoVASUB_VV_M8, VASUB_VV, 0x3, 0x0 }, // 443 |
6435 | | { PseudoVASUB_VV_M8_MASK, VASUB_VV, 0x3, 0x0 }, // 444 |
6436 | | { PseudoVASUB_VV_MF8, VASUB_VV, 0x5, 0x0 }, // 445 |
6437 | | { PseudoVASUB_VV_MF8_MASK, VASUB_VV, 0x5, 0x0 }, // 446 |
6438 | | { PseudoVASUB_VV_MF4, VASUB_VV, 0x6, 0x0 }, // 447 |
6439 | | { PseudoVASUB_VV_MF4_MASK, VASUB_VV, 0x6, 0x0 }, // 448 |
6440 | | { PseudoVASUB_VV_MF2, VASUB_VV, 0x7, 0x0 }, // 449 |
6441 | | { PseudoVASUB_VV_MF2_MASK, VASUB_VV, 0x7, 0x0 }, // 450 |
6442 | | { PseudoVASUB_VX_M1, VASUB_VX, 0x0, 0x0 }, // 451 |
6443 | | { PseudoVASUB_VX_M1_MASK, VASUB_VX, 0x0, 0x0 }, // 452 |
6444 | | { PseudoVASUB_VX_M2, VASUB_VX, 0x1, 0x0 }, // 453 |
6445 | | { PseudoVASUB_VX_M2_MASK, VASUB_VX, 0x1, 0x0 }, // 454 |
6446 | | { PseudoVASUB_VX_M4, VASUB_VX, 0x2, 0x0 }, // 455 |
6447 | | { PseudoVASUB_VX_M4_MASK, VASUB_VX, 0x2, 0x0 }, // 456 |
6448 | | { PseudoVASUB_VX_M8, VASUB_VX, 0x3, 0x0 }, // 457 |
6449 | | { PseudoVASUB_VX_M8_MASK, VASUB_VX, 0x3, 0x0 }, // 458 |
6450 | | { PseudoVASUB_VX_MF8, VASUB_VX, 0x5, 0x0 }, // 459 |
6451 | | { PseudoVASUB_VX_MF8_MASK, VASUB_VX, 0x5, 0x0 }, // 460 |
6452 | | { PseudoVASUB_VX_MF4, VASUB_VX, 0x6, 0x0 }, // 461 |
6453 | | { PseudoVASUB_VX_MF4_MASK, VASUB_VX, 0x6, 0x0 }, // 462 |
6454 | | { PseudoVASUB_VX_MF2, VASUB_VX, 0x7, 0x0 }, // 463 |
6455 | | { PseudoVASUB_VX_MF2_MASK, VASUB_VX, 0x7, 0x0 }, // 464 |
6456 | | { PseudoVBREV8_V_M1, VBREV8_V, 0x0, 0x0 }, // 465 |
6457 | | { PseudoVBREV8_V_M1_MASK, VBREV8_V, 0x0, 0x0 }, // 466 |
6458 | | { PseudoVBREV8_V_M2, VBREV8_V, 0x1, 0x0 }, // 467 |
6459 | | { PseudoVBREV8_V_M2_MASK, VBREV8_V, 0x1, 0x0 }, // 468 |
6460 | | { PseudoVBREV8_V_M4, VBREV8_V, 0x2, 0x0 }, // 469 |
6461 | | { PseudoVBREV8_V_M4_MASK, VBREV8_V, 0x2, 0x0 }, // 470 |
6462 | | { PseudoVBREV8_V_M8, VBREV8_V, 0x3, 0x0 }, // 471 |
6463 | | { PseudoVBREV8_V_M8_MASK, VBREV8_V, 0x3, 0x0 }, // 472 |
6464 | | { PseudoVBREV8_V_MF8, VBREV8_V, 0x5, 0x0 }, // 473 |
6465 | | { PseudoVBREV8_V_MF8_MASK, VBREV8_V, 0x5, 0x0 }, // 474 |
6466 | | { PseudoVBREV8_V_MF4, VBREV8_V, 0x6, 0x0 }, // 475 |
6467 | | { PseudoVBREV8_V_MF4_MASK, VBREV8_V, 0x6, 0x0 }, // 476 |
6468 | | { PseudoVBREV8_V_MF2, VBREV8_V, 0x7, 0x0 }, // 477 |
6469 | | { PseudoVBREV8_V_MF2_MASK, VBREV8_V, 0x7, 0x0 }, // 478 |
6470 | | { PseudoVBREV_V_M1, VBREV_V, 0x0, 0x0 }, // 479 |
6471 | | { PseudoVBREV_V_M1_MASK, VBREV_V, 0x0, 0x0 }, // 480 |
6472 | | { PseudoVBREV_V_M2, VBREV_V, 0x1, 0x0 }, // 481 |
6473 | | { PseudoVBREV_V_M2_MASK, VBREV_V, 0x1, 0x0 }, // 482 |
6474 | | { PseudoVBREV_V_M4, VBREV_V, 0x2, 0x0 }, // 483 |
6475 | | { PseudoVBREV_V_M4_MASK, VBREV_V, 0x2, 0x0 }, // 484 |
6476 | | { PseudoVBREV_V_M8, VBREV_V, 0x3, 0x0 }, // 485 |
6477 | | { PseudoVBREV_V_M8_MASK, VBREV_V, 0x3, 0x0 }, // 486 |
6478 | | { PseudoVBREV_V_MF8, VBREV_V, 0x5, 0x0 }, // 487 |
6479 | | { PseudoVBREV_V_MF8_MASK, VBREV_V, 0x5, 0x0 }, // 488 |
6480 | | { PseudoVBREV_V_MF4, VBREV_V, 0x6, 0x0 }, // 489 |
6481 | | { PseudoVBREV_V_MF4_MASK, VBREV_V, 0x6, 0x0 }, // 490 |
6482 | | { PseudoVBREV_V_MF2, VBREV_V, 0x7, 0x0 }, // 491 |
6483 | | { PseudoVBREV_V_MF2_MASK, VBREV_V, 0x7, 0x0 }, // 492 |
6484 | | { PseudoVCLMULH_VV_M1, VCLMULH_VV, 0x0, 0x0 }, // 493 |
6485 | | { PseudoVCLMULH_VV_M1_MASK, VCLMULH_VV, 0x0, 0x0 }, // 494 |
6486 | | { PseudoVCLMULH_VV_M2, VCLMULH_VV, 0x1, 0x0 }, // 495 |
6487 | | { PseudoVCLMULH_VV_M2_MASK, VCLMULH_VV, 0x1, 0x0 }, // 496 |
6488 | | { PseudoVCLMULH_VV_M4, VCLMULH_VV, 0x2, 0x0 }, // 497 |
6489 | | { PseudoVCLMULH_VV_M4_MASK, VCLMULH_VV, 0x2, 0x0 }, // 498 |
6490 | | { PseudoVCLMULH_VV_M8, VCLMULH_VV, 0x3, 0x0 }, // 499 |
6491 | | { PseudoVCLMULH_VV_M8_MASK, VCLMULH_VV, 0x3, 0x0 }, // 500 |
6492 | | { PseudoVCLMULH_VV_MF8, VCLMULH_VV, 0x5, 0x0 }, // 501 |
6493 | | { PseudoVCLMULH_VV_MF8_MASK, VCLMULH_VV, 0x5, 0x0 }, // 502 |
6494 | | { PseudoVCLMULH_VV_MF4, VCLMULH_VV, 0x6, 0x0 }, // 503 |
6495 | | { PseudoVCLMULH_VV_MF4_MASK, VCLMULH_VV, 0x6, 0x0 }, // 504 |
6496 | | { PseudoVCLMULH_VV_MF2, VCLMULH_VV, 0x7, 0x0 }, // 505 |
6497 | | { PseudoVCLMULH_VV_MF2_MASK, VCLMULH_VV, 0x7, 0x0 }, // 506 |
6498 | | { PseudoVCLMULH_VX_M1, VCLMULH_VX, 0x0, 0x0 }, // 507 |
6499 | | { PseudoVCLMULH_VX_M1_MASK, VCLMULH_VX, 0x0, 0x0 }, // 508 |
6500 | | { PseudoVCLMULH_VX_M2, VCLMULH_VX, 0x1, 0x0 }, // 509 |
6501 | | { PseudoVCLMULH_VX_M2_MASK, VCLMULH_VX, 0x1, 0x0 }, // 510 |
6502 | | { PseudoVCLMULH_VX_M4, VCLMULH_VX, 0x2, 0x0 }, // 511 |
6503 | | { PseudoVCLMULH_VX_M4_MASK, VCLMULH_VX, 0x2, 0x0 }, // 512 |
6504 | | { PseudoVCLMULH_VX_M8, VCLMULH_VX, 0x3, 0x0 }, // 513 |
6505 | | { PseudoVCLMULH_VX_M8_MASK, VCLMULH_VX, 0x3, 0x0 }, // 514 |
6506 | | { PseudoVCLMULH_VX_MF8, VCLMULH_VX, 0x5, 0x0 }, // 515 |
6507 | | { PseudoVCLMULH_VX_MF8_MASK, VCLMULH_VX, 0x5, 0x0 }, // 516 |
6508 | | { PseudoVCLMULH_VX_MF4, VCLMULH_VX, 0x6, 0x0 }, // 517 |
6509 | | { PseudoVCLMULH_VX_MF4_MASK, VCLMULH_VX, 0x6, 0x0 }, // 518 |
6510 | | { PseudoVCLMULH_VX_MF2, VCLMULH_VX, 0x7, 0x0 }, // 519 |
6511 | | { PseudoVCLMULH_VX_MF2_MASK, VCLMULH_VX, 0x7, 0x0 }, // 520 |
6512 | | { PseudoVCLMUL_VV_M1, VCLMUL_VV, 0x0, 0x0 }, // 521 |
6513 | | { PseudoVCLMUL_VV_M1_MASK, VCLMUL_VV, 0x0, 0x0 }, // 522 |
6514 | | { PseudoVCLMUL_VV_M2, VCLMUL_VV, 0x1, 0x0 }, // 523 |
6515 | | { PseudoVCLMUL_VV_M2_MASK, VCLMUL_VV, 0x1, 0x0 }, // 524 |
6516 | | { PseudoVCLMUL_VV_M4, VCLMUL_VV, 0x2, 0x0 }, // 525 |
6517 | | { PseudoVCLMUL_VV_M4_MASK, VCLMUL_VV, 0x2, 0x0 }, // 526 |
6518 | | { PseudoVCLMUL_VV_M8, VCLMUL_VV, 0x3, 0x0 }, // 527 |
6519 | | { PseudoVCLMUL_VV_M8_MASK, VCLMUL_VV, 0x3, 0x0 }, // 528 |
6520 | | { PseudoVCLMUL_VV_MF8, VCLMUL_VV, 0x5, 0x0 }, // 529 |
6521 | | { PseudoVCLMUL_VV_MF8_MASK, VCLMUL_VV, 0x5, 0x0 }, // 530 |
6522 | | { PseudoVCLMUL_VV_MF4, VCLMUL_VV, 0x6, 0x0 }, // 531 |
6523 | | { PseudoVCLMUL_VV_MF4_MASK, VCLMUL_VV, 0x6, 0x0 }, // 532 |
6524 | | { PseudoVCLMUL_VV_MF2, VCLMUL_VV, 0x7, 0x0 }, // 533 |
6525 | | { PseudoVCLMUL_VV_MF2_MASK, VCLMUL_VV, 0x7, 0x0 }, // 534 |
6526 | | { PseudoVCLMUL_VX_M1, VCLMUL_VX, 0x0, 0x0 }, // 535 |
6527 | | { PseudoVCLMUL_VX_M1_MASK, VCLMUL_VX, 0x0, 0x0 }, // 536 |
6528 | | { PseudoVCLMUL_VX_M2, VCLMUL_VX, 0x1, 0x0 }, // 537 |
6529 | | { PseudoVCLMUL_VX_M2_MASK, VCLMUL_VX, 0x1, 0x0 }, // 538 |
6530 | | { PseudoVCLMUL_VX_M4, VCLMUL_VX, 0x2, 0x0 }, // 539 |
6531 | | { PseudoVCLMUL_VX_M4_MASK, VCLMUL_VX, 0x2, 0x0 }, // 540 |
6532 | | { PseudoVCLMUL_VX_M8, VCLMUL_VX, 0x3, 0x0 }, // 541 |
6533 | | { PseudoVCLMUL_VX_M8_MASK, VCLMUL_VX, 0x3, 0x0 }, // 542 |
6534 | | { PseudoVCLMUL_VX_MF8, VCLMUL_VX, 0x5, 0x0 }, // 543 |
6535 | | { PseudoVCLMUL_VX_MF8_MASK, VCLMUL_VX, 0x5, 0x0 }, // 544 |
6536 | | { PseudoVCLMUL_VX_MF4, VCLMUL_VX, 0x6, 0x0 }, // 545 |
6537 | | { PseudoVCLMUL_VX_MF4_MASK, VCLMUL_VX, 0x6, 0x0 }, // 546 |
6538 | | { PseudoVCLMUL_VX_MF2, VCLMUL_VX, 0x7, 0x0 }, // 547 |
6539 | | { PseudoVCLMUL_VX_MF2_MASK, VCLMUL_VX, 0x7, 0x0 }, // 548 |
6540 | | { PseudoVCLZ_V_M1, VCLZ_V, 0x0, 0x0 }, // 549 |
6541 | | { PseudoVCLZ_V_M1_MASK, VCLZ_V, 0x0, 0x0 }, // 550 |
6542 | | { PseudoVCLZ_V_M2, VCLZ_V, 0x1, 0x0 }, // 551 |
6543 | | { PseudoVCLZ_V_M2_MASK, VCLZ_V, 0x1, 0x0 }, // 552 |
6544 | | { PseudoVCLZ_V_M4, VCLZ_V, 0x2, 0x0 }, // 553 |
6545 | | { PseudoVCLZ_V_M4_MASK, VCLZ_V, 0x2, 0x0 }, // 554 |
6546 | | { PseudoVCLZ_V_M8, VCLZ_V, 0x3, 0x0 }, // 555 |
6547 | | { PseudoVCLZ_V_M8_MASK, VCLZ_V, 0x3, 0x0 }, // 556 |
6548 | | { PseudoVCLZ_V_MF8, VCLZ_V, 0x5, 0x0 }, // 557 |
6549 | | { PseudoVCLZ_V_MF8_MASK, VCLZ_V, 0x5, 0x0 }, // 558 |
6550 | | { PseudoVCLZ_V_MF4, VCLZ_V, 0x6, 0x0 }, // 559 |
6551 | | { PseudoVCLZ_V_MF4_MASK, VCLZ_V, 0x6, 0x0 }, // 560 |
6552 | | { PseudoVCLZ_V_MF2, VCLZ_V, 0x7, 0x0 }, // 561 |
6553 | | { PseudoVCLZ_V_MF2_MASK, VCLZ_V, 0x7, 0x0 }, // 562 |
6554 | | { PseudoVCOMPRESS_VM_M1_E8, VCOMPRESS_VM, 0x0, 0x8 }, // 563 |
6555 | | { PseudoVCOMPRESS_VM_M1_E16, VCOMPRESS_VM, 0x0, 0x10 }, // 564 |
6556 | | { PseudoVCOMPRESS_VM_M1_E32, VCOMPRESS_VM, 0x0, 0x20 }, // 565 |
6557 | | { PseudoVCOMPRESS_VM_M1_E64, VCOMPRESS_VM, 0x0, 0x40 }, // 566 |
6558 | | { PseudoVCOMPRESS_VM_M2_E8, VCOMPRESS_VM, 0x1, 0x8 }, // 567 |
6559 | | { PseudoVCOMPRESS_VM_M2_E16, VCOMPRESS_VM, 0x1, 0x10 }, // 568 |
6560 | | { PseudoVCOMPRESS_VM_M2_E32, VCOMPRESS_VM, 0x1, 0x20 }, // 569 |
6561 | | { PseudoVCOMPRESS_VM_M2_E64, VCOMPRESS_VM, 0x1, 0x40 }, // 570 |
6562 | | { PseudoVCOMPRESS_VM_M4_E8, VCOMPRESS_VM, 0x2, 0x8 }, // 571 |
6563 | | { PseudoVCOMPRESS_VM_M4_E16, VCOMPRESS_VM, 0x2, 0x10 }, // 572 |
6564 | | { PseudoVCOMPRESS_VM_M4_E32, VCOMPRESS_VM, 0x2, 0x20 }, // 573 |
6565 | | { PseudoVCOMPRESS_VM_M4_E64, VCOMPRESS_VM, 0x2, 0x40 }, // 574 |
6566 | | { PseudoVCOMPRESS_VM_M8_E8, VCOMPRESS_VM, 0x3, 0x8 }, // 575 |
6567 | | { PseudoVCOMPRESS_VM_M8_E16, VCOMPRESS_VM, 0x3, 0x10 }, // 576 |
6568 | | { PseudoVCOMPRESS_VM_M8_E32, VCOMPRESS_VM, 0x3, 0x20 }, // 577 |
6569 | | { PseudoVCOMPRESS_VM_M8_E64, VCOMPRESS_VM, 0x3, 0x40 }, // 578 |
6570 | | { PseudoVCOMPRESS_VM_MF8_E8, VCOMPRESS_VM, 0x5, 0x8 }, // 579 |
6571 | | { PseudoVCOMPRESS_VM_MF4_E8, VCOMPRESS_VM, 0x6, 0x8 }, // 580 |
6572 | | { PseudoVCOMPRESS_VM_MF4_E16, VCOMPRESS_VM, 0x6, 0x10 }, // 581 |
6573 | | { PseudoVCOMPRESS_VM_MF2_E8, VCOMPRESS_VM, 0x7, 0x8 }, // 582 |
6574 | | { PseudoVCOMPRESS_VM_MF2_E16, VCOMPRESS_VM, 0x7, 0x10 }, // 583 |
6575 | | { PseudoVCOMPRESS_VM_MF2_E32, VCOMPRESS_VM, 0x7, 0x20 }, // 584 |
6576 | | { PseudoVCPOP_M_B8, VCPOP_M, 0x0, 0x0 }, // 585 |
6577 | | { PseudoVCPOP_M_B8_MASK, VCPOP_M, 0x0, 0x0 }, // 586 |
6578 | | { PseudoVCPOP_M_B16, VCPOP_M, 0x1, 0x0 }, // 587 |
6579 | | { PseudoVCPOP_M_B16_MASK, VCPOP_M, 0x1, 0x0 }, // 588 |
6580 | | { PseudoVCPOP_M_B32, VCPOP_M, 0x2, 0x0 }, // 589 |
6581 | | { PseudoVCPOP_M_B32_MASK, VCPOP_M, 0x2, 0x0 }, // 590 |
6582 | | { PseudoVCPOP_M_B64, VCPOP_M, 0x3, 0x0 }, // 591 |
6583 | | { PseudoVCPOP_M_B64_MASK, VCPOP_M, 0x3, 0x0 }, // 592 |
6584 | | { PseudoVCPOP_M_B1, VCPOP_M, 0x5, 0x0 }, // 593 |
6585 | | { PseudoVCPOP_M_B1_MASK, VCPOP_M, 0x5, 0x0 }, // 594 |
6586 | | { PseudoVCPOP_M_B2, VCPOP_M, 0x6, 0x0 }, // 595 |
6587 | | { PseudoVCPOP_M_B2_MASK, VCPOP_M, 0x6, 0x0 }, // 596 |
6588 | | { PseudoVCPOP_M_B4, VCPOP_M, 0x7, 0x0 }, // 597 |
6589 | | { PseudoVCPOP_M_B4_MASK, VCPOP_M, 0x7, 0x0 }, // 598 |
6590 | | { PseudoVCPOP_V_M1, VCPOP_V, 0x0, 0x0 }, // 599 |
6591 | | { PseudoVCPOP_V_M1_MASK, VCPOP_V, 0x0, 0x0 }, // 600 |
6592 | | { PseudoVCPOP_V_M2, VCPOP_V, 0x1, 0x0 }, // 601 |
6593 | | { PseudoVCPOP_V_M2_MASK, VCPOP_V, 0x1, 0x0 }, // 602 |
6594 | | { PseudoVCPOP_V_M4, VCPOP_V, 0x2, 0x0 }, // 603 |
6595 | | { PseudoVCPOP_V_M4_MASK, VCPOP_V, 0x2, 0x0 }, // 604 |
6596 | | { PseudoVCPOP_V_M8, VCPOP_V, 0x3, 0x0 }, // 605 |
6597 | | { PseudoVCPOP_V_M8_MASK, VCPOP_V, 0x3, 0x0 }, // 606 |
6598 | | { PseudoVCPOP_V_MF8, VCPOP_V, 0x5, 0x0 }, // 607 |
6599 | | { PseudoVCPOP_V_MF8_MASK, VCPOP_V, 0x5, 0x0 }, // 608 |
6600 | | { PseudoVCPOP_V_MF4, VCPOP_V, 0x6, 0x0 }, // 609 |
6601 | | { PseudoVCPOP_V_MF4_MASK, VCPOP_V, 0x6, 0x0 }, // 610 |
6602 | | { PseudoVCPOP_V_MF2, VCPOP_V, 0x7, 0x0 }, // 611 |
6603 | | { PseudoVCPOP_V_MF2_MASK, VCPOP_V, 0x7, 0x0 }, // 612 |
6604 | | { PseudoVCTZ_V_M1, VCTZ_V, 0x0, 0x0 }, // 613 |
6605 | | { PseudoVCTZ_V_M1_MASK, VCTZ_V, 0x0, 0x0 }, // 614 |
6606 | | { PseudoVCTZ_V_M2, VCTZ_V, 0x1, 0x0 }, // 615 |
6607 | | { PseudoVCTZ_V_M2_MASK, VCTZ_V, 0x1, 0x0 }, // 616 |
6608 | | { PseudoVCTZ_V_M4, VCTZ_V, 0x2, 0x0 }, // 617 |
6609 | | { PseudoVCTZ_V_M4_MASK, VCTZ_V, 0x2, 0x0 }, // 618 |
6610 | | { PseudoVCTZ_V_M8, VCTZ_V, 0x3, 0x0 }, // 619 |
6611 | | { PseudoVCTZ_V_M8_MASK, VCTZ_V, 0x3, 0x0 }, // 620 |
6612 | | { PseudoVCTZ_V_MF8, VCTZ_V, 0x5, 0x0 }, // 621 |
6613 | | { PseudoVCTZ_V_MF8_MASK, VCTZ_V, 0x5, 0x0 }, // 622 |
6614 | | { PseudoVCTZ_V_MF4, VCTZ_V, 0x6, 0x0 }, // 623 |
6615 | | { PseudoVCTZ_V_MF4_MASK, VCTZ_V, 0x6, 0x0 }, // 624 |
6616 | | { PseudoVCTZ_V_MF2, VCTZ_V, 0x7, 0x0 }, // 625 |
6617 | | { PseudoVCTZ_V_MF2_MASK, VCTZ_V, 0x7, 0x0 }, // 626 |
6618 | | { PseudoVC_FPR16V_SE_M1, VC_FV, 0x0, 0x0 }, // 627 |
6619 | | { PseudoVC_FPR32V_SE_M1, VC_FV, 0x0, 0x0 }, // 628 |
6620 | | { PseudoVC_FPR64V_SE_M1, VC_FV, 0x0, 0x0 }, // 629 |
6621 | | { PseudoVC_FPR16V_SE_M2, VC_FV, 0x1, 0x0 }, // 630 |
6622 | | { PseudoVC_FPR32V_SE_M2, VC_FV, 0x1, 0x0 }, // 631 |
6623 | | { PseudoVC_FPR64V_SE_M2, VC_FV, 0x1, 0x0 }, // 632 |
6624 | | { PseudoVC_FPR16V_SE_M4, VC_FV, 0x2, 0x0 }, // 633 |
6625 | | { PseudoVC_FPR32V_SE_M4, VC_FV, 0x2, 0x0 }, // 634 |
6626 | | { PseudoVC_FPR64V_SE_M4, VC_FV, 0x2, 0x0 }, // 635 |
6627 | | { PseudoVC_FPR16V_SE_M8, VC_FV, 0x3, 0x0 }, // 636 |
6628 | | { PseudoVC_FPR32V_SE_M8, VC_FV, 0x3, 0x0 }, // 637 |
6629 | | { PseudoVC_FPR64V_SE_M8, VC_FV, 0x3, 0x0 }, // 638 |
6630 | | { PseudoVC_FPR16V_SE_MF4, VC_FV, 0x6, 0x0 }, // 639 |
6631 | | { PseudoVC_FPR16V_SE_MF2, VC_FV, 0x7, 0x0 }, // 640 |
6632 | | { PseudoVC_FPR32V_SE_MF2, VC_FV, 0x7, 0x0 }, // 641 |
6633 | | { PseudoVC_FPR16VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 642 |
6634 | | { PseudoVC_FPR32VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 643 |
6635 | | { PseudoVC_FPR64VV_SE_M1, VC_FVV, 0x0, 0x0 }, // 644 |
6636 | | { PseudoVC_FPR16VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 645 |
6637 | | { PseudoVC_FPR32VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 646 |
6638 | | { PseudoVC_FPR64VV_SE_M2, VC_FVV, 0x1, 0x0 }, // 647 |
6639 | | { PseudoVC_FPR16VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 648 |
6640 | | { PseudoVC_FPR32VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 649 |
6641 | | { PseudoVC_FPR64VV_SE_M4, VC_FVV, 0x2, 0x0 }, // 650 |
6642 | | { PseudoVC_FPR16VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 651 |
6643 | | { PseudoVC_FPR32VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 652 |
6644 | | { PseudoVC_FPR64VV_SE_M8, VC_FVV, 0x3, 0x0 }, // 653 |
6645 | | { PseudoVC_FPR16VV_SE_MF4, VC_FVV, 0x6, 0x0 }, // 654 |
6646 | | { PseudoVC_FPR16VV_SE_MF2, VC_FVV, 0x7, 0x0 }, // 655 |
6647 | | { PseudoVC_FPR32VV_SE_MF2, VC_FVV, 0x7, 0x0 }, // 656 |
6648 | | { PseudoVC_FPR16VW_SE_M1, VC_FVW, 0x0, 0x0 }, // 657 |
6649 | | { PseudoVC_FPR32VW_SE_M1, VC_FVW, 0x0, 0x0 }, // 658 |
6650 | | { PseudoVC_FPR16VW_SE_M2, VC_FVW, 0x1, 0x0 }, // 659 |
6651 | | { PseudoVC_FPR32VW_SE_M2, VC_FVW, 0x1, 0x0 }, // 660 |
6652 | | { PseudoVC_FPR16VW_SE_M4, VC_FVW, 0x2, 0x0 }, // 661 |
6653 | | { PseudoVC_FPR32VW_SE_M4, VC_FVW, 0x2, 0x0 }, // 662 |
6654 | | { PseudoVC_FPR16VW_SE_M8, VC_FVW, 0x3, 0x0 }, // 663 |
6655 | | { PseudoVC_FPR32VW_SE_M8, VC_FVW, 0x3, 0x0 }, // 664 |
6656 | | { PseudoVC_FPR16VW_SE_MF4, VC_FVW, 0x6, 0x0 }, // 665 |
6657 | | { PseudoVC_FPR16VW_SE_MF2, VC_FVW, 0x7, 0x0 }, // 666 |
6658 | | { PseudoVC_FPR32VW_SE_MF2, VC_FVW, 0x7, 0x0 }, // 667 |
6659 | | { PseudoVC_I_SE_M1, VC_I, 0x0, 0x0 }, // 668 |
6660 | | { PseudoVC_I_SE_M2, VC_I, 0x1, 0x0 }, // 669 |
6661 | | { PseudoVC_I_SE_M4, VC_I, 0x2, 0x0 }, // 670 |
6662 | | { PseudoVC_I_SE_M8, VC_I, 0x3, 0x0 }, // 671 |
6663 | | { PseudoVC_I_SE_MF8, VC_I, 0x5, 0x0 }, // 672 |
6664 | | { PseudoVC_I_SE_MF4, VC_I, 0x6, 0x0 }, // 673 |
6665 | | { PseudoVC_I_SE_MF2, VC_I, 0x7, 0x0 }, // 674 |
6666 | | { PseudoVC_IV_SE_M1, VC_IV, 0x0, 0x0 }, // 675 |
6667 | | { PseudoVC_IV_SE_M2, VC_IV, 0x1, 0x0 }, // 676 |
6668 | | { PseudoVC_IV_SE_M4, VC_IV, 0x2, 0x0 }, // 677 |
6669 | | { PseudoVC_IV_SE_M8, VC_IV, 0x3, 0x0 }, // 678 |
6670 | | { PseudoVC_IV_SE_MF8, VC_IV, 0x5, 0x0 }, // 679 |
6671 | | { PseudoVC_IV_SE_MF4, VC_IV, 0x6, 0x0 }, // 680 |
6672 | | { PseudoVC_IV_SE_MF2, VC_IV, 0x7, 0x0 }, // 681 |
6673 | | { PseudoVC_IVV_SE_M1, VC_IVV, 0x0, 0x0 }, // 682 |
6674 | | { PseudoVC_IVV_SE_M2, VC_IVV, 0x1, 0x0 }, // 683 |
6675 | | { PseudoVC_IVV_SE_M4, VC_IVV, 0x2, 0x0 }, // 684 |
6676 | | { PseudoVC_IVV_SE_M8, VC_IVV, 0x3, 0x0 }, // 685 |
6677 | | { PseudoVC_IVV_SE_MF8, VC_IVV, 0x5, 0x0 }, // 686 |
6678 | | { PseudoVC_IVV_SE_MF4, VC_IVV, 0x6, 0x0 }, // 687 |
6679 | | { PseudoVC_IVV_SE_MF2, VC_IVV, 0x7, 0x0 }, // 688 |
6680 | | { PseudoVC_IVW_SE_M1, VC_IVW, 0x0, 0x0 }, // 689 |
6681 | | { PseudoVC_IVW_SE_M2, VC_IVW, 0x1, 0x0 }, // 690 |
6682 | | { PseudoVC_IVW_SE_M4, VC_IVW, 0x2, 0x0 }, // 691 |
6683 | | { PseudoVC_IVW_SE_MF8, VC_IVW, 0x5, 0x0 }, // 692 |
6684 | | { PseudoVC_IVW_SE_MF4, VC_IVW, 0x6, 0x0 }, // 693 |
6685 | | { PseudoVC_IVW_SE_MF2, VC_IVW, 0x7, 0x0 }, // 694 |
6686 | | { PseudoVC_VV_SE_M1, VC_VV, 0x0, 0x0 }, // 695 |
6687 | | { PseudoVC_VV_SE_M2, VC_VV, 0x1, 0x0 }, // 696 |
6688 | | { PseudoVC_VV_SE_M4, VC_VV, 0x2, 0x0 }, // 697 |
6689 | | { PseudoVC_VV_SE_M8, VC_VV, 0x3, 0x0 }, // 698 |
6690 | | { PseudoVC_VV_SE_MF8, VC_VV, 0x5, 0x0 }, // 699 |
6691 | | { PseudoVC_VV_SE_MF4, VC_VV, 0x6, 0x0 }, // 700 |
6692 | | { PseudoVC_VV_SE_MF2, VC_VV, 0x7, 0x0 }, // 701 |
6693 | | { PseudoVC_VVV_SE_M1, VC_VVV, 0x0, 0x0 }, // 702 |
6694 | | { PseudoVC_VVV_SE_M2, VC_VVV, 0x1, 0x0 }, // 703 |
6695 | | { PseudoVC_VVV_SE_M4, VC_VVV, 0x2, 0x0 }, // 704 |
6696 | | { PseudoVC_VVV_SE_M8, VC_VVV, 0x3, 0x0 }, // 705 |
6697 | | { PseudoVC_VVV_SE_MF8, VC_VVV, 0x5, 0x0 }, // 706 |
6698 | | { PseudoVC_VVV_SE_MF4, VC_VVV, 0x6, 0x0 }, // 707 |
6699 | | { PseudoVC_VVV_SE_MF2, VC_VVV, 0x7, 0x0 }, // 708 |
6700 | | { PseudoVC_VVW_SE_M1, VC_VVW, 0x0, 0x0 }, // 709 |
6701 | | { PseudoVC_VVW_SE_M2, VC_VVW, 0x1, 0x0 }, // 710 |
6702 | | { PseudoVC_VVW_SE_M4, VC_VVW, 0x2, 0x0 }, // 711 |
6703 | | { PseudoVC_VVW_SE_MF8, VC_VVW, 0x5, 0x0 }, // 712 |
6704 | | { PseudoVC_VVW_SE_MF4, VC_VVW, 0x6, 0x0 }, // 713 |
6705 | | { PseudoVC_VVW_SE_MF2, VC_VVW, 0x7, 0x0 }, // 714 |
6706 | | { PseudoVC_V_FPR16V_M1, VC_V_FV, 0x0, 0x0 }, // 715 |
6707 | | { PseudoVC_V_FPR16V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 716 |
6708 | | { PseudoVC_V_FPR32V_M1, VC_V_FV, 0x0, 0x0 }, // 717 |
6709 | | { PseudoVC_V_FPR32V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 718 |
6710 | | { PseudoVC_V_FPR64V_M1, VC_V_FV, 0x0, 0x0 }, // 719 |
6711 | | { PseudoVC_V_FPR64V_SE_M1, VC_V_FV, 0x0, 0x0 }, // 720 |
6712 | | { PseudoVC_V_FPR16V_M2, VC_V_FV, 0x1, 0x0 }, // 721 |
6713 | | { PseudoVC_V_FPR16V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 722 |
6714 | | { PseudoVC_V_FPR32V_M2, VC_V_FV, 0x1, 0x0 }, // 723 |
6715 | | { PseudoVC_V_FPR32V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 724 |
6716 | | { PseudoVC_V_FPR64V_M2, VC_V_FV, 0x1, 0x0 }, // 725 |
6717 | | { PseudoVC_V_FPR64V_SE_M2, VC_V_FV, 0x1, 0x0 }, // 726 |
6718 | | { PseudoVC_V_FPR16V_M4, VC_V_FV, 0x2, 0x0 }, // 727 |
6719 | | { PseudoVC_V_FPR16V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 728 |
6720 | | { PseudoVC_V_FPR32V_M4, VC_V_FV, 0x2, 0x0 }, // 729 |
6721 | | { PseudoVC_V_FPR32V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 730 |
6722 | | { PseudoVC_V_FPR64V_M4, VC_V_FV, 0x2, 0x0 }, // 731 |
6723 | | { PseudoVC_V_FPR64V_SE_M4, VC_V_FV, 0x2, 0x0 }, // 732 |
6724 | | { PseudoVC_V_FPR16V_M8, VC_V_FV, 0x3, 0x0 }, // 733 |
6725 | | { PseudoVC_V_FPR16V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 734 |
6726 | | { PseudoVC_V_FPR32V_M8, VC_V_FV, 0x3, 0x0 }, // 735 |
6727 | | { PseudoVC_V_FPR32V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 736 |
6728 | | { PseudoVC_V_FPR64V_M8, VC_V_FV, 0x3, 0x0 }, // 737 |
6729 | | { PseudoVC_V_FPR64V_SE_M8, VC_V_FV, 0x3, 0x0 }, // 738 |
6730 | | { PseudoVC_V_FPR16V_MF4, VC_V_FV, 0x6, 0x0 }, // 739 |
6731 | | { PseudoVC_V_FPR16V_SE_MF4, VC_V_FV, 0x6, 0x0 }, // 740 |
6732 | | { PseudoVC_V_FPR16V_MF2, VC_V_FV, 0x7, 0x0 }, // 741 |
6733 | | { PseudoVC_V_FPR16V_SE_MF2, VC_V_FV, 0x7, 0x0 }, // 742 |
6734 | | { PseudoVC_V_FPR32V_MF2, VC_V_FV, 0x7, 0x0 }, // 743 |
6735 | | { PseudoVC_V_FPR32V_SE_MF2, VC_V_FV, 0x7, 0x0 }, // 744 |
6736 | | { PseudoVC_V_FPR16VV_M1, VC_V_FVV, 0x0, 0x0 }, // 745 |
6737 | | { PseudoVC_V_FPR16VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 746 |
6738 | | { PseudoVC_V_FPR32VV_M1, VC_V_FVV, 0x0, 0x0 }, // 747 |
6739 | | { PseudoVC_V_FPR32VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 748 |
6740 | | { PseudoVC_V_FPR64VV_M1, VC_V_FVV, 0x0, 0x0 }, // 749 |
6741 | | { PseudoVC_V_FPR64VV_SE_M1, VC_V_FVV, 0x0, 0x0 }, // 750 |
6742 | | { PseudoVC_V_FPR16VV_M2, VC_V_FVV, 0x1, 0x0 }, // 751 |
6743 | | { PseudoVC_V_FPR16VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 752 |
6744 | | { PseudoVC_V_FPR32VV_M2, VC_V_FVV, 0x1, 0x0 }, // 753 |
6745 | | { PseudoVC_V_FPR32VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 754 |
6746 | | { PseudoVC_V_FPR64VV_M2, VC_V_FVV, 0x1, 0x0 }, // 755 |
6747 | | { PseudoVC_V_FPR64VV_SE_M2, VC_V_FVV, 0x1, 0x0 }, // 756 |
6748 | | { PseudoVC_V_FPR16VV_M4, VC_V_FVV, 0x2, 0x0 }, // 757 |
6749 | | { PseudoVC_V_FPR16VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 758 |
6750 | | { PseudoVC_V_FPR32VV_M4, VC_V_FVV, 0x2, 0x0 }, // 759 |
6751 | | { PseudoVC_V_FPR32VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 760 |
6752 | | { PseudoVC_V_FPR64VV_M4, VC_V_FVV, 0x2, 0x0 }, // 761 |
6753 | | { PseudoVC_V_FPR64VV_SE_M4, VC_V_FVV, 0x2, 0x0 }, // 762 |
6754 | | { PseudoVC_V_FPR16VV_M8, VC_V_FVV, 0x3, 0x0 }, // 763 |
6755 | | { PseudoVC_V_FPR16VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 764 |
6756 | | { PseudoVC_V_FPR32VV_M8, VC_V_FVV, 0x3, 0x0 }, // 765 |
6757 | | { PseudoVC_V_FPR32VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 766 |
6758 | | { PseudoVC_V_FPR64VV_M8, VC_V_FVV, 0x3, 0x0 }, // 767 |
6759 | | { PseudoVC_V_FPR64VV_SE_M8, VC_V_FVV, 0x3, 0x0 }, // 768 |
6760 | | { PseudoVC_V_FPR16VV_MF4, VC_V_FVV, 0x6, 0x0 }, // 769 |
6761 | | { PseudoVC_V_FPR16VV_SE_MF4, VC_V_FVV, 0x6, 0x0 }, // 770 |
6762 | | { PseudoVC_V_FPR16VV_MF2, VC_V_FVV, 0x7, 0x0 }, // 771 |
6763 | | { PseudoVC_V_FPR16VV_SE_MF2, VC_V_FVV, 0x7, 0x0 }, // 772 |
6764 | | { PseudoVC_V_FPR32VV_MF2, VC_V_FVV, 0x7, 0x0 }, // 773 |
6765 | | { PseudoVC_V_FPR32VV_SE_MF2, VC_V_FVV, 0x7, 0x0 }, // 774 |
6766 | | { PseudoVC_V_FPR16VW_M1, VC_V_FVW, 0x0, 0x0 }, // 775 |
6767 | | { PseudoVC_V_FPR16VW_SE_M1, VC_V_FVW, 0x0, 0x0 }, // 776 |
6768 | | { PseudoVC_V_FPR32VW_M1, VC_V_FVW, 0x0, 0x0 }, // 777 |
6769 | | { PseudoVC_V_FPR32VW_SE_M1, VC_V_FVW, 0x0, 0x0 }, // 778 |
6770 | | { PseudoVC_V_FPR16VW_M2, VC_V_FVW, 0x1, 0x0 }, // 779 |
6771 | | { PseudoVC_V_FPR16VW_SE_M2, VC_V_FVW, 0x1, 0x0 }, // 780 |
6772 | | { PseudoVC_V_FPR32VW_M2, VC_V_FVW, 0x1, 0x0 }, // 781 |
6773 | | { PseudoVC_V_FPR32VW_SE_M2, VC_V_FVW, 0x1, 0x0 }, // 782 |
6774 | | { PseudoVC_V_FPR16VW_M4, VC_V_FVW, 0x2, 0x0 }, // 783 |
6775 | | { PseudoVC_V_FPR16VW_SE_M4, VC_V_FVW, 0x2, 0x0 }, // 784 |
6776 | | { PseudoVC_V_FPR32VW_M4, VC_V_FVW, 0x2, 0x0 }, // 785 |
6777 | | { PseudoVC_V_FPR32VW_SE_M4, VC_V_FVW, 0x2, 0x0 }, // 786 |
6778 | | { PseudoVC_V_FPR16VW_M8, VC_V_FVW, 0x3, 0x0 }, // 787 |
6779 | | { PseudoVC_V_FPR16VW_SE_M8, VC_V_FVW, 0x3, 0x0 }, // 788 |
6780 | | { PseudoVC_V_FPR32VW_M8, VC_V_FVW, 0x3, 0x0 }, // 789 |
6781 | | { PseudoVC_V_FPR32VW_SE_M8, VC_V_FVW, 0x3, 0x0 }, // 790 |
6782 | | { PseudoVC_V_FPR16VW_MF4, VC_V_FVW, 0x6, 0x0 }, // 791 |
6783 | | { PseudoVC_V_FPR16VW_SE_MF4, VC_V_FVW, 0x6, 0x0 }, // 792 |
6784 | | { PseudoVC_V_FPR16VW_MF2, VC_V_FVW, 0x7, 0x0 }, // 793 |
6785 | | { PseudoVC_V_FPR16VW_SE_MF2, VC_V_FVW, 0x7, 0x0 }, // 794 |
6786 | | { PseudoVC_V_FPR32VW_MF2, VC_V_FVW, 0x7, 0x0 }, // 795 |
6787 | | { PseudoVC_V_FPR32VW_SE_MF2, VC_V_FVW, 0x7, 0x0 }, // 796 |
6788 | | { PseudoVC_V_I_M1, VC_V_I, 0x0, 0x0 }, // 797 |
6789 | | { PseudoVC_V_I_SE_M1, VC_V_I, 0x0, 0x0 }, // 798 |
6790 | | { PseudoVC_V_I_M2, VC_V_I, 0x1, 0x0 }, // 799 |
6791 | | { PseudoVC_V_I_SE_M2, VC_V_I, 0x1, 0x0 }, // 800 |
6792 | | { PseudoVC_V_I_M4, VC_V_I, 0x2, 0x0 }, // 801 |
6793 | | { PseudoVC_V_I_SE_M4, VC_V_I, 0x2, 0x0 }, // 802 |
6794 | | { PseudoVC_V_I_M8, VC_V_I, 0x3, 0x0 }, // 803 |
6795 | | { PseudoVC_V_I_SE_M8, VC_V_I, 0x3, 0x0 }, // 804 |
6796 | | { PseudoVC_V_I_MF8, VC_V_I, 0x5, 0x0 }, // 805 |
6797 | | { PseudoVC_V_I_SE_MF8, VC_V_I, 0x5, 0x0 }, // 806 |
6798 | | { PseudoVC_V_I_MF4, VC_V_I, 0x6, 0x0 }, // 807 |
6799 | | { PseudoVC_V_I_SE_MF4, VC_V_I, 0x6, 0x0 }, // 808 |
6800 | | { PseudoVC_V_I_MF2, VC_V_I, 0x7, 0x0 }, // 809 |
6801 | | { PseudoVC_V_I_SE_MF2, VC_V_I, 0x7, 0x0 }, // 810 |
6802 | | { PseudoVC_V_IV_M1, VC_V_IV, 0x0, 0x0 }, // 811 |
6803 | | { PseudoVC_V_IV_SE_M1, VC_V_IV, 0x0, 0x0 }, // 812 |
6804 | | { PseudoVC_V_IV_M2, VC_V_IV, 0x1, 0x0 }, // 813 |
6805 | | { PseudoVC_V_IV_SE_M2, VC_V_IV, 0x1, 0x0 }, // 814 |
6806 | | { PseudoVC_V_IV_M4, VC_V_IV, 0x2, 0x0 }, // 815 |
6807 | | { PseudoVC_V_IV_SE_M4, VC_V_IV, 0x2, 0x0 }, // 816 |
6808 | | { PseudoVC_V_IV_M8, VC_V_IV, 0x3, 0x0 }, // 817 |
6809 | | { PseudoVC_V_IV_SE_M8, VC_V_IV, 0x3, 0x0 }, // 818 |
6810 | | { PseudoVC_V_IV_MF8, VC_V_IV, 0x5, 0x0 }, // 819 |
6811 | | { PseudoVC_V_IV_SE_MF8, VC_V_IV, 0x5, 0x0 }, // 820 |
6812 | | { PseudoVC_V_IV_MF4, VC_V_IV, 0x6, 0x0 }, // 821 |
6813 | | { PseudoVC_V_IV_SE_MF4, VC_V_IV, 0x6, 0x0 }, // 822 |
6814 | | { PseudoVC_V_IV_MF2, VC_V_IV, 0x7, 0x0 }, // 823 |
6815 | | { PseudoVC_V_IV_SE_MF2, VC_V_IV, 0x7, 0x0 }, // 824 |
6816 | | { PseudoVC_V_IVV_M1, VC_V_IVV, 0x0, 0x0 }, // 825 |
6817 | | { PseudoVC_V_IVV_SE_M1, VC_V_IVV, 0x0, 0x0 }, // 826 |
6818 | | { PseudoVC_V_IVV_M2, VC_V_IVV, 0x1, 0x0 }, // 827 |
6819 | | { PseudoVC_V_IVV_SE_M2, VC_V_IVV, 0x1, 0x0 }, // 828 |
6820 | | { PseudoVC_V_IVV_M4, VC_V_IVV, 0x2, 0x0 }, // 829 |
6821 | | { PseudoVC_V_IVV_SE_M4, VC_V_IVV, 0x2, 0x0 }, // 830 |
6822 | | { PseudoVC_V_IVV_M8, VC_V_IVV, 0x3, 0x0 }, // 831 |
6823 | | { PseudoVC_V_IVV_SE_M8, VC_V_IVV, 0x3, 0x0 }, // 832 |
6824 | | { PseudoVC_V_IVV_MF8, VC_V_IVV, 0x5, 0x0 }, // 833 |
6825 | | { PseudoVC_V_IVV_SE_MF8, VC_V_IVV, 0x5, 0x0 }, // 834 |
6826 | | { PseudoVC_V_IVV_MF4, VC_V_IVV, 0x6, 0x0 }, // 835 |
6827 | | { PseudoVC_V_IVV_SE_MF4, VC_V_IVV, 0x6, 0x0 }, // 836 |
6828 | | { PseudoVC_V_IVV_MF2, VC_V_IVV, 0x7, 0x0 }, // 837 |
6829 | | { PseudoVC_V_IVV_SE_MF2, VC_V_IVV, 0x7, 0x0 }, // 838 |
6830 | | { PseudoVC_V_IVW_M1, VC_V_IVW, 0x0, 0x0 }, // 839 |
6831 | | { PseudoVC_V_IVW_SE_M1, VC_V_IVW, 0x0, 0x0 }, // 840 |
6832 | | { PseudoVC_V_IVW_M2, VC_V_IVW, 0x1, 0x0 }, // 841 |
6833 | | { PseudoVC_V_IVW_SE_M2, VC_V_IVW, 0x1, 0x0 }, // 842 |
6834 | | { PseudoVC_V_IVW_M4, VC_V_IVW, 0x2, 0x0 }, // 843 |
6835 | | { PseudoVC_V_IVW_SE_M4, VC_V_IVW, 0x2, 0x0 }, // 844 |
6836 | | { PseudoVC_V_IVW_MF8, VC_V_IVW, 0x5, 0x0 }, // 845 |
6837 | | { PseudoVC_V_IVW_SE_MF8, VC_V_IVW, 0x5, 0x0 }, // 846 |
6838 | | { PseudoVC_V_IVW_MF4, VC_V_IVW, 0x6, 0x0 }, // 847 |
6839 | | { PseudoVC_V_IVW_SE_MF4, VC_V_IVW, 0x6, 0x0 }, // 848 |
6840 | | { PseudoVC_V_IVW_MF2, VC_V_IVW, 0x7, 0x0 }, // 849 |
6841 | | { PseudoVC_V_IVW_SE_MF2, VC_V_IVW, 0x7, 0x0 }, // 850 |
6842 | | { PseudoVC_V_VV_M1, VC_V_VV, 0x0, 0x0 }, // 851 |
6843 | | { PseudoVC_V_VV_SE_M1, VC_V_VV, 0x0, 0x0 }, // 852 |
6844 | | { PseudoVC_V_VV_M2, VC_V_VV, 0x1, 0x0 }, // 853 |
6845 | | { PseudoVC_V_VV_SE_M2, VC_V_VV, 0x1, 0x0 }, // 854 |
6846 | | { PseudoVC_V_VV_M4, VC_V_VV, 0x2, 0x0 }, // 855 |
6847 | | { PseudoVC_V_VV_SE_M4, VC_V_VV, 0x2, 0x0 }, // 856 |
6848 | | { PseudoVC_V_VV_M8, VC_V_VV, 0x3, 0x0 }, // 857 |
6849 | | { PseudoVC_V_VV_SE_M8, VC_V_VV, 0x3, 0x0 }, // 858 |
6850 | | { PseudoVC_V_VV_MF8, VC_V_VV, 0x5, 0x0 }, // 859 |
6851 | | { PseudoVC_V_VV_SE_MF8, VC_V_VV, 0x5, 0x0 }, // 860 |
6852 | | { PseudoVC_V_VV_MF4, VC_V_VV, 0x6, 0x0 }, // 861 |
6853 | | { PseudoVC_V_VV_SE_MF4, VC_V_VV, 0x6, 0x0 }, // 862 |
6854 | | { PseudoVC_V_VV_MF2, VC_V_VV, 0x7, 0x0 }, // 863 |
6855 | | { PseudoVC_V_VV_SE_MF2, VC_V_VV, 0x7, 0x0 }, // 864 |
6856 | | { PseudoVC_V_VVV_M1, VC_V_VVV, 0x0, 0x0 }, // 865 |
6857 | | { PseudoVC_V_VVV_SE_M1, VC_V_VVV, 0x0, 0x0 }, // 866 |
6858 | | { PseudoVC_V_VVV_M2, VC_V_VVV, 0x1, 0x0 }, // 867 |
6859 | | { PseudoVC_V_VVV_SE_M2, VC_V_VVV, 0x1, 0x0 }, // 868 |
6860 | | { PseudoVC_V_VVV_M4, VC_V_VVV, 0x2, 0x0 }, // 869 |
6861 | | { PseudoVC_V_VVV_SE_M4, VC_V_VVV, 0x2, 0x0 }, // 870 |
6862 | | { PseudoVC_V_VVV_M8, VC_V_VVV, 0x3, 0x0 }, // 871 |
6863 | | { PseudoVC_V_VVV_SE_M8, VC_V_VVV, 0x3, 0x0 }, // 872 |
6864 | | { PseudoVC_V_VVV_MF8, VC_V_VVV, 0x5, 0x0 }, // 873 |
6865 | | { PseudoVC_V_VVV_SE_MF8, VC_V_VVV, 0x5, 0x0 }, // 874 |
6866 | | { PseudoVC_V_VVV_MF4, VC_V_VVV, 0x6, 0x0 }, // 875 |
6867 | | { PseudoVC_V_VVV_SE_MF4, VC_V_VVV, 0x6, 0x0 }, // 876 |
6868 | | { PseudoVC_V_VVV_MF2, VC_V_VVV, 0x7, 0x0 }, // 877 |
6869 | | { PseudoVC_V_VVV_SE_MF2, VC_V_VVV, 0x7, 0x0 }, // 878 |
6870 | | { PseudoVC_V_VVW_M1, VC_V_VVW, 0x0, 0x0 }, // 879 |
6871 | | { PseudoVC_V_VVW_SE_M1, VC_V_VVW, 0x0, 0x0 }, // 880 |
6872 | | { PseudoVC_V_VVW_M2, VC_V_VVW, 0x1, 0x0 }, // 881 |
6873 | | { PseudoVC_V_VVW_SE_M2, VC_V_VVW, 0x1, 0x0 }, // 882 |
6874 | | { PseudoVC_V_VVW_M4, VC_V_VVW, 0x2, 0x0 }, // 883 |
6875 | | { PseudoVC_V_VVW_SE_M4, VC_V_VVW, 0x2, 0x0 }, // 884 |
6876 | | { PseudoVC_V_VVW_MF8, VC_V_VVW, 0x5, 0x0 }, // 885 |
6877 | | { PseudoVC_V_VVW_SE_MF8, VC_V_VVW, 0x5, 0x0 }, // 886 |
6878 | | { PseudoVC_V_VVW_MF4, VC_V_VVW, 0x6, 0x0 }, // 887 |
6879 | | { PseudoVC_V_VVW_SE_MF4, VC_V_VVW, 0x6, 0x0 }, // 888 |
6880 | | { PseudoVC_V_VVW_MF2, VC_V_VVW, 0x7, 0x0 }, // 889 |
6881 | | { PseudoVC_V_VVW_SE_MF2, VC_V_VVW, 0x7, 0x0 }, // 890 |
6882 | | { PseudoVC_V_X_M1, VC_V_X, 0x0, 0x0 }, // 891 |
6883 | | { PseudoVC_V_X_SE_M1, VC_V_X, 0x0, 0x0 }, // 892 |
6884 | | { PseudoVC_V_X_M2, VC_V_X, 0x1, 0x0 }, // 893 |
6885 | | { PseudoVC_V_X_SE_M2, VC_V_X, 0x1, 0x0 }, // 894 |
6886 | | { PseudoVC_V_X_M4, VC_V_X, 0x2, 0x0 }, // 895 |
6887 | | { PseudoVC_V_X_SE_M4, VC_V_X, 0x2, 0x0 }, // 896 |
6888 | | { PseudoVC_V_X_M8, VC_V_X, 0x3, 0x0 }, // 897 |
6889 | | { PseudoVC_V_X_SE_M8, VC_V_X, 0x3, 0x0 }, // 898 |
6890 | | { PseudoVC_V_X_MF8, VC_V_X, 0x5, 0x0 }, // 899 |
6891 | | { PseudoVC_V_X_SE_MF8, VC_V_X, 0x5, 0x0 }, // 900 |
6892 | | { PseudoVC_V_X_MF4, VC_V_X, 0x6, 0x0 }, // 901 |
6893 | | { PseudoVC_V_X_SE_MF4, VC_V_X, 0x6, 0x0 }, // 902 |
6894 | | { PseudoVC_V_X_MF2, VC_V_X, 0x7, 0x0 }, // 903 |
6895 | | { PseudoVC_V_X_SE_MF2, VC_V_X, 0x7, 0x0 }, // 904 |
6896 | | { PseudoVC_V_XV_M1, VC_V_XV, 0x0, 0x0 }, // 905 |
6897 | | { PseudoVC_V_XV_SE_M1, VC_V_XV, 0x0, 0x0 }, // 906 |
6898 | | { PseudoVC_V_XV_M2, VC_V_XV, 0x1, 0x0 }, // 907 |
6899 | | { PseudoVC_V_XV_SE_M2, VC_V_XV, 0x1, 0x0 }, // 908 |
6900 | | { PseudoVC_V_XV_M4, VC_V_XV, 0x2, 0x0 }, // 909 |
6901 | | { PseudoVC_V_XV_SE_M4, VC_V_XV, 0x2, 0x0 }, // 910 |
6902 | | { PseudoVC_V_XV_M8, VC_V_XV, 0x3, 0x0 }, // 911 |
6903 | | { PseudoVC_V_XV_SE_M8, VC_V_XV, 0x3, 0x0 }, // 912 |
6904 | | { PseudoVC_V_XV_MF8, VC_V_XV, 0x5, 0x0 }, // 913 |
6905 | | { PseudoVC_V_XV_SE_MF8, VC_V_XV, 0x5, 0x0 }, // 914 |
6906 | | { PseudoVC_V_XV_MF4, VC_V_XV, 0x6, 0x0 }, // 915 |
6907 | | { PseudoVC_V_XV_SE_MF4, VC_V_XV, 0x6, 0x0 }, // 916 |
6908 | | { PseudoVC_V_XV_MF2, VC_V_XV, 0x7, 0x0 }, // 917 |
6909 | | { PseudoVC_V_XV_SE_MF2, VC_V_XV, 0x7, 0x0 }, // 918 |
6910 | | { PseudoVC_V_XVV_M1, VC_V_XVV, 0x0, 0x0 }, // 919 |
6911 | | { PseudoVC_V_XVV_SE_M1, VC_V_XVV, 0x0, 0x0 }, // 920 |
6912 | | { PseudoVC_V_XVV_M2, VC_V_XVV, 0x1, 0x0 }, // 921 |
6913 | | { PseudoVC_V_XVV_SE_M2, VC_V_XVV, 0x1, 0x0 }, // 922 |
6914 | | { PseudoVC_V_XVV_M4, VC_V_XVV, 0x2, 0x0 }, // 923 |
6915 | | { PseudoVC_V_XVV_SE_M4, VC_V_XVV, 0x2, 0x0 }, // 924 |
6916 | | { PseudoVC_V_XVV_M8, VC_V_XVV, 0x3, 0x0 }, // 925 |
6917 | | { PseudoVC_V_XVV_SE_M8, VC_V_XVV, 0x3, 0x0 }, // 926 |
6918 | | { PseudoVC_V_XVV_MF8, VC_V_XVV, 0x5, 0x0 }, // 927 |
6919 | | { PseudoVC_V_XVV_SE_MF8, VC_V_XVV, 0x5, 0x0 }, // 928 |
6920 | | { PseudoVC_V_XVV_MF4, VC_V_XVV, 0x6, 0x0 }, // 929 |
6921 | | { PseudoVC_V_XVV_SE_MF4, VC_V_XVV, 0x6, 0x0 }, // 930 |
6922 | | { PseudoVC_V_XVV_MF2, VC_V_XVV, 0x7, 0x0 }, // 931 |
6923 | | { PseudoVC_V_XVV_SE_MF2, VC_V_XVV, 0x7, 0x0 }, // 932 |
6924 | | { PseudoVC_V_XVW_M1, VC_V_XVW, 0x0, 0x0 }, // 933 |
6925 | | { PseudoVC_V_XVW_SE_M1, VC_V_XVW, 0x0, 0x0 }, // 934 |
6926 | | { PseudoVC_V_XVW_M2, VC_V_XVW, 0x1, 0x0 }, // 935 |
6927 | | { PseudoVC_V_XVW_SE_M2, VC_V_XVW, 0x1, 0x0 }, // 936 |
6928 | | { PseudoVC_V_XVW_M4, VC_V_XVW, 0x2, 0x0 }, // 937 |
6929 | | { PseudoVC_V_XVW_SE_M4, VC_V_XVW, 0x2, 0x0 }, // 938 |
6930 | | { PseudoVC_V_XVW_MF8, VC_V_XVW, 0x5, 0x0 }, // 939 |
6931 | | { PseudoVC_V_XVW_SE_MF8, VC_V_XVW, 0x5, 0x0 }, // 940 |
6932 | | { PseudoVC_V_XVW_MF4, VC_V_XVW, 0x6, 0x0 }, // 941 |
6933 | | { PseudoVC_V_XVW_SE_MF4, VC_V_XVW, 0x6, 0x0 }, // 942 |
6934 | | { PseudoVC_V_XVW_MF2, VC_V_XVW, 0x7, 0x0 }, // 943 |
6935 | | { PseudoVC_V_XVW_SE_MF2, VC_V_XVW, 0x7, 0x0 }, // 944 |
6936 | | { PseudoVC_X_SE_M1, VC_X, 0x0, 0x0 }, // 945 |
6937 | | { PseudoVC_X_SE_M2, VC_X, 0x1, 0x0 }, // 946 |
6938 | | { PseudoVC_X_SE_M4, VC_X, 0x2, 0x0 }, // 947 |
6939 | | { PseudoVC_X_SE_M8, VC_X, 0x3, 0x0 }, // 948 |
6940 | | { PseudoVC_X_SE_MF8, VC_X, 0x5, 0x0 }, // 949 |
6941 | | { PseudoVC_X_SE_MF4, VC_X, 0x6, 0x0 }, // 950 |
6942 | | { PseudoVC_X_SE_MF2, VC_X, 0x7, 0x0 }, // 951 |
6943 | | { PseudoVC_XV_SE_M1, VC_XV, 0x0, 0x0 }, // 952 |
6944 | | { PseudoVC_XV_SE_M2, VC_XV, 0x1, 0x0 }, // 953 |
6945 | | { PseudoVC_XV_SE_M4, VC_XV, 0x2, 0x0 }, // 954 |
6946 | | { PseudoVC_XV_SE_M8, VC_XV, 0x3, 0x0 }, // 955 |
6947 | | { PseudoVC_XV_SE_MF8, VC_XV, 0x5, 0x0 }, // 956 |
6948 | | { PseudoVC_XV_SE_MF4, VC_XV, 0x6, 0x0 }, // 957 |
6949 | | { PseudoVC_XV_SE_MF2, VC_XV, 0x7, 0x0 }, // 958 |
6950 | | { PseudoVC_XVV_SE_M1, VC_XVV, 0x0, 0x0 }, // 959 |
6951 | | { PseudoVC_XVV_SE_M2, VC_XVV, 0x1, 0x0 }, // 960 |
6952 | | { PseudoVC_XVV_SE_M4, VC_XVV, 0x2, 0x0 }, // 961 |
6953 | | { PseudoVC_XVV_SE_M8, VC_XVV, 0x3, 0x0 }, // 962 |
6954 | | { PseudoVC_XVV_SE_MF8, VC_XVV, 0x5, 0x0 }, // 963 |
6955 | | { PseudoVC_XVV_SE_MF4, VC_XVV, 0x6, 0x0 }, // 964 |
6956 | | { PseudoVC_XVV_SE_MF2, VC_XVV, 0x7, 0x0 }, // 965 |
6957 | | { PseudoVC_XVW_SE_M1, VC_XVW, 0x0, 0x0 }, // 966 |
6958 | | { PseudoVC_XVW_SE_M2, VC_XVW, 0x1, 0x0 }, // 967 |
6959 | | { PseudoVC_XVW_SE_M4, VC_XVW, 0x2, 0x0 }, // 968 |
6960 | | { PseudoVC_XVW_SE_MF8, VC_XVW, 0x5, 0x0 }, // 969 |
6961 | | { PseudoVC_XVW_SE_MF4, VC_XVW, 0x6, 0x0 }, // 970 |
6962 | | { PseudoVC_XVW_SE_MF2, VC_XVW, 0x7, 0x0 }, // 971 |
6963 | | { PseudoVDIVU_VV_M1_E8, VDIVU_VV, 0x0, 0x8 }, // 972 |
6964 | | { PseudoVDIVU_VV_M1_E8_MASK, VDIVU_VV, 0x0, 0x8 }, // 973 |
6965 | | { PseudoVDIVU_VV_M1_E16, VDIVU_VV, 0x0, 0x10 }, // 974 |
6966 | | { PseudoVDIVU_VV_M1_E16_MASK, VDIVU_VV, 0x0, 0x10 }, // 975 |
6967 | | { PseudoVDIVU_VV_M1_E32, VDIVU_VV, 0x0, 0x20 }, // 976 |
6968 | | { PseudoVDIVU_VV_M1_E32_MASK, VDIVU_VV, 0x0, 0x20 }, // 977 |
6969 | | { PseudoVDIVU_VV_M1_E64, VDIVU_VV, 0x0, 0x40 }, // 978 |
6970 | | { PseudoVDIVU_VV_M1_E64_MASK, VDIVU_VV, 0x0, 0x40 }, // 979 |
6971 | | { PseudoVDIVU_VV_M2_E8, VDIVU_VV, 0x1, 0x8 }, // 980 |
6972 | | { PseudoVDIVU_VV_M2_E8_MASK, VDIVU_VV, 0x1, 0x8 }, // 981 |
6973 | | { PseudoVDIVU_VV_M2_E16, VDIVU_VV, 0x1, 0x10 }, // 982 |
6974 | | { PseudoVDIVU_VV_M2_E16_MASK, VDIVU_VV, 0x1, 0x10 }, // 983 |
6975 | | { PseudoVDIVU_VV_M2_E32, VDIVU_VV, 0x1, 0x20 }, // 984 |
6976 | | { PseudoVDIVU_VV_M2_E32_MASK, VDIVU_VV, 0x1, 0x20 }, // 985 |
6977 | | { PseudoVDIVU_VV_M2_E64, VDIVU_VV, 0x1, 0x40 }, // 986 |
6978 | | { PseudoVDIVU_VV_M2_E64_MASK, VDIVU_VV, 0x1, 0x40 }, // 987 |
6979 | | { PseudoVDIVU_VV_M4_E8, VDIVU_VV, 0x2, 0x8 }, // 988 |
6980 | | { PseudoVDIVU_VV_M4_E8_MASK, VDIVU_VV, 0x2, 0x8 }, // 989 |
6981 | | { PseudoVDIVU_VV_M4_E16, VDIVU_VV, 0x2, 0x10 }, // 990 |
6982 | | { PseudoVDIVU_VV_M4_E16_MASK, VDIVU_VV, 0x2, 0x10 }, // 991 |
6983 | | { PseudoVDIVU_VV_M4_E32, VDIVU_VV, 0x2, 0x20 }, // 992 |
6984 | | { PseudoVDIVU_VV_M4_E32_MASK, VDIVU_VV, 0x2, 0x20 }, // 993 |
6985 | | { PseudoVDIVU_VV_M4_E64, VDIVU_VV, 0x2, 0x40 }, // 994 |
6986 | | { PseudoVDIVU_VV_M4_E64_MASK, VDIVU_VV, 0x2, 0x40 }, // 995 |
6987 | | { PseudoVDIVU_VV_M8_E8, VDIVU_VV, 0x3, 0x8 }, // 996 |
6988 | | { PseudoVDIVU_VV_M8_E8_MASK, VDIVU_VV, 0x3, 0x8 }, // 997 |
6989 | | { PseudoVDIVU_VV_M8_E16, VDIVU_VV, 0x3, 0x10 }, // 998 |
6990 | | { PseudoVDIVU_VV_M8_E16_MASK, VDIVU_VV, 0x3, 0x10 }, // 999 |
6991 | | { PseudoVDIVU_VV_M8_E32, VDIVU_VV, 0x3, 0x20 }, // 1000 |
6992 | | { PseudoVDIVU_VV_M8_E32_MASK, VDIVU_VV, 0x3, 0x20 }, // 1001 |
6993 | | { PseudoVDIVU_VV_M8_E64, VDIVU_VV, 0x3, 0x40 }, // 1002 |
6994 | | { PseudoVDIVU_VV_M8_E64_MASK, VDIVU_VV, 0x3, 0x40 }, // 1003 |
6995 | | { PseudoVDIVU_VV_MF8_E8, VDIVU_VV, 0x5, 0x8 }, // 1004 |
6996 | | { PseudoVDIVU_VV_MF8_E8_MASK, VDIVU_VV, 0x5, 0x8 }, // 1005 |
6997 | | { PseudoVDIVU_VV_MF4_E8, VDIVU_VV, 0x6, 0x8 }, // 1006 |
6998 | | { PseudoVDIVU_VV_MF4_E8_MASK, VDIVU_VV, 0x6, 0x8 }, // 1007 |
6999 | | { PseudoVDIVU_VV_MF4_E16, VDIVU_VV, 0x6, 0x10 }, // 1008 |
7000 | | { PseudoVDIVU_VV_MF4_E16_MASK, VDIVU_VV, 0x6, 0x10 }, // 1009 |
7001 | | { PseudoVDIVU_VV_MF2_E8, VDIVU_VV, 0x7, 0x8 }, // 1010 |
7002 | | { PseudoVDIVU_VV_MF2_E8_MASK, VDIVU_VV, 0x7, 0x8 }, // 1011 |
7003 | | { PseudoVDIVU_VV_MF2_E16, VDIVU_VV, 0x7, 0x10 }, // 1012 |
7004 | | { PseudoVDIVU_VV_MF2_E16_MASK, VDIVU_VV, 0x7, 0x10 }, // 1013 |
7005 | | { PseudoVDIVU_VV_MF2_E32, VDIVU_VV, 0x7, 0x20 }, // 1014 |
7006 | | { PseudoVDIVU_VV_MF2_E32_MASK, VDIVU_VV, 0x7, 0x20 }, // 1015 |
7007 | | { PseudoVDIVU_VX_M1_E8, VDIVU_VX, 0x0, 0x8 }, // 1016 |
7008 | | { PseudoVDIVU_VX_M1_E8_MASK, VDIVU_VX, 0x0, 0x8 }, // 1017 |
7009 | | { PseudoVDIVU_VX_M1_E16, VDIVU_VX, 0x0, 0x10 }, // 1018 |
7010 | | { PseudoVDIVU_VX_M1_E16_MASK, VDIVU_VX, 0x0, 0x10 }, // 1019 |
7011 | | { PseudoVDIVU_VX_M1_E32, VDIVU_VX, 0x0, 0x20 }, // 1020 |
7012 | | { PseudoVDIVU_VX_M1_E32_MASK, VDIVU_VX, 0x0, 0x20 }, // 1021 |
7013 | | { PseudoVDIVU_VX_M1_E64, VDIVU_VX, 0x0, 0x40 }, // 1022 |
7014 | | { PseudoVDIVU_VX_M1_E64_MASK, VDIVU_VX, 0x0, 0x40 }, // 1023 |
7015 | | { PseudoVDIVU_VX_M2_E8, VDIVU_VX, 0x1, 0x8 }, // 1024 |
7016 | | { PseudoVDIVU_VX_M2_E8_MASK, VDIVU_VX, 0x1, 0x8 }, // 1025 |
7017 | | { PseudoVDIVU_VX_M2_E16, VDIVU_VX, 0x1, 0x10 }, // 1026 |
7018 | | { PseudoVDIVU_VX_M2_E16_MASK, VDIVU_VX, 0x1, 0x10 }, // 1027 |
7019 | | { PseudoVDIVU_VX_M2_E32, VDIVU_VX, 0x1, 0x20 }, // 1028 |
7020 | | { PseudoVDIVU_VX_M2_E32_MASK, VDIVU_VX, 0x1, 0x20 }, // 1029 |
7021 | | { PseudoVDIVU_VX_M2_E64, VDIVU_VX, 0x1, 0x40 }, // 1030 |
7022 | | { PseudoVDIVU_VX_M2_E64_MASK, VDIVU_VX, 0x1, 0x40 }, // 1031 |
7023 | | { PseudoVDIVU_VX_M4_E8, VDIVU_VX, 0x2, 0x8 }, // 1032 |
7024 | | { PseudoVDIVU_VX_M4_E8_MASK, VDIVU_VX, 0x2, 0x8 }, // 1033 |
7025 | | { PseudoVDIVU_VX_M4_E16, VDIVU_VX, 0x2, 0x10 }, // 1034 |
7026 | | { PseudoVDIVU_VX_M4_E16_MASK, VDIVU_VX, 0x2, 0x10 }, // 1035 |
7027 | | { PseudoVDIVU_VX_M4_E32, VDIVU_VX, 0x2, 0x20 }, // 1036 |
7028 | | { PseudoVDIVU_VX_M4_E32_MASK, VDIVU_VX, 0x2, 0x20 }, // 1037 |
7029 | | { PseudoVDIVU_VX_M4_E64, VDIVU_VX, 0x2, 0x40 }, // 1038 |
7030 | | { PseudoVDIVU_VX_M4_E64_MASK, VDIVU_VX, 0x2, 0x40 }, // 1039 |
7031 | | { PseudoVDIVU_VX_M8_E8, VDIVU_VX, 0x3, 0x8 }, // 1040 |
7032 | | { PseudoVDIVU_VX_M8_E8_MASK, VDIVU_VX, 0x3, 0x8 }, // 1041 |
7033 | | { PseudoVDIVU_VX_M8_E16, VDIVU_VX, 0x3, 0x10 }, // 1042 |
7034 | | { PseudoVDIVU_VX_M8_E16_MASK, VDIVU_VX, 0x3, 0x10 }, // 1043 |
7035 | | { PseudoVDIVU_VX_M8_E32, VDIVU_VX, 0x3, 0x20 }, // 1044 |
7036 | | { PseudoVDIVU_VX_M8_E32_MASK, VDIVU_VX, 0x3, 0x20 }, // 1045 |
7037 | | { PseudoVDIVU_VX_M8_E64, VDIVU_VX, 0x3, 0x40 }, // 1046 |
7038 | | { PseudoVDIVU_VX_M8_E64_MASK, VDIVU_VX, 0x3, 0x40 }, // 1047 |
7039 | | { PseudoVDIVU_VX_MF8_E8, VDIVU_VX, 0x5, 0x8 }, // 1048 |
7040 | | { PseudoVDIVU_VX_MF8_E8_MASK, VDIVU_VX, 0x5, 0x8 }, // 1049 |
7041 | | { PseudoVDIVU_VX_MF4_E8, VDIVU_VX, 0x6, 0x8 }, // 1050 |
7042 | | { PseudoVDIVU_VX_MF4_E8_MASK, VDIVU_VX, 0x6, 0x8 }, // 1051 |
7043 | | { PseudoVDIVU_VX_MF4_E16, VDIVU_VX, 0x6, 0x10 }, // 1052 |
7044 | | { PseudoVDIVU_VX_MF4_E16_MASK, VDIVU_VX, 0x6, 0x10 }, // 1053 |
7045 | | { PseudoVDIVU_VX_MF2_E8, VDIVU_VX, 0x7, 0x8 }, // 1054 |
7046 | | { PseudoVDIVU_VX_MF2_E8_MASK, VDIVU_VX, 0x7, 0x8 }, // 1055 |
7047 | | { PseudoVDIVU_VX_MF2_E16, VDIVU_VX, 0x7, 0x10 }, // 1056 |
7048 | | { PseudoVDIVU_VX_MF2_E16_MASK, VDIVU_VX, 0x7, 0x10 }, // 1057 |
7049 | | { PseudoVDIVU_VX_MF2_E32, VDIVU_VX, 0x7, 0x20 }, // 1058 |
7050 | | { PseudoVDIVU_VX_MF2_E32_MASK, VDIVU_VX, 0x7, 0x20 }, // 1059 |
7051 | | { PseudoVDIV_VV_M1_E8, VDIV_VV, 0x0, 0x8 }, // 1060 |
7052 | | { PseudoVDIV_VV_M1_E8_MASK, VDIV_VV, 0x0, 0x8 }, // 1061 |
7053 | | { PseudoVDIV_VV_M1_E16, VDIV_VV, 0x0, 0x10 }, // 1062 |
7054 | | { PseudoVDIV_VV_M1_E16_MASK, VDIV_VV, 0x0, 0x10 }, // 1063 |
7055 | | { PseudoVDIV_VV_M1_E32, VDIV_VV, 0x0, 0x20 }, // 1064 |
7056 | | { PseudoVDIV_VV_M1_E32_MASK, VDIV_VV, 0x0, 0x20 }, // 1065 |
7057 | | { PseudoVDIV_VV_M1_E64, VDIV_VV, 0x0, 0x40 }, // 1066 |
7058 | | { PseudoVDIV_VV_M1_E64_MASK, VDIV_VV, 0x0, 0x40 }, // 1067 |
7059 | | { PseudoVDIV_VV_M2_E8, VDIV_VV, 0x1, 0x8 }, // 1068 |
7060 | | { PseudoVDIV_VV_M2_E8_MASK, VDIV_VV, 0x1, 0x8 }, // 1069 |
7061 | | { PseudoVDIV_VV_M2_E16, VDIV_VV, 0x1, 0x10 }, // 1070 |
7062 | | { PseudoVDIV_VV_M2_E16_MASK, VDIV_VV, 0x1, 0x10 }, // 1071 |
7063 | | { PseudoVDIV_VV_M2_E32, VDIV_VV, 0x1, 0x20 }, // 1072 |
7064 | | { PseudoVDIV_VV_M2_E32_MASK, VDIV_VV, 0x1, 0x20 }, // 1073 |
7065 | | { PseudoVDIV_VV_M2_E64, VDIV_VV, 0x1, 0x40 }, // 1074 |
7066 | | { PseudoVDIV_VV_M2_E64_MASK, VDIV_VV, 0x1, 0x40 }, // 1075 |
7067 | | { PseudoVDIV_VV_M4_E8, VDIV_VV, 0x2, 0x8 }, // 1076 |
7068 | | { PseudoVDIV_VV_M4_E8_MASK, VDIV_VV, 0x2, 0x8 }, // 1077 |
7069 | | { PseudoVDIV_VV_M4_E16, VDIV_VV, 0x2, 0x10 }, // 1078 |
7070 | | { PseudoVDIV_VV_M4_E16_MASK, VDIV_VV, 0x2, 0x10 }, // 1079 |
7071 | | { PseudoVDIV_VV_M4_E32, VDIV_VV, 0x2, 0x20 }, // 1080 |
7072 | | { PseudoVDIV_VV_M4_E32_MASK, VDIV_VV, 0x2, 0x20 }, // 1081 |
7073 | | { PseudoVDIV_VV_M4_E64, VDIV_VV, 0x2, 0x40 }, // 1082 |
7074 | | { PseudoVDIV_VV_M4_E64_MASK, VDIV_VV, 0x2, 0x40 }, // 1083 |
7075 | | { PseudoVDIV_VV_M8_E8, VDIV_VV, 0x3, 0x8 }, // 1084 |
7076 | | { PseudoVDIV_VV_M8_E8_MASK, VDIV_VV, 0x3, 0x8 }, // 1085 |
7077 | | { PseudoVDIV_VV_M8_E16, VDIV_VV, 0x3, 0x10 }, // 1086 |
7078 | | { PseudoVDIV_VV_M8_E16_MASK, VDIV_VV, 0x3, 0x10 }, // 1087 |
7079 | | { PseudoVDIV_VV_M8_E32, VDIV_VV, 0x3, 0x20 }, // 1088 |
7080 | | { PseudoVDIV_VV_M8_E32_MASK, VDIV_VV, 0x3, 0x20 }, // 1089 |
7081 | | { PseudoVDIV_VV_M8_E64, VDIV_VV, 0x3, 0x40 }, // 1090 |
7082 | | { PseudoVDIV_VV_M8_E64_MASK, VDIV_VV, 0x3, 0x40 }, // 1091 |
7083 | | { PseudoVDIV_VV_MF8_E8, VDIV_VV, 0x5, 0x8 }, // 1092 |
7084 | | { PseudoVDIV_VV_MF8_E8_MASK, VDIV_VV, 0x5, 0x8 }, // 1093 |
7085 | | { PseudoVDIV_VV_MF4_E8, VDIV_VV, 0x6, 0x8 }, // 1094 |
7086 | | { PseudoVDIV_VV_MF4_E8_MASK, VDIV_VV, 0x6, 0x8 }, // 1095 |
7087 | | { PseudoVDIV_VV_MF4_E16, VDIV_VV, 0x6, 0x10 }, // 1096 |
7088 | | { PseudoVDIV_VV_MF4_E16_MASK, VDIV_VV, 0x6, 0x10 }, // 1097 |
7089 | | { PseudoVDIV_VV_MF2_E8, VDIV_VV, 0x7, 0x8 }, // 1098 |
7090 | | { PseudoVDIV_VV_MF2_E8_MASK, VDIV_VV, 0x7, 0x8 }, // 1099 |
7091 | | { PseudoVDIV_VV_MF2_E16, VDIV_VV, 0x7, 0x10 }, // 1100 |
7092 | | { PseudoVDIV_VV_MF2_E16_MASK, VDIV_VV, 0x7, 0x10 }, // 1101 |
7093 | | { PseudoVDIV_VV_MF2_E32, VDIV_VV, 0x7, 0x20 }, // 1102 |
7094 | | { PseudoVDIV_VV_MF2_E32_MASK, VDIV_VV, 0x7, 0x20 }, // 1103 |
7095 | | { PseudoVDIV_VX_M1_E8, VDIV_VX, 0x0, 0x8 }, // 1104 |
7096 | | { PseudoVDIV_VX_M1_E8_MASK, VDIV_VX, 0x0, 0x8 }, // 1105 |
7097 | | { PseudoVDIV_VX_M1_E16, VDIV_VX, 0x0, 0x10 }, // 1106 |
7098 | | { PseudoVDIV_VX_M1_E16_MASK, VDIV_VX, 0x0, 0x10 }, // 1107 |
7099 | | { PseudoVDIV_VX_M1_E32, VDIV_VX, 0x0, 0x20 }, // 1108 |
7100 | | { PseudoVDIV_VX_M1_E32_MASK, VDIV_VX, 0x0, 0x20 }, // 1109 |
7101 | | { PseudoVDIV_VX_M1_E64, VDIV_VX, 0x0, 0x40 }, // 1110 |
7102 | | { PseudoVDIV_VX_M1_E64_MASK, VDIV_VX, 0x0, 0x40 }, // 1111 |
7103 | | { PseudoVDIV_VX_M2_E8, VDIV_VX, 0x1, 0x8 }, // 1112 |
7104 | | { PseudoVDIV_VX_M2_E8_MASK, VDIV_VX, 0x1, 0x8 }, // 1113 |
7105 | | { PseudoVDIV_VX_M2_E16, VDIV_VX, 0x1, 0x10 }, // 1114 |
7106 | | { PseudoVDIV_VX_M2_E16_MASK, VDIV_VX, 0x1, 0x10 }, // 1115 |
7107 | | { PseudoVDIV_VX_M2_E32, VDIV_VX, 0x1, 0x20 }, // 1116 |
7108 | | { PseudoVDIV_VX_M2_E32_MASK, VDIV_VX, 0x1, 0x20 }, // 1117 |
7109 | | { PseudoVDIV_VX_M2_E64, VDIV_VX, 0x1, 0x40 }, // 1118 |
7110 | | { PseudoVDIV_VX_M2_E64_MASK, VDIV_VX, 0x1, 0x40 }, // 1119 |
7111 | | { PseudoVDIV_VX_M4_E8, VDIV_VX, 0x2, 0x8 }, // 1120 |
7112 | | { PseudoVDIV_VX_M4_E8_MASK, VDIV_VX, 0x2, 0x8 }, // 1121 |
7113 | | { PseudoVDIV_VX_M4_E16, VDIV_VX, 0x2, 0x10 }, // 1122 |
7114 | | { PseudoVDIV_VX_M4_E16_MASK, VDIV_VX, 0x2, 0x10 }, // 1123 |
7115 | | { PseudoVDIV_VX_M4_E32, VDIV_VX, 0x2, 0x20 }, // 1124 |
7116 | | { PseudoVDIV_VX_M4_E32_MASK, VDIV_VX, 0x2, 0x20 }, // 1125 |
7117 | | { PseudoVDIV_VX_M4_E64, VDIV_VX, 0x2, 0x40 }, // 1126 |
7118 | | { PseudoVDIV_VX_M4_E64_MASK, VDIV_VX, 0x2, 0x40 }, // 1127 |
7119 | | { PseudoVDIV_VX_M8_E8, VDIV_VX, 0x3, 0x8 }, // 1128 |
7120 | | { PseudoVDIV_VX_M8_E8_MASK, VDIV_VX, 0x3, 0x8 }, // 1129 |
7121 | | { PseudoVDIV_VX_M8_E16, VDIV_VX, 0x3, 0x10 }, // 1130 |
7122 | | { PseudoVDIV_VX_M8_E16_MASK, VDIV_VX, 0x3, 0x10 }, // 1131 |
7123 | | { PseudoVDIV_VX_M8_E32, VDIV_VX, 0x3, 0x20 }, // 1132 |
7124 | | { PseudoVDIV_VX_M8_E32_MASK, VDIV_VX, 0x3, 0x20 }, // 1133 |
7125 | | { PseudoVDIV_VX_M8_E64, VDIV_VX, 0x3, 0x40 }, // 1134 |
7126 | | { PseudoVDIV_VX_M8_E64_MASK, VDIV_VX, 0x3, 0x40 }, // 1135 |
7127 | | { PseudoVDIV_VX_MF8_E8, VDIV_VX, 0x5, 0x8 }, // 1136 |
7128 | | { PseudoVDIV_VX_MF8_E8_MASK, VDIV_VX, 0x5, 0x8 }, // 1137 |
7129 | | { PseudoVDIV_VX_MF4_E8, VDIV_VX, 0x6, 0x8 }, // 1138 |
7130 | | { PseudoVDIV_VX_MF4_E8_MASK, VDIV_VX, 0x6, 0x8 }, // 1139 |
7131 | | { PseudoVDIV_VX_MF4_E16, VDIV_VX, 0x6, 0x10 }, // 1140 |
7132 | | { PseudoVDIV_VX_MF4_E16_MASK, VDIV_VX, 0x6, 0x10 }, // 1141 |
7133 | | { PseudoVDIV_VX_MF2_E8, VDIV_VX, 0x7, 0x8 }, // 1142 |
7134 | | { PseudoVDIV_VX_MF2_E8_MASK, VDIV_VX, 0x7, 0x8 }, // 1143 |
7135 | | { PseudoVDIV_VX_MF2_E16, VDIV_VX, 0x7, 0x10 }, // 1144 |
7136 | | { PseudoVDIV_VX_MF2_E16_MASK, VDIV_VX, 0x7, 0x10 }, // 1145 |
7137 | | { PseudoVDIV_VX_MF2_E32, VDIV_VX, 0x7, 0x20 }, // 1146 |
7138 | | { PseudoVDIV_VX_MF2_E32_MASK, VDIV_VX, 0x7, 0x20 }, // 1147 |
7139 | | { PseudoVFADD_VFPR16_M1, VFADD_VF, 0x0, 0x0 }, // 1148 |
7140 | | { PseudoVFADD_VFPR16_M1_MASK, VFADD_VF, 0x0, 0x0 }, // 1149 |
7141 | | { PseudoVFADD_VFPR32_M1, VFADD_VF, 0x0, 0x0 }, // 1150 |
7142 | | { PseudoVFADD_VFPR32_M1_MASK, VFADD_VF, 0x0, 0x0 }, // 1151 |
7143 | | { PseudoVFADD_VFPR64_M1, VFADD_VF, 0x0, 0x0 }, // 1152 |
7144 | | { PseudoVFADD_VFPR64_M1_MASK, VFADD_VF, 0x0, 0x0 }, // 1153 |
7145 | | { PseudoVFADD_VFPR16_M2, VFADD_VF, 0x1, 0x0 }, // 1154 |
7146 | | { PseudoVFADD_VFPR16_M2_MASK, VFADD_VF, 0x1, 0x0 }, // 1155 |
7147 | | { PseudoVFADD_VFPR32_M2, VFADD_VF, 0x1, 0x0 }, // 1156 |
7148 | | { PseudoVFADD_VFPR32_M2_MASK, VFADD_VF, 0x1, 0x0 }, // 1157 |
7149 | | { PseudoVFADD_VFPR64_M2, VFADD_VF, 0x1, 0x0 }, // 1158 |
7150 | | { PseudoVFADD_VFPR64_M2_MASK, VFADD_VF, 0x1, 0x0 }, // 1159 |
7151 | | { PseudoVFADD_VFPR16_M4, VFADD_VF, 0x2, 0x0 }, // 1160 |
7152 | | { PseudoVFADD_VFPR16_M4_MASK, VFADD_VF, 0x2, 0x0 }, // 1161 |
7153 | | { PseudoVFADD_VFPR32_M4, VFADD_VF, 0x2, 0x0 }, // 1162 |
7154 | | { PseudoVFADD_VFPR32_M4_MASK, VFADD_VF, 0x2, 0x0 }, // 1163 |
7155 | | { PseudoVFADD_VFPR64_M4, VFADD_VF, 0x2, 0x0 }, // 1164 |
7156 | | { PseudoVFADD_VFPR64_M4_MASK, VFADD_VF, 0x2, 0x0 }, // 1165 |
7157 | | { PseudoVFADD_VFPR16_M8, VFADD_VF, 0x3, 0x0 }, // 1166 |
7158 | | { PseudoVFADD_VFPR16_M8_MASK, VFADD_VF, 0x3, 0x0 }, // 1167 |
7159 | | { PseudoVFADD_VFPR32_M8, VFADD_VF, 0x3, 0x0 }, // 1168 |
7160 | | { PseudoVFADD_VFPR32_M8_MASK, VFADD_VF, 0x3, 0x0 }, // 1169 |
7161 | | { PseudoVFADD_VFPR64_M8, VFADD_VF, 0x3, 0x0 }, // 1170 |
7162 | | { PseudoVFADD_VFPR64_M8_MASK, VFADD_VF, 0x3, 0x0 }, // 1171 |
7163 | | { PseudoVFADD_VFPR16_MF4, VFADD_VF, 0x6, 0x0 }, // 1172 |
7164 | | { PseudoVFADD_VFPR16_MF4_MASK, VFADD_VF, 0x6, 0x0 }, // 1173 |
7165 | | { PseudoVFADD_VFPR16_MF2, VFADD_VF, 0x7, 0x0 }, // 1174 |
7166 | | { PseudoVFADD_VFPR16_MF2_MASK, VFADD_VF, 0x7, 0x0 }, // 1175 |
7167 | | { PseudoVFADD_VFPR32_MF2, VFADD_VF, 0x7, 0x0 }, // 1176 |
7168 | | { PseudoVFADD_VFPR32_MF2_MASK, VFADD_VF, 0x7, 0x0 }, // 1177 |
7169 | | { PseudoVFADD_VV_M1, VFADD_VV, 0x0, 0x0 }, // 1178 |
7170 | | { PseudoVFADD_VV_M1_MASK, VFADD_VV, 0x0, 0x0 }, // 1179 |
7171 | | { PseudoVFADD_VV_M2, VFADD_VV, 0x1, 0x0 }, // 1180 |
7172 | | { PseudoVFADD_VV_M2_MASK, VFADD_VV, 0x1, 0x0 }, // 1181 |
7173 | | { PseudoVFADD_VV_M4, VFADD_VV, 0x2, 0x0 }, // 1182 |
7174 | | { PseudoVFADD_VV_M4_MASK, VFADD_VV, 0x2, 0x0 }, // 1183 |
7175 | | { PseudoVFADD_VV_M8, VFADD_VV, 0x3, 0x0 }, // 1184 |
7176 | | { PseudoVFADD_VV_M8_MASK, VFADD_VV, 0x3, 0x0 }, // 1185 |
7177 | | { PseudoVFADD_VV_MF4, VFADD_VV, 0x6, 0x0 }, // 1186 |
7178 | | { PseudoVFADD_VV_MF4_MASK, VFADD_VV, 0x6, 0x0 }, // 1187 |
7179 | | { PseudoVFADD_VV_MF2, VFADD_VV, 0x7, 0x0 }, // 1188 |
7180 | | { PseudoVFADD_VV_MF2_MASK, VFADD_VV, 0x7, 0x0 }, // 1189 |
7181 | | { PseudoVFCLASS_V_M1, VFCLASS_V, 0x0, 0x0 }, // 1190 |
7182 | | { PseudoVFCLASS_V_M1_MASK, VFCLASS_V, 0x0, 0x0 }, // 1191 |
7183 | | { PseudoVFCLASS_V_M2, VFCLASS_V, 0x1, 0x0 }, // 1192 |
7184 | | { PseudoVFCLASS_V_M2_MASK, VFCLASS_V, 0x1, 0x0 }, // 1193 |
7185 | | { PseudoVFCLASS_V_M4, VFCLASS_V, 0x2, 0x0 }, // 1194 |
7186 | | { PseudoVFCLASS_V_M4_MASK, VFCLASS_V, 0x2, 0x0 }, // 1195 |
7187 | | { PseudoVFCLASS_V_M8, VFCLASS_V, 0x3, 0x0 }, // 1196 |
7188 | | { PseudoVFCLASS_V_M8_MASK, VFCLASS_V, 0x3, 0x0 }, // 1197 |
7189 | | { PseudoVFCLASS_V_MF4, VFCLASS_V, 0x6, 0x0 }, // 1198 |
7190 | | { PseudoVFCLASS_V_MF4_MASK, VFCLASS_V, 0x6, 0x0 }, // 1199 |
7191 | | { PseudoVFCLASS_V_MF2, VFCLASS_V, 0x7, 0x0 }, // 1200 |
7192 | | { PseudoVFCLASS_V_MF2_MASK, VFCLASS_V, 0x7, 0x0 }, // 1201 |
7193 | | { PseudoVFCVT_F_XU_V_M1, VFCVT_F_XU_V, 0x0, 0x0 }, // 1202 |
7194 | | { PseudoVFCVT_F_XU_V_M1_MASK, VFCVT_F_XU_V, 0x0, 0x0 }, // 1203 |
7195 | | { PseudoVFCVT_RM_F_XU_V_M1, VFCVT_F_XU_V, 0x0, 0x0 }, // 1204 |
7196 | | { PseudoVFCVT_RM_F_XU_V_M1_MASK, VFCVT_F_XU_V, 0x0, 0x0 }, // 1205 |
7197 | | { PseudoVFCVT_F_XU_V_M2, VFCVT_F_XU_V, 0x1, 0x0 }, // 1206 |
7198 | | { PseudoVFCVT_F_XU_V_M2_MASK, VFCVT_F_XU_V, 0x1, 0x0 }, // 1207 |
7199 | | { PseudoVFCVT_RM_F_XU_V_M2, VFCVT_F_XU_V, 0x1, 0x0 }, // 1208 |
7200 | | { PseudoVFCVT_RM_F_XU_V_M2_MASK, VFCVT_F_XU_V, 0x1, 0x0 }, // 1209 |
7201 | | { PseudoVFCVT_F_XU_V_M4, VFCVT_F_XU_V, 0x2, 0x0 }, // 1210 |
7202 | | { PseudoVFCVT_F_XU_V_M4_MASK, VFCVT_F_XU_V, 0x2, 0x0 }, // 1211 |
7203 | | { PseudoVFCVT_RM_F_XU_V_M4, VFCVT_F_XU_V, 0x2, 0x0 }, // 1212 |
7204 | | { PseudoVFCVT_RM_F_XU_V_M4_MASK, VFCVT_F_XU_V, 0x2, 0x0 }, // 1213 |
7205 | | { PseudoVFCVT_F_XU_V_M8, VFCVT_F_XU_V, 0x3, 0x0 }, // 1214 |
7206 | | { PseudoVFCVT_F_XU_V_M8_MASK, VFCVT_F_XU_V, 0x3, 0x0 }, // 1215 |
7207 | | { PseudoVFCVT_RM_F_XU_V_M8, VFCVT_F_XU_V, 0x3, 0x0 }, // 1216 |
7208 | | { PseudoVFCVT_RM_F_XU_V_M8_MASK, VFCVT_F_XU_V, 0x3, 0x0 }, // 1217 |
7209 | | { PseudoVFCVT_F_XU_V_MF4, VFCVT_F_XU_V, 0x6, 0x0 }, // 1218 |
7210 | | { PseudoVFCVT_F_XU_V_MF4_MASK, VFCVT_F_XU_V, 0x6, 0x0 }, // 1219 |
7211 | | { PseudoVFCVT_RM_F_XU_V_MF4, VFCVT_F_XU_V, 0x6, 0x0 }, // 1220 |
7212 | | { PseudoVFCVT_RM_F_XU_V_MF4_MASK, VFCVT_F_XU_V, 0x6, 0x0 }, // 1221 |
7213 | | { PseudoVFCVT_F_XU_V_MF2, VFCVT_F_XU_V, 0x7, 0x0 }, // 1222 |
7214 | | { PseudoVFCVT_F_XU_V_MF2_MASK, VFCVT_F_XU_V, 0x7, 0x0 }, // 1223 |
7215 | | { PseudoVFCVT_RM_F_XU_V_MF2, VFCVT_F_XU_V, 0x7, 0x0 }, // 1224 |
7216 | | { PseudoVFCVT_RM_F_XU_V_MF2_MASK, VFCVT_F_XU_V, 0x7, 0x0 }, // 1225 |
7217 | | { PseudoVFCVT_F_X_V_M1, VFCVT_F_X_V, 0x0, 0x0 }, // 1226 |
7218 | | { PseudoVFCVT_F_X_V_M1_MASK, VFCVT_F_X_V, 0x0, 0x0 }, // 1227 |
7219 | | { PseudoVFCVT_RM_F_X_V_M1, VFCVT_F_X_V, 0x0, 0x0 }, // 1228 |
7220 | | { PseudoVFCVT_RM_F_X_V_M1_MASK, VFCVT_F_X_V, 0x0, 0x0 }, // 1229 |
7221 | | { PseudoVFCVT_F_X_V_M2, VFCVT_F_X_V, 0x1, 0x0 }, // 1230 |
7222 | | { PseudoVFCVT_F_X_V_M2_MASK, VFCVT_F_X_V, 0x1, 0x0 }, // 1231 |
7223 | | { PseudoVFCVT_RM_F_X_V_M2, VFCVT_F_X_V, 0x1, 0x0 }, // 1232 |
7224 | | { PseudoVFCVT_RM_F_X_V_M2_MASK, VFCVT_F_X_V, 0x1, 0x0 }, // 1233 |
7225 | | { PseudoVFCVT_F_X_V_M4, VFCVT_F_X_V, 0x2, 0x0 }, // 1234 |
7226 | | { PseudoVFCVT_F_X_V_M4_MASK, VFCVT_F_X_V, 0x2, 0x0 }, // 1235 |
7227 | | { PseudoVFCVT_RM_F_X_V_M4, VFCVT_F_X_V, 0x2, 0x0 }, // 1236 |
7228 | | { PseudoVFCVT_RM_F_X_V_M4_MASK, VFCVT_F_X_V, 0x2, 0x0 }, // 1237 |
7229 | | { PseudoVFCVT_F_X_V_M8, VFCVT_F_X_V, 0x3, 0x0 }, // 1238 |
7230 | | { PseudoVFCVT_F_X_V_M8_MASK, VFCVT_F_X_V, 0x3, 0x0 }, // 1239 |
7231 | | { PseudoVFCVT_RM_F_X_V_M8, VFCVT_F_X_V, 0x3, 0x0 }, // 1240 |
7232 | | { PseudoVFCVT_RM_F_X_V_M8_MASK, VFCVT_F_X_V, 0x3, 0x0 }, // 1241 |
7233 | | { PseudoVFCVT_F_X_V_MF4, VFCVT_F_X_V, 0x6, 0x0 }, // 1242 |
7234 | | { PseudoVFCVT_F_X_V_MF4_MASK, VFCVT_F_X_V, 0x6, 0x0 }, // 1243 |
7235 | | { PseudoVFCVT_RM_F_X_V_MF4, VFCVT_F_X_V, 0x6, 0x0 }, // 1244 |
7236 | | { PseudoVFCVT_RM_F_X_V_MF4_MASK, VFCVT_F_X_V, 0x6, 0x0 }, // 1245 |
7237 | | { PseudoVFCVT_F_X_V_MF2, VFCVT_F_X_V, 0x7, 0x0 }, // 1246 |
7238 | | { PseudoVFCVT_F_X_V_MF2_MASK, VFCVT_F_X_V, 0x7, 0x0 }, // 1247 |
7239 | | { PseudoVFCVT_RM_F_X_V_MF2, VFCVT_F_X_V, 0x7, 0x0 }, // 1248 |
7240 | | { PseudoVFCVT_RM_F_X_V_MF2_MASK, VFCVT_F_X_V, 0x7, 0x0 }, // 1249 |
7241 | | { PseudoVFCVT_RTZ_XU_F_V_M1, VFCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 1250 |
7242 | | { PseudoVFCVT_RTZ_XU_F_V_M1_MASK, VFCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 1251 |
7243 | | { PseudoVFCVT_RTZ_XU_F_V_M2, VFCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 1252 |
7244 | | { PseudoVFCVT_RTZ_XU_F_V_M2_MASK, VFCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 1253 |
7245 | | { PseudoVFCVT_RTZ_XU_F_V_M4, VFCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 1254 |
7246 | | { PseudoVFCVT_RTZ_XU_F_V_M4_MASK, VFCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 1255 |
7247 | | { PseudoVFCVT_RTZ_XU_F_V_M8, VFCVT_RTZ_XU_F_V, 0x3, 0x0 }, // 1256 |
7248 | | { PseudoVFCVT_RTZ_XU_F_V_M8_MASK, VFCVT_RTZ_XU_F_V, 0x3, 0x0 }, // 1257 |
7249 | | { PseudoVFCVT_RTZ_XU_F_V_MF4, VFCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 1258 |
7250 | | { PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, VFCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 1259 |
7251 | | { PseudoVFCVT_RTZ_XU_F_V_MF2, VFCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 1260 |
7252 | | { PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, VFCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 1261 |
7253 | | { PseudoVFCVT_RTZ_X_F_V_M1, VFCVT_RTZ_X_F_V, 0x0, 0x0 }, // 1262 |
7254 | | { PseudoVFCVT_RTZ_X_F_V_M1_MASK, VFCVT_RTZ_X_F_V, 0x0, 0x0 }, // 1263 |
7255 | | { PseudoVFCVT_RTZ_X_F_V_M2, VFCVT_RTZ_X_F_V, 0x1, 0x0 }, // 1264 |
7256 | | { PseudoVFCVT_RTZ_X_F_V_M2_MASK, VFCVT_RTZ_X_F_V, 0x1, 0x0 }, // 1265 |
7257 | | { PseudoVFCVT_RTZ_X_F_V_M4, VFCVT_RTZ_X_F_V, 0x2, 0x0 }, // 1266 |
7258 | | { PseudoVFCVT_RTZ_X_F_V_M4_MASK, VFCVT_RTZ_X_F_V, 0x2, 0x0 }, // 1267 |
7259 | | { PseudoVFCVT_RTZ_X_F_V_M8, VFCVT_RTZ_X_F_V, 0x3, 0x0 }, // 1268 |
7260 | | { PseudoVFCVT_RTZ_X_F_V_M8_MASK, VFCVT_RTZ_X_F_V, 0x3, 0x0 }, // 1269 |
7261 | | { PseudoVFCVT_RTZ_X_F_V_MF4, VFCVT_RTZ_X_F_V, 0x6, 0x0 }, // 1270 |
7262 | | { PseudoVFCVT_RTZ_X_F_V_MF4_MASK, VFCVT_RTZ_X_F_V, 0x6, 0x0 }, // 1271 |
7263 | | { PseudoVFCVT_RTZ_X_F_V_MF2, VFCVT_RTZ_X_F_V, 0x7, 0x0 }, // 1272 |
7264 | | { PseudoVFCVT_RTZ_X_F_V_MF2_MASK, VFCVT_RTZ_X_F_V, 0x7, 0x0 }, // 1273 |
7265 | | { PseudoVFCVT_RM_XU_F_V_M1, VFCVT_XU_F_V, 0x0, 0x0 }, // 1274 |
7266 | | { PseudoVFCVT_RM_XU_F_V_M1_MASK, VFCVT_XU_F_V, 0x0, 0x0 }, // 1275 |
7267 | | { PseudoVFCVT_XU_F_V_M1, VFCVT_XU_F_V, 0x0, 0x0 }, // 1276 |
7268 | | { PseudoVFCVT_XU_F_V_M1_MASK, VFCVT_XU_F_V, 0x0, 0x0 }, // 1277 |
7269 | | { PseudoVFCVT_RM_XU_F_V_M2, VFCVT_XU_F_V, 0x1, 0x0 }, // 1278 |
7270 | | { PseudoVFCVT_RM_XU_F_V_M2_MASK, VFCVT_XU_F_V, 0x1, 0x0 }, // 1279 |
7271 | | { PseudoVFCVT_XU_F_V_M2, VFCVT_XU_F_V, 0x1, 0x0 }, // 1280 |
7272 | | { PseudoVFCVT_XU_F_V_M2_MASK, VFCVT_XU_F_V, 0x1, 0x0 }, // 1281 |
7273 | | { PseudoVFCVT_RM_XU_F_V_M4, VFCVT_XU_F_V, 0x2, 0x0 }, // 1282 |
7274 | | { PseudoVFCVT_RM_XU_F_V_M4_MASK, VFCVT_XU_F_V, 0x2, 0x0 }, // 1283 |
7275 | | { PseudoVFCVT_XU_F_V_M4, VFCVT_XU_F_V, 0x2, 0x0 }, // 1284 |
7276 | | { PseudoVFCVT_XU_F_V_M4_MASK, VFCVT_XU_F_V, 0x2, 0x0 }, // 1285 |
7277 | | { PseudoVFCVT_RM_XU_F_V_M8, VFCVT_XU_F_V, 0x3, 0x0 }, // 1286 |
7278 | | { PseudoVFCVT_RM_XU_F_V_M8_MASK, VFCVT_XU_F_V, 0x3, 0x0 }, // 1287 |
7279 | | { PseudoVFCVT_XU_F_V_M8, VFCVT_XU_F_V, 0x3, 0x0 }, // 1288 |
7280 | | { PseudoVFCVT_XU_F_V_M8_MASK, VFCVT_XU_F_V, 0x3, 0x0 }, // 1289 |
7281 | | { PseudoVFCVT_RM_XU_F_V_MF4, VFCVT_XU_F_V, 0x6, 0x0 }, // 1290 |
7282 | | { PseudoVFCVT_RM_XU_F_V_MF4_MASK, VFCVT_XU_F_V, 0x6, 0x0 }, // 1291 |
7283 | | { PseudoVFCVT_XU_F_V_MF4, VFCVT_XU_F_V, 0x6, 0x0 }, // 1292 |
7284 | | { PseudoVFCVT_XU_F_V_MF4_MASK, VFCVT_XU_F_V, 0x6, 0x0 }, // 1293 |
7285 | | { PseudoVFCVT_RM_XU_F_V_MF2, VFCVT_XU_F_V, 0x7, 0x0 }, // 1294 |
7286 | | { PseudoVFCVT_RM_XU_F_V_MF2_MASK, VFCVT_XU_F_V, 0x7, 0x0 }, // 1295 |
7287 | | { PseudoVFCVT_XU_F_V_MF2, VFCVT_XU_F_V, 0x7, 0x0 }, // 1296 |
7288 | | { PseudoVFCVT_XU_F_V_MF2_MASK, VFCVT_XU_F_V, 0x7, 0x0 }, // 1297 |
7289 | | { PseudoVFCVT_RM_X_F_V_M1, VFCVT_X_F_V, 0x0, 0x0 }, // 1298 |
7290 | | { PseudoVFCVT_RM_X_F_V_M1_MASK, VFCVT_X_F_V, 0x0, 0x0 }, // 1299 |
7291 | | { PseudoVFCVT_X_F_V_M1, VFCVT_X_F_V, 0x0, 0x0 }, // 1300 |
7292 | | { PseudoVFCVT_X_F_V_M1_MASK, VFCVT_X_F_V, 0x0, 0x0 }, // 1301 |
7293 | | { PseudoVFCVT_RM_X_F_V_M2, VFCVT_X_F_V, 0x1, 0x0 }, // 1302 |
7294 | | { PseudoVFCVT_RM_X_F_V_M2_MASK, VFCVT_X_F_V, 0x1, 0x0 }, // 1303 |
7295 | | { PseudoVFCVT_X_F_V_M2, VFCVT_X_F_V, 0x1, 0x0 }, // 1304 |
7296 | | { PseudoVFCVT_X_F_V_M2_MASK, VFCVT_X_F_V, 0x1, 0x0 }, // 1305 |
7297 | | { PseudoVFCVT_RM_X_F_V_M4, VFCVT_X_F_V, 0x2, 0x0 }, // 1306 |
7298 | | { PseudoVFCVT_RM_X_F_V_M4_MASK, VFCVT_X_F_V, 0x2, 0x0 }, // 1307 |
7299 | | { PseudoVFCVT_X_F_V_M4, VFCVT_X_F_V, 0x2, 0x0 }, // 1308 |
7300 | | { PseudoVFCVT_X_F_V_M4_MASK, VFCVT_X_F_V, 0x2, 0x0 }, // 1309 |
7301 | | { PseudoVFCVT_RM_X_F_V_M8, VFCVT_X_F_V, 0x3, 0x0 }, // 1310 |
7302 | | { PseudoVFCVT_RM_X_F_V_M8_MASK, VFCVT_X_F_V, 0x3, 0x0 }, // 1311 |
7303 | | { PseudoVFCVT_X_F_V_M8, VFCVT_X_F_V, 0x3, 0x0 }, // 1312 |
7304 | | { PseudoVFCVT_X_F_V_M8_MASK, VFCVT_X_F_V, 0x3, 0x0 }, // 1313 |
7305 | | { PseudoVFCVT_RM_X_F_V_MF4, VFCVT_X_F_V, 0x6, 0x0 }, // 1314 |
7306 | | { PseudoVFCVT_RM_X_F_V_MF4_MASK, VFCVT_X_F_V, 0x6, 0x0 }, // 1315 |
7307 | | { PseudoVFCVT_X_F_V_MF4, VFCVT_X_F_V, 0x6, 0x0 }, // 1316 |
7308 | | { PseudoVFCVT_X_F_V_MF4_MASK, VFCVT_X_F_V, 0x6, 0x0 }, // 1317 |
7309 | | { PseudoVFCVT_RM_X_F_V_MF2, VFCVT_X_F_V, 0x7, 0x0 }, // 1318 |
7310 | | { PseudoVFCVT_RM_X_F_V_MF2_MASK, VFCVT_X_F_V, 0x7, 0x0 }, // 1319 |
7311 | | { PseudoVFCVT_X_F_V_MF2, VFCVT_X_F_V, 0x7, 0x0 }, // 1320 |
7312 | | { PseudoVFCVT_X_F_V_MF2_MASK, VFCVT_X_F_V, 0x7, 0x0 }, // 1321 |
7313 | | { PseudoVFDIV_VFPR16_M1_E16, VFDIV_VF, 0x0, 0x10 }, // 1322 |
7314 | | { PseudoVFDIV_VFPR16_M1_E16_MASK, VFDIV_VF, 0x0, 0x10 }, // 1323 |
7315 | | { PseudoVFDIV_VFPR32_M1_E32, VFDIV_VF, 0x0, 0x20 }, // 1324 |
7316 | | { PseudoVFDIV_VFPR32_M1_E32_MASK, VFDIV_VF, 0x0, 0x20 }, // 1325 |
7317 | | { PseudoVFDIV_VFPR64_M1_E64, VFDIV_VF, 0x0, 0x40 }, // 1326 |
7318 | | { PseudoVFDIV_VFPR64_M1_E64_MASK, VFDIV_VF, 0x0, 0x40 }, // 1327 |
7319 | | { PseudoVFDIV_VFPR16_M2_E16, VFDIV_VF, 0x1, 0x10 }, // 1328 |
7320 | | { PseudoVFDIV_VFPR16_M2_E16_MASK, VFDIV_VF, 0x1, 0x10 }, // 1329 |
7321 | | { PseudoVFDIV_VFPR32_M2_E32, VFDIV_VF, 0x1, 0x20 }, // 1330 |
7322 | | { PseudoVFDIV_VFPR32_M2_E32_MASK, VFDIV_VF, 0x1, 0x20 }, // 1331 |
7323 | | { PseudoVFDIV_VFPR64_M2_E64, VFDIV_VF, 0x1, 0x40 }, // 1332 |
7324 | | { PseudoVFDIV_VFPR64_M2_E64_MASK, VFDIV_VF, 0x1, 0x40 }, // 1333 |
7325 | | { PseudoVFDIV_VFPR16_M4_E16, VFDIV_VF, 0x2, 0x10 }, // 1334 |
7326 | | { PseudoVFDIV_VFPR16_M4_E16_MASK, VFDIV_VF, 0x2, 0x10 }, // 1335 |
7327 | | { PseudoVFDIV_VFPR32_M4_E32, VFDIV_VF, 0x2, 0x20 }, // 1336 |
7328 | | { PseudoVFDIV_VFPR32_M4_E32_MASK, VFDIV_VF, 0x2, 0x20 }, // 1337 |
7329 | | { PseudoVFDIV_VFPR64_M4_E64, VFDIV_VF, 0x2, 0x40 }, // 1338 |
7330 | | { PseudoVFDIV_VFPR64_M4_E64_MASK, VFDIV_VF, 0x2, 0x40 }, // 1339 |
7331 | | { PseudoVFDIV_VFPR16_M8_E16, VFDIV_VF, 0x3, 0x10 }, // 1340 |
7332 | | { PseudoVFDIV_VFPR16_M8_E16_MASK, VFDIV_VF, 0x3, 0x10 }, // 1341 |
7333 | | { PseudoVFDIV_VFPR32_M8_E32, VFDIV_VF, 0x3, 0x20 }, // 1342 |
7334 | | { PseudoVFDIV_VFPR32_M8_E32_MASK, VFDIV_VF, 0x3, 0x20 }, // 1343 |
7335 | | { PseudoVFDIV_VFPR64_M8_E64, VFDIV_VF, 0x3, 0x40 }, // 1344 |
7336 | | { PseudoVFDIV_VFPR64_M8_E64_MASK, VFDIV_VF, 0x3, 0x40 }, // 1345 |
7337 | | { PseudoVFDIV_VFPR16_MF4_E16, VFDIV_VF, 0x6, 0x10 }, // 1346 |
7338 | | { PseudoVFDIV_VFPR16_MF4_E16_MASK, VFDIV_VF, 0x6, 0x10 }, // 1347 |
7339 | | { PseudoVFDIV_VFPR16_MF2_E16, VFDIV_VF, 0x7, 0x10 }, // 1348 |
7340 | | { PseudoVFDIV_VFPR16_MF2_E16_MASK, VFDIV_VF, 0x7, 0x10 }, // 1349 |
7341 | | { PseudoVFDIV_VFPR32_MF2_E32, VFDIV_VF, 0x7, 0x20 }, // 1350 |
7342 | | { PseudoVFDIV_VFPR32_MF2_E32_MASK, VFDIV_VF, 0x7, 0x20 }, // 1351 |
7343 | | { PseudoVFDIV_VV_M1_E16, VFDIV_VV, 0x0, 0x10 }, // 1352 |
7344 | | { PseudoVFDIV_VV_M1_E16_MASK, VFDIV_VV, 0x0, 0x10 }, // 1353 |
7345 | | { PseudoVFDIV_VV_M1_E32, VFDIV_VV, 0x0, 0x20 }, // 1354 |
7346 | | { PseudoVFDIV_VV_M1_E32_MASK, VFDIV_VV, 0x0, 0x20 }, // 1355 |
7347 | | { PseudoVFDIV_VV_M1_E64, VFDIV_VV, 0x0, 0x40 }, // 1356 |
7348 | | { PseudoVFDIV_VV_M1_E64_MASK, VFDIV_VV, 0x0, 0x40 }, // 1357 |
7349 | | { PseudoVFDIV_VV_M2_E16, VFDIV_VV, 0x1, 0x10 }, // 1358 |
7350 | | { PseudoVFDIV_VV_M2_E16_MASK, VFDIV_VV, 0x1, 0x10 }, // 1359 |
7351 | | { PseudoVFDIV_VV_M2_E32, VFDIV_VV, 0x1, 0x20 }, // 1360 |
7352 | | { PseudoVFDIV_VV_M2_E32_MASK, VFDIV_VV, 0x1, 0x20 }, // 1361 |
7353 | | { PseudoVFDIV_VV_M2_E64, VFDIV_VV, 0x1, 0x40 }, // 1362 |
7354 | | { PseudoVFDIV_VV_M2_E64_MASK, VFDIV_VV, 0x1, 0x40 }, // 1363 |
7355 | | { PseudoVFDIV_VV_M4_E16, VFDIV_VV, 0x2, 0x10 }, // 1364 |
7356 | | { PseudoVFDIV_VV_M4_E16_MASK, VFDIV_VV, 0x2, 0x10 }, // 1365 |
7357 | | { PseudoVFDIV_VV_M4_E32, VFDIV_VV, 0x2, 0x20 }, // 1366 |
7358 | | { PseudoVFDIV_VV_M4_E32_MASK, VFDIV_VV, 0x2, 0x20 }, // 1367 |
7359 | | { PseudoVFDIV_VV_M4_E64, VFDIV_VV, 0x2, 0x40 }, // 1368 |
7360 | | { PseudoVFDIV_VV_M4_E64_MASK, VFDIV_VV, 0x2, 0x40 }, // 1369 |
7361 | | { PseudoVFDIV_VV_M8_E16, VFDIV_VV, 0x3, 0x10 }, // 1370 |
7362 | | { PseudoVFDIV_VV_M8_E16_MASK, VFDIV_VV, 0x3, 0x10 }, // 1371 |
7363 | | { PseudoVFDIV_VV_M8_E32, VFDIV_VV, 0x3, 0x20 }, // 1372 |
7364 | | { PseudoVFDIV_VV_M8_E32_MASK, VFDIV_VV, 0x3, 0x20 }, // 1373 |
7365 | | { PseudoVFDIV_VV_M8_E64, VFDIV_VV, 0x3, 0x40 }, // 1374 |
7366 | | { PseudoVFDIV_VV_M8_E64_MASK, VFDIV_VV, 0x3, 0x40 }, // 1375 |
7367 | | { PseudoVFDIV_VV_MF4_E16, VFDIV_VV, 0x6, 0x10 }, // 1376 |
7368 | | { PseudoVFDIV_VV_MF4_E16_MASK, VFDIV_VV, 0x6, 0x10 }, // 1377 |
7369 | | { PseudoVFDIV_VV_MF2_E16, VFDIV_VV, 0x7, 0x10 }, // 1378 |
7370 | | { PseudoVFDIV_VV_MF2_E16_MASK, VFDIV_VV, 0x7, 0x10 }, // 1379 |
7371 | | { PseudoVFDIV_VV_MF2_E32, VFDIV_VV, 0x7, 0x20 }, // 1380 |
7372 | | { PseudoVFDIV_VV_MF2_E32_MASK, VFDIV_VV, 0x7, 0x20 }, // 1381 |
7373 | | { PseudoVFIRST_M_B8, VFIRST_M, 0x0, 0x0 }, // 1382 |
7374 | | { PseudoVFIRST_M_B8_MASK, VFIRST_M, 0x0, 0x0 }, // 1383 |
7375 | | { PseudoVFIRST_M_B16, VFIRST_M, 0x1, 0x0 }, // 1384 |
7376 | | { PseudoVFIRST_M_B16_MASK, VFIRST_M, 0x1, 0x0 }, // 1385 |
7377 | | { PseudoVFIRST_M_B32, VFIRST_M, 0x2, 0x0 }, // 1386 |
7378 | | { PseudoVFIRST_M_B32_MASK, VFIRST_M, 0x2, 0x0 }, // 1387 |
7379 | | { PseudoVFIRST_M_B64, VFIRST_M, 0x3, 0x0 }, // 1388 |
7380 | | { PseudoVFIRST_M_B64_MASK, VFIRST_M, 0x3, 0x0 }, // 1389 |
7381 | | { PseudoVFIRST_M_B1, VFIRST_M, 0x5, 0x0 }, // 1390 |
7382 | | { PseudoVFIRST_M_B1_MASK, VFIRST_M, 0x5, 0x0 }, // 1391 |
7383 | | { PseudoVFIRST_M_B2, VFIRST_M, 0x6, 0x0 }, // 1392 |
7384 | | { PseudoVFIRST_M_B2_MASK, VFIRST_M, 0x6, 0x0 }, // 1393 |
7385 | | { PseudoVFIRST_M_B4, VFIRST_M, 0x7, 0x0 }, // 1394 |
7386 | | { PseudoVFIRST_M_B4_MASK, VFIRST_M, 0x7, 0x0 }, // 1395 |
7387 | | { PseudoVFMACC_VFPR16_M1, VFMACC_VF, 0x0, 0x0 }, // 1396 |
7388 | | { PseudoVFMACC_VFPR16_M1_MASK, VFMACC_VF, 0x0, 0x0 }, // 1397 |
7389 | | { PseudoVFMACC_VFPR32_M1, VFMACC_VF, 0x0, 0x0 }, // 1398 |
7390 | | { PseudoVFMACC_VFPR32_M1_MASK, VFMACC_VF, 0x0, 0x0 }, // 1399 |
7391 | | { PseudoVFMACC_VFPR64_M1, VFMACC_VF, 0x0, 0x0 }, // 1400 |
7392 | | { PseudoVFMACC_VFPR64_M1_MASK, VFMACC_VF, 0x0, 0x0 }, // 1401 |
7393 | | { PseudoVFMACC_VFPR16_M2, VFMACC_VF, 0x1, 0x0 }, // 1402 |
7394 | | { PseudoVFMACC_VFPR16_M2_MASK, VFMACC_VF, 0x1, 0x0 }, // 1403 |
7395 | | { PseudoVFMACC_VFPR32_M2, VFMACC_VF, 0x1, 0x0 }, // 1404 |
7396 | | { PseudoVFMACC_VFPR32_M2_MASK, VFMACC_VF, 0x1, 0x0 }, // 1405 |
7397 | | { PseudoVFMACC_VFPR64_M2, VFMACC_VF, 0x1, 0x0 }, // 1406 |
7398 | | { PseudoVFMACC_VFPR64_M2_MASK, VFMACC_VF, 0x1, 0x0 }, // 1407 |
7399 | | { PseudoVFMACC_VFPR16_M4, VFMACC_VF, 0x2, 0x0 }, // 1408 |
7400 | | { PseudoVFMACC_VFPR16_M4_MASK, VFMACC_VF, 0x2, 0x0 }, // 1409 |
7401 | | { PseudoVFMACC_VFPR32_M4, VFMACC_VF, 0x2, 0x0 }, // 1410 |
7402 | | { PseudoVFMACC_VFPR32_M4_MASK, VFMACC_VF, 0x2, 0x0 }, // 1411 |
7403 | | { PseudoVFMACC_VFPR64_M4, VFMACC_VF, 0x2, 0x0 }, // 1412 |
7404 | | { PseudoVFMACC_VFPR64_M4_MASK, VFMACC_VF, 0x2, 0x0 }, // 1413 |
7405 | | { PseudoVFMACC_VFPR16_M8, VFMACC_VF, 0x3, 0x0 }, // 1414 |
7406 | | { PseudoVFMACC_VFPR16_M8_MASK, VFMACC_VF, 0x3, 0x0 }, // 1415 |
7407 | | { PseudoVFMACC_VFPR32_M8, VFMACC_VF, 0x3, 0x0 }, // 1416 |
7408 | | { PseudoVFMACC_VFPR32_M8_MASK, VFMACC_VF, 0x3, 0x0 }, // 1417 |
7409 | | { PseudoVFMACC_VFPR64_M8, VFMACC_VF, 0x3, 0x0 }, // 1418 |
7410 | | { PseudoVFMACC_VFPR64_M8_MASK, VFMACC_VF, 0x3, 0x0 }, // 1419 |
7411 | | { PseudoVFMACC_VFPR16_MF4, VFMACC_VF, 0x6, 0x0 }, // 1420 |
7412 | | { PseudoVFMACC_VFPR16_MF4_MASK, VFMACC_VF, 0x6, 0x0 }, // 1421 |
7413 | | { PseudoVFMACC_VFPR16_MF2, VFMACC_VF, 0x7, 0x0 }, // 1422 |
7414 | | { PseudoVFMACC_VFPR16_MF2_MASK, VFMACC_VF, 0x7, 0x0 }, // 1423 |
7415 | | { PseudoVFMACC_VFPR32_MF2, VFMACC_VF, 0x7, 0x0 }, // 1424 |
7416 | | { PseudoVFMACC_VFPR32_MF2_MASK, VFMACC_VF, 0x7, 0x0 }, // 1425 |
7417 | | { PseudoVFMACC_VV_M1, VFMACC_VV, 0x0, 0x0 }, // 1426 |
7418 | | { PseudoVFMACC_VV_M1_MASK, VFMACC_VV, 0x0, 0x0 }, // 1427 |
7419 | | { PseudoVFMACC_VV_M2, VFMACC_VV, 0x1, 0x0 }, // 1428 |
7420 | | { PseudoVFMACC_VV_M2_MASK, VFMACC_VV, 0x1, 0x0 }, // 1429 |
7421 | | { PseudoVFMACC_VV_M4, VFMACC_VV, 0x2, 0x0 }, // 1430 |
7422 | | { PseudoVFMACC_VV_M4_MASK, VFMACC_VV, 0x2, 0x0 }, // 1431 |
7423 | | { PseudoVFMACC_VV_M8, VFMACC_VV, 0x3, 0x0 }, // 1432 |
7424 | | { PseudoVFMACC_VV_M8_MASK, VFMACC_VV, 0x3, 0x0 }, // 1433 |
7425 | | { PseudoVFMACC_VV_MF4, VFMACC_VV, 0x6, 0x0 }, // 1434 |
7426 | | { PseudoVFMACC_VV_MF4_MASK, VFMACC_VV, 0x6, 0x0 }, // 1435 |
7427 | | { PseudoVFMACC_VV_MF2, VFMACC_VV, 0x7, 0x0 }, // 1436 |
7428 | | { PseudoVFMACC_VV_MF2_MASK, VFMACC_VV, 0x7, 0x0 }, // 1437 |
7429 | | { PseudoVFMADD_VFPR16_M1, VFMADD_VF, 0x0, 0x0 }, // 1438 |
7430 | | { PseudoVFMADD_VFPR16_M1_MASK, VFMADD_VF, 0x0, 0x0 }, // 1439 |
7431 | | { PseudoVFMADD_VFPR32_M1, VFMADD_VF, 0x0, 0x0 }, // 1440 |
7432 | | { PseudoVFMADD_VFPR32_M1_MASK, VFMADD_VF, 0x0, 0x0 }, // 1441 |
7433 | | { PseudoVFMADD_VFPR64_M1, VFMADD_VF, 0x0, 0x0 }, // 1442 |
7434 | | { PseudoVFMADD_VFPR64_M1_MASK, VFMADD_VF, 0x0, 0x0 }, // 1443 |
7435 | | { PseudoVFMADD_VFPR16_M2, VFMADD_VF, 0x1, 0x0 }, // 1444 |
7436 | | { PseudoVFMADD_VFPR16_M2_MASK, VFMADD_VF, 0x1, 0x0 }, // 1445 |
7437 | | { PseudoVFMADD_VFPR32_M2, VFMADD_VF, 0x1, 0x0 }, // 1446 |
7438 | | { PseudoVFMADD_VFPR32_M2_MASK, VFMADD_VF, 0x1, 0x0 }, // 1447 |
7439 | | { PseudoVFMADD_VFPR64_M2, VFMADD_VF, 0x1, 0x0 }, // 1448 |
7440 | | { PseudoVFMADD_VFPR64_M2_MASK, VFMADD_VF, 0x1, 0x0 }, // 1449 |
7441 | | { PseudoVFMADD_VFPR16_M4, VFMADD_VF, 0x2, 0x0 }, // 1450 |
7442 | | { PseudoVFMADD_VFPR16_M4_MASK, VFMADD_VF, 0x2, 0x0 }, // 1451 |
7443 | | { PseudoVFMADD_VFPR32_M4, VFMADD_VF, 0x2, 0x0 }, // 1452 |
7444 | | { PseudoVFMADD_VFPR32_M4_MASK, VFMADD_VF, 0x2, 0x0 }, // 1453 |
7445 | | { PseudoVFMADD_VFPR64_M4, VFMADD_VF, 0x2, 0x0 }, // 1454 |
7446 | | { PseudoVFMADD_VFPR64_M4_MASK, VFMADD_VF, 0x2, 0x0 }, // 1455 |
7447 | | { PseudoVFMADD_VFPR16_M8, VFMADD_VF, 0x3, 0x0 }, // 1456 |
7448 | | { PseudoVFMADD_VFPR16_M8_MASK, VFMADD_VF, 0x3, 0x0 }, // 1457 |
7449 | | { PseudoVFMADD_VFPR32_M8, VFMADD_VF, 0x3, 0x0 }, // 1458 |
7450 | | { PseudoVFMADD_VFPR32_M8_MASK, VFMADD_VF, 0x3, 0x0 }, // 1459 |
7451 | | { PseudoVFMADD_VFPR64_M8, VFMADD_VF, 0x3, 0x0 }, // 1460 |
7452 | | { PseudoVFMADD_VFPR64_M8_MASK, VFMADD_VF, 0x3, 0x0 }, // 1461 |
7453 | | { PseudoVFMADD_VFPR16_MF4, VFMADD_VF, 0x6, 0x0 }, // 1462 |
7454 | | { PseudoVFMADD_VFPR16_MF4_MASK, VFMADD_VF, 0x6, 0x0 }, // 1463 |
7455 | | { PseudoVFMADD_VFPR16_MF2, VFMADD_VF, 0x7, 0x0 }, // 1464 |
7456 | | { PseudoVFMADD_VFPR16_MF2_MASK, VFMADD_VF, 0x7, 0x0 }, // 1465 |
7457 | | { PseudoVFMADD_VFPR32_MF2, VFMADD_VF, 0x7, 0x0 }, // 1466 |
7458 | | { PseudoVFMADD_VFPR32_MF2_MASK, VFMADD_VF, 0x7, 0x0 }, // 1467 |
7459 | | { PseudoVFMADD_VV_M1, VFMADD_VV, 0x0, 0x0 }, // 1468 |
7460 | | { PseudoVFMADD_VV_M1_MASK, VFMADD_VV, 0x0, 0x0 }, // 1469 |
7461 | | { PseudoVFMADD_VV_M2, VFMADD_VV, 0x1, 0x0 }, // 1470 |
7462 | | { PseudoVFMADD_VV_M2_MASK, VFMADD_VV, 0x1, 0x0 }, // 1471 |
7463 | | { PseudoVFMADD_VV_M4, VFMADD_VV, 0x2, 0x0 }, // 1472 |
7464 | | { PseudoVFMADD_VV_M4_MASK, VFMADD_VV, 0x2, 0x0 }, // 1473 |
7465 | | { PseudoVFMADD_VV_M8, VFMADD_VV, 0x3, 0x0 }, // 1474 |
7466 | | { PseudoVFMADD_VV_M8_MASK, VFMADD_VV, 0x3, 0x0 }, // 1475 |
7467 | | { PseudoVFMADD_VV_MF4, VFMADD_VV, 0x6, 0x0 }, // 1476 |
7468 | | { PseudoVFMADD_VV_MF4_MASK, VFMADD_VV, 0x6, 0x0 }, // 1477 |
7469 | | { PseudoVFMADD_VV_MF2, VFMADD_VV, 0x7, 0x0 }, // 1478 |
7470 | | { PseudoVFMADD_VV_MF2_MASK, VFMADD_VV, 0x7, 0x0 }, // 1479 |
7471 | | { PseudoVFMAX_VFPR16_M1, VFMAX_VF, 0x0, 0x0 }, // 1480 |
7472 | | { PseudoVFMAX_VFPR16_M1_MASK, VFMAX_VF, 0x0, 0x0 }, // 1481 |
7473 | | { PseudoVFMAX_VFPR32_M1, VFMAX_VF, 0x0, 0x0 }, // 1482 |
7474 | | { PseudoVFMAX_VFPR32_M1_MASK, VFMAX_VF, 0x0, 0x0 }, // 1483 |
7475 | | { PseudoVFMAX_VFPR64_M1, VFMAX_VF, 0x0, 0x0 }, // 1484 |
7476 | | { PseudoVFMAX_VFPR64_M1_MASK, VFMAX_VF, 0x0, 0x0 }, // 1485 |
7477 | | { PseudoVFMAX_VFPR16_M2, VFMAX_VF, 0x1, 0x0 }, // 1486 |
7478 | | { PseudoVFMAX_VFPR16_M2_MASK, VFMAX_VF, 0x1, 0x0 }, // 1487 |
7479 | | { PseudoVFMAX_VFPR32_M2, VFMAX_VF, 0x1, 0x0 }, // 1488 |
7480 | | { PseudoVFMAX_VFPR32_M2_MASK, VFMAX_VF, 0x1, 0x0 }, // 1489 |
7481 | | { PseudoVFMAX_VFPR64_M2, VFMAX_VF, 0x1, 0x0 }, // 1490 |
7482 | | { PseudoVFMAX_VFPR64_M2_MASK, VFMAX_VF, 0x1, 0x0 }, // 1491 |
7483 | | { PseudoVFMAX_VFPR16_M4, VFMAX_VF, 0x2, 0x0 }, // 1492 |
7484 | | { PseudoVFMAX_VFPR16_M4_MASK, VFMAX_VF, 0x2, 0x0 }, // 1493 |
7485 | | { PseudoVFMAX_VFPR32_M4, VFMAX_VF, 0x2, 0x0 }, // 1494 |
7486 | | { PseudoVFMAX_VFPR32_M4_MASK, VFMAX_VF, 0x2, 0x0 }, // 1495 |
7487 | | { PseudoVFMAX_VFPR64_M4, VFMAX_VF, 0x2, 0x0 }, // 1496 |
7488 | | { PseudoVFMAX_VFPR64_M4_MASK, VFMAX_VF, 0x2, 0x0 }, // 1497 |
7489 | | { PseudoVFMAX_VFPR16_M8, VFMAX_VF, 0x3, 0x0 }, // 1498 |
7490 | | { PseudoVFMAX_VFPR16_M8_MASK, VFMAX_VF, 0x3, 0x0 }, // 1499 |
7491 | | { PseudoVFMAX_VFPR32_M8, VFMAX_VF, 0x3, 0x0 }, // 1500 |
7492 | | { PseudoVFMAX_VFPR32_M8_MASK, VFMAX_VF, 0x3, 0x0 }, // 1501 |
7493 | | { PseudoVFMAX_VFPR64_M8, VFMAX_VF, 0x3, 0x0 }, // 1502 |
7494 | | { PseudoVFMAX_VFPR64_M8_MASK, VFMAX_VF, 0x3, 0x0 }, // 1503 |
7495 | | { PseudoVFMAX_VFPR16_MF4, VFMAX_VF, 0x6, 0x0 }, // 1504 |
7496 | | { PseudoVFMAX_VFPR16_MF4_MASK, VFMAX_VF, 0x6, 0x0 }, // 1505 |
7497 | | { PseudoVFMAX_VFPR16_MF2, VFMAX_VF, 0x7, 0x0 }, // 1506 |
7498 | | { PseudoVFMAX_VFPR16_MF2_MASK, VFMAX_VF, 0x7, 0x0 }, // 1507 |
7499 | | { PseudoVFMAX_VFPR32_MF2, VFMAX_VF, 0x7, 0x0 }, // 1508 |
7500 | | { PseudoVFMAX_VFPR32_MF2_MASK, VFMAX_VF, 0x7, 0x0 }, // 1509 |
7501 | | { PseudoVFMAX_VV_M1, VFMAX_VV, 0x0, 0x0 }, // 1510 |
7502 | | { PseudoVFMAX_VV_M1_MASK, VFMAX_VV, 0x0, 0x0 }, // 1511 |
7503 | | { PseudoVFMAX_VV_M2, VFMAX_VV, 0x1, 0x0 }, // 1512 |
7504 | | { PseudoVFMAX_VV_M2_MASK, VFMAX_VV, 0x1, 0x0 }, // 1513 |
7505 | | { PseudoVFMAX_VV_M4, VFMAX_VV, 0x2, 0x0 }, // 1514 |
7506 | | { PseudoVFMAX_VV_M4_MASK, VFMAX_VV, 0x2, 0x0 }, // 1515 |
7507 | | { PseudoVFMAX_VV_M8, VFMAX_VV, 0x3, 0x0 }, // 1516 |
7508 | | { PseudoVFMAX_VV_M8_MASK, VFMAX_VV, 0x3, 0x0 }, // 1517 |
7509 | | { PseudoVFMAX_VV_MF4, VFMAX_VV, 0x6, 0x0 }, // 1518 |
7510 | | { PseudoVFMAX_VV_MF4_MASK, VFMAX_VV, 0x6, 0x0 }, // 1519 |
7511 | | { PseudoVFMAX_VV_MF2, VFMAX_VV, 0x7, 0x0 }, // 1520 |
7512 | | { PseudoVFMAX_VV_MF2_MASK, VFMAX_VV, 0x7, 0x0 }, // 1521 |
7513 | | { PseudoVFMERGE_VFPR16M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1522 |
7514 | | { PseudoVFMERGE_VFPR32M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1523 |
7515 | | { PseudoVFMERGE_VFPR64M_M1, VFMERGE_VFM, 0x0, 0x0 }, // 1524 |
7516 | | { PseudoVFMERGE_VFPR16M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1525 |
7517 | | { PseudoVFMERGE_VFPR32M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1526 |
7518 | | { PseudoVFMERGE_VFPR64M_M2, VFMERGE_VFM, 0x1, 0x0 }, // 1527 |
7519 | | { PseudoVFMERGE_VFPR16M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1528 |
7520 | | { PseudoVFMERGE_VFPR32M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1529 |
7521 | | { PseudoVFMERGE_VFPR64M_M4, VFMERGE_VFM, 0x2, 0x0 }, // 1530 |
7522 | | { PseudoVFMERGE_VFPR16M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1531 |
7523 | | { PseudoVFMERGE_VFPR32M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1532 |
7524 | | { PseudoVFMERGE_VFPR64M_M8, VFMERGE_VFM, 0x3, 0x0 }, // 1533 |
7525 | | { PseudoVFMERGE_VFPR16M_MF4, VFMERGE_VFM, 0x6, 0x0 }, // 1534 |
7526 | | { PseudoVFMERGE_VFPR16M_MF2, VFMERGE_VFM, 0x7, 0x0 }, // 1535 |
7527 | | { PseudoVFMERGE_VFPR32M_MF2, VFMERGE_VFM, 0x7, 0x0 }, // 1536 |
7528 | | { PseudoVFMIN_VFPR16_M1, VFMIN_VF, 0x0, 0x0 }, // 1537 |
7529 | | { PseudoVFMIN_VFPR16_M1_MASK, VFMIN_VF, 0x0, 0x0 }, // 1538 |
7530 | | { PseudoVFMIN_VFPR32_M1, VFMIN_VF, 0x0, 0x0 }, // 1539 |
7531 | | { PseudoVFMIN_VFPR32_M1_MASK, VFMIN_VF, 0x0, 0x0 }, // 1540 |
7532 | | { PseudoVFMIN_VFPR64_M1, VFMIN_VF, 0x0, 0x0 }, // 1541 |
7533 | | { PseudoVFMIN_VFPR64_M1_MASK, VFMIN_VF, 0x0, 0x0 }, // 1542 |
7534 | | { PseudoVFMIN_VFPR16_M2, VFMIN_VF, 0x1, 0x0 }, // 1543 |
7535 | | { PseudoVFMIN_VFPR16_M2_MASK, VFMIN_VF, 0x1, 0x0 }, // 1544 |
7536 | | { PseudoVFMIN_VFPR32_M2, VFMIN_VF, 0x1, 0x0 }, // 1545 |
7537 | | { PseudoVFMIN_VFPR32_M2_MASK, VFMIN_VF, 0x1, 0x0 }, // 1546 |
7538 | | { PseudoVFMIN_VFPR64_M2, VFMIN_VF, 0x1, 0x0 }, // 1547 |
7539 | | { PseudoVFMIN_VFPR64_M2_MASK, VFMIN_VF, 0x1, 0x0 }, // 1548 |
7540 | | { PseudoVFMIN_VFPR16_M4, VFMIN_VF, 0x2, 0x0 }, // 1549 |
7541 | | { PseudoVFMIN_VFPR16_M4_MASK, VFMIN_VF, 0x2, 0x0 }, // 1550 |
7542 | | { PseudoVFMIN_VFPR32_M4, VFMIN_VF, 0x2, 0x0 }, // 1551 |
7543 | | { PseudoVFMIN_VFPR32_M4_MASK, VFMIN_VF, 0x2, 0x0 }, // 1552 |
7544 | | { PseudoVFMIN_VFPR64_M4, VFMIN_VF, 0x2, 0x0 }, // 1553 |
7545 | | { PseudoVFMIN_VFPR64_M4_MASK, VFMIN_VF, 0x2, 0x0 }, // 1554 |
7546 | | { PseudoVFMIN_VFPR16_M8, VFMIN_VF, 0x3, 0x0 }, // 1555 |
7547 | | { PseudoVFMIN_VFPR16_M8_MASK, VFMIN_VF, 0x3, 0x0 }, // 1556 |
7548 | | { PseudoVFMIN_VFPR32_M8, VFMIN_VF, 0x3, 0x0 }, // 1557 |
7549 | | { PseudoVFMIN_VFPR32_M8_MASK, VFMIN_VF, 0x3, 0x0 }, // 1558 |
7550 | | { PseudoVFMIN_VFPR64_M8, VFMIN_VF, 0x3, 0x0 }, // 1559 |
7551 | | { PseudoVFMIN_VFPR64_M8_MASK, VFMIN_VF, 0x3, 0x0 }, // 1560 |
7552 | | { PseudoVFMIN_VFPR16_MF4, VFMIN_VF, 0x6, 0x0 }, // 1561 |
7553 | | { PseudoVFMIN_VFPR16_MF4_MASK, VFMIN_VF, 0x6, 0x0 }, // 1562 |
7554 | | { PseudoVFMIN_VFPR16_MF2, VFMIN_VF, 0x7, 0x0 }, // 1563 |
7555 | | { PseudoVFMIN_VFPR16_MF2_MASK, VFMIN_VF, 0x7, 0x0 }, // 1564 |
7556 | | { PseudoVFMIN_VFPR32_MF2, VFMIN_VF, 0x7, 0x0 }, // 1565 |
7557 | | { PseudoVFMIN_VFPR32_MF2_MASK, VFMIN_VF, 0x7, 0x0 }, // 1566 |
7558 | | { PseudoVFMIN_VV_M1, VFMIN_VV, 0x0, 0x0 }, // 1567 |
7559 | | { PseudoVFMIN_VV_M1_MASK, VFMIN_VV, 0x0, 0x0 }, // 1568 |
7560 | | { PseudoVFMIN_VV_M2, VFMIN_VV, 0x1, 0x0 }, // 1569 |
7561 | | { PseudoVFMIN_VV_M2_MASK, VFMIN_VV, 0x1, 0x0 }, // 1570 |
7562 | | { PseudoVFMIN_VV_M4, VFMIN_VV, 0x2, 0x0 }, // 1571 |
7563 | | { PseudoVFMIN_VV_M4_MASK, VFMIN_VV, 0x2, 0x0 }, // 1572 |
7564 | | { PseudoVFMIN_VV_M8, VFMIN_VV, 0x3, 0x0 }, // 1573 |
7565 | | { PseudoVFMIN_VV_M8_MASK, VFMIN_VV, 0x3, 0x0 }, // 1574 |
7566 | | { PseudoVFMIN_VV_MF4, VFMIN_VV, 0x6, 0x0 }, // 1575 |
7567 | | { PseudoVFMIN_VV_MF4_MASK, VFMIN_VV, 0x6, 0x0 }, // 1576 |
7568 | | { PseudoVFMIN_VV_MF2, VFMIN_VV, 0x7, 0x0 }, // 1577 |
7569 | | { PseudoVFMIN_VV_MF2_MASK, VFMIN_VV, 0x7, 0x0 }, // 1578 |
7570 | | { PseudoVFMSAC_VFPR16_M1, VFMSAC_VF, 0x0, 0x0 }, // 1579 |
7571 | | { PseudoVFMSAC_VFPR16_M1_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1580 |
7572 | | { PseudoVFMSAC_VFPR32_M1, VFMSAC_VF, 0x0, 0x0 }, // 1581 |
7573 | | { PseudoVFMSAC_VFPR32_M1_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1582 |
7574 | | { PseudoVFMSAC_VFPR64_M1, VFMSAC_VF, 0x0, 0x0 }, // 1583 |
7575 | | { PseudoVFMSAC_VFPR64_M1_MASK, VFMSAC_VF, 0x0, 0x0 }, // 1584 |
7576 | | { PseudoVFMSAC_VFPR16_M2, VFMSAC_VF, 0x1, 0x0 }, // 1585 |
7577 | | { PseudoVFMSAC_VFPR16_M2_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1586 |
7578 | | { PseudoVFMSAC_VFPR32_M2, VFMSAC_VF, 0x1, 0x0 }, // 1587 |
7579 | | { PseudoVFMSAC_VFPR32_M2_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1588 |
7580 | | { PseudoVFMSAC_VFPR64_M2, VFMSAC_VF, 0x1, 0x0 }, // 1589 |
7581 | | { PseudoVFMSAC_VFPR64_M2_MASK, VFMSAC_VF, 0x1, 0x0 }, // 1590 |
7582 | | { PseudoVFMSAC_VFPR16_M4, VFMSAC_VF, 0x2, 0x0 }, // 1591 |
7583 | | { PseudoVFMSAC_VFPR16_M4_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1592 |
7584 | | { PseudoVFMSAC_VFPR32_M4, VFMSAC_VF, 0x2, 0x0 }, // 1593 |
7585 | | { PseudoVFMSAC_VFPR32_M4_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1594 |
7586 | | { PseudoVFMSAC_VFPR64_M4, VFMSAC_VF, 0x2, 0x0 }, // 1595 |
7587 | | { PseudoVFMSAC_VFPR64_M4_MASK, VFMSAC_VF, 0x2, 0x0 }, // 1596 |
7588 | | { PseudoVFMSAC_VFPR16_M8, VFMSAC_VF, 0x3, 0x0 }, // 1597 |
7589 | | { PseudoVFMSAC_VFPR16_M8_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1598 |
7590 | | { PseudoVFMSAC_VFPR32_M8, VFMSAC_VF, 0x3, 0x0 }, // 1599 |
7591 | | { PseudoVFMSAC_VFPR32_M8_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1600 |
7592 | | { PseudoVFMSAC_VFPR64_M8, VFMSAC_VF, 0x3, 0x0 }, // 1601 |
7593 | | { PseudoVFMSAC_VFPR64_M8_MASK, VFMSAC_VF, 0x3, 0x0 }, // 1602 |
7594 | | { PseudoVFMSAC_VFPR16_MF4, VFMSAC_VF, 0x6, 0x0 }, // 1603 |
7595 | | { PseudoVFMSAC_VFPR16_MF4_MASK, VFMSAC_VF, 0x6, 0x0 }, // 1604 |
7596 | | { PseudoVFMSAC_VFPR16_MF2, VFMSAC_VF, 0x7, 0x0 }, // 1605 |
7597 | | { PseudoVFMSAC_VFPR16_MF2_MASK, VFMSAC_VF, 0x7, 0x0 }, // 1606 |
7598 | | { PseudoVFMSAC_VFPR32_MF2, VFMSAC_VF, 0x7, 0x0 }, // 1607 |
7599 | | { PseudoVFMSAC_VFPR32_MF2_MASK, VFMSAC_VF, 0x7, 0x0 }, // 1608 |
7600 | | { PseudoVFMSAC_VV_M1, VFMSAC_VV, 0x0, 0x0 }, // 1609 |
7601 | | { PseudoVFMSAC_VV_M1_MASK, VFMSAC_VV, 0x0, 0x0 }, // 1610 |
7602 | | { PseudoVFMSAC_VV_M2, VFMSAC_VV, 0x1, 0x0 }, // 1611 |
7603 | | { PseudoVFMSAC_VV_M2_MASK, VFMSAC_VV, 0x1, 0x0 }, // 1612 |
7604 | | { PseudoVFMSAC_VV_M4, VFMSAC_VV, 0x2, 0x0 }, // 1613 |
7605 | | { PseudoVFMSAC_VV_M4_MASK, VFMSAC_VV, 0x2, 0x0 }, // 1614 |
7606 | | { PseudoVFMSAC_VV_M8, VFMSAC_VV, 0x3, 0x0 }, // 1615 |
7607 | | { PseudoVFMSAC_VV_M8_MASK, VFMSAC_VV, 0x3, 0x0 }, // 1616 |
7608 | | { PseudoVFMSAC_VV_MF4, VFMSAC_VV, 0x6, 0x0 }, // 1617 |
7609 | | { PseudoVFMSAC_VV_MF4_MASK, VFMSAC_VV, 0x6, 0x0 }, // 1618 |
7610 | | { PseudoVFMSAC_VV_MF2, VFMSAC_VV, 0x7, 0x0 }, // 1619 |
7611 | | { PseudoVFMSAC_VV_MF2_MASK, VFMSAC_VV, 0x7, 0x0 }, // 1620 |
7612 | | { PseudoVFMSUB_VFPR16_M1, VFMSUB_VF, 0x0, 0x0 }, // 1621 |
7613 | | { PseudoVFMSUB_VFPR16_M1_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1622 |
7614 | | { PseudoVFMSUB_VFPR32_M1, VFMSUB_VF, 0x0, 0x0 }, // 1623 |
7615 | | { PseudoVFMSUB_VFPR32_M1_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1624 |
7616 | | { PseudoVFMSUB_VFPR64_M1, VFMSUB_VF, 0x0, 0x0 }, // 1625 |
7617 | | { PseudoVFMSUB_VFPR64_M1_MASK, VFMSUB_VF, 0x0, 0x0 }, // 1626 |
7618 | | { PseudoVFMSUB_VFPR16_M2, VFMSUB_VF, 0x1, 0x0 }, // 1627 |
7619 | | { PseudoVFMSUB_VFPR16_M2_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1628 |
7620 | | { PseudoVFMSUB_VFPR32_M2, VFMSUB_VF, 0x1, 0x0 }, // 1629 |
7621 | | { PseudoVFMSUB_VFPR32_M2_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1630 |
7622 | | { PseudoVFMSUB_VFPR64_M2, VFMSUB_VF, 0x1, 0x0 }, // 1631 |
7623 | | { PseudoVFMSUB_VFPR64_M2_MASK, VFMSUB_VF, 0x1, 0x0 }, // 1632 |
7624 | | { PseudoVFMSUB_VFPR16_M4, VFMSUB_VF, 0x2, 0x0 }, // 1633 |
7625 | | { PseudoVFMSUB_VFPR16_M4_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1634 |
7626 | | { PseudoVFMSUB_VFPR32_M4, VFMSUB_VF, 0x2, 0x0 }, // 1635 |
7627 | | { PseudoVFMSUB_VFPR32_M4_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1636 |
7628 | | { PseudoVFMSUB_VFPR64_M4, VFMSUB_VF, 0x2, 0x0 }, // 1637 |
7629 | | { PseudoVFMSUB_VFPR64_M4_MASK, VFMSUB_VF, 0x2, 0x0 }, // 1638 |
7630 | | { PseudoVFMSUB_VFPR16_M8, VFMSUB_VF, 0x3, 0x0 }, // 1639 |
7631 | | { PseudoVFMSUB_VFPR16_M8_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1640 |
7632 | | { PseudoVFMSUB_VFPR32_M8, VFMSUB_VF, 0x3, 0x0 }, // 1641 |
7633 | | { PseudoVFMSUB_VFPR32_M8_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1642 |
7634 | | { PseudoVFMSUB_VFPR64_M8, VFMSUB_VF, 0x3, 0x0 }, // 1643 |
7635 | | { PseudoVFMSUB_VFPR64_M8_MASK, VFMSUB_VF, 0x3, 0x0 }, // 1644 |
7636 | | { PseudoVFMSUB_VFPR16_MF4, VFMSUB_VF, 0x6, 0x0 }, // 1645 |
7637 | | { PseudoVFMSUB_VFPR16_MF4_MASK, VFMSUB_VF, 0x6, 0x0 }, // 1646 |
7638 | | { PseudoVFMSUB_VFPR16_MF2, VFMSUB_VF, 0x7, 0x0 }, // 1647 |
7639 | | { PseudoVFMSUB_VFPR16_MF2_MASK, VFMSUB_VF, 0x7, 0x0 }, // 1648 |
7640 | | { PseudoVFMSUB_VFPR32_MF2, VFMSUB_VF, 0x7, 0x0 }, // 1649 |
7641 | | { PseudoVFMSUB_VFPR32_MF2_MASK, VFMSUB_VF, 0x7, 0x0 }, // 1650 |
7642 | | { PseudoVFMSUB_VV_M1, VFMSUB_VV, 0x0, 0x0 }, // 1651 |
7643 | | { PseudoVFMSUB_VV_M1_MASK, VFMSUB_VV, 0x0, 0x0 }, // 1652 |
7644 | | { PseudoVFMSUB_VV_M2, VFMSUB_VV, 0x1, 0x0 }, // 1653 |
7645 | | { PseudoVFMSUB_VV_M2_MASK, VFMSUB_VV, 0x1, 0x0 }, // 1654 |
7646 | | { PseudoVFMSUB_VV_M4, VFMSUB_VV, 0x2, 0x0 }, // 1655 |
7647 | | { PseudoVFMSUB_VV_M4_MASK, VFMSUB_VV, 0x2, 0x0 }, // 1656 |
7648 | | { PseudoVFMSUB_VV_M8, VFMSUB_VV, 0x3, 0x0 }, // 1657 |
7649 | | { PseudoVFMSUB_VV_M8_MASK, VFMSUB_VV, 0x3, 0x0 }, // 1658 |
7650 | | { PseudoVFMSUB_VV_MF4, VFMSUB_VV, 0x6, 0x0 }, // 1659 |
7651 | | { PseudoVFMSUB_VV_MF4_MASK, VFMSUB_VV, 0x6, 0x0 }, // 1660 |
7652 | | { PseudoVFMSUB_VV_MF2, VFMSUB_VV, 0x7, 0x0 }, // 1661 |
7653 | | { PseudoVFMSUB_VV_MF2_MASK, VFMSUB_VV, 0x7, 0x0 }, // 1662 |
7654 | | { PseudoVFMUL_VFPR16_M1, VFMUL_VF, 0x0, 0x0 }, // 1663 |
7655 | | { PseudoVFMUL_VFPR16_M1_MASK, VFMUL_VF, 0x0, 0x0 }, // 1664 |
7656 | | { PseudoVFMUL_VFPR32_M1, VFMUL_VF, 0x0, 0x0 }, // 1665 |
7657 | | { PseudoVFMUL_VFPR32_M1_MASK, VFMUL_VF, 0x0, 0x0 }, // 1666 |
7658 | | { PseudoVFMUL_VFPR64_M1, VFMUL_VF, 0x0, 0x0 }, // 1667 |
7659 | | { PseudoVFMUL_VFPR64_M1_MASK, VFMUL_VF, 0x0, 0x0 }, // 1668 |
7660 | | { PseudoVFMUL_VFPR16_M2, VFMUL_VF, 0x1, 0x0 }, // 1669 |
7661 | | { PseudoVFMUL_VFPR16_M2_MASK, VFMUL_VF, 0x1, 0x0 }, // 1670 |
7662 | | { PseudoVFMUL_VFPR32_M2, VFMUL_VF, 0x1, 0x0 }, // 1671 |
7663 | | { PseudoVFMUL_VFPR32_M2_MASK, VFMUL_VF, 0x1, 0x0 }, // 1672 |
7664 | | { PseudoVFMUL_VFPR64_M2, VFMUL_VF, 0x1, 0x0 }, // 1673 |
7665 | | { PseudoVFMUL_VFPR64_M2_MASK, VFMUL_VF, 0x1, 0x0 }, // 1674 |
7666 | | { PseudoVFMUL_VFPR16_M4, VFMUL_VF, 0x2, 0x0 }, // 1675 |
7667 | | { PseudoVFMUL_VFPR16_M4_MASK, VFMUL_VF, 0x2, 0x0 }, // 1676 |
7668 | | { PseudoVFMUL_VFPR32_M4, VFMUL_VF, 0x2, 0x0 }, // 1677 |
7669 | | { PseudoVFMUL_VFPR32_M4_MASK, VFMUL_VF, 0x2, 0x0 }, // 1678 |
7670 | | { PseudoVFMUL_VFPR64_M4, VFMUL_VF, 0x2, 0x0 }, // 1679 |
7671 | | { PseudoVFMUL_VFPR64_M4_MASK, VFMUL_VF, 0x2, 0x0 }, // 1680 |
7672 | | { PseudoVFMUL_VFPR16_M8, VFMUL_VF, 0x3, 0x0 }, // 1681 |
7673 | | { PseudoVFMUL_VFPR16_M8_MASK, VFMUL_VF, 0x3, 0x0 }, // 1682 |
7674 | | { PseudoVFMUL_VFPR32_M8, VFMUL_VF, 0x3, 0x0 }, // 1683 |
7675 | | { PseudoVFMUL_VFPR32_M8_MASK, VFMUL_VF, 0x3, 0x0 }, // 1684 |
7676 | | { PseudoVFMUL_VFPR64_M8, VFMUL_VF, 0x3, 0x0 }, // 1685 |
7677 | | { PseudoVFMUL_VFPR64_M8_MASK, VFMUL_VF, 0x3, 0x0 }, // 1686 |
7678 | | { PseudoVFMUL_VFPR16_MF4, VFMUL_VF, 0x6, 0x0 }, // 1687 |
7679 | | { PseudoVFMUL_VFPR16_MF4_MASK, VFMUL_VF, 0x6, 0x0 }, // 1688 |
7680 | | { PseudoVFMUL_VFPR16_MF2, VFMUL_VF, 0x7, 0x0 }, // 1689 |
7681 | | { PseudoVFMUL_VFPR16_MF2_MASK, VFMUL_VF, 0x7, 0x0 }, // 1690 |
7682 | | { PseudoVFMUL_VFPR32_MF2, VFMUL_VF, 0x7, 0x0 }, // 1691 |
7683 | | { PseudoVFMUL_VFPR32_MF2_MASK, VFMUL_VF, 0x7, 0x0 }, // 1692 |
7684 | | { PseudoVFMUL_VV_M1, VFMUL_VV, 0x0, 0x0 }, // 1693 |
7685 | | { PseudoVFMUL_VV_M1_MASK, VFMUL_VV, 0x0, 0x0 }, // 1694 |
7686 | | { PseudoVFMUL_VV_M2, VFMUL_VV, 0x1, 0x0 }, // 1695 |
7687 | | { PseudoVFMUL_VV_M2_MASK, VFMUL_VV, 0x1, 0x0 }, // 1696 |
7688 | | { PseudoVFMUL_VV_M4, VFMUL_VV, 0x2, 0x0 }, // 1697 |
7689 | | { PseudoVFMUL_VV_M4_MASK, VFMUL_VV, 0x2, 0x0 }, // 1698 |
7690 | | { PseudoVFMUL_VV_M8, VFMUL_VV, 0x3, 0x0 }, // 1699 |
7691 | | { PseudoVFMUL_VV_M8_MASK, VFMUL_VV, 0x3, 0x0 }, // 1700 |
7692 | | { PseudoVFMUL_VV_MF4, VFMUL_VV, 0x6, 0x0 }, // 1701 |
7693 | | { PseudoVFMUL_VV_MF4_MASK, VFMUL_VV, 0x6, 0x0 }, // 1702 |
7694 | | { PseudoVFMUL_VV_MF2, VFMUL_VV, 0x7, 0x0 }, // 1703 |
7695 | | { PseudoVFMUL_VV_MF2_MASK, VFMUL_VV, 0x7, 0x0 }, // 1704 |
7696 | | { PseudoVFMV_FPR16_S_M1, VFMV_F_S, 0x0, 0x0 }, // 1705 |
7697 | | { PseudoVFMV_FPR32_S_M1, VFMV_F_S, 0x0, 0x0 }, // 1706 |
7698 | | { PseudoVFMV_FPR64_S_M1, VFMV_F_S, 0x0, 0x0 }, // 1707 |
7699 | | { PseudoVFMV_FPR16_S_M2, VFMV_F_S, 0x1, 0x0 }, // 1708 |
7700 | | { PseudoVFMV_FPR32_S_M2, VFMV_F_S, 0x1, 0x0 }, // 1709 |
7701 | | { PseudoVFMV_FPR64_S_M2, VFMV_F_S, 0x1, 0x0 }, // 1710 |
7702 | | { PseudoVFMV_FPR16_S_M4, VFMV_F_S, 0x2, 0x0 }, // 1711 |
7703 | | { PseudoVFMV_FPR32_S_M4, VFMV_F_S, 0x2, 0x0 }, // 1712 |
7704 | | { PseudoVFMV_FPR64_S_M4, VFMV_F_S, 0x2, 0x0 }, // 1713 |
7705 | | { PseudoVFMV_FPR16_S_M8, VFMV_F_S, 0x3, 0x0 }, // 1714 |
7706 | | { PseudoVFMV_FPR32_S_M8, VFMV_F_S, 0x3, 0x0 }, // 1715 |
7707 | | { PseudoVFMV_FPR64_S_M8, VFMV_F_S, 0x3, 0x0 }, // 1716 |
7708 | | { PseudoVFMV_FPR16_S_MF4, VFMV_F_S, 0x6, 0x0 }, // 1717 |
7709 | | { PseudoVFMV_FPR16_S_MF2, VFMV_F_S, 0x7, 0x0 }, // 1718 |
7710 | | { PseudoVFMV_FPR32_S_MF2, VFMV_F_S, 0x7, 0x0 }, // 1719 |
7711 | | { PseudoVFMV_S_FPR16_M1, VFMV_S_F, 0x0, 0x0 }, // 1720 |
7712 | | { PseudoVFMV_S_FPR32_M1, VFMV_S_F, 0x0, 0x0 }, // 1721 |
7713 | | { PseudoVFMV_S_FPR64_M1, VFMV_S_F, 0x0, 0x0 }, // 1722 |
7714 | | { PseudoVFMV_S_FPR16_M2, VFMV_S_F, 0x1, 0x0 }, // 1723 |
7715 | | { PseudoVFMV_S_FPR32_M2, VFMV_S_F, 0x1, 0x0 }, // 1724 |
7716 | | { PseudoVFMV_S_FPR64_M2, VFMV_S_F, 0x1, 0x0 }, // 1725 |
7717 | | { PseudoVFMV_S_FPR16_M4, VFMV_S_F, 0x2, 0x0 }, // 1726 |
7718 | | { PseudoVFMV_S_FPR32_M4, VFMV_S_F, 0x2, 0x0 }, // 1727 |
7719 | | { PseudoVFMV_S_FPR64_M4, VFMV_S_F, 0x2, 0x0 }, // 1728 |
7720 | | { PseudoVFMV_S_FPR16_M8, VFMV_S_F, 0x3, 0x0 }, // 1729 |
7721 | | { PseudoVFMV_S_FPR32_M8, VFMV_S_F, 0x3, 0x0 }, // 1730 |
7722 | | { PseudoVFMV_S_FPR64_M8, VFMV_S_F, 0x3, 0x0 }, // 1731 |
7723 | | { PseudoVFMV_S_FPR16_MF4, VFMV_S_F, 0x6, 0x0 }, // 1732 |
7724 | | { PseudoVFMV_S_FPR16_MF2, VFMV_S_F, 0x7, 0x0 }, // 1733 |
7725 | | { PseudoVFMV_S_FPR32_MF2, VFMV_S_F, 0x7, 0x0 }, // 1734 |
7726 | | { PseudoVFMV_V_FPR16_M1, VFMV_V_F, 0x0, 0x0 }, // 1735 |
7727 | | { PseudoVFMV_V_FPR32_M1, VFMV_V_F, 0x0, 0x0 }, // 1736 |
7728 | | { PseudoVFMV_V_FPR64_M1, VFMV_V_F, 0x0, 0x0 }, // 1737 |
7729 | | { PseudoVFMV_V_FPR16_M2, VFMV_V_F, 0x1, 0x0 }, // 1738 |
7730 | | { PseudoVFMV_V_FPR32_M2, VFMV_V_F, 0x1, 0x0 }, // 1739 |
7731 | | { PseudoVFMV_V_FPR64_M2, VFMV_V_F, 0x1, 0x0 }, // 1740 |
7732 | | { PseudoVFMV_V_FPR16_M4, VFMV_V_F, 0x2, 0x0 }, // 1741 |
7733 | | { PseudoVFMV_V_FPR32_M4, VFMV_V_F, 0x2, 0x0 }, // 1742 |
7734 | | { PseudoVFMV_V_FPR64_M4, VFMV_V_F, 0x2, 0x0 }, // 1743 |
7735 | | { PseudoVFMV_V_FPR16_M8, VFMV_V_F, 0x3, 0x0 }, // 1744 |
7736 | | { PseudoVFMV_V_FPR32_M8, VFMV_V_F, 0x3, 0x0 }, // 1745 |
7737 | | { PseudoVFMV_V_FPR64_M8, VFMV_V_F, 0x3, 0x0 }, // 1746 |
7738 | | { PseudoVFMV_V_FPR16_MF4, VFMV_V_F, 0x6, 0x0 }, // 1747 |
7739 | | { PseudoVFMV_V_FPR16_MF2, VFMV_V_F, 0x7, 0x0 }, // 1748 |
7740 | | { PseudoVFMV_V_FPR32_MF2, VFMV_V_F, 0x7, 0x0 }, // 1749 |
7741 | | { PseudoVFNCVTBF16_F_F_W_M1, VFNCVTBF16_F_F_W, 0x0, 0x0 }, // 1750 |
7742 | | { PseudoVFNCVTBF16_F_F_W_M1_MASK, VFNCVTBF16_F_F_W, 0x0, 0x0 }, // 1751 |
7743 | | { PseudoVFNCVTBF16_F_F_W_M2, VFNCVTBF16_F_F_W, 0x1, 0x0 }, // 1752 |
7744 | | { PseudoVFNCVTBF16_F_F_W_M2_MASK, VFNCVTBF16_F_F_W, 0x1, 0x0 }, // 1753 |
7745 | | { PseudoVFNCVTBF16_F_F_W_M4, VFNCVTBF16_F_F_W, 0x2, 0x0 }, // 1754 |
7746 | | { PseudoVFNCVTBF16_F_F_W_M4_MASK, VFNCVTBF16_F_F_W, 0x2, 0x0 }, // 1755 |
7747 | | { PseudoVFNCVTBF16_F_F_W_MF4, VFNCVTBF16_F_F_W, 0x6, 0x0 }, // 1756 |
7748 | | { PseudoVFNCVTBF16_F_F_W_MF4_MASK, VFNCVTBF16_F_F_W, 0x6, 0x0 }, // 1757 |
7749 | | { PseudoVFNCVTBF16_F_F_W_MF2, VFNCVTBF16_F_F_W, 0x7, 0x0 }, // 1758 |
7750 | | { PseudoVFNCVTBF16_F_F_W_MF2_MASK, VFNCVTBF16_F_F_W, 0x7, 0x0 }, // 1759 |
7751 | | { PseudoVFNCVT_F_F_W_M1, VFNCVT_F_F_W, 0x0, 0x0 }, // 1760 |
7752 | | { PseudoVFNCVT_F_F_W_M1_MASK, VFNCVT_F_F_W, 0x0, 0x0 }, // 1761 |
7753 | | { PseudoVFNCVT_F_F_W_M2, VFNCVT_F_F_W, 0x1, 0x0 }, // 1762 |
7754 | | { PseudoVFNCVT_F_F_W_M2_MASK, VFNCVT_F_F_W, 0x1, 0x0 }, // 1763 |
7755 | | { PseudoVFNCVT_F_F_W_M4, VFNCVT_F_F_W, 0x2, 0x0 }, // 1764 |
7756 | | { PseudoVFNCVT_F_F_W_M4_MASK, VFNCVT_F_F_W, 0x2, 0x0 }, // 1765 |
7757 | | { PseudoVFNCVT_F_F_W_MF4, VFNCVT_F_F_W, 0x6, 0x0 }, // 1766 |
7758 | | { PseudoVFNCVT_F_F_W_MF4_MASK, VFNCVT_F_F_W, 0x6, 0x0 }, // 1767 |
7759 | | { PseudoVFNCVT_F_F_W_MF2, VFNCVT_F_F_W, 0x7, 0x0 }, // 1768 |
7760 | | { PseudoVFNCVT_F_F_W_MF2_MASK, VFNCVT_F_F_W, 0x7, 0x0 }, // 1769 |
7761 | | { PseudoVFNCVT_F_XU_W_M1, VFNCVT_F_XU_W, 0x0, 0x0 }, // 1770 |
7762 | | { PseudoVFNCVT_F_XU_W_M1_MASK, VFNCVT_F_XU_W, 0x0, 0x0 }, // 1771 |
7763 | | { PseudoVFNCVT_RM_F_XU_W_M1, VFNCVT_F_XU_W, 0x0, 0x0 }, // 1772 |
7764 | | { PseudoVFNCVT_RM_F_XU_W_M1_MASK, VFNCVT_F_XU_W, 0x0, 0x0 }, // 1773 |
7765 | | { PseudoVFNCVT_F_XU_W_M2, VFNCVT_F_XU_W, 0x1, 0x0 }, // 1774 |
7766 | | { PseudoVFNCVT_F_XU_W_M2_MASK, VFNCVT_F_XU_W, 0x1, 0x0 }, // 1775 |
7767 | | { PseudoVFNCVT_RM_F_XU_W_M2, VFNCVT_F_XU_W, 0x1, 0x0 }, // 1776 |
7768 | | { PseudoVFNCVT_RM_F_XU_W_M2_MASK, VFNCVT_F_XU_W, 0x1, 0x0 }, // 1777 |
7769 | | { PseudoVFNCVT_F_XU_W_M4, VFNCVT_F_XU_W, 0x2, 0x0 }, // 1778 |
7770 | | { PseudoVFNCVT_F_XU_W_M4_MASK, VFNCVT_F_XU_W, 0x2, 0x0 }, // 1779 |
7771 | | { PseudoVFNCVT_RM_F_XU_W_M4, VFNCVT_F_XU_W, 0x2, 0x0 }, // 1780 |
7772 | | { PseudoVFNCVT_RM_F_XU_W_M4_MASK, VFNCVT_F_XU_W, 0x2, 0x0 }, // 1781 |
7773 | | { PseudoVFNCVT_F_XU_W_MF4, VFNCVT_F_XU_W, 0x6, 0x0 }, // 1782 |
7774 | | { PseudoVFNCVT_F_XU_W_MF4_MASK, VFNCVT_F_XU_W, 0x6, 0x0 }, // 1783 |
7775 | | { PseudoVFNCVT_RM_F_XU_W_MF4, VFNCVT_F_XU_W, 0x6, 0x0 }, // 1784 |
7776 | | { PseudoVFNCVT_RM_F_XU_W_MF4_MASK, VFNCVT_F_XU_W, 0x6, 0x0 }, // 1785 |
7777 | | { PseudoVFNCVT_F_XU_W_MF2, VFNCVT_F_XU_W, 0x7, 0x0 }, // 1786 |
7778 | | { PseudoVFNCVT_F_XU_W_MF2_MASK, VFNCVT_F_XU_W, 0x7, 0x0 }, // 1787 |
7779 | | { PseudoVFNCVT_RM_F_XU_W_MF2, VFNCVT_F_XU_W, 0x7, 0x0 }, // 1788 |
7780 | | { PseudoVFNCVT_RM_F_XU_W_MF2_MASK, VFNCVT_F_XU_W, 0x7, 0x0 }, // 1789 |
7781 | | { PseudoVFNCVT_F_X_W_M1, VFNCVT_F_X_W, 0x0, 0x0 }, // 1790 |
7782 | | { PseudoVFNCVT_F_X_W_M1_MASK, VFNCVT_F_X_W, 0x0, 0x0 }, // 1791 |
7783 | | { PseudoVFNCVT_RM_F_X_W_M1, VFNCVT_F_X_W, 0x0, 0x0 }, // 1792 |
7784 | | { PseudoVFNCVT_RM_F_X_W_M1_MASK, VFNCVT_F_X_W, 0x0, 0x0 }, // 1793 |
7785 | | { PseudoVFNCVT_F_X_W_M2, VFNCVT_F_X_W, 0x1, 0x0 }, // 1794 |
7786 | | { PseudoVFNCVT_F_X_W_M2_MASK, VFNCVT_F_X_W, 0x1, 0x0 }, // 1795 |
7787 | | { PseudoVFNCVT_RM_F_X_W_M2, VFNCVT_F_X_W, 0x1, 0x0 }, // 1796 |
7788 | | { PseudoVFNCVT_RM_F_X_W_M2_MASK, VFNCVT_F_X_W, 0x1, 0x0 }, // 1797 |
7789 | | { PseudoVFNCVT_F_X_W_M4, VFNCVT_F_X_W, 0x2, 0x0 }, // 1798 |
7790 | | { PseudoVFNCVT_F_X_W_M4_MASK, VFNCVT_F_X_W, 0x2, 0x0 }, // 1799 |
7791 | | { PseudoVFNCVT_RM_F_X_W_M4, VFNCVT_F_X_W, 0x2, 0x0 }, // 1800 |
7792 | | { PseudoVFNCVT_RM_F_X_W_M4_MASK, VFNCVT_F_X_W, 0x2, 0x0 }, // 1801 |
7793 | | { PseudoVFNCVT_F_X_W_MF4, VFNCVT_F_X_W, 0x6, 0x0 }, // 1802 |
7794 | | { PseudoVFNCVT_F_X_W_MF4_MASK, VFNCVT_F_X_W, 0x6, 0x0 }, // 1803 |
7795 | | { PseudoVFNCVT_RM_F_X_W_MF4, VFNCVT_F_X_W, 0x6, 0x0 }, // 1804 |
7796 | | { PseudoVFNCVT_RM_F_X_W_MF4_MASK, VFNCVT_F_X_W, 0x6, 0x0 }, // 1805 |
7797 | | { PseudoVFNCVT_F_X_W_MF2, VFNCVT_F_X_W, 0x7, 0x0 }, // 1806 |
7798 | | { PseudoVFNCVT_F_X_W_MF2_MASK, VFNCVT_F_X_W, 0x7, 0x0 }, // 1807 |
7799 | | { PseudoVFNCVT_RM_F_X_W_MF2, VFNCVT_F_X_W, 0x7, 0x0 }, // 1808 |
7800 | | { PseudoVFNCVT_RM_F_X_W_MF2_MASK, VFNCVT_F_X_W, 0x7, 0x0 }, // 1809 |
7801 | | { PseudoVFNCVT_ROD_F_F_W_M1, VFNCVT_ROD_F_F_W, 0x0, 0x0 }, // 1810 |
7802 | | { PseudoVFNCVT_ROD_F_F_W_M1_MASK, VFNCVT_ROD_F_F_W, 0x0, 0x0 }, // 1811 |
7803 | | { PseudoVFNCVT_ROD_F_F_W_M2, VFNCVT_ROD_F_F_W, 0x1, 0x0 }, // 1812 |
7804 | | { PseudoVFNCVT_ROD_F_F_W_M2_MASK, VFNCVT_ROD_F_F_W, 0x1, 0x0 }, // 1813 |
7805 | | { PseudoVFNCVT_ROD_F_F_W_M4, VFNCVT_ROD_F_F_W, 0x2, 0x0 }, // 1814 |
7806 | | { PseudoVFNCVT_ROD_F_F_W_M4_MASK, VFNCVT_ROD_F_F_W, 0x2, 0x0 }, // 1815 |
7807 | | { PseudoVFNCVT_ROD_F_F_W_MF4, VFNCVT_ROD_F_F_W, 0x6, 0x0 }, // 1816 |
7808 | | { PseudoVFNCVT_ROD_F_F_W_MF4_MASK, VFNCVT_ROD_F_F_W, 0x6, 0x0 }, // 1817 |
7809 | | { PseudoVFNCVT_ROD_F_F_W_MF2, VFNCVT_ROD_F_F_W, 0x7, 0x0 }, // 1818 |
7810 | | { PseudoVFNCVT_ROD_F_F_W_MF2_MASK, VFNCVT_ROD_F_F_W, 0x7, 0x0 }, // 1819 |
7811 | | { PseudoVFNCVT_RTZ_XU_F_W_M1, VFNCVT_RTZ_XU_F_W, 0x0, 0x0 }, // 1820 |
7812 | | { PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, VFNCVT_RTZ_XU_F_W, 0x0, 0x0 }, // 1821 |
7813 | | { PseudoVFNCVT_RTZ_XU_F_W_M2, VFNCVT_RTZ_XU_F_W, 0x1, 0x0 }, // 1822 |
7814 | | { PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, VFNCVT_RTZ_XU_F_W, 0x1, 0x0 }, // 1823 |
7815 | | { PseudoVFNCVT_RTZ_XU_F_W_M4, VFNCVT_RTZ_XU_F_W, 0x2, 0x0 }, // 1824 |
7816 | | { PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, VFNCVT_RTZ_XU_F_W, 0x2, 0x0 }, // 1825 |
7817 | | { PseudoVFNCVT_RTZ_XU_F_W_MF8, VFNCVT_RTZ_XU_F_W, 0x5, 0x0 }, // 1826 |
7818 | | { PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, VFNCVT_RTZ_XU_F_W, 0x5, 0x0 }, // 1827 |
7819 | | { PseudoVFNCVT_RTZ_XU_F_W_MF4, VFNCVT_RTZ_XU_F_W, 0x6, 0x0 }, // 1828 |
7820 | | { PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, VFNCVT_RTZ_XU_F_W, 0x6, 0x0 }, // 1829 |
7821 | | { PseudoVFNCVT_RTZ_XU_F_W_MF2, VFNCVT_RTZ_XU_F_W, 0x7, 0x0 }, // 1830 |
7822 | | { PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, VFNCVT_RTZ_XU_F_W, 0x7, 0x0 }, // 1831 |
7823 | | { PseudoVFNCVT_RTZ_X_F_W_M1, VFNCVT_RTZ_X_F_W, 0x0, 0x0 }, // 1832 |
7824 | | { PseudoVFNCVT_RTZ_X_F_W_M1_MASK, VFNCVT_RTZ_X_F_W, 0x0, 0x0 }, // 1833 |
7825 | | { PseudoVFNCVT_RTZ_X_F_W_M2, VFNCVT_RTZ_X_F_W, 0x1, 0x0 }, // 1834 |
7826 | | { PseudoVFNCVT_RTZ_X_F_W_M2_MASK, VFNCVT_RTZ_X_F_W, 0x1, 0x0 }, // 1835 |
7827 | | { PseudoVFNCVT_RTZ_X_F_W_M4, VFNCVT_RTZ_X_F_W, 0x2, 0x0 }, // 1836 |
7828 | | { PseudoVFNCVT_RTZ_X_F_W_M4_MASK, VFNCVT_RTZ_X_F_W, 0x2, 0x0 }, // 1837 |
7829 | | { PseudoVFNCVT_RTZ_X_F_W_MF8, VFNCVT_RTZ_X_F_W, 0x5, 0x0 }, // 1838 |
7830 | | { PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, VFNCVT_RTZ_X_F_W, 0x5, 0x0 }, // 1839 |
7831 | | { PseudoVFNCVT_RTZ_X_F_W_MF4, VFNCVT_RTZ_X_F_W, 0x6, 0x0 }, // 1840 |
7832 | | { PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, VFNCVT_RTZ_X_F_W, 0x6, 0x0 }, // 1841 |
7833 | | { PseudoVFNCVT_RTZ_X_F_W_MF2, VFNCVT_RTZ_X_F_W, 0x7, 0x0 }, // 1842 |
7834 | | { PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, VFNCVT_RTZ_X_F_W, 0x7, 0x0 }, // 1843 |
7835 | | { PseudoVFNCVT_RM_XU_F_W_M1, VFNCVT_XU_F_W, 0x0, 0x0 }, // 1844 |
7836 | | { PseudoVFNCVT_RM_XU_F_W_M1_MASK, VFNCVT_XU_F_W, 0x0, 0x0 }, // 1845 |
7837 | | { PseudoVFNCVT_XU_F_W_M1, VFNCVT_XU_F_W, 0x0, 0x0 }, // 1846 |
7838 | | { PseudoVFNCVT_XU_F_W_M1_MASK, VFNCVT_XU_F_W, 0x0, 0x0 }, // 1847 |
7839 | | { PseudoVFNCVT_RM_XU_F_W_M2, VFNCVT_XU_F_W, 0x1, 0x0 }, // 1848 |
7840 | | { PseudoVFNCVT_RM_XU_F_W_M2_MASK, VFNCVT_XU_F_W, 0x1, 0x0 }, // 1849 |
7841 | | { PseudoVFNCVT_XU_F_W_M2, VFNCVT_XU_F_W, 0x1, 0x0 }, // 1850 |
7842 | | { PseudoVFNCVT_XU_F_W_M2_MASK, VFNCVT_XU_F_W, 0x1, 0x0 }, // 1851 |
7843 | | { PseudoVFNCVT_RM_XU_F_W_M4, VFNCVT_XU_F_W, 0x2, 0x0 }, // 1852 |
7844 | | { PseudoVFNCVT_RM_XU_F_W_M4_MASK, VFNCVT_XU_F_W, 0x2, 0x0 }, // 1853 |
7845 | | { PseudoVFNCVT_XU_F_W_M4, VFNCVT_XU_F_W, 0x2, 0x0 }, // 1854 |
7846 | | { PseudoVFNCVT_XU_F_W_M4_MASK, VFNCVT_XU_F_W, 0x2, 0x0 }, // 1855 |
7847 | | { PseudoVFNCVT_RM_XU_F_W_MF8, VFNCVT_XU_F_W, 0x5, 0x0 }, // 1856 |
7848 | | { PseudoVFNCVT_RM_XU_F_W_MF8_MASK, VFNCVT_XU_F_W, 0x5, 0x0 }, // 1857 |
7849 | | { PseudoVFNCVT_XU_F_W_MF8, VFNCVT_XU_F_W, 0x5, 0x0 }, // 1858 |
7850 | | { PseudoVFNCVT_XU_F_W_MF8_MASK, VFNCVT_XU_F_W, 0x5, 0x0 }, // 1859 |
7851 | | { PseudoVFNCVT_RM_XU_F_W_MF4, VFNCVT_XU_F_W, 0x6, 0x0 }, // 1860 |
7852 | | { PseudoVFNCVT_RM_XU_F_W_MF4_MASK, VFNCVT_XU_F_W, 0x6, 0x0 }, // 1861 |
7853 | | { PseudoVFNCVT_XU_F_W_MF4, VFNCVT_XU_F_W, 0x6, 0x0 }, // 1862 |
7854 | | { PseudoVFNCVT_XU_F_W_MF4_MASK, VFNCVT_XU_F_W, 0x6, 0x0 }, // 1863 |
7855 | | { PseudoVFNCVT_RM_XU_F_W_MF2, VFNCVT_XU_F_W, 0x7, 0x0 }, // 1864 |
7856 | | { PseudoVFNCVT_RM_XU_F_W_MF2_MASK, VFNCVT_XU_F_W, 0x7, 0x0 }, // 1865 |
7857 | | { PseudoVFNCVT_XU_F_W_MF2, VFNCVT_XU_F_W, 0x7, 0x0 }, // 1866 |
7858 | | { PseudoVFNCVT_XU_F_W_MF2_MASK, VFNCVT_XU_F_W, 0x7, 0x0 }, // 1867 |
7859 | | { PseudoVFNCVT_RM_X_F_W_M1, VFNCVT_X_F_W, 0x0, 0x0 }, // 1868 |
7860 | | { PseudoVFNCVT_RM_X_F_W_M1_MASK, VFNCVT_X_F_W, 0x0, 0x0 }, // 1869 |
7861 | | { PseudoVFNCVT_X_F_W_M1, VFNCVT_X_F_W, 0x0, 0x0 }, // 1870 |
7862 | | { PseudoVFNCVT_X_F_W_M1_MASK, VFNCVT_X_F_W, 0x0, 0x0 }, // 1871 |
7863 | | { PseudoVFNCVT_RM_X_F_W_M2, VFNCVT_X_F_W, 0x1, 0x0 }, // 1872 |
7864 | | { PseudoVFNCVT_RM_X_F_W_M2_MASK, VFNCVT_X_F_W, 0x1, 0x0 }, // 1873 |
7865 | | { PseudoVFNCVT_X_F_W_M2, VFNCVT_X_F_W, 0x1, 0x0 }, // 1874 |
7866 | | { PseudoVFNCVT_X_F_W_M2_MASK, VFNCVT_X_F_W, 0x1, 0x0 }, // 1875 |
7867 | | { PseudoVFNCVT_RM_X_F_W_M4, VFNCVT_X_F_W, 0x2, 0x0 }, // 1876 |
7868 | | { PseudoVFNCVT_RM_X_F_W_M4_MASK, VFNCVT_X_F_W, 0x2, 0x0 }, // 1877 |
7869 | | { PseudoVFNCVT_X_F_W_M4, VFNCVT_X_F_W, 0x2, 0x0 }, // 1878 |
7870 | | { PseudoVFNCVT_X_F_W_M4_MASK, VFNCVT_X_F_W, 0x2, 0x0 }, // 1879 |
7871 | | { PseudoVFNCVT_RM_X_F_W_MF8, VFNCVT_X_F_W, 0x5, 0x0 }, // 1880 |
7872 | | { PseudoVFNCVT_RM_X_F_W_MF8_MASK, VFNCVT_X_F_W, 0x5, 0x0 }, // 1881 |
7873 | | { PseudoVFNCVT_X_F_W_MF8, VFNCVT_X_F_W, 0x5, 0x0 }, // 1882 |
7874 | | { PseudoVFNCVT_X_F_W_MF8_MASK, VFNCVT_X_F_W, 0x5, 0x0 }, // 1883 |
7875 | | { PseudoVFNCVT_RM_X_F_W_MF4, VFNCVT_X_F_W, 0x6, 0x0 }, // 1884 |
7876 | | { PseudoVFNCVT_RM_X_F_W_MF4_MASK, VFNCVT_X_F_W, 0x6, 0x0 }, // 1885 |
7877 | | { PseudoVFNCVT_X_F_W_MF4, VFNCVT_X_F_W, 0x6, 0x0 }, // 1886 |
7878 | | { PseudoVFNCVT_X_F_W_MF4_MASK, VFNCVT_X_F_W, 0x6, 0x0 }, // 1887 |
7879 | | { PseudoVFNCVT_RM_X_F_W_MF2, VFNCVT_X_F_W, 0x7, 0x0 }, // 1888 |
7880 | | { PseudoVFNCVT_RM_X_F_W_MF2_MASK, VFNCVT_X_F_W, 0x7, 0x0 }, // 1889 |
7881 | | { PseudoVFNCVT_X_F_W_MF2, VFNCVT_X_F_W, 0x7, 0x0 }, // 1890 |
7882 | | { PseudoVFNCVT_X_F_W_MF2_MASK, VFNCVT_X_F_W, 0x7, 0x0 }, // 1891 |
7883 | | { PseudoVFNMACC_VFPR16_M1, VFNMACC_VF, 0x0, 0x0 }, // 1892 |
7884 | | { PseudoVFNMACC_VFPR16_M1_MASK, VFNMACC_VF, 0x0, 0x0 }, // 1893 |
7885 | | { PseudoVFNMACC_VFPR32_M1, VFNMACC_VF, 0x0, 0x0 }, // 1894 |
7886 | | { PseudoVFNMACC_VFPR32_M1_MASK, VFNMACC_VF, 0x0, 0x0 }, // 1895 |
7887 | | { PseudoVFNMACC_VFPR64_M1, VFNMACC_VF, 0x0, 0x0 }, // 1896 |
7888 | | { PseudoVFNMACC_VFPR64_M1_MASK, VFNMACC_VF, 0x0, 0x0 }, // 1897 |
7889 | | { PseudoVFNMACC_VFPR16_M2, VFNMACC_VF, 0x1, 0x0 }, // 1898 |
7890 | | { PseudoVFNMACC_VFPR16_M2_MASK, VFNMACC_VF, 0x1, 0x0 }, // 1899 |
7891 | | { PseudoVFNMACC_VFPR32_M2, VFNMACC_VF, 0x1, 0x0 }, // 1900 |
7892 | | { PseudoVFNMACC_VFPR32_M2_MASK, VFNMACC_VF, 0x1, 0x0 }, // 1901 |
7893 | | { PseudoVFNMACC_VFPR64_M2, VFNMACC_VF, 0x1, 0x0 }, // 1902 |
7894 | | { PseudoVFNMACC_VFPR64_M2_MASK, VFNMACC_VF, 0x1, 0x0 }, // 1903 |
7895 | | { PseudoVFNMACC_VFPR16_M4, VFNMACC_VF, 0x2, 0x0 }, // 1904 |
7896 | | { PseudoVFNMACC_VFPR16_M4_MASK, VFNMACC_VF, 0x2, 0x0 }, // 1905 |
7897 | | { PseudoVFNMACC_VFPR32_M4, VFNMACC_VF, 0x2, 0x0 }, // 1906 |
7898 | | { PseudoVFNMACC_VFPR32_M4_MASK, VFNMACC_VF, 0x2, 0x0 }, // 1907 |
7899 | | { PseudoVFNMACC_VFPR64_M4, VFNMACC_VF, 0x2, 0x0 }, // 1908 |
7900 | | { PseudoVFNMACC_VFPR64_M4_MASK, VFNMACC_VF, 0x2, 0x0 }, // 1909 |
7901 | | { PseudoVFNMACC_VFPR16_M8, VFNMACC_VF, 0x3, 0x0 }, // 1910 |
7902 | | { PseudoVFNMACC_VFPR16_M8_MASK, VFNMACC_VF, 0x3, 0x0 }, // 1911 |
7903 | | { PseudoVFNMACC_VFPR32_M8, VFNMACC_VF, 0x3, 0x0 }, // 1912 |
7904 | | { PseudoVFNMACC_VFPR32_M8_MASK, VFNMACC_VF, 0x3, 0x0 }, // 1913 |
7905 | | { PseudoVFNMACC_VFPR64_M8, VFNMACC_VF, 0x3, 0x0 }, // 1914 |
7906 | | { PseudoVFNMACC_VFPR64_M8_MASK, VFNMACC_VF, 0x3, 0x0 }, // 1915 |
7907 | | { PseudoVFNMACC_VFPR16_MF4, VFNMACC_VF, 0x6, 0x0 }, // 1916 |
7908 | | { PseudoVFNMACC_VFPR16_MF4_MASK, VFNMACC_VF, 0x6, 0x0 }, // 1917 |
7909 | | { PseudoVFNMACC_VFPR16_MF2, VFNMACC_VF, 0x7, 0x0 }, // 1918 |
7910 | | { PseudoVFNMACC_VFPR16_MF2_MASK, VFNMACC_VF, 0x7, 0x0 }, // 1919 |
7911 | | { PseudoVFNMACC_VFPR32_MF2, VFNMACC_VF, 0x7, 0x0 }, // 1920 |
7912 | | { PseudoVFNMACC_VFPR32_MF2_MASK, VFNMACC_VF, 0x7, 0x0 }, // 1921 |
7913 | | { PseudoVFNMACC_VV_M1, VFNMACC_VV, 0x0, 0x0 }, // 1922 |
7914 | | { PseudoVFNMACC_VV_M1_MASK, VFNMACC_VV, 0x0, 0x0 }, // 1923 |
7915 | | { PseudoVFNMACC_VV_M2, VFNMACC_VV, 0x1, 0x0 }, // 1924 |
7916 | | { PseudoVFNMACC_VV_M2_MASK, VFNMACC_VV, 0x1, 0x0 }, // 1925 |
7917 | | { PseudoVFNMACC_VV_M4, VFNMACC_VV, 0x2, 0x0 }, // 1926 |
7918 | | { PseudoVFNMACC_VV_M4_MASK, VFNMACC_VV, 0x2, 0x0 }, // 1927 |
7919 | | { PseudoVFNMACC_VV_M8, VFNMACC_VV, 0x3, 0x0 }, // 1928 |
7920 | | { PseudoVFNMACC_VV_M8_MASK, VFNMACC_VV, 0x3, 0x0 }, // 1929 |
7921 | | { PseudoVFNMACC_VV_MF4, VFNMACC_VV, 0x6, 0x0 }, // 1930 |
7922 | | { PseudoVFNMACC_VV_MF4_MASK, VFNMACC_VV, 0x6, 0x0 }, // 1931 |
7923 | | { PseudoVFNMACC_VV_MF2, VFNMACC_VV, 0x7, 0x0 }, // 1932 |
7924 | | { PseudoVFNMACC_VV_MF2_MASK, VFNMACC_VV, 0x7, 0x0 }, // 1933 |
7925 | | { PseudoVFNMADD_VFPR16_M1, VFNMADD_VF, 0x0, 0x0 }, // 1934 |
7926 | | { PseudoVFNMADD_VFPR16_M1_MASK, VFNMADD_VF, 0x0, 0x0 }, // 1935 |
7927 | | { PseudoVFNMADD_VFPR32_M1, VFNMADD_VF, 0x0, 0x0 }, // 1936 |
7928 | | { PseudoVFNMADD_VFPR32_M1_MASK, VFNMADD_VF, 0x0, 0x0 }, // 1937 |
7929 | | { PseudoVFNMADD_VFPR64_M1, VFNMADD_VF, 0x0, 0x0 }, // 1938 |
7930 | | { PseudoVFNMADD_VFPR64_M1_MASK, VFNMADD_VF, 0x0, 0x0 }, // 1939 |
7931 | | { PseudoVFNMADD_VFPR16_M2, VFNMADD_VF, 0x1, 0x0 }, // 1940 |
7932 | | { PseudoVFNMADD_VFPR16_M2_MASK, VFNMADD_VF, 0x1, 0x0 }, // 1941 |
7933 | | { PseudoVFNMADD_VFPR32_M2, VFNMADD_VF, 0x1, 0x0 }, // 1942 |
7934 | | { PseudoVFNMADD_VFPR32_M2_MASK, VFNMADD_VF, 0x1, 0x0 }, // 1943 |
7935 | | { PseudoVFNMADD_VFPR64_M2, VFNMADD_VF, 0x1, 0x0 }, // 1944 |
7936 | | { PseudoVFNMADD_VFPR64_M2_MASK, VFNMADD_VF, 0x1, 0x0 }, // 1945 |
7937 | | { PseudoVFNMADD_VFPR16_M4, VFNMADD_VF, 0x2, 0x0 }, // 1946 |
7938 | | { PseudoVFNMADD_VFPR16_M4_MASK, VFNMADD_VF, 0x2, 0x0 }, // 1947 |
7939 | | { PseudoVFNMADD_VFPR32_M4, VFNMADD_VF, 0x2, 0x0 }, // 1948 |
7940 | | { PseudoVFNMADD_VFPR32_M4_MASK, VFNMADD_VF, 0x2, 0x0 }, // 1949 |
7941 | | { PseudoVFNMADD_VFPR64_M4, VFNMADD_VF, 0x2, 0x0 }, // 1950 |
7942 | | { PseudoVFNMADD_VFPR64_M4_MASK, VFNMADD_VF, 0x2, 0x0 }, // 1951 |
7943 | | { PseudoVFNMADD_VFPR16_M8, VFNMADD_VF, 0x3, 0x0 }, // 1952 |
7944 | | { PseudoVFNMADD_VFPR16_M8_MASK, VFNMADD_VF, 0x3, 0x0 }, // 1953 |
7945 | | { PseudoVFNMADD_VFPR32_M8, VFNMADD_VF, 0x3, 0x0 }, // 1954 |
7946 | | { PseudoVFNMADD_VFPR32_M8_MASK, VFNMADD_VF, 0x3, 0x0 }, // 1955 |
7947 | | { PseudoVFNMADD_VFPR64_M8, VFNMADD_VF, 0x3, 0x0 }, // 1956 |
7948 | | { PseudoVFNMADD_VFPR64_M8_MASK, VFNMADD_VF, 0x3, 0x0 }, // 1957 |
7949 | | { PseudoVFNMADD_VFPR16_MF4, VFNMADD_VF, 0x6, 0x0 }, // 1958 |
7950 | | { PseudoVFNMADD_VFPR16_MF4_MASK, VFNMADD_VF, 0x6, 0x0 }, // 1959 |
7951 | | { PseudoVFNMADD_VFPR16_MF2, VFNMADD_VF, 0x7, 0x0 }, // 1960 |
7952 | | { PseudoVFNMADD_VFPR16_MF2_MASK, VFNMADD_VF, 0x7, 0x0 }, // 1961 |
7953 | | { PseudoVFNMADD_VFPR32_MF2, VFNMADD_VF, 0x7, 0x0 }, // 1962 |
7954 | | { PseudoVFNMADD_VFPR32_MF2_MASK, VFNMADD_VF, 0x7, 0x0 }, // 1963 |
7955 | | { PseudoVFNMADD_VV_M1, VFNMADD_VV, 0x0, 0x0 }, // 1964 |
7956 | | { PseudoVFNMADD_VV_M1_MASK, VFNMADD_VV, 0x0, 0x0 }, // 1965 |
7957 | | { PseudoVFNMADD_VV_M2, VFNMADD_VV, 0x1, 0x0 }, // 1966 |
7958 | | { PseudoVFNMADD_VV_M2_MASK, VFNMADD_VV, 0x1, 0x0 }, // 1967 |
7959 | | { PseudoVFNMADD_VV_M4, VFNMADD_VV, 0x2, 0x0 }, // 1968 |
7960 | | { PseudoVFNMADD_VV_M4_MASK, VFNMADD_VV, 0x2, 0x0 }, // 1969 |
7961 | | { PseudoVFNMADD_VV_M8, VFNMADD_VV, 0x3, 0x0 }, // 1970 |
7962 | | { PseudoVFNMADD_VV_M8_MASK, VFNMADD_VV, 0x3, 0x0 }, // 1971 |
7963 | | { PseudoVFNMADD_VV_MF4, VFNMADD_VV, 0x6, 0x0 }, // 1972 |
7964 | | { PseudoVFNMADD_VV_MF4_MASK, VFNMADD_VV, 0x6, 0x0 }, // 1973 |
7965 | | { PseudoVFNMADD_VV_MF2, VFNMADD_VV, 0x7, 0x0 }, // 1974 |
7966 | | { PseudoVFNMADD_VV_MF2_MASK, VFNMADD_VV, 0x7, 0x0 }, // 1975 |
7967 | | { PseudoVFNMSAC_VFPR16_M1, VFNMSAC_VF, 0x0, 0x0 }, // 1976 |
7968 | | { PseudoVFNMSAC_VFPR16_M1_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 1977 |
7969 | | { PseudoVFNMSAC_VFPR32_M1, VFNMSAC_VF, 0x0, 0x0 }, // 1978 |
7970 | | { PseudoVFNMSAC_VFPR32_M1_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 1979 |
7971 | | { PseudoVFNMSAC_VFPR64_M1, VFNMSAC_VF, 0x0, 0x0 }, // 1980 |
7972 | | { PseudoVFNMSAC_VFPR64_M1_MASK, VFNMSAC_VF, 0x0, 0x0 }, // 1981 |
7973 | | { PseudoVFNMSAC_VFPR16_M2, VFNMSAC_VF, 0x1, 0x0 }, // 1982 |
7974 | | { PseudoVFNMSAC_VFPR16_M2_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 1983 |
7975 | | { PseudoVFNMSAC_VFPR32_M2, VFNMSAC_VF, 0x1, 0x0 }, // 1984 |
7976 | | { PseudoVFNMSAC_VFPR32_M2_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 1985 |
7977 | | { PseudoVFNMSAC_VFPR64_M2, VFNMSAC_VF, 0x1, 0x0 }, // 1986 |
7978 | | { PseudoVFNMSAC_VFPR64_M2_MASK, VFNMSAC_VF, 0x1, 0x0 }, // 1987 |
7979 | | { PseudoVFNMSAC_VFPR16_M4, VFNMSAC_VF, 0x2, 0x0 }, // 1988 |
7980 | | { PseudoVFNMSAC_VFPR16_M4_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 1989 |
7981 | | { PseudoVFNMSAC_VFPR32_M4, VFNMSAC_VF, 0x2, 0x0 }, // 1990 |
7982 | | { PseudoVFNMSAC_VFPR32_M4_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 1991 |
7983 | | { PseudoVFNMSAC_VFPR64_M4, VFNMSAC_VF, 0x2, 0x0 }, // 1992 |
7984 | | { PseudoVFNMSAC_VFPR64_M4_MASK, VFNMSAC_VF, 0x2, 0x0 }, // 1993 |
7985 | | { PseudoVFNMSAC_VFPR16_M8, VFNMSAC_VF, 0x3, 0x0 }, // 1994 |
7986 | | { PseudoVFNMSAC_VFPR16_M8_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 1995 |
7987 | | { PseudoVFNMSAC_VFPR32_M8, VFNMSAC_VF, 0x3, 0x0 }, // 1996 |
7988 | | { PseudoVFNMSAC_VFPR32_M8_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 1997 |
7989 | | { PseudoVFNMSAC_VFPR64_M8, VFNMSAC_VF, 0x3, 0x0 }, // 1998 |
7990 | | { PseudoVFNMSAC_VFPR64_M8_MASK, VFNMSAC_VF, 0x3, 0x0 }, // 1999 |
7991 | | { PseudoVFNMSAC_VFPR16_MF4, VFNMSAC_VF, 0x6, 0x0 }, // 2000 |
7992 | | { PseudoVFNMSAC_VFPR16_MF4_MASK, VFNMSAC_VF, 0x6, 0x0 }, // 2001 |
7993 | | { PseudoVFNMSAC_VFPR16_MF2, VFNMSAC_VF, 0x7, 0x0 }, // 2002 |
7994 | | { PseudoVFNMSAC_VFPR16_MF2_MASK, VFNMSAC_VF, 0x7, 0x0 }, // 2003 |
7995 | | { PseudoVFNMSAC_VFPR32_MF2, VFNMSAC_VF, 0x7, 0x0 }, // 2004 |
7996 | | { PseudoVFNMSAC_VFPR32_MF2_MASK, VFNMSAC_VF, 0x7, 0x0 }, // 2005 |
7997 | | { PseudoVFNMSAC_VV_M1, VFNMSAC_VV, 0x0, 0x0 }, // 2006 |
7998 | | { PseudoVFNMSAC_VV_M1_MASK, VFNMSAC_VV, 0x0, 0x0 }, // 2007 |
7999 | | { PseudoVFNMSAC_VV_M2, VFNMSAC_VV, 0x1, 0x0 }, // 2008 |
8000 | | { PseudoVFNMSAC_VV_M2_MASK, VFNMSAC_VV, 0x1, 0x0 }, // 2009 |
8001 | | { PseudoVFNMSAC_VV_M4, VFNMSAC_VV, 0x2, 0x0 }, // 2010 |
8002 | | { PseudoVFNMSAC_VV_M4_MASK, VFNMSAC_VV, 0x2, 0x0 }, // 2011 |
8003 | | { PseudoVFNMSAC_VV_M8, VFNMSAC_VV, 0x3, 0x0 }, // 2012 |
8004 | | { PseudoVFNMSAC_VV_M8_MASK, VFNMSAC_VV, 0x3, 0x0 }, // 2013 |
8005 | | { PseudoVFNMSAC_VV_MF4, VFNMSAC_VV, 0x6, 0x0 }, // 2014 |
8006 | | { PseudoVFNMSAC_VV_MF4_MASK, VFNMSAC_VV, 0x6, 0x0 }, // 2015 |
8007 | | { PseudoVFNMSAC_VV_MF2, VFNMSAC_VV, 0x7, 0x0 }, // 2016 |
8008 | | { PseudoVFNMSAC_VV_MF2_MASK, VFNMSAC_VV, 0x7, 0x0 }, // 2017 |
8009 | | { PseudoVFNMSUB_VFPR16_M1, VFNMSUB_VF, 0x0, 0x0 }, // 2018 |
8010 | | { PseudoVFNMSUB_VFPR16_M1_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2019 |
8011 | | { PseudoVFNMSUB_VFPR32_M1, VFNMSUB_VF, 0x0, 0x0 }, // 2020 |
8012 | | { PseudoVFNMSUB_VFPR32_M1_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2021 |
8013 | | { PseudoVFNMSUB_VFPR64_M1, VFNMSUB_VF, 0x0, 0x0 }, // 2022 |
8014 | | { PseudoVFNMSUB_VFPR64_M1_MASK, VFNMSUB_VF, 0x0, 0x0 }, // 2023 |
8015 | | { PseudoVFNMSUB_VFPR16_M2, VFNMSUB_VF, 0x1, 0x0 }, // 2024 |
8016 | | { PseudoVFNMSUB_VFPR16_M2_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2025 |
8017 | | { PseudoVFNMSUB_VFPR32_M2, VFNMSUB_VF, 0x1, 0x0 }, // 2026 |
8018 | | { PseudoVFNMSUB_VFPR32_M2_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2027 |
8019 | | { PseudoVFNMSUB_VFPR64_M2, VFNMSUB_VF, 0x1, 0x0 }, // 2028 |
8020 | | { PseudoVFNMSUB_VFPR64_M2_MASK, VFNMSUB_VF, 0x1, 0x0 }, // 2029 |
8021 | | { PseudoVFNMSUB_VFPR16_M4, VFNMSUB_VF, 0x2, 0x0 }, // 2030 |
8022 | | { PseudoVFNMSUB_VFPR16_M4_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2031 |
8023 | | { PseudoVFNMSUB_VFPR32_M4, VFNMSUB_VF, 0x2, 0x0 }, // 2032 |
8024 | | { PseudoVFNMSUB_VFPR32_M4_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2033 |
8025 | | { PseudoVFNMSUB_VFPR64_M4, VFNMSUB_VF, 0x2, 0x0 }, // 2034 |
8026 | | { PseudoVFNMSUB_VFPR64_M4_MASK, VFNMSUB_VF, 0x2, 0x0 }, // 2035 |
8027 | | { PseudoVFNMSUB_VFPR16_M8, VFNMSUB_VF, 0x3, 0x0 }, // 2036 |
8028 | | { PseudoVFNMSUB_VFPR16_M8_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2037 |
8029 | | { PseudoVFNMSUB_VFPR32_M8, VFNMSUB_VF, 0x3, 0x0 }, // 2038 |
8030 | | { PseudoVFNMSUB_VFPR32_M8_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2039 |
8031 | | { PseudoVFNMSUB_VFPR64_M8, VFNMSUB_VF, 0x3, 0x0 }, // 2040 |
8032 | | { PseudoVFNMSUB_VFPR64_M8_MASK, VFNMSUB_VF, 0x3, 0x0 }, // 2041 |
8033 | | { PseudoVFNMSUB_VFPR16_MF4, VFNMSUB_VF, 0x6, 0x0 }, // 2042 |
8034 | | { PseudoVFNMSUB_VFPR16_MF4_MASK, VFNMSUB_VF, 0x6, 0x0 }, // 2043 |
8035 | | { PseudoVFNMSUB_VFPR16_MF2, VFNMSUB_VF, 0x7, 0x0 }, // 2044 |
8036 | | { PseudoVFNMSUB_VFPR16_MF2_MASK, VFNMSUB_VF, 0x7, 0x0 }, // 2045 |
8037 | | { PseudoVFNMSUB_VFPR32_MF2, VFNMSUB_VF, 0x7, 0x0 }, // 2046 |
8038 | | { PseudoVFNMSUB_VFPR32_MF2_MASK, VFNMSUB_VF, 0x7, 0x0 }, // 2047 |
8039 | | { PseudoVFNMSUB_VV_M1, VFNMSUB_VV, 0x0, 0x0 }, // 2048 |
8040 | | { PseudoVFNMSUB_VV_M1_MASK, VFNMSUB_VV, 0x0, 0x0 }, // 2049 |
8041 | | { PseudoVFNMSUB_VV_M2, VFNMSUB_VV, 0x1, 0x0 }, // 2050 |
8042 | | { PseudoVFNMSUB_VV_M2_MASK, VFNMSUB_VV, 0x1, 0x0 }, // 2051 |
8043 | | { PseudoVFNMSUB_VV_M4, VFNMSUB_VV, 0x2, 0x0 }, // 2052 |
8044 | | { PseudoVFNMSUB_VV_M4_MASK, VFNMSUB_VV, 0x2, 0x0 }, // 2053 |
8045 | | { PseudoVFNMSUB_VV_M8, VFNMSUB_VV, 0x3, 0x0 }, // 2054 |
8046 | | { PseudoVFNMSUB_VV_M8_MASK, VFNMSUB_VV, 0x3, 0x0 }, // 2055 |
8047 | | { PseudoVFNMSUB_VV_MF4, VFNMSUB_VV, 0x6, 0x0 }, // 2056 |
8048 | | { PseudoVFNMSUB_VV_MF4_MASK, VFNMSUB_VV, 0x6, 0x0 }, // 2057 |
8049 | | { PseudoVFNMSUB_VV_MF2, VFNMSUB_VV, 0x7, 0x0 }, // 2058 |
8050 | | { PseudoVFNMSUB_VV_MF2_MASK, VFNMSUB_VV, 0x7, 0x0 }, // 2059 |
8051 | | { PseudoVFNRCLIP_XU_F_QF_M1, VFNRCLIP_XU_F_QF, 0x0, 0x0 }, // 2060 |
8052 | | { PseudoVFNRCLIP_XU_F_QF_M1_MASK, VFNRCLIP_XU_F_QF, 0x0, 0x0 }, // 2061 |
8053 | | { PseudoVFNRCLIP_XU_F_QF_M2, VFNRCLIP_XU_F_QF, 0x1, 0x0 }, // 2062 |
8054 | | { PseudoVFNRCLIP_XU_F_QF_M2_MASK, VFNRCLIP_XU_F_QF, 0x1, 0x0 }, // 2063 |
8055 | | { PseudoVFNRCLIP_XU_F_QF_MF8, VFNRCLIP_XU_F_QF, 0x5, 0x0 }, // 2064 |
8056 | | { PseudoVFNRCLIP_XU_F_QF_MF8_MASK, VFNRCLIP_XU_F_QF, 0x5, 0x0 }, // 2065 |
8057 | | { PseudoVFNRCLIP_XU_F_QF_MF4, VFNRCLIP_XU_F_QF, 0x6, 0x0 }, // 2066 |
8058 | | { PseudoVFNRCLIP_XU_F_QF_MF4_MASK, VFNRCLIP_XU_F_QF, 0x6, 0x0 }, // 2067 |
8059 | | { PseudoVFNRCLIP_XU_F_QF_MF2, VFNRCLIP_XU_F_QF, 0x7, 0x0 }, // 2068 |
8060 | | { PseudoVFNRCLIP_XU_F_QF_MF2_MASK, VFNRCLIP_XU_F_QF, 0x7, 0x0 }, // 2069 |
8061 | | { PseudoVFNRCLIP_X_F_QF_M1, VFNRCLIP_X_F_QF, 0x0, 0x0 }, // 2070 |
8062 | | { PseudoVFNRCLIP_X_F_QF_M1_MASK, VFNRCLIP_X_F_QF, 0x0, 0x0 }, // 2071 |
8063 | | { PseudoVFNRCLIP_X_F_QF_M2, VFNRCLIP_X_F_QF, 0x1, 0x0 }, // 2072 |
8064 | | { PseudoVFNRCLIP_X_F_QF_M2_MASK, VFNRCLIP_X_F_QF, 0x1, 0x0 }, // 2073 |
8065 | | { PseudoVFNRCLIP_X_F_QF_MF8, VFNRCLIP_X_F_QF, 0x5, 0x0 }, // 2074 |
8066 | | { PseudoVFNRCLIP_X_F_QF_MF8_MASK, VFNRCLIP_X_F_QF, 0x5, 0x0 }, // 2075 |
8067 | | { PseudoVFNRCLIP_X_F_QF_MF4, VFNRCLIP_X_F_QF, 0x6, 0x0 }, // 2076 |
8068 | | { PseudoVFNRCLIP_X_F_QF_MF4_MASK, VFNRCLIP_X_F_QF, 0x6, 0x0 }, // 2077 |
8069 | | { PseudoVFNRCLIP_X_F_QF_MF2, VFNRCLIP_X_F_QF, 0x7, 0x0 }, // 2078 |
8070 | | { PseudoVFNRCLIP_X_F_QF_MF2_MASK, VFNRCLIP_X_F_QF, 0x7, 0x0 }, // 2079 |
8071 | | { PseudoVFRDIV_VFPR16_M1_E16, VFRDIV_VF, 0x0, 0x10 }, // 2080 |
8072 | | { PseudoVFRDIV_VFPR16_M1_E16_MASK, VFRDIV_VF, 0x0, 0x10 }, // 2081 |
8073 | | { PseudoVFRDIV_VFPR32_M1_E32, VFRDIV_VF, 0x0, 0x20 }, // 2082 |
8074 | | { PseudoVFRDIV_VFPR32_M1_E32_MASK, VFRDIV_VF, 0x0, 0x20 }, // 2083 |
8075 | | { PseudoVFRDIV_VFPR64_M1_E64, VFRDIV_VF, 0x0, 0x40 }, // 2084 |
8076 | | { PseudoVFRDIV_VFPR64_M1_E64_MASK, VFRDIV_VF, 0x0, 0x40 }, // 2085 |
8077 | | { PseudoVFRDIV_VFPR16_M2_E16, VFRDIV_VF, 0x1, 0x10 }, // 2086 |
8078 | | { PseudoVFRDIV_VFPR16_M2_E16_MASK, VFRDIV_VF, 0x1, 0x10 }, // 2087 |
8079 | | { PseudoVFRDIV_VFPR32_M2_E32, VFRDIV_VF, 0x1, 0x20 }, // 2088 |
8080 | | { PseudoVFRDIV_VFPR32_M2_E32_MASK, VFRDIV_VF, 0x1, 0x20 }, // 2089 |
8081 | | { PseudoVFRDIV_VFPR64_M2_E64, VFRDIV_VF, 0x1, 0x40 }, // 2090 |
8082 | | { PseudoVFRDIV_VFPR64_M2_E64_MASK, VFRDIV_VF, 0x1, 0x40 }, // 2091 |
8083 | | { PseudoVFRDIV_VFPR16_M4_E16, VFRDIV_VF, 0x2, 0x10 }, // 2092 |
8084 | | { PseudoVFRDIV_VFPR16_M4_E16_MASK, VFRDIV_VF, 0x2, 0x10 }, // 2093 |
8085 | | { PseudoVFRDIV_VFPR32_M4_E32, VFRDIV_VF, 0x2, 0x20 }, // 2094 |
8086 | | { PseudoVFRDIV_VFPR32_M4_E32_MASK, VFRDIV_VF, 0x2, 0x20 }, // 2095 |
8087 | | { PseudoVFRDIV_VFPR64_M4_E64, VFRDIV_VF, 0x2, 0x40 }, // 2096 |
8088 | | { PseudoVFRDIV_VFPR64_M4_E64_MASK, VFRDIV_VF, 0x2, 0x40 }, // 2097 |
8089 | | { PseudoVFRDIV_VFPR16_M8_E16, VFRDIV_VF, 0x3, 0x10 }, // 2098 |
8090 | | { PseudoVFRDIV_VFPR16_M8_E16_MASK, VFRDIV_VF, 0x3, 0x10 }, // 2099 |
8091 | | { PseudoVFRDIV_VFPR32_M8_E32, VFRDIV_VF, 0x3, 0x20 }, // 2100 |
8092 | | { PseudoVFRDIV_VFPR32_M8_E32_MASK, VFRDIV_VF, 0x3, 0x20 }, // 2101 |
8093 | | { PseudoVFRDIV_VFPR64_M8_E64, VFRDIV_VF, 0x3, 0x40 }, // 2102 |
8094 | | { PseudoVFRDIV_VFPR64_M8_E64_MASK, VFRDIV_VF, 0x3, 0x40 }, // 2103 |
8095 | | { PseudoVFRDIV_VFPR16_MF4_E16, VFRDIV_VF, 0x6, 0x10 }, // 2104 |
8096 | | { PseudoVFRDIV_VFPR16_MF4_E16_MASK, VFRDIV_VF, 0x6, 0x10 }, // 2105 |
8097 | | { PseudoVFRDIV_VFPR16_MF2_E16, VFRDIV_VF, 0x7, 0x10 }, // 2106 |
8098 | | { PseudoVFRDIV_VFPR16_MF2_E16_MASK, VFRDIV_VF, 0x7, 0x10 }, // 2107 |
8099 | | { PseudoVFRDIV_VFPR32_MF2_E32, VFRDIV_VF, 0x7, 0x20 }, // 2108 |
8100 | | { PseudoVFRDIV_VFPR32_MF2_E32_MASK, VFRDIV_VF, 0x7, 0x20 }, // 2109 |
8101 | | { PseudoVFREC7_V_M1, VFREC7_V, 0x0, 0x0 }, // 2110 |
8102 | | { PseudoVFREC7_V_M1_MASK, VFREC7_V, 0x0, 0x0 }, // 2111 |
8103 | | { PseudoVFREC7_V_M2, VFREC7_V, 0x1, 0x0 }, // 2112 |
8104 | | { PseudoVFREC7_V_M2_MASK, VFREC7_V, 0x1, 0x0 }, // 2113 |
8105 | | { PseudoVFREC7_V_M4, VFREC7_V, 0x2, 0x0 }, // 2114 |
8106 | | { PseudoVFREC7_V_M4_MASK, VFREC7_V, 0x2, 0x0 }, // 2115 |
8107 | | { PseudoVFREC7_V_M8, VFREC7_V, 0x3, 0x0 }, // 2116 |
8108 | | { PseudoVFREC7_V_M8_MASK, VFREC7_V, 0x3, 0x0 }, // 2117 |
8109 | | { PseudoVFREC7_V_MF4, VFREC7_V, 0x6, 0x0 }, // 2118 |
8110 | | { PseudoVFREC7_V_MF4_MASK, VFREC7_V, 0x6, 0x0 }, // 2119 |
8111 | | { PseudoVFREC7_V_MF2, VFREC7_V, 0x7, 0x0 }, // 2120 |
8112 | | { PseudoVFREC7_V_MF2_MASK, VFREC7_V, 0x7, 0x0 }, // 2121 |
8113 | | { PseudoVFREDMAX_VS_M1_E16, VFREDMAX_VS, 0x0, 0x10 }, // 2122 |
8114 | | { PseudoVFREDMAX_VS_M1_E16_MASK, VFREDMAX_VS, 0x0, 0x10 }, // 2123 |
8115 | | { PseudoVFREDMAX_VS_M1_E32, VFREDMAX_VS, 0x0, 0x20 }, // 2124 |
8116 | | { PseudoVFREDMAX_VS_M1_E32_MASK, VFREDMAX_VS, 0x0, 0x20 }, // 2125 |
8117 | | { PseudoVFREDMAX_VS_M1_E64, VFREDMAX_VS, 0x0, 0x40 }, // 2126 |
8118 | | { PseudoVFREDMAX_VS_M1_E64_MASK, VFREDMAX_VS, 0x0, 0x40 }, // 2127 |
8119 | | { PseudoVFREDMAX_VS_M2_E16, VFREDMAX_VS, 0x1, 0x10 }, // 2128 |
8120 | | { PseudoVFREDMAX_VS_M2_E16_MASK, VFREDMAX_VS, 0x1, 0x10 }, // 2129 |
8121 | | { PseudoVFREDMAX_VS_M2_E32, VFREDMAX_VS, 0x1, 0x20 }, // 2130 |
8122 | | { PseudoVFREDMAX_VS_M2_E32_MASK, VFREDMAX_VS, 0x1, 0x20 }, // 2131 |
8123 | | { PseudoVFREDMAX_VS_M2_E64, VFREDMAX_VS, 0x1, 0x40 }, // 2132 |
8124 | | { PseudoVFREDMAX_VS_M2_E64_MASK, VFREDMAX_VS, 0x1, 0x40 }, // 2133 |
8125 | | { PseudoVFREDMAX_VS_M4_E16, VFREDMAX_VS, 0x2, 0x10 }, // 2134 |
8126 | | { PseudoVFREDMAX_VS_M4_E16_MASK, VFREDMAX_VS, 0x2, 0x10 }, // 2135 |
8127 | | { PseudoVFREDMAX_VS_M4_E32, VFREDMAX_VS, 0x2, 0x20 }, // 2136 |
8128 | | { PseudoVFREDMAX_VS_M4_E32_MASK, VFREDMAX_VS, 0x2, 0x20 }, // 2137 |
8129 | | { PseudoVFREDMAX_VS_M4_E64, VFREDMAX_VS, 0x2, 0x40 }, // 2138 |
8130 | | { PseudoVFREDMAX_VS_M4_E64_MASK, VFREDMAX_VS, 0x2, 0x40 }, // 2139 |
8131 | | { PseudoVFREDMAX_VS_M8_E16, VFREDMAX_VS, 0x3, 0x10 }, // 2140 |
8132 | | { PseudoVFREDMAX_VS_M8_E16_MASK, VFREDMAX_VS, 0x3, 0x10 }, // 2141 |
8133 | | { PseudoVFREDMAX_VS_M8_E32, VFREDMAX_VS, 0x3, 0x20 }, // 2142 |
8134 | | { PseudoVFREDMAX_VS_M8_E32_MASK, VFREDMAX_VS, 0x3, 0x20 }, // 2143 |
8135 | | { PseudoVFREDMAX_VS_M8_E64, VFREDMAX_VS, 0x3, 0x40 }, // 2144 |
8136 | | { PseudoVFREDMAX_VS_M8_E64_MASK, VFREDMAX_VS, 0x3, 0x40 }, // 2145 |
8137 | | { PseudoVFREDMAX_VS_MF4_E16, VFREDMAX_VS, 0x6, 0x10 }, // 2146 |
8138 | | { PseudoVFREDMAX_VS_MF4_E16_MASK, VFREDMAX_VS, 0x6, 0x10 }, // 2147 |
8139 | | { PseudoVFREDMAX_VS_MF2_E16, VFREDMAX_VS, 0x7, 0x10 }, // 2148 |
8140 | | { PseudoVFREDMAX_VS_MF2_E16_MASK, VFREDMAX_VS, 0x7, 0x10 }, // 2149 |
8141 | | { PseudoVFREDMAX_VS_MF2_E32, VFREDMAX_VS, 0x7, 0x20 }, // 2150 |
8142 | | { PseudoVFREDMAX_VS_MF2_E32_MASK, VFREDMAX_VS, 0x7, 0x20 }, // 2151 |
8143 | | { PseudoVFREDMIN_VS_M1_E16, VFREDMIN_VS, 0x0, 0x10 }, // 2152 |
8144 | | { PseudoVFREDMIN_VS_M1_E16_MASK, VFREDMIN_VS, 0x0, 0x10 }, // 2153 |
8145 | | { PseudoVFREDMIN_VS_M1_E32, VFREDMIN_VS, 0x0, 0x20 }, // 2154 |
8146 | | { PseudoVFREDMIN_VS_M1_E32_MASK, VFREDMIN_VS, 0x0, 0x20 }, // 2155 |
8147 | | { PseudoVFREDMIN_VS_M1_E64, VFREDMIN_VS, 0x0, 0x40 }, // 2156 |
8148 | | { PseudoVFREDMIN_VS_M1_E64_MASK, VFREDMIN_VS, 0x0, 0x40 }, // 2157 |
8149 | | { PseudoVFREDMIN_VS_M2_E16, VFREDMIN_VS, 0x1, 0x10 }, // 2158 |
8150 | | { PseudoVFREDMIN_VS_M2_E16_MASK, VFREDMIN_VS, 0x1, 0x10 }, // 2159 |
8151 | | { PseudoVFREDMIN_VS_M2_E32, VFREDMIN_VS, 0x1, 0x20 }, // 2160 |
8152 | | { PseudoVFREDMIN_VS_M2_E32_MASK, VFREDMIN_VS, 0x1, 0x20 }, // 2161 |
8153 | | { PseudoVFREDMIN_VS_M2_E64, VFREDMIN_VS, 0x1, 0x40 }, // 2162 |
8154 | | { PseudoVFREDMIN_VS_M2_E64_MASK, VFREDMIN_VS, 0x1, 0x40 }, // 2163 |
8155 | | { PseudoVFREDMIN_VS_M4_E16, VFREDMIN_VS, 0x2, 0x10 }, // 2164 |
8156 | | { PseudoVFREDMIN_VS_M4_E16_MASK, VFREDMIN_VS, 0x2, 0x10 }, // 2165 |
8157 | | { PseudoVFREDMIN_VS_M4_E32, VFREDMIN_VS, 0x2, 0x20 }, // 2166 |
8158 | | { PseudoVFREDMIN_VS_M4_E32_MASK, VFREDMIN_VS, 0x2, 0x20 }, // 2167 |
8159 | | { PseudoVFREDMIN_VS_M4_E64, VFREDMIN_VS, 0x2, 0x40 }, // 2168 |
8160 | | { PseudoVFREDMIN_VS_M4_E64_MASK, VFREDMIN_VS, 0x2, 0x40 }, // 2169 |
8161 | | { PseudoVFREDMIN_VS_M8_E16, VFREDMIN_VS, 0x3, 0x10 }, // 2170 |
8162 | | { PseudoVFREDMIN_VS_M8_E16_MASK, VFREDMIN_VS, 0x3, 0x10 }, // 2171 |
8163 | | { PseudoVFREDMIN_VS_M8_E32, VFREDMIN_VS, 0x3, 0x20 }, // 2172 |
8164 | | { PseudoVFREDMIN_VS_M8_E32_MASK, VFREDMIN_VS, 0x3, 0x20 }, // 2173 |
8165 | | { PseudoVFREDMIN_VS_M8_E64, VFREDMIN_VS, 0x3, 0x40 }, // 2174 |
8166 | | { PseudoVFREDMIN_VS_M8_E64_MASK, VFREDMIN_VS, 0x3, 0x40 }, // 2175 |
8167 | | { PseudoVFREDMIN_VS_MF4_E16, VFREDMIN_VS, 0x6, 0x10 }, // 2176 |
8168 | | { PseudoVFREDMIN_VS_MF4_E16_MASK, VFREDMIN_VS, 0x6, 0x10 }, // 2177 |
8169 | | { PseudoVFREDMIN_VS_MF2_E16, VFREDMIN_VS, 0x7, 0x10 }, // 2178 |
8170 | | { PseudoVFREDMIN_VS_MF2_E16_MASK, VFREDMIN_VS, 0x7, 0x10 }, // 2179 |
8171 | | { PseudoVFREDMIN_VS_MF2_E32, VFREDMIN_VS, 0x7, 0x20 }, // 2180 |
8172 | | { PseudoVFREDMIN_VS_MF2_E32_MASK, VFREDMIN_VS, 0x7, 0x20 }, // 2181 |
8173 | | { PseudoVFREDOSUM_VS_M1_E16, VFREDOSUM_VS, 0x0, 0x10 }, // 2182 |
8174 | | { PseudoVFREDOSUM_VS_M1_E16_MASK, VFREDOSUM_VS, 0x0, 0x10 }, // 2183 |
8175 | | { PseudoVFREDOSUM_VS_M1_E32, VFREDOSUM_VS, 0x0, 0x20 }, // 2184 |
8176 | | { PseudoVFREDOSUM_VS_M1_E32_MASK, VFREDOSUM_VS, 0x0, 0x20 }, // 2185 |
8177 | | { PseudoVFREDOSUM_VS_M1_E64, VFREDOSUM_VS, 0x0, 0x40 }, // 2186 |
8178 | | { PseudoVFREDOSUM_VS_M1_E64_MASK, VFREDOSUM_VS, 0x0, 0x40 }, // 2187 |
8179 | | { PseudoVFREDOSUM_VS_M2_E16, VFREDOSUM_VS, 0x1, 0x10 }, // 2188 |
8180 | | { PseudoVFREDOSUM_VS_M2_E16_MASK, VFREDOSUM_VS, 0x1, 0x10 }, // 2189 |
8181 | | { PseudoVFREDOSUM_VS_M2_E32, VFREDOSUM_VS, 0x1, 0x20 }, // 2190 |
8182 | | { PseudoVFREDOSUM_VS_M2_E32_MASK, VFREDOSUM_VS, 0x1, 0x20 }, // 2191 |
8183 | | { PseudoVFREDOSUM_VS_M2_E64, VFREDOSUM_VS, 0x1, 0x40 }, // 2192 |
8184 | | { PseudoVFREDOSUM_VS_M2_E64_MASK, VFREDOSUM_VS, 0x1, 0x40 }, // 2193 |
8185 | | { PseudoVFREDOSUM_VS_M4_E16, VFREDOSUM_VS, 0x2, 0x10 }, // 2194 |
8186 | | { PseudoVFREDOSUM_VS_M4_E16_MASK, VFREDOSUM_VS, 0x2, 0x10 }, // 2195 |
8187 | | { PseudoVFREDOSUM_VS_M4_E32, VFREDOSUM_VS, 0x2, 0x20 }, // 2196 |
8188 | | { PseudoVFREDOSUM_VS_M4_E32_MASK, VFREDOSUM_VS, 0x2, 0x20 }, // 2197 |
8189 | | { PseudoVFREDOSUM_VS_M4_E64, VFREDOSUM_VS, 0x2, 0x40 }, // 2198 |
8190 | | { PseudoVFREDOSUM_VS_M4_E64_MASK, VFREDOSUM_VS, 0x2, 0x40 }, // 2199 |
8191 | | { PseudoVFREDOSUM_VS_M8_E16, VFREDOSUM_VS, 0x3, 0x10 }, // 2200 |
8192 | | { PseudoVFREDOSUM_VS_M8_E16_MASK, VFREDOSUM_VS, 0x3, 0x10 }, // 2201 |
8193 | | { PseudoVFREDOSUM_VS_M8_E32, VFREDOSUM_VS, 0x3, 0x20 }, // 2202 |
8194 | | { PseudoVFREDOSUM_VS_M8_E32_MASK, VFREDOSUM_VS, 0x3, 0x20 }, // 2203 |
8195 | | { PseudoVFREDOSUM_VS_M8_E64, VFREDOSUM_VS, 0x3, 0x40 }, // 2204 |
8196 | | { PseudoVFREDOSUM_VS_M8_E64_MASK, VFREDOSUM_VS, 0x3, 0x40 }, // 2205 |
8197 | | { PseudoVFREDOSUM_VS_MF4_E16, VFREDOSUM_VS, 0x6, 0x10 }, // 2206 |
8198 | | { PseudoVFREDOSUM_VS_MF4_E16_MASK, VFREDOSUM_VS, 0x6, 0x10 }, // 2207 |
8199 | | { PseudoVFREDOSUM_VS_MF2_E16, VFREDOSUM_VS, 0x7, 0x10 }, // 2208 |
8200 | | { PseudoVFREDOSUM_VS_MF2_E16_MASK, VFREDOSUM_VS, 0x7, 0x10 }, // 2209 |
8201 | | { PseudoVFREDOSUM_VS_MF2_E32, VFREDOSUM_VS, 0x7, 0x20 }, // 2210 |
8202 | | { PseudoVFREDOSUM_VS_MF2_E32_MASK, VFREDOSUM_VS, 0x7, 0x20 }, // 2211 |
8203 | | { PseudoVFREDUSUM_VS_M1_E16, VFREDUSUM_VS, 0x0, 0x10 }, // 2212 |
8204 | | { PseudoVFREDUSUM_VS_M1_E16_MASK, VFREDUSUM_VS, 0x0, 0x10 }, // 2213 |
8205 | | { PseudoVFREDUSUM_VS_M1_E32, VFREDUSUM_VS, 0x0, 0x20 }, // 2214 |
8206 | | { PseudoVFREDUSUM_VS_M1_E32_MASK, VFREDUSUM_VS, 0x0, 0x20 }, // 2215 |
8207 | | { PseudoVFREDUSUM_VS_M1_E64, VFREDUSUM_VS, 0x0, 0x40 }, // 2216 |
8208 | | { PseudoVFREDUSUM_VS_M1_E64_MASK, VFREDUSUM_VS, 0x0, 0x40 }, // 2217 |
8209 | | { PseudoVFREDUSUM_VS_M2_E16, VFREDUSUM_VS, 0x1, 0x10 }, // 2218 |
8210 | | { PseudoVFREDUSUM_VS_M2_E16_MASK, VFREDUSUM_VS, 0x1, 0x10 }, // 2219 |
8211 | | { PseudoVFREDUSUM_VS_M2_E32, VFREDUSUM_VS, 0x1, 0x20 }, // 2220 |
8212 | | { PseudoVFREDUSUM_VS_M2_E32_MASK, VFREDUSUM_VS, 0x1, 0x20 }, // 2221 |
8213 | | { PseudoVFREDUSUM_VS_M2_E64, VFREDUSUM_VS, 0x1, 0x40 }, // 2222 |
8214 | | { PseudoVFREDUSUM_VS_M2_E64_MASK, VFREDUSUM_VS, 0x1, 0x40 }, // 2223 |
8215 | | { PseudoVFREDUSUM_VS_M4_E16, VFREDUSUM_VS, 0x2, 0x10 }, // 2224 |
8216 | | { PseudoVFREDUSUM_VS_M4_E16_MASK, VFREDUSUM_VS, 0x2, 0x10 }, // 2225 |
8217 | | { PseudoVFREDUSUM_VS_M4_E32, VFREDUSUM_VS, 0x2, 0x20 }, // 2226 |
8218 | | { PseudoVFREDUSUM_VS_M4_E32_MASK, VFREDUSUM_VS, 0x2, 0x20 }, // 2227 |
8219 | | { PseudoVFREDUSUM_VS_M4_E64, VFREDUSUM_VS, 0x2, 0x40 }, // 2228 |
8220 | | { PseudoVFREDUSUM_VS_M4_E64_MASK, VFREDUSUM_VS, 0x2, 0x40 }, // 2229 |
8221 | | { PseudoVFREDUSUM_VS_M8_E16, VFREDUSUM_VS, 0x3, 0x10 }, // 2230 |
8222 | | { PseudoVFREDUSUM_VS_M8_E16_MASK, VFREDUSUM_VS, 0x3, 0x10 }, // 2231 |
8223 | | { PseudoVFREDUSUM_VS_M8_E32, VFREDUSUM_VS, 0x3, 0x20 }, // 2232 |
8224 | | { PseudoVFREDUSUM_VS_M8_E32_MASK, VFREDUSUM_VS, 0x3, 0x20 }, // 2233 |
8225 | | { PseudoVFREDUSUM_VS_M8_E64, VFREDUSUM_VS, 0x3, 0x40 }, // 2234 |
8226 | | { PseudoVFREDUSUM_VS_M8_E64_MASK, VFREDUSUM_VS, 0x3, 0x40 }, // 2235 |
8227 | | { PseudoVFREDUSUM_VS_MF4_E16, VFREDUSUM_VS, 0x6, 0x10 }, // 2236 |
8228 | | { PseudoVFREDUSUM_VS_MF4_E16_MASK, VFREDUSUM_VS, 0x6, 0x10 }, // 2237 |
8229 | | { PseudoVFREDUSUM_VS_MF2_E16, VFREDUSUM_VS, 0x7, 0x10 }, // 2238 |
8230 | | { PseudoVFREDUSUM_VS_MF2_E16_MASK, VFREDUSUM_VS, 0x7, 0x10 }, // 2239 |
8231 | | { PseudoVFREDUSUM_VS_MF2_E32, VFREDUSUM_VS, 0x7, 0x20 }, // 2240 |
8232 | | { PseudoVFREDUSUM_VS_MF2_E32_MASK, VFREDUSUM_VS, 0x7, 0x20 }, // 2241 |
8233 | | { PseudoVFRSQRT7_V_M1, VFRSQRT7_V, 0x0, 0x0 }, // 2242 |
8234 | | { PseudoVFRSQRT7_V_M1_MASK, VFRSQRT7_V, 0x0, 0x0 }, // 2243 |
8235 | | { PseudoVFRSQRT7_V_M2, VFRSQRT7_V, 0x1, 0x0 }, // 2244 |
8236 | | { PseudoVFRSQRT7_V_M2_MASK, VFRSQRT7_V, 0x1, 0x0 }, // 2245 |
8237 | | { PseudoVFRSQRT7_V_M4, VFRSQRT7_V, 0x2, 0x0 }, // 2246 |
8238 | | { PseudoVFRSQRT7_V_M4_MASK, VFRSQRT7_V, 0x2, 0x0 }, // 2247 |
8239 | | { PseudoVFRSQRT7_V_M8, VFRSQRT7_V, 0x3, 0x0 }, // 2248 |
8240 | | { PseudoVFRSQRT7_V_M8_MASK, VFRSQRT7_V, 0x3, 0x0 }, // 2249 |
8241 | | { PseudoVFRSQRT7_V_MF4, VFRSQRT7_V, 0x6, 0x0 }, // 2250 |
8242 | | { PseudoVFRSQRT7_V_MF4_MASK, VFRSQRT7_V, 0x6, 0x0 }, // 2251 |
8243 | | { PseudoVFRSQRT7_V_MF2, VFRSQRT7_V, 0x7, 0x0 }, // 2252 |
8244 | | { PseudoVFRSQRT7_V_MF2_MASK, VFRSQRT7_V, 0x7, 0x0 }, // 2253 |
8245 | | { PseudoVFRSUB_VFPR16_M1, VFRSUB_VF, 0x0, 0x0 }, // 2254 |
8246 | | { PseudoVFRSUB_VFPR16_M1_MASK, VFRSUB_VF, 0x0, 0x0 }, // 2255 |
8247 | | { PseudoVFRSUB_VFPR32_M1, VFRSUB_VF, 0x0, 0x0 }, // 2256 |
8248 | | { PseudoVFRSUB_VFPR32_M1_MASK, VFRSUB_VF, 0x0, 0x0 }, // 2257 |
8249 | | { PseudoVFRSUB_VFPR64_M1, VFRSUB_VF, 0x0, 0x0 }, // 2258 |
8250 | | { PseudoVFRSUB_VFPR64_M1_MASK, VFRSUB_VF, 0x0, 0x0 }, // 2259 |
8251 | | { PseudoVFRSUB_VFPR16_M2, VFRSUB_VF, 0x1, 0x0 }, // 2260 |
8252 | | { PseudoVFRSUB_VFPR16_M2_MASK, VFRSUB_VF, 0x1, 0x0 }, // 2261 |
8253 | | { PseudoVFRSUB_VFPR32_M2, VFRSUB_VF, 0x1, 0x0 }, // 2262 |
8254 | | { PseudoVFRSUB_VFPR32_M2_MASK, VFRSUB_VF, 0x1, 0x0 }, // 2263 |
8255 | | { PseudoVFRSUB_VFPR64_M2, VFRSUB_VF, 0x1, 0x0 }, // 2264 |
8256 | | { PseudoVFRSUB_VFPR64_M2_MASK, VFRSUB_VF, 0x1, 0x0 }, // 2265 |
8257 | | { PseudoVFRSUB_VFPR16_M4, VFRSUB_VF, 0x2, 0x0 }, // 2266 |
8258 | | { PseudoVFRSUB_VFPR16_M4_MASK, VFRSUB_VF, 0x2, 0x0 }, // 2267 |
8259 | | { PseudoVFRSUB_VFPR32_M4, VFRSUB_VF, 0x2, 0x0 }, // 2268 |
8260 | | { PseudoVFRSUB_VFPR32_M4_MASK, VFRSUB_VF, 0x2, 0x0 }, // 2269 |
8261 | | { PseudoVFRSUB_VFPR64_M4, VFRSUB_VF, 0x2, 0x0 }, // 2270 |
8262 | | { PseudoVFRSUB_VFPR64_M4_MASK, VFRSUB_VF, 0x2, 0x0 }, // 2271 |
8263 | | { PseudoVFRSUB_VFPR16_M8, VFRSUB_VF, 0x3, 0x0 }, // 2272 |
8264 | | { PseudoVFRSUB_VFPR16_M8_MASK, VFRSUB_VF, 0x3, 0x0 }, // 2273 |
8265 | | { PseudoVFRSUB_VFPR32_M8, VFRSUB_VF, 0x3, 0x0 }, // 2274 |
8266 | | { PseudoVFRSUB_VFPR32_M8_MASK, VFRSUB_VF, 0x3, 0x0 }, // 2275 |
8267 | | { PseudoVFRSUB_VFPR64_M8, VFRSUB_VF, 0x3, 0x0 }, // 2276 |
8268 | | { PseudoVFRSUB_VFPR64_M8_MASK, VFRSUB_VF, 0x3, 0x0 }, // 2277 |
8269 | | { PseudoVFRSUB_VFPR16_MF4, VFRSUB_VF, 0x6, 0x0 }, // 2278 |
8270 | | { PseudoVFRSUB_VFPR16_MF4_MASK, VFRSUB_VF, 0x6, 0x0 }, // 2279 |
8271 | | { PseudoVFRSUB_VFPR16_MF2, VFRSUB_VF, 0x7, 0x0 }, // 2280 |
8272 | | { PseudoVFRSUB_VFPR16_MF2_MASK, VFRSUB_VF, 0x7, 0x0 }, // 2281 |
8273 | | { PseudoVFRSUB_VFPR32_MF2, VFRSUB_VF, 0x7, 0x0 }, // 2282 |
8274 | | { PseudoVFRSUB_VFPR32_MF2_MASK, VFRSUB_VF, 0x7, 0x0 }, // 2283 |
8275 | | { PseudoVFSGNJN_VFPR16_M1, VFSGNJN_VF, 0x0, 0x0 }, // 2284 |
8276 | | { PseudoVFSGNJN_VFPR16_M1_MASK, VFSGNJN_VF, 0x0, 0x0 }, // 2285 |
8277 | | { PseudoVFSGNJN_VFPR32_M1, VFSGNJN_VF, 0x0, 0x0 }, // 2286 |
8278 | | { PseudoVFSGNJN_VFPR32_M1_MASK, VFSGNJN_VF, 0x0, 0x0 }, // 2287 |
8279 | | { PseudoVFSGNJN_VFPR64_M1, VFSGNJN_VF, 0x0, 0x0 }, // 2288 |
8280 | | { PseudoVFSGNJN_VFPR64_M1_MASK, VFSGNJN_VF, 0x0, 0x0 }, // 2289 |
8281 | | { PseudoVFSGNJN_VFPR16_M2, VFSGNJN_VF, 0x1, 0x0 }, // 2290 |
8282 | | { PseudoVFSGNJN_VFPR16_M2_MASK, VFSGNJN_VF, 0x1, 0x0 }, // 2291 |
8283 | | { PseudoVFSGNJN_VFPR32_M2, VFSGNJN_VF, 0x1, 0x0 }, // 2292 |
8284 | | { PseudoVFSGNJN_VFPR32_M2_MASK, VFSGNJN_VF, 0x1, 0x0 }, // 2293 |
8285 | | { PseudoVFSGNJN_VFPR64_M2, VFSGNJN_VF, 0x1, 0x0 }, // 2294 |
8286 | | { PseudoVFSGNJN_VFPR64_M2_MASK, VFSGNJN_VF, 0x1, 0x0 }, // 2295 |
8287 | | { PseudoVFSGNJN_VFPR16_M4, VFSGNJN_VF, 0x2, 0x0 }, // 2296 |
8288 | | { PseudoVFSGNJN_VFPR16_M4_MASK, VFSGNJN_VF, 0x2, 0x0 }, // 2297 |
8289 | | { PseudoVFSGNJN_VFPR32_M4, VFSGNJN_VF, 0x2, 0x0 }, // 2298 |
8290 | | { PseudoVFSGNJN_VFPR32_M4_MASK, VFSGNJN_VF, 0x2, 0x0 }, // 2299 |
8291 | | { PseudoVFSGNJN_VFPR64_M4, VFSGNJN_VF, 0x2, 0x0 }, // 2300 |
8292 | | { PseudoVFSGNJN_VFPR64_M4_MASK, VFSGNJN_VF, 0x2, 0x0 }, // 2301 |
8293 | | { PseudoVFSGNJN_VFPR16_M8, VFSGNJN_VF, 0x3, 0x0 }, // 2302 |
8294 | | { PseudoVFSGNJN_VFPR16_M8_MASK, VFSGNJN_VF, 0x3, 0x0 }, // 2303 |
8295 | | { PseudoVFSGNJN_VFPR32_M8, VFSGNJN_VF, 0x3, 0x0 }, // 2304 |
8296 | | { PseudoVFSGNJN_VFPR32_M8_MASK, VFSGNJN_VF, 0x3, 0x0 }, // 2305 |
8297 | | { PseudoVFSGNJN_VFPR64_M8, VFSGNJN_VF, 0x3, 0x0 }, // 2306 |
8298 | | { PseudoVFSGNJN_VFPR64_M8_MASK, VFSGNJN_VF, 0x3, 0x0 }, // 2307 |
8299 | | { PseudoVFSGNJN_VFPR16_MF4, VFSGNJN_VF, 0x6, 0x0 }, // 2308 |
8300 | | { PseudoVFSGNJN_VFPR16_MF4_MASK, VFSGNJN_VF, 0x6, 0x0 }, // 2309 |
8301 | | { PseudoVFSGNJN_VFPR16_MF2, VFSGNJN_VF, 0x7, 0x0 }, // 2310 |
8302 | | { PseudoVFSGNJN_VFPR16_MF2_MASK, VFSGNJN_VF, 0x7, 0x0 }, // 2311 |
8303 | | { PseudoVFSGNJN_VFPR32_MF2, VFSGNJN_VF, 0x7, 0x0 }, // 2312 |
8304 | | { PseudoVFSGNJN_VFPR32_MF2_MASK, VFSGNJN_VF, 0x7, 0x0 }, // 2313 |
8305 | | { PseudoVFSGNJN_VV_M1, VFSGNJN_VV, 0x0, 0x0 }, // 2314 |
8306 | | { PseudoVFSGNJN_VV_M1_MASK, VFSGNJN_VV, 0x0, 0x0 }, // 2315 |
8307 | | { PseudoVFSGNJN_VV_M2, VFSGNJN_VV, 0x1, 0x0 }, // 2316 |
8308 | | { PseudoVFSGNJN_VV_M2_MASK, VFSGNJN_VV, 0x1, 0x0 }, // 2317 |
8309 | | { PseudoVFSGNJN_VV_M4, VFSGNJN_VV, 0x2, 0x0 }, // 2318 |
8310 | | { PseudoVFSGNJN_VV_M4_MASK, VFSGNJN_VV, 0x2, 0x0 }, // 2319 |
8311 | | { PseudoVFSGNJN_VV_M8, VFSGNJN_VV, 0x3, 0x0 }, // 2320 |
8312 | | { PseudoVFSGNJN_VV_M8_MASK, VFSGNJN_VV, 0x3, 0x0 }, // 2321 |
8313 | | { PseudoVFSGNJN_VV_MF4, VFSGNJN_VV, 0x6, 0x0 }, // 2322 |
8314 | | { PseudoVFSGNJN_VV_MF4_MASK, VFSGNJN_VV, 0x6, 0x0 }, // 2323 |
8315 | | { PseudoVFSGNJN_VV_MF2, VFSGNJN_VV, 0x7, 0x0 }, // 2324 |
8316 | | { PseudoVFSGNJN_VV_MF2_MASK, VFSGNJN_VV, 0x7, 0x0 }, // 2325 |
8317 | | { PseudoVFSGNJX_VFPR16_M1, VFSGNJX_VF, 0x0, 0x0 }, // 2326 |
8318 | | { PseudoVFSGNJX_VFPR16_M1_MASK, VFSGNJX_VF, 0x0, 0x0 }, // 2327 |
8319 | | { PseudoVFSGNJX_VFPR32_M1, VFSGNJX_VF, 0x0, 0x0 }, // 2328 |
8320 | | { PseudoVFSGNJX_VFPR32_M1_MASK, VFSGNJX_VF, 0x0, 0x0 }, // 2329 |
8321 | | { PseudoVFSGNJX_VFPR64_M1, VFSGNJX_VF, 0x0, 0x0 }, // 2330 |
8322 | | { PseudoVFSGNJX_VFPR64_M1_MASK, VFSGNJX_VF, 0x0, 0x0 }, // 2331 |
8323 | | { PseudoVFSGNJX_VFPR16_M2, VFSGNJX_VF, 0x1, 0x0 }, // 2332 |
8324 | | { PseudoVFSGNJX_VFPR16_M2_MASK, VFSGNJX_VF, 0x1, 0x0 }, // 2333 |
8325 | | { PseudoVFSGNJX_VFPR32_M2, VFSGNJX_VF, 0x1, 0x0 }, // 2334 |
8326 | | { PseudoVFSGNJX_VFPR32_M2_MASK, VFSGNJX_VF, 0x1, 0x0 }, // 2335 |
8327 | | { PseudoVFSGNJX_VFPR64_M2, VFSGNJX_VF, 0x1, 0x0 }, // 2336 |
8328 | | { PseudoVFSGNJX_VFPR64_M2_MASK, VFSGNJX_VF, 0x1, 0x0 }, // 2337 |
8329 | | { PseudoVFSGNJX_VFPR16_M4, VFSGNJX_VF, 0x2, 0x0 }, // 2338 |
8330 | | { PseudoVFSGNJX_VFPR16_M4_MASK, VFSGNJX_VF, 0x2, 0x0 }, // 2339 |
8331 | | { PseudoVFSGNJX_VFPR32_M4, VFSGNJX_VF, 0x2, 0x0 }, // 2340 |
8332 | | { PseudoVFSGNJX_VFPR32_M4_MASK, VFSGNJX_VF, 0x2, 0x0 }, // 2341 |
8333 | | { PseudoVFSGNJX_VFPR64_M4, VFSGNJX_VF, 0x2, 0x0 }, // 2342 |
8334 | | { PseudoVFSGNJX_VFPR64_M4_MASK, VFSGNJX_VF, 0x2, 0x0 }, // 2343 |
8335 | | { PseudoVFSGNJX_VFPR16_M8, VFSGNJX_VF, 0x3, 0x0 }, // 2344 |
8336 | | { PseudoVFSGNJX_VFPR16_M8_MASK, VFSGNJX_VF, 0x3, 0x0 }, // 2345 |
8337 | | { PseudoVFSGNJX_VFPR32_M8, VFSGNJX_VF, 0x3, 0x0 }, // 2346 |
8338 | | { PseudoVFSGNJX_VFPR32_M8_MASK, VFSGNJX_VF, 0x3, 0x0 }, // 2347 |
8339 | | { PseudoVFSGNJX_VFPR64_M8, VFSGNJX_VF, 0x3, 0x0 }, // 2348 |
8340 | | { PseudoVFSGNJX_VFPR64_M8_MASK, VFSGNJX_VF, 0x3, 0x0 }, // 2349 |
8341 | | { PseudoVFSGNJX_VFPR16_MF4, VFSGNJX_VF, 0x6, 0x0 }, // 2350 |
8342 | | { PseudoVFSGNJX_VFPR16_MF4_MASK, VFSGNJX_VF, 0x6, 0x0 }, // 2351 |
8343 | | { PseudoVFSGNJX_VFPR16_MF2, VFSGNJX_VF, 0x7, 0x0 }, // 2352 |
8344 | | { PseudoVFSGNJX_VFPR16_MF2_MASK, VFSGNJX_VF, 0x7, 0x0 }, // 2353 |
8345 | | { PseudoVFSGNJX_VFPR32_MF2, VFSGNJX_VF, 0x7, 0x0 }, // 2354 |
8346 | | { PseudoVFSGNJX_VFPR32_MF2_MASK, VFSGNJX_VF, 0x7, 0x0 }, // 2355 |
8347 | | { PseudoVFSGNJX_VV_M1, VFSGNJX_VV, 0x0, 0x0 }, // 2356 |
8348 | | { PseudoVFSGNJX_VV_M1_MASK, VFSGNJX_VV, 0x0, 0x0 }, // 2357 |
8349 | | { PseudoVFSGNJX_VV_M2, VFSGNJX_VV, 0x1, 0x0 }, // 2358 |
8350 | | { PseudoVFSGNJX_VV_M2_MASK, VFSGNJX_VV, 0x1, 0x0 }, // 2359 |
8351 | | { PseudoVFSGNJX_VV_M4, VFSGNJX_VV, 0x2, 0x0 }, // 2360 |
8352 | | { PseudoVFSGNJX_VV_M4_MASK, VFSGNJX_VV, 0x2, 0x0 }, // 2361 |
8353 | | { PseudoVFSGNJX_VV_M8, VFSGNJX_VV, 0x3, 0x0 }, // 2362 |
8354 | | { PseudoVFSGNJX_VV_M8_MASK, VFSGNJX_VV, 0x3, 0x0 }, // 2363 |
8355 | | { PseudoVFSGNJX_VV_MF4, VFSGNJX_VV, 0x6, 0x0 }, // 2364 |
8356 | | { PseudoVFSGNJX_VV_MF4_MASK, VFSGNJX_VV, 0x6, 0x0 }, // 2365 |
8357 | | { PseudoVFSGNJX_VV_MF2, VFSGNJX_VV, 0x7, 0x0 }, // 2366 |
8358 | | { PseudoVFSGNJX_VV_MF2_MASK, VFSGNJX_VV, 0x7, 0x0 }, // 2367 |
8359 | | { PseudoVFSGNJ_VFPR16_M1, VFSGNJ_VF, 0x0, 0x0 }, // 2368 |
8360 | | { PseudoVFSGNJ_VFPR16_M1_MASK, VFSGNJ_VF, 0x0, 0x0 }, // 2369 |
8361 | | { PseudoVFSGNJ_VFPR32_M1, VFSGNJ_VF, 0x0, 0x0 }, // 2370 |
8362 | | { PseudoVFSGNJ_VFPR32_M1_MASK, VFSGNJ_VF, 0x0, 0x0 }, // 2371 |
8363 | | { PseudoVFSGNJ_VFPR64_M1, VFSGNJ_VF, 0x0, 0x0 }, // 2372 |
8364 | | { PseudoVFSGNJ_VFPR64_M1_MASK, VFSGNJ_VF, 0x0, 0x0 }, // 2373 |
8365 | | { PseudoVFSGNJ_VFPR16_M2, VFSGNJ_VF, 0x1, 0x0 }, // 2374 |
8366 | | { PseudoVFSGNJ_VFPR16_M2_MASK, VFSGNJ_VF, 0x1, 0x0 }, // 2375 |
8367 | | { PseudoVFSGNJ_VFPR32_M2, VFSGNJ_VF, 0x1, 0x0 }, // 2376 |
8368 | | { PseudoVFSGNJ_VFPR32_M2_MASK, VFSGNJ_VF, 0x1, 0x0 }, // 2377 |
8369 | | { PseudoVFSGNJ_VFPR64_M2, VFSGNJ_VF, 0x1, 0x0 }, // 2378 |
8370 | | { PseudoVFSGNJ_VFPR64_M2_MASK, VFSGNJ_VF, 0x1, 0x0 }, // 2379 |
8371 | | { PseudoVFSGNJ_VFPR16_M4, VFSGNJ_VF, 0x2, 0x0 }, // 2380 |
8372 | | { PseudoVFSGNJ_VFPR16_M4_MASK, VFSGNJ_VF, 0x2, 0x0 }, // 2381 |
8373 | | { PseudoVFSGNJ_VFPR32_M4, VFSGNJ_VF, 0x2, 0x0 }, // 2382 |
8374 | | { PseudoVFSGNJ_VFPR32_M4_MASK, VFSGNJ_VF, 0x2, 0x0 }, // 2383 |
8375 | | { PseudoVFSGNJ_VFPR64_M4, VFSGNJ_VF, 0x2, 0x0 }, // 2384 |
8376 | | { PseudoVFSGNJ_VFPR64_M4_MASK, VFSGNJ_VF, 0x2, 0x0 }, // 2385 |
8377 | | { PseudoVFSGNJ_VFPR16_M8, VFSGNJ_VF, 0x3, 0x0 }, // 2386 |
8378 | | { PseudoVFSGNJ_VFPR16_M8_MASK, VFSGNJ_VF, 0x3, 0x0 }, // 2387 |
8379 | | { PseudoVFSGNJ_VFPR32_M8, VFSGNJ_VF, 0x3, 0x0 }, // 2388 |
8380 | | { PseudoVFSGNJ_VFPR32_M8_MASK, VFSGNJ_VF, 0x3, 0x0 }, // 2389 |
8381 | | { PseudoVFSGNJ_VFPR64_M8, VFSGNJ_VF, 0x3, 0x0 }, // 2390 |
8382 | | { PseudoVFSGNJ_VFPR64_M8_MASK, VFSGNJ_VF, 0x3, 0x0 }, // 2391 |
8383 | | { PseudoVFSGNJ_VFPR16_MF4, VFSGNJ_VF, 0x6, 0x0 }, // 2392 |
8384 | | { PseudoVFSGNJ_VFPR16_MF4_MASK, VFSGNJ_VF, 0x6, 0x0 }, // 2393 |
8385 | | { PseudoVFSGNJ_VFPR16_MF2, VFSGNJ_VF, 0x7, 0x0 }, // 2394 |
8386 | | { PseudoVFSGNJ_VFPR16_MF2_MASK, VFSGNJ_VF, 0x7, 0x0 }, // 2395 |
8387 | | { PseudoVFSGNJ_VFPR32_MF2, VFSGNJ_VF, 0x7, 0x0 }, // 2396 |
8388 | | { PseudoVFSGNJ_VFPR32_MF2_MASK, VFSGNJ_VF, 0x7, 0x0 }, // 2397 |
8389 | | { PseudoVFSGNJ_VV_M1, VFSGNJ_VV, 0x0, 0x0 }, // 2398 |
8390 | | { PseudoVFSGNJ_VV_M1_MASK, VFSGNJ_VV, 0x0, 0x0 }, // 2399 |
8391 | | { PseudoVFSGNJ_VV_M2, VFSGNJ_VV, 0x1, 0x0 }, // 2400 |
8392 | | { PseudoVFSGNJ_VV_M2_MASK, VFSGNJ_VV, 0x1, 0x0 }, // 2401 |
8393 | | { PseudoVFSGNJ_VV_M4, VFSGNJ_VV, 0x2, 0x0 }, // 2402 |
8394 | | { PseudoVFSGNJ_VV_M4_MASK, VFSGNJ_VV, 0x2, 0x0 }, // 2403 |
8395 | | { PseudoVFSGNJ_VV_M8, VFSGNJ_VV, 0x3, 0x0 }, // 2404 |
8396 | | { PseudoVFSGNJ_VV_M8_MASK, VFSGNJ_VV, 0x3, 0x0 }, // 2405 |
8397 | | { PseudoVFSGNJ_VV_MF4, VFSGNJ_VV, 0x6, 0x0 }, // 2406 |
8398 | | { PseudoVFSGNJ_VV_MF4_MASK, VFSGNJ_VV, 0x6, 0x0 }, // 2407 |
8399 | | { PseudoVFSGNJ_VV_MF2, VFSGNJ_VV, 0x7, 0x0 }, // 2408 |
8400 | | { PseudoVFSGNJ_VV_MF2_MASK, VFSGNJ_VV, 0x7, 0x0 }, // 2409 |
8401 | | { PseudoVFSLIDE1DOWN_VFPR16_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2410 |
8402 | | { PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2411 |
8403 | | { PseudoVFSLIDE1DOWN_VFPR32_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2412 |
8404 | | { PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2413 |
8405 | | { PseudoVFSLIDE1DOWN_VFPR64_M1, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2414 |
8406 | | { PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, VFSLIDE1DOWN_VF, 0x0, 0x0 }, // 2415 |
8407 | | { PseudoVFSLIDE1DOWN_VFPR16_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2416 |
8408 | | { PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2417 |
8409 | | { PseudoVFSLIDE1DOWN_VFPR32_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2418 |
8410 | | { PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2419 |
8411 | | { PseudoVFSLIDE1DOWN_VFPR64_M2, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2420 |
8412 | | { PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, VFSLIDE1DOWN_VF, 0x1, 0x0 }, // 2421 |
8413 | | { PseudoVFSLIDE1DOWN_VFPR16_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2422 |
8414 | | { PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2423 |
8415 | | { PseudoVFSLIDE1DOWN_VFPR32_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2424 |
8416 | | { PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2425 |
8417 | | { PseudoVFSLIDE1DOWN_VFPR64_M4, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2426 |
8418 | | { PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, VFSLIDE1DOWN_VF, 0x2, 0x0 }, // 2427 |
8419 | | { PseudoVFSLIDE1DOWN_VFPR16_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2428 |
8420 | | { PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2429 |
8421 | | { PseudoVFSLIDE1DOWN_VFPR32_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2430 |
8422 | | { PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2431 |
8423 | | { PseudoVFSLIDE1DOWN_VFPR64_M8, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2432 |
8424 | | { PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, VFSLIDE1DOWN_VF, 0x3, 0x0 }, // 2433 |
8425 | | { PseudoVFSLIDE1DOWN_VFPR16_MF4, VFSLIDE1DOWN_VF, 0x6, 0x0 }, // 2434 |
8426 | | { PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, VFSLIDE1DOWN_VF, 0x6, 0x0 }, // 2435 |
8427 | | { PseudoVFSLIDE1DOWN_VFPR16_MF2, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2436 |
8428 | | { PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2437 |
8429 | | { PseudoVFSLIDE1DOWN_VFPR32_MF2, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2438 |
8430 | | { PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, VFSLIDE1DOWN_VF, 0x7, 0x0 }, // 2439 |
8431 | | { PseudoVFSLIDE1UP_VFPR16_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2440 |
8432 | | { PseudoVFSLIDE1UP_VFPR16_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2441 |
8433 | | { PseudoVFSLIDE1UP_VFPR32_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2442 |
8434 | | { PseudoVFSLIDE1UP_VFPR32_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2443 |
8435 | | { PseudoVFSLIDE1UP_VFPR64_M1, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2444 |
8436 | | { PseudoVFSLIDE1UP_VFPR64_M1_MASK, VFSLIDE1UP_VF, 0x0, 0x0 }, // 2445 |
8437 | | { PseudoVFSLIDE1UP_VFPR16_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2446 |
8438 | | { PseudoVFSLIDE1UP_VFPR16_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2447 |
8439 | | { PseudoVFSLIDE1UP_VFPR32_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2448 |
8440 | | { PseudoVFSLIDE1UP_VFPR32_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2449 |
8441 | | { PseudoVFSLIDE1UP_VFPR64_M2, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2450 |
8442 | | { PseudoVFSLIDE1UP_VFPR64_M2_MASK, VFSLIDE1UP_VF, 0x1, 0x0 }, // 2451 |
8443 | | { PseudoVFSLIDE1UP_VFPR16_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2452 |
8444 | | { PseudoVFSLIDE1UP_VFPR16_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2453 |
8445 | | { PseudoVFSLIDE1UP_VFPR32_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2454 |
8446 | | { PseudoVFSLIDE1UP_VFPR32_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2455 |
8447 | | { PseudoVFSLIDE1UP_VFPR64_M4, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2456 |
8448 | | { PseudoVFSLIDE1UP_VFPR64_M4_MASK, VFSLIDE1UP_VF, 0x2, 0x0 }, // 2457 |
8449 | | { PseudoVFSLIDE1UP_VFPR16_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2458 |
8450 | | { PseudoVFSLIDE1UP_VFPR16_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2459 |
8451 | | { PseudoVFSLIDE1UP_VFPR32_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2460 |
8452 | | { PseudoVFSLIDE1UP_VFPR32_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2461 |
8453 | | { PseudoVFSLIDE1UP_VFPR64_M8, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2462 |
8454 | | { PseudoVFSLIDE1UP_VFPR64_M8_MASK, VFSLIDE1UP_VF, 0x3, 0x0 }, // 2463 |
8455 | | { PseudoVFSLIDE1UP_VFPR16_MF4, VFSLIDE1UP_VF, 0x6, 0x0 }, // 2464 |
8456 | | { PseudoVFSLIDE1UP_VFPR16_MF4_MASK, VFSLIDE1UP_VF, 0x6, 0x0 }, // 2465 |
8457 | | { PseudoVFSLIDE1UP_VFPR16_MF2, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2466 |
8458 | | { PseudoVFSLIDE1UP_VFPR16_MF2_MASK, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2467 |
8459 | | { PseudoVFSLIDE1UP_VFPR32_MF2, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2468 |
8460 | | { PseudoVFSLIDE1UP_VFPR32_MF2_MASK, VFSLIDE1UP_VF, 0x7, 0x0 }, // 2469 |
8461 | | { PseudoVFSQRT_V_M1_E16, VFSQRT_V, 0x0, 0x10 }, // 2470 |
8462 | | { PseudoVFSQRT_V_M1_E16_MASK, VFSQRT_V, 0x0, 0x10 }, // 2471 |
8463 | | { PseudoVFSQRT_V_M1_E32, VFSQRT_V, 0x0, 0x20 }, // 2472 |
8464 | | { PseudoVFSQRT_V_M1_E32_MASK, VFSQRT_V, 0x0, 0x20 }, // 2473 |
8465 | | { PseudoVFSQRT_V_M1_E64, VFSQRT_V, 0x0, 0x40 }, // 2474 |
8466 | | { PseudoVFSQRT_V_M1_E64_MASK, VFSQRT_V, 0x0, 0x40 }, // 2475 |
8467 | | { PseudoVFSQRT_V_M2_E16, VFSQRT_V, 0x1, 0x10 }, // 2476 |
8468 | | { PseudoVFSQRT_V_M2_E16_MASK, VFSQRT_V, 0x1, 0x10 }, // 2477 |
8469 | | { PseudoVFSQRT_V_M2_E32, VFSQRT_V, 0x1, 0x20 }, // 2478 |
8470 | | { PseudoVFSQRT_V_M2_E32_MASK, VFSQRT_V, 0x1, 0x20 }, // 2479 |
8471 | | { PseudoVFSQRT_V_M2_E64, VFSQRT_V, 0x1, 0x40 }, // 2480 |
8472 | | { PseudoVFSQRT_V_M2_E64_MASK, VFSQRT_V, 0x1, 0x40 }, // 2481 |
8473 | | { PseudoVFSQRT_V_M4_E16, VFSQRT_V, 0x2, 0x10 }, // 2482 |
8474 | | { PseudoVFSQRT_V_M4_E16_MASK, VFSQRT_V, 0x2, 0x10 }, // 2483 |
8475 | | { PseudoVFSQRT_V_M4_E32, VFSQRT_V, 0x2, 0x20 }, // 2484 |
8476 | | { PseudoVFSQRT_V_M4_E32_MASK, VFSQRT_V, 0x2, 0x20 }, // 2485 |
8477 | | { PseudoVFSQRT_V_M4_E64, VFSQRT_V, 0x2, 0x40 }, // 2486 |
8478 | | { PseudoVFSQRT_V_M4_E64_MASK, VFSQRT_V, 0x2, 0x40 }, // 2487 |
8479 | | { PseudoVFSQRT_V_M8_E16, VFSQRT_V, 0x3, 0x10 }, // 2488 |
8480 | | { PseudoVFSQRT_V_M8_E16_MASK, VFSQRT_V, 0x3, 0x10 }, // 2489 |
8481 | | { PseudoVFSQRT_V_M8_E32, VFSQRT_V, 0x3, 0x20 }, // 2490 |
8482 | | { PseudoVFSQRT_V_M8_E32_MASK, VFSQRT_V, 0x3, 0x20 }, // 2491 |
8483 | | { PseudoVFSQRT_V_M8_E64, VFSQRT_V, 0x3, 0x40 }, // 2492 |
8484 | | { PseudoVFSQRT_V_M8_E64_MASK, VFSQRT_V, 0x3, 0x40 }, // 2493 |
8485 | | { PseudoVFSQRT_V_MF4_E16, VFSQRT_V, 0x6, 0x10 }, // 2494 |
8486 | | { PseudoVFSQRT_V_MF4_E16_MASK, VFSQRT_V, 0x6, 0x10 }, // 2495 |
8487 | | { PseudoVFSQRT_V_MF2_E16, VFSQRT_V, 0x7, 0x10 }, // 2496 |
8488 | | { PseudoVFSQRT_V_MF2_E16_MASK, VFSQRT_V, 0x7, 0x10 }, // 2497 |
8489 | | { PseudoVFSQRT_V_MF2_E32, VFSQRT_V, 0x7, 0x20 }, // 2498 |
8490 | | { PseudoVFSQRT_V_MF2_E32_MASK, VFSQRT_V, 0x7, 0x20 }, // 2499 |
8491 | | { PseudoVFSUB_VFPR16_M1, VFSUB_VF, 0x0, 0x0 }, // 2500 |
8492 | | { PseudoVFSUB_VFPR16_M1_MASK, VFSUB_VF, 0x0, 0x0 }, // 2501 |
8493 | | { PseudoVFSUB_VFPR32_M1, VFSUB_VF, 0x0, 0x0 }, // 2502 |
8494 | | { PseudoVFSUB_VFPR32_M1_MASK, VFSUB_VF, 0x0, 0x0 }, // 2503 |
8495 | | { PseudoVFSUB_VFPR64_M1, VFSUB_VF, 0x0, 0x0 }, // 2504 |
8496 | | { PseudoVFSUB_VFPR64_M1_MASK, VFSUB_VF, 0x0, 0x0 }, // 2505 |
8497 | | { PseudoVFSUB_VFPR16_M2, VFSUB_VF, 0x1, 0x0 }, // 2506 |
8498 | | { PseudoVFSUB_VFPR16_M2_MASK, VFSUB_VF, 0x1, 0x0 }, // 2507 |
8499 | | { PseudoVFSUB_VFPR32_M2, VFSUB_VF, 0x1, 0x0 }, // 2508 |
8500 | | { PseudoVFSUB_VFPR32_M2_MASK, VFSUB_VF, 0x1, 0x0 }, // 2509 |
8501 | | { PseudoVFSUB_VFPR64_M2, VFSUB_VF, 0x1, 0x0 }, // 2510 |
8502 | | { PseudoVFSUB_VFPR64_M2_MASK, VFSUB_VF, 0x1, 0x0 }, // 2511 |
8503 | | { PseudoVFSUB_VFPR16_M4, VFSUB_VF, 0x2, 0x0 }, // 2512 |
8504 | | { PseudoVFSUB_VFPR16_M4_MASK, VFSUB_VF, 0x2, 0x0 }, // 2513 |
8505 | | { PseudoVFSUB_VFPR32_M4, VFSUB_VF, 0x2, 0x0 }, // 2514 |
8506 | | { PseudoVFSUB_VFPR32_M4_MASK, VFSUB_VF, 0x2, 0x0 }, // 2515 |
8507 | | { PseudoVFSUB_VFPR64_M4, VFSUB_VF, 0x2, 0x0 }, // 2516 |
8508 | | { PseudoVFSUB_VFPR64_M4_MASK, VFSUB_VF, 0x2, 0x0 }, // 2517 |
8509 | | { PseudoVFSUB_VFPR16_M8, VFSUB_VF, 0x3, 0x0 }, // 2518 |
8510 | | { PseudoVFSUB_VFPR16_M8_MASK, VFSUB_VF, 0x3, 0x0 }, // 2519 |
8511 | | { PseudoVFSUB_VFPR32_M8, VFSUB_VF, 0x3, 0x0 }, // 2520 |
8512 | | { PseudoVFSUB_VFPR32_M8_MASK, VFSUB_VF, 0x3, 0x0 }, // 2521 |
8513 | | { PseudoVFSUB_VFPR64_M8, VFSUB_VF, 0x3, 0x0 }, // 2522 |
8514 | | { PseudoVFSUB_VFPR64_M8_MASK, VFSUB_VF, 0x3, 0x0 }, // 2523 |
8515 | | { PseudoVFSUB_VFPR16_MF4, VFSUB_VF, 0x6, 0x0 }, // 2524 |
8516 | | { PseudoVFSUB_VFPR16_MF4_MASK, VFSUB_VF, 0x6, 0x0 }, // 2525 |
8517 | | { PseudoVFSUB_VFPR16_MF2, VFSUB_VF, 0x7, 0x0 }, // 2526 |
8518 | | { PseudoVFSUB_VFPR16_MF2_MASK, VFSUB_VF, 0x7, 0x0 }, // 2527 |
8519 | | { PseudoVFSUB_VFPR32_MF2, VFSUB_VF, 0x7, 0x0 }, // 2528 |
8520 | | { PseudoVFSUB_VFPR32_MF2_MASK, VFSUB_VF, 0x7, 0x0 }, // 2529 |
8521 | | { PseudoVFSUB_VV_M1, VFSUB_VV, 0x0, 0x0 }, // 2530 |
8522 | | { PseudoVFSUB_VV_M1_MASK, VFSUB_VV, 0x0, 0x0 }, // 2531 |
8523 | | { PseudoVFSUB_VV_M2, VFSUB_VV, 0x1, 0x0 }, // 2532 |
8524 | | { PseudoVFSUB_VV_M2_MASK, VFSUB_VV, 0x1, 0x0 }, // 2533 |
8525 | | { PseudoVFSUB_VV_M4, VFSUB_VV, 0x2, 0x0 }, // 2534 |
8526 | | { PseudoVFSUB_VV_M4_MASK, VFSUB_VV, 0x2, 0x0 }, // 2535 |
8527 | | { PseudoVFSUB_VV_M8, VFSUB_VV, 0x3, 0x0 }, // 2536 |
8528 | | { PseudoVFSUB_VV_M8_MASK, VFSUB_VV, 0x3, 0x0 }, // 2537 |
8529 | | { PseudoVFSUB_VV_MF4, VFSUB_VV, 0x6, 0x0 }, // 2538 |
8530 | | { PseudoVFSUB_VV_MF4_MASK, VFSUB_VV, 0x6, 0x0 }, // 2539 |
8531 | | { PseudoVFSUB_VV_MF2, VFSUB_VV, 0x7, 0x0 }, // 2540 |
8532 | | { PseudoVFSUB_VV_MF2_MASK, VFSUB_VV, 0x7, 0x0 }, // 2541 |
8533 | | { PseudoVFWADD_VFPR16_M1, VFWADD_VF, 0x0, 0x0 }, // 2542 |
8534 | | { PseudoVFWADD_VFPR16_M1_MASK, VFWADD_VF, 0x0, 0x0 }, // 2543 |
8535 | | { PseudoVFWADD_VFPR32_M1, VFWADD_VF, 0x0, 0x0 }, // 2544 |
8536 | | { PseudoVFWADD_VFPR32_M1_MASK, VFWADD_VF, 0x0, 0x0 }, // 2545 |
8537 | | { PseudoVFWADD_VFPR16_M2, VFWADD_VF, 0x1, 0x0 }, // 2546 |
8538 | | { PseudoVFWADD_VFPR16_M2_MASK, VFWADD_VF, 0x1, 0x0 }, // 2547 |
8539 | | { PseudoVFWADD_VFPR32_M2, VFWADD_VF, 0x1, 0x0 }, // 2548 |
8540 | | { PseudoVFWADD_VFPR32_M2_MASK, VFWADD_VF, 0x1, 0x0 }, // 2549 |
8541 | | { PseudoVFWADD_VFPR16_M4, VFWADD_VF, 0x2, 0x0 }, // 2550 |
8542 | | { PseudoVFWADD_VFPR16_M4_MASK, VFWADD_VF, 0x2, 0x0 }, // 2551 |
8543 | | { PseudoVFWADD_VFPR32_M4, VFWADD_VF, 0x2, 0x0 }, // 2552 |
8544 | | { PseudoVFWADD_VFPR32_M4_MASK, VFWADD_VF, 0x2, 0x0 }, // 2553 |
8545 | | { PseudoVFWADD_VFPR16_MF4, VFWADD_VF, 0x6, 0x0 }, // 2554 |
8546 | | { PseudoVFWADD_VFPR16_MF4_MASK, VFWADD_VF, 0x6, 0x0 }, // 2555 |
8547 | | { PseudoVFWADD_VFPR16_MF2, VFWADD_VF, 0x7, 0x0 }, // 2556 |
8548 | | { PseudoVFWADD_VFPR16_MF2_MASK, VFWADD_VF, 0x7, 0x0 }, // 2557 |
8549 | | { PseudoVFWADD_VFPR32_MF2, VFWADD_VF, 0x7, 0x0 }, // 2558 |
8550 | | { PseudoVFWADD_VFPR32_MF2_MASK, VFWADD_VF, 0x7, 0x0 }, // 2559 |
8551 | | { PseudoVFWADD_VV_M1, VFWADD_VV, 0x0, 0x0 }, // 2560 |
8552 | | { PseudoVFWADD_VV_M1_MASK, VFWADD_VV, 0x0, 0x0 }, // 2561 |
8553 | | { PseudoVFWADD_VV_M2, VFWADD_VV, 0x1, 0x0 }, // 2562 |
8554 | | { PseudoVFWADD_VV_M2_MASK, VFWADD_VV, 0x1, 0x0 }, // 2563 |
8555 | | { PseudoVFWADD_VV_M4, VFWADD_VV, 0x2, 0x0 }, // 2564 |
8556 | | { PseudoVFWADD_VV_M4_MASK, VFWADD_VV, 0x2, 0x0 }, // 2565 |
8557 | | { PseudoVFWADD_VV_MF4, VFWADD_VV, 0x6, 0x0 }, // 2566 |
8558 | | { PseudoVFWADD_VV_MF4_MASK, VFWADD_VV, 0x6, 0x0 }, // 2567 |
8559 | | { PseudoVFWADD_VV_MF2, VFWADD_VV, 0x7, 0x0 }, // 2568 |
8560 | | { PseudoVFWADD_VV_MF2_MASK, VFWADD_VV, 0x7, 0x0 }, // 2569 |
8561 | | { PseudoVFWADD_WFPR16_M1, VFWADD_WF, 0x0, 0x0 }, // 2570 |
8562 | | { PseudoVFWADD_WFPR16_M1_MASK, VFWADD_WF, 0x0, 0x0 }, // 2571 |
8563 | | { PseudoVFWADD_WFPR32_M1, VFWADD_WF, 0x0, 0x0 }, // 2572 |
8564 | | { PseudoVFWADD_WFPR32_M1_MASK, VFWADD_WF, 0x0, 0x0 }, // 2573 |
8565 | | { PseudoVFWADD_WFPR16_M2, VFWADD_WF, 0x1, 0x0 }, // 2574 |
8566 | | { PseudoVFWADD_WFPR16_M2_MASK, VFWADD_WF, 0x1, 0x0 }, // 2575 |
8567 | | { PseudoVFWADD_WFPR32_M2, VFWADD_WF, 0x1, 0x0 }, // 2576 |
8568 | | { PseudoVFWADD_WFPR32_M2_MASK, VFWADD_WF, 0x1, 0x0 }, // 2577 |
8569 | | { PseudoVFWADD_WFPR16_M4, VFWADD_WF, 0x2, 0x0 }, // 2578 |
8570 | | { PseudoVFWADD_WFPR16_M4_MASK, VFWADD_WF, 0x2, 0x0 }, // 2579 |
8571 | | { PseudoVFWADD_WFPR32_M4, VFWADD_WF, 0x2, 0x0 }, // 2580 |
8572 | | { PseudoVFWADD_WFPR32_M4_MASK, VFWADD_WF, 0x2, 0x0 }, // 2581 |
8573 | | { PseudoVFWADD_WFPR16_MF4, VFWADD_WF, 0x6, 0x0 }, // 2582 |
8574 | | { PseudoVFWADD_WFPR16_MF4_MASK, VFWADD_WF, 0x6, 0x0 }, // 2583 |
8575 | | { PseudoVFWADD_WFPR16_MF2, VFWADD_WF, 0x7, 0x0 }, // 2584 |
8576 | | { PseudoVFWADD_WFPR16_MF2_MASK, VFWADD_WF, 0x7, 0x0 }, // 2585 |
8577 | | { PseudoVFWADD_WFPR32_MF2, VFWADD_WF, 0x7, 0x0 }, // 2586 |
8578 | | { PseudoVFWADD_WFPR32_MF2_MASK, VFWADD_WF, 0x7, 0x0 }, // 2587 |
8579 | | { PseudoVFWADD_WV_M1, VFWADD_WV, 0x0, 0x0 }, // 2588 |
8580 | | { PseudoVFWADD_WV_M1_MASK, VFWADD_WV, 0x0, 0x0 }, // 2589 |
8581 | | { PseudoVFWADD_WV_M1_MASK_TIED, VFWADD_WV, 0x0, 0x0 }, // 2590 |
8582 | | { PseudoVFWADD_WV_M1_TIED, VFWADD_WV, 0x0, 0x0 }, // 2591 |
8583 | | { PseudoVFWADD_WV_M2, VFWADD_WV, 0x1, 0x0 }, // 2592 |
8584 | | { PseudoVFWADD_WV_M2_MASK, VFWADD_WV, 0x1, 0x0 }, // 2593 |
8585 | | { PseudoVFWADD_WV_M2_MASK_TIED, VFWADD_WV, 0x1, 0x0 }, // 2594 |
8586 | | { PseudoVFWADD_WV_M2_TIED, VFWADD_WV, 0x1, 0x0 }, // 2595 |
8587 | | { PseudoVFWADD_WV_M4, VFWADD_WV, 0x2, 0x0 }, // 2596 |
8588 | | { PseudoVFWADD_WV_M4_MASK, VFWADD_WV, 0x2, 0x0 }, // 2597 |
8589 | | { PseudoVFWADD_WV_M4_MASK_TIED, VFWADD_WV, 0x2, 0x0 }, // 2598 |
8590 | | { PseudoVFWADD_WV_M4_TIED, VFWADD_WV, 0x2, 0x0 }, // 2599 |
8591 | | { PseudoVFWADD_WV_MF4, VFWADD_WV, 0x6, 0x0 }, // 2600 |
8592 | | { PseudoVFWADD_WV_MF4_MASK, VFWADD_WV, 0x6, 0x0 }, // 2601 |
8593 | | { PseudoVFWADD_WV_MF4_MASK_TIED, VFWADD_WV, 0x6, 0x0 }, // 2602 |
8594 | | { PseudoVFWADD_WV_MF4_TIED, VFWADD_WV, 0x6, 0x0 }, // 2603 |
8595 | | { PseudoVFWADD_WV_MF2, VFWADD_WV, 0x7, 0x0 }, // 2604 |
8596 | | { PseudoVFWADD_WV_MF2_MASK, VFWADD_WV, 0x7, 0x0 }, // 2605 |
8597 | | { PseudoVFWADD_WV_MF2_MASK_TIED, VFWADD_WV, 0x7, 0x0 }, // 2606 |
8598 | | { PseudoVFWADD_WV_MF2_TIED, VFWADD_WV, 0x7, 0x0 }, // 2607 |
8599 | | { PseudoVFWCVTBF16_F_F_V_M1, VFWCVTBF16_F_F_V, 0x0, 0x0 }, // 2608 |
8600 | | { PseudoVFWCVTBF16_F_F_V_M1_MASK, VFWCVTBF16_F_F_V, 0x0, 0x0 }, // 2609 |
8601 | | { PseudoVFWCVTBF16_F_F_V_M2, VFWCVTBF16_F_F_V, 0x1, 0x0 }, // 2610 |
8602 | | { PseudoVFWCVTBF16_F_F_V_M2_MASK, VFWCVTBF16_F_F_V, 0x1, 0x0 }, // 2611 |
8603 | | { PseudoVFWCVTBF16_F_F_V_M4, VFWCVTBF16_F_F_V, 0x2, 0x0 }, // 2612 |
8604 | | { PseudoVFWCVTBF16_F_F_V_M4_MASK, VFWCVTBF16_F_F_V, 0x2, 0x0 }, // 2613 |
8605 | | { PseudoVFWCVTBF16_F_F_V_MF4, VFWCVTBF16_F_F_V, 0x6, 0x0 }, // 2614 |
8606 | | { PseudoVFWCVTBF16_F_F_V_MF4_MASK, VFWCVTBF16_F_F_V, 0x6, 0x0 }, // 2615 |
8607 | | { PseudoVFWCVTBF16_F_F_V_MF2, VFWCVTBF16_F_F_V, 0x7, 0x0 }, // 2616 |
8608 | | { PseudoVFWCVTBF16_F_F_V_MF2_MASK, VFWCVTBF16_F_F_V, 0x7, 0x0 }, // 2617 |
8609 | | { PseudoVFWCVT_F_F_V_M1, VFWCVT_F_F_V, 0x0, 0x0 }, // 2618 |
8610 | | { PseudoVFWCVT_F_F_V_M1_MASK, VFWCVT_F_F_V, 0x0, 0x0 }, // 2619 |
8611 | | { PseudoVFWCVT_F_F_V_M2, VFWCVT_F_F_V, 0x1, 0x0 }, // 2620 |
8612 | | { PseudoVFWCVT_F_F_V_M2_MASK, VFWCVT_F_F_V, 0x1, 0x0 }, // 2621 |
8613 | | { PseudoVFWCVT_F_F_V_M4, VFWCVT_F_F_V, 0x2, 0x0 }, // 2622 |
8614 | | { PseudoVFWCVT_F_F_V_M4_MASK, VFWCVT_F_F_V, 0x2, 0x0 }, // 2623 |
8615 | | { PseudoVFWCVT_F_F_V_MF4, VFWCVT_F_F_V, 0x6, 0x0 }, // 2624 |
8616 | | { PseudoVFWCVT_F_F_V_MF4_MASK, VFWCVT_F_F_V, 0x6, 0x0 }, // 2625 |
8617 | | { PseudoVFWCVT_F_F_V_MF2, VFWCVT_F_F_V, 0x7, 0x0 }, // 2626 |
8618 | | { PseudoVFWCVT_F_F_V_MF2_MASK, VFWCVT_F_F_V, 0x7, 0x0 }, // 2627 |
8619 | | { PseudoVFWCVT_F_XU_V_M1, VFWCVT_F_XU_V, 0x0, 0x0 }, // 2628 |
8620 | | { PseudoVFWCVT_F_XU_V_M1_MASK, VFWCVT_F_XU_V, 0x0, 0x0 }, // 2629 |
8621 | | { PseudoVFWCVT_F_XU_V_M2, VFWCVT_F_XU_V, 0x1, 0x0 }, // 2630 |
8622 | | { PseudoVFWCVT_F_XU_V_M2_MASK, VFWCVT_F_XU_V, 0x1, 0x0 }, // 2631 |
8623 | | { PseudoVFWCVT_F_XU_V_M4, VFWCVT_F_XU_V, 0x2, 0x0 }, // 2632 |
8624 | | { PseudoVFWCVT_F_XU_V_M4_MASK, VFWCVT_F_XU_V, 0x2, 0x0 }, // 2633 |
8625 | | { PseudoVFWCVT_F_XU_V_MF8, VFWCVT_F_XU_V, 0x5, 0x0 }, // 2634 |
8626 | | { PseudoVFWCVT_F_XU_V_MF8_MASK, VFWCVT_F_XU_V, 0x5, 0x0 }, // 2635 |
8627 | | { PseudoVFWCVT_F_XU_V_MF4, VFWCVT_F_XU_V, 0x6, 0x0 }, // 2636 |
8628 | | { PseudoVFWCVT_F_XU_V_MF4_MASK, VFWCVT_F_XU_V, 0x6, 0x0 }, // 2637 |
8629 | | { PseudoVFWCVT_F_XU_V_MF2, VFWCVT_F_XU_V, 0x7, 0x0 }, // 2638 |
8630 | | { PseudoVFWCVT_F_XU_V_MF2_MASK, VFWCVT_F_XU_V, 0x7, 0x0 }, // 2639 |
8631 | | { PseudoVFWCVT_F_X_V_M1, VFWCVT_F_X_V, 0x0, 0x0 }, // 2640 |
8632 | | { PseudoVFWCVT_F_X_V_M1_MASK, VFWCVT_F_X_V, 0x0, 0x0 }, // 2641 |
8633 | | { PseudoVFWCVT_F_X_V_M2, VFWCVT_F_X_V, 0x1, 0x0 }, // 2642 |
8634 | | { PseudoVFWCVT_F_X_V_M2_MASK, VFWCVT_F_X_V, 0x1, 0x0 }, // 2643 |
8635 | | { PseudoVFWCVT_F_X_V_M4, VFWCVT_F_X_V, 0x2, 0x0 }, // 2644 |
8636 | | { PseudoVFWCVT_F_X_V_M4_MASK, VFWCVT_F_X_V, 0x2, 0x0 }, // 2645 |
8637 | | { PseudoVFWCVT_F_X_V_MF8, VFWCVT_F_X_V, 0x5, 0x0 }, // 2646 |
8638 | | { PseudoVFWCVT_F_X_V_MF8_MASK, VFWCVT_F_X_V, 0x5, 0x0 }, // 2647 |
8639 | | { PseudoVFWCVT_F_X_V_MF4, VFWCVT_F_X_V, 0x6, 0x0 }, // 2648 |
8640 | | { PseudoVFWCVT_F_X_V_MF4_MASK, VFWCVT_F_X_V, 0x6, 0x0 }, // 2649 |
8641 | | { PseudoVFWCVT_F_X_V_MF2, VFWCVT_F_X_V, 0x7, 0x0 }, // 2650 |
8642 | | { PseudoVFWCVT_F_X_V_MF2_MASK, VFWCVT_F_X_V, 0x7, 0x0 }, // 2651 |
8643 | | { PseudoVFWCVT_RTZ_XU_F_V_M1, VFWCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 2652 |
8644 | | { PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, VFWCVT_RTZ_XU_F_V, 0x0, 0x0 }, // 2653 |
8645 | | { PseudoVFWCVT_RTZ_XU_F_V_M2, VFWCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 2654 |
8646 | | { PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, VFWCVT_RTZ_XU_F_V, 0x1, 0x0 }, // 2655 |
8647 | | { PseudoVFWCVT_RTZ_XU_F_V_M4, VFWCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 2656 |
8648 | | { PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, VFWCVT_RTZ_XU_F_V, 0x2, 0x0 }, // 2657 |
8649 | | { PseudoVFWCVT_RTZ_XU_F_V_MF4, VFWCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 2658 |
8650 | | { PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, VFWCVT_RTZ_XU_F_V, 0x6, 0x0 }, // 2659 |
8651 | | { PseudoVFWCVT_RTZ_XU_F_V_MF2, VFWCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 2660 |
8652 | | { PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, VFWCVT_RTZ_XU_F_V, 0x7, 0x0 }, // 2661 |
8653 | | { PseudoVFWCVT_RTZ_X_F_V_M1, VFWCVT_RTZ_X_F_V, 0x0, 0x0 }, // 2662 |
8654 | | { PseudoVFWCVT_RTZ_X_F_V_M1_MASK, VFWCVT_RTZ_X_F_V, 0x0, 0x0 }, // 2663 |
8655 | | { PseudoVFWCVT_RTZ_X_F_V_M2, VFWCVT_RTZ_X_F_V, 0x1, 0x0 }, // 2664 |
8656 | | { PseudoVFWCVT_RTZ_X_F_V_M2_MASK, VFWCVT_RTZ_X_F_V, 0x1, 0x0 }, // 2665 |
8657 | | { PseudoVFWCVT_RTZ_X_F_V_M4, VFWCVT_RTZ_X_F_V, 0x2, 0x0 }, // 2666 |
8658 | | { PseudoVFWCVT_RTZ_X_F_V_M4_MASK, VFWCVT_RTZ_X_F_V, 0x2, 0x0 }, // 2667 |
8659 | | { PseudoVFWCVT_RTZ_X_F_V_MF4, VFWCVT_RTZ_X_F_V, 0x6, 0x0 }, // 2668 |
8660 | | { PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, VFWCVT_RTZ_X_F_V, 0x6, 0x0 }, // 2669 |
8661 | | { PseudoVFWCVT_RTZ_X_F_V_MF2, VFWCVT_RTZ_X_F_V, 0x7, 0x0 }, // 2670 |
8662 | | { PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, VFWCVT_RTZ_X_F_V, 0x7, 0x0 }, // 2671 |
8663 | | { PseudoVFWCVT_RM_XU_F_V_M1, VFWCVT_XU_F_V, 0x0, 0x0 }, // 2672 |
8664 | | { PseudoVFWCVT_RM_XU_F_V_M1_MASK, VFWCVT_XU_F_V, 0x0, 0x0 }, // 2673 |
8665 | | { PseudoVFWCVT_XU_F_V_M1, VFWCVT_XU_F_V, 0x0, 0x0 }, // 2674 |
8666 | | { PseudoVFWCVT_XU_F_V_M1_MASK, VFWCVT_XU_F_V, 0x0, 0x0 }, // 2675 |
8667 | | { PseudoVFWCVT_RM_XU_F_V_M2, VFWCVT_XU_F_V, 0x1, 0x0 }, // 2676 |
8668 | | { PseudoVFWCVT_RM_XU_F_V_M2_MASK, VFWCVT_XU_F_V, 0x1, 0x0 }, // 2677 |
8669 | | { PseudoVFWCVT_XU_F_V_M2, VFWCVT_XU_F_V, 0x1, 0x0 }, // 2678 |
8670 | | { PseudoVFWCVT_XU_F_V_M2_MASK, VFWCVT_XU_F_V, 0x1, 0x0 }, // 2679 |
8671 | | { PseudoVFWCVT_RM_XU_F_V_M4, VFWCVT_XU_F_V, 0x2, 0x0 }, // 2680 |
8672 | | { PseudoVFWCVT_RM_XU_F_V_M4_MASK, VFWCVT_XU_F_V, 0x2, 0x0 }, // 2681 |
8673 | | { PseudoVFWCVT_XU_F_V_M4, VFWCVT_XU_F_V, 0x2, 0x0 }, // 2682 |
8674 | | { PseudoVFWCVT_XU_F_V_M4_MASK, VFWCVT_XU_F_V, 0x2, 0x0 }, // 2683 |
8675 | | { PseudoVFWCVT_RM_XU_F_V_MF4, VFWCVT_XU_F_V, 0x6, 0x0 }, // 2684 |
8676 | | { PseudoVFWCVT_RM_XU_F_V_MF4_MASK, VFWCVT_XU_F_V, 0x6, 0x0 }, // 2685 |
8677 | | { PseudoVFWCVT_XU_F_V_MF4, VFWCVT_XU_F_V, 0x6, 0x0 }, // 2686 |
8678 | | { PseudoVFWCVT_XU_F_V_MF4_MASK, VFWCVT_XU_F_V, 0x6, 0x0 }, // 2687 |
8679 | | { PseudoVFWCVT_RM_XU_F_V_MF2, VFWCVT_XU_F_V, 0x7, 0x0 }, // 2688 |
8680 | | { PseudoVFWCVT_RM_XU_F_V_MF2_MASK, VFWCVT_XU_F_V, 0x7, 0x0 }, // 2689 |
8681 | | { PseudoVFWCVT_XU_F_V_MF2, VFWCVT_XU_F_V, 0x7, 0x0 }, // 2690 |
8682 | | { PseudoVFWCVT_XU_F_V_MF2_MASK, VFWCVT_XU_F_V, 0x7, 0x0 }, // 2691 |
8683 | | { PseudoVFWCVT_RM_X_F_V_M1, VFWCVT_X_F_V, 0x0, 0x0 }, // 2692 |
8684 | | { PseudoVFWCVT_RM_X_F_V_M1_MASK, VFWCVT_X_F_V, 0x0, 0x0 }, // 2693 |
8685 | | { PseudoVFWCVT_X_F_V_M1, VFWCVT_X_F_V, 0x0, 0x0 }, // 2694 |
8686 | | { PseudoVFWCVT_X_F_V_M1_MASK, VFWCVT_X_F_V, 0x0, 0x0 }, // 2695 |
8687 | | { PseudoVFWCVT_RM_X_F_V_M2, VFWCVT_X_F_V, 0x1, 0x0 }, // 2696 |
8688 | | { PseudoVFWCVT_RM_X_F_V_M2_MASK, VFWCVT_X_F_V, 0x1, 0x0 }, // 2697 |
8689 | | { PseudoVFWCVT_X_F_V_M2, VFWCVT_X_F_V, 0x1, 0x0 }, // 2698 |
8690 | | { PseudoVFWCVT_X_F_V_M2_MASK, VFWCVT_X_F_V, 0x1, 0x0 }, // 2699 |
8691 | | { PseudoVFWCVT_RM_X_F_V_M4, VFWCVT_X_F_V, 0x2, 0x0 }, // 2700 |
8692 | | { PseudoVFWCVT_RM_X_F_V_M4_MASK, VFWCVT_X_F_V, 0x2, 0x0 }, // 2701 |
8693 | | { PseudoVFWCVT_X_F_V_M4, VFWCVT_X_F_V, 0x2, 0x0 }, // 2702 |
8694 | | { PseudoVFWCVT_X_F_V_M4_MASK, VFWCVT_X_F_V, 0x2, 0x0 }, // 2703 |
8695 | | { PseudoVFWCVT_RM_X_F_V_MF4, VFWCVT_X_F_V, 0x6, 0x0 }, // 2704 |
8696 | | { PseudoVFWCVT_RM_X_F_V_MF4_MASK, VFWCVT_X_F_V, 0x6, 0x0 }, // 2705 |
8697 | | { PseudoVFWCVT_X_F_V_MF4, VFWCVT_X_F_V, 0x6, 0x0 }, // 2706 |
8698 | | { PseudoVFWCVT_X_F_V_MF4_MASK, VFWCVT_X_F_V, 0x6, 0x0 }, // 2707 |
8699 | | { PseudoVFWCVT_RM_X_F_V_MF2, VFWCVT_X_F_V, 0x7, 0x0 }, // 2708 |
8700 | | { PseudoVFWCVT_RM_X_F_V_MF2_MASK, VFWCVT_X_F_V, 0x7, 0x0 }, // 2709 |
8701 | | { PseudoVFWCVT_X_F_V_MF2, VFWCVT_X_F_V, 0x7, 0x0 }, // 2710 |
8702 | | { PseudoVFWCVT_X_F_V_MF2_MASK, VFWCVT_X_F_V, 0x7, 0x0 }, // 2711 |
8703 | | { PseudoVFWMACCBF16_VFPR16_M1, VFWMACCBF16_VF, 0x0, 0x0 }, // 2712 |
8704 | | { PseudoVFWMACCBF16_VFPR16_M1_MASK, VFWMACCBF16_VF, 0x0, 0x0 }, // 2713 |
8705 | | { PseudoVFWMACCBF16_VFPR16_M2, VFWMACCBF16_VF, 0x1, 0x0 }, // 2714 |
8706 | | { PseudoVFWMACCBF16_VFPR16_M2_MASK, VFWMACCBF16_VF, 0x1, 0x0 }, // 2715 |
8707 | | { PseudoVFWMACCBF16_VFPR16_M4, VFWMACCBF16_VF, 0x2, 0x0 }, // 2716 |
8708 | | { PseudoVFWMACCBF16_VFPR16_M4_MASK, VFWMACCBF16_VF, 0x2, 0x0 }, // 2717 |
8709 | | { PseudoVFWMACCBF16_VFPR16_MF4, VFWMACCBF16_VF, 0x6, 0x0 }, // 2718 |
8710 | | { PseudoVFWMACCBF16_VFPR16_MF4_MASK, VFWMACCBF16_VF, 0x6, 0x0 }, // 2719 |
8711 | | { PseudoVFWMACCBF16_VFPR16_MF2, VFWMACCBF16_VF, 0x7, 0x0 }, // 2720 |
8712 | | { PseudoVFWMACCBF16_VFPR16_MF2_MASK, VFWMACCBF16_VF, 0x7, 0x0 }, // 2721 |
8713 | | { PseudoVFWMACCBF16_VV_M1, VFWMACCBF16_VV, 0x0, 0x0 }, // 2722 |
8714 | | { PseudoVFWMACCBF16_VV_M1_MASK, VFWMACCBF16_VV, 0x0, 0x0 }, // 2723 |
8715 | | { PseudoVFWMACCBF16_VV_M2, VFWMACCBF16_VV, 0x1, 0x0 }, // 2724 |
8716 | | { PseudoVFWMACCBF16_VV_M2_MASK, VFWMACCBF16_VV, 0x1, 0x0 }, // 2725 |
8717 | | { PseudoVFWMACCBF16_VV_M4, VFWMACCBF16_VV, 0x2, 0x0 }, // 2726 |
8718 | | { PseudoVFWMACCBF16_VV_M4_MASK, VFWMACCBF16_VV, 0x2, 0x0 }, // 2727 |
8719 | | { PseudoVFWMACCBF16_VV_MF4, VFWMACCBF16_VV, 0x6, 0x0 }, // 2728 |
8720 | | { PseudoVFWMACCBF16_VV_MF4_MASK, VFWMACCBF16_VV, 0x6, 0x0 }, // 2729 |
8721 | | { PseudoVFWMACCBF16_VV_MF2, VFWMACCBF16_VV, 0x7, 0x0 }, // 2730 |
8722 | | { PseudoVFWMACCBF16_VV_MF2_MASK, VFWMACCBF16_VV, 0x7, 0x0 }, // 2731 |
8723 | | { PseudoVFWMACC_4x4x4_M1, VFWMACC_4x4x4, 0x0, 0x0 }, // 2732 |
8724 | | { PseudoVFWMACC_4x4x4_M2, VFWMACC_4x4x4, 0x1, 0x0 }, // 2733 |
8725 | | { PseudoVFWMACC_4x4x4_M4, VFWMACC_4x4x4, 0x2, 0x0 }, // 2734 |
8726 | | { PseudoVFWMACC_4x4x4_M8, VFWMACC_4x4x4, 0x3, 0x0 }, // 2735 |
8727 | | { PseudoVFWMACC_4x4x4_MF4, VFWMACC_4x4x4, 0x6, 0x0 }, // 2736 |
8728 | | { PseudoVFWMACC_4x4x4_MF2, VFWMACC_4x4x4, 0x7, 0x0 }, // 2737 |
8729 | | { PseudoVFWMACC_VFPR16_M1, VFWMACC_VF, 0x0, 0x0 }, // 2738 |
8730 | | { PseudoVFWMACC_VFPR16_M1_MASK, VFWMACC_VF, 0x0, 0x0 }, // 2739 |
8731 | | { PseudoVFWMACC_VFPR32_M1, VFWMACC_VF, 0x0, 0x0 }, // 2740 |
8732 | | { PseudoVFWMACC_VFPR32_M1_MASK, VFWMACC_VF, 0x0, 0x0 }, // 2741 |
8733 | | { PseudoVFWMACC_VFPR16_M2, VFWMACC_VF, 0x1, 0x0 }, // 2742 |
8734 | | { PseudoVFWMACC_VFPR16_M2_MASK, VFWMACC_VF, 0x1, 0x0 }, // 2743 |
8735 | | { PseudoVFWMACC_VFPR32_M2, VFWMACC_VF, 0x1, 0x0 }, // 2744 |
8736 | | { PseudoVFWMACC_VFPR32_M2_MASK, VFWMACC_VF, 0x1, 0x0 }, // 2745 |
8737 | | { PseudoVFWMACC_VFPR16_M4, VFWMACC_VF, 0x2, 0x0 }, // 2746 |
8738 | | { PseudoVFWMACC_VFPR16_M4_MASK, VFWMACC_VF, 0x2, 0x0 }, // 2747 |
8739 | | { PseudoVFWMACC_VFPR32_M4, VFWMACC_VF, 0x2, 0x0 }, // 2748 |
8740 | | { PseudoVFWMACC_VFPR32_M4_MASK, VFWMACC_VF, 0x2, 0x0 }, // 2749 |
8741 | | { PseudoVFWMACC_VFPR16_MF4, VFWMACC_VF, 0x6, 0x0 }, // 2750 |
8742 | | { PseudoVFWMACC_VFPR16_MF4_MASK, VFWMACC_VF, 0x6, 0x0 }, // 2751 |
8743 | | { PseudoVFWMACC_VFPR16_MF2, VFWMACC_VF, 0x7, 0x0 }, // 2752 |
8744 | | { PseudoVFWMACC_VFPR16_MF2_MASK, VFWMACC_VF, 0x7, 0x0 }, // 2753 |
8745 | | { PseudoVFWMACC_VFPR32_MF2, VFWMACC_VF, 0x7, 0x0 }, // 2754 |
8746 | | { PseudoVFWMACC_VFPR32_MF2_MASK, VFWMACC_VF, 0x7, 0x0 }, // 2755 |
8747 | | { PseudoVFWMACC_VV_M1, VFWMACC_VV, 0x0, 0x0 }, // 2756 |
8748 | | { PseudoVFWMACC_VV_M1_MASK, VFWMACC_VV, 0x0, 0x0 }, // 2757 |
8749 | | { PseudoVFWMACC_VV_M2, VFWMACC_VV, 0x1, 0x0 }, // 2758 |
8750 | | { PseudoVFWMACC_VV_M2_MASK, VFWMACC_VV, 0x1, 0x0 }, // 2759 |
8751 | | { PseudoVFWMACC_VV_M4, VFWMACC_VV, 0x2, 0x0 }, // 2760 |
8752 | | { PseudoVFWMACC_VV_M4_MASK, VFWMACC_VV, 0x2, 0x0 }, // 2761 |
8753 | | { PseudoVFWMACC_VV_MF4, VFWMACC_VV, 0x6, 0x0 }, // 2762 |
8754 | | { PseudoVFWMACC_VV_MF4_MASK, VFWMACC_VV, 0x6, 0x0 }, // 2763 |
8755 | | { PseudoVFWMACC_VV_MF2, VFWMACC_VV, 0x7, 0x0 }, // 2764 |
8756 | | { PseudoVFWMACC_VV_MF2_MASK, VFWMACC_VV, 0x7, 0x0 }, // 2765 |
8757 | | { PseudoVFWMSAC_VFPR16_M1, VFWMSAC_VF, 0x0, 0x0 }, // 2766 |
8758 | | { PseudoVFWMSAC_VFPR16_M1_MASK, VFWMSAC_VF, 0x0, 0x0 }, // 2767 |
8759 | | { PseudoVFWMSAC_VFPR32_M1, VFWMSAC_VF, 0x0, 0x0 }, // 2768 |
8760 | | { PseudoVFWMSAC_VFPR32_M1_MASK, VFWMSAC_VF, 0x0, 0x0 }, // 2769 |
8761 | | { PseudoVFWMSAC_VFPR16_M2, VFWMSAC_VF, 0x1, 0x0 }, // 2770 |
8762 | | { PseudoVFWMSAC_VFPR16_M2_MASK, VFWMSAC_VF, 0x1, 0x0 }, // 2771 |
8763 | | { PseudoVFWMSAC_VFPR32_M2, VFWMSAC_VF, 0x1, 0x0 }, // 2772 |
8764 | | { PseudoVFWMSAC_VFPR32_M2_MASK, VFWMSAC_VF, 0x1, 0x0 }, // 2773 |
8765 | | { PseudoVFWMSAC_VFPR16_M4, VFWMSAC_VF, 0x2, 0x0 }, // 2774 |
8766 | | { PseudoVFWMSAC_VFPR16_M4_MASK, VFWMSAC_VF, 0x2, 0x0 }, // 2775 |
8767 | | { PseudoVFWMSAC_VFPR32_M4, VFWMSAC_VF, 0x2, 0x0 }, // 2776 |
8768 | | { PseudoVFWMSAC_VFPR32_M4_MASK, VFWMSAC_VF, 0x2, 0x0 }, // 2777 |
8769 | | { PseudoVFWMSAC_VFPR16_MF4, VFWMSAC_VF, 0x6, 0x0 }, // 2778 |
8770 | | { PseudoVFWMSAC_VFPR16_MF4_MASK, VFWMSAC_VF, 0x6, 0x0 }, // 2779 |
8771 | | { PseudoVFWMSAC_VFPR16_MF2, VFWMSAC_VF, 0x7, 0x0 }, // 2780 |
8772 | | { PseudoVFWMSAC_VFPR16_MF2_MASK, VFWMSAC_VF, 0x7, 0x0 }, // 2781 |
8773 | | { PseudoVFWMSAC_VFPR32_MF2, VFWMSAC_VF, 0x7, 0x0 }, // 2782 |
8774 | | { PseudoVFWMSAC_VFPR32_MF2_MASK, VFWMSAC_VF, 0x7, 0x0 }, // 2783 |
8775 | | { PseudoVFWMSAC_VV_M1, VFWMSAC_VV, 0x0, 0x0 }, // 2784 |
8776 | | { PseudoVFWMSAC_VV_M1_MASK, VFWMSAC_VV, 0x0, 0x0 }, // 2785 |
8777 | | { PseudoVFWMSAC_VV_M2, VFWMSAC_VV, 0x1, 0x0 }, // 2786 |
8778 | | { PseudoVFWMSAC_VV_M2_MASK, VFWMSAC_VV, 0x1, 0x0 }, // 2787 |
8779 | | { PseudoVFWMSAC_VV_M4, VFWMSAC_VV, 0x2, 0x0 }, // 2788 |
8780 | | { PseudoVFWMSAC_VV_M4_MASK, VFWMSAC_VV, 0x2, 0x0 }, // 2789 |
8781 | | { PseudoVFWMSAC_VV_MF4, VFWMSAC_VV, 0x6, 0x0 }, // 2790 |
8782 | | { PseudoVFWMSAC_VV_MF4_MASK, VFWMSAC_VV, 0x6, 0x0 }, // 2791 |
8783 | | { PseudoVFWMSAC_VV_MF2, VFWMSAC_VV, 0x7, 0x0 }, // 2792 |
8784 | | { PseudoVFWMSAC_VV_MF2_MASK, VFWMSAC_VV, 0x7, 0x0 }, // 2793 |
8785 | | { PseudoVFWMUL_VFPR16_M1, VFWMUL_VF, 0x0, 0x0 }, // 2794 |
8786 | | { PseudoVFWMUL_VFPR16_M1_MASK, VFWMUL_VF, 0x0, 0x0 }, // 2795 |
8787 | | { PseudoVFWMUL_VFPR32_M1, VFWMUL_VF, 0x0, 0x0 }, // 2796 |
8788 | | { PseudoVFWMUL_VFPR32_M1_MASK, VFWMUL_VF, 0x0, 0x0 }, // 2797 |
8789 | | { PseudoVFWMUL_VFPR16_M2, VFWMUL_VF, 0x1, 0x0 }, // 2798 |
8790 | | { PseudoVFWMUL_VFPR16_M2_MASK, VFWMUL_VF, 0x1, 0x0 }, // 2799 |
8791 | | { PseudoVFWMUL_VFPR32_M2, VFWMUL_VF, 0x1, 0x0 }, // 2800 |
8792 | | { PseudoVFWMUL_VFPR32_M2_MASK, VFWMUL_VF, 0x1, 0x0 }, // 2801 |
8793 | | { PseudoVFWMUL_VFPR16_M4, VFWMUL_VF, 0x2, 0x0 }, // 2802 |
8794 | | { PseudoVFWMUL_VFPR16_M4_MASK, VFWMUL_VF, 0x2, 0x0 }, // 2803 |
8795 | | { PseudoVFWMUL_VFPR32_M4, VFWMUL_VF, 0x2, 0x0 }, // 2804 |
8796 | | { PseudoVFWMUL_VFPR32_M4_MASK, VFWMUL_VF, 0x2, 0x0 }, // 2805 |
8797 | | { PseudoVFWMUL_VFPR16_MF4, VFWMUL_VF, 0x6, 0x0 }, // 2806 |
8798 | | { PseudoVFWMUL_VFPR16_MF4_MASK, VFWMUL_VF, 0x6, 0x0 }, // 2807 |
8799 | | { PseudoVFWMUL_VFPR16_MF2, VFWMUL_VF, 0x7, 0x0 }, // 2808 |
8800 | | { PseudoVFWMUL_VFPR16_MF2_MASK, VFWMUL_VF, 0x7, 0x0 }, // 2809 |
8801 | | { PseudoVFWMUL_VFPR32_MF2, VFWMUL_VF, 0x7, 0x0 }, // 2810 |
8802 | | { PseudoVFWMUL_VFPR32_MF2_MASK, VFWMUL_VF, 0x7, 0x0 }, // 2811 |
8803 | | { PseudoVFWMUL_VV_M1, VFWMUL_VV, 0x0, 0x0 }, // 2812 |
8804 | | { PseudoVFWMUL_VV_M1_MASK, VFWMUL_VV, 0x0, 0x0 }, // 2813 |
8805 | | { PseudoVFWMUL_VV_M2, VFWMUL_VV, 0x1, 0x0 }, // 2814 |
8806 | | { PseudoVFWMUL_VV_M2_MASK, VFWMUL_VV, 0x1, 0x0 }, // 2815 |
8807 | | { PseudoVFWMUL_VV_M4, VFWMUL_VV, 0x2, 0x0 }, // 2816 |
8808 | | { PseudoVFWMUL_VV_M4_MASK, VFWMUL_VV, 0x2, 0x0 }, // 2817 |
8809 | | { PseudoVFWMUL_VV_MF4, VFWMUL_VV, 0x6, 0x0 }, // 2818 |
8810 | | { PseudoVFWMUL_VV_MF4_MASK, VFWMUL_VV, 0x6, 0x0 }, // 2819 |
8811 | | { PseudoVFWMUL_VV_MF2, VFWMUL_VV, 0x7, 0x0 }, // 2820 |
8812 | | { PseudoVFWMUL_VV_MF2_MASK, VFWMUL_VV, 0x7, 0x0 }, // 2821 |
8813 | | { PseudoVFWNMACC_VFPR16_M1, VFWNMACC_VF, 0x0, 0x0 }, // 2822 |
8814 | | { PseudoVFWNMACC_VFPR16_M1_MASK, VFWNMACC_VF, 0x0, 0x0 }, // 2823 |
8815 | | { PseudoVFWNMACC_VFPR32_M1, VFWNMACC_VF, 0x0, 0x0 }, // 2824 |
8816 | | { PseudoVFWNMACC_VFPR32_M1_MASK, VFWNMACC_VF, 0x0, 0x0 }, // 2825 |
8817 | | { PseudoVFWNMACC_VFPR16_M2, VFWNMACC_VF, 0x1, 0x0 }, // 2826 |
8818 | | { PseudoVFWNMACC_VFPR16_M2_MASK, VFWNMACC_VF, 0x1, 0x0 }, // 2827 |
8819 | | { PseudoVFWNMACC_VFPR32_M2, VFWNMACC_VF, 0x1, 0x0 }, // 2828 |
8820 | | { PseudoVFWNMACC_VFPR32_M2_MASK, VFWNMACC_VF, 0x1, 0x0 }, // 2829 |
8821 | | { PseudoVFWNMACC_VFPR16_M4, VFWNMACC_VF, 0x2, 0x0 }, // 2830 |
8822 | | { PseudoVFWNMACC_VFPR16_M4_MASK, VFWNMACC_VF, 0x2, 0x0 }, // 2831 |
8823 | | { PseudoVFWNMACC_VFPR32_M4, VFWNMACC_VF, 0x2, 0x0 }, // 2832 |
8824 | | { PseudoVFWNMACC_VFPR32_M4_MASK, VFWNMACC_VF, 0x2, 0x0 }, // 2833 |
8825 | | { PseudoVFWNMACC_VFPR16_MF4, VFWNMACC_VF, 0x6, 0x0 }, // 2834 |
8826 | | { PseudoVFWNMACC_VFPR16_MF4_MASK, VFWNMACC_VF, 0x6, 0x0 }, // 2835 |
8827 | | { PseudoVFWNMACC_VFPR16_MF2, VFWNMACC_VF, 0x7, 0x0 }, // 2836 |
8828 | | { PseudoVFWNMACC_VFPR16_MF2_MASK, VFWNMACC_VF, 0x7, 0x0 }, // 2837 |
8829 | | { PseudoVFWNMACC_VFPR32_MF2, VFWNMACC_VF, 0x7, 0x0 }, // 2838 |
8830 | | { PseudoVFWNMACC_VFPR32_MF2_MASK, VFWNMACC_VF, 0x7, 0x0 }, // 2839 |
8831 | | { PseudoVFWNMACC_VV_M1, VFWNMACC_VV, 0x0, 0x0 }, // 2840 |
8832 | | { PseudoVFWNMACC_VV_M1_MASK, VFWNMACC_VV, 0x0, 0x0 }, // 2841 |
8833 | | { PseudoVFWNMACC_VV_M2, VFWNMACC_VV, 0x1, 0x0 }, // 2842 |
8834 | | { PseudoVFWNMACC_VV_M2_MASK, VFWNMACC_VV, 0x1, 0x0 }, // 2843 |
8835 | | { PseudoVFWNMACC_VV_M4, VFWNMACC_VV, 0x2, 0x0 }, // 2844 |
8836 | | { PseudoVFWNMACC_VV_M4_MASK, VFWNMACC_VV, 0x2, 0x0 }, // 2845 |
8837 | | { PseudoVFWNMACC_VV_MF4, VFWNMACC_VV, 0x6, 0x0 }, // 2846 |
8838 | | { PseudoVFWNMACC_VV_MF4_MASK, VFWNMACC_VV, 0x6, 0x0 }, // 2847 |
8839 | | { PseudoVFWNMACC_VV_MF2, VFWNMACC_VV, 0x7, 0x0 }, // 2848 |
8840 | | { PseudoVFWNMACC_VV_MF2_MASK, VFWNMACC_VV, 0x7, 0x0 }, // 2849 |
8841 | | { PseudoVFWNMSAC_VFPR16_M1, VFWNMSAC_VF, 0x0, 0x0 }, // 2850 |
8842 | | { PseudoVFWNMSAC_VFPR16_M1_MASK, VFWNMSAC_VF, 0x0, 0x0 }, // 2851 |
8843 | | { PseudoVFWNMSAC_VFPR32_M1, VFWNMSAC_VF, 0x0, 0x0 }, // 2852 |
8844 | | { PseudoVFWNMSAC_VFPR32_M1_MASK, VFWNMSAC_VF, 0x0, 0x0 }, // 2853 |
8845 | | { PseudoVFWNMSAC_VFPR16_M2, VFWNMSAC_VF, 0x1, 0x0 }, // 2854 |
8846 | | { PseudoVFWNMSAC_VFPR16_M2_MASK, VFWNMSAC_VF, 0x1, 0x0 }, // 2855 |
8847 | | { PseudoVFWNMSAC_VFPR32_M2, VFWNMSAC_VF, 0x1, 0x0 }, // 2856 |
8848 | | { PseudoVFWNMSAC_VFPR32_M2_MASK, VFWNMSAC_VF, 0x1, 0x0 }, // 2857 |
8849 | | { PseudoVFWNMSAC_VFPR16_M4, VFWNMSAC_VF, 0x2, 0x0 }, // 2858 |
8850 | | { PseudoVFWNMSAC_VFPR16_M4_MASK, VFWNMSAC_VF, 0x2, 0x0 }, // 2859 |
8851 | | { PseudoVFWNMSAC_VFPR32_M4, VFWNMSAC_VF, 0x2, 0x0 }, // 2860 |
8852 | | { PseudoVFWNMSAC_VFPR32_M4_MASK, VFWNMSAC_VF, 0x2, 0x0 }, // 2861 |
8853 | | { PseudoVFWNMSAC_VFPR16_MF4, VFWNMSAC_VF, 0x6, 0x0 }, // 2862 |
8854 | | { PseudoVFWNMSAC_VFPR16_MF4_MASK, VFWNMSAC_VF, 0x6, 0x0 }, // 2863 |
8855 | | { PseudoVFWNMSAC_VFPR16_MF2, VFWNMSAC_VF, 0x7, 0x0 }, // 2864 |
8856 | | { PseudoVFWNMSAC_VFPR16_MF2_MASK, VFWNMSAC_VF, 0x7, 0x0 }, // 2865 |
8857 | | { PseudoVFWNMSAC_VFPR32_MF2, VFWNMSAC_VF, 0x7, 0x0 }, // 2866 |
8858 | | { PseudoVFWNMSAC_VFPR32_MF2_MASK, VFWNMSAC_VF, 0x7, 0x0 }, // 2867 |
8859 | | { PseudoVFWNMSAC_VV_M1, VFWNMSAC_VV, 0x0, 0x0 }, // 2868 |
8860 | | { PseudoVFWNMSAC_VV_M1_MASK, VFWNMSAC_VV, 0x0, 0x0 }, // 2869 |
8861 | | { PseudoVFWNMSAC_VV_M2, VFWNMSAC_VV, 0x1, 0x0 }, // 2870 |
8862 | | { PseudoVFWNMSAC_VV_M2_MASK, VFWNMSAC_VV, 0x1, 0x0 }, // 2871 |
8863 | | { PseudoVFWNMSAC_VV_M4, VFWNMSAC_VV, 0x2, 0x0 }, // 2872 |
8864 | | { PseudoVFWNMSAC_VV_M4_MASK, VFWNMSAC_VV, 0x2, 0x0 }, // 2873 |
8865 | | { PseudoVFWNMSAC_VV_MF4, VFWNMSAC_VV, 0x6, 0x0 }, // 2874 |
8866 | | { PseudoVFWNMSAC_VV_MF4_MASK, VFWNMSAC_VV, 0x6, 0x0 }, // 2875 |
8867 | | { PseudoVFWNMSAC_VV_MF2, VFWNMSAC_VV, 0x7, 0x0 }, // 2876 |
8868 | | { PseudoVFWNMSAC_VV_MF2_MASK, VFWNMSAC_VV, 0x7, 0x0 }, // 2877 |
8869 | | { PseudoVFWREDOSUM_VS_M1_E16, VFWREDOSUM_VS, 0x0, 0x10 }, // 2878 |
8870 | | { PseudoVFWREDOSUM_VS_M1_E16_MASK, VFWREDOSUM_VS, 0x0, 0x10 }, // 2879 |
8871 | | { PseudoVFWREDOSUM_VS_M1_E32, VFWREDOSUM_VS, 0x0, 0x20 }, // 2880 |
8872 | | { PseudoVFWREDOSUM_VS_M1_E32_MASK, VFWREDOSUM_VS, 0x0, 0x20 }, // 2881 |
8873 | | { PseudoVFWREDOSUM_VS_M2_E16, VFWREDOSUM_VS, 0x1, 0x10 }, // 2882 |
8874 | | { PseudoVFWREDOSUM_VS_M2_E16_MASK, VFWREDOSUM_VS, 0x1, 0x10 }, // 2883 |
8875 | | { PseudoVFWREDOSUM_VS_M2_E32, VFWREDOSUM_VS, 0x1, 0x20 }, // 2884 |
8876 | | { PseudoVFWREDOSUM_VS_M2_E32_MASK, VFWREDOSUM_VS, 0x1, 0x20 }, // 2885 |
8877 | | { PseudoVFWREDOSUM_VS_M4_E16, VFWREDOSUM_VS, 0x2, 0x10 }, // 2886 |
8878 | | { PseudoVFWREDOSUM_VS_M4_E16_MASK, VFWREDOSUM_VS, 0x2, 0x10 }, // 2887 |
8879 | | { PseudoVFWREDOSUM_VS_M4_E32, VFWREDOSUM_VS, 0x2, 0x20 }, // 2888 |
8880 | | { PseudoVFWREDOSUM_VS_M4_E32_MASK, VFWREDOSUM_VS, 0x2, 0x20 }, // 2889 |
8881 | | { PseudoVFWREDOSUM_VS_M8_E16, VFWREDOSUM_VS, 0x3, 0x10 }, // 2890 |
8882 | | { PseudoVFWREDOSUM_VS_M8_E16_MASK, VFWREDOSUM_VS, 0x3, 0x10 }, // 2891 |
8883 | | { PseudoVFWREDOSUM_VS_M8_E32, VFWREDOSUM_VS, 0x3, 0x20 }, // 2892 |
8884 | | { PseudoVFWREDOSUM_VS_M8_E32_MASK, VFWREDOSUM_VS, 0x3, 0x20 }, // 2893 |
8885 | | { PseudoVFWREDOSUM_VS_MF4_E16, VFWREDOSUM_VS, 0x6, 0x10 }, // 2894 |
8886 | | { PseudoVFWREDOSUM_VS_MF4_E16_MASK, VFWREDOSUM_VS, 0x6, 0x10 }, // 2895 |
8887 | | { PseudoVFWREDOSUM_VS_MF2_E16, VFWREDOSUM_VS, 0x7, 0x10 }, // 2896 |
8888 | | { PseudoVFWREDOSUM_VS_MF2_E16_MASK, VFWREDOSUM_VS, 0x7, 0x10 }, // 2897 |
8889 | | { PseudoVFWREDOSUM_VS_MF2_E32, VFWREDOSUM_VS, 0x7, 0x20 }, // 2898 |
8890 | | { PseudoVFWREDOSUM_VS_MF2_E32_MASK, VFWREDOSUM_VS, 0x7, 0x20 }, // 2899 |
8891 | | { PseudoVFWREDUSUM_VS_M1_E16, VFWREDUSUM_VS, 0x0, 0x10 }, // 2900 |
8892 | | { PseudoVFWREDUSUM_VS_M1_E16_MASK, VFWREDUSUM_VS, 0x0, 0x10 }, // 2901 |
8893 | | { PseudoVFWREDUSUM_VS_M1_E32, VFWREDUSUM_VS, 0x0, 0x20 }, // 2902 |
8894 | | { PseudoVFWREDUSUM_VS_M1_E32_MASK, VFWREDUSUM_VS, 0x0, 0x20 }, // 2903 |
8895 | | { PseudoVFWREDUSUM_VS_M2_E16, VFWREDUSUM_VS, 0x1, 0x10 }, // 2904 |
8896 | | { PseudoVFWREDUSUM_VS_M2_E16_MASK, VFWREDUSUM_VS, 0x1, 0x10 }, // 2905 |
8897 | | { PseudoVFWREDUSUM_VS_M2_E32, VFWREDUSUM_VS, 0x1, 0x20 }, // 2906 |
8898 | | { PseudoVFWREDUSUM_VS_M2_E32_MASK, VFWREDUSUM_VS, 0x1, 0x20 }, // 2907 |
8899 | | { PseudoVFWREDUSUM_VS_M4_E16, VFWREDUSUM_VS, 0x2, 0x10 }, // 2908 |
8900 | | { PseudoVFWREDUSUM_VS_M4_E16_MASK, VFWREDUSUM_VS, 0x2, 0x10 }, // 2909 |
8901 | | { PseudoVFWREDUSUM_VS_M4_E32, VFWREDUSUM_VS, 0x2, 0x20 }, // 2910 |
8902 | | { PseudoVFWREDUSUM_VS_M4_E32_MASK, VFWREDUSUM_VS, 0x2, 0x20 }, // 2911 |
8903 | | { PseudoVFWREDUSUM_VS_M8_E16, VFWREDUSUM_VS, 0x3, 0x10 }, // 2912 |
8904 | | { PseudoVFWREDUSUM_VS_M8_E16_MASK, VFWREDUSUM_VS, 0x3, 0x10 }, // 2913 |
8905 | | { PseudoVFWREDUSUM_VS_M8_E32, VFWREDUSUM_VS, 0x3, 0x20 }, // 2914 |
8906 | | { PseudoVFWREDUSUM_VS_M8_E32_MASK, VFWREDUSUM_VS, 0x3, 0x20 }, // 2915 |
8907 | | { PseudoVFWREDUSUM_VS_MF4_E16, VFWREDUSUM_VS, 0x6, 0x10 }, // 2916 |
8908 | | { PseudoVFWREDUSUM_VS_MF4_E16_MASK, VFWREDUSUM_VS, 0x6, 0x10 }, // 2917 |
8909 | | { PseudoVFWREDUSUM_VS_MF2_E16, VFWREDUSUM_VS, 0x7, 0x10 }, // 2918 |
8910 | | { PseudoVFWREDUSUM_VS_MF2_E16_MASK, VFWREDUSUM_VS, 0x7, 0x10 }, // 2919 |
8911 | | { PseudoVFWREDUSUM_VS_MF2_E32, VFWREDUSUM_VS, 0x7, 0x20 }, // 2920 |
8912 | | { PseudoVFWREDUSUM_VS_MF2_E32_MASK, VFWREDUSUM_VS, 0x7, 0x20 }, // 2921 |
8913 | | { PseudoVFWSUB_VFPR16_M1, VFWSUB_VF, 0x0, 0x0 }, // 2922 |
8914 | | { PseudoVFWSUB_VFPR16_M1_MASK, VFWSUB_VF, 0x0, 0x0 }, // 2923 |
8915 | | { PseudoVFWSUB_VFPR32_M1, VFWSUB_VF, 0x0, 0x0 }, // 2924 |
8916 | | { PseudoVFWSUB_VFPR32_M1_MASK, VFWSUB_VF, 0x0, 0x0 }, // 2925 |
8917 | | { PseudoVFWSUB_VFPR16_M2, VFWSUB_VF, 0x1, 0x0 }, // 2926 |
8918 | | { PseudoVFWSUB_VFPR16_M2_MASK, VFWSUB_VF, 0x1, 0x0 }, // 2927 |
8919 | | { PseudoVFWSUB_VFPR32_M2, VFWSUB_VF, 0x1, 0x0 }, // 2928 |
8920 | | { PseudoVFWSUB_VFPR32_M2_MASK, VFWSUB_VF, 0x1, 0x0 }, // 2929 |
8921 | | { PseudoVFWSUB_VFPR16_M4, VFWSUB_VF, 0x2, 0x0 }, // 2930 |
8922 | | { PseudoVFWSUB_VFPR16_M4_MASK, VFWSUB_VF, 0x2, 0x0 }, // 2931 |
8923 | | { PseudoVFWSUB_VFPR32_M4, VFWSUB_VF, 0x2, 0x0 }, // 2932 |
8924 | | { PseudoVFWSUB_VFPR32_M4_MASK, VFWSUB_VF, 0x2, 0x0 }, // 2933 |
8925 | | { PseudoVFWSUB_VFPR16_MF4, VFWSUB_VF, 0x6, 0x0 }, // 2934 |
8926 | | { PseudoVFWSUB_VFPR16_MF4_MASK, VFWSUB_VF, 0x6, 0x0 }, // 2935 |
8927 | | { PseudoVFWSUB_VFPR16_MF2, VFWSUB_VF, 0x7, 0x0 }, // 2936 |
8928 | | { PseudoVFWSUB_VFPR16_MF2_MASK, VFWSUB_VF, 0x7, 0x0 }, // 2937 |
8929 | | { PseudoVFWSUB_VFPR32_MF2, VFWSUB_VF, 0x7, 0x0 }, // 2938 |
8930 | | { PseudoVFWSUB_VFPR32_MF2_MASK, VFWSUB_VF, 0x7, 0x0 }, // 2939 |
8931 | | { PseudoVFWSUB_VV_M1, VFWSUB_VV, 0x0, 0x0 }, // 2940 |
8932 | | { PseudoVFWSUB_VV_M1_MASK, VFWSUB_VV, 0x0, 0x0 }, // 2941 |
8933 | | { PseudoVFWSUB_VV_M2, VFWSUB_VV, 0x1, 0x0 }, // 2942 |
8934 | | { PseudoVFWSUB_VV_M2_MASK, VFWSUB_VV, 0x1, 0x0 }, // 2943 |
8935 | | { PseudoVFWSUB_VV_M4, VFWSUB_VV, 0x2, 0x0 }, // 2944 |
8936 | | { PseudoVFWSUB_VV_M4_MASK, VFWSUB_VV, 0x2, 0x0 }, // 2945 |
8937 | | { PseudoVFWSUB_VV_MF4, VFWSUB_VV, 0x6, 0x0 }, // 2946 |
8938 | | { PseudoVFWSUB_VV_MF4_MASK, VFWSUB_VV, 0x6, 0x0 }, // 2947 |
8939 | | { PseudoVFWSUB_VV_MF2, VFWSUB_VV, 0x7, 0x0 }, // 2948 |
8940 | | { PseudoVFWSUB_VV_MF2_MASK, VFWSUB_VV, 0x7, 0x0 }, // 2949 |
8941 | | { PseudoVFWSUB_WFPR16_M1, VFWSUB_WF, 0x0, 0x0 }, // 2950 |
8942 | | { PseudoVFWSUB_WFPR16_M1_MASK, VFWSUB_WF, 0x0, 0x0 }, // 2951 |
8943 | | { PseudoVFWSUB_WFPR32_M1, VFWSUB_WF, 0x0, 0x0 }, // 2952 |
8944 | | { PseudoVFWSUB_WFPR32_M1_MASK, VFWSUB_WF, 0x0, 0x0 }, // 2953 |
8945 | | { PseudoVFWSUB_WFPR16_M2, VFWSUB_WF, 0x1, 0x0 }, // 2954 |
8946 | | { PseudoVFWSUB_WFPR16_M2_MASK, VFWSUB_WF, 0x1, 0x0 }, // 2955 |
8947 | | { PseudoVFWSUB_WFPR32_M2, VFWSUB_WF, 0x1, 0x0 }, // 2956 |
8948 | | { PseudoVFWSUB_WFPR32_M2_MASK, VFWSUB_WF, 0x1, 0x0 }, // 2957 |
8949 | | { PseudoVFWSUB_WFPR16_M4, VFWSUB_WF, 0x2, 0x0 }, // 2958 |
8950 | | { PseudoVFWSUB_WFPR16_M4_MASK, VFWSUB_WF, 0x2, 0x0 }, // 2959 |
8951 | | { PseudoVFWSUB_WFPR32_M4, VFWSUB_WF, 0x2, 0x0 }, // 2960 |
8952 | | { PseudoVFWSUB_WFPR32_M4_MASK, VFWSUB_WF, 0x2, 0x0 }, // 2961 |
8953 | | { PseudoVFWSUB_WFPR16_MF4, VFWSUB_WF, 0x6, 0x0 }, // 2962 |
8954 | | { PseudoVFWSUB_WFPR16_MF4_MASK, VFWSUB_WF, 0x6, 0x0 }, // 2963 |
8955 | | { PseudoVFWSUB_WFPR16_MF2, VFWSUB_WF, 0x7, 0x0 }, // 2964 |
8956 | | { PseudoVFWSUB_WFPR16_MF2_MASK, VFWSUB_WF, 0x7, 0x0 }, // 2965 |
8957 | | { PseudoVFWSUB_WFPR32_MF2, VFWSUB_WF, 0x7, 0x0 }, // 2966 |
8958 | | { PseudoVFWSUB_WFPR32_MF2_MASK, VFWSUB_WF, 0x7, 0x0 }, // 2967 |
8959 | | { PseudoVFWSUB_WV_M1, VFWSUB_WV, 0x0, 0x0 }, // 2968 |
8960 | | { PseudoVFWSUB_WV_M1_MASK, VFWSUB_WV, 0x0, 0x0 }, // 2969 |
8961 | | { PseudoVFWSUB_WV_M1_MASK_TIED, VFWSUB_WV, 0x0, 0x0 }, // 2970 |
8962 | | { PseudoVFWSUB_WV_M1_TIED, VFWSUB_WV, 0x0, 0x0 }, // 2971 |
8963 | | { PseudoVFWSUB_WV_M2, VFWSUB_WV, 0x1, 0x0 }, // 2972 |
8964 | | { PseudoVFWSUB_WV_M2_MASK, VFWSUB_WV, 0x1, 0x0 }, // 2973 |
8965 | | { PseudoVFWSUB_WV_M2_MASK_TIED, VFWSUB_WV, 0x1, 0x0 }, // 2974 |
8966 | | { PseudoVFWSUB_WV_M2_TIED, VFWSUB_WV, 0x1, 0x0 }, // 2975 |
8967 | | { PseudoVFWSUB_WV_M4, VFWSUB_WV, 0x2, 0x0 }, // 2976 |
8968 | | { PseudoVFWSUB_WV_M4_MASK, VFWSUB_WV, 0x2, 0x0 }, // 2977 |
8969 | | { PseudoVFWSUB_WV_M4_MASK_TIED, VFWSUB_WV, 0x2, 0x0 }, // 2978 |
8970 | | { PseudoVFWSUB_WV_M4_TIED, VFWSUB_WV, 0x2, 0x0 }, // 2979 |
8971 | | { PseudoVFWSUB_WV_MF4, VFWSUB_WV, 0x6, 0x0 }, // 2980 |
8972 | | { PseudoVFWSUB_WV_MF4_MASK, VFWSUB_WV, 0x6, 0x0 }, // 2981 |
8973 | | { PseudoVFWSUB_WV_MF4_MASK_TIED, VFWSUB_WV, 0x6, 0x0 }, // 2982 |
8974 | | { PseudoVFWSUB_WV_MF4_TIED, VFWSUB_WV, 0x6, 0x0 }, // 2983 |
8975 | | { PseudoVFWSUB_WV_MF2, VFWSUB_WV, 0x7, 0x0 }, // 2984 |
8976 | | { PseudoVFWSUB_WV_MF2_MASK, VFWSUB_WV, 0x7, 0x0 }, // 2985 |
8977 | | { PseudoVFWSUB_WV_MF2_MASK_TIED, VFWSUB_WV, 0x7, 0x0 }, // 2986 |
8978 | | { PseudoVFWSUB_WV_MF2_TIED, VFWSUB_WV, 0x7, 0x0 }, // 2987 |
8979 | | { PseudoVGHSH_VV_M1, VGHSH_VV, 0x0, 0x0 }, // 2988 |
8980 | | { PseudoVGHSH_VV_M2, VGHSH_VV, 0x1, 0x0 }, // 2989 |
8981 | | { PseudoVGHSH_VV_M4, VGHSH_VV, 0x2, 0x0 }, // 2990 |
8982 | | { PseudoVGHSH_VV_M8, VGHSH_VV, 0x3, 0x0 }, // 2991 |
8983 | | { PseudoVGHSH_VV_MF2, VGHSH_VV, 0x7, 0x0 }, // 2992 |
8984 | | { PseudoVGMUL_VV_M1, VGMUL_VV, 0x0, 0x0 }, // 2993 |
8985 | | { PseudoVGMUL_VV_M2, VGMUL_VV, 0x1, 0x0 }, // 2994 |
8986 | | { PseudoVGMUL_VV_M4, VGMUL_VV, 0x2, 0x0 }, // 2995 |
8987 | | { PseudoVGMUL_VV_M8, VGMUL_VV, 0x3, 0x0 }, // 2996 |
8988 | | { PseudoVGMUL_VV_MF2, VGMUL_VV, 0x7, 0x0 }, // 2997 |
8989 | | { PseudoVID_V_M1, VID_V, 0x0, 0x0 }, // 2998 |
8990 | | { PseudoVID_V_M1_MASK, VID_V, 0x0, 0x0 }, // 2999 |
8991 | | { PseudoVID_V_M2, VID_V, 0x1, 0x0 }, // 3000 |
8992 | | { PseudoVID_V_M2_MASK, VID_V, 0x1, 0x0 }, // 3001 |
8993 | | { PseudoVID_V_M4, VID_V, 0x2, 0x0 }, // 3002 |
8994 | | { PseudoVID_V_M4_MASK, VID_V, 0x2, 0x0 }, // 3003 |
8995 | | { PseudoVID_V_M8, VID_V, 0x3, 0x0 }, // 3004 |
8996 | | { PseudoVID_V_M8_MASK, VID_V, 0x3, 0x0 }, // 3005 |
8997 | | { PseudoVID_V_MF8, VID_V, 0x5, 0x0 }, // 3006 |
8998 | | { PseudoVID_V_MF8_MASK, VID_V, 0x5, 0x0 }, // 3007 |
8999 | | { PseudoVID_V_MF4, VID_V, 0x6, 0x0 }, // 3008 |
9000 | | { PseudoVID_V_MF4_MASK, VID_V, 0x6, 0x0 }, // 3009 |
9001 | | { PseudoVID_V_MF2, VID_V, 0x7, 0x0 }, // 3010 |
9002 | | { PseudoVID_V_MF2_MASK, VID_V, 0x7, 0x0 }, // 3011 |
9003 | | { PseudoVIOTA_M_M1, VIOTA_M, 0x0, 0x0 }, // 3012 |
9004 | | { PseudoVIOTA_M_M1_MASK, VIOTA_M, 0x0, 0x0 }, // 3013 |
9005 | | { PseudoVIOTA_M_M2, VIOTA_M, 0x1, 0x0 }, // 3014 |
9006 | | { PseudoVIOTA_M_M2_MASK, VIOTA_M, 0x1, 0x0 }, // 3015 |
9007 | | { PseudoVIOTA_M_M4, VIOTA_M, 0x2, 0x0 }, // 3016 |
9008 | | { PseudoVIOTA_M_M4_MASK, VIOTA_M, 0x2, 0x0 }, // 3017 |
9009 | | { PseudoVIOTA_M_M8, VIOTA_M, 0x3, 0x0 }, // 3018 |
9010 | | { PseudoVIOTA_M_M8_MASK, VIOTA_M, 0x3, 0x0 }, // 3019 |
9011 | | { PseudoVIOTA_M_MF8, VIOTA_M, 0x5, 0x0 }, // 3020 |
9012 | | { PseudoVIOTA_M_MF8_MASK, VIOTA_M, 0x5, 0x0 }, // 3021 |
9013 | | { PseudoVIOTA_M_MF4, VIOTA_M, 0x6, 0x0 }, // 3022 |
9014 | | { PseudoVIOTA_M_MF4_MASK, VIOTA_M, 0x6, 0x0 }, // 3023 |
9015 | | { PseudoVIOTA_M_MF2, VIOTA_M, 0x7, 0x0 }, // 3024 |
9016 | | { PseudoVIOTA_M_MF2_MASK, VIOTA_M, 0x7, 0x0 }, // 3025 |
9017 | | { PseudoVLE16FF_V_M1, VLE16FF_V, 0x0, 0x10 }, // 3026 |
9018 | | { PseudoVLE16FF_V_M1_MASK, VLE16FF_V, 0x0, 0x10 }, // 3027 |
9019 | | { PseudoVLE16FF_V_M2, VLE16FF_V, 0x1, 0x10 }, // 3028 |
9020 | | { PseudoVLE16FF_V_M2_MASK, VLE16FF_V, 0x1, 0x10 }, // 3029 |
9021 | | { PseudoVLE16FF_V_M4, VLE16FF_V, 0x2, 0x10 }, // 3030 |
9022 | | { PseudoVLE16FF_V_M4_MASK, VLE16FF_V, 0x2, 0x10 }, // 3031 |
9023 | | { PseudoVLE16FF_V_M8, VLE16FF_V, 0x3, 0x10 }, // 3032 |
9024 | | { PseudoVLE16FF_V_M8_MASK, VLE16FF_V, 0x3, 0x10 }, // 3033 |
9025 | | { PseudoVLE16FF_V_MF4, VLE16FF_V, 0x6, 0x10 }, // 3034 |
9026 | | { PseudoVLE16FF_V_MF4_MASK, VLE16FF_V, 0x6, 0x10 }, // 3035 |
9027 | | { PseudoVLE16FF_V_MF2, VLE16FF_V, 0x7, 0x10 }, // 3036 |
9028 | | { PseudoVLE16FF_V_MF2_MASK, VLE16FF_V, 0x7, 0x10 }, // 3037 |
9029 | | { PseudoVLE16_V_M1, VLE16_V, 0x0, 0x10 }, // 3038 |
9030 | | { PseudoVLE16_V_M1_MASK, VLE16_V, 0x0, 0x10 }, // 3039 |
9031 | | { PseudoVLE16_V_M2, VLE16_V, 0x1, 0x10 }, // 3040 |
9032 | | { PseudoVLE16_V_M2_MASK, VLE16_V, 0x1, 0x10 }, // 3041 |
9033 | | { PseudoVLE16_V_M4, VLE16_V, 0x2, 0x10 }, // 3042 |
9034 | | { PseudoVLE16_V_M4_MASK, VLE16_V, 0x2, 0x10 }, // 3043 |
9035 | | { PseudoVLE16_V_M8, VLE16_V, 0x3, 0x10 }, // 3044 |
9036 | | { PseudoVLE16_V_M8_MASK, VLE16_V, 0x3, 0x10 }, // 3045 |
9037 | | { PseudoVLE16_V_MF4, VLE16_V, 0x6, 0x10 }, // 3046 |
9038 | | { PseudoVLE16_V_MF4_MASK, VLE16_V, 0x6, 0x10 }, // 3047 |
9039 | | { PseudoVLE16_V_MF2, VLE16_V, 0x7, 0x10 }, // 3048 |
9040 | | { PseudoVLE16_V_MF2_MASK, VLE16_V, 0x7, 0x10 }, // 3049 |
9041 | | { PseudoVLE32FF_V_M1, VLE32FF_V, 0x0, 0x20 }, // 3050 |
9042 | | { PseudoVLE32FF_V_M1_MASK, VLE32FF_V, 0x0, 0x20 }, // 3051 |
9043 | | { PseudoVLE32FF_V_M2, VLE32FF_V, 0x1, 0x20 }, // 3052 |
9044 | | { PseudoVLE32FF_V_M2_MASK, VLE32FF_V, 0x1, 0x20 }, // 3053 |
9045 | | { PseudoVLE32FF_V_M4, VLE32FF_V, 0x2, 0x20 }, // 3054 |
9046 | | { PseudoVLE32FF_V_M4_MASK, VLE32FF_V, 0x2, 0x20 }, // 3055 |
9047 | | { PseudoVLE32FF_V_M8, VLE32FF_V, 0x3, 0x20 }, // 3056 |
9048 | | { PseudoVLE32FF_V_M8_MASK, VLE32FF_V, 0x3, 0x20 }, // 3057 |
9049 | | { PseudoVLE32FF_V_MF2, VLE32FF_V, 0x7, 0x20 }, // 3058 |
9050 | | { PseudoVLE32FF_V_MF2_MASK, VLE32FF_V, 0x7, 0x20 }, // 3059 |
9051 | | { PseudoVLE32_V_M1, VLE32_V, 0x0, 0x20 }, // 3060 |
9052 | | { PseudoVLE32_V_M1_MASK, VLE32_V, 0x0, 0x20 }, // 3061 |
9053 | | { PseudoVLE32_V_M2, VLE32_V, 0x1, 0x20 }, // 3062 |
9054 | | { PseudoVLE32_V_M2_MASK, VLE32_V, 0x1, 0x20 }, // 3063 |
9055 | | { PseudoVLE32_V_M4, VLE32_V, 0x2, 0x20 }, // 3064 |
9056 | | { PseudoVLE32_V_M4_MASK, VLE32_V, 0x2, 0x20 }, // 3065 |
9057 | | { PseudoVLE32_V_M8, VLE32_V, 0x3, 0x20 }, // 3066 |
9058 | | { PseudoVLE32_V_M8_MASK, VLE32_V, 0x3, 0x20 }, // 3067 |
9059 | | { PseudoVLE32_V_MF2, VLE32_V, 0x7, 0x20 }, // 3068 |
9060 | | { PseudoVLE32_V_MF2_MASK, VLE32_V, 0x7, 0x20 }, // 3069 |
9061 | | { PseudoVLE64FF_V_M1, VLE64FF_V, 0x0, 0x40 }, // 3070 |
9062 | | { PseudoVLE64FF_V_M1_MASK, VLE64FF_V, 0x0, 0x40 }, // 3071 |
9063 | | { PseudoVLE64FF_V_M2, VLE64FF_V, 0x1, 0x40 }, // 3072 |
9064 | | { PseudoVLE64FF_V_M2_MASK, VLE64FF_V, 0x1, 0x40 }, // 3073 |
9065 | | { PseudoVLE64FF_V_M4, VLE64FF_V, 0x2, 0x40 }, // 3074 |
9066 | | { PseudoVLE64FF_V_M4_MASK, VLE64FF_V, 0x2, 0x40 }, // 3075 |
9067 | | { PseudoVLE64FF_V_M8, VLE64FF_V, 0x3, 0x40 }, // 3076 |
9068 | | { PseudoVLE64FF_V_M8_MASK, VLE64FF_V, 0x3, 0x40 }, // 3077 |
9069 | | { PseudoVLE64_V_M1, VLE64_V, 0x0, 0x40 }, // 3078 |
9070 | | { PseudoVLE64_V_M1_MASK, VLE64_V, 0x0, 0x40 }, // 3079 |
9071 | | { PseudoVLE64_V_M2, VLE64_V, 0x1, 0x40 }, // 3080 |
9072 | | { PseudoVLE64_V_M2_MASK, VLE64_V, 0x1, 0x40 }, // 3081 |
9073 | | { PseudoVLE64_V_M4, VLE64_V, 0x2, 0x40 }, // 3082 |
9074 | | { PseudoVLE64_V_M4_MASK, VLE64_V, 0x2, 0x40 }, // 3083 |
9075 | | { PseudoVLE64_V_M8, VLE64_V, 0x3, 0x40 }, // 3084 |
9076 | | { PseudoVLE64_V_M8_MASK, VLE64_V, 0x3, 0x40 }, // 3085 |
9077 | | { PseudoVLE8FF_V_M1, VLE8FF_V, 0x0, 0x8 }, // 3086 |
9078 | | { PseudoVLE8FF_V_M1_MASK, VLE8FF_V, 0x0, 0x8 }, // 3087 |
9079 | | { PseudoVLE8FF_V_M2, VLE8FF_V, 0x1, 0x8 }, // 3088 |
9080 | | { PseudoVLE8FF_V_M2_MASK, VLE8FF_V, 0x1, 0x8 }, // 3089 |
9081 | | { PseudoVLE8FF_V_M4, VLE8FF_V, 0x2, 0x8 }, // 3090 |
9082 | | { PseudoVLE8FF_V_M4_MASK, VLE8FF_V, 0x2, 0x8 }, // 3091 |
9083 | | { PseudoVLE8FF_V_M8, VLE8FF_V, 0x3, 0x8 }, // 3092 |
9084 | | { PseudoVLE8FF_V_M8_MASK, VLE8FF_V, 0x3, 0x8 }, // 3093 |
9085 | | { PseudoVLE8FF_V_MF8, VLE8FF_V, 0x5, 0x8 }, // 3094 |
9086 | | { PseudoVLE8FF_V_MF8_MASK, VLE8FF_V, 0x5, 0x8 }, // 3095 |
9087 | | { PseudoVLE8FF_V_MF4, VLE8FF_V, 0x6, 0x8 }, // 3096 |
9088 | | { PseudoVLE8FF_V_MF4_MASK, VLE8FF_V, 0x6, 0x8 }, // 3097 |
9089 | | { PseudoVLE8FF_V_MF2, VLE8FF_V, 0x7, 0x8 }, // 3098 |
9090 | | { PseudoVLE8FF_V_MF2_MASK, VLE8FF_V, 0x7, 0x8 }, // 3099 |
9091 | | { PseudoVLE8_V_M1, VLE8_V, 0x0, 0x8 }, // 3100 |
9092 | | { PseudoVLE8_V_M1_MASK, VLE8_V, 0x0, 0x8 }, // 3101 |
9093 | | { PseudoVLE8_V_M2, VLE8_V, 0x1, 0x8 }, // 3102 |
9094 | | { PseudoVLE8_V_M2_MASK, VLE8_V, 0x1, 0x8 }, // 3103 |
9095 | | { PseudoVLE8_V_M4, VLE8_V, 0x2, 0x8 }, // 3104 |
9096 | | { PseudoVLE8_V_M4_MASK, VLE8_V, 0x2, 0x8 }, // 3105 |
9097 | | { PseudoVLE8_V_M8, VLE8_V, 0x3, 0x8 }, // 3106 |
9098 | | { PseudoVLE8_V_M8_MASK, VLE8_V, 0x3, 0x8 }, // 3107 |
9099 | | { PseudoVLE8_V_MF8, VLE8_V, 0x5, 0x8 }, // 3108 |
9100 | | { PseudoVLE8_V_MF8_MASK, VLE8_V, 0x5, 0x8 }, // 3109 |
9101 | | { PseudoVLE8_V_MF4, VLE8_V, 0x6, 0x8 }, // 3110 |
9102 | | { PseudoVLE8_V_MF4_MASK, VLE8_V, 0x6, 0x8 }, // 3111 |
9103 | | { PseudoVLE8_V_MF2, VLE8_V, 0x7, 0x8 }, // 3112 |
9104 | | { PseudoVLE8_V_MF2_MASK, VLE8_V, 0x7, 0x8 }, // 3113 |
9105 | | { PseudoVLM_V_B8, VLM_V, 0x0, 0x0 }, // 3114 |
9106 | | { PseudoVLM_V_B16, VLM_V, 0x1, 0x0 }, // 3115 |
9107 | | { PseudoVLM_V_B32, VLM_V, 0x2, 0x0 }, // 3116 |
9108 | | { PseudoVLM_V_B64, VLM_V, 0x3, 0x0 }, // 3117 |
9109 | | { PseudoVLM_V_B1, VLM_V, 0x5, 0x0 }, // 3118 |
9110 | | { PseudoVLM_V_B2, VLM_V, 0x6, 0x0 }, // 3119 |
9111 | | { PseudoVLM_V_B4, VLM_V, 0x7, 0x0 }, // 3120 |
9112 | | { PseudoVLOXEI16_V_M1_M1, VLOXEI16_V, 0x0, 0x0 }, // 3121 |
9113 | | { PseudoVLOXEI16_V_M1_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3122 |
9114 | | { PseudoVLOXEI16_V_M2_M1, VLOXEI16_V, 0x0, 0x0 }, // 3123 |
9115 | | { PseudoVLOXEI16_V_M2_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3124 |
9116 | | { PseudoVLOXEI16_V_MF2_M1, VLOXEI16_V, 0x0, 0x0 }, // 3125 |
9117 | | { PseudoVLOXEI16_V_MF2_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3126 |
9118 | | { PseudoVLOXEI16_V_MF4_M1, VLOXEI16_V, 0x0, 0x0 }, // 3127 |
9119 | | { PseudoVLOXEI16_V_MF4_M1_MASK, VLOXEI16_V, 0x0, 0x0 }, // 3128 |
9120 | | { PseudoVLOXEI16_V_M1_M2, VLOXEI16_V, 0x1, 0x0 }, // 3129 |
9121 | | { PseudoVLOXEI16_V_M1_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3130 |
9122 | | { PseudoVLOXEI16_V_M2_M2, VLOXEI16_V, 0x1, 0x0 }, // 3131 |
9123 | | { PseudoVLOXEI16_V_M2_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3132 |
9124 | | { PseudoVLOXEI16_V_M4_M2, VLOXEI16_V, 0x1, 0x0 }, // 3133 |
9125 | | { PseudoVLOXEI16_V_M4_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3134 |
9126 | | { PseudoVLOXEI16_V_MF2_M2, VLOXEI16_V, 0x1, 0x0 }, // 3135 |
9127 | | { PseudoVLOXEI16_V_MF2_M2_MASK, VLOXEI16_V, 0x1, 0x0 }, // 3136 |
9128 | | { PseudoVLOXEI16_V_M1_M4, VLOXEI16_V, 0x2, 0x0 }, // 3137 |
9129 | | { PseudoVLOXEI16_V_M1_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3138 |
9130 | | { PseudoVLOXEI16_V_M2_M4, VLOXEI16_V, 0x2, 0x0 }, // 3139 |
9131 | | { PseudoVLOXEI16_V_M2_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3140 |
9132 | | { PseudoVLOXEI16_V_M4_M4, VLOXEI16_V, 0x2, 0x0 }, // 3141 |
9133 | | { PseudoVLOXEI16_V_M4_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3142 |
9134 | | { PseudoVLOXEI16_V_M8_M4, VLOXEI16_V, 0x2, 0x0 }, // 3143 |
9135 | | { PseudoVLOXEI16_V_M8_M4_MASK, VLOXEI16_V, 0x2, 0x0 }, // 3144 |
9136 | | { PseudoVLOXEI16_V_M2_M8, VLOXEI16_V, 0x3, 0x0 }, // 3145 |
9137 | | { PseudoVLOXEI16_V_M2_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3146 |
9138 | | { PseudoVLOXEI16_V_M4_M8, VLOXEI16_V, 0x3, 0x0 }, // 3147 |
9139 | | { PseudoVLOXEI16_V_M4_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3148 |
9140 | | { PseudoVLOXEI16_V_M8_M8, VLOXEI16_V, 0x3, 0x0 }, // 3149 |
9141 | | { PseudoVLOXEI16_V_M8_M8_MASK, VLOXEI16_V, 0x3, 0x0 }, // 3150 |
9142 | | { PseudoVLOXEI16_V_MF4_MF8, VLOXEI16_V, 0x5, 0x0 }, // 3151 |
9143 | | { PseudoVLOXEI16_V_MF4_MF8_MASK, VLOXEI16_V, 0x5, 0x0 }, // 3152 |
9144 | | { PseudoVLOXEI16_V_MF2_MF4, VLOXEI16_V, 0x6, 0x0 }, // 3153 |
9145 | | { PseudoVLOXEI16_V_MF2_MF4_MASK, VLOXEI16_V, 0x6, 0x0 }, // 3154 |
9146 | | { PseudoVLOXEI16_V_MF4_MF4, VLOXEI16_V, 0x6, 0x0 }, // 3155 |
9147 | | { PseudoVLOXEI16_V_MF4_MF4_MASK, VLOXEI16_V, 0x6, 0x0 }, // 3156 |
9148 | | { PseudoVLOXEI16_V_M1_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3157 |
9149 | | { PseudoVLOXEI16_V_M1_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3158 |
9150 | | { PseudoVLOXEI16_V_MF2_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3159 |
9151 | | { PseudoVLOXEI16_V_MF2_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3160 |
9152 | | { PseudoVLOXEI16_V_MF4_MF2, VLOXEI16_V, 0x7, 0x0 }, // 3161 |
9153 | | { PseudoVLOXEI16_V_MF4_MF2_MASK, VLOXEI16_V, 0x7, 0x0 }, // 3162 |
9154 | | { PseudoVLOXEI32_V_M1_M1, VLOXEI32_V, 0x0, 0x0 }, // 3163 |
9155 | | { PseudoVLOXEI32_V_M1_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3164 |
9156 | | { PseudoVLOXEI32_V_M2_M1, VLOXEI32_V, 0x0, 0x0 }, // 3165 |
9157 | | { PseudoVLOXEI32_V_M2_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3166 |
9158 | | { PseudoVLOXEI32_V_M4_M1, VLOXEI32_V, 0x0, 0x0 }, // 3167 |
9159 | | { PseudoVLOXEI32_V_M4_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3168 |
9160 | | { PseudoVLOXEI32_V_MF2_M1, VLOXEI32_V, 0x0, 0x0 }, // 3169 |
9161 | | { PseudoVLOXEI32_V_MF2_M1_MASK, VLOXEI32_V, 0x0, 0x0 }, // 3170 |
9162 | | { PseudoVLOXEI32_V_M1_M2, VLOXEI32_V, 0x1, 0x0 }, // 3171 |
9163 | | { PseudoVLOXEI32_V_M1_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3172 |
9164 | | { PseudoVLOXEI32_V_M2_M2, VLOXEI32_V, 0x1, 0x0 }, // 3173 |
9165 | | { PseudoVLOXEI32_V_M2_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3174 |
9166 | | { PseudoVLOXEI32_V_M4_M2, VLOXEI32_V, 0x1, 0x0 }, // 3175 |
9167 | | { PseudoVLOXEI32_V_M4_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3176 |
9168 | | { PseudoVLOXEI32_V_M8_M2, VLOXEI32_V, 0x1, 0x0 }, // 3177 |
9169 | | { PseudoVLOXEI32_V_M8_M2_MASK, VLOXEI32_V, 0x1, 0x0 }, // 3178 |
9170 | | { PseudoVLOXEI32_V_M2_M4, VLOXEI32_V, 0x2, 0x0 }, // 3179 |
9171 | | { PseudoVLOXEI32_V_M2_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3180 |
9172 | | { PseudoVLOXEI32_V_M4_M4, VLOXEI32_V, 0x2, 0x0 }, // 3181 |
9173 | | { PseudoVLOXEI32_V_M4_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3182 |
9174 | | { PseudoVLOXEI32_V_M8_M4, VLOXEI32_V, 0x2, 0x0 }, // 3183 |
9175 | | { PseudoVLOXEI32_V_M8_M4_MASK, VLOXEI32_V, 0x2, 0x0 }, // 3184 |
9176 | | { PseudoVLOXEI32_V_M4_M8, VLOXEI32_V, 0x3, 0x0 }, // 3185 |
9177 | | { PseudoVLOXEI32_V_M4_M8_MASK, VLOXEI32_V, 0x3, 0x0 }, // 3186 |
9178 | | { PseudoVLOXEI32_V_M8_M8, VLOXEI32_V, 0x3, 0x0 }, // 3187 |
9179 | | { PseudoVLOXEI32_V_M8_M8_MASK, VLOXEI32_V, 0x3, 0x0 }, // 3188 |
9180 | | { PseudoVLOXEI32_V_MF2_MF8, VLOXEI32_V, 0x5, 0x0 }, // 3189 |
9181 | | { PseudoVLOXEI32_V_MF2_MF8_MASK, VLOXEI32_V, 0x5, 0x0 }, // 3190 |
9182 | | { PseudoVLOXEI32_V_M1_MF4, VLOXEI32_V, 0x6, 0x0 }, // 3191 |
9183 | | { PseudoVLOXEI32_V_M1_MF4_MASK, VLOXEI32_V, 0x6, 0x0 }, // 3192 |
9184 | | { PseudoVLOXEI32_V_MF2_MF4, VLOXEI32_V, 0x6, 0x0 }, // 3193 |
9185 | | { PseudoVLOXEI32_V_MF2_MF4_MASK, VLOXEI32_V, 0x6, 0x0 }, // 3194 |
9186 | | { PseudoVLOXEI32_V_M1_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3195 |
9187 | | { PseudoVLOXEI32_V_M1_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3196 |
9188 | | { PseudoVLOXEI32_V_M2_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3197 |
9189 | | { PseudoVLOXEI32_V_M2_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3198 |
9190 | | { PseudoVLOXEI32_V_MF2_MF2, VLOXEI32_V, 0x7, 0x0 }, // 3199 |
9191 | | { PseudoVLOXEI32_V_MF2_MF2_MASK, VLOXEI32_V, 0x7, 0x0 }, // 3200 |
9192 | | { PseudoVLOXEI64_V_M1_M1, VLOXEI64_V, 0x0, 0x0 }, // 3201 |
9193 | | { PseudoVLOXEI64_V_M1_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3202 |
9194 | | { PseudoVLOXEI64_V_M2_M1, VLOXEI64_V, 0x0, 0x0 }, // 3203 |
9195 | | { PseudoVLOXEI64_V_M2_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3204 |
9196 | | { PseudoVLOXEI64_V_M4_M1, VLOXEI64_V, 0x0, 0x0 }, // 3205 |
9197 | | { PseudoVLOXEI64_V_M4_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3206 |
9198 | | { PseudoVLOXEI64_V_M8_M1, VLOXEI64_V, 0x0, 0x0 }, // 3207 |
9199 | | { PseudoVLOXEI64_V_M8_M1_MASK, VLOXEI64_V, 0x0, 0x0 }, // 3208 |
9200 | | { PseudoVLOXEI64_V_M2_M2, VLOXEI64_V, 0x1, 0x0 }, // 3209 |
9201 | | { PseudoVLOXEI64_V_M2_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3210 |
9202 | | { PseudoVLOXEI64_V_M4_M2, VLOXEI64_V, 0x1, 0x0 }, // 3211 |
9203 | | { PseudoVLOXEI64_V_M4_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3212 |
9204 | | { PseudoVLOXEI64_V_M8_M2, VLOXEI64_V, 0x1, 0x0 }, // 3213 |
9205 | | { PseudoVLOXEI64_V_M8_M2_MASK, VLOXEI64_V, 0x1, 0x0 }, // 3214 |
9206 | | { PseudoVLOXEI64_V_M4_M4, VLOXEI64_V, 0x2, 0x0 }, // 3215 |
9207 | | { PseudoVLOXEI64_V_M4_M4_MASK, VLOXEI64_V, 0x2, 0x0 }, // 3216 |
9208 | | { PseudoVLOXEI64_V_M8_M4, VLOXEI64_V, 0x2, 0x0 }, // 3217 |
9209 | | { PseudoVLOXEI64_V_M8_M4_MASK, VLOXEI64_V, 0x2, 0x0 }, // 3218 |
9210 | | { PseudoVLOXEI64_V_M8_M8, VLOXEI64_V, 0x3, 0x0 }, // 3219 |
9211 | | { PseudoVLOXEI64_V_M8_M8_MASK, VLOXEI64_V, 0x3, 0x0 }, // 3220 |
9212 | | { PseudoVLOXEI64_V_M1_MF8, VLOXEI64_V, 0x5, 0x0 }, // 3221 |
9213 | | { PseudoVLOXEI64_V_M1_MF8_MASK, VLOXEI64_V, 0x5, 0x0 }, // 3222 |
9214 | | { PseudoVLOXEI64_V_M1_MF4, VLOXEI64_V, 0x6, 0x0 }, // 3223 |
9215 | | { PseudoVLOXEI64_V_M1_MF4_MASK, VLOXEI64_V, 0x6, 0x0 }, // 3224 |
9216 | | { PseudoVLOXEI64_V_M2_MF4, VLOXEI64_V, 0x6, 0x0 }, // 3225 |
9217 | | { PseudoVLOXEI64_V_M2_MF4_MASK, VLOXEI64_V, 0x6, 0x0 }, // 3226 |
9218 | | { PseudoVLOXEI64_V_M1_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3227 |
9219 | | { PseudoVLOXEI64_V_M1_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3228 |
9220 | | { PseudoVLOXEI64_V_M2_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3229 |
9221 | | { PseudoVLOXEI64_V_M2_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3230 |
9222 | | { PseudoVLOXEI64_V_M4_MF2, VLOXEI64_V, 0x7, 0x0 }, // 3231 |
9223 | | { PseudoVLOXEI64_V_M4_MF2_MASK, VLOXEI64_V, 0x7, 0x0 }, // 3232 |
9224 | | { PseudoVLOXEI8_V_M1_M1, VLOXEI8_V, 0x0, 0x0 }, // 3233 |
9225 | | { PseudoVLOXEI8_V_M1_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3234 |
9226 | | { PseudoVLOXEI8_V_MF2_M1, VLOXEI8_V, 0x0, 0x0 }, // 3235 |
9227 | | { PseudoVLOXEI8_V_MF2_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3236 |
9228 | | { PseudoVLOXEI8_V_MF4_M1, VLOXEI8_V, 0x0, 0x0 }, // 3237 |
9229 | | { PseudoVLOXEI8_V_MF4_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3238 |
9230 | | { PseudoVLOXEI8_V_MF8_M1, VLOXEI8_V, 0x0, 0x0 }, // 3239 |
9231 | | { PseudoVLOXEI8_V_MF8_M1_MASK, VLOXEI8_V, 0x0, 0x0 }, // 3240 |
9232 | | { PseudoVLOXEI8_V_M1_M2, VLOXEI8_V, 0x1, 0x0 }, // 3241 |
9233 | | { PseudoVLOXEI8_V_M1_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3242 |
9234 | | { PseudoVLOXEI8_V_M2_M2, VLOXEI8_V, 0x1, 0x0 }, // 3243 |
9235 | | { PseudoVLOXEI8_V_M2_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3244 |
9236 | | { PseudoVLOXEI8_V_MF2_M2, VLOXEI8_V, 0x1, 0x0 }, // 3245 |
9237 | | { PseudoVLOXEI8_V_MF2_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3246 |
9238 | | { PseudoVLOXEI8_V_MF4_M2, VLOXEI8_V, 0x1, 0x0 }, // 3247 |
9239 | | { PseudoVLOXEI8_V_MF4_M2_MASK, VLOXEI8_V, 0x1, 0x0 }, // 3248 |
9240 | | { PseudoVLOXEI8_V_M1_M4, VLOXEI8_V, 0x2, 0x0 }, // 3249 |
9241 | | { PseudoVLOXEI8_V_M1_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3250 |
9242 | | { PseudoVLOXEI8_V_M2_M4, VLOXEI8_V, 0x2, 0x0 }, // 3251 |
9243 | | { PseudoVLOXEI8_V_M2_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3252 |
9244 | | { PseudoVLOXEI8_V_M4_M4, VLOXEI8_V, 0x2, 0x0 }, // 3253 |
9245 | | { PseudoVLOXEI8_V_M4_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3254 |
9246 | | { PseudoVLOXEI8_V_MF2_M4, VLOXEI8_V, 0x2, 0x0 }, // 3255 |
9247 | | { PseudoVLOXEI8_V_MF2_M4_MASK, VLOXEI8_V, 0x2, 0x0 }, // 3256 |
9248 | | { PseudoVLOXEI8_V_M1_M8, VLOXEI8_V, 0x3, 0x0 }, // 3257 |
9249 | | { PseudoVLOXEI8_V_M1_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3258 |
9250 | | { PseudoVLOXEI8_V_M2_M8, VLOXEI8_V, 0x3, 0x0 }, // 3259 |
9251 | | { PseudoVLOXEI8_V_M2_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3260 |
9252 | | { PseudoVLOXEI8_V_M4_M8, VLOXEI8_V, 0x3, 0x0 }, // 3261 |
9253 | | { PseudoVLOXEI8_V_M4_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3262 |
9254 | | { PseudoVLOXEI8_V_M8_M8, VLOXEI8_V, 0x3, 0x0 }, // 3263 |
9255 | | { PseudoVLOXEI8_V_M8_M8_MASK, VLOXEI8_V, 0x3, 0x0 }, // 3264 |
9256 | | { PseudoVLOXEI8_V_MF8_MF8, VLOXEI8_V, 0x5, 0x0 }, // 3265 |
9257 | | { PseudoVLOXEI8_V_MF8_MF8_MASK, VLOXEI8_V, 0x5, 0x0 }, // 3266 |
9258 | | { PseudoVLOXEI8_V_MF4_MF4, VLOXEI8_V, 0x6, 0x0 }, // 3267 |
9259 | | { PseudoVLOXEI8_V_MF4_MF4_MASK, VLOXEI8_V, 0x6, 0x0 }, // 3268 |
9260 | | { PseudoVLOXEI8_V_MF8_MF4, VLOXEI8_V, 0x6, 0x0 }, // 3269 |
9261 | | { PseudoVLOXEI8_V_MF8_MF4_MASK, VLOXEI8_V, 0x6, 0x0 }, // 3270 |
9262 | | { PseudoVLOXEI8_V_MF2_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3271 |
9263 | | { PseudoVLOXEI8_V_MF2_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3272 |
9264 | | { PseudoVLOXEI8_V_MF4_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3273 |
9265 | | { PseudoVLOXEI8_V_MF4_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3274 |
9266 | | { PseudoVLOXEI8_V_MF8_MF2, VLOXEI8_V, 0x7, 0x0 }, // 3275 |
9267 | | { PseudoVLOXEI8_V_MF8_MF2_MASK, VLOXEI8_V, 0x7, 0x0 }, // 3276 |
9268 | | { PseudoVLOXSEG2EI16_V_M1_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3277 |
9269 | | { PseudoVLOXSEG2EI16_V_M1_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3278 |
9270 | | { PseudoVLOXSEG2EI16_V_M2_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3279 |
9271 | | { PseudoVLOXSEG2EI16_V_M2_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3280 |
9272 | | { PseudoVLOXSEG2EI16_V_MF2_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3281 |
9273 | | { PseudoVLOXSEG2EI16_V_MF2_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3282 |
9274 | | { PseudoVLOXSEG2EI16_V_MF4_M1, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3283 |
9275 | | { PseudoVLOXSEG2EI16_V_MF4_M1_MASK, VLOXSEG2EI16_V, 0x0, 0x0 }, // 3284 |
9276 | | { PseudoVLOXSEG2EI16_V_M1_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3285 |
9277 | | { PseudoVLOXSEG2EI16_V_M1_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3286 |
9278 | | { PseudoVLOXSEG2EI16_V_M2_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3287 |
9279 | | { PseudoVLOXSEG2EI16_V_M2_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3288 |
9280 | | { PseudoVLOXSEG2EI16_V_M4_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3289 |
9281 | | { PseudoVLOXSEG2EI16_V_M4_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3290 |
9282 | | { PseudoVLOXSEG2EI16_V_MF2_M2, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3291 |
9283 | | { PseudoVLOXSEG2EI16_V_MF2_M2_MASK, VLOXSEG2EI16_V, 0x1, 0x0 }, // 3292 |
9284 | | { PseudoVLOXSEG2EI16_V_M1_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3293 |
9285 | | { PseudoVLOXSEG2EI16_V_M1_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3294 |
9286 | | { PseudoVLOXSEG2EI16_V_M2_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3295 |
9287 | | { PseudoVLOXSEG2EI16_V_M2_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3296 |
9288 | | { PseudoVLOXSEG2EI16_V_M4_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3297 |
9289 | | { PseudoVLOXSEG2EI16_V_M4_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3298 |
9290 | | { PseudoVLOXSEG2EI16_V_M8_M4, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3299 |
9291 | | { PseudoVLOXSEG2EI16_V_M8_M4_MASK, VLOXSEG2EI16_V, 0x2, 0x0 }, // 3300 |
9292 | | { PseudoVLOXSEG2EI16_V_MF4_MF8, VLOXSEG2EI16_V, 0x5, 0x0 }, // 3301 |
9293 | | { PseudoVLOXSEG2EI16_V_MF4_MF8_MASK, VLOXSEG2EI16_V, 0x5, 0x0 }, // 3302 |
9294 | | { PseudoVLOXSEG2EI16_V_MF2_MF4, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3303 |
9295 | | { PseudoVLOXSEG2EI16_V_MF2_MF4_MASK, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3304 |
9296 | | { PseudoVLOXSEG2EI16_V_MF4_MF4, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3305 |
9297 | | { PseudoVLOXSEG2EI16_V_MF4_MF4_MASK, VLOXSEG2EI16_V, 0x6, 0x0 }, // 3306 |
9298 | | { PseudoVLOXSEG2EI16_V_M1_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3307 |
9299 | | { PseudoVLOXSEG2EI16_V_M1_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3308 |
9300 | | { PseudoVLOXSEG2EI16_V_MF2_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3309 |
9301 | | { PseudoVLOXSEG2EI16_V_MF2_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3310 |
9302 | | { PseudoVLOXSEG2EI16_V_MF4_MF2, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3311 |
9303 | | { PseudoVLOXSEG2EI16_V_MF4_MF2_MASK, VLOXSEG2EI16_V, 0x7, 0x0 }, // 3312 |
9304 | | { PseudoVLOXSEG2EI32_V_M1_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3313 |
9305 | | { PseudoVLOXSEG2EI32_V_M1_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3314 |
9306 | | { PseudoVLOXSEG2EI32_V_M2_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3315 |
9307 | | { PseudoVLOXSEG2EI32_V_M2_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3316 |
9308 | | { PseudoVLOXSEG2EI32_V_M4_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3317 |
9309 | | { PseudoVLOXSEG2EI32_V_M4_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3318 |
9310 | | { PseudoVLOXSEG2EI32_V_MF2_M1, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3319 |
9311 | | { PseudoVLOXSEG2EI32_V_MF2_M1_MASK, VLOXSEG2EI32_V, 0x0, 0x0 }, // 3320 |
9312 | | { PseudoVLOXSEG2EI32_V_M1_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3321 |
9313 | | { PseudoVLOXSEG2EI32_V_M1_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3322 |
9314 | | { PseudoVLOXSEG2EI32_V_M2_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3323 |
9315 | | { PseudoVLOXSEG2EI32_V_M2_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3324 |
9316 | | { PseudoVLOXSEG2EI32_V_M4_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3325 |
9317 | | { PseudoVLOXSEG2EI32_V_M4_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3326 |
9318 | | { PseudoVLOXSEG2EI32_V_M8_M2, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3327 |
9319 | | { PseudoVLOXSEG2EI32_V_M8_M2_MASK, VLOXSEG2EI32_V, 0x1, 0x0 }, // 3328 |
9320 | | { PseudoVLOXSEG2EI32_V_M2_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3329 |
9321 | | { PseudoVLOXSEG2EI32_V_M2_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3330 |
9322 | | { PseudoVLOXSEG2EI32_V_M4_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3331 |
9323 | | { PseudoVLOXSEG2EI32_V_M4_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3332 |
9324 | | { PseudoVLOXSEG2EI32_V_M8_M4, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3333 |
9325 | | { PseudoVLOXSEG2EI32_V_M8_M4_MASK, VLOXSEG2EI32_V, 0x2, 0x0 }, // 3334 |
9326 | | { PseudoVLOXSEG2EI32_V_MF2_MF8, VLOXSEG2EI32_V, 0x5, 0x0 }, // 3335 |
9327 | | { PseudoVLOXSEG2EI32_V_MF2_MF8_MASK, VLOXSEG2EI32_V, 0x5, 0x0 }, // 3336 |
9328 | | { PseudoVLOXSEG2EI32_V_M1_MF4, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3337 |
9329 | | { PseudoVLOXSEG2EI32_V_M1_MF4_MASK, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3338 |
9330 | | { PseudoVLOXSEG2EI32_V_MF2_MF4, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3339 |
9331 | | { PseudoVLOXSEG2EI32_V_MF2_MF4_MASK, VLOXSEG2EI32_V, 0x6, 0x0 }, // 3340 |
9332 | | { PseudoVLOXSEG2EI32_V_M1_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3341 |
9333 | | { PseudoVLOXSEG2EI32_V_M1_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3342 |
9334 | | { PseudoVLOXSEG2EI32_V_M2_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3343 |
9335 | | { PseudoVLOXSEG2EI32_V_M2_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3344 |
9336 | | { PseudoVLOXSEG2EI32_V_MF2_MF2, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3345 |
9337 | | { PseudoVLOXSEG2EI32_V_MF2_MF2_MASK, VLOXSEG2EI32_V, 0x7, 0x0 }, // 3346 |
9338 | | { PseudoVLOXSEG2EI64_V_M1_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3347 |
9339 | | { PseudoVLOXSEG2EI64_V_M1_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3348 |
9340 | | { PseudoVLOXSEG2EI64_V_M2_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3349 |
9341 | | { PseudoVLOXSEG2EI64_V_M2_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3350 |
9342 | | { PseudoVLOXSEG2EI64_V_M4_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3351 |
9343 | | { PseudoVLOXSEG2EI64_V_M4_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3352 |
9344 | | { PseudoVLOXSEG2EI64_V_M8_M1, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3353 |
9345 | | { PseudoVLOXSEG2EI64_V_M8_M1_MASK, VLOXSEG2EI64_V, 0x0, 0x0 }, // 3354 |
9346 | | { PseudoVLOXSEG2EI64_V_M2_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3355 |
9347 | | { PseudoVLOXSEG2EI64_V_M2_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3356 |
9348 | | { PseudoVLOXSEG2EI64_V_M4_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3357 |
9349 | | { PseudoVLOXSEG2EI64_V_M4_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3358 |
9350 | | { PseudoVLOXSEG2EI64_V_M8_M2, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3359 |
9351 | | { PseudoVLOXSEG2EI64_V_M8_M2_MASK, VLOXSEG2EI64_V, 0x1, 0x0 }, // 3360 |
9352 | | { PseudoVLOXSEG2EI64_V_M4_M4, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3361 |
9353 | | { PseudoVLOXSEG2EI64_V_M4_M4_MASK, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3362 |
9354 | | { PseudoVLOXSEG2EI64_V_M8_M4, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3363 |
9355 | | { PseudoVLOXSEG2EI64_V_M8_M4_MASK, VLOXSEG2EI64_V, 0x2, 0x0 }, // 3364 |
9356 | | { PseudoVLOXSEG2EI64_V_M1_MF8, VLOXSEG2EI64_V, 0x5, 0x0 }, // 3365 |
9357 | | { PseudoVLOXSEG2EI64_V_M1_MF8_MASK, VLOXSEG2EI64_V, 0x5, 0x0 }, // 3366 |
9358 | | { PseudoVLOXSEG2EI64_V_M1_MF4, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3367 |
9359 | | { PseudoVLOXSEG2EI64_V_M1_MF4_MASK, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3368 |
9360 | | { PseudoVLOXSEG2EI64_V_M2_MF4, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3369 |
9361 | | { PseudoVLOXSEG2EI64_V_M2_MF4_MASK, VLOXSEG2EI64_V, 0x6, 0x0 }, // 3370 |
9362 | | { PseudoVLOXSEG2EI64_V_M1_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3371 |
9363 | | { PseudoVLOXSEG2EI64_V_M1_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3372 |
9364 | | { PseudoVLOXSEG2EI64_V_M2_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3373 |
9365 | | { PseudoVLOXSEG2EI64_V_M2_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3374 |
9366 | | { PseudoVLOXSEG2EI64_V_M4_MF2, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3375 |
9367 | | { PseudoVLOXSEG2EI64_V_M4_MF2_MASK, VLOXSEG2EI64_V, 0x7, 0x0 }, // 3376 |
9368 | | { PseudoVLOXSEG2EI8_V_M1_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3377 |
9369 | | { PseudoVLOXSEG2EI8_V_M1_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3378 |
9370 | | { PseudoVLOXSEG2EI8_V_MF2_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3379 |
9371 | | { PseudoVLOXSEG2EI8_V_MF2_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3380 |
9372 | | { PseudoVLOXSEG2EI8_V_MF4_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3381 |
9373 | | { PseudoVLOXSEG2EI8_V_MF4_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3382 |
9374 | | { PseudoVLOXSEG2EI8_V_MF8_M1, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3383 |
9375 | | { PseudoVLOXSEG2EI8_V_MF8_M1_MASK, VLOXSEG2EI8_V, 0x0, 0x0 }, // 3384 |
9376 | | { PseudoVLOXSEG2EI8_V_M1_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3385 |
9377 | | { PseudoVLOXSEG2EI8_V_M1_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3386 |
9378 | | { PseudoVLOXSEG2EI8_V_M2_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3387 |
9379 | | { PseudoVLOXSEG2EI8_V_M2_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3388 |
9380 | | { PseudoVLOXSEG2EI8_V_MF2_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3389 |
9381 | | { PseudoVLOXSEG2EI8_V_MF2_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3390 |
9382 | | { PseudoVLOXSEG2EI8_V_MF4_M2, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3391 |
9383 | | { PseudoVLOXSEG2EI8_V_MF4_M2_MASK, VLOXSEG2EI8_V, 0x1, 0x0 }, // 3392 |
9384 | | { PseudoVLOXSEG2EI8_V_M1_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3393 |
9385 | | { PseudoVLOXSEG2EI8_V_M1_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3394 |
9386 | | { PseudoVLOXSEG2EI8_V_M2_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3395 |
9387 | | { PseudoVLOXSEG2EI8_V_M2_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3396 |
9388 | | { PseudoVLOXSEG2EI8_V_M4_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3397 |
9389 | | { PseudoVLOXSEG2EI8_V_M4_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3398 |
9390 | | { PseudoVLOXSEG2EI8_V_MF2_M4, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3399 |
9391 | | { PseudoVLOXSEG2EI8_V_MF2_M4_MASK, VLOXSEG2EI8_V, 0x2, 0x0 }, // 3400 |
9392 | | { PseudoVLOXSEG2EI8_V_MF8_MF8, VLOXSEG2EI8_V, 0x5, 0x0 }, // 3401 |
9393 | | { PseudoVLOXSEG2EI8_V_MF8_MF8_MASK, VLOXSEG2EI8_V, 0x5, 0x0 }, // 3402 |
9394 | | { PseudoVLOXSEG2EI8_V_MF4_MF4, VLOXSEG2EI8_V, 0x6, 0x0 }, // 3403 |
9395 | | { PseudoVLOXSEG2EI8_V_MF4_MF4_MASK, VLOXSEG2EI8_V, 0x6, 0x0 }, // 3404 |
9396 | | { PseudoVLOXSEG2EI8_V_MF8_MF4, VLOXSEG2EI8_V, 0x6, 0x0 }, // 3405 |
9397 | | { PseudoVLOXSEG2EI8_V_MF8_MF4_MASK, VLOXSEG2EI8_V, 0x6, 0x0 }, // 3406 |
9398 | | { PseudoVLOXSEG2EI8_V_MF2_MF2, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3407 |
9399 | | { PseudoVLOXSEG2EI8_V_MF2_MF2_MASK, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3408 |
9400 | | { PseudoVLOXSEG2EI8_V_MF4_MF2, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3409 |
9401 | | { PseudoVLOXSEG2EI8_V_MF4_MF2_MASK, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3410 |
9402 | | { PseudoVLOXSEG2EI8_V_MF8_MF2, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3411 |
9403 | | { PseudoVLOXSEG2EI8_V_MF8_MF2_MASK, VLOXSEG2EI8_V, 0x7, 0x0 }, // 3412 |
9404 | | { PseudoVLOXSEG3EI16_V_M1_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3413 |
9405 | | { PseudoVLOXSEG3EI16_V_M1_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3414 |
9406 | | { PseudoVLOXSEG3EI16_V_M2_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3415 |
9407 | | { PseudoVLOXSEG3EI16_V_M2_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3416 |
9408 | | { PseudoVLOXSEG3EI16_V_MF2_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3417 |
9409 | | { PseudoVLOXSEG3EI16_V_MF2_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3418 |
9410 | | { PseudoVLOXSEG3EI16_V_MF4_M1, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3419 |
9411 | | { PseudoVLOXSEG3EI16_V_MF4_M1_MASK, VLOXSEG3EI16_V, 0x0, 0x0 }, // 3420 |
9412 | | { PseudoVLOXSEG3EI16_V_M1_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3421 |
9413 | | { PseudoVLOXSEG3EI16_V_M1_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3422 |
9414 | | { PseudoVLOXSEG3EI16_V_M2_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3423 |
9415 | | { PseudoVLOXSEG3EI16_V_M2_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3424 |
9416 | | { PseudoVLOXSEG3EI16_V_M4_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3425 |
9417 | | { PseudoVLOXSEG3EI16_V_M4_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3426 |
9418 | | { PseudoVLOXSEG3EI16_V_MF2_M2, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3427 |
9419 | | { PseudoVLOXSEG3EI16_V_MF2_M2_MASK, VLOXSEG3EI16_V, 0x1, 0x0 }, // 3428 |
9420 | | { PseudoVLOXSEG3EI16_V_MF4_MF8, VLOXSEG3EI16_V, 0x5, 0x0 }, // 3429 |
9421 | | { PseudoVLOXSEG3EI16_V_MF4_MF8_MASK, VLOXSEG3EI16_V, 0x5, 0x0 }, // 3430 |
9422 | | { PseudoVLOXSEG3EI16_V_MF2_MF4, VLOXSEG3EI16_V, 0x6, 0x0 }, // 3431 |
9423 | | { PseudoVLOXSEG3EI16_V_MF2_MF4_MASK, VLOXSEG3EI16_V, 0x6, 0x0 }, // 3432 |
9424 | | { PseudoVLOXSEG3EI16_V_MF4_MF4, VLOXSEG3EI16_V, 0x6, 0x0 }, // 3433 |
9425 | | { PseudoVLOXSEG3EI16_V_MF4_MF4_MASK, VLOXSEG3EI16_V, 0x6, 0x0 }, // 3434 |
9426 | | { PseudoVLOXSEG3EI16_V_M1_MF2, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3435 |
9427 | | { PseudoVLOXSEG3EI16_V_M1_MF2_MASK, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3436 |
9428 | | { PseudoVLOXSEG3EI16_V_MF2_MF2, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3437 |
9429 | | { PseudoVLOXSEG3EI16_V_MF2_MF2_MASK, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3438 |
9430 | | { PseudoVLOXSEG3EI16_V_MF4_MF2, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3439 |
9431 | | { PseudoVLOXSEG3EI16_V_MF4_MF2_MASK, VLOXSEG3EI16_V, 0x7, 0x0 }, // 3440 |
9432 | | { PseudoVLOXSEG3EI32_V_M1_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3441 |
9433 | | { PseudoVLOXSEG3EI32_V_M1_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3442 |
9434 | | { PseudoVLOXSEG3EI32_V_M2_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3443 |
9435 | | { PseudoVLOXSEG3EI32_V_M2_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3444 |
9436 | | { PseudoVLOXSEG3EI32_V_M4_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3445 |
9437 | | { PseudoVLOXSEG3EI32_V_M4_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3446 |
9438 | | { PseudoVLOXSEG3EI32_V_MF2_M1, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3447 |
9439 | | { PseudoVLOXSEG3EI32_V_MF2_M1_MASK, VLOXSEG3EI32_V, 0x0, 0x0 }, // 3448 |
9440 | | { PseudoVLOXSEG3EI32_V_M1_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3449 |
9441 | | { PseudoVLOXSEG3EI32_V_M1_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3450 |
9442 | | { PseudoVLOXSEG3EI32_V_M2_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3451 |
9443 | | { PseudoVLOXSEG3EI32_V_M2_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3452 |
9444 | | { PseudoVLOXSEG3EI32_V_M4_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3453 |
9445 | | { PseudoVLOXSEG3EI32_V_M4_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3454 |
9446 | | { PseudoVLOXSEG3EI32_V_M8_M2, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3455 |
9447 | | { PseudoVLOXSEG3EI32_V_M8_M2_MASK, VLOXSEG3EI32_V, 0x1, 0x0 }, // 3456 |
9448 | | { PseudoVLOXSEG3EI32_V_MF2_MF8, VLOXSEG3EI32_V, 0x5, 0x0 }, // 3457 |
9449 | | { PseudoVLOXSEG3EI32_V_MF2_MF8_MASK, VLOXSEG3EI32_V, 0x5, 0x0 }, // 3458 |
9450 | | { PseudoVLOXSEG3EI32_V_M1_MF4, VLOXSEG3EI32_V, 0x6, 0x0 }, // 3459 |
9451 | | { PseudoVLOXSEG3EI32_V_M1_MF4_MASK, VLOXSEG3EI32_V, 0x6, 0x0 }, // 3460 |
9452 | | { PseudoVLOXSEG3EI32_V_MF2_MF4, VLOXSEG3EI32_V, 0x6, 0x0 }, // 3461 |
9453 | | { PseudoVLOXSEG3EI32_V_MF2_MF4_MASK, VLOXSEG3EI32_V, 0x6, 0x0 }, // 3462 |
9454 | | { PseudoVLOXSEG3EI32_V_M1_MF2, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3463 |
9455 | | { PseudoVLOXSEG3EI32_V_M1_MF2_MASK, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3464 |
9456 | | { PseudoVLOXSEG3EI32_V_M2_MF2, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3465 |
9457 | | { PseudoVLOXSEG3EI32_V_M2_MF2_MASK, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3466 |
9458 | | { PseudoVLOXSEG3EI32_V_MF2_MF2, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3467 |
9459 | | { PseudoVLOXSEG3EI32_V_MF2_MF2_MASK, VLOXSEG3EI32_V, 0x7, 0x0 }, // 3468 |
9460 | | { PseudoVLOXSEG3EI64_V_M1_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3469 |
9461 | | { PseudoVLOXSEG3EI64_V_M1_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3470 |
9462 | | { PseudoVLOXSEG3EI64_V_M2_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3471 |
9463 | | { PseudoVLOXSEG3EI64_V_M2_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3472 |
9464 | | { PseudoVLOXSEG3EI64_V_M4_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3473 |
9465 | | { PseudoVLOXSEG3EI64_V_M4_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3474 |
9466 | | { PseudoVLOXSEG3EI64_V_M8_M1, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3475 |
9467 | | { PseudoVLOXSEG3EI64_V_M8_M1_MASK, VLOXSEG3EI64_V, 0x0, 0x0 }, // 3476 |
9468 | | { PseudoVLOXSEG3EI64_V_M2_M2, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3477 |
9469 | | { PseudoVLOXSEG3EI64_V_M2_M2_MASK, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3478 |
9470 | | { PseudoVLOXSEG3EI64_V_M4_M2, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3479 |
9471 | | { PseudoVLOXSEG3EI64_V_M4_M2_MASK, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3480 |
9472 | | { PseudoVLOXSEG3EI64_V_M8_M2, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3481 |
9473 | | { PseudoVLOXSEG3EI64_V_M8_M2_MASK, VLOXSEG3EI64_V, 0x1, 0x0 }, // 3482 |
9474 | | { PseudoVLOXSEG3EI64_V_M1_MF8, VLOXSEG3EI64_V, 0x5, 0x0 }, // 3483 |
9475 | | { PseudoVLOXSEG3EI64_V_M1_MF8_MASK, VLOXSEG3EI64_V, 0x5, 0x0 }, // 3484 |
9476 | | { PseudoVLOXSEG3EI64_V_M1_MF4, VLOXSEG3EI64_V, 0x6, 0x0 }, // 3485 |
9477 | | { PseudoVLOXSEG3EI64_V_M1_MF4_MASK, VLOXSEG3EI64_V, 0x6, 0x0 }, // 3486 |
9478 | | { PseudoVLOXSEG3EI64_V_M2_MF4, VLOXSEG3EI64_V, 0x6, 0x0 }, // 3487 |
9479 | | { PseudoVLOXSEG3EI64_V_M2_MF4_MASK, VLOXSEG3EI64_V, 0x6, 0x0 }, // 3488 |
9480 | | { PseudoVLOXSEG3EI64_V_M1_MF2, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3489 |
9481 | | { PseudoVLOXSEG3EI64_V_M1_MF2_MASK, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3490 |
9482 | | { PseudoVLOXSEG3EI64_V_M2_MF2, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3491 |
9483 | | { PseudoVLOXSEG3EI64_V_M2_MF2_MASK, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3492 |
9484 | | { PseudoVLOXSEG3EI64_V_M4_MF2, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3493 |
9485 | | { PseudoVLOXSEG3EI64_V_M4_MF2_MASK, VLOXSEG3EI64_V, 0x7, 0x0 }, // 3494 |
9486 | | { PseudoVLOXSEG3EI8_V_M1_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3495 |
9487 | | { PseudoVLOXSEG3EI8_V_M1_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3496 |
9488 | | { PseudoVLOXSEG3EI8_V_MF2_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3497 |
9489 | | { PseudoVLOXSEG3EI8_V_MF2_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3498 |
9490 | | { PseudoVLOXSEG3EI8_V_MF4_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3499 |
9491 | | { PseudoVLOXSEG3EI8_V_MF4_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3500 |
9492 | | { PseudoVLOXSEG3EI8_V_MF8_M1, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3501 |
9493 | | { PseudoVLOXSEG3EI8_V_MF8_M1_MASK, VLOXSEG3EI8_V, 0x0, 0x0 }, // 3502 |
9494 | | { PseudoVLOXSEG3EI8_V_M1_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3503 |
9495 | | { PseudoVLOXSEG3EI8_V_M1_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3504 |
9496 | | { PseudoVLOXSEG3EI8_V_M2_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3505 |
9497 | | { PseudoVLOXSEG3EI8_V_M2_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3506 |
9498 | | { PseudoVLOXSEG3EI8_V_MF2_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3507 |
9499 | | { PseudoVLOXSEG3EI8_V_MF2_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3508 |
9500 | | { PseudoVLOXSEG3EI8_V_MF4_M2, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3509 |
9501 | | { PseudoVLOXSEG3EI8_V_MF4_M2_MASK, VLOXSEG3EI8_V, 0x1, 0x0 }, // 3510 |
9502 | | { PseudoVLOXSEG3EI8_V_MF8_MF8, VLOXSEG3EI8_V, 0x5, 0x0 }, // 3511 |
9503 | | { PseudoVLOXSEG3EI8_V_MF8_MF8_MASK, VLOXSEG3EI8_V, 0x5, 0x0 }, // 3512 |
9504 | | { PseudoVLOXSEG3EI8_V_MF4_MF4, VLOXSEG3EI8_V, 0x6, 0x0 }, // 3513 |
9505 | | { PseudoVLOXSEG3EI8_V_MF4_MF4_MASK, VLOXSEG3EI8_V, 0x6, 0x0 }, // 3514 |
9506 | | { PseudoVLOXSEG3EI8_V_MF8_MF4, VLOXSEG3EI8_V, 0x6, 0x0 }, // 3515 |
9507 | | { PseudoVLOXSEG3EI8_V_MF8_MF4_MASK, VLOXSEG3EI8_V, 0x6, 0x0 }, // 3516 |
9508 | | { PseudoVLOXSEG3EI8_V_MF2_MF2, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3517 |
9509 | | { PseudoVLOXSEG3EI8_V_MF2_MF2_MASK, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3518 |
9510 | | { PseudoVLOXSEG3EI8_V_MF4_MF2, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3519 |
9511 | | { PseudoVLOXSEG3EI8_V_MF4_MF2_MASK, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3520 |
9512 | | { PseudoVLOXSEG3EI8_V_MF8_MF2, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3521 |
9513 | | { PseudoVLOXSEG3EI8_V_MF8_MF2_MASK, VLOXSEG3EI8_V, 0x7, 0x0 }, // 3522 |
9514 | | { PseudoVLOXSEG4EI16_V_M1_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3523 |
9515 | | { PseudoVLOXSEG4EI16_V_M1_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3524 |
9516 | | { PseudoVLOXSEG4EI16_V_M2_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3525 |
9517 | | { PseudoVLOXSEG4EI16_V_M2_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3526 |
9518 | | { PseudoVLOXSEG4EI16_V_MF2_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3527 |
9519 | | { PseudoVLOXSEG4EI16_V_MF2_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3528 |
9520 | | { PseudoVLOXSEG4EI16_V_MF4_M1, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3529 |
9521 | | { PseudoVLOXSEG4EI16_V_MF4_M1_MASK, VLOXSEG4EI16_V, 0x0, 0x0 }, // 3530 |
9522 | | { PseudoVLOXSEG4EI16_V_M1_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3531 |
9523 | | { PseudoVLOXSEG4EI16_V_M1_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3532 |
9524 | | { PseudoVLOXSEG4EI16_V_M2_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3533 |
9525 | | { PseudoVLOXSEG4EI16_V_M2_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3534 |
9526 | | { PseudoVLOXSEG4EI16_V_M4_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3535 |
9527 | | { PseudoVLOXSEG4EI16_V_M4_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3536 |
9528 | | { PseudoVLOXSEG4EI16_V_MF2_M2, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3537 |
9529 | | { PseudoVLOXSEG4EI16_V_MF2_M2_MASK, VLOXSEG4EI16_V, 0x1, 0x0 }, // 3538 |
9530 | | { PseudoVLOXSEG4EI16_V_MF4_MF8, VLOXSEG4EI16_V, 0x5, 0x0 }, // 3539 |
9531 | | { PseudoVLOXSEG4EI16_V_MF4_MF8_MASK, VLOXSEG4EI16_V, 0x5, 0x0 }, // 3540 |
9532 | | { PseudoVLOXSEG4EI16_V_MF2_MF4, VLOXSEG4EI16_V, 0x6, 0x0 }, // 3541 |
9533 | | { PseudoVLOXSEG4EI16_V_MF2_MF4_MASK, VLOXSEG4EI16_V, 0x6, 0x0 }, // 3542 |
9534 | | { PseudoVLOXSEG4EI16_V_MF4_MF4, VLOXSEG4EI16_V, 0x6, 0x0 }, // 3543 |
9535 | | { PseudoVLOXSEG4EI16_V_MF4_MF4_MASK, VLOXSEG4EI16_V, 0x6, 0x0 }, // 3544 |
9536 | | { PseudoVLOXSEG4EI16_V_M1_MF2, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3545 |
9537 | | { PseudoVLOXSEG4EI16_V_M1_MF2_MASK, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3546 |
9538 | | { PseudoVLOXSEG4EI16_V_MF2_MF2, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3547 |
9539 | | { PseudoVLOXSEG4EI16_V_MF2_MF2_MASK, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3548 |
9540 | | { PseudoVLOXSEG4EI16_V_MF4_MF2, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3549 |
9541 | | { PseudoVLOXSEG4EI16_V_MF4_MF2_MASK, VLOXSEG4EI16_V, 0x7, 0x0 }, // 3550 |
9542 | | { PseudoVLOXSEG4EI32_V_M1_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3551 |
9543 | | { PseudoVLOXSEG4EI32_V_M1_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3552 |
9544 | | { PseudoVLOXSEG4EI32_V_M2_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3553 |
9545 | | { PseudoVLOXSEG4EI32_V_M2_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3554 |
9546 | | { PseudoVLOXSEG4EI32_V_M4_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3555 |
9547 | | { PseudoVLOXSEG4EI32_V_M4_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3556 |
9548 | | { PseudoVLOXSEG4EI32_V_MF2_M1, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3557 |
9549 | | { PseudoVLOXSEG4EI32_V_MF2_M1_MASK, VLOXSEG4EI32_V, 0x0, 0x0 }, // 3558 |
9550 | | { PseudoVLOXSEG4EI32_V_M1_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3559 |
9551 | | { PseudoVLOXSEG4EI32_V_M1_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3560 |
9552 | | { PseudoVLOXSEG4EI32_V_M2_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3561 |
9553 | | { PseudoVLOXSEG4EI32_V_M2_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3562 |
9554 | | { PseudoVLOXSEG4EI32_V_M4_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3563 |
9555 | | { PseudoVLOXSEG4EI32_V_M4_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3564 |
9556 | | { PseudoVLOXSEG4EI32_V_M8_M2, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3565 |
9557 | | { PseudoVLOXSEG4EI32_V_M8_M2_MASK, VLOXSEG4EI32_V, 0x1, 0x0 }, // 3566 |
9558 | | { PseudoVLOXSEG4EI32_V_MF2_MF8, VLOXSEG4EI32_V, 0x5, 0x0 }, // 3567 |
9559 | | { PseudoVLOXSEG4EI32_V_MF2_MF8_MASK, VLOXSEG4EI32_V, 0x5, 0x0 }, // 3568 |
9560 | | { PseudoVLOXSEG4EI32_V_M1_MF4, VLOXSEG4EI32_V, 0x6, 0x0 }, // 3569 |
9561 | | { PseudoVLOXSEG4EI32_V_M1_MF4_MASK, VLOXSEG4EI32_V, 0x6, 0x0 }, // 3570 |
9562 | | { PseudoVLOXSEG4EI32_V_MF2_MF4, VLOXSEG4EI32_V, 0x6, 0x0 }, // 3571 |
9563 | | { PseudoVLOXSEG4EI32_V_MF2_MF4_MASK, VLOXSEG4EI32_V, 0x6, 0x0 }, // 3572 |
9564 | | { PseudoVLOXSEG4EI32_V_M1_MF2, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3573 |
9565 | | { PseudoVLOXSEG4EI32_V_M1_MF2_MASK, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3574 |
9566 | | { PseudoVLOXSEG4EI32_V_M2_MF2, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3575 |
9567 | | { PseudoVLOXSEG4EI32_V_M2_MF2_MASK, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3576 |
9568 | | { PseudoVLOXSEG4EI32_V_MF2_MF2, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3577 |
9569 | | { PseudoVLOXSEG4EI32_V_MF2_MF2_MASK, VLOXSEG4EI32_V, 0x7, 0x0 }, // 3578 |
9570 | | { PseudoVLOXSEG4EI64_V_M1_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3579 |
9571 | | { PseudoVLOXSEG4EI64_V_M1_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3580 |
9572 | | { PseudoVLOXSEG4EI64_V_M2_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3581 |
9573 | | { PseudoVLOXSEG4EI64_V_M2_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3582 |
9574 | | { PseudoVLOXSEG4EI64_V_M4_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3583 |
9575 | | { PseudoVLOXSEG4EI64_V_M4_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3584 |
9576 | | { PseudoVLOXSEG4EI64_V_M8_M1, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3585 |
9577 | | { PseudoVLOXSEG4EI64_V_M8_M1_MASK, VLOXSEG4EI64_V, 0x0, 0x0 }, // 3586 |
9578 | | { PseudoVLOXSEG4EI64_V_M2_M2, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3587 |
9579 | | { PseudoVLOXSEG4EI64_V_M2_M2_MASK, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3588 |
9580 | | { PseudoVLOXSEG4EI64_V_M4_M2, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3589 |
9581 | | { PseudoVLOXSEG4EI64_V_M4_M2_MASK, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3590 |
9582 | | { PseudoVLOXSEG4EI64_V_M8_M2, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3591 |
9583 | | { PseudoVLOXSEG4EI64_V_M8_M2_MASK, VLOXSEG4EI64_V, 0x1, 0x0 }, // 3592 |
9584 | | { PseudoVLOXSEG4EI64_V_M1_MF8, VLOXSEG4EI64_V, 0x5, 0x0 }, // 3593 |
9585 | | { PseudoVLOXSEG4EI64_V_M1_MF8_MASK, VLOXSEG4EI64_V, 0x5, 0x0 }, // 3594 |
9586 | | { PseudoVLOXSEG4EI64_V_M1_MF4, VLOXSEG4EI64_V, 0x6, 0x0 }, // 3595 |
9587 | | { PseudoVLOXSEG4EI64_V_M1_MF4_MASK, VLOXSEG4EI64_V, 0x6, 0x0 }, // 3596 |
9588 | | { PseudoVLOXSEG4EI64_V_M2_MF4, VLOXSEG4EI64_V, 0x6, 0x0 }, // 3597 |
9589 | | { PseudoVLOXSEG4EI64_V_M2_MF4_MASK, VLOXSEG4EI64_V, 0x6, 0x0 }, // 3598 |
9590 | | { PseudoVLOXSEG4EI64_V_M1_MF2, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3599 |
9591 | | { PseudoVLOXSEG4EI64_V_M1_MF2_MASK, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3600 |
9592 | | { PseudoVLOXSEG4EI64_V_M2_MF2, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3601 |
9593 | | { PseudoVLOXSEG4EI64_V_M2_MF2_MASK, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3602 |
9594 | | { PseudoVLOXSEG4EI64_V_M4_MF2, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3603 |
9595 | | { PseudoVLOXSEG4EI64_V_M4_MF2_MASK, VLOXSEG4EI64_V, 0x7, 0x0 }, // 3604 |
9596 | | { PseudoVLOXSEG4EI8_V_M1_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3605 |
9597 | | { PseudoVLOXSEG4EI8_V_M1_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3606 |
9598 | | { PseudoVLOXSEG4EI8_V_MF2_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3607 |
9599 | | { PseudoVLOXSEG4EI8_V_MF2_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3608 |
9600 | | { PseudoVLOXSEG4EI8_V_MF4_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3609 |
9601 | | { PseudoVLOXSEG4EI8_V_MF4_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3610 |
9602 | | { PseudoVLOXSEG4EI8_V_MF8_M1, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3611 |
9603 | | { PseudoVLOXSEG4EI8_V_MF8_M1_MASK, VLOXSEG4EI8_V, 0x0, 0x0 }, // 3612 |
9604 | | { PseudoVLOXSEG4EI8_V_M1_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3613 |
9605 | | { PseudoVLOXSEG4EI8_V_M1_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3614 |
9606 | | { PseudoVLOXSEG4EI8_V_M2_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3615 |
9607 | | { PseudoVLOXSEG4EI8_V_M2_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3616 |
9608 | | { PseudoVLOXSEG4EI8_V_MF2_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3617 |
9609 | | { PseudoVLOXSEG4EI8_V_MF2_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3618 |
9610 | | { PseudoVLOXSEG4EI8_V_MF4_M2, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3619 |
9611 | | { PseudoVLOXSEG4EI8_V_MF4_M2_MASK, VLOXSEG4EI8_V, 0x1, 0x0 }, // 3620 |
9612 | | { PseudoVLOXSEG4EI8_V_MF8_MF8, VLOXSEG4EI8_V, 0x5, 0x0 }, // 3621 |
9613 | | { PseudoVLOXSEG4EI8_V_MF8_MF8_MASK, VLOXSEG4EI8_V, 0x5, 0x0 }, // 3622 |
9614 | | { PseudoVLOXSEG4EI8_V_MF4_MF4, VLOXSEG4EI8_V, 0x6, 0x0 }, // 3623 |
9615 | | { PseudoVLOXSEG4EI8_V_MF4_MF4_MASK, VLOXSEG4EI8_V, 0x6, 0x0 }, // 3624 |
9616 | | { PseudoVLOXSEG4EI8_V_MF8_MF4, VLOXSEG4EI8_V, 0x6, 0x0 }, // 3625 |
9617 | | { PseudoVLOXSEG4EI8_V_MF8_MF4_MASK, VLOXSEG4EI8_V, 0x6, 0x0 }, // 3626 |
9618 | | { PseudoVLOXSEG4EI8_V_MF2_MF2, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3627 |
9619 | | { PseudoVLOXSEG4EI8_V_MF2_MF2_MASK, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3628 |
9620 | | { PseudoVLOXSEG4EI8_V_MF4_MF2, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3629 |
9621 | | { PseudoVLOXSEG4EI8_V_MF4_MF2_MASK, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3630 |
9622 | | { PseudoVLOXSEG4EI8_V_MF8_MF2, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3631 |
9623 | | { PseudoVLOXSEG4EI8_V_MF8_MF2_MASK, VLOXSEG4EI8_V, 0x7, 0x0 }, // 3632 |
9624 | | { PseudoVLOXSEG5EI16_V_M1_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3633 |
9625 | | { PseudoVLOXSEG5EI16_V_M1_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3634 |
9626 | | { PseudoVLOXSEG5EI16_V_M2_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3635 |
9627 | | { PseudoVLOXSEG5EI16_V_M2_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3636 |
9628 | | { PseudoVLOXSEG5EI16_V_MF2_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3637 |
9629 | | { PseudoVLOXSEG5EI16_V_MF2_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3638 |
9630 | | { PseudoVLOXSEG5EI16_V_MF4_M1, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3639 |
9631 | | { PseudoVLOXSEG5EI16_V_MF4_M1_MASK, VLOXSEG5EI16_V, 0x0, 0x0 }, // 3640 |
9632 | | { PseudoVLOXSEG5EI16_V_MF4_MF8, VLOXSEG5EI16_V, 0x5, 0x0 }, // 3641 |
9633 | | { PseudoVLOXSEG5EI16_V_MF4_MF8_MASK, VLOXSEG5EI16_V, 0x5, 0x0 }, // 3642 |
9634 | | { PseudoVLOXSEG5EI16_V_MF2_MF4, VLOXSEG5EI16_V, 0x6, 0x0 }, // 3643 |
9635 | | { PseudoVLOXSEG5EI16_V_MF2_MF4_MASK, VLOXSEG5EI16_V, 0x6, 0x0 }, // 3644 |
9636 | | { PseudoVLOXSEG5EI16_V_MF4_MF4, VLOXSEG5EI16_V, 0x6, 0x0 }, // 3645 |
9637 | | { PseudoVLOXSEG5EI16_V_MF4_MF4_MASK, VLOXSEG5EI16_V, 0x6, 0x0 }, // 3646 |
9638 | | { PseudoVLOXSEG5EI16_V_M1_MF2, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3647 |
9639 | | { PseudoVLOXSEG5EI16_V_M1_MF2_MASK, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3648 |
9640 | | { PseudoVLOXSEG5EI16_V_MF2_MF2, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3649 |
9641 | | { PseudoVLOXSEG5EI16_V_MF2_MF2_MASK, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3650 |
9642 | | { PseudoVLOXSEG5EI16_V_MF4_MF2, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3651 |
9643 | | { PseudoVLOXSEG5EI16_V_MF4_MF2_MASK, VLOXSEG5EI16_V, 0x7, 0x0 }, // 3652 |
9644 | | { PseudoVLOXSEG5EI32_V_M1_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3653 |
9645 | | { PseudoVLOXSEG5EI32_V_M1_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3654 |
9646 | | { PseudoVLOXSEG5EI32_V_M2_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3655 |
9647 | | { PseudoVLOXSEG5EI32_V_M2_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3656 |
9648 | | { PseudoVLOXSEG5EI32_V_M4_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3657 |
9649 | | { PseudoVLOXSEG5EI32_V_M4_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3658 |
9650 | | { PseudoVLOXSEG5EI32_V_MF2_M1, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3659 |
9651 | | { PseudoVLOXSEG5EI32_V_MF2_M1_MASK, VLOXSEG5EI32_V, 0x0, 0x0 }, // 3660 |
9652 | | { PseudoVLOXSEG5EI32_V_MF2_MF8, VLOXSEG5EI32_V, 0x5, 0x0 }, // 3661 |
9653 | | { PseudoVLOXSEG5EI32_V_MF2_MF8_MASK, VLOXSEG5EI32_V, 0x5, 0x0 }, // 3662 |
9654 | | { PseudoVLOXSEG5EI32_V_M1_MF4, VLOXSEG5EI32_V, 0x6, 0x0 }, // 3663 |
9655 | | { PseudoVLOXSEG5EI32_V_M1_MF4_MASK, VLOXSEG5EI32_V, 0x6, 0x0 }, // 3664 |
9656 | | { PseudoVLOXSEG5EI32_V_MF2_MF4, VLOXSEG5EI32_V, 0x6, 0x0 }, // 3665 |
9657 | | { PseudoVLOXSEG5EI32_V_MF2_MF4_MASK, VLOXSEG5EI32_V, 0x6, 0x0 }, // 3666 |
9658 | | { PseudoVLOXSEG5EI32_V_M1_MF2, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3667 |
9659 | | { PseudoVLOXSEG5EI32_V_M1_MF2_MASK, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3668 |
9660 | | { PseudoVLOXSEG5EI32_V_M2_MF2, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3669 |
9661 | | { PseudoVLOXSEG5EI32_V_M2_MF2_MASK, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3670 |
9662 | | { PseudoVLOXSEG5EI32_V_MF2_MF2, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3671 |
9663 | | { PseudoVLOXSEG5EI32_V_MF2_MF2_MASK, VLOXSEG5EI32_V, 0x7, 0x0 }, // 3672 |
9664 | | { PseudoVLOXSEG5EI64_V_M1_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3673 |
9665 | | { PseudoVLOXSEG5EI64_V_M1_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3674 |
9666 | | { PseudoVLOXSEG5EI64_V_M2_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3675 |
9667 | | { PseudoVLOXSEG5EI64_V_M2_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3676 |
9668 | | { PseudoVLOXSEG5EI64_V_M4_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3677 |
9669 | | { PseudoVLOXSEG5EI64_V_M4_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3678 |
9670 | | { PseudoVLOXSEG5EI64_V_M8_M1, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3679 |
9671 | | { PseudoVLOXSEG5EI64_V_M8_M1_MASK, VLOXSEG5EI64_V, 0x0, 0x0 }, // 3680 |
9672 | | { PseudoVLOXSEG5EI64_V_M1_MF8, VLOXSEG5EI64_V, 0x5, 0x0 }, // 3681 |
9673 | | { PseudoVLOXSEG5EI64_V_M1_MF8_MASK, VLOXSEG5EI64_V, 0x5, 0x0 }, // 3682 |
9674 | | { PseudoVLOXSEG5EI64_V_M1_MF4, VLOXSEG5EI64_V, 0x6, 0x0 }, // 3683 |
9675 | | { PseudoVLOXSEG5EI64_V_M1_MF4_MASK, VLOXSEG5EI64_V, 0x6, 0x0 }, // 3684 |
9676 | | { PseudoVLOXSEG5EI64_V_M2_MF4, VLOXSEG5EI64_V, 0x6, 0x0 }, // 3685 |
9677 | | { PseudoVLOXSEG5EI64_V_M2_MF4_MASK, VLOXSEG5EI64_V, 0x6, 0x0 }, // 3686 |
9678 | | { PseudoVLOXSEG5EI64_V_M1_MF2, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3687 |
9679 | | { PseudoVLOXSEG5EI64_V_M1_MF2_MASK, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3688 |
9680 | | { PseudoVLOXSEG5EI64_V_M2_MF2, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3689 |
9681 | | { PseudoVLOXSEG5EI64_V_M2_MF2_MASK, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3690 |
9682 | | { PseudoVLOXSEG5EI64_V_M4_MF2, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3691 |
9683 | | { PseudoVLOXSEG5EI64_V_M4_MF2_MASK, VLOXSEG5EI64_V, 0x7, 0x0 }, // 3692 |
9684 | | { PseudoVLOXSEG5EI8_V_M1_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3693 |
9685 | | { PseudoVLOXSEG5EI8_V_M1_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3694 |
9686 | | { PseudoVLOXSEG5EI8_V_MF2_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3695 |
9687 | | { PseudoVLOXSEG5EI8_V_MF2_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3696 |
9688 | | { PseudoVLOXSEG5EI8_V_MF4_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3697 |
9689 | | { PseudoVLOXSEG5EI8_V_MF4_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3698 |
9690 | | { PseudoVLOXSEG5EI8_V_MF8_M1, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3699 |
9691 | | { PseudoVLOXSEG5EI8_V_MF8_M1_MASK, VLOXSEG5EI8_V, 0x0, 0x0 }, // 3700 |
9692 | | { PseudoVLOXSEG5EI8_V_MF8_MF8, VLOXSEG5EI8_V, 0x5, 0x0 }, // 3701 |
9693 | | { PseudoVLOXSEG5EI8_V_MF8_MF8_MASK, VLOXSEG5EI8_V, 0x5, 0x0 }, // 3702 |
9694 | | { PseudoVLOXSEG5EI8_V_MF4_MF4, VLOXSEG5EI8_V, 0x6, 0x0 }, // 3703 |
9695 | | { PseudoVLOXSEG5EI8_V_MF4_MF4_MASK, VLOXSEG5EI8_V, 0x6, 0x0 }, // 3704 |
9696 | | { PseudoVLOXSEG5EI8_V_MF8_MF4, VLOXSEG5EI8_V, 0x6, 0x0 }, // 3705 |
9697 | | { PseudoVLOXSEG5EI8_V_MF8_MF4_MASK, VLOXSEG5EI8_V, 0x6, 0x0 }, // 3706 |
9698 | | { PseudoVLOXSEG5EI8_V_MF2_MF2, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3707 |
9699 | | { PseudoVLOXSEG5EI8_V_MF2_MF2_MASK, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3708 |
9700 | | { PseudoVLOXSEG5EI8_V_MF4_MF2, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3709 |
9701 | | { PseudoVLOXSEG5EI8_V_MF4_MF2_MASK, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3710 |
9702 | | { PseudoVLOXSEG5EI8_V_MF8_MF2, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3711 |
9703 | | { PseudoVLOXSEG5EI8_V_MF8_MF2_MASK, VLOXSEG5EI8_V, 0x7, 0x0 }, // 3712 |
9704 | | { PseudoVLOXSEG6EI16_V_M1_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3713 |
9705 | | { PseudoVLOXSEG6EI16_V_M1_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3714 |
9706 | | { PseudoVLOXSEG6EI16_V_M2_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3715 |
9707 | | { PseudoVLOXSEG6EI16_V_M2_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3716 |
9708 | | { PseudoVLOXSEG6EI16_V_MF2_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3717 |
9709 | | { PseudoVLOXSEG6EI16_V_MF2_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3718 |
9710 | | { PseudoVLOXSEG6EI16_V_MF4_M1, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3719 |
9711 | | { PseudoVLOXSEG6EI16_V_MF4_M1_MASK, VLOXSEG6EI16_V, 0x0, 0x0 }, // 3720 |
9712 | | { PseudoVLOXSEG6EI16_V_MF4_MF8, VLOXSEG6EI16_V, 0x5, 0x0 }, // 3721 |
9713 | | { PseudoVLOXSEG6EI16_V_MF4_MF8_MASK, VLOXSEG6EI16_V, 0x5, 0x0 }, // 3722 |
9714 | | { PseudoVLOXSEG6EI16_V_MF2_MF4, VLOXSEG6EI16_V, 0x6, 0x0 }, // 3723 |
9715 | | { PseudoVLOXSEG6EI16_V_MF2_MF4_MASK, VLOXSEG6EI16_V, 0x6, 0x0 }, // 3724 |
9716 | | { PseudoVLOXSEG6EI16_V_MF4_MF4, VLOXSEG6EI16_V, 0x6, 0x0 }, // 3725 |
9717 | | { PseudoVLOXSEG6EI16_V_MF4_MF4_MASK, VLOXSEG6EI16_V, 0x6, 0x0 }, // 3726 |
9718 | | { PseudoVLOXSEG6EI16_V_M1_MF2, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3727 |
9719 | | { PseudoVLOXSEG6EI16_V_M1_MF2_MASK, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3728 |
9720 | | { PseudoVLOXSEG6EI16_V_MF2_MF2, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3729 |
9721 | | { PseudoVLOXSEG6EI16_V_MF2_MF2_MASK, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3730 |
9722 | | { PseudoVLOXSEG6EI16_V_MF4_MF2, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3731 |
9723 | | { PseudoVLOXSEG6EI16_V_MF4_MF2_MASK, VLOXSEG6EI16_V, 0x7, 0x0 }, // 3732 |
9724 | | { PseudoVLOXSEG6EI32_V_M1_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3733 |
9725 | | { PseudoVLOXSEG6EI32_V_M1_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3734 |
9726 | | { PseudoVLOXSEG6EI32_V_M2_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3735 |
9727 | | { PseudoVLOXSEG6EI32_V_M2_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3736 |
9728 | | { PseudoVLOXSEG6EI32_V_M4_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3737 |
9729 | | { PseudoVLOXSEG6EI32_V_M4_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3738 |
9730 | | { PseudoVLOXSEG6EI32_V_MF2_M1, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3739 |
9731 | | { PseudoVLOXSEG6EI32_V_MF2_M1_MASK, VLOXSEG6EI32_V, 0x0, 0x0 }, // 3740 |
9732 | | { PseudoVLOXSEG6EI32_V_MF2_MF8, VLOXSEG6EI32_V, 0x5, 0x0 }, // 3741 |
9733 | | { PseudoVLOXSEG6EI32_V_MF2_MF8_MASK, VLOXSEG6EI32_V, 0x5, 0x0 }, // 3742 |
9734 | | { PseudoVLOXSEG6EI32_V_M1_MF4, VLOXSEG6EI32_V, 0x6, 0x0 }, // 3743 |
9735 | | { PseudoVLOXSEG6EI32_V_M1_MF4_MASK, VLOXSEG6EI32_V, 0x6, 0x0 }, // 3744 |
9736 | | { PseudoVLOXSEG6EI32_V_MF2_MF4, VLOXSEG6EI32_V, 0x6, 0x0 }, // 3745 |
9737 | | { PseudoVLOXSEG6EI32_V_MF2_MF4_MASK, VLOXSEG6EI32_V, 0x6, 0x0 }, // 3746 |
9738 | | { PseudoVLOXSEG6EI32_V_M1_MF2, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3747 |
9739 | | { PseudoVLOXSEG6EI32_V_M1_MF2_MASK, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3748 |
9740 | | { PseudoVLOXSEG6EI32_V_M2_MF2, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3749 |
9741 | | { PseudoVLOXSEG6EI32_V_M2_MF2_MASK, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3750 |
9742 | | { PseudoVLOXSEG6EI32_V_MF2_MF2, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3751 |
9743 | | { PseudoVLOXSEG6EI32_V_MF2_MF2_MASK, VLOXSEG6EI32_V, 0x7, 0x0 }, // 3752 |
9744 | | { PseudoVLOXSEG6EI64_V_M1_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3753 |
9745 | | { PseudoVLOXSEG6EI64_V_M1_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3754 |
9746 | | { PseudoVLOXSEG6EI64_V_M2_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3755 |
9747 | | { PseudoVLOXSEG6EI64_V_M2_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3756 |
9748 | | { PseudoVLOXSEG6EI64_V_M4_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3757 |
9749 | | { PseudoVLOXSEG6EI64_V_M4_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3758 |
9750 | | { PseudoVLOXSEG6EI64_V_M8_M1, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3759 |
9751 | | { PseudoVLOXSEG6EI64_V_M8_M1_MASK, VLOXSEG6EI64_V, 0x0, 0x0 }, // 3760 |
9752 | | { PseudoVLOXSEG6EI64_V_M1_MF8, VLOXSEG6EI64_V, 0x5, 0x0 }, // 3761 |
9753 | | { PseudoVLOXSEG6EI64_V_M1_MF8_MASK, VLOXSEG6EI64_V, 0x5, 0x0 }, // 3762 |
9754 | | { PseudoVLOXSEG6EI64_V_M1_MF4, VLOXSEG6EI64_V, 0x6, 0x0 }, // 3763 |
9755 | | { PseudoVLOXSEG6EI64_V_M1_MF4_MASK, VLOXSEG6EI64_V, 0x6, 0x0 }, // 3764 |
9756 | | { PseudoVLOXSEG6EI64_V_M2_MF4, VLOXSEG6EI64_V, 0x6, 0x0 }, // 3765 |
9757 | | { PseudoVLOXSEG6EI64_V_M2_MF4_MASK, VLOXSEG6EI64_V, 0x6, 0x0 }, // 3766 |
9758 | | { PseudoVLOXSEG6EI64_V_M1_MF2, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3767 |
9759 | | { PseudoVLOXSEG6EI64_V_M1_MF2_MASK, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3768 |
9760 | | { PseudoVLOXSEG6EI64_V_M2_MF2, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3769 |
9761 | | { PseudoVLOXSEG6EI64_V_M2_MF2_MASK, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3770 |
9762 | | { PseudoVLOXSEG6EI64_V_M4_MF2, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3771 |
9763 | | { PseudoVLOXSEG6EI64_V_M4_MF2_MASK, VLOXSEG6EI64_V, 0x7, 0x0 }, // 3772 |
9764 | | { PseudoVLOXSEG6EI8_V_M1_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3773 |
9765 | | { PseudoVLOXSEG6EI8_V_M1_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3774 |
9766 | | { PseudoVLOXSEG6EI8_V_MF2_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3775 |
9767 | | { PseudoVLOXSEG6EI8_V_MF2_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3776 |
9768 | | { PseudoVLOXSEG6EI8_V_MF4_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3777 |
9769 | | { PseudoVLOXSEG6EI8_V_MF4_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3778 |
9770 | | { PseudoVLOXSEG6EI8_V_MF8_M1, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3779 |
9771 | | { PseudoVLOXSEG6EI8_V_MF8_M1_MASK, VLOXSEG6EI8_V, 0x0, 0x0 }, // 3780 |
9772 | | { PseudoVLOXSEG6EI8_V_MF8_MF8, VLOXSEG6EI8_V, 0x5, 0x0 }, // 3781 |
9773 | | { PseudoVLOXSEG6EI8_V_MF8_MF8_MASK, VLOXSEG6EI8_V, 0x5, 0x0 }, // 3782 |
9774 | | { PseudoVLOXSEG6EI8_V_MF4_MF4, VLOXSEG6EI8_V, 0x6, 0x0 }, // 3783 |
9775 | | { PseudoVLOXSEG6EI8_V_MF4_MF4_MASK, VLOXSEG6EI8_V, 0x6, 0x0 }, // 3784 |
9776 | | { PseudoVLOXSEG6EI8_V_MF8_MF4, VLOXSEG6EI8_V, 0x6, 0x0 }, // 3785 |
9777 | | { PseudoVLOXSEG6EI8_V_MF8_MF4_MASK, VLOXSEG6EI8_V, 0x6, 0x0 }, // 3786 |
9778 | | { PseudoVLOXSEG6EI8_V_MF2_MF2, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3787 |
9779 | | { PseudoVLOXSEG6EI8_V_MF2_MF2_MASK, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3788 |
9780 | | { PseudoVLOXSEG6EI8_V_MF4_MF2, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3789 |
9781 | | { PseudoVLOXSEG6EI8_V_MF4_MF2_MASK, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3790 |
9782 | | { PseudoVLOXSEG6EI8_V_MF8_MF2, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3791 |
9783 | | { PseudoVLOXSEG6EI8_V_MF8_MF2_MASK, VLOXSEG6EI8_V, 0x7, 0x0 }, // 3792 |
9784 | | { PseudoVLOXSEG7EI16_V_M1_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3793 |
9785 | | { PseudoVLOXSEG7EI16_V_M1_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3794 |
9786 | | { PseudoVLOXSEG7EI16_V_M2_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3795 |
9787 | | { PseudoVLOXSEG7EI16_V_M2_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3796 |
9788 | | { PseudoVLOXSEG7EI16_V_MF2_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3797 |
9789 | | { PseudoVLOXSEG7EI16_V_MF2_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3798 |
9790 | | { PseudoVLOXSEG7EI16_V_MF4_M1, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3799 |
9791 | | { PseudoVLOXSEG7EI16_V_MF4_M1_MASK, VLOXSEG7EI16_V, 0x0, 0x0 }, // 3800 |
9792 | | { PseudoVLOXSEG7EI16_V_MF4_MF8, VLOXSEG7EI16_V, 0x5, 0x0 }, // 3801 |
9793 | | { PseudoVLOXSEG7EI16_V_MF4_MF8_MASK, VLOXSEG7EI16_V, 0x5, 0x0 }, // 3802 |
9794 | | { PseudoVLOXSEG7EI16_V_MF2_MF4, VLOXSEG7EI16_V, 0x6, 0x0 }, // 3803 |
9795 | | { PseudoVLOXSEG7EI16_V_MF2_MF4_MASK, VLOXSEG7EI16_V, 0x6, 0x0 }, // 3804 |
9796 | | { PseudoVLOXSEG7EI16_V_MF4_MF4, VLOXSEG7EI16_V, 0x6, 0x0 }, // 3805 |
9797 | | { PseudoVLOXSEG7EI16_V_MF4_MF4_MASK, VLOXSEG7EI16_V, 0x6, 0x0 }, // 3806 |
9798 | | { PseudoVLOXSEG7EI16_V_M1_MF2, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3807 |
9799 | | { PseudoVLOXSEG7EI16_V_M1_MF2_MASK, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3808 |
9800 | | { PseudoVLOXSEG7EI16_V_MF2_MF2, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3809 |
9801 | | { PseudoVLOXSEG7EI16_V_MF2_MF2_MASK, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3810 |
9802 | | { PseudoVLOXSEG7EI16_V_MF4_MF2, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3811 |
9803 | | { PseudoVLOXSEG7EI16_V_MF4_MF2_MASK, VLOXSEG7EI16_V, 0x7, 0x0 }, // 3812 |
9804 | | { PseudoVLOXSEG7EI32_V_M1_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3813 |
9805 | | { PseudoVLOXSEG7EI32_V_M1_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3814 |
9806 | | { PseudoVLOXSEG7EI32_V_M2_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3815 |
9807 | | { PseudoVLOXSEG7EI32_V_M2_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3816 |
9808 | | { PseudoVLOXSEG7EI32_V_M4_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3817 |
9809 | | { PseudoVLOXSEG7EI32_V_M4_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3818 |
9810 | | { PseudoVLOXSEG7EI32_V_MF2_M1, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3819 |
9811 | | { PseudoVLOXSEG7EI32_V_MF2_M1_MASK, VLOXSEG7EI32_V, 0x0, 0x0 }, // 3820 |
9812 | | { PseudoVLOXSEG7EI32_V_MF2_MF8, VLOXSEG7EI32_V, 0x5, 0x0 }, // 3821 |
9813 | | { PseudoVLOXSEG7EI32_V_MF2_MF8_MASK, VLOXSEG7EI32_V, 0x5, 0x0 }, // 3822 |
9814 | | { PseudoVLOXSEG7EI32_V_M1_MF4, VLOXSEG7EI32_V, 0x6, 0x0 }, // 3823 |
9815 | | { PseudoVLOXSEG7EI32_V_M1_MF4_MASK, VLOXSEG7EI32_V, 0x6, 0x0 }, // 3824 |
9816 | | { PseudoVLOXSEG7EI32_V_MF2_MF4, VLOXSEG7EI32_V, 0x6, 0x0 }, // 3825 |
9817 | | { PseudoVLOXSEG7EI32_V_MF2_MF4_MASK, VLOXSEG7EI32_V, 0x6, 0x0 }, // 3826 |
9818 | | { PseudoVLOXSEG7EI32_V_M1_MF2, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3827 |
9819 | | { PseudoVLOXSEG7EI32_V_M1_MF2_MASK, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3828 |
9820 | | { PseudoVLOXSEG7EI32_V_M2_MF2, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3829 |
9821 | | { PseudoVLOXSEG7EI32_V_M2_MF2_MASK, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3830 |
9822 | | { PseudoVLOXSEG7EI32_V_MF2_MF2, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3831 |
9823 | | { PseudoVLOXSEG7EI32_V_MF2_MF2_MASK, VLOXSEG7EI32_V, 0x7, 0x0 }, // 3832 |
9824 | | { PseudoVLOXSEG7EI64_V_M1_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3833 |
9825 | | { PseudoVLOXSEG7EI64_V_M1_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3834 |
9826 | | { PseudoVLOXSEG7EI64_V_M2_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3835 |
9827 | | { PseudoVLOXSEG7EI64_V_M2_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3836 |
9828 | | { PseudoVLOXSEG7EI64_V_M4_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3837 |
9829 | | { PseudoVLOXSEG7EI64_V_M4_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3838 |
9830 | | { PseudoVLOXSEG7EI64_V_M8_M1, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3839 |
9831 | | { PseudoVLOXSEG7EI64_V_M8_M1_MASK, VLOXSEG7EI64_V, 0x0, 0x0 }, // 3840 |
9832 | | { PseudoVLOXSEG7EI64_V_M1_MF8, VLOXSEG7EI64_V, 0x5, 0x0 }, // 3841 |
9833 | | { PseudoVLOXSEG7EI64_V_M1_MF8_MASK, VLOXSEG7EI64_V, 0x5, 0x0 }, // 3842 |
9834 | | { PseudoVLOXSEG7EI64_V_M1_MF4, VLOXSEG7EI64_V, 0x6, 0x0 }, // 3843 |
9835 | | { PseudoVLOXSEG7EI64_V_M1_MF4_MASK, VLOXSEG7EI64_V, 0x6, 0x0 }, // 3844 |
9836 | | { PseudoVLOXSEG7EI64_V_M2_MF4, VLOXSEG7EI64_V, 0x6, 0x0 }, // 3845 |
9837 | | { PseudoVLOXSEG7EI64_V_M2_MF4_MASK, VLOXSEG7EI64_V, 0x6, 0x0 }, // 3846 |
9838 | | { PseudoVLOXSEG7EI64_V_M1_MF2, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3847 |
9839 | | { PseudoVLOXSEG7EI64_V_M1_MF2_MASK, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3848 |
9840 | | { PseudoVLOXSEG7EI64_V_M2_MF2, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3849 |
9841 | | { PseudoVLOXSEG7EI64_V_M2_MF2_MASK, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3850 |
9842 | | { PseudoVLOXSEG7EI64_V_M4_MF2, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3851 |
9843 | | { PseudoVLOXSEG7EI64_V_M4_MF2_MASK, VLOXSEG7EI64_V, 0x7, 0x0 }, // 3852 |
9844 | | { PseudoVLOXSEG7EI8_V_M1_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3853 |
9845 | | { PseudoVLOXSEG7EI8_V_M1_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3854 |
9846 | | { PseudoVLOXSEG7EI8_V_MF2_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3855 |
9847 | | { PseudoVLOXSEG7EI8_V_MF2_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3856 |
9848 | | { PseudoVLOXSEG7EI8_V_MF4_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3857 |
9849 | | { PseudoVLOXSEG7EI8_V_MF4_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3858 |
9850 | | { PseudoVLOXSEG7EI8_V_MF8_M1, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3859 |
9851 | | { PseudoVLOXSEG7EI8_V_MF8_M1_MASK, VLOXSEG7EI8_V, 0x0, 0x0 }, // 3860 |
9852 | | { PseudoVLOXSEG7EI8_V_MF8_MF8, VLOXSEG7EI8_V, 0x5, 0x0 }, // 3861 |
9853 | | { PseudoVLOXSEG7EI8_V_MF8_MF8_MASK, VLOXSEG7EI8_V, 0x5, 0x0 }, // 3862 |
9854 | | { PseudoVLOXSEG7EI8_V_MF4_MF4, VLOXSEG7EI8_V, 0x6, 0x0 }, // 3863 |
9855 | | { PseudoVLOXSEG7EI8_V_MF4_MF4_MASK, VLOXSEG7EI8_V, 0x6, 0x0 }, // 3864 |
9856 | | { PseudoVLOXSEG7EI8_V_MF8_MF4, VLOXSEG7EI8_V, 0x6, 0x0 }, // 3865 |
9857 | | { PseudoVLOXSEG7EI8_V_MF8_MF4_MASK, VLOXSEG7EI8_V, 0x6, 0x0 }, // 3866 |
9858 | | { PseudoVLOXSEG7EI8_V_MF2_MF2, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3867 |
9859 | | { PseudoVLOXSEG7EI8_V_MF2_MF2_MASK, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3868 |
9860 | | { PseudoVLOXSEG7EI8_V_MF4_MF2, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3869 |
9861 | | { PseudoVLOXSEG7EI8_V_MF4_MF2_MASK, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3870 |
9862 | | { PseudoVLOXSEG7EI8_V_MF8_MF2, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3871 |
9863 | | { PseudoVLOXSEG7EI8_V_MF8_MF2_MASK, VLOXSEG7EI8_V, 0x7, 0x0 }, // 3872 |
9864 | | { PseudoVLOXSEG8EI16_V_M1_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3873 |
9865 | | { PseudoVLOXSEG8EI16_V_M1_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3874 |
9866 | | { PseudoVLOXSEG8EI16_V_M2_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3875 |
9867 | | { PseudoVLOXSEG8EI16_V_M2_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3876 |
9868 | | { PseudoVLOXSEG8EI16_V_MF2_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3877 |
9869 | | { PseudoVLOXSEG8EI16_V_MF2_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3878 |
9870 | | { PseudoVLOXSEG8EI16_V_MF4_M1, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3879 |
9871 | | { PseudoVLOXSEG8EI16_V_MF4_M1_MASK, VLOXSEG8EI16_V, 0x0, 0x0 }, // 3880 |
9872 | | { PseudoVLOXSEG8EI16_V_MF4_MF8, VLOXSEG8EI16_V, 0x5, 0x0 }, // 3881 |
9873 | | { PseudoVLOXSEG8EI16_V_MF4_MF8_MASK, VLOXSEG8EI16_V, 0x5, 0x0 }, // 3882 |
9874 | | { PseudoVLOXSEG8EI16_V_MF2_MF4, VLOXSEG8EI16_V, 0x6, 0x0 }, // 3883 |
9875 | | { PseudoVLOXSEG8EI16_V_MF2_MF4_MASK, VLOXSEG8EI16_V, 0x6, 0x0 }, // 3884 |
9876 | | { PseudoVLOXSEG8EI16_V_MF4_MF4, VLOXSEG8EI16_V, 0x6, 0x0 }, // 3885 |
9877 | | { PseudoVLOXSEG8EI16_V_MF4_MF4_MASK, VLOXSEG8EI16_V, 0x6, 0x0 }, // 3886 |
9878 | | { PseudoVLOXSEG8EI16_V_M1_MF2, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3887 |
9879 | | { PseudoVLOXSEG8EI16_V_M1_MF2_MASK, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3888 |
9880 | | { PseudoVLOXSEG8EI16_V_MF2_MF2, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3889 |
9881 | | { PseudoVLOXSEG8EI16_V_MF2_MF2_MASK, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3890 |
9882 | | { PseudoVLOXSEG8EI16_V_MF4_MF2, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3891 |
9883 | | { PseudoVLOXSEG8EI16_V_MF4_MF2_MASK, VLOXSEG8EI16_V, 0x7, 0x0 }, // 3892 |
9884 | | { PseudoVLOXSEG8EI32_V_M1_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3893 |
9885 | | { PseudoVLOXSEG8EI32_V_M1_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3894 |
9886 | | { PseudoVLOXSEG8EI32_V_M2_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3895 |
9887 | | { PseudoVLOXSEG8EI32_V_M2_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3896 |
9888 | | { PseudoVLOXSEG8EI32_V_M4_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3897 |
9889 | | { PseudoVLOXSEG8EI32_V_M4_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3898 |
9890 | | { PseudoVLOXSEG8EI32_V_MF2_M1, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3899 |
9891 | | { PseudoVLOXSEG8EI32_V_MF2_M1_MASK, VLOXSEG8EI32_V, 0x0, 0x0 }, // 3900 |
9892 | | { PseudoVLOXSEG8EI32_V_MF2_MF8, VLOXSEG8EI32_V, 0x5, 0x0 }, // 3901 |
9893 | | { PseudoVLOXSEG8EI32_V_MF2_MF8_MASK, VLOXSEG8EI32_V, 0x5, 0x0 }, // 3902 |
9894 | | { PseudoVLOXSEG8EI32_V_M1_MF4, VLOXSEG8EI32_V, 0x6, 0x0 }, // 3903 |
9895 | | { PseudoVLOXSEG8EI32_V_M1_MF4_MASK, VLOXSEG8EI32_V, 0x6, 0x0 }, // 3904 |
9896 | | { PseudoVLOXSEG8EI32_V_MF2_MF4, VLOXSEG8EI32_V, 0x6, 0x0 }, // 3905 |
9897 | | { PseudoVLOXSEG8EI32_V_MF2_MF4_MASK, VLOXSEG8EI32_V, 0x6, 0x0 }, // 3906 |
9898 | | { PseudoVLOXSEG8EI32_V_M1_MF2, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3907 |
9899 | | { PseudoVLOXSEG8EI32_V_M1_MF2_MASK, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3908 |
9900 | | { PseudoVLOXSEG8EI32_V_M2_MF2, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3909 |
9901 | | { PseudoVLOXSEG8EI32_V_M2_MF2_MASK, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3910 |
9902 | | { PseudoVLOXSEG8EI32_V_MF2_MF2, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3911 |
9903 | | { PseudoVLOXSEG8EI32_V_MF2_MF2_MASK, VLOXSEG8EI32_V, 0x7, 0x0 }, // 3912 |
9904 | | { PseudoVLOXSEG8EI64_V_M1_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3913 |
9905 | | { PseudoVLOXSEG8EI64_V_M1_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3914 |
9906 | | { PseudoVLOXSEG8EI64_V_M2_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3915 |
9907 | | { PseudoVLOXSEG8EI64_V_M2_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3916 |
9908 | | { PseudoVLOXSEG8EI64_V_M4_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3917 |
9909 | | { PseudoVLOXSEG8EI64_V_M4_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3918 |
9910 | | { PseudoVLOXSEG8EI64_V_M8_M1, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3919 |
9911 | | { PseudoVLOXSEG8EI64_V_M8_M1_MASK, VLOXSEG8EI64_V, 0x0, 0x0 }, // 3920 |
9912 | | { PseudoVLOXSEG8EI64_V_M1_MF8, VLOXSEG8EI64_V, 0x5, 0x0 }, // 3921 |
9913 | | { PseudoVLOXSEG8EI64_V_M1_MF8_MASK, VLOXSEG8EI64_V, 0x5, 0x0 }, // 3922 |
9914 | | { PseudoVLOXSEG8EI64_V_M1_MF4, VLOXSEG8EI64_V, 0x6, 0x0 }, // 3923 |
9915 | | { PseudoVLOXSEG8EI64_V_M1_MF4_MASK, VLOXSEG8EI64_V, 0x6, 0x0 }, // 3924 |
9916 | | { PseudoVLOXSEG8EI64_V_M2_MF4, VLOXSEG8EI64_V, 0x6, 0x0 }, // 3925 |
9917 | | { PseudoVLOXSEG8EI64_V_M2_MF4_MASK, VLOXSEG8EI64_V, 0x6, 0x0 }, // 3926 |
9918 | | { PseudoVLOXSEG8EI64_V_M1_MF2, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3927 |
9919 | | { PseudoVLOXSEG8EI64_V_M1_MF2_MASK, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3928 |
9920 | | { PseudoVLOXSEG8EI64_V_M2_MF2, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3929 |
9921 | | { PseudoVLOXSEG8EI64_V_M2_MF2_MASK, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3930 |
9922 | | { PseudoVLOXSEG8EI64_V_M4_MF2, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3931 |
9923 | | { PseudoVLOXSEG8EI64_V_M4_MF2_MASK, VLOXSEG8EI64_V, 0x7, 0x0 }, // 3932 |
9924 | | { PseudoVLOXSEG8EI8_V_M1_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3933 |
9925 | | { PseudoVLOXSEG8EI8_V_M1_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3934 |
9926 | | { PseudoVLOXSEG8EI8_V_MF2_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3935 |
9927 | | { PseudoVLOXSEG8EI8_V_MF2_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3936 |
9928 | | { PseudoVLOXSEG8EI8_V_MF4_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3937 |
9929 | | { PseudoVLOXSEG8EI8_V_MF4_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3938 |
9930 | | { PseudoVLOXSEG8EI8_V_MF8_M1, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3939 |
9931 | | { PseudoVLOXSEG8EI8_V_MF8_M1_MASK, VLOXSEG8EI8_V, 0x0, 0x0 }, // 3940 |
9932 | | { PseudoVLOXSEG8EI8_V_MF8_MF8, VLOXSEG8EI8_V, 0x5, 0x0 }, // 3941 |
9933 | | { PseudoVLOXSEG8EI8_V_MF8_MF8_MASK, VLOXSEG8EI8_V, 0x5, 0x0 }, // 3942 |
9934 | | { PseudoVLOXSEG8EI8_V_MF4_MF4, VLOXSEG8EI8_V, 0x6, 0x0 }, // 3943 |
9935 | | { PseudoVLOXSEG8EI8_V_MF4_MF4_MASK, VLOXSEG8EI8_V, 0x6, 0x0 }, // 3944 |
9936 | | { PseudoVLOXSEG8EI8_V_MF8_MF4, VLOXSEG8EI8_V, 0x6, 0x0 }, // 3945 |
9937 | | { PseudoVLOXSEG8EI8_V_MF8_MF4_MASK, VLOXSEG8EI8_V, 0x6, 0x0 }, // 3946 |
9938 | | { PseudoVLOXSEG8EI8_V_MF2_MF2, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3947 |
9939 | | { PseudoVLOXSEG8EI8_V_MF2_MF2_MASK, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3948 |
9940 | | { PseudoVLOXSEG8EI8_V_MF4_MF2, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3949 |
9941 | | { PseudoVLOXSEG8EI8_V_MF4_MF2_MASK, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3950 |
9942 | | { PseudoVLOXSEG8EI8_V_MF8_MF2, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3951 |
9943 | | { PseudoVLOXSEG8EI8_V_MF8_MF2_MASK, VLOXSEG8EI8_V, 0x7, 0x0 }, // 3952 |
9944 | | { PseudoVLSE16_V_M1, VLSE16_V, 0x0, 0x10 }, // 3953 |
9945 | | { PseudoVLSE16_V_M1_MASK, VLSE16_V, 0x0, 0x10 }, // 3954 |
9946 | | { PseudoVLSE16_V_M2, VLSE16_V, 0x1, 0x10 }, // 3955 |
9947 | | { PseudoVLSE16_V_M2_MASK, VLSE16_V, 0x1, 0x10 }, // 3956 |
9948 | | { PseudoVLSE16_V_M4, VLSE16_V, 0x2, 0x10 }, // 3957 |
9949 | | { PseudoVLSE16_V_M4_MASK, VLSE16_V, 0x2, 0x10 }, // 3958 |
9950 | | { PseudoVLSE16_V_M8, VLSE16_V, 0x3, 0x10 }, // 3959 |
9951 | | { PseudoVLSE16_V_M8_MASK, VLSE16_V, 0x3, 0x10 }, // 3960 |
9952 | | { PseudoVLSE16_V_MF4, VLSE16_V, 0x6, 0x10 }, // 3961 |
9953 | | { PseudoVLSE16_V_MF4_MASK, VLSE16_V, 0x6, 0x10 }, // 3962 |
9954 | | { PseudoVLSE16_V_MF2, VLSE16_V, 0x7, 0x10 }, // 3963 |
9955 | | { PseudoVLSE16_V_MF2_MASK, VLSE16_V, 0x7, 0x10 }, // 3964 |
9956 | | { PseudoVLSE32_V_M1, VLSE32_V, 0x0, 0x20 }, // 3965 |
9957 | | { PseudoVLSE32_V_M1_MASK, VLSE32_V, 0x0, 0x20 }, // 3966 |
9958 | | { PseudoVLSE32_V_M2, VLSE32_V, 0x1, 0x20 }, // 3967 |
9959 | | { PseudoVLSE32_V_M2_MASK, VLSE32_V, 0x1, 0x20 }, // 3968 |
9960 | | { PseudoVLSE32_V_M4, VLSE32_V, 0x2, 0x20 }, // 3969 |
9961 | | { PseudoVLSE32_V_M4_MASK, VLSE32_V, 0x2, 0x20 }, // 3970 |
9962 | | { PseudoVLSE32_V_M8, VLSE32_V, 0x3, 0x20 }, // 3971 |
9963 | | { PseudoVLSE32_V_M8_MASK, VLSE32_V, 0x3, 0x20 }, // 3972 |
9964 | | { PseudoVLSE32_V_MF2, VLSE32_V, 0x7, 0x20 }, // 3973 |
9965 | | { PseudoVLSE32_V_MF2_MASK, VLSE32_V, 0x7, 0x20 }, // 3974 |
9966 | | { PseudoVLSE64_V_M1, VLSE64_V, 0x0, 0x40 }, // 3975 |
9967 | | { PseudoVLSE64_V_M1_MASK, VLSE64_V, 0x0, 0x40 }, // 3976 |
9968 | | { PseudoVLSE64_V_M2, VLSE64_V, 0x1, 0x40 }, // 3977 |
9969 | | { PseudoVLSE64_V_M2_MASK, VLSE64_V, 0x1, 0x40 }, // 3978 |
9970 | | { PseudoVLSE64_V_M4, VLSE64_V, 0x2, 0x40 }, // 3979 |
9971 | | { PseudoVLSE64_V_M4_MASK, VLSE64_V, 0x2, 0x40 }, // 3980 |
9972 | | { PseudoVLSE64_V_M8, VLSE64_V, 0x3, 0x40 }, // 3981 |
9973 | | { PseudoVLSE64_V_M8_MASK, VLSE64_V, 0x3, 0x40 }, // 3982 |
9974 | | { PseudoVLSE8_V_M1, VLSE8_V, 0x0, 0x8 }, // 3983 |
9975 | | { PseudoVLSE8_V_M1_MASK, VLSE8_V, 0x0, 0x8 }, // 3984 |
9976 | | { PseudoVLSE8_V_M2, VLSE8_V, 0x1, 0x8 }, // 3985 |
9977 | | { PseudoVLSE8_V_M2_MASK, VLSE8_V, 0x1, 0x8 }, // 3986 |
9978 | | { PseudoVLSE8_V_M4, VLSE8_V, 0x2, 0x8 }, // 3987 |
9979 | | { PseudoVLSE8_V_M4_MASK, VLSE8_V, 0x2, 0x8 }, // 3988 |
9980 | | { PseudoVLSE8_V_M8, VLSE8_V, 0x3, 0x8 }, // 3989 |
9981 | | { PseudoVLSE8_V_M8_MASK, VLSE8_V, 0x3, 0x8 }, // 3990 |
9982 | | { PseudoVLSE8_V_MF8, VLSE8_V, 0x5, 0x8 }, // 3991 |
9983 | | { PseudoVLSE8_V_MF8_MASK, VLSE8_V, 0x5, 0x8 }, // 3992 |
9984 | | { PseudoVLSE8_V_MF4, VLSE8_V, 0x6, 0x8 }, // 3993 |
9985 | | { PseudoVLSE8_V_MF4_MASK, VLSE8_V, 0x6, 0x8 }, // 3994 |
9986 | | { PseudoVLSE8_V_MF2, VLSE8_V, 0x7, 0x8 }, // 3995 |
9987 | | { PseudoVLSE8_V_MF2_MASK, VLSE8_V, 0x7, 0x8 }, // 3996 |
9988 | | { PseudoVLSEG2E16FF_V_M1, VLSEG2E16FF_V, 0x0, 0x10 }, // 3997 |
9989 | | { PseudoVLSEG2E16FF_V_M1_MASK, VLSEG2E16FF_V, 0x0, 0x10 }, // 3998 |
9990 | | { PseudoVLSEG2E16FF_V_M2, VLSEG2E16FF_V, 0x1, 0x10 }, // 3999 |
9991 | | { PseudoVLSEG2E16FF_V_M2_MASK, VLSEG2E16FF_V, 0x1, 0x10 }, // 4000 |
9992 | | { PseudoVLSEG2E16FF_V_M4, VLSEG2E16FF_V, 0x2, 0x10 }, // 4001 |
9993 | | { PseudoVLSEG2E16FF_V_M4_MASK, VLSEG2E16FF_V, 0x2, 0x10 }, // 4002 |
9994 | | { PseudoVLSEG2E16FF_V_MF4, VLSEG2E16FF_V, 0x6, 0x10 }, // 4003 |
9995 | | { PseudoVLSEG2E16FF_V_MF4_MASK, VLSEG2E16FF_V, 0x6, 0x10 }, // 4004 |
9996 | | { PseudoVLSEG2E16FF_V_MF2, VLSEG2E16FF_V, 0x7, 0x10 }, // 4005 |
9997 | | { PseudoVLSEG2E16FF_V_MF2_MASK, VLSEG2E16FF_V, 0x7, 0x10 }, // 4006 |
9998 | | { PseudoVLSEG2E16_V_M1, VLSEG2E16_V, 0x0, 0x10 }, // 4007 |
9999 | | { PseudoVLSEG2E16_V_M1_MASK, VLSEG2E16_V, 0x0, 0x10 }, // 4008 |
10000 | | { PseudoVLSEG2E16_V_M2, VLSEG2E16_V, 0x1, 0x10 }, // 4009 |
10001 | | { PseudoVLSEG2E16_V_M2_MASK, VLSEG2E16_V, 0x1, 0x10 }, // 4010 |
10002 | | { PseudoVLSEG2E16_V_M4, VLSEG2E16_V, 0x2, 0x10 }, // 4011 |
10003 | | { PseudoVLSEG2E16_V_M4_MASK, VLSEG2E16_V, 0x2, 0x10 }, // 4012 |
10004 | | { PseudoVLSEG2E16_V_MF4, VLSEG2E16_V, 0x6, 0x10 }, // 4013 |
10005 | | { PseudoVLSEG2E16_V_MF4_MASK, VLSEG2E16_V, 0x6, 0x10 }, // 4014 |
10006 | | { PseudoVLSEG2E16_V_MF2, VLSEG2E16_V, 0x7, 0x10 }, // 4015 |
10007 | | { PseudoVLSEG2E16_V_MF2_MASK, VLSEG2E16_V, 0x7, 0x10 }, // 4016 |
10008 | | { PseudoVLSEG2E32FF_V_M1, VLSEG2E32FF_V, 0x0, 0x20 }, // 4017 |
10009 | | { PseudoVLSEG2E32FF_V_M1_MASK, VLSEG2E32FF_V, 0x0, 0x20 }, // 4018 |
10010 | | { PseudoVLSEG2E32FF_V_M2, VLSEG2E32FF_V, 0x1, 0x20 }, // 4019 |
10011 | | { PseudoVLSEG2E32FF_V_M2_MASK, VLSEG2E32FF_V, 0x1, 0x20 }, // 4020 |
10012 | | { PseudoVLSEG2E32FF_V_M4, VLSEG2E32FF_V, 0x2, 0x20 }, // 4021 |
10013 | | { PseudoVLSEG2E32FF_V_M4_MASK, VLSEG2E32FF_V, 0x2, 0x20 }, // 4022 |
10014 | | { PseudoVLSEG2E32FF_V_MF2, VLSEG2E32FF_V, 0x7, 0x20 }, // 4023 |
10015 | | { PseudoVLSEG2E32FF_V_MF2_MASK, VLSEG2E32FF_V, 0x7, 0x20 }, // 4024 |
10016 | | { PseudoVLSEG2E32_V_M1, VLSEG2E32_V, 0x0, 0x20 }, // 4025 |
10017 | | { PseudoVLSEG2E32_V_M1_MASK, VLSEG2E32_V, 0x0, 0x20 }, // 4026 |
10018 | | { PseudoVLSEG2E32_V_M2, VLSEG2E32_V, 0x1, 0x20 }, // 4027 |
10019 | | { PseudoVLSEG2E32_V_M2_MASK, VLSEG2E32_V, 0x1, 0x20 }, // 4028 |
10020 | | { PseudoVLSEG2E32_V_M4, VLSEG2E32_V, 0x2, 0x20 }, // 4029 |
10021 | | { PseudoVLSEG2E32_V_M4_MASK, VLSEG2E32_V, 0x2, 0x20 }, // 4030 |
10022 | | { PseudoVLSEG2E32_V_MF2, VLSEG2E32_V, 0x7, 0x20 }, // 4031 |
10023 | | { PseudoVLSEG2E32_V_MF2_MASK, VLSEG2E32_V, 0x7, 0x20 }, // 4032 |
10024 | | { PseudoVLSEG2E64FF_V_M1, VLSEG2E64FF_V, 0x0, 0x40 }, // 4033 |
10025 | | { PseudoVLSEG2E64FF_V_M1_MASK, VLSEG2E64FF_V, 0x0, 0x40 }, // 4034 |
10026 | | { PseudoVLSEG2E64FF_V_M2, VLSEG2E64FF_V, 0x1, 0x40 }, // 4035 |
10027 | | { PseudoVLSEG2E64FF_V_M2_MASK, VLSEG2E64FF_V, 0x1, 0x40 }, // 4036 |
10028 | | { PseudoVLSEG2E64FF_V_M4, VLSEG2E64FF_V, 0x2, 0x40 }, // 4037 |
10029 | | { PseudoVLSEG2E64FF_V_M4_MASK, VLSEG2E64FF_V, 0x2, 0x40 }, // 4038 |
10030 | | { PseudoVLSEG2E64_V_M1, VLSEG2E64_V, 0x0, 0x40 }, // 4039 |
10031 | | { PseudoVLSEG2E64_V_M1_MASK, VLSEG2E64_V, 0x0, 0x40 }, // 4040 |
10032 | | { PseudoVLSEG2E64_V_M2, VLSEG2E64_V, 0x1, 0x40 }, // 4041 |
10033 | | { PseudoVLSEG2E64_V_M2_MASK, VLSEG2E64_V, 0x1, 0x40 }, // 4042 |
10034 | | { PseudoVLSEG2E64_V_M4, VLSEG2E64_V, 0x2, 0x40 }, // 4043 |
10035 | | { PseudoVLSEG2E64_V_M4_MASK, VLSEG2E64_V, 0x2, 0x40 }, // 4044 |
10036 | | { PseudoVLSEG2E8FF_V_M1, VLSEG2E8FF_V, 0x0, 0x8 }, // 4045 |
10037 | | { PseudoVLSEG2E8FF_V_M1_MASK, VLSEG2E8FF_V, 0x0, 0x8 }, // 4046 |
10038 | | { PseudoVLSEG2E8FF_V_M2, VLSEG2E8FF_V, 0x1, 0x8 }, // 4047 |
10039 | | { PseudoVLSEG2E8FF_V_M2_MASK, VLSEG2E8FF_V, 0x1, 0x8 }, // 4048 |
10040 | | { PseudoVLSEG2E8FF_V_M4, VLSEG2E8FF_V, 0x2, 0x8 }, // 4049 |
10041 | | { PseudoVLSEG2E8FF_V_M4_MASK, VLSEG2E8FF_V, 0x2, 0x8 }, // 4050 |
10042 | | { PseudoVLSEG2E8FF_V_MF8, VLSEG2E8FF_V, 0x5, 0x8 }, // 4051 |
10043 | | { PseudoVLSEG2E8FF_V_MF8_MASK, VLSEG2E8FF_V, 0x5, 0x8 }, // 4052 |
10044 | | { PseudoVLSEG2E8FF_V_MF4, VLSEG2E8FF_V, 0x6, 0x8 }, // 4053 |
10045 | | { PseudoVLSEG2E8FF_V_MF4_MASK, VLSEG2E8FF_V, 0x6, 0x8 }, // 4054 |
10046 | | { PseudoVLSEG2E8FF_V_MF2, VLSEG2E8FF_V, 0x7, 0x8 }, // 4055 |
10047 | | { PseudoVLSEG2E8FF_V_MF2_MASK, VLSEG2E8FF_V, 0x7, 0x8 }, // 4056 |
10048 | | { PseudoVLSEG2E8_V_M1, VLSEG2E8_V, 0x0, 0x8 }, // 4057 |
10049 | | { PseudoVLSEG2E8_V_M1_MASK, VLSEG2E8_V, 0x0, 0x8 }, // 4058 |
10050 | | { PseudoVLSEG2E8_V_M2, VLSEG2E8_V, 0x1, 0x8 }, // 4059 |
10051 | | { PseudoVLSEG2E8_V_M2_MASK, VLSEG2E8_V, 0x1, 0x8 }, // 4060 |
10052 | | { PseudoVLSEG2E8_V_M4, VLSEG2E8_V, 0x2, 0x8 }, // 4061 |
10053 | | { PseudoVLSEG2E8_V_M4_MASK, VLSEG2E8_V, 0x2, 0x8 }, // 4062 |
10054 | | { PseudoVLSEG2E8_V_MF8, VLSEG2E8_V, 0x5, 0x8 }, // 4063 |
10055 | | { PseudoVLSEG2E8_V_MF8_MASK, VLSEG2E8_V, 0x5, 0x8 }, // 4064 |
10056 | | { PseudoVLSEG2E8_V_MF4, VLSEG2E8_V, 0x6, 0x8 }, // 4065 |
10057 | | { PseudoVLSEG2E8_V_MF4_MASK, VLSEG2E8_V, 0x6, 0x8 }, // 4066 |
10058 | | { PseudoVLSEG2E8_V_MF2, VLSEG2E8_V, 0x7, 0x8 }, // 4067 |
10059 | | { PseudoVLSEG2E8_V_MF2_MASK, VLSEG2E8_V, 0x7, 0x8 }, // 4068 |
10060 | | { PseudoVLSEG3E16FF_V_M1, VLSEG3E16FF_V, 0x0, 0x10 }, // 4069 |
10061 | | { PseudoVLSEG3E16FF_V_M1_MASK, VLSEG3E16FF_V, 0x0, 0x10 }, // 4070 |
10062 | | { PseudoVLSEG3E16FF_V_M2, VLSEG3E16FF_V, 0x1, 0x10 }, // 4071 |
10063 | | { PseudoVLSEG3E16FF_V_M2_MASK, VLSEG3E16FF_V, 0x1, 0x10 }, // 4072 |
10064 | | { PseudoVLSEG3E16FF_V_MF4, VLSEG3E16FF_V, 0x6, 0x10 }, // 4073 |
10065 | | { PseudoVLSEG3E16FF_V_MF4_MASK, VLSEG3E16FF_V, 0x6, 0x10 }, // 4074 |
10066 | | { PseudoVLSEG3E16FF_V_MF2, VLSEG3E16FF_V, 0x7, 0x10 }, // 4075 |
10067 | | { PseudoVLSEG3E16FF_V_MF2_MASK, VLSEG3E16FF_V, 0x7, 0x10 }, // 4076 |
10068 | | { PseudoVLSEG3E16_V_M1, VLSEG3E16_V, 0x0, 0x10 }, // 4077 |
10069 | | { PseudoVLSEG3E16_V_M1_MASK, VLSEG3E16_V, 0x0, 0x10 }, // 4078 |
10070 | | { PseudoVLSEG3E16_V_M2, VLSEG3E16_V, 0x1, 0x10 }, // 4079 |
10071 | | { PseudoVLSEG3E16_V_M2_MASK, VLSEG3E16_V, 0x1, 0x10 }, // 4080 |
10072 | | { PseudoVLSEG3E16_V_MF4, VLSEG3E16_V, 0x6, 0x10 }, // 4081 |
10073 | | { PseudoVLSEG3E16_V_MF4_MASK, VLSEG3E16_V, 0x6, 0x10 }, // 4082 |
10074 | | { PseudoVLSEG3E16_V_MF2, VLSEG3E16_V, 0x7, 0x10 }, // 4083 |
10075 | | { PseudoVLSEG3E16_V_MF2_MASK, VLSEG3E16_V, 0x7, 0x10 }, // 4084 |
10076 | | { PseudoVLSEG3E32FF_V_M1, VLSEG3E32FF_V, 0x0, 0x20 }, // 4085 |
10077 | | { PseudoVLSEG3E32FF_V_M1_MASK, VLSEG3E32FF_V, 0x0, 0x20 }, // 4086 |
10078 | | { PseudoVLSEG3E32FF_V_M2, VLSEG3E32FF_V, 0x1, 0x20 }, // 4087 |
10079 | | { PseudoVLSEG3E32FF_V_M2_MASK, VLSEG3E32FF_V, 0x1, 0x20 }, // 4088 |
10080 | | { PseudoVLSEG3E32FF_V_MF2, VLSEG3E32FF_V, 0x7, 0x20 }, // 4089 |
10081 | | { PseudoVLSEG3E32FF_V_MF2_MASK, VLSEG3E32FF_V, 0x7, 0x20 }, // 4090 |
10082 | | { PseudoVLSEG3E32_V_M1, VLSEG3E32_V, 0x0, 0x20 }, // 4091 |
10083 | | { PseudoVLSEG3E32_V_M1_MASK, VLSEG3E32_V, 0x0, 0x20 }, // 4092 |
10084 | | { PseudoVLSEG3E32_V_M2, VLSEG3E32_V, 0x1, 0x20 }, // 4093 |
10085 | | { PseudoVLSEG3E32_V_M2_MASK, VLSEG3E32_V, 0x1, 0x20 }, // 4094 |
10086 | | { PseudoVLSEG3E32_V_MF2, VLSEG3E32_V, 0x7, 0x20 }, // 4095 |
10087 | | { PseudoVLSEG3E32_V_MF2_MASK, VLSEG3E32_V, 0x7, 0x20 }, // 4096 |
10088 | | { PseudoVLSEG3E64FF_V_M1, VLSEG3E64FF_V, 0x0, 0x40 }, // 4097 |
10089 | | { PseudoVLSEG3E64FF_V_M1_MASK, VLSEG3E64FF_V, 0x0, 0x40 }, // 4098 |
10090 | | { PseudoVLSEG3E64FF_V_M2, VLSEG3E64FF_V, 0x1, 0x40 }, // 4099 |
10091 | | { PseudoVLSEG3E64FF_V_M2_MASK, VLSEG3E64FF_V, 0x1, 0x40 }, // 4100 |
10092 | | { PseudoVLSEG3E64_V_M1, VLSEG3E64_V, 0x0, 0x40 }, // 4101 |
10093 | | { PseudoVLSEG3E64_V_M1_MASK, VLSEG3E64_V, 0x0, 0x40 }, // 4102 |
10094 | | { PseudoVLSEG3E64_V_M2, VLSEG3E64_V, 0x1, 0x40 }, // 4103 |
10095 | | { PseudoVLSEG3E64_V_M2_MASK, VLSEG3E64_V, 0x1, 0x40 }, // 4104 |
10096 | | { PseudoVLSEG3E8FF_V_M1, VLSEG3E8FF_V, 0x0, 0x8 }, // 4105 |
10097 | | { PseudoVLSEG3E8FF_V_M1_MASK, VLSEG3E8FF_V, 0x0, 0x8 }, // 4106 |
10098 | | { PseudoVLSEG3E8FF_V_M2, VLSEG3E8FF_V, 0x1, 0x8 }, // 4107 |
10099 | | { PseudoVLSEG3E8FF_V_M2_MASK, VLSEG3E8FF_V, 0x1, 0x8 }, // 4108 |
10100 | | { PseudoVLSEG3E8FF_V_MF8, VLSEG3E8FF_V, 0x5, 0x8 }, // 4109 |
10101 | | { PseudoVLSEG3E8FF_V_MF8_MASK, VLSEG3E8FF_V, 0x5, 0x8 }, // 4110 |
10102 | | { PseudoVLSEG3E8FF_V_MF4, VLSEG3E8FF_V, 0x6, 0x8 }, // 4111 |
10103 | | { PseudoVLSEG3E8FF_V_MF4_MASK, VLSEG3E8FF_V, 0x6, 0x8 }, // 4112 |
10104 | | { PseudoVLSEG3E8FF_V_MF2, VLSEG3E8FF_V, 0x7, 0x8 }, // 4113 |
10105 | | { PseudoVLSEG3E8FF_V_MF2_MASK, VLSEG3E8FF_V, 0x7, 0x8 }, // 4114 |
10106 | | { PseudoVLSEG3E8_V_M1, VLSEG3E8_V, 0x0, 0x8 }, // 4115 |
10107 | | { PseudoVLSEG3E8_V_M1_MASK, VLSEG3E8_V, 0x0, 0x8 }, // 4116 |
10108 | | { PseudoVLSEG3E8_V_M2, VLSEG3E8_V, 0x1, 0x8 }, // 4117 |
10109 | | { PseudoVLSEG3E8_V_M2_MASK, VLSEG3E8_V, 0x1, 0x8 }, // 4118 |
10110 | | { PseudoVLSEG3E8_V_MF8, VLSEG3E8_V, 0x5, 0x8 }, // 4119 |
10111 | | { PseudoVLSEG3E8_V_MF8_MASK, VLSEG3E8_V, 0x5, 0x8 }, // 4120 |
10112 | | { PseudoVLSEG3E8_V_MF4, VLSEG3E8_V, 0x6, 0x8 }, // 4121 |
10113 | | { PseudoVLSEG3E8_V_MF4_MASK, VLSEG3E8_V, 0x6, 0x8 }, // 4122 |
10114 | | { PseudoVLSEG3E8_V_MF2, VLSEG3E8_V, 0x7, 0x8 }, // 4123 |
10115 | | { PseudoVLSEG3E8_V_MF2_MASK, VLSEG3E8_V, 0x7, 0x8 }, // 4124 |
10116 | | { PseudoVLSEG4E16FF_V_M1, VLSEG4E16FF_V, 0x0, 0x10 }, // 4125 |
10117 | | { PseudoVLSEG4E16FF_V_M1_MASK, VLSEG4E16FF_V, 0x0, 0x10 }, // 4126 |
10118 | | { PseudoVLSEG4E16FF_V_M2, VLSEG4E16FF_V, 0x1, 0x10 }, // 4127 |
10119 | | { PseudoVLSEG4E16FF_V_M2_MASK, VLSEG4E16FF_V, 0x1, 0x10 }, // 4128 |
10120 | | { PseudoVLSEG4E16FF_V_MF4, VLSEG4E16FF_V, 0x6, 0x10 }, // 4129 |
10121 | | { PseudoVLSEG4E16FF_V_MF4_MASK, VLSEG4E16FF_V, 0x6, 0x10 }, // 4130 |
10122 | | { PseudoVLSEG4E16FF_V_MF2, VLSEG4E16FF_V, 0x7, 0x10 }, // 4131 |
10123 | | { PseudoVLSEG4E16FF_V_MF2_MASK, VLSEG4E16FF_V, 0x7, 0x10 }, // 4132 |
10124 | | { PseudoVLSEG4E16_V_M1, VLSEG4E16_V, 0x0, 0x10 }, // 4133 |
10125 | | { PseudoVLSEG4E16_V_M1_MASK, VLSEG4E16_V, 0x0, 0x10 }, // 4134 |
10126 | | { PseudoVLSEG4E16_V_M2, VLSEG4E16_V, 0x1, 0x10 }, // 4135 |
10127 | | { PseudoVLSEG4E16_V_M2_MASK, VLSEG4E16_V, 0x1, 0x10 }, // 4136 |
10128 | | { PseudoVLSEG4E16_V_MF4, VLSEG4E16_V, 0x6, 0x10 }, // 4137 |
10129 | | { PseudoVLSEG4E16_V_MF4_MASK, VLSEG4E16_V, 0x6, 0x10 }, // 4138 |
10130 | | { PseudoVLSEG4E16_V_MF2, VLSEG4E16_V, 0x7, 0x10 }, // 4139 |
10131 | | { PseudoVLSEG4E16_V_MF2_MASK, VLSEG4E16_V, 0x7, 0x10 }, // 4140 |
10132 | | { PseudoVLSEG4E32FF_V_M1, VLSEG4E32FF_V, 0x0, 0x20 }, // 4141 |
10133 | | { PseudoVLSEG4E32FF_V_M1_MASK, VLSEG4E32FF_V, 0x0, 0x20 }, // 4142 |
10134 | | { PseudoVLSEG4E32FF_V_M2, VLSEG4E32FF_V, 0x1, 0x20 }, // 4143 |
10135 | | { PseudoVLSEG4E32FF_V_M2_MASK, VLSEG4E32FF_V, 0x1, 0x20 }, // 4144 |
10136 | | { PseudoVLSEG4E32FF_V_MF2, VLSEG4E32FF_V, 0x7, 0x20 }, // 4145 |
10137 | | { PseudoVLSEG4E32FF_V_MF2_MASK, VLSEG4E32FF_V, 0x7, 0x20 }, // 4146 |
10138 | | { PseudoVLSEG4E32_V_M1, VLSEG4E32_V, 0x0, 0x20 }, // 4147 |
10139 | | { PseudoVLSEG4E32_V_M1_MASK, VLSEG4E32_V, 0x0, 0x20 }, // 4148 |
10140 | | { PseudoVLSEG4E32_V_M2, VLSEG4E32_V, 0x1, 0x20 }, // 4149 |
10141 | | { PseudoVLSEG4E32_V_M2_MASK, VLSEG4E32_V, 0x1, 0x20 }, // 4150 |
10142 | | { PseudoVLSEG4E32_V_MF2, VLSEG4E32_V, 0x7, 0x20 }, // 4151 |
10143 | | { PseudoVLSEG4E32_V_MF2_MASK, VLSEG4E32_V, 0x7, 0x20 }, // 4152 |
10144 | | { PseudoVLSEG4E64FF_V_M1, VLSEG4E64FF_V, 0x0, 0x40 }, // 4153 |
10145 | | { PseudoVLSEG4E64FF_V_M1_MASK, VLSEG4E64FF_V, 0x0, 0x40 }, // 4154 |
10146 | | { PseudoVLSEG4E64FF_V_M2, VLSEG4E64FF_V, 0x1, 0x40 }, // 4155 |
10147 | | { PseudoVLSEG4E64FF_V_M2_MASK, VLSEG4E64FF_V, 0x1, 0x40 }, // 4156 |
10148 | | { PseudoVLSEG4E64_V_M1, VLSEG4E64_V, 0x0, 0x40 }, // 4157 |
10149 | | { PseudoVLSEG4E64_V_M1_MASK, VLSEG4E64_V, 0x0, 0x40 }, // 4158 |
10150 | | { PseudoVLSEG4E64_V_M2, VLSEG4E64_V, 0x1, 0x40 }, // 4159 |
10151 | | { PseudoVLSEG4E64_V_M2_MASK, VLSEG4E64_V, 0x1, 0x40 }, // 4160 |
10152 | | { PseudoVLSEG4E8FF_V_M1, VLSEG4E8FF_V, 0x0, 0x8 }, // 4161 |
10153 | | { PseudoVLSEG4E8FF_V_M1_MASK, VLSEG4E8FF_V, 0x0, 0x8 }, // 4162 |
10154 | | { PseudoVLSEG4E8FF_V_M2, VLSEG4E8FF_V, 0x1, 0x8 }, // 4163 |
10155 | | { PseudoVLSEG4E8FF_V_M2_MASK, VLSEG4E8FF_V, 0x1, 0x8 }, // 4164 |
10156 | | { PseudoVLSEG4E8FF_V_MF8, VLSEG4E8FF_V, 0x5, 0x8 }, // 4165 |
10157 | | { PseudoVLSEG4E8FF_V_MF8_MASK, VLSEG4E8FF_V, 0x5, 0x8 }, // 4166 |
10158 | | { PseudoVLSEG4E8FF_V_MF4, VLSEG4E8FF_V, 0x6, 0x8 }, // 4167 |
10159 | | { PseudoVLSEG4E8FF_V_MF4_MASK, VLSEG4E8FF_V, 0x6, 0x8 }, // 4168 |
10160 | | { PseudoVLSEG4E8FF_V_MF2, VLSEG4E8FF_V, 0x7, 0x8 }, // 4169 |
10161 | | { PseudoVLSEG4E8FF_V_MF2_MASK, VLSEG4E8FF_V, 0x7, 0x8 }, // 4170 |
10162 | | { PseudoVLSEG4E8_V_M1, VLSEG4E8_V, 0x0, 0x8 }, // 4171 |
10163 | | { PseudoVLSEG4E8_V_M1_MASK, VLSEG4E8_V, 0x0, 0x8 }, // 4172 |
10164 | | { PseudoVLSEG4E8_V_M2, VLSEG4E8_V, 0x1, 0x8 }, // 4173 |
10165 | | { PseudoVLSEG4E8_V_M2_MASK, VLSEG4E8_V, 0x1, 0x8 }, // 4174 |
10166 | | { PseudoVLSEG4E8_V_MF8, VLSEG4E8_V, 0x5, 0x8 }, // 4175 |
10167 | | { PseudoVLSEG4E8_V_MF8_MASK, VLSEG4E8_V, 0x5, 0x8 }, // 4176 |
10168 | | { PseudoVLSEG4E8_V_MF4, VLSEG4E8_V, 0x6, 0x8 }, // 4177 |
10169 | | { PseudoVLSEG4E8_V_MF4_MASK, VLSEG4E8_V, 0x6, 0x8 }, // 4178 |
10170 | | { PseudoVLSEG4E8_V_MF2, VLSEG4E8_V, 0x7, 0x8 }, // 4179 |
10171 | | { PseudoVLSEG4E8_V_MF2_MASK, VLSEG4E8_V, 0x7, 0x8 }, // 4180 |
10172 | | { PseudoVLSEG5E16FF_V_M1, VLSEG5E16FF_V, 0x0, 0x10 }, // 4181 |
10173 | | { PseudoVLSEG5E16FF_V_M1_MASK, VLSEG5E16FF_V, 0x0, 0x10 }, // 4182 |
10174 | | { PseudoVLSEG5E16FF_V_MF4, VLSEG5E16FF_V, 0x6, 0x10 }, // 4183 |
10175 | | { PseudoVLSEG5E16FF_V_MF4_MASK, VLSEG5E16FF_V, 0x6, 0x10 }, // 4184 |
10176 | | { PseudoVLSEG5E16FF_V_MF2, VLSEG5E16FF_V, 0x7, 0x10 }, // 4185 |
10177 | | { PseudoVLSEG5E16FF_V_MF2_MASK, VLSEG5E16FF_V, 0x7, 0x10 }, // 4186 |
10178 | | { PseudoVLSEG5E16_V_M1, VLSEG5E16_V, 0x0, 0x10 }, // 4187 |
10179 | | { PseudoVLSEG5E16_V_M1_MASK, VLSEG5E16_V, 0x0, 0x10 }, // 4188 |
10180 | | { PseudoVLSEG5E16_V_MF4, VLSEG5E16_V, 0x6, 0x10 }, // 4189 |
10181 | | { PseudoVLSEG5E16_V_MF4_MASK, VLSEG5E16_V, 0x6, 0x10 }, // 4190 |
10182 | | { PseudoVLSEG5E16_V_MF2, VLSEG5E16_V, 0x7, 0x10 }, // 4191 |
10183 | | { PseudoVLSEG5E16_V_MF2_MASK, VLSEG5E16_V, 0x7, 0x10 }, // 4192 |
10184 | | { PseudoVLSEG5E32FF_V_M1, VLSEG5E32FF_V, 0x0, 0x20 }, // 4193 |
10185 | | { PseudoVLSEG5E32FF_V_M1_MASK, VLSEG5E32FF_V, 0x0, 0x20 }, // 4194 |
10186 | | { PseudoVLSEG5E32FF_V_MF2, VLSEG5E32FF_V, 0x7, 0x20 }, // 4195 |
10187 | | { PseudoVLSEG5E32FF_V_MF2_MASK, VLSEG5E32FF_V, 0x7, 0x20 }, // 4196 |
10188 | | { PseudoVLSEG5E32_V_M1, VLSEG5E32_V, 0x0, 0x20 }, // 4197 |
10189 | | { PseudoVLSEG5E32_V_M1_MASK, VLSEG5E32_V, 0x0, 0x20 }, // 4198 |
10190 | | { PseudoVLSEG5E32_V_MF2, VLSEG5E32_V, 0x7, 0x20 }, // 4199 |
10191 | | { PseudoVLSEG5E32_V_MF2_MASK, VLSEG5E32_V, 0x7, 0x20 }, // 4200 |
10192 | | { PseudoVLSEG5E64FF_V_M1, VLSEG5E64FF_V, 0x0, 0x40 }, // 4201 |
10193 | | { PseudoVLSEG5E64FF_V_M1_MASK, VLSEG5E64FF_V, 0x0, 0x40 }, // 4202 |
10194 | | { PseudoVLSEG5E64_V_M1, VLSEG5E64_V, 0x0, 0x40 }, // 4203 |
10195 | | { PseudoVLSEG5E64_V_M1_MASK, VLSEG5E64_V, 0x0, 0x40 }, // 4204 |
10196 | | { PseudoVLSEG5E8FF_V_M1, VLSEG5E8FF_V, 0x0, 0x8 }, // 4205 |
10197 | | { PseudoVLSEG5E8FF_V_M1_MASK, VLSEG5E8FF_V, 0x0, 0x8 }, // 4206 |
10198 | | { PseudoVLSEG5E8FF_V_MF8, VLSEG5E8FF_V, 0x5, 0x8 }, // 4207 |
10199 | | { PseudoVLSEG5E8FF_V_MF8_MASK, VLSEG5E8FF_V, 0x5, 0x8 }, // 4208 |
10200 | | { PseudoVLSEG5E8FF_V_MF4, VLSEG5E8FF_V, 0x6, 0x8 }, // 4209 |
10201 | | { PseudoVLSEG5E8FF_V_MF4_MASK, VLSEG5E8FF_V, 0x6, 0x8 }, // 4210 |
10202 | | { PseudoVLSEG5E8FF_V_MF2, VLSEG5E8FF_V, 0x7, 0x8 }, // 4211 |
10203 | | { PseudoVLSEG5E8FF_V_MF2_MASK, VLSEG5E8FF_V, 0x7, 0x8 }, // 4212 |
10204 | | { PseudoVLSEG5E8_V_M1, VLSEG5E8_V, 0x0, 0x8 }, // 4213 |
10205 | | { PseudoVLSEG5E8_V_M1_MASK, VLSEG5E8_V, 0x0, 0x8 }, // 4214 |
10206 | | { PseudoVLSEG5E8_V_MF8, VLSEG5E8_V, 0x5, 0x8 }, // 4215 |
10207 | | { PseudoVLSEG5E8_V_MF8_MASK, VLSEG5E8_V, 0x5, 0x8 }, // 4216 |
10208 | | { PseudoVLSEG5E8_V_MF4, VLSEG5E8_V, 0x6, 0x8 }, // 4217 |
10209 | | { PseudoVLSEG5E8_V_MF4_MASK, VLSEG5E8_V, 0x6, 0x8 }, // 4218 |
10210 | | { PseudoVLSEG5E8_V_MF2, VLSEG5E8_V, 0x7, 0x8 }, // 4219 |
10211 | | { PseudoVLSEG5E8_V_MF2_MASK, VLSEG5E8_V, 0x7, 0x8 }, // 4220 |
10212 | | { PseudoVLSEG6E16FF_V_M1, VLSEG6E16FF_V, 0x0, 0x10 }, // 4221 |
10213 | | { PseudoVLSEG6E16FF_V_M1_MASK, VLSEG6E16FF_V, 0x0, 0x10 }, // 4222 |
10214 | | { PseudoVLSEG6E16FF_V_MF4, VLSEG6E16FF_V, 0x6, 0x10 }, // 4223 |
10215 | | { PseudoVLSEG6E16FF_V_MF4_MASK, VLSEG6E16FF_V, 0x6, 0x10 }, // 4224 |
10216 | | { PseudoVLSEG6E16FF_V_MF2, VLSEG6E16FF_V, 0x7, 0x10 }, // 4225 |
10217 | | { PseudoVLSEG6E16FF_V_MF2_MASK, VLSEG6E16FF_V, 0x7, 0x10 }, // 4226 |
10218 | | { PseudoVLSEG6E16_V_M1, VLSEG6E16_V, 0x0, 0x10 }, // 4227 |
10219 | | { PseudoVLSEG6E16_V_M1_MASK, VLSEG6E16_V, 0x0, 0x10 }, // 4228 |
10220 | | { PseudoVLSEG6E16_V_MF4, VLSEG6E16_V, 0x6, 0x10 }, // 4229 |
10221 | | { PseudoVLSEG6E16_V_MF4_MASK, VLSEG6E16_V, 0x6, 0x10 }, // 4230 |
10222 | | { PseudoVLSEG6E16_V_MF2, VLSEG6E16_V, 0x7, 0x10 }, // 4231 |
10223 | | { PseudoVLSEG6E16_V_MF2_MASK, VLSEG6E16_V, 0x7, 0x10 }, // 4232 |
10224 | | { PseudoVLSEG6E32FF_V_M1, VLSEG6E32FF_V, 0x0, 0x20 }, // 4233 |
10225 | | { PseudoVLSEG6E32FF_V_M1_MASK, VLSEG6E32FF_V, 0x0, 0x20 }, // 4234 |
10226 | | { PseudoVLSEG6E32FF_V_MF2, VLSEG6E32FF_V, 0x7, 0x20 }, // 4235 |
10227 | | { PseudoVLSEG6E32FF_V_MF2_MASK, VLSEG6E32FF_V, 0x7, 0x20 }, // 4236 |
10228 | | { PseudoVLSEG6E32_V_M1, VLSEG6E32_V, 0x0, 0x20 }, // 4237 |
10229 | | { PseudoVLSEG6E32_V_M1_MASK, VLSEG6E32_V, 0x0, 0x20 }, // 4238 |
10230 | | { PseudoVLSEG6E32_V_MF2, VLSEG6E32_V, 0x7, 0x20 }, // 4239 |
10231 | | { PseudoVLSEG6E32_V_MF2_MASK, VLSEG6E32_V, 0x7, 0x20 }, // 4240 |
10232 | | { PseudoVLSEG6E64FF_V_M1, VLSEG6E64FF_V, 0x0, 0x40 }, // 4241 |
10233 | | { PseudoVLSEG6E64FF_V_M1_MASK, VLSEG6E64FF_V, 0x0, 0x40 }, // 4242 |
10234 | | { PseudoVLSEG6E64_V_M1, VLSEG6E64_V, 0x0, 0x40 }, // 4243 |
10235 | | { PseudoVLSEG6E64_V_M1_MASK, VLSEG6E64_V, 0x0, 0x40 }, // 4244 |
10236 | | { PseudoVLSEG6E8FF_V_M1, VLSEG6E8FF_V, 0x0, 0x8 }, // 4245 |
10237 | | { PseudoVLSEG6E8FF_V_M1_MASK, VLSEG6E8FF_V, 0x0, 0x8 }, // 4246 |
10238 | | { PseudoVLSEG6E8FF_V_MF8, VLSEG6E8FF_V, 0x5, 0x8 }, // 4247 |
10239 | | { PseudoVLSEG6E8FF_V_MF8_MASK, VLSEG6E8FF_V, 0x5, 0x8 }, // 4248 |
10240 | | { PseudoVLSEG6E8FF_V_MF4, VLSEG6E8FF_V, 0x6, 0x8 }, // 4249 |
10241 | | { PseudoVLSEG6E8FF_V_MF4_MASK, VLSEG6E8FF_V, 0x6, 0x8 }, // 4250 |
10242 | | { PseudoVLSEG6E8FF_V_MF2, VLSEG6E8FF_V, 0x7, 0x8 }, // 4251 |
10243 | | { PseudoVLSEG6E8FF_V_MF2_MASK, VLSEG6E8FF_V, 0x7, 0x8 }, // 4252 |
10244 | | { PseudoVLSEG6E8_V_M1, VLSEG6E8_V, 0x0, 0x8 }, // 4253 |
10245 | | { PseudoVLSEG6E8_V_M1_MASK, VLSEG6E8_V, 0x0, 0x8 }, // 4254 |
10246 | | { PseudoVLSEG6E8_V_MF8, VLSEG6E8_V, 0x5, 0x8 }, // 4255 |
10247 | | { PseudoVLSEG6E8_V_MF8_MASK, VLSEG6E8_V, 0x5, 0x8 }, // 4256 |
10248 | | { PseudoVLSEG6E8_V_MF4, VLSEG6E8_V, 0x6, 0x8 }, // 4257 |
10249 | | { PseudoVLSEG6E8_V_MF4_MASK, VLSEG6E8_V, 0x6, 0x8 }, // 4258 |
10250 | | { PseudoVLSEG6E8_V_MF2, VLSEG6E8_V, 0x7, 0x8 }, // 4259 |
10251 | | { PseudoVLSEG6E8_V_MF2_MASK, VLSEG6E8_V, 0x7, 0x8 }, // 4260 |
10252 | | { PseudoVLSEG7E16FF_V_M1, VLSEG7E16FF_V, 0x0, 0x10 }, // 4261 |
10253 | | { PseudoVLSEG7E16FF_V_M1_MASK, VLSEG7E16FF_V, 0x0, 0x10 }, // 4262 |
10254 | | { PseudoVLSEG7E16FF_V_MF4, VLSEG7E16FF_V, 0x6, 0x10 }, // 4263 |
10255 | | { PseudoVLSEG7E16FF_V_MF4_MASK, VLSEG7E16FF_V, 0x6, 0x10 }, // 4264 |
10256 | | { PseudoVLSEG7E16FF_V_MF2, VLSEG7E16FF_V, 0x7, 0x10 }, // 4265 |
10257 | | { PseudoVLSEG7E16FF_V_MF2_MASK, VLSEG7E16FF_V, 0x7, 0x10 }, // 4266 |
10258 | | { PseudoVLSEG7E16_V_M1, VLSEG7E16_V, 0x0, 0x10 }, // 4267 |
10259 | | { PseudoVLSEG7E16_V_M1_MASK, VLSEG7E16_V, 0x0, 0x10 }, // 4268 |
10260 | | { PseudoVLSEG7E16_V_MF4, VLSEG7E16_V, 0x6, 0x10 }, // 4269 |
10261 | | { PseudoVLSEG7E16_V_MF4_MASK, VLSEG7E16_V, 0x6, 0x10 }, // 4270 |
10262 | | { PseudoVLSEG7E16_V_MF2, VLSEG7E16_V, 0x7, 0x10 }, // 4271 |
10263 | | { PseudoVLSEG7E16_V_MF2_MASK, VLSEG7E16_V, 0x7, 0x10 }, // 4272 |
10264 | | { PseudoVLSEG7E32FF_V_M1, VLSEG7E32FF_V, 0x0, 0x20 }, // 4273 |
10265 | | { PseudoVLSEG7E32FF_V_M1_MASK, VLSEG7E32FF_V, 0x0, 0x20 }, // 4274 |
10266 | | { PseudoVLSEG7E32FF_V_MF2, VLSEG7E32FF_V, 0x7, 0x20 }, // 4275 |
10267 | | { PseudoVLSEG7E32FF_V_MF2_MASK, VLSEG7E32FF_V, 0x7, 0x20 }, // 4276 |
10268 | | { PseudoVLSEG7E32_V_M1, VLSEG7E32_V, 0x0, 0x20 }, // 4277 |
10269 | | { PseudoVLSEG7E32_V_M1_MASK, VLSEG7E32_V, 0x0, 0x20 }, // 4278 |
10270 | | { PseudoVLSEG7E32_V_MF2, VLSEG7E32_V, 0x7, 0x20 }, // 4279 |
10271 | | { PseudoVLSEG7E32_V_MF2_MASK, VLSEG7E32_V, 0x7, 0x20 }, // 4280 |
10272 | | { PseudoVLSEG7E64FF_V_M1, VLSEG7E64FF_V, 0x0, 0x40 }, // 4281 |
10273 | | { PseudoVLSEG7E64FF_V_M1_MASK, VLSEG7E64FF_V, 0x0, 0x40 }, // 4282 |
10274 | | { PseudoVLSEG7E64_V_M1, VLSEG7E64_V, 0x0, 0x40 }, // 4283 |
10275 | | { PseudoVLSEG7E64_V_M1_MASK, VLSEG7E64_V, 0x0, 0x40 }, // 4284 |
10276 | | { PseudoVLSEG7E8FF_V_M1, VLSEG7E8FF_V, 0x0, 0x8 }, // 4285 |
10277 | | { PseudoVLSEG7E8FF_V_M1_MASK, VLSEG7E8FF_V, 0x0, 0x8 }, // 4286 |
10278 | | { PseudoVLSEG7E8FF_V_MF8, VLSEG7E8FF_V, 0x5, 0x8 }, // 4287 |
10279 | | { PseudoVLSEG7E8FF_V_MF8_MASK, VLSEG7E8FF_V, 0x5, 0x8 }, // 4288 |
10280 | | { PseudoVLSEG7E8FF_V_MF4, VLSEG7E8FF_V, 0x6, 0x8 }, // 4289 |
10281 | | { PseudoVLSEG7E8FF_V_MF4_MASK, VLSEG7E8FF_V, 0x6, 0x8 }, // 4290 |
10282 | | { PseudoVLSEG7E8FF_V_MF2, VLSEG7E8FF_V, 0x7, 0x8 }, // 4291 |
10283 | | { PseudoVLSEG7E8FF_V_MF2_MASK, VLSEG7E8FF_V, 0x7, 0x8 }, // 4292 |
10284 | | { PseudoVLSEG7E8_V_M1, VLSEG7E8_V, 0x0, 0x8 }, // 4293 |
10285 | | { PseudoVLSEG7E8_V_M1_MASK, VLSEG7E8_V, 0x0, 0x8 }, // 4294 |
10286 | | { PseudoVLSEG7E8_V_MF8, VLSEG7E8_V, 0x5, 0x8 }, // 4295 |
10287 | | { PseudoVLSEG7E8_V_MF8_MASK, VLSEG7E8_V, 0x5, 0x8 }, // 4296 |
10288 | | { PseudoVLSEG7E8_V_MF4, VLSEG7E8_V, 0x6, 0x8 }, // 4297 |
10289 | | { PseudoVLSEG7E8_V_MF4_MASK, VLSEG7E8_V, 0x6, 0x8 }, // 4298 |
10290 | | { PseudoVLSEG7E8_V_MF2, VLSEG7E8_V, 0x7, 0x8 }, // 4299 |
10291 | | { PseudoVLSEG7E8_V_MF2_MASK, VLSEG7E8_V, 0x7, 0x8 }, // 4300 |
10292 | | { PseudoVLSEG8E16FF_V_M1, VLSEG8E16FF_V, 0x0, 0x10 }, // 4301 |
10293 | | { PseudoVLSEG8E16FF_V_M1_MASK, VLSEG8E16FF_V, 0x0, 0x10 }, // 4302 |
10294 | | { PseudoVLSEG8E16FF_V_MF4, VLSEG8E16FF_V, 0x6, 0x10 }, // 4303 |
10295 | | { PseudoVLSEG8E16FF_V_MF4_MASK, VLSEG8E16FF_V, 0x6, 0x10 }, // 4304 |
10296 | | { PseudoVLSEG8E16FF_V_MF2, VLSEG8E16FF_V, 0x7, 0x10 }, // 4305 |
10297 | | { PseudoVLSEG8E16FF_V_MF2_MASK, VLSEG8E16FF_V, 0x7, 0x10 }, // 4306 |
10298 | | { PseudoVLSEG8E16_V_M1, VLSEG8E16_V, 0x0, 0x10 }, // 4307 |
10299 | | { PseudoVLSEG8E16_V_M1_MASK, VLSEG8E16_V, 0x0, 0x10 }, // 4308 |
10300 | | { PseudoVLSEG8E16_V_MF4, VLSEG8E16_V, 0x6, 0x10 }, // 4309 |
10301 | | { PseudoVLSEG8E16_V_MF4_MASK, VLSEG8E16_V, 0x6, 0x10 }, // 4310 |
10302 | | { PseudoVLSEG8E16_V_MF2, VLSEG8E16_V, 0x7, 0x10 }, // 4311 |
10303 | | { PseudoVLSEG8E16_V_MF2_MASK, VLSEG8E16_V, 0x7, 0x10 }, // 4312 |
10304 | | { PseudoVLSEG8E32FF_V_M1, VLSEG8E32FF_V, 0x0, 0x20 }, // 4313 |
10305 | | { PseudoVLSEG8E32FF_V_M1_MASK, VLSEG8E32FF_V, 0x0, 0x20 }, // 4314 |
10306 | | { PseudoVLSEG8E32FF_V_MF2, VLSEG8E32FF_V, 0x7, 0x20 }, // 4315 |
10307 | | { PseudoVLSEG8E32FF_V_MF2_MASK, VLSEG8E32FF_V, 0x7, 0x20 }, // 4316 |
10308 | | { PseudoVLSEG8E32_V_M1, VLSEG8E32_V, 0x0, 0x20 }, // 4317 |
10309 | | { PseudoVLSEG8E32_V_M1_MASK, VLSEG8E32_V, 0x0, 0x20 }, // 4318 |
10310 | | { PseudoVLSEG8E32_V_MF2, VLSEG8E32_V, 0x7, 0x20 }, // 4319 |
10311 | | { PseudoVLSEG8E32_V_MF2_MASK, VLSEG8E32_V, 0x7, 0x20 }, // 4320 |
10312 | | { PseudoVLSEG8E64FF_V_M1, VLSEG8E64FF_V, 0x0, 0x40 }, // 4321 |
10313 | | { PseudoVLSEG8E64FF_V_M1_MASK, VLSEG8E64FF_V, 0x0, 0x40 }, // 4322 |
10314 | | { PseudoVLSEG8E64_V_M1, VLSEG8E64_V, 0x0, 0x40 }, // 4323 |
10315 | | { PseudoVLSEG8E64_V_M1_MASK, VLSEG8E64_V, 0x0, 0x40 }, // 4324 |
10316 | | { PseudoVLSEG8E8FF_V_M1, VLSEG8E8FF_V, 0x0, 0x8 }, // 4325 |
10317 | | { PseudoVLSEG8E8FF_V_M1_MASK, VLSEG8E8FF_V, 0x0, 0x8 }, // 4326 |
10318 | | { PseudoVLSEG8E8FF_V_MF8, VLSEG8E8FF_V, 0x5, 0x8 }, // 4327 |
10319 | | { PseudoVLSEG8E8FF_V_MF8_MASK, VLSEG8E8FF_V, 0x5, 0x8 }, // 4328 |
10320 | | { PseudoVLSEG8E8FF_V_MF4, VLSEG8E8FF_V, 0x6, 0x8 }, // 4329 |
10321 | | { PseudoVLSEG8E8FF_V_MF4_MASK, VLSEG8E8FF_V, 0x6, 0x8 }, // 4330 |
10322 | | { PseudoVLSEG8E8FF_V_MF2, VLSEG8E8FF_V, 0x7, 0x8 }, // 4331 |
10323 | | { PseudoVLSEG8E8FF_V_MF2_MASK, VLSEG8E8FF_V, 0x7, 0x8 }, // 4332 |
10324 | | { PseudoVLSEG8E8_V_M1, VLSEG8E8_V, 0x0, 0x8 }, // 4333 |
10325 | | { PseudoVLSEG8E8_V_M1_MASK, VLSEG8E8_V, 0x0, 0x8 }, // 4334 |
10326 | | { PseudoVLSEG8E8_V_MF8, VLSEG8E8_V, 0x5, 0x8 }, // 4335 |
10327 | | { PseudoVLSEG8E8_V_MF8_MASK, VLSEG8E8_V, 0x5, 0x8 }, // 4336 |
10328 | | { PseudoVLSEG8E8_V_MF4, VLSEG8E8_V, 0x6, 0x8 }, // 4337 |
10329 | | { PseudoVLSEG8E8_V_MF4_MASK, VLSEG8E8_V, 0x6, 0x8 }, // 4338 |
10330 | | { PseudoVLSEG8E8_V_MF2, VLSEG8E8_V, 0x7, 0x8 }, // 4339 |
10331 | | { PseudoVLSEG8E8_V_MF2_MASK, VLSEG8E8_V, 0x7, 0x8 }, // 4340 |
10332 | | { PseudoVLSSEG2E16_V_M1, VLSSEG2E16_V, 0x0, 0x10 }, // 4341 |
10333 | | { PseudoVLSSEG2E16_V_M1_MASK, VLSSEG2E16_V, 0x0, 0x10 }, // 4342 |
10334 | | { PseudoVLSSEG2E16_V_M2, VLSSEG2E16_V, 0x1, 0x10 }, // 4343 |
10335 | | { PseudoVLSSEG2E16_V_M2_MASK, VLSSEG2E16_V, 0x1, 0x10 }, // 4344 |
10336 | | { PseudoVLSSEG2E16_V_M4, VLSSEG2E16_V, 0x2, 0x10 }, // 4345 |
10337 | | { PseudoVLSSEG2E16_V_M4_MASK, VLSSEG2E16_V, 0x2, 0x10 }, // 4346 |
10338 | | { PseudoVLSSEG2E16_V_MF4, VLSSEG2E16_V, 0x6, 0x10 }, // 4347 |
10339 | | { PseudoVLSSEG2E16_V_MF4_MASK, VLSSEG2E16_V, 0x6, 0x10 }, // 4348 |
10340 | | { PseudoVLSSEG2E16_V_MF2, VLSSEG2E16_V, 0x7, 0x10 }, // 4349 |
10341 | | { PseudoVLSSEG2E16_V_MF2_MASK, VLSSEG2E16_V, 0x7, 0x10 }, // 4350 |
10342 | | { PseudoVLSSEG2E32_V_M1, VLSSEG2E32_V, 0x0, 0x20 }, // 4351 |
10343 | | { PseudoVLSSEG2E32_V_M1_MASK, VLSSEG2E32_V, 0x0, 0x20 }, // 4352 |
10344 | | { PseudoVLSSEG2E32_V_M2, VLSSEG2E32_V, 0x1, 0x20 }, // 4353 |
10345 | | { PseudoVLSSEG2E32_V_M2_MASK, VLSSEG2E32_V, 0x1, 0x20 }, // 4354 |
10346 | | { PseudoVLSSEG2E32_V_M4, VLSSEG2E32_V, 0x2, 0x20 }, // 4355 |
10347 | | { PseudoVLSSEG2E32_V_M4_MASK, VLSSEG2E32_V, 0x2, 0x20 }, // 4356 |
10348 | | { PseudoVLSSEG2E32_V_MF2, VLSSEG2E32_V, 0x7, 0x20 }, // 4357 |
10349 | | { PseudoVLSSEG2E32_V_MF2_MASK, VLSSEG2E32_V, 0x7, 0x20 }, // 4358 |
10350 | | { PseudoVLSSEG2E64_V_M1, VLSSEG2E64_V, 0x0, 0x40 }, // 4359 |
10351 | | { PseudoVLSSEG2E64_V_M1_MASK, VLSSEG2E64_V, 0x0, 0x40 }, // 4360 |
10352 | | { PseudoVLSSEG2E64_V_M2, VLSSEG2E64_V, 0x1, 0x40 }, // 4361 |
10353 | | { PseudoVLSSEG2E64_V_M2_MASK, VLSSEG2E64_V, 0x1, 0x40 }, // 4362 |
10354 | | { PseudoVLSSEG2E64_V_M4, VLSSEG2E64_V, 0x2, 0x40 }, // 4363 |
10355 | | { PseudoVLSSEG2E64_V_M4_MASK, VLSSEG2E64_V, 0x2, 0x40 }, // 4364 |
10356 | | { PseudoVLSSEG2E8_V_M1, VLSSEG2E8_V, 0x0, 0x8 }, // 4365 |
10357 | | { PseudoVLSSEG2E8_V_M1_MASK, VLSSEG2E8_V, 0x0, 0x8 }, // 4366 |
10358 | | { PseudoVLSSEG2E8_V_M2, VLSSEG2E8_V, 0x1, 0x8 }, // 4367 |
10359 | | { PseudoVLSSEG2E8_V_M2_MASK, VLSSEG2E8_V, 0x1, 0x8 }, // 4368 |
10360 | | { PseudoVLSSEG2E8_V_M4, VLSSEG2E8_V, 0x2, 0x8 }, // 4369 |
10361 | | { PseudoVLSSEG2E8_V_M4_MASK, VLSSEG2E8_V, 0x2, 0x8 }, // 4370 |
10362 | | { PseudoVLSSEG2E8_V_MF8, VLSSEG2E8_V, 0x5, 0x8 }, // 4371 |
10363 | | { PseudoVLSSEG2E8_V_MF8_MASK, VLSSEG2E8_V, 0x5, 0x8 }, // 4372 |
10364 | | { PseudoVLSSEG2E8_V_MF4, VLSSEG2E8_V, 0x6, 0x8 }, // 4373 |
10365 | | { PseudoVLSSEG2E8_V_MF4_MASK, VLSSEG2E8_V, 0x6, 0x8 }, // 4374 |
10366 | | { PseudoVLSSEG2E8_V_MF2, VLSSEG2E8_V, 0x7, 0x8 }, // 4375 |
10367 | | { PseudoVLSSEG2E8_V_MF2_MASK, VLSSEG2E8_V, 0x7, 0x8 }, // 4376 |
10368 | | { PseudoVLSSEG3E16_V_M1, VLSSEG3E16_V, 0x0, 0x10 }, // 4377 |
10369 | | { PseudoVLSSEG3E16_V_M1_MASK, VLSSEG3E16_V, 0x0, 0x10 }, // 4378 |
10370 | | { PseudoVLSSEG3E16_V_M2, VLSSEG3E16_V, 0x1, 0x10 }, // 4379 |
10371 | | { PseudoVLSSEG3E16_V_M2_MASK, VLSSEG3E16_V, 0x1, 0x10 }, // 4380 |
10372 | | { PseudoVLSSEG3E16_V_MF4, VLSSEG3E16_V, 0x6, 0x10 }, // 4381 |
10373 | | { PseudoVLSSEG3E16_V_MF4_MASK, VLSSEG3E16_V, 0x6, 0x10 }, // 4382 |
10374 | | { PseudoVLSSEG3E16_V_MF2, VLSSEG3E16_V, 0x7, 0x10 }, // 4383 |
10375 | | { PseudoVLSSEG3E16_V_MF2_MASK, VLSSEG3E16_V, 0x7, 0x10 }, // 4384 |
10376 | | { PseudoVLSSEG3E32_V_M1, VLSSEG3E32_V, 0x0, 0x20 }, // 4385 |
10377 | | { PseudoVLSSEG3E32_V_M1_MASK, VLSSEG3E32_V, 0x0, 0x20 }, // 4386 |
10378 | | { PseudoVLSSEG3E32_V_M2, VLSSEG3E32_V, 0x1, 0x20 }, // 4387 |
10379 | | { PseudoVLSSEG3E32_V_M2_MASK, VLSSEG3E32_V, 0x1, 0x20 }, // 4388 |
10380 | | { PseudoVLSSEG3E32_V_MF2, VLSSEG3E32_V, 0x7, 0x20 }, // 4389 |
10381 | | { PseudoVLSSEG3E32_V_MF2_MASK, VLSSEG3E32_V, 0x7, 0x20 }, // 4390 |
10382 | | { PseudoVLSSEG3E64_V_M1, VLSSEG3E64_V, 0x0, 0x40 }, // 4391 |
10383 | | { PseudoVLSSEG3E64_V_M1_MASK, VLSSEG3E64_V, 0x0, 0x40 }, // 4392 |
10384 | | { PseudoVLSSEG3E64_V_M2, VLSSEG3E64_V, 0x1, 0x40 }, // 4393 |
10385 | | { PseudoVLSSEG3E64_V_M2_MASK, VLSSEG3E64_V, 0x1, 0x40 }, // 4394 |
10386 | | { PseudoVLSSEG3E8_V_M1, VLSSEG3E8_V, 0x0, 0x8 }, // 4395 |
10387 | | { PseudoVLSSEG3E8_V_M1_MASK, VLSSEG3E8_V, 0x0, 0x8 }, // 4396 |
10388 | | { PseudoVLSSEG3E8_V_M2, VLSSEG3E8_V, 0x1, 0x8 }, // 4397 |
10389 | | { PseudoVLSSEG3E8_V_M2_MASK, VLSSEG3E8_V, 0x1, 0x8 }, // 4398 |
10390 | | { PseudoVLSSEG3E8_V_MF8, VLSSEG3E8_V, 0x5, 0x8 }, // 4399 |
10391 | | { PseudoVLSSEG3E8_V_MF8_MASK, VLSSEG3E8_V, 0x5, 0x8 }, // 4400 |
10392 | | { PseudoVLSSEG3E8_V_MF4, VLSSEG3E8_V, 0x6, 0x8 }, // 4401 |
10393 | | { PseudoVLSSEG3E8_V_MF4_MASK, VLSSEG3E8_V, 0x6, 0x8 }, // 4402 |
10394 | | { PseudoVLSSEG3E8_V_MF2, VLSSEG3E8_V, 0x7, 0x8 }, // 4403 |
10395 | | { PseudoVLSSEG3E8_V_MF2_MASK, VLSSEG3E8_V, 0x7, 0x8 }, // 4404 |
10396 | | { PseudoVLSSEG4E16_V_M1, VLSSEG4E16_V, 0x0, 0x10 }, // 4405 |
10397 | | { PseudoVLSSEG4E16_V_M1_MASK, VLSSEG4E16_V, 0x0, 0x10 }, // 4406 |
10398 | | { PseudoVLSSEG4E16_V_M2, VLSSEG4E16_V, 0x1, 0x10 }, // 4407 |
10399 | | { PseudoVLSSEG4E16_V_M2_MASK, VLSSEG4E16_V, 0x1, 0x10 }, // 4408 |
10400 | | { PseudoVLSSEG4E16_V_MF4, VLSSEG4E16_V, 0x6, 0x10 }, // 4409 |
10401 | | { PseudoVLSSEG4E16_V_MF4_MASK, VLSSEG4E16_V, 0x6, 0x10 }, // 4410 |
10402 | | { PseudoVLSSEG4E16_V_MF2, VLSSEG4E16_V, 0x7, 0x10 }, // 4411 |
10403 | | { PseudoVLSSEG4E16_V_MF2_MASK, VLSSEG4E16_V, 0x7, 0x10 }, // 4412 |
10404 | | { PseudoVLSSEG4E32_V_M1, VLSSEG4E32_V, 0x0, 0x20 }, // 4413 |
10405 | | { PseudoVLSSEG4E32_V_M1_MASK, VLSSEG4E32_V, 0x0, 0x20 }, // 4414 |
10406 | | { PseudoVLSSEG4E32_V_M2, VLSSEG4E32_V, 0x1, 0x20 }, // 4415 |
10407 | | { PseudoVLSSEG4E32_V_M2_MASK, VLSSEG4E32_V, 0x1, 0x20 }, // 4416 |
10408 | | { PseudoVLSSEG4E32_V_MF2, VLSSEG4E32_V, 0x7, 0x20 }, // 4417 |
10409 | | { PseudoVLSSEG4E32_V_MF2_MASK, VLSSEG4E32_V, 0x7, 0x20 }, // 4418 |
10410 | | { PseudoVLSSEG4E64_V_M1, VLSSEG4E64_V, 0x0, 0x40 }, // 4419 |
10411 | | { PseudoVLSSEG4E64_V_M1_MASK, VLSSEG4E64_V, 0x0, 0x40 }, // 4420 |
10412 | | { PseudoVLSSEG4E64_V_M2, VLSSEG4E64_V, 0x1, 0x40 }, // 4421 |
10413 | | { PseudoVLSSEG4E64_V_M2_MASK, VLSSEG4E64_V, 0x1, 0x40 }, // 4422 |
10414 | | { PseudoVLSSEG4E8_V_M1, VLSSEG4E8_V, 0x0, 0x8 }, // 4423 |
10415 | | { PseudoVLSSEG4E8_V_M1_MASK, VLSSEG4E8_V, 0x0, 0x8 }, // 4424 |
10416 | | { PseudoVLSSEG4E8_V_M2, VLSSEG4E8_V, 0x1, 0x8 }, // 4425 |
10417 | | { PseudoVLSSEG4E8_V_M2_MASK, VLSSEG4E8_V, 0x1, 0x8 }, // 4426 |
10418 | | { PseudoVLSSEG4E8_V_MF8, VLSSEG4E8_V, 0x5, 0x8 }, // 4427 |
10419 | | { PseudoVLSSEG4E8_V_MF8_MASK, VLSSEG4E8_V, 0x5, 0x8 }, // 4428 |
10420 | | { PseudoVLSSEG4E8_V_MF4, VLSSEG4E8_V, 0x6, 0x8 }, // 4429 |
10421 | | { PseudoVLSSEG4E8_V_MF4_MASK, VLSSEG4E8_V, 0x6, 0x8 }, // 4430 |
10422 | | { PseudoVLSSEG4E8_V_MF2, VLSSEG4E8_V, 0x7, 0x8 }, // 4431 |
10423 | | { PseudoVLSSEG4E8_V_MF2_MASK, VLSSEG4E8_V, 0x7, 0x8 }, // 4432 |
10424 | | { PseudoVLSSEG5E16_V_M1, VLSSEG5E16_V, 0x0, 0x10 }, // 4433 |
10425 | | { PseudoVLSSEG5E16_V_M1_MASK, VLSSEG5E16_V, 0x0, 0x10 }, // 4434 |
10426 | | { PseudoVLSSEG5E16_V_MF4, VLSSEG5E16_V, 0x6, 0x10 }, // 4435 |
10427 | | { PseudoVLSSEG5E16_V_MF4_MASK, VLSSEG5E16_V, 0x6, 0x10 }, // 4436 |
10428 | | { PseudoVLSSEG5E16_V_MF2, VLSSEG5E16_V, 0x7, 0x10 }, // 4437 |
10429 | | { PseudoVLSSEG5E16_V_MF2_MASK, VLSSEG5E16_V, 0x7, 0x10 }, // 4438 |
10430 | | { PseudoVLSSEG5E32_V_M1, VLSSEG5E32_V, 0x0, 0x20 }, // 4439 |
10431 | | { PseudoVLSSEG5E32_V_M1_MASK, VLSSEG5E32_V, 0x0, 0x20 }, // 4440 |
10432 | | { PseudoVLSSEG5E32_V_MF2, VLSSEG5E32_V, 0x7, 0x20 }, // 4441 |
10433 | | { PseudoVLSSEG5E32_V_MF2_MASK, VLSSEG5E32_V, 0x7, 0x20 }, // 4442 |
10434 | | { PseudoVLSSEG5E64_V_M1, VLSSEG5E64_V, 0x0, 0x40 }, // 4443 |
10435 | | { PseudoVLSSEG5E64_V_M1_MASK, VLSSEG5E64_V, 0x0, 0x40 }, // 4444 |
10436 | | { PseudoVLSSEG5E8_V_M1, VLSSEG5E8_V, 0x0, 0x8 }, // 4445 |
10437 | | { PseudoVLSSEG5E8_V_M1_MASK, VLSSEG5E8_V, 0x0, 0x8 }, // 4446 |
10438 | | { PseudoVLSSEG5E8_V_MF8, VLSSEG5E8_V, 0x5, 0x8 }, // 4447 |
10439 | | { PseudoVLSSEG5E8_V_MF8_MASK, VLSSEG5E8_V, 0x5, 0x8 }, // 4448 |
10440 | | { PseudoVLSSEG5E8_V_MF4, VLSSEG5E8_V, 0x6, 0x8 }, // 4449 |
10441 | | { PseudoVLSSEG5E8_V_MF4_MASK, VLSSEG5E8_V, 0x6, 0x8 }, // 4450 |
10442 | | { PseudoVLSSEG5E8_V_MF2, VLSSEG5E8_V, 0x7, 0x8 }, // 4451 |
10443 | | { PseudoVLSSEG5E8_V_MF2_MASK, VLSSEG5E8_V, 0x7, 0x8 }, // 4452 |
10444 | | { PseudoVLSSEG6E16_V_M1, VLSSEG6E16_V, 0x0, 0x10 }, // 4453 |
10445 | | { PseudoVLSSEG6E16_V_M1_MASK, VLSSEG6E16_V, 0x0, 0x10 }, // 4454 |
10446 | | { PseudoVLSSEG6E16_V_MF4, VLSSEG6E16_V, 0x6, 0x10 }, // 4455 |
10447 | | { PseudoVLSSEG6E16_V_MF4_MASK, VLSSEG6E16_V, 0x6, 0x10 }, // 4456 |
10448 | | { PseudoVLSSEG6E16_V_MF2, VLSSEG6E16_V, 0x7, 0x10 }, // 4457 |
10449 | | { PseudoVLSSEG6E16_V_MF2_MASK, VLSSEG6E16_V, 0x7, 0x10 }, // 4458 |
10450 | | { PseudoVLSSEG6E32_V_M1, VLSSEG6E32_V, 0x0, 0x20 }, // 4459 |
10451 | | { PseudoVLSSEG6E32_V_M1_MASK, VLSSEG6E32_V, 0x0, 0x20 }, // 4460 |
10452 | | { PseudoVLSSEG6E32_V_MF2, VLSSEG6E32_V, 0x7, 0x20 }, // 4461 |
10453 | | { PseudoVLSSEG6E32_V_MF2_MASK, VLSSEG6E32_V, 0x7, 0x20 }, // 4462 |
10454 | | { PseudoVLSSEG6E64_V_M1, VLSSEG6E64_V, 0x0, 0x40 }, // 4463 |
10455 | | { PseudoVLSSEG6E64_V_M1_MASK, VLSSEG6E64_V, 0x0, 0x40 }, // 4464 |
10456 | | { PseudoVLSSEG6E8_V_M1, VLSSEG6E8_V, 0x0, 0x8 }, // 4465 |
10457 | | { PseudoVLSSEG6E8_V_M1_MASK, VLSSEG6E8_V, 0x0, 0x8 }, // 4466 |
10458 | | { PseudoVLSSEG6E8_V_MF8, VLSSEG6E8_V, 0x5, 0x8 }, // 4467 |
10459 | | { PseudoVLSSEG6E8_V_MF8_MASK, VLSSEG6E8_V, 0x5, 0x8 }, // 4468 |
10460 | | { PseudoVLSSEG6E8_V_MF4, VLSSEG6E8_V, 0x6, 0x8 }, // 4469 |
10461 | | { PseudoVLSSEG6E8_V_MF4_MASK, VLSSEG6E8_V, 0x6, 0x8 }, // 4470 |
10462 | | { PseudoVLSSEG6E8_V_MF2, VLSSEG6E8_V, 0x7, 0x8 }, // 4471 |
10463 | | { PseudoVLSSEG6E8_V_MF2_MASK, VLSSEG6E8_V, 0x7, 0x8 }, // 4472 |
10464 | | { PseudoVLSSEG7E16_V_M1, VLSSEG7E16_V, 0x0, 0x10 }, // 4473 |
10465 | | { PseudoVLSSEG7E16_V_M1_MASK, VLSSEG7E16_V, 0x0, 0x10 }, // 4474 |
10466 | | { PseudoVLSSEG7E16_V_MF4, VLSSEG7E16_V, 0x6, 0x10 }, // 4475 |
10467 | | { PseudoVLSSEG7E16_V_MF4_MASK, VLSSEG7E16_V, 0x6, 0x10 }, // 4476 |
10468 | | { PseudoVLSSEG7E16_V_MF2, VLSSEG7E16_V, 0x7, 0x10 }, // 4477 |
10469 | | { PseudoVLSSEG7E16_V_MF2_MASK, VLSSEG7E16_V, 0x7, 0x10 }, // 4478 |
10470 | | { PseudoVLSSEG7E32_V_M1, VLSSEG7E32_V, 0x0, 0x20 }, // 4479 |
10471 | | { PseudoVLSSEG7E32_V_M1_MASK, VLSSEG7E32_V, 0x0, 0x20 }, // 4480 |
10472 | | { PseudoVLSSEG7E32_V_MF2, VLSSEG7E32_V, 0x7, 0x20 }, // 4481 |
10473 | | { PseudoVLSSEG7E32_V_MF2_MASK, VLSSEG7E32_V, 0x7, 0x20 }, // 4482 |
10474 | | { PseudoVLSSEG7E64_V_M1, VLSSEG7E64_V, 0x0, 0x40 }, // 4483 |
10475 | | { PseudoVLSSEG7E64_V_M1_MASK, VLSSEG7E64_V, 0x0, 0x40 }, // 4484 |
10476 | | { PseudoVLSSEG7E8_V_M1, VLSSEG7E8_V, 0x0, 0x8 }, // 4485 |
10477 | | { PseudoVLSSEG7E8_V_M1_MASK, VLSSEG7E8_V, 0x0, 0x8 }, // 4486 |
10478 | | { PseudoVLSSEG7E8_V_MF8, VLSSEG7E8_V, 0x5, 0x8 }, // 4487 |
10479 | | { PseudoVLSSEG7E8_V_MF8_MASK, VLSSEG7E8_V, 0x5, 0x8 }, // 4488 |
10480 | | { PseudoVLSSEG7E8_V_MF4, VLSSEG7E8_V, 0x6, 0x8 }, // 4489 |
10481 | | { PseudoVLSSEG7E8_V_MF4_MASK, VLSSEG7E8_V, 0x6, 0x8 }, // 4490 |
10482 | | { PseudoVLSSEG7E8_V_MF2, VLSSEG7E8_V, 0x7, 0x8 }, // 4491 |
10483 | | { PseudoVLSSEG7E8_V_MF2_MASK, VLSSEG7E8_V, 0x7, 0x8 }, // 4492 |
10484 | | { PseudoVLSSEG8E16_V_M1, VLSSEG8E16_V, 0x0, 0x10 }, // 4493 |
10485 | | { PseudoVLSSEG8E16_V_M1_MASK, VLSSEG8E16_V, 0x0, 0x10 }, // 4494 |
10486 | | { PseudoVLSSEG8E16_V_MF4, VLSSEG8E16_V, 0x6, 0x10 }, // 4495 |
10487 | | { PseudoVLSSEG8E16_V_MF4_MASK, VLSSEG8E16_V, 0x6, 0x10 }, // 4496 |
10488 | | { PseudoVLSSEG8E16_V_MF2, VLSSEG8E16_V, 0x7, 0x10 }, // 4497 |
10489 | | { PseudoVLSSEG8E16_V_MF2_MASK, VLSSEG8E16_V, 0x7, 0x10 }, // 4498 |
10490 | | { PseudoVLSSEG8E32_V_M1, VLSSEG8E32_V, 0x0, 0x20 }, // 4499 |
10491 | | { PseudoVLSSEG8E32_V_M1_MASK, VLSSEG8E32_V, 0x0, 0x20 }, // 4500 |
10492 | | { PseudoVLSSEG8E32_V_MF2, VLSSEG8E32_V, 0x7, 0x20 }, // 4501 |
10493 | | { PseudoVLSSEG8E32_V_MF2_MASK, VLSSEG8E32_V, 0x7, 0x20 }, // 4502 |
10494 | | { PseudoVLSSEG8E64_V_M1, VLSSEG8E64_V, 0x0, 0x40 }, // 4503 |
10495 | | { PseudoVLSSEG8E64_V_M1_MASK, VLSSEG8E64_V, 0x0, 0x40 }, // 4504 |
10496 | | { PseudoVLSSEG8E8_V_M1, VLSSEG8E8_V, 0x0, 0x8 }, // 4505 |
10497 | | { PseudoVLSSEG8E8_V_M1_MASK, VLSSEG8E8_V, 0x0, 0x8 }, // 4506 |
10498 | | { PseudoVLSSEG8E8_V_MF8, VLSSEG8E8_V, 0x5, 0x8 }, // 4507 |
10499 | | { PseudoVLSSEG8E8_V_MF8_MASK, VLSSEG8E8_V, 0x5, 0x8 }, // 4508 |
10500 | | { PseudoVLSSEG8E8_V_MF4, VLSSEG8E8_V, 0x6, 0x8 }, // 4509 |
10501 | | { PseudoVLSSEG8E8_V_MF4_MASK, VLSSEG8E8_V, 0x6, 0x8 }, // 4510 |
10502 | | { PseudoVLSSEG8E8_V_MF2, VLSSEG8E8_V, 0x7, 0x8 }, // 4511 |
10503 | | { PseudoVLSSEG8E8_V_MF2_MASK, VLSSEG8E8_V, 0x7, 0x8 }, // 4512 |
10504 | | { PseudoVLUXEI16_V_M1_M1, VLUXEI16_V, 0x0, 0x0 }, // 4513 |
10505 | | { PseudoVLUXEI16_V_M1_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 4514 |
10506 | | { PseudoVLUXEI16_V_M2_M1, VLUXEI16_V, 0x0, 0x0 }, // 4515 |
10507 | | { PseudoVLUXEI16_V_M2_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 4516 |
10508 | | { PseudoVLUXEI16_V_MF2_M1, VLUXEI16_V, 0x0, 0x0 }, // 4517 |
10509 | | { PseudoVLUXEI16_V_MF2_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 4518 |
10510 | | { PseudoVLUXEI16_V_MF4_M1, VLUXEI16_V, 0x0, 0x0 }, // 4519 |
10511 | | { PseudoVLUXEI16_V_MF4_M1_MASK, VLUXEI16_V, 0x0, 0x0 }, // 4520 |
10512 | | { PseudoVLUXEI16_V_M1_M2, VLUXEI16_V, 0x1, 0x0 }, // 4521 |
10513 | | { PseudoVLUXEI16_V_M1_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 4522 |
10514 | | { PseudoVLUXEI16_V_M2_M2, VLUXEI16_V, 0x1, 0x0 }, // 4523 |
10515 | | { PseudoVLUXEI16_V_M2_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 4524 |
10516 | | { PseudoVLUXEI16_V_M4_M2, VLUXEI16_V, 0x1, 0x0 }, // 4525 |
10517 | | { PseudoVLUXEI16_V_M4_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 4526 |
10518 | | { PseudoVLUXEI16_V_MF2_M2, VLUXEI16_V, 0x1, 0x0 }, // 4527 |
10519 | | { PseudoVLUXEI16_V_MF2_M2_MASK, VLUXEI16_V, 0x1, 0x0 }, // 4528 |
10520 | | { PseudoVLUXEI16_V_M1_M4, VLUXEI16_V, 0x2, 0x0 }, // 4529 |
10521 | | { PseudoVLUXEI16_V_M1_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 4530 |
10522 | | { PseudoVLUXEI16_V_M2_M4, VLUXEI16_V, 0x2, 0x0 }, // 4531 |
10523 | | { PseudoVLUXEI16_V_M2_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 4532 |
10524 | | { PseudoVLUXEI16_V_M4_M4, VLUXEI16_V, 0x2, 0x0 }, // 4533 |
10525 | | { PseudoVLUXEI16_V_M4_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 4534 |
10526 | | { PseudoVLUXEI16_V_M8_M4, VLUXEI16_V, 0x2, 0x0 }, // 4535 |
10527 | | { PseudoVLUXEI16_V_M8_M4_MASK, VLUXEI16_V, 0x2, 0x0 }, // 4536 |
10528 | | { PseudoVLUXEI16_V_M2_M8, VLUXEI16_V, 0x3, 0x0 }, // 4537 |
10529 | | { PseudoVLUXEI16_V_M2_M8_MASK, VLUXEI16_V, 0x3, 0x0 }, // 4538 |
10530 | | { PseudoVLUXEI16_V_M4_M8, VLUXEI16_V, 0x3, 0x0 }, // 4539 |
10531 | | { PseudoVLUXEI16_V_M4_M8_MASK, VLUXEI16_V, 0x3, 0x0 }, // 4540 |
10532 | | { PseudoVLUXEI16_V_M8_M8, VLUXEI16_V, 0x3, 0x0 }, // 4541 |
10533 | | { PseudoVLUXEI16_V_M8_M8_MASK, VLUXEI16_V, 0x3, 0x0 }, // 4542 |
10534 | | { PseudoVLUXEI16_V_MF4_MF8, VLUXEI16_V, 0x5, 0x0 }, // 4543 |
10535 | | { PseudoVLUXEI16_V_MF4_MF8_MASK, VLUXEI16_V, 0x5, 0x0 }, // 4544 |
10536 | | { PseudoVLUXEI16_V_MF2_MF4, VLUXEI16_V, 0x6, 0x0 }, // 4545 |
10537 | | { PseudoVLUXEI16_V_MF2_MF4_MASK, VLUXEI16_V, 0x6, 0x0 }, // 4546 |
10538 | | { PseudoVLUXEI16_V_MF4_MF4, VLUXEI16_V, 0x6, 0x0 }, // 4547 |
10539 | | { PseudoVLUXEI16_V_MF4_MF4_MASK, VLUXEI16_V, 0x6, 0x0 }, // 4548 |
10540 | | { PseudoVLUXEI16_V_M1_MF2, VLUXEI16_V, 0x7, 0x0 }, // 4549 |
10541 | | { PseudoVLUXEI16_V_M1_MF2_MASK, VLUXEI16_V, 0x7, 0x0 }, // 4550 |
10542 | | { PseudoVLUXEI16_V_MF2_MF2, VLUXEI16_V, 0x7, 0x0 }, // 4551 |
10543 | | { PseudoVLUXEI16_V_MF2_MF2_MASK, VLUXEI16_V, 0x7, 0x0 }, // 4552 |
10544 | | { PseudoVLUXEI16_V_MF4_MF2, VLUXEI16_V, 0x7, 0x0 }, // 4553 |
10545 | | { PseudoVLUXEI16_V_MF4_MF2_MASK, VLUXEI16_V, 0x7, 0x0 }, // 4554 |
10546 | | { PseudoVLUXEI32_V_M1_M1, VLUXEI32_V, 0x0, 0x0 }, // 4555 |
10547 | | { PseudoVLUXEI32_V_M1_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 4556 |
10548 | | { PseudoVLUXEI32_V_M2_M1, VLUXEI32_V, 0x0, 0x0 }, // 4557 |
10549 | | { PseudoVLUXEI32_V_M2_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 4558 |
10550 | | { PseudoVLUXEI32_V_M4_M1, VLUXEI32_V, 0x0, 0x0 }, // 4559 |
10551 | | { PseudoVLUXEI32_V_M4_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 4560 |
10552 | | { PseudoVLUXEI32_V_MF2_M1, VLUXEI32_V, 0x0, 0x0 }, // 4561 |
10553 | | { PseudoVLUXEI32_V_MF2_M1_MASK, VLUXEI32_V, 0x0, 0x0 }, // 4562 |
10554 | | { PseudoVLUXEI32_V_M1_M2, VLUXEI32_V, 0x1, 0x0 }, // 4563 |
10555 | | { PseudoVLUXEI32_V_M1_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 4564 |
10556 | | { PseudoVLUXEI32_V_M2_M2, VLUXEI32_V, 0x1, 0x0 }, // 4565 |
10557 | | { PseudoVLUXEI32_V_M2_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 4566 |
10558 | | { PseudoVLUXEI32_V_M4_M2, VLUXEI32_V, 0x1, 0x0 }, // 4567 |
10559 | | { PseudoVLUXEI32_V_M4_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 4568 |
10560 | | { PseudoVLUXEI32_V_M8_M2, VLUXEI32_V, 0x1, 0x0 }, // 4569 |
10561 | | { PseudoVLUXEI32_V_M8_M2_MASK, VLUXEI32_V, 0x1, 0x0 }, // 4570 |
10562 | | { PseudoVLUXEI32_V_M2_M4, VLUXEI32_V, 0x2, 0x0 }, // 4571 |
10563 | | { PseudoVLUXEI32_V_M2_M4_MASK, VLUXEI32_V, 0x2, 0x0 }, // 4572 |
10564 | | { PseudoVLUXEI32_V_M4_M4, VLUXEI32_V, 0x2, 0x0 }, // 4573 |
10565 | | { PseudoVLUXEI32_V_M4_M4_MASK, VLUXEI32_V, 0x2, 0x0 }, // 4574 |
10566 | | { PseudoVLUXEI32_V_M8_M4, VLUXEI32_V, 0x2, 0x0 }, // 4575 |
10567 | | { PseudoVLUXEI32_V_M8_M4_MASK, VLUXEI32_V, 0x2, 0x0 }, // 4576 |
10568 | | { PseudoVLUXEI32_V_M4_M8, VLUXEI32_V, 0x3, 0x0 }, // 4577 |
10569 | | { PseudoVLUXEI32_V_M4_M8_MASK, VLUXEI32_V, 0x3, 0x0 }, // 4578 |
10570 | | { PseudoVLUXEI32_V_M8_M8, VLUXEI32_V, 0x3, 0x0 }, // 4579 |
10571 | | { PseudoVLUXEI32_V_M8_M8_MASK, VLUXEI32_V, 0x3, 0x0 }, // 4580 |
10572 | | { PseudoVLUXEI32_V_MF2_MF8, VLUXEI32_V, 0x5, 0x0 }, // 4581 |
10573 | | { PseudoVLUXEI32_V_MF2_MF8_MASK, VLUXEI32_V, 0x5, 0x0 }, // 4582 |
10574 | | { PseudoVLUXEI32_V_M1_MF4, VLUXEI32_V, 0x6, 0x0 }, // 4583 |
10575 | | { PseudoVLUXEI32_V_M1_MF4_MASK, VLUXEI32_V, 0x6, 0x0 }, // 4584 |
10576 | | { PseudoVLUXEI32_V_MF2_MF4, VLUXEI32_V, 0x6, 0x0 }, // 4585 |
10577 | | { PseudoVLUXEI32_V_MF2_MF4_MASK, VLUXEI32_V, 0x6, 0x0 }, // 4586 |
10578 | | { PseudoVLUXEI32_V_M1_MF2, VLUXEI32_V, 0x7, 0x0 }, // 4587 |
10579 | | { PseudoVLUXEI32_V_M1_MF2_MASK, VLUXEI32_V, 0x7, 0x0 }, // 4588 |
10580 | | { PseudoVLUXEI32_V_M2_MF2, VLUXEI32_V, 0x7, 0x0 }, // 4589 |
10581 | | { PseudoVLUXEI32_V_M2_MF2_MASK, VLUXEI32_V, 0x7, 0x0 }, // 4590 |
10582 | | { PseudoVLUXEI32_V_MF2_MF2, VLUXEI32_V, 0x7, 0x0 }, // 4591 |
10583 | | { PseudoVLUXEI32_V_MF2_MF2_MASK, VLUXEI32_V, 0x7, 0x0 }, // 4592 |
10584 | | { PseudoVLUXEI64_V_M1_M1, VLUXEI64_V, 0x0, 0x0 }, // 4593 |
10585 | | { PseudoVLUXEI64_V_M1_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 4594 |
10586 | | { PseudoVLUXEI64_V_M2_M1, VLUXEI64_V, 0x0, 0x0 }, // 4595 |
10587 | | { PseudoVLUXEI64_V_M2_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 4596 |
10588 | | { PseudoVLUXEI64_V_M4_M1, VLUXEI64_V, 0x0, 0x0 }, // 4597 |
10589 | | { PseudoVLUXEI64_V_M4_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 4598 |
10590 | | { PseudoVLUXEI64_V_M8_M1, VLUXEI64_V, 0x0, 0x0 }, // 4599 |
10591 | | { PseudoVLUXEI64_V_M8_M1_MASK, VLUXEI64_V, 0x0, 0x0 }, // 4600 |
10592 | | { PseudoVLUXEI64_V_M2_M2, VLUXEI64_V, 0x1, 0x0 }, // 4601 |
10593 | | { PseudoVLUXEI64_V_M2_M2_MASK, VLUXEI64_V, 0x1, 0x0 }, // 4602 |
10594 | | { PseudoVLUXEI64_V_M4_M2, VLUXEI64_V, 0x1, 0x0 }, // 4603 |
10595 | | { PseudoVLUXEI64_V_M4_M2_MASK, VLUXEI64_V, 0x1, 0x0 }, // 4604 |
10596 | | { PseudoVLUXEI64_V_M8_M2, VLUXEI64_V, 0x1, 0x0 }, // 4605 |
10597 | | { PseudoVLUXEI64_V_M8_M2_MASK, VLUXEI64_V, 0x1, 0x0 }, // 4606 |
10598 | | { PseudoVLUXEI64_V_M4_M4, VLUXEI64_V, 0x2, 0x0 }, // 4607 |
10599 | | { PseudoVLUXEI64_V_M4_M4_MASK, VLUXEI64_V, 0x2, 0x0 }, // 4608 |
10600 | | { PseudoVLUXEI64_V_M8_M4, VLUXEI64_V, 0x2, 0x0 }, // 4609 |
10601 | | { PseudoVLUXEI64_V_M8_M4_MASK, VLUXEI64_V, 0x2, 0x0 }, // 4610 |
10602 | | { PseudoVLUXEI64_V_M8_M8, VLUXEI64_V, 0x3, 0x0 }, // 4611 |
10603 | | { PseudoVLUXEI64_V_M8_M8_MASK, VLUXEI64_V, 0x3, 0x0 }, // 4612 |
10604 | | { PseudoVLUXEI64_V_M1_MF8, VLUXEI64_V, 0x5, 0x0 }, // 4613 |
10605 | | { PseudoVLUXEI64_V_M1_MF8_MASK, VLUXEI64_V, 0x5, 0x0 }, // 4614 |
10606 | | { PseudoVLUXEI64_V_M1_MF4, VLUXEI64_V, 0x6, 0x0 }, // 4615 |
10607 | | { PseudoVLUXEI64_V_M1_MF4_MASK, VLUXEI64_V, 0x6, 0x0 }, // 4616 |
10608 | | { PseudoVLUXEI64_V_M2_MF4, VLUXEI64_V, 0x6, 0x0 }, // 4617 |
10609 | | { PseudoVLUXEI64_V_M2_MF4_MASK, VLUXEI64_V, 0x6, 0x0 }, // 4618 |
10610 | | { PseudoVLUXEI64_V_M1_MF2, VLUXEI64_V, 0x7, 0x0 }, // 4619 |
10611 | | { PseudoVLUXEI64_V_M1_MF2_MASK, VLUXEI64_V, 0x7, 0x0 }, // 4620 |
10612 | | { PseudoVLUXEI64_V_M2_MF2, VLUXEI64_V, 0x7, 0x0 }, // 4621 |
10613 | | { PseudoVLUXEI64_V_M2_MF2_MASK, VLUXEI64_V, 0x7, 0x0 }, // 4622 |
10614 | | { PseudoVLUXEI64_V_M4_MF2, VLUXEI64_V, 0x7, 0x0 }, // 4623 |
10615 | | { PseudoVLUXEI64_V_M4_MF2_MASK, VLUXEI64_V, 0x7, 0x0 }, // 4624 |
10616 | | { PseudoVLUXEI8_V_M1_M1, VLUXEI8_V, 0x0, 0x0 }, // 4625 |
10617 | | { PseudoVLUXEI8_V_M1_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 4626 |
10618 | | { PseudoVLUXEI8_V_MF2_M1, VLUXEI8_V, 0x0, 0x0 }, // 4627 |
10619 | | { PseudoVLUXEI8_V_MF2_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 4628 |
10620 | | { PseudoVLUXEI8_V_MF4_M1, VLUXEI8_V, 0x0, 0x0 }, // 4629 |
10621 | | { PseudoVLUXEI8_V_MF4_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 4630 |
10622 | | { PseudoVLUXEI8_V_MF8_M1, VLUXEI8_V, 0x0, 0x0 }, // 4631 |
10623 | | { PseudoVLUXEI8_V_MF8_M1_MASK, VLUXEI8_V, 0x0, 0x0 }, // 4632 |
10624 | | { PseudoVLUXEI8_V_M1_M2, VLUXEI8_V, 0x1, 0x0 }, // 4633 |
10625 | | { PseudoVLUXEI8_V_M1_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 4634 |
10626 | | { PseudoVLUXEI8_V_M2_M2, VLUXEI8_V, 0x1, 0x0 }, // 4635 |
10627 | | { PseudoVLUXEI8_V_M2_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 4636 |
10628 | | { PseudoVLUXEI8_V_MF2_M2, VLUXEI8_V, 0x1, 0x0 }, // 4637 |
10629 | | { PseudoVLUXEI8_V_MF2_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 4638 |
10630 | | { PseudoVLUXEI8_V_MF4_M2, VLUXEI8_V, 0x1, 0x0 }, // 4639 |
10631 | | { PseudoVLUXEI8_V_MF4_M2_MASK, VLUXEI8_V, 0x1, 0x0 }, // 4640 |
10632 | | { PseudoVLUXEI8_V_M1_M4, VLUXEI8_V, 0x2, 0x0 }, // 4641 |
10633 | | { PseudoVLUXEI8_V_M1_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 4642 |
10634 | | { PseudoVLUXEI8_V_M2_M4, VLUXEI8_V, 0x2, 0x0 }, // 4643 |
10635 | | { PseudoVLUXEI8_V_M2_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 4644 |
10636 | | { PseudoVLUXEI8_V_M4_M4, VLUXEI8_V, 0x2, 0x0 }, // 4645 |
10637 | | { PseudoVLUXEI8_V_M4_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 4646 |
10638 | | { PseudoVLUXEI8_V_MF2_M4, VLUXEI8_V, 0x2, 0x0 }, // 4647 |
10639 | | { PseudoVLUXEI8_V_MF2_M4_MASK, VLUXEI8_V, 0x2, 0x0 }, // 4648 |
10640 | | { PseudoVLUXEI8_V_M1_M8, VLUXEI8_V, 0x3, 0x0 }, // 4649 |
10641 | | { PseudoVLUXEI8_V_M1_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 4650 |
10642 | | { PseudoVLUXEI8_V_M2_M8, VLUXEI8_V, 0x3, 0x0 }, // 4651 |
10643 | | { PseudoVLUXEI8_V_M2_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 4652 |
10644 | | { PseudoVLUXEI8_V_M4_M8, VLUXEI8_V, 0x3, 0x0 }, // 4653 |
10645 | | { PseudoVLUXEI8_V_M4_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 4654 |
10646 | | { PseudoVLUXEI8_V_M8_M8, VLUXEI8_V, 0x3, 0x0 }, // 4655 |
10647 | | { PseudoVLUXEI8_V_M8_M8_MASK, VLUXEI8_V, 0x3, 0x0 }, // 4656 |
10648 | | { PseudoVLUXEI8_V_MF8_MF8, VLUXEI8_V, 0x5, 0x0 }, // 4657 |
10649 | | { PseudoVLUXEI8_V_MF8_MF8_MASK, VLUXEI8_V, 0x5, 0x0 }, // 4658 |
10650 | | { PseudoVLUXEI8_V_MF4_MF4, VLUXEI8_V, 0x6, 0x0 }, // 4659 |
10651 | | { PseudoVLUXEI8_V_MF4_MF4_MASK, VLUXEI8_V, 0x6, 0x0 }, // 4660 |
10652 | | { PseudoVLUXEI8_V_MF8_MF4, VLUXEI8_V, 0x6, 0x0 }, // 4661 |
10653 | | { PseudoVLUXEI8_V_MF8_MF4_MASK, VLUXEI8_V, 0x6, 0x0 }, // 4662 |
10654 | | { PseudoVLUXEI8_V_MF2_MF2, VLUXEI8_V, 0x7, 0x0 }, // 4663 |
10655 | | { PseudoVLUXEI8_V_MF2_MF2_MASK, VLUXEI8_V, 0x7, 0x0 }, // 4664 |
10656 | | { PseudoVLUXEI8_V_MF4_MF2, VLUXEI8_V, 0x7, 0x0 }, // 4665 |
10657 | | { PseudoVLUXEI8_V_MF4_MF2_MASK, VLUXEI8_V, 0x7, 0x0 }, // 4666 |
10658 | | { PseudoVLUXEI8_V_MF8_MF2, VLUXEI8_V, 0x7, 0x0 }, // 4667 |
10659 | | { PseudoVLUXEI8_V_MF8_MF2_MASK, VLUXEI8_V, 0x7, 0x0 }, // 4668 |
10660 | | { PseudoVLUXSEG2EI16_V_M1_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4669 |
10661 | | { PseudoVLUXSEG2EI16_V_M1_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4670 |
10662 | | { PseudoVLUXSEG2EI16_V_M2_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4671 |
10663 | | { PseudoVLUXSEG2EI16_V_M2_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4672 |
10664 | | { PseudoVLUXSEG2EI16_V_MF2_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4673 |
10665 | | { PseudoVLUXSEG2EI16_V_MF2_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4674 |
10666 | | { PseudoVLUXSEG2EI16_V_MF4_M1, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4675 |
10667 | | { PseudoVLUXSEG2EI16_V_MF4_M1_MASK, VLUXSEG2EI16_V, 0x0, 0x0 }, // 4676 |
10668 | | { PseudoVLUXSEG2EI16_V_M1_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4677 |
10669 | | { PseudoVLUXSEG2EI16_V_M1_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4678 |
10670 | | { PseudoVLUXSEG2EI16_V_M2_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4679 |
10671 | | { PseudoVLUXSEG2EI16_V_M2_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4680 |
10672 | | { PseudoVLUXSEG2EI16_V_M4_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4681 |
10673 | | { PseudoVLUXSEG2EI16_V_M4_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4682 |
10674 | | { PseudoVLUXSEG2EI16_V_MF2_M2, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4683 |
10675 | | { PseudoVLUXSEG2EI16_V_MF2_M2_MASK, VLUXSEG2EI16_V, 0x1, 0x0 }, // 4684 |
10676 | | { PseudoVLUXSEG2EI16_V_M1_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4685 |
10677 | | { PseudoVLUXSEG2EI16_V_M1_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4686 |
10678 | | { PseudoVLUXSEG2EI16_V_M2_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4687 |
10679 | | { PseudoVLUXSEG2EI16_V_M2_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4688 |
10680 | | { PseudoVLUXSEG2EI16_V_M4_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4689 |
10681 | | { PseudoVLUXSEG2EI16_V_M4_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4690 |
10682 | | { PseudoVLUXSEG2EI16_V_M8_M4, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4691 |
10683 | | { PseudoVLUXSEG2EI16_V_M8_M4_MASK, VLUXSEG2EI16_V, 0x2, 0x0 }, // 4692 |
10684 | | { PseudoVLUXSEG2EI16_V_MF4_MF8, VLUXSEG2EI16_V, 0x5, 0x0 }, // 4693 |
10685 | | { PseudoVLUXSEG2EI16_V_MF4_MF8_MASK, VLUXSEG2EI16_V, 0x5, 0x0 }, // 4694 |
10686 | | { PseudoVLUXSEG2EI16_V_MF2_MF4, VLUXSEG2EI16_V, 0x6, 0x0 }, // 4695 |
10687 | | { PseudoVLUXSEG2EI16_V_MF2_MF4_MASK, VLUXSEG2EI16_V, 0x6, 0x0 }, // 4696 |
10688 | | { PseudoVLUXSEG2EI16_V_MF4_MF4, VLUXSEG2EI16_V, 0x6, 0x0 }, // 4697 |
10689 | | { PseudoVLUXSEG2EI16_V_MF4_MF4_MASK, VLUXSEG2EI16_V, 0x6, 0x0 }, // 4698 |
10690 | | { PseudoVLUXSEG2EI16_V_M1_MF2, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4699 |
10691 | | { PseudoVLUXSEG2EI16_V_M1_MF2_MASK, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4700 |
10692 | | { PseudoVLUXSEG2EI16_V_MF2_MF2, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4701 |
10693 | | { PseudoVLUXSEG2EI16_V_MF2_MF2_MASK, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4702 |
10694 | | { PseudoVLUXSEG2EI16_V_MF4_MF2, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4703 |
10695 | | { PseudoVLUXSEG2EI16_V_MF4_MF2_MASK, VLUXSEG2EI16_V, 0x7, 0x0 }, // 4704 |
10696 | | { PseudoVLUXSEG2EI32_V_M1_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4705 |
10697 | | { PseudoVLUXSEG2EI32_V_M1_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4706 |
10698 | | { PseudoVLUXSEG2EI32_V_M2_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4707 |
10699 | | { PseudoVLUXSEG2EI32_V_M2_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4708 |
10700 | | { PseudoVLUXSEG2EI32_V_M4_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4709 |
10701 | | { PseudoVLUXSEG2EI32_V_M4_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4710 |
10702 | | { PseudoVLUXSEG2EI32_V_MF2_M1, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4711 |
10703 | | { PseudoVLUXSEG2EI32_V_MF2_M1_MASK, VLUXSEG2EI32_V, 0x0, 0x0 }, // 4712 |
10704 | | { PseudoVLUXSEG2EI32_V_M1_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4713 |
10705 | | { PseudoVLUXSEG2EI32_V_M1_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4714 |
10706 | | { PseudoVLUXSEG2EI32_V_M2_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4715 |
10707 | | { PseudoVLUXSEG2EI32_V_M2_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4716 |
10708 | | { PseudoVLUXSEG2EI32_V_M4_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4717 |
10709 | | { PseudoVLUXSEG2EI32_V_M4_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4718 |
10710 | | { PseudoVLUXSEG2EI32_V_M8_M2, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4719 |
10711 | | { PseudoVLUXSEG2EI32_V_M8_M2_MASK, VLUXSEG2EI32_V, 0x1, 0x0 }, // 4720 |
10712 | | { PseudoVLUXSEG2EI32_V_M2_M4, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4721 |
10713 | | { PseudoVLUXSEG2EI32_V_M2_M4_MASK, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4722 |
10714 | | { PseudoVLUXSEG2EI32_V_M4_M4, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4723 |
10715 | | { PseudoVLUXSEG2EI32_V_M4_M4_MASK, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4724 |
10716 | | { PseudoVLUXSEG2EI32_V_M8_M4, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4725 |
10717 | | { PseudoVLUXSEG2EI32_V_M8_M4_MASK, VLUXSEG2EI32_V, 0x2, 0x0 }, // 4726 |
10718 | | { PseudoVLUXSEG2EI32_V_MF2_MF8, VLUXSEG2EI32_V, 0x5, 0x0 }, // 4727 |
10719 | | { PseudoVLUXSEG2EI32_V_MF2_MF8_MASK, VLUXSEG2EI32_V, 0x5, 0x0 }, // 4728 |
10720 | | { PseudoVLUXSEG2EI32_V_M1_MF4, VLUXSEG2EI32_V, 0x6, 0x0 }, // 4729 |
10721 | | { PseudoVLUXSEG2EI32_V_M1_MF4_MASK, VLUXSEG2EI32_V, 0x6, 0x0 }, // 4730 |
10722 | | { PseudoVLUXSEG2EI32_V_MF2_MF4, VLUXSEG2EI32_V, 0x6, 0x0 }, // 4731 |
10723 | | { PseudoVLUXSEG2EI32_V_MF2_MF4_MASK, VLUXSEG2EI32_V, 0x6, 0x0 }, // 4732 |
10724 | | { PseudoVLUXSEG2EI32_V_M1_MF2, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4733 |
10725 | | { PseudoVLUXSEG2EI32_V_M1_MF2_MASK, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4734 |
10726 | | { PseudoVLUXSEG2EI32_V_M2_MF2, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4735 |
10727 | | { PseudoVLUXSEG2EI32_V_M2_MF2_MASK, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4736 |
10728 | | { PseudoVLUXSEG2EI32_V_MF2_MF2, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4737 |
10729 | | { PseudoVLUXSEG2EI32_V_MF2_MF2_MASK, VLUXSEG2EI32_V, 0x7, 0x0 }, // 4738 |
10730 | | { PseudoVLUXSEG2EI64_V_M1_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4739 |
10731 | | { PseudoVLUXSEG2EI64_V_M1_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4740 |
10732 | | { PseudoVLUXSEG2EI64_V_M2_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4741 |
10733 | | { PseudoVLUXSEG2EI64_V_M2_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4742 |
10734 | | { PseudoVLUXSEG2EI64_V_M4_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4743 |
10735 | | { PseudoVLUXSEG2EI64_V_M4_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4744 |
10736 | | { PseudoVLUXSEG2EI64_V_M8_M1, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4745 |
10737 | | { PseudoVLUXSEG2EI64_V_M8_M1_MASK, VLUXSEG2EI64_V, 0x0, 0x0 }, // 4746 |
10738 | | { PseudoVLUXSEG2EI64_V_M2_M2, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4747 |
10739 | | { PseudoVLUXSEG2EI64_V_M2_M2_MASK, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4748 |
10740 | | { PseudoVLUXSEG2EI64_V_M4_M2, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4749 |
10741 | | { PseudoVLUXSEG2EI64_V_M4_M2_MASK, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4750 |
10742 | | { PseudoVLUXSEG2EI64_V_M8_M2, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4751 |
10743 | | { PseudoVLUXSEG2EI64_V_M8_M2_MASK, VLUXSEG2EI64_V, 0x1, 0x0 }, // 4752 |
10744 | | { PseudoVLUXSEG2EI64_V_M4_M4, VLUXSEG2EI64_V, 0x2, 0x0 }, // 4753 |
10745 | | { PseudoVLUXSEG2EI64_V_M4_M4_MASK, VLUXSEG2EI64_V, 0x2, 0x0 }, // 4754 |
10746 | | { PseudoVLUXSEG2EI64_V_M8_M4, VLUXSEG2EI64_V, 0x2, 0x0 }, // 4755 |
10747 | | { PseudoVLUXSEG2EI64_V_M8_M4_MASK, VLUXSEG2EI64_V, 0x2, 0x0 }, // 4756 |
10748 | | { PseudoVLUXSEG2EI64_V_M1_MF8, VLUXSEG2EI64_V, 0x5, 0x0 }, // 4757 |
10749 | | { PseudoVLUXSEG2EI64_V_M1_MF8_MASK, VLUXSEG2EI64_V, 0x5, 0x0 }, // 4758 |
10750 | | { PseudoVLUXSEG2EI64_V_M1_MF4, VLUXSEG2EI64_V, 0x6, 0x0 }, // 4759 |
10751 | | { PseudoVLUXSEG2EI64_V_M1_MF4_MASK, VLUXSEG2EI64_V, 0x6, 0x0 }, // 4760 |
10752 | | { PseudoVLUXSEG2EI64_V_M2_MF4, VLUXSEG2EI64_V, 0x6, 0x0 }, // 4761 |
10753 | | { PseudoVLUXSEG2EI64_V_M2_MF4_MASK, VLUXSEG2EI64_V, 0x6, 0x0 }, // 4762 |
10754 | | { PseudoVLUXSEG2EI64_V_M1_MF2, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4763 |
10755 | | { PseudoVLUXSEG2EI64_V_M1_MF2_MASK, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4764 |
10756 | | { PseudoVLUXSEG2EI64_V_M2_MF2, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4765 |
10757 | | { PseudoVLUXSEG2EI64_V_M2_MF2_MASK, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4766 |
10758 | | { PseudoVLUXSEG2EI64_V_M4_MF2, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4767 |
10759 | | { PseudoVLUXSEG2EI64_V_M4_MF2_MASK, VLUXSEG2EI64_V, 0x7, 0x0 }, // 4768 |
10760 | | { PseudoVLUXSEG2EI8_V_M1_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4769 |
10761 | | { PseudoVLUXSEG2EI8_V_M1_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4770 |
10762 | | { PseudoVLUXSEG2EI8_V_MF2_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4771 |
10763 | | { PseudoVLUXSEG2EI8_V_MF2_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4772 |
10764 | | { PseudoVLUXSEG2EI8_V_MF4_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4773 |
10765 | | { PseudoVLUXSEG2EI8_V_MF4_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4774 |
10766 | | { PseudoVLUXSEG2EI8_V_MF8_M1, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4775 |
10767 | | { PseudoVLUXSEG2EI8_V_MF8_M1_MASK, VLUXSEG2EI8_V, 0x0, 0x0 }, // 4776 |
10768 | | { PseudoVLUXSEG2EI8_V_M1_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4777 |
10769 | | { PseudoVLUXSEG2EI8_V_M1_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4778 |
10770 | | { PseudoVLUXSEG2EI8_V_M2_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4779 |
10771 | | { PseudoVLUXSEG2EI8_V_M2_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4780 |
10772 | | { PseudoVLUXSEG2EI8_V_MF2_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4781 |
10773 | | { PseudoVLUXSEG2EI8_V_MF2_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4782 |
10774 | | { PseudoVLUXSEG2EI8_V_MF4_M2, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4783 |
10775 | | { PseudoVLUXSEG2EI8_V_MF4_M2_MASK, VLUXSEG2EI8_V, 0x1, 0x0 }, // 4784 |
10776 | | { PseudoVLUXSEG2EI8_V_M1_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4785 |
10777 | | { PseudoVLUXSEG2EI8_V_M1_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4786 |
10778 | | { PseudoVLUXSEG2EI8_V_M2_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4787 |
10779 | | { PseudoVLUXSEG2EI8_V_M2_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4788 |
10780 | | { PseudoVLUXSEG2EI8_V_M4_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4789 |
10781 | | { PseudoVLUXSEG2EI8_V_M4_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4790 |
10782 | | { PseudoVLUXSEG2EI8_V_MF2_M4, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4791 |
10783 | | { PseudoVLUXSEG2EI8_V_MF2_M4_MASK, VLUXSEG2EI8_V, 0x2, 0x0 }, // 4792 |
10784 | | { PseudoVLUXSEG2EI8_V_MF8_MF8, VLUXSEG2EI8_V, 0x5, 0x0 }, // 4793 |
10785 | | { PseudoVLUXSEG2EI8_V_MF8_MF8_MASK, VLUXSEG2EI8_V, 0x5, 0x0 }, // 4794 |
10786 | | { PseudoVLUXSEG2EI8_V_MF4_MF4, VLUXSEG2EI8_V, 0x6, 0x0 }, // 4795 |
10787 | | { PseudoVLUXSEG2EI8_V_MF4_MF4_MASK, VLUXSEG2EI8_V, 0x6, 0x0 }, // 4796 |
10788 | | { PseudoVLUXSEG2EI8_V_MF8_MF4, VLUXSEG2EI8_V, 0x6, 0x0 }, // 4797 |
10789 | | { PseudoVLUXSEG2EI8_V_MF8_MF4_MASK, VLUXSEG2EI8_V, 0x6, 0x0 }, // 4798 |
10790 | | { PseudoVLUXSEG2EI8_V_MF2_MF2, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4799 |
10791 | | { PseudoVLUXSEG2EI8_V_MF2_MF2_MASK, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4800 |
10792 | | { PseudoVLUXSEG2EI8_V_MF4_MF2, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4801 |
10793 | | { PseudoVLUXSEG2EI8_V_MF4_MF2_MASK, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4802 |
10794 | | { PseudoVLUXSEG2EI8_V_MF8_MF2, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4803 |
10795 | | { PseudoVLUXSEG2EI8_V_MF8_MF2_MASK, VLUXSEG2EI8_V, 0x7, 0x0 }, // 4804 |
10796 | | { PseudoVLUXSEG3EI16_V_M1_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4805 |
10797 | | { PseudoVLUXSEG3EI16_V_M1_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4806 |
10798 | | { PseudoVLUXSEG3EI16_V_M2_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4807 |
10799 | | { PseudoVLUXSEG3EI16_V_M2_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4808 |
10800 | | { PseudoVLUXSEG3EI16_V_MF2_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4809 |
10801 | | { PseudoVLUXSEG3EI16_V_MF2_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4810 |
10802 | | { PseudoVLUXSEG3EI16_V_MF4_M1, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4811 |
10803 | | { PseudoVLUXSEG3EI16_V_MF4_M1_MASK, VLUXSEG3EI16_V, 0x0, 0x0 }, // 4812 |
10804 | | { PseudoVLUXSEG3EI16_V_M1_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4813 |
10805 | | { PseudoVLUXSEG3EI16_V_M1_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4814 |
10806 | | { PseudoVLUXSEG3EI16_V_M2_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4815 |
10807 | | { PseudoVLUXSEG3EI16_V_M2_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4816 |
10808 | | { PseudoVLUXSEG3EI16_V_M4_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4817 |
10809 | | { PseudoVLUXSEG3EI16_V_M4_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4818 |
10810 | | { PseudoVLUXSEG3EI16_V_MF2_M2, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4819 |
10811 | | { PseudoVLUXSEG3EI16_V_MF2_M2_MASK, VLUXSEG3EI16_V, 0x1, 0x0 }, // 4820 |
10812 | | { PseudoVLUXSEG3EI16_V_MF4_MF8, VLUXSEG3EI16_V, 0x5, 0x0 }, // 4821 |
10813 | | { PseudoVLUXSEG3EI16_V_MF4_MF8_MASK, VLUXSEG3EI16_V, 0x5, 0x0 }, // 4822 |
10814 | | { PseudoVLUXSEG3EI16_V_MF2_MF4, VLUXSEG3EI16_V, 0x6, 0x0 }, // 4823 |
10815 | | { PseudoVLUXSEG3EI16_V_MF2_MF4_MASK, VLUXSEG3EI16_V, 0x6, 0x0 }, // 4824 |
10816 | | { PseudoVLUXSEG3EI16_V_MF4_MF4, VLUXSEG3EI16_V, 0x6, 0x0 }, // 4825 |
10817 | | { PseudoVLUXSEG3EI16_V_MF4_MF4_MASK, VLUXSEG3EI16_V, 0x6, 0x0 }, // 4826 |
10818 | | { PseudoVLUXSEG3EI16_V_M1_MF2, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4827 |
10819 | | { PseudoVLUXSEG3EI16_V_M1_MF2_MASK, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4828 |
10820 | | { PseudoVLUXSEG3EI16_V_MF2_MF2, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4829 |
10821 | | { PseudoVLUXSEG3EI16_V_MF2_MF2_MASK, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4830 |
10822 | | { PseudoVLUXSEG3EI16_V_MF4_MF2, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4831 |
10823 | | { PseudoVLUXSEG3EI16_V_MF4_MF2_MASK, VLUXSEG3EI16_V, 0x7, 0x0 }, // 4832 |
10824 | | { PseudoVLUXSEG3EI32_V_M1_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4833 |
10825 | | { PseudoVLUXSEG3EI32_V_M1_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4834 |
10826 | | { PseudoVLUXSEG3EI32_V_M2_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4835 |
10827 | | { PseudoVLUXSEG3EI32_V_M2_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4836 |
10828 | | { PseudoVLUXSEG3EI32_V_M4_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4837 |
10829 | | { PseudoVLUXSEG3EI32_V_M4_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4838 |
10830 | | { PseudoVLUXSEG3EI32_V_MF2_M1, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4839 |
10831 | | { PseudoVLUXSEG3EI32_V_MF2_M1_MASK, VLUXSEG3EI32_V, 0x0, 0x0 }, // 4840 |
10832 | | { PseudoVLUXSEG3EI32_V_M1_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4841 |
10833 | | { PseudoVLUXSEG3EI32_V_M1_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4842 |
10834 | | { PseudoVLUXSEG3EI32_V_M2_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4843 |
10835 | | { PseudoVLUXSEG3EI32_V_M2_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4844 |
10836 | | { PseudoVLUXSEG3EI32_V_M4_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4845 |
10837 | | { PseudoVLUXSEG3EI32_V_M4_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4846 |
10838 | | { PseudoVLUXSEG3EI32_V_M8_M2, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4847 |
10839 | | { PseudoVLUXSEG3EI32_V_M8_M2_MASK, VLUXSEG3EI32_V, 0x1, 0x0 }, // 4848 |
10840 | | { PseudoVLUXSEG3EI32_V_MF2_MF8, VLUXSEG3EI32_V, 0x5, 0x0 }, // 4849 |
10841 | | { PseudoVLUXSEG3EI32_V_MF2_MF8_MASK, VLUXSEG3EI32_V, 0x5, 0x0 }, // 4850 |
10842 | | { PseudoVLUXSEG3EI32_V_M1_MF4, VLUXSEG3EI32_V, 0x6, 0x0 }, // 4851 |
10843 | | { PseudoVLUXSEG3EI32_V_M1_MF4_MASK, VLUXSEG3EI32_V, 0x6, 0x0 }, // 4852 |
10844 | | { PseudoVLUXSEG3EI32_V_MF2_MF4, VLUXSEG3EI32_V, 0x6, 0x0 }, // 4853 |
10845 | | { PseudoVLUXSEG3EI32_V_MF2_MF4_MASK, VLUXSEG3EI32_V, 0x6, 0x0 }, // 4854 |
10846 | | { PseudoVLUXSEG3EI32_V_M1_MF2, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4855 |
10847 | | { PseudoVLUXSEG3EI32_V_M1_MF2_MASK, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4856 |
10848 | | { PseudoVLUXSEG3EI32_V_M2_MF2, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4857 |
10849 | | { PseudoVLUXSEG3EI32_V_M2_MF2_MASK, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4858 |
10850 | | { PseudoVLUXSEG3EI32_V_MF2_MF2, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4859 |
10851 | | { PseudoVLUXSEG3EI32_V_MF2_MF2_MASK, VLUXSEG3EI32_V, 0x7, 0x0 }, // 4860 |
10852 | | { PseudoVLUXSEG3EI64_V_M1_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4861 |
10853 | | { PseudoVLUXSEG3EI64_V_M1_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4862 |
10854 | | { PseudoVLUXSEG3EI64_V_M2_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4863 |
10855 | | { PseudoVLUXSEG3EI64_V_M2_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4864 |
10856 | | { PseudoVLUXSEG3EI64_V_M4_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4865 |
10857 | | { PseudoVLUXSEG3EI64_V_M4_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4866 |
10858 | | { PseudoVLUXSEG3EI64_V_M8_M1, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4867 |
10859 | | { PseudoVLUXSEG3EI64_V_M8_M1_MASK, VLUXSEG3EI64_V, 0x0, 0x0 }, // 4868 |
10860 | | { PseudoVLUXSEG3EI64_V_M2_M2, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4869 |
10861 | | { PseudoVLUXSEG3EI64_V_M2_M2_MASK, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4870 |
10862 | | { PseudoVLUXSEG3EI64_V_M4_M2, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4871 |
10863 | | { PseudoVLUXSEG3EI64_V_M4_M2_MASK, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4872 |
10864 | | { PseudoVLUXSEG3EI64_V_M8_M2, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4873 |
10865 | | { PseudoVLUXSEG3EI64_V_M8_M2_MASK, VLUXSEG3EI64_V, 0x1, 0x0 }, // 4874 |
10866 | | { PseudoVLUXSEG3EI64_V_M1_MF8, VLUXSEG3EI64_V, 0x5, 0x0 }, // 4875 |
10867 | | { PseudoVLUXSEG3EI64_V_M1_MF8_MASK, VLUXSEG3EI64_V, 0x5, 0x0 }, // 4876 |
10868 | | { PseudoVLUXSEG3EI64_V_M1_MF4, VLUXSEG3EI64_V, 0x6, 0x0 }, // 4877 |
10869 | | { PseudoVLUXSEG3EI64_V_M1_MF4_MASK, VLUXSEG3EI64_V, 0x6, 0x0 }, // 4878 |
10870 | | { PseudoVLUXSEG3EI64_V_M2_MF4, VLUXSEG3EI64_V, 0x6, 0x0 }, // 4879 |
10871 | | { PseudoVLUXSEG3EI64_V_M2_MF4_MASK, VLUXSEG3EI64_V, 0x6, 0x0 }, // 4880 |
10872 | | { PseudoVLUXSEG3EI64_V_M1_MF2, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4881 |
10873 | | { PseudoVLUXSEG3EI64_V_M1_MF2_MASK, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4882 |
10874 | | { PseudoVLUXSEG3EI64_V_M2_MF2, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4883 |
10875 | | { PseudoVLUXSEG3EI64_V_M2_MF2_MASK, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4884 |
10876 | | { PseudoVLUXSEG3EI64_V_M4_MF2, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4885 |
10877 | | { PseudoVLUXSEG3EI64_V_M4_MF2_MASK, VLUXSEG3EI64_V, 0x7, 0x0 }, // 4886 |
10878 | | { PseudoVLUXSEG3EI8_V_M1_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4887 |
10879 | | { PseudoVLUXSEG3EI8_V_M1_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4888 |
10880 | | { PseudoVLUXSEG3EI8_V_MF2_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4889 |
10881 | | { PseudoVLUXSEG3EI8_V_MF2_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4890 |
10882 | | { PseudoVLUXSEG3EI8_V_MF4_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4891 |
10883 | | { PseudoVLUXSEG3EI8_V_MF4_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4892 |
10884 | | { PseudoVLUXSEG3EI8_V_MF8_M1, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4893 |
10885 | | { PseudoVLUXSEG3EI8_V_MF8_M1_MASK, VLUXSEG3EI8_V, 0x0, 0x0 }, // 4894 |
10886 | | { PseudoVLUXSEG3EI8_V_M1_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4895 |
10887 | | { PseudoVLUXSEG3EI8_V_M1_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4896 |
10888 | | { PseudoVLUXSEG3EI8_V_M2_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4897 |
10889 | | { PseudoVLUXSEG3EI8_V_M2_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4898 |
10890 | | { PseudoVLUXSEG3EI8_V_MF2_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4899 |
10891 | | { PseudoVLUXSEG3EI8_V_MF2_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4900 |
10892 | | { PseudoVLUXSEG3EI8_V_MF4_M2, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4901 |
10893 | | { PseudoVLUXSEG3EI8_V_MF4_M2_MASK, VLUXSEG3EI8_V, 0x1, 0x0 }, // 4902 |
10894 | | { PseudoVLUXSEG3EI8_V_MF8_MF8, VLUXSEG3EI8_V, 0x5, 0x0 }, // 4903 |
10895 | | { PseudoVLUXSEG3EI8_V_MF8_MF8_MASK, VLUXSEG3EI8_V, 0x5, 0x0 }, // 4904 |
10896 | | { PseudoVLUXSEG3EI8_V_MF4_MF4, VLUXSEG3EI8_V, 0x6, 0x0 }, // 4905 |
10897 | | { PseudoVLUXSEG3EI8_V_MF4_MF4_MASK, VLUXSEG3EI8_V, 0x6, 0x0 }, // 4906 |
10898 | | { PseudoVLUXSEG3EI8_V_MF8_MF4, VLUXSEG3EI8_V, 0x6, 0x0 }, // 4907 |
10899 | | { PseudoVLUXSEG3EI8_V_MF8_MF4_MASK, VLUXSEG3EI8_V, 0x6, 0x0 }, // 4908 |
10900 | | { PseudoVLUXSEG3EI8_V_MF2_MF2, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4909 |
10901 | | { PseudoVLUXSEG3EI8_V_MF2_MF2_MASK, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4910 |
10902 | | { PseudoVLUXSEG3EI8_V_MF4_MF2, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4911 |
10903 | | { PseudoVLUXSEG3EI8_V_MF4_MF2_MASK, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4912 |
10904 | | { PseudoVLUXSEG3EI8_V_MF8_MF2, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4913 |
10905 | | { PseudoVLUXSEG3EI8_V_MF8_MF2_MASK, VLUXSEG3EI8_V, 0x7, 0x0 }, // 4914 |
10906 | | { PseudoVLUXSEG4EI16_V_M1_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4915 |
10907 | | { PseudoVLUXSEG4EI16_V_M1_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4916 |
10908 | | { PseudoVLUXSEG4EI16_V_M2_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4917 |
10909 | | { PseudoVLUXSEG4EI16_V_M2_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4918 |
10910 | | { PseudoVLUXSEG4EI16_V_MF2_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4919 |
10911 | | { PseudoVLUXSEG4EI16_V_MF2_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4920 |
10912 | | { PseudoVLUXSEG4EI16_V_MF4_M1, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4921 |
10913 | | { PseudoVLUXSEG4EI16_V_MF4_M1_MASK, VLUXSEG4EI16_V, 0x0, 0x0 }, // 4922 |
10914 | | { PseudoVLUXSEG4EI16_V_M1_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4923 |
10915 | | { PseudoVLUXSEG4EI16_V_M1_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4924 |
10916 | | { PseudoVLUXSEG4EI16_V_M2_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4925 |
10917 | | { PseudoVLUXSEG4EI16_V_M2_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4926 |
10918 | | { PseudoVLUXSEG4EI16_V_M4_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4927 |
10919 | | { PseudoVLUXSEG4EI16_V_M4_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4928 |
10920 | | { PseudoVLUXSEG4EI16_V_MF2_M2, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4929 |
10921 | | { PseudoVLUXSEG4EI16_V_MF2_M2_MASK, VLUXSEG4EI16_V, 0x1, 0x0 }, // 4930 |
10922 | | { PseudoVLUXSEG4EI16_V_MF4_MF8, VLUXSEG4EI16_V, 0x5, 0x0 }, // 4931 |
10923 | | { PseudoVLUXSEG4EI16_V_MF4_MF8_MASK, VLUXSEG4EI16_V, 0x5, 0x0 }, // 4932 |
10924 | | { PseudoVLUXSEG4EI16_V_MF2_MF4, VLUXSEG4EI16_V, 0x6, 0x0 }, // 4933 |
10925 | | { PseudoVLUXSEG4EI16_V_MF2_MF4_MASK, VLUXSEG4EI16_V, 0x6, 0x0 }, // 4934 |
10926 | | { PseudoVLUXSEG4EI16_V_MF4_MF4, VLUXSEG4EI16_V, 0x6, 0x0 }, // 4935 |
10927 | | { PseudoVLUXSEG4EI16_V_MF4_MF4_MASK, VLUXSEG4EI16_V, 0x6, 0x0 }, // 4936 |
10928 | | { PseudoVLUXSEG4EI16_V_M1_MF2, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4937 |
10929 | | { PseudoVLUXSEG4EI16_V_M1_MF2_MASK, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4938 |
10930 | | { PseudoVLUXSEG4EI16_V_MF2_MF2, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4939 |
10931 | | { PseudoVLUXSEG4EI16_V_MF2_MF2_MASK, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4940 |
10932 | | { PseudoVLUXSEG4EI16_V_MF4_MF2, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4941 |
10933 | | { PseudoVLUXSEG4EI16_V_MF4_MF2_MASK, VLUXSEG4EI16_V, 0x7, 0x0 }, // 4942 |
10934 | | { PseudoVLUXSEG4EI32_V_M1_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4943 |
10935 | | { PseudoVLUXSEG4EI32_V_M1_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4944 |
10936 | | { PseudoVLUXSEG4EI32_V_M2_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4945 |
10937 | | { PseudoVLUXSEG4EI32_V_M2_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4946 |
10938 | | { PseudoVLUXSEG4EI32_V_M4_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4947 |
10939 | | { PseudoVLUXSEG4EI32_V_M4_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4948 |
10940 | | { PseudoVLUXSEG4EI32_V_MF2_M1, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4949 |
10941 | | { PseudoVLUXSEG4EI32_V_MF2_M1_MASK, VLUXSEG4EI32_V, 0x0, 0x0 }, // 4950 |
10942 | | { PseudoVLUXSEG4EI32_V_M1_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4951 |
10943 | | { PseudoVLUXSEG4EI32_V_M1_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4952 |
10944 | | { PseudoVLUXSEG4EI32_V_M2_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4953 |
10945 | | { PseudoVLUXSEG4EI32_V_M2_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4954 |
10946 | | { PseudoVLUXSEG4EI32_V_M4_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4955 |
10947 | | { PseudoVLUXSEG4EI32_V_M4_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4956 |
10948 | | { PseudoVLUXSEG4EI32_V_M8_M2, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4957 |
10949 | | { PseudoVLUXSEG4EI32_V_M8_M2_MASK, VLUXSEG4EI32_V, 0x1, 0x0 }, // 4958 |
10950 | | { PseudoVLUXSEG4EI32_V_MF2_MF8, VLUXSEG4EI32_V, 0x5, 0x0 }, // 4959 |
10951 | | { PseudoVLUXSEG4EI32_V_MF2_MF8_MASK, VLUXSEG4EI32_V, 0x5, 0x0 }, // 4960 |
10952 | | { PseudoVLUXSEG4EI32_V_M1_MF4, VLUXSEG4EI32_V, 0x6, 0x0 }, // 4961 |
10953 | | { PseudoVLUXSEG4EI32_V_M1_MF4_MASK, VLUXSEG4EI32_V, 0x6, 0x0 }, // 4962 |
10954 | | { PseudoVLUXSEG4EI32_V_MF2_MF4, VLUXSEG4EI32_V, 0x6, 0x0 }, // 4963 |
10955 | | { PseudoVLUXSEG4EI32_V_MF2_MF4_MASK, VLUXSEG4EI32_V, 0x6, 0x0 }, // 4964 |
10956 | | { PseudoVLUXSEG4EI32_V_M1_MF2, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4965 |
10957 | | { PseudoVLUXSEG4EI32_V_M1_MF2_MASK, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4966 |
10958 | | { PseudoVLUXSEG4EI32_V_M2_MF2, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4967 |
10959 | | { PseudoVLUXSEG4EI32_V_M2_MF2_MASK, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4968 |
10960 | | { PseudoVLUXSEG4EI32_V_MF2_MF2, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4969 |
10961 | | { PseudoVLUXSEG4EI32_V_MF2_MF2_MASK, VLUXSEG4EI32_V, 0x7, 0x0 }, // 4970 |
10962 | | { PseudoVLUXSEG4EI64_V_M1_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4971 |
10963 | | { PseudoVLUXSEG4EI64_V_M1_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4972 |
10964 | | { PseudoVLUXSEG4EI64_V_M2_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4973 |
10965 | | { PseudoVLUXSEG4EI64_V_M2_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4974 |
10966 | | { PseudoVLUXSEG4EI64_V_M4_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4975 |
10967 | | { PseudoVLUXSEG4EI64_V_M4_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4976 |
10968 | | { PseudoVLUXSEG4EI64_V_M8_M1, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4977 |
10969 | | { PseudoVLUXSEG4EI64_V_M8_M1_MASK, VLUXSEG4EI64_V, 0x0, 0x0 }, // 4978 |
10970 | | { PseudoVLUXSEG4EI64_V_M2_M2, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4979 |
10971 | | { PseudoVLUXSEG4EI64_V_M2_M2_MASK, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4980 |
10972 | | { PseudoVLUXSEG4EI64_V_M4_M2, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4981 |
10973 | | { PseudoVLUXSEG4EI64_V_M4_M2_MASK, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4982 |
10974 | | { PseudoVLUXSEG4EI64_V_M8_M2, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4983 |
10975 | | { PseudoVLUXSEG4EI64_V_M8_M2_MASK, VLUXSEG4EI64_V, 0x1, 0x0 }, // 4984 |
10976 | | { PseudoVLUXSEG4EI64_V_M1_MF8, VLUXSEG4EI64_V, 0x5, 0x0 }, // 4985 |
10977 | | { PseudoVLUXSEG4EI64_V_M1_MF8_MASK, VLUXSEG4EI64_V, 0x5, 0x0 }, // 4986 |
10978 | | { PseudoVLUXSEG4EI64_V_M1_MF4, VLUXSEG4EI64_V, 0x6, 0x0 }, // 4987 |
10979 | | { PseudoVLUXSEG4EI64_V_M1_MF4_MASK, VLUXSEG4EI64_V, 0x6, 0x0 }, // 4988 |
10980 | | { PseudoVLUXSEG4EI64_V_M2_MF4, VLUXSEG4EI64_V, 0x6, 0x0 }, // 4989 |
10981 | | { PseudoVLUXSEG4EI64_V_M2_MF4_MASK, VLUXSEG4EI64_V, 0x6, 0x0 }, // 4990 |
10982 | | { PseudoVLUXSEG4EI64_V_M1_MF2, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4991 |
10983 | | { PseudoVLUXSEG4EI64_V_M1_MF2_MASK, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4992 |
10984 | | { PseudoVLUXSEG4EI64_V_M2_MF2, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4993 |
10985 | | { PseudoVLUXSEG4EI64_V_M2_MF2_MASK, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4994 |
10986 | | { PseudoVLUXSEG4EI64_V_M4_MF2, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4995 |
10987 | | { PseudoVLUXSEG4EI64_V_M4_MF2_MASK, VLUXSEG4EI64_V, 0x7, 0x0 }, // 4996 |
10988 | | { PseudoVLUXSEG4EI8_V_M1_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 4997 |
10989 | | { PseudoVLUXSEG4EI8_V_M1_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 4998 |
10990 | | { PseudoVLUXSEG4EI8_V_MF2_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 4999 |
10991 | | { PseudoVLUXSEG4EI8_V_MF2_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5000 |
10992 | | { PseudoVLUXSEG4EI8_V_MF4_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5001 |
10993 | | { PseudoVLUXSEG4EI8_V_MF4_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5002 |
10994 | | { PseudoVLUXSEG4EI8_V_MF8_M1, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5003 |
10995 | | { PseudoVLUXSEG4EI8_V_MF8_M1_MASK, VLUXSEG4EI8_V, 0x0, 0x0 }, // 5004 |
10996 | | { PseudoVLUXSEG4EI8_V_M1_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5005 |
10997 | | { PseudoVLUXSEG4EI8_V_M1_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5006 |
10998 | | { PseudoVLUXSEG4EI8_V_M2_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5007 |
10999 | | { PseudoVLUXSEG4EI8_V_M2_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5008 |
11000 | | { PseudoVLUXSEG4EI8_V_MF2_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5009 |
11001 | | { PseudoVLUXSEG4EI8_V_MF2_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5010 |
11002 | | { PseudoVLUXSEG4EI8_V_MF4_M2, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5011 |
11003 | | { PseudoVLUXSEG4EI8_V_MF4_M2_MASK, VLUXSEG4EI8_V, 0x1, 0x0 }, // 5012 |
11004 | | { PseudoVLUXSEG4EI8_V_MF8_MF8, VLUXSEG4EI8_V, 0x5, 0x0 }, // 5013 |
11005 | | { PseudoVLUXSEG4EI8_V_MF8_MF8_MASK, VLUXSEG4EI8_V, 0x5, 0x0 }, // 5014 |
11006 | | { PseudoVLUXSEG4EI8_V_MF4_MF4, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5015 |
11007 | | { PseudoVLUXSEG4EI8_V_MF4_MF4_MASK, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5016 |
11008 | | { PseudoVLUXSEG4EI8_V_MF8_MF4, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5017 |
11009 | | { PseudoVLUXSEG4EI8_V_MF8_MF4_MASK, VLUXSEG4EI8_V, 0x6, 0x0 }, // 5018 |
11010 | | { PseudoVLUXSEG4EI8_V_MF2_MF2, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5019 |
11011 | | { PseudoVLUXSEG4EI8_V_MF2_MF2_MASK, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5020 |
11012 | | { PseudoVLUXSEG4EI8_V_MF4_MF2, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5021 |
11013 | | { PseudoVLUXSEG4EI8_V_MF4_MF2_MASK, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5022 |
11014 | | { PseudoVLUXSEG4EI8_V_MF8_MF2, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5023 |
11015 | | { PseudoVLUXSEG4EI8_V_MF8_MF2_MASK, VLUXSEG4EI8_V, 0x7, 0x0 }, // 5024 |
11016 | | { PseudoVLUXSEG5EI16_V_M1_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5025 |
11017 | | { PseudoVLUXSEG5EI16_V_M1_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5026 |
11018 | | { PseudoVLUXSEG5EI16_V_M2_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5027 |
11019 | | { PseudoVLUXSEG5EI16_V_M2_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5028 |
11020 | | { PseudoVLUXSEG5EI16_V_MF2_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5029 |
11021 | | { PseudoVLUXSEG5EI16_V_MF2_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5030 |
11022 | | { PseudoVLUXSEG5EI16_V_MF4_M1, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5031 |
11023 | | { PseudoVLUXSEG5EI16_V_MF4_M1_MASK, VLUXSEG5EI16_V, 0x0, 0x0 }, // 5032 |
11024 | | { PseudoVLUXSEG5EI16_V_MF4_MF8, VLUXSEG5EI16_V, 0x5, 0x0 }, // 5033 |
11025 | | { PseudoVLUXSEG5EI16_V_MF4_MF8_MASK, VLUXSEG5EI16_V, 0x5, 0x0 }, // 5034 |
11026 | | { PseudoVLUXSEG5EI16_V_MF2_MF4, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5035 |
11027 | | { PseudoVLUXSEG5EI16_V_MF2_MF4_MASK, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5036 |
11028 | | { PseudoVLUXSEG5EI16_V_MF4_MF4, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5037 |
11029 | | { PseudoVLUXSEG5EI16_V_MF4_MF4_MASK, VLUXSEG5EI16_V, 0x6, 0x0 }, // 5038 |
11030 | | { PseudoVLUXSEG5EI16_V_M1_MF2, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5039 |
11031 | | { PseudoVLUXSEG5EI16_V_M1_MF2_MASK, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5040 |
11032 | | { PseudoVLUXSEG5EI16_V_MF2_MF2, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5041 |
11033 | | { PseudoVLUXSEG5EI16_V_MF2_MF2_MASK, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5042 |
11034 | | { PseudoVLUXSEG5EI16_V_MF4_MF2, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5043 |
11035 | | { PseudoVLUXSEG5EI16_V_MF4_MF2_MASK, VLUXSEG5EI16_V, 0x7, 0x0 }, // 5044 |
11036 | | { PseudoVLUXSEG5EI32_V_M1_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5045 |
11037 | | { PseudoVLUXSEG5EI32_V_M1_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5046 |
11038 | | { PseudoVLUXSEG5EI32_V_M2_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5047 |
11039 | | { PseudoVLUXSEG5EI32_V_M2_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5048 |
11040 | | { PseudoVLUXSEG5EI32_V_M4_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5049 |
11041 | | { PseudoVLUXSEG5EI32_V_M4_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5050 |
11042 | | { PseudoVLUXSEG5EI32_V_MF2_M1, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5051 |
11043 | | { PseudoVLUXSEG5EI32_V_MF2_M1_MASK, VLUXSEG5EI32_V, 0x0, 0x0 }, // 5052 |
11044 | | { PseudoVLUXSEG5EI32_V_MF2_MF8, VLUXSEG5EI32_V, 0x5, 0x0 }, // 5053 |
11045 | | { PseudoVLUXSEG5EI32_V_MF2_MF8_MASK, VLUXSEG5EI32_V, 0x5, 0x0 }, // 5054 |
11046 | | { PseudoVLUXSEG5EI32_V_M1_MF4, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5055 |
11047 | | { PseudoVLUXSEG5EI32_V_M1_MF4_MASK, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5056 |
11048 | | { PseudoVLUXSEG5EI32_V_MF2_MF4, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5057 |
11049 | | { PseudoVLUXSEG5EI32_V_MF2_MF4_MASK, VLUXSEG5EI32_V, 0x6, 0x0 }, // 5058 |
11050 | | { PseudoVLUXSEG5EI32_V_M1_MF2, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5059 |
11051 | | { PseudoVLUXSEG5EI32_V_M1_MF2_MASK, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5060 |
11052 | | { PseudoVLUXSEG5EI32_V_M2_MF2, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5061 |
11053 | | { PseudoVLUXSEG5EI32_V_M2_MF2_MASK, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5062 |
11054 | | { PseudoVLUXSEG5EI32_V_MF2_MF2, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5063 |
11055 | | { PseudoVLUXSEG5EI32_V_MF2_MF2_MASK, VLUXSEG5EI32_V, 0x7, 0x0 }, // 5064 |
11056 | | { PseudoVLUXSEG5EI64_V_M1_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5065 |
11057 | | { PseudoVLUXSEG5EI64_V_M1_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5066 |
11058 | | { PseudoVLUXSEG5EI64_V_M2_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5067 |
11059 | | { PseudoVLUXSEG5EI64_V_M2_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5068 |
11060 | | { PseudoVLUXSEG5EI64_V_M4_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5069 |
11061 | | { PseudoVLUXSEG5EI64_V_M4_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5070 |
11062 | | { PseudoVLUXSEG5EI64_V_M8_M1, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5071 |
11063 | | { PseudoVLUXSEG5EI64_V_M8_M1_MASK, VLUXSEG5EI64_V, 0x0, 0x0 }, // 5072 |
11064 | | { PseudoVLUXSEG5EI64_V_M1_MF8, VLUXSEG5EI64_V, 0x5, 0x0 }, // 5073 |
11065 | | { PseudoVLUXSEG5EI64_V_M1_MF8_MASK, VLUXSEG5EI64_V, 0x5, 0x0 }, // 5074 |
11066 | | { PseudoVLUXSEG5EI64_V_M1_MF4, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5075 |
11067 | | { PseudoVLUXSEG5EI64_V_M1_MF4_MASK, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5076 |
11068 | | { PseudoVLUXSEG5EI64_V_M2_MF4, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5077 |
11069 | | { PseudoVLUXSEG5EI64_V_M2_MF4_MASK, VLUXSEG5EI64_V, 0x6, 0x0 }, // 5078 |
11070 | | { PseudoVLUXSEG5EI64_V_M1_MF2, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5079 |
11071 | | { PseudoVLUXSEG5EI64_V_M1_MF2_MASK, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5080 |
11072 | | { PseudoVLUXSEG5EI64_V_M2_MF2, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5081 |
11073 | | { PseudoVLUXSEG5EI64_V_M2_MF2_MASK, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5082 |
11074 | | { PseudoVLUXSEG5EI64_V_M4_MF2, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5083 |
11075 | | { PseudoVLUXSEG5EI64_V_M4_MF2_MASK, VLUXSEG5EI64_V, 0x7, 0x0 }, // 5084 |
11076 | | { PseudoVLUXSEG5EI8_V_M1_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5085 |
11077 | | { PseudoVLUXSEG5EI8_V_M1_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5086 |
11078 | | { PseudoVLUXSEG5EI8_V_MF2_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5087 |
11079 | | { PseudoVLUXSEG5EI8_V_MF2_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5088 |
11080 | | { PseudoVLUXSEG5EI8_V_MF4_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5089 |
11081 | | { PseudoVLUXSEG5EI8_V_MF4_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5090 |
11082 | | { PseudoVLUXSEG5EI8_V_MF8_M1, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5091 |
11083 | | { PseudoVLUXSEG5EI8_V_MF8_M1_MASK, VLUXSEG5EI8_V, 0x0, 0x0 }, // 5092 |
11084 | | { PseudoVLUXSEG5EI8_V_MF8_MF8, VLUXSEG5EI8_V, 0x5, 0x0 }, // 5093 |
11085 | | { PseudoVLUXSEG5EI8_V_MF8_MF8_MASK, VLUXSEG5EI8_V, 0x5, 0x0 }, // 5094 |
11086 | | { PseudoVLUXSEG5EI8_V_MF4_MF4, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5095 |
11087 | | { PseudoVLUXSEG5EI8_V_MF4_MF4_MASK, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5096 |
11088 | | { PseudoVLUXSEG5EI8_V_MF8_MF4, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5097 |
11089 | | { PseudoVLUXSEG5EI8_V_MF8_MF4_MASK, VLUXSEG5EI8_V, 0x6, 0x0 }, // 5098 |
11090 | | { PseudoVLUXSEG5EI8_V_MF2_MF2, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5099 |
11091 | | { PseudoVLUXSEG5EI8_V_MF2_MF2_MASK, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5100 |
11092 | | { PseudoVLUXSEG5EI8_V_MF4_MF2, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5101 |
11093 | | { PseudoVLUXSEG5EI8_V_MF4_MF2_MASK, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5102 |
11094 | | { PseudoVLUXSEG5EI8_V_MF8_MF2, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5103 |
11095 | | { PseudoVLUXSEG5EI8_V_MF8_MF2_MASK, VLUXSEG5EI8_V, 0x7, 0x0 }, // 5104 |
11096 | | { PseudoVLUXSEG6EI16_V_M1_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5105 |
11097 | | { PseudoVLUXSEG6EI16_V_M1_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5106 |
11098 | | { PseudoVLUXSEG6EI16_V_M2_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5107 |
11099 | | { PseudoVLUXSEG6EI16_V_M2_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5108 |
11100 | | { PseudoVLUXSEG6EI16_V_MF2_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5109 |
11101 | | { PseudoVLUXSEG6EI16_V_MF2_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5110 |
11102 | | { PseudoVLUXSEG6EI16_V_MF4_M1, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5111 |
11103 | | { PseudoVLUXSEG6EI16_V_MF4_M1_MASK, VLUXSEG6EI16_V, 0x0, 0x0 }, // 5112 |
11104 | | { PseudoVLUXSEG6EI16_V_MF4_MF8, VLUXSEG6EI16_V, 0x5, 0x0 }, // 5113 |
11105 | | { PseudoVLUXSEG6EI16_V_MF4_MF8_MASK, VLUXSEG6EI16_V, 0x5, 0x0 }, // 5114 |
11106 | | { PseudoVLUXSEG6EI16_V_MF2_MF4, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5115 |
11107 | | { PseudoVLUXSEG6EI16_V_MF2_MF4_MASK, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5116 |
11108 | | { PseudoVLUXSEG6EI16_V_MF4_MF4, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5117 |
11109 | | { PseudoVLUXSEG6EI16_V_MF4_MF4_MASK, VLUXSEG6EI16_V, 0x6, 0x0 }, // 5118 |
11110 | | { PseudoVLUXSEG6EI16_V_M1_MF2, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5119 |
11111 | | { PseudoVLUXSEG6EI16_V_M1_MF2_MASK, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5120 |
11112 | | { PseudoVLUXSEG6EI16_V_MF2_MF2, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5121 |
11113 | | { PseudoVLUXSEG6EI16_V_MF2_MF2_MASK, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5122 |
11114 | | { PseudoVLUXSEG6EI16_V_MF4_MF2, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5123 |
11115 | | { PseudoVLUXSEG6EI16_V_MF4_MF2_MASK, VLUXSEG6EI16_V, 0x7, 0x0 }, // 5124 |
11116 | | { PseudoVLUXSEG6EI32_V_M1_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5125 |
11117 | | { PseudoVLUXSEG6EI32_V_M1_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5126 |
11118 | | { PseudoVLUXSEG6EI32_V_M2_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5127 |
11119 | | { PseudoVLUXSEG6EI32_V_M2_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5128 |
11120 | | { PseudoVLUXSEG6EI32_V_M4_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5129 |
11121 | | { PseudoVLUXSEG6EI32_V_M4_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5130 |
11122 | | { PseudoVLUXSEG6EI32_V_MF2_M1, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5131 |
11123 | | { PseudoVLUXSEG6EI32_V_MF2_M1_MASK, VLUXSEG6EI32_V, 0x0, 0x0 }, // 5132 |
11124 | | { PseudoVLUXSEG6EI32_V_MF2_MF8, VLUXSEG6EI32_V, 0x5, 0x0 }, // 5133 |
11125 | | { PseudoVLUXSEG6EI32_V_MF2_MF8_MASK, VLUXSEG6EI32_V, 0x5, 0x0 }, // 5134 |
11126 | | { PseudoVLUXSEG6EI32_V_M1_MF4, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5135 |
11127 | | { PseudoVLUXSEG6EI32_V_M1_MF4_MASK, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5136 |
11128 | | { PseudoVLUXSEG6EI32_V_MF2_MF4, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5137 |
11129 | | { PseudoVLUXSEG6EI32_V_MF2_MF4_MASK, VLUXSEG6EI32_V, 0x6, 0x0 }, // 5138 |
11130 | | { PseudoVLUXSEG6EI32_V_M1_MF2, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5139 |
11131 | | { PseudoVLUXSEG6EI32_V_M1_MF2_MASK, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5140 |
11132 | | { PseudoVLUXSEG6EI32_V_M2_MF2, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5141 |
11133 | | { PseudoVLUXSEG6EI32_V_M2_MF2_MASK, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5142 |
11134 | | { PseudoVLUXSEG6EI32_V_MF2_MF2, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5143 |
11135 | | { PseudoVLUXSEG6EI32_V_MF2_MF2_MASK, VLUXSEG6EI32_V, 0x7, 0x0 }, // 5144 |
11136 | | { PseudoVLUXSEG6EI64_V_M1_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5145 |
11137 | | { PseudoVLUXSEG6EI64_V_M1_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5146 |
11138 | | { PseudoVLUXSEG6EI64_V_M2_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5147 |
11139 | | { PseudoVLUXSEG6EI64_V_M2_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5148 |
11140 | | { PseudoVLUXSEG6EI64_V_M4_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5149 |
11141 | | { PseudoVLUXSEG6EI64_V_M4_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5150 |
11142 | | { PseudoVLUXSEG6EI64_V_M8_M1, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5151 |
11143 | | { PseudoVLUXSEG6EI64_V_M8_M1_MASK, VLUXSEG6EI64_V, 0x0, 0x0 }, // 5152 |
11144 | | { PseudoVLUXSEG6EI64_V_M1_MF8, VLUXSEG6EI64_V, 0x5, 0x0 }, // 5153 |
11145 | | { PseudoVLUXSEG6EI64_V_M1_MF8_MASK, VLUXSEG6EI64_V, 0x5, 0x0 }, // 5154 |
11146 | | { PseudoVLUXSEG6EI64_V_M1_MF4, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5155 |
11147 | | { PseudoVLUXSEG6EI64_V_M1_MF4_MASK, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5156 |
11148 | | { PseudoVLUXSEG6EI64_V_M2_MF4, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5157 |
11149 | | { PseudoVLUXSEG6EI64_V_M2_MF4_MASK, VLUXSEG6EI64_V, 0x6, 0x0 }, // 5158 |
11150 | | { PseudoVLUXSEG6EI64_V_M1_MF2, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5159 |
11151 | | { PseudoVLUXSEG6EI64_V_M1_MF2_MASK, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5160 |
11152 | | { PseudoVLUXSEG6EI64_V_M2_MF2, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5161 |
11153 | | { PseudoVLUXSEG6EI64_V_M2_MF2_MASK, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5162 |
11154 | | { PseudoVLUXSEG6EI64_V_M4_MF2, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5163 |
11155 | | { PseudoVLUXSEG6EI64_V_M4_MF2_MASK, VLUXSEG6EI64_V, 0x7, 0x0 }, // 5164 |
11156 | | { PseudoVLUXSEG6EI8_V_M1_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5165 |
11157 | | { PseudoVLUXSEG6EI8_V_M1_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5166 |
11158 | | { PseudoVLUXSEG6EI8_V_MF2_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5167 |
11159 | | { PseudoVLUXSEG6EI8_V_MF2_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5168 |
11160 | | { PseudoVLUXSEG6EI8_V_MF4_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5169 |
11161 | | { PseudoVLUXSEG6EI8_V_MF4_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5170 |
11162 | | { PseudoVLUXSEG6EI8_V_MF8_M1, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5171 |
11163 | | { PseudoVLUXSEG6EI8_V_MF8_M1_MASK, VLUXSEG6EI8_V, 0x0, 0x0 }, // 5172 |
11164 | | { PseudoVLUXSEG6EI8_V_MF8_MF8, VLUXSEG6EI8_V, 0x5, 0x0 }, // 5173 |
11165 | | { PseudoVLUXSEG6EI8_V_MF8_MF8_MASK, VLUXSEG6EI8_V, 0x5, 0x0 }, // 5174 |
11166 | | { PseudoVLUXSEG6EI8_V_MF4_MF4, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5175 |
11167 | | { PseudoVLUXSEG6EI8_V_MF4_MF4_MASK, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5176 |
11168 | | { PseudoVLUXSEG6EI8_V_MF8_MF4, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5177 |
11169 | | { PseudoVLUXSEG6EI8_V_MF8_MF4_MASK, VLUXSEG6EI8_V, 0x6, 0x0 }, // 5178 |
11170 | | { PseudoVLUXSEG6EI8_V_MF2_MF2, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5179 |
11171 | | { PseudoVLUXSEG6EI8_V_MF2_MF2_MASK, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5180 |
11172 | | { PseudoVLUXSEG6EI8_V_MF4_MF2, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5181 |
11173 | | { PseudoVLUXSEG6EI8_V_MF4_MF2_MASK, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5182 |
11174 | | { PseudoVLUXSEG6EI8_V_MF8_MF2, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5183 |
11175 | | { PseudoVLUXSEG6EI8_V_MF8_MF2_MASK, VLUXSEG6EI8_V, 0x7, 0x0 }, // 5184 |
11176 | | { PseudoVLUXSEG7EI16_V_M1_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5185 |
11177 | | { PseudoVLUXSEG7EI16_V_M1_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5186 |
11178 | | { PseudoVLUXSEG7EI16_V_M2_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5187 |
11179 | | { PseudoVLUXSEG7EI16_V_M2_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5188 |
11180 | | { PseudoVLUXSEG7EI16_V_MF2_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5189 |
11181 | | { PseudoVLUXSEG7EI16_V_MF2_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5190 |
11182 | | { PseudoVLUXSEG7EI16_V_MF4_M1, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5191 |
11183 | | { PseudoVLUXSEG7EI16_V_MF4_M1_MASK, VLUXSEG7EI16_V, 0x0, 0x0 }, // 5192 |
11184 | | { PseudoVLUXSEG7EI16_V_MF4_MF8, VLUXSEG7EI16_V, 0x5, 0x0 }, // 5193 |
11185 | | { PseudoVLUXSEG7EI16_V_MF4_MF8_MASK, VLUXSEG7EI16_V, 0x5, 0x0 }, // 5194 |
11186 | | { PseudoVLUXSEG7EI16_V_MF2_MF4, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5195 |
11187 | | { PseudoVLUXSEG7EI16_V_MF2_MF4_MASK, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5196 |
11188 | | { PseudoVLUXSEG7EI16_V_MF4_MF4, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5197 |
11189 | | { PseudoVLUXSEG7EI16_V_MF4_MF4_MASK, VLUXSEG7EI16_V, 0x6, 0x0 }, // 5198 |
11190 | | { PseudoVLUXSEG7EI16_V_M1_MF2, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5199 |
11191 | | { PseudoVLUXSEG7EI16_V_M1_MF2_MASK, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5200 |
11192 | | { PseudoVLUXSEG7EI16_V_MF2_MF2, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5201 |
11193 | | { PseudoVLUXSEG7EI16_V_MF2_MF2_MASK, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5202 |
11194 | | { PseudoVLUXSEG7EI16_V_MF4_MF2, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5203 |
11195 | | { PseudoVLUXSEG7EI16_V_MF4_MF2_MASK, VLUXSEG7EI16_V, 0x7, 0x0 }, // 5204 |
11196 | | { PseudoVLUXSEG7EI32_V_M1_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5205 |
11197 | | { PseudoVLUXSEG7EI32_V_M1_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5206 |
11198 | | { PseudoVLUXSEG7EI32_V_M2_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5207 |
11199 | | { PseudoVLUXSEG7EI32_V_M2_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5208 |
11200 | | { PseudoVLUXSEG7EI32_V_M4_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5209 |
11201 | | { PseudoVLUXSEG7EI32_V_M4_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5210 |
11202 | | { PseudoVLUXSEG7EI32_V_MF2_M1, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5211 |
11203 | | { PseudoVLUXSEG7EI32_V_MF2_M1_MASK, VLUXSEG7EI32_V, 0x0, 0x0 }, // 5212 |
11204 | | { PseudoVLUXSEG7EI32_V_MF2_MF8, VLUXSEG7EI32_V, 0x5, 0x0 }, // 5213 |
11205 | | { PseudoVLUXSEG7EI32_V_MF2_MF8_MASK, VLUXSEG7EI32_V, 0x5, 0x0 }, // 5214 |
11206 | | { PseudoVLUXSEG7EI32_V_M1_MF4, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5215 |
11207 | | { PseudoVLUXSEG7EI32_V_M1_MF4_MASK, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5216 |
11208 | | { PseudoVLUXSEG7EI32_V_MF2_MF4, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5217 |
11209 | | { PseudoVLUXSEG7EI32_V_MF2_MF4_MASK, VLUXSEG7EI32_V, 0x6, 0x0 }, // 5218 |
11210 | | { PseudoVLUXSEG7EI32_V_M1_MF2, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5219 |
11211 | | { PseudoVLUXSEG7EI32_V_M1_MF2_MASK, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5220 |
11212 | | { PseudoVLUXSEG7EI32_V_M2_MF2, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5221 |
11213 | | { PseudoVLUXSEG7EI32_V_M2_MF2_MASK, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5222 |
11214 | | { PseudoVLUXSEG7EI32_V_MF2_MF2, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5223 |
11215 | | { PseudoVLUXSEG7EI32_V_MF2_MF2_MASK, VLUXSEG7EI32_V, 0x7, 0x0 }, // 5224 |
11216 | | { PseudoVLUXSEG7EI64_V_M1_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5225 |
11217 | | { PseudoVLUXSEG7EI64_V_M1_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5226 |
11218 | | { PseudoVLUXSEG7EI64_V_M2_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5227 |
11219 | | { PseudoVLUXSEG7EI64_V_M2_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5228 |
11220 | | { PseudoVLUXSEG7EI64_V_M4_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5229 |
11221 | | { PseudoVLUXSEG7EI64_V_M4_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5230 |
11222 | | { PseudoVLUXSEG7EI64_V_M8_M1, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5231 |
11223 | | { PseudoVLUXSEG7EI64_V_M8_M1_MASK, VLUXSEG7EI64_V, 0x0, 0x0 }, // 5232 |
11224 | | { PseudoVLUXSEG7EI64_V_M1_MF8, VLUXSEG7EI64_V, 0x5, 0x0 }, // 5233 |
11225 | | { PseudoVLUXSEG7EI64_V_M1_MF8_MASK, VLUXSEG7EI64_V, 0x5, 0x0 }, // 5234 |
11226 | | { PseudoVLUXSEG7EI64_V_M1_MF4, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5235 |
11227 | | { PseudoVLUXSEG7EI64_V_M1_MF4_MASK, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5236 |
11228 | | { PseudoVLUXSEG7EI64_V_M2_MF4, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5237 |
11229 | | { PseudoVLUXSEG7EI64_V_M2_MF4_MASK, VLUXSEG7EI64_V, 0x6, 0x0 }, // 5238 |
11230 | | { PseudoVLUXSEG7EI64_V_M1_MF2, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5239 |
11231 | | { PseudoVLUXSEG7EI64_V_M1_MF2_MASK, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5240 |
11232 | | { PseudoVLUXSEG7EI64_V_M2_MF2, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5241 |
11233 | | { PseudoVLUXSEG7EI64_V_M2_MF2_MASK, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5242 |
11234 | | { PseudoVLUXSEG7EI64_V_M4_MF2, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5243 |
11235 | | { PseudoVLUXSEG7EI64_V_M4_MF2_MASK, VLUXSEG7EI64_V, 0x7, 0x0 }, // 5244 |
11236 | | { PseudoVLUXSEG7EI8_V_M1_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5245 |
11237 | | { PseudoVLUXSEG7EI8_V_M1_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5246 |
11238 | | { PseudoVLUXSEG7EI8_V_MF2_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5247 |
11239 | | { PseudoVLUXSEG7EI8_V_MF2_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5248 |
11240 | | { PseudoVLUXSEG7EI8_V_MF4_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5249 |
11241 | | { PseudoVLUXSEG7EI8_V_MF4_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5250 |
11242 | | { PseudoVLUXSEG7EI8_V_MF8_M1, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5251 |
11243 | | { PseudoVLUXSEG7EI8_V_MF8_M1_MASK, VLUXSEG7EI8_V, 0x0, 0x0 }, // 5252 |
11244 | | { PseudoVLUXSEG7EI8_V_MF8_MF8, VLUXSEG7EI8_V, 0x5, 0x0 }, // 5253 |
11245 | | { PseudoVLUXSEG7EI8_V_MF8_MF8_MASK, VLUXSEG7EI8_V, 0x5, 0x0 }, // 5254 |
11246 | | { PseudoVLUXSEG7EI8_V_MF4_MF4, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5255 |
11247 | | { PseudoVLUXSEG7EI8_V_MF4_MF4_MASK, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5256 |
11248 | | { PseudoVLUXSEG7EI8_V_MF8_MF4, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5257 |
11249 | | { PseudoVLUXSEG7EI8_V_MF8_MF4_MASK, VLUXSEG7EI8_V, 0x6, 0x0 }, // 5258 |
11250 | | { PseudoVLUXSEG7EI8_V_MF2_MF2, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5259 |
11251 | | { PseudoVLUXSEG7EI8_V_MF2_MF2_MASK, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5260 |
11252 | | { PseudoVLUXSEG7EI8_V_MF4_MF2, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5261 |
11253 | | { PseudoVLUXSEG7EI8_V_MF4_MF2_MASK, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5262 |
11254 | | { PseudoVLUXSEG7EI8_V_MF8_MF2, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5263 |
11255 | | { PseudoVLUXSEG7EI8_V_MF8_MF2_MASK, VLUXSEG7EI8_V, 0x7, 0x0 }, // 5264 |
11256 | | { PseudoVLUXSEG8EI16_V_M1_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5265 |
11257 | | { PseudoVLUXSEG8EI16_V_M1_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5266 |
11258 | | { PseudoVLUXSEG8EI16_V_M2_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5267 |
11259 | | { PseudoVLUXSEG8EI16_V_M2_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5268 |
11260 | | { PseudoVLUXSEG8EI16_V_MF2_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5269 |
11261 | | { PseudoVLUXSEG8EI16_V_MF2_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5270 |
11262 | | { PseudoVLUXSEG8EI16_V_MF4_M1, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5271 |
11263 | | { PseudoVLUXSEG8EI16_V_MF4_M1_MASK, VLUXSEG8EI16_V, 0x0, 0x0 }, // 5272 |
11264 | | { PseudoVLUXSEG8EI16_V_MF4_MF8, VLUXSEG8EI16_V, 0x5, 0x0 }, // 5273 |
11265 | | { PseudoVLUXSEG8EI16_V_MF4_MF8_MASK, VLUXSEG8EI16_V, 0x5, 0x0 }, // 5274 |
11266 | | { PseudoVLUXSEG8EI16_V_MF2_MF4, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5275 |
11267 | | { PseudoVLUXSEG8EI16_V_MF2_MF4_MASK, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5276 |
11268 | | { PseudoVLUXSEG8EI16_V_MF4_MF4, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5277 |
11269 | | { PseudoVLUXSEG8EI16_V_MF4_MF4_MASK, VLUXSEG8EI16_V, 0x6, 0x0 }, // 5278 |
11270 | | { PseudoVLUXSEG8EI16_V_M1_MF2, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5279 |
11271 | | { PseudoVLUXSEG8EI16_V_M1_MF2_MASK, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5280 |
11272 | | { PseudoVLUXSEG8EI16_V_MF2_MF2, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5281 |
11273 | | { PseudoVLUXSEG8EI16_V_MF2_MF2_MASK, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5282 |
11274 | | { PseudoVLUXSEG8EI16_V_MF4_MF2, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5283 |
11275 | | { PseudoVLUXSEG8EI16_V_MF4_MF2_MASK, VLUXSEG8EI16_V, 0x7, 0x0 }, // 5284 |
11276 | | { PseudoVLUXSEG8EI32_V_M1_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5285 |
11277 | | { PseudoVLUXSEG8EI32_V_M1_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5286 |
11278 | | { PseudoVLUXSEG8EI32_V_M2_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5287 |
11279 | | { PseudoVLUXSEG8EI32_V_M2_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5288 |
11280 | | { PseudoVLUXSEG8EI32_V_M4_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5289 |
11281 | | { PseudoVLUXSEG8EI32_V_M4_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5290 |
11282 | | { PseudoVLUXSEG8EI32_V_MF2_M1, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5291 |
11283 | | { PseudoVLUXSEG8EI32_V_MF2_M1_MASK, VLUXSEG8EI32_V, 0x0, 0x0 }, // 5292 |
11284 | | { PseudoVLUXSEG8EI32_V_MF2_MF8, VLUXSEG8EI32_V, 0x5, 0x0 }, // 5293 |
11285 | | { PseudoVLUXSEG8EI32_V_MF2_MF8_MASK, VLUXSEG8EI32_V, 0x5, 0x0 }, // 5294 |
11286 | | { PseudoVLUXSEG8EI32_V_M1_MF4, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5295 |
11287 | | { PseudoVLUXSEG8EI32_V_M1_MF4_MASK, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5296 |
11288 | | { PseudoVLUXSEG8EI32_V_MF2_MF4, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5297 |
11289 | | { PseudoVLUXSEG8EI32_V_MF2_MF4_MASK, VLUXSEG8EI32_V, 0x6, 0x0 }, // 5298 |
11290 | | { PseudoVLUXSEG8EI32_V_M1_MF2, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5299 |
11291 | | { PseudoVLUXSEG8EI32_V_M1_MF2_MASK, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5300 |
11292 | | { PseudoVLUXSEG8EI32_V_M2_MF2, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5301 |
11293 | | { PseudoVLUXSEG8EI32_V_M2_MF2_MASK, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5302 |
11294 | | { PseudoVLUXSEG8EI32_V_MF2_MF2, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5303 |
11295 | | { PseudoVLUXSEG8EI32_V_MF2_MF2_MASK, VLUXSEG8EI32_V, 0x7, 0x0 }, // 5304 |
11296 | | { PseudoVLUXSEG8EI64_V_M1_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5305 |
11297 | | { PseudoVLUXSEG8EI64_V_M1_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5306 |
11298 | | { PseudoVLUXSEG8EI64_V_M2_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5307 |
11299 | | { PseudoVLUXSEG8EI64_V_M2_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5308 |
11300 | | { PseudoVLUXSEG8EI64_V_M4_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5309 |
11301 | | { PseudoVLUXSEG8EI64_V_M4_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5310 |
11302 | | { PseudoVLUXSEG8EI64_V_M8_M1, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5311 |
11303 | | { PseudoVLUXSEG8EI64_V_M8_M1_MASK, VLUXSEG8EI64_V, 0x0, 0x0 }, // 5312 |
11304 | | { PseudoVLUXSEG8EI64_V_M1_MF8, VLUXSEG8EI64_V, 0x5, 0x0 }, // 5313 |
11305 | | { PseudoVLUXSEG8EI64_V_M1_MF8_MASK, VLUXSEG8EI64_V, 0x5, 0x0 }, // 5314 |
11306 | | { PseudoVLUXSEG8EI64_V_M1_MF4, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5315 |
11307 | | { PseudoVLUXSEG8EI64_V_M1_MF4_MASK, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5316 |
11308 | | { PseudoVLUXSEG8EI64_V_M2_MF4, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5317 |
11309 | | { PseudoVLUXSEG8EI64_V_M2_MF4_MASK, VLUXSEG8EI64_V, 0x6, 0x0 }, // 5318 |
11310 | | { PseudoVLUXSEG8EI64_V_M1_MF2, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5319 |
11311 | | { PseudoVLUXSEG8EI64_V_M1_MF2_MASK, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5320 |
11312 | | { PseudoVLUXSEG8EI64_V_M2_MF2, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5321 |
11313 | | { PseudoVLUXSEG8EI64_V_M2_MF2_MASK, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5322 |
11314 | | { PseudoVLUXSEG8EI64_V_M4_MF2, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5323 |
11315 | | { PseudoVLUXSEG8EI64_V_M4_MF2_MASK, VLUXSEG8EI64_V, 0x7, 0x0 }, // 5324 |
11316 | | { PseudoVLUXSEG8EI8_V_M1_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5325 |
11317 | | { PseudoVLUXSEG8EI8_V_M1_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5326 |
11318 | | { PseudoVLUXSEG8EI8_V_MF2_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5327 |
11319 | | { PseudoVLUXSEG8EI8_V_MF2_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5328 |
11320 | | { PseudoVLUXSEG8EI8_V_MF4_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5329 |
11321 | | { PseudoVLUXSEG8EI8_V_MF4_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5330 |
11322 | | { PseudoVLUXSEG8EI8_V_MF8_M1, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5331 |
11323 | | { PseudoVLUXSEG8EI8_V_MF8_M1_MASK, VLUXSEG8EI8_V, 0x0, 0x0 }, // 5332 |
11324 | | { PseudoVLUXSEG8EI8_V_MF8_MF8, VLUXSEG8EI8_V, 0x5, 0x0 }, // 5333 |
11325 | | { PseudoVLUXSEG8EI8_V_MF8_MF8_MASK, VLUXSEG8EI8_V, 0x5, 0x0 }, // 5334 |
11326 | | { PseudoVLUXSEG8EI8_V_MF4_MF4, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5335 |
11327 | | { PseudoVLUXSEG8EI8_V_MF4_MF4_MASK, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5336 |
11328 | | { PseudoVLUXSEG8EI8_V_MF8_MF4, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5337 |
11329 | | { PseudoVLUXSEG8EI8_V_MF8_MF4_MASK, VLUXSEG8EI8_V, 0x6, 0x0 }, // 5338 |
11330 | | { PseudoVLUXSEG8EI8_V_MF2_MF2, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5339 |
11331 | | { PseudoVLUXSEG8EI8_V_MF2_MF2_MASK, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5340 |
11332 | | { PseudoVLUXSEG8EI8_V_MF4_MF2, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5341 |
11333 | | { PseudoVLUXSEG8EI8_V_MF4_MF2_MASK, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5342 |
11334 | | { PseudoVLUXSEG8EI8_V_MF8_MF2, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5343 |
11335 | | { PseudoVLUXSEG8EI8_V_MF8_MF2_MASK, VLUXSEG8EI8_V, 0x7, 0x0 }, // 5344 |
11336 | | { PseudoVMACC_VV_M1, VMACC_VV, 0x0, 0x0 }, // 5345 |
11337 | | { PseudoVMACC_VV_M1_MASK, VMACC_VV, 0x0, 0x0 }, // 5346 |
11338 | | { PseudoVMACC_VV_M2, VMACC_VV, 0x1, 0x0 }, // 5347 |
11339 | | { PseudoVMACC_VV_M2_MASK, VMACC_VV, 0x1, 0x0 }, // 5348 |
11340 | | { PseudoVMACC_VV_M4, VMACC_VV, 0x2, 0x0 }, // 5349 |
11341 | | { PseudoVMACC_VV_M4_MASK, VMACC_VV, 0x2, 0x0 }, // 5350 |
11342 | | { PseudoVMACC_VV_M8, VMACC_VV, 0x3, 0x0 }, // 5351 |
11343 | | { PseudoVMACC_VV_M8_MASK, VMACC_VV, 0x3, 0x0 }, // 5352 |
11344 | | { PseudoVMACC_VV_MF8, VMACC_VV, 0x5, 0x0 }, // 5353 |
11345 | | { PseudoVMACC_VV_MF8_MASK, VMACC_VV, 0x5, 0x0 }, // 5354 |
11346 | | { PseudoVMACC_VV_MF4, VMACC_VV, 0x6, 0x0 }, // 5355 |
11347 | | { PseudoVMACC_VV_MF4_MASK, VMACC_VV, 0x6, 0x0 }, // 5356 |
11348 | | { PseudoVMACC_VV_MF2, VMACC_VV, 0x7, 0x0 }, // 5357 |
11349 | | { PseudoVMACC_VV_MF2_MASK, VMACC_VV, 0x7, 0x0 }, // 5358 |
11350 | | { PseudoVMACC_VX_M1, VMACC_VX, 0x0, 0x0 }, // 5359 |
11351 | | { PseudoVMACC_VX_M1_MASK, VMACC_VX, 0x0, 0x0 }, // 5360 |
11352 | | { PseudoVMACC_VX_M2, VMACC_VX, 0x1, 0x0 }, // 5361 |
11353 | | { PseudoVMACC_VX_M2_MASK, VMACC_VX, 0x1, 0x0 }, // 5362 |
11354 | | { PseudoVMACC_VX_M4, VMACC_VX, 0x2, 0x0 }, // 5363 |
11355 | | { PseudoVMACC_VX_M4_MASK, VMACC_VX, 0x2, 0x0 }, // 5364 |
11356 | | { PseudoVMACC_VX_M8, VMACC_VX, 0x3, 0x0 }, // 5365 |
11357 | | { PseudoVMACC_VX_M8_MASK, VMACC_VX, 0x3, 0x0 }, // 5366 |
11358 | | { PseudoVMACC_VX_MF8, VMACC_VX, 0x5, 0x0 }, // 5367 |
11359 | | { PseudoVMACC_VX_MF8_MASK, VMACC_VX, 0x5, 0x0 }, // 5368 |
11360 | | { PseudoVMACC_VX_MF4, VMACC_VX, 0x6, 0x0 }, // 5369 |
11361 | | { PseudoVMACC_VX_MF4_MASK, VMACC_VX, 0x6, 0x0 }, // 5370 |
11362 | | { PseudoVMACC_VX_MF2, VMACC_VX, 0x7, 0x0 }, // 5371 |
11363 | | { PseudoVMACC_VX_MF2_MASK, VMACC_VX, 0x7, 0x0 }, // 5372 |
11364 | | { PseudoVMADC_VI_M1, VMADC_VI, 0x0, 0x0 }, // 5373 |
11365 | | { PseudoVMADC_VI_M2, VMADC_VI, 0x1, 0x0 }, // 5374 |
11366 | | { PseudoVMADC_VI_M4, VMADC_VI, 0x2, 0x0 }, // 5375 |
11367 | | { PseudoVMADC_VI_M8, VMADC_VI, 0x3, 0x0 }, // 5376 |
11368 | | { PseudoVMADC_VI_MF8, VMADC_VI, 0x5, 0x0 }, // 5377 |
11369 | | { PseudoVMADC_VI_MF4, VMADC_VI, 0x6, 0x0 }, // 5378 |
11370 | | { PseudoVMADC_VI_MF2, VMADC_VI, 0x7, 0x0 }, // 5379 |
11371 | | { PseudoVMADC_VIM_M1, VMADC_VIM, 0x0, 0x0 }, // 5380 |
11372 | | { PseudoVMADC_VIM_M2, VMADC_VIM, 0x1, 0x0 }, // 5381 |
11373 | | { PseudoVMADC_VIM_M4, VMADC_VIM, 0x2, 0x0 }, // 5382 |
11374 | | { PseudoVMADC_VIM_M8, VMADC_VIM, 0x3, 0x0 }, // 5383 |
11375 | | { PseudoVMADC_VIM_MF8, VMADC_VIM, 0x5, 0x0 }, // 5384 |
11376 | | { PseudoVMADC_VIM_MF4, VMADC_VIM, 0x6, 0x0 }, // 5385 |
11377 | | { PseudoVMADC_VIM_MF2, VMADC_VIM, 0x7, 0x0 }, // 5386 |
11378 | | { PseudoVMADC_VV_M1, VMADC_VV, 0x0, 0x0 }, // 5387 |
11379 | | { PseudoVMADC_VV_M2, VMADC_VV, 0x1, 0x0 }, // 5388 |
11380 | | { PseudoVMADC_VV_M4, VMADC_VV, 0x2, 0x0 }, // 5389 |
11381 | | { PseudoVMADC_VV_M8, VMADC_VV, 0x3, 0x0 }, // 5390 |
11382 | | { PseudoVMADC_VV_MF8, VMADC_VV, 0x5, 0x0 }, // 5391 |
11383 | | { PseudoVMADC_VV_MF4, VMADC_VV, 0x6, 0x0 }, // 5392 |
11384 | | { PseudoVMADC_VV_MF2, VMADC_VV, 0x7, 0x0 }, // 5393 |
11385 | | { PseudoVMADC_VVM_M1, VMADC_VVM, 0x0, 0x0 }, // 5394 |
11386 | | { PseudoVMADC_VVM_M2, VMADC_VVM, 0x1, 0x0 }, // 5395 |
11387 | | { PseudoVMADC_VVM_M4, VMADC_VVM, 0x2, 0x0 }, // 5396 |
11388 | | { PseudoVMADC_VVM_M8, VMADC_VVM, 0x3, 0x0 }, // 5397 |
11389 | | { PseudoVMADC_VVM_MF8, VMADC_VVM, 0x5, 0x0 }, // 5398 |
11390 | | { PseudoVMADC_VVM_MF4, VMADC_VVM, 0x6, 0x0 }, // 5399 |
11391 | | { PseudoVMADC_VVM_MF2, VMADC_VVM, 0x7, 0x0 }, // 5400 |
11392 | | { PseudoVMADC_VX_M1, VMADC_VX, 0x0, 0x0 }, // 5401 |
11393 | | { PseudoVMADC_VX_M2, VMADC_VX, 0x1, 0x0 }, // 5402 |
11394 | | { PseudoVMADC_VX_M4, VMADC_VX, 0x2, 0x0 }, // 5403 |
11395 | | { PseudoVMADC_VX_M8, VMADC_VX, 0x3, 0x0 }, // 5404 |
11396 | | { PseudoVMADC_VX_MF8, VMADC_VX, 0x5, 0x0 }, // 5405 |
11397 | | { PseudoVMADC_VX_MF4, VMADC_VX, 0x6, 0x0 }, // 5406 |
11398 | | { PseudoVMADC_VX_MF2, VMADC_VX, 0x7, 0x0 }, // 5407 |
11399 | | { PseudoVMADC_VXM_M1, VMADC_VXM, 0x0, 0x0 }, // 5408 |
11400 | | { PseudoVMADC_VXM_M2, VMADC_VXM, 0x1, 0x0 }, // 5409 |
11401 | | { PseudoVMADC_VXM_M4, VMADC_VXM, 0x2, 0x0 }, // 5410 |
11402 | | { PseudoVMADC_VXM_M8, VMADC_VXM, 0x3, 0x0 }, // 5411 |
11403 | | { PseudoVMADC_VXM_MF8, VMADC_VXM, 0x5, 0x0 }, // 5412 |
11404 | | { PseudoVMADC_VXM_MF4, VMADC_VXM, 0x6, 0x0 }, // 5413 |
11405 | | { PseudoVMADC_VXM_MF2, VMADC_VXM, 0x7, 0x0 }, // 5414 |
11406 | | { PseudoVMADD_VV_M1, VMADD_VV, 0x0, 0x0 }, // 5415 |
11407 | | { PseudoVMADD_VV_M1_MASK, VMADD_VV, 0x0, 0x0 }, // 5416 |
11408 | | { PseudoVMADD_VV_M2, VMADD_VV, 0x1, 0x0 }, // 5417 |
11409 | | { PseudoVMADD_VV_M2_MASK, VMADD_VV, 0x1, 0x0 }, // 5418 |
11410 | | { PseudoVMADD_VV_M4, VMADD_VV, 0x2, 0x0 }, // 5419 |
11411 | | { PseudoVMADD_VV_M4_MASK, VMADD_VV, 0x2, 0x0 }, // 5420 |
11412 | | { PseudoVMADD_VV_M8, VMADD_VV, 0x3, 0x0 }, // 5421 |
11413 | | { PseudoVMADD_VV_M8_MASK, VMADD_VV, 0x3, 0x0 }, // 5422 |
11414 | | { PseudoVMADD_VV_MF8, VMADD_VV, 0x5, 0x0 }, // 5423 |
11415 | | { PseudoVMADD_VV_MF8_MASK, VMADD_VV, 0x5, 0x0 }, // 5424 |
11416 | | { PseudoVMADD_VV_MF4, VMADD_VV, 0x6, 0x0 }, // 5425 |
11417 | | { PseudoVMADD_VV_MF4_MASK, VMADD_VV, 0x6, 0x0 }, // 5426 |
11418 | | { PseudoVMADD_VV_MF2, VMADD_VV, 0x7, 0x0 }, // 5427 |
11419 | | { PseudoVMADD_VV_MF2_MASK, VMADD_VV, 0x7, 0x0 }, // 5428 |
11420 | | { PseudoVMADD_VX_M1, VMADD_VX, 0x0, 0x0 }, // 5429 |
11421 | | { PseudoVMADD_VX_M1_MASK, VMADD_VX, 0x0, 0x0 }, // 5430 |
11422 | | { PseudoVMADD_VX_M2, VMADD_VX, 0x1, 0x0 }, // 5431 |
11423 | | { PseudoVMADD_VX_M2_MASK, VMADD_VX, 0x1, 0x0 }, // 5432 |
11424 | | { PseudoVMADD_VX_M4, VMADD_VX, 0x2, 0x0 }, // 5433 |
11425 | | { PseudoVMADD_VX_M4_MASK, VMADD_VX, 0x2, 0x0 }, // 5434 |
11426 | | { PseudoVMADD_VX_M8, VMADD_VX, 0x3, 0x0 }, // 5435 |
11427 | | { PseudoVMADD_VX_M8_MASK, VMADD_VX, 0x3, 0x0 }, // 5436 |
11428 | | { PseudoVMADD_VX_MF8, VMADD_VX, 0x5, 0x0 }, // 5437 |
11429 | | { PseudoVMADD_VX_MF8_MASK, VMADD_VX, 0x5, 0x0 }, // 5438 |
11430 | | { PseudoVMADD_VX_MF4, VMADD_VX, 0x6, 0x0 }, // 5439 |
11431 | | { PseudoVMADD_VX_MF4_MASK, VMADD_VX, 0x6, 0x0 }, // 5440 |
11432 | | { PseudoVMADD_VX_MF2, VMADD_VX, 0x7, 0x0 }, // 5441 |
11433 | | { PseudoVMADD_VX_MF2_MASK, VMADD_VX, 0x7, 0x0 }, // 5442 |
11434 | | { PseudoVMANDN_MM_M1, VMANDN_MM, 0x0, 0x0 }, // 5443 |
11435 | | { PseudoVMANDN_MM_M2, VMANDN_MM, 0x1, 0x0 }, // 5444 |
11436 | | { PseudoVMANDN_MM_M4, VMANDN_MM, 0x2, 0x0 }, // 5445 |
11437 | | { PseudoVMANDN_MM_M8, VMANDN_MM, 0x3, 0x0 }, // 5446 |
11438 | | { PseudoVMANDN_MM_MF8, VMANDN_MM, 0x5, 0x0 }, // 5447 |
11439 | | { PseudoVMANDN_MM_MF4, VMANDN_MM, 0x6, 0x0 }, // 5448 |
11440 | | { PseudoVMANDN_MM_MF2, VMANDN_MM, 0x7, 0x0 }, // 5449 |
11441 | | { PseudoVMAND_MM_M1, VMAND_MM, 0x0, 0x0 }, // 5450 |
11442 | | { PseudoVMAND_MM_M2, VMAND_MM, 0x1, 0x0 }, // 5451 |
11443 | | { PseudoVMAND_MM_M4, VMAND_MM, 0x2, 0x0 }, // 5452 |
11444 | | { PseudoVMAND_MM_M8, VMAND_MM, 0x3, 0x0 }, // 5453 |
11445 | | { PseudoVMAND_MM_MF8, VMAND_MM, 0x5, 0x0 }, // 5454 |
11446 | | { PseudoVMAND_MM_MF4, VMAND_MM, 0x6, 0x0 }, // 5455 |
11447 | | { PseudoVMAND_MM_MF2, VMAND_MM, 0x7, 0x0 }, // 5456 |
11448 | | { PseudoVMAXU_VV_M1, VMAXU_VV, 0x0, 0x0 }, // 5457 |
11449 | | { PseudoVMAXU_VV_M1_MASK, VMAXU_VV, 0x0, 0x0 }, // 5458 |
11450 | | { PseudoVMAXU_VV_M2, VMAXU_VV, 0x1, 0x0 }, // 5459 |
11451 | | { PseudoVMAXU_VV_M2_MASK, VMAXU_VV, 0x1, 0x0 }, // 5460 |
11452 | | { PseudoVMAXU_VV_M4, VMAXU_VV, 0x2, 0x0 }, // 5461 |
11453 | | { PseudoVMAXU_VV_M4_MASK, VMAXU_VV, 0x2, 0x0 }, // 5462 |
11454 | | { PseudoVMAXU_VV_M8, VMAXU_VV, 0x3, 0x0 }, // 5463 |
11455 | | { PseudoVMAXU_VV_M8_MASK, VMAXU_VV, 0x3, 0x0 }, // 5464 |
11456 | | { PseudoVMAXU_VV_MF8, VMAXU_VV, 0x5, 0x0 }, // 5465 |
11457 | | { PseudoVMAXU_VV_MF8_MASK, VMAXU_VV, 0x5, 0x0 }, // 5466 |
11458 | | { PseudoVMAXU_VV_MF4, VMAXU_VV, 0x6, 0x0 }, // 5467 |
11459 | | { PseudoVMAXU_VV_MF4_MASK, VMAXU_VV, 0x6, 0x0 }, // 5468 |
11460 | | { PseudoVMAXU_VV_MF2, VMAXU_VV, 0x7, 0x0 }, // 5469 |
11461 | | { PseudoVMAXU_VV_MF2_MASK, VMAXU_VV, 0x7, 0x0 }, // 5470 |
11462 | | { PseudoVMAXU_VX_M1, VMAXU_VX, 0x0, 0x0 }, // 5471 |
11463 | | { PseudoVMAXU_VX_M1_MASK, VMAXU_VX, 0x0, 0x0 }, // 5472 |
11464 | | { PseudoVMAXU_VX_M2, VMAXU_VX, 0x1, 0x0 }, // 5473 |
11465 | | { PseudoVMAXU_VX_M2_MASK, VMAXU_VX, 0x1, 0x0 }, // 5474 |
11466 | | { PseudoVMAXU_VX_M4, VMAXU_VX, 0x2, 0x0 }, // 5475 |
11467 | | { PseudoVMAXU_VX_M4_MASK, VMAXU_VX, 0x2, 0x0 }, // 5476 |
11468 | | { PseudoVMAXU_VX_M8, VMAXU_VX, 0x3, 0x0 }, // 5477 |
11469 | | { PseudoVMAXU_VX_M8_MASK, VMAXU_VX, 0x3, 0x0 }, // 5478 |
11470 | | { PseudoVMAXU_VX_MF8, VMAXU_VX, 0x5, 0x0 }, // 5479 |
11471 | | { PseudoVMAXU_VX_MF8_MASK, VMAXU_VX, 0x5, 0x0 }, // 5480 |
11472 | | { PseudoVMAXU_VX_MF4, VMAXU_VX, 0x6, 0x0 }, // 5481 |
11473 | | { PseudoVMAXU_VX_MF4_MASK, VMAXU_VX, 0x6, 0x0 }, // 5482 |
11474 | | { PseudoVMAXU_VX_MF2, VMAXU_VX, 0x7, 0x0 }, // 5483 |
11475 | | { PseudoVMAXU_VX_MF2_MASK, VMAXU_VX, 0x7, 0x0 }, // 5484 |
11476 | | { PseudoVMAX_VV_M1, VMAX_VV, 0x0, 0x0 }, // 5485 |
11477 | | { PseudoVMAX_VV_M1_MASK, VMAX_VV, 0x0, 0x0 }, // 5486 |
11478 | | { PseudoVMAX_VV_M2, VMAX_VV, 0x1, 0x0 }, // 5487 |
11479 | | { PseudoVMAX_VV_M2_MASK, VMAX_VV, 0x1, 0x0 }, // 5488 |
11480 | | { PseudoVMAX_VV_M4, VMAX_VV, 0x2, 0x0 }, // 5489 |
11481 | | { PseudoVMAX_VV_M4_MASK, VMAX_VV, 0x2, 0x0 }, // 5490 |
11482 | | { PseudoVMAX_VV_M8, VMAX_VV, 0x3, 0x0 }, // 5491 |
11483 | | { PseudoVMAX_VV_M8_MASK, VMAX_VV, 0x3, 0x0 }, // 5492 |
11484 | | { PseudoVMAX_VV_MF8, VMAX_VV, 0x5, 0x0 }, // 5493 |
11485 | | { PseudoVMAX_VV_MF8_MASK, VMAX_VV, 0x5, 0x0 }, // 5494 |
11486 | | { PseudoVMAX_VV_MF4, VMAX_VV, 0x6, 0x0 }, // 5495 |
11487 | | { PseudoVMAX_VV_MF4_MASK, VMAX_VV, 0x6, 0x0 }, // 5496 |
11488 | | { PseudoVMAX_VV_MF2, VMAX_VV, 0x7, 0x0 }, // 5497 |
11489 | | { PseudoVMAX_VV_MF2_MASK, VMAX_VV, 0x7, 0x0 }, // 5498 |
11490 | | { PseudoVMAX_VX_M1, VMAX_VX, 0x0, 0x0 }, // 5499 |
11491 | | { PseudoVMAX_VX_M1_MASK, VMAX_VX, 0x0, 0x0 }, // 5500 |
11492 | | { PseudoVMAX_VX_M2, VMAX_VX, 0x1, 0x0 }, // 5501 |
11493 | | { PseudoVMAX_VX_M2_MASK, VMAX_VX, 0x1, 0x0 }, // 5502 |
11494 | | { PseudoVMAX_VX_M4, VMAX_VX, 0x2, 0x0 }, // 5503 |
11495 | | { PseudoVMAX_VX_M4_MASK, VMAX_VX, 0x2, 0x0 }, // 5504 |
11496 | | { PseudoVMAX_VX_M8, VMAX_VX, 0x3, 0x0 }, // 5505 |
11497 | | { PseudoVMAX_VX_M8_MASK, VMAX_VX, 0x3, 0x0 }, // 5506 |
11498 | | { PseudoVMAX_VX_MF8, VMAX_VX, 0x5, 0x0 }, // 5507 |
11499 | | { PseudoVMAX_VX_MF8_MASK, VMAX_VX, 0x5, 0x0 }, // 5508 |
11500 | | { PseudoVMAX_VX_MF4, VMAX_VX, 0x6, 0x0 }, // 5509 |
11501 | | { PseudoVMAX_VX_MF4_MASK, VMAX_VX, 0x6, 0x0 }, // 5510 |
11502 | | { PseudoVMAX_VX_MF2, VMAX_VX, 0x7, 0x0 }, // 5511 |
11503 | | { PseudoVMAX_VX_MF2_MASK, VMAX_VX, 0x7, 0x0 }, // 5512 |
11504 | | { PseudoVMERGE_VIM_M1, VMERGE_VIM, 0x0, 0x0 }, // 5513 |
11505 | | { PseudoVMERGE_VIM_M2, VMERGE_VIM, 0x1, 0x0 }, // 5514 |
11506 | | { PseudoVMERGE_VIM_M4, VMERGE_VIM, 0x2, 0x0 }, // 5515 |
11507 | | { PseudoVMERGE_VIM_M8, VMERGE_VIM, 0x3, 0x0 }, // 5516 |
11508 | | { PseudoVMERGE_VIM_MF8, VMERGE_VIM, 0x5, 0x0 }, // 5517 |
11509 | | { PseudoVMERGE_VIM_MF4, VMERGE_VIM, 0x6, 0x0 }, // 5518 |
11510 | | { PseudoVMERGE_VIM_MF2, VMERGE_VIM, 0x7, 0x0 }, // 5519 |
11511 | | { PseudoVMERGE_VVM_M1, VMERGE_VVM, 0x0, 0x0 }, // 5520 |
11512 | | { PseudoVMERGE_VVM_M2, VMERGE_VVM, 0x1, 0x0 }, // 5521 |
11513 | | { PseudoVMERGE_VVM_M4, VMERGE_VVM, 0x2, 0x0 }, // 5522 |
11514 | | { PseudoVMERGE_VVM_M8, VMERGE_VVM, 0x3, 0x0 }, // 5523 |
11515 | | { PseudoVMERGE_VVM_MF8, VMERGE_VVM, 0x5, 0x0 }, // 5524 |
11516 | | { PseudoVMERGE_VVM_MF4, VMERGE_VVM, 0x6, 0x0 }, // 5525 |
11517 | | { PseudoVMERGE_VVM_MF2, VMERGE_VVM, 0x7, 0x0 }, // 5526 |
11518 | | { PseudoVMERGE_VXM_M1, VMERGE_VXM, 0x0, 0x0 }, // 5527 |
11519 | | { PseudoVMERGE_VXM_M2, VMERGE_VXM, 0x1, 0x0 }, // 5528 |
11520 | | { PseudoVMERGE_VXM_M4, VMERGE_VXM, 0x2, 0x0 }, // 5529 |
11521 | | { PseudoVMERGE_VXM_M8, VMERGE_VXM, 0x3, 0x0 }, // 5530 |
11522 | | { PseudoVMERGE_VXM_MF8, VMERGE_VXM, 0x5, 0x0 }, // 5531 |
11523 | | { PseudoVMERGE_VXM_MF4, VMERGE_VXM, 0x6, 0x0 }, // 5532 |
11524 | | { PseudoVMERGE_VXM_MF2, VMERGE_VXM, 0x7, 0x0 }, // 5533 |
11525 | | { PseudoVMFEQ_VFPR16_M1, VMFEQ_VF, 0x0, 0x0 }, // 5534 |
11526 | | { PseudoVMFEQ_VFPR16_M1_MASK, VMFEQ_VF, 0x0, 0x0 }, // 5535 |
11527 | | { PseudoVMFEQ_VFPR32_M1, VMFEQ_VF, 0x0, 0x0 }, // 5536 |
11528 | | { PseudoVMFEQ_VFPR32_M1_MASK, VMFEQ_VF, 0x0, 0x0 }, // 5537 |
11529 | | { PseudoVMFEQ_VFPR64_M1, VMFEQ_VF, 0x0, 0x0 }, // 5538 |
11530 | | { PseudoVMFEQ_VFPR64_M1_MASK, VMFEQ_VF, 0x0, 0x0 }, // 5539 |
11531 | | { PseudoVMFEQ_VFPR16_M2, VMFEQ_VF, 0x1, 0x0 }, // 5540 |
11532 | | { PseudoVMFEQ_VFPR16_M2_MASK, VMFEQ_VF, 0x1, 0x0 }, // 5541 |
11533 | | { PseudoVMFEQ_VFPR32_M2, VMFEQ_VF, 0x1, 0x0 }, // 5542 |
11534 | | { PseudoVMFEQ_VFPR32_M2_MASK, VMFEQ_VF, 0x1, 0x0 }, // 5543 |
11535 | | { PseudoVMFEQ_VFPR64_M2, VMFEQ_VF, 0x1, 0x0 }, // 5544 |
11536 | | { PseudoVMFEQ_VFPR64_M2_MASK, VMFEQ_VF, 0x1, 0x0 }, // 5545 |
11537 | | { PseudoVMFEQ_VFPR16_M4, VMFEQ_VF, 0x2, 0x0 }, // 5546 |
11538 | | { PseudoVMFEQ_VFPR16_M4_MASK, VMFEQ_VF, 0x2, 0x0 }, // 5547 |
11539 | | { PseudoVMFEQ_VFPR32_M4, VMFEQ_VF, 0x2, 0x0 }, // 5548 |
11540 | | { PseudoVMFEQ_VFPR32_M4_MASK, VMFEQ_VF, 0x2, 0x0 }, // 5549 |
11541 | | { PseudoVMFEQ_VFPR64_M4, VMFEQ_VF, 0x2, 0x0 }, // 5550 |
11542 | | { PseudoVMFEQ_VFPR64_M4_MASK, VMFEQ_VF, 0x2, 0x0 }, // 5551 |
11543 | | { PseudoVMFEQ_VFPR16_M8, VMFEQ_VF, 0x3, 0x0 }, // 5552 |
11544 | | { PseudoVMFEQ_VFPR16_M8_MASK, VMFEQ_VF, 0x3, 0x0 }, // 5553 |
11545 | | { PseudoVMFEQ_VFPR32_M8, VMFEQ_VF, 0x3, 0x0 }, // 5554 |
11546 | | { PseudoVMFEQ_VFPR32_M8_MASK, VMFEQ_VF, 0x3, 0x0 }, // 5555 |
11547 | | { PseudoVMFEQ_VFPR64_M8, VMFEQ_VF, 0x3, 0x0 }, // 5556 |
11548 | | { PseudoVMFEQ_VFPR64_M8_MASK, VMFEQ_VF, 0x3, 0x0 }, // 5557 |
11549 | | { PseudoVMFEQ_VFPR16_MF4, VMFEQ_VF, 0x6, 0x0 }, // 5558 |
11550 | | { PseudoVMFEQ_VFPR16_MF4_MASK, VMFEQ_VF, 0x6, 0x0 }, // 5559 |
11551 | | { PseudoVMFEQ_VFPR16_MF2, VMFEQ_VF, 0x7, 0x0 }, // 5560 |
11552 | | { PseudoVMFEQ_VFPR16_MF2_MASK, VMFEQ_VF, 0x7, 0x0 }, // 5561 |
11553 | | { PseudoVMFEQ_VFPR32_MF2, VMFEQ_VF, 0x7, 0x0 }, // 5562 |
11554 | | { PseudoVMFEQ_VFPR32_MF2_MASK, VMFEQ_VF, 0x7, 0x0 }, // 5563 |
11555 | | { PseudoVMFEQ_VV_M1, VMFEQ_VV, 0x0, 0x0 }, // 5564 |
11556 | | { PseudoVMFEQ_VV_M1_MASK, VMFEQ_VV, 0x0, 0x0 }, // 5565 |
11557 | | { PseudoVMFEQ_VV_M2, VMFEQ_VV, 0x1, 0x0 }, // 5566 |
11558 | | { PseudoVMFEQ_VV_M2_MASK, VMFEQ_VV, 0x1, 0x0 }, // 5567 |
11559 | | { PseudoVMFEQ_VV_M4, VMFEQ_VV, 0x2, 0x0 }, // 5568 |
11560 | | { PseudoVMFEQ_VV_M4_MASK, VMFEQ_VV, 0x2, 0x0 }, // 5569 |
11561 | | { PseudoVMFEQ_VV_M8, VMFEQ_VV, 0x3, 0x0 }, // 5570 |
11562 | | { PseudoVMFEQ_VV_M8_MASK, VMFEQ_VV, 0x3, 0x0 }, // 5571 |
11563 | | { PseudoVMFEQ_VV_MF4, VMFEQ_VV, 0x6, 0x0 }, // 5572 |
11564 | | { PseudoVMFEQ_VV_MF4_MASK, VMFEQ_VV, 0x6, 0x0 }, // 5573 |
11565 | | { PseudoVMFEQ_VV_MF2, VMFEQ_VV, 0x7, 0x0 }, // 5574 |
11566 | | { PseudoVMFEQ_VV_MF2_MASK, VMFEQ_VV, 0x7, 0x0 }, // 5575 |
11567 | | { PseudoVMFGE_VFPR16_M1, VMFGE_VF, 0x0, 0x0 }, // 5576 |
11568 | | { PseudoVMFGE_VFPR16_M1_MASK, VMFGE_VF, 0x0, 0x0 }, // 5577 |
11569 | | { PseudoVMFGE_VFPR32_M1, VMFGE_VF, 0x0, 0x0 }, // 5578 |
11570 | | { PseudoVMFGE_VFPR32_M1_MASK, VMFGE_VF, 0x0, 0x0 }, // 5579 |
11571 | | { PseudoVMFGE_VFPR64_M1, VMFGE_VF, 0x0, 0x0 }, // 5580 |
11572 | | { PseudoVMFGE_VFPR64_M1_MASK, VMFGE_VF, 0x0, 0x0 }, // 5581 |
11573 | | { PseudoVMFGE_VFPR16_M2, VMFGE_VF, 0x1, 0x0 }, // 5582 |
11574 | | { PseudoVMFGE_VFPR16_M2_MASK, VMFGE_VF, 0x1, 0x0 }, // 5583 |
11575 | | { PseudoVMFGE_VFPR32_M2, VMFGE_VF, 0x1, 0x0 }, // 5584 |
11576 | | { PseudoVMFGE_VFPR32_M2_MASK, VMFGE_VF, 0x1, 0x0 }, // 5585 |
11577 | | { PseudoVMFGE_VFPR64_M2, VMFGE_VF, 0x1, 0x0 }, // 5586 |
11578 | | { PseudoVMFGE_VFPR64_M2_MASK, VMFGE_VF, 0x1, 0x0 }, // 5587 |
11579 | | { PseudoVMFGE_VFPR16_M4, VMFGE_VF, 0x2, 0x0 }, // 5588 |
11580 | | { PseudoVMFGE_VFPR16_M4_MASK, VMFGE_VF, 0x2, 0x0 }, // 5589 |
11581 | | { PseudoVMFGE_VFPR32_M4, VMFGE_VF, 0x2, 0x0 }, // 5590 |
11582 | | { PseudoVMFGE_VFPR32_M4_MASK, VMFGE_VF, 0x2, 0x0 }, // 5591 |
11583 | | { PseudoVMFGE_VFPR64_M4, VMFGE_VF, 0x2, 0x0 }, // 5592 |
11584 | | { PseudoVMFGE_VFPR64_M4_MASK, VMFGE_VF, 0x2, 0x0 }, // 5593 |
11585 | | { PseudoVMFGE_VFPR16_M8, VMFGE_VF, 0x3, 0x0 }, // 5594 |
11586 | | { PseudoVMFGE_VFPR16_M8_MASK, VMFGE_VF, 0x3, 0x0 }, // 5595 |
11587 | | { PseudoVMFGE_VFPR32_M8, VMFGE_VF, 0x3, 0x0 }, // 5596 |
11588 | | { PseudoVMFGE_VFPR32_M8_MASK, VMFGE_VF, 0x3, 0x0 }, // 5597 |
11589 | | { PseudoVMFGE_VFPR64_M8, VMFGE_VF, 0x3, 0x0 }, // 5598 |
11590 | | { PseudoVMFGE_VFPR64_M8_MASK, VMFGE_VF, 0x3, 0x0 }, // 5599 |
11591 | | { PseudoVMFGE_VFPR16_MF4, VMFGE_VF, 0x6, 0x0 }, // 5600 |
11592 | | { PseudoVMFGE_VFPR16_MF4_MASK, VMFGE_VF, 0x6, 0x0 }, // 5601 |
11593 | | { PseudoVMFGE_VFPR16_MF2, VMFGE_VF, 0x7, 0x0 }, // 5602 |
11594 | | { PseudoVMFGE_VFPR16_MF2_MASK, VMFGE_VF, 0x7, 0x0 }, // 5603 |
11595 | | { PseudoVMFGE_VFPR32_MF2, VMFGE_VF, 0x7, 0x0 }, // 5604 |
11596 | | { PseudoVMFGE_VFPR32_MF2_MASK, VMFGE_VF, 0x7, 0x0 }, // 5605 |
11597 | | { PseudoVMFGT_VFPR16_M1, VMFGT_VF, 0x0, 0x0 }, // 5606 |
11598 | | { PseudoVMFGT_VFPR16_M1_MASK, VMFGT_VF, 0x0, 0x0 }, // 5607 |
11599 | | { PseudoVMFGT_VFPR32_M1, VMFGT_VF, 0x0, 0x0 }, // 5608 |
11600 | | { PseudoVMFGT_VFPR32_M1_MASK, VMFGT_VF, 0x0, 0x0 }, // 5609 |
11601 | | { PseudoVMFGT_VFPR64_M1, VMFGT_VF, 0x0, 0x0 }, // 5610 |
11602 | | { PseudoVMFGT_VFPR64_M1_MASK, VMFGT_VF, 0x0, 0x0 }, // 5611 |
11603 | | { PseudoVMFGT_VFPR16_M2, VMFGT_VF, 0x1, 0x0 }, // 5612 |
11604 | | { PseudoVMFGT_VFPR16_M2_MASK, VMFGT_VF, 0x1, 0x0 }, // 5613 |
11605 | | { PseudoVMFGT_VFPR32_M2, VMFGT_VF, 0x1, 0x0 }, // 5614 |
11606 | | { PseudoVMFGT_VFPR32_M2_MASK, VMFGT_VF, 0x1, 0x0 }, // 5615 |
11607 | | { PseudoVMFGT_VFPR64_M2, VMFGT_VF, 0x1, 0x0 }, // 5616 |
11608 | | { PseudoVMFGT_VFPR64_M2_MASK, VMFGT_VF, 0x1, 0x0 }, // 5617 |
11609 | | { PseudoVMFGT_VFPR16_M4, VMFGT_VF, 0x2, 0x0 }, // 5618 |
11610 | | { PseudoVMFGT_VFPR16_M4_MASK, VMFGT_VF, 0x2, 0x0 }, // 5619 |
11611 | | { PseudoVMFGT_VFPR32_M4, VMFGT_VF, 0x2, 0x0 }, // 5620 |
11612 | | { PseudoVMFGT_VFPR32_M4_MASK, VMFGT_VF, 0x2, 0x0 }, // 5621 |
11613 | | { PseudoVMFGT_VFPR64_M4, VMFGT_VF, 0x2, 0x0 }, // 5622 |
11614 | | { PseudoVMFGT_VFPR64_M4_MASK, VMFGT_VF, 0x2, 0x0 }, // 5623 |
11615 | | { PseudoVMFGT_VFPR16_M8, VMFGT_VF, 0x3, 0x0 }, // 5624 |
11616 | | { PseudoVMFGT_VFPR16_M8_MASK, VMFGT_VF, 0x3, 0x0 }, // 5625 |
11617 | | { PseudoVMFGT_VFPR32_M8, VMFGT_VF, 0x3, 0x0 }, // 5626 |
11618 | | { PseudoVMFGT_VFPR32_M8_MASK, VMFGT_VF, 0x3, 0x0 }, // 5627 |
11619 | | { PseudoVMFGT_VFPR64_M8, VMFGT_VF, 0x3, 0x0 }, // 5628 |
11620 | | { PseudoVMFGT_VFPR64_M8_MASK, VMFGT_VF, 0x3, 0x0 }, // 5629 |
11621 | | { PseudoVMFGT_VFPR16_MF4, VMFGT_VF, 0x6, 0x0 }, // 5630 |
11622 | | { PseudoVMFGT_VFPR16_MF4_MASK, VMFGT_VF, 0x6, 0x0 }, // 5631 |
11623 | | { PseudoVMFGT_VFPR16_MF2, VMFGT_VF, 0x7, 0x0 }, // 5632 |
11624 | | { PseudoVMFGT_VFPR16_MF2_MASK, VMFGT_VF, 0x7, 0x0 }, // 5633 |
11625 | | { PseudoVMFGT_VFPR32_MF2, VMFGT_VF, 0x7, 0x0 }, // 5634 |
11626 | | { PseudoVMFGT_VFPR32_MF2_MASK, VMFGT_VF, 0x7, 0x0 }, // 5635 |
11627 | | { PseudoVMFLE_VFPR16_M1, VMFLE_VF, 0x0, 0x0 }, // 5636 |
11628 | | { PseudoVMFLE_VFPR16_M1_MASK, VMFLE_VF, 0x0, 0x0 }, // 5637 |
11629 | | { PseudoVMFLE_VFPR32_M1, VMFLE_VF, 0x0, 0x0 }, // 5638 |
11630 | | { PseudoVMFLE_VFPR32_M1_MASK, VMFLE_VF, 0x0, 0x0 }, // 5639 |
11631 | | { PseudoVMFLE_VFPR64_M1, VMFLE_VF, 0x0, 0x0 }, // 5640 |
11632 | | { PseudoVMFLE_VFPR64_M1_MASK, VMFLE_VF, 0x0, 0x0 }, // 5641 |
11633 | | { PseudoVMFLE_VFPR16_M2, VMFLE_VF, 0x1, 0x0 }, // 5642 |
11634 | | { PseudoVMFLE_VFPR16_M2_MASK, VMFLE_VF, 0x1, 0x0 }, // 5643 |
11635 | | { PseudoVMFLE_VFPR32_M2, VMFLE_VF, 0x1, 0x0 }, // 5644 |
11636 | | { PseudoVMFLE_VFPR32_M2_MASK, VMFLE_VF, 0x1, 0x0 }, // 5645 |
11637 | | { PseudoVMFLE_VFPR64_M2, VMFLE_VF, 0x1, 0x0 }, // 5646 |
11638 | | { PseudoVMFLE_VFPR64_M2_MASK, VMFLE_VF, 0x1, 0x0 }, // 5647 |
11639 | | { PseudoVMFLE_VFPR16_M4, VMFLE_VF, 0x2, 0x0 }, // 5648 |
11640 | | { PseudoVMFLE_VFPR16_M4_MASK, VMFLE_VF, 0x2, 0x0 }, // 5649 |
11641 | | { PseudoVMFLE_VFPR32_M4, VMFLE_VF, 0x2, 0x0 }, // 5650 |
11642 | | { PseudoVMFLE_VFPR32_M4_MASK, VMFLE_VF, 0x2, 0x0 }, // 5651 |
11643 | | { PseudoVMFLE_VFPR64_M4, VMFLE_VF, 0x2, 0x0 }, // 5652 |
11644 | | { PseudoVMFLE_VFPR64_M4_MASK, VMFLE_VF, 0x2, 0x0 }, // 5653 |
11645 | | { PseudoVMFLE_VFPR16_M8, VMFLE_VF, 0x3, 0x0 }, // 5654 |
11646 | | { PseudoVMFLE_VFPR16_M8_MASK, VMFLE_VF, 0x3, 0x0 }, // 5655 |
11647 | | { PseudoVMFLE_VFPR32_M8, VMFLE_VF, 0x3, 0x0 }, // 5656 |
11648 | | { PseudoVMFLE_VFPR32_M8_MASK, VMFLE_VF, 0x3, 0x0 }, // 5657 |
11649 | | { PseudoVMFLE_VFPR64_M8, VMFLE_VF, 0x3, 0x0 }, // 5658 |
11650 | | { PseudoVMFLE_VFPR64_M8_MASK, VMFLE_VF, 0x3, 0x0 }, // 5659 |
11651 | | { PseudoVMFLE_VFPR16_MF4, VMFLE_VF, 0x6, 0x0 }, // 5660 |
11652 | | { PseudoVMFLE_VFPR16_MF4_MASK, VMFLE_VF, 0x6, 0x0 }, // 5661 |
11653 | | { PseudoVMFLE_VFPR16_MF2, VMFLE_VF, 0x7, 0x0 }, // 5662 |
11654 | | { PseudoVMFLE_VFPR16_MF2_MASK, VMFLE_VF, 0x7, 0x0 }, // 5663 |
11655 | | { PseudoVMFLE_VFPR32_MF2, VMFLE_VF, 0x7, 0x0 }, // 5664 |
11656 | | { PseudoVMFLE_VFPR32_MF2_MASK, VMFLE_VF, 0x7, 0x0 }, // 5665 |
11657 | | { PseudoVMFLE_VV_M1, VMFLE_VV, 0x0, 0x0 }, // 5666 |
11658 | | { PseudoVMFLE_VV_M1_MASK, VMFLE_VV, 0x0, 0x0 }, // 5667 |
11659 | | { PseudoVMFLE_VV_M2, VMFLE_VV, 0x1, 0x0 }, // 5668 |
11660 | | { PseudoVMFLE_VV_M2_MASK, VMFLE_VV, 0x1, 0x0 }, // 5669 |
11661 | | { PseudoVMFLE_VV_M4, VMFLE_VV, 0x2, 0x0 }, // 5670 |
11662 | | { PseudoVMFLE_VV_M4_MASK, VMFLE_VV, 0x2, 0x0 }, // 5671 |
11663 | | { PseudoVMFLE_VV_M8, VMFLE_VV, 0x3, 0x0 }, // 5672 |
11664 | | { PseudoVMFLE_VV_M8_MASK, VMFLE_VV, 0x3, 0x0 }, // 5673 |
11665 | | { PseudoVMFLE_VV_MF4, VMFLE_VV, 0x6, 0x0 }, // 5674 |
11666 | | { PseudoVMFLE_VV_MF4_MASK, VMFLE_VV, 0x6, 0x0 }, // 5675 |
11667 | | { PseudoVMFLE_VV_MF2, VMFLE_VV, 0x7, 0x0 }, // 5676 |
11668 | | { PseudoVMFLE_VV_MF2_MASK, VMFLE_VV, 0x7, 0x0 }, // 5677 |
11669 | | { PseudoVMFLT_VFPR16_M1, VMFLT_VF, 0x0, 0x0 }, // 5678 |
11670 | | { PseudoVMFLT_VFPR16_M1_MASK, VMFLT_VF, 0x0, 0x0 }, // 5679 |
11671 | | { PseudoVMFLT_VFPR32_M1, VMFLT_VF, 0x0, 0x0 }, // 5680 |
11672 | | { PseudoVMFLT_VFPR32_M1_MASK, VMFLT_VF, 0x0, 0x0 }, // 5681 |
11673 | | { PseudoVMFLT_VFPR64_M1, VMFLT_VF, 0x0, 0x0 }, // 5682 |
11674 | | { PseudoVMFLT_VFPR64_M1_MASK, VMFLT_VF, 0x0, 0x0 }, // 5683 |
11675 | | { PseudoVMFLT_VFPR16_M2, VMFLT_VF, 0x1, 0x0 }, // 5684 |
11676 | | { PseudoVMFLT_VFPR16_M2_MASK, VMFLT_VF, 0x1, 0x0 }, // 5685 |
11677 | | { PseudoVMFLT_VFPR32_M2, VMFLT_VF, 0x1, 0x0 }, // 5686 |
11678 | | { PseudoVMFLT_VFPR32_M2_MASK, VMFLT_VF, 0x1, 0x0 }, // 5687 |
11679 | | { PseudoVMFLT_VFPR64_M2, VMFLT_VF, 0x1, 0x0 }, // 5688 |
11680 | | { PseudoVMFLT_VFPR64_M2_MASK, VMFLT_VF, 0x1, 0x0 }, // 5689 |
11681 | | { PseudoVMFLT_VFPR16_M4, VMFLT_VF, 0x2, 0x0 }, // 5690 |
11682 | | { PseudoVMFLT_VFPR16_M4_MASK, VMFLT_VF, 0x2, 0x0 }, // 5691 |
11683 | | { PseudoVMFLT_VFPR32_M4, VMFLT_VF, 0x2, 0x0 }, // 5692 |
11684 | | { PseudoVMFLT_VFPR32_M4_MASK, VMFLT_VF, 0x2, 0x0 }, // 5693 |
11685 | | { PseudoVMFLT_VFPR64_M4, VMFLT_VF, 0x2, 0x0 }, // 5694 |
11686 | | { PseudoVMFLT_VFPR64_M4_MASK, VMFLT_VF, 0x2, 0x0 }, // 5695 |
11687 | | { PseudoVMFLT_VFPR16_M8, VMFLT_VF, 0x3, 0x0 }, // 5696 |
11688 | | { PseudoVMFLT_VFPR16_M8_MASK, VMFLT_VF, 0x3, 0x0 }, // 5697 |
11689 | | { PseudoVMFLT_VFPR32_M8, VMFLT_VF, 0x3, 0x0 }, // 5698 |
11690 | | { PseudoVMFLT_VFPR32_M8_MASK, VMFLT_VF, 0x3, 0x0 }, // 5699 |
11691 | | { PseudoVMFLT_VFPR64_M8, VMFLT_VF, 0x3, 0x0 }, // 5700 |
11692 | | { PseudoVMFLT_VFPR64_M8_MASK, VMFLT_VF, 0x3, 0x0 }, // 5701 |
11693 | | { PseudoVMFLT_VFPR16_MF4, VMFLT_VF, 0x6, 0x0 }, // 5702 |
11694 | | { PseudoVMFLT_VFPR16_MF4_MASK, VMFLT_VF, 0x6, 0x0 }, // 5703 |
11695 | | { PseudoVMFLT_VFPR16_MF2, VMFLT_VF, 0x7, 0x0 }, // 5704 |
11696 | | { PseudoVMFLT_VFPR16_MF2_MASK, VMFLT_VF, 0x7, 0x0 }, // 5705 |
11697 | | { PseudoVMFLT_VFPR32_MF2, VMFLT_VF, 0x7, 0x0 }, // 5706 |
11698 | | { PseudoVMFLT_VFPR32_MF2_MASK, VMFLT_VF, 0x7, 0x0 }, // 5707 |
11699 | | { PseudoVMFLT_VV_M1, VMFLT_VV, 0x0, 0x0 }, // 5708 |
11700 | | { PseudoVMFLT_VV_M1_MASK, VMFLT_VV, 0x0, 0x0 }, // 5709 |
11701 | | { PseudoVMFLT_VV_M2, VMFLT_VV, 0x1, 0x0 }, // 5710 |
11702 | | { PseudoVMFLT_VV_M2_MASK, VMFLT_VV, 0x1, 0x0 }, // 5711 |
11703 | | { PseudoVMFLT_VV_M4, VMFLT_VV, 0x2, 0x0 }, // 5712 |
11704 | | { PseudoVMFLT_VV_M4_MASK, VMFLT_VV, 0x2, 0x0 }, // 5713 |
11705 | | { PseudoVMFLT_VV_M8, VMFLT_VV, 0x3, 0x0 }, // 5714 |
11706 | | { PseudoVMFLT_VV_M8_MASK, VMFLT_VV, 0x3, 0x0 }, // 5715 |
11707 | | { PseudoVMFLT_VV_MF4, VMFLT_VV, 0x6, 0x0 }, // 5716 |
11708 | | { PseudoVMFLT_VV_MF4_MASK, VMFLT_VV, 0x6, 0x0 }, // 5717 |
11709 | | { PseudoVMFLT_VV_MF2, VMFLT_VV, 0x7, 0x0 }, // 5718 |
11710 | | { PseudoVMFLT_VV_MF2_MASK, VMFLT_VV, 0x7, 0x0 }, // 5719 |
11711 | | { PseudoVMFNE_VFPR16_M1, VMFNE_VF, 0x0, 0x0 }, // 5720 |
11712 | | { PseudoVMFNE_VFPR16_M1_MASK, VMFNE_VF, 0x0, 0x0 }, // 5721 |
11713 | | { PseudoVMFNE_VFPR32_M1, VMFNE_VF, 0x0, 0x0 }, // 5722 |
11714 | | { PseudoVMFNE_VFPR32_M1_MASK, VMFNE_VF, 0x0, 0x0 }, // 5723 |
11715 | | { PseudoVMFNE_VFPR64_M1, VMFNE_VF, 0x0, 0x0 }, // 5724 |
11716 | | { PseudoVMFNE_VFPR64_M1_MASK, VMFNE_VF, 0x0, 0x0 }, // 5725 |
11717 | | { PseudoVMFNE_VFPR16_M2, VMFNE_VF, 0x1, 0x0 }, // 5726 |
11718 | | { PseudoVMFNE_VFPR16_M2_MASK, VMFNE_VF, 0x1, 0x0 }, // 5727 |
11719 | | { PseudoVMFNE_VFPR32_M2, VMFNE_VF, 0x1, 0x0 }, // 5728 |
11720 | | { PseudoVMFNE_VFPR32_M2_MASK, VMFNE_VF, 0x1, 0x0 }, // 5729 |
11721 | | { PseudoVMFNE_VFPR64_M2, VMFNE_VF, 0x1, 0x0 }, // 5730 |
11722 | | { PseudoVMFNE_VFPR64_M2_MASK, VMFNE_VF, 0x1, 0x0 }, // 5731 |
11723 | | { PseudoVMFNE_VFPR16_M4, VMFNE_VF, 0x2, 0x0 }, // 5732 |
11724 | | { PseudoVMFNE_VFPR16_M4_MASK, VMFNE_VF, 0x2, 0x0 }, // 5733 |
11725 | | { PseudoVMFNE_VFPR32_M4, VMFNE_VF, 0x2, 0x0 }, // 5734 |
11726 | | { PseudoVMFNE_VFPR32_M4_MASK, VMFNE_VF, 0x2, 0x0 }, // 5735 |
11727 | | { PseudoVMFNE_VFPR64_M4, VMFNE_VF, 0x2, 0x0 }, // 5736 |
11728 | | { PseudoVMFNE_VFPR64_M4_MASK, VMFNE_VF, 0x2, 0x0 }, // 5737 |
11729 | | { PseudoVMFNE_VFPR16_M8, VMFNE_VF, 0x3, 0x0 }, // 5738 |
11730 | | { PseudoVMFNE_VFPR16_M8_MASK, VMFNE_VF, 0x3, 0x0 }, // 5739 |
11731 | | { PseudoVMFNE_VFPR32_M8, VMFNE_VF, 0x3, 0x0 }, // 5740 |
11732 | | { PseudoVMFNE_VFPR32_M8_MASK, VMFNE_VF, 0x3, 0x0 }, // 5741 |
11733 | | { PseudoVMFNE_VFPR64_M8, VMFNE_VF, 0x3, 0x0 }, // 5742 |
11734 | | { PseudoVMFNE_VFPR64_M8_MASK, VMFNE_VF, 0x3, 0x0 }, // 5743 |
11735 | | { PseudoVMFNE_VFPR16_MF4, VMFNE_VF, 0x6, 0x0 }, // 5744 |
11736 | | { PseudoVMFNE_VFPR16_MF4_MASK, VMFNE_VF, 0x6, 0x0 }, // 5745 |
11737 | | { PseudoVMFNE_VFPR16_MF2, VMFNE_VF, 0x7, 0x0 }, // 5746 |
11738 | | { PseudoVMFNE_VFPR16_MF2_MASK, VMFNE_VF, 0x7, 0x0 }, // 5747 |
11739 | | { PseudoVMFNE_VFPR32_MF2, VMFNE_VF, 0x7, 0x0 }, // 5748 |
11740 | | { PseudoVMFNE_VFPR32_MF2_MASK, VMFNE_VF, 0x7, 0x0 }, // 5749 |
11741 | | { PseudoVMFNE_VV_M1, VMFNE_VV, 0x0, 0x0 }, // 5750 |
11742 | | { PseudoVMFNE_VV_M1_MASK, VMFNE_VV, 0x0, 0x0 }, // 5751 |
11743 | | { PseudoVMFNE_VV_M2, VMFNE_VV, 0x1, 0x0 }, // 5752 |
11744 | | { PseudoVMFNE_VV_M2_MASK, VMFNE_VV, 0x1, 0x0 }, // 5753 |
11745 | | { PseudoVMFNE_VV_M4, VMFNE_VV, 0x2, 0x0 }, // 5754 |
11746 | | { PseudoVMFNE_VV_M4_MASK, VMFNE_VV, 0x2, 0x0 }, // 5755 |
11747 | | { PseudoVMFNE_VV_M8, VMFNE_VV, 0x3, 0x0 }, // 5756 |
11748 | | { PseudoVMFNE_VV_M8_MASK, VMFNE_VV, 0x3, 0x0 }, // 5757 |
11749 | | { PseudoVMFNE_VV_MF4, VMFNE_VV, 0x6, 0x0 }, // 5758 |
11750 | | { PseudoVMFNE_VV_MF4_MASK, VMFNE_VV, 0x6, 0x0 }, // 5759 |
11751 | | { PseudoVMFNE_VV_MF2, VMFNE_VV, 0x7, 0x0 }, // 5760 |
11752 | | { PseudoVMFNE_VV_MF2_MASK, VMFNE_VV, 0x7, 0x0 }, // 5761 |
11753 | | { PseudoVMINU_VV_M1, VMINU_VV, 0x0, 0x0 }, // 5762 |
11754 | | { PseudoVMINU_VV_M1_MASK, VMINU_VV, 0x0, 0x0 }, // 5763 |
11755 | | { PseudoVMINU_VV_M2, VMINU_VV, 0x1, 0x0 }, // 5764 |
11756 | | { PseudoVMINU_VV_M2_MASK, VMINU_VV, 0x1, 0x0 }, // 5765 |
11757 | | { PseudoVMINU_VV_M4, VMINU_VV, 0x2, 0x0 }, // 5766 |
11758 | | { PseudoVMINU_VV_M4_MASK, VMINU_VV, 0x2, 0x0 }, // 5767 |
11759 | | { PseudoVMINU_VV_M8, VMINU_VV, 0x3, 0x0 }, // 5768 |
11760 | | { PseudoVMINU_VV_M8_MASK, VMINU_VV, 0x3, 0x0 }, // 5769 |
11761 | | { PseudoVMINU_VV_MF8, VMINU_VV, 0x5, 0x0 }, // 5770 |
11762 | | { PseudoVMINU_VV_MF8_MASK, VMINU_VV, 0x5, 0x0 }, // 5771 |
11763 | | { PseudoVMINU_VV_MF4, VMINU_VV, 0x6, 0x0 }, // 5772 |
11764 | | { PseudoVMINU_VV_MF4_MASK, VMINU_VV, 0x6, 0x0 }, // 5773 |
11765 | | { PseudoVMINU_VV_MF2, VMINU_VV, 0x7, 0x0 }, // 5774 |
11766 | | { PseudoVMINU_VV_MF2_MASK, VMINU_VV, 0x7, 0x0 }, // 5775 |
11767 | | { PseudoVMINU_VX_M1, VMINU_VX, 0x0, 0x0 }, // 5776 |
11768 | | { PseudoVMINU_VX_M1_MASK, VMINU_VX, 0x0, 0x0 }, // 5777 |
11769 | | { PseudoVMINU_VX_M2, VMINU_VX, 0x1, 0x0 }, // 5778 |
11770 | | { PseudoVMINU_VX_M2_MASK, VMINU_VX, 0x1, 0x0 }, // 5779 |
11771 | | { PseudoVMINU_VX_M4, VMINU_VX, 0x2, 0x0 }, // 5780 |
11772 | | { PseudoVMINU_VX_M4_MASK, VMINU_VX, 0x2, 0x0 }, // 5781 |
11773 | | { PseudoVMINU_VX_M8, VMINU_VX, 0x3, 0x0 }, // 5782 |
11774 | | { PseudoVMINU_VX_M8_MASK, VMINU_VX, 0x3, 0x0 }, // 5783 |
11775 | | { PseudoVMINU_VX_MF8, VMINU_VX, 0x5, 0x0 }, // 5784 |
11776 | | { PseudoVMINU_VX_MF8_MASK, VMINU_VX, 0x5, 0x0 }, // 5785 |
11777 | | { PseudoVMINU_VX_MF4, VMINU_VX, 0x6, 0x0 }, // 5786 |
11778 | | { PseudoVMINU_VX_MF4_MASK, VMINU_VX, 0x6, 0x0 }, // 5787 |
11779 | | { PseudoVMINU_VX_MF2, VMINU_VX, 0x7, 0x0 }, // 5788 |
11780 | | { PseudoVMINU_VX_MF2_MASK, VMINU_VX, 0x7, 0x0 }, // 5789 |
11781 | | { PseudoVMIN_VV_M1, VMIN_VV, 0x0, 0x0 }, // 5790 |
11782 | | { PseudoVMIN_VV_M1_MASK, VMIN_VV, 0x0, 0x0 }, // 5791 |
11783 | | { PseudoVMIN_VV_M2, VMIN_VV, 0x1, 0x0 }, // 5792 |
11784 | | { PseudoVMIN_VV_M2_MASK, VMIN_VV, 0x1, 0x0 }, // 5793 |
11785 | | { PseudoVMIN_VV_M4, VMIN_VV, 0x2, 0x0 }, // 5794 |
11786 | | { PseudoVMIN_VV_M4_MASK, VMIN_VV, 0x2, 0x0 }, // 5795 |
11787 | | { PseudoVMIN_VV_M8, VMIN_VV, 0x3, 0x0 }, // 5796 |
11788 | | { PseudoVMIN_VV_M8_MASK, VMIN_VV, 0x3, 0x0 }, // 5797 |
11789 | | { PseudoVMIN_VV_MF8, VMIN_VV, 0x5, 0x0 }, // 5798 |
11790 | | { PseudoVMIN_VV_MF8_MASK, VMIN_VV, 0x5, 0x0 }, // 5799 |
11791 | | { PseudoVMIN_VV_MF4, VMIN_VV, 0x6, 0x0 }, // 5800 |
11792 | | { PseudoVMIN_VV_MF4_MASK, VMIN_VV, 0x6, 0x0 }, // 5801 |
11793 | | { PseudoVMIN_VV_MF2, VMIN_VV, 0x7, 0x0 }, // 5802 |
11794 | | { PseudoVMIN_VV_MF2_MASK, VMIN_VV, 0x7, 0x0 }, // 5803 |
11795 | | { PseudoVMIN_VX_M1, VMIN_VX, 0x0, 0x0 }, // 5804 |
11796 | | { PseudoVMIN_VX_M1_MASK, VMIN_VX, 0x0, 0x0 }, // 5805 |
11797 | | { PseudoVMIN_VX_M2, VMIN_VX, 0x1, 0x0 }, // 5806 |
11798 | | { PseudoVMIN_VX_M2_MASK, VMIN_VX, 0x1, 0x0 }, // 5807 |
11799 | | { PseudoVMIN_VX_M4, VMIN_VX, 0x2, 0x0 }, // 5808 |
11800 | | { PseudoVMIN_VX_M4_MASK, VMIN_VX, 0x2, 0x0 }, // 5809 |
11801 | | { PseudoVMIN_VX_M8, VMIN_VX, 0x3, 0x0 }, // 5810 |
11802 | | { PseudoVMIN_VX_M8_MASK, VMIN_VX, 0x3, 0x0 }, // 5811 |
11803 | | { PseudoVMIN_VX_MF8, VMIN_VX, 0x5, 0x0 }, // 5812 |
11804 | | { PseudoVMIN_VX_MF8_MASK, VMIN_VX, 0x5, 0x0 }, // 5813 |
11805 | | { PseudoVMIN_VX_MF4, VMIN_VX, 0x6, 0x0 }, // 5814 |
11806 | | { PseudoVMIN_VX_MF4_MASK, VMIN_VX, 0x6, 0x0 }, // 5815 |
11807 | | { PseudoVMIN_VX_MF2, VMIN_VX, 0x7, 0x0 }, // 5816 |
11808 | | { PseudoVMIN_VX_MF2_MASK, VMIN_VX, 0x7, 0x0 }, // 5817 |
11809 | | { PseudoVMNAND_MM_M1, VMNAND_MM, 0x0, 0x0 }, // 5818 |
11810 | | { PseudoVMNAND_MM_M2, VMNAND_MM, 0x1, 0x0 }, // 5819 |
11811 | | { PseudoVMNAND_MM_M4, VMNAND_MM, 0x2, 0x0 }, // 5820 |
11812 | | { PseudoVMNAND_MM_M8, VMNAND_MM, 0x3, 0x0 }, // 5821 |
11813 | | { PseudoVMNAND_MM_MF8, VMNAND_MM, 0x5, 0x0 }, // 5822 |
11814 | | { PseudoVMNAND_MM_MF4, VMNAND_MM, 0x6, 0x0 }, // 5823 |
11815 | | { PseudoVMNAND_MM_MF2, VMNAND_MM, 0x7, 0x0 }, // 5824 |
11816 | | { PseudoVMNOR_MM_M1, VMNOR_MM, 0x0, 0x0 }, // 5825 |
11817 | | { PseudoVMNOR_MM_M2, VMNOR_MM, 0x1, 0x0 }, // 5826 |
11818 | | { PseudoVMNOR_MM_M4, VMNOR_MM, 0x2, 0x0 }, // 5827 |
11819 | | { PseudoVMNOR_MM_M8, VMNOR_MM, 0x3, 0x0 }, // 5828 |
11820 | | { PseudoVMNOR_MM_MF8, VMNOR_MM, 0x5, 0x0 }, // 5829 |
11821 | | { PseudoVMNOR_MM_MF4, VMNOR_MM, 0x6, 0x0 }, // 5830 |
11822 | | { PseudoVMNOR_MM_MF2, VMNOR_MM, 0x7, 0x0 }, // 5831 |
11823 | | { PseudoVMORN_MM_M1, VMORN_MM, 0x0, 0x0 }, // 5832 |
11824 | | { PseudoVMORN_MM_M2, VMORN_MM, 0x1, 0x0 }, // 5833 |
11825 | | { PseudoVMORN_MM_M4, VMORN_MM, 0x2, 0x0 }, // 5834 |
11826 | | { PseudoVMORN_MM_M8, VMORN_MM, 0x3, 0x0 }, // 5835 |
11827 | | { PseudoVMORN_MM_MF8, VMORN_MM, 0x5, 0x0 }, // 5836 |
11828 | | { PseudoVMORN_MM_MF4, VMORN_MM, 0x6, 0x0 }, // 5837 |
11829 | | { PseudoVMORN_MM_MF2, VMORN_MM, 0x7, 0x0 }, // 5838 |
11830 | | { PseudoVMOR_MM_M1, VMOR_MM, 0x0, 0x0 }, // 5839 |
11831 | | { PseudoVMOR_MM_M2, VMOR_MM, 0x1, 0x0 }, // 5840 |
11832 | | { PseudoVMOR_MM_M4, VMOR_MM, 0x2, 0x0 }, // 5841 |
11833 | | { PseudoVMOR_MM_M8, VMOR_MM, 0x3, 0x0 }, // 5842 |
11834 | | { PseudoVMOR_MM_MF8, VMOR_MM, 0x5, 0x0 }, // 5843 |
11835 | | { PseudoVMOR_MM_MF4, VMOR_MM, 0x6, 0x0 }, // 5844 |
11836 | | { PseudoVMOR_MM_MF2, VMOR_MM, 0x7, 0x0 }, // 5845 |
11837 | | { PseudoVMSBC_VV_M1, VMSBC_VV, 0x0, 0x0 }, // 5846 |
11838 | | { PseudoVMSBC_VV_M2, VMSBC_VV, 0x1, 0x0 }, // 5847 |
11839 | | { PseudoVMSBC_VV_M4, VMSBC_VV, 0x2, 0x0 }, // 5848 |
11840 | | { PseudoVMSBC_VV_M8, VMSBC_VV, 0x3, 0x0 }, // 5849 |
11841 | | { PseudoVMSBC_VV_MF8, VMSBC_VV, 0x5, 0x0 }, // 5850 |
11842 | | { PseudoVMSBC_VV_MF4, VMSBC_VV, 0x6, 0x0 }, // 5851 |
11843 | | { PseudoVMSBC_VV_MF2, VMSBC_VV, 0x7, 0x0 }, // 5852 |
11844 | | { PseudoVMSBC_VVM_M1, VMSBC_VVM, 0x0, 0x0 }, // 5853 |
11845 | | { PseudoVMSBC_VVM_M2, VMSBC_VVM, 0x1, 0x0 }, // 5854 |
11846 | | { PseudoVMSBC_VVM_M4, VMSBC_VVM, 0x2, 0x0 }, // 5855 |
11847 | | { PseudoVMSBC_VVM_M8, VMSBC_VVM, 0x3, 0x0 }, // 5856 |
11848 | | { PseudoVMSBC_VVM_MF8, VMSBC_VVM, 0x5, 0x0 }, // 5857 |
11849 | | { PseudoVMSBC_VVM_MF4, VMSBC_VVM, 0x6, 0x0 }, // 5858 |
11850 | | { PseudoVMSBC_VVM_MF2, VMSBC_VVM, 0x7, 0x0 }, // 5859 |
11851 | | { PseudoVMSBC_VX_M1, VMSBC_VX, 0x0, 0x0 }, // 5860 |
11852 | | { PseudoVMSBC_VX_M2, VMSBC_VX, 0x1, 0x0 }, // 5861 |
11853 | | { PseudoVMSBC_VX_M4, VMSBC_VX, 0x2, 0x0 }, // 5862 |
11854 | | { PseudoVMSBC_VX_M8, VMSBC_VX, 0x3, 0x0 }, // 5863 |
11855 | | { PseudoVMSBC_VX_MF8, VMSBC_VX, 0x5, 0x0 }, // 5864 |
11856 | | { PseudoVMSBC_VX_MF4, VMSBC_VX, 0x6, 0x0 }, // 5865 |
11857 | | { PseudoVMSBC_VX_MF2, VMSBC_VX, 0x7, 0x0 }, // 5866 |
11858 | | { PseudoVMSBC_VXM_M1, VMSBC_VXM, 0x0, 0x0 }, // 5867 |
11859 | | { PseudoVMSBC_VXM_M2, VMSBC_VXM, 0x1, 0x0 }, // 5868 |
11860 | | { PseudoVMSBC_VXM_M4, VMSBC_VXM, 0x2, 0x0 }, // 5869 |
11861 | | { PseudoVMSBC_VXM_M8, VMSBC_VXM, 0x3, 0x0 }, // 5870 |
11862 | | { PseudoVMSBC_VXM_MF8, VMSBC_VXM, 0x5, 0x0 }, // 5871 |
11863 | | { PseudoVMSBC_VXM_MF4, VMSBC_VXM, 0x6, 0x0 }, // 5872 |
11864 | | { PseudoVMSBC_VXM_MF2, VMSBC_VXM, 0x7, 0x0 }, // 5873 |
11865 | | { PseudoVMSBF_M_B8, VMSBF_M, 0x0, 0x0 }, // 5874 |
11866 | | { PseudoVMSBF_M_B8_MASK, VMSBF_M, 0x0, 0x0 }, // 5875 |
11867 | | { PseudoVMSBF_M_B16, VMSBF_M, 0x1, 0x0 }, // 5876 |
11868 | | { PseudoVMSBF_M_B16_MASK, VMSBF_M, 0x1, 0x0 }, // 5877 |
11869 | | { PseudoVMSBF_M_B32, VMSBF_M, 0x2, 0x0 }, // 5878 |
11870 | | { PseudoVMSBF_M_B32_MASK, VMSBF_M, 0x2, 0x0 }, // 5879 |
11871 | | { PseudoVMSBF_M_B64, VMSBF_M, 0x3, 0x0 }, // 5880 |
11872 | | { PseudoVMSBF_M_B64_MASK, VMSBF_M, 0x3, 0x0 }, // 5881 |
11873 | | { PseudoVMSBF_M_B1, VMSBF_M, 0x5, 0x0 }, // 5882 |
11874 | | { PseudoVMSBF_M_B1_MASK, VMSBF_M, 0x5, 0x0 }, // 5883 |
11875 | | { PseudoVMSBF_M_B2, VMSBF_M, 0x6, 0x0 }, // 5884 |
11876 | | { PseudoVMSBF_M_B2_MASK, VMSBF_M, 0x6, 0x0 }, // 5885 |
11877 | | { PseudoVMSBF_M_B4, VMSBF_M, 0x7, 0x0 }, // 5886 |
11878 | | { PseudoVMSBF_M_B4_MASK, VMSBF_M, 0x7, 0x0 }, // 5887 |
11879 | | { PseudoVMSEQ_VI_M1, VMSEQ_VI, 0x0, 0x0 }, // 5888 |
11880 | | { PseudoVMSEQ_VI_M1_MASK, VMSEQ_VI, 0x0, 0x0 }, // 5889 |
11881 | | { PseudoVMSEQ_VI_M2, VMSEQ_VI, 0x1, 0x0 }, // 5890 |
11882 | | { PseudoVMSEQ_VI_M2_MASK, VMSEQ_VI, 0x1, 0x0 }, // 5891 |
11883 | | { PseudoVMSEQ_VI_M4, VMSEQ_VI, 0x2, 0x0 }, // 5892 |
11884 | | { PseudoVMSEQ_VI_M4_MASK, VMSEQ_VI, 0x2, 0x0 }, // 5893 |
11885 | | { PseudoVMSEQ_VI_M8, VMSEQ_VI, 0x3, 0x0 }, // 5894 |
11886 | | { PseudoVMSEQ_VI_M8_MASK, VMSEQ_VI, 0x3, 0x0 }, // 5895 |
11887 | | { PseudoVMSEQ_VI_MF8, VMSEQ_VI, 0x5, 0x0 }, // 5896 |
11888 | | { PseudoVMSEQ_VI_MF8_MASK, VMSEQ_VI, 0x5, 0x0 }, // 5897 |
11889 | | { PseudoVMSEQ_VI_MF4, VMSEQ_VI, 0x6, 0x0 }, // 5898 |
11890 | | { PseudoVMSEQ_VI_MF4_MASK, VMSEQ_VI, 0x6, 0x0 }, // 5899 |
11891 | | { PseudoVMSEQ_VI_MF2, VMSEQ_VI, 0x7, 0x0 }, // 5900 |
11892 | | { PseudoVMSEQ_VI_MF2_MASK, VMSEQ_VI, 0x7, 0x0 }, // 5901 |
11893 | | { PseudoVMSEQ_VV_M1, VMSEQ_VV, 0x0, 0x0 }, // 5902 |
11894 | | { PseudoVMSEQ_VV_M1_MASK, VMSEQ_VV, 0x0, 0x0 }, // 5903 |
11895 | | { PseudoVMSEQ_VV_M2, VMSEQ_VV, 0x1, 0x0 }, // 5904 |
11896 | | { PseudoVMSEQ_VV_M2_MASK, VMSEQ_VV, 0x1, 0x0 }, // 5905 |
11897 | | { PseudoVMSEQ_VV_M4, VMSEQ_VV, 0x2, 0x0 }, // 5906 |
11898 | | { PseudoVMSEQ_VV_M4_MASK, VMSEQ_VV, 0x2, 0x0 }, // 5907 |
11899 | | { PseudoVMSEQ_VV_M8, VMSEQ_VV, 0x3, 0x0 }, // 5908 |
11900 | | { PseudoVMSEQ_VV_M8_MASK, VMSEQ_VV, 0x3, 0x0 }, // 5909 |
11901 | | { PseudoVMSEQ_VV_MF8, VMSEQ_VV, 0x5, 0x0 }, // 5910 |
11902 | | { PseudoVMSEQ_VV_MF8_MASK, VMSEQ_VV, 0x5, 0x0 }, // 5911 |
11903 | | { PseudoVMSEQ_VV_MF4, VMSEQ_VV, 0x6, 0x0 }, // 5912 |
11904 | | { PseudoVMSEQ_VV_MF4_MASK, VMSEQ_VV, 0x6, 0x0 }, // 5913 |
11905 | | { PseudoVMSEQ_VV_MF2, VMSEQ_VV, 0x7, 0x0 }, // 5914 |
11906 | | { PseudoVMSEQ_VV_MF2_MASK, VMSEQ_VV, 0x7, 0x0 }, // 5915 |
11907 | | { PseudoVMSEQ_VX_M1, VMSEQ_VX, 0x0, 0x0 }, // 5916 |
11908 | | { PseudoVMSEQ_VX_M1_MASK, VMSEQ_VX, 0x0, 0x0 }, // 5917 |
11909 | | { PseudoVMSEQ_VX_M2, VMSEQ_VX, 0x1, 0x0 }, // 5918 |
11910 | | { PseudoVMSEQ_VX_M2_MASK, VMSEQ_VX, 0x1, 0x0 }, // 5919 |
11911 | | { PseudoVMSEQ_VX_M4, VMSEQ_VX, 0x2, 0x0 }, // 5920 |
11912 | | { PseudoVMSEQ_VX_M4_MASK, VMSEQ_VX, 0x2, 0x0 }, // 5921 |
11913 | | { PseudoVMSEQ_VX_M8, VMSEQ_VX, 0x3, 0x0 }, // 5922 |
11914 | | { PseudoVMSEQ_VX_M8_MASK, VMSEQ_VX, 0x3, 0x0 }, // 5923 |
11915 | | { PseudoVMSEQ_VX_MF8, VMSEQ_VX, 0x5, 0x0 }, // 5924 |
11916 | | { PseudoVMSEQ_VX_MF8_MASK, VMSEQ_VX, 0x5, 0x0 }, // 5925 |
11917 | | { PseudoVMSEQ_VX_MF4, VMSEQ_VX, 0x6, 0x0 }, // 5926 |
11918 | | { PseudoVMSEQ_VX_MF4_MASK, VMSEQ_VX, 0x6, 0x0 }, // 5927 |
11919 | | { PseudoVMSEQ_VX_MF2, VMSEQ_VX, 0x7, 0x0 }, // 5928 |
11920 | | { PseudoVMSEQ_VX_MF2_MASK, VMSEQ_VX, 0x7, 0x0 }, // 5929 |
11921 | | { PseudoVMSGTU_VI_M1, VMSGTU_VI, 0x0, 0x0 }, // 5930 |
11922 | | { PseudoVMSGTU_VI_M1_MASK, VMSGTU_VI, 0x0, 0x0 }, // 5931 |
11923 | | { PseudoVMSGTU_VI_M2, VMSGTU_VI, 0x1, 0x0 }, // 5932 |
11924 | | { PseudoVMSGTU_VI_M2_MASK, VMSGTU_VI, 0x1, 0x0 }, // 5933 |
11925 | | { PseudoVMSGTU_VI_M4, VMSGTU_VI, 0x2, 0x0 }, // 5934 |
11926 | | { PseudoVMSGTU_VI_M4_MASK, VMSGTU_VI, 0x2, 0x0 }, // 5935 |
11927 | | { PseudoVMSGTU_VI_M8, VMSGTU_VI, 0x3, 0x0 }, // 5936 |
11928 | | { PseudoVMSGTU_VI_M8_MASK, VMSGTU_VI, 0x3, 0x0 }, // 5937 |
11929 | | { PseudoVMSGTU_VI_MF8, VMSGTU_VI, 0x5, 0x0 }, // 5938 |
11930 | | { PseudoVMSGTU_VI_MF8_MASK, VMSGTU_VI, 0x5, 0x0 }, // 5939 |
11931 | | { PseudoVMSGTU_VI_MF4, VMSGTU_VI, 0x6, 0x0 }, // 5940 |
11932 | | { PseudoVMSGTU_VI_MF4_MASK, VMSGTU_VI, 0x6, 0x0 }, // 5941 |
11933 | | { PseudoVMSGTU_VI_MF2, VMSGTU_VI, 0x7, 0x0 }, // 5942 |
11934 | | { PseudoVMSGTU_VI_MF2_MASK, VMSGTU_VI, 0x7, 0x0 }, // 5943 |
11935 | | { PseudoVMSGTU_VX_M1, VMSGTU_VX, 0x0, 0x0 }, // 5944 |
11936 | | { PseudoVMSGTU_VX_M1_MASK, VMSGTU_VX, 0x0, 0x0 }, // 5945 |
11937 | | { PseudoVMSGTU_VX_M2, VMSGTU_VX, 0x1, 0x0 }, // 5946 |
11938 | | { PseudoVMSGTU_VX_M2_MASK, VMSGTU_VX, 0x1, 0x0 }, // 5947 |
11939 | | { PseudoVMSGTU_VX_M4, VMSGTU_VX, 0x2, 0x0 }, // 5948 |
11940 | | { PseudoVMSGTU_VX_M4_MASK, VMSGTU_VX, 0x2, 0x0 }, // 5949 |
11941 | | { PseudoVMSGTU_VX_M8, VMSGTU_VX, 0x3, 0x0 }, // 5950 |
11942 | | { PseudoVMSGTU_VX_M8_MASK, VMSGTU_VX, 0x3, 0x0 }, // 5951 |
11943 | | { PseudoVMSGTU_VX_MF8, VMSGTU_VX, 0x5, 0x0 }, // 5952 |
11944 | | { PseudoVMSGTU_VX_MF8_MASK, VMSGTU_VX, 0x5, 0x0 }, // 5953 |
11945 | | { PseudoVMSGTU_VX_MF4, VMSGTU_VX, 0x6, 0x0 }, // 5954 |
11946 | | { PseudoVMSGTU_VX_MF4_MASK, VMSGTU_VX, 0x6, 0x0 }, // 5955 |
11947 | | { PseudoVMSGTU_VX_MF2, VMSGTU_VX, 0x7, 0x0 }, // 5956 |
11948 | | { PseudoVMSGTU_VX_MF2_MASK, VMSGTU_VX, 0x7, 0x0 }, // 5957 |
11949 | | { PseudoVMSGT_VI_M1, VMSGT_VI, 0x0, 0x0 }, // 5958 |
11950 | | { PseudoVMSGT_VI_M1_MASK, VMSGT_VI, 0x0, 0x0 }, // 5959 |
11951 | | { PseudoVMSGT_VI_M2, VMSGT_VI, 0x1, 0x0 }, // 5960 |
11952 | | { PseudoVMSGT_VI_M2_MASK, VMSGT_VI, 0x1, 0x0 }, // 5961 |
11953 | | { PseudoVMSGT_VI_M4, VMSGT_VI, 0x2, 0x0 }, // 5962 |
11954 | | { PseudoVMSGT_VI_M4_MASK, VMSGT_VI, 0x2, 0x0 }, // 5963 |
11955 | | { PseudoVMSGT_VI_M8, VMSGT_VI, 0x3, 0x0 }, // 5964 |
11956 | | { PseudoVMSGT_VI_M8_MASK, VMSGT_VI, 0x3, 0x0 }, // 5965 |
11957 | | { PseudoVMSGT_VI_MF8, VMSGT_VI, 0x5, 0x0 }, // 5966 |
11958 | | { PseudoVMSGT_VI_MF8_MASK, VMSGT_VI, 0x5, 0x0 }, // 5967 |
11959 | | { PseudoVMSGT_VI_MF4, VMSGT_VI, 0x6, 0x0 }, // 5968 |
11960 | | { PseudoVMSGT_VI_MF4_MASK, VMSGT_VI, 0x6, 0x0 }, // 5969 |
11961 | | { PseudoVMSGT_VI_MF2, VMSGT_VI, 0x7, 0x0 }, // 5970 |
11962 | | { PseudoVMSGT_VI_MF2_MASK, VMSGT_VI, 0x7, 0x0 }, // 5971 |
11963 | | { PseudoVMSGT_VX_M1, VMSGT_VX, 0x0, 0x0 }, // 5972 |
11964 | | { PseudoVMSGT_VX_M1_MASK, VMSGT_VX, 0x0, 0x0 }, // 5973 |
11965 | | { PseudoVMSGT_VX_M2, VMSGT_VX, 0x1, 0x0 }, // 5974 |
11966 | | { PseudoVMSGT_VX_M2_MASK, VMSGT_VX, 0x1, 0x0 }, // 5975 |
11967 | | { PseudoVMSGT_VX_M4, VMSGT_VX, 0x2, 0x0 }, // 5976 |
11968 | | { PseudoVMSGT_VX_M4_MASK, VMSGT_VX, 0x2, 0x0 }, // 5977 |
11969 | | { PseudoVMSGT_VX_M8, VMSGT_VX, 0x3, 0x0 }, // 5978 |
11970 | | { PseudoVMSGT_VX_M8_MASK, VMSGT_VX, 0x3, 0x0 }, // 5979 |
11971 | | { PseudoVMSGT_VX_MF8, VMSGT_VX, 0x5, 0x0 }, // 5980 |
11972 | | { PseudoVMSGT_VX_MF8_MASK, VMSGT_VX, 0x5, 0x0 }, // 5981 |
11973 | | { PseudoVMSGT_VX_MF4, VMSGT_VX, 0x6, 0x0 }, // 5982 |
11974 | | { PseudoVMSGT_VX_MF4_MASK, VMSGT_VX, 0x6, 0x0 }, // 5983 |
11975 | | { PseudoVMSGT_VX_MF2, VMSGT_VX, 0x7, 0x0 }, // 5984 |
11976 | | { PseudoVMSGT_VX_MF2_MASK, VMSGT_VX, 0x7, 0x0 }, // 5985 |
11977 | | { PseudoVMSIF_M_B8, VMSIF_M, 0x0, 0x0 }, // 5986 |
11978 | | { PseudoVMSIF_M_B8_MASK, VMSIF_M, 0x0, 0x0 }, // 5987 |
11979 | | { PseudoVMSIF_M_B16, VMSIF_M, 0x1, 0x0 }, // 5988 |
11980 | | { PseudoVMSIF_M_B16_MASK, VMSIF_M, 0x1, 0x0 }, // 5989 |
11981 | | { PseudoVMSIF_M_B32, VMSIF_M, 0x2, 0x0 }, // 5990 |
11982 | | { PseudoVMSIF_M_B32_MASK, VMSIF_M, 0x2, 0x0 }, // 5991 |
11983 | | { PseudoVMSIF_M_B64, VMSIF_M, 0x3, 0x0 }, // 5992 |
11984 | | { PseudoVMSIF_M_B64_MASK, VMSIF_M, 0x3, 0x0 }, // 5993 |
11985 | | { PseudoVMSIF_M_B1, VMSIF_M, 0x5, 0x0 }, // 5994 |
11986 | | { PseudoVMSIF_M_B1_MASK, VMSIF_M, 0x5, 0x0 }, // 5995 |
11987 | | { PseudoVMSIF_M_B2, VMSIF_M, 0x6, 0x0 }, // 5996 |
11988 | | { PseudoVMSIF_M_B2_MASK, VMSIF_M, 0x6, 0x0 }, // 5997 |
11989 | | { PseudoVMSIF_M_B4, VMSIF_M, 0x7, 0x0 }, // 5998 |
11990 | | { PseudoVMSIF_M_B4_MASK, VMSIF_M, 0x7, 0x0 }, // 5999 |
11991 | | { PseudoVMSLEU_VI_M1, VMSLEU_VI, 0x0, 0x0 }, // 6000 |
11992 | | { PseudoVMSLEU_VI_M1_MASK, VMSLEU_VI, 0x0, 0x0 }, // 6001 |
11993 | | { PseudoVMSLEU_VI_M2, VMSLEU_VI, 0x1, 0x0 }, // 6002 |
11994 | | { PseudoVMSLEU_VI_M2_MASK, VMSLEU_VI, 0x1, 0x0 }, // 6003 |
11995 | | { PseudoVMSLEU_VI_M4, VMSLEU_VI, 0x2, 0x0 }, // 6004 |
11996 | | { PseudoVMSLEU_VI_M4_MASK, VMSLEU_VI, 0x2, 0x0 }, // 6005 |
11997 | | { PseudoVMSLEU_VI_M8, VMSLEU_VI, 0x3, 0x0 }, // 6006 |
11998 | | { PseudoVMSLEU_VI_M8_MASK, VMSLEU_VI, 0x3, 0x0 }, // 6007 |
11999 | | { PseudoVMSLEU_VI_MF8, VMSLEU_VI, 0x5, 0x0 }, // 6008 |
12000 | | { PseudoVMSLEU_VI_MF8_MASK, VMSLEU_VI, 0x5, 0x0 }, // 6009 |
12001 | | { PseudoVMSLEU_VI_MF4, VMSLEU_VI, 0x6, 0x0 }, // 6010 |
12002 | | { PseudoVMSLEU_VI_MF4_MASK, VMSLEU_VI, 0x6, 0x0 }, // 6011 |
12003 | | { PseudoVMSLEU_VI_MF2, VMSLEU_VI, 0x7, 0x0 }, // 6012 |
12004 | | { PseudoVMSLEU_VI_MF2_MASK, VMSLEU_VI, 0x7, 0x0 }, // 6013 |
12005 | | { PseudoVMSLEU_VV_M1, VMSLEU_VV, 0x0, 0x0 }, // 6014 |
12006 | | { PseudoVMSLEU_VV_M1_MASK, VMSLEU_VV, 0x0, 0x0 }, // 6015 |
12007 | | { PseudoVMSLEU_VV_M2, VMSLEU_VV, 0x1, 0x0 }, // 6016 |
12008 | | { PseudoVMSLEU_VV_M2_MASK, VMSLEU_VV, 0x1, 0x0 }, // 6017 |
12009 | | { PseudoVMSLEU_VV_M4, VMSLEU_VV, 0x2, 0x0 }, // 6018 |
12010 | | { PseudoVMSLEU_VV_M4_MASK, VMSLEU_VV, 0x2, 0x0 }, // 6019 |
12011 | | { PseudoVMSLEU_VV_M8, VMSLEU_VV, 0x3, 0x0 }, // 6020 |
12012 | | { PseudoVMSLEU_VV_M8_MASK, VMSLEU_VV, 0x3, 0x0 }, // 6021 |
12013 | | { PseudoVMSLEU_VV_MF8, VMSLEU_VV, 0x5, 0x0 }, // 6022 |
12014 | | { PseudoVMSLEU_VV_MF8_MASK, VMSLEU_VV, 0x5, 0x0 }, // 6023 |
12015 | | { PseudoVMSLEU_VV_MF4, VMSLEU_VV, 0x6, 0x0 }, // 6024 |
12016 | | { PseudoVMSLEU_VV_MF4_MASK, VMSLEU_VV, 0x6, 0x0 }, // 6025 |
12017 | | { PseudoVMSLEU_VV_MF2, VMSLEU_VV, 0x7, 0x0 }, // 6026 |
12018 | | { PseudoVMSLEU_VV_MF2_MASK, VMSLEU_VV, 0x7, 0x0 }, // 6027 |
12019 | | { PseudoVMSLEU_VX_M1, VMSLEU_VX, 0x0, 0x0 }, // 6028 |
12020 | | { PseudoVMSLEU_VX_M1_MASK, VMSLEU_VX, 0x0, 0x0 }, // 6029 |
12021 | | { PseudoVMSLEU_VX_M2, VMSLEU_VX, 0x1, 0x0 }, // 6030 |
12022 | | { PseudoVMSLEU_VX_M2_MASK, VMSLEU_VX, 0x1, 0x0 }, // 6031 |
12023 | | { PseudoVMSLEU_VX_M4, VMSLEU_VX, 0x2, 0x0 }, // 6032 |
12024 | | { PseudoVMSLEU_VX_M4_MASK, VMSLEU_VX, 0x2, 0x0 }, // 6033 |
12025 | | { PseudoVMSLEU_VX_M8, VMSLEU_VX, 0x3, 0x0 }, // 6034 |
12026 | | { PseudoVMSLEU_VX_M8_MASK, VMSLEU_VX, 0x3, 0x0 }, // 6035 |
12027 | | { PseudoVMSLEU_VX_MF8, VMSLEU_VX, 0x5, 0x0 }, // 6036 |
12028 | | { PseudoVMSLEU_VX_MF8_MASK, VMSLEU_VX, 0x5, 0x0 }, // 6037 |
12029 | | { PseudoVMSLEU_VX_MF4, VMSLEU_VX, 0x6, 0x0 }, // 6038 |
12030 | | { PseudoVMSLEU_VX_MF4_MASK, VMSLEU_VX, 0x6, 0x0 }, // 6039 |
12031 | | { PseudoVMSLEU_VX_MF2, VMSLEU_VX, 0x7, 0x0 }, // 6040 |
12032 | | { PseudoVMSLEU_VX_MF2_MASK, VMSLEU_VX, 0x7, 0x0 }, // 6041 |
12033 | | { PseudoVMSLE_VI_M1, VMSLE_VI, 0x0, 0x0 }, // 6042 |
12034 | | { PseudoVMSLE_VI_M1_MASK, VMSLE_VI, 0x0, 0x0 }, // 6043 |
12035 | | { PseudoVMSLE_VI_M2, VMSLE_VI, 0x1, 0x0 }, // 6044 |
12036 | | { PseudoVMSLE_VI_M2_MASK, VMSLE_VI, 0x1, 0x0 }, // 6045 |
12037 | | { PseudoVMSLE_VI_M4, VMSLE_VI, 0x2, 0x0 }, // 6046 |
12038 | | { PseudoVMSLE_VI_M4_MASK, VMSLE_VI, 0x2, 0x0 }, // 6047 |
12039 | | { PseudoVMSLE_VI_M8, VMSLE_VI, 0x3, 0x0 }, // 6048 |
12040 | | { PseudoVMSLE_VI_M8_MASK, VMSLE_VI, 0x3, 0x0 }, // 6049 |
12041 | | { PseudoVMSLE_VI_MF8, VMSLE_VI, 0x5, 0x0 }, // 6050 |
12042 | | { PseudoVMSLE_VI_MF8_MASK, VMSLE_VI, 0x5, 0x0 }, // 6051 |
12043 | | { PseudoVMSLE_VI_MF4, VMSLE_VI, 0x6, 0x0 }, // 6052 |
12044 | | { PseudoVMSLE_VI_MF4_MASK, VMSLE_VI, 0x6, 0x0 }, // 6053 |
12045 | | { PseudoVMSLE_VI_MF2, VMSLE_VI, 0x7, 0x0 }, // 6054 |
12046 | | { PseudoVMSLE_VI_MF2_MASK, VMSLE_VI, 0x7, 0x0 }, // 6055 |
12047 | | { PseudoVMSLE_VV_M1, VMSLE_VV, 0x0, 0x0 }, // 6056 |
12048 | | { PseudoVMSLE_VV_M1_MASK, VMSLE_VV, 0x0, 0x0 }, // 6057 |
12049 | | { PseudoVMSLE_VV_M2, VMSLE_VV, 0x1, 0x0 }, // 6058 |
12050 | | { PseudoVMSLE_VV_M2_MASK, VMSLE_VV, 0x1, 0x0 }, // 6059 |
12051 | | { PseudoVMSLE_VV_M4, VMSLE_VV, 0x2, 0x0 }, // 6060 |
12052 | | { PseudoVMSLE_VV_M4_MASK, VMSLE_VV, 0x2, 0x0 }, // 6061 |
12053 | | { PseudoVMSLE_VV_M8, VMSLE_VV, 0x3, 0x0 }, // 6062 |
12054 | | { PseudoVMSLE_VV_M8_MASK, VMSLE_VV, 0x3, 0x0 }, // 6063 |
12055 | | { PseudoVMSLE_VV_MF8, VMSLE_VV, 0x5, 0x0 }, // 6064 |
12056 | | { PseudoVMSLE_VV_MF8_MASK, VMSLE_VV, 0x5, 0x0 }, // 6065 |
12057 | | { PseudoVMSLE_VV_MF4, VMSLE_VV, 0x6, 0x0 }, // 6066 |
12058 | | { PseudoVMSLE_VV_MF4_MASK, VMSLE_VV, 0x6, 0x0 }, // 6067 |
12059 | | { PseudoVMSLE_VV_MF2, VMSLE_VV, 0x7, 0x0 }, // 6068 |
12060 | | { PseudoVMSLE_VV_MF2_MASK, VMSLE_VV, 0x7, 0x0 }, // 6069 |
12061 | | { PseudoVMSLE_VX_M1, VMSLE_VX, 0x0, 0x0 }, // 6070 |
12062 | | { PseudoVMSLE_VX_M1_MASK, VMSLE_VX, 0x0, 0x0 }, // 6071 |
12063 | | { PseudoVMSLE_VX_M2, VMSLE_VX, 0x1, 0x0 }, // 6072 |
12064 | | { PseudoVMSLE_VX_M2_MASK, VMSLE_VX, 0x1, 0x0 }, // 6073 |
12065 | | { PseudoVMSLE_VX_M4, VMSLE_VX, 0x2, 0x0 }, // 6074 |
12066 | | { PseudoVMSLE_VX_M4_MASK, VMSLE_VX, 0x2, 0x0 }, // 6075 |
12067 | | { PseudoVMSLE_VX_M8, VMSLE_VX, 0x3, 0x0 }, // 6076 |
12068 | | { PseudoVMSLE_VX_M8_MASK, VMSLE_VX, 0x3, 0x0 }, // 6077 |
12069 | | { PseudoVMSLE_VX_MF8, VMSLE_VX, 0x5, 0x0 }, // 6078 |
12070 | | { PseudoVMSLE_VX_MF8_MASK, VMSLE_VX, 0x5, 0x0 }, // 6079 |
12071 | | { PseudoVMSLE_VX_MF4, VMSLE_VX, 0x6, 0x0 }, // 6080 |
12072 | | { PseudoVMSLE_VX_MF4_MASK, VMSLE_VX, 0x6, 0x0 }, // 6081 |
12073 | | { PseudoVMSLE_VX_MF2, VMSLE_VX, 0x7, 0x0 }, // 6082 |
12074 | | { PseudoVMSLE_VX_MF2_MASK, VMSLE_VX, 0x7, 0x0 }, // 6083 |
12075 | | { PseudoVMSLTU_VV_M1, VMSLTU_VV, 0x0, 0x0 }, // 6084 |
12076 | | { PseudoVMSLTU_VV_M1_MASK, VMSLTU_VV, 0x0, 0x0 }, // 6085 |
12077 | | { PseudoVMSLTU_VV_M2, VMSLTU_VV, 0x1, 0x0 }, // 6086 |
12078 | | { PseudoVMSLTU_VV_M2_MASK, VMSLTU_VV, 0x1, 0x0 }, // 6087 |
12079 | | { PseudoVMSLTU_VV_M4, VMSLTU_VV, 0x2, 0x0 }, // 6088 |
12080 | | { PseudoVMSLTU_VV_M4_MASK, VMSLTU_VV, 0x2, 0x0 }, // 6089 |
12081 | | { PseudoVMSLTU_VV_M8, VMSLTU_VV, 0x3, 0x0 }, // 6090 |
12082 | | { PseudoVMSLTU_VV_M8_MASK, VMSLTU_VV, 0x3, 0x0 }, // 6091 |
12083 | | { PseudoVMSLTU_VV_MF8, VMSLTU_VV, 0x5, 0x0 }, // 6092 |
12084 | | { PseudoVMSLTU_VV_MF8_MASK, VMSLTU_VV, 0x5, 0x0 }, // 6093 |
12085 | | { PseudoVMSLTU_VV_MF4, VMSLTU_VV, 0x6, 0x0 }, // 6094 |
12086 | | { PseudoVMSLTU_VV_MF4_MASK, VMSLTU_VV, 0x6, 0x0 }, // 6095 |
12087 | | { PseudoVMSLTU_VV_MF2, VMSLTU_VV, 0x7, 0x0 }, // 6096 |
12088 | | { PseudoVMSLTU_VV_MF2_MASK, VMSLTU_VV, 0x7, 0x0 }, // 6097 |
12089 | | { PseudoVMSLTU_VX_M1, VMSLTU_VX, 0x0, 0x0 }, // 6098 |
12090 | | { PseudoVMSLTU_VX_M1_MASK, VMSLTU_VX, 0x0, 0x0 }, // 6099 |
12091 | | { PseudoVMSLTU_VX_M2, VMSLTU_VX, 0x1, 0x0 }, // 6100 |
12092 | | { PseudoVMSLTU_VX_M2_MASK, VMSLTU_VX, 0x1, 0x0 }, // 6101 |
12093 | | { PseudoVMSLTU_VX_M4, VMSLTU_VX, 0x2, 0x0 }, // 6102 |
12094 | | { PseudoVMSLTU_VX_M4_MASK, VMSLTU_VX, 0x2, 0x0 }, // 6103 |
12095 | | { PseudoVMSLTU_VX_M8, VMSLTU_VX, 0x3, 0x0 }, // 6104 |
12096 | | { PseudoVMSLTU_VX_M8_MASK, VMSLTU_VX, 0x3, 0x0 }, // 6105 |
12097 | | { PseudoVMSLTU_VX_MF8, VMSLTU_VX, 0x5, 0x0 }, // 6106 |
12098 | | { PseudoVMSLTU_VX_MF8_MASK, VMSLTU_VX, 0x5, 0x0 }, // 6107 |
12099 | | { PseudoVMSLTU_VX_MF4, VMSLTU_VX, 0x6, 0x0 }, // 6108 |
12100 | | { PseudoVMSLTU_VX_MF4_MASK, VMSLTU_VX, 0x6, 0x0 }, // 6109 |
12101 | | { PseudoVMSLTU_VX_MF2, VMSLTU_VX, 0x7, 0x0 }, // 6110 |
12102 | | { PseudoVMSLTU_VX_MF2_MASK, VMSLTU_VX, 0x7, 0x0 }, // 6111 |
12103 | | { PseudoVMSLT_VV_M1, VMSLT_VV, 0x0, 0x0 }, // 6112 |
12104 | | { PseudoVMSLT_VV_M1_MASK, VMSLT_VV, 0x0, 0x0 }, // 6113 |
12105 | | { PseudoVMSLT_VV_M2, VMSLT_VV, 0x1, 0x0 }, // 6114 |
12106 | | { PseudoVMSLT_VV_M2_MASK, VMSLT_VV, 0x1, 0x0 }, // 6115 |
12107 | | { PseudoVMSLT_VV_M4, VMSLT_VV, 0x2, 0x0 }, // 6116 |
12108 | | { PseudoVMSLT_VV_M4_MASK, VMSLT_VV, 0x2, 0x0 }, // 6117 |
12109 | | { PseudoVMSLT_VV_M8, VMSLT_VV, 0x3, 0x0 }, // 6118 |
12110 | | { PseudoVMSLT_VV_M8_MASK, VMSLT_VV, 0x3, 0x0 }, // 6119 |
12111 | | { PseudoVMSLT_VV_MF8, VMSLT_VV, 0x5, 0x0 }, // 6120 |
12112 | | { PseudoVMSLT_VV_MF8_MASK, VMSLT_VV, 0x5, 0x0 }, // 6121 |
12113 | | { PseudoVMSLT_VV_MF4, VMSLT_VV, 0x6, 0x0 }, // 6122 |
12114 | | { PseudoVMSLT_VV_MF4_MASK, VMSLT_VV, 0x6, 0x0 }, // 6123 |
12115 | | { PseudoVMSLT_VV_MF2, VMSLT_VV, 0x7, 0x0 }, // 6124 |
12116 | | { PseudoVMSLT_VV_MF2_MASK, VMSLT_VV, 0x7, 0x0 }, // 6125 |
12117 | | { PseudoVMSLT_VX_M1, VMSLT_VX, 0x0, 0x0 }, // 6126 |
12118 | | { PseudoVMSLT_VX_M1_MASK, VMSLT_VX, 0x0, 0x0 }, // 6127 |
12119 | | { PseudoVMSLT_VX_M2, VMSLT_VX, 0x1, 0x0 }, // 6128 |
12120 | | { PseudoVMSLT_VX_M2_MASK, VMSLT_VX, 0x1, 0x0 }, // 6129 |
12121 | | { PseudoVMSLT_VX_M4, VMSLT_VX, 0x2, 0x0 }, // 6130 |
12122 | | { PseudoVMSLT_VX_M4_MASK, VMSLT_VX, 0x2, 0x0 }, // 6131 |
12123 | | { PseudoVMSLT_VX_M8, VMSLT_VX, 0x3, 0x0 }, // 6132 |
12124 | | { PseudoVMSLT_VX_M8_MASK, VMSLT_VX, 0x3, 0x0 }, // 6133 |
12125 | | { PseudoVMSLT_VX_MF8, VMSLT_VX, 0x5, 0x0 }, // 6134 |
12126 | | { PseudoVMSLT_VX_MF8_MASK, VMSLT_VX, 0x5, 0x0 }, // 6135 |
12127 | | { PseudoVMSLT_VX_MF4, VMSLT_VX, 0x6, 0x0 }, // 6136 |
12128 | | { PseudoVMSLT_VX_MF4_MASK, VMSLT_VX, 0x6, 0x0 }, // 6137 |
12129 | | { PseudoVMSLT_VX_MF2, VMSLT_VX, 0x7, 0x0 }, // 6138 |
12130 | | { PseudoVMSLT_VX_MF2_MASK, VMSLT_VX, 0x7, 0x0 }, // 6139 |
12131 | | { PseudoVMSNE_VI_M1, VMSNE_VI, 0x0, 0x0 }, // 6140 |
12132 | | { PseudoVMSNE_VI_M1_MASK, VMSNE_VI, 0x0, 0x0 }, // 6141 |
12133 | | { PseudoVMSNE_VI_M2, VMSNE_VI, 0x1, 0x0 }, // 6142 |
12134 | | { PseudoVMSNE_VI_M2_MASK, VMSNE_VI, 0x1, 0x0 }, // 6143 |
12135 | | { PseudoVMSNE_VI_M4, VMSNE_VI, 0x2, 0x0 }, // 6144 |
12136 | | { PseudoVMSNE_VI_M4_MASK, VMSNE_VI, 0x2, 0x0 }, // 6145 |
12137 | | { PseudoVMSNE_VI_M8, VMSNE_VI, 0x3, 0x0 }, // 6146 |
12138 | | { PseudoVMSNE_VI_M8_MASK, VMSNE_VI, 0x3, 0x0 }, // 6147 |
12139 | | { PseudoVMSNE_VI_MF8, VMSNE_VI, 0x5, 0x0 }, // 6148 |
12140 | | { PseudoVMSNE_VI_MF8_MASK, VMSNE_VI, 0x5, 0x0 }, // 6149 |
12141 | | { PseudoVMSNE_VI_MF4, VMSNE_VI, 0x6, 0x0 }, // 6150 |
12142 | | { PseudoVMSNE_VI_MF4_MASK, VMSNE_VI, 0x6, 0x0 }, // 6151 |
12143 | | { PseudoVMSNE_VI_MF2, VMSNE_VI, 0x7, 0x0 }, // 6152 |
12144 | | { PseudoVMSNE_VI_MF2_MASK, VMSNE_VI, 0x7, 0x0 }, // 6153 |
12145 | | { PseudoVMSNE_VV_M1, VMSNE_VV, 0x0, 0x0 }, // 6154 |
12146 | | { PseudoVMSNE_VV_M1_MASK, VMSNE_VV, 0x0, 0x0 }, // 6155 |
12147 | | { PseudoVMSNE_VV_M2, VMSNE_VV, 0x1, 0x0 }, // 6156 |
12148 | | { PseudoVMSNE_VV_M2_MASK, VMSNE_VV, 0x1, 0x0 }, // 6157 |
12149 | | { PseudoVMSNE_VV_M4, VMSNE_VV, 0x2, 0x0 }, // 6158 |
12150 | | { PseudoVMSNE_VV_M4_MASK, VMSNE_VV, 0x2, 0x0 }, // 6159 |
12151 | | { PseudoVMSNE_VV_M8, VMSNE_VV, 0x3, 0x0 }, // 6160 |
12152 | | { PseudoVMSNE_VV_M8_MASK, VMSNE_VV, 0x3, 0x0 }, // 6161 |
12153 | | { PseudoVMSNE_VV_MF8, VMSNE_VV, 0x5, 0x0 }, // 6162 |
12154 | | { PseudoVMSNE_VV_MF8_MASK, VMSNE_VV, 0x5, 0x0 }, // 6163 |
12155 | | { PseudoVMSNE_VV_MF4, VMSNE_VV, 0x6, 0x0 }, // 6164 |
12156 | | { PseudoVMSNE_VV_MF4_MASK, VMSNE_VV, 0x6, 0x0 }, // 6165 |
12157 | | { PseudoVMSNE_VV_MF2, VMSNE_VV, 0x7, 0x0 }, // 6166 |
12158 | | { PseudoVMSNE_VV_MF2_MASK, VMSNE_VV, 0x7, 0x0 }, // 6167 |
12159 | | { PseudoVMSNE_VX_M1, VMSNE_VX, 0x0, 0x0 }, // 6168 |
12160 | | { PseudoVMSNE_VX_M1_MASK, VMSNE_VX, 0x0, 0x0 }, // 6169 |
12161 | | { PseudoVMSNE_VX_M2, VMSNE_VX, 0x1, 0x0 }, // 6170 |
12162 | | { PseudoVMSNE_VX_M2_MASK, VMSNE_VX, 0x1, 0x0 }, // 6171 |
12163 | | { PseudoVMSNE_VX_M4, VMSNE_VX, 0x2, 0x0 }, // 6172 |
12164 | | { PseudoVMSNE_VX_M4_MASK, VMSNE_VX, 0x2, 0x0 }, // 6173 |
12165 | | { PseudoVMSNE_VX_M8, VMSNE_VX, 0x3, 0x0 }, // 6174 |
12166 | | { PseudoVMSNE_VX_M8_MASK, VMSNE_VX, 0x3, 0x0 }, // 6175 |
12167 | | { PseudoVMSNE_VX_MF8, VMSNE_VX, 0x5, 0x0 }, // 6176 |
12168 | | { PseudoVMSNE_VX_MF8_MASK, VMSNE_VX, 0x5, 0x0 }, // 6177 |
12169 | | { PseudoVMSNE_VX_MF4, VMSNE_VX, 0x6, 0x0 }, // 6178 |
12170 | | { PseudoVMSNE_VX_MF4_MASK, VMSNE_VX, 0x6, 0x0 }, // 6179 |
12171 | | { PseudoVMSNE_VX_MF2, VMSNE_VX, 0x7, 0x0 }, // 6180 |
12172 | | { PseudoVMSNE_VX_MF2_MASK, VMSNE_VX, 0x7, 0x0 }, // 6181 |
12173 | | { PseudoVMSOF_M_B8, VMSOF_M, 0x0, 0x0 }, // 6182 |
12174 | | { PseudoVMSOF_M_B8_MASK, VMSOF_M, 0x0, 0x0 }, // 6183 |
12175 | | { PseudoVMSOF_M_B16, VMSOF_M, 0x1, 0x0 }, // 6184 |
12176 | | { PseudoVMSOF_M_B16_MASK, VMSOF_M, 0x1, 0x0 }, // 6185 |
12177 | | { PseudoVMSOF_M_B32, VMSOF_M, 0x2, 0x0 }, // 6186 |
12178 | | { PseudoVMSOF_M_B32_MASK, VMSOF_M, 0x2, 0x0 }, // 6187 |
12179 | | { PseudoVMSOF_M_B64, VMSOF_M, 0x3, 0x0 }, // 6188 |
12180 | | { PseudoVMSOF_M_B64_MASK, VMSOF_M, 0x3, 0x0 }, // 6189 |
12181 | | { PseudoVMSOF_M_B1, VMSOF_M, 0x5, 0x0 }, // 6190 |
12182 | | { PseudoVMSOF_M_B1_MASK, VMSOF_M, 0x5, 0x0 }, // 6191 |
12183 | | { PseudoVMSOF_M_B2, VMSOF_M, 0x6, 0x0 }, // 6192 |
12184 | | { PseudoVMSOF_M_B2_MASK, VMSOF_M, 0x6, 0x0 }, // 6193 |
12185 | | { PseudoVMSOF_M_B4, VMSOF_M, 0x7, 0x0 }, // 6194 |
12186 | | { PseudoVMSOF_M_B4_MASK, VMSOF_M, 0x7, 0x0 }, // 6195 |
12187 | | { PseudoVMULHSU_VV_M1, VMULHSU_VV, 0x0, 0x0 }, // 6196 |
12188 | | { PseudoVMULHSU_VV_M1_MASK, VMULHSU_VV, 0x0, 0x0 }, // 6197 |
12189 | | { PseudoVMULHSU_VV_M2, VMULHSU_VV, 0x1, 0x0 }, // 6198 |
12190 | | { PseudoVMULHSU_VV_M2_MASK, VMULHSU_VV, 0x1, 0x0 }, // 6199 |
12191 | | { PseudoVMULHSU_VV_M4, VMULHSU_VV, 0x2, 0x0 }, // 6200 |
12192 | | { PseudoVMULHSU_VV_M4_MASK, VMULHSU_VV, 0x2, 0x0 }, // 6201 |
12193 | | { PseudoVMULHSU_VV_M8, VMULHSU_VV, 0x3, 0x0 }, // 6202 |
12194 | | { PseudoVMULHSU_VV_M8_MASK, VMULHSU_VV, 0x3, 0x0 }, // 6203 |
12195 | | { PseudoVMULHSU_VV_MF8, VMULHSU_VV, 0x5, 0x0 }, // 6204 |
12196 | | { PseudoVMULHSU_VV_MF8_MASK, VMULHSU_VV, 0x5, 0x0 }, // 6205 |
12197 | | { PseudoVMULHSU_VV_MF4, VMULHSU_VV, 0x6, 0x0 }, // 6206 |
12198 | | { PseudoVMULHSU_VV_MF4_MASK, VMULHSU_VV, 0x6, 0x0 }, // 6207 |
12199 | | { PseudoVMULHSU_VV_MF2, VMULHSU_VV, 0x7, 0x0 }, // 6208 |
12200 | | { PseudoVMULHSU_VV_MF2_MASK, VMULHSU_VV, 0x7, 0x0 }, // 6209 |
12201 | | { PseudoVMULHSU_VX_M1, VMULHSU_VX, 0x0, 0x0 }, // 6210 |
12202 | | { PseudoVMULHSU_VX_M1_MASK, VMULHSU_VX, 0x0, 0x0 }, // 6211 |
12203 | | { PseudoVMULHSU_VX_M2, VMULHSU_VX, 0x1, 0x0 }, // 6212 |
12204 | | { PseudoVMULHSU_VX_M2_MASK, VMULHSU_VX, 0x1, 0x0 }, // 6213 |
12205 | | { PseudoVMULHSU_VX_M4, VMULHSU_VX, 0x2, 0x0 }, // 6214 |
12206 | | { PseudoVMULHSU_VX_M4_MASK, VMULHSU_VX, 0x2, 0x0 }, // 6215 |
12207 | | { PseudoVMULHSU_VX_M8, VMULHSU_VX, 0x3, 0x0 }, // 6216 |
12208 | | { PseudoVMULHSU_VX_M8_MASK, VMULHSU_VX, 0x3, 0x0 }, // 6217 |
12209 | | { PseudoVMULHSU_VX_MF8, VMULHSU_VX, 0x5, 0x0 }, // 6218 |
12210 | | { PseudoVMULHSU_VX_MF8_MASK, VMULHSU_VX, 0x5, 0x0 }, // 6219 |
12211 | | { PseudoVMULHSU_VX_MF4, VMULHSU_VX, 0x6, 0x0 }, // 6220 |
12212 | | { PseudoVMULHSU_VX_MF4_MASK, VMULHSU_VX, 0x6, 0x0 }, // 6221 |
12213 | | { PseudoVMULHSU_VX_MF2, VMULHSU_VX, 0x7, 0x0 }, // 6222 |
12214 | | { PseudoVMULHSU_VX_MF2_MASK, VMULHSU_VX, 0x7, 0x0 }, // 6223 |
12215 | | { PseudoVMULHU_VV_M1, VMULHU_VV, 0x0, 0x0 }, // 6224 |
12216 | | { PseudoVMULHU_VV_M1_MASK, VMULHU_VV, 0x0, 0x0 }, // 6225 |
12217 | | { PseudoVMULHU_VV_M2, VMULHU_VV, 0x1, 0x0 }, // 6226 |
12218 | | { PseudoVMULHU_VV_M2_MASK, VMULHU_VV, 0x1, 0x0 }, // 6227 |
12219 | | { PseudoVMULHU_VV_M4, VMULHU_VV, 0x2, 0x0 }, // 6228 |
12220 | | { PseudoVMULHU_VV_M4_MASK, VMULHU_VV, 0x2, 0x0 }, // 6229 |
12221 | | { PseudoVMULHU_VV_M8, VMULHU_VV, 0x3, 0x0 }, // 6230 |
12222 | | { PseudoVMULHU_VV_M8_MASK, VMULHU_VV, 0x3, 0x0 }, // 6231 |
12223 | | { PseudoVMULHU_VV_MF8, VMULHU_VV, 0x5, 0x0 }, // 6232 |
12224 | | { PseudoVMULHU_VV_MF8_MASK, VMULHU_VV, 0x5, 0x0 }, // 6233 |
12225 | | { PseudoVMULHU_VV_MF4, VMULHU_VV, 0x6, 0x0 }, // 6234 |
12226 | | { PseudoVMULHU_VV_MF4_MASK, VMULHU_VV, 0x6, 0x0 }, // 6235 |
12227 | | { PseudoVMULHU_VV_MF2, VMULHU_VV, 0x7, 0x0 }, // 6236 |
12228 | | { PseudoVMULHU_VV_MF2_MASK, VMULHU_VV, 0x7, 0x0 }, // 6237 |
12229 | | { PseudoVMULHU_VX_M1, VMULHU_VX, 0x0, 0x0 }, // 6238 |
12230 | | { PseudoVMULHU_VX_M1_MASK, VMULHU_VX, 0x0, 0x0 }, // 6239 |
12231 | | { PseudoVMULHU_VX_M2, VMULHU_VX, 0x1, 0x0 }, // 6240 |
12232 | | { PseudoVMULHU_VX_M2_MASK, VMULHU_VX, 0x1, 0x0 }, // 6241 |
12233 | | { PseudoVMULHU_VX_M4, VMULHU_VX, 0x2, 0x0 }, // 6242 |
12234 | | { PseudoVMULHU_VX_M4_MASK, VMULHU_VX, 0x2, 0x0 }, // 6243 |
12235 | | { PseudoVMULHU_VX_M8, VMULHU_VX, 0x3, 0x0 }, // 6244 |
12236 | | { PseudoVMULHU_VX_M8_MASK, VMULHU_VX, 0x3, 0x0 }, // 6245 |
12237 | | { PseudoVMULHU_VX_MF8, VMULHU_VX, 0x5, 0x0 }, // 6246 |
12238 | | { PseudoVMULHU_VX_MF8_MASK, VMULHU_VX, 0x5, 0x0 }, // 6247 |
12239 | | { PseudoVMULHU_VX_MF4, VMULHU_VX, 0x6, 0x0 }, // 6248 |
12240 | | { PseudoVMULHU_VX_MF4_MASK, VMULHU_VX, 0x6, 0x0 }, // 6249 |
12241 | | { PseudoVMULHU_VX_MF2, VMULHU_VX, 0x7, 0x0 }, // 6250 |
12242 | | { PseudoVMULHU_VX_MF2_MASK, VMULHU_VX, 0x7, 0x0 }, // 6251 |
12243 | | { PseudoVMULH_VV_M1, VMULH_VV, 0x0, 0x0 }, // 6252 |
12244 | | { PseudoVMULH_VV_M1_MASK, VMULH_VV, 0x0, 0x0 }, // 6253 |
12245 | | { PseudoVMULH_VV_M2, VMULH_VV, 0x1, 0x0 }, // 6254 |
12246 | | { PseudoVMULH_VV_M2_MASK, VMULH_VV, 0x1, 0x0 }, // 6255 |
12247 | | { PseudoVMULH_VV_M4, VMULH_VV, 0x2, 0x0 }, // 6256 |
12248 | | { PseudoVMULH_VV_M4_MASK, VMULH_VV, 0x2, 0x0 }, // 6257 |
12249 | | { PseudoVMULH_VV_M8, VMULH_VV, 0x3, 0x0 }, // 6258 |
12250 | | { PseudoVMULH_VV_M8_MASK, VMULH_VV, 0x3, 0x0 }, // 6259 |
12251 | | { PseudoVMULH_VV_MF8, VMULH_VV, 0x5, 0x0 }, // 6260 |
12252 | | { PseudoVMULH_VV_MF8_MASK, VMULH_VV, 0x5, 0x0 }, // 6261 |
12253 | | { PseudoVMULH_VV_MF4, VMULH_VV, 0x6, 0x0 }, // 6262 |
12254 | | { PseudoVMULH_VV_MF4_MASK, VMULH_VV, 0x6, 0x0 }, // 6263 |
12255 | | { PseudoVMULH_VV_MF2, VMULH_VV, 0x7, 0x0 }, // 6264 |
12256 | | { PseudoVMULH_VV_MF2_MASK, VMULH_VV, 0x7, 0x0 }, // 6265 |
12257 | | { PseudoVMULH_VX_M1, VMULH_VX, 0x0, 0x0 }, // 6266 |
12258 | | { PseudoVMULH_VX_M1_MASK, VMULH_VX, 0x0, 0x0 }, // 6267 |
12259 | | { PseudoVMULH_VX_M2, VMULH_VX, 0x1, 0x0 }, // 6268 |
12260 | | { PseudoVMULH_VX_M2_MASK, VMULH_VX, 0x1, 0x0 }, // 6269 |
12261 | | { PseudoVMULH_VX_M4, VMULH_VX, 0x2, 0x0 }, // 6270 |
12262 | | { PseudoVMULH_VX_M4_MASK, VMULH_VX, 0x2, 0x0 }, // 6271 |
12263 | | { PseudoVMULH_VX_M8, VMULH_VX, 0x3, 0x0 }, // 6272 |
12264 | | { PseudoVMULH_VX_M8_MASK, VMULH_VX, 0x3, 0x0 }, // 6273 |
12265 | | { PseudoVMULH_VX_MF8, VMULH_VX, 0x5, 0x0 }, // 6274 |
12266 | | { PseudoVMULH_VX_MF8_MASK, VMULH_VX, 0x5, 0x0 }, // 6275 |
12267 | | { PseudoVMULH_VX_MF4, VMULH_VX, 0x6, 0x0 }, // 6276 |
12268 | | { PseudoVMULH_VX_MF4_MASK, VMULH_VX, 0x6, 0x0 }, // 6277 |
12269 | | { PseudoVMULH_VX_MF2, VMULH_VX, 0x7, 0x0 }, // 6278 |
12270 | | { PseudoVMULH_VX_MF2_MASK, VMULH_VX, 0x7, 0x0 }, // 6279 |
12271 | | { PseudoVMUL_VV_M1, VMUL_VV, 0x0, 0x0 }, // 6280 |
12272 | | { PseudoVMUL_VV_M1_MASK, VMUL_VV, 0x0, 0x0 }, // 6281 |
12273 | | { PseudoVMUL_VV_M2, VMUL_VV, 0x1, 0x0 }, // 6282 |
12274 | | { PseudoVMUL_VV_M2_MASK, VMUL_VV, 0x1, 0x0 }, // 6283 |
12275 | | { PseudoVMUL_VV_M4, VMUL_VV, 0x2, 0x0 }, // 6284 |
12276 | | { PseudoVMUL_VV_M4_MASK, VMUL_VV, 0x2, 0x0 }, // 6285 |
12277 | | { PseudoVMUL_VV_M8, VMUL_VV, 0x3, 0x0 }, // 6286 |
12278 | | { PseudoVMUL_VV_M8_MASK, VMUL_VV, 0x3, 0x0 }, // 6287 |
12279 | | { PseudoVMUL_VV_MF8, VMUL_VV, 0x5, 0x0 }, // 6288 |
12280 | | { PseudoVMUL_VV_MF8_MASK, VMUL_VV, 0x5, 0x0 }, // 6289 |
12281 | | { PseudoVMUL_VV_MF4, VMUL_VV, 0x6, 0x0 }, // 6290 |
12282 | | { PseudoVMUL_VV_MF4_MASK, VMUL_VV, 0x6, 0x0 }, // 6291 |
12283 | | { PseudoVMUL_VV_MF2, VMUL_VV, 0x7, 0x0 }, // 6292 |
12284 | | { PseudoVMUL_VV_MF2_MASK, VMUL_VV, 0x7, 0x0 }, // 6293 |
12285 | | { PseudoVMUL_VX_M1, VMUL_VX, 0x0, 0x0 }, // 6294 |
12286 | | { PseudoVMUL_VX_M1_MASK, VMUL_VX, 0x0, 0x0 }, // 6295 |
12287 | | { PseudoVMUL_VX_M2, VMUL_VX, 0x1, 0x0 }, // 6296 |
12288 | | { PseudoVMUL_VX_M2_MASK, VMUL_VX, 0x1, 0x0 }, // 6297 |
12289 | | { PseudoVMUL_VX_M4, VMUL_VX, 0x2, 0x0 }, // 6298 |
12290 | | { PseudoVMUL_VX_M4_MASK, VMUL_VX, 0x2, 0x0 }, // 6299 |
12291 | | { PseudoVMUL_VX_M8, VMUL_VX, 0x3, 0x0 }, // 6300 |
12292 | | { PseudoVMUL_VX_M8_MASK, VMUL_VX, 0x3, 0x0 }, // 6301 |
12293 | | { PseudoVMUL_VX_MF8, VMUL_VX, 0x5, 0x0 }, // 6302 |
12294 | | { PseudoVMUL_VX_MF8_MASK, VMUL_VX, 0x5, 0x0 }, // 6303 |
12295 | | { PseudoVMUL_VX_MF4, VMUL_VX, 0x6, 0x0 }, // 6304 |
12296 | | { PseudoVMUL_VX_MF4_MASK, VMUL_VX, 0x6, 0x0 }, // 6305 |
12297 | | { PseudoVMUL_VX_MF2, VMUL_VX, 0x7, 0x0 }, // 6306 |
12298 | | { PseudoVMUL_VX_MF2_MASK, VMUL_VX, 0x7, 0x0 }, // 6307 |
12299 | | { PseudoVMV_S_X, VMV_S_X, 0x0, 0x0 }, // 6308 |
12300 | | { PseudoVMV_V_I_M1, VMV_V_I, 0x0, 0x0 }, // 6309 |
12301 | | { PseudoVMV_V_I_M2, VMV_V_I, 0x1, 0x0 }, // 6310 |
12302 | | { PseudoVMV_V_I_M4, VMV_V_I, 0x2, 0x0 }, // 6311 |
12303 | | { PseudoVMV_V_I_M8, VMV_V_I, 0x3, 0x0 }, // 6312 |
12304 | | { PseudoVMV_V_I_MF8, VMV_V_I, 0x5, 0x0 }, // 6313 |
12305 | | { PseudoVMV_V_I_MF4, VMV_V_I, 0x6, 0x0 }, // 6314 |
12306 | | { PseudoVMV_V_I_MF2, VMV_V_I, 0x7, 0x0 }, // 6315 |
12307 | | { PseudoVMV_V_V_M1, VMV_V_V, 0x0, 0x0 }, // 6316 |
12308 | | { PseudoVMV_V_V_M2, VMV_V_V, 0x1, 0x0 }, // 6317 |
12309 | | { PseudoVMV_V_V_M4, VMV_V_V, 0x2, 0x0 }, // 6318 |
12310 | | { PseudoVMV_V_V_M8, VMV_V_V, 0x3, 0x0 }, // 6319 |
12311 | | { PseudoVMV_V_V_MF8, VMV_V_V, 0x5, 0x0 }, // 6320 |
12312 | | { PseudoVMV_V_V_MF4, VMV_V_V, 0x6, 0x0 }, // 6321 |
12313 | | { PseudoVMV_V_V_MF2, VMV_V_V, 0x7, 0x0 }, // 6322 |
12314 | | { PseudoVMV_V_X_M1, VMV_V_X, 0x0, 0x0 }, // 6323 |
12315 | | { PseudoVMV_V_X_M2, VMV_V_X, 0x1, 0x0 }, // 6324 |
12316 | | { PseudoVMV_V_X_M4, VMV_V_X, 0x2, 0x0 }, // 6325 |
12317 | | { PseudoVMV_V_X_M8, VMV_V_X, 0x3, 0x0 }, // 6326 |
12318 | | { PseudoVMV_V_X_MF8, VMV_V_X, 0x5, 0x0 }, // 6327 |
12319 | | { PseudoVMV_V_X_MF4, VMV_V_X, 0x6, 0x0 }, // 6328 |
12320 | | { PseudoVMV_V_X_MF2, VMV_V_X, 0x7, 0x0 }, // 6329 |
12321 | | { PseudoVMV_X_S, VMV_X_S, 0x0, 0x0 }, // 6330 |
12322 | | { PseudoVMSET_M_B8, VMXNOR_MM, 0x0, 0x0 }, // 6331 |
12323 | | { PseudoVMXNOR_MM_M1, VMXNOR_MM, 0x0, 0x0 }, // 6332 |
12324 | | { PseudoVMSET_M_B16, VMXNOR_MM, 0x1, 0x0 }, // 6333 |
12325 | | { PseudoVMXNOR_MM_M2, VMXNOR_MM, 0x1, 0x0 }, // 6334 |
12326 | | { PseudoVMSET_M_B32, VMXNOR_MM, 0x2, 0x0 }, // 6335 |
12327 | | { PseudoVMXNOR_MM_M4, VMXNOR_MM, 0x2, 0x0 }, // 6336 |
12328 | | { PseudoVMSET_M_B64, VMXNOR_MM, 0x3, 0x0 }, // 6337 |
12329 | | { PseudoVMXNOR_MM_M8, VMXNOR_MM, 0x3, 0x0 }, // 6338 |
12330 | | { PseudoVMSET_M_B1, VMXNOR_MM, 0x5, 0x0 }, // 6339 |
12331 | | { PseudoVMXNOR_MM_MF8, VMXNOR_MM, 0x5, 0x0 }, // 6340 |
12332 | | { PseudoVMSET_M_B2, VMXNOR_MM, 0x6, 0x0 }, // 6341 |
12333 | | { PseudoVMXNOR_MM_MF4, VMXNOR_MM, 0x6, 0x0 }, // 6342 |
12334 | | { PseudoVMSET_M_B4, VMXNOR_MM, 0x7, 0x0 }, // 6343 |
12335 | | { PseudoVMXNOR_MM_MF2, VMXNOR_MM, 0x7, 0x0 }, // 6344 |
12336 | | { PseudoVMCLR_M_B8, VMXOR_MM, 0x0, 0x0 }, // 6345 |
12337 | | { PseudoVMXOR_MM_M1, VMXOR_MM, 0x0, 0x0 }, // 6346 |
12338 | | { PseudoVMCLR_M_B16, VMXOR_MM, 0x1, 0x0 }, // 6347 |
12339 | | { PseudoVMXOR_MM_M2, VMXOR_MM, 0x1, 0x0 }, // 6348 |
12340 | | { PseudoVMCLR_M_B32, VMXOR_MM, 0x2, 0x0 }, // 6349 |
12341 | | { PseudoVMXOR_MM_M4, VMXOR_MM, 0x2, 0x0 }, // 6350 |
12342 | | { PseudoVMCLR_M_B64, VMXOR_MM, 0x3, 0x0 }, // 6351 |
12343 | | { PseudoVMXOR_MM_M8, VMXOR_MM, 0x3, 0x0 }, // 6352 |
12344 | | { PseudoVMCLR_M_B1, VMXOR_MM, 0x5, 0x0 }, // 6353 |
12345 | | { PseudoVMXOR_MM_MF8, VMXOR_MM, 0x5, 0x0 }, // 6354 |
12346 | | { PseudoVMCLR_M_B2, VMXOR_MM, 0x6, 0x0 }, // 6355 |
12347 | | { PseudoVMXOR_MM_MF4, VMXOR_MM, 0x6, 0x0 }, // 6356 |
12348 | | { PseudoVMCLR_M_B4, VMXOR_MM, 0x7, 0x0 }, // 6357 |
12349 | | { PseudoVMXOR_MM_MF2, VMXOR_MM, 0x7, 0x0 }, // 6358 |
12350 | | { PseudoVNCLIPU_WI_M1, VNCLIPU_WI, 0x0, 0x0 }, // 6359 |
12351 | | { PseudoVNCLIPU_WI_M1_MASK, VNCLIPU_WI, 0x0, 0x0 }, // 6360 |
12352 | | { PseudoVNCLIPU_WI_M2, VNCLIPU_WI, 0x1, 0x0 }, // 6361 |
12353 | | { PseudoVNCLIPU_WI_M2_MASK, VNCLIPU_WI, 0x1, 0x0 }, // 6362 |
12354 | | { PseudoVNCLIPU_WI_M4, VNCLIPU_WI, 0x2, 0x0 }, // 6363 |
12355 | | { PseudoVNCLIPU_WI_M4_MASK, VNCLIPU_WI, 0x2, 0x0 }, // 6364 |
12356 | | { PseudoVNCLIPU_WI_MF8, VNCLIPU_WI, 0x5, 0x0 }, // 6365 |
12357 | | { PseudoVNCLIPU_WI_MF8_MASK, VNCLIPU_WI, 0x5, 0x0 }, // 6366 |
12358 | | { PseudoVNCLIPU_WI_MF4, VNCLIPU_WI, 0x6, 0x0 }, // 6367 |
12359 | | { PseudoVNCLIPU_WI_MF4_MASK, VNCLIPU_WI, 0x6, 0x0 }, // 6368 |
12360 | | { PseudoVNCLIPU_WI_MF2, VNCLIPU_WI, 0x7, 0x0 }, // 6369 |
12361 | | { PseudoVNCLIPU_WI_MF2_MASK, VNCLIPU_WI, 0x7, 0x0 }, // 6370 |
12362 | | { PseudoVNCLIPU_WV_M1, VNCLIPU_WV, 0x0, 0x0 }, // 6371 |
12363 | | { PseudoVNCLIPU_WV_M1_MASK, VNCLIPU_WV, 0x0, 0x0 }, // 6372 |
12364 | | { PseudoVNCLIPU_WV_M2, VNCLIPU_WV, 0x1, 0x0 }, // 6373 |
12365 | | { PseudoVNCLIPU_WV_M2_MASK, VNCLIPU_WV, 0x1, 0x0 }, // 6374 |
12366 | | { PseudoVNCLIPU_WV_M4, VNCLIPU_WV, 0x2, 0x0 }, // 6375 |
12367 | | { PseudoVNCLIPU_WV_M4_MASK, VNCLIPU_WV, 0x2, 0x0 }, // 6376 |
12368 | | { PseudoVNCLIPU_WV_MF8, VNCLIPU_WV, 0x5, 0x0 }, // 6377 |
12369 | | { PseudoVNCLIPU_WV_MF8_MASK, VNCLIPU_WV, 0x5, 0x0 }, // 6378 |
12370 | | { PseudoVNCLIPU_WV_MF4, VNCLIPU_WV, 0x6, 0x0 }, // 6379 |
12371 | | { PseudoVNCLIPU_WV_MF4_MASK, VNCLIPU_WV, 0x6, 0x0 }, // 6380 |
12372 | | { PseudoVNCLIPU_WV_MF2, VNCLIPU_WV, 0x7, 0x0 }, // 6381 |
12373 | | { PseudoVNCLIPU_WV_MF2_MASK, VNCLIPU_WV, 0x7, 0x0 }, // 6382 |
12374 | | { PseudoVNCLIPU_WX_M1, VNCLIPU_WX, 0x0, 0x0 }, // 6383 |
12375 | | { PseudoVNCLIPU_WX_M1_MASK, VNCLIPU_WX, 0x0, 0x0 }, // 6384 |
12376 | | { PseudoVNCLIPU_WX_M2, VNCLIPU_WX, 0x1, 0x0 }, // 6385 |
12377 | | { PseudoVNCLIPU_WX_M2_MASK, VNCLIPU_WX, 0x1, 0x0 }, // 6386 |
12378 | | { PseudoVNCLIPU_WX_M4, VNCLIPU_WX, 0x2, 0x0 }, // 6387 |
12379 | | { PseudoVNCLIPU_WX_M4_MASK, VNCLIPU_WX, 0x2, 0x0 }, // 6388 |
12380 | | { PseudoVNCLIPU_WX_MF8, VNCLIPU_WX, 0x5, 0x0 }, // 6389 |
12381 | | { PseudoVNCLIPU_WX_MF8_MASK, VNCLIPU_WX, 0x5, 0x0 }, // 6390 |
12382 | | { PseudoVNCLIPU_WX_MF4, VNCLIPU_WX, 0x6, 0x0 }, // 6391 |
12383 | | { PseudoVNCLIPU_WX_MF4_MASK, VNCLIPU_WX, 0x6, 0x0 }, // 6392 |
12384 | | { PseudoVNCLIPU_WX_MF2, VNCLIPU_WX, 0x7, 0x0 }, // 6393 |
12385 | | { PseudoVNCLIPU_WX_MF2_MASK, VNCLIPU_WX, 0x7, 0x0 }, // 6394 |
12386 | | { PseudoVNCLIP_WI_M1, VNCLIP_WI, 0x0, 0x0 }, // 6395 |
12387 | | { PseudoVNCLIP_WI_M1_MASK, VNCLIP_WI, 0x0, 0x0 }, // 6396 |
12388 | | { PseudoVNCLIP_WI_M2, VNCLIP_WI, 0x1, 0x0 }, // 6397 |
12389 | | { PseudoVNCLIP_WI_M2_MASK, VNCLIP_WI, 0x1, 0x0 }, // 6398 |
12390 | | { PseudoVNCLIP_WI_M4, VNCLIP_WI, 0x2, 0x0 }, // 6399 |
12391 | | { PseudoVNCLIP_WI_M4_MASK, VNCLIP_WI, 0x2, 0x0 }, // 6400 |
12392 | | { PseudoVNCLIP_WI_MF8, VNCLIP_WI, 0x5, 0x0 }, // 6401 |
12393 | | { PseudoVNCLIP_WI_MF8_MASK, VNCLIP_WI, 0x5, 0x0 }, // 6402 |
12394 | | { PseudoVNCLIP_WI_MF4, VNCLIP_WI, 0x6, 0x0 }, // 6403 |
12395 | | { PseudoVNCLIP_WI_MF4_MASK, VNCLIP_WI, 0x6, 0x0 }, // 6404 |
12396 | | { PseudoVNCLIP_WI_MF2, VNCLIP_WI, 0x7, 0x0 }, // 6405 |
12397 | | { PseudoVNCLIP_WI_MF2_MASK, VNCLIP_WI, 0x7, 0x0 }, // 6406 |
12398 | | { PseudoVNCLIP_WV_M1, VNCLIP_WV, 0x0, 0x0 }, // 6407 |
12399 | | { PseudoVNCLIP_WV_M1_MASK, VNCLIP_WV, 0x0, 0x0 }, // 6408 |
12400 | | { PseudoVNCLIP_WV_M2, VNCLIP_WV, 0x1, 0x0 }, // 6409 |
12401 | | { PseudoVNCLIP_WV_M2_MASK, VNCLIP_WV, 0x1, 0x0 }, // 6410 |
12402 | | { PseudoVNCLIP_WV_M4, VNCLIP_WV, 0x2, 0x0 }, // 6411 |
12403 | | { PseudoVNCLIP_WV_M4_MASK, VNCLIP_WV, 0x2, 0x0 }, // 6412 |
12404 | | { PseudoVNCLIP_WV_MF8, VNCLIP_WV, 0x5, 0x0 }, // 6413 |
12405 | | { PseudoVNCLIP_WV_MF8_MASK, VNCLIP_WV, 0x5, 0x0 }, // 6414 |
12406 | | { PseudoVNCLIP_WV_MF4, VNCLIP_WV, 0x6, 0x0 }, // 6415 |
12407 | | { PseudoVNCLIP_WV_MF4_MASK, VNCLIP_WV, 0x6, 0x0 }, // 6416 |
12408 | | { PseudoVNCLIP_WV_MF2, VNCLIP_WV, 0x7, 0x0 }, // 6417 |
12409 | | { PseudoVNCLIP_WV_MF2_MASK, VNCLIP_WV, 0x7, 0x0 }, // 6418 |
12410 | | { PseudoVNCLIP_WX_M1, VNCLIP_WX, 0x0, 0x0 }, // 6419 |
12411 | | { PseudoVNCLIP_WX_M1_MASK, VNCLIP_WX, 0x0, 0x0 }, // 6420 |
12412 | | { PseudoVNCLIP_WX_M2, VNCLIP_WX, 0x1, 0x0 }, // 6421 |
12413 | | { PseudoVNCLIP_WX_M2_MASK, VNCLIP_WX, 0x1, 0x0 }, // 6422 |
12414 | | { PseudoVNCLIP_WX_M4, VNCLIP_WX, 0x2, 0x0 }, // 6423 |
12415 | | { PseudoVNCLIP_WX_M4_MASK, VNCLIP_WX, 0x2, 0x0 }, // 6424 |
12416 | | { PseudoVNCLIP_WX_MF8, VNCLIP_WX, 0x5, 0x0 }, // 6425 |
12417 | | { PseudoVNCLIP_WX_MF8_MASK, VNCLIP_WX, 0x5, 0x0 }, // 6426 |
12418 | | { PseudoVNCLIP_WX_MF4, VNCLIP_WX, 0x6, 0x0 }, // 6427 |
12419 | | { PseudoVNCLIP_WX_MF4_MASK, VNCLIP_WX, 0x6, 0x0 }, // 6428 |
12420 | | { PseudoVNCLIP_WX_MF2, VNCLIP_WX, 0x7, 0x0 }, // 6429 |
12421 | | { PseudoVNCLIP_WX_MF2_MASK, VNCLIP_WX, 0x7, 0x0 }, // 6430 |
12422 | | { PseudoVNMSAC_VV_M1, VNMSAC_VV, 0x0, 0x0 }, // 6431 |
12423 | | { PseudoVNMSAC_VV_M1_MASK, VNMSAC_VV, 0x0, 0x0 }, // 6432 |
12424 | | { PseudoVNMSAC_VV_M2, VNMSAC_VV, 0x1, 0x0 }, // 6433 |
12425 | | { PseudoVNMSAC_VV_M2_MASK, VNMSAC_VV, 0x1, 0x0 }, // 6434 |
12426 | | { PseudoVNMSAC_VV_M4, VNMSAC_VV, 0x2, 0x0 }, // 6435 |
12427 | | { PseudoVNMSAC_VV_M4_MASK, VNMSAC_VV, 0x2, 0x0 }, // 6436 |
12428 | | { PseudoVNMSAC_VV_M8, VNMSAC_VV, 0x3, 0x0 }, // 6437 |
12429 | | { PseudoVNMSAC_VV_M8_MASK, VNMSAC_VV, 0x3, 0x0 }, // 6438 |
12430 | | { PseudoVNMSAC_VV_MF8, VNMSAC_VV, 0x5, 0x0 }, // 6439 |
12431 | | { PseudoVNMSAC_VV_MF8_MASK, VNMSAC_VV, 0x5, 0x0 }, // 6440 |
12432 | | { PseudoVNMSAC_VV_MF4, VNMSAC_VV, 0x6, 0x0 }, // 6441 |
12433 | | { PseudoVNMSAC_VV_MF4_MASK, VNMSAC_VV, 0x6, 0x0 }, // 6442 |
12434 | | { PseudoVNMSAC_VV_MF2, VNMSAC_VV, 0x7, 0x0 }, // 6443 |
12435 | | { PseudoVNMSAC_VV_MF2_MASK, VNMSAC_VV, 0x7, 0x0 }, // 6444 |
12436 | | { PseudoVNMSAC_VX_M1, VNMSAC_VX, 0x0, 0x0 }, // 6445 |
12437 | | { PseudoVNMSAC_VX_M1_MASK, VNMSAC_VX, 0x0, 0x0 }, // 6446 |
12438 | | { PseudoVNMSAC_VX_M2, VNMSAC_VX, 0x1, 0x0 }, // 6447 |
12439 | | { PseudoVNMSAC_VX_M2_MASK, VNMSAC_VX, 0x1, 0x0 }, // 6448 |
12440 | | { PseudoVNMSAC_VX_M4, VNMSAC_VX, 0x2, 0x0 }, // 6449 |
12441 | | { PseudoVNMSAC_VX_M4_MASK, VNMSAC_VX, 0x2, 0x0 }, // 6450 |
12442 | | { PseudoVNMSAC_VX_M8, VNMSAC_VX, 0x3, 0x0 }, // 6451 |
12443 | | { PseudoVNMSAC_VX_M8_MASK, VNMSAC_VX, 0x3, 0x0 }, // 6452 |
12444 | | { PseudoVNMSAC_VX_MF8, VNMSAC_VX, 0x5, 0x0 }, // 6453 |
12445 | | { PseudoVNMSAC_VX_MF8_MASK, VNMSAC_VX, 0x5, 0x0 }, // 6454 |
12446 | | { PseudoVNMSAC_VX_MF4, VNMSAC_VX, 0x6, 0x0 }, // 6455 |
12447 | | { PseudoVNMSAC_VX_MF4_MASK, VNMSAC_VX, 0x6, 0x0 }, // 6456 |
12448 | | { PseudoVNMSAC_VX_MF2, VNMSAC_VX, 0x7, 0x0 }, // 6457 |
12449 | | { PseudoVNMSAC_VX_MF2_MASK, VNMSAC_VX, 0x7, 0x0 }, // 6458 |
12450 | | { PseudoVNMSUB_VV_M1, VNMSUB_VV, 0x0, 0x0 }, // 6459 |
12451 | | { PseudoVNMSUB_VV_M1_MASK, VNMSUB_VV, 0x0, 0x0 }, // 6460 |
12452 | | { PseudoVNMSUB_VV_M2, VNMSUB_VV, 0x1, 0x0 }, // 6461 |
12453 | | { PseudoVNMSUB_VV_M2_MASK, VNMSUB_VV, 0x1, 0x0 }, // 6462 |
12454 | | { PseudoVNMSUB_VV_M4, VNMSUB_VV, 0x2, 0x0 }, // 6463 |
12455 | | { PseudoVNMSUB_VV_M4_MASK, VNMSUB_VV, 0x2, 0x0 }, // 6464 |
12456 | | { PseudoVNMSUB_VV_M8, VNMSUB_VV, 0x3, 0x0 }, // 6465 |
12457 | | { PseudoVNMSUB_VV_M8_MASK, VNMSUB_VV, 0x3, 0x0 }, // 6466 |
12458 | | { PseudoVNMSUB_VV_MF8, VNMSUB_VV, 0x5, 0x0 }, // 6467 |
12459 | | { PseudoVNMSUB_VV_MF8_MASK, VNMSUB_VV, 0x5, 0x0 }, // 6468 |
12460 | | { PseudoVNMSUB_VV_MF4, VNMSUB_VV, 0x6, 0x0 }, // 6469 |
12461 | | { PseudoVNMSUB_VV_MF4_MASK, VNMSUB_VV, 0x6, 0x0 }, // 6470 |
12462 | | { PseudoVNMSUB_VV_MF2, VNMSUB_VV, 0x7, 0x0 }, // 6471 |
12463 | | { PseudoVNMSUB_VV_MF2_MASK, VNMSUB_VV, 0x7, 0x0 }, // 6472 |
12464 | | { PseudoVNMSUB_VX_M1, VNMSUB_VX, 0x0, 0x0 }, // 6473 |
12465 | | { PseudoVNMSUB_VX_M1_MASK, VNMSUB_VX, 0x0, 0x0 }, // 6474 |
12466 | | { PseudoVNMSUB_VX_M2, VNMSUB_VX, 0x1, 0x0 }, // 6475 |
12467 | | { PseudoVNMSUB_VX_M2_MASK, VNMSUB_VX, 0x1, 0x0 }, // 6476 |
12468 | | { PseudoVNMSUB_VX_M4, VNMSUB_VX, 0x2, 0x0 }, // 6477 |
12469 | | { PseudoVNMSUB_VX_M4_MASK, VNMSUB_VX, 0x2, 0x0 }, // 6478 |
12470 | | { PseudoVNMSUB_VX_M8, VNMSUB_VX, 0x3, 0x0 }, // 6479 |
12471 | | { PseudoVNMSUB_VX_M8_MASK, VNMSUB_VX, 0x3, 0x0 }, // 6480 |
12472 | | { PseudoVNMSUB_VX_MF8, VNMSUB_VX, 0x5, 0x0 }, // 6481 |
12473 | | { PseudoVNMSUB_VX_MF8_MASK, VNMSUB_VX, 0x5, 0x0 }, // 6482 |
12474 | | { PseudoVNMSUB_VX_MF4, VNMSUB_VX, 0x6, 0x0 }, // 6483 |
12475 | | { PseudoVNMSUB_VX_MF4_MASK, VNMSUB_VX, 0x6, 0x0 }, // 6484 |
12476 | | { PseudoVNMSUB_VX_MF2, VNMSUB_VX, 0x7, 0x0 }, // 6485 |
12477 | | { PseudoVNMSUB_VX_MF2_MASK, VNMSUB_VX, 0x7, 0x0 }, // 6486 |
12478 | | { PseudoVNSRA_WI_M1, VNSRA_WI, 0x0, 0x0 }, // 6487 |
12479 | | { PseudoVNSRA_WI_M1_MASK, VNSRA_WI, 0x0, 0x0 }, // 6488 |
12480 | | { PseudoVNSRA_WI_M2, VNSRA_WI, 0x1, 0x0 }, // 6489 |
12481 | | { PseudoVNSRA_WI_M2_MASK, VNSRA_WI, 0x1, 0x0 }, // 6490 |
12482 | | { PseudoVNSRA_WI_M4, VNSRA_WI, 0x2, 0x0 }, // 6491 |
12483 | | { PseudoVNSRA_WI_M4_MASK, VNSRA_WI, 0x2, 0x0 }, // 6492 |
12484 | | { PseudoVNSRA_WI_MF8, VNSRA_WI, 0x5, 0x0 }, // 6493 |
12485 | | { PseudoVNSRA_WI_MF8_MASK, VNSRA_WI, 0x5, 0x0 }, // 6494 |
12486 | | { PseudoVNSRA_WI_MF4, VNSRA_WI, 0x6, 0x0 }, // 6495 |
12487 | | { PseudoVNSRA_WI_MF4_MASK, VNSRA_WI, 0x6, 0x0 }, // 6496 |
12488 | | { PseudoVNSRA_WI_MF2, VNSRA_WI, 0x7, 0x0 }, // 6497 |
12489 | | { PseudoVNSRA_WI_MF2_MASK, VNSRA_WI, 0x7, 0x0 }, // 6498 |
12490 | | { PseudoVNSRA_WV_M1, VNSRA_WV, 0x0, 0x0 }, // 6499 |
12491 | | { PseudoVNSRA_WV_M1_MASK, VNSRA_WV, 0x0, 0x0 }, // 6500 |
12492 | | { PseudoVNSRA_WV_M2, VNSRA_WV, 0x1, 0x0 }, // 6501 |
12493 | | { PseudoVNSRA_WV_M2_MASK, VNSRA_WV, 0x1, 0x0 }, // 6502 |
12494 | | { PseudoVNSRA_WV_M4, VNSRA_WV, 0x2, 0x0 }, // 6503 |
12495 | | { PseudoVNSRA_WV_M4_MASK, VNSRA_WV, 0x2, 0x0 }, // 6504 |
12496 | | { PseudoVNSRA_WV_MF8, VNSRA_WV, 0x5, 0x0 }, // 6505 |
12497 | | { PseudoVNSRA_WV_MF8_MASK, VNSRA_WV, 0x5, 0x0 }, // 6506 |
12498 | | { PseudoVNSRA_WV_MF4, VNSRA_WV, 0x6, 0x0 }, // 6507 |
12499 | | { PseudoVNSRA_WV_MF4_MASK, VNSRA_WV, 0x6, 0x0 }, // 6508 |
12500 | | { PseudoVNSRA_WV_MF2, VNSRA_WV, 0x7, 0x0 }, // 6509 |
12501 | | { PseudoVNSRA_WV_MF2_MASK, VNSRA_WV, 0x7, 0x0 }, // 6510 |
12502 | | { PseudoVNSRA_WX_M1, VNSRA_WX, 0x0, 0x0 }, // 6511 |
12503 | | { PseudoVNSRA_WX_M1_MASK, VNSRA_WX, 0x0, 0x0 }, // 6512 |
12504 | | { PseudoVNSRA_WX_M2, VNSRA_WX, 0x1, 0x0 }, // 6513 |
12505 | | { PseudoVNSRA_WX_M2_MASK, VNSRA_WX, 0x1, 0x0 }, // 6514 |
12506 | | { PseudoVNSRA_WX_M4, VNSRA_WX, 0x2, 0x0 }, // 6515 |
12507 | | { PseudoVNSRA_WX_M4_MASK, VNSRA_WX, 0x2, 0x0 }, // 6516 |
12508 | | { PseudoVNSRA_WX_MF8, VNSRA_WX, 0x5, 0x0 }, // 6517 |
12509 | | { PseudoVNSRA_WX_MF8_MASK, VNSRA_WX, 0x5, 0x0 }, // 6518 |
12510 | | { PseudoVNSRA_WX_MF4, VNSRA_WX, 0x6, 0x0 }, // 6519 |
12511 | | { PseudoVNSRA_WX_MF4_MASK, VNSRA_WX, 0x6, 0x0 }, // 6520 |
12512 | | { PseudoVNSRA_WX_MF2, VNSRA_WX, 0x7, 0x0 }, // 6521 |
12513 | | { PseudoVNSRA_WX_MF2_MASK, VNSRA_WX, 0x7, 0x0 }, // 6522 |
12514 | | { PseudoVNSRL_WI_M1, VNSRL_WI, 0x0, 0x0 }, // 6523 |
12515 | | { PseudoVNSRL_WI_M1_MASK, VNSRL_WI, 0x0, 0x0 }, // 6524 |
12516 | | { PseudoVNSRL_WI_M2, VNSRL_WI, 0x1, 0x0 }, // 6525 |
12517 | | { PseudoVNSRL_WI_M2_MASK, VNSRL_WI, 0x1, 0x0 }, // 6526 |
12518 | | { PseudoVNSRL_WI_M4, VNSRL_WI, 0x2, 0x0 }, // 6527 |
12519 | | { PseudoVNSRL_WI_M4_MASK, VNSRL_WI, 0x2, 0x0 }, // 6528 |
12520 | | { PseudoVNSRL_WI_MF8, VNSRL_WI, 0x5, 0x0 }, // 6529 |
12521 | | { PseudoVNSRL_WI_MF8_MASK, VNSRL_WI, 0x5, 0x0 }, // 6530 |
12522 | | { PseudoVNSRL_WI_MF4, VNSRL_WI, 0x6, 0x0 }, // 6531 |
12523 | | { PseudoVNSRL_WI_MF4_MASK, VNSRL_WI, 0x6, 0x0 }, // 6532 |
12524 | | { PseudoVNSRL_WI_MF2, VNSRL_WI, 0x7, 0x0 }, // 6533 |
12525 | | { PseudoVNSRL_WI_MF2_MASK, VNSRL_WI, 0x7, 0x0 }, // 6534 |
12526 | | { PseudoVNSRL_WV_M1, VNSRL_WV, 0x0, 0x0 }, // 6535 |
12527 | | { PseudoVNSRL_WV_M1_MASK, VNSRL_WV, 0x0, 0x0 }, // 6536 |
12528 | | { PseudoVNSRL_WV_M2, VNSRL_WV, 0x1, 0x0 }, // 6537 |
12529 | | { PseudoVNSRL_WV_M2_MASK, VNSRL_WV, 0x1, 0x0 }, // 6538 |
12530 | | { PseudoVNSRL_WV_M4, VNSRL_WV, 0x2, 0x0 }, // 6539 |
12531 | | { PseudoVNSRL_WV_M4_MASK, VNSRL_WV, 0x2, 0x0 }, // 6540 |
12532 | | { PseudoVNSRL_WV_MF8, VNSRL_WV, 0x5, 0x0 }, // 6541 |
12533 | | { PseudoVNSRL_WV_MF8_MASK, VNSRL_WV, 0x5, 0x0 }, // 6542 |
12534 | | { PseudoVNSRL_WV_MF4, VNSRL_WV, 0x6, 0x0 }, // 6543 |
12535 | | { PseudoVNSRL_WV_MF4_MASK, VNSRL_WV, 0x6, 0x0 }, // 6544 |
12536 | | { PseudoVNSRL_WV_MF2, VNSRL_WV, 0x7, 0x0 }, // 6545 |
12537 | | { PseudoVNSRL_WV_MF2_MASK, VNSRL_WV, 0x7, 0x0 }, // 6546 |
12538 | | { PseudoVNSRL_WX_M1, VNSRL_WX, 0x0, 0x0 }, // 6547 |
12539 | | { PseudoVNSRL_WX_M1_MASK, VNSRL_WX, 0x0, 0x0 }, // 6548 |
12540 | | { PseudoVNSRL_WX_M2, VNSRL_WX, 0x1, 0x0 }, // 6549 |
12541 | | { PseudoVNSRL_WX_M2_MASK, VNSRL_WX, 0x1, 0x0 }, // 6550 |
12542 | | { PseudoVNSRL_WX_M4, VNSRL_WX, 0x2, 0x0 }, // 6551 |
12543 | | { PseudoVNSRL_WX_M4_MASK, VNSRL_WX, 0x2, 0x0 }, // 6552 |
12544 | | { PseudoVNSRL_WX_MF8, VNSRL_WX, 0x5, 0x0 }, // 6553 |
12545 | | { PseudoVNSRL_WX_MF8_MASK, VNSRL_WX, 0x5, 0x0 }, // 6554 |
12546 | | { PseudoVNSRL_WX_MF4, VNSRL_WX, 0x6, 0x0 }, // 6555 |
12547 | | { PseudoVNSRL_WX_MF4_MASK, VNSRL_WX, 0x6, 0x0 }, // 6556 |
12548 | | { PseudoVNSRL_WX_MF2, VNSRL_WX, 0x7, 0x0 }, // 6557 |
12549 | | { PseudoVNSRL_WX_MF2_MASK, VNSRL_WX, 0x7, 0x0 }, // 6558 |
12550 | | { PseudoVOR_VI_M1, VOR_VI, 0x0, 0x0 }, // 6559 |
12551 | | { PseudoVOR_VI_M1_MASK, VOR_VI, 0x0, 0x0 }, // 6560 |
12552 | | { PseudoVOR_VI_M2, VOR_VI, 0x1, 0x0 }, // 6561 |
12553 | | { PseudoVOR_VI_M2_MASK, VOR_VI, 0x1, 0x0 }, // 6562 |
12554 | | { PseudoVOR_VI_M4, VOR_VI, 0x2, 0x0 }, // 6563 |
12555 | | { PseudoVOR_VI_M4_MASK, VOR_VI, 0x2, 0x0 }, // 6564 |
12556 | | { PseudoVOR_VI_M8, VOR_VI, 0x3, 0x0 }, // 6565 |
12557 | | { PseudoVOR_VI_M8_MASK, VOR_VI, 0x3, 0x0 }, // 6566 |
12558 | | { PseudoVOR_VI_MF8, VOR_VI, 0x5, 0x0 }, // 6567 |
12559 | | { PseudoVOR_VI_MF8_MASK, VOR_VI, 0x5, 0x0 }, // 6568 |
12560 | | { PseudoVOR_VI_MF4, VOR_VI, 0x6, 0x0 }, // 6569 |
12561 | | { PseudoVOR_VI_MF4_MASK, VOR_VI, 0x6, 0x0 }, // 6570 |
12562 | | { PseudoVOR_VI_MF2, VOR_VI, 0x7, 0x0 }, // 6571 |
12563 | | { PseudoVOR_VI_MF2_MASK, VOR_VI, 0x7, 0x0 }, // 6572 |
12564 | | { PseudoVOR_VV_M1, VOR_VV, 0x0, 0x0 }, // 6573 |
12565 | | { PseudoVOR_VV_M1_MASK, VOR_VV, 0x0, 0x0 }, // 6574 |
12566 | | { PseudoVOR_VV_M2, VOR_VV, 0x1, 0x0 }, // 6575 |
12567 | | { PseudoVOR_VV_M2_MASK, VOR_VV, 0x1, 0x0 }, // 6576 |
12568 | | { PseudoVOR_VV_M4, VOR_VV, 0x2, 0x0 }, // 6577 |
12569 | | { PseudoVOR_VV_M4_MASK, VOR_VV, 0x2, 0x0 }, // 6578 |
12570 | | { PseudoVOR_VV_M8, VOR_VV, 0x3, 0x0 }, // 6579 |
12571 | | { PseudoVOR_VV_M8_MASK, VOR_VV, 0x3, 0x0 }, // 6580 |
12572 | | { PseudoVOR_VV_MF8, VOR_VV, 0x5, 0x0 }, // 6581 |
12573 | | { PseudoVOR_VV_MF8_MASK, VOR_VV, 0x5, 0x0 }, // 6582 |
12574 | | { PseudoVOR_VV_MF4, VOR_VV, 0x6, 0x0 }, // 6583 |
12575 | | { PseudoVOR_VV_MF4_MASK, VOR_VV, 0x6, 0x0 }, // 6584 |
12576 | | { PseudoVOR_VV_MF2, VOR_VV, 0x7, 0x0 }, // 6585 |
12577 | | { PseudoVOR_VV_MF2_MASK, VOR_VV, 0x7, 0x0 }, // 6586 |
12578 | | { PseudoVOR_VX_M1, VOR_VX, 0x0, 0x0 }, // 6587 |
12579 | | { PseudoVOR_VX_M1_MASK, VOR_VX, 0x0, 0x0 }, // 6588 |
12580 | | { PseudoVOR_VX_M2, VOR_VX, 0x1, 0x0 }, // 6589 |
12581 | | { PseudoVOR_VX_M2_MASK, VOR_VX, 0x1, 0x0 }, // 6590 |
12582 | | { PseudoVOR_VX_M4, VOR_VX, 0x2, 0x0 }, // 6591 |
12583 | | { PseudoVOR_VX_M4_MASK, VOR_VX, 0x2, 0x0 }, // 6592 |
12584 | | { PseudoVOR_VX_M8, VOR_VX, 0x3, 0x0 }, // 6593 |
12585 | | { PseudoVOR_VX_M8_MASK, VOR_VX, 0x3, 0x0 }, // 6594 |
12586 | | { PseudoVOR_VX_MF8, VOR_VX, 0x5, 0x0 }, // 6595 |
12587 | | { PseudoVOR_VX_MF8_MASK, VOR_VX, 0x5, 0x0 }, // 6596 |
12588 | | { PseudoVOR_VX_MF4, VOR_VX, 0x6, 0x0 }, // 6597 |
12589 | | { PseudoVOR_VX_MF4_MASK, VOR_VX, 0x6, 0x0 }, // 6598 |
12590 | | { PseudoVOR_VX_MF2, VOR_VX, 0x7, 0x0 }, // 6599 |
12591 | | { PseudoVOR_VX_MF2_MASK, VOR_VX, 0x7, 0x0 }, // 6600 |
12592 | | { PseudoVQMACCSU_2x8x2_M1, VQMACCSU_2x8x2, 0x0, 0x0 }, // 6601 |
12593 | | { PseudoVQMACCSU_2x8x2_M2, VQMACCSU_2x8x2, 0x1, 0x0 }, // 6602 |
12594 | | { PseudoVQMACCSU_2x8x2_M4, VQMACCSU_2x8x2, 0x2, 0x0 }, // 6603 |
12595 | | { PseudoVQMACCSU_2x8x2_M8, VQMACCSU_2x8x2, 0x3, 0x0 }, // 6604 |
12596 | | { PseudoVQMACCSU_4x8x4_M1, VQMACCSU_4x8x4, 0x0, 0x0 }, // 6605 |
12597 | | { PseudoVQMACCSU_4x8x4_M2, VQMACCSU_4x8x4, 0x1, 0x0 }, // 6606 |
12598 | | { PseudoVQMACCSU_4x8x4_M4, VQMACCSU_4x8x4, 0x2, 0x0 }, // 6607 |
12599 | | { PseudoVQMACCSU_4x8x4_MF2, VQMACCSU_4x8x4, 0x7, 0x0 }, // 6608 |
12600 | | { PseudoVQMACCUS_2x8x2_M1, VQMACCUS_2x8x2, 0x0, 0x0 }, // 6609 |
12601 | | { PseudoVQMACCUS_2x8x2_M2, VQMACCUS_2x8x2, 0x1, 0x0 }, // 6610 |
12602 | | { PseudoVQMACCUS_2x8x2_M4, VQMACCUS_2x8x2, 0x2, 0x0 }, // 6611 |
12603 | | { PseudoVQMACCUS_2x8x2_M8, VQMACCUS_2x8x2, 0x3, 0x0 }, // 6612 |
12604 | | { PseudoVQMACCUS_4x8x4_M1, VQMACCUS_4x8x4, 0x0, 0x0 }, // 6613 |
12605 | | { PseudoVQMACCUS_4x8x4_M2, VQMACCUS_4x8x4, 0x1, 0x0 }, // 6614 |
12606 | | { PseudoVQMACCUS_4x8x4_M4, VQMACCUS_4x8x4, 0x2, 0x0 }, // 6615 |
12607 | | { PseudoVQMACCUS_4x8x4_MF2, VQMACCUS_4x8x4, 0x7, 0x0 }, // 6616 |
12608 | | { PseudoVQMACCU_2x8x2_M1, VQMACCU_2x8x2, 0x0, 0x0 }, // 6617 |
12609 | | { PseudoVQMACCU_2x8x2_M2, VQMACCU_2x8x2, 0x1, 0x0 }, // 6618 |
12610 | | { PseudoVQMACCU_2x8x2_M4, VQMACCU_2x8x2, 0x2, 0x0 }, // 6619 |
12611 | | { PseudoVQMACCU_2x8x2_M8, VQMACCU_2x8x2, 0x3, 0x0 }, // 6620 |
12612 | | { PseudoVQMACCU_4x8x4_M1, VQMACCU_4x8x4, 0x0, 0x0 }, // 6621 |
12613 | | { PseudoVQMACCU_4x8x4_M2, VQMACCU_4x8x4, 0x1, 0x0 }, // 6622 |
12614 | | { PseudoVQMACCU_4x8x4_M4, VQMACCU_4x8x4, 0x2, 0x0 }, // 6623 |
12615 | | { PseudoVQMACCU_4x8x4_MF2, VQMACCU_4x8x4, 0x7, 0x0 }, // 6624 |
12616 | | { PseudoVQMACC_2x8x2_M1, VQMACC_2x8x2, 0x0, 0x0 }, // 6625 |
12617 | | { PseudoVQMACC_2x8x2_M2, VQMACC_2x8x2, 0x1, 0x0 }, // 6626 |
12618 | | { PseudoVQMACC_2x8x2_M4, VQMACC_2x8x2, 0x2, 0x0 }, // 6627 |
12619 | | { PseudoVQMACC_2x8x2_M8, VQMACC_2x8x2, 0x3, 0x0 }, // 6628 |
12620 | | { PseudoVQMACC_4x8x4_M1, VQMACC_4x8x4, 0x0, 0x0 }, // 6629 |
12621 | | { PseudoVQMACC_4x8x4_M2, VQMACC_4x8x4, 0x1, 0x0 }, // 6630 |
12622 | | { PseudoVQMACC_4x8x4_M4, VQMACC_4x8x4, 0x2, 0x0 }, // 6631 |
12623 | | { PseudoVQMACC_4x8x4_MF2, VQMACC_4x8x4, 0x7, 0x0 }, // 6632 |
12624 | | { PseudoVREDAND_VS_M1_E8, VREDAND_VS, 0x0, 0x8 }, // 6633 |
12625 | | { PseudoVREDAND_VS_M1_E8_MASK, VREDAND_VS, 0x0, 0x8 }, // 6634 |
12626 | | { PseudoVREDAND_VS_M1_E16, VREDAND_VS, 0x0, 0x10 }, // 6635 |
12627 | | { PseudoVREDAND_VS_M1_E16_MASK, VREDAND_VS, 0x0, 0x10 }, // 6636 |
12628 | | { PseudoVREDAND_VS_M1_E32, VREDAND_VS, 0x0, 0x20 }, // 6637 |
12629 | | { PseudoVREDAND_VS_M1_E32_MASK, VREDAND_VS, 0x0, 0x20 }, // 6638 |
12630 | | { PseudoVREDAND_VS_M1_E64, VREDAND_VS, 0x0, 0x40 }, // 6639 |
12631 | | { PseudoVREDAND_VS_M1_E64_MASK, VREDAND_VS, 0x0, 0x40 }, // 6640 |
12632 | | { PseudoVREDAND_VS_M2_E8, VREDAND_VS, 0x1, 0x8 }, // 6641 |
12633 | | { PseudoVREDAND_VS_M2_E8_MASK, VREDAND_VS, 0x1, 0x8 }, // 6642 |
12634 | | { PseudoVREDAND_VS_M2_E16, VREDAND_VS, 0x1, 0x10 }, // 6643 |
12635 | | { PseudoVREDAND_VS_M2_E16_MASK, VREDAND_VS, 0x1, 0x10 }, // 6644 |
12636 | | { PseudoVREDAND_VS_M2_E32, VREDAND_VS, 0x1, 0x20 }, // 6645 |
12637 | | { PseudoVREDAND_VS_M2_E32_MASK, VREDAND_VS, 0x1, 0x20 }, // 6646 |
12638 | | { PseudoVREDAND_VS_M2_E64, VREDAND_VS, 0x1, 0x40 }, // 6647 |
12639 | | { PseudoVREDAND_VS_M2_E64_MASK, VREDAND_VS, 0x1, 0x40 }, // 6648 |
12640 | | { PseudoVREDAND_VS_M4_E8, VREDAND_VS, 0x2, 0x8 }, // 6649 |
12641 | | { PseudoVREDAND_VS_M4_E8_MASK, VREDAND_VS, 0x2, 0x8 }, // 6650 |
12642 | | { PseudoVREDAND_VS_M4_E16, VREDAND_VS, 0x2, 0x10 }, // 6651 |
12643 | | { PseudoVREDAND_VS_M4_E16_MASK, VREDAND_VS, 0x2, 0x10 }, // 6652 |
12644 | | { PseudoVREDAND_VS_M4_E32, VREDAND_VS, 0x2, 0x20 }, // 6653 |
12645 | | { PseudoVREDAND_VS_M4_E32_MASK, VREDAND_VS, 0x2, 0x20 }, // 6654 |
12646 | | { PseudoVREDAND_VS_M4_E64, VREDAND_VS, 0x2, 0x40 }, // 6655 |
12647 | | { PseudoVREDAND_VS_M4_E64_MASK, VREDAND_VS, 0x2, 0x40 }, // 6656 |
12648 | | { PseudoVREDAND_VS_M8_E8, VREDAND_VS, 0x3, 0x8 }, // 6657 |
12649 | | { PseudoVREDAND_VS_M8_E8_MASK, VREDAND_VS, 0x3, 0x8 }, // 6658 |
12650 | | { PseudoVREDAND_VS_M8_E16, VREDAND_VS, 0x3, 0x10 }, // 6659 |
12651 | | { PseudoVREDAND_VS_M8_E16_MASK, VREDAND_VS, 0x3, 0x10 }, // 6660 |
12652 | | { PseudoVREDAND_VS_M8_E32, VREDAND_VS, 0x3, 0x20 }, // 6661 |
12653 | | { PseudoVREDAND_VS_M8_E32_MASK, VREDAND_VS, 0x3, 0x20 }, // 6662 |
12654 | | { PseudoVREDAND_VS_M8_E64, VREDAND_VS, 0x3, 0x40 }, // 6663 |
12655 | | { PseudoVREDAND_VS_M8_E64_MASK, VREDAND_VS, 0x3, 0x40 }, // 6664 |
12656 | | { PseudoVREDAND_VS_MF8_E8, VREDAND_VS, 0x5, 0x8 }, // 6665 |
12657 | | { PseudoVREDAND_VS_MF8_E8_MASK, VREDAND_VS, 0x5, 0x8 }, // 6666 |
12658 | | { PseudoVREDAND_VS_MF4_E8, VREDAND_VS, 0x6, 0x8 }, // 6667 |
12659 | | { PseudoVREDAND_VS_MF4_E8_MASK, VREDAND_VS, 0x6, 0x8 }, // 6668 |
12660 | | { PseudoVREDAND_VS_MF4_E16, VREDAND_VS, 0x6, 0x10 }, // 6669 |
12661 | | { PseudoVREDAND_VS_MF4_E16_MASK, VREDAND_VS, 0x6, 0x10 }, // 6670 |
12662 | | { PseudoVREDAND_VS_MF2_E8, VREDAND_VS, 0x7, 0x8 }, // 6671 |
12663 | | { PseudoVREDAND_VS_MF2_E8_MASK, VREDAND_VS, 0x7, 0x8 }, // 6672 |
12664 | | { PseudoVREDAND_VS_MF2_E16, VREDAND_VS, 0x7, 0x10 }, // 6673 |
12665 | | { PseudoVREDAND_VS_MF2_E16_MASK, VREDAND_VS, 0x7, 0x10 }, // 6674 |
12666 | | { PseudoVREDAND_VS_MF2_E32, VREDAND_VS, 0x7, 0x20 }, // 6675 |
12667 | | { PseudoVREDAND_VS_MF2_E32_MASK, VREDAND_VS, 0x7, 0x20 }, // 6676 |
12668 | | { PseudoVREDMAXU_VS_M1_E8, VREDMAXU_VS, 0x0, 0x8 }, // 6677 |
12669 | | { PseudoVREDMAXU_VS_M1_E8_MASK, VREDMAXU_VS, 0x0, 0x8 }, // 6678 |
12670 | | { PseudoVREDMAXU_VS_M1_E16, VREDMAXU_VS, 0x0, 0x10 }, // 6679 |
12671 | | { PseudoVREDMAXU_VS_M1_E16_MASK, VREDMAXU_VS, 0x0, 0x10 }, // 6680 |
12672 | | { PseudoVREDMAXU_VS_M1_E32, VREDMAXU_VS, 0x0, 0x20 }, // 6681 |
12673 | | { PseudoVREDMAXU_VS_M1_E32_MASK, VREDMAXU_VS, 0x0, 0x20 }, // 6682 |
12674 | | { PseudoVREDMAXU_VS_M1_E64, VREDMAXU_VS, 0x0, 0x40 }, // 6683 |
12675 | | { PseudoVREDMAXU_VS_M1_E64_MASK, VREDMAXU_VS, 0x0, 0x40 }, // 6684 |
12676 | | { PseudoVREDMAXU_VS_M2_E8, VREDMAXU_VS, 0x1, 0x8 }, // 6685 |
12677 | | { PseudoVREDMAXU_VS_M2_E8_MASK, VREDMAXU_VS, 0x1, 0x8 }, // 6686 |
12678 | | { PseudoVREDMAXU_VS_M2_E16, VREDMAXU_VS, 0x1, 0x10 }, // 6687 |
12679 | | { PseudoVREDMAXU_VS_M2_E16_MASK, VREDMAXU_VS, 0x1, 0x10 }, // 6688 |
12680 | | { PseudoVREDMAXU_VS_M2_E32, VREDMAXU_VS, 0x1, 0x20 }, // 6689 |
12681 | | { PseudoVREDMAXU_VS_M2_E32_MASK, VREDMAXU_VS, 0x1, 0x20 }, // 6690 |
12682 | | { PseudoVREDMAXU_VS_M2_E64, VREDMAXU_VS, 0x1, 0x40 }, // 6691 |
12683 | | { PseudoVREDMAXU_VS_M2_E64_MASK, VREDMAXU_VS, 0x1, 0x40 }, // 6692 |
12684 | | { PseudoVREDMAXU_VS_M4_E8, VREDMAXU_VS, 0x2, 0x8 }, // 6693 |
12685 | | { PseudoVREDMAXU_VS_M4_E8_MASK, VREDMAXU_VS, 0x2, 0x8 }, // 6694 |
12686 | | { PseudoVREDMAXU_VS_M4_E16, VREDMAXU_VS, 0x2, 0x10 }, // 6695 |
12687 | | { PseudoVREDMAXU_VS_M4_E16_MASK, VREDMAXU_VS, 0x2, 0x10 }, // 6696 |
12688 | | { PseudoVREDMAXU_VS_M4_E32, VREDMAXU_VS, 0x2, 0x20 }, // 6697 |
12689 | | { PseudoVREDMAXU_VS_M4_E32_MASK, VREDMAXU_VS, 0x2, 0x20 }, // 6698 |
12690 | | { PseudoVREDMAXU_VS_M4_E64, VREDMAXU_VS, 0x2, 0x40 }, // 6699 |
12691 | | { PseudoVREDMAXU_VS_M4_E64_MASK, VREDMAXU_VS, 0x2, 0x40 }, // 6700 |
12692 | | { PseudoVREDMAXU_VS_M8_E8, VREDMAXU_VS, 0x3, 0x8 }, // 6701 |
12693 | | { PseudoVREDMAXU_VS_M8_E8_MASK, VREDMAXU_VS, 0x3, 0x8 }, // 6702 |
12694 | | { PseudoVREDMAXU_VS_M8_E16, VREDMAXU_VS, 0x3, 0x10 }, // 6703 |
12695 | | { PseudoVREDMAXU_VS_M8_E16_MASK, VREDMAXU_VS, 0x3, 0x10 }, // 6704 |
12696 | | { PseudoVREDMAXU_VS_M8_E32, VREDMAXU_VS, 0x3, 0x20 }, // 6705 |
12697 | | { PseudoVREDMAXU_VS_M8_E32_MASK, VREDMAXU_VS, 0x3, 0x20 }, // 6706 |
12698 | | { PseudoVREDMAXU_VS_M8_E64, VREDMAXU_VS, 0x3, 0x40 }, // 6707 |
12699 | | { PseudoVREDMAXU_VS_M8_E64_MASK, VREDMAXU_VS, 0x3, 0x40 }, // 6708 |
12700 | | { PseudoVREDMAXU_VS_MF8_E8, VREDMAXU_VS, 0x5, 0x8 }, // 6709 |
12701 | | { PseudoVREDMAXU_VS_MF8_E8_MASK, VREDMAXU_VS, 0x5, 0x8 }, // 6710 |
12702 | | { PseudoVREDMAXU_VS_MF4_E8, VREDMAXU_VS, 0x6, 0x8 }, // 6711 |
12703 | | { PseudoVREDMAXU_VS_MF4_E8_MASK, VREDMAXU_VS, 0x6, 0x8 }, // 6712 |
12704 | | { PseudoVREDMAXU_VS_MF4_E16, VREDMAXU_VS, 0x6, 0x10 }, // 6713 |
12705 | | { PseudoVREDMAXU_VS_MF4_E16_MASK, VREDMAXU_VS, 0x6, 0x10 }, // 6714 |
12706 | | { PseudoVREDMAXU_VS_MF2_E8, VREDMAXU_VS, 0x7, 0x8 }, // 6715 |
12707 | | { PseudoVREDMAXU_VS_MF2_E8_MASK, VREDMAXU_VS, 0x7, 0x8 }, // 6716 |
12708 | | { PseudoVREDMAXU_VS_MF2_E16, VREDMAXU_VS, 0x7, 0x10 }, // 6717 |
12709 | | { PseudoVREDMAXU_VS_MF2_E16_MASK, VREDMAXU_VS, 0x7, 0x10 }, // 6718 |
12710 | | { PseudoVREDMAXU_VS_MF2_E32, VREDMAXU_VS, 0x7, 0x20 }, // 6719 |
12711 | | { PseudoVREDMAXU_VS_MF2_E32_MASK, VREDMAXU_VS, 0x7, 0x20 }, // 6720 |
12712 | | { PseudoVREDMAX_VS_M1_E8, VREDMAX_VS, 0x0, 0x8 }, // 6721 |
12713 | | { PseudoVREDMAX_VS_M1_E8_MASK, VREDMAX_VS, 0x0, 0x8 }, // 6722 |
12714 | | { PseudoVREDMAX_VS_M1_E16, VREDMAX_VS, 0x0, 0x10 }, // 6723 |
12715 | | { PseudoVREDMAX_VS_M1_E16_MASK, VREDMAX_VS, 0x0, 0x10 }, // 6724 |
12716 | | { PseudoVREDMAX_VS_M1_E32, VREDMAX_VS, 0x0, 0x20 }, // 6725 |
12717 | | { PseudoVREDMAX_VS_M1_E32_MASK, VREDMAX_VS, 0x0, 0x20 }, // 6726 |
12718 | | { PseudoVREDMAX_VS_M1_E64, VREDMAX_VS, 0x0, 0x40 }, // 6727 |
12719 | | { PseudoVREDMAX_VS_M1_E64_MASK, VREDMAX_VS, 0x0, 0x40 }, // 6728 |
12720 | | { PseudoVREDMAX_VS_M2_E8, VREDMAX_VS, 0x1, 0x8 }, // 6729 |
12721 | | { PseudoVREDMAX_VS_M2_E8_MASK, VREDMAX_VS, 0x1, 0x8 }, // 6730 |
12722 | | { PseudoVREDMAX_VS_M2_E16, VREDMAX_VS, 0x1, 0x10 }, // 6731 |
12723 | | { PseudoVREDMAX_VS_M2_E16_MASK, VREDMAX_VS, 0x1, 0x10 }, // 6732 |
12724 | | { PseudoVREDMAX_VS_M2_E32, VREDMAX_VS, 0x1, 0x20 }, // 6733 |
12725 | | { PseudoVREDMAX_VS_M2_E32_MASK, VREDMAX_VS, 0x1, 0x20 }, // 6734 |
12726 | | { PseudoVREDMAX_VS_M2_E64, VREDMAX_VS, 0x1, 0x40 }, // 6735 |
12727 | | { PseudoVREDMAX_VS_M2_E64_MASK, VREDMAX_VS, 0x1, 0x40 }, // 6736 |
12728 | | { PseudoVREDMAX_VS_M4_E8, VREDMAX_VS, 0x2, 0x8 }, // 6737 |
12729 | | { PseudoVREDMAX_VS_M4_E8_MASK, VREDMAX_VS, 0x2, 0x8 }, // 6738 |
12730 | | { PseudoVREDMAX_VS_M4_E16, VREDMAX_VS, 0x2, 0x10 }, // 6739 |
12731 | | { PseudoVREDMAX_VS_M4_E16_MASK, VREDMAX_VS, 0x2, 0x10 }, // 6740 |
12732 | | { PseudoVREDMAX_VS_M4_E32, VREDMAX_VS, 0x2, 0x20 }, // 6741 |
12733 | | { PseudoVREDMAX_VS_M4_E32_MASK, VREDMAX_VS, 0x2, 0x20 }, // 6742 |
12734 | | { PseudoVREDMAX_VS_M4_E64, VREDMAX_VS, 0x2, 0x40 }, // 6743 |
12735 | | { PseudoVREDMAX_VS_M4_E64_MASK, VREDMAX_VS, 0x2, 0x40 }, // 6744 |
12736 | | { PseudoVREDMAX_VS_M8_E8, VREDMAX_VS, 0x3, 0x8 }, // 6745 |
12737 | | { PseudoVREDMAX_VS_M8_E8_MASK, VREDMAX_VS, 0x3, 0x8 }, // 6746 |
12738 | | { PseudoVREDMAX_VS_M8_E16, VREDMAX_VS, 0x3, 0x10 }, // 6747 |
12739 | | { PseudoVREDMAX_VS_M8_E16_MASK, VREDMAX_VS, 0x3, 0x10 }, // 6748 |
12740 | | { PseudoVREDMAX_VS_M8_E32, VREDMAX_VS, 0x3, 0x20 }, // 6749 |
12741 | | { PseudoVREDMAX_VS_M8_E32_MASK, VREDMAX_VS, 0x3, 0x20 }, // 6750 |
12742 | | { PseudoVREDMAX_VS_M8_E64, VREDMAX_VS, 0x3, 0x40 }, // 6751 |
12743 | | { PseudoVREDMAX_VS_M8_E64_MASK, VREDMAX_VS, 0x3, 0x40 }, // 6752 |
12744 | | { PseudoVREDMAX_VS_MF8_E8, VREDMAX_VS, 0x5, 0x8 }, // 6753 |
12745 | | { PseudoVREDMAX_VS_MF8_E8_MASK, VREDMAX_VS, 0x5, 0x8 }, // 6754 |
12746 | | { PseudoVREDMAX_VS_MF4_E8, VREDMAX_VS, 0x6, 0x8 }, // 6755 |
12747 | | { PseudoVREDMAX_VS_MF4_E8_MASK, VREDMAX_VS, 0x6, 0x8 }, // 6756 |
12748 | | { PseudoVREDMAX_VS_MF4_E16, VREDMAX_VS, 0x6, 0x10 }, // 6757 |
12749 | | { PseudoVREDMAX_VS_MF4_E16_MASK, VREDMAX_VS, 0x6, 0x10 }, // 6758 |
12750 | | { PseudoVREDMAX_VS_MF2_E8, VREDMAX_VS, 0x7, 0x8 }, // 6759 |
12751 | | { PseudoVREDMAX_VS_MF2_E8_MASK, VREDMAX_VS, 0x7, 0x8 }, // 6760 |
12752 | | { PseudoVREDMAX_VS_MF2_E16, VREDMAX_VS, 0x7, 0x10 }, // 6761 |
12753 | | { PseudoVREDMAX_VS_MF2_E16_MASK, VREDMAX_VS, 0x7, 0x10 }, // 6762 |
12754 | | { PseudoVREDMAX_VS_MF2_E32, VREDMAX_VS, 0x7, 0x20 }, // 6763 |
12755 | | { PseudoVREDMAX_VS_MF2_E32_MASK, VREDMAX_VS, 0x7, 0x20 }, // 6764 |
12756 | | { PseudoVREDMINU_VS_M1_E8, VREDMINU_VS, 0x0, 0x8 }, // 6765 |
12757 | | { PseudoVREDMINU_VS_M1_E8_MASK, VREDMINU_VS, 0x0, 0x8 }, // 6766 |
12758 | | { PseudoVREDMINU_VS_M1_E16, VREDMINU_VS, 0x0, 0x10 }, // 6767 |
12759 | | { PseudoVREDMINU_VS_M1_E16_MASK, VREDMINU_VS, 0x0, 0x10 }, // 6768 |
12760 | | { PseudoVREDMINU_VS_M1_E32, VREDMINU_VS, 0x0, 0x20 }, // 6769 |
12761 | | { PseudoVREDMINU_VS_M1_E32_MASK, VREDMINU_VS, 0x0, 0x20 }, // 6770 |
12762 | | { PseudoVREDMINU_VS_M1_E64, VREDMINU_VS, 0x0, 0x40 }, // 6771 |
12763 | | { PseudoVREDMINU_VS_M1_E64_MASK, VREDMINU_VS, 0x0, 0x40 }, // 6772 |
12764 | | { PseudoVREDMINU_VS_M2_E8, VREDMINU_VS, 0x1, 0x8 }, // 6773 |
12765 | | { PseudoVREDMINU_VS_M2_E8_MASK, VREDMINU_VS, 0x1, 0x8 }, // 6774 |
12766 | | { PseudoVREDMINU_VS_M2_E16, VREDMINU_VS, 0x1, 0x10 }, // 6775 |
12767 | | { PseudoVREDMINU_VS_M2_E16_MASK, VREDMINU_VS, 0x1, 0x10 }, // 6776 |
12768 | | { PseudoVREDMINU_VS_M2_E32, VREDMINU_VS, 0x1, 0x20 }, // 6777 |
12769 | | { PseudoVREDMINU_VS_M2_E32_MASK, VREDMINU_VS, 0x1, 0x20 }, // 6778 |
12770 | | { PseudoVREDMINU_VS_M2_E64, VREDMINU_VS, 0x1, 0x40 }, // 6779 |
12771 | | { PseudoVREDMINU_VS_M2_E64_MASK, VREDMINU_VS, 0x1, 0x40 }, // 6780 |
12772 | | { PseudoVREDMINU_VS_M4_E8, VREDMINU_VS, 0x2, 0x8 }, // 6781 |
12773 | | { PseudoVREDMINU_VS_M4_E8_MASK, VREDMINU_VS, 0x2, 0x8 }, // 6782 |
12774 | | { PseudoVREDMINU_VS_M4_E16, VREDMINU_VS, 0x2, 0x10 }, // 6783 |
12775 | | { PseudoVREDMINU_VS_M4_E16_MASK, VREDMINU_VS, 0x2, 0x10 }, // 6784 |
12776 | | { PseudoVREDMINU_VS_M4_E32, VREDMINU_VS, 0x2, 0x20 }, // 6785 |
12777 | | { PseudoVREDMINU_VS_M4_E32_MASK, VREDMINU_VS, 0x2, 0x20 }, // 6786 |
12778 | | { PseudoVREDMINU_VS_M4_E64, VREDMINU_VS, 0x2, 0x40 }, // 6787 |
12779 | | { PseudoVREDMINU_VS_M4_E64_MASK, VREDMINU_VS, 0x2, 0x40 }, // 6788 |
12780 | | { PseudoVREDMINU_VS_M8_E8, VREDMINU_VS, 0x3, 0x8 }, // 6789 |
12781 | | { PseudoVREDMINU_VS_M8_E8_MASK, VREDMINU_VS, 0x3, 0x8 }, // 6790 |
12782 | | { PseudoVREDMINU_VS_M8_E16, VREDMINU_VS, 0x3, 0x10 }, // 6791 |
12783 | | { PseudoVREDMINU_VS_M8_E16_MASK, VREDMINU_VS, 0x3, 0x10 }, // 6792 |
12784 | | { PseudoVREDMINU_VS_M8_E32, VREDMINU_VS, 0x3, 0x20 }, // 6793 |
12785 | | { PseudoVREDMINU_VS_M8_E32_MASK, VREDMINU_VS, 0x3, 0x20 }, // 6794 |
12786 | | { PseudoVREDMINU_VS_M8_E64, VREDMINU_VS, 0x3, 0x40 }, // 6795 |
12787 | | { PseudoVREDMINU_VS_M8_E64_MASK, VREDMINU_VS, 0x3, 0x40 }, // 6796 |
12788 | | { PseudoVREDMINU_VS_MF8_E8, VREDMINU_VS, 0x5, 0x8 }, // 6797 |
12789 | | { PseudoVREDMINU_VS_MF8_E8_MASK, VREDMINU_VS, 0x5, 0x8 }, // 6798 |
12790 | | { PseudoVREDMINU_VS_MF4_E8, VREDMINU_VS, 0x6, 0x8 }, // 6799 |
12791 | | { PseudoVREDMINU_VS_MF4_E8_MASK, VREDMINU_VS, 0x6, 0x8 }, // 6800 |
12792 | | { PseudoVREDMINU_VS_MF4_E16, VREDMINU_VS, 0x6, 0x10 }, // 6801 |
12793 | | { PseudoVREDMINU_VS_MF4_E16_MASK, VREDMINU_VS, 0x6, 0x10 }, // 6802 |
12794 | | { PseudoVREDMINU_VS_MF2_E8, VREDMINU_VS, 0x7, 0x8 }, // 6803 |
12795 | | { PseudoVREDMINU_VS_MF2_E8_MASK, VREDMINU_VS, 0x7, 0x8 }, // 6804 |
12796 | | { PseudoVREDMINU_VS_MF2_E16, VREDMINU_VS, 0x7, 0x10 }, // 6805 |
12797 | | { PseudoVREDMINU_VS_MF2_E16_MASK, VREDMINU_VS, 0x7, 0x10 }, // 6806 |
12798 | | { PseudoVREDMINU_VS_MF2_E32, VREDMINU_VS, 0x7, 0x20 }, // 6807 |
12799 | | { PseudoVREDMINU_VS_MF2_E32_MASK, VREDMINU_VS, 0x7, 0x20 }, // 6808 |
12800 | | { PseudoVREDMIN_VS_M1_E8, VREDMIN_VS, 0x0, 0x8 }, // 6809 |
12801 | | { PseudoVREDMIN_VS_M1_E8_MASK, VREDMIN_VS, 0x0, 0x8 }, // 6810 |
12802 | | { PseudoVREDMIN_VS_M1_E16, VREDMIN_VS, 0x0, 0x10 }, // 6811 |
12803 | | { PseudoVREDMIN_VS_M1_E16_MASK, VREDMIN_VS, 0x0, 0x10 }, // 6812 |
12804 | | { PseudoVREDMIN_VS_M1_E32, VREDMIN_VS, 0x0, 0x20 }, // 6813 |
12805 | | { PseudoVREDMIN_VS_M1_E32_MASK, VREDMIN_VS, 0x0, 0x20 }, // 6814 |
12806 | | { PseudoVREDMIN_VS_M1_E64, VREDMIN_VS, 0x0, 0x40 }, // 6815 |
12807 | | { PseudoVREDMIN_VS_M1_E64_MASK, VREDMIN_VS, 0x0, 0x40 }, // 6816 |
12808 | | { PseudoVREDMIN_VS_M2_E8, VREDMIN_VS, 0x1, 0x8 }, // 6817 |
12809 | | { PseudoVREDMIN_VS_M2_E8_MASK, VREDMIN_VS, 0x1, 0x8 }, // 6818 |
12810 | | { PseudoVREDMIN_VS_M2_E16, VREDMIN_VS, 0x1, 0x10 }, // 6819 |
12811 | | { PseudoVREDMIN_VS_M2_E16_MASK, VREDMIN_VS, 0x1, 0x10 }, // 6820 |
12812 | | { PseudoVREDMIN_VS_M2_E32, VREDMIN_VS, 0x1, 0x20 }, // 6821 |
12813 | | { PseudoVREDMIN_VS_M2_E32_MASK, VREDMIN_VS, 0x1, 0x20 }, // 6822 |
12814 | | { PseudoVREDMIN_VS_M2_E64, VREDMIN_VS, 0x1, 0x40 }, // 6823 |
12815 | | { PseudoVREDMIN_VS_M2_E64_MASK, VREDMIN_VS, 0x1, 0x40 }, // 6824 |
12816 | | { PseudoVREDMIN_VS_M4_E8, VREDMIN_VS, 0x2, 0x8 }, // 6825 |
12817 | | { PseudoVREDMIN_VS_M4_E8_MASK, VREDMIN_VS, 0x2, 0x8 }, // 6826 |
12818 | | { PseudoVREDMIN_VS_M4_E16, VREDMIN_VS, 0x2, 0x10 }, // 6827 |
12819 | | { PseudoVREDMIN_VS_M4_E16_MASK, VREDMIN_VS, 0x2, 0x10 }, // 6828 |
12820 | | { PseudoVREDMIN_VS_M4_E32, VREDMIN_VS, 0x2, 0x20 }, // 6829 |
12821 | | { PseudoVREDMIN_VS_M4_E32_MASK, VREDMIN_VS, 0x2, 0x20 }, // 6830 |
12822 | | { PseudoVREDMIN_VS_M4_E64, VREDMIN_VS, 0x2, 0x40 }, // 6831 |
12823 | | { PseudoVREDMIN_VS_M4_E64_MASK, VREDMIN_VS, 0x2, 0x40 }, // 6832 |
12824 | | { PseudoVREDMIN_VS_M8_E8, VREDMIN_VS, 0x3, 0x8 }, // 6833 |
12825 | | { PseudoVREDMIN_VS_M8_E8_MASK, VREDMIN_VS, 0x3, 0x8 }, // 6834 |
12826 | | { PseudoVREDMIN_VS_M8_E16, VREDMIN_VS, 0x3, 0x10 }, // 6835 |
12827 | | { PseudoVREDMIN_VS_M8_E16_MASK, VREDMIN_VS, 0x3, 0x10 }, // 6836 |
12828 | | { PseudoVREDMIN_VS_M8_E32, VREDMIN_VS, 0x3, 0x20 }, // 6837 |
12829 | | { PseudoVREDMIN_VS_M8_E32_MASK, VREDMIN_VS, 0x3, 0x20 }, // 6838 |
12830 | | { PseudoVREDMIN_VS_M8_E64, VREDMIN_VS, 0x3, 0x40 }, // 6839 |
12831 | | { PseudoVREDMIN_VS_M8_E64_MASK, VREDMIN_VS, 0x3, 0x40 }, // 6840 |
12832 | | { PseudoVREDMIN_VS_MF8_E8, VREDMIN_VS, 0x5, 0x8 }, // 6841 |
12833 | | { PseudoVREDMIN_VS_MF8_E8_MASK, VREDMIN_VS, 0x5, 0x8 }, // 6842 |
12834 | | { PseudoVREDMIN_VS_MF4_E8, VREDMIN_VS, 0x6, 0x8 }, // 6843 |
12835 | | { PseudoVREDMIN_VS_MF4_E8_MASK, VREDMIN_VS, 0x6, 0x8 }, // 6844 |
12836 | | { PseudoVREDMIN_VS_MF4_E16, VREDMIN_VS, 0x6, 0x10 }, // 6845 |
12837 | | { PseudoVREDMIN_VS_MF4_E16_MASK, VREDMIN_VS, 0x6, 0x10 }, // 6846 |
12838 | | { PseudoVREDMIN_VS_MF2_E8, VREDMIN_VS, 0x7, 0x8 }, // 6847 |
12839 | | { PseudoVREDMIN_VS_MF2_E8_MASK, VREDMIN_VS, 0x7, 0x8 }, // 6848 |
12840 | | { PseudoVREDMIN_VS_MF2_E16, VREDMIN_VS, 0x7, 0x10 }, // 6849 |
12841 | | { PseudoVREDMIN_VS_MF2_E16_MASK, VREDMIN_VS, 0x7, 0x10 }, // 6850 |
12842 | | { PseudoVREDMIN_VS_MF2_E32, VREDMIN_VS, 0x7, 0x20 }, // 6851 |
12843 | | { PseudoVREDMIN_VS_MF2_E32_MASK, VREDMIN_VS, 0x7, 0x20 }, // 6852 |
12844 | | { PseudoVREDOR_VS_M1_E8, VREDOR_VS, 0x0, 0x8 }, // 6853 |
12845 | | { PseudoVREDOR_VS_M1_E8_MASK, VREDOR_VS, 0x0, 0x8 }, // 6854 |
12846 | | { PseudoVREDOR_VS_M1_E16, VREDOR_VS, 0x0, 0x10 }, // 6855 |
12847 | | { PseudoVREDOR_VS_M1_E16_MASK, VREDOR_VS, 0x0, 0x10 }, // 6856 |
12848 | | { PseudoVREDOR_VS_M1_E32, VREDOR_VS, 0x0, 0x20 }, // 6857 |
12849 | | { PseudoVREDOR_VS_M1_E32_MASK, VREDOR_VS, 0x0, 0x20 }, // 6858 |
12850 | | { PseudoVREDOR_VS_M1_E64, VREDOR_VS, 0x0, 0x40 }, // 6859 |
12851 | | { PseudoVREDOR_VS_M1_E64_MASK, VREDOR_VS, 0x0, 0x40 }, // 6860 |
12852 | | { PseudoVREDOR_VS_M2_E8, VREDOR_VS, 0x1, 0x8 }, // 6861 |
12853 | | { PseudoVREDOR_VS_M2_E8_MASK, VREDOR_VS, 0x1, 0x8 }, // 6862 |
12854 | | { PseudoVREDOR_VS_M2_E16, VREDOR_VS, 0x1, 0x10 }, // 6863 |
12855 | | { PseudoVREDOR_VS_M2_E16_MASK, VREDOR_VS, 0x1, 0x10 }, // 6864 |
12856 | | { PseudoVREDOR_VS_M2_E32, VREDOR_VS, 0x1, 0x20 }, // 6865 |
12857 | | { PseudoVREDOR_VS_M2_E32_MASK, VREDOR_VS, 0x1, 0x20 }, // 6866 |
12858 | | { PseudoVREDOR_VS_M2_E64, VREDOR_VS, 0x1, 0x40 }, // 6867 |
12859 | | { PseudoVREDOR_VS_M2_E64_MASK, VREDOR_VS, 0x1, 0x40 }, // 6868 |
12860 | | { PseudoVREDOR_VS_M4_E8, VREDOR_VS, 0x2, 0x8 }, // 6869 |
12861 | | { PseudoVREDOR_VS_M4_E8_MASK, VREDOR_VS, 0x2, 0x8 }, // 6870 |
12862 | | { PseudoVREDOR_VS_M4_E16, VREDOR_VS, 0x2, 0x10 }, // 6871 |
12863 | | { PseudoVREDOR_VS_M4_E16_MASK, VREDOR_VS, 0x2, 0x10 }, // 6872 |
12864 | | { PseudoVREDOR_VS_M4_E32, VREDOR_VS, 0x2, 0x20 }, // 6873 |
12865 | | { PseudoVREDOR_VS_M4_E32_MASK, VREDOR_VS, 0x2, 0x20 }, // 6874 |
12866 | | { PseudoVREDOR_VS_M4_E64, VREDOR_VS, 0x2, 0x40 }, // 6875 |
12867 | | { PseudoVREDOR_VS_M4_E64_MASK, VREDOR_VS, 0x2, 0x40 }, // 6876 |
12868 | | { PseudoVREDOR_VS_M8_E8, VREDOR_VS, 0x3, 0x8 }, // 6877 |
12869 | | { PseudoVREDOR_VS_M8_E8_MASK, VREDOR_VS, 0x3, 0x8 }, // 6878 |
12870 | | { PseudoVREDOR_VS_M8_E16, VREDOR_VS, 0x3, 0x10 }, // 6879 |
12871 | | { PseudoVREDOR_VS_M8_E16_MASK, VREDOR_VS, 0x3, 0x10 }, // 6880 |
12872 | | { PseudoVREDOR_VS_M8_E32, VREDOR_VS, 0x3, 0x20 }, // 6881 |
12873 | | { PseudoVREDOR_VS_M8_E32_MASK, VREDOR_VS, 0x3, 0x20 }, // 6882 |
12874 | | { PseudoVREDOR_VS_M8_E64, VREDOR_VS, 0x3, 0x40 }, // 6883 |
12875 | | { PseudoVREDOR_VS_M8_E64_MASK, VREDOR_VS, 0x3, 0x40 }, // 6884 |
12876 | | { PseudoVREDOR_VS_MF8_E8, VREDOR_VS, 0x5, 0x8 }, // 6885 |
12877 | | { PseudoVREDOR_VS_MF8_E8_MASK, VREDOR_VS, 0x5, 0x8 }, // 6886 |
12878 | | { PseudoVREDOR_VS_MF4_E8, VREDOR_VS, 0x6, 0x8 }, // 6887 |
12879 | | { PseudoVREDOR_VS_MF4_E8_MASK, VREDOR_VS, 0x6, 0x8 }, // 6888 |
12880 | | { PseudoVREDOR_VS_MF4_E16, VREDOR_VS, 0x6, 0x10 }, // 6889 |
12881 | | { PseudoVREDOR_VS_MF4_E16_MASK, VREDOR_VS, 0x6, 0x10 }, // 6890 |
12882 | | { PseudoVREDOR_VS_MF2_E8, VREDOR_VS, 0x7, 0x8 }, // 6891 |
12883 | | { PseudoVREDOR_VS_MF2_E8_MASK, VREDOR_VS, 0x7, 0x8 }, // 6892 |
12884 | | { PseudoVREDOR_VS_MF2_E16, VREDOR_VS, 0x7, 0x10 }, // 6893 |
12885 | | { PseudoVREDOR_VS_MF2_E16_MASK, VREDOR_VS, 0x7, 0x10 }, // 6894 |
12886 | | { PseudoVREDOR_VS_MF2_E32, VREDOR_VS, 0x7, 0x20 }, // 6895 |
12887 | | { PseudoVREDOR_VS_MF2_E32_MASK, VREDOR_VS, 0x7, 0x20 }, // 6896 |
12888 | | { PseudoVREDSUM_VS_M1_E8, VREDSUM_VS, 0x0, 0x8 }, // 6897 |
12889 | | { PseudoVREDSUM_VS_M1_E8_MASK, VREDSUM_VS, 0x0, 0x8 }, // 6898 |
12890 | | { PseudoVREDSUM_VS_M1_E16, VREDSUM_VS, 0x0, 0x10 }, // 6899 |
12891 | | { PseudoVREDSUM_VS_M1_E16_MASK, VREDSUM_VS, 0x0, 0x10 }, // 6900 |
12892 | | { PseudoVREDSUM_VS_M1_E32, VREDSUM_VS, 0x0, 0x20 }, // 6901 |
12893 | | { PseudoVREDSUM_VS_M1_E32_MASK, VREDSUM_VS, 0x0, 0x20 }, // 6902 |
12894 | | { PseudoVREDSUM_VS_M1_E64, VREDSUM_VS, 0x0, 0x40 }, // 6903 |
12895 | | { PseudoVREDSUM_VS_M1_E64_MASK, VREDSUM_VS, 0x0, 0x40 }, // 6904 |
12896 | | { PseudoVREDSUM_VS_M2_E8, VREDSUM_VS, 0x1, 0x8 }, // 6905 |
12897 | | { PseudoVREDSUM_VS_M2_E8_MASK, VREDSUM_VS, 0x1, 0x8 }, // 6906 |
12898 | | { PseudoVREDSUM_VS_M2_E16, VREDSUM_VS, 0x1, 0x10 }, // 6907 |
12899 | | { PseudoVREDSUM_VS_M2_E16_MASK, VREDSUM_VS, 0x1, 0x10 }, // 6908 |
12900 | | { PseudoVREDSUM_VS_M2_E32, VREDSUM_VS, 0x1, 0x20 }, // 6909 |
12901 | | { PseudoVREDSUM_VS_M2_E32_MASK, VREDSUM_VS, 0x1, 0x20 }, // 6910 |
12902 | | { PseudoVREDSUM_VS_M2_E64, VREDSUM_VS, 0x1, 0x40 }, // 6911 |
12903 | | { PseudoVREDSUM_VS_M2_E64_MASK, VREDSUM_VS, 0x1, 0x40 }, // 6912 |
12904 | | { PseudoVREDSUM_VS_M4_E8, VREDSUM_VS, 0x2, 0x8 }, // 6913 |
12905 | | { PseudoVREDSUM_VS_M4_E8_MASK, VREDSUM_VS, 0x2, 0x8 }, // 6914 |
12906 | | { PseudoVREDSUM_VS_M4_E16, VREDSUM_VS, 0x2, 0x10 }, // 6915 |
12907 | | { PseudoVREDSUM_VS_M4_E16_MASK, VREDSUM_VS, 0x2, 0x10 }, // 6916 |
12908 | | { PseudoVREDSUM_VS_M4_E32, VREDSUM_VS, 0x2, 0x20 }, // 6917 |
12909 | | { PseudoVREDSUM_VS_M4_E32_MASK, VREDSUM_VS, 0x2, 0x20 }, // 6918 |
12910 | | { PseudoVREDSUM_VS_M4_E64, VREDSUM_VS, 0x2, 0x40 }, // 6919 |
12911 | | { PseudoVREDSUM_VS_M4_E64_MASK, VREDSUM_VS, 0x2, 0x40 }, // 6920 |
12912 | | { PseudoVREDSUM_VS_M8_E8, VREDSUM_VS, 0x3, 0x8 }, // 6921 |
12913 | | { PseudoVREDSUM_VS_M8_E8_MASK, VREDSUM_VS, 0x3, 0x8 }, // 6922 |
12914 | | { PseudoVREDSUM_VS_M8_E16, VREDSUM_VS, 0x3, 0x10 }, // 6923 |
12915 | | { PseudoVREDSUM_VS_M8_E16_MASK, VREDSUM_VS, 0x3, 0x10 }, // 6924 |
12916 | | { PseudoVREDSUM_VS_M8_E32, VREDSUM_VS, 0x3, 0x20 }, // 6925 |
12917 | | { PseudoVREDSUM_VS_M8_E32_MASK, VREDSUM_VS, 0x3, 0x20 }, // 6926 |
12918 | | { PseudoVREDSUM_VS_M8_E64, VREDSUM_VS, 0x3, 0x40 }, // 6927 |
12919 | | { PseudoVREDSUM_VS_M8_E64_MASK, VREDSUM_VS, 0x3, 0x40 }, // 6928 |
12920 | | { PseudoVREDSUM_VS_MF8_E8, VREDSUM_VS, 0x5, 0x8 }, // 6929 |
12921 | | { PseudoVREDSUM_VS_MF8_E8_MASK, VREDSUM_VS, 0x5, 0x8 }, // 6930 |
12922 | | { PseudoVREDSUM_VS_MF4_E8, VREDSUM_VS, 0x6, 0x8 }, // 6931 |
12923 | | { PseudoVREDSUM_VS_MF4_E8_MASK, VREDSUM_VS, 0x6, 0x8 }, // 6932 |
12924 | | { PseudoVREDSUM_VS_MF4_E16, VREDSUM_VS, 0x6, 0x10 }, // 6933 |
12925 | | { PseudoVREDSUM_VS_MF4_E16_MASK, VREDSUM_VS, 0x6, 0x10 }, // 6934 |
12926 | | { PseudoVREDSUM_VS_MF2_E8, VREDSUM_VS, 0x7, 0x8 }, // 6935 |
12927 | | { PseudoVREDSUM_VS_MF2_E8_MASK, VREDSUM_VS, 0x7, 0x8 }, // 6936 |
12928 | | { PseudoVREDSUM_VS_MF2_E16, VREDSUM_VS, 0x7, 0x10 }, // 6937 |
12929 | | { PseudoVREDSUM_VS_MF2_E16_MASK, VREDSUM_VS, 0x7, 0x10 }, // 6938 |
12930 | | { PseudoVREDSUM_VS_MF2_E32, VREDSUM_VS, 0x7, 0x20 }, // 6939 |
12931 | | { PseudoVREDSUM_VS_MF2_E32_MASK, VREDSUM_VS, 0x7, 0x20 }, // 6940 |
12932 | | { PseudoVREDXOR_VS_M1_E8, VREDXOR_VS, 0x0, 0x8 }, // 6941 |
12933 | | { PseudoVREDXOR_VS_M1_E8_MASK, VREDXOR_VS, 0x0, 0x8 }, // 6942 |
12934 | | { PseudoVREDXOR_VS_M1_E16, VREDXOR_VS, 0x0, 0x10 }, // 6943 |
12935 | | { PseudoVREDXOR_VS_M1_E16_MASK, VREDXOR_VS, 0x0, 0x10 }, // 6944 |
12936 | | { PseudoVREDXOR_VS_M1_E32, VREDXOR_VS, 0x0, 0x20 }, // 6945 |
12937 | | { PseudoVREDXOR_VS_M1_E32_MASK, VREDXOR_VS, 0x0, 0x20 }, // 6946 |
12938 | | { PseudoVREDXOR_VS_M1_E64, VREDXOR_VS, 0x0, 0x40 }, // 6947 |
12939 | | { PseudoVREDXOR_VS_M1_E64_MASK, VREDXOR_VS, 0x0, 0x40 }, // 6948 |
12940 | | { PseudoVREDXOR_VS_M2_E8, VREDXOR_VS, 0x1, 0x8 }, // 6949 |
12941 | | { PseudoVREDXOR_VS_M2_E8_MASK, VREDXOR_VS, 0x1, 0x8 }, // 6950 |
12942 | | { PseudoVREDXOR_VS_M2_E16, VREDXOR_VS, 0x1, 0x10 }, // 6951 |
12943 | | { PseudoVREDXOR_VS_M2_E16_MASK, VREDXOR_VS, 0x1, 0x10 }, // 6952 |
12944 | | { PseudoVREDXOR_VS_M2_E32, VREDXOR_VS, 0x1, 0x20 }, // 6953 |
12945 | | { PseudoVREDXOR_VS_M2_E32_MASK, VREDXOR_VS, 0x1, 0x20 }, // 6954 |
12946 | | { PseudoVREDXOR_VS_M2_E64, VREDXOR_VS, 0x1, 0x40 }, // 6955 |
12947 | | { PseudoVREDXOR_VS_M2_E64_MASK, VREDXOR_VS, 0x1, 0x40 }, // 6956 |
12948 | | { PseudoVREDXOR_VS_M4_E8, VREDXOR_VS, 0x2, 0x8 }, // 6957 |
12949 | | { PseudoVREDXOR_VS_M4_E8_MASK, VREDXOR_VS, 0x2, 0x8 }, // 6958 |
12950 | | { PseudoVREDXOR_VS_M4_E16, VREDXOR_VS, 0x2, 0x10 }, // 6959 |
12951 | | { PseudoVREDXOR_VS_M4_E16_MASK, VREDXOR_VS, 0x2, 0x10 }, // 6960 |
12952 | | { PseudoVREDXOR_VS_M4_E32, VREDXOR_VS, 0x2, 0x20 }, // 6961 |
12953 | | { PseudoVREDXOR_VS_M4_E32_MASK, VREDXOR_VS, 0x2, 0x20 }, // 6962 |
12954 | | { PseudoVREDXOR_VS_M4_E64, VREDXOR_VS, 0x2, 0x40 }, // 6963 |
12955 | | { PseudoVREDXOR_VS_M4_E64_MASK, VREDXOR_VS, 0x2, 0x40 }, // 6964 |
12956 | | { PseudoVREDXOR_VS_M8_E8, VREDXOR_VS, 0x3, 0x8 }, // 6965 |
12957 | | { PseudoVREDXOR_VS_M8_E8_MASK, VREDXOR_VS, 0x3, 0x8 }, // 6966 |
12958 | | { PseudoVREDXOR_VS_M8_E16, VREDXOR_VS, 0x3, 0x10 }, // 6967 |
12959 | | { PseudoVREDXOR_VS_M8_E16_MASK, VREDXOR_VS, 0x3, 0x10 }, // 6968 |
12960 | | { PseudoVREDXOR_VS_M8_E32, VREDXOR_VS, 0x3, 0x20 }, // 6969 |
12961 | | { PseudoVREDXOR_VS_M8_E32_MASK, VREDXOR_VS, 0x3, 0x20 }, // 6970 |
12962 | | { PseudoVREDXOR_VS_M8_E64, VREDXOR_VS, 0x3, 0x40 }, // 6971 |
12963 | | { PseudoVREDXOR_VS_M8_E64_MASK, VREDXOR_VS, 0x3, 0x40 }, // 6972 |
12964 | | { PseudoVREDXOR_VS_MF8_E8, VREDXOR_VS, 0x5, 0x8 }, // 6973 |
12965 | | { PseudoVREDXOR_VS_MF8_E8_MASK, VREDXOR_VS, 0x5, 0x8 }, // 6974 |
12966 | | { PseudoVREDXOR_VS_MF4_E8, VREDXOR_VS, 0x6, 0x8 }, // 6975 |
12967 | | { PseudoVREDXOR_VS_MF4_E8_MASK, VREDXOR_VS, 0x6, 0x8 }, // 6976 |
12968 | | { PseudoVREDXOR_VS_MF4_E16, VREDXOR_VS, 0x6, 0x10 }, // 6977 |
12969 | | { PseudoVREDXOR_VS_MF4_E16_MASK, VREDXOR_VS, 0x6, 0x10 }, // 6978 |
12970 | | { PseudoVREDXOR_VS_MF2_E8, VREDXOR_VS, 0x7, 0x8 }, // 6979 |
12971 | | { PseudoVREDXOR_VS_MF2_E8_MASK, VREDXOR_VS, 0x7, 0x8 }, // 6980 |
12972 | | { PseudoVREDXOR_VS_MF2_E16, VREDXOR_VS, 0x7, 0x10 }, // 6981 |
12973 | | { PseudoVREDXOR_VS_MF2_E16_MASK, VREDXOR_VS, 0x7, 0x10 }, // 6982 |
12974 | | { PseudoVREDXOR_VS_MF2_E32, VREDXOR_VS, 0x7, 0x20 }, // 6983 |
12975 | | { PseudoVREDXOR_VS_MF2_E32_MASK, VREDXOR_VS, 0x7, 0x20 }, // 6984 |
12976 | | { PseudoVREMU_VV_M1_E8, VREMU_VV, 0x0, 0x8 }, // 6985 |
12977 | | { PseudoVREMU_VV_M1_E8_MASK, VREMU_VV, 0x0, 0x8 }, // 6986 |
12978 | | { PseudoVREMU_VV_M1_E16, VREMU_VV, 0x0, 0x10 }, // 6987 |
12979 | | { PseudoVREMU_VV_M1_E16_MASK, VREMU_VV, 0x0, 0x10 }, // 6988 |
12980 | | { PseudoVREMU_VV_M1_E32, VREMU_VV, 0x0, 0x20 }, // 6989 |
12981 | | { PseudoVREMU_VV_M1_E32_MASK, VREMU_VV, 0x0, 0x20 }, // 6990 |
12982 | | { PseudoVREMU_VV_M1_E64, VREMU_VV, 0x0, 0x40 }, // 6991 |
12983 | | { PseudoVREMU_VV_M1_E64_MASK, VREMU_VV, 0x0, 0x40 }, // 6992 |
12984 | | { PseudoVREMU_VV_M2_E8, VREMU_VV, 0x1, 0x8 }, // 6993 |
12985 | | { PseudoVREMU_VV_M2_E8_MASK, VREMU_VV, 0x1, 0x8 }, // 6994 |
12986 | | { PseudoVREMU_VV_M2_E16, VREMU_VV, 0x1, 0x10 }, // 6995 |
12987 | | { PseudoVREMU_VV_M2_E16_MASK, VREMU_VV, 0x1, 0x10 }, // 6996 |
12988 | | { PseudoVREMU_VV_M2_E32, VREMU_VV, 0x1, 0x20 }, // 6997 |
12989 | | { PseudoVREMU_VV_M2_E32_MASK, VREMU_VV, 0x1, 0x20 }, // 6998 |
12990 | | { PseudoVREMU_VV_M2_E64, VREMU_VV, 0x1, 0x40 }, // 6999 |
12991 | | { PseudoVREMU_VV_M2_E64_MASK, VREMU_VV, 0x1, 0x40 }, // 7000 |
12992 | | { PseudoVREMU_VV_M4_E8, VREMU_VV, 0x2, 0x8 }, // 7001 |
12993 | | { PseudoVREMU_VV_M4_E8_MASK, VREMU_VV, 0x2, 0x8 }, // 7002 |
12994 | | { PseudoVREMU_VV_M4_E16, VREMU_VV, 0x2, 0x10 }, // 7003 |
12995 | | { PseudoVREMU_VV_M4_E16_MASK, VREMU_VV, 0x2, 0x10 }, // 7004 |
12996 | | { PseudoVREMU_VV_M4_E32, VREMU_VV, 0x2, 0x20 }, // 7005 |
12997 | | { PseudoVREMU_VV_M4_E32_MASK, VREMU_VV, 0x2, 0x20 }, // 7006 |
12998 | | { PseudoVREMU_VV_M4_E64, VREMU_VV, 0x2, 0x40 }, // 7007 |
12999 | | { PseudoVREMU_VV_M4_E64_MASK, VREMU_VV, 0x2, 0x40 }, // 7008 |
13000 | | { PseudoVREMU_VV_M8_E8, VREMU_VV, 0x3, 0x8 }, // 7009 |
13001 | | { PseudoVREMU_VV_M8_E8_MASK, VREMU_VV, 0x3, 0x8 }, // 7010 |
13002 | | { PseudoVREMU_VV_M8_E16, VREMU_VV, 0x3, 0x10 }, // 7011 |
13003 | | { PseudoVREMU_VV_M8_E16_MASK, VREMU_VV, 0x3, 0x10 }, // 7012 |
13004 | | { PseudoVREMU_VV_M8_E32, VREMU_VV, 0x3, 0x20 }, // 7013 |
13005 | | { PseudoVREMU_VV_M8_E32_MASK, VREMU_VV, 0x3, 0x20 }, // 7014 |
13006 | | { PseudoVREMU_VV_M8_E64, VREMU_VV, 0x3, 0x40 }, // 7015 |
13007 | | { PseudoVREMU_VV_M8_E64_MASK, VREMU_VV, 0x3, 0x40 }, // 7016 |
13008 | | { PseudoVREMU_VV_MF8_E8, VREMU_VV, 0x5, 0x8 }, // 7017 |
13009 | | { PseudoVREMU_VV_MF8_E8_MASK, VREMU_VV, 0x5, 0x8 }, // 7018 |
13010 | | { PseudoVREMU_VV_MF4_E8, VREMU_VV, 0x6, 0x8 }, // 7019 |
13011 | | { PseudoVREMU_VV_MF4_E8_MASK, VREMU_VV, 0x6, 0x8 }, // 7020 |
13012 | | { PseudoVREMU_VV_MF4_E16, VREMU_VV, 0x6, 0x10 }, // 7021 |
13013 | | { PseudoVREMU_VV_MF4_E16_MASK, VREMU_VV, 0x6, 0x10 }, // 7022 |
13014 | | { PseudoVREMU_VV_MF2_E8, VREMU_VV, 0x7, 0x8 }, // 7023 |
13015 | | { PseudoVREMU_VV_MF2_E8_MASK, VREMU_VV, 0x7, 0x8 }, // 7024 |
13016 | | { PseudoVREMU_VV_MF2_E16, VREMU_VV, 0x7, 0x10 }, // 7025 |
13017 | | { PseudoVREMU_VV_MF2_E16_MASK, VREMU_VV, 0x7, 0x10 }, // 7026 |
13018 | | { PseudoVREMU_VV_MF2_E32, VREMU_VV, 0x7, 0x20 }, // 7027 |
13019 | | { PseudoVREMU_VV_MF2_E32_MASK, VREMU_VV, 0x7, 0x20 }, // 7028 |
13020 | | { PseudoVREMU_VX_M1_E8, VREMU_VX, 0x0, 0x8 }, // 7029 |
13021 | | { PseudoVREMU_VX_M1_E8_MASK, VREMU_VX, 0x0, 0x8 }, // 7030 |
13022 | | { PseudoVREMU_VX_M1_E16, VREMU_VX, 0x0, 0x10 }, // 7031 |
13023 | | { PseudoVREMU_VX_M1_E16_MASK, VREMU_VX, 0x0, 0x10 }, // 7032 |
13024 | | { PseudoVREMU_VX_M1_E32, VREMU_VX, 0x0, 0x20 }, // 7033 |
13025 | | { PseudoVREMU_VX_M1_E32_MASK, VREMU_VX, 0x0, 0x20 }, // 7034 |
13026 | | { PseudoVREMU_VX_M1_E64, VREMU_VX, 0x0, 0x40 }, // 7035 |
13027 | | { PseudoVREMU_VX_M1_E64_MASK, VREMU_VX, 0x0, 0x40 }, // 7036 |
13028 | | { PseudoVREMU_VX_M2_E8, VREMU_VX, 0x1, 0x8 }, // 7037 |
13029 | | { PseudoVREMU_VX_M2_E8_MASK, VREMU_VX, 0x1, 0x8 }, // 7038 |
13030 | | { PseudoVREMU_VX_M2_E16, VREMU_VX, 0x1, 0x10 }, // 7039 |
13031 | | { PseudoVREMU_VX_M2_E16_MASK, VREMU_VX, 0x1, 0x10 }, // 7040 |
13032 | | { PseudoVREMU_VX_M2_E32, VREMU_VX, 0x1, 0x20 }, // 7041 |
13033 | | { PseudoVREMU_VX_M2_E32_MASK, VREMU_VX, 0x1, 0x20 }, // 7042 |
13034 | | { PseudoVREMU_VX_M2_E64, VREMU_VX, 0x1, 0x40 }, // 7043 |
13035 | | { PseudoVREMU_VX_M2_E64_MASK, VREMU_VX, 0x1, 0x40 }, // 7044 |
13036 | | { PseudoVREMU_VX_M4_E8, VREMU_VX, 0x2, 0x8 }, // 7045 |
13037 | | { PseudoVREMU_VX_M4_E8_MASK, VREMU_VX, 0x2, 0x8 }, // 7046 |
13038 | | { PseudoVREMU_VX_M4_E16, VREMU_VX, 0x2, 0x10 }, // 7047 |
13039 | | { PseudoVREMU_VX_M4_E16_MASK, VREMU_VX, 0x2, 0x10 }, // 7048 |
13040 | | { PseudoVREMU_VX_M4_E32, VREMU_VX, 0x2, 0x20 }, // 7049 |
13041 | | { PseudoVREMU_VX_M4_E32_MASK, VREMU_VX, 0x2, 0x20 }, // 7050 |
13042 | | { PseudoVREMU_VX_M4_E64, VREMU_VX, 0x2, 0x40 }, // 7051 |
13043 | | { PseudoVREMU_VX_M4_E64_MASK, VREMU_VX, 0x2, 0x40 }, // 7052 |
13044 | | { PseudoVREMU_VX_M8_E8, VREMU_VX, 0x3, 0x8 }, // 7053 |
13045 | | { PseudoVREMU_VX_M8_E8_MASK, VREMU_VX, 0x3, 0x8 }, // 7054 |
13046 | | { PseudoVREMU_VX_M8_E16, VREMU_VX, 0x3, 0x10 }, // 7055 |
13047 | | { PseudoVREMU_VX_M8_E16_MASK, VREMU_VX, 0x3, 0x10 }, // 7056 |
13048 | | { PseudoVREMU_VX_M8_E32, VREMU_VX, 0x3, 0x20 }, // 7057 |
13049 | | { PseudoVREMU_VX_M8_E32_MASK, VREMU_VX, 0x3, 0x20 }, // 7058 |
13050 | | { PseudoVREMU_VX_M8_E64, VREMU_VX, 0x3, 0x40 }, // 7059 |
13051 | | { PseudoVREMU_VX_M8_E64_MASK, VREMU_VX, 0x3, 0x40 }, // 7060 |
13052 | | { PseudoVREMU_VX_MF8_E8, VREMU_VX, 0x5, 0x8 }, // 7061 |
13053 | | { PseudoVREMU_VX_MF8_E8_MASK, VREMU_VX, 0x5, 0x8 }, // 7062 |
13054 | | { PseudoVREMU_VX_MF4_E8, VREMU_VX, 0x6, 0x8 }, // 7063 |
13055 | | { PseudoVREMU_VX_MF4_E8_MASK, VREMU_VX, 0x6, 0x8 }, // 7064 |
13056 | | { PseudoVREMU_VX_MF4_E16, VREMU_VX, 0x6, 0x10 }, // 7065 |
13057 | | { PseudoVREMU_VX_MF4_E16_MASK, VREMU_VX, 0x6, 0x10 }, // 7066 |
13058 | | { PseudoVREMU_VX_MF2_E8, VREMU_VX, 0x7, 0x8 }, // 7067 |
13059 | | { PseudoVREMU_VX_MF2_E8_MASK, VREMU_VX, 0x7, 0x8 }, // 7068 |
13060 | | { PseudoVREMU_VX_MF2_E16, VREMU_VX, 0x7, 0x10 }, // 7069 |
13061 | | { PseudoVREMU_VX_MF2_E16_MASK, VREMU_VX, 0x7, 0x10 }, // 7070 |
13062 | | { PseudoVREMU_VX_MF2_E32, VREMU_VX, 0x7, 0x20 }, // 7071 |
13063 | | { PseudoVREMU_VX_MF2_E32_MASK, VREMU_VX, 0x7, 0x20 }, // 7072 |
13064 | | { PseudoVREM_VV_M1_E8, VREM_VV, 0x0, 0x8 }, // 7073 |
13065 | | { PseudoVREM_VV_M1_E8_MASK, VREM_VV, 0x0, 0x8 }, // 7074 |
13066 | | { PseudoVREM_VV_M1_E16, VREM_VV, 0x0, 0x10 }, // 7075 |
13067 | | { PseudoVREM_VV_M1_E16_MASK, VREM_VV, 0x0, 0x10 }, // 7076 |
13068 | | { PseudoVREM_VV_M1_E32, VREM_VV, 0x0, 0x20 }, // 7077 |
13069 | | { PseudoVREM_VV_M1_E32_MASK, VREM_VV, 0x0, 0x20 }, // 7078 |
13070 | | { PseudoVREM_VV_M1_E64, VREM_VV, 0x0, 0x40 }, // 7079 |
13071 | | { PseudoVREM_VV_M1_E64_MASK, VREM_VV, 0x0, 0x40 }, // 7080 |
13072 | | { PseudoVREM_VV_M2_E8, VREM_VV, 0x1, 0x8 }, // 7081 |
13073 | | { PseudoVREM_VV_M2_E8_MASK, VREM_VV, 0x1, 0x8 }, // 7082 |
13074 | | { PseudoVREM_VV_M2_E16, VREM_VV, 0x1, 0x10 }, // 7083 |
13075 | | { PseudoVREM_VV_M2_E16_MASK, VREM_VV, 0x1, 0x10 }, // 7084 |
13076 | | { PseudoVREM_VV_M2_E32, VREM_VV, 0x1, 0x20 }, // 7085 |
13077 | | { PseudoVREM_VV_M2_E32_MASK, VREM_VV, 0x1, 0x20 }, // 7086 |
13078 | | { PseudoVREM_VV_M2_E64, VREM_VV, 0x1, 0x40 }, // 7087 |
13079 | | { PseudoVREM_VV_M2_E64_MASK, VREM_VV, 0x1, 0x40 }, // 7088 |
13080 | | { PseudoVREM_VV_M4_E8, VREM_VV, 0x2, 0x8 }, // 7089 |
13081 | | { PseudoVREM_VV_M4_E8_MASK, VREM_VV, 0x2, 0x8 }, // 7090 |
13082 | | { PseudoVREM_VV_M4_E16, VREM_VV, 0x2, 0x10 }, // 7091 |
13083 | | { PseudoVREM_VV_M4_E16_MASK, VREM_VV, 0x2, 0x10 }, // 7092 |
13084 | | { PseudoVREM_VV_M4_E32, VREM_VV, 0x2, 0x20 }, // 7093 |
13085 | | { PseudoVREM_VV_M4_E32_MASK, VREM_VV, 0x2, 0x20 }, // 7094 |
13086 | | { PseudoVREM_VV_M4_E64, VREM_VV, 0x2, 0x40 }, // 7095 |
13087 | | { PseudoVREM_VV_M4_E64_MASK, VREM_VV, 0x2, 0x40 }, // 7096 |
13088 | | { PseudoVREM_VV_M8_E8, VREM_VV, 0x3, 0x8 }, // 7097 |
13089 | | { PseudoVREM_VV_M8_E8_MASK, VREM_VV, 0x3, 0x8 }, // 7098 |
13090 | | { PseudoVREM_VV_M8_E16, VREM_VV, 0x3, 0x10 }, // 7099 |
13091 | | { PseudoVREM_VV_M8_E16_MASK, VREM_VV, 0x3, 0x10 }, // 7100 |
13092 | | { PseudoVREM_VV_M8_E32, VREM_VV, 0x3, 0x20 }, // 7101 |
13093 | | { PseudoVREM_VV_M8_E32_MASK, VREM_VV, 0x3, 0x20 }, // 7102 |
13094 | | { PseudoVREM_VV_M8_E64, VREM_VV, 0x3, 0x40 }, // 7103 |
13095 | | { PseudoVREM_VV_M8_E64_MASK, VREM_VV, 0x3, 0x40 }, // 7104 |
13096 | | { PseudoVREM_VV_MF8_E8, VREM_VV, 0x5, 0x8 }, // 7105 |
13097 | | { PseudoVREM_VV_MF8_E8_MASK, VREM_VV, 0x5, 0x8 }, // 7106 |
13098 | | { PseudoVREM_VV_MF4_E8, VREM_VV, 0x6, 0x8 }, // 7107 |
13099 | | { PseudoVREM_VV_MF4_E8_MASK, VREM_VV, 0x6, 0x8 }, // 7108 |
13100 | | { PseudoVREM_VV_MF4_E16, VREM_VV, 0x6, 0x10 }, // 7109 |
13101 | | { PseudoVREM_VV_MF4_E16_MASK, VREM_VV, 0x6, 0x10 }, // 7110 |
13102 | | { PseudoVREM_VV_MF2_E8, VREM_VV, 0x7, 0x8 }, // 7111 |
13103 | | { PseudoVREM_VV_MF2_E8_MASK, VREM_VV, 0x7, 0x8 }, // 7112 |
13104 | | { PseudoVREM_VV_MF2_E16, VREM_VV, 0x7, 0x10 }, // 7113 |
13105 | | { PseudoVREM_VV_MF2_E16_MASK, VREM_VV, 0x7, 0x10 }, // 7114 |
13106 | | { PseudoVREM_VV_MF2_E32, VREM_VV, 0x7, 0x20 }, // 7115 |
13107 | | { PseudoVREM_VV_MF2_E32_MASK, VREM_VV, 0x7, 0x20 }, // 7116 |
13108 | | { PseudoVREM_VX_M1_E8, VREM_VX, 0x0, 0x8 }, // 7117 |
13109 | | { PseudoVREM_VX_M1_E8_MASK, VREM_VX, 0x0, 0x8 }, // 7118 |
13110 | | { PseudoVREM_VX_M1_E16, VREM_VX, 0x0, 0x10 }, // 7119 |
13111 | | { PseudoVREM_VX_M1_E16_MASK, VREM_VX, 0x0, 0x10 }, // 7120 |
13112 | | { PseudoVREM_VX_M1_E32, VREM_VX, 0x0, 0x20 }, // 7121 |
13113 | | { PseudoVREM_VX_M1_E32_MASK, VREM_VX, 0x0, 0x20 }, // 7122 |
13114 | | { PseudoVREM_VX_M1_E64, VREM_VX, 0x0, 0x40 }, // 7123 |
13115 | | { PseudoVREM_VX_M1_E64_MASK, VREM_VX, 0x0, 0x40 }, // 7124 |
13116 | | { PseudoVREM_VX_M2_E8, VREM_VX, 0x1, 0x8 }, // 7125 |
13117 | | { PseudoVREM_VX_M2_E8_MASK, VREM_VX, 0x1, 0x8 }, // 7126 |
13118 | | { PseudoVREM_VX_M2_E16, VREM_VX, 0x1, 0x10 }, // 7127 |
13119 | | { PseudoVREM_VX_M2_E16_MASK, VREM_VX, 0x1, 0x10 }, // 7128 |
13120 | | { PseudoVREM_VX_M2_E32, VREM_VX, 0x1, 0x20 }, // 7129 |
13121 | | { PseudoVREM_VX_M2_E32_MASK, VREM_VX, 0x1, 0x20 }, // 7130 |
13122 | | { PseudoVREM_VX_M2_E64, VREM_VX, 0x1, 0x40 }, // 7131 |
13123 | | { PseudoVREM_VX_M2_E64_MASK, VREM_VX, 0x1, 0x40 }, // 7132 |
13124 | | { PseudoVREM_VX_M4_E8, VREM_VX, 0x2, 0x8 }, // 7133 |
13125 | | { PseudoVREM_VX_M4_E8_MASK, VREM_VX, 0x2, 0x8 }, // 7134 |
13126 | | { PseudoVREM_VX_M4_E16, VREM_VX, 0x2, 0x10 }, // 7135 |
13127 | | { PseudoVREM_VX_M4_E16_MASK, VREM_VX, 0x2, 0x10 }, // 7136 |
13128 | | { PseudoVREM_VX_M4_E32, VREM_VX, 0x2, 0x20 }, // 7137 |
13129 | | { PseudoVREM_VX_M4_E32_MASK, VREM_VX, 0x2, 0x20 }, // 7138 |
13130 | | { PseudoVREM_VX_M4_E64, VREM_VX, 0x2, 0x40 }, // 7139 |
13131 | | { PseudoVREM_VX_M4_E64_MASK, VREM_VX, 0x2, 0x40 }, // 7140 |
13132 | | { PseudoVREM_VX_M8_E8, VREM_VX, 0x3, 0x8 }, // 7141 |
13133 | | { PseudoVREM_VX_M8_E8_MASK, VREM_VX, 0x3, 0x8 }, // 7142 |
13134 | | { PseudoVREM_VX_M8_E16, VREM_VX, 0x3, 0x10 }, // 7143 |
13135 | | { PseudoVREM_VX_M8_E16_MASK, VREM_VX, 0x3, 0x10 }, // 7144 |
13136 | | { PseudoVREM_VX_M8_E32, VREM_VX, 0x3, 0x20 }, // 7145 |
13137 | | { PseudoVREM_VX_M8_E32_MASK, VREM_VX, 0x3, 0x20 }, // 7146 |
13138 | | { PseudoVREM_VX_M8_E64, VREM_VX, 0x3, 0x40 }, // 7147 |
13139 | | { PseudoVREM_VX_M8_E64_MASK, VREM_VX, 0x3, 0x40 }, // 7148 |
13140 | | { PseudoVREM_VX_MF8_E8, VREM_VX, 0x5, 0x8 }, // 7149 |
13141 | | { PseudoVREM_VX_MF8_E8_MASK, VREM_VX, 0x5, 0x8 }, // 7150 |
13142 | | { PseudoVREM_VX_MF4_E8, VREM_VX, 0x6, 0x8 }, // 7151 |
13143 | | { PseudoVREM_VX_MF4_E8_MASK, VREM_VX, 0x6, 0x8 }, // 7152 |
13144 | | { PseudoVREM_VX_MF4_E16, VREM_VX, 0x6, 0x10 }, // 7153 |
13145 | | { PseudoVREM_VX_MF4_E16_MASK, VREM_VX, 0x6, 0x10 }, // 7154 |
13146 | | { PseudoVREM_VX_MF2_E8, VREM_VX, 0x7, 0x8 }, // 7155 |
13147 | | { PseudoVREM_VX_MF2_E8_MASK, VREM_VX, 0x7, 0x8 }, // 7156 |
13148 | | { PseudoVREM_VX_MF2_E16, VREM_VX, 0x7, 0x10 }, // 7157 |
13149 | | { PseudoVREM_VX_MF2_E16_MASK, VREM_VX, 0x7, 0x10 }, // 7158 |
13150 | | { PseudoVREM_VX_MF2_E32, VREM_VX, 0x7, 0x20 }, // 7159 |
13151 | | { PseudoVREM_VX_MF2_E32_MASK, VREM_VX, 0x7, 0x20 }, // 7160 |
13152 | | { PseudoVREV8_V_M1, VREV8_V, 0x0, 0x0 }, // 7161 |
13153 | | { PseudoVREV8_V_M1_MASK, VREV8_V, 0x0, 0x0 }, // 7162 |
13154 | | { PseudoVREV8_V_M2, VREV8_V, 0x1, 0x0 }, // 7163 |
13155 | | { PseudoVREV8_V_M2_MASK, VREV8_V, 0x1, 0x0 }, // 7164 |
13156 | | { PseudoVREV8_V_M4, VREV8_V, 0x2, 0x0 }, // 7165 |
13157 | | { PseudoVREV8_V_M4_MASK, VREV8_V, 0x2, 0x0 }, // 7166 |
13158 | | { PseudoVREV8_V_M8, VREV8_V, 0x3, 0x0 }, // 7167 |
13159 | | { PseudoVREV8_V_M8_MASK, VREV8_V, 0x3, 0x0 }, // 7168 |
13160 | | { PseudoVREV8_V_MF8, VREV8_V, 0x5, 0x0 }, // 7169 |
13161 | | { PseudoVREV8_V_MF8_MASK, VREV8_V, 0x5, 0x0 }, // 7170 |
13162 | | { PseudoVREV8_V_MF4, VREV8_V, 0x6, 0x0 }, // 7171 |
13163 | | { PseudoVREV8_V_MF4_MASK, VREV8_V, 0x6, 0x0 }, // 7172 |
13164 | | { PseudoVREV8_V_MF2, VREV8_V, 0x7, 0x0 }, // 7173 |
13165 | | { PseudoVREV8_V_MF2_MASK, VREV8_V, 0x7, 0x0 }, // 7174 |
13166 | | { PseudoVRGATHEREI16_VV_M1_E8_M1, VRGATHEREI16_VV, 0x0, 0x8 }, // 7175 |
13167 | | { PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7176 |
13168 | | { PseudoVRGATHEREI16_VV_M1_E8_M2, VRGATHEREI16_VV, 0x0, 0x8 }, // 7177 |
13169 | | { PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7178 |
13170 | | { PseudoVRGATHEREI16_VV_M1_E8_MF2, VRGATHEREI16_VV, 0x0, 0x8 }, // 7179 |
13171 | | { PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7180 |
13172 | | { PseudoVRGATHEREI16_VV_M1_E8_MF4, VRGATHEREI16_VV, 0x0, 0x8 }, // 7181 |
13173 | | { PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x8 }, // 7182 |
13174 | | { PseudoVRGATHEREI16_VV_M1_E16_M1, VRGATHEREI16_VV, 0x0, 0x10 }, // 7183 |
13175 | | { PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7184 |
13176 | | { PseudoVRGATHEREI16_VV_M1_E16_M2, VRGATHEREI16_VV, 0x0, 0x10 }, // 7185 |
13177 | | { PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7186 |
13178 | | { PseudoVRGATHEREI16_VV_M1_E16_MF2, VRGATHEREI16_VV, 0x0, 0x10 }, // 7187 |
13179 | | { PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7188 |
13180 | | { PseudoVRGATHEREI16_VV_M1_E16_MF4, VRGATHEREI16_VV, 0x0, 0x10 }, // 7189 |
13181 | | { PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x10 }, // 7190 |
13182 | | { PseudoVRGATHEREI16_VV_M1_E32_M1, VRGATHEREI16_VV, 0x0, 0x20 }, // 7191 |
13183 | | { PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7192 |
13184 | | { PseudoVRGATHEREI16_VV_M1_E32_M2, VRGATHEREI16_VV, 0x0, 0x20 }, // 7193 |
13185 | | { PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7194 |
13186 | | { PseudoVRGATHEREI16_VV_M1_E32_MF2, VRGATHEREI16_VV, 0x0, 0x20 }, // 7195 |
13187 | | { PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7196 |
13188 | | { PseudoVRGATHEREI16_VV_M1_E32_MF4, VRGATHEREI16_VV, 0x0, 0x20 }, // 7197 |
13189 | | { PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x20 }, // 7198 |
13190 | | { PseudoVRGATHEREI16_VV_M1_E64_M1, VRGATHEREI16_VV, 0x0, 0x40 }, // 7199 |
13191 | | { PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7200 |
13192 | | { PseudoVRGATHEREI16_VV_M1_E64_M2, VRGATHEREI16_VV, 0x0, 0x40 }, // 7201 |
13193 | | { PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7202 |
13194 | | { PseudoVRGATHEREI16_VV_M1_E64_MF2, VRGATHEREI16_VV, 0x0, 0x40 }, // 7203 |
13195 | | { PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7204 |
13196 | | { PseudoVRGATHEREI16_VV_M1_E64_MF4, VRGATHEREI16_VV, 0x0, 0x40 }, // 7205 |
13197 | | { PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, VRGATHEREI16_VV, 0x0, 0x40 }, // 7206 |
13198 | | { PseudoVRGATHEREI16_VV_M2_E8_M1, VRGATHEREI16_VV, 0x1, 0x8 }, // 7207 |
13199 | | { PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7208 |
13200 | | { PseudoVRGATHEREI16_VV_M2_E8_M2, VRGATHEREI16_VV, 0x1, 0x8 }, // 7209 |
13201 | | { PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7210 |
13202 | | { PseudoVRGATHEREI16_VV_M2_E8_M4, VRGATHEREI16_VV, 0x1, 0x8 }, // 7211 |
13203 | | { PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7212 |
13204 | | { PseudoVRGATHEREI16_VV_M2_E8_MF2, VRGATHEREI16_VV, 0x1, 0x8 }, // 7213 |
13205 | | { PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x8 }, // 7214 |
13206 | | { PseudoVRGATHEREI16_VV_M2_E16_M1, VRGATHEREI16_VV, 0x1, 0x10 }, // 7215 |
13207 | | { PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7216 |
13208 | | { PseudoVRGATHEREI16_VV_M2_E16_M2, VRGATHEREI16_VV, 0x1, 0x10 }, // 7217 |
13209 | | { PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7218 |
13210 | | { PseudoVRGATHEREI16_VV_M2_E16_M4, VRGATHEREI16_VV, 0x1, 0x10 }, // 7219 |
13211 | | { PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7220 |
13212 | | { PseudoVRGATHEREI16_VV_M2_E16_MF2, VRGATHEREI16_VV, 0x1, 0x10 }, // 7221 |
13213 | | { PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x10 }, // 7222 |
13214 | | { PseudoVRGATHEREI16_VV_M2_E32_M1, VRGATHEREI16_VV, 0x1, 0x20 }, // 7223 |
13215 | | { PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7224 |
13216 | | { PseudoVRGATHEREI16_VV_M2_E32_M2, VRGATHEREI16_VV, 0x1, 0x20 }, // 7225 |
13217 | | { PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7226 |
13218 | | { PseudoVRGATHEREI16_VV_M2_E32_M4, VRGATHEREI16_VV, 0x1, 0x20 }, // 7227 |
13219 | | { PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7228 |
13220 | | { PseudoVRGATHEREI16_VV_M2_E32_MF2, VRGATHEREI16_VV, 0x1, 0x20 }, // 7229 |
13221 | | { PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x20 }, // 7230 |
13222 | | { PseudoVRGATHEREI16_VV_M2_E64_M1, VRGATHEREI16_VV, 0x1, 0x40 }, // 7231 |
13223 | | { PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7232 |
13224 | | { PseudoVRGATHEREI16_VV_M2_E64_M2, VRGATHEREI16_VV, 0x1, 0x40 }, // 7233 |
13225 | | { PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7234 |
13226 | | { PseudoVRGATHEREI16_VV_M2_E64_M4, VRGATHEREI16_VV, 0x1, 0x40 }, // 7235 |
13227 | | { PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7236 |
13228 | | { PseudoVRGATHEREI16_VV_M2_E64_MF2, VRGATHEREI16_VV, 0x1, 0x40 }, // 7237 |
13229 | | { PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, VRGATHEREI16_VV, 0x1, 0x40 }, // 7238 |
13230 | | { PseudoVRGATHEREI16_VV_M4_E8_M1, VRGATHEREI16_VV, 0x2, 0x8 }, // 7239 |
13231 | | { PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7240 |
13232 | | { PseudoVRGATHEREI16_VV_M4_E8_M2, VRGATHEREI16_VV, 0x2, 0x8 }, // 7241 |
13233 | | { PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7242 |
13234 | | { PseudoVRGATHEREI16_VV_M4_E8_M4, VRGATHEREI16_VV, 0x2, 0x8 }, // 7243 |
13235 | | { PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7244 |
13236 | | { PseudoVRGATHEREI16_VV_M4_E8_M8, VRGATHEREI16_VV, 0x2, 0x8 }, // 7245 |
13237 | | { PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, VRGATHEREI16_VV, 0x2, 0x8 }, // 7246 |
13238 | | { PseudoVRGATHEREI16_VV_M4_E16_M1, VRGATHEREI16_VV, 0x2, 0x10 }, // 7247 |
13239 | | { PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7248 |
13240 | | { PseudoVRGATHEREI16_VV_M4_E16_M2, VRGATHEREI16_VV, 0x2, 0x10 }, // 7249 |
13241 | | { PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7250 |
13242 | | { PseudoVRGATHEREI16_VV_M4_E16_M4, VRGATHEREI16_VV, 0x2, 0x10 }, // 7251 |
13243 | | { PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7252 |
13244 | | { PseudoVRGATHEREI16_VV_M4_E16_M8, VRGATHEREI16_VV, 0x2, 0x10 }, // 7253 |
13245 | | { PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, VRGATHEREI16_VV, 0x2, 0x10 }, // 7254 |
13246 | | { PseudoVRGATHEREI16_VV_M4_E32_M1, VRGATHEREI16_VV, 0x2, 0x20 }, // 7255 |
13247 | | { PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7256 |
13248 | | { PseudoVRGATHEREI16_VV_M4_E32_M2, VRGATHEREI16_VV, 0x2, 0x20 }, // 7257 |
13249 | | { PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7258 |
13250 | | { PseudoVRGATHEREI16_VV_M4_E32_M4, VRGATHEREI16_VV, 0x2, 0x20 }, // 7259 |
13251 | | { PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7260 |
13252 | | { PseudoVRGATHEREI16_VV_M4_E32_M8, VRGATHEREI16_VV, 0x2, 0x20 }, // 7261 |
13253 | | { PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, VRGATHEREI16_VV, 0x2, 0x20 }, // 7262 |
13254 | | { PseudoVRGATHEREI16_VV_M4_E64_M1, VRGATHEREI16_VV, 0x2, 0x40 }, // 7263 |
13255 | | { PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7264 |
13256 | | { PseudoVRGATHEREI16_VV_M4_E64_M2, VRGATHEREI16_VV, 0x2, 0x40 }, // 7265 |
13257 | | { PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7266 |
13258 | | { PseudoVRGATHEREI16_VV_M4_E64_M4, VRGATHEREI16_VV, 0x2, 0x40 }, // 7267 |
13259 | | { PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7268 |
13260 | | { PseudoVRGATHEREI16_VV_M4_E64_M8, VRGATHEREI16_VV, 0x2, 0x40 }, // 7269 |
13261 | | { PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, VRGATHEREI16_VV, 0x2, 0x40 }, // 7270 |
13262 | | { PseudoVRGATHEREI16_VV_M8_E8_M2, VRGATHEREI16_VV, 0x3, 0x8 }, // 7271 |
13263 | | { PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, VRGATHEREI16_VV, 0x3, 0x8 }, // 7272 |
13264 | | { PseudoVRGATHEREI16_VV_M8_E8_M4, VRGATHEREI16_VV, 0x3, 0x8 }, // 7273 |
13265 | | { PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, VRGATHEREI16_VV, 0x3, 0x8 }, // 7274 |
13266 | | { PseudoVRGATHEREI16_VV_M8_E8_M8, VRGATHEREI16_VV, 0x3, 0x8 }, // 7275 |
13267 | | { PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, VRGATHEREI16_VV, 0x3, 0x8 }, // 7276 |
13268 | | { PseudoVRGATHEREI16_VV_M8_E16_M2, VRGATHEREI16_VV, 0x3, 0x10 }, // 7277 |
13269 | | { PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, VRGATHEREI16_VV, 0x3, 0x10 }, // 7278 |
13270 | | { PseudoVRGATHEREI16_VV_M8_E16_M4, VRGATHEREI16_VV, 0x3, 0x10 }, // 7279 |
13271 | | { PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, VRGATHEREI16_VV, 0x3, 0x10 }, // 7280 |
13272 | | { PseudoVRGATHEREI16_VV_M8_E16_M8, VRGATHEREI16_VV, 0x3, 0x10 }, // 7281 |
13273 | | { PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, VRGATHEREI16_VV, 0x3, 0x10 }, // 7282 |
13274 | | { PseudoVRGATHEREI16_VV_M8_E32_M2, VRGATHEREI16_VV, 0x3, 0x20 }, // 7283 |
13275 | | { PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, VRGATHEREI16_VV, 0x3, 0x20 }, // 7284 |
13276 | | { PseudoVRGATHEREI16_VV_M8_E32_M4, VRGATHEREI16_VV, 0x3, 0x20 }, // 7285 |
13277 | | { PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, VRGATHEREI16_VV, 0x3, 0x20 }, // 7286 |
13278 | | { PseudoVRGATHEREI16_VV_M8_E32_M8, VRGATHEREI16_VV, 0x3, 0x20 }, // 7287 |
13279 | | { PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, VRGATHEREI16_VV, 0x3, 0x20 }, // 7288 |
13280 | | { PseudoVRGATHEREI16_VV_M8_E64_M2, VRGATHEREI16_VV, 0x3, 0x40 }, // 7289 |
13281 | | { PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, VRGATHEREI16_VV, 0x3, 0x40 }, // 7290 |
13282 | | { PseudoVRGATHEREI16_VV_M8_E64_M4, VRGATHEREI16_VV, 0x3, 0x40 }, // 7291 |
13283 | | { PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, VRGATHEREI16_VV, 0x3, 0x40 }, // 7292 |
13284 | | { PseudoVRGATHEREI16_VV_M8_E64_M8, VRGATHEREI16_VV, 0x3, 0x40 }, // 7293 |
13285 | | { PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, VRGATHEREI16_VV, 0x3, 0x40 }, // 7294 |
13286 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF4, VRGATHEREI16_VV, 0x5, 0x8 }, // 7295 |
13287 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, VRGATHEREI16_VV, 0x5, 0x8 }, // 7296 |
13288 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF8, VRGATHEREI16_VV, 0x5, 0x8 }, // 7297 |
13289 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, VRGATHEREI16_VV, 0x5, 0x8 }, // 7298 |
13290 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF2, VRGATHEREI16_VV, 0x6, 0x8 }, // 7299 |
13291 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, VRGATHEREI16_VV, 0x6, 0x8 }, // 7300 |
13292 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF4, VRGATHEREI16_VV, 0x6, 0x8 }, // 7301 |
13293 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, VRGATHEREI16_VV, 0x6, 0x8 }, // 7302 |
13294 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF8, VRGATHEREI16_VV, 0x6, 0x8 }, // 7303 |
13295 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, VRGATHEREI16_VV, 0x6, 0x8 }, // 7304 |
13296 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF2, VRGATHEREI16_VV, 0x6, 0x10 }, // 7305 |
13297 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, VRGATHEREI16_VV, 0x6, 0x10 }, // 7306 |
13298 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF4, VRGATHEREI16_VV, 0x6, 0x10 }, // 7307 |
13299 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, VRGATHEREI16_VV, 0x6, 0x10 }, // 7308 |
13300 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF8, VRGATHEREI16_VV, 0x6, 0x10 }, // 7309 |
13301 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, VRGATHEREI16_VV, 0x6, 0x10 }, // 7310 |
13302 | | { PseudoVRGATHEREI16_VV_MF2_E8_M1, VRGATHEREI16_VV, 0x7, 0x8 }, // 7311 |
13303 | | { PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7312 |
13304 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF2, VRGATHEREI16_VV, 0x7, 0x8 }, // 7313 |
13305 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7314 |
13306 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF4, VRGATHEREI16_VV, 0x7, 0x8 }, // 7315 |
13307 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7316 |
13308 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF8, VRGATHEREI16_VV, 0x7, 0x8 }, // 7317 |
13309 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, VRGATHEREI16_VV, 0x7, 0x8 }, // 7318 |
13310 | | { PseudoVRGATHEREI16_VV_MF2_E16_M1, VRGATHEREI16_VV, 0x7, 0x10 }, // 7319 |
13311 | | { PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7320 |
13312 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF2, VRGATHEREI16_VV, 0x7, 0x10 }, // 7321 |
13313 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7322 |
13314 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF4, VRGATHEREI16_VV, 0x7, 0x10 }, // 7323 |
13315 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7324 |
13316 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF8, VRGATHEREI16_VV, 0x7, 0x10 }, // 7325 |
13317 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, VRGATHEREI16_VV, 0x7, 0x10 }, // 7326 |
13318 | | { PseudoVRGATHEREI16_VV_MF2_E32_M1, VRGATHEREI16_VV, 0x7, 0x20 }, // 7327 |
13319 | | { PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7328 |
13320 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF2, VRGATHEREI16_VV, 0x7, 0x20 }, // 7329 |
13321 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7330 |
13322 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF4, VRGATHEREI16_VV, 0x7, 0x20 }, // 7331 |
13323 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7332 |
13324 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF8, VRGATHEREI16_VV, 0x7, 0x20 }, // 7333 |
13325 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, VRGATHEREI16_VV, 0x7, 0x20 }, // 7334 |
13326 | | { PseudoVRGATHER_VI_M1, VRGATHER_VI, 0x0, 0x0 }, // 7335 |
13327 | | { PseudoVRGATHER_VI_M1_MASK, VRGATHER_VI, 0x0, 0x0 }, // 7336 |
13328 | | { PseudoVRGATHER_VI_M2, VRGATHER_VI, 0x1, 0x0 }, // 7337 |
13329 | | { PseudoVRGATHER_VI_M2_MASK, VRGATHER_VI, 0x1, 0x0 }, // 7338 |
13330 | | { PseudoVRGATHER_VI_M4, VRGATHER_VI, 0x2, 0x0 }, // 7339 |
13331 | | { PseudoVRGATHER_VI_M4_MASK, VRGATHER_VI, 0x2, 0x0 }, // 7340 |
13332 | | { PseudoVRGATHER_VI_M8, VRGATHER_VI, 0x3, 0x0 }, // 7341 |
13333 | | { PseudoVRGATHER_VI_M8_MASK, VRGATHER_VI, 0x3, 0x0 }, // 7342 |
13334 | | { PseudoVRGATHER_VI_MF8, VRGATHER_VI, 0x5, 0x0 }, // 7343 |
13335 | | { PseudoVRGATHER_VI_MF8_MASK, VRGATHER_VI, 0x5, 0x0 }, // 7344 |
13336 | | { PseudoVRGATHER_VI_MF4, VRGATHER_VI, 0x6, 0x0 }, // 7345 |
13337 | | { PseudoVRGATHER_VI_MF4_MASK, VRGATHER_VI, 0x6, 0x0 }, // 7346 |
13338 | | { PseudoVRGATHER_VI_MF2, VRGATHER_VI, 0x7, 0x0 }, // 7347 |
13339 | | { PseudoVRGATHER_VI_MF2_MASK, VRGATHER_VI, 0x7, 0x0 }, // 7348 |
13340 | | { PseudoVRGATHER_VV_M1_E8, VRGATHER_VV, 0x0, 0x8 }, // 7349 |
13341 | | { PseudoVRGATHER_VV_M1_E8_MASK, VRGATHER_VV, 0x0, 0x8 }, // 7350 |
13342 | | { PseudoVRGATHER_VV_M1_E16, VRGATHER_VV, 0x0, 0x10 }, // 7351 |
13343 | | { PseudoVRGATHER_VV_M1_E16_MASK, VRGATHER_VV, 0x0, 0x10 }, // 7352 |
13344 | | { PseudoVRGATHER_VV_M1_E32, VRGATHER_VV, 0x0, 0x20 }, // 7353 |
13345 | | { PseudoVRGATHER_VV_M1_E32_MASK, VRGATHER_VV, 0x0, 0x20 }, // 7354 |
13346 | | { PseudoVRGATHER_VV_M1_E64, VRGATHER_VV, 0x0, 0x40 }, // 7355 |
13347 | | { PseudoVRGATHER_VV_M1_E64_MASK, VRGATHER_VV, 0x0, 0x40 }, // 7356 |
13348 | | { PseudoVRGATHER_VV_M2_E8, VRGATHER_VV, 0x1, 0x8 }, // 7357 |
13349 | | { PseudoVRGATHER_VV_M2_E8_MASK, VRGATHER_VV, 0x1, 0x8 }, // 7358 |
13350 | | { PseudoVRGATHER_VV_M2_E16, VRGATHER_VV, 0x1, 0x10 }, // 7359 |
13351 | | { PseudoVRGATHER_VV_M2_E16_MASK, VRGATHER_VV, 0x1, 0x10 }, // 7360 |
13352 | | { PseudoVRGATHER_VV_M2_E32, VRGATHER_VV, 0x1, 0x20 }, // 7361 |
13353 | | { PseudoVRGATHER_VV_M2_E32_MASK, VRGATHER_VV, 0x1, 0x20 }, // 7362 |
13354 | | { PseudoVRGATHER_VV_M2_E64, VRGATHER_VV, 0x1, 0x40 }, // 7363 |
13355 | | { PseudoVRGATHER_VV_M2_E64_MASK, VRGATHER_VV, 0x1, 0x40 }, // 7364 |
13356 | | { PseudoVRGATHER_VV_M4_E8, VRGATHER_VV, 0x2, 0x8 }, // 7365 |
13357 | | { PseudoVRGATHER_VV_M4_E8_MASK, VRGATHER_VV, 0x2, 0x8 }, // 7366 |
13358 | | { PseudoVRGATHER_VV_M4_E16, VRGATHER_VV, 0x2, 0x10 }, // 7367 |
13359 | | { PseudoVRGATHER_VV_M4_E16_MASK, VRGATHER_VV, 0x2, 0x10 }, // 7368 |
13360 | | { PseudoVRGATHER_VV_M4_E32, VRGATHER_VV, 0x2, 0x20 }, // 7369 |
13361 | | { PseudoVRGATHER_VV_M4_E32_MASK, VRGATHER_VV, 0x2, 0x20 }, // 7370 |
13362 | | { PseudoVRGATHER_VV_M4_E64, VRGATHER_VV, 0x2, 0x40 }, // 7371 |
13363 | | { PseudoVRGATHER_VV_M4_E64_MASK, VRGATHER_VV, 0x2, 0x40 }, // 7372 |
13364 | | { PseudoVRGATHER_VV_M8_E8, VRGATHER_VV, 0x3, 0x8 }, // 7373 |
13365 | | { PseudoVRGATHER_VV_M8_E8_MASK, VRGATHER_VV, 0x3, 0x8 }, // 7374 |
13366 | | { PseudoVRGATHER_VV_M8_E16, VRGATHER_VV, 0x3, 0x10 }, // 7375 |
13367 | | { PseudoVRGATHER_VV_M8_E16_MASK, VRGATHER_VV, 0x3, 0x10 }, // 7376 |
13368 | | { PseudoVRGATHER_VV_M8_E32, VRGATHER_VV, 0x3, 0x20 }, // 7377 |
13369 | | { PseudoVRGATHER_VV_M8_E32_MASK, VRGATHER_VV, 0x3, 0x20 }, // 7378 |
13370 | | { PseudoVRGATHER_VV_M8_E64, VRGATHER_VV, 0x3, 0x40 }, // 7379 |
13371 | | { PseudoVRGATHER_VV_M8_E64_MASK, VRGATHER_VV, 0x3, 0x40 }, // 7380 |
13372 | | { PseudoVRGATHER_VV_MF8_E8, VRGATHER_VV, 0x5, 0x8 }, // 7381 |
13373 | | { PseudoVRGATHER_VV_MF8_E8_MASK, VRGATHER_VV, 0x5, 0x8 }, // 7382 |
13374 | | { PseudoVRGATHER_VV_MF4_E8, VRGATHER_VV, 0x6, 0x8 }, // 7383 |
13375 | | { PseudoVRGATHER_VV_MF4_E8_MASK, VRGATHER_VV, 0x6, 0x8 }, // 7384 |
13376 | | { PseudoVRGATHER_VV_MF4_E16, VRGATHER_VV, 0x6, 0x10 }, // 7385 |
13377 | | { PseudoVRGATHER_VV_MF4_E16_MASK, VRGATHER_VV, 0x6, 0x10 }, // 7386 |
13378 | | { PseudoVRGATHER_VV_MF2_E8, VRGATHER_VV, 0x7, 0x8 }, // 7387 |
13379 | | { PseudoVRGATHER_VV_MF2_E8_MASK, VRGATHER_VV, 0x7, 0x8 }, // 7388 |
13380 | | { PseudoVRGATHER_VV_MF2_E16, VRGATHER_VV, 0x7, 0x10 }, // 7389 |
13381 | | { PseudoVRGATHER_VV_MF2_E16_MASK, VRGATHER_VV, 0x7, 0x10 }, // 7390 |
13382 | | { PseudoVRGATHER_VV_MF2_E32, VRGATHER_VV, 0x7, 0x20 }, // 7391 |
13383 | | { PseudoVRGATHER_VV_MF2_E32_MASK, VRGATHER_VV, 0x7, 0x20 }, // 7392 |
13384 | | { PseudoVRGATHER_VX_M1, VRGATHER_VX, 0x0, 0x0 }, // 7393 |
13385 | | { PseudoVRGATHER_VX_M1_MASK, VRGATHER_VX, 0x0, 0x0 }, // 7394 |
13386 | | { PseudoVRGATHER_VX_M2, VRGATHER_VX, 0x1, 0x0 }, // 7395 |
13387 | | { PseudoVRGATHER_VX_M2_MASK, VRGATHER_VX, 0x1, 0x0 }, // 7396 |
13388 | | { PseudoVRGATHER_VX_M4, VRGATHER_VX, 0x2, 0x0 }, // 7397 |
13389 | | { PseudoVRGATHER_VX_M4_MASK, VRGATHER_VX, 0x2, 0x0 }, // 7398 |
13390 | | { PseudoVRGATHER_VX_M8, VRGATHER_VX, 0x3, 0x0 }, // 7399 |
13391 | | { PseudoVRGATHER_VX_M8_MASK, VRGATHER_VX, 0x3, 0x0 }, // 7400 |
13392 | | { PseudoVRGATHER_VX_MF8, VRGATHER_VX, 0x5, 0x0 }, // 7401 |
13393 | | { PseudoVRGATHER_VX_MF8_MASK, VRGATHER_VX, 0x5, 0x0 }, // 7402 |
13394 | | { PseudoVRGATHER_VX_MF4, VRGATHER_VX, 0x6, 0x0 }, // 7403 |
13395 | | { PseudoVRGATHER_VX_MF4_MASK, VRGATHER_VX, 0x6, 0x0 }, // 7404 |
13396 | | { PseudoVRGATHER_VX_MF2, VRGATHER_VX, 0x7, 0x0 }, // 7405 |
13397 | | { PseudoVRGATHER_VX_MF2_MASK, VRGATHER_VX, 0x7, 0x0 }, // 7406 |
13398 | | { PseudoVROL_VV_M1, VROL_VV, 0x0, 0x0 }, // 7407 |
13399 | | { PseudoVROL_VV_M1_MASK, VROL_VV, 0x0, 0x0 }, // 7408 |
13400 | | { PseudoVROL_VV_M2, VROL_VV, 0x1, 0x0 }, // 7409 |
13401 | | { PseudoVROL_VV_M2_MASK, VROL_VV, 0x1, 0x0 }, // 7410 |
13402 | | { PseudoVROL_VV_M4, VROL_VV, 0x2, 0x0 }, // 7411 |
13403 | | { PseudoVROL_VV_M4_MASK, VROL_VV, 0x2, 0x0 }, // 7412 |
13404 | | { PseudoVROL_VV_M8, VROL_VV, 0x3, 0x0 }, // 7413 |
13405 | | { PseudoVROL_VV_M8_MASK, VROL_VV, 0x3, 0x0 }, // 7414 |
13406 | | { PseudoVROL_VV_MF8, VROL_VV, 0x5, 0x0 }, // 7415 |
13407 | | { PseudoVROL_VV_MF8_MASK, VROL_VV, 0x5, 0x0 }, // 7416 |
13408 | | { PseudoVROL_VV_MF4, VROL_VV, 0x6, 0x0 }, // 7417 |
13409 | | { PseudoVROL_VV_MF4_MASK, VROL_VV, 0x6, 0x0 }, // 7418 |
13410 | | { PseudoVROL_VV_MF2, VROL_VV, 0x7, 0x0 }, // 7419 |
13411 | | { PseudoVROL_VV_MF2_MASK, VROL_VV, 0x7, 0x0 }, // 7420 |
13412 | | { PseudoVROL_VX_M1, VROL_VX, 0x0, 0x0 }, // 7421 |
13413 | | { PseudoVROL_VX_M1_MASK, VROL_VX, 0x0, 0x0 }, // 7422 |
13414 | | { PseudoVROL_VX_M2, VROL_VX, 0x1, 0x0 }, // 7423 |
13415 | | { PseudoVROL_VX_M2_MASK, VROL_VX, 0x1, 0x0 }, // 7424 |
13416 | | { PseudoVROL_VX_M4, VROL_VX, 0x2, 0x0 }, // 7425 |
13417 | | { PseudoVROL_VX_M4_MASK, VROL_VX, 0x2, 0x0 }, // 7426 |
13418 | | { PseudoVROL_VX_M8, VROL_VX, 0x3, 0x0 }, // 7427 |
13419 | | { PseudoVROL_VX_M8_MASK, VROL_VX, 0x3, 0x0 }, // 7428 |
13420 | | { PseudoVROL_VX_MF8, VROL_VX, 0x5, 0x0 }, // 7429 |
13421 | | { PseudoVROL_VX_MF8_MASK, VROL_VX, 0x5, 0x0 }, // 7430 |
13422 | | { PseudoVROL_VX_MF4, VROL_VX, 0x6, 0x0 }, // 7431 |
13423 | | { PseudoVROL_VX_MF4_MASK, VROL_VX, 0x6, 0x0 }, // 7432 |
13424 | | { PseudoVROL_VX_MF2, VROL_VX, 0x7, 0x0 }, // 7433 |
13425 | | { PseudoVROL_VX_MF2_MASK, VROL_VX, 0x7, 0x0 }, // 7434 |
13426 | | { PseudoVROR_VI_M1, VROR_VI, 0x0, 0x0 }, // 7435 |
13427 | | { PseudoVROR_VI_M1_MASK, VROR_VI, 0x0, 0x0 }, // 7436 |
13428 | | { PseudoVROR_VI_M2, VROR_VI, 0x1, 0x0 }, // 7437 |
13429 | | { PseudoVROR_VI_M2_MASK, VROR_VI, 0x1, 0x0 }, // 7438 |
13430 | | { PseudoVROR_VI_M4, VROR_VI, 0x2, 0x0 }, // 7439 |
13431 | | { PseudoVROR_VI_M4_MASK, VROR_VI, 0x2, 0x0 }, // 7440 |
13432 | | { PseudoVROR_VI_M8, VROR_VI, 0x3, 0x0 }, // 7441 |
13433 | | { PseudoVROR_VI_M8_MASK, VROR_VI, 0x3, 0x0 }, // 7442 |
13434 | | { PseudoVROR_VI_MF8, VROR_VI, 0x5, 0x0 }, // 7443 |
13435 | | { PseudoVROR_VI_MF8_MASK, VROR_VI, 0x5, 0x0 }, // 7444 |
13436 | | { PseudoVROR_VI_MF4, VROR_VI, 0x6, 0x0 }, // 7445 |
13437 | | { PseudoVROR_VI_MF4_MASK, VROR_VI, 0x6, 0x0 }, // 7446 |
13438 | | { PseudoVROR_VI_MF2, VROR_VI, 0x7, 0x0 }, // 7447 |
13439 | | { PseudoVROR_VI_MF2_MASK, VROR_VI, 0x7, 0x0 }, // 7448 |
13440 | | { PseudoVROR_VV_M1, VROR_VV, 0x0, 0x0 }, // 7449 |
13441 | | { PseudoVROR_VV_M1_MASK, VROR_VV, 0x0, 0x0 }, // 7450 |
13442 | | { PseudoVROR_VV_M2, VROR_VV, 0x1, 0x0 }, // 7451 |
13443 | | { PseudoVROR_VV_M2_MASK, VROR_VV, 0x1, 0x0 }, // 7452 |
13444 | | { PseudoVROR_VV_M4, VROR_VV, 0x2, 0x0 }, // 7453 |
13445 | | { PseudoVROR_VV_M4_MASK, VROR_VV, 0x2, 0x0 }, // 7454 |
13446 | | { PseudoVROR_VV_M8, VROR_VV, 0x3, 0x0 }, // 7455 |
13447 | | { PseudoVROR_VV_M8_MASK, VROR_VV, 0x3, 0x0 }, // 7456 |
13448 | | { PseudoVROR_VV_MF8, VROR_VV, 0x5, 0x0 }, // 7457 |
13449 | | { PseudoVROR_VV_MF8_MASK, VROR_VV, 0x5, 0x0 }, // 7458 |
13450 | | { PseudoVROR_VV_MF4, VROR_VV, 0x6, 0x0 }, // 7459 |
13451 | | { PseudoVROR_VV_MF4_MASK, VROR_VV, 0x6, 0x0 }, // 7460 |
13452 | | { PseudoVROR_VV_MF2, VROR_VV, 0x7, 0x0 }, // 7461 |
13453 | | { PseudoVROR_VV_MF2_MASK, VROR_VV, 0x7, 0x0 }, // 7462 |
13454 | | { PseudoVROR_VX_M1, VROR_VX, 0x0, 0x0 }, // 7463 |
13455 | | { PseudoVROR_VX_M1_MASK, VROR_VX, 0x0, 0x0 }, // 7464 |
13456 | | { PseudoVROR_VX_M2, VROR_VX, 0x1, 0x0 }, // 7465 |
13457 | | { PseudoVROR_VX_M2_MASK, VROR_VX, 0x1, 0x0 }, // 7466 |
13458 | | { PseudoVROR_VX_M4, VROR_VX, 0x2, 0x0 }, // 7467 |
13459 | | { PseudoVROR_VX_M4_MASK, VROR_VX, 0x2, 0x0 }, // 7468 |
13460 | | { PseudoVROR_VX_M8, VROR_VX, 0x3, 0x0 }, // 7469 |
13461 | | { PseudoVROR_VX_M8_MASK, VROR_VX, 0x3, 0x0 }, // 7470 |
13462 | | { PseudoVROR_VX_MF8, VROR_VX, 0x5, 0x0 }, // 7471 |
13463 | | { PseudoVROR_VX_MF8_MASK, VROR_VX, 0x5, 0x0 }, // 7472 |
13464 | | { PseudoVROR_VX_MF4, VROR_VX, 0x6, 0x0 }, // 7473 |
13465 | | { PseudoVROR_VX_MF4_MASK, VROR_VX, 0x6, 0x0 }, // 7474 |
13466 | | { PseudoVROR_VX_MF2, VROR_VX, 0x7, 0x0 }, // 7475 |
13467 | | { PseudoVROR_VX_MF2_MASK, VROR_VX, 0x7, 0x0 }, // 7476 |
13468 | | { PseudoVRSUB_VI_M1, VRSUB_VI, 0x0, 0x0 }, // 7477 |
13469 | | { PseudoVRSUB_VI_M1_MASK, VRSUB_VI, 0x0, 0x0 }, // 7478 |
13470 | | { PseudoVRSUB_VI_M2, VRSUB_VI, 0x1, 0x0 }, // 7479 |
13471 | | { PseudoVRSUB_VI_M2_MASK, VRSUB_VI, 0x1, 0x0 }, // 7480 |
13472 | | { PseudoVRSUB_VI_M4, VRSUB_VI, 0x2, 0x0 }, // 7481 |
13473 | | { PseudoVRSUB_VI_M4_MASK, VRSUB_VI, 0x2, 0x0 }, // 7482 |
13474 | | { PseudoVRSUB_VI_M8, VRSUB_VI, 0x3, 0x0 }, // 7483 |
13475 | | { PseudoVRSUB_VI_M8_MASK, VRSUB_VI, 0x3, 0x0 }, // 7484 |
13476 | | { PseudoVRSUB_VI_MF8, VRSUB_VI, 0x5, 0x0 }, // 7485 |
13477 | | { PseudoVRSUB_VI_MF8_MASK, VRSUB_VI, 0x5, 0x0 }, // 7486 |
13478 | | { PseudoVRSUB_VI_MF4, VRSUB_VI, 0x6, 0x0 }, // 7487 |
13479 | | { PseudoVRSUB_VI_MF4_MASK, VRSUB_VI, 0x6, 0x0 }, // 7488 |
13480 | | { PseudoVRSUB_VI_MF2, VRSUB_VI, 0x7, 0x0 }, // 7489 |
13481 | | { PseudoVRSUB_VI_MF2_MASK, VRSUB_VI, 0x7, 0x0 }, // 7490 |
13482 | | { PseudoVRSUB_VX_M1, VRSUB_VX, 0x0, 0x0 }, // 7491 |
13483 | | { PseudoVRSUB_VX_M1_MASK, VRSUB_VX, 0x0, 0x0 }, // 7492 |
13484 | | { PseudoVRSUB_VX_M2, VRSUB_VX, 0x1, 0x0 }, // 7493 |
13485 | | { PseudoVRSUB_VX_M2_MASK, VRSUB_VX, 0x1, 0x0 }, // 7494 |
13486 | | { PseudoVRSUB_VX_M4, VRSUB_VX, 0x2, 0x0 }, // 7495 |
13487 | | { PseudoVRSUB_VX_M4_MASK, VRSUB_VX, 0x2, 0x0 }, // 7496 |
13488 | | { PseudoVRSUB_VX_M8, VRSUB_VX, 0x3, 0x0 }, // 7497 |
13489 | | { PseudoVRSUB_VX_M8_MASK, VRSUB_VX, 0x3, 0x0 }, // 7498 |
13490 | | { PseudoVRSUB_VX_MF8, VRSUB_VX, 0x5, 0x0 }, // 7499 |
13491 | | { PseudoVRSUB_VX_MF8_MASK, VRSUB_VX, 0x5, 0x0 }, // 7500 |
13492 | | { PseudoVRSUB_VX_MF4, VRSUB_VX, 0x6, 0x0 }, // 7501 |
13493 | | { PseudoVRSUB_VX_MF4_MASK, VRSUB_VX, 0x6, 0x0 }, // 7502 |
13494 | | { PseudoVRSUB_VX_MF2, VRSUB_VX, 0x7, 0x0 }, // 7503 |
13495 | | { PseudoVRSUB_VX_MF2_MASK, VRSUB_VX, 0x7, 0x0 }, // 7504 |
13496 | | { PseudoVSADDU_VI_M1, VSADDU_VI, 0x0, 0x0 }, // 7505 |
13497 | | { PseudoVSADDU_VI_M1_MASK, VSADDU_VI, 0x0, 0x0 }, // 7506 |
13498 | | { PseudoVSADDU_VI_M2, VSADDU_VI, 0x1, 0x0 }, // 7507 |
13499 | | { PseudoVSADDU_VI_M2_MASK, VSADDU_VI, 0x1, 0x0 }, // 7508 |
13500 | | { PseudoVSADDU_VI_M4, VSADDU_VI, 0x2, 0x0 }, // 7509 |
13501 | | { PseudoVSADDU_VI_M4_MASK, VSADDU_VI, 0x2, 0x0 }, // 7510 |
13502 | | { PseudoVSADDU_VI_M8, VSADDU_VI, 0x3, 0x0 }, // 7511 |
13503 | | { PseudoVSADDU_VI_M8_MASK, VSADDU_VI, 0x3, 0x0 }, // 7512 |
13504 | | { PseudoVSADDU_VI_MF8, VSADDU_VI, 0x5, 0x0 }, // 7513 |
13505 | | { PseudoVSADDU_VI_MF8_MASK, VSADDU_VI, 0x5, 0x0 }, // 7514 |
13506 | | { PseudoVSADDU_VI_MF4, VSADDU_VI, 0x6, 0x0 }, // 7515 |
13507 | | { PseudoVSADDU_VI_MF4_MASK, VSADDU_VI, 0x6, 0x0 }, // 7516 |
13508 | | { PseudoVSADDU_VI_MF2, VSADDU_VI, 0x7, 0x0 }, // 7517 |
13509 | | { PseudoVSADDU_VI_MF2_MASK, VSADDU_VI, 0x7, 0x0 }, // 7518 |
13510 | | { PseudoVSADDU_VV_M1, VSADDU_VV, 0x0, 0x0 }, // 7519 |
13511 | | { PseudoVSADDU_VV_M1_MASK, VSADDU_VV, 0x0, 0x0 }, // 7520 |
13512 | | { PseudoVSADDU_VV_M2, VSADDU_VV, 0x1, 0x0 }, // 7521 |
13513 | | { PseudoVSADDU_VV_M2_MASK, VSADDU_VV, 0x1, 0x0 }, // 7522 |
13514 | | { PseudoVSADDU_VV_M4, VSADDU_VV, 0x2, 0x0 }, // 7523 |
13515 | | { PseudoVSADDU_VV_M4_MASK, VSADDU_VV, 0x2, 0x0 }, // 7524 |
13516 | | { PseudoVSADDU_VV_M8, VSADDU_VV, 0x3, 0x0 }, // 7525 |
13517 | | { PseudoVSADDU_VV_M8_MASK, VSADDU_VV, 0x3, 0x0 }, // 7526 |
13518 | | { PseudoVSADDU_VV_MF8, VSADDU_VV, 0x5, 0x0 }, // 7527 |
13519 | | { PseudoVSADDU_VV_MF8_MASK, VSADDU_VV, 0x5, 0x0 }, // 7528 |
13520 | | { PseudoVSADDU_VV_MF4, VSADDU_VV, 0x6, 0x0 }, // 7529 |
13521 | | { PseudoVSADDU_VV_MF4_MASK, VSADDU_VV, 0x6, 0x0 }, // 7530 |
13522 | | { PseudoVSADDU_VV_MF2, VSADDU_VV, 0x7, 0x0 }, // 7531 |
13523 | | { PseudoVSADDU_VV_MF2_MASK, VSADDU_VV, 0x7, 0x0 }, // 7532 |
13524 | | { PseudoVSADDU_VX_M1, VSADDU_VX, 0x0, 0x0 }, // 7533 |
13525 | | { PseudoVSADDU_VX_M1_MASK, VSADDU_VX, 0x0, 0x0 }, // 7534 |
13526 | | { PseudoVSADDU_VX_M2, VSADDU_VX, 0x1, 0x0 }, // 7535 |
13527 | | { PseudoVSADDU_VX_M2_MASK, VSADDU_VX, 0x1, 0x0 }, // 7536 |
13528 | | { PseudoVSADDU_VX_M4, VSADDU_VX, 0x2, 0x0 }, // 7537 |
13529 | | { PseudoVSADDU_VX_M4_MASK, VSADDU_VX, 0x2, 0x0 }, // 7538 |
13530 | | { PseudoVSADDU_VX_M8, VSADDU_VX, 0x3, 0x0 }, // 7539 |
13531 | | { PseudoVSADDU_VX_M8_MASK, VSADDU_VX, 0x3, 0x0 }, // 7540 |
13532 | | { PseudoVSADDU_VX_MF8, VSADDU_VX, 0x5, 0x0 }, // 7541 |
13533 | | { PseudoVSADDU_VX_MF8_MASK, VSADDU_VX, 0x5, 0x0 }, // 7542 |
13534 | | { PseudoVSADDU_VX_MF4, VSADDU_VX, 0x6, 0x0 }, // 7543 |
13535 | | { PseudoVSADDU_VX_MF4_MASK, VSADDU_VX, 0x6, 0x0 }, // 7544 |
13536 | | { PseudoVSADDU_VX_MF2, VSADDU_VX, 0x7, 0x0 }, // 7545 |
13537 | | { PseudoVSADDU_VX_MF2_MASK, VSADDU_VX, 0x7, 0x0 }, // 7546 |
13538 | | { PseudoVSADD_VI_M1, VSADD_VI, 0x0, 0x0 }, // 7547 |
13539 | | { PseudoVSADD_VI_M1_MASK, VSADD_VI, 0x0, 0x0 }, // 7548 |
13540 | | { PseudoVSADD_VI_M2, VSADD_VI, 0x1, 0x0 }, // 7549 |
13541 | | { PseudoVSADD_VI_M2_MASK, VSADD_VI, 0x1, 0x0 }, // 7550 |
13542 | | { PseudoVSADD_VI_M4, VSADD_VI, 0x2, 0x0 }, // 7551 |
13543 | | { PseudoVSADD_VI_M4_MASK, VSADD_VI, 0x2, 0x0 }, // 7552 |
13544 | | { PseudoVSADD_VI_M8, VSADD_VI, 0x3, 0x0 }, // 7553 |
13545 | | { PseudoVSADD_VI_M8_MASK, VSADD_VI, 0x3, 0x0 }, // 7554 |
13546 | | { PseudoVSADD_VI_MF8, VSADD_VI, 0x5, 0x0 }, // 7555 |
13547 | | { PseudoVSADD_VI_MF8_MASK, VSADD_VI, 0x5, 0x0 }, // 7556 |
13548 | | { PseudoVSADD_VI_MF4, VSADD_VI, 0x6, 0x0 }, // 7557 |
13549 | | { PseudoVSADD_VI_MF4_MASK, VSADD_VI, 0x6, 0x0 }, // 7558 |
13550 | | { PseudoVSADD_VI_MF2, VSADD_VI, 0x7, 0x0 }, // 7559 |
13551 | | { PseudoVSADD_VI_MF2_MASK, VSADD_VI, 0x7, 0x0 }, // 7560 |
13552 | | { PseudoVSADD_VV_M1, VSADD_VV, 0x0, 0x0 }, // 7561 |
13553 | | { PseudoVSADD_VV_M1_MASK, VSADD_VV, 0x0, 0x0 }, // 7562 |
13554 | | { PseudoVSADD_VV_M2, VSADD_VV, 0x1, 0x0 }, // 7563 |
13555 | | { PseudoVSADD_VV_M2_MASK, VSADD_VV, 0x1, 0x0 }, // 7564 |
13556 | | { PseudoVSADD_VV_M4, VSADD_VV, 0x2, 0x0 }, // 7565 |
13557 | | { PseudoVSADD_VV_M4_MASK, VSADD_VV, 0x2, 0x0 }, // 7566 |
13558 | | { PseudoVSADD_VV_M8, VSADD_VV, 0x3, 0x0 }, // 7567 |
13559 | | { PseudoVSADD_VV_M8_MASK, VSADD_VV, 0x3, 0x0 }, // 7568 |
13560 | | { PseudoVSADD_VV_MF8, VSADD_VV, 0x5, 0x0 }, // 7569 |
13561 | | { PseudoVSADD_VV_MF8_MASK, VSADD_VV, 0x5, 0x0 }, // 7570 |
13562 | | { PseudoVSADD_VV_MF4, VSADD_VV, 0x6, 0x0 }, // 7571 |
13563 | | { PseudoVSADD_VV_MF4_MASK, VSADD_VV, 0x6, 0x0 }, // 7572 |
13564 | | { PseudoVSADD_VV_MF2, VSADD_VV, 0x7, 0x0 }, // 7573 |
13565 | | { PseudoVSADD_VV_MF2_MASK, VSADD_VV, 0x7, 0x0 }, // 7574 |
13566 | | { PseudoVSADD_VX_M1, VSADD_VX, 0x0, 0x0 }, // 7575 |
13567 | | { PseudoVSADD_VX_M1_MASK, VSADD_VX, 0x0, 0x0 }, // 7576 |
13568 | | { PseudoVSADD_VX_M2, VSADD_VX, 0x1, 0x0 }, // 7577 |
13569 | | { PseudoVSADD_VX_M2_MASK, VSADD_VX, 0x1, 0x0 }, // 7578 |
13570 | | { PseudoVSADD_VX_M4, VSADD_VX, 0x2, 0x0 }, // 7579 |
13571 | | { PseudoVSADD_VX_M4_MASK, VSADD_VX, 0x2, 0x0 }, // 7580 |
13572 | | { PseudoVSADD_VX_M8, VSADD_VX, 0x3, 0x0 }, // 7581 |
13573 | | { PseudoVSADD_VX_M8_MASK, VSADD_VX, 0x3, 0x0 }, // 7582 |
13574 | | { PseudoVSADD_VX_MF8, VSADD_VX, 0x5, 0x0 }, // 7583 |
13575 | | { PseudoVSADD_VX_MF8_MASK, VSADD_VX, 0x5, 0x0 }, // 7584 |
13576 | | { PseudoVSADD_VX_MF4, VSADD_VX, 0x6, 0x0 }, // 7585 |
13577 | | { PseudoVSADD_VX_MF4_MASK, VSADD_VX, 0x6, 0x0 }, // 7586 |
13578 | | { PseudoVSADD_VX_MF2, VSADD_VX, 0x7, 0x0 }, // 7587 |
13579 | | { PseudoVSADD_VX_MF2_MASK, VSADD_VX, 0x7, 0x0 }, // 7588 |
13580 | | { PseudoVSBC_VVM_M1, VSBC_VVM, 0x0, 0x0 }, // 7589 |
13581 | | { PseudoVSBC_VVM_M2, VSBC_VVM, 0x1, 0x0 }, // 7590 |
13582 | | { PseudoVSBC_VVM_M4, VSBC_VVM, 0x2, 0x0 }, // 7591 |
13583 | | { PseudoVSBC_VVM_M8, VSBC_VVM, 0x3, 0x0 }, // 7592 |
13584 | | { PseudoVSBC_VVM_MF8, VSBC_VVM, 0x5, 0x0 }, // 7593 |
13585 | | { PseudoVSBC_VVM_MF4, VSBC_VVM, 0x6, 0x0 }, // 7594 |
13586 | | { PseudoVSBC_VVM_MF2, VSBC_VVM, 0x7, 0x0 }, // 7595 |
13587 | | { PseudoVSBC_VXM_M1, VSBC_VXM, 0x0, 0x0 }, // 7596 |
13588 | | { PseudoVSBC_VXM_M2, VSBC_VXM, 0x1, 0x0 }, // 7597 |
13589 | | { PseudoVSBC_VXM_M4, VSBC_VXM, 0x2, 0x0 }, // 7598 |
13590 | | { PseudoVSBC_VXM_M8, VSBC_VXM, 0x3, 0x0 }, // 7599 |
13591 | | { PseudoVSBC_VXM_MF8, VSBC_VXM, 0x5, 0x0 }, // 7600 |
13592 | | { PseudoVSBC_VXM_MF4, VSBC_VXM, 0x6, 0x0 }, // 7601 |
13593 | | { PseudoVSBC_VXM_MF2, VSBC_VXM, 0x7, 0x0 }, // 7602 |
13594 | | { PseudoVSE16_V_M1, VSE16_V, 0x0, 0x10 }, // 7603 |
13595 | | { PseudoVSE16_V_M1_MASK, VSE16_V, 0x0, 0x10 }, // 7604 |
13596 | | { PseudoVSE16_V_M2, VSE16_V, 0x1, 0x10 }, // 7605 |
13597 | | { PseudoVSE16_V_M2_MASK, VSE16_V, 0x1, 0x10 }, // 7606 |
13598 | | { PseudoVSE16_V_M4, VSE16_V, 0x2, 0x10 }, // 7607 |
13599 | | { PseudoVSE16_V_M4_MASK, VSE16_V, 0x2, 0x10 }, // 7608 |
13600 | | { PseudoVSE16_V_M8, VSE16_V, 0x3, 0x10 }, // 7609 |
13601 | | { PseudoVSE16_V_M8_MASK, VSE16_V, 0x3, 0x10 }, // 7610 |
13602 | | { PseudoVSE16_V_MF4, VSE16_V, 0x6, 0x10 }, // 7611 |
13603 | | { PseudoVSE16_V_MF4_MASK, VSE16_V, 0x6, 0x10 }, // 7612 |
13604 | | { PseudoVSE16_V_MF2, VSE16_V, 0x7, 0x10 }, // 7613 |
13605 | | { PseudoVSE16_V_MF2_MASK, VSE16_V, 0x7, 0x10 }, // 7614 |
13606 | | { PseudoVSE32_V_M1, VSE32_V, 0x0, 0x20 }, // 7615 |
13607 | | { PseudoVSE32_V_M1_MASK, VSE32_V, 0x0, 0x20 }, // 7616 |
13608 | | { PseudoVSE32_V_M2, VSE32_V, 0x1, 0x20 }, // 7617 |
13609 | | { PseudoVSE32_V_M2_MASK, VSE32_V, 0x1, 0x20 }, // 7618 |
13610 | | { PseudoVSE32_V_M4, VSE32_V, 0x2, 0x20 }, // 7619 |
13611 | | { PseudoVSE32_V_M4_MASK, VSE32_V, 0x2, 0x20 }, // 7620 |
13612 | | { PseudoVSE32_V_M8, VSE32_V, 0x3, 0x20 }, // 7621 |
13613 | | { PseudoVSE32_V_M8_MASK, VSE32_V, 0x3, 0x20 }, // 7622 |
13614 | | { PseudoVSE32_V_MF2, VSE32_V, 0x7, 0x20 }, // 7623 |
13615 | | { PseudoVSE32_V_MF2_MASK, VSE32_V, 0x7, 0x20 }, // 7624 |
13616 | | { PseudoVSE64_V_M1, VSE64_V, 0x0, 0x40 }, // 7625 |
13617 | | { PseudoVSE64_V_M1_MASK, VSE64_V, 0x0, 0x40 }, // 7626 |
13618 | | { PseudoVSE64_V_M2, VSE64_V, 0x1, 0x40 }, // 7627 |
13619 | | { PseudoVSE64_V_M2_MASK, VSE64_V, 0x1, 0x40 }, // 7628 |
13620 | | { PseudoVSE64_V_M4, VSE64_V, 0x2, 0x40 }, // 7629 |
13621 | | { PseudoVSE64_V_M4_MASK, VSE64_V, 0x2, 0x40 }, // 7630 |
13622 | | { PseudoVSE64_V_M8, VSE64_V, 0x3, 0x40 }, // 7631 |
13623 | | { PseudoVSE64_V_M8_MASK, VSE64_V, 0x3, 0x40 }, // 7632 |
13624 | | { PseudoVSE8_V_M1, VSE8_V, 0x0, 0x8 }, // 7633 |
13625 | | { PseudoVSE8_V_M1_MASK, VSE8_V, 0x0, 0x8 }, // 7634 |
13626 | | { PseudoVSE8_V_M2, VSE8_V, 0x1, 0x8 }, // 7635 |
13627 | | { PseudoVSE8_V_M2_MASK, VSE8_V, 0x1, 0x8 }, // 7636 |
13628 | | { PseudoVSE8_V_M4, VSE8_V, 0x2, 0x8 }, // 7637 |
13629 | | { PseudoVSE8_V_M4_MASK, VSE8_V, 0x2, 0x8 }, // 7638 |
13630 | | { PseudoVSE8_V_M8, VSE8_V, 0x3, 0x8 }, // 7639 |
13631 | | { PseudoVSE8_V_M8_MASK, VSE8_V, 0x3, 0x8 }, // 7640 |
13632 | | { PseudoVSE8_V_MF8, VSE8_V, 0x5, 0x8 }, // 7641 |
13633 | | { PseudoVSE8_V_MF8_MASK, VSE8_V, 0x5, 0x8 }, // 7642 |
13634 | | { PseudoVSE8_V_MF4, VSE8_V, 0x6, 0x8 }, // 7643 |
13635 | | { PseudoVSE8_V_MF4_MASK, VSE8_V, 0x6, 0x8 }, // 7644 |
13636 | | { PseudoVSE8_V_MF2, VSE8_V, 0x7, 0x8 }, // 7645 |
13637 | | { PseudoVSE8_V_MF2_MASK, VSE8_V, 0x7, 0x8 }, // 7646 |
13638 | | { PseudoVSEXT_VF2_M1, VSEXT_VF2, 0x0, 0x0 }, // 7647 |
13639 | | { PseudoVSEXT_VF2_M1_MASK, VSEXT_VF2, 0x0, 0x0 }, // 7648 |
13640 | | { PseudoVSEXT_VF2_M2, VSEXT_VF2, 0x1, 0x0 }, // 7649 |
13641 | | { PseudoVSEXT_VF2_M2_MASK, VSEXT_VF2, 0x1, 0x0 }, // 7650 |
13642 | | { PseudoVSEXT_VF2_M4, VSEXT_VF2, 0x2, 0x0 }, // 7651 |
13643 | | { PseudoVSEXT_VF2_M4_MASK, VSEXT_VF2, 0x2, 0x0 }, // 7652 |
13644 | | { PseudoVSEXT_VF2_M8, VSEXT_VF2, 0x3, 0x0 }, // 7653 |
13645 | | { PseudoVSEXT_VF2_M8_MASK, VSEXT_VF2, 0x3, 0x0 }, // 7654 |
13646 | | { PseudoVSEXT_VF2_MF4, VSEXT_VF2, 0x6, 0x0 }, // 7655 |
13647 | | { PseudoVSEXT_VF2_MF4_MASK, VSEXT_VF2, 0x6, 0x0 }, // 7656 |
13648 | | { PseudoVSEXT_VF2_MF2, VSEXT_VF2, 0x7, 0x0 }, // 7657 |
13649 | | { PseudoVSEXT_VF2_MF2_MASK, VSEXT_VF2, 0x7, 0x0 }, // 7658 |
13650 | | { PseudoVSEXT_VF4_M1, VSEXT_VF4, 0x0, 0x0 }, // 7659 |
13651 | | { PseudoVSEXT_VF4_M1_MASK, VSEXT_VF4, 0x0, 0x0 }, // 7660 |
13652 | | { PseudoVSEXT_VF4_M2, VSEXT_VF4, 0x1, 0x0 }, // 7661 |
13653 | | { PseudoVSEXT_VF4_M2_MASK, VSEXT_VF4, 0x1, 0x0 }, // 7662 |
13654 | | { PseudoVSEXT_VF4_M4, VSEXT_VF4, 0x2, 0x0 }, // 7663 |
13655 | | { PseudoVSEXT_VF4_M4_MASK, VSEXT_VF4, 0x2, 0x0 }, // 7664 |
13656 | | { PseudoVSEXT_VF4_M8, VSEXT_VF4, 0x3, 0x0 }, // 7665 |
13657 | | { PseudoVSEXT_VF4_M8_MASK, VSEXT_VF4, 0x3, 0x0 }, // 7666 |
13658 | | { PseudoVSEXT_VF4_MF2, VSEXT_VF4, 0x7, 0x0 }, // 7667 |
13659 | | { PseudoVSEXT_VF4_MF2_MASK, VSEXT_VF4, 0x7, 0x0 }, // 7668 |
13660 | | { PseudoVSEXT_VF8_M1, VSEXT_VF8, 0x0, 0x0 }, // 7669 |
13661 | | { PseudoVSEXT_VF8_M1_MASK, VSEXT_VF8, 0x0, 0x0 }, // 7670 |
13662 | | { PseudoVSEXT_VF8_M2, VSEXT_VF8, 0x1, 0x0 }, // 7671 |
13663 | | { PseudoVSEXT_VF8_M2_MASK, VSEXT_VF8, 0x1, 0x0 }, // 7672 |
13664 | | { PseudoVSEXT_VF8_M4, VSEXT_VF8, 0x2, 0x0 }, // 7673 |
13665 | | { PseudoVSEXT_VF8_M4_MASK, VSEXT_VF8, 0x2, 0x0 }, // 7674 |
13666 | | { PseudoVSEXT_VF8_M8, VSEXT_VF8, 0x3, 0x0 }, // 7675 |
13667 | | { PseudoVSEXT_VF8_M8_MASK, VSEXT_VF8, 0x3, 0x0 }, // 7676 |
13668 | | { PseudoVSHA2CH_VV_M1, VSHA2CH_VV, 0x0, 0x0 }, // 7677 |
13669 | | { PseudoVSHA2CH_VV_M2, VSHA2CH_VV, 0x1, 0x0 }, // 7678 |
13670 | | { PseudoVSHA2CH_VV_M4, VSHA2CH_VV, 0x2, 0x0 }, // 7679 |
13671 | | { PseudoVSHA2CH_VV_M8, VSHA2CH_VV, 0x3, 0x0 }, // 7680 |
13672 | | { PseudoVSHA2CH_VV_MF2, VSHA2CH_VV, 0x7, 0x0 }, // 7681 |
13673 | | { PseudoVSHA2CL_VV_M1, VSHA2CL_VV, 0x0, 0x0 }, // 7682 |
13674 | | { PseudoVSHA2CL_VV_M2, VSHA2CL_VV, 0x1, 0x0 }, // 7683 |
13675 | | { PseudoVSHA2CL_VV_M4, VSHA2CL_VV, 0x2, 0x0 }, // 7684 |
13676 | | { PseudoVSHA2CL_VV_M8, VSHA2CL_VV, 0x3, 0x0 }, // 7685 |
13677 | | { PseudoVSHA2CL_VV_MF2, VSHA2CL_VV, 0x7, 0x0 }, // 7686 |
13678 | | { PseudoVSHA2MS_VV_M1, VSHA2MS_VV, 0x0, 0x0 }, // 7687 |
13679 | | { PseudoVSHA2MS_VV_M2, VSHA2MS_VV, 0x1, 0x0 }, // 7688 |
13680 | | { PseudoVSHA2MS_VV_M4, VSHA2MS_VV, 0x2, 0x0 }, // 7689 |
13681 | | { PseudoVSHA2MS_VV_M8, VSHA2MS_VV, 0x3, 0x0 }, // 7690 |
13682 | | { PseudoVSHA2MS_VV_MF2, VSHA2MS_VV, 0x7, 0x0 }, // 7691 |
13683 | | { PseudoVSLIDE1DOWN_VX_M1, VSLIDE1DOWN_VX, 0x0, 0x0 }, // 7692 |
13684 | | { PseudoVSLIDE1DOWN_VX_M1_MASK, VSLIDE1DOWN_VX, 0x0, 0x0 }, // 7693 |
13685 | | { PseudoVSLIDE1DOWN_VX_M2, VSLIDE1DOWN_VX, 0x1, 0x0 }, // 7694 |
13686 | | { PseudoVSLIDE1DOWN_VX_M2_MASK, VSLIDE1DOWN_VX, 0x1, 0x0 }, // 7695 |
13687 | | { PseudoVSLIDE1DOWN_VX_M4, VSLIDE1DOWN_VX, 0x2, 0x0 }, // 7696 |
13688 | | { PseudoVSLIDE1DOWN_VX_M4_MASK, VSLIDE1DOWN_VX, 0x2, 0x0 }, // 7697 |
13689 | | { PseudoVSLIDE1DOWN_VX_M8, VSLIDE1DOWN_VX, 0x3, 0x0 }, // 7698 |
13690 | | { PseudoVSLIDE1DOWN_VX_M8_MASK, VSLIDE1DOWN_VX, 0x3, 0x0 }, // 7699 |
13691 | | { PseudoVSLIDE1DOWN_VX_MF8, VSLIDE1DOWN_VX, 0x5, 0x0 }, // 7700 |
13692 | | { PseudoVSLIDE1DOWN_VX_MF8_MASK, VSLIDE1DOWN_VX, 0x5, 0x0 }, // 7701 |
13693 | | { PseudoVSLIDE1DOWN_VX_MF4, VSLIDE1DOWN_VX, 0x6, 0x0 }, // 7702 |
13694 | | { PseudoVSLIDE1DOWN_VX_MF4_MASK, VSLIDE1DOWN_VX, 0x6, 0x0 }, // 7703 |
13695 | | { PseudoVSLIDE1DOWN_VX_MF2, VSLIDE1DOWN_VX, 0x7, 0x0 }, // 7704 |
13696 | | { PseudoVSLIDE1DOWN_VX_MF2_MASK, VSLIDE1DOWN_VX, 0x7, 0x0 }, // 7705 |
13697 | | { PseudoVSLIDE1UP_VX_M1, VSLIDE1UP_VX, 0x0, 0x0 }, // 7706 |
13698 | | { PseudoVSLIDE1UP_VX_M1_MASK, VSLIDE1UP_VX, 0x0, 0x0 }, // 7707 |
13699 | | { PseudoVSLIDE1UP_VX_M2, VSLIDE1UP_VX, 0x1, 0x0 }, // 7708 |
13700 | | { PseudoVSLIDE1UP_VX_M2_MASK, VSLIDE1UP_VX, 0x1, 0x0 }, // 7709 |
13701 | | { PseudoVSLIDE1UP_VX_M4, VSLIDE1UP_VX, 0x2, 0x0 }, // 7710 |
13702 | | { PseudoVSLIDE1UP_VX_M4_MASK, VSLIDE1UP_VX, 0x2, 0x0 }, // 7711 |
13703 | | { PseudoVSLIDE1UP_VX_M8, VSLIDE1UP_VX, 0x3, 0x0 }, // 7712 |
13704 | | { PseudoVSLIDE1UP_VX_M8_MASK, VSLIDE1UP_VX, 0x3, 0x0 }, // 7713 |
13705 | | { PseudoVSLIDE1UP_VX_MF8, VSLIDE1UP_VX, 0x5, 0x0 }, // 7714 |
13706 | | { PseudoVSLIDE1UP_VX_MF8_MASK, VSLIDE1UP_VX, 0x5, 0x0 }, // 7715 |
13707 | | { PseudoVSLIDE1UP_VX_MF4, VSLIDE1UP_VX, 0x6, 0x0 }, // 7716 |
13708 | | { PseudoVSLIDE1UP_VX_MF4_MASK, VSLIDE1UP_VX, 0x6, 0x0 }, // 7717 |
13709 | | { PseudoVSLIDE1UP_VX_MF2, VSLIDE1UP_VX, 0x7, 0x0 }, // 7718 |
13710 | | { PseudoVSLIDE1UP_VX_MF2_MASK, VSLIDE1UP_VX, 0x7, 0x0 }, // 7719 |
13711 | | { PseudoVSLIDEDOWN_VI_M1, VSLIDEDOWN_VI, 0x0, 0x0 }, // 7720 |
13712 | | { PseudoVSLIDEDOWN_VI_M1_MASK, VSLIDEDOWN_VI, 0x0, 0x0 }, // 7721 |
13713 | | { PseudoVSLIDEDOWN_VI_M2, VSLIDEDOWN_VI, 0x1, 0x0 }, // 7722 |
13714 | | { PseudoVSLIDEDOWN_VI_M2_MASK, VSLIDEDOWN_VI, 0x1, 0x0 }, // 7723 |
13715 | | { PseudoVSLIDEDOWN_VI_M4, VSLIDEDOWN_VI, 0x2, 0x0 }, // 7724 |
13716 | | { PseudoVSLIDEDOWN_VI_M4_MASK, VSLIDEDOWN_VI, 0x2, 0x0 }, // 7725 |
13717 | | { PseudoVSLIDEDOWN_VI_M8, VSLIDEDOWN_VI, 0x3, 0x0 }, // 7726 |
13718 | | { PseudoVSLIDEDOWN_VI_M8_MASK, VSLIDEDOWN_VI, 0x3, 0x0 }, // 7727 |
13719 | | { PseudoVSLIDEDOWN_VI_MF8, VSLIDEDOWN_VI, 0x5, 0x0 }, // 7728 |
13720 | | { PseudoVSLIDEDOWN_VI_MF8_MASK, VSLIDEDOWN_VI, 0x5, 0x0 }, // 7729 |
13721 | | { PseudoVSLIDEDOWN_VI_MF4, VSLIDEDOWN_VI, 0x6, 0x0 }, // 7730 |
13722 | | { PseudoVSLIDEDOWN_VI_MF4_MASK, VSLIDEDOWN_VI, 0x6, 0x0 }, // 7731 |
13723 | | { PseudoVSLIDEDOWN_VI_MF2, VSLIDEDOWN_VI, 0x7, 0x0 }, // 7732 |
13724 | | { PseudoVSLIDEDOWN_VI_MF2_MASK, VSLIDEDOWN_VI, 0x7, 0x0 }, // 7733 |
13725 | | { PseudoVSLIDEDOWN_VX_M1, VSLIDEDOWN_VX, 0x0, 0x0 }, // 7734 |
13726 | | { PseudoVSLIDEDOWN_VX_M1_MASK, VSLIDEDOWN_VX, 0x0, 0x0 }, // 7735 |
13727 | | { PseudoVSLIDEDOWN_VX_M2, VSLIDEDOWN_VX, 0x1, 0x0 }, // 7736 |
13728 | | { PseudoVSLIDEDOWN_VX_M2_MASK, VSLIDEDOWN_VX, 0x1, 0x0 }, // 7737 |
13729 | | { PseudoVSLIDEDOWN_VX_M4, VSLIDEDOWN_VX, 0x2, 0x0 }, // 7738 |
13730 | | { PseudoVSLIDEDOWN_VX_M4_MASK, VSLIDEDOWN_VX, 0x2, 0x0 }, // 7739 |
13731 | | { PseudoVSLIDEDOWN_VX_M8, VSLIDEDOWN_VX, 0x3, 0x0 }, // 7740 |
13732 | | { PseudoVSLIDEDOWN_VX_M8_MASK, VSLIDEDOWN_VX, 0x3, 0x0 }, // 7741 |
13733 | | { PseudoVSLIDEDOWN_VX_MF8, VSLIDEDOWN_VX, 0x5, 0x0 }, // 7742 |
13734 | | { PseudoVSLIDEDOWN_VX_MF8_MASK, VSLIDEDOWN_VX, 0x5, 0x0 }, // 7743 |
13735 | | { PseudoVSLIDEDOWN_VX_MF4, VSLIDEDOWN_VX, 0x6, 0x0 }, // 7744 |
13736 | | { PseudoVSLIDEDOWN_VX_MF4_MASK, VSLIDEDOWN_VX, 0x6, 0x0 }, // 7745 |
13737 | | { PseudoVSLIDEDOWN_VX_MF2, VSLIDEDOWN_VX, 0x7, 0x0 }, // 7746 |
13738 | | { PseudoVSLIDEDOWN_VX_MF2_MASK, VSLIDEDOWN_VX, 0x7, 0x0 }, // 7747 |
13739 | | { PseudoVSLIDEUP_VI_M1, VSLIDEUP_VI, 0x0, 0x0 }, // 7748 |
13740 | | { PseudoVSLIDEUP_VI_M1_MASK, VSLIDEUP_VI, 0x0, 0x0 }, // 7749 |
13741 | | { PseudoVSLIDEUP_VI_M2, VSLIDEUP_VI, 0x1, 0x0 }, // 7750 |
13742 | | { PseudoVSLIDEUP_VI_M2_MASK, VSLIDEUP_VI, 0x1, 0x0 }, // 7751 |
13743 | | { PseudoVSLIDEUP_VI_M4, VSLIDEUP_VI, 0x2, 0x0 }, // 7752 |
13744 | | { PseudoVSLIDEUP_VI_M4_MASK, VSLIDEUP_VI, 0x2, 0x0 }, // 7753 |
13745 | | { PseudoVSLIDEUP_VI_M8, VSLIDEUP_VI, 0x3, 0x0 }, // 7754 |
13746 | | { PseudoVSLIDEUP_VI_M8_MASK, VSLIDEUP_VI, 0x3, 0x0 }, // 7755 |
13747 | | { PseudoVSLIDEUP_VI_MF8, VSLIDEUP_VI, 0x5, 0x0 }, // 7756 |
13748 | | { PseudoVSLIDEUP_VI_MF8_MASK, VSLIDEUP_VI, 0x5, 0x0 }, // 7757 |
13749 | | { PseudoVSLIDEUP_VI_MF4, VSLIDEUP_VI, 0x6, 0x0 }, // 7758 |
13750 | | { PseudoVSLIDEUP_VI_MF4_MASK, VSLIDEUP_VI, 0x6, 0x0 }, // 7759 |
13751 | | { PseudoVSLIDEUP_VI_MF2, VSLIDEUP_VI, 0x7, 0x0 }, // 7760 |
13752 | | { PseudoVSLIDEUP_VI_MF2_MASK, VSLIDEUP_VI, 0x7, 0x0 }, // 7761 |
13753 | | { PseudoVSLIDEUP_VX_M1, VSLIDEUP_VX, 0x0, 0x0 }, // 7762 |
13754 | | { PseudoVSLIDEUP_VX_M1_MASK, VSLIDEUP_VX, 0x0, 0x0 }, // 7763 |
13755 | | { PseudoVSLIDEUP_VX_M2, VSLIDEUP_VX, 0x1, 0x0 }, // 7764 |
13756 | | { PseudoVSLIDEUP_VX_M2_MASK, VSLIDEUP_VX, 0x1, 0x0 }, // 7765 |
13757 | | { PseudoVSLIDEUP_VX_M4, VSLIDEUP_VX, 0x2, 0x0 }, // 7766 |
13758 | | { PseudoVSLIDEUP_VX_M4_MASK, VSLIDEUP_VX, 0x2, 0x0 }, // 7767 |
13759 | | { PseudoVSLIDEUP_VX_M8, VSLIDEUP_VX, 0x3, 0x0 }, // 7768 |
13760 | | { PseudoVSLIDEUP_VX_M8_MASK, VSLIDEUP_VX, 0x3, 0x0 }, // 7769 |
13761 | | { PseudoVSLIDEUP_VX_MF8, VSLIDEUP_VX, 0x5, 0x0 }, // 7770 |
13762 | | { PseudoVSLIDEUP_VX_MF8_MASK, VSLIDEUP_VX, 0x5, 0x0 }, // 7771 |
13763 | | { PseudoVSLIDEUP_VX_MF4, VSLIDEUP_VX, 0x6, 0x0 }, // 7772 |
13764 | | { PseudoVSLIDEUP_VX_MF4_MASK, VSLIDEUP_VX, 0x6, 0x0 }, // 7773 |
13765 | | { PseudoVSLIDEUP_VX_MF2, VSLIDEUP_VX, 0x7, 0x0 }, // 7774 |
13766 | | { PseudoVSLIDEUP_VX_MF2_MASK, VSLIDEUP_VX, 0x7, 0x0 }, // 7775 |
13767 | | { PseudoVSLL_VI_M1, VSLL_VI, 0x0, 0x0 }, // 7776 |
13768 | | { PseudoVSLL_VI_M1_MASK, VSLL_VI, 0x0, 0x0 }, // 7777 |
13769 | | { PseudoVSLL_VI_M2, VSLL_VI, 0x1, 0x0 }, // 7778 |
13770 | | { PseudoVSLL_VI_M2_MASK, VSLL_VI, 0x1, 0x0 }, // 7779 |
13771 | | { PseudoVSLL_VI_M4, VSLL_VI, 0x2, 0x0 }, // 7780 |
13772 | | { PseudoVSLL_VI_M4_MASK, VSLL_VI, 0x2, 0x0 }, // 7781 |
13773 | | { PseudoVSLL_VI_M8, VSLL_VI, 0x3, 0x0 }, // 7782 |
13774 | | { PseudoVSLL_VI_M8_MASK, VSLL_VI, 0x3, 0x0 }, // 7783 |
13775 | | { PseudoVSLL_VI_MF8, VSLL_VI, 0x5, 0x0 }, // 7784 |
13776 | | { PseudoVSLL_VI_MF8_MASK, VSLL_VI, 0x5, 0x0 }, // 7785 |
13777 | | { PseudoVSLL_VI_MF4, VSLL_VI, 0x6, 0x0 }, // 7786 |
13778 | | { PseudoVSLL_VI_MF4_MASK, VSLL_VI, 0x6, 0x0 }, // 7787 |
13779 | | { PseudoVSLL_VI_MF2, VSLL_VI, 0x7, 0x0 }, // 7788 |
13780 | | { PseudoVSLL_VI_MF2_MASK, VSLL_VI, 0x7, 0x0 }, // 7789 |
13781 | | { PseudoVSLL_VV_M1, VSLL_VV, 0x0, 0x0 }, // 7790 |
13782 | | { PseudoVSLL_VV_M1_MASK, VSLL_VV, 0x0, 0x0 }, // 7791 |
13783 | | { PseudoVSLL_VV_M2, VSLL_VV, 0x1, 0x0 }, // 7792 |
13784 | | { PseudoVSLL_VV_M2_MASK, VSLL_VV, 0x1, 0x0 }, // 7793 |
13785 | | { PseudoVSLL_VV_M4, VSLL_VV, 0x2, 0x0 }, // 7794 |
13786 | | { PseudoVSLL_VV_M4_MASK, VSLL_VV, 0x2, 0x0 }, // 7795 |
13787 | | { PseudoVSLL_VV_M8, VSLL_VV, 0x3, 0x0 }, // 7796 |
13788 | | { PseudoVSLL_VV_M8_MASK, VSLL_VV, 0x3, 0x0 }, // 7797 |
13789 | | { PseudoVSLL_VV_MF8, VSLL_VV, 0x5, 0x0 }, // 7798 |
13790 | | { PseudoVSLL_VV_MF8_MASK, VSLL_VV, 0x5, 0x0 }, // 7799 |
13791 | | { PseudoVSLL_VV_MF4, VSLL_VV, 0x6, 0x0 }, // 7800 |
13792 | | { PseudoVSLL_VV_MF4_MASK, VSLL_VV, 0x6, 0x0 }, // 7801 |
13793 | | { PseudoVSLL_VV_MF2, VSLL_VV, 0x7, 0x0 }, // 7802 |
13794 | | { PseudoVSLL_VV_MF2_MASK, VSLL_VV, 0x7, 0x0 }, // 7803 |
13795 | | { PseudoVSLL_VX_M1, VSLL_VX, 0x0, 0x0 }, // 7804 |
13796 | | { PseudoVSLL_VX_M1_MASK, VSLL_VX, 0x0, 0x0 }, // 7805 |
13797 | | { PseudoVSLL_VX_M2, VSLL_VX, 0x1, 0x0 }, // 7806 |
13798 | | { PseudoVSLL_VX_M2_MASK, VSLL_VX, 0x1, 0x0 }, // 7807 |
13799 | | { PseudoVSLL_VX_M4, VSLL_VX, 0x2, 0x0 }, // 7808 |
13800 | | { PseudoVSLL_VX_M4_MASK, VSLL_VX, 0x2, 0x0 }, // 7809 |
13801 | | { PseudoVSLL_VX_M8, VSLL_VX, 0x3, 0x0 }, // 7810 |
13802 | | { PseudoVSLL_VX_M8_MASK, VSLL_VX, 0x3, 0x0 }, // 7811 |
13803 | | { PseudoVSLL_VX_MF8, VSLL_VX, 0x5, 0x0 }, // 7812 |
13804 | | { PseudoVSLL_VX_MF8_MASK, VSLL_VX, 0x5, 0x0 }, // 7813 |
13805 | | { PseudoVSLL_VX_MF4, VSLL_VX, 0x6, 0x0 }, // 7814 |
13806 | | { PseudoVSLL_VX_MF4_MASK, VSLL_VX, 0x6, 0x0 }, // 7815 |
13807 | | { PseudoVSLL_VX_MF2, VSLL_VX, 0x7, 0x0 }, // 7816 |
13808 | | { PseudoVSLL_VX_MF2_MASK, VSLL_VX, 0x7, 0x0 }, // 7817 |
13809 | | { PseudoVSM3C_VI_M1, VSM3C_VI, 0x0, 0x0 }, // 7818 |
13810 | | { PseudoVSM3C_VI_M2, VSM3C_VI, 0x1, 0x0 }, // 7819 |
13811 | | { PseudoVSM3C_VI_M4, VSM3C_VI, 0x2, 0x0 }, // 7820 |
13812 | | { PseudoVSM3C_VI_M8, VSM3C_VI, 0x3, 0x0 }, // 7821 |
13813 | | { PseudoVSM3C_VI_MF2, VSM3C_VI, 0x7, 0x0 }, // 7822 |
13814 | | { PseudoVSM3ME_VV_M1, VSM3ME_VV, 0x0, 0x0 }, // 7823 |
13815 | | { PseudoVSM3ME_VV_M2, VSM3ME_VV, 0x1, 0x0 }, // 7824 |
13816 | | { PseudoVSM3ME_VV_M4, VSM3ME_VV, 0x2, 0x0 }, // 7825 |
13817 | | { PseudoVSM3ME_VV_M8, VSM3ME_VV, 0x3, 0x0 }, // 7826 |
13818 | | { PseudoVSM3ME_VV_MF2, VSM3ME_VV, 0x7, 0x0 }, // 7827 |
13819 | | { PseudoVSM4K_VI_M1, VSM4K_VI, 0x0, 0x0 }, // 7828 |
13820 | | { PseudoVSM4K_VI_M2, VSM4K_VI, 0x1, 0x0 }, // 7829 |
13821 | | { PseudoVSM4K_VI_M4, VSM4K_VI, 0x2, 0x0 }, // 7830 |
13822 | | { PseudoVSM4K_VI_M8, VSM4K_VI, 0x3, 0x0 }, // 7831 |
13823 | | { PseudoVSM4K_VI_MF2, VSM4K_VI, 0x7, 0x0 }, // 7832 |
13824 | | { PseudoVSM4R_VS_M1_M1, VSM4R_VS, 0x0, 0x0 }, // 7833 |
13825 | | { PseudoVSM4R_VS_M1_MF2, VSM4R_VS, 0x0, 0x0 }, // 7834 |
13826 | | { PseudoVSM4R_VS_M1_MF4, VSM4R_VS, 0x0, 0x0 }, // 7835 |
13827 | | { PseudoVSM4R_VS_M1_MF8, VSM4R_VS, 0x0, 0x0 }, // 7836 |
13828 | | { PseudoVSM4R_VS_M2_M1, VSM4R_VS, 0x1, 0x0 }, // 7837 |
13829 | | { PseudoVSM4R_VS_M2_M2, VSM4R_VS, 0x1, 0x0 }, // 7838 |
13830 | | { PseudoVSM4R_VS_M2_MF2, VSM4R_VS, 0x1, 0x0 }, // 7839 |
13831 | | { PseudoVSM4R_VS_M2_MF4, VSM4R_VS, 0x1, 0x0 }, // 7840 |
13832 | | { PseudoVSM4R_VS_M2_MF8, VSM4R_VS, 0x1, 0x0 }, // 7841 |
13833 | | { PseudoVSM4R_VS_M4_M1, VSM4R_VS, 0x2, 0x0 }, // 7842 |
13834 | | { PseudoVSM4R_VS_M4_M2, VSM4R_VS, 0x2, 0x0 }, // 7843 |
13835 | | { PseudoVSM4R_VS_M4_M4, VSM4R_VS, 0x2, 0x0 }, // 7844 |
13836 | | { PseudoVSM4R_VS_M4_MF2, VSM4R_VS, 0x2, 0x0 }, // 7845 |
13837 | | { PseudoVSM4R_VS_M4_MF4, VSM4R_VS, 0x2, 0x0 }, // 7846 |
13838 | | { PseudoVSM4R_VS_M4_MF8, VSM4R_VS, 0x2, 0x0 }, // 7847 |
13839 | | { PseudoVSM4R_VS_M8_M1, VSM4R_VS, 0x3, 0x0 }, // 7848 |
13840 | | { PseudoVSM4R_VS_M8_M2, VSM4R_VS, 0x3, 0x0 }, // 7849 |
13841 | | { PseudoVSM4R_VS_M8_M4, VSM4R_VS, 0x3, 0x0 }, // 7850 |
13842 | | { PseudoVSM4R_VS_M8_MF2, VSM4R_VS, 0x3, 0x0 }, // 7851 |
13843 | | { PseudoVSM4R_VS_M8_MF4, VSM4R_VS, 0x3, 0x0 }, // 7852 |
13844 | | { PseudoVSM4R_VS_M8_MF8, VSM4R_VS, 0x3, 0x0 }, // 7853 |
13845 | | { PseudoVSM4R_VS_MF2_MF2, VSM4R_VS, 0x7, 0x0 }, // 7854 |
13846 | | { PseudoVSM4R_VS_MF2_MF4, VSM4R_VS, 0x7, 0x0 }, // 7855 |
13847 | | { PseudoVSM4R_VS_MF2_MF8, VSM4R_VS, 0x7, 0x0 }, // 7856 |
13848 | | { PseudoVSM4R_VV_M1, VSM4R_VV, 0x0, 0x0 }, // 7857 |
13849 | | { PseudoVSM4R_VV_M2, VSM4R_VV, 0x1, 0x0 }, // 7858 |
13850 | | { PseudoVSM4R_VV_M4, VSM4R_VV, 0x2, 0x0 }, // 7859 |
13851 | | { PseudoVSM4R_VV_M8, VSM4R_VV, 0x3, 0x0 }, // 7860 |
13852 | | { PseudoVSM4R_VV_MF2, VSM4R_VV, 0x7, 0x0 }, // 7861 |
13853 | | { PseudoVSMUL_VV_M1, VSMUL_VV, 0x0, 0x0 }, // 7862 |
13854 | | { PseudoVSMUL_VV_M1_MASK, VSMUL_VV, 0x0, 0x0 }, // 7863 |
13855 | | { PseudoVSMUL_VV_M2, VSMUL_VV, 0x1, 0x0 }, // 7864 |
13856 | | { PseudoVSMUL_VV_M2_MASK, VSMUL_VV, 0x1, 0x0 }, // 7865 |
13857 | | { PseudoVSMUL_VV_M4, VSMUL_VV, 0x2, 0x0 }, // 7866 |
13858 | | { PseudoVSMUL_VV_M4_MASK, VSMUL_VV, 0x2, 0x0 }, // 7867 |
13859 | | { PseudoVSMUL_VV_M8, VSMUL_VV, 0x3, 0x0 }, // 7868 |
13860 | | { PseudoVSMUL_VV_M8_MASK, VSMUL_VV, 0x3, 0x0 }, // 7869 |
13861 | | { PseudoVSMUL_VV_MF8, VSMUL_VV, 0x5, 0x0 }, // 7870 |
13862 | | { PseudoVSMUL_VV_MF8_MASK, VSMUL_VV, 0x5, 0x0 }, // 7871 |
13863 | | { PseudoVSMUL_VV_MF4, VSMUL_VV, 0x6, 0x0 }, // 7872 |
13864 | | { PseudoVSMUL_VV_MF4_MASK, VSMUL_VV, 0x6, 0x0 }, // 7873 |
13865 | | { PseudoVSMUL_VV_MF2, VSMUL_VV, 0x7, 0x0 }, // 7874 |
13866 | | { PseudoVSMUL_VV_MF2_MASK, VSMUL_VV, 0x7, 0x0 }, // 7875 |
13867 | | { PseudoVSMUL_VX_M1, VSMUL_VX, 0x0, 0x0 }, // 7876 |
13868 | | { PseudoVSMUL_VX_M1_MASK, VSMUL_VX, 0x0, 0x0 }, // 7877 |
13869 | | { PseudoVSMUL_VX_M2, VSMUL_VX, 0x1, 0x0 }, // 7878 |
13870 | | { PseudoVSMUL_VX_M2_MASK, VSMUL_VX, 0x1, 0x0 }, // 7879 |
13871 | | { PseudoVSMUL_VX_M4, VSMUL_VX, 0x2, 0x0 }, // 7880 |
13872 | | { PseudoVSMUL_VX_M4_MASK, VSMUL_VX, 0x2, 0x0 }, // 7881 |
13873 | | { PseudoVSMUL_VX_M8, VSMUL_VX, 0x3, 0x0 }, // 7882 |
13874 | | { PseudoVSMUL_VX_M8_MASK, VSMUL_VX, 0x3, 0x0 }, // 7883 |
13875 | | { PseudoVSMUL_VX_MF8, VSMUL_VX, 0x5, 0x0 }, // 7884 |
13876 | | { PseudoVSMUL_VX_MF8_MASK, VSMUL_VX, 0x5, 0x0 }, // 7885 |
13877 | | { PseudoVSMUL_VX_MF4, VSMUL_VX, 0x6, 0x0 }, // 7886 |
13878 | | { PseudoVSMUL_VX_MF4_MASK, VSMUL_VX, 0x6, 0x0 }, // 7887 |
13879 | | { PseudoVSMUL_VX_MF2, VSMUL_VX, 0x7, 0x0 }, // 7888 |
13880 | | { PseudoVSMUL_VX_MF2_MASK, VSMUL_VX, 0x7, 0x0 }, // 7889 |
13881 | | { PseudoVSM_V_B8, VSM_V, 0x0, 0x0 }, // 7890 |
13882 | | { PseudoVSM_V_B16, VSM_V, 0x1, 0x0 }, // 7891 |
13883 | | { PseudoVSM_V_B32, VSM_V, 0x2, 0x0 }, // 7892 |
13884 | | { PseudoVSM_V_B64, VSM_V, 0x3, 0x0 }, // 7893 |
13885 | | { PseudoVSM_V_B1, VSM_V, 0x5, 0x0 }, // 7894 |
13886 | | { PseudoVSM_V_B2, VSM_V, 0x6, 0x0 }, // 7895 |
13887 | | { PseudoVSM_V_B4, VSM_V, 0x7, 0x0 }, // 7896 |
13888 | | { PseudoVSOXEI16_V_M1_M1, VSOXEI16_V, 0x0, 0x0 }, // 7897 |
13889 | | { PseudoVSOXEI16_V_M1_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 7898 |
13890 | | { PseudoVSOXEI16_V_M2_M1, VSOXEI16_V, 0x0, 0x0 }, // 7899 |
13891 | | { PseudoVSOXEI16_V_M2_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 7900 |
13892 | | { PseudoVSOXEI16_V_MF2_M1, VSOXEI16_V, 0x0, 0x0 }, // 7901 |
13893 | | { PseudoVSOXEI16_V_MF2_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 7902 |
13894 | | { PseudoVSOXEI16_V_MF4_M1, VSOXEI16_V, 0x0, 0x0 }, // 7903 |
13895 | | { PseudoVSOXEI16_V_MF4_M1_MASK, VSOXEI16_V, 0x0, 0x0 }, // 7904 |
13896 | | { PseudoVSOXEI16_V_M1_M2, VSOXEI16_V, 0x1, 0x0 }, // 7905 |
13897 | | { PseudoVSOXEI16_V_M1_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 7906 |
13898 | | { PseudoVSOXEI16_V_M2_M2, VSOXEI16_V, 0x1, 0x0 }, // 7907 |
13899 | | { PseudoVSOXEI16_V_M2_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 7908 |
13900 | | { PseudoVSOXEI16_V_M4_M2, VSOXEI16_V, 0x1, 0x0 }, // 7909 |
13901 | | { PseudoVSOXEI16_V_M4_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 7910 |
13902 | | { PseudoVSOXEI16_V_MF2_M2, VSOXEI16_V, 0x1, 0x0 }, // 7911 |
13903 | | { PseudoVSOXEI16_V_MF2_M2_MASK, VSOXEI16_V, 0x1, 0x0 }, // 7912 |
13904 | | { PseudoVSOXEI16_V_M1_M4, VSOXEI16_V, 0x2, 0x0 }, // 7913 |
13905 | | { PseudoVSOXEI16_V_M1_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 7914 |
13906 | | { PseudoVSOXEI16_V_M2_M4, VSOXEI16_V, 0x2, 0x0 }, // 7915 |
13907 | | { PseudoVSOXEI16_V_M2_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 7916 |
13908 | | { PseudoVSOXEI16_V_M4_M4, VSOXEI16_V, 0x2, 0x0 }, // 7917 |
13909 | | { PseudoVSOXEI16_V_M4_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 7918 |
13910 | | { PseudoVSOXEI16_V_M8_M4, VSOXEI16_V, 0x2, 0x0 }, // 7919 |
13911 | | { PseudoVSOXEI16_V_M8_M4_MASK, VSOXEI16_V, 0x2, 0x0 }, // 7920 |
13912 | | { PseudoVSOXEI16_V_M2_M8, VSOXEI16_V, 0x3, 0x0 }, // 7921 |
13913 | | { PseudoVSOXEI16_V_M2_M8_MASK, VSOXEI16_V, 0x3, 0x0 }, // 7922 |
13914 | | { PseudoVSOXEI16_V_M4_M8, VSOXEI16_V, 0x3, 0x0 }, // 7923 |
13915 | | { PseudoVSOXEI16_V_M4_M8_MASK, VSOXEI16_V, 0x3, 0x0 }, // 7924 |
13916 | | { PseudoVSOXEI16_V_M8_M8, VSOXEI16_V, 0x3, 0x0 }, // 7925 |
13917 | | { PseudoVSOXEI16_V_M8_M8_MASK, VSOXEI16_V, 0x3, 0x0 }, // 7926 |
13918 | | { PseudoVSOXEI16_V_MF4_MF8, VSOXEI16_V, 0x5, 0x0 }, // 7927 |
13919 | | { PseudoVSOXEI16_V_MF4_MF8_MASK, VSOXEI16_V, 0x5, 0x0 }, // 7928 |
13920 | | { PseudoVSOXEI16_V_MF2_MF4, VSOXEI16_V, 0x6, 0x0 }, // 7929 |
13921 | | { PseudoVSOXEI16_V_MF2_MF4_MASK, VSOXEI16_V, 0x6, 0x0 }, // 7930 |
13922 | | { PseudoVSOXEI16_V_MF4_MF4, VSOXEI16_V, 0x6, 0x0 }, // 7931 |
13923 | | { PseudoVSOXEI16_V_MF4_MF4_MASK, VSOXEI16_V, 0x6, 0x0 }, // 7932 |
13924 | | { PseudoVSOXEI16_V_M1_MF2, VSOXEI16_V, 0x7, 0x0 }, // 7933 |
13925 | | { PseudoVSOXEI16_V_M1_MF2_MASK, VSOXEI16_V, 0x7, 0x0 }, // 7934 |
13926 | | { PseudoVSOXEI16_V_MF2_MF2, VSOXEI16_V, 0x7, 0x0 }, // 7935 |
13927 | | { PseudoVSOXEI16_V_MF2_MF2_MASK, VSOXEI16_V, 0x7, 0x0 }, // 7936 |
13928 | | { PseudoVSOXEI16_V_MF4_MF2, VSOXEI16_V, 0x7, 0x0 }, // 7937 |
13929 | | { PseudoVSOXEI16_V_MF4_MF2_MASK, VSOXEI16_V, 0x7, 0x0 }, // 7938 |
13930 | | { PseudoVSOXEI32_V_M1_M1, VSOXEI32_V, 0x0, 0x0 }, // 7939 |
13931 | | { PseudoVSOXEI32_V_M1_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 7940 |
13932 | | { PseudoVSOXEI32_V_M2_M1, VSOXEI32_V, 0x0, 0x0 }, // 7941 |
13933 | | { PseudoVSOXEI32_V_M2_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 7942 |
13934 | | { PseudoVSOXEI32_V_M4_M1, VSOXEI32_V, 0x0, 0x0 }, // 7943 |
13935 | | { PseudoVSOXEI32_V_M4_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 7944 |
13936 | | { PseudoVSOXEI32_V_MF2_M1, VSOXEI32_V, 0x0, 0x0 }, // 7945 |
13937 | | { PseudoVSOXEI32_V_MF2_M1_MASK, VSOXEI32_V, 0x0, 0x0 }, // 7946 |
13938 | | { PseudoVSOXEI32_V_M1_M2, VSOXEI32_V, 0x1, 0x0 }, // 7947 |
13939 | | { PseudoVSOXEI32_V_M1_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 7948 |
13940 | | { PseudoVSOXEI32_V_M2_M2, VSOXEI32_V, 0x1, 0x0 }, // 7949 |
13941 | | { PseudoVSOXEI32_V_M2_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 7950 |
13942 | | { PseudoVSOXEI32_V_M4_M2, VSOXEI32_V, 0x1, 0x0 }, // 7951 |
13943 | | { PseudoVSOXEI32_V_M4_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 7952 |
13944 | | { PseudoVSOXEI32_V_M8_M2, VSOXEI32_V, 0x1, 0x0 }, // 7953 |
13945 | | { PseudoVSOXEI32_V_M8_M2_MASK, VSOXEI32_V, 0x1, 0x0 }, // 7954 |
13946 | | { PseudoVSOXEI32_V_M2_M4, VSOXEI32_V, 0x2, 0x0 }, // 7955 |
13947 | | { PseudoVSOXEI32_V_M2_M4_MASK, VSOXEI32_V, 0x2, 0x0 }, // 7956 |
13948 | | { PseudoVSOXEI32_V_M4_M4, VSOXEI32_V, 0x2, 0x0 }, // 7957 |
13949 | | { PseudoVSOXEI32_V_M4_M4_MASK, VSOXEI32_V, 0x2, 0x0 }, // 7958 |
13950 | | { PseudoVSOXEI32_V_M8_M4, VSOXEI32_V, 0x2, 0x0 }, // 7959 |
13951 | | { PseudoVSOXEI32_V_M8_M4_MASK, VSOXEI32_V, 0x2, 0x0 }, // 7960 |
13952 | | { PseudoVSOXEI32_V_M4_M8, VSOXEI32_V, 0x3, 0x0 }, // 7961 |
13953 | | { PseudoVSOXEI32_V_M4_M8_MASK, VSOXEI32_V, 0x3, 0x0 }, // 7962 |
13954 | | { PseudoVSOXEI32_V_M8_M8, VSOXEI32_V, 0x3, 0x0 }, // 7963 |
13955 | | { PseudoVSOXEI32_V_M8_M8_MASK, VSOXEI32_V, 0x3, 0x0 }, // 7964 |
13956 | | { PseudoVSOXEI32_V_MF2_MF8, VSOXEI32_V, 0x5, 0x0 }, // 7965 |
13957 | | { PseudoVSOXEI32_V_MF2_MF8_MASK, VSOXEI32_V, 0x5, 0x0 }, // 7966 |
13958 | | { PseudoVSOXEI32_V_M1_MF4, VSOXEI32_V, 0x6, 0x0 }, // 7967 |
13959 | | { PseudoVSOXEI32_V_M1_MF4_MASK, VSOXEI32_V, 0x6, 0x0 }, // 7968 |
13960 | | { PseudoVSOXEI32_V_MF2_MF4, VSOXEI32_V, 0x6, 0x0 }, // 7969 |
13961 | | { PseudoVSOXEI32_V_MF2_MF4_MASK, VSOXEI32_V, 0x6, 0x0 }, // 7970 |
13962 | | { PseudoVSOXEI32_V_M1_MF2, VSOXEI32_V, 0x7, 0x0 }, // 7971 |
13963 | | { PseudoVSOXEI32_V_M1_MF2_MASK, VSOXEI32_V, 0x7, 0x0 }, // 7972 |
13964 | | { PseudoVSOXEI32_V_M2_MF2, VSOXEI32_V, 0x7, 0x0 }, // 7973 |
13965 | | { PseudoVSOXEI32_V_M2_MF2_MASK, VSOXEI32_V, 0x7, 0x0 }, // 7974 |
13966 | | { PseudoVSOXEI32_V_MF2_MF2, VSOXEI32_V, 0x7, 0x0 }, // 7975 |
13967 | | { PseudoVSOXEI32_V_MF2_MF2_MASK, VSOXEI32_V, 0x7, 0x0 }, // 7976 |
13968 | | { PseudoVSOXEI64_V_M1_M1, VSOXEI64_V, 0x0, 0x0 }, // 7977 |
13969 | | { PseudoVSOXEI64_V_M1_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 7978 |
13970 | | { PseudoVSOXEI64_V_M2_M1, VSOXEI64_V, 0x0, 0x0 }, // 7979 |
13971 | | { PseudoVSOXEI64_V_M2_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 7980 |
13972 | | { PseudoVSOXEI64_V_M4_M1, VSOXEI64_V, 0x0, 0x0 }, // 7981 |
13973 | | { PseudoVSOXEI64_V_M4_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 7982 |
13974 | | { PseudoVSOXEI64_V_M8_M1, VSOXEI64_V, 0x0, 0x0 }, // 7983 |
13975 | | { PseudoVSOXEI64_V_M8_M1_MASK, VSOXEI64_V, 0x0, 0x0 }, // 7984 |
13976 | | { PseudoVSOXEI64_V_M2_M2, VSOXEI64_V, 0x1, 0x0 }, // 7985 |
13977 | | { PseudoVSOXEI64_V_M2_M2_MASK, VSOXEI64_V, 0x1, 0x0 }, // 7986 |
13978 | | { PseudoVSOXEI64_V_M4_M2, VSOXEI64_V, 0x1, 0x0 }, // 7987 |
13979 | | { PseudoVSOXEI64_V_M4_M2_MASK, VSOXEI64_V, 0x1, 0x0 }, // 7988 |
13980 | | { PseudoVSOXEI64_V_M8_M2, VSOXEI64_V, 0x1, 0x0 }, // 7989 |
13981 | | { PseudoVSOXEI64_V_M8_M2_MASK, VSOXEI64_V, 0x1, 0x0 }, // 7990 |
13982 | | { PseudoVSOXEI64_V_M4_M4, VSOXEI64_V, 0x2, 0x0 }, // 7991 |
13983 | | { PseudoVSOXEI64_V_M4_M4_MASK, VSOXEI64_V, 0x2, 0x0 }, // 7992 |
13984 | | { PseudoVSOXEI64_V_M8_M4, VSOXEI64_V, 0x2, 0x0 }, // 7993 |
13985 | | { PseudoVSOXEI64_V_M8_M4_MASK, VSOXEI64_V, 0x2, 0x0 }, // 7994 |
13986 | | { PseudoVSOXEI64_V_M8_M8, VSOXEI64_V, 0x3, 0x0 }, // 7995 |
13987 | | { PseudoVSOXEI64_V_M8_M8_MASK, VSOXEI64_V, 0x3, 0x0 }, // 7996 |
13988 | | { PseudoVSOXEI64_V_M1_MF8, VSOXEI64_V, 0x5, 0x0 }, // 7997 |
13989 | | { PseudoVSOXEI64_V_M1_MF8_MASK, VSOXEI64_V, 0x5, 0x0 }, // 7998 |
13990 | | { PseudoVSOXEI64_V_M1_MF4, VSOXEI64_V, 0x6, 0x0 }, // 7999 |
13991 | | { PseudoVSOXEI64_V_M1_MF4_MASK, VSOXEI64_V, 0x6, 0x0 }, // 8000 |
13992 | | { PseudoVSOXEI64_V_M2_MF4, VSOXEI64_V, 0x6, 0x0 }, // 8001 |
13993 | | { PseudoVSOXEI64_V_M2_MF4_MASK, VSOXEI64_V, 0x6, 0x0 }, // 8002 |
13994 | | { PseudoVSOXEI64_V_M1_MF2, VSOXEI64_V, 0x7, 0x0 }, // 8003 |
13995 | | { PseudoVSOXEI64_V_M1_MF2_MASK, VSOXEI64_V, 0x7, 0x0 }, // 8004 |
13996 | | { PseudoVSOXEI64_V_M2_MF2, VSOXEI64_V, 0x7, 0x0 }, // 8005 |
13997 | | { PseudoVSOXEI64_V_M2_MF2_MASK, VSOXEI64_V, 0x7, 0x0 }, // 8006 |
13998 | | { PseudoVSOXEI64_V_M4_MF2, VSOXEI64_V, 0x7, 0x0 }, // 8007 |
13999 | | { PseudoVSOXEI64_V_M4_MF2_MASK, VSOXEI64_V, 0x7, 0x0 }, // 8008 |
14000 | | { PseudoVSOXEI8_V_M1_M1, VSOXEI8_V, 0x0, 0x0 }, // 8009 |
14001 | | { PseudoVSOXEI8_V_M1_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8010 |
14002 | | { PseudoVSOXEI8_V_MF2_M1, VSOXEI8_V, 0x0, 0x0 }, // 8011 |
14003 | | { PseudoVSOXEI8_V_MF2_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8012 |
14004 | | { PseudoVSOXEI8_V_MF4_M1, VSOXEI8_V, 0x0, 0x0 }, // 8013 |
14005 | | { PseudoVSOXEI8_V_MF4_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8014 |
14006 | | { PseudoVSOXEI8_V_MF8_M1, VSOXEI8_V, 0x0, 0x0 }, // 8015 |
14007 | | { PseudoVSOXEI8_V_MF8_M1_MASK, VSOXEI8_V, 0x0, 0x0 }, // 8016 |
14008 | | { PseudoVSOXEI8_V_M1_M2, VSOXEI8_V, 0x1, 0x0 }, // 8017 |
14009 | | { PseudoVSOXEI8_V_M1_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8018 |
14010 | | { PseudoVSOXEI8_V_M2_M2, VSOXEI8_V, 0x1, 0x0 }, // 8019 |
14011 | | { PseudoVSOXEI8_V_M2_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8020 |
14012 | | { PseudoVSOXEI8_V_MF2_M2, VSOXEI8_V, 0x1, 0x0 }, // 8021 |
14013 | | { PseudoVSOXEI8_V_MF2_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8022 |
14014 | | { PseudoVSOXEI8_V_MF4_M2, VSOXEI8_V, 0x1, 0x0 }, // 8023 |
14015 | | { PseudoVSOXEI8_V_MF4_M2_MASK, VSOXEI8_V, 0x1, 0x0 }, // 8024 |
14016 | | { PseudoVSOXEI8_V_M1_M4, VSOXEI8_V, 0x2, 0x0 }, // 8025 |
14017 | | { PseudoVSOXEI8_V_M1_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8026 |
14018 | | { PseudoVSOXEI8_V_M2_M4, VSOXEI8_V, 0x2, 0x0 }, // 8027 |
14019 | | { PseudoVSOXEI8_V_M2_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8028 |
14020 | | { PseudoVSOXEI8_V_M4_M4, VSOXEI8_V, 0x2, 0x0 }, // 8029 |
14021 | | { PseudoVSOXEI8_V_M4_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8030 |
14022 | | { PseudoVSOXEI8_V_MF2_M4, VSOXEI8_V, 0x2, 0x0 }, // 8031 |
14023 | | { PseudoVSOXEI8_V_MF2_M4_MASK, VSOXEI8_V, 0x2, 0x0 }, // 8032 |
14024 | | { PseudoVSOXEI8_V_M1_M8, VSOXEI8_V, 0x3, 0x0 }, // 8033 |
14025 | | { PseudoVSOXEI8_V_M1_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8034 |
14026 | | { PseudoVSOXEI8_V_M2_M8, VSOXEI8_V, 0x3, 0x0 }, // 8035 |
14027 | | { PseudoVSOXEI8_V_M2_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8036 |
14028 | | { PseudoVSOXEI8_V_M4_M8, VSOXEI8_V, 0x3, 0x0 }, // 8037 |
14029 | | { PseudoVSOXEI8_V_M4_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8038 |
14030 | | { PseudoVSOXEI8_V_M8_M8, VSOXEI8_V, 0x3, 0x0 }, // 8039 |
14031 | | { PseudoVSOXEI8_V_M8_M8_MASK, VSOXEI8_V, 0x3, 0x0 }, // 8040 |
14032 | | { PseudoVSOXEI8_V_MF8_MF8, VSOXEI8_V, 0x5, 0x0 }, // 8041 |
14033 | | { PseudoVSOXEI8_V_MF8_MF8_MASK, VSOXEI8_V, 0x5, 0x0 }, // 8042 |
14034 | | { PseudoVSOXEI8_V_MF4_MF4, VSOXEI8_V, 0x6, 0x0 }, // 8043 |
14035 | | { PseudoVSOXEI8_V_MF4_MF4_MASK, VSOXEI8_V, 0x6, 0x0 }, // 8044 |
14036 | | { PseudoVSOXEI8_V_MF8_MF4, VSOXEI8_V, 0x6, 0x0 }, // 8045 |
14037 | | { PseudoVSOXEI8_V_MF8_MF4_MASK, VSOXEI8_V, 0x6, 0x0 }, // 8046 |
14038 | | { PseudoVSOXEI8_V_MF2_MF2, VSOXEI8_V, 0x7, 0x0 }, // 8047 |
14039 | | { PseudoVSOXEI8_V_MF2_MF2_MASK, VSOXEI8_V, 0x7, 0x0 }, // 8048 |
14040 | | { PseudoVSOXEI8_V_MF4_MF2, VSOXEI8_V, 0x7, 0x0 }, // 8049 |
14041 | | { PseudoVSOXEI8_V_MF4_MF2_MASK, VSOXEI8_V, 0x7, 0x0 }, // 8050 |
14042 | | { PseudoVSOXEI8_V_MF8_MF2, VSOXEI8_V, 0x7, 0x0 }, // 8051 |
14043 | | { PseudoVSOXEI8_V_MF8_MF2_MASK, VSOXEI8_V, 0x7, 0x0 }, // 8052 |
14044 | | { PseudoVSOXSEG2EI16_V_M1_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8053 |
14045 | | { PseudoVSOXSEG2EI16_V_M1_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8054 |
14046 | | { PseudoVSOXSEG2EI16_V_M2_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8055 |
14047 | | { PseudoVSOXSEG2EI16_V_M2_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8056 |
14048 | | { PseudoVSOXSEG2EI16_V_MF2_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8057 |
14049 | | { PseudoVSOXSEG2EI16_V_MF2_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8058 |
14050 | | { PseudoVSOXSEG2EI16_V_MF4_M1, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8059 |
14051 | | { PseudoVSOXSEG2EI16_V_MF4_M1_MASK, VSOXSEG2EI16_V, 0x0, 0x0 }, // 8060 |
14052 | | { PseudoVSOXSEG2EI16_V_M1_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8061 |
14053 | | { PseudoVSOXSEG2EI16_V_M1_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8062 |
14054 | | { PseudoVSOXSEG2EI16_V_M2_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8063 |
14055 | | { PseudoVSOXSEG2EI16_V_M2_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8064 |
14056 | | { PseudoVSOXSEG2EI16_V_M4_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8065 |
14057 | | { PseudoVSOXSEG2EI16_V_M4_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8066 |
14058 | | { PseudoVSOXSEG2EI16_V_MF2_M2, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8067 |
14059 | | { PseudoVSOXSEG2EI16_V_MF2_M2_MASK, VSOXSEG2EI16_V, 0x1, 0x0 }, // 8068 |
14060 | | { PseudoVSOXSEG2EI16_V_M1_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8069 |
14061 | | { PseudoVSOXSEG2EI16_V_M1_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8070 |
14062 | | { PseudoVSOXSEG2EI16_V_M2_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8071 |
14063 | | { PseudoVSOXSEG2EI16_V_M2_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8072 |
14064 | | { PseudoVSOXSEG2EI16_V_M4_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8073 |
14065 | | { PseudoVSOXSEG2EI16_V_M4_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8074 |
14066 | | { PseudoVSOXSEG2EI16_V_M8_M4, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8075 |
14067 | | { PseudoVSOXSEG2EI16_V_M8_M4_MASK, VSOXSEG2EI16_V, 0x2, 0x0 }, // 8076 |
14068 | | { PseudoVSOXSEG2EI16_V_MF4_MF8, VSOXSEG2EI16_V, 0x5, 0x0 }, // 8077 |
14069 | | { PseudoVSOXSEG2EI16_V_MF4_MF8_MASK, VSOXSEG2EI16_V, 0x5, 0x0 }, // 8078 |
14070 | | { PseudoVSOXSEG2EI16_V_MF2_MF4, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8079 |
14071 | | { PseudoVSOXSEG2EI16_V_MF2_MF4_MASK, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8080 |
14072 | | { PseudoVSOXSEG2EI16_V_MF4_MF4, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8081 |
14073 | | { PseudoVSOXSEG2EI16_V_MF4_MF4_MASK, VSOXSEG2EI16_V, 0x6, 0x0 }, // 8082 |
14074 | | { PseudoVSOXSEG2EI16_V_M1_MF2, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8083 |
14075 | | { PseudoVSOXSEG2EI16_V_M1_MF2_MASK, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8084 |
14076 | | { PseudoVSOXSEG2EI16_V_MF2_MF2, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8085 |
14077 | | { PseudoVSOXSEG2EI16_V_MF2_MF2_MASK, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8086 |
14078 | | { PseudoVSOXSEG2EI16_V_MF4_MF2, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8087 |
14079 | | { PseudoVSOXSEG2EI16_V_MF4_MF2_MASK, VSOXSEG2EI16_V, 0x7, 0x0 }, // 8088 |
14080 | | { PseudoVSOXSEG2EI32_V_M1_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8089 |
14081 | | { PseudoVSOXSEG2EI32_V_M1_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8090 |
14082 | | { PseudoVSOXSEG2EI32_V_M2_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8091 |
14083 | | { PseudoVSOXSEG2EI32_V_M2_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8092 |
14084 | | { PseudoVSOXSEG2EI32_V_M4_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8093 |
14085 | | { PseudoVSOXSEG2EI32_V_M4_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8094 |
14086 | | { PseudoVSOXSEG2EI32_V_MF2_M1, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8095 |
14087 | | { PseudoVSOXSEG2EI32_V_MF2_M1_MASK, VSOXSEG2EI32_V, 0x0, 0x0 }, // 8096 |
14088 | | { PseudoVSOXSEG2EI32_V_M1_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8097 |
14089 | | { PseudoVSOXSEG2EI32_V_M1_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8098 |
14090 | | { PseudoVSOXSEG2EI32_V_M2_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8099 |
14091 | | { PseudoVSOXSEG2EI32_V_M2_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8100 |
14092 | | { PseudoVSOXSEG2EI32_V_M4_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8101 |
14093 | | { PseudoVSOXSEG2EI32_V_M4_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8102 |
14094 | | { PseudoVSOXSEG2EI32_V_M8_M2, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8103 |
14095 | | { PseudoVSOXSEG2EI32_V_M8_M2_MASK, VSOXSEG2EI32_V, 0x1, 0x0 }, // 8104 |
14096 | | { PseudoVSOXSEG2EI32_V_M2_M4, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8105 |
14097 | | { PseudoVSOXSEG2EI32_V_M2_M4_MASK, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8106 |
14098 | | { PseudoVSOXSEG2EI32_V_M4_M4, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8107 |
14099 | | { PseudoVSOXSEG2EI32_V_M4_M4_MASK, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8108 |
14100 | | { PseudoVSOXSEG2EI32_V_M8_M4, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8109 |
14101 | | { PseudoVSOXSEG2EI32_V_M8_M4_MASK, VSOXSEG2EI32_V, 0x2, 0x0 }, // 8110 |
14102 | | { PseudoVSOXSEG2EI32_V_MF2_MF8, VSOXSEG2EI32_V, 0x5, 0x0 }, // 8111 |
14103 | | { PseudoVSOXSEG2EI32_V_MF2_MF8_MASK, VSOXSEG2EI32_V, 0x5, 0x0 }, // 8112 |
14104 | | { PseudoVSOXSEG2EI32_V_M1_MF4, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8113 |
14105 | | { PseudoVSOXSEG2EI32_V_M1_MF4_MASK, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8114 |
14106 | | { PseudoVSOXSEG2EI32_V_MF2_MF4, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8115 |
14107 | | { PseudoVSOXSEG2EI32_V_MF2_MF4_MASK, VSOXSEG2EI32_V, 0x6, 0x0 }, // 8116 |
14108 | | { PseudoVSOXSEG2EI32_V_M1_MF2, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8117 |
14109 | | { PseudoVSOXSEG2EI32_V_M1_MF2_MASK, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8118 |
14110 | | { PseudoVSOXSEG2EI32_V_M2_MF2, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8119 |
14111 | | { PseudoVSOXSEG2EI32_V_M2_MF2_MASK, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8120 |
14112 | | { PseudoVSOXSEG2EI32_V_MF2_MF2, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8121 |
14113 | | { PseudoVSOXSEG2EI32_V_MF2_MF2_MASK, VSOXSEG2EI32_V, 0x7, 0x0 }, // 8122 |
14114 | | { PseudoVSOXSEG2EI64_V_M1_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8123 |
14115 | | { PseudoVSOXSEG2EI64_V_M1_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8124 |
14116 | | { PseudoVSOXSEG2EI64_V_M2_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8125 |
14117 | | { PseudoVSOXSEG2EI64_V_M2_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8126 |
14118 | | { PseudoVSOXSEG2EI64_V_M4_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8127 |
14119 | | { PseudoVSOXSEG2EI64_V_M4_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8128 |
14120 | | { PseudoVSOXSEG2EI64_V_M8_M1, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8129 |
14121 | | { PseudoVSOXSEG2EI64_V_M8_M1_MASK, VSOXSEG2EI64_V, 0x0, 0x0 }, // 8130 |
14122 | | { PseudoVSOXSEG2EI64_V_M2_M2, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8131 |
14123 | | { PseudoVSOXSEG2EI64_V_M2_M2_MASK, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8132 |
14124 | | { PseudoVSOXSEG2EI64_V_M4_M2, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8133 |
14125 | | { PseudoVSOXSEG2EI64_V_M4_M2_MASK, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8134 |
14126 | | { PseudoVSOXSEG2EI64_V_M8_M2, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8135 |
14127 | | { PseudoVSOXSEG2EI64_V_M8_M2_MASK, VSOXSEG2EI64_V, 0x1, 0x0 }, // 8136 |
14128 | | { PseudoVSOXSEG2EI64_V_M4_M4, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8137 |
14129 | | { PseudoVSOXSEG2EI64_V_M4_M4_MASK, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8138 |
14130 | | { PseudoVSOXSEG2EI64_V_M8_M4, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8139 |
14131 | | { PseudoVSOXSEG2EI64_V_M8_M4_MASK, VSOXSEG2EI64_V, 0x2, 0x0 }, // 8140 |
14132 | | { PseudoVSOXSEG2EI64_V_M1_MF8, VSOXSEG2EI64_V, 0x5, 0x0 }, // 8141 |
14133 | | { PseudoVSOXSEG2EI64_V_M1_MF8_MASK, VSOXSEG2EI64_V, 0x5, 0x0 }, // 8142 |
14134 | | { PseudoVSOXSEG2EI64_V_M1_MF4, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8143 |
14135 | | { PseudoVSOXSEG2EI64_V_M1_MF4_MASK, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8144 |
14136 | | { PseudoVSOXSEG2EI64_V_M2_MF4, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8145 |
14137 | | { PseudoVSOXSEG2EI64_V_M2_MF4_MASK, VSOXSEG2EI64_V, 0x6, 0x0 }, // 8146 |
14138 | | { PseudoVSOXSEG2EI64_V_M1_MF2, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8147 |
14139 | | { PseudoVSOXSEG2EI64_V_M1_MF2_MASK, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8148 |
14140 | | { PseudoVSOXSEG2EI64_V_M2_MF2, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8149 |
14141 | | { PseudoVSOXSEG2EI64_V_M2_MF2_MASK, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8150 |
14142 | | { PseudoVSOXSEG2EI64_V_M4_MF2, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8151 |
14143 | | { PseudoVSOXSEG2EI64_V_M4_MF2_MASK, VSOXSEG2EI64_V, 0x7, 0x0 }, // 8152 |
14144 | | { PseudoVSOXSEG2EI8_V_M1_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8153 |
14145 | | { PseudoVSOXSEG2EI8_V_M1_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8154 |
14146 | | { PseudoVSOXSEG2EI8_V_MF2_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8155 |
14147 | | { PseudoVSOXSEG2EI8_V_MF2_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8156 |
14148 | | { PseudoVSOXSEG2EI8_V_MF4_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8157 |
14149 | | { PseudoVSOXSEG2EI8_V_MF4_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8158 |
14150 | | { PseudoVSOXSEG2EI8_V_MF8_M1, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8159 |
14151 | | { PseudoVSOXSEG2EI8_V_MF8_M1_MASK, VSOXSEG2EI8_V, 0x0, 0x0 }, // 8160 |
14152 | | { PseudoVSOXSEG2EI8_V_M1_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8161 |
14153 | | { PseudoVSOXSEG2EI8_V_M1_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8162 |
14154 | | { PseudoVSOXSEG2EI8_V_M2_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8163 |
14155 | | { PseudoVSOXSEG2EI8_V_M2_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8164 |
14156 | | { PseudoVSOXSEG2EI8_V_MF2_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8165 |
14157 | | { PseudoVSOXSEG2EI8_V_MF2_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8166 |
14158 | | { PseudoVSOXSEG2EI8_V_MF4_M2, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8167 |
14159 | | { PseudoVSOXSEG2EI8_V_MF4_M2_MASK, VSOXSEG2EI8_V, 0x1, 0x0 }, // 8168 |
14160 | | { PseudoVSOXSEG2EI8_V_M1_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8169 |
14161 | | { PseudoVSOXSEG2EI8_V_M1_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8170 |
14162 | | { PseudoVSOXSEG2EI8_V_M2_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8171 |
14163 | | { PseudoVSOXSEG2EI8_V_M2_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8172 |
14164 | | { PseudoVSOXSEG2EI8_V_M4_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8173 |
14165 | | { PseudoVSOXSEG2EI8_V_M4_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8174 |
14166 | | { PseudoVSOXSEG2EI8_V_MF2_M4, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8175 |
14167 | | { PseudoVSOXSEG2EI8_V_MF2_M4_MASK, VSOXSEG2EI8_V, 0x2, 0x0 }, // 8176 |
14168 | | { PseudoVSOXSEG2EI8_V_MF8_MF8, VSOXSEG2EI8_V, 0x5, 0x0 }, // 8177 |
14169 | | { PseudoVSOXSEG2EI8_V_MF8_MF8_MASK, VSOXSEG2EI8_V, 0x5, 0x0 }, // 8178 |
14170 | | { PseudoVSOXSEG2EI8_V_MF4_MF4, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8179 |
14171 | | { PseudoVSOXSEG2EI8_V_MF4_MF4_MASK, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8180 |
14172 | | { PseudoVSOXSEG2EI8_V_MF8_MF4, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8181 |
14173 | | { PseudoVSOXSEG2EI8_V_MF8_MF4_MASK, VSOXSEG2EI8_V, 0x6, 0x0 }, // 8182 |
14174 | | { PseudoVSOXSEG2EI8_V_MF2_MF2, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8183 |
14175 | | { PseudoVSOXSEG2EI8_V_MF2_MF2_MASK, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8184 |
14176 | | { PseudoVSOXSEG2EI8_V_MF4_MF2, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8185 |
14177 | | { PseudoVSOXSEG2EI8_V_MF4_MF2_MASK, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8186 |
14178 | | { PseudoVSOXSEG2EI8_V_MF8_MF2, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8187 |
14179 | | { PseudoVSOXSEG2EI8_V_MF8_MF2_MASK, VSOXSEG2EI8_V, 0x7, 0x0 }, // 8188 |
14180 | | { PseudoVSOXSEG3EI16_V_M1_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8189 |
14181 | | { PseudoVSOXSEG3EI16_V_M1_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8190 |
14182 | | { PseudoVSOXSEG3EI16_V_M2_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8191 |
14183 | | { PseudoVSOXSEG3EI16_V_M2_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8192 |
14184 | | { PseudoVSOXSEG3EI16_V_MF2_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8193 |
14185 | | { PseudoVSOXSEG3EI16_V_MF2_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8194 |
14186 | | { PseudoVSOXSEG3EI16_V_MF4_M1, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8195 |
14187 | | { PseudoVSOXSEG3EI16_V_MF4_M1_MASK, VSOXSEG3EI16_V, 0x0, 0x0 }, // 8196 |
14188 | | { PseudoVSOXSEG3EI16_V_M1_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8197 |
14189 | | { PseudoVSOXSEG3EI16_V_M1_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8198 |
14190 | | { PseudoVSOXSEG3EI16_V_M2_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8199 |
14191 | | { PseudoVSOXSEG3EI16_V_M2_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8200 |
14192 | | { PseudoVSOXSEG3EI16_V_M4_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8201 |
14193 | | { PseudoVSOXSEG3EI16_V_M4_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8202 |
14194 | | { PseudoVSOXSEG3EI16_V_MF2_M2, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8203 |
14195 | | { PseudoVSOXSEG3EI16_V_MF2_M2_MASK, VSOXSEG3EI16_V, 0x1, 0x0 }, // 8204 |
14196 | | { PseudoVSOXSEG3EI16_V_MF4_MF8, VSOXSEG3EI16_V, 0x5, 0x0 }, // 8205 |
14197 | | { PseudoVSOXSEG3EI16_V_MF4_MF8_MASK, VSOXSEG3EI16_V, 0x5, 0x0 }, // 8206 |
14198 | | { PseudoVSOXSEG3EI16_V_MF2_MF4, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8207 |
14199 | | { PseudoVSOXSEG3EI16_V_MF2_MF4_MASK, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8208 |
14200 | | { PseudoVSOXSEG3EI16_V_MF4_MF4, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8209 |
14201 | | { PseudoVSOXSEG3EI16_V_MF4_MF4_MASK, VSOXSEG3EI16_V, 0x6, 0x0 }, // 8210 |
14202 | | { PseudoVSOXSEG3EI16_V_M1_MF2, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8211 |
14203 | | { PseudoVSOXSEG3EI16_V_M1_MF2_MASK, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8212 |
14204 | | { PseudoVSOXSEG3EI16_V_MF2_MF2, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8213 |
14205 | | { PseudoVSOXSEG3EI16_V_MF2_MF2_MASK, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8214 |
14206 | | { PseudoVSOXSEG3EI16_V_MF4_MF2, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8215 |
14207 | | { PseudoVSOXSEG3EI16_V_MF4_MF2_MASK, VSOXSEG3EI16_V, 0x7, 0x0 }, // 8216 |
14208 | | { PseudoVSOXSEG3EI32_V_M1_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8217 |
14209 | | { PseudoVSOXSEG3EI32_V_M1_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8218 |
14210 | | { PseudoVSOXSEG3EI32_V_M2_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8219 |
14211 | | { PseudoVSOXSEG3EI32_V_M2_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8220 |
14212 | | { PseudoVSOXSEG3EI32_V_M4_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8221 |
14213 | | { PseudoVSOXSEG3EI32_V_M4_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8222 |
14214 | | { PseudoVSOXSEG3EI32_V_MF2_M1, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8223 |
14215 | | { PseudoVSOXSEG3EI32_V_MF2_M1_MASK, VSOXSEG3EI32_V, 0x0, 0x0 }, // 8224 |
14216 | | { PseudoVSOXSEG3EI32_V_M1_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8225 |
14217 | | { PseudoVSOXSEG3EI32_V_M1_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8226 |
14218 | | { PseudoVSOXSEG3EI32_V_M2_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8227 |
14219 | | { PseudoVSOXSEG3EI32_V_M2_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8228 |
14220 | | { PseudoVSOXSEG3EI32_V_M4_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8229 |
14221 | | { PseudoVSOXSEG3EI32_V_M4_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8230 |
14222 | | { PseudoVSOXSEG3EI32_V_M8_M2, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8231 |
14223 | | { PseudoVSOXSEG3EI32_V_M8_M2_MASK, VSOXSEG3EI32_V, 0x1, 0x0 }, // 8232 |
14224 | | { PseudoVSOXSEG3EI32_V_MF2_MF8, VSOXSEG3EI32_V, 0x5, 0x0 }, // 8233 |
14225 | | { PseudoVSOXSEG3EI32_V_MF2_MF8_MASK, VSOXSEG3EI32_V, 0x5, 0x0 }, // 8234 |
14226 | | { PseudoVSOXSEG3EI32_V_M1_MF4, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8235 |
14227 | | { PseudoVSOXSEG3EI32_V_M1_MF4_MASK, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8236 |
14228 | | { PseudoVSOXSEG3EI32_V_MF2_MF4, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8237 |
14229 | | { PseudoVSOXSEG3EI32_V_MF2_MF4_MASK, VSOXSEG3EI32_V, 0x6, 0x0 }, // 8238 |
14230 | | { PseudoVSOXSEG3EI32_V_M1_MF2, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8239 |
14231 | | { PseudoVSOXSEG3EI32_V_M1_MF2_MASK, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8240 |
14232 | | { PseudoVSOXSEG3EI32_V_M2_MF2, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8241 |
14233 | | { PseudoVSOXSEG3EI32_V_M2_MF2_MASK, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8242 |
14234 | | { PseudoVSOXSEG3EI32_V_MF2_MF2, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8243 |
14235 | | { PseudoVSOXSEG3EI32_V_MF2_MF2_MASK, VSOXSEG3EI32_V, 0x7, 0x0 }, // 8244 |
14236 | | { PseudoVSOXSEG3EI64_V_M1_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8245 |
14237 | | { PseudoVSOXSEG3EI64_V_M1_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8246 |
14238 | | { PseudoVSOXSEG3EI64_V_M2_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8247 |
14239 | | { PseudoVSOXSEG3EI64_V_M2_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8248 |
14240 | | { PseudoVSOXSEG3EI64_V_M4_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8249 |
14241 | | { PseudoVSOXSEG3EI64_V_M4_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8250 |
14242 | | { PseudoVSOXSEG3EI64_V_M8_M1, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8251 |
14243 | | { PseudoVSOXSEG3EI64_V_M8_M1_MASK, VSOXSEG3EI64_V, 0x0, 0x0 }, // 8252 |
14244 | | { PseudoVSOXSEG3EI64_V_M2_M2, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8253 |
14245 | | { PseudoVSOXSEG3EI64_V_M2_M2_MASK, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8254 |
14246 | | { PseudoVSOXSEG3EI64_V_M4_M2, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8255 |
14247 | | { PseudoVSOXSEG3EI64_V_M4_M2_MASK, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8256 |
14248 | | { PseudoVSOXSEG3EI64_V_M8_M2, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8257 |
14249 | | { PseudoVSOXSEG3EI64_V_M8_M2_MASK, VSOXSEG3EI64_V, 0x1, 0x0 }, // 8258 |
14250 | | { PseudoVSOXSEG3EI64_V_M1_MF8, VSOXSEG3EI64_V, 0x5, 0x0 }, // 8259 |
14251 | | { PseudoVSOXSEG3EI64_V_M1_MF8_MASK, VSOXSEG3EI64_V, 0x5, 0x0 }, // 8260 |
14252 | | { PseudoVSOXSEG3EI64_V_M1_MF4, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8261 |
14253 | | { PseudoVSOXSEG3EI64_V_M1_MF4_MASK, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8262 |
14254 | | { PseudoVSOXSEG3EI64_V_M2_MF4, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8263 |
14255 | | { PseudoVSOXSEG3EI64_V_M2_MF4_MASK, VSOXSEG3EI64_V, 0x6, 0x0 }, // 8264 |
14256 | | { PseudoVSOXSEG3EI64_V_M1_MF2, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8265 |
14257 | | { PseudoVSOXSEG3EI64_V_M1_MF2_MASK, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8266 |
14258 | | { PseudoVSOXSEG3EI64_V_M2_MF2, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8267 |
14259 | | { PseudoVSOXSEG3EI64_V_M2_MF2_MASK, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8268 |
14260 | | { PseudoVSOXSEG3EI64_V_M4_MF2, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8269 |
14261 | | { PseudoVSOXSEG3EI64_V_M4_MF2_MASK, VSOXSEG3EI64_V, 0x7, 0x0 }, // 8270 |
14262 | | { PseudoVSOXSEG3EI8_V_M1_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8271 |
14263 | | { PseudoVSOXSEG3EI8_V_M1_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8272 |
14264 | | { PseudoVSOXSEG3EI8_V_MF2_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8273 |
14265 | | { PseudoVSOXSEG3EI8_V_MF2_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8274 |
14266 | | { PseudoVSOXSEG3EI8_V_MF4_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8275 |
14267 | | { PseudoVSOXSEG3EI8_V_MF4_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8276 |
14268 | | { PseudoVSOXSEG3EI8_V_MF8_M1, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8277 |
14269 | | { PseudoVSOXSEG3EI8_V_MF8_M1_MASK, VSOXSEG3EI8_V, 0x0, 0x0 }, // 8278 |
14270 | | { PseudoVSOXSEG3EI8_V_M1_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8279 |
14271 | | { PseudoVSOXSEG3EI8_V_M1_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8280 |
14272 | | { PseudoVSOXSEG3EI8_V_M2_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8281 |
14273 | | { PseudoVSOXSEG3EI8_V_M2_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8282 |
14274 | | { PseudoVSOXSEG3EI8_V_MF2_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8283 |
14275 | | { PseudoVSOXSEG3EI8_V_MF2_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8284 |
14276 | | { PseudoVSOXSEG3EI8_V_MF4_M2, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8285 |
14277 | | { PseudoVSOXSEG3EI8_V_MF4_M2_MASK, VSOXSEG3EI8_V, 0x1, 0x0 }, // 8286 |
14278 | | { PseudoVSOXSEG3EI8_V_MF8_MF8, VSOXSEG3EI8_V, 0x5, 0x0 }, // 8287 |
14279 | | { PseudoVSOXSEG3EI8_V_MF8_MF8_MASK, VSOXSEG3EI8_V, 0x5, 0x0 }, // 8288 |
14280 | | { PseudoVSOXSEG3EI8_V_MF4_MF4, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8289 |
14281 | | { PseudoVSOXSEG3EI8_V_MF4_MF4_MASK, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8290 |
14282 | | { PseudoVSOXSEG3EI8_V_MF8_MF4, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8291 |
14283 | | { PseudoVSOXSEG3EI8_V_MF8_MF4_MASK, VSOXSEG3EI8_V, 0x6, 0x0 }, // 8292 |
14284 | | { PseudoVSOXSEG3EI8_V_MF2_MF2, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8293 |
14285 | | { PseudoVSOXSEG3EI8_V_MF2_MF2_MASK, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8294 |
14286 | | { PseudoVSOXSEG3EI8_V_MF4_MF2, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8295 |
14287 | | { PseudoVSOXSEG3EI8_V_MF4_MF2_MASK, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8296 |
14288 | | { PseudoVSOXSEG3EI8_V_MF8_MF2, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8297 |
14289 | | { PseudoVSOXSEG3EI8_V_MF8_MF2_MASK, VSOXSEG3EI8_V, 0x7, 0x0 }, // 8298 |
14290 | | { PseudoVSOXSEG4EI16_V_M1_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8299 |
14291 | | { PseudoVSOXSEG4EI16_V_M1_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8300 |
14292 | | { PseudoVSOXSEG4EI16_V_M2_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8301 |
14293 | | { PseudoVSOXSEG4EI16_V_M2_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8302 |
14294 | | { PseudoVSOXSEG4EI16_V_MF2_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8303 |
14295 | | { PseudoVSOXSEG4EI16_V_MF2_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8304 |
14296 | | { PseudoVSOXSEG4EI16_V_MF4_M1, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8305 |
14297 | | { PseudoVSOXSEG4EI16_V_MF4_M1_MASK, VSOXSEG4EI16_V, 0x0, 0x0 }, // 8306 |
14298 | | { PseudoVSOXSEG4EI16_V_M1_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8307 |
14299 | | { PseudoVSOXSEG4EI16_V_M1_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8308 |
14300 | | { PseudoVSOXSEG4EI16_V_M2_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8309 |
14301 | | { PseudoVSOXSEG4EI16_V_M2_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8310 |
14302 | | { PseudoVSOXSEG4EI16_V_M4_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8311 |
14303 | | { PseudoVSOXSEG4EI16_V_M4_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8312 |
14304 | | { PseudoVSOXSEG4EI16_V_MF2_M2, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8313 |
14305 | | { PseudoVSOXSEG4EI16_V_MF2_M2_MASK, VSOXSEG4EI16_V, 0x1, 0x0 }, // 8314 |
14306 | | { PseudoVSOXSEG4EI16_V_MF4_MF8, VSOXSEG4EI16_V, 0x5, 0x0 }, // 8315 |
14307 | | { PseudoVSOXSEG4EI16_V_MF4_MF8_MASK, VSOXSEG4EI16_V, 0x5, 0x0 }, // 8316 |
14308 | | { PseudoVSOXSEG4EI16_V_MF2_MF4, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8317 |
14309 | | { PseudoVSOXSEG4EI16_V_MF2_MF4_MASK, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8318 |
14310 | | { PseudoVSOXSEG4EI16_V_MF4_MF4, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8319 |
14311 | | { PseudoVSOXSEG4EI16_V_MF4_MF4_MASK, VSOXSEG4EI16_V, 0x6, 0x0 }, // 8320 |
14312 | | { PseudoVSOXSEG4EI16_V_M1_MF2, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8321 |
14313 | | { PseudoVSOXSEG4EI16_V_M1_MF2_MASK, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8322 |
14314 | | { PseudoVSOXSEG4EI16_V_MF2_MF2, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8323 |
14315 | | { PseudoVSOXSEG4EI16_V_MF2_MF2_MASK, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8324 |
14316 | | { PseudoVSOXSEG4EI16_V_MF4_MF2, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8325 |
14317 | | { PseudoVSOXSEG4EI16_V_MF4_MF2_MASK, VSOXSEG4EI16_V, 0x7, 0x0 }, // 8326 |
14318 | | { PseudoVSOXSEG4EI32_V_M1_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8327 |
14319 | | { PseudoVSOXSEG4EI32_V_M1_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8328 |
14320 | | { PseudoVSOXSEG4EI32_V_M2_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8329 |
14321 | | { PseudoVSOXSEG4EI32_V_M2_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8330 |
14322 | | { PseudoVSOXSEG4EI32_V_M4_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8331 |
14323 | | { PseudoVSOXSEG4EI32_V_M4_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8332 |
14324 | | { PseudoVSOXSEG4EI32_V_MF2_M1, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8333 |
14325 | | { PseudoVSOXSEG4EI32_V_MF2_M1_MASK, VSOXSEG4EI32_V, 0x0, 0x0 }, // 8334 |
14326 | | { PseudoVSOXSEG4EI32_V_M1_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8335 |
14327 | | { PseudoVSOXSEG4EI32_V_M1_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8336 |
14328 | | { PseudoVSOXSEG4EI32_V_M2_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8337 |
14329 | | { PseudoVSOXSEG4EI32_V_M2_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8338 |
14330 | | { PseudoVSOXSEG4EI32_V_M4_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8339 |
14331 | | { PseudoVSOXSEG4EI32_V_M4_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8340 |
14332 | | { PseudoVSOXSEG4EI32_V_M8_M2, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8341 |
14333 | | { PseudoVSOXSEG4EI32_V_M8_M2_MASK, VSOXSEG4EI32_V, 0x1, 0x0 }, // 8342 |
14334 | | { PseudoVSOXSEG4EI32_V_MF2_MF8, VSOXSEG4EI32_V, 0x5, 0x0 }, // 8343 |
14335 | | { PseudoVSOXSEG4EI32_V_MF2_MF8_MASK, VSOXSEG4EI32_V, 0x5, 0x0 }, // 8344 |
14336 | | { PseudoVSOXSEG4EI32_V_M1_MF4, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8345 |
14337 | | { PseudoVSOXSEG4EI32_V_M1_MF4_MASK, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8346 |
14338 | | { PseudoVSOXSEG4EI32_V_MF2_MF4, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8347 |
14339 | | { PseudoVSOXSEG4EI32_V_MF2_MF4_MASK, VSOXSEG4EI32_V, 0x6, 0x0 }, // 8348 |
14340 | | { PseudoVSOXSEG4EI32_V_M1_MF2, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8349 |
14341 | | { PseudoVSOXSEG4EI32_V_M1_MF2_MASK, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8350 |
14342 | | { PseudoVSOXSEG4EI32_V_M2_MF2, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8351 |
14343 | | { PseudoVSOXSEG4EI32_V_M2_MF2_MASK, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8352 |
14344 | | { PseudoVSOXSEG4EI32_V_MF2_MF2, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8353 |
14345 | | { PseudoVSOXSEG4EI32_V_MF2_MF2_MASK, VSOXSEG4EI32_V, 0x7, 0x0 }, // 8354 |
14346 | | { PseudoVSOXSEG4EI64_V_M1_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8355 |
14347 | | { PseudoVSOXSEG4EI64_V_M1_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8356 |
14348 | | { PseudoVSOXSEG4EI64_V_M2_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8357 |
14349 | | { PseudoVSOXSEG4EI64_V_M2_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8358 |
14350 | | { PseudoVSOXSEG4EI64_V_M4_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8359 |
14351 | | { PseudoVSOXSEG4EI64_V_M4_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8360 |
14352 | | { PseudoVSOXSEG4EI64_V_M8_M1, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8361 |
14353 | | { PseudoVSOXSEG4EI64_V_M8_M1_MASK, VSOXSEG4EI64_V, 0x0, 0x0 }, // 8362 |
14354 | | { PseudoVSOXSEG4EI64_V_M2_M2, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8363 |
14355 | | { PseudoVSOXSEG4EI64_V_M2_M2_MASK, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8364 |
14356 | | { PseudoVSOXSEG4EI64_V_M4_M2, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8365 |
14357 | | { PseudoVSOXSEG4EI64_V_M4_M2_MASK, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8366 |
14358 | | { PseudoVSOXSEG4EI64_V_M8_M2, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8367 |
14359 | | { PseudoVSOXSEG4EI64_V_M8_M2_MASK, VSOXSEG4EI64_V, 0x1, 0x0 }, // 8368 |
14360 | | { PseudoVSOXSEG4EI64_V_M1_MF8, VSOXSEG4EI64_V, 0x5, 0x0 }, // 8369 |
14361 | | { PseudoVSOXSEG4EI64_V_M1_MF8_MASK, VSOXSEG4EI64_V, 0x5, 0x0 }, // 8370 |
14362 | | { PseudoVSOXSEG4EI64_V_M1_MF4, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8371 |
14363 | | { PseudoVSOXSEG4EI64_V_M1_MF4_MASK, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8372 |
14364 | | { PseudoVSOXSEG4EI64_V_M2_MF4, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8373 |
14365 | | { PseudoVSOXSEG4EI64_V_M2_MF4_MASK, VSOXSEG4EI64_V, 0x6, 0x0 }, // 8374 |
14366 | | { PseudoVSOXSEG4EI64_V_M1_MF2, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8375 |
14367 | | { PseudoVSOXSEG4EI64_V_M1_MF2_MASK, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8376 |
14368 | | { PseudoVSOXSEG4EI64_V_M2_MF2, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8377 |
14369 | | { PseudoVSOXSEG4EI64_V_M2_MF2_MASK, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8378 |
14370 | | { PseudoVSOXSEG4EI64_V_M4_MF2, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8379 |
14371 | | { PseudoVSOXSEG4EI64_V_M4_MF2_MASK, VSOXSEG4EI64_V, 0x7, 0x0 }, // 8380 |
14372 | | { PseudoVSOXSEG4EI8_V_M1_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8381 |
14373 | | { PseudoVSOXSEG4EI8_V_M1_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8382 |
14374 | | { PseudoVSOXSEG4EI8_V_MF2_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8383 |
14375 | | { PseudoVSOXSEG4EI8_V_MF2_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8384 |
14376 | | { PseudoVSOXSEG4EI8_V_MF4_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8385 |
14377 | | { PseudoVSOXSEG4EI8_V_MF4_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8386 |
14378 | | { PseudoVSOXSEG4EI8_V_MF8_M1, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8387 |
14379 | | { PseudoVSOXSEG4EI8_V_MF8_M1_MASK, VSOXSEG4EI8_V, 0x0, 0x0 }, // 8388 |
14380 | | { PseudoVSOXSEG4EI8_V_M1_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8389 |
14381 | | { PseudoVSOXSEG4EI8_V_M1_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8390 |
14382 | | { PseudoVSOXSEG4EI8_V_M2_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8391 |
14383 | | { PseudoVSOXSEG4EI8_V_M2_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8392 |
14384 | | { PseudoVSOXSEG4EI8_V_MF2_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8393 |
14385 | | { PseudoVSOXSEG4EI8_V_MF2_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8394 |
14386 | | { PseudoVSOXSEG4EI8_V_MF4_M2, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8395 |
14387 | | { PseudoVSOXSEG4EI8_V_MF4_M2_MASK, VSOXSEG4EI8_V, 0x1, 0x0 }, // 8396 |
14388 | | { PseudoVSOXSEG4EI8_V_MF8_MF8, VSOXSEG4EI8_V, 0x5, 0x0 }, // 8397 |
14389 | | { PseudoVSOXSEG4EI8_V_MF8_MF8_MASK, VSOXSEG4EI8_V, 0x5, 0x0 }, // 8398 |
14390 | | { PseudoVSOXSEG4EI8_V_MF4_MF4, VSOXSEG4EI8_V, 0x6, 0x0 }, // 8399 |
14391 | | { PseudoVSOXSEG4EI8_V_MF4_MF4_MASK, VSOXSEG4EI8_V, 0x6, 0x0 }, // 8400 |
14392 | | { PseudoVSOXSEG4EI8_V_MF8_MF4, VSOXSEG4EI8_V, 0x6, 0x0 }, // 8401 |
14393 | | { PseudoVSOXSEG4EI8_V_MF8_MF4_MASK, VSOXSEG4EI8_V, 0x6, 0x0 }, // 8402 |
14394 | | { PseudoVSOXSEG4EI8_V_MF2_MF2, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8403 |
14395 | | { PseudoVSOXSEG4EI8_V_MF2_MF2_MASK, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8404 |
14396 | | { PseudoVSOXSEG4EI8_V_MF4_MF2, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8405 |
14397 | | { PseudoVSOXSEG4EI8_V_MF4_MF2_MASK, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8406 |
14398 | | { PseudoVSOXSEG4EI8_V_MF8_MF2, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8407 |
14399 | | { PseudoVSOXSEG4EI8_V_MF8_MF2_MASK, VSOXSEG4EI8_V, 0x7, 0x0 }, // 8408 |
14400 | | { PseudoVSOXSEG5EI16_V_M1_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8409 |
14401 | | { PseudoVSOXSEG5EI16_V_M1_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8410 |
14402 | | { PseudoVSOXSEG5EI16_V_M2_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8411 |
14403 | | { PseudoVSOXSEG5EI16_V_M2_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8412 |
14404 | | { PseudoVSOXSEG5EI16_V_MF2_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8413 |
14405 | | { PseudoVSOXSEG5EI16_V_MF2_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8414 |
14406 | | { PseudoVSOXSEG5EI16_V_MF4_M1, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8415 |
14407 | | { PseudoVSOXSEG5EI16_V_MF4_M1_MASK, VSOXSEG5EI16_V, 0x0, 0x0 }, // 8416 |
14408 | | { PseudoVSOXSEG5EI16_V_MF4_MF8, VSOXSEG5EI16_V, 0x5, 0x0 }, // 8417 |
14409 | | { PseudoVSOXSEG5EI16_V_MF4_MF8_MASK, VSOXSEG5EI16_V, 0x5, 0x0 }, // 8418 |
14410 | | { PseudoVSOXSEG5EI16_V_MF2_MF4, VSOXSEG5EI16_V, 0x6, 0x0 }, // 8419 |
14411 | | { PseudoVSOXSEG5EI16_V_MF2_MF4_MASK, VSOXSEG5EI16_V, 0x6, 0x0 }, // 8420 |
14412 | | { PseudoVSOXSEG5EI16_V_MF4_MF4, VSOXSEG5EI16_V, 0x6, 0x0 }, // 8421 |
14413 | | { PseudoVSOXSEG5EI16_V_MF4_MF4_MASK, VSOXSEG5EI16_V, 0x6, 0x0 }, // 8422 |
14414 | | { PseudoVSOXSEG5EI16_V_M1_MF2, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8423 |
14415 | | { PseudoVSOXSEG5EI16_V_M1_MF2_MASK, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8424 |
14416 | | { PseudoVSOXSEG5EI16_V_MF2_MF2, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8425 |
14417 | | { PseudoVSOXSEG5EI16_V_MF2_MF2_MASK, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8426 |
14418 | | { PseudoVSOXSEG5EI16_V_MF4_MF2, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8427 |
14419 | | { PseudoVSOXSEG5EI16_V_MF4_MF2_MASK, VSOXSEG5EI16_V, 0x7, 0x0 }, // 8428 |
14420 | | { PseudoVSOXSEG5EI32_V_M1_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8429 |
14421 | | { PseudoVSOXSEG5EI32_V_M1_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8430 |
14422 | | { PseudoVSOXSEG5EI32_V_M2_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8431 |
14423 | | { PseudoVSOXSEG5EI32_V_M2_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8432 |
14424 | | { PseudoVSOXSEG5EI32_V_M4_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8433 |
14425 | | { PseudoVSOXSEG5EI32_V_M4_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8434 |
14426 | | { PseudoVSOXSEG5EI32_V_MF2_M1, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8435 |
14427 | | { PseudoVSOXSEG5EI32_V_MF2_M1_MASK, VSOXSEG5EI32_V, 0x0, 0x0 }, // 8436 |
14428 | | { PseudoVSOXSEG5EI32_V_MF2_MF8, VSOXSEG5EI32_V, 0x5, 0x0 }, // 8437 |
14429 | | { PseudoVSOXSEG5EI32_V_MF2_MF8_MASK, VSOXSEG5EI32_V, 0x5, 0x0 }, // 8438 |
14430 | | { PseudoVSOXSEG5EI32_V_M1_MF4, VSOXSEG5EI32_V, 0x6, 0x0 }, // 8439 |
14431 | | { PseudoVSOXSEG5EI32_V_M1_MF4_MASK, VSOXSEG5EI32_V, 0x6, 0x0 }, // 8440 |
14432 | | { PseudoVSOXSEG5EI32_V_MF2_MF4, VSOXSEG5EI32_V, 0x6, 0x0 }, // 8441 |
14433 | | { PseudoVSOXSEG5EI32_V_MF2_MF4_MASK, VSOXSEG5EI32_V, 0x6, 0x0 }, // 8442 |
14434 | | { PseudoVSOXSEG5EI32_V_M1_MF2, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8443 |
14435 | | { PseudoVSOXSEG5EI32_V_M1_MF2_MASK, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8444 |
14436 | | { PseudoVSOXSEG5EI32_V_M2_MF2, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8445 |
14437 | | { PseudoVSOXSEG5EI32_V_M2_MF2_MASK, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8446 |
14438 | | { PseudoVSOXSEG5EI32_V_MF2_MF2, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8447 |
14439 | | { PseudoVSOXSEG5EI32_V_MF2_MF2_MASK, VSOXSEG5EI32_V, 0x7, 0x0 }, // 8448 |
14440 | | { PseudoVSOXSEG5EI64_V_M1_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8449 |
14441 | | { PseudoVSOXSEG5EI64_V_M1_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8450 |
14442 | | { PseudoVSOXSEG5EI64_V_M2_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8451 |
14443 | | { PseudoVSOXSEG5EI64_V_M2_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8452 |
14444 | | { PseudoVSOXSEG5EI64_V_M4_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8453 |
14445 | | { PseudoVSOXSEG5EI64_V_M4_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8454 |
14446 | | { PseudoVSOXSEG5EI64_V_M8_M1, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8455 |
14447 | | { PseudoVSOXSEG5EI64_V_M8_M1_MASK, VSOXSEG5EI64_V, 0x0, 0x0 }, // 8456 |
14448 | | { PseudoVSOXSEG5EI64_V_M1_MF8, VSOXSEG5EI64_V, 0x5, 0x0 }, // 8457 |
14449 | | { PseudoVSOXSEG5EI64_V_M1_MF8_MASK, VSOXSEG5EI64_V, 0x5, 0x0 }, // 8458 |
14450 | | { PseudoVSOXSEG5EI64_V_M1_MF4, VSOXSEG5EI64_V, 0x6, 0x0 }, // 8459 |
14451 | | { PseudoVSOXSEG5EI64_V_M1_MF4_MASK, VSOXSEG5EI64_V, 0x6, 0x0 }, // 8460 |
14452 | | { PseudoVSOXSEG5EI64_V_M2_MF4, VSOXSEG5EI64_V, 0x6, 0x0 }, // 8461 |
14453 | | { PseudoVSOXSEG5EI64_V_M2_MF4_MASK, VSOXSEG5EI64_V, 0x6, 0x0 }, // 8462 |
14454 | | { PseudoVSOXSEG5EI64_V_M1_MF2, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8463 |
14455 | | { PseudoVSOXSEG5EI64_V_M1_MF2_MASK, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8464 |
14456 | | { PseudoVSOXSEG5EI64_V_M2_MF2, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8465 |
14457 | | { PseudoVSOXSEG5EI64_V_M2_MF2_MASK, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8466 |
14458 | | { PseudoVSOXSEG5EI64_V_M4_MF2, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8467 |
14459 | | { PseudoVSOXSEG5EI64_V_M4_MF2_MASK, VSOXSEG5EI64_V, 0x7, 0x0 }, // 8468 |
14460 | | { PseudoVSOXSEG5EI8_V_M1_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8469 |
14461 | | { PseudoVSOXSEG5EI8_V_M1_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8470 |
14462 | | { PseudoVSOXSEG5EI8_V_MF2_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8471 |
14463 | | { PseudoVSOXSEG5EI8_V_MF2_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8472 |
14464 | | { PseudoVSOXSEG5EI8_V_MF4_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8473 |
14465 | | { PseudoVSOXSEG5EI8_V_MF4_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8474 |
14466 | | { PseudoVSOXSEG5EI8_V_MF8_M1, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8475 |
14467 | | { PseudoVSOXSEG5EI8_V_MF8_M1_MASK, VSOXSEG5EI8_V, 0x0, 0x0 }, // 8476 |
14468 | | { PseudoVSOXSEG5EI8_V_MF8_MF8, VSOXSEG5EI8_V, 0x5, 0x0 }, // 8477 |
14469 | | { PseudoVSOXSEG5EI8_V_MF8_MF8_MASK, VSOXSEG5EI8_V, 0x5, 0x0 }, // 8478 |
14470 | | { PseudoVSOXSEG5EI8_V_MF4_MF4, VSOXSEG5EI8_V, 0x6, 0x0 }, // 8479 |
14471 | | { PseudoVSOXSEG5EI8_V_MF4_MF4_MASK, VSOXSEG5EI8_V, 0x6, 0x0 }, // 8480 |
14472 | | { PseudoVSOXSEG5EI8_V_MF8_MF4, VSOXSEG5EI8_V, 0x6, 0x0 }, // 8481 |
14473 | | { PseudoVSOXSEG5EI8_V_MF8_MF4_MASK, VSOXSEG5EI8_V, 0x6, 0x0 }, // 8482 |
14474 | | { PseudoVSOXSEG5EI8_V_MF2_MF2, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8483 |
14475 | | { PseudoVSOXSEG5EI8_V_MF2_MF2_MASK, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8484 |
14476 | | { PseudoVSOXSEG5EI8_V_MF4_MF2, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8485 |
14477 | | { PseudoVSOXSEG5EI8_V_MF4_MF2_MASK, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8486 |
14478 | | { PseudoVSOXSEG5EI8_V_MF8_MF2, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8487 |
14479 | | { PseudoVSOXSEG5EI8_V_MF8_MF2_MASK, VSOXSEG5EI8_V, 0x7, 0x0 }, // 8488 |
14480 | | { PseudoVSOXSEG6EI16_V_M1_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8489 |
14481 | | { PseudoVSOXSEG6EI16_V_M1_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8490 |
14482 | | { PseudoVSOXSEG6EI16_V_M2_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8491 |
14483 | | { PseudoVSOXSEG6EI16_V_M2_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8492 |
14484 | | { PseudoVSOXSEG6EI16_V_MF2_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8493 |
14485 | | { PseudoVSOXSEG6EI16_V_MF2_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8494 |
14486 | | { PseudoVSOXSEG6EI16_V_MF4_M1, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8495 |
14487 | | { PseudoVSOXSEG6EI16_V_MF4_M1_MASK, VSOXSEG6EI16_V, 0x0, 0x0 }, // 8496 |
14488 | | { PseudoVSOXSEG6EI16_V_MF4_MF8, VSOXSEG6EI16_V, 0x5, 0x0 }, // 8497 |
14489 | | { PseudoVSOXSEG6EI16_V_MF4_MF8_MASK, VSOXSEG6EI16_V, 0x5, 0x0 }, // 8498 |
14490 | | { PseudoVSOXSEG6EI16_V_MF2_MF4, VSOXSEG6EI16_V, 0x6, 0x0 }, // 8499 |
14491 | | { PseudoVSOXSEG6EI16_V_MF2_MF4_MASK, VSOXSEG6EI16_V, 0x6, 0x0 }, // 8500 |
14492 | | { PseudoVSOXSEG6EI16_V_MF4_MF4, VSOXSEG6EI16_V, 0x6, 0x0 }, // 8501 |
14493 | | { PseudoVSOXSEG6EI16_V_MF4_MF4_MASK, VSOXSEG6EI16_V, 0x6, 0x0 }, // 8502 |
14494 | | { PseudoVSOXSEG6EI16_V_M1_MF2, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8503 |
14495 | | { PseudoVSOXSEG6EI16_V_M1_MF2_MASK, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8504 |
14496 | | { PseudoVSOXSEG6EI16_V_MF2_MF2, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8505 |
14497 | | { PseudoVSOXSEG6EI16_V_MF2_MF2_MASK, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8506 |
14498 | | { PseudoVSOXSEG6EI16_V_MF4_MF2, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8507 |
14499 | | { PseudoVSOXSEG6EI16_V_MF4_MF2_MASK, VSOXSEG6EI16_V, 0x7, 0x0 }, // 8508 |
14500 | | { PseudoVSOXSEG6EI32_V_M1_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8509 |
14501 | | { PseudoVSOXSEG6EI32_V_M1_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8510 |
14502 | | { PseudoVSOXSEG6EI32_V_M2_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8511 |
14503 | | { PseudoVSOXSEG6EI32_V_M2_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8512 |
14504 | | { PseudoVSOXSEG6EI32_V_M4_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8513 |
14505 | | { PseudoVSOXSEG6EI32_V_M4_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8514 |
14506 | | { PseudoVSOXSEG6EI32_V_MF2_M1, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8515 |
14507 | | { PseudoVSOXSEG6EI32_V_MF2_M1_MASK, VSOXSEG6EI32_V, 0x0, 0x0 }, // 8516 |
14508 | | { PseudoVSOXSEG6EI32_V_MF2_MF8, VSOXSEG6EI32_V, 0x5, 0x0 }, // 8517 |
14509 | | { PseudoVSOXSEG6EI32_V_MF2_MF8_MASK, VSOXSEG6EI32_V, 0x5, 0x0 }, // 8518 |
14510 | | { PseudoVSOXSEG6EI32_V_M1_MF4, VSOXSEG6EI32_V, 0x6, 0x0 }, // 8519 |
14511 | | { PseudoVSOXSEG6EI32_V_M1_MF4_MASK, VSOXSEG6EI32_V, 0x6, 0x0 }, // 8520 |
14512 | | { PseudoVSOXSEG6EI32_V_MF2_MF4, VSOXSEG6EI32_V, 0x6, 0x0 }, // 8521 |
14513 | | { PseudoVSOXSEG6EI32_V_MF2_MF4_MASK, VSOXSEG6EI32_V, 0x6, 0x0 }, // 8522 |
14514 | | { PseudoVSOXSEG6EI32_V_M1_MF2, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8523 |
14515 | | { PseudoVSOXSEG6EI32_V_M1_MF2_MASK, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8524 |
14516 | | { PseudoVSOXSEG6EI32_V_M2_MF2, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8525 |
14517 | | { PseudoVSOXSEG6EI32_V_M2_MF2_MASK, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8526 |
14518 | | { PseudoVSOXSEG6EI32_V_MF2_MF2, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8527 |
14519 | | { PseudoVSOXSEG6EI32_V_MF2_MF2_MASK, VSOXSEG6EI32_V, 0x7, 0x0 }, // 8528 |
14520 | | { PseudoVSOXSEG6EI64_V_M1_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8529 |
14521 | | { PseudoVSOXSEG6EI64_V_M1_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8530 |
14522 | | { PseudoVSOXSEG6EI64_V_M2_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8531 |
14523 | | { PseudoVSOXSEG6EI64_V_M2_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8532 |
14524 | | { PseudoVSOXSEG6EI64_V_M4_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8533 |
14525 | | { PseudoVSOXSEG6EI64_V_M4_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8534 |
14526 | | { PseudoVSOXSEG6EI64_V_M8_M1, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8535 |
14527 | | { PseudoVSOXSEG6EI64_V_M8_M1_MASK, VSOXSEG6EI64_V, 0x0, 0x0 }, // 8536 |
14528 | | { PseudoVSOXSEG6EI64_V_M1_MF8, VSOXSEG6EI64_V, 0x5, 0x0 }, // 8537 |
14529 | | { PseudoVSOXSEG6EI64_V_M1_MF8_MASK, VSOXSEG6EI64_V, 0x5, 0x0 }, // 8538 |
14530 | | { PseudoVSOXSEG6EI64_V_M1_MF4, VSOXSEG6EI64_V, 0x6, 0x0 }, // 8539 |
14531 | | { PseudoVSOXSEG6EI64_V_M1_MF4_MASK, VSOXSEG6EI64_V, 0x6, 0x0 }, // 8540 |
14532 | | { PseudoVSOXSEG6EI64_V_M2_MF4, VSOXSEG6EI64_V, 0x6, 0x0 }, // 8541 |
14533 | | { PseudoVSOXSEG6EI64_V_M2_MF4_MASK, VSOXSEG6EI64_V, 0x6, 0x0 }, // 8542 |
14534 | | { PseudoVSOXSEG6EI64_V_M1_MF2, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8543 |
14535 | | { PseudoVSOXSEG6EI64_V_M1_MF2_MASK, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8544 |
14536 | | { PseudoVSOXSEG6EI64_V_M2_MF2, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8545 |
14537 | | { PseudoVSOXSEG6EI64_V_M2_MF2_MASK, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8546 |
14538 | | { PseudoVSOXSEG6EI64_V_M4_MF2, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8547 |
14539 | | { PseudoVSOXSEG6EI64_V_M4_MF2_MASK, VSOXSEG6EI64_V, 0x7, 0x0 }, // 8548 |
14540 | | { PseudoVSOXSEG6EI8_V_M1_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8549 |
14541 | | { PseudoVSOXSEG6EI8_V_M1_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8550 |
14542 | | { PseudoVSOXSEG6EI8_V_MF2_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8551 |
14543 | | { PseudoVSOXSEG6EI8_V_MF2_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8552 |
14544 | | { PseudoVSOXSEG6EI8_V_MF4_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8553 |
14545 | | { PseudoVSOXSEG6EI8_V_MF4_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8554 |
14546 | | { PseudoVSOXSEG6EI8_V_MF8_M1, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8555 |
14547 | | { PseudoVSOXSEG6EI8_V_MF8_M1_MASK, VSOXSEG6EI8_V, 0x0, 0x0 }, // 8556 |
14548 | | { PseudoVSOXSEG6EI8_V_MF8_MF8, VSOXSEG6EI8_V, 0x5, 0x0 }, // 8557 |
14549 | | { PseudoVSOXSEG6EI8_V_MF8_MF8_MASK, VSOXSEG6EI8_V, 0x5, 0x0 }, // 8558 |
14550 | | { PseudoVSOXSEG6EI8_V_MF4_MF4, VSOXSEG6EI8_V, 0x6, 0x0 }, // 8559 |
14551 | | { PseudoVSOXSEG6EI8_V_MF4_MF4_MASK, VSOXSEG6EI8_V, 0x6, 0x0 }, // 8560 |
14552 | | { PseudoVSOXSEG6EI8_V_MF8_MF4, VSOXSEG6EI8_V, 0x6, 0x0 }, // 8561 |
14553 | | { PseudoVSOXSEG6EI8_V_MF8_MF4_MASK, VSOXSEG6EI8_V, 0x6, 0x0 }, // 8562 |
14554 | | { PseudoVSOXSEG6EI8_V_MF2_MF2, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8563 |
14555 | | { PseudoVSOXSEG6EI8_V_MF2_MF2_MASK, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8564 |
14556 | | { PseudoVSOXSEG6EI8_V_MF4_MF2, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8565 |
14557 | | { PseudoVSOXSEG6EI8_V_MF4_MF2_MASK, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8566 |
14558 | | { PseudoVSOXSEG6EI8_V_MF8_MF2, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8567 |
14559 | | { PseudoVSOXSEG6EI8_V_MF8_MF2_MASK, VSOXSEG6EI8_V, 0x7, 0x0 }, // 8568 |
14560 | | { PseudoVSOXSEG7EI16_V_M1_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8569 |
14561 | | { PseudoVSOXSEG7EI16_V_M1_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8570 |
14562 | | { PseudoVSOXSEG7EI16_V_M2_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8571 |
14563 | | { PseudoVSOXSEG7EI16_V_M2_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8572 |
14564 | | { PseudoVSOXSEG7EI16_V_MF2_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8573 |
14565 | | { PseudoVSOXSEG7EI16_V_MF2_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8574 |
14566 | | { PseudoVSOXSEG7EI16_V_MF4_M1, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8575 |
14567 | | { PseudoVSOXSEG7EI16_V_MF4_M1_MASK, VSOXSEG7EI16_V, 0x0, 0x0 }, // 8576 |
14568 | | { PseudoVSOXSEG7EI16_V_MF4_MF8, VSOXSEG7EI16_V, 0x5, 0x0 }, // 8577 |
14569 | | { PseudoVSOXSEG7EI16_V_MF4_MF8_MASK, VSOXSEG7EI16_V, 0x5, 0x0 }, // 8578 |
14570 | | { PseudoVSOXSEG7EI16_V_MF2_MF4, VSOXSEG7EI16_V, 0x6, 0x0 }, // 8579 |
14571 | | { PseudoVSOXSEG7EI16_V_MF2_MF4_MASK, VSOXSEG7EI16_V, 0x6, 0x0 }, // 8580 |
14572 | | { PseudoVSOXSEG7EI16_V_MF4_MF4, VSOXSEG7EI16_V, 0x6, 0x0 }, // 8581 |
14573 | | { PseudoVSOXSEG7EI16_V_MF4_MF4_MASK, VSOXSEG7EI16_V, 0x6, 0x0 }, // 8582 |
14574 | | { PseudoVSOXSEG7EI16_V_M1_MF2, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8583 |
14575 | | { PseudoVSOXSEG7EI16_V_M1_MF2_MASK, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8584 |
14576 | | { PseudoVSOXSEG7EI16_V_MF2_MF2, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8585 |
14577 | | { PseudoVSOXSEG7EI16_V_MF2_MF2_MASK, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8586 |
14578 | | { PseudoVSOXSEG7EI16_V_MF4_MF2, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8587 |
14579 | | { PseudoVSOXSEG7EI16_V_MF4_MF2_MASK, VSOXSEG7EI16_V, 0x7, 0x0 }, // 8588 |
14580 | | { PseudoVSOXSEG7EI32_V_M1_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8589 |
14581 | | { PseudoVSOXSEG7EI32_V_M1_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8590 |
14582 | | { PseudoVSOXSEG7EI32_V_M2_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8591 |
14583 | | { PseudoVSOXSEG7EI32_V_M2_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8592 |
14584 | | { PseudoVSOXSEG7EI32_V_M4_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8593 |
14585 | | { PseudoVSOXSEG7EI32_V_M4_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8594 |
14586 | | { PseudoVSOXSEG7EI32_V_MF2_M1, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8595 |
14587 | | { PseudoVSOXSEG7EI32_V_MF2_M1_MASK, VSOXSEG7EI32_V, 0x0, 0x0 }, // 8596 |
14588 | | { PseudoVSOXSEG7EI32_V_MF2_MF8, VSOXSEG7EI32_V, 0x5, 0x0 }, // 8597 |
14589 | | { PseudoVSOXSEG7EI32_V_MF2_MF8_MASK, VSOXSEG7EI32_V, 0x5, 0x0 }, // 8598 |
14590 | | { PseudoVSOXSEG7EI32_V_M1_MF4, VSOXSEG7EI32_V, 0x6, 0x0 }, // 8599 |
14591 | | { PseudoVSOXSEG7EI32_V_M1_MF4_MASK, VSOXSEG7EI32_V, 0x6, 0x0 }, // 8600 |
14592 | | { PseudoVSOXSEG7EI32_V_MF2_MF4, VSOXSEG7EI32_V, 0x6, 0x0 }, // 8601 |
14593 | | { PseudoVSOXSEG7EI32_V_MF2_MF4_MASK, VSOXSEG7EI32_V, 0x6, 0x0 }, // 8602 |
14594 | | { PseudoVSOXSEG7EI32_V_M1_MF2, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8603 |
14595 | | { PseudoVSOXSEG7EI32_V_M1_MF2_MASK, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8604 |
14596 | | { PseudoVSOXSEG7EI32_V_M2_MF2, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8605 |
14597 | | { PseudoVSOXSEG7EI32_V_M2_MF2_MASK, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8606 |
14598 | | { PseudoVSOXSEG7EI32_V_MF2_MF2, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8607 |
14599 | | { PseudoVSOXSEG7EI32_V_MF2_MF2_MASK, VSOXSEG7EI32_V, 0x7, 0x0 }, // 8608 |
14600 | | { PseudoVSOXSEG7EI64_V_M1_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8609 |
14601 | | { PseudoVSOXSEG7EI64_V_M1_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8610 |
14602 | | { PseudoVSOXSEG7EI64_V_M2_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8611 |
14603 | | { PseudoVSOXSEG7EI64_V_M2_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8612 |
14604 | | { PseudoVSOXSEG7EI64_V_M4_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8613 |
14605 | | { PseudoVSOXSEG7EI64_V_M4_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8614 |
14606 | | { PseudoVSOXSEG7EI64_V_M8_M1, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8615 |
14607 | | { PseudoVSOXSEG7EI64_V_M8_M1_MASK, VSOXSEG7EI64_V, 0x0, 0x0 }, // 8616 |
14608 | | { PseudoVSOXSEG7EI64_V_M1_MF8, VSOXSEG7EI64_V, 0x5, 0x0 }, // 8617 |
14609 | | { PseudoVSOXSEG7EI64_V_M1_MF8_MASK, VSOXSEG7EI64_V, 0x5, 0x0 }, // 8618 |
14610 | | { PseudoVSOXSEG7EI64_V_M1_MF4, VSOXSEG7EI64_V, 0x6, 0x0 }, // 8619 |
14611 | | { PseudoVSOXSEG7EI64_V_M1_MF4_MASK, VSOXSEG7EI64_V, 0x6, 0x0 }, // 8620 |
14612 | | { PseudoVSOXSEG7EI64_V_M2_MF4, VSOXSEG7EI64_V, 0x6, 0x0 }, // 8621 |
14613 | | { PseudoVSOXSEG7EI64_V_M2_MF4_MASK, VSOXSEG7EI64_V, 0x6, 0x0 }, // 8622 |
14614 | | { PseudoVSOXSEG7EI64_V_M1_MF2, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8623 |
14615 | | { PseudoVSOXSEG7EI64_V_M1_MF2_MASK, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8624 |
14616 | | { PseudoVSOXSEG7EI64_V_M2_MF2, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8625 |
14617 | | { PseudoVSOXSEG7EI64_V_M2_MF2_MASK, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8626 |
14618 | | { PseudoVSOXSEG7EI64_V_M4_MF2, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8627 |
14619 | | { PseudoVSOXSEG7EI64_V_M4_MF2_MASK, VSOXSEG7EI64_V, 0x7, 0x0 }, // 8628 |
14620 | | { PseudoVSOXSEG7EI8_V_M1_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8629 |
14621 | | { PseudoVSOXSEG7EI8_V_M1_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8630 |
14622 | | { PseudoVSOXSEG7EI8_V_MF2_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8631 |
14623 | | { PseudoVSOXSEG7EI8_V_MF2_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8632 |
14624 | | { PseudoVSOXSEG7EI8_V_MF4_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8633 |
14625 | | { PseudoVSOXSEG7EI8_V_MF4_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8634 |
14626 | | { PseudoVSOXSEG7EI8_V_MF8_M1, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8635 |
14627 | | { PseudoVSOXSEG7EI8_V_MF8_M1_MASK, VSOXSEG7EI8_V, 0x0, 0x0 }, // 8636 |
14628 | | { PseudoVSOXSEG7EI8_V_MF8_MF8, VSOXSEG7EI8_V, 0x5, 0x0 }, // 8637 |
14629 | | { PseudoVSOXSEG7EI8_V_MF8_MF8_MASK, VSOXSEG7EI8_V, 0x5, 0x0 }, // 8638 |
14630 | | { PseudoVSOXSEG7EI8_V_MF4_MF4, VSOXSEG7EI8_V, 0x6, 0x0 }, // 8639 |
14631 | | { PseudoVSOXSEG7EI8_V_MF4_MF4_MASK, VSOXSEG7EI8_V, 0x6, 0x0 }, // 8640 |
14632 | | { PseudoVSOXSEG7EI8_V_MF8_MF4, VSOXSEG7EI8_V, 0x6, 0x0 }, // 8641 |
14633 | | { PseudoVSOXSEG7EI8_V_MF8_MF4_MASK, VSOXSEG7EI8_V, 0x6, 0x0 }, // 8642 |
14634 | | { PseudoVSOXSEG7EI8_V_MF2_MF2, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8643 |
14635 | | { PseudoVSOXSEG7EI8_V_MF2_MF2_MASK, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8644 |
14636 | | { PseudoVSOXSEG7EI8_V_MF4_MF2, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8645 |
14637 | | { PseudoVSOXSEG7EI8_V_MF4_MF2_MASK, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8646 |
14638 | | { PseudoVSOXSEG7EI8_V_MF8_MF2, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8647 |
14639 | | { PseudoVSOXSEG7EI8_V_MF8_MF2_MASK, VSOXSEG7EI8_V, 0x7, 0x0 }, // 8648 |
14640 | | { PseudoVSOXSEG8EI16_V_M1_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8649 |
14641 | | { PseudoVSOXSEG8EI16_V_M1_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8650 |
14642 | | { PseudoVSOXSEG8EI16_V_M2_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8651 |
14643 | | { PseudoVSOXSEG8EI16_V_M2_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8652 |
14644 | | { PseudoVSOXSEG8EI16_V_MF2_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8653 |
14645 | | { PseudoVSOXSEG8EI16_V_MF2_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8654 |
14646 | | { PseudoVSOXSEG8EI16_V_MF4_M1, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8655 |
14647 | | { PseudoVSOXSEG8EI16_V_MF4_M1_MASK, VSOXSEG8EI16_V, 0x0, 0x0 }, // 8656 |
14648 | | { PseudoVSOXSEG8EI16_V_MF4_MF8, VSOXSEG8EI16_V, 0x5, 0x0 }, // 8657 |
14649 | | { PseudoVSOXSEG8EI16_V_MF4_MF8_MASK, VSOXSEG8EI16_V, 0x5, 0x0 }, // 8658 |
14650 | | { PseudoVSOXSEG8EI16_V_MF2_MF4, VSOXSEG8EI16_V, 0x6, 0x0 }, // 8659 |
14651 | | { PseudoVSOXSEG8EI16_V_MF2_MF4_MASK, VSOXSEG8EI16_V, 0x6, 0x0 }, // 8660 |
14652 | | { PseudoVSOXSEG8EI16_V_MF4_MF4, VSOXSEG8EI16_V, 0x6, 0x0 }, // 8661 |
14653 | | { PseudoVSOXSEG8EI16_V_MF4_MF4_MASK, VSOXSEG8EI16_V, 0x6, 0x0 }, // 8662 |
14654 | | { PseudoVSOXSEG8EI16_V_M1_MF2, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8663 |
14655 | | { PseudoVSOXSEG8EI16_V_M1_MF2_MASK, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8664 |
14656 | | { PseudoVSOXSEG8EI16_V_MF2_MF2, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8665 |
14657 | | { PseudoVSOXSEG8EI16_V_MF2_MF2_MASK, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8666 |
14658 | | { PseudoVSOXSEG8EI16_V_MF4_MF2, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8667 |
14659 | | { PseudoVSOXSEG8EI16_V_MF4_MF2_MASK, VSOXSEG8EI16_V, 0x7, 0x0 }, // 8668 |
14660 | | { PseudoVSOXSEG8EI32_V_M1_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8669 |
14661 | | { PseudoVSOXSEG8EI32_V_M1_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8670 |
14662 | | { PseudoVSOXSEG8EI32_V_M2_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8671 |
14663 | | { PseudoVSOXSEG8EI32_V_M2_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8672 |
14664 | | { PseudoVSOXSEG8EI32_V_M4_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8673 |
14665 | | { PseudoVSOXSEG8EI32_V_M4_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8674 |
14666 | | { PseudoVSOXSEG8EI32_V_MF2_M1, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8675 |
14667 | | { PseudoVSOXSEG8EI32_V_MF2_M1_MASK, VSOXSEG8EI32_V, 0x0, 0x0 }, // 8676 |
14668 | | { PseudoVSOXSEG8EI32_V_MF2_MF8, VSOXSEG8EI32_V, 0x5, 0x0 }, // 8677 |
14669 | | { PseudoVSOXSEG8EI32_V_MF2_MF8_MASK, VSOXSEG8EI32_V, 0x5, 0x0 }, // 8678 |
14670 | | { PseudoVSOXSEG8EI32_V_M1_MF4, VSOXSEG8EI32_V, 0x6, 0x0 }, // 8679 |
14671 | | { PseudoVSOXSEG8EI32_V_M1_MF4_MASK, VSOXSEG8EI32_V, 0x6, 0x0 }, // 8680 |
14672 | | { PseudoVSOXSEG8EI32_V_MF2_MF4, VSOXSEG8EI32_V, 0x6, 0x0 }, // 8681 |
14673 | | { PseudoVSOXSEG8EI32_V_MF2_MF4_MASK, VSOXSEG8EI32_V, 0x6, 0x0 }, // 8682 |
14674 | | { PseudoVSOXSEG8EI32_V_M1_MF2, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8683 |
14675 | | { PseudoVSOXSEG8EI32_V_M1_MF2_MASK, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8684 |
14676 | | { PseudoVSOXSEG8EI32_V_M2_MF2, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8685 |
14677 | | { PseudoVSOXSEG8EI32_V_M2_MF2_MASK, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8686 |
14678 | | { PseudoVSOXSEG8EI32_V_MF2_MF2, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8687 |
14679 | | { PseudoVSOXSEG8EI32_V_MF2_MF2_MASK, VSOXSEG8EI32_V, 0x7, 0x0 }, // 8688 |
14680 | | { PseudoVSOXSEG8EI64_V_M1_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8689 |
14681 | | { PseudoVSOXSEG8EI64_V_M1_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8690 |
14682 | | { PseudoVSOXSEG8EI64_V_M2_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8691 |
14683 | | { PseudoVSOXSEG8EI64_V_M2_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8692 |
14684 | | { PseudoVSOXSEG8EI64_V_M4_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8693 |
14685 | | { PseudoVSOXSEG8EI64_V_M4_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8694 |
14686 | | { PseudoVSOXSEG8EI64_V_M8_M1, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8695 |
14687 | | { PseudoVSOXSEG8EI64_V_M8_M1_MASK, VSOXSEG8EI64_V, 0x0, 0x0 }, // 8696 |
14688 | | { PseudoVSOXSEG8EI64_V_M1_MF8, VSOXSEG8EI64_V, 0x5, 0x0 }, // 8697 |
14689 | | { PseudoVSOXSEG8EI64_V_M1_MF8_MASK, VSOXSEG8EI64_V, 0x5, 0x0 }, // 8698 |
14690 | | { PseudoVSOXSEG8EI64_V_M1_MF4, VSOXSEG8EI64_V, 0x6, 0x0 }, // 8699 |
14691 | | { PseudoVSOXSEG8EI64_V_M1_MF4_MASK, VSOXSEG8EI64_V, 0x6, 0x0 }, // 8700 |
14692 | | { PseudoVSOXSEG8EI64_V_M2_MF4, VSOXSEG8EI64_V, 0x6, 0x0 }, // 8701 |
14693 | | { PseudoVSOXSEG8EI64_V_M2_MF4_MASK, VSOXSEG8EI64_V, 0x6, 0x0 }, // 8702 |
14694 | | { PseudoVSOXSEG8EI64_V_M1_MF2, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8703 |
14695 | | { PseudoVSOXSEG8EI64_V_M1_MF2_MASK, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8704 |
14696 | | { PseudoVSOXSEG8EI64_V_M2_MF2, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8705 |
14697 | | { PseudoVSOXSEG8EI64_V_M2_MF2_MASK, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8706 |
14698 | | { PseudoVSOXSEG8EI64_V_M4_MF2, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8707 |
14699 | | { PseudoVSOXSEG8EI64_V_M4_MF2_MASK, VSOXSEG8EI64_V, 0x7, 0x0 }, // 8708 |
14700 | | { PseudoVSOXSEG8EI8_V_M1_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8709 |
14701 | | { PseudoVSOXSEG8EI8_V_M1_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8710 |
14702 | | { PseudoVSOXSEG8EI8_V_MF2_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8711 |
14703 | | { PseudoVSOXSEG8EI8_V_MF2_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8712 |
14704 | | { PseudoVSOXSEG8EI8_V_MF4_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8713 |
14705 | | { PseudoVSOXSEG8EI8_V_MF4_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8714 |
14706 | | { PseudoVSOXSEG8EI8_V_MF8_M1, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8715 |
14707 | | { PseudoVSOXSEG8EI8_V_MF8_M1_MASK, VSOXSEG8EI8_V, 0x0, 0x0 }, // 8716 |
14708 | | { PseudoVSOXSEG8EI8_V_MF8_MF8, VSOXSEG8EI8_V, 0x5, 0x0 }, // 8717 |
14709 | | { PseudoVSOXSEG8EI8_V_MF8_MF8_MASK, VSOXSEG8EI8_V, 0x5, 0x0 }, // 8718 |
14710 | | { PseudoVSOXSEG8EI8_V_MF4_MF4, VSOXSEG8EI8_V, 0x6, 0x0 }, // 8719 |
14711 | | { PseudoVSOXSEG8EI8_V_MF4_MF4_MASK, VSOXSEG8EI8_V, 0x6, 0x0 }, // 8720 |
14712 | | { PseudoVSOXSEG8EI8_V_MF8_MF4, VSOXSEG8EI8_V, 0x6, 0x0 }, // 8721 |
14713 | | { PseudoVSOXSEG8EI8_V_MF8_MF4_MASK, VSOXSEG8EI8_V, 0x6, 0x0 }, // 8722 |
14714 | | { PseudoVSOXSEG8EI8_V_MF2_MF2, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8723 |
14715 | | { PseudoVSOXSEG8EI8_V_MF2_MF2_MASK, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8724 |
14716 | | { PseudoVSOXSEG8EI8_V_MF4_MF2, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8725 |
14717 | | { PseudoVSOXSEG8EI8_V_MF4_MF2_MASK, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8726 |
14718 | | { PseudoVSOXSEG8EI8_V_MF8_MF2, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8727 |
14719 | | { PseudoVSOXSEG8EI8_V_MF8_MF2_MASK, VSOXSEG8EI8_V, 0x7, 0x0 }, // 8728 |
14720 | | { PseudoVSRA_VI_M1, VSRA_VI, 0x0, 0x0 }, // 8729 |
14721 | | { PseudoVSRA_VI_M1_MASK, VSRA_VI, 0x0, 0x0 }, // 8730 |
14722 | | { PseudoVSRA_VI_M2, VSRA_VI, 0x1, 0x0 }, // 8731 |
14723 | | { PseudoVSRA_VI_M2_MASK, VSRA_VI, 0x1, 0x0 }, // 8732 |
14724 | | { PseudoVSRA_VI_M4, VSRA_VI, 0x2, 0x0 }, // 8733 |
14725 | | { PseudoVSRA_VI_M4_MASK, VSRA_VI, 0x2, 0x0 }, // 8734 |
14726 | | { PseudoVSRA_VI_M8, VSRA_VI, 0x3, 0x0 }, // 8735 |
14727 | | { PseudoVSRA_VI_M8_MASK, VSRA_VI, 0x3, 0x0 }, // 8736 |
14728 | | { PseudoVSRA_VI_MF8, VSRA_VI, 0x5, 0x0 }, // 8737 |
14729 | | { PseudoVSRA_VI_MF8_MASK, VSRA_VI, 0x5, 0x0 }, // 8738 |
14730 | | { PseudoVSRA_VI_MF4, VSRA_VI, 0x6, 0x0 }, // 8739 |
14731 | | { PseudoVSRA_VI_MF4_MASK, VSRA_VI, 0x6, 0x0 }, // 8740 |
14732 | | { PseudoVSRA_VI_MF2, VSRA_VI, 0x7, 0x0 }, // 8741 |
14733 | | { PseudoVSRA_VI_MF2_MASK, VSRA_VI, 0x7, 0x0 }, // 8742 |
14734 | | { PseudoVSRA_VV_M1, VSRA_VV, 0x0, 0x0 }, // 8743 |
14735 | | { PseudoVSRA_VV_M1_MASK, VSRA_VV, 0x0, 0x0 }, // 8744 |
14736 | | { PseudoVSRA_VV_M2, VSRA_VV, 0x1, 0x0 }, // 8745 |
14737 | | { PseudoVSRA_VV_M2_MASK, VSRA_VV, 0x1, 0x0 }, // 8746 |
14738 | | { PseudoVSRA_VV_M4, VSRA_VV, 0x2, 0x0 }, // 8747 |
14739 | | { PseudoVSRA_VV_M4_MASK, VSRA_VV, 0x2, 0x0 }, // 8748 |
14740 | | { PseudoVSRA_VV_M8, VSRA_VV, 0x3, 0x0 }, // 8749 |
14741 | | { PseudoVSRA_VV_M8_MASK, VSRA_VV, 0x3, 0x0 }, // 8750 |
14742 | | { PseudoVSRA_VV_MF8, VSRA_VV, 0x5, 0x0 }, // 8751 |
14743 | | { PseudoVSRA_VV_MF8_MASK, VSRA_VV, 0x5, 0x0 }, // 8752 |
14744 | | { PseudoVSRA_VV_MF4, VSRA_VV, 0x6, 0x0 }, // 8753 |
14745 | | { PseudoVSRA_VV_MF4_MASK, VSRA_VV, 0x6, 0x0 }, // 8754 |
14746 | | { PseudoVSRA_VV_MF2, VSRA_VV, 0x7, 0x0 }, // 8755 |
14747 | | { PseudoVSRA_VV_MF2_MASK, VSRA_VV, 0x7, 0x0 }, // 8756 |
14748 | | { PseudoVSRA_VX_M1, VSRA_VX, 0x0, 0x0 }, // 8757 |
14749 | | { PseudoVSRA_VX_M1_MASK, VSRA_VX, 0x0, 0x0 }, // 8758 |
14750 | | { PseudoVSRA_VX_M2, VSRA_VX, 0x1, 0x0 }, // 8759 |
14751 | | { PseudoVSRA_VX_M2_MASK, VSRA_VX, 0x1, 0x0 }, // 8760 |
14752 | | { PseudoVSRA_VX_M4, VSRA_VX, 0x2, 0x0 }, // 8761 |
14753 | | { PseudoVSRA_VX_M4_MASK, VSRA_VX, 0x2, 0x0 }, // 8762 |
14754 | | { PseudoVSRA_VX_M8, VSRA_VX, 0x3, 0x0 }, // 8763 |
14755 | | { PseudoVSRA_VX_M8_MASK, VSRA_VX, 0x3, 0x0 }, // 8764 |
14756 | | { PseudoVSRA_VX_MF8, VSRA_VX, 0x5, 0x0 }, // 8765 |
14757 | | { PseudoVSRA_VX_MF8_MASK, VSRA_VX, 0x5, 0x0 }, // 8766 |
14758 | | { PseudoVSRA_VX_MF4, VSRA_VX, 0x6, 0x0 }, // 8767 |
14759 | | { PseudoVSRA_VX_MF4_MASK, VSRA_VX, 0x6, 0x0 }, // 8768 |
14760 | | { PseudoVSRA_VX_MF2, VSRA_VX, 0x7, 0x0 }, // 8769 |
14761 | | { PseudoVSRA_VX_MF2_MASK, VSRA_VX, 0x7, 0x0 }, // 8770 |
14762 | | { PseudoVSRL_VI_M1, VSRL_VI, 0x0, 0x0 }, // 8771 |
14763 | | { PseudoVSRL_VI_M1_MASK, VSRL_VI, 0x0, 0x0 }, // 8772 |
14764 | | { PseudoVSRL_VI_M2, VSRL_VI, 0x1, 0x0 }, // 8773 |
14765 | | { PseudoVSRL_VI_M2_MASK, VSRL_VI, 0x1, 0x0 }, // 8774 |
14766 | | { PseudoVSRL_VI_M4, VSRL_VI, 0x2, 0x0 }, // 8775 |
14767 | | { PseudoVSRL_VI_M4_MASK, VSRL_VI, 0x2, 0x0 }, // 8776 |
14768 | | { PseudoVSRL_VI_M8, VSRL_VI, 0x3, 0x0 }, // 8777 |
14769 | | { PseudoVSRL_VI_M8_MASK, VSRL_VI, 0x3, 0x0 }, // 8778 |
14770 | | { PseudoVSRL_VI_MF8, VSRL_VI, 0x5, 0x0 }, // 8779 |
14771 | | { PseudoVSRL_VI_MF8_MASK, VSRL_VI, 0x5, 0x0 }, // 8780 |
14772 | | { PseudoVSRL_VI_MF4, VSRL_VI, 0x6, 0x0 }, // 8781 |
14773 | | { PseudoVSRL_VI_MF4_MASK, VSRL_VI, 0x6, 0x0 }, // 8782 |
14774 | | { PseudoVSRL_VI_MF2, VSRL_VI, 0x7, 0x0 }, // 8783 |
14775 | | { PseudoVSRL_VI_MF2_MASK, VSRL_VI, 0x7, 0x0 }, // 8784 |
14776 | | { PseudoVSRL_VV_M1, VSRL_VV, 0x0, 0x0 }, // 8785 |
14777 | | { PseudoVSRL_VV_M1_MASK, VSRL_VV, 0x0, 0x0 }, // 8786 |
14778 | | { PseudoVSRL_VV_M2, VSRL_VV, 0x1, 0x0 }, // 8787 |
14779 | | { PseudoVSRL_VV_M2_MASK, VSRL_VV, 0x1, 0x0 }, // 8788 |
14780 | | { PseudoVSRL_VV_M4, VSRL_VV, 0x2, 0x0 }, // 8789 |
14781 | | { PseudoVSRL_VV_M4_MASK, VSRL_VV, 0x2, 0x0 }, // 8790 |
14782 | | { PseudoVSRL_VV_M8, VSRL_VV, 0x3, 0x0 }, // 8791 |
14783 | | { PseudoVSRL_VV_M8_MASK, VSRL_VV, 0x3, 0x0 }, // 8792 |
14784 | | { PseudoVSRL_VV_MF8, VSRL_VV, 0x5, 0x0 }, // 8793 |
14785 | | { PseudoVSRL_VV_MF8_MASK, VSRL_VV, 0x5, 0x0 }, // 8794 |
14786 | | { PseudoVSRL_VV_MF4, VSRL_VV, 0x6, 0x0 }, // 8795 |
14787 | | { PseudoVSRL_VV_MF4_MASK, VSRL_VV, 0x6, 0x0 }, // 8796 |
14788 | | { PseudoVSRL_VV_MF2, VSRL_VV, 0x7, 0x0 }, // 8797 |
14789 | | { PseudoVSRL_VV_MF2_MASK, VSRL_VV, 0x7, 0x0 }, // 8798 |
14790 | | { PseudoVSRL_VX_M1, VSRL_VX, 0x0, 0x0 }, // 8799 |
14791 | | { PseudoVSRL_VX_M1_MASK, VSRL_VX, 0x0, 0x0 }, // 8800 |
14792 | | { PseudoVSRL_VX_M2, VSRL_VX, 0x1, 0x0 }, // 8801 |
14793 | | { PseudoVSRL_VX_M2_MASK, VSRL_VX, 0x1, 0x0 }, // 8802 |
14794 | | { PseudoVSRL_VX_M4, VSRL_VX, 0x2, 0x0 }, // 8803 |
14795 | | { PseudoVSRL_VX_M4_MASK, VSRL_VX, 0x2, 0x0 }, // 8804 |
14796 | | { PseudoVSRL_VX_M8, VSRL_VX, 0x3, 0x0 }, // 8805 |
14797 | | { PseudoVSRL_VX_M8_MASK, VSRL_VX, 0x3, 0x0 }, // 8806 |
14798 | | { PseudoVSRL_VX_MF8, VSRL_VX, 0x5, 0x0 }, // 8807 |
14799 | | { PseudoVSRL_VX_MF8_MASK, VSRL_VX, 0x5, 0x0 }, // 8808 |
14800 | | { PseudoVSRL_VX_MF4, VSRL_VX, 0x6, 0x0 }, // 8809 |
14801 | | { PseudoVSRL_VX_MF4_MASK, VSRL_VX, 0x6, 0x0 }, // 8810 |
14802 | | { PseudoVSRL_VX_MF2, VSRL_VX, 0x7, 0x0 }, // 8811 |
14803 | | { PseudoVSRL_VX_MF2_MASK, VSRL_VX, 0x7, 0x0 }, // 8812 |
14804 | | { PseudoVSSE16_V_M1, VSSE16_V, 0x0, 0x10 }, // 8813 |
14805 | | { PseudoVSSE16_V_M1_MASK, VSSE16_V, 0x0, 0x10 }, // 8814 |
14806 | | { PseudoVSSE16_V_M2, VSSE16_V, 0x1, 0x10 }, // 8815 |
14807 | | { PseudoVSSE16_V_M2_MASK, VSSE16_V, 0x1, 0x10 }, // 8816 |
14808 | | { PseudoVSSE16_V_M4, VSSE16_V, 0x2, 0x10 }, // 8817 |
14809 | | { PseudoVSSE16_V_M4_MASK, VSSE16_V, 0x2, 0x10 }, // 8818 |
14810 | | { PseudoVSSE16_V_M8, VSSE16_V, 0x3, 0x10 }, // 8819 |
14811 | | { PseudoVSSE16_V_M8_MASK, VSSE16_V, 0x3, 0x10 }, // 8820 |
14812 | | { PseudoVSSE16_V_MF4, VSSE16_V, 0x6, 0x10 }, // 8821 |
14813 | | { PseudoVSSE16_V_MF4_MASK, VSSE16_V, 0x6, 0x10 }, // 8822 |
14814 | | { PseudoVSSE16_V_MF2, VSSE16_V, 0x7, 0x10 }, // 8823 |
14815 | | { PseudoVSSE16_V_MF2_MASK, VSSE16_V, 0x7, 0x10 }, // 8824 |
14816 | | { PseudoVSSE32_V_M1, VSSE32_V, 0x0, 0x20 }, // 8825 |
14817 | | { PseudoVSSE32_V_M1_MASK, VSSE32_V, 0x0, 0x20 }, // 8826 |
14818 | | { PseudoVSSE32_V_M2, VSSE32_V, 0x1, 0x20 }, // 8827 |
14819 | | { PseudoVSSE32_V_M2_MASK, VSSE32_V, 0x1, 0x20 }, // 8828 |
14820 | | { PseudoVSSE32_V_M4, VSSE32_V, 0x2, 0x20 }, // 8829 |
14821 | | { PseudoVSSE32_V_M4_MASK, VSSE32_V, 0x2, 0x20 }, // 8830 |
14822 | | { PseudoVSSE32_V_M8, VSSE32_V, 0x3, 0x20 }, // 8831 |
14823 | | { PseudoVSSE32_V_M8_MASK, VSSE32_V, 0x3, 0x20 }, // 8832 |
14824 | | { PseudoVSSE32_V_MF2, VSSE32_V, 0x7, 0x20 }, // 8833 |
14825 | | { PseudoVSSE32_V_MF2_MASK, VSSE32_V, 0x7, 0x20 }, // 8834 |
14826 | | { PseudoVSSE64_V_M1, VSSE64_V, 0x0, 0x40 }, // 8835 |
14827 | | { PseudoVSSE64_V_M1_MASK, VSSE64_V, 0x0, 0x40 }, // 8836 |
14828 | | { PseudoVSSE64_V_M2, VSSE64_V, 0x1, 0x40 }, // 8837 |
14829 | | { PseudoVSSE64_V_M2_MASK, VSSE64_V, 0x1, 0x40 }, // 8838 |
14830 | | { PseudoVSSE64_V_M4, VSSE64_V, 0x2, 0x40 }, // 8839 |
14831 | | { PseudoVSSE64_V_M4_MASK, VSSE64_V, 0x2, 0x40 }, // 8840 |
14832 | | { PseudoVSSE64_V_M8, VSSE64_V, 0x3, 0x40 }, // 8841 |
14833 | | { PseudoVSSE64_V_M8_MASK, VSSE64_V, 0x3, 0x40 }, // 8842 |
14834 | | { PseudoVSSE8_V_M1, VSSE8_V, 0x0, 0x8 }, // 8843 |
14835 | | { PseudoVSSE8_V_M1_MASK, VSSE8_V, 0x0, 0x8 }, // 8844 |
14836 | | { PseudoVSSE8_V_M2, VSSE8_V, 0x1, 0x8 }, // 8845 |
14837 | | { PseudoVSSE8_V_M2_MASK, VSSE8_V, 0x1, 0x8 }, // 8846 |
14838 | | { PseudoVSSE8_V_M4, VSSE8_V, 0x2, 0x8 }, // 8847 |
14839 | | { PseudoVSSE8_V_M4_MASK, VSSE8_V, 0x2, 0x8 }, // 8848 |
14840 | | { PseudoVSSE8_V_M8, VSSE8_V, 0x3, 0x8 }, // 8849 |
14841 | | { PseudoVSSE8_V_M8_MASK, VSSE8_V, 0x3, 0x8 }, // 8850 |
14842 | | { PseudoVSSE8_V_MF8, VSSE8_V, 0x5, 0x8 }, // 8851 |
14843 | | { PseudoVSSE8_V_MF8_MASK, VSSE8_V, 0x5, 0x8 }, // 8852 |
14844 | | { PseudoVSSE8_V_MF4, VSSE8_V, 0x6, 0x8 }, // 8853 |
14845 | | { PseudoVSSE8_V_MF4_MASK, VSSE8_V, 0x6, 0x8 }, // 8854 |
14846 | | { PseudoVSSE8_V_MF2, VSSE8_V, 0x7, 0x8 }, // 8855 |
14847 | | { PseudoVSSE8_V_MF2_MASK, VSSE8_V, 0x7, 0x8 }, // 8856 |
14848 | | { PseudoVSSEG2E16_V_M1, VSSEG2E16_V, 0x0, 0x10 }, // 8857 |
14849 | | { PseudoVSSEG2E16_V_M1_MASK, VSSEG2E16_V, 0x0, 0x10 }, // 8858 |
14850 | | { PseudoVSSEG2E16_V_M2, VSSEG2E16_V, 0x1, 0x10 }, // 8859 |
14851 | | { PseudoVSSEG2E16_V_M2_MASK, VSSEG2E16_V, 0x1, 0x10 }, // 8860 |
14852 | | { PseudoVSSEG2E16_V_M4, VSSEG2E16_V, 0x2, 0x10 }, // 8861 |
14853 | | { PseudoVSSEG2E16_V_M4_MASK, VSSEG2E16_V, 0x2, 0x10 }, // 8862 |
14854 | | { PseudoVSSEG2E16_V_MF4, VSSEG2E16_V, 0x6, 0x10 }, // 8863 |
14855 | | { PseudoVSSEG2E16_V_MF4_MASK, VSSEG2E16_V, 0x6, 0x10 }, // 8864 |
14856 | | { PseudoVSSEG2E16_V_MF2, VSSEG2E16_V, 0x7, 0x10 }, // 8865 |
14857 | | { PseudoVSSEG2E16_V_MF2_MASK, VSSEG2E16_V, 0x7, 0x10 }, // 8866 |
14858 | | { PseudoVSSEG2E32_V_M1, VSSEG2E32_V, 0x0, 0x20 }, // 8867 |
14859 | | { PseudoVSSEG2E32_V_M1_MASK, VSSEG2E32_V, 0x0, 0x20 }, // 8868 |
14860 | | { PseudoVSSEG2E32_V_M2, VSSEG2E32_V, 0x1, 0x20 }, // 8869 |
14861 | | { PseudoVSSEG2E32_V_M2_MASK, VSSEG2E32_V, 0x1, 0x20 }, // 8870 |
14862 | | { PseudoVSSEG2E32_V_M4, VSSEG2E32_V, 0x2, 0x20 }, // 8871 |
14863 | | { PseudoVSSEG2E32_V_M4_MASK, VSSEG2E32_V, 0x2, 0x20 }, // 8872 |
14864 | | { PseudoVSSEG2E32_V_MF2, VSSEG2E32_V, 0x7, 0x20 }, // 8873 |
14865 | | { PseudoVSSEG2E32_V_MF2_MASK, VSSEG2E32_V, 0x7, 0x20 }, // 8874 |
14866 | | { PseudoVSSEG2E64_V_M1, VSSEG2E64_V, 0x0, 0x40 }, // 8875 |
14867 | | { PseudoVSSEG2E64_V_M1_MASK, VSSEG2E64_V, 0x0, 0x40 }, // 8876 |
14868 | | { PseudoVSSEG2E64_V_M2, VSSEG2E64_V, 0x1, 0x40 }, // 8877 |
14869 | | { PseudoVSSEG2E64_V_M2_MASK, VSSEG2E64_V, 0x1, 0x40 }, // 8878 |
14870 | | { PseudoVSSEG2E64_V_M4, VSSEG2E64_V, 0x2, 0x40 }, // 8879 |
14871 | | { PseudoVSSEG2E64_V_M4_MASK, VSSEG2E64_V, 0x2, 0x40 }, // 8880 |
14872 | | { PseudoVSSEG2E8_V_M1, VSSEG2E8_V, 0x0, 0x8 }, // 8881 |
14873 | | { PseudoVSSEG2E8_V_M1_MASK, VSSEG2E8_V, 0x0, 0x8 }, // 8882 |
14874 | | { PseudoVSSEG2E8_V_M2, VSSEG2E8_V, 0x1, 0x8 }, // 8883 |
14875 | | { PseudoVSSEG2E8_V_M2_MASK, VSSEG2E8_V, 0x1, 0x8 }, // 8884 |
14876 | | { PseudoVSSEG2E8_V_M4, VSSEG2E8_V, 0x2, 0x8 }, // 8885 |
14877 | | { PseudoVSSEG2E8_V_M4_MASK, VSSEG2E8_V, 0x2, 0x8 }, // 8886 |
14878 | | { PseudoVSSEG2E8_V_MF8, VSSEG2E8_V, 0x5, 0x8 }, // 8887 |
14879 | | { PseudoVSSEG2E8_V_MF8_MASK, VSSEG2E8_V, 0x5, 0x8 }, // 8888 |
14880 | | { PseudoVSSEG2E8_V_MF4, VSSEG2E8_V, 0x6, 0x8 }, // 8889 |
14881 | | { PseudoVSSEG2E8_V_MF4_MASK, VSSEG2E8_V, 0x6, 0x8 }, // 8890 |
14882 | | { PseudoVSSEG2E8_V_MF2, VSSEG2E8_V, 0x7, 0x8 }, // 8891 |
14883 | | { PseudoVSSEG2E8_V_MF2_MASK, VSSEG2E8_V, 0x7, 0x8 }, // 8892 |
14884 | | { PseudoVSSEG3E16_V_M1, VSSEG3E16_V, 0x0, 0x10 }, // 8893 |
14885 | | { PseudoVSSEG3E16_V_M1_MASK, VSSEG3E16_V, 0x0, 0x10 }, // 8894 |
14886 | | { PseudoVSSEG3E16_V_M2, VSSEG3E16_V, 0x1, 0x10 }, // 8895 |
14887 | | { PseudoVSSEG3E16_V_M2_MASK, VSSEG3E16_V, 0x1, 0x10 }, // 8896 |
14888 | | { PseudoVSSEG3E16_V_MF4, VSSEG3E16_V, 0x6, 0x10 }, // 8897 |
14889 | | { PseudoVSSEG3E16_V_MF4_MASK, VSSEG3E16_V, 0x6, 0x10 }, // 8898 |
14890 | | { PseudoVSSEG3E16_V_MF2, VSSEG3E16_V, 0x7, 0x10 }, // 8899 |
14891 | | { PseudoVSSEG3E16_V_MF2_MASK, VSSEG3E16_V, 0x7, 0x10 }, // 8900 |
14892 | | { PseudoVSSEG3E32_V_M1, VSSEG3E32_V, 0x0, 0x20 }, // 8901 |
14893 | | { PseudoVSSEG3E32_V_M1_MASK, VSSEG3E32_V, 0x0, 0x20 }, // 8902 |
14894 | | { PseudoVSSEG3E32_V_M2, VSSEG3E32_V, 0x1, 0x20 }, // 8903 |
14895 | | { PseudoVSSEG3E32_V_M2_MASK, VSSEG3E32_V, 0x1, 0x20 }, // 8904 |
14896 | | { PseudoVSSEG3E32_V_MF2, VSSEG3E32_V, 0x7, 0x20 }, // 8905 |
14897 | | { PseudoVSSEG3E32_V_MF2_MASK, VSSEG3E32_V, 0x7, 0x20 }, // 8906 |
14898 | | { PseudoVSSEG3E64_V_M1, VSSEG3E64_V, 0x0, 0x40 }, // 8907 |
14899 | | { PseudoVSSEG3E64_V_M1_MASK, VSSEG3E64_V, 0x0, 0x40 }, // 8908 |
14900 | | { PseudoVSSEG3E64_V_M2, VSSEG3E64_V, 0x1, 0x40 }, // 8909 |
14901 | | { PseudoVSSEG3E64_V_M2_MASK, VSSEG3E64_V, 0x1, 0x40 }, // 8910 |
14902 | | { PseudoVSSEG3E8_V_M1, VSSEG3E8_V, 0x0, 0x8 }, // 8911 |
14903 | | { PseudoVSSEG3E8_V_M1_MASK, VSSEG3E8_V, 0x0, 0x8 }, // 8912 |
14904 | | { PseudoVSSEG3E8_V_M2, VSSEG3E8_V, 0x1, 0x8 }, // 8913 |
14905 | | { PseudoVSSEG3E8_V_M2_MASK, VSSEG3E8_V, 0x1, 0x8 }, // 8914 |
14906 | | { PseudoVSSEG3E8_V_MF8, VSSEG3E8_V, 0x5, 0x8 }, // 8915 |
14907 | | { PseudoVSSEG3E8_V_MF8_MASK, VSSEG3E8_V, 0x5, 0x8 }, // 8916 |
14908 | | { PseudoVSSEG3E8_V_MF4, VSSEG3E8_V, 0x6, 0x8 }, // 8917 |
14909 | | { PseudoVSSEG3E8_V_MF4_MASK, VSSEG3E8_V, 0x6, 0x8 }, // 8918 |
14910 | | { PseudoVSSEG3E8_V_MF2, VSSEG3E8_V, 0x7, 0x8 }, // 8919 |
14911 | | { PseudoVSSEG3E8_V_MF2_MASK, VSSEG3E8_V, 0x7, 0x8 }, // 8920 |
14912 | | { PseudoVSSEG4E16_V_M1, VSSEG4E16_V, 0x0, 0x10 }, // 8921 |
14913 | | { PseudoVSSEG4E16_V_M1_MASK, VSSEG4E16_V, 0x0, 0x10 }, // 8922 |
14914 | | { PseudoVSSEG4E16_V_M2, VSSEG4E16_V, 0x1, 0x10 }, // 8923 |
14915 | | { PseudoVSSEG4E16_V_M2_MASK, VSSEG4E16_V, 0x1, 0x10 }, // 8924 |
14916 | | { PseudoVSSEG4E16_V_MF4, VSSEG4E16_V, 0x6, 0x10 }, // 8925 |
14917 | | { PseudoVSSEG4E16_V_MF4_MASK, VSSEG4E16_V, 0x6, 0x10 }, // 8926 |
14918 | | { PseudoVSSEG4E16_V_MF2, VSSEG4E16_V, 0x7, 0x10 }, // 8927 |
14919 | | { PseudoVSSEG4E16_V_MF2_MASK, VSSEG4E16_V, 0x7, 0x10 }, // 8928 |
14920 | | { PseudoVSSEG4E32_V_M1, VSSEG4E32_V, 0x0, 0x20 }, // 8929 |
14921 | | { PseudoVSSEG4E32_V_M1_MASK, VSSEG4E32_V, 0x0, 0x20 }, // 8930 |
14922 | | { PseudoVSSEG4E32_V_M2, VSSEG4E32_V, 0x1, 0x20 }, // 8931 |
14923 | | { PseudoVSSEG4E32_V_M2_MASK, VSSEG4E32_V, 0x1, 0x20 }, // 8932 |
14924 | | { PseudoVSSEG4E32_V_MF2, VSSEG4E32_V, 0x7, 0x20 }, // 8933 |
14925 | | { PseudoVSSEG4E32_V_MF2_MASK, VSSEG4E32_V, 0x7, 0x20 }, // 8934 |
14926 | | { PseudoVSSEG4E64_V_M1, VSSEG4E64_V, 0x0, 0x40 }, // 8935 |
14927 | | { PseudoVSSEG4E64_V_M1_MASK, VSSEG4E64_V, 0x0, 0x40 }, // 8936 |
14928 | | { PseudoVSSEG4E64_V_M2, VSSEG4E64_V, 0x1, 0x40 }, // 8937 |
14929 | | { PseudoVSSEG4E64_V_M2_MASK, VSSEG4E64_V, 0x1, 0x40 }, // 8938 |
14930 | | { PseudoVSSEG4E8_V_M1, VSSEG4E8_V, 0x0, 0x8 }, // 8939 |
14931 | | { PseudoVSSEG4E8_V_M1_MASK, VSSEG4E8_V, 0x0, 0x8 }, // 8940 |
14932 | | { PseudoVSSEG4E8_V_M2, VSSEG4E8_V, 0x1, 0x8 }, // 8941 |
14933 | | { PseudoVSSEG4E8_V_M2_MASK, VSSEG4E8_V, 0x1, 0x8 }, // 8942 |
14934 | | { PseudoVSSEG4E8_V_MF8, VSSEG4E8_V, 0x5, 0x8 }, // 8943 |
14935 | | { PseudoVSSEG4E8_V_MF8_MASK, VSSEG4E8_V, 0x5, 0x8 }, // 8944 |
14936 | | { PseudoVSSEG4E8_V_MF4, VSSEG4E8_V, 0x6, 0x8 }, // 8945 |
14937 | | { PseudoVSSEG4E8_V_MF4_MASK, VSSEG4E8_V, 0x6, 0x8 }, // 8946 |
14938 | | { PseudoVSSEG4E8_V_MF2, VSSEG4E8_V, 0x7, 0x8 }, // 8947 |
14939 | | { PseudoVSSEG4E8_V_MF2_MASK, VSSEG4E8_V, 0x7, 0x8 }, // 8948 |
14940 | | { PseudoVSSEG5E16_V_M1, VSSEG5E16_V, 0x0, 0x10 }, // 8949 |
14941 | | { PseudoVSSEG5E16_V_M1_MASK, VSSEG5E16_V, 0x0, 0x10 }, // 8950 |
14942 | | { PseudoVSSEG5E16_V_MF4, VSSEG5E16_V, 0x6, 0x10 }, // 8951 |
14943 | | { PseudoVSSEG5E16_V_MF4_MASK, VSSEG5E16_V, 0x6, 0x10 }, // 8952 |
14944 | | { PseudoVSSEG5E16_V_MF2, VSSEG5E16_V, 0x7, 0x10 }, // 8953 |
14945 | | { PseudoVSSEG5E16_V_MF2_MASK, VSSEG5E16_V, 0x7, 0x10 }, // 8954 |
14946 | | { PseudoVSSEG5E32_V_M1, VSSEG5E32_V, 0x0, 0x20 }, // 8955 |
14947 | | { PseudoVSSEG5E32_V_M1_MASK, VSSEG5E32_V, 0x0, 0x20 }, // 8956 |
14948 | | { PseudoVSSEG5E32_V_MF2, VSSEG5E32_V, 0x7, 0x20 }, // 8957 |
14949 | | { PseudoVSSEG5E32_V_MF2_MASK, VSSEG5E32_V, 0x7, 0x20 }, // 8958 |
14950 | | { PseudoVSSEG5E64_V_M1, VSSEG5E64_V, 0x0, 0x40 }, // 8959 |
14951 | | { PseudoVSSEG5E64_V_M1_MASK, VSSEG5E64_V, 0x0, 0x40 }, // 8960 |
14952 | | { PseudoVSSEG5E8_V_M1, VSSEG5E8_V, 0x0, 0x8 }, // 8961 |
14953 | | { PseudoVSSEG5E8_V_M1_MASK, VSSEG5E8_V, 0x0, 0x8 }, // 8962 |
14954 | | { PseudoVSSEG5E8_V_MF8, VSSEG5E8_V, 0x5, 0x8 }, // 8963 |
14955 | | { PseudoVSSEG5E8_V_MF8_MASK, VSSEG5E8_V, 0x5, 0x8 }, // 8964 |
14956 | | { PseudoVSSEG5E8_V_MF4, VSSEG5E8_V, 0x6, 0x8 }, // 8965 |
14957 | | { PseudoVSSEG5E8_V_MF4_MASK, VSSEG5E8_V, 0x6, 0x8 }, // 8966 |
14958 | | { PseudoVSSEG5E8_V_MF2, VSSEG5E8_V, 0x7, 0x8 }, // 8967 |
14959 | | { PseudoVSSEG5E8_V_MF2_MASK, VSSEG5E8_V, 0x7, 0x8 }, // 8968 |
14960 | | { PseudoVSSEG6E16_V_M1, VSSEG6E16_V, 0x0, 0x10 }, // 8969 |
14961 | | { PseudoVSSEG6E16_V_M1_MASK, VSSEG6E16_V, 0x0, 0x10 }, // 8970 |
14962 | | { PseudoVSSEG6E16_V_MF4, VSSEG6E16_V, 0x6, 0x10 }, // 8971 |
14963 | | { PseudoVSSEG6E16_V_MF4_MASK, VSSEG6E16_V, 0x6, 0x10 }, // 8972 |
14964 | | { PseudoVSSEG6E16_V_MF2, VSSEG6E16_V, 0x7, 0x10 }, // 8973 |
14965 | | { PseudoVSSEG6E16_V_MF2_MASK, VSSEG6E16_V, 0x7, 0x10 }, // 8974 |
14966 | | { PseudoVSSEG6E32_V_M1, VSSEG6E32_V, 0x0, 0x20 }, // 8975 |
14967 | | { PseudoVSSEG6E32_V_M1_MASK, VSSEG6E32_V, 0x0, 0x20 }, // 8976 |
14968 | | { PseudoVSSEG6E32_V_MF2, VSSEG6E32_V, 0x7, 0x20 }, // 8977 |
14969 | | { PseudoVSSEG6E32_V_MF2_MASK, VSSEG6E32_V, 0x7, 0x20 }, // 8978 |
14970 | | { PseudoVSSEG6E64_V_M1, VSSEG6E64_V, 0x0, 0x40 }, // 8979 |
14971 | | { PseudoVSSEG6E64_V_M1_MASK, VSSEG6E64_V, 0x0, 0x40 }, // 8980 |
14972 | | { PseudoVSSEG6E8_V_M1, VSSEG6E8_V, 0x0, 0x8 }, // 8981 |
14973 | | { PseudoVSSEG6E8_V_M1_MASK, VSSEG6E8_V, 0x0, 0x8 }, // 8982 |
14974 | | { PseudoVSSEG6E8_V_MF8, VSSEG6E8_V, 0x5, 0x8 }, // 8983 |
14975 | | { PseudoVSSEG6E8_V_MF8_MASK, VSSEG6E8_V, 0x5, 0x8 }, // 8984 |
14976 | | { PseudoVSSEG6E8_V_MF4, VSSEG6E8_V, 0x6, 0x8 }, // 8985 |
14977 | | { PseudoVSSEG6E8_V_MF4_MASK, VSSEG6E8_V, 0x6, 0x8 }, // 8986 |
14978 | | { PseudoVSSEG6E8_V_MF2, VSSEG6E8_V, 0x7, 0x8 }, // 8987 |
14979 | | { PseudoVSSEG6E8_V_MF2_MASK, VSSEG6E8_V, 0x7, 0x8 }, // 8988 |
14980 | | { PseudoVSSEG7E16_V_M1, VSSEG7E16_V, 0x0, 0x10 }, // 8989 |
14981 | | { PseudoVSSEG7E16_V_M1_MASK, VSSEG7E16_V, 0x0, 0x10 }, // 8990 |
14982 | | { PseudoVSSEG7E16_V_MF4, VSSEG7E16_V, 0x6, 0x10 }, // 8991 |
14983 | | { PseudoVSSEG7E16_V_MF4_MASK, VSSEG7E16_V, 0x6, 0x10 }, // 8992 |
14984 | | { PseudoVSSEG7E16_V_MF2, VSSEG7E16_V, 0x7, 0x10 }, // 8993 |
14985 | | { PseudoVSSEG7E16_V_MF2_MASK, VSSEG7E16_V, 0x7, 0x10 }, // 8994 |
14986 | | { PseudoVSSEG7E32_V_M1, VSSEG7E32_V, 0x0, 0x20 }, // 8995 |
14987 | | { PseudoVSSEG7E32_V_M1_MASK, VSSEG7E32_V, 0x0, 0x20 }, // 8996 |
14988 | | { PseudoVSSEG7E32_V_MF2, VSSEG7E32_V, 0x7, 0x20 }, // 8997 |
14989 | | { PseudoVSSEG7E32_V_MF2_MASK, VSSEG7E32_V, 0x7, 0x20 }, // 8998 |
14990 | | { PseudoVSSEG7E64_V_M1, VSSEG7E64_V, 0x0, 0x40 }, // 8999 |
14991 | | { PseudoVSSEG7E64_V_M1_MASK, VSSEG7E64_V, 0x0, 0x40 }, // 9000 |
14992 | | { PseudoVSSEG7E8_V_M1, VSSEG7E8_V, 0x0, 0x8 }, // 9001 |
14993 | | { PseudoVSSEG7E8_V_M1_MASK, VSSEG7E8_V, 0x0, 0x8 }, // 9002 |
14994 | | { PseudoVSSEG7E8_V_MF8, VSSEG7E8_V, 0x5, 0x8 }, // 9003 |
14995 | | { PseudoVSSEG7E8_V_MF8_MASK, VSSEG7E8_V, 0x5, 0x8 }, // 9004 |
14996 | | { PseudoVSSEG7E8_V_MF4, VSSEG7E8_V, 0x6, 0x8 }, // 9005 |
14997 | | { PseudoVSSEG7E8_V_MF4_MASK, VSSEG7E8_V, 0x6, 0x8 }, // 9006 |
14998 | | { PseudoVSSEG7E8_V_MF2, VSSEG7E8_V, 0x7, 0x8 }, // 9007 |
14999 | | { PseudoVSSEG7E8_V_MF2_MASK, VSSEG7E8_V, 0x7, 0x8 }, // 9008 |
15000 | | { PseudoVSSEG8E16_V_M1, VSSEG8E16_V, 0x0, 0x10 }, // 9009 |
15001 | | { PseudoVSSEG8E16_V_M1_MASK, VSSEG8E16_V, 0x0, 0x10 }, // 9010 |
15002 | | { PseudoVSSEG8E16_V_MF4, VSSEG8E16_V, 0x6, 0x10 }, // 9011 |
15003 | | { PseudoVSSEG8E16_V_MF4_MASK, VSSEG8E16_V, 0x6, 0x10 }, // 9012 |
15004 | | { PseudoVSSEG8E16_V_MF2, VSSEG8E16_V, 0x7, 0x10 }, // 9013 |
15005 | | { PseudoVSSEG8E16_V_MF2_MASK, VSSEG8E16_V, 0x7, 0x10 }, // 9014 |
15006 | | { PseudoVSSEG8E32_V_M1, VSSEG8E32_V, 0x0, 0x20 }, // 9015 |
15007 | | { PseudoVSSEG8E32_V_M1_MASK, VSSEG8E32_V, 0x0, 0x20 }, // 9016 |
15008 | | { PseudoVSSEG8E32_V_MF2, VSSEG8E32_V, 0x7, 0x20 }, // 9017 |
15009 | | { PseudoVSSEG8E32_V_MF2_MASK, VSSEG8E32_V, 0x7, 0x20 }, // 9018 |
15010 | | { PseudoVSSEG8E64_V_M1, VSSEG8E64_V, 0x0, 0x40 }, // 9019 |
15011 | | { PseudoVSSEG8E64_V_M1_MASK, VSSEG8E64_V, 0x0, 0x40 }, // 9020 |
15012 | | { PseudoVSSEG8E8_V_M1, VSSEG8E8_V, 0x0, 0x8 }, // 9021 |
15013 | | { PseudoVSSEG8E8_V_M1_MASK, VSSEG8E8_V, 0x0, 0x8 }, // 9022 |
15014 | | { PseudoVSSEG8E8_V_MF8, VSSEG8E8_V, 0x5, 0x8 }, // 9023 |
15015 | | { PseudoVSSEG8E8_V_MF8_MASK, VSSEG8E8_V, 0x5, 0x8 }, // 9024 |
15016 | | { PseudoVSSEG8E8_V_MF4, VSSEG8E8_V, 0x6, 0x8 }, // 9025 |
15017 | | { PseudoVSSEG8E8_V_MF4_MASK, VSSEG8E8_V, 0x6, 0x8 }, // 9026 |
15018 | | { PseudoVSSEG8E8_V_MF2, VSSEG8E8_V, 0x7, 0x8 }, // 9027 |
15019 | | { PseudoVSSEG8E8_V_MF2_MASK, VSSEG8E8_V, 0x7, 0x8 }, // 9028 |
15020 | | { PseudoVSSRA_VI_M1, VSSRA_VI, 0x0, 0x0 }, // 9029 |
15021 | | { PseudoVSSRA_VI_M1_MASK, VSSRA_VI, 0x0, 0x0 }, // 9030 |
15022 | | { PseudoVSSRA_VI_M2, VSSRA_VI, 0x1, 0x0 }, // 9031 |
15023 | | { PseudoVSSRA_VI_M2_MASK, VSSRA_VI, 0x1, 0x0 }, // 9032 |
15024 | | { PseudoVSSRA_VI_M4, VSSRA_VI, 0x2, 0x0 }, // 9033 |
15025 | | { PseudoVSSRA_VI_M4_MASK, VSSRA_VI, 0x2, 0x0 }, // 9034 |
15026 | | { PseudoVSSRA_VI_M8, VSSRA_VI, 0x3, 0x0 }, // 9035 |
15027 | | { PseudoVSSRA_VI_M8_MASK, VSSRA_VI, 0x3, 0x0 }, // 9036 |
15028 | | { PseudoVSSRA_VI_MF8, VSSRA_VI, 0x5, 0x0 }, // 9037 |
15029 | | { PseudoVSSRA_VI_MF8_MASK, VSSRA_VI, 0x5, 0x0 }, // 9038 |
15030 | | { PseudoVSSRA_VI_MF4, VSSRA_VI, 0x6, 0x0 }, // 9039 |
15031 | | { PseudoVSSRA_VI_MF4_MASK, VSSRA_VI, 0x6, 0x0 }, // 9040 |
15032 | | { PseudoVSSRA_VI_MF2, VSSRA_VI, 0x7, 0x0 }, // 9041 |
15033 | | { PseudoVSSRA_VI_MF2_MASK, VSSRA_VI, 0x7, 0x0 }, // 9042 |
15034 | | { PseudoVSSRA_VV_M1, VSSRA_VV, 0x0, 0x0 }, // 9043 |
15035 | | { PseudoVSSRA_VV_M1_MASK, VSSRA_VV, 0x0, 0x0 }, // 9044 |
15036 | | { PseudoVSSRA_VV_M2, VSSRA_VV, 0x1, 0x0 }, // 9045 |
15037 | | { PseudoVSSRA_VV_M2_MASK, VSSRA_VV, 0x1, 0x0 }, // 9046 |
15038 | | { PseudoVSSRA_VV_M4, VSSRA_VV, 0x2, 0x0 }, // 9047 |
15039 | | { PseudoVSSRA_VV_M4_MASK, VSSRA_VV, 0x2, 0x0 }, // 9048 |
15040 | | { PseudoVSSRA_VV_M8, VSSRA_VV, 0x3, 0x0 }, // 9049 |
15041 | | { PseudoVSSRA_VV_M8_MASK, VSSRA_VV, 0x3, 0x0 }, // 9050 |
15042 | | { PseudoVSSRA_VV_MF8, VSSRA_VV, 0x5, 0x0 }, // 9051 |
15043 | | { PseudoVSSRA_VV_MF8_MASK, VSSRA_VV, 0x5, 0x0 }, // 9052 |
15044 | | { PseudoVSSRA_VV_MF4, VSSRA_VV, 0x6, 0x0 }, // 9053 |
15045 | | { PseudoVSSRA_VV_MF4_MASK, VSSRA_VV, 0x6, 0x0 }, // 9054 |
15046 | | { PseudoVSSRA_VV_MF2, VSSRA_VV, 0x7, 0x0 }, // 9055 |
15047 | | { PseudoVSSRA_VV_MF2_MASK, VSSRA_VV, 0x7, 0x0 }, // 9056 |
15048 | | { PseudoVSSRA_VX_M1, VSSRA_VX, 0x0, 0x0 }, // 9057 |
15049 | | { PseudoVSSRA_VX_M1_MASK, VSSRA_VX, 0x0, 0x0 }, // 9058 |
15050 | | { PseudoVSSRA_VX_M2, VSSRA_VX, 0x1, 0x0 }, // 9059 |
15051 | | { PseudoVSSRA_VX_M2_MASK, VSSRA_VX, 0x1, 0x0 }, // 9060 |
15052 | | { PseudoVSSRA_VX_M4, VSSRA_VX, 0x2, 0x0 }, // 9061 |
15053 | | { PseudoVSSRA_VX_M4_MASK, VSSRA_VX, 0x2, 0x0 }, // 9062 |
15054 | | { PseudoVSSRA_VX_M8, VSSRA_VX, 0x3, 0x0 }, // 9063 |
15055 | | { PseudoVSSRA_VX_M8_MASK, VSSRA_VX, 0x3, 0x0 }, // 9064 |
15056 | | { PseudoVSSRA_VX_MF8, VSSRA_VX, 0x5, 0x0 }, // 9065 |
15057 | | { PseudoVSSRA_VX_MF8_MASK, VSSRA_VX, 0x5, 0x0 }, // 9066 |
15058 | | { PseudoVSSRA_VX_MF4, VSSRA_VX, 0x6, 0x0 }, // 9067 |
15059 | | { PseudoVSSRA_VX_MF4_MASK, VSSRA_VX, 0x6, 0x0 }, // 9068 |
15060 | | { PseudoVSSRA_VX_MF2, VSSRA_VX, 0x7, 0x0 }, // 9069 |
15061 | | { PseudoVSSRA_VX_MF2_MASK, VSSRA_VX, 0x7, 0x0 }, // 9070 |
15062 | | { PseudoVSSRL_VI_M1, VSSRL_VI, 0x0, 0x0 }, // 9071 |
15063 | | { PseudoVSSRL_VI_M1_MASK, VSSRL_VI, 0x0, 0x0 }, // 9072 |
15064 | | { PseudoVSSRL_VI_M2, VSSRL_VI, 0x1, 0x0 }, // 9073 |
15065 | | { PseudoVSSRL_VI_M2_MASK, VSSRL_VI, 0x1, 0x0 }, // 9074 |
15066 | | { PseudoVSSRL_VI_M4, VSSRL_VI, 0x2, 0x0 }, // 9075 |
15067 | | { PseudoVSSRL_VI_M4_MASK, VSSRL_VI, 0x2, 0x0 }, // 9076 |
15068 | | { PseudoVSSRL_VI_M8, VSSRL_VI, 0x3, 0x0 }, // 9077 |
15069 | | { PseudoVSSRL_VI_M8_MASK, VSSRL_VI, 0x3, 0x0 }, // 9078 |
15070 | | { PseudoVSSRL_VI_MF8, VSSRL_VI, 0x5, 0x0 }, // 9079 |
15071 | | { PseudoVSSRL_VI_MF8_MASK, VSSRL_VI, 0x5, 0x0 }, // 9080 |
15072 | | { PseudoVSSRL_VI_MF4, VSSRL_VI, 0x6, 0x0 }, // 9081 |
15073 | | { PseudoVSSRL_VI_MF4_MASK, VSSRL_VI, 0x6, 0x0 }, // 9082 |
15074 | | { PseudoVSSRL_VI_MF2, VSSRL_VI, 0x7, 0x0 }, // 9083 |
15075 | | { PseudoVSSRL_VI_MF2_MASK, VSSRL_VI, 0x7, 0x0 }, // 9084 |
15076 | | { PseudoVSSRL_VV_M1, VSSRL_VV, 0x0, 0x0 }, // 9085 |
15077 | | { PseudoVSSRL_VV_M1_MASK, VSSRL_VV, 0x0, 0x0 }, // 9086 |
15078 | | { PseudoVSSRL_VV_M2, VSSRL_VV, 0x1, 0x0 }, // 9087 |
15079 | | { PseudoVSSRL_VV_M2_MASK, VSSRL_VV, 0x1, 0x0 }, // 9088 |
15080 | | { PseudoVSSRL_VV_M4, VSSRL_VV, 0x2, 0x0 }, // 9089 |
15081 | | { PseudoVSSRL_VV_M4_MASK, VSSRL_VV, 0x2, 0x0 }, // 9090 |
15082 | | { PseudoVSSRL_VV_M8, VSSRL_VV, 0x3, 0x0 }, // 9091 |
15083 | | { PseudoVSSRL_VV_M8_MASK, VSSRL_VV, 0x3, 0x0 }, // 9092 |
15084 | | { PseudoVSSRL_VV_MF8, VSSRL_VV, 0x5, 0x0 }, // 9093 |
15085 | | { PseudoVSSRL_VV_MF8_MASK, VSSRL_VV, 0x5, 0x0 }, // 9094 |
15086 | | { PseudoVSSRL_VV_MF4, VSSRL_VV, 0x6, 0x0 }, // 9095 |
15087 | | { PseudoVSSRL_VV_MF4_MASK, VSSRL_VV, 0x6, 0x0 }, // 9096 |
15088 | | { PseudoVSSRL_VV_MF2, VSSRL_VV, 0x7, 0x0 }, // 9097 |
15089 | | { PseudoVSSRL_VV_MF2_MASK, VSSRL_VV, 0x7, 0x0 }, // 9098 |
15090 | | { PseudoVSSRL_VX_M1, VSSRL_VX, 0x0, 0x0 }, // 9099 |
15091 | | { PseudoVSSRL_VX_M1_MASK, VSSRL_VX, 0x0, 0x0 }, // 9100 |
15092 | | { PseudoVSSRL_VX_M2, VSSRL_VX, 0x1, 0x0 }, // 9101 |
15093 | | { PseudoVSSRL_VX_M2_MASK, VSSRL_VX, 0x1, 0x0 }, // 9102 |
15094 | | { PseudoVSSRL_VX_M4, VSSRL_VX, 0x2, 0x0 }, // 9103 |
15095 | | { PseudoVSSRL_VX_M4_MASK, VSSRL_VX, 0x2, 0x0 }, // 9104 |
15096 | | { PseudoVSSRL_VX_M8, VSSRL_VX, 0x3, 0x0 }, // 9105 |
15097 | | { PseudoVSSRL_VX_M8_MASK, VSSRL_VX, 0x3, 0x0 }, // 9106 |
15098 | | { PseudoVSSRL_VX_MF8, VSSRL_VX, 0x5, 0x0 }, // 9107 |
15099 | | { PseudoVSSRL_VX_MF8_MASK, VSSRL_VX, 0x5, 0x0 }, // 9108 |
15100 | | { PseudoVSSRL_VX_MF4, VSSRL_VX, 0x6, 0x0 }, // 9109 |
15101 | | { PseudoVSSRL_VX_MF4_MASK, VSSRL_VX, 0x6, 0x0 }, // 9110 |
15102 | | { PseudoVSSRL_VX_MF2, VSSRL_VX, 0x7, 0x0 }, // 9111 |
15103 | | { PseudoVSSRL_VX_MF2_MASK, VSSRL_VX, 0x7, 0x0 }, // 9112 |
15104 | | { PseudoVSSSEG2E16_V_M1, VSSSEG2E16_V, 0x0, 0x10 }, // 9113 |
15105 | | { PseudoVSSSEG2E16_V_M1_MASK, VSSSEG2E16_V, 0x0, 0x10 }, // 9114 |
15106 | | { PseudoVSSSEG2E16_V_M2, VSSSEG2E16_V, 0x1, 0x10 }, // 9115 |
15107 | | { PseudoVSSSEG2E16_V_M2_MASK, VSSSEG2E16_V, 0x1, 0x10 }, // 9116 |
15108 | | { PseudoVSSSEG2E16_V_M4, VSSSEG2E16_V, 0x2, 0x10 }, // 9117 |
15109 | | { PseudoVSSSEG2E16_V_M4_MASK, VSSSEG2E16_V, 0x2, 0x10 }, // 9118 |
15110 | | { PseudoVSSSEG2E16_V_MF4, VSSSEG2E16_V, 0x6, 0x10 }, // 9119 |
15111 | | { PseudoVSSSEG2E16_V_MF4_MASK, VSSSEG2E16_V, 0x6, 0x10 }, // 9120 |
15112 | | { PseudoVSSSEG2E16_V_MF2, VSSSEG2E16_V, 0x7, 0x10 }, // 9121 |
15113 | | { PseudoVSSSEG2E16_V_MF2_MASK, VSSSEG2E16_V, 0x7, 0x10 }, // 9122 |
15114 | | { PseudoVSSSEG2E32_V_M1, VSSSEG2E32_V, 0x0, 0x20 }, // 9123 |
15115 | | { PseudoVSSSEG2E32_V_M1_MASK, VSSSEG2E32_V, 0x0, 0x20 }, // 9124 |
15116 | | { PseudoVSSSEG2E32_V_M2, VSSSEG2E32_V, 0x1, 0x20 }, // 9125 |
15117 | | { PseudoVSSSEG2E32_V_M2_MASK, VSSSEG2E32_V, 0x1, 0x20 }, // 9126 |
15118 | | { PseudoVSSSEG2E32_V_M4, VSSSEG2E32_V, 0x2, 0x20 }, // 9127 |
15119 | | { PseudoVSSSEG2E32_V_M4_MASK, VSSSEG2E32_V, 0x2, 0x20 }, // 9128 |
15120 | | { PseudoVSSSEG2E32_V_MF2, VSSSEG2E32_V, 0x7, 0x20 }, // 9129 |
15121 | | { PseudoVSSSEG2E32_V_MF2_MASK, VSSSEG2E32_V, 0x7, 0x20 }, // 9130 |
15122 | | { PseudoVSSSEG2E64_V_M1, VSSSEG2E64_V, 0x0, 0x40 }, // 9131 |
15123 | | { PseudoVSSSEG2E64_V_M1_MASK, VSSSEG2E64_V, 0x0, 0x40 }, // 9132 |
15124 | | { PseudoVSSSEG2E64_V_M2, VSSSEG2E64_V, 0x1, 0x40 }, // 9133 |
15125 | | { PseudoVSSSEG2E64_V_M2_MASK, VSSSEG2E64_V, 0x1, 0x40 }, // 9134 |
15126 | | { PseudoVSSSEG2E64_V_M4, VSSSEG2E64_V, 0x2, 0x40 }, // 9135 |
15127 | | { PseudoVSSSEG2E64_V_M4_MASK, VSSSEG2E64_V, 0x2, 0x40 }, // 9136 |
15128 | | { PseudoVSSSEG2E8_V_M1, VSSSEG2E8_V, 0x0, 0x8 }, // 9137 |
15129 | | { PseudoVSSSEG2E8_V_M1_MASK, VSSSEG2E8_V, 0x0, 0x8 }, // 9138 |
15130 | | { PseudoVSSSEG2E8_V_M2, VSSSEG2E8_V, 0x1, 0x8 }, // 9139 |
15131 | | { PseudoVSSSEG2E8_V_M2_MASK, VSSSEG2E8_V, 0x1, 0x8 }, // 9140 |
15132 | | { PseudoVSSSEG2E8_V_M4, VSSSEG2E8_V, 0x2, 0x8 }, // 9141 |
15133 | | { PseudoVSSSEG2E8_V_M4_MASK, VSSSEG2E8_V, 0x2, 0x8 }, // 9142 |
15134 | | { PseudoVSSSEG2E8_V_MF8, VSSSEG2E8_V, 0x5, 0x8 }, // 9143 |
15135 | | { PseudoVSSSEG2E8_V_MF8_MASK, VSSSEG2E8_V, 0x5, 0x8 }, // 9144 |
15136 | | { PseudoVSSSEG2E8_V_MF4, VSSSEG2E8_V, 0x6, 0x8 }, // 9145 |
15137 | | { PseudoVSSSEG2E8_V_MF4_MASK, VSSSEG2E8_V, 0x6, 0x8 }, // 9146 |
15138 | | { PseudoVSSSEG2E8_V_MF2, VSSSEG2E8_V, 0x7, 0x8 }, // 9147 |
15139 | | { PseudoVSSSEG2E8_V_MF2_MASK, VSSSEG2E8_V, 0x7, 0x8 }, // 9148 |
15140 | | { PseudoVSSSEG3E16_V_M1, VSSSEG3E16_V, 0x0, 0x10 }, // 9149 |
15141 | | { PseudoVSSSEG3E16_V_M1_MASK, VSSSEG3E16_V, 0x0, 0x10 }, // 9150 |
15142 | | { PseudoVSSSEG3E16_V_M2, VSSSEG3E16_V, 0x1, 0x10 }, // 9151 |
15143 | | { PseudoVSSSEG3E16_V_M2_MASK, VSSSEG3E16_V, 0x1, 0x10 }, // 9152 |
15144 | | { PseudoVSSSEG3E16_V_MF4, VSSSEG3E16_V, 0x6, 0x10 }, // 9153 |
15145 | | { PseudoVSSSEG3E16_V_MF4_MASK, VSSSEG3E16_V, 0x6, 0x10 }, // 9154 |
15146 | | { PseudoVSSSEG3E16_V_MF2, VSSSEG3E16_V, 0x7, 0x10 }, // 9155 |
15147 | | { PseudoVSSSEG3E16_V_MF2_MASK, VSSSEG3E16_V, 0x7, 0x10 }, // 9156 |
15148 | | { PseudoVSSSEG3E32_V_M1, VSSSEG3E32_V, 0x0, 0x20 }, // 9157 |
15149 | | { PseudoVSSSEG3E32_V_M1_MASK, VSSSEG3E32_V, 0x0, 0x20 }, // 9158 |
15150 | | { PseudoVSSSEG3E32_V_M2, VSSSEG3E32_V, 0x1, 0x20 }, // 9159 |
15151 | | { PseudoVSSSEG3E32_V_M2_MASK, VSSSEG3E32_V, 0x1, 0x20 }, // 9160 |
15152 | | { PseudoVSSSEG3E32_V_MF2, VSSSEG3E32_V, 0x7, 0x20 }, // 9161 |
15153 | | { PseudoVSSSEG3E32_V_MF2_MASK, VSSSEG3E32_V, 0x7, 0x20 }, // 9162 |
15154 | | { PseudoVSSSEG3E64_V_M1, VSSSEG3E64_V, 0x0, 0x40 }, // 9163 |
15155 | | { PseudoVSSSEG3E64_V_M1_MASK, VSSSEG3E64_V, 0x0, 0x40 }, // 9164 |
15156 | | { PseudoVSSSEG3E64_V_M2, VSSSEG3E64_V, 0x1, 0x40 }, // 9165 |
15157 | | { PseudoVSSSEG3E64_V_M2_MASK, VSSSEG3E64_V, 0x1, 0x40 }, // 9166 |
15158 | | { PseudoVSSSEG3E8_V_M1, VSSSEG3E8_V, 0x0, 0x8 }, // 9167 |
15159 | | { PseudoVSSSEG3E8_V_M1_MASK, VSSSEG3E8_V, 0x0, 0x8 }, // 9168 |
15160 | | { PseudoVSSSEG3E8_V_M2, VSSSEG3E8_V, 0x1, 0x8 }, // 9169 |
15161 | | { PseudoVSSSEG3E8_V_M2_MASK, VSSSEG3E8_V, 0x1, 0x8 }, // 9170 |
15162 | | { PseudoVSSSEG3E8_V_MF8, VSSSEG3E8_V, 0x5, 0x8 }, // 9171 |
15163 | | { PseudoVSSSEG3E8_V_MF8_MASK, VSSSEG3E8_V, 0x5, 0x8 }, // 9172 |
15164 | | { PseudoVSSSEG3E8_V_MF4, VSSSEG3E8_V, 0x6, 0x8 }, // 9173 |
15165 | | { PseudoVSSSEG3E8_V_MF4_MASK, VSSSEG3E8_V, 0x6, 0x8 }, // 9174 |
15166 | | { PseudoVSSSEG3E8_V_MF2, VSSSEG3E8_V, 0x7, 0x8 }, // 9175 |
15167 | | { PseudoVSSSEG3E8_V_MF2_MASK, VSSSEG3E8_V, 0x7, 0x8 }, // 9176 |
15168 | | { PseudoVSSSEG4E16_V_M1, VSSSEG4E16_V, 0x0, 0x10 }, // 9177 |
15169 | | { PseudoVSSSEG4E16_V_M1_MASK, VSSSEG4E16_V, 0x0, 0x10 }, // 9178 |
15170 | | { PseudoVSSSEG4E16_V_M2, VSSSEG4E16_V, 0x1, 0x10 }, // 9179 |
15171 | | { PseudoVSSSEG4E16_V_M2_MASK, VSSSEG4E16_V, 0x1, 0x10 }, // 9180 |
15172 | | { PseudoVSSSEG4E16_V_MF4, VSSSEG4E16_V, 0x6, 0x10 }, // 9181 |
15173 | | { PseudoVSSSEG4E16_V_MF4_MASK, VSSSEG4E16_V, 0x6, 0x10 }, // 9182 |
15174 | | { PseudoVSSSEG4E16_V_MF2, VSSSEG4E16_V, 0x7, 0x10 }, // 9183 |
15175 | | { PseudoVSSSEG4E16_V_MF2_MASK, VSSSEG4E16_V, 0x7, 0x10 }, // 9184 |
15176 | | { PseudoVSSSEG4E32_V_M1, VSSSEG4E32_V, 0x0, 0x20 }, // 9185 |
15177 | | { PseudoVSSSEG4E32_V_M1_MASK, VSSSEG4E32_V, 0x0, 0x20 }, // 9186 |
15178 | | { PseudoVSSSEG4E32_V_M2, VSSSEG4E32_V, 0x1, 0x20 }, // 9187 |
15179 | | { PseudoVSSSEG4E32_V_M2_MASK, VSSSEG4E32_V, 0x1, 0x20 }, // 9188 |
15180 | | { PseudoVSSSEG4E32_V_MF2, VSSSEG4E32_V, 0x7, 0x20 }, // 9189 |
15181 | | { PseudoVSSSEG4E32_V_MF2_MASK, VSSSEG4E32_V, 0x7, 0x20 }, // 9190 |
15182 | | { PseudoVSSSEG4E64_V_M1, VSSSEG4E64_V, 0x0, 0x40 }, // 9191 |
15183 | | { PseudoVSSSEG4E64_V_M1_MASK, VSSSEG4E64_V, 0x0, 0x40 }, // 9192 |
15184 | | { PseudoVSSSEG4E64_V_M2, VSSSEG4E64_V, 0x1, 0x40 }, // 9193 |
15185 | | { PseudoVSSSEG4E64_V_M2_MASK, VSSSEG4E64_V, 0x1, 0x40 }, // 9194 |
15186 | | { PseudoVSSSEG4E8_V_M1, VSSSEG4E8_V, 0x0, 0x8 }, // 9195 |
15187 | | { PseudoVSSSEG4E8_V_M1_MASK, VSSSEG4E8_V, 0x0, 0x8 }, // 9196 |
15188 | | { PseudoVSSSEG4E8_V_M2, VSSSEG4E8_V, 0x1, 0x8 }, // 9197 |
15189 | | { PseudoVSSSEG4E8_V_M2_MASK, VSSSEG4E8_V, 0x1, 0x8 }, // 9198 |
15190 | | { PseudoVSSSEG4E8_V_MF8, VSSSEG4E8_V, 0x5, 0x8 }, // 9199 |
15191 | | { PseudoVSSSEG4E8_V_MF8_MASK, VSSSEG4E8_V, 0x5, 0x8 }, // 9200 |
15192 | | { PseudoVSSSEG4E8_V_MF4, VSSSEG4E8_V, 0x6, 0x8 }, // 9201 |
15193 | | { PseudoVSSSEG4E8_V_MF4_MASK, VSSSEG4E8_V, 0x6, 0x8 }, // 9202 |
15194 | | { PseudoVSSSEG4E8_V_MF2, VSSSEG4E8_V, 0x7, 0x8 }, // 9203 |
15195 | | { PseudoVSSSEG4E8_V_MF2_MASK, VSSSEG4E8_V, 0x7, 0x8 }, // 9204 |
15196 | | { PseudoVSSSEG5E16_V_M1, VSSSEG5E16_V, 0x0, 0x10 }, // 9205 |
15197 | | { PseudoVSSSEG5E16_V_M1_MASK, VSSSEG5E16_V, 0x0, 0x10 }, // 9206 |
15198 | | { PseudoVSSSEG5E16_V_MF4, VSSSEG5E16_V, 0x6, 0x10 }, // 9207 |
15199 | | { PseudoVSSSEG5E16_V_MF4_MASK, VSSSEG5E16_V, 0x6, 0x10 }, // 9208 |
15200 | | { PseudoVSSSEG5E16_V_MF2, VSSSEG5E16_V, 0x7, 0x10 }, // 9209 |
15201 | | { PseudoVSSSEG5E16_V_MF2_MASK, VSSSEG5E16_V, 0x7, 0x10 }, // 9210 |
15202 | | { PseudoVSSSEG5E32_V_M1, VSSSEG5E32_V, 0x0, 0x20 }, // 9211 |
15203 | | { PseudoVSSSEG5E32_V_M1_MASK, VSSSEG5E32_V, 0x0, 0x20 }, // 9212 |
15204 | | { PseudoVSSSEG5E32_V_MF2, VSSSEG5E32_V, 0x7, 0x20 }, // 9213 |
15205 | | { PseudoVSSSEG5E32_V_MF2_MASK, VSSSEG5E32_V, 0x7, 0x20 }, // 9214 |
15206 | | { PseudoVSSSEG5E64_V_M1, VSSSEG5E64_V, 0x0, 0x40 }, // 9215 |
15207 | | { PseudoVSSSEG5E64_V_M1_MASK, VSSSEG5E64_V, 0x0, 0x40 }, // 9216 |
15208 | | { PseudoVSSSEG5E8_V_M1, VSSSEG5E8_V, 0x0, 0x8 }, // 9217 |
15209 | | { PseudoVSSSEG5E8_V_M1_MASK, VSSSEG5E8_V, 0x0, 0x8 }, // 9218 |
15210 | | { PseudoVSSSEG5E8_V_MF8, VSSSEG5E8_V, 0x5, 0x8 }, // 9219 |
15211 | | { PseudoVSSSEG5E8_V_MF8_MASK, VSSSEG5E8_V, 0x5, 0x8 }, // 9220 |
15212 | | { PseudoVSSSEG5E8_V_MF4, VSSSEG5E8_V, 0x6, 0x8 }, // 9221 |
15213 | | { PseudoVSSSEG5E8_V_MF4_MASK, VSSSEG5E8_V, 0x6, 0x8 }, // 9222 |
15214 | | { PseudoVSSSEG5E8_V_MF2, VSSSEG5E8_V, 0x7, 0x8 }, // 9223 |
15215 | | { PseudoVSSSEG5E8_V_MF2_MASK, VSSSEG5E8_V, 0x7, 0x8 }, // 9224 |
15216 | | { PseudoVSSSEG6E16_V_M1, VSSSEG6E16_V, 0x0, 0x10 }, // 9225 |
15217 | | { PseudoVSSSEG6E16_V_M1_MASK, VSSSEG6E16_V, 0x0, 0x10 }, // 9226 |
15218 | | { PseudoVSSSEG6E16_V_MF4, VSSSEG6E16_V, 0x6, 0x10 }, // 9227 |
15219 | | { PseudoVSSSEG6E16_V_MF4_MASK, VSSSEG6E16_V, 0x6, 0x10 }, // 9228 |
15220 | | { PseudoVSSSEG6E16_V_MF2, VSSSEG6E16_V, 0x7, 0x10 }, // 9229 |
15221 | | { PseudoVSSSEG6E16_V_MF2_MASK, VSSSEG6E16_V, 0x7, 0x10 }, // 9230 |
15222 | | { PseudoVSSSEG6E32_V_M1, VSSSEG6E32_V, 0x0, 0x20 }, // 9231 |
15223 | | { PseudoVSSSEG6E32_V_M1_MASK, VSSSEG6E32_V, 0x0, 0x20 }, // 9232 |
15224 | | { PseudoVSSSEG6E32_V_MF2, VSSSEG6E32_V, 0x7, 0x20 }, // 9233 |
15225 | | { PseudoVSSSEG6E32_V_MF2_MASK, VSSSEG6E32_V, 0x7, 0x20 }, // 9234 |
15226 | | { PseudoVSSSEG6E64_V_M1, VSSSEG6E64_V, 0x0, 0x40 }, // 9235 |
15227 | | { PseudoVSSSEG6E64_V_M1_MASK, VSSSEG6E64_V, 0x0, 0x40 }, // 9236 |
15228 | | { PseudoVSSSEG6E8_V_M1, VSSSEG6E8_V, 0x0, 0x8 }, // 9237 |
15229 | | { PseudoVSSSEG6E8_V_M1_MASK, VSSSEG6E8_V, 0x0, 0x8 }, // 9238 |
15230 | | { PseudoVSSSEG6E8_V_MF8, VSSSEG6E8_V, 0x5, 0x8 }, // 9239 |
15231 | | { PseudoVSSSEG6E8_V_MF8_MASK, VSSSEG6E8_V, 0x5, 0x8 }, // 9240 |
15232 | | { PseudoVSSSEG6E8_V_MF4, VSSSEG6E8_V, 0x6, 0x8 }, // 9241 |
15233 | | { PseudoVSSSEG6E8_V_MF4_MASK, VSSSEG6E8_V, 0x6, 0x8 }, // 9242 |
15234 | | { PseudoVSSSEG6E8_V_MF2, VSSSEG6E8_V, 0x7, 0x8 }, // 9243 |
15235 | | { PseudoVSSSEG6E8_V_MF2_MASK, VSSSEG6E8_V, 0x7, 0x8 }, // 9244 |
15236 | | { PseudoVSSSEG7E16_V_M1, VSSSEG7E16_V, 0x0, 0x10 }, // 9245 |
15237 | | { PseudoVSSSEG7E16_V_M1_MASK, VSSSEG7E16_V, 0x0, 0x10 }, // 9246 |
15238 | | { PseudoVSSSEG7E16_V_MF4, VSSSEG7E16_V, 0x6, 0x10 }, // 9247 |
15239 | | { PseudoVSSSEG7E16_V_MF4_MASK, VSSSEG7E16_V, 0x6, 0x10 }, // 9248 |
15240 | | { PseudoVSSSEG7E16_V_MF2, VSSSEG7E16_V, 0x7, 0x10 }, // 9249 |
15241 | | { PseudoVSSSEG7E16_V_MF2_MASK, VSSSEG7E16_V, 0x7, 0x10 }, // 9250 |
15242 | | { PseudoVSSSEG7E32_V_M1, VSSSEG7E32_V, 0x0, 0x20 }, // 9251 |
15243 | | { PseudoVSSSEG7E32_V_M1_MASK, VSSSEG7E32_V, 0x0, 0x20 }, // 9252 |
15244 | | { PseudoVSSSEG7E32_V_MF2, VSSSEG7E32_V, 0x7, 0x20 }, // 9253 |
15245 | | { PseudoVSSSEG7E32_V_MF2_MASK, VSSSEG7E32_V, 0x7, 0x20 }, // 9254 |
15246 | | { PseudoVSSSEG7E64_V_M1, VSSSEG7E64_V, 0x0, 0x40 }, // 9255 |
15247 | | { PseudoVSSSEG7E64_V_M1_MASK, VSSSEG7E64_V, 0x0, 0x40 }, // 9256 |
15248 | | { PseudoVSSSEG7E8_V_M1, VSSSEG7E8_V, 0x0, 0x8 }, // 9257 |
15249 | | { PseudoVSSSEG7E8_V_M1_MASK, VSSSEG7E8_V, 0x0, 0x8 }, // 9258 |
15250 | | { PseudoVSSSEG7E8_V_MF8, VSSSEG7E8_V, 0x5, 0x8 }, // 9259 |
15251 | | { PseudoVSSSEG7E8_V_MF8_MASK, VSSSEG7E8_V, 0x5, 0x8 }, // 9260 |
15252 | | { PseudoVSSSEG7E8_V_MF4, VSSSEG7E8_V, 0x6, 0x8 }, // 9261 |
15253 | | { PseudoVSSSEG7E8_V_MF4_MASK, VSSSEG7E8_V, 0x6, 0x8 }, // 9262 |
15254 | | { PseudoVSSSEG7E8_V_MF2, VSSSEG7E8_V, 0x7, 0x8 }, // 9263 |
15255 | | { PseudoVSSSEG7E8_V_MF2_MASK, VSSSEG7E8_V, 0x7, 0x8 }, // 9264 |
15256 | | { PseudoVSSSEG8E16_V_M1, VSSSEG8E16_V, 0x0, 0x10 }, // 9265 |
15257 | | { PseudoVSSSEG8E16_V_M1_MASK, VSSSEG8E16_V, 0x0, 0x10 }, // 9266 |
15258 | | { PseudoVSSSEG8E16_V_MF4, VSSSEG8E16_V, 0x6, 0x10 }, // 9267 |
15259 | | { PseudoVSSSEG8E16_V_MF4_MASK, VSSSEG8E16_V, 0x6, 0x10 }, // 9268 |
15260 | | { PseudoVSSSEG8E16_V_MF2, VSSSEG8E16_V, 0x7, 0x10 }, // 9269 |
15261 | | { PseudoVSSSEG8E16_V_MF2_MASK, VSSSEG8E16_V, 0x7, 0x10 }, // 9270 |
15262 | | { PseudoVSSSEG8E32_V_M1, VSSSEG8E32_V, 0x0, 0x20 }, // 9271 |
15263 | | { PseudoVSSSEG8E32_V_M1_MASK, VSSSEG8E32_V, 0x0, 0x20 }, // 9272 |
15264 | | { PseudoVSSSEG8E32_V_MF2, VSSSEG8E32_V, 0x7, 0x20 }, // 9273 |
15265 | | { PseudoVSSSEG8E32_V_MF2_MASK, VSSSEG8E32_V, 0x7, 0x20 }, // 9274 |
15266 | | { PseudoVSSSEG8E64_V_M1, VSSSEG8E64_V, 0x0, 0x40 }, // 9275 |
15267 | | { PseudoVSSSEG8E64_V_M1_MASK, VSSSEG8E64_V, 0x0, 0x40 }, // 9276 |
15268 | | { PseudoVSSSEG8E8_V_M1, VSSSEG8E8_V, 0x0, 0x8 }, // 9277 |
15269 | | { PseudoVSSSEG8E8_V_M1_MASK, VSSSEG8E8_V, 0x0, 0x8 }, // 9278 |
15270 | | { PseudoVSSSEG8E8_V_MF8, VSSSEG8E8_V, 0x5, 0x8 }, // 9279 |
15271 | | { PseudoVSSSEG8E8_V_MF8_MASK, VSSSEG8E8_V, 0x5, 0x8 }, // 9280 |
15272 | | { PseudoVSSSEG8E8_V_MF4, VSSSEG8E8_V, 0x6, 0x8 }, // 9281 |
15273 | | { PseudoVSSSEG8E8_V_MF4_MASK, VSSSEG8E8_V, 0x6, 0x8 }, // 9282 |
15274 | | { PseudoVSSSEG8E8_V_MF2, VSSSEG8E8_V, 0x7, 0x8 }, // 9283 |
15275 | | { PseudoVSSSEG8E8_V_MF2_MASK, VSSSEG8E8_V, 0x7, 0x8 }, // 9284 |
15276 | | { PseudoVSSUBU_VV_M1, VSSUBU_VV, 0x0, 0x0 }, // 9285 |
15277 | | { PseudoVSSUBU_VV_M1_MASK, VSSUBU_VV, 0x0, 0x0 }, // 9286 |
15278 | | { PseudoVSSUBU_VV_M2, VSSUBU_VV, 0x1, 0x0 }, // 9287 |
15279 | | { PseudoVSSUBU_VV_M2_MASK, VSSUBU_VV, 0x1, 0x0 }, // 9288 |
15280 | | { PseudoVSSUBU_VV_M4, VSSUBU_VV, 0x2, 0x0 }, // 9289 |
15281 | | { PseudoVSSUBU_VV_M4_MASK, VSSUBU_VV, 0x2, 0x0 }, // 9290 |
15282 | | { PseudoVSSUBU_VV_M8, VSSUBU_VV, 0x3, 0x0 }, // 9291 |
15283 | | { PseudoVSSUBU_VV_M8_MASK, VSSUBU_VV, 0x3, 0x0 }, // 9292 |
15284 | | { PseudoVSSUBU_VV_MF8, VSSUBU_VV, 0x5, 0x0 }, // 9293 |
15285 | | { PseudoVSSUBU_VV_MF8_MASK, VSSUBU_VV, 0x5, 0x0 }, // 9294 |
15286 | | { PseudoVSSUBU_VV_MF4, VSSUBU_VV, 0x6, 0x0 }, // 9295 |
15287 | | { PseudoVSSUBU_VV_MF4_MASK, VSSUBU_VV, 0x6, 0x0 }, // 9296 |
15288 | | { PseudoVSSUBU_VV_MF2, VSSUBU_VV, 0x7, 0x0 }, // 9297 |
15289 | | { PseudoVSSUBU_VV_MF2_MASK, VSSUBU_VV, 0x7, 0x0 }, // 9298 |
15290 | | { PseudoVSSUBU_VX_M1, VSSUBU_VX, 0x0, 0x0 }, // 9299 |
15291 | | { PseudoVSSUBU_VX_M1_MASK, VSSUBU_VX, 0x0, 0x0 }, // 9300 |
15292 | | { PseudoVSSUBU_VX_M2, VSSUBU_VX, 0x1, 0x0 }, // 9301 |
15293 | | { PseudoVSSUBU_VX_M2_MASK, VSSUBU_VX, 0x1, 0x0 }, // 9302 |
15294 | | { PseudoVSSUBU_VX_M4, VSSUBU_VX, 0x2, 0x0 }, // 9303 |
15295 | | { PseudoVSSUBU_VX_M4_MASK, VSSUBU_VX, 0x2, 0x0 }, // 9304 |
15296 | | { PseudoVSSUBU_VX_M8, VSSUBU_VX, 0x3, 0x0 }, // 9305 |
15297 | | { PseudoVSSUBU_VX_M8_MASK, VSSUBU_VX, 0x3, 0x0 }, // 9306 |
15298 | | { PseudoVSSUBU_VX_MF8, VSSUBU_VX, 0x5, 0x0 }, // 9307 |
15299 | | { PseudoVSSUBU_VX_MF8_MASK, VSSUBU_VX, 0x5, 0x0 }, // 9308 |
15300 | | { PseudoVSSUBU_VX_MF4, VSSUBU_VX, 0x6, 0x0 }, // 9309 |
15301 | | { PseudoVSSUBU_VX_MF4_MASK, VSSUBU_VX, 0x6, 0x0 }, // 9310 |
15302 | | { PseudoVSSUBU_VX_MF2, VSSUBU_VX, 0x7, 0x0 }, // 9311 |
15303 | | { PseudoVSSUBU_VX_MF2_MASK, VSSUBU_VX, 0x7, 0x0 }, // 9312 |
15304 | | { PseudoVSSUB_VV_M1, VSSUB_VV, 0x0, 0x0 }, // 9313 |
15305 | | { PseudoVSSUB_VV_M1_MASK, VSSUB_VV, 0x0, 0x0 }, // 9314 |
15306 | | { PseudoVSSUB_VV_M2, VSSUB_VV, 0x1, 0x0 }, // 9315 |
15307 | | { PseudoVSSUB_VV_M2_MASK, VSSUB_VV, 0x1, 0x0 }, // 9316 |
15308 | | { PseudoVSSUB_VV_M4, VSSUB_VV, 0x2, 0x0 }, // 9317 |
15309 | | { PseudoVSSUB_VV_M4_MASK, VSSUB_VV, 0x2, 0x0 }, // 9318 |
15310 | | { PseudoVSSUB_VV_M8, VSSUB_VV, 0x3, 0x0 }, // 9319 |
15311 | | { PseudoVSSUB_VV_M8_MASK, VSSUB_VV, 0x3, 0x0 }, // 9320 |
15312 | | { PseudoVSSUB_VV_MF8, VSSUB_VV, 0x5, 0x0 }, // 9321 |
15313 | | { PseudoVSSUB_VV_MF8_MASK, VSSUB_VV, 0x5, 0x0 }, // 9322 |
15314 | | { PseudoVSSUB_VV_MF4, VSSUB_VV, 0x6, 0x0 }, // 9323 |
15315 | | { PseudoVSSUB_VV_MF4_MASK, VSSUB_VV, 0x6, 0x0 }, // 9324 |
15316 | | { PseudoVSSUB_VV_MF2, VSSUB_VV, 0x7, 0x0 }, // 9325 |
15317 | | { PseudoVSSUB_VV_MF2_MASK, VSSUB_VV, 0x7, 0x0 }, // 9326 |
15318 | | { PseudoVSSUB_VX_M1, VSSUB_VX, 0x0, 0x0 }, // 9327 |
15319 | | { PseudoVSSUB_VX_M1_MASK, VSSUB_VX, 0x0, 0x0 }, // 9328 |
15320 | | { PseudoVSSUB_VX_M2, VSSUB_VX, 0x1, 0x0 }, // 9329 |
15321 | | { PseudoVSSUB_VX_M2_MASK, VSSUB_VX, 0x1, 0x0 }, // 9330 |
15322 | | { PseudoVSSUB_VX_M4, VSSUB_VX, 0x2, 0x0 }, // 9331 |
15323 | | { PseudoVSSUB_VX_M4_MASK, VSSUB_VX, 0x2, 0x0 }, // 9332 |
15324 | | { PseudoVSSUB_VX_M8, VSSUB_VX, 0x3, 0x0 }, // 9333 |
15325 | | { PseudoVSSUB_VX_M8_MASK, VSSUB_VX, 0x3, 0x0 }, // 9334 |
15326 | | { PseudoVSSUB_VX_MF8, VSSUB_VX, 0x5, 0x0 }, // 9335 |
15327 | | { PseudoVSSUB_VX_MF8_MASK, VSSUB_VX, 0x5, 0x0 }, // 9336 |
15328 | | { PseudoVSSUB_VX_MF4, VSSUB_VX, 0x6, 0x0 }, // 9337 |
15329 | | { PseudoVSSUB_VX_MF4_MASK, VSSUB_VX, 0x6, 0x0 }, // 9338 |
15330 | | { PseudoVSSUB_VX_MF2, VSSUB_VX, 0x7, 0x0 }, // 9339 |
15331 | | { PseudoVSSUB_VX_MF2_MASK, VSSUB_VX, 0x7, 0x0 }, // 9340 |
15332 | | { PseudoVSUB_VV_M1, VSUB_VV, 0x0, 0x0 }, // 9341 |
15333 | | { PseudoVSUB_VV_M1_MASK, VSUB_VV, 0x0, 0x0 }, // 9342 |
15334 | | { PseudoVSUB_VV_M2, VSUB_VV, 0x1, 0x0 }, // 9343 |
15335 | | { PseudoVSUB_VV_M2_MASK, VSUB_VV, 0x1, 0x0 }, // 9344 |
15336 | | { PseudoVSUB_VV_M4, VSUB_VV, 0x2, 0x0 }, // 9345 |
15337 | | { PseudoVSUB_VV_M4_MASK, VSUB_VV, 0x2, 0x0 }, // 9346 |
15338 | | { PseudoVSUB_VV_M8, VSUB_VV, 0x3, 0x0 }, // 9347 |
15339 | | { PseudoVSUB_VV_M8_MASK, VSUB_VV, 0x3, 0x0 }, // 9348 |
15340 | | { PseudoVSUB_VV_MF8, VSUB_VV, 0x5, 0x0 }, // 9349 |
15341 | | { PseudoVSUB_VV_MF8_MASK, VSUB_VV, 0x5, 0x0 }, // 9350 |
15342 | | { PseudoVSUB_VV_MF4, VSUB_VV, 0x6, 0x0 }, // 9351 |
15343 | | { PseudoVSUB_VV_MF4_MASK, VSUB_VV, 0x6, 0x0 }, // 9352 |
15344 | | { PseudoVSUB_VV_MF2, VSUB_VV, 0x7, 0x0 }, // 9353 |
15345 | | { PseudoVSUB_VV_MF2_MASK, VSUB_VV, 0x7, 0x0 }, // 9354 |
15346 | | { PseudoVSUB_VX_M1, VSUB_VX, 0x0, 0x0 }, // 9355 |
15347 | | { PseudoVSUB_VX_M1_MASK, VSUB_VX, 0x0, 0x0 }, // 9356 |
15348 | | { PseudoVSUB_VX_M2, VSUB_VX, 0x1, 0x0 }, // 9357 |
15349 | | { PseudoVSUB_VX_M2_MASK, VSUB_VX, 0x1, 0x0 }, // 9358 |
15350 | | { PseudoVSUB_VX_M4, VSUB_VX, 0x2, 0x0 }, // 9359 |
15351 | | { PseudoVSUB_VX_M4_MASK, VSUB_VX, 0x2, 0x0 }, // 9360 |
15352 | | { PseudoVSUB_VX_M8, VSUB_VX, 0x3, 0x0 }, // 9361 |
15353 | | { PseudoVSUB_VX_M8_MASK, VSUB_VX, 0x3, 0x0 }, // 9362 |
15354 | | { PseudoVSUB_VX_MF8, VSUB_VX, 0x5, 0x0 }, // 9363 |
15355 | | { PseudoVSUB_VX_MF8_MASK, VSUB_VX, 0x5, 0x0 }, // 9364 |
15356 | | { PseudoVSUB_VX_MF4, VSUB_VX, 0x6, 0x0 }, // 9365 |
15357 | | { PseudoVSUB_VX_MF4_MASK, VSUB_VX, 0x6, 0x0 }, // 9366 |
15358 | | { PseudoVSUB_VX_MF2, VSUB_VX, 0x7, 0x0 }, // 9367 |
15359 | | { PseudoVSUB_VX_MF2_MASK, VSUB_VX, 0x7, 0x0 }, // 9368 |
15360 | | { PseudoVSUXEI16_V_M1_M1, VSUXEI16_V, 0x0, 0x0 }, // 9369 |
15361 | | { PseudoVSUXEI16_V_M1_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9370 |
15362 | | { PseudoVSUXEI16_V_M2_M1, VSUXEI16_V, 0x0, 0x0 }, // 9371 |
15363 | | { PseudoVSUXEI16_V_M2_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9372 |
15364 | | { PseudoVSUXEI16_V_MF2_M1, VSUXEI16_V, 0x0, 0x0 }, // 9373 |
15365 | | { PseudoVSUXEI16_V_MF2_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9374 |
15366 | | { PseudoVSUXEI16_V_MF4_M1, VSUXEI16_V, 0x0, 0x0 }, // 9375 |
15367 | | { PseudoVSUXEI16_V_MF4_M1_MASK, VSUXEI16_V, 0x0, 0x0 }, // 9376 |
15368 | | { PseudoVSUXEI16_V_M1_M2, VSUXEI16_V, 0x1, 0x0 }, // 9377 |
15369 | | { PseudoVSUXEI16_V_M1_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9378 |
15370 | | { PseudoVSUXEI16_V_M2_M2, VSUXEI16_V, 0x1, 0x0 }, // 9379 |
15371 | | { PseudoVSUXEI16_V_M2_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9380 |
15372 | | { PseudoVSUXEI16_V_M4_M2, VSUXEI16_V, 0x1, 0x0 }, // 9381 |
15373 | | { PseudoVSUXEI16_V_M4_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9382 |
15374 | | { PseudoVSUXEI16_V_MF2_M2, VSUXEI16_V, 0x1, 0x0 }, // 9383 |
15375 | | { PseudoVSUXEI16_V_MF2_M2_MASK, VSUXEI16_V, 0x1, 0x0 }, // 9384 |
15376 | | { PseudoVSUXEI16_V_M1_M4, VSUXEI16_V, 0x2, 0x0 }, // 9385 |
15377 | | { PseudoVSUXEI16_V_M1_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9386 |
15378 | | { PseudoVSUXEI16_V_M2_M4, VSUXEI16_V, 0x2, 0x0 }, // 9387 |
15379 | | { PseudoVSUXEI16_V_M2_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9388 |
15380 | | { PseudoVSUXEI16_V_M4_M4, VSUXEI16_V, 0x2, 0x0 }, // 9389 |
15381 | | { PseudoVSUXEI16_V_M4_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9390 |
15382 | | { PseudoVSUXEI16_V_M8_M4, VSUXEI16_V, 0x2, 0x0 }, // 9391 |
15383 | | { PseudoVSUXEI16_V_M8_M4_MASK, VSUXEI16_V, 0x2, 0x0 }, // 9392 |
15384 | | { PseudoVSUXEI16_V_M2_M8, VSUXEI16_V, 0x3, 0x0 }, // 9393 |
15385 | | { PseudoVSUXEI16_V_M2_M8_MASK, VSUXEI16_V, 0x3, 0x0 }, // 9394 |
15386 | | { PseudoVSUXEI16_V_M4_M8, VSUXEI16_V, 0x3, 0x0 }, // 9395 |
15387 | | { PseudoVSUXEI16_V_M4_M8_MASK, VSUXEI16_V, 0x3, 0x0 }, // 9396 |
15388 | | { PseudoVSUXEI16_V_M8_M8, VSUXEI16_V, 0x3, 0x0 }, // 9397 |
15389 | | { PseudoVSUXEI16_V_M8_M8_MASK, VSUXEI16_V, 0x3, 0x0 }, // 9398 |
15390 | | { PseudoVSUXEI16_V_MF4_MF8, VSUXEI16_V, 0x5, 0x0 }, // 9399 |
15391 | | { PseudoVSUXEI16_V_MF4_MF8_MASK, VSUXEI16_V, 0x5, 0x0 }, // 9400 |
15392 | | { PseudoVSUXEI16_V_MF2_MF4, VSUXEI16_V, 0x6, 0x0 }, // 9401 |
15393 | | { PseudoVSUXEI16_V_MF2_MF4_MASK, VSUXEI16_V, 0x6, 0x0 }, // 9402 |
15394 | | { PseudoVSUXEI16_V_MF4_MF4, VSUXEI16_V, 0x6, 0x0 }, // 9403 |
15395 | | { PseudoVSUXEI16_V_MF4_MF4_MASK, VSUXEI16_V, 0x6, 0x0 }, // 9404 |
15396 | | { PseudoVSUXEI16_V_M1_MF2, VSUXEI16_V, 0x7, 0x0 }, // 9405 |
15397 | | { PseudoVSUXEI16_V_M1_MF2_MASK, VSUXEI16_V, 0x7, 0x0 }, // 9406 |
15398 | | { PseudoVSUXEI16_V_MF2_MF2, VSUXEI16_V, 0x7, 0x0 }, // 9407 |
15399 | | { PseudoVSUXEI16_V_MF2_MF2_MASK, VSUXEI16_V, 0x7, 0x0 }, // 9408 |
15400 | | { PseudoVSUXEI16_V_MF4_MF2, VSUXEI16_V, 0x7, 0x0 }, // 9409 |
15401 | | { PseudoVSUXEI16_V_MF4_MF2_MASK, VSUXEI16_V, 0x7, 0x0 }, // 9410 |
15402 | | { PseudoVSUXEI32_V_M1_M1, VSUXEI32_V, 0x0, 0x0 }, // 9411 |
15403 | | { PseudoVSUXEI32_V_M1_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 9412 |
15404 | | { PseudoVSUXEI32_V_M2_M1, VSUXEI32_V, 0x0, 0x0 }, // 9413 |
15405 | | { PseudoVSUXEI32_V_M2_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 9414 |
15406 | | { PseudoVSUXEI32_V_M4_M1, VSUXEI32_V, 0x0, 0x0 }, // 9415 |
15407 | | { PseudoVSUXEI32_V_M4_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 9416 |
15408 | | { PseudoVSUXEI32_V_MF2_M1, VSUXEI32_V, 0x0, 0x0 }, // 9417 |
15409 | | { PseudoVSUXEI32_V_MF2_M1_MASK, VSUXEI32_V, 0x0, 0x0 }, // 9418 |
15410 | | { PseudoVSUXEI32_V_M1_M2, VSUXEI32_V, 0x1, 0x0 }, // 9419 |
15411 | | { PseudoVSUXEI32_V_M1_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 9420 |
15412 | | { PseudoVSUXEI32_V_M2_M2, VSUXEI32_V, 0x1, 0x0 }, // 9421 |
15413 | | { PseudoVSUXEI32_V_M2_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 9422 |
15414 | | { PseudoVSUXEI32_V_M4_M2, VSUXEI32_V, 0x1, 0x0 }, // 9423 |
15415 | | { PseudoVSUXEI32_V_M4_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 9424 |
15416 | | { PseudoVSUXEI32_V_M8_M2, VSUXEI32_V, 0x1, 0x0 }, // 9425 |
15417 | | { PseudoVSUXEI32_V_M8_M2_MASK, VSUXEI32_V, 0x1, 0x0 }, // 9426 |
15418 | | { PseudoVSUXEI32_V_M2_M4, VSUXEI32_V, 0x2, 0x0 }, // 9427 |
15419 | | { PseudoVSUXEI32_V_M2_M4_MASK, VSUXEI32_V, 0x2, 0x0 }, // 9428 |
15420 | | { PseudoVSUXEI32_V_M4_M4, VSUXEI32_V, 0x2, 0x0 }, // 9429 |
15421 | | { PseudoVSUXEI32_V_M4_M4_MASK, VSUXEI32_V, 0x2, 0x0 }, // 9430 |
15422 | | { PseudoVSUXEI32_V_M8_M4, VSUXEI32_V, 0x2, 0x0 }, // 9431 |
15423 | | { PseudoVSUXEI32_V_M8_M4_MASK, VSUXEI32_V, 0x2, 0x0 }, // 9432 |
15424 | | { PseudoVSUXEI32_V_M4_M8, VSUXEI32_V, 0x3, 0x0 }, // 9433 |
15425 | | { PseudoVSUXEI32_V_M4_M8_MASK, VSUXEI32_V, 0x3, 0x0 }, // 9434 |
15426 | | { PseudoVSUXEI32_V_M8_M8, VSUXEI32_V, 0x3, 0x0 }, // 9435 |
15427 | | { PseudoVSUXEI32_V_M8_M8_MASK, VSUXEI32_V, 0x3, 0x0 }, // 9436 |
15428 | | { PseudoVSUXEI32_V_MF2_MF8, VSUXEI32_V, 0x5, 0x0 }, // 9437 |
15429 | | { PseudoVSUXEI32_V_MF2_MF8_MASK, VSUXEI32_V, 0x5, 0x0 }, // 9438 |
15430 | | { PseudoVSUXEI32_V_M1_MF4, VSUXEI32_V, 0x6, 0x0 }, // 9439 |
15431 | | { PseudoVSUXEI32_V_M1_MF4_MASK, VSUXEI32_V, 0x6, 0x0 }, // 9440 |
15432 | | { PseudoVSUXEI32_V_MF2_MF4, VSUXEI32_V, 0x6, 0x0 }, // 9441 |
15433 | | { PseudoVSUXEI32_V_MF2_MF4_MASK, VSUXEI32_V, 0x6, 0x0 }, // 9442 |
15434 | | { PseudoVSUXEI32_V_M1_MF2, VSUXEI32_V, 0x7, 0x0 }, // 9443 |
15435 | | { PseudoVSUXEI32_V_M1_MF2_MASK, VSUXEI32_V, 0x7, 0x0 }, // 9444 |
15436 | | { PseudoVSUXEI32_V_M2_MF2, VSUXEI32_V, 0x7, 0x0 }, // 9445 |
15437 | | { PseudoVSUXEI32_V_M2_MF2_MASK, VSUXEI32_V, 0x7, 0x0 }, // 9446 |
15438 | | { PseudoVSUXEI32_V_MF2_MF2, VSUXEI32_V, 0x7, 0x0 }, // 9447 |
15439 | | { PseudoVSUXEI32_V_MF2_MF2_MASK, VSUXEI32_V, 0x7, 0x0 }, // 9448 |
15440 | | { PseudoVSUXEI64_V_M1_M1, VSUXEI64_V, 0x0, 0x0 }, // 9449 |
15441 | | { PseudoVSUXEI64_V_M1_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 9450 |
15442 | | { PseudoVSUXEI64_V_M2_M1, VSUXEI64_V, 0x0, 0x0 }, // 9451 |
15443 | | { PseudoVSUXEI64_V_M2_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 9452 |
15444 | | { PseudoVSUXEI64_V_M4_M1, VSUXEI64_V, 0x0, 0x0 }, // 9453 |
15445 | | { PseudoVSUXEI64_V_M4_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 9454 |
15446 | | { PseudoVSUXEI64_V_M8_M1, VSUXEI64_V, 0x0, 0x0 }, // 9455 |
15447 | | { PseudoVSUXEI64_V_M8_M1_MASK, VSUXEI64_V, 0x0, 0x0 }, // 9456 |
15448 | | { PseudoVSUXEI64_V_M2_M2, VSUXEI64_V, 0x1, 0x0 }, // 9457 |
15449 | | { PseudoVSUXEI64_V_M2_M2_MASK, VSUXEI64_V, 0x1, 0x0 }, // 9458 |
15450 | | { PseudoVSUXEI64_V_M4_M2, VSUXEI64_V, 0x1, 0x0 }, // 9459 |
15451 | | { PseudoVSUXEI64_V_M4_M2_MASK, VSUXEI64_V, 0x1, 0x0 }, // 9460 |
15452 | | { PseudoVSUXEI64_V_M8_M2, VSUXEI64_V, 0x1, 0x0 }, // 9461 |
15453 | | { PseudoVSUXEI64_V_M8_M2_MASK, VSUXEI64_V, 0x1, 0x0 }, // 9462 |
15454 | | { PseudoVSUXEI64_V_M4_M4, VSUXEI64_V, 0x2, 0x0 }, // 9463 |
15455 | | { PseudoVSUXEI64_V_M4_M4_MASK, VSUXEI64_V, 0x2, 0x0 }, // 9464 |
15456 | | { PseudoVSUXEI64_V_M8_M4, VSUXEI64_V, 0x2, 0x0 }, // 9465 |
15457 | | { PseudoVSUXEI64_V_M8_M4_MASK, VSUXEI64_V, 0x2, 0x0 }, // 9466 |
15458 | | { PseudoVSUXEI64_V_M8_M8, VSUXEI64_V, 0x3, 0x0 }, // 9467 |
15459 | | { PseudoVSUXEI64_V_M8_M8_MASK, VSUXEI64_V, 0x3, 0x0 }, // 9468 |
15460 | | { PseudoVSUXEI64_V_M1_MF8, VSUXEI64_V, 0x5, 0x0 }, // 9469 |
15461 | | { PseudoVSUXEI64_V_M1_MF8_MASK, VSUXEI64_V, 0x5, 0x0 }, // 9470 |
15462 | | { PseudoVSUXEI64_V_M1_MF4, VSUXEI64_V, 0x6, 0x0 }, // 9471 |
15463 | | { PseudoVSUXEI64_V_M1_MF4_MASK, VSUXEI64_V, 0x6, 0x0 }, // 9472 |
15464 | | { PseudoVSUXEI64_V_M2_MF4, VSUXEI64_V, 0x6, 0x0 }, // 9473 |
15465 | | { PseudoVSUXEI64_V_M2_MF4_MASK, VSUXEI64_V, 0x6, 0x0 }, // 9474 |
15466 | | { PseudoVSUXEI64_V_M1_MF2, VSUXEI64_V, 0x7, 0x0 }, // 9475 |
15467 | | { PseudoVSUXEI64_V_M1_MF2_MASK, VSUXEI64_V, 0x7, 0x0 }, // 9476 |
15468 | | { PseudoVSUXEI64_V_M2_MF2, VSUXEI64_V, 0x7, 0x0 }, // 9477 |
15469 | | { PseudoVSUXEI64_V_M2_MF2_MASK, VSUXEI64_V, 0x7, 0x0 }, // 9478 |
15470 | | { PseudoVSUXEI64_V_M4_MF2, VSUXEI64_V, 0x7, 0x0 }, // 9479 |
15471 | | { PseudoVSUXEI64_V_M4_MF2_MASK, VSUXEI64_V, 0x7, 0x0 }, // 9480 |
15472 | | { PseudoVSUXEI8_V_M1_M1, VSUXEI8_V, 0x0, 0x0 }, // 9481 |
15473 | | { PseudoVSUXEI8_V_M1_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 9482 |
15474 | | { PseudoVSUXEI8_V_MF2_M1, VSUXEI8_V, 0x0, 0x0 }, // 9483 |
15475 | | { PseudoVSUXEI8_V_MF2_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 9484 |
15476 | | { PseudoVSUXEI8_V_MF4_M1, VSUXEI8_V, 0x0, 0x0 }, // 9485 |
15477 | | { PseudoVSUXEI8_V_MF4_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 9486 |
15478 | | { PseudoVSUXEI8_V_MF8_M1, VSUXEI8_V, 0x0, 0x0 }, // 9487 |
15479 | | { PseudoVSUXEI8_V_MF8_M1_MASK, VSUXEI8_V, 0x0, 0x0 }, // 9488 |
15480 | | { PseudoVSUXEI8_V_M1_M2, VSUXEI8_V, 0x1, 0x0 }, // 9489 |
15481 | | { PseudoVSUXEI8_V_M1_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 9490 |
15482 | | { PseudoVSUXEI8_V_M2_M2, VSUXEI8_V, 0x1, 0x0 }, // 9491 |
15483 | | { PseudoVSUXEI8_V_M2_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 9492 |
15484 | | { PseudoVSUXEI8_V_MF2_M2, VSUXEI8_V, 0x1, 0x0 }, // 9493 |
15485 | | { PseudoVSUXEI8_V_MF2_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 9494 |
15486 | | { PseudoVSUXEI8_V_MF4_M2, VSUXEI8_V, 0x1, 0x0 }, // 9495 |
15487 | | { PseudoVSUXEI8_V_MF4_M2_MASK, VSUXEI8_V, 0x1, 0x0 }, // 9496 |
15488 | | { PseudoVSUXEI8_V_M1_M4, VSUXEI8_V, 0x2, 0x0 }, // 9497 |
15489 | | { PseudoVSUXEI8_V_M1_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 9498 |
15490 | | { PseudoVSUXEI8_V_M2_M4, VSUXEI8_V, 0x2, 0x0 }, // 9499 |
15491 | | { PseudoVSUXEI8_V_M2_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 9500 |
15492 | | { PseudoVSUXEI8_V_M4_M4, VSUXEI8_V, 0x2, 0x0 }, // 9501 |
15493 | | { PseudoVSUXEI8_V_M4_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 9502 |
15494 | | { PseudoVSUXEI8_V_MF2_M4, VSUXEI8_V, 0x2, 0x0 }, // 9503 |
15495 | | { PseudoVSUXEI8_V_MF2_M4_MASK, VSUXEI8_V, 0x2, 0x0 }, // 9504 |
15496 | | { PseudoVSUXEI8_V_M1_M8, VSUXEI8_V, 0x3, 0x0 }, // 9505 |
15497 | | { PseudoVSUXEI8_V_M1_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 9506 |
15498 | | { PseudoVSUXEI8_V_M2_M8, VSUXEI8_V, 0x3, 0x0 }, // 9507 |
15499 | | { PseudoVSUXEI8_V_M2_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 9508 |
15500 | | { PseudoVSUXEI8_V_M4_M8, VSUXEI8_V, 0x3, 0x0 }, // 9509 |
15501 | | { PseudoVSUXEI8_V_M4_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 9510 |
15502 | | { PseudoVSUXEI8_V_M8_M8, VSUXEI8_V, 0x3, 0x0 }, // 9511 |
15503 | | { PseudoVSUXEI8_V_M8_M8_MASK, VSUXEI8_V, 0x3, 0x0 }, // 9512 |
15504 | | { PseudoVSUXEI8_V_MF8_MF8, VSUXEI8_V, 0x5, 0x0 }, // 9513 |
15505 | | { PseudoVSUXEI8_V_MF8_MF8_MASK, VSUXEI8_V, 0x5, 0x0 }, // 9514 |
15506 | | { PseudoVSUXEI8_V_MF4_MF4, VSUXEI8_V, 0x6, 0x0 }, // 9515 |
15507 | | { PseudoVSUXEI8_V_MF4_MF4_MASK, VSUXEI8_V, 0x6, 0x0 }, // 9516 |
15508 | | { PseudoVSUXEI8_V_MF8_MF4, VSUXEI8_V, 0x6, 0x0 }, // 9517 |
15509 | | { PseudoVSUXEI8_V_MF8_MF4_MASK, VSUXEI8_V, 0x6, 0x0 }, // 9518 |
15510 | | { PseudoVSUXEI8_V_MF2_MF2, VSUXEI8_V, 0x7, 0x0 }, // 9519 |
15511 | | { PseudoVSUXEI8_V_MF2_MF2_MASK, VSUXEI8_V, 0x7, 0x0 }, // 9520 |
15512 | | { PseudoVSUXEI8_V_MF4_MF2, VSUXEI8_V, 0x7, 0x0 }, // 9521 |
15513 | | { PseudoVSUXEI8_V_MF4_MF2_MASK, VSUXEI8_V, 0x7, 0x0 }, // 9522 |
15514 | | { PseudoVSUXEI8_V_MF8_MF2, VSUXEI8_V, 0x7, 0x0 }, // 9523 |
15515 | | { PseudoVSUXEI8_V_MF8_MF2_MASK, VSUXEI8_V, 0x7, 0x0 }, // 9524 |
15516 | | { PseudoVSUXSEG2EI16_V_M1_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9525 |
15517 | | { PseudoVSUXSEG2EI16_V_M1_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9526 |
15518 | | { PseudoVSUXSEG2EI16_V_M2_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9527 |
15519 | | { PseudoVSUXSEG2EI16_V_M2_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9528 |
15520 | | { PseudoVSUXSEG2EI16_V_MF2_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9529 |
15521 | | { PseudoVSUXSEG2EI16_V_MF2_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9530 |
15522 | | { PseudoVSUXSEG2EI16_V_MF4_M1, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9531 |
15523 | | { PseudoVSUXSEG2EI16_V_MF4_M1_MASK, VSUXSEG2EI16_V, 0x0, 0x0 }, // 9532 |
15524 | | { PseudoVSUXSEG2EI16_V_M1_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9533 |
15525 | | { PseudoVSUXSEG2EI16_V_M1_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9534 |
15526 | | { PseudoVSUXSEG2EI16_V_M2_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9535 |
15527 | | { PseudoVSUXSEG2EI16_V_M2_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9536 |
15528 | | { PseudoVSUXSEG2EI16_V_M4_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9537 |
15529 | | { PseudoVSUXSEG2EI16_V_M4_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9538 |
15530 | | { PseudoVSUXSEG2EI16_V_MF2_M2, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9539 |
15531 | | { PseudoVSUXSEG2EI16_V_MF2_M2_MASK, VSUXSEG2EI16_V, 0x1, 0x0 }, // 9540 |
15532 | | { PseudoVSUXSEG2EI16_V_M1_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9541 |
15533 | | { PseudoVSUXSEG2EI16_V_M1_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9542 |
15534 | | { PseudoVSUXSEG2EI16_V_M2_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9543 |
15535 | | { PseudoVSUXSEG2EI16_V_M2_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9544 |
15536 | | { PseudoVSUXSEG2EI16_V_M4_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9545 |
15537 | | { PseudoVSUXSEG2EI16_V_M4_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9546 |
15538 | | { PseudoVSUXSEG2EI16_V_M8_M4, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9547 |
15539 | | { PseudoVSUXSEG2EI16_V_M8_M4_MASK, VSUXSEG2EI16_V, 0x2, 0x0 }, // 9548 |
15540 | | { PseudoVSUXSEG2EI16_V_MF4_MF8, VSUXSEG2EI16_V, 0x5, 0x0 }, // 9549 |
15541 | | { PseudoVSUXSEG2EI16_V_MF4_MF8_MASK, VSUXSEG2EI16_V, 0x5, 0x0 }, // 9550 |
15542 | | { PseudoVSUXSEG2EI16_V_MF2_MF4, VSUXSEG2EI16_V, 0x6, 0x0 }, // 9551 |
15543 | | { PseudoVSUXSEG2EI16_V_MF2_MF4_MASK, VSUXSEG2EI16_V, 0x6, 0x0 }, // 9552 |
15544 | | { PseudoVSUXSEG2EI16_V_MF4_MF4, VSUXSEG2EI16_V, 0x6, 0x0 }, // 9553 |
15545 | | { PseudoVSUXSEG2EI16_V_MF4_MF4_MASK, VSUXSEG2EI16_V, 0x6, 0x0 }, // 9554 |
15546 | | { PseudoVSUXSEG2EI16_V_M1_MF2, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9555 |
15547 | | { PseudoVSUXSEG2EI16_V_M1_MF2_MASK, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9556 |
15548 | | { PseudoVSUXSEG2EI16_V_MF2_MF2, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9557 |
15549 | | { PseudoVSUXSEG2EI16_V_MF2_MF2_MASK, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9558 |
15550 | | { PseudoVSUXSEG2EI16_V_MF4_MF2, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9559 |
15551 | | { PseudoVSUXSEG2EI16_V_MF4_MF2_MASK, VSUXSEG2EI16_V, 0x7, 0x0 }, // 9560 |
15552 | | { PseudoVSUXSEG2EI32_V_M1_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9561 |
15553 | | { PseudoVSUXSEG2EI32_V_M1_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9562 |
15554 | | { PseudoVSUXSEG2EI32_V_M2_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9563 |
15555 | | { PseudoVSUXSEG2EI32_V_M2_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9564 |
15556 | | { PseudoVSUXSEG2EI32_V_M4_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9565 |
15557 | | { PseudoVSUXSEG2EI32_V_M4_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9566 |
15558 | | { PseudoVSUXSEG2EI32_V_MF2_M1, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9567 |
15559 | | { PseudoVSUXSEG2EI32_V_MF2_M1_MASK, VSUXSEG2EI32_V, 0x0, 0x0 }, // 9568 |
15560 | | { PseudoVSUXSEG2EI32_V_M1_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9569 |
15561 | | { PseudoVSUXSEG2EI32_V_M1_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9570 |
15562 | | { PseudoVSUXSEG2EI32_V_M2_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9571 |
15563 | | { PseudoVSUXSEG2EI32_V_M2_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9572 |
15564 | | { PseudoVSUXSEG2EI32_V_M4_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9573 |
15565 | | { PseudoVSUXSEG2EI32_V_M4_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9574 |
15566 | | { PseudoVSUXSEG2EI32_V_M8_M2, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9575 |
15567 | | { PseudoVSUXSEG2EI32_V_M8_M2_MASK, VSUXSEG2EI32_V, 0x1, 0x0 }, // 9576 |
15568 | | { PseudoVSUXSEG2EI32_V_M2_M4, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9577 |
15569 | | { PseudoVSUXSEG2EI32_V_M2_M4_MASK, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9578 |
15570 | | { PseudoVSUXSEG2EI32_V_M4_M4, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9579 |
15571 | | { PseudoVSUXSEG2EI32_V_M4_M4_MASK, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9580 |
15572 | | { PseudoVSUXSEG2EI32_V_M8_M4, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9581 |
15573 | | { PseudoVSUXSEG2EI32_V_M8_M4_MASK, VSUXSEG2EI32_V, 0x2, 0x0 }, // 9582 |
15574 | | { PseudoVSUXSEG2EI32_V_MF2_MF8, VSUXSEG2EI32_V, 0x5, 0x0 }, // 9583 |
15575 | | { PseudoVSUXSEG2EI32_V_MF2_MF8_MASK, VSUXSEG2EI32_V, 0x5, 0x0 }, // 9584 |
15576 | | { PseudoVSUXSEG2EI32_V_M1_MF4, VSUXSEG2EI32_V, 0x6, 0x0 }, // 9585 |
15577 | | { PseudoVSUXSEG2EI32_V_M1_MF4_MASK, VSUXSEG2EI32_V, 0x6, 0x0 }, // 9586 |
15578 | | { PseudoVSUXSEG2EI32_V_MF2_MF4, VSUXSEG2EI32_V, 0x6, 0x0 }, // 9587 |
15579 | | { PseudoVSUXSEG2EI32_V_MF2_MF4_MASK, VSUXSEG2EI32_V, 0x6, 0x0 }, // 9588 |
15580 | | { PseudoVSUXSEG2EI32_V_M1_MF2, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9589 |
15581 | | { PseudoVSUXSEG2EI32_V_M1_MF2_MASK, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9590 |
15582 | | { PseudoVSUXSEG2EI32_V_M2_MF2, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9591 |
15583 | | { PseudoVSUXSEG2EI32_V_M2_MF2_MASK, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9592 |
15584 | | { PseudoVSUXSEG2EI32_V_MF2_MF2, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9593 |
15585 | | { PseudoVSUXSEG2EI32_V_MF2_MF2_MASK, VSUXSEG2EI32_V, 0x7, 0x0 }, // 9594 |
15586 | | { PseudoVSUXSEG2EI64_V_M1_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9595 |
15587 | | { PseudoVSUXSEG2EI64_V_M1_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9596 |
15588 | | { PseudoVSUXSEG2EI64_V_M2_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9597 |
15589 | | { PseudoVSUXSEG2EI64_V_M2_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9598 |
15590 | | { PseudoVSUXSEG2EI64_V_M4_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9599 |
15591 | | { PseudoVSUXSEG2EI64_V_M4_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9600 |
15592 | | { PseudoVSUXSEG2EI64_V_M8_M1, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9601 |
15593 | | { PseudoVSUXSEG2EI64_V_M8_M1_MASK, VSUXSEG2EI64_V, 0x0, 0x0 }, // 9602 |
15594 | | { PseudoVSUXSEG2EI64_V_M2_M2, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9603 |
15595 | | { PseudoVSUXSEG2EI64_V_M2_M2_MASK, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9604 |
15596 | | { PseudoVSUXSEG2EI64_V_M4_M2, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9605 |
15597 | | { PseudoVSUXSEG2EI64_V_M4_M2_MASK, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9606 |
15598 | | { PseudoVSUXSEG2EI64_V_M8_M2, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9607 |
15599 | | { PseudoVSUXSEG2EI64_V_M8_M2_MASK, VSUXSEG2EI64_V, 0x1, 0x0 }, // 9608 |
15600 | | { PseudoVSUXSEG2EI64_V_M4_M4, VSUXSEG2EI64_V, 0x2, 0x0 }, // 9609 |
15601 | | { PseudoVSUXSEG2EI64_V_M4_M4_MASK, VSUXSEG2EI64_V, 0x2, 0x0 }, // 9610 |
15602 | | { PseudoVSUXSEG2EI64_V_M8_M4, VSUXSEG2EI64_V, 0x2, 0x0 }, // 9611 |
15603 | | { PseudoVSUXSEG2EI64_V_M8_M4_MASK, VSUXSEG2EI64_V, 0x2, 0x0 }, // 9612 |
15604 | | { PseudoVSUXSEG2EI64_V_M1_MF8, VSUXSEG2EI64_V, 0x5, 0x0 }, // 9613 |
15605 | | { PseudoVSUXSEG2EI64_V_M1_MF8_MASK, VSUXSEG2EI64_V, 0x5, 0x0 }, // 9614 |
15606 | | { PseudoVSUXSEG2EI64_V_M1_MF4, VSUXSEG2EI64_V, 0x6, 0x0 }, // 9615 |
15607 | | { PseudoVSUXSEG2EI64_V_M1_MF4_MASK, VSUXSEG2EI64_V, 0x6, 0x0 }, // 9616 |
15608 | | { PseudoVSUXSEG2EI64_V_M2_MF4, VSUXSEG2EI64_V, 0x6, 0x0 }, // 9617 |
15609 | | { PseudoVSUXSEG2EI64_V_M2_MF4_MASK, VSUXSEG2EI64_V, 0x6, 0x0 }, // 9618 |
15610 | | { PseudoVSUXSEG2EI64_V_M1_MF2, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9619 |
15611 | | { PseudoVSUXSEG2EI64_V_M1_MF2_MASK, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9620 |
15612 | | { PseudoVSUXSEG2EI64_V_M2_MF2, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9621 |
15613 | | { PseudoVSUXSEG2EI64_V_M2_MF2_MASK, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9622 |
15614 | | { PseudoVSUXSEG2EI64_V_M4_MF2, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9623 |
15615 | | { PseudoVSUXSEG2EI64_V_M4_MF2_MASK, VSUXSEG2EI64_V, 0x7, 0x0 }, // 9624 |
15616 | | { PseudoVSUXSEG2EI8_V_M1_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9625 |
15617 | | { PseudoVSUXSEG2EI8_V_M1_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9626 |
15618 | | { PseudoVSUXSEG2EI8_V_MF2_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9627 |
15619 | | { PseudoVSUXSEG2EI8_V_MF2_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9628 |
15620 | | { PseudoVSUXSEG2EI8_V_MF4_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9629 |
15621 | | { PseudoVSUXSEG2EI8_V_MF4_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9630 |
15622 | | { PseudoVSUXSEG2EI8_V_MF8_M1, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9631 |
15623 | | { PseudoVSUXSEG2EI8_V_MF8_M1_MASK, VSUXSEG2EI8_V, 0x0, 0x0 }, // 9632 |
15624 | | { PseudoVSUXSEG2EI8_V_M1_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9633 |
15625 | | { PseudoVSUXSEG2EI8_V_M1_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9634 |
15626 | | { PseudoVSUXSEG2EI8_V_M2_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9635 |
15627 | | { PseudoVSUXSEG2EI8_V_M2_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9636 |
15628 | | { PseudoVSUXSEG2EI8_V_MF2_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9637 |
15629 | | { PseudoVSUXSEG2EI8_V_MF2_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9638 |
15630 | | { PseudoVSUXSEG2EI8_V_MF4_M2, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9639 |
15631 | | { PseudoVSUXSEG2EI8_V_MF4_M2_MASK, VSUXSEG2EI8_V, 0x1, 0x0 }, // 9640 |
15632 | | { PseudoVSUXSEG2EI8_V_M1_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9641 |
15633 | | { PseudoVSUXSEG2EI8_V_M1_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9642 |
15634 | | { PseudoVSUXSEG2EI8_V_M2_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9643 |
15635 | | { PseudoVSUXSEG2EI8_V_M2_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9644 |
15636 | | { PseudoVSUXSEG2EI8_V_M4_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9645 |
15637 | | { PseudoVSUXSEG2EI8_V_M4_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9646 |
15638 | | { PseudoVSUXSEG2EI8_V_MF2_M4, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9647 |
15639 | | { PseudoVSUXSEG2EI8_V_MF2_M4_MASK, VSUXSEG2EI8_V, 0x2, 0x0 }, // 9648 |
15640 | | { PseudoVSUXSEG2EI8_V_MF8_MF8, VSUXSEG2EI8_V, 0x5, 0x0 }, // 9649 |
15641 | | { PseudoVSUXSEG2EI8_V_MF8_MF8_MASK, VSUXSEG2EI8_V, 0x5, 0x0 }, // 9650 |
15642 | | { PseudoVSUXSEG2EI8_V_MF4_MF4, VSUXSEG2EI8_V, 0x6, 0x0 }, // 9651 |
15643 | | { PseudoVSUXSEG2EI8_V_MF4_MF4_MASK, VSUXSEG2EI8_V, 0x6, 0x0 }, // 9652 |
15644 | | { PseudoVSUXSEG2EI8_V_MF8_MF4, VSUXSEG2EI8_V, 0x6, 0x0 }, // 9653 |
15645 | | { PseudoVSUXSEG2EI8_V_MF8_MF4_MASK, VSUXSEG2EI8_V, 0x6, 0x0 }, // 9654 |
15646 | | { PseudoVSUXSEG2EI8_V_MF2_MF2, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9655 |
15647 | | { PseudoVSUXSEG2EI8_V_MF2_MF2_MASK, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9656 |
15648 | | { PseudoVSUXSEG2EI8_V_MF4_MF2, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9657 |
15649 | | { PseudoVSUXSEG2EI8_V_MF4_MF2_MASK, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9658 |
15650 | | { PseudoVSUXSEG2EI8_V_MF8_MF2, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9659 |
15651 | | { PseudoVSUXSEG2EI8_V_MF8_MF2_MASK, VSUXSEG2EI8_V, 0x7, 0x0 }, // 9660 |
15652 | | { PseudoVSUXSEG3EI16_V_M1_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9661 |
15653 | | { PseudoVSUXSEG3EI16_V_M1_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9662 |
15654 | | { PseudoVSUXSEG3EI16_V_M2_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9663 |
15655 | | { PseudoVSUXSEG3EI16_V_M2_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9664 |
15656 | | { PseudoVSUXSEG3EI16_V_MF2_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9665 |
15657 | | { PseudoVSUXSEG3EI16_V_MF2_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9666 |
15658 | | { PseudoVSUXSEG3EI16_V_MF4_M1, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9667 |
15659 | | { PseudoVSUXSEG3EI16_V_MF4_M1_MASK, VSUXSEG3EI16_V, 0x0, 0x0 }, // 9668 |
15660 | | { PseudoVSUXSEG3EI16_V_M1_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9669 |
15661 | | { PseudoVSUXSEG3EI16_V_M1_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9670 |
15662 | | { PseudoVSUXSEG3EI16_V_M2_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9671 |
15663 | | { PseudoVSUXSEG3EI16_V_M2_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9672 |
15664 | | { PseudoVSUXSEG3EI16_V_M4_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9673 |
15665 | | { PseudoVSUXSEG3EI16_V_M4_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9674 |
15666 | | { PseudoVSUXSEG3EI16_V_MF2_M2, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9675 |
15667 | | { PseudoVSUXSEG3EI16_V_MF2_M2_MASK, VSUXSEG3EI16_V, 0x1, 0x0 }, // 9676 |
15668 | | { PseudoVSUXSEG3EI16_V_MF4_MF8, VSUXSEG3EI16_V, 0x5, 0x0 }, // 9677 |
15669 | | { PseudoVSUXSEG3EI16_V_MF4_MF8_MASK, VSUXSEG3EI16_V, 0x5, 0x0 }, // 9678 |
15670 | | { PseudoVSUXSEG3EI16_V_MF2_MF4, VSUXSEG3EI16_V, 0x6, 0x0 }, // 9679 |
15671 | | { PseudoVSUXSEG3EI16_V_MF2_MF4_MASK, VSUXSEG3EI16_V, 0x6, 0x0 }, // 9680 |
15672 | | { PseudoVSUXSEG3EI16_V_MF4_MF4, VSUXSEG3EI16_V, 0x6, 0x0 }, // 9681 |
15673 | | { PseudoVSUXSEG3EI16_V_MF4_MF4_MASK, VSUXSEG3EI16_V, 0x6, 0x0 }, // 9682 |
15674 | | { PseudoVSUXSEG3EI16_V_M1_MF2, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9683 |
15675 | | { PseudoVSUXSEG3EI16_V_M1_MF2_MASK, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9684 |
15676 | | { PseudoVSUXSEG3EI16_V_MF2_MF2, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9685 |
15677 | | { PseudoVSUXSEG3EI16_V_MF2_MF2_MASK, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9686 |
15678 | | { PseudoVSUXSEG3EI16_V_MF4_MF2, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9687 |
15679 | | { PseudoVSUXSEG3EI16_V_MF4_MF2_MASK, VSUXSEG3EI16_V, 0x7, 0x0 }, // 9688 |
15680 | | { PseudoVSUXSEG3EI32_V_M1_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9689 |
15681 | | { PseudoVSUXSEG3EI32_V_M1_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9690 |
15682 | | { PseudoVSUXSEG3EI32_V_M2_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9691 |
15683 | | { PseudoVSUXSEG3EI32_V_M2_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9692 |
15684 | | { PseudoVSUXSEG3EI32_V_M4_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9693 |
15685 | | { PseudoVSUXSEG3EI32_V_M4_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9694 |
15686 | | { PseudoVSUXSEG3EI32_V_MF2_M1, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9695 |
15687 | | { PseudoVSUXSEG3EI32_V_MF2_M1_MASK, VSUXSEG3EI32_V, 0x0, 0x0 }, // 9696 |
15688 | | { PseudoVSUXSEG3EI32_V_M1_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9697 |
15689 | | { PseudoVSUXSEG3EI32_V_M1_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9698 |
15690 | | { PseudoVSUXSEG3EI32_V_M2_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9699 |
15691 | | { PseudoVSUXSEG3EI32_V_M2_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9700 |
15692 | | { PseudoVSUXSEG3EI32_V_M4_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9701 |
15693 | | { PseudoVSUXSEG3EI32_V_M4_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9702 |
15694 | | { PseudoVSUXSEG3EI32_V_M8_M2, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9703 |
15695 | | { PseudoVSUXSEG3EI32_V_M8_M2_MASK, VSUXSEG3EI32_V, 0x1, 0x0 }, // 9704 |
15696 | | { PseudoVSUXSEG3EI32_V_MF2_MF8, VSUXSEG3EI32_V, 0x5, 0x0 }, // 9705 |
15697 | | { PseudoVSUXSEG3EI32_V_MF2_MF8_MASK, VSUXSEG3EI32_V, 0x5, 0x0 }, // 9706 |
15698 | | { PseudoVSUXSEG3EI32_V_M1_MF4, VSUXSEG3EI32_V, 0x6, 0x0 }, // 9707 |
15699 | | { PseudoVSUXSEG3EI32_V_M1_MF4_MASK, VSUXSEG3EI32_V, 0x6, 0x0 }, // 9708 |
15700 | | { PseudoVSUXSEG3EI32_V_MF2_MF4, VSUXSEG3EI32_V, 0x6, 0x0 }, // 9709 |
15701 | | { PseudoVSUXSEG3EI32_V_MF2_MF4_MASK, VSUXSEG3EI32_V, 0x6, 0x0 }, // 9710 |
15702 | | { PseudoVSUXSEG3EI32_V_M1_MF2, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9711 |
15703 | | { PseudoVSUXSEG3EI32_V_M1_MF2_MASK, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9712 |
15704 | | { PseudoVSUXSEG3EI32_V_M2_MF2, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9713 |
15705 | | { PseudoVSUXSEG3EI32_V_M2_MF2_MASK, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9714 |
15706 | | { PseudoVSUXSEG3EI32_V_MF2_MF2, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9715 |
15707 | | { PseudoVSUXSEG3EI32_V_MF2_MF2_MASK, VSUXSEG3EI32_V, 0x7, 0x0 }, // 9716 |
15708 | | { PseudoVSUXSEG3EI64_V_M1_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9717 |
15709 | | { PseudoVSUXSEG3EI64_V_M1_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9718 |
15710 | | { PseudoVSUXSEG3EI64_V_M2_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9719 |
15711 | | { PseudoVSUXSEG3EI64_V_M2_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9720 |
15712 | | { PseudoVSUXSEG3EI64_V_M4_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9721 |
15713 | | { PseudoVSUXSEG3EI64_V_M4_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9722 |
15714 | | { PseudoVSUXSEG3EI64_V_M8_M1, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9723 |
15715 | | { PseudoVSUXSEG3EI64_V_M8_M1_MASK, VSUXSEG3EI64_V, 0x0, 0x0 }, // 9724 |
15716 | | { PseudoVSUXSEG3EI64_V_M2_M2, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9725 |
15717 | | { PseudoVSUXSEG3EI64_V_M2_M2_MASK, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9726 |
15718 | | { PseudoVSUXSEG3EI64_V_M4_M2, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9727 |
15719 | | { PseudoVSUXSEG3EI64_V_M4_M2_MASK, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9728 |
15720 | | { PseudoVSUXSEG3EI64_V_M8_M2, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9729 |
15721 | | { PseudoVSUXSEG3EI64_V_M8_M2_MASK, VSUXSEG3EI64_V, 0x1, 0x0 }, // 9730 |
15722 | | { PseudoVSUXSEG3EI64_V_M1_MF8, VSUXSEG3EI64_V, 0x5, 0x0 }, // 9731 |
15723 | | { PseudoVSUXSEG3EI64_V_M1_MF8_MASK, VSUXSEG3EI64_V, 0x5, 0x0 }, // 9732 |
15724 | | { PseudoVSUXSEG3EI64_V_M1_MF4, VSUXSEG3EI64_V, 0x6, 0x0 }, // 9733 |
15725 | | { PseudoVSUXSEG3EI64_V_M1_MF4_MASK, VSUXSEG3EI64_V, 0x6, 0x0 }, // 9734 |
15726 | | { PseudoVSUXSEG3EI64_V_M2_MF4, VSUXSEG3EI64_V, 0x6, 0x0 }, // 9735 |
15727 | | { PseudoVSUXSEG3EI64_V_M2_MF4_MASK, VSUXSEG3EI64_V, 0x6, 0x0 }, // 9736 |
15728 | | { PseudoVSUXSEG3EI64_V_M1_MF2, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9737 |
15729 | | { PseudoVSUXSEG3EI64_V_M1_MF2_MASK, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9738 |
15730 | | { PseudoVSUXSEG3EI64_V_M2_MF2, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9739 |
15731 | | { PseudoVSUXSEG3EI64_V_M2_MF2_MASK, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9740 |
15732 | | { PseudoVSUXSEG3EI64_V_M4_MF2, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9741 |
15733 | | { PseudoVSUXSEG3EI64_V_M4_MF2_MASK, VSUXSEG3EI64_V, 0x7, 0x0 }, // 9742 |
15734 | | { PseudoVSUXSEG3EI8_V_M1_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9743 |
15735 | | { PseudoVSUXSEG3EI8_V_M1_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9744 |
15736 | | { PseudoVSUXSEG3EI8_V_MF2_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9745 |
15737 | | { PseudoVSUXSEG3EI8_V_MF2_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9746 |
15738 | | { PseudoVSUXSEG3EI8_V_MF4_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9747 |
15739 | | { PseudoVSUXSEG3EI8_V_MF4_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9748 |
15740 | | { PseudoVSUXSEG3EI8_V_MF8_M1, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9749 |
15741 | | { PseudoVSUXSEG3EI8_V_MF8_M1_MASK, VSUXSEG3EI8_V, 0x0, 0x0 }, // 9750 |
15742 | | { PseudoVSUXSEG3EI8_V_M1_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9751 |
15743 | | { PseudoVSUXSEG3EI8_V_M1_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9752 |
15744 | | { PseudoVSUXSEG3EI8_V_M2_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9753 |
15745 | | { PseudoVSUXSEG3EI8_V_M2_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9754 |
15746 | | { PseudoVSUXSEG3EI8_V_MF2_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9755 |
15747 | | { PseudoVSUXSEG3EI8_V_MF2_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9756 |
15748 | | { PseudoVSUXSEG3EI8_V_MF4_M2, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9757 |
15749 | | { PseudoVSUXSEG3EI8_V_MF4_M2_MASK, VSUXSEG3EI8_V, 0x1, 0x0 }, // 9758 |
15750 | | { PseudoVSUXSEG3EI8_V_MF8_MF8, VSUXSEG3EI8_V, 0x5, 0x0 }, // 9759 |
15751 | | { PseudoVSUXSEG3EI8_V_MF8_MF8_MASK, VSUXSEG3EI8_V, 0x5, 0x0 }, // 9760 |
15752 | | { PseudoVSUXSEG3EI8_V_MF4_MF4, VSUXSEG3EI8_V, 0x6, 0x0 }, // 9761 |
15753 | | { PseudoVSUXSEG3EI8_V_MF4_MF4_MASK, VSUXSEG3EI8_V, 0x6, 0x0 }, // 9762 |
15754 | | { PseudoVSUXSEG3EI8_V_MF8_MF4, VSUXSEG3EI8_V, 0x6, 0x0 }, // 9763 |
15755 | | { PseudoVSUXSEG3EI8_V_MF8_MF4_MASK, VSUXSEG3EI8_V, 0x6, 0x0 }, // 9764 |
15756 | | { PseudoVSUXSEG3EI8_V_MF2_MF2, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9765 |
15757 | | { PseudoVSUXSEG3EI8_V_MF2_MF2_MASK, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9766 |
15758 | | { PseudoVSUXSEG3EI8_V_MF4_MF2, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9767 |
15759 | | { PseudoVSUXSEG3EI8_V_MF4_MF2_MASK, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9768 |
15760 | | { PseudoVSUXSEG3EI8_V_MF8_MF2, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9769 |
15761 | | { PseudoVSUXSEG3EI8_V_MF8_MF2_MASK, VSUXSEG3EI8_V, 0x7, 0x0 }, // 9770 |
15762 | | { PseudoVSUXSEG4EI16_V_M1_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9771 |
15763 | | { PseudoVSUXSEG4EI16_V_M1_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9772 |
15764 | | { PseudoVSUXSEG4EI16_V_M2_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9773 |
15765 | | { PseudoVSUXSEG4EI16_V_M2_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9774 |
15766 | | { PseudoVSUXSEG4EI16_V_MF2_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9775 |
15767 | | { PseudoVSUXSEG4EI16_V_MF2_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9776 |
15768 | | { PseudoVSUXSEG4EI16_V_MF4_M1, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9777 |
15769 | | { PseudoVSUXSEG4EI16_V_MF4_M1_MASK, VSUXSEG4EI16_V, 0x0, 0x0 }, // 9778 |
15770 | | { PseudoVSUXSEG4EI16_V_M1_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9779 |
15771 | | { PseudoVSUXSEG4EI16_V_M1_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9780 |
15772 | | { PseudoVSUXSEG4EI16_V_M2_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9781 |
15773 | | { PseudoVSUXSEG4EI16_V_M2_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9782 |
15774 | | { PseudoVSUXSEG4EI16_V_M4_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9783 |
15775 | | { PseudoVSUXSEG4EI16_V_M4_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9784 |
15776 | | { PseudoVSUXSEG4EI16_V_MF2_M2, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9785 |
15777 | | { PseudoVSUXSEG4EI16_V_MF2_M2_MASK, VSUXSEG4EI16_V, 0x1, 0x0 }, // 9786 |
15778 | | { PseudoVSUXSEG4EI16_V_MF4_MF8, VSUXSEG4EI16_V, 0x5, 0x0 }, // 9787 |
15779 | | { PseudoVSUXSEG4EI16_V_MF4_MF8_MASK, VSUXSEG4EI16_V, 0x5, 0x0 }, // 9788 |
15780 | | { PseudoVSUXSEG4EI16_V_MF2_MF4, VSUXSEG4EI16_V, 0x6, 0x0 }, // 9789 |
15781 | | { PseudoVSUXSEG4EI16_V_MF2_MF4_MASK, VSUXSEG4EI16_V, 0x6, 0x0 }, // 9790 |
15782 | | { PseudoVSUXSEG4EI16_V_MF4_MF4, VSUXSEG4EI16_V, 0x6, 0x0 }, // 9791 |
15783 | | { PseudoVSUXSEG4EI16_V_MF4_MF4_MASK, VSUXSEG4EI16_V, 0x6, 0x0 }, // 9792 |
15784 | | { PseudoVSUXSEG4EI16_V_M1_MF2, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9793 |
15785 | | { PseudoVSUXSEG4EI16_V_M1_MF2_MASK, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9794 |
15786 | | { PseudoVSUXSEG4EI16_V_MF2_MF2, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9795 |
15787 | | { PseudoVSUXSEG4EI16_V_MF2_MF2_MASK, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9796 |
15788 | | { PseudoVSUXSEG4EI16_V_MF4_MF2, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9797 |
15789 | | { PseudoVSUXSEG4EI16_V_MF4_MF2_MASK, VSUXSEG4EI16_V, 0x7, 0x0 }, // 9798 |
15790 | | { PseudoVSUXSEG4EI32_V_M1_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9799 |
15791 | | { PseudoVSUXSEG4EI32_V_M1_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9800 |
15792 | | { PseudoVSUXSEG4EI32_V_M2_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9801 |
15793 | | { PseudoVSUXSEG4EI32_V_M2_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9802 |
15794 | | { PseudoVSUXSEG4EI32_V_M4_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9803 |
15795 | | { PseudoVSUXSEG4EI32_V_M4_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9804 |
15796 | | { PseudoVSUXSEG4EI32_V_MF2_M1, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9805 |
15797 | | { PseudoVSUXSEG4EI32_V_MF2_M1_MASK, VSUXSEG4EI32_V, 0x0, 0x0 }, // 9806 |
15798 | | { PseudoVSUXSEG4EI32_V_M1_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9807 |
15799 | | { PseudoVSUXSEG4EI32_V_M1_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9808 |
15800 | | { PseudoVSUXSEG4EI32_V_M2_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9809 |
15801 | | { PseudoVSUXSEG4EI32_V_M2_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9810 |
15802 | | { PseudoVSUXSEG4EI32_V_M4_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9811 |
15803 | | { PseudoVSUXSEG4EI32_V_M4_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9812 |
15804 | | { PseudoVSUXSEG4EI32_V_M8_M2, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9813 |
15805 | | { PseudoVSUXSEG4EI32_V_M8_M2_MASK, VSUXSEG4EI32_V, 0x1, 0x0 }, // 9814 |
15806 | | { PseudoVSUXSEG4EI32_V_MF2_MF8, VSUXSEG4EI32_V, 0x5, 0x0 }, // 9815 |
15807 | | { PseudoVSUXSEG4EI32_V_MF2_MF8_MASK, VSUXSEG4EI32_V, 0x5, 0x0 }, // 9816 |
15808 | | { PseudoVSUXSEG4EI32_V_M1_MF4, VSUXSEG4EI32_V, 0x6, 0x0 }, // 9817 |
15809 | | { PseudoVSUXSEG4EI32_V_M1_MF4_MASK, VSUXSEG4EI32_V, 0x6, 0x0 }, // 9818 |
15810 | | { PseudoVSUXSEG4EI32_V_MF2_MF4, VSUXSEG4EI32_V, 0x6, 0x0 }, // 9819 |
15811 | | { PseudoVSUXSEG4EI32_V_MF2_MF4_MASK, VSUXSEG4EI32_V, 0x6, 0x0 }, // 9820 |
15812 | | { PseudoVSUXSEG4EI32_V_M1_MF2, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9821 |
15813 | | { PseudoVSUXSEG4EI32_V_M1_MF2_MASK, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9822 |
15814 | | { PseudoVSUXSEG4EI32_V_M2_MF2, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9823 |
15815 | | { PseudoVSUXSEG4EI32_V_M2_MF2_MASK, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9824 |
15816 | | { PseudoVSUXSEG4EI32_V_MF2_MF2, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9825 |
15817 | | { PseudoVSUXSEG4EI32_V_MF2_MF2_MASK, VSUXSEG4EI32_V, 0x7, 0x0 }, // 9826 |
15818 | | { PseudoVSUXSEG4EI64_V_M1_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9827 |
15819 | | { PseudoVSUXSEG4EI64_V_M1_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9828 |
15820 | | { PseudoVSUXSEG4EI64_V_M2_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9829 |
15821 | | { PseudoVSUXSEG4EI64_V_M2_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9830 |
15822 | | { PseudoVSUXSEG4EI64_V_M4_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9831 |
15823 | | { PseudoVSUXSEG4EI64_V_M4_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9832 |
15824 | | { PseudoVSUXSEG4EI64_V_M8_M1, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9833 |
15825 | | { PseudoVSUXSEG4EI64_V_M8_M1_MASK, VSUXSEG4EI64_V, 0x0, 0x0 }, // 9834 |
15826 | | { PseudoVSUXSEG4EI64_V_M2_M2, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9835 |
15827 | | { PseudoVSUXSEG4EI64_V_M2_M2_MASK, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9836 |
15828 | | { PseudoVSUXSEG4EI64_V_M4_M2, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9837 |
15829 | | { PseudoVSUXSEG4EI64_V_M4_M2_MASK, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9838 |
15830 | | { PseudoVSUXSEG4EI64_V_M8_M2, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9839 |
15831 | | { PseudoVSUXSEG4EI64_V_M8_M2_MASK, VSUXSEG4EI64_V, 0x1, 0x0 }, // 9840 |
15832 | | { PseudoVSUXSEG4EI64_V_M1_MF8, VSUXSEG4EI64_V, 0x5, 0x0 }, // 9841 |
15833 | | { PseudoVSUXSEG4EI64_V_M1_MF8_MASK, VSUXSEG4EI64_V, 0x5, 0x0 }, // 9842 |
15834 | | { PseudoVSUXSEG4EI64_V_M1_MF4, VSUXSEG4EI64_V, 0x6, 0x0 }, // 9843 |
15835 | | { PseudoVSUXSEG4EI64_V_M1_MF4_MASK, VSUXSEG4EI64_V, 0x6, 0x0 }, // 9844 |
15836 | | { PseudoVSUXSEG4EI64_V_M2_MF4, VSUXSEG4EI64_V, 0x6, 0x0 }, // 9845 |
15837 | | { PseudoVSUXSEG4EI64_V_M2_MF4_MASK, VSUXSEG4EI64_V, 0x6, 0x0 }, // 9846 |
15838 | | { PseudoVSUXSEG4EI64_V_M1_MF2, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9847 |
15839 | | { PseudoVSUXSEG4EI64_V_M1_MF2_MASK, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9848 |
15840 | | { PseudoVSUXSEG4EI64_V_M2_MF2, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9849 |
15841 | | { PseudoVSUXSEG4EI64_V_M2_MF2_MASK, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9850 |
15842 | | { PseudoVSUXSEG4EI64_V_M4_MF2, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9851 |
15843 | | { PseudoVSUXSEG4EI64_V_M4_MF2_MASK, VSUXSEG4EI64_V, 0x7, 0x0 }, // 9852 |
15844 | | { PseudoVSUXSEG4EI8_V_M1_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9853 |
15845 | | { PseudoVSUXSEG4EI8_V_M1_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9854 |
15846 | | { PseudoVSUXSEG4EI8_V_MF2_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9855 |
15847 | | { PseudoVSUXSEG4EI8_V_MF2_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9856 |
15848 | | { PseudoVSUXSEG4EI8_V_MF4_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9857 |
15849 | | { PseudoVSUXSEG4EI8_V_MF4_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9858 |
15850 | | { PseudoVSUXSEG4EI8_V_MF8_M1, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9859 |
15851 | | { PseudoVSUXSEG4EI8_V_MF8_M1_MASK, VSUXSEG4EI8_V, 0x0, 0x0 }, // 9860 |
15852 | | { PseudoVSUXSEG4EI8_V_M1_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9861 |
15853 | | { PseudoVSUXSEG4EI8_V_M1_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9862 |
15854 | | { PseudoVSUXSEG4EI8_V_M2_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9863 |
15855 | | { PseudoVSUXSEG4EI8_V_M2_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9864 |
15856 | | { PseudoVSUXSEG4EI8_V_MF2_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9865 |
15857 | | { PseudoVSUXSEG4EI8_V_MF2_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9866 |
15858 | | { PseudoVSUXSEG4EI8_V_MF4_M2, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9867 |
15859 | | { PseudoVSUXSEG4EI8_V_MF4_M2_MASK, VSUXSEG4EI8_V, 0x1, 0x0 }, // 9868 |
15860 | | { PseudoVSUXSEG4EI8_V_MF8_MF8, VSUXSEG4EI8_V, 0x5, 0x0 }, // 9869 |
15861 | | { PseudoVSUXSEG4EI8_V_MF8_MF8_MASK, VSUXSEG4EI8_V, 0x5, 0x0 }, // 9870 |
15862 | | { PseudoVSUXSEG4EI8_V_MF4_MF4, VSUXSEG4EI8_V, 0x6, 0x0 }, // 9871 |
15863 | | { PseudoVSUXSEG4EI8_V_MF4_MF4_MASK, VSUXSEG4EI8_V, 0x6, 0x0 }, // 9872 |
15864 | | { PseudoVSUXSEG4EI8_V_MF8_MF4, VSUXSEG4EI8_V, 0x6, 0x0 }, // 9873 |
15865 | | { PseudoVSUXSEG4EI8_V_MF8_MF4_MASK, VSUXSEG4EI8_V, 0x6, 0x0 }, // 9874 |
15866 | | { PseudoVSUXSEG4EI8_V_MF2_MF2, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9875 |
15867 | | { PseudoVSUXSEG4EI8_V_MF2_MF2_MASK, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9876 |
15868 | | { PseudoVSUXSEG4EI8_V_MF4_MF2, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9877 |
15869 | | { PseudoVSUXSEG4EI8_V_MF4_MF2_MASK, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9878 |
15870 | | { PseudoVSUXSEG4EI8_V_MF8_MF2, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9879 |
15871 | | { PseudoVSUXSEG4EI8_V_MF8_MF2_MASK, VSUXSEG4EI8_V, 0x7, 0x0 }, // 9880 |
15872 | | { PseudoVSUXSEG5EI16_V_M1_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9881 |
15873 | | { PseudoVSUXSEG5EI16_V_M1_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9882 |
15874 | | { PseudoVSUXSEG5EI16_V_M2_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9883 |
15875 | | { PseudoVSUXSEG5EI16_V_M2_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9884 |
15876 | | { PseudoVSUXSEG5EI16_V_MF2_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9885 |
15877 | | { PseudoVSUXSEG5EI16_V_MF2_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9886 |
15878 | | { PseudoVSUXSEG5EI16_V_MF4_M1, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9887 |
15879 | | { PseudoVSUXSEG5EI16_V_MF4_M1_MASK, VSUXSEG5EI16_V, 0x0, 0x0 }, // 9888 |
15880 | | { PseudoVSUXSEG5EI16_V_MF4_MF8, VSUXSEG5EI16_V, 0x5, 0x0 }, // 9889 |
15881 | | { PseudoVSUXSEG5EI16_V_MF4_MF8_MASK, VSUXSEG5EI16_V, 0x5, 0x0 }, // 9890 |
15882 | | { PseudoVSUXSEG5EI16_V_MF2_MF4, VSUXSEG5EI16_V, 0x6, 0x0 }, // 9891 |
15883 | | { PseudoVSUXSEG5EI16_V_MF2_MF4_MASK, VSUXSEG5EI16_V, 0x6, 0x0 }, // 9892 |
15884 | | { PseudoVSUXSEG5EI16_V_MF4_MF4, VSUXSEG5EI16_V, 0x6, 0x0 }, // 9893 |
15885 | | { PseudoVSUXSEG5EI16_V_MF4_MF4_MASK, VSUXSEG5EI16_V, 0x6, 0x0 }, // 9894 |
15886 | | { PseudoVSUXSEG5EI16_V_M1_MF2, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9895 |
15887 | | { PseudoVSUXSEG5EI16_V_M1_MF2_MASK, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9896 |
15888 | | { PseudoVSUXSEG5EI16_V_MF2_MF2, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9897 |
15889 | | { PseudoVSUXSEG5EI16_V_MF2_MF2_MASK, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9898 |
15890 | | { PseudoVSUXSEG5EI16_V_MF4_MF2, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9899 |
15891 | | { PseudoVSUXSEG5EI16_V_MF4_MF2_MASK, VSUXSEG5EI16_V, 0x7, 0x0 }, // 9900 |
15892 | | { PseudoVSUXSEG5EI32_V_M1_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9901 |
15893 | | { PseudoVSUXSEG5EI32_V_M1_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9902 |
15894 | | { PseudoVSUXSEG5EI32_V_M2_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9903 |
15895 | | { PseudoVSUXSEG5EI32_V_M2_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9904 |
15896 | | { PseudoVSUXSEG5EI32_V_M4_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9905 |
15897 | | { PseudoVSUXSEG5EI32_V_M4_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9906 |
15898 | | { PseudoVSUXSEG5EI32_V_MF2_M1, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9907 |
15899 | | { PseudoVSUXSEG5EI32_V_MF2_M1_MASK, VSUXSEG5EI32_V, 0x0, 0x0 }, // 9908 |
15900 | | { PseudoVSUXSEG5EI32_V_MF2_MF8, VSUXSEG5EI32_V, 0x5, 0x0 }, // 9909 |
15901 | | { PseudoVSUXSEG5EI32_V_MF2_MF8_MASK, VSUXSEG5EI32_V, 0x5, 0x0 }, // 9910 |
15902 | | { PseudoVSUXSEG5EI32_V_M1_MF4, VSUXSEG5EI32_V, 0x6, 0x0 }, // 9911 |
15903 | | { PseudoVSUXSEG5EI32_V_M1_MF4_MASK, VSUXSEG5EI32_V, 0x6, 0x0 }, // 9912 |
15904 | | { PseudoVSUXSEG5EI32_V_MF2_MF4, VSUXSEG5EI32_V, 0x6, 0x0 }, // 9913 |
15905 | | { PseudoVSUXSEG5EI32_V_MF2_MF4_MASK, VSUXSEG5EI32_V, 0x6, 0x0 }, // 9914 |
15906 | | { PseudoVSUXSEG5EI32_V_M1_MF2, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9915 |
15907 | | { PseudoVSUXSEG5EI32_V_M1_MF2_MASK, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9916 |
15908 | | { PseudoVSUXSEG5EI32_V_M2_MF2, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9917 |
15909 | | { PseudoVSUXSEG5EI32_V_M2_MF2_MASK, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9918 |
15910 | | { PseudoVSUXSEG5EI32_V_MF2_MF2, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9919 |
15911 | | { PseudoVSUXSEG5EI32_V_MF2_MF2_MASK, VSUXSEG5EI32_V, 0x7, 0x0 }, // 9920 |
15912 | | { PseudoVSUXSEG5EI64_V_M1_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9921 |
15913 | | { PseudoVSUXSEG5EI64_V_M1_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9922 |
15914 | | { PseudoVSUXSEG5EI64_V_M2_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9923 |
15915 | | { PseudoVSUXSEG5EI64_V_M2_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9924 |
15916 | | { PseudoVSUXSEG5EI64_V_M4_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9925 |
15917 | | { PseudoVSUXSEG5EI64_V_M4_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9926 |
15918 | | { PseudoVSUXSEG5EI64_V_M8_M1, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9927 |
15919 | | { PseudoVSUXSEG5EI64_V_M8_M1_MASK, VSUXSEG5EI64_V, 0x0, 0x0 }, // 9928 |
15920 | | { PseudoVSUXSEG5EI64_V_M1_MF8, VSUXSEG5EI64_V, 0x5, 0x0 }, // 9929 |
15921 | | { PseudoVSUXSEG5EI64_V_M1_MF8_MASK, VSUXSEG5EI64_V, 0x5, 0x0 }, // 9930 |
15922 | | { PseudoVSUXSEG5EI64_V_M1_MF4, VSUXSEG5EI64_V, 0x6, 0x0 }, // 9931 |
15923 | | { PseudoVSUXSEG5EI64_V_M1_MF4_MASK, VSUXSEG5EI64_V, 0x6, 0x0 }, // 9932 |
15924 | | { PseudoVSUXSEG5EI64_V_M2_MF4, VSUXSEG5EI64_V, 0x6, 0x0 }, // 9933 |
15925 | | { PseudoVSUXSEG5EI64_V_M2_MF4_MASK, VSUXSEG5EI64_V, 0x6, 0x0 }, // 9934 |
15926 | | { PseudoVSUXSEG5EI64_V_M1_MF2, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9935 |
15927 | | { PseudoVSUXSEG5EI64_V_M1_MF2_MASK, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9936 |
15928 | | { PseudoVSUXSEG5EI64_V_M2_MF2, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9937 |
15929 | | { PseudoVSUXSEG5EI64_V_M2_MF2_MASK, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9938 |
15930 | | { PseudoVSUXSEG5EI64_V_M4_MF2, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9939 |
15931 | | { PseudoVSUXSEG5EI64_V_M4_MF2_MASK, VSUXSEG5EI64_V, 0x7, 0x0 }, // 9940 |
15932 | | { PseudoVSUXSEG5EI8_V_M1_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9941 |
15933 | | { PseudoVSUXSEG5EI8_V_M1_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9942 |
15934 | | { PseudoVSUXSEG5EI8_V_MF2_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9943 |
15935 | | { PseudoVSUXSEG5EI8_V_MF2_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9944 |
15936 | | { PseudoVSUXSEG5EI8_V_MF4_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9945 |
15937 | | { PseudoVSUXSEG5EI8_V_MF4_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9946 |
15938 | | { PseudoVSUXSEG5EI8_V_MF8_M1, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9947 |
15939 | | { PseudoVSUXSEG5EI8_V_MF8_M1_MASK, VSUXSEG5EI8_V, 0x0, 0x0 }, // 9948 |
15940 | | { PseudoVSUXSEG5EI8_V_MF8_MF8, VSUXSEG5EI8_V, 0x5, 0x0 }, // 9949 |
15941 | | { PseudoVSUXSEG5EI8_V_MF8_MF8_MASK, VSUXSEG5EI8_V, 0x5, 0x0 }, // 9950 |
15942 | | { PseudoVSUXSEG5EI8_V_MF4_MF4, VSUXSEG5EI8_V, 0x6, 0x0 }, // 9951 |
15943 | | { PseudoVSUXSEG5EI8_V_MF4_MF4_MASK, VSUXSEG5EI8_V, 0x6, 0x0 }, // 9952 |
15944 | | { PseudoVSUXSEG5EI8_V_MF8_MF4, VSUXSEG5EI8_V, 0x6, 0x0 }, // 9953 |
15945 | | { PseudoVSUXSEG5EI8_V_MF8_MF4_MASK, VSUXSEG5EI8_V, 0x6, 0x0 }, // 9954 |
15946 | | { PseudoVSUXSEG5EI8_V_MF2_MF2, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9955 |
15947 | | { PseudoVSUXSEG5EI8_V_MF2_MF2_MASK, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9956 |
15948 | | { PseudoVSUXSEG5EI8_V_MF4_MF2, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9957 |
15949 | | { PseudoVSUXSEG5EI8_V_MF4_MF2_MASK, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9958 |
15950 | | { PseudoVSUXSEG5EI8_V_MF8_MF2, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9959 |
15951 | | { PseudoVSUXSEG5EI8_V_MF8_MF2_MASK, VSUXSEG5EI8_V, 0x7, 0x0 }, // 9960 |
15952 | | { PseudoVSUXSEG6EI16_V_M1_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9961 |
15953 | | { PseudoVSUXSEG6EI16_V_M1_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9962 |
15954 | | { PseudoVSUXSEG6EI16_V_M2_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9963 |
15955 | | { PseudoVSUXSEG6EI16_V_M2_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9964 |
15956 | | { PseudoVSUXSEG6EI16_V_MF2_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9965 |
15957 | | { PseudoVSUXSEG6EI16_V_MF2_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9966 |
15958 | | { PseudoVSUXSEG6EI16_V_MF4_M1, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9967 |
15959 | | { PseudoVSUXSEG6EI16_V_MF4_M1_MASK, VSUXSEG6EI16_V, 0x0, 0x0 }, // 9968 |
15960 | | { PseudoVSUXSEG6EI16_V_MF4_MF8, VSUXSEG6EI16_V, 0x5, 0x0 }, // 9969 |
15961 | | { PseudoVSUXSEG6EI16_V_MF4_MF8_MASK, VSUXSEG6EI16_V, 0x5, 0x0 }, // 9970 |
15962 | | { PseudoVSUXSEG6EI16_V_MF2_MF4, VSUXSEG6EI16_V, 0x6, 0x0 }, // 9971 |
15963 | | { PseudoVSUXSEG6EI16_V_MF2_MF4_MASK, VSUXSEG6EI16_V, 0x6, 0x0 }, // 9972 |
15964 | | { PseudoVSUXSEG6EI16_V_MF4_MF4, VSUXSEG6EI16_V, 0x6, 0x0 }, // 9973 |
15965 | | { PseudoVSUXSEG6EI16_V_MF4_MF4_MASK, VSUXSEG6EI16_V, 0x6, 0x0 }, // 9974 |
15966 | | { PseudoVSUXSEG6EI16_V_M1_MF2, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9975 |
15967 | | { PseudoVSUXSEG6EI16_V_M1_MF2_MASK, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9976 |
15968 | | { PseudoVSUXSEG6EI16_V_MF2_MF2, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9977 |
15969 | | { PseudoVSUXSEG6EI16_V_MF2_MF2_MASK, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9978 |
15970 | | { PseudoVSUXSEG6EI16_V_MF4_MF2, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9979 |
15971 | | { PseudoVSUXSEG6EI16_V_MF4_MF2_MASK, VSUXSEG6EI16_V, 0x7, 0x0 }, // 9980 |
15972 | | { PseudoVSUXSEG6EI32_V_M1_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9981 |
15973 | | { PseudoVSUXSEG6EI32_V_M1_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9982 |
15974 | | { PseudoVSUXSEG6EI32_V_M2_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9983 |
15975 | | { PseudoVSUXSEG6EI32_V_M2_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9984 |
15976 | | { PseudoVSUXSEG6EI32_V_M4_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9985 |
15977 | | { PseudoVSUXSEG6EI32_V_M4_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9986 |
15978 | | { PseudoVSUXSEG6EI32_V_MF2_M1, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9987 |
15979 | | { PseudoVSUXSEG6EI32_V_MF2_M1_MASK, VSUXSEG6EI32_V, 0x0, 0x0 }, // 9988 |
15980 | | { PseudoVSUXSEG6EI32_V_MF2_MF8, VSUXSEG6EI32_V, 0x5, 0x0 }, // 9989 |
15981 | | { PseudoVSUXSEG6EI32_V_MF2_MF8_MASK, VSUXSEG6EI32_V, 0x5, 0x0 }, // 9990 |
15982 | | { PseudoVSUXSEG6EI32_V_M1_MF4, VSUXSEG6EI32_V, 0x6, 0x0 }, // 9991 |
15983 | | { PseudoVSUXSEG6EI32_V_M1_MF4_MASK, VSUXSEG6EI32_V, 0x6, 0x0 }, // 9992 |
15984 | | { PseudoVSUXSEG6EI32_V_MF2_MF4, VSUXSEG6EI32_V, 0x6, 0x0 }, // 9993 |
15985 | | { PseudoVSUXSEG6EI32_V_MF2_MF4_MASK, VSUXSEG6EI32_V, 0x6, 0x0 }, // 9994 |
15986 | | { PseudoVSUXSEG6EI32_V_M1_MF2, VSUXSEG6EI32_V, 0x7, 0x0 }, // 9995 |
15987 | | { PseudoVSUXSEG6EI32_V_M1_MF2_MASK, VSUXSEG6EI32_V, 0x7, 0x0 }, // 9996 |
15988 | | { PseudoVSUXSEG6EI32_V_M2_MF2, VSUXSEG6EI32_V, 0x7, 0x0 }, // 9997 |
15989 | | { PseudoVSUXSEG6EI32_V_M2_MF2_MASK, VSUXSEG6EI32_V, 0x7, 0x0 }, // 9998 |
15990 | | { PseudoVSUXSEG6EI32_V_MF2_MF2, VSUXSEG6EI32_V, 0x7, 0x0 }, // 9999 |
15991 | | { PseudoVSUXSEG6EI32_V_MF2_MF2_MASK, VSUXSEG6EI32_V, 0x7, 0x0 }, // 10000 |
15992 | | { PseudoVSUXSEG6EI64_V_M1_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10001 |
15993 | | { PseudoVSUXSEG6EI64_V_M1_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10002 |
15994 | | { PseudoVSUXSEG6EI64_V_M2_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10003 |
15995 | | { PseudoVSUXSEG6EI64_V_M2_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10004 |
15996 | | { PseudoVSUXSEG6EI64_V_M4_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10005 |
15997 | | { PseudoVSUXSEG6EI64_V_M4_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10006 |
15998 | | { PseudoVSUXSEG6EI64_V_M8_M1, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10007 |
15999 | | { PseudoVSUXSEG6EI64_V_M8_M1_MASK, VSUXSEG6EI64_V, 0x0, 0x0 }, // 10008 |
16000 | | { PseudoVSUXSEG6EI64_V_M1_MF8, VSUXSEG6EI64_V, 0x5, 0x0 }, // 10009 |
16001 | | { PseudoVSUXSEG6EI64_V_M1_MF8_MASK, VSUXSEG6EI64_V, 0x5, 0x0 }, // 10010 |
16002 | | { PseudoVSUXSEG6EI64_V_M1_MF4, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10011 |
16003 | | { PseudoVSUXSEG6EI64_V_M1_MF4_MASK, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10012 |
16004 | | { PseudoVSUXSEG6EI64_V_M2_MF4, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10013 |
16005 | | { PseudoVSUXSEG6EI64_V_M2_MF4_MASK, VSUXSEG6EI64_V, 0x6, 0x0 }, // 10014 |
16006 | | { PseudoVSUXSEG6EI64_V_M1_MF2, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10015 |
16007 | | { PseudoVSUXSEG6EI64_V_M1_MF2_MASK, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10016 |
16008 | | { PseudoVSUXSEG6EI64_V_M2_MF2, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10017 |
16009 | | { PseudoVSUXSEG6EI64_V_M2_MF2_MASK, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10018 |
16010 | | { PseudoVSUXSEG6EI64_V_M4_MF2, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10019 |
16011 | | { PseudoVSUXSEG6EI64_V_M4_MF2_MASK, VSUXSEG6EI64_V, 0x7, 0x0 }, // 10020 |
16012 | | { PseudoVSUXSEG6EI8_V_M1_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10021 |
16013 | | { PseudoVSUXSEG6EI8_V_M1_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10022 |
16014 | | { PseudoVSUXSEG6EI8_V_MF2_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10023 |
16015 | | { PseudoVSUXSEG6EI8_V_MF2_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10024 |
16016 | | { PseudoVSUXSEG6EI8_V_MF4_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10025 |
16017 | | { PseudoVSUXSEG6EI8_V_MF4_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10026 |
16018 | | { PseudoVSUXSEG6EI8_V_MF8_M1, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10027 |
16019 | | { PseudoVSUXSEG6EI8_V_MF8_M1_MASK, VSUXSEG6EI8_V, 0x0, 0x0 }, // 10028 |
16020 | | { PseudoVSUXSEG6EI8_V_MF8_MF8, VSUXSEG6EI8_V, 0x5, 0x0 }, // 10029 |
16021 | | { PseudoVSUXSEG6EI8_V_MF8_MF8_MASK, VSUXSEG6EI8_V, 0x5, 0x0 }, // 10030 |
16022 | | { PseudoVSUXSEG6EI8_V_MF4_MF4, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10031 |
16023 | | { PseudoVSUXSEG6EI8_V_MF4_MF4_MASK, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10032 |
16024 | | { PseudoVSUXSEG6EI8_V_MF8_MF4, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10033 |
16025 | | { PseudoVSUXSEG6EI8_V_MF8_MF4_MASK, VSUXSEG6EI8_V, 0x6, 0x0 }, // 10034 |
16026 | | { PseudoVSUXSEG6EI8_V_MF2_MF2, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10035 |
16027 | | { PseudoVSUXSEG6EI8_V_MF2_MF2_MASK, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10036 |
16028 | | { PseudoVSUXSEG6EI8_V_MF4_MF2, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10037 |
16029 | | { PseudoVSUXSEG6EI8_V_MF4_MF2_MASK, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10038 |
16030 | | { PseudoVSUXSEG6EI8_V_MF8_MF2, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10039 |
16031 | | { PseudoVSUXSEG6EI8_V_MF8_MF2_MASK, VSUXSEG6EI8_V, 0x7, 0x0 }, // 10040 |
16032 | | { PseudoVSUXSEG7EI16_V_M1_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10041 |
16033 | | { PseudoVSUXSEG7EI16_V_M1_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10042 |
16034 | | { PseudoVSUXSEG7EI16_V_M2_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10043 |
16035 | | { PseudoVSUXSEG7EI16_V_M2_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10044 |
16036 | | { PseudoVSUXSEG7EI16_V_MF2_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10045 |
16037 | | { PseudoVSUXSEG7EI16_V_MF2_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10046 |
16038 | | { PseudoVSUXSEG7EI16_V_MF4_M1, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10047 |
16039 | | { PseudoVSUXSEG7EI16_V_MF4_M1_MASK, VSUXSEG7EI16_V, 0x0, 0x0 }, // 10048 |
16040 | | { PseudoVSUXSEG7EI16_V_MF4_MF8, VSUXSEG7EI16_V, 0x5, 0x0 }, // 10049 |
16041 | | { PseudoVSUXSEG7EI16_V_MF4_MF8_MASK, VSUXSEG7EI16_V, 0x5, 0x0 }, // 10050 |
16042 | | { PseudoVSUXSEG7EI16_V_MF2_MF4, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10051 |
16043 | | { PseudoVSUXSEG7EI16_V_MF2_MF4_MASK, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10052 |
16044 | | { PseudoVSUXSEG7EI16_V_MF4_MF4, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10053 |
16045 | | { PseudoVSUXSEG7EI16_V_MF4_MF4_MASK, VSUXSEG7EI16_V, 0x6, 0x0 }, // 10054 |
16046 | | { PseudoVSUXSEG7EI16_V_M1_MF2, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10055 |
16047 | | { PseudoVSUXSEG7EI16_V_M1_MF2_MASK, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10056 |
16048 | | { PseudoVSUXSEG7EI16_V_MF2_MF2, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10057 |
16049 | | { PseudoVSUXSEG7EI16_V_MF2_MF2_MASK, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10058 |
16050 | | { PseudoVSUXSEG7EI16_V_MF4_MF2, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10059 |
16051 | | { PseudoVSUXSEG7EI16_V_MF4_MF2_MASK, VSUXSEG7EI16_V, 0x7, 0x0 }, // 10060 |
16052 | | { PseudoVSUXSEG7EI32_V_M1_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10061 |
16053 | | { PseudoVSUXSEG7EI32_V_M1_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10062 |
16054 | | { PseudoVSUXSEG7EI32_V_M2_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10063 |
16055 | | { PseudoVSUXSEG7EI32_V_M2_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10064 |
16056 | | { PseudoVSUXSEG7EI32_V_M4_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10065 |
16057 | | { PseudoVSUXSEG7EI32_V_M4_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10066 |
16058 | | { PseudoVSUXSEG7EI32_V_MF2_M1, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10067 |
16059 | | { PseudoVSUXSEG7EI32_V_MF2_M1_MASK, VSUXSEG7EI32_V, 0x0, 0x0 }, // 10068 |
16060 | | { PseudoVSUXSEG7EI32_V_MF2_MF8, VSUXSEG7EI32_V, 0x5, 0x0 }, // 10069 |
16061 | | { PseudoVSUXSEG7EI32_V_MF2_MF8_MASK, VSUXSEG7EI32_V, 0x5, 0x0 }, // 10070 |
16062 | | { PseudoVSUXSEG7EI32_V_M1_MF4, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10071 |
16063 | | { PseudoVSUXSEG7EI32_V_M1_MF4_MASK, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10072 |
16064 | | { PseudoVSUXSEG7EI32_V_MF2_MF4, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10073 |
16065 | | { PseudoVSUXSEG7EI32_V_MF2_MF4_MASK, VSUXSEG7EI32_V, 0x6, 0x0 }, // 10074 |
16066 | | { PseudoVSUXSEG7EI32_V_M1_MF2, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10075 |
16067 | | { PseudoVSUXSEG7EI32_V_M1_MF2_MASK, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10076 |
16068 | | { PseudoVSUXSEG7EI32_V_M2_MF2, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10077 |
16069 | | { PseudoVSUXSEG7EI32_V_M2_MF2_MASK, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10078 |
16070 | | { PseudoVSUXSEG7EI32_V_MF2_MF2, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10079 |
16071 | | { PseudoVSUXSEG7EI32_V_MF2_MF2_MASK, VSUXSEG7EI32_V, 0x7, 0x0 }, // 10080 |
16072 | | { PseudoVSUXSEG7EI64_V_M1_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10081 |
16073 | | { PseudoVSUXSEG7EI64_V_M1_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10082 |
16074 | | { PseudoVSUXSEG7EI64_V_M2_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10083 |
16075 | | { PseudoVSUXSEG7EI64_V_M2_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10084 |
16076 | | { PseudoVSUXSEG7EI64_V_M4_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10085 |
16077 | | { PseudoVSUXSEG7EI64_V_M4_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10086 |
16078 | | { PseudoVSUXSEG7EI64_V_M8_M1, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10087 |
16079 | | { PseudoVSUXSEG7EI64_V_M8_M1_MASK, VSUXSEG7EI64_V, 0x0, 0x0 }, // 10088 |
16080 | | { PseudoVSUXSEG7EI64_V_M1_MF8, VSUXSEG7EI64_V, 0x5, 0x0 }, // 10089 |
16081 | | { PseudoVSUXSEG7EI64_V_M1_MF8_MASK, VSUXSEG7EI64_V, 0x5, 0x0 }, // 10090 |
16082 | | { PseudoVSUXSEG7EI64_V_M1_MF4, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10091 |
16083 | | { PseudoVSUXSEG7EI64_V_M1_MF4_MASK, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10092 |
16084 | | { PseudoVSUXSEG7EI64_V_M2_MF4, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10093 |
16085 | | { PseudoVSUXSEG7EI64_V_M2_MF4_MASK, VSUXSEG7EI64_V, 0x6, 0x0 }, // 10094 |
16086 | | { PseudoVSUXSEG7EI64_V_M1_MF2, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10095 |
16087 | | { PseudoVSUXSEG7EI64_V_M1_MF2_MASK, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10096 |
16088 | | { PseudoVSUXSEG7EI64_V_M2_MF2, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10097 |
16089 | | { PseudoVSUXSEG7EI64_V_M2_MF2_MASK, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10098 |
16090 | | { PseudoVSUXSEG7EI64_V_M4_MF2, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10099 |
16091 | | { PseudoVSUXSEG7EI64_V_M4_MF2_MASK, VSUXSEG7EI64_V, 0x7, 0x0 }, // 10100 |
16092 | | { PseudoVSUXSEG7EI8_V_M1_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10101 |
16093 | | { PseudoVSUXSEG7EI8_V_M1_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10102 |
16094 | | { PseudoVSUXSEG7EI8_V_MF2_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10103 |
16095 | | { PseudoVSUXSEG7EI8_V_MF2_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10104 |
16096 | | { PseudoVSUXSEG7EI8_V_MF4_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10105 |
16097 | | { PseudoVSUXSEG7EI8_V_MF4_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10106 |
16098 | | { PseudoVSUXSEG7EI8_V_MF8_M1, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10107 |
16099 | | { PseudoVSUXSEG7EI8_V_MF8_M1_MASK, VSUXSEG7EI8_V, 0x0, 0x0 }, // 10108 |
16100 | | { PseudoVSUXSEG7EI8_V_MF8_MF8, VSUXSEG7EI8_V, 0x5, 0x0 }, // 10109 |
16101 | | { PseudoVSUXSEG7EI8_V_MF8_MF8_MASK, VSUXSEG7EI8_V, 0x5, 0x0 }, // 10110 |
16102 | | { PseudoVSUXSEG7EI8_V_MF4_MF4, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10111 |
16103 | | { PseudoVSUXSEG7EI8_V_MF4_MF4_MASK, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10112 |
16104 | | { PseudoVSUXSEG7EI8_V_MF8_MF4, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10113 |
16105 | | { PseudoVSUXSEG7EI8_V_MF8_MF4_MASK, VSUXSEG7EI8_V, 0x6, 0x0 }, // 10114 |
16106 | | { PseudoVSUXSEG7EI8_V_MF2_MF2, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10115 |
16107 | | { PseudoVSUXSEG7EI8_V_MF2_MF2_MASK, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10116 |
16108 | | { PseudoVSUXSEG7EI8_V_MF4_MF2, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10117 |
16109 | | { PseudoVSUXSEG7EI8_V_MF4_MF2_MASK, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10118 |
16110 | | { PseudoVSUXSEG7EI8_V_MF8_MF2, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10119 |
16111 | | { PseudoVSUXSEG7EI8_V_MF8_MF2_MASK, VSUXSEG7EI8_V, 0x7, 0x0 }, // 10120 |
16112 | | { PseudoVSUXSEG8EI16_V_M1_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10121 |
16113 | | { PseudoVSUXSEG8EI16_V_M1_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10122 |
16114 | | { PseudoVSUXSEG8EI16_V_M2_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10123 |
16115 | | { PseudoVSUXSEG8EI16_V_M2_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10124 |
16116 | | { PseudoVSUXSEG8EI16_V_MF2_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10125 |
16117 | | { PseudoVSUXSEG8EI16_V_MF2_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10126 |
16118 | | { PseudoVSUXSEG8EI16_V_MF4_M1, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10127 |
16119 | | { PseudoVSUXSEG8EI16_V_MF4_M1_MASK, VSUXSEG8EI16_V, 0x0, 0x0 }, // 10128 |
16120 | | { PseudoVSUXSEG8EI16_V_MF4_MF8, VSUXSEG8EI16_V, 0x5, 0x0 }, // 10129 |
16121 | | { PseudoVSUXSEG8EI16_V_MF4_MF8_MASK, VSUXSEG8EI16_V, 0x5, 0x0 }, // 10130 |
16122 | | { PseudoVSUXSEG8EI16_V_MF2_MF4, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10131 |
16123 | | { PseudoVSUXSEG8EI16_V_MF2_MF4_MASK, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10132 |
16124 | | { PseudoVSUXSEG8EI16_V_MF4_MF4, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10133 |
16125 | | { PseudoVSUXSEG8EI16_V_MF4_MF4_MASK, VSUXSEG8EI16_V, 0x6, 0x0 }, // 10134 |
16126 | | { PseudoVSUXSEG8EI16_V_M1_MF2, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10135 |
16127 | | { PseudoVSUXSEG8EI16_V_M1_MF2_MASK, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10136 |
16128 | | { PseudoVSUXSEG8EI16_V_MF2_MF2, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10137 |
16129 | | { PseudoVSUXSEG8EI16_V_MF2_MF2_MASK, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10138 |
16130 | | { PseudoVSUXSEG8EI16_V_MF4_MF2, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10139 |
16131 | | { PseudoVSUXSEG8EI16_V_MF4_MF2_MASK, VSUXSEG8EI16_V, 0x7, 0x0 }, // 10140 |
16132 | | { PseudoVSUXSEG8EI32_V_M1_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10141 |
16133 | | { PseudoVSUXSEG8EI32_V_M1_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10142 |
16134 | | { PseudoVSUXSEG8EI32_V_M2_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10143 |
16135 | | { PseudoVSUXSEG8EI32_V_M2_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10144 |
16136 | | { PseudoVSUXSEG8EI32_V_M4_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10145 |
16137 | | { PseudoVSUXSEG8EI32_V_M4_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10146 |
16138 | | { PseudoVSUXSEG8EI32_V_MF2_M1, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10147 |
16139 | | { PseudoVSUXSEG8EI32_V_MF2_M1_MASK, VSUXSEG8EI32_V, 0x0, 0x0 }, // 10148 |
16140 | | { PseudoVSUXSEG8EI32_V_MF2_MF8, VSUXSEG8EI32_V, 0x5, 0x0 }, // 10149 |
16141 | | { PseudoVSUXSEG8EI32_V_MF2_MF8_MASK, VSUXSEG8EI32_V, 0x5, 0x0 }, // 10150 |
16142 | | { PseudoVSUXSEG8EI32_V_M1_MF4, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10151 |
16143 | | { PseudoVSUXSEG8EI32_V_M1_MF4_MASK, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10152 |
16144 | | { PseudoVSUXSEG8EI32_V_MF2_MF4, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10153 |
16145 | | { PseudoVSUXSEG8EI32_V_MF2_MF4_MASK, VSUXSEG8EI32_V, 0x6, 0x0 }, // 10154 |
16146 | | { PseudoVSUXSEG8EI32_V_M1_MF2, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10155 |
16147 | | { PseudoVSUXSEG8EI32_V_M1_MF2_MASK, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10156 |
16148 | | { PseudoVSUXSEG8EI32_V_M2_MF2, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10157 |
16149 | | { PseudoVSUXSEG8EI32_V_M2_MF2_MASK, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10158 |
16150 | | { PseudoVSUXSEG8EI32_V_MF2_MF2, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10159 |
16151 | | { PseudoVSUXSEG8EI32_V_MF2_MF2_MASK, VSUXSEG8EI32_V, 0x7, 0x0 }, // 10160 |
16152 | | { PseudoVSUXSEG8EI64_V_M1_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10161 |
16153 | | { PseudoVSUXSEG8EI64_V_M1_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10162 |
16154 | | { PseudoVSUXSEG8EI64_V_M2_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10163 |
16155 | | { PseudoVSUXSEG8EI64_V_M2_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10164 |
16156 | | { PseudoVSUXSEG8EI64_V_M4_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10165 |
16157 | | { PseudoVSUXSEG8EI64_V_M4_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10166 |
16158 | | { PseudoVSUXSEG8EI64_V_M8_M1, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10167 |
16159 | | { PseudoVSUXSEG8EI64_V_M8_M1_MASK, VSUXSEG8EI64_V, 0x0, 0x0 }, // 10168 |
16160 | | { PseudoVSUXSEG8EI64_V_M1_MF8, VSUXSEG8EI64_V, 0x5, 0x0 }, // 10169 |
16161 | | { PseudoVSUXSEG8EI64_V_M1_MF8_MASK, VSUXSEG8EI64_V, 0x5, 0x0 }, // 10170 |
16162 | | { PseudoVSUXSEG8EI64_V_M1_MF4, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10171 |
16163 | | { PseudoVSUXSEG8EI64_V_M1_MF4_MASK, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10172 |
16164 | | { PseudoVSUXSEG8EI64_V_M2_MF4, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10173 |
16165 | | { PseudoVSUXSEG8EI64_V_M2_MF4_MASK, VSUXSEG8EI64_V, 0x6, 0x0 }, // 10174 |
16166 | | { PseudoVSUXSEG8EI64_V_M1_MF2, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10175 |
16167 | | { PseudoVSUXSEG8EI64_V_M1_MF2_MASK, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10176 |
16168 | | { PseudoVSUXSEG8EI64_V_M2_MF2, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10177 |
16169 | | { PseudoVSUXSEG8EI64_V_M2_MF2_MASK, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10178 |
16170 | | { PseudoVSUXSEG8EI64_V_M4_MF2, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10179 |
16171 | | { PseudoVSUXSEG8EI64_V_M4_MF2_MASK, VSUXSEG8EI64_V, 0x7, 0x0 }, // 10180 |
16172 | | { PseudoVSUXSEG8EI8_V_M1_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10181 |
16173 | | { PseudoVSUXSEG8EI8_V_M1_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10182 |
16174 | | { PseudoVSUXSEG8EI8_V_MF2_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10183 |
16175 | | { PseudoVSUXSEG8EI8_V_MF2_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10184 |
16176 | | { PseudoVSUXSEG8EI8_V_MF4_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10185 |
16177 | | { PseudoVSUXSEG8EI8_V_MF4_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10186 |
16178 | | { PseudoVSUXSEG8EI8_V_MF8_M1, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10187 |
16179 | | { PseudoVSUXSEG8EI8_V_MF8_M1_MASK, VSUXSEG8EI8_V, 0x0, 0x0 }, // 10188 |
16180 | | { PseudoVSUXSEG8EI8_V_MF8_MF8, VSUXSEG8EI8_V, 0x5, 0x0 }, // 10189 |
16181 | | { PseudoVSUXSEG8EI8_V_MF8_MF8_MASK, VSUXSEG8EI8_V, 0x5, 0x0 }, // 10190 |
16182 | | { PseudoVSUXSEG8EI8_V_MF4_MF4, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10191 |
16183 | | { PseudoVSUXSEG8EI8_V_MF4_MF4_MASK, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10192 |
16184 | | { PseudoVSUXSEG8EI8_V_MF8_MF4, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10193 |
16185 | | { PseudoVSUXSEG8EI8_V_MF8_MF4_MASK, VSUXSEG8EI8_V, 0x6, 0x0 }, // 10194 |
16186 | | { PseudoVSUXSEG8EI8_V_MF2_MF2, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10195 |
16187 | | { PseudoVSUXSEG8EI8_V_MF2_MF2_MASK, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10196 |
16188 | | { PseudoVSUXSEG8EI8_V_MF4_MF2, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10197 |
16189 | | { PseudoVSUXSEG8EI8_V_MF4_MF2_MASK, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10198 |
16190 | | { PseudoVSUXSEG8EI8_V_MF8_MF2, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10199 |
16191 | | { PseudoVSUXSEG8EI8_V_MF8_MF2_MASK, VSUXSEG8EI8_V, 0x7, 0x0 }, // 10200 |
16192 | | { PseudoVWADDU_VV_M1, VWADDU_VV, 0x0, 0x0 }, // 10201 |
16193 | | { PseudoVWADDU_VV_M1_MASK, VWADDU_VV, 0x0, 0x0 }, // 10202 |
16194 | | { PseudoVWADDU_VV_M2, VWADDU_VV, 0x1, 0x0 }, // 10203 |
16195 | | { PseudoVWADDU_VV_M2_MASK, VWADDU_VV, 0x1, 0x0 }, // 10204 |
16196 | | { PseudoVWADDU_VV_M4, VWADDU_VV, 0x2, 0x0 }, // 10205 |
16197 | | { PseudoVWADDU_VV_M4_MASK, VWADDU_VV, 0x2, 0x0 }, // 10206 |
16198 | | { PseudoVWADDU_VV_MF8, VWADDU_VV, 0x5, 0x0 }, // 10207 |
16199 | | { PseudoVWADDU_VV_MF8_MASK, VWADDU_VV, 0x5, 0x0 }, // 10208 |
16200 | | { PseudoVWADDU_VV_MF4, VWADDU_VV, 0x6, 0x0 }, // 10209 |
16201 | | { PseudoVWADDU_VV_MF4_MASK, VWADDU_VV, 0x6, 0x0 }, // 10210 |
16202 | | { PseudoVWADDU_VV_MF2, VWADDU_VV, 0x7, 0x0 }, // 10211 |
16203 | | { PseudoVWADDU_VV_MF2_MASK, VWADDU_VV, 0x7, 0x0 }, // 10212 |
16204 | | { PseudoVWADDU_VX_M1, VWADDU_VX, 0x0, 0x0 }, // 10213 |
16205 | | { PseudoVWADDU_VX_M1_MASK, VWADDU_VX, 0x0, 0x0 }, // 10214 |
16206 | | { PseudoVWADDU_VX_M2, VWADDU_VX, 0x1, 0x0 }, // 10215 |
16207 | | { PseudoVWADDU_VX_M2_MASK, VWADDU_VX, 0x1, 0x0 }, // 10216 |
16208 | | { PseudoVWADDU_VX_M4, VWADDU_VX, 0x2, 0x0 }, // 10217 |
16209 | | { PseudoVWADDU_VX_M4_MASK, VWADDU_VX, 0x2, 0x0 }, // 10218 |
16210 | | { PseudoVWADDU_VX_MF8, VWADDU_VX, 0x5, 0x0 }, // 10219 |
16211 | | { PseudoVWADDU_VX_MF8_MASK, VWADDU_VX, 0x5, 0x0 }, // 10220 |
16212 | | { PseudoVWADDU_VX_MF4, VWADDU_VX, 0x6, 0x0 }, // 10221 |
16213 | | { PseudoVWADDU_VX_MF4_MASK, VWADDU_VX, 0x6, 0x0 }, // 10222 |
16214 | | { PseudoVWADDU_VX_MF2, VWADDU_VX, 0x7, 0x0 }, // 10223 |
16215 | | { PseudoVWADDU_VX_MF2_MASK, VWADDU_VX, 0x7, 0x0 }, // 10224 |
16216 | | { PseudoVWADDU_WV_M1, VWADDU_WV, 0x0, 0x0 }, // 10225 |
16217 | | { PseudoVWADDU_WV_M1_MASK, VWADDU_WV, 0x0, 0x0 }, // 10226 |
16218 | | { PseudoVWADDU_WV_M1_MASK_TIED, VWADDU_WV, 0x0, 0x0 }, // 10227 |
16219 | | { PseudoVWADDU_WV_M1_TIED, VWADDU_WV, 0x0, 0x0 }, // 10228 |
16220 | | { PseudoVWADDU_WV_M2, VWADDU_WV, 0x1, 0x0 }, // 10229 |
16221 | | { PseudoVWADDU_WV_M2_MASK, VWADDU_WV, 0x1, 0x0 }, // 10230 |
16222 | | { PseudoVWADDU_WV_M2_MASK_TIED, VWADDU_WV, 0x1, 0x0 }, // 10231 |
16223 | | { PseudoVWADDU_WV_M2_TIED, VWADDU_WV, 0x1, 0x0 }, // 10232 |
16224 | | { PseudoVWADDU_WV_M4, VWADDU_WV, 0x2, 0x0 }, // 10233 |
16225 | | { PseudoVWADDU_WV_M4_MASK, VWADDU_WV, 0x2, 0x0 }, // 10234 |
16226 | | { PseudoVWADDU_WV_M4_MASK_TIED, VWADDU_WV, 0x2, 0x0 }, // 10235 |
16227 | | { PseudoVWADDU_WV_M4_TIED, VWADDU_WV, 0x2, 0x0 }, // 10236 |
16228 | | { PseudoVWADDU_WV_MF8, VWADDU_WV, 0x5, 0x0 }, // 10237 |
16229 | | { PseudoVWADDU_WV_MF8_MASK, VWADDU_WV, 0x5, 0x0 }, // 10238 |
16230 | | { PseudoVWADDU_WV_MF8_MASK_TIED, VWADDU_WV, 0x5, 0x0 }, // 10239 |
16231 | | { PseudoVWADDU_WV_MF8_TIED, VWADDU_WV, 0x5, 0x0 }, // 10240 |
16232 | | { PseudoVWADDU_WV_MF4, VWADDU_WV, 0x6, 0x0 }, // 10241 |
16233 | | { PseudoVWADDU_WV_MF4_MASK, VWADDU_WV, 0x6, 0x0 }, // 10242 |
16234 | | { PseudoVWADDU_WV_MF4_MASK_TIED, VWADDU_WV, 0x6, 0x0 }, // 10243 |
16235 | | { PseudoVWADDU_WV_MF4_TIED, VWADDU_WV, 0x6, 0x0 }, // 10244 |
16236 | | { PseudoVWADDU_WV_MF2, VWADDU_WV, 0x7, 0x0 }, // 10245 |
16237 | | { PseudoVWADDU_WV_MF2_MASK, VWADDU_WV, 0x7, 0x0 }, // 10246 |
16238 | | { PseudoVWADDU_WV_MF2_MASK_TIED, VWADDU_WV, 0x7, 0x0 }, // 10247 |
16239 | | { PseudoVWADDU_WV_MF2_TIED, VWADDU_WV, 0x7, 0x0 }, // 10248 |
16240 | | { PseudoVWADDU_WX_M1, VWADDU_WX, 0x0, 0x0 }, // 10249 |
16241 | | { PseudoVWADDU_WX_M1_MASK, VWADDU_WX, 0x0, 0x0 }, // 10250 |
16242 | | { PseudoVWADDU_WX_M2, VWADDU_WX, 0x1, 0x0 }, // 10251 |
16243 | | { PseudoVWADDU_WX_M2_MASK, VWADDU_WX, 0x1, 0x0 }, // 10252 |
16244 | | { PseudoVWADDU_WX_M4, VWADDU_WX, 0x2, 0x0 }, // 10253 |
16245 | | { PseudoVWADDU_WX_M4_MASK, VWADDU_WX, 0x2, 0x0 }, // 10254 |
16246 | | { PseudoVWADDU_WX_MF8, VWADDU_WX, 0x5, 0x0 }, // 10255 |
16247 | | { PseudoVWADDU_WX_MF8_MASK, VWADDU_WX, 0x5, 0x0 }, // 10256 |
16248 | | { PseudoVWADDU_WX_MF4, VWADDU_WX, 0x6, 0x0 }, // 10257 |
16249 | | { PseudoVWADDU_WX_MF4_MASK, VWADDU_WX, 0x6, 0x0 }, // 10258 |
16250 | | { PseudoVWADDU_WX_MF2, VWADDU_WX, 0x7, 0x0 }, // 10259 |
16251 | | { PseudoVWADDU_WX_MF2_MASK, VWADDU_WX, 0x7, 0x0 }, // 10260 |
16252 | | { PseudoVWADD_VV_M1, VWADD_VV, 0x0, 0x0 }, // 10261 |
16253 | | { PseudoVWADD_VV_M1_MASK, VWADD_VV, 0x0, 0x0 }, // 10262 |
16254 | | { PseudoVWADD_VV_M2, VWADD_VV, 0x1, 0x0 }, // 10263 |
16255 | | { PseudoVWADD_VV_M2_MASK, VWADD_VV, 0x1, 0x0 }, // 10264 |
16256 | | { PseudoVWADD_VV_M4, VWADD_VV, 0x2, 0x0 }, // 10265 |
16257 | | { PseudoVWADD_VV_M4_MASK, VWADD_VV, 0x2, 0x0 }, // 10266 |
16258 | | { PseudoVWADD_VV_MF8, VWADD_VV, 0x5, 0x0 }, // 10267 |
16259 | | { PseudoVWADD_VV_MF8_MASK, VWADD_VV, 0x5, 0x0 }, // 10268 |
16260 | | { PseudoVWADD_VV_MF4, VWADD_VV, 0x6, 0x0 }, // 10269 |
16261 | | { PseudoVWADD_VV_MF4_MASK, VWADD_VV, 0x6, 0x0 }, // 10270 |
16262 | | { PseudoVWADD_VV_MF2, VWADD_VV, 0x7, 0x0 }, // 10271 |
16263 | | { PseudoVWADD_VV_MF2_MASK, VWADD_VV, 0x7, 0x0 }, // 10272 |
16264 | | { PseudoVWADD_VX_M1, VWADD_VX, 0x0, 0x0 }, // 10273 |
16265 | | { PseudoVWADD_VX_M1_MASK, VWADD_VX, 0x0, 0x0 }, // 10274 |
16266 | | { PseudoVWADD_VX_M2, VWADD_VX, 0x1, 0x0 }, // 10275 |
16267 | | { PseudoVWADD_VX_M2_MASK, VWADD_VX, 0x1, 0x0 }, // 10276 |
16268 | | { PseudoVWADD_VX_M4, VWADD_VX, 0x2, 0x0 }, // 10277 |
16269 | | { PseudoVWADD_VX_M4_MASK, VWADD_VX, 0x2, 0x0 }, // 10278 |
16270 | | { PseudoVWADD_VX_MF8, VWADD_VX, 0x5, 0x0 }, // 10279 |
16271 | | { PseudoVWADD_VX_MF8_MASK, VWADD_VX, 0x5, 0x0 }, // 10280 |
16272 | | { PseudoVWADD_VX_MF4, VWADD_VX, 0x6, 0x0 }, // 10281 |
16273 | | { PseudoVWADD_VX_MF4_MASK, VWADD_VX, 0x6, 0x0 }, // 10282 |
16274 | | { PseudoVWADD_VX_MF2, VWADD_VX, 0x7, 0x0 }, // 10283 |
16275 | | { PseudoVWADD_VX_MF2_MASK, VWADD_VX, 0x7, 0x0 }, // 10284 |
16276 | | { PseudoVWADD_WV_M1, VWADD_WV, 0x0, 0x0 }, // 10285 |
16277 | | { PseudoVWADD_WV_M1_MASK, VWADD_WV, 0x0, 0x0 }, // 10286 |
16278 | | { PseudoVWADD_WV_M1_MASK_TIED, VWADD_WV, 0x0, 0x0 }, // 10287 |
16279 | | { PseudoVWADD_WV_M1_TIED, VWADD_WV, 0x0, 0x0 }, // 10288 |
16280 | | { PseudoVWADD_WV_M2, VWADD_WV, 0x1, 0x0 }, // 10289 |
16281 | | { PseudoVWADD_WV_M2_MASK, VWADD_WV, 0x1, 0x0 }, // 10290 |
16282 | | { PseudoVWADD_WV_M2_MASK_TIED, VWADD_WV, 0x1, 0x0 }, // 10291 |
16283 | | { PseudoVWADD_WV_M2_TIED, VWADD_WV, 0x1, 0x0 }, // 10292 |
16284 | | { PseudoVWADD_WV_M4, VWADD_WV, 0x2, 0x0 }, // 10293 |
16285 | | { PseudoVWADD_WV_M4_MASK, VWADD_WV, 0x2, 0x0 }, // 10294 |
16286 | | { PseudoVWADD_WV_M4_MASK_TIED, VWADD_WV, 0x2, 0x0 }, // 10295 |
16287 | | { PseudoVWADD_WV_M4_TIED, VWADD_WV, 0x2, 0x0 }, // 10296 |
16288 | | { PseudoVWADD_WV_MF8, VWADD_WV, 0x5, 0x0 }, // 10297 |
16289 | | { PseudoVWADD_WV_MF8_MASK, VWADD_WV, 0x5, 0x0 }, // 10298 |
16290 | | { PseudoVWADD_WV_MF8_MASK_TIED, VWADD_WV, 0x5, 0x0 }, // 10299 |
16291 | | { PseudoVWADD_WV_MF8_TIED, VWADD_WV, 0x5, 0x0 }, // 10300 |
16292 | | { PseudoVWADD_WV_MF4, VWADD_WV, 0x6, 0x0 }, // 10301 |
16293 | | { PseudoVWADD_WV_MF4_MASK, VWADD_WV, 0x6, 0x0 }, // 10302 |
16294 | | { PseudoVWADD_WV_MF4_MASK_TIED, VWADD_WV, 0x6, 0x0 }, // 10303 |
16295 | | { PseudoVWADD_WV_MF4_TIED, VWADD_WV, 0x6, 0x0 }, // 10304 |
16296 | | { PseudoVWADD_WV_MF2, VWADD_WV, 0x7, 0x0 }, // 10305 |
16297 | | { PseudoVWADD_WV_MF2_MASK, VWADD_WV, 0x7, 0x0 }, // 10306 |
16298 | | { PseudoVWADD_WV_MF2_MASK_TIED, VWADD_WV, 0x7, 0x0 }, // 10307 |
16299 | | { PseudoVWADD_WV_MF2_TIED, VWADD_WV, 0x7, 0x0 }, // 10308 |
16300 | | { PseudoVWADD_WX_M1, VWADD_WX, 0x0, 0x0 }, // 10309 |
16301 | | { PseudoVWADD_WX_M1_MASK, VWADD_WX, 0x0, 0x0 }, // 10310 |
16302 | | { PseudoVWADD_WX_M2, VWADD_WX, 0x1, 0x0 }, // 10311 |
16303 | | { PseudoVWADD_WX_M2_MASK, VWADD_WX, 0x1, 0x0 }, // 10312 |
16304 | | { PseudoVWADD_WX_M4, VWADD_WX, 0x2, 0x0 }, // 10313 |
16305 | | { PseudoVWADD_WX_M4_MASK, VWADD_WX, 0x2, 0x0 }, // 10314 |
16306 | | { PseudoVWADD_WX_MF8, VWADD_WX, 0x5, 0x0 }, // 10315 |
16307 | | { PseudoVWADD_WX_MF8_MASK, VWADD_WX, 0x5, 0x0 }, // 10316 |
16308 | | { PseudoVWADD_WX_MF4, VWADD_WX, 0x6, 0x0 }, // 10317 |
16309 | | { PseudoVWADD_WX_MF4_MASK, VWADD_WX, 0x6, 0x0 }, // 10318 |
16310 | | { PseudoVWADD_WX_MF2, VWADD_WX, 0x7, 0x0 }, // 10319 |
16311 | | { PseudoVWADD_WX_MF2_MASK, VWADD_WX, 0x7, 0x0 }, // 10320 |
16312 | | { PseudoVWMACCSU_VV_M1, VWMACCSU_VV, 0x0, 0x0 }, // 10321 |
16313 | | { PseudoVWMACCSU_VV_M1_MASK, VWMACCSU_VV, 0x0, 0x0 }, // 10322 |
16314 | | { PseudoVWMACCSU_VV_M2, VWMACCSU_VV, 0x1, 0x0 }, // 10323 |
16315 | | { PseudoVWMACCSU_VV_M2_MASK, VWMACCSU_VV, 0x1, 0x0 }, // 10324 |
16316 | | { PseudoVWMACCSU_VV_M4, VWMACCSU_VV, 0x2, 0x0 }, // 10325 |
16317 | | { PseudoVWMACCSU_VV_M4_MASK, VWMACCSU_VV, 0x2, 0x0 }, // 10326 |
16318 | | { PseudoVWMACCSU_VV_MF8, VWMACCSU_VV, 0x5, 0x0 }, // 10327 |
16319 | | { PseudoVWMACCSU_VV_MF8_MASK, VWMACCSU_VV, 0x5, 0x0 }, // 10328 |
16320 | | { PseudoVWMACCSU_VV_MF4, VWMACCSU_VV, 0x6, 0x0 }, // 10329 |
16321 | | { PseudoVWMACCSU_VV_MF4_MASK, VWMACCSU_VV, 0x6, 0x0 }, // 10330 |
16322 | | { PseudoVWMACCSU_VV_MF2, VWMACCSU_VV, 0x7, 0x0 }, // 10331 |
16323 | | { PseudoVWMACCSU_VV_MF2_MASK, VWMACCSU_VV, 0x7, 0x0 }, // 10332 |
16324 | | { PseudoVWMACCSU_VX_M1, VWMACCSU_VX, 0x0, 0x0 }, // 10333 |
16325 | | { PseudoVWMACCSU_VX_M1_MASK, VWMACCSU_VX, 0x0, 0x0 }, // 10334 |
16326 | | { PseudoVWMACCSU_VX_M2, VWMACCSU_VX, 0x1, 0x0 }, // 10335 |
16327 | | { PseudoVWMACCSU_VX_M2_MASK, VWMACCSU_VX, 0x1, 0x0 }, // 10336 |
16328 | | { PseudoVWMACCSU_VX_M4, VWMACCSU_VX, 0x2, 0x0 }, // 10337 |
16329 | | { PseudoVWMACCSU_VX_M4_MASK, VWMACCSU_VX, 0x2, 0x0 }, // 10338 |
16330 | | { PseudoVWMACCSU_VX_MF8, VWMACCSU_VX, 0x5, 0x0 }, // 10339 |
16331 | | { PseudoVWMACCSU_VX_MF8_MASK, VWMACCSU_VX, 0x5, 0x0 }, // 10340 |
16332 | | { PseudoVWMACCSU_VX_MF4, VWMACCSU_VX, 0x6, 0x0 }, // 10341 |
16333 | | { PseudoVWMACCSU_VX_MF4_MASK, VWMACCSU_VX, 0x6, 0x0 }, // 10342 |
16334 | | { PseudoVWMACCSU_VX_MF2, VWMACCSU_VX, 0x7, 0x0 }, // 10343 |
16335 | | { PseudoVWMACCSU_VX_MF2_MASK, VWMACCSU_VX, 0x7, 0x0 }, // 10344 |
16336 | | { PseudoVWMACCUS_VX_M1, VWMACCUS_VX, 0x0, 0x0 }, // 10345 |
16337 | | { PseudoVWMACCUS_VX_M1_MASK, VWMACCUS_VX, 0x0, 0x0 }, // 10346 |
16338 | | { PseudoVWMACCUS_VX_M2, VWMACCUS_VX, 0x1, 0x0 }, // 10347 |
16339 | | { PseudoVWMACCUS_VX_M2_MASK, VWMACCUS_VX, 0x1, 0x0 }, // 10348 |
16340 | | { PseudoVWMACCUS_VX_M4, VWMACCUS_VX, 0x2, 0x0 }, // 10349 |
16341 | | { PseudoVWMACCUS_VX_M4_MASK, VWMACCUS_VX, 0x2, 0x0 }, // 10350 |
16342 | | { PseudoVWMACCUS_VX_MF8, VWMACCUS_VX, 0x5, 0x0 }, // 10351 |
16343 | | { PseudoVWMACCUS_VX_MF8_MASK, VWMACCUS_VX, 0x5, 0x0 }, // 10352 |
16344 | | { PseudoVWMACCUS_VX_MF4, VWMACCUS_VX, 0x6, 0x0 }, // 10353 |
16345 | | { PseudoVWMACCUS_VX_MF4_MASK, VWMACCUS_VX, 0x6, 0x0 }, // 10354 |
16346 | | { PseudoVWMACCUS_VX_MF2, VWMACCUS_VX, 0x7, 0x0 }, // 10355 |
16347 | | { PseudoVWMACCUS_VX_MF2_MASK, VWMACCUS_VX, 0x7, 0x0 }, // 10356 |
16348 | | { PseudoVWMACCU_VV_M1, VWMACCU_VV, 0x0, 0x0 }, // 10357 |
16349 | | { PseudoVWMACCU_VV_M1_MASK, VWMACCU_VV, 0x0, 0x0 }, // 10358 |
16350 | | { PseudoVWMACCU_VV_M2, VWMACCU_VV, 0x1, 0x0 }, // 10359 |
16351 | | { PseudoVWMACCU_VV_M2_MASK, VWMACCU_VV, 0x1, 0x0 }, // 10360 |
16352 | | { PseudoVWMACCU_VV_M4, VWMACCU_VV, 0x2, 0x0 }, // 10361 |
16353 | | { PseudoVWMACCU_VV_M4_MASK, VWMACCU_VV, 0x2, 0x0 }, // 10362 |
16354 | | { PseudoVWMACCU_VV_MF8, VWMACCU_VV, 0x5, 0x0 }, // 10363 |
16355 | | { PseudoVWMACCU_VV_MF8_MASK, VWMACCU_VV, 0x5, 0x0 }, // 10364 |
16356 | | { PseudoVWMACCU_VV_MF4, VWMACCU_VV, 0x6, 0x0 }, // 10365 |
16357 | | { PseudoVWMACCU_VV_MF4_MASK, VWMACCU_VV, 0x6, 0x0 }, // 10366 |
16358 | | { PseudoVWMACCU_VV_MF2, VWMACCU_VV, 0x7, 0x0 }, // 10367 |
16359 | | { PseudoVWMACCU_VV_MF2_MASK, VWMACCU_VV, 0x7, 0x0 }, // 10368 |
16360 | | { PseudoVWMACCU_VX_M1, VWMACCU_VX, 0x0, 0x0 }, // 10369 |
16361 | | { PseudoVWMACCU_VX_M1_MASK, VWMACCU_VX, 0x0, 0x0 }, // 10370 |
16362 | | { PseudoVWMACCU_VX_M2, VWMACCU_VX, 0x1, 0x0 }, // 10371 |
16363 | | { PseudoVWMACCU_VX_M2_MASK, VWMACCU_VX, 0x1, 0x0 }, // 10372 |
16364 | | { PseudoVWMACCU_VX_M4, VWMACCU_VX, 0x2, 0x0 }, // 10373 |
16365 | | { PseudoVWMACCU_VX_M4_MASK, VWMACCU_VX, 0x2, 0x0 }, // 10374 |
16366 | | { PseudoVWMACCU_VX_MF8, VWMACCU_VX, 0x5, 0x0 }, // 10375 |
16367 | | { PseudoVWMACCU_VX_MF8_MASK, VWMACCU_VX, 0x5, 0x0 }, // 10376 |
16368 | | { PseudoVWMACCU_VX_MF4, VWMACCU_VX, 0x6, 0x0 }, // 10377 |
16369 | | { PseudoVWMACCU_VX_MF4_MASK, VWMACCU_VX, 0x6, 0x0 }, // 10378 |
16370 | | { PseudoVWMACCU_VX_MF2, VWMACCU_VX, 0x7, 0x0 }, // 10379 |
16371 | | { PseudoVWMACCU_VX_MF2_MASK, VWMACCU_VX, 0x7, 0x0 }, // 10380 |
16372 | | { PseudoVWMACC_VV_M1, VWMACC_VV, 0x0, 0x0 }, // 10381 |
16373 | | { PseudoVWMACC_VV_M1_MASK, VWMACC_VV, 0x0, 0x0 }, // 10382 |
16374 | | { PseudoVWMACC_VV_M2, VWMACC_VV, 0x1, 0x0 }, // 10383 |
16375 | | { PseudoVWMACC_VV_M2_MASK, VWMACC_VV, 0x1, 0x0 }, // 10384 |
16376 | | { PseudoVWMACC_VV_M4, VWMACC_VV, 0x2, 0x0 }, // 10385 |
16377 | | { PseudoVWMACC_VV_M4_MASK, VWMACC_VV, 0x2, 0x0 }, // 10386 |
16378 | | { PseudoVWMACC_VV_MF8, VWMACC_VV, 0x5, 0x0 }, // 10387 |
16379 | | { PseudoVWMACC_VV_MF8_MASK, VWMACC_VV, 0x5, 0x0 }, // 10388 |
16380 | | { PseudoVWMACC_VV_MF4, VWMACC_VV, 0x6, 0x0 }, // 10389 |
16381 | | { PseudoVWMACC_VV_MF4_MASK, VWMACC_VV, 0x6, 0x0 }, // 10390 |
16382 | | { PseudoVWMACC_VV_MF2, VWMACC_VV, 0x7, 0x0 }, // 10391 |
16383 | | { PseudoVWMACC_VV_MF2_MASK, VWMACC_VV, 0x7, 0x0 }, // 10392 |
16384 | | { PseudoVWMACC_VX_M1, VWMACC_VX, 0x0, 0x0 }, // 10393 |
16385 | | { PseudoVWMACC_VX_M1_MASK, VWMACC_VX, 0x0, 0x0 }, // 10394 |
16386 | | { PseudoVWMACC_VX_M2, VWMACC_VX, 0x1, 0x0 }, // 10395 |
16387 | | { PseudoVWMACC_VX_M2_MASK, VWMACC_VX, 0x1, 0x0 }, // 10396 |
16388 | | { PseudoVWMACC_VX_M4, VWMACC_VX, 0x2, 0x0 }, // 10397 |
16389 | | { PseudoVWMACC_VX_M4_MASK, VWMACC_VX, 0x2, 0x0 }, // 10398 |
16390 | | { PseudoVWMACC_VX_MF8, VWMACC_VX, 0x5, 0x0 }, // 10399 |
16391 | | { PseudoVWMACC_VX_MF8_MASK, VWMACC_VX, 0x5, 0x0 }, // 10400 |
16392 | | { PseudoVWMACC_VX_MF4, VWMACC_VX, 0x6, 0x0 }, // 10401 |
16393 | | { PseudoVWMACC_VX_MF4_MASK, VWMACC_VX, 0x6, 0x0 }, // 10402 |
16394 | | { PseudoVWMACC_VX_MF2, VWMACC_VX, 0x7, 0x0 }, // 10403 |
16395 | | { PseudoVWMACC_VX_MF2_MASK, VWMACC_VX, 0x7, 0x0 }, // 10404 |
16396 | | { PseudoVWMULSU_VV_M1, VWMULSU_VV, 0x0, 0x0 }, // 10405 |
16397 | | { PseudoVWMULSU_VV_M1_MASK, VWMULSU_VV, 0x0, 0x0 }, // 10406 |
16398 | | { PseudoVWMULSU_VV_M2, VWMULSU_VV, 0x1, 0x0 }, // 10407 |
16399 | | { PseudoVWMULSU_VV_M2_MASK, VWMULSU_VV, 0x1, 0x0 }, // 10408 |
16400 | | { PseudoVWMULSU_VV_M4, VWMULSU_VV, 0x2, 0x0 }, // 10409 |
16401 | | { PseudoVWMULSU_VV_M4_MASK, VWMULSU_VV, 0x2, 0x0 }, // 10410 |
16402 | | { PseudoVWMULSU_VV_MF8, VWMULSU_VV, 0x5, 0x0 }, // 10411 |
16403 | | { PseudoVWMULSU_VV_MF8_MASK, VWMULSU_VV, 0x5, 0x0 }, // 10412 |
16404 | | { PseudoVWMULSU_VV_MF4, VWMULSU_VV, 0x6, 0x0 }, // 10413 |
16405 | | { PseudoVWMULSU_VV_MF4_MASK, VWMULSU_VV, 0x6, 0x0 }, // 10414 |
16406 | | { PseudoVWMULSU_VV_MF2, VWMULSU_VV, 0x7, 0x0 }, // 10415 |
16407 | | { PseudoVWMULSU_VV_MF2_MASK, VWMULSU_VV, 0x7, 0x0 }, // 10416 |
16408 | | { PseudoVWMULSU_VX_M1, VWMULSU_VX, 0x0, 0x0 }, // 10417 |
16409 | | { PseudoVWMULSU_VX_M1_MASK, VWMULSU_VX, 0x0, 0x0 }, // 10418 |
16410 | | { PseudoVWMULSU_VX_M2, VWMULSU_VX, 0x1, 0x0 }, // 10419 |
16411 | | { PseudoVWMULSU_VX_M2_MASK, VWMULSU_VX, 0x1, 0x0 }, // 10420 |
16412 | | { PseudoVWMULSU_VX_M4, VWMULSU_VX, 0x2, 0x0 }, // 10421 |
16413 | | { PseudoVWMULSU_VX_M4_MASK, VWMULSU_VX, 0x2, 0x0 }, // 10422 |
16414 | | { PseudoVWMULSU_VX_MF8, VWMULSU_VX, 0x5, 0x0 }, // 10423 |
16415 | | { PseudoVWMULSU_VX_MF8_MASK, VWMULSU_VX, 0x5, 0x0 }, // 10424 |
16416 | | { PseudoVWMULSU_VX_MF4, VWMULSU_VX, 0x6, 0x0 }, // 10425 |
16417 | | { PseudoVWMULSU_VX_MF4_MASK, VWMULSU_VX, 0x6, 0x0 }, // 10426 |
16418 | | { PseudoVWMULSU_VX_MF2, VWMULSU_VX, 0x7, 0x0 }, // 10427 |
16419 | | { PseudoVWMULSU_VX_MF2_MASK, VWMULSU_VX, 0x7, 0x0 }, // 10428 |
16420 | | { PseudoVWMULU_VV_M1, VWMULU_VV, 0x0, 0x0 }, // 10429 |
16421 | | { PseudoVWMULU_VV_M1_MASK, VWMULU_VV, 0x0, 0x0 }, // 10430 |
16422 | | { PseudoVWMULU_VV_M2, VWMULU_VV, 0x1, 0x0 }, // 10431 |
16423 | | { PseudoVWMULU_VV_M2_MASK, VWMULU_VV, 0x1, 0x0 }, // 10432 |
16424 | | { PseudoVWMULU_VV_M4, VWMULU_VV, 0x2, 0x0 }, // 10433 |
16425 | | { PseudoVWMULU_VV_M4_MASK, VWMULU_VV, 0x2, 0x0 }, // 10434 |
16426 | | { PseudoVWMULU_VV_MF8, VWMULU_VV, 0x5, 0x0 }, // 10435 |
16427 | | { PseudoVWMULU_VV_MF8_MASK, VWMULU_VV, 0x5, 0x0 }, // 10436 |
16428 | | { PseudoVWMULU_VV_MF4, VWMULU_VV, 0x6, 0x0 }, // 10437 |
16429 | | { PseudoVWMULU_VV_MF4_MASK, VWMULU_VV, 0x6, 0x0 }, // 10438 |
16430 | | { PseudoVWMULU_VV_MF2, VWMULU_VV, 0x7, 0x0 }, // 10439 |
16431 | | { PseudoVWMULU_VV_MF2_MASK, VWMULU_VV, 0x7, 0x0 }, // 10440 |
16432 | | { PseudoVWMULU_VX_M1, VWMULU_VX, 0x0, 0x0 }, // 10441 |
16433 | | { PseudoVWMULU_VX_M1_MASK, VWMULU_VX, 0x0, 0x0 }, // 10442 |
16434 | | { PseudoVWMULU_VX_M2, VWMULU_VX, 0x1, 0x0 }, // 10443 |
16435 | | { PseudoVWMULU_VX_M2_MASK, VWMULU_VX, 0x1, 0x0 }, // 10444 |
16436 | | { PseudoVWMULU_VX_M4, VWMULU_VX, 0x2, 0x0 }, // 10445 |
16437 | | { PseudoVWMULU_VX_M4_MASK, VWMULU_VX, 0x2, 0x0 }, // 10446 |
16438 | | { PseudoVWMULU_VX_MF8, VWMULU_VX, 0x5, 0x0 }, // 10447 |
16439 | | { PseudoVWMULU_VX_MF8_MASK, VWMULU_VX, 0x5, 0x0 }, // 10448 |
16440 | | { PseudoVWMULU_VX_MF4, VWMULU_VX, 0x6, 0x0 }, // 10449 |
16441 | | { PseudoVWMULU_VX_MF4_MASK, VWMULU_VX, 0x6, 0x0 }, // 10450 |
16442 | | { PseudoVWMULU_VX_MF2, VWMULU_VX, 0x7, 0x0 }, // 10451 |
16443 | | { PseudoVWMULU_VX_MF2_MASK, VWMULU_VX, 0x7, 0x0 }, // 10452 |
16444 | | { PseudoVWMUL_VV_M1, VWMUL_VV, 0x0, 0x0 }, // 10453 |
16445 | | { PseudoVWMUL_VV_M1_MASK, VWMUL_VV, 0x0, 0x0 }, // 10454 |
16446 | | { PseudoVWMUL_VV_M2, VWMUL_VV, 0x1, 0x0 }, // 10455 |
16447 | | { PseudoVWMUL_VV_M2_MASK, VWMUL_VV, 0x1, 0x0 }, // 10456 |
16448 | | { PseudoVWMUL_VV_M4, VWMUL_VV, 0x2, 0x0 }, // 10457 |
16449 | | { PseudoVWMUL_VV_M4_MASK, VWMUL_VV, 0x2, 0x0 }, // 10458 |
16450 | | { PseudoVWMUL_VV_MF8, VWMUL_VV, 0x5, 0x0 }, // 10459 |
16451 | | { PseudoVWMUL_VV_MF8_MASK, VWMUL_VV, 0x5, 0x0 }, // 10460 |
16452 | | { PseudoVWMUL_VV_MF4, VWMUL_VV, 0x6, 0x0 }, // 10461 |
16453 | | { PseudoVWMUL_VV_MF4_MASK, VWMUL_VV, 0x6, 0x0 }, // 10462 |
16454 | | { PseudoVWMUL_VV_MF2, VWMUL_VV, 0x7, 0x0 }, // 10463 |
16455 | | { PseudoVWMUL_VV_MF2_MASK, VWMUL_VV, 0x7, 0x0 }, // 10464 |
16456 | | { PseudoVWMUL_VX_M1, VWMUL_VX, 0x0, 0x0 }, // 10465 |
16457 | | { PseudoVWMUL_VX_M1_MASK, VWMUL_VX, 0x0, 0x0 }, // 10466 |
16458 | | { PseudoVWMUL_VX_M2, VWMUL_VX, 0x1, 0x0 }, // 10467 |
16459 | | { PseudoVWMUL_VX_M2_MASK, VWMUL_VX, 0x1, 0x0 }, // 10468 |
16460 | | { PseudoVWMUL_VX_M4, VWMUL_VX, 0x2, 0x0 }, // 10469 |
16461 | | { PseudoVWMUL_VX_M4_MASK, VWMUL_VX, 0x2, 0x0 }, // 10470 |
16462 | | { PseudoVWMUL_VX_MF8, VWMUL_VX, 0x5, 0x0 }, // 10471 |
16463 | | { PseudoVWMUL_VX_MF8_MASK, VWMUL_VX, 0x5, 0x0 }, // 10472 |
16464 | | { PseudoVWMUL_VX_MF4, VWMUL_VX, 0x6, 0x0 }, // 10473 |
16465 | | { PseudoVWMUL_VX_MF4_MASK, VWMUL_VX, 0x6, 0x0 }, // 10474 |
16466 | | { PseudoVWMUL_VX_MF2, VWMUL_VX, 0x7, 0x0 }, // 10475 |
16467 | | { PseudoVWMUL_VX_MF2_MASK, VWMUL_VX, 0x7, 0x0 }, // 10476 |
16468 | | { PseudoVWREDSUMU_VS_M1_E8, VWREDSUMU_VS, 0x0, 0x8 }, // 10477 |
16469 | | { PseudoVWREDSUMU_VS_M1_E8_MASK, VWREDSUMU_VS, 0x0, 0x8 }, // 10478 |
16470 | | { PseudoVWREDSUMU_VS_M1_E16, VWREDSUMU_VS, 0x0, 0x10 }, // 10479 |
16471 | | { PseudoVWREDSUMU_VS_M1_E16_MASK, VWREDSUMU_VS, 0x0, 0x10 }, // 10480 |
16472 | | { PseudoVWREDSUMU_VS_M1_E32, VWREDSUMU_VS, 0x0, 0x20 }, // 10481 |
16473 | | { PseudoVWREDSUMU_VS_M1_E32_MASK, VWREDSUMU_VS, 0x0, 0x20 }, // 10482 |
16474 | | { PseudoVWREDSUMU_VS_M2_E8, VWREDSUMU_VS, 0x1, 0x8 }, // 10483 |
16475 | | { PseudoVWREDSUMU_VS_M2_E8_MASK, VWREDSUMU_VS, 0x1, 0x8 }, // 10484 |
16476 | | { PseudoVWREDSUMU_VS_M2_E16, VWREDSUMU_VS, 0x1, 0x10 }, // 10485 |
16477 | | { PseudoVWREDSUMU_VS_M2_E16_MASK, VWREDSUMU_VS, 0x1, 0x10 }, // 10486 |
16478 | | { PseudoVWREDSUMU_VS_M2_E32, VWREDSUMU_VS, 0x1, 0x20 }, // 10487 |
16479 | | { PseudoVWREDSUMU_VS_M2_E32_MASK, VWREDSUMU_VS, 0x1, 0x20 }, // 10488 |
16480 | | { PseudoVWREDSUMU_VS_M4_E8, VWREDSUMU_VS, 0x2, 0x8 }, // 10489 |
16481 | | { PseudoVWREDSUMU_VS_M4_E8_MASK, VWREDSUMU_VS, 0x2, 0x8 }, // 10490 |
16482 | | { PseudoVWREDSUMU_VS_M4_E16, VWREDSUMU_VS, 0x2, 0x10 }, // 10491 |
16483 | | { PseudoVWREDSUMU_VS_M4_E16_MASK, VWREDSUMU_VS, 0x2, 0x10 }, // 10492 |
16484 | | { PseudoVWREDSUMU_VS_M4_E32, VWREDSUMU_VS, 0x2, 0x20 }, // 10493 |
16485 | | { PseudoVWREDSUMU_VS_M4_E32_MASK, VWREDSUMU_VS, 0x2, 0x20 }, // 10494 |
16486 | | { PseudoVWREDSUMU_VS_M8_E8, VWREDSUMU_VS, 0x3, 0x8 }, // 10495 |
16487 | | { PseudoVWREDSUMU_VS_M8_E8_MASK, VWREDSUMU_VS, 0x3, 0x8 }, // 10496 |
16488 | | { PseudoVWREDSUMU_VS_M8_E16, VWREDSUMU_VS, 0x3, 0x10 }, // 10497 |
16489 | | { PseudoVWREDSUMU_VS_M8_E16_MASK, VWREDSUMU_VS, 0x3, 0x10 }, // 10498 |
16490 | | { PseudoVWREDSUMU_VS_M8_E32, VWREDSUMU_VS, 0x3, 0x20 }, // 10499 |
16491 | | { PseudoVWREDSUMU_VS_M8_E32_MASK, VWREDSUMU_VS, 0x3, 0x20 }, // 10500 |
16492 | | { PseudoVWREDSUMU_VS_MF8_E8, VWREDSUMU_VS, 0x5, 0x8 }, // 10501 |
16493 | | { PseudoVWREDSUMU_VS_MF8_E8_MASK, VWREDSUMU_VS, 0x5, 0x8 }, // 10502 |
16494 | | { PseudoVWREDSUMU_VS_MF4_E8, VWREDSUMU_VS, 0x6, 0x8 }, // 10503 |
16495 | | { PseudoVWREDSUMU_VS_MF4_E8_MASK, VWREDSUMU_VS, 0x6, 0x8 }, // 10504 |
16496 | | { PseudoVWREDSUMU_VS_MF4_E16, VWREDSUMU_VS, 0x6, 0x10 }, // 10505 |
16497 | | { PseudoVWREDSUMU_VS_MF4_E16_MASK, VWREDSUMU_VS, 0x6, 0x10 }, // 10506 |
16498 | | { PseudoVWREDSUMU_VS_MF2_E8, VWREDSUMU_VS, 0x7, 0x8 }, // 10507 |
16499 | | { PseudoVWREDSUMU_VS_MF2_E8_MASK, VWREDSUMU_VS, 0x7, 0x8 }, // 10508 |
16500 | | { PseudoVWREDSUMU_VS_MF2_E16, VWREDSUMU_VS, 0x7, 0x10 }, // 10509 |
16501 | | { PseudoVWREDSUMU_VS_MF2_E16_MASK, VWREDSUMU_VS, 0x7, 0x10 }, // 10510 |
16502 | | { PseudoVWREDSUMU_VS_MF2_E32, VWREDSUMU_VS, 0x7, 0x20 }, // 10511 |
16503 | | { PseudoVWREDSUMU_VS_MF2_E32_MASK, VWREDSUMU_VS, 0x7, 0x20 }, // 10512 |
16504 | | { PseudoVWREDSUM_VS_M1_E8, VWREDSUM_VS, 0x0, 0x8 }, // 10513 |
16505 | | { PseudoVWREDSUM_VS_M1_E8_MASK, VWREDSUM_VS, 0x0, 0x8 }, // 10514 |
16506 | | { PseudoVWREDSUM_VS_M1_E16, VWREDSUM_VS, 0x0, 0x10 }, // 10515 |
16507 | | { PseudoVWREDSUM_VS_M1_E16_MASK, VWREDSUM_VS, 0x0, 0x10 }, // 10516 |
16508 | | { PseudoVWREDSUM_VS_M1_E32, VWREDSUM_VS, 0x0, 0x20 }, // 10517 |
16509 | | { PseudoVWREDSUM_VS_M1_E32_MASK, VWREDSUM_VS, 0x0, 0x20 }, // 10518 |
16510 | | { PseudoVWREDSUM_VS_M2_E8, VWREDSUM_VS, 0x1, 0x8 }, // 10519 |
16511 | | { PseudoVWREDSUM_VS_M2_E8_MASK, VWREDSUM_VS, 0x1, 0x8 }, // 10520 |
16512 | | { PseudoVWREDSUM_VS_M2_E16, VWREDSUM_VS, 0x1, 0x10 }, // 10521 |
16513 | | { PseudoVWREDSUM_VS_M2_E16_MASK, VWREDSUM_VS, 0x1, 0x10 }, // 10522 |
16514 | | { PseudoVWREDSUM_VS_M2_E32, VWREDSUM_VS, 0x1, 0x20 }, // 10523 |
16515 | | { PseudoVWREDSUM_VS_M2_E32_MASK, VWREDSUM_VS, 0x1, 0x20 }, // 10524 |
16516 | | { PseudoVWREDSUM_VS_M4_E8, VWREDSUM_VS, 0x2, 0x8 }, // 10525 |
16517 | | { PseudoVWREDSUM_VS_M4_E8_MASK, VWREDSUM_VS, 0x2, 0x8 }, // 10526 |
16518 | | { PseudoVWREDSUM_VS_M4_E16, VWREDSUM_VS, 0x2, 0x10 }, // 10527 |
16519 | | { PseudoVWREDSUM_VS_M4_E16_MASK, VWREDSUM_VS, 0x2, 0x10 }, // 10528 |
16520 | | { PseudoVWREDSUM_VS_M4_E32, VWREDSUM_VS, 0x2, 0x20 }, // 10529 |
16521 | | { PseudoVWREDSUM_VS_M4_E32_MASK, VWREDSUM_VS, 0x2, 0x20 }, // 10530 |
16522 | | { PseudoVWREDSUM_VS_M8_E8, VWREDSUM_VS, 0x3, 0x8 }, // 10531 |
16523 | | { PseudoVWREDSUM_VS_M8_E8_MASK, VWREDSUM_VS, 0x3, 0x8 }, // 10532 |
16524 | | { PseudoVWREDSUM_VS_M8_E16, VWREDSUM_VS, 0x3, 0x10 }, // 10533 |
16525 | | { PseudoVWREDSUM_VS_M8_E16_MASK, VWREDSUM_VS, 0x3, 0x10 }, // 10534 |
16526 | | { PseudoVWREDSUM_VS_M8_E32, VWREDSUM_VS, 0x3, 0x20 }, // 10535 |
16527 | | { PseudoVWREDSUM_VS_M8_E32_MASK, VWREDSUM_VS, 0x3, 0x20 }, // 10536 |
16528 | | { PseudoVWREDSUM_VS_MF8_E8, VWREDSUM_VS, 0x5, 0x8 }, // 10537 |
16529 | | { PseudoVWREDSUM_VS_MF8_E8_MASK, VWREDSUM_VS, 0x5, 0x8 }, // 10538 |
16530 | | { PseudoVWREDSUM_VS_MF4_E8, VWREDSUM_VS, 0x6, 0x8 }, // 10539 |
16531 | | { PseudoVWREDSUM_VS_MF4_E8_MASK, VWREDSUM_VS, 0x6, 0x8 }, // 10540 |
16532 | | { PseudoVWREDSUM_VS_MF4_E16, VWREDSUM_VS, 0x6, 0x10 }, // 10541 |
16533 | | { PseudoVWREDSUM_VS_MF4_E16_MASK, VWREDSUM_VS, 0x6, 0x10 }, // 10542 |
16534 | | { PseudoVWREDSUM_VS_MF2_E8, VWREDSUM_VS, 0x7, 0x8 }, // 10543 |
16535 | | { PseudoVWREDSUM_VS_MF2_E8_MASK, VWREDSUM_VS, 0x7, 0x8 }, // 10544 |
16536 | | { PseudoVWREDSUM_VS_MF2_E16, VWREDSUM_VS, 0x7, 0x10 }, // 10545 |
16537 | | { PseudoVWREDSUM_VS_MF2_E16_MASK, VWREDSUM_VS, 0x7, 0x10 }, // 10546 |
16538 | | { PseudoVWREDSUM_VS_MF2_E32, VWREDSUM_VS, 0x7, 0x20 }, // 10547 |
16539 | | { PseudoVWREDSUM_VS_MF2_E32_MASK, VWREDSUM_VS, 0x7, 0x20 }, // 10548 |
16540 | | { PseudoVWSLL_VI_M1, VWSLL_VI, 0x0, 0x0 }, // 10549 |
16541 | | { PseudoVWSLL_VI_M1_MASK, VWSLL_VI, 0x0, 0x0 }, // 10550 |
16542 | | { PseudoVWSLL_VI_M2, VWSLL_VI, 0x1, 0x0 }, // 10551 |
16543 | | { PseudoVWSLL_VI_M2_MASK, VWSLL_VI, 0x1, 0x0 }, // 10552 |
16544 | | { PseudoVWSLL_VI_M4, VWSLL_VI, 0x2, 0x0 }, // 10553 |
16545 | | { PseudoVWSLL_VI_M4_MASK, VWSLL_VI, 0x2, 0x0 }, // 10554 |
16546 | | { PseudoVWSLL_VI_MF8, VWSLL_VI, 0x5, 0x0 }, // 10555 |
16547 | | { PseudoVWSLL_VI_MF8_MASK, VWSLL_VI, 0x5, 0x0 }, // 10556 |
16548 | | { PseudoVWSLL_VI_MF4, VWSLL_VI, 0x6, 0x0 }, // 10557 |
16549 | | { PseudoVWSLL_VI_MF4_MASK, VWSLL_VI, 0x6, 0x0 }, // 10558 |
16550 | | { PseudoVWSLL_VI_MF2, VWSLL_VI, 0x7, 0x0 }, // 10559 |
16551 | | { PseudoVWSLL_VI_MF2_MASK, VWSLL_VI, 0x7, 0x0 }, // 10560 |
16552 | | { PseudoVWSLL_VV_M1, VWSLL_VV, 0x0, 0x0 }, // 10561 |
16553 | | { PseudoVWSLL_VV_M1_MASK, VWSLL_VV, 0x0, 0x0 }, // 10562 |
16554 | | { PseudoVWSLL_VV_M2, VWSLL_VV, 0x1, 0x0 }, // 10563 |
16555 | | { PseudoVWSLL_VV_M2_MASK, VWSLL_VV, 0x1, 0x0 }, // 10564 |
16556 | | { PseudoVWSLL_VV_M4, VWSLL_VV, 0x2, 0x0 }, // 10565 |
16557 | | { PseudoVWSLL_VV_M4_MASK, VWSLL_VV, 0x2, 0x0 }, // 10566 |
16558 | | { PseudoVWSLL_VV_MF8, VWSLL_VV, 0x5, 0x0 }, // 10567 |
16559 | | { PseudoVWSLL_VV_MF8_MASK, VWSLL_VV, 0x5, 0x0 }, // 10568 |
16560 | | { PseudoVWSLL_VV_MF4, VWSLL_VV, 0x6, 0x0 }, // 10569 |
16561 | | { PseudoVWSLL_VV_MF4_MASK, VWSLL_VV, 0x6, 0x0 }, // 10570 |
16562 | | { PseudoVWSLL_VV_MF2, VWSLL_VV, 0x7, 0x0 }, // 10571 |
16563 | | { PseudoVWSLL_VV_MF2_MASK, VWSLL_VV, 0x7, 0x0 }, // 10572 |
16564 | | { PseudoVWSLL_VX_M1, VWSLL_VX, 0x0, 0x0 }, // 10573 |
16565 | | { PseudoVWSLL_VX_M1_MASK, VWSLL_VX, 0x0, 0x0 }, // 10574 |
16566 | | { PseudoVWSLL_VX_M2, VWSLL_VX, 0x1, 0x0 }, // 10575 |
16567 | | { PseudoVWSLL_VX_M2_MASK, VWSLL_VX, 0x1, 0x0 }, // 10576 |
16568 | | { PseudoVWSLL_VX_M4, VWSLL_VX, 0x2, 0x0 }, // 10577 |
16569 | | { PseudoVWSLL_VX_M4_MASK, VWSLL_VX, 0x2, 0x0 }, // 10578 |
16570 | | { PseudoVWSLL_VX_MF8, VWSLL_VX, 0x5, 0x0 }, // 10579 |
16571 | | { PseudoVWSLL_VX_MF8_MASK, VWSLL_VX, 0x5, 0x0 }, // 10580 |
16572 | | { PseudoVWSLL_VX_MF4, VWSLL_VX, 0x6, 0x0 }, // 10581 |
16573 | | { PseudoVWSLL_VX_MF4_MASK, VWSLL_VX, 0x6, 0x0 }, // 10582 |
16574 | | { PseudoVWSLL_VX_MF2, VWSLL_VX, 0x7, 0x0 }, // 10583 |
16575 | | { PseudoVWSLL_VX_MF2_MASK, VWSLL_VX, 0x7, 0x0 }, // 10584 |
16576 | | { PseudoVWSUBU_VV_M1, VWSUBU_VV, 0x0, 0x0 }, // 10585 |
16577 | | { PseudoVWSUBU_VV_M1_MASK, VWSUBU_VV, 0x0, 0x0 }, // 10586 |
16578 | | { PseudoVWSUBU_VV_M2, VWSUBU_VV, 0x1, 0x0 }, // 10587 |
16579 | | { PseudoVWSUBU_VV_M2_MASK, VWSUBU_VV, 0x1, 0x0 }, // 10588 |
16580 | | { PseudoVWSUBU_VV_M4, VWSUBU_VV, 0x2, 0x0 }, // 10589 |
16581 | | { PseudoVWSUBU_VV_M4_MASK, VWSUBU_VV, 0x2, 0x0 }, // 10590 |
16582 | | { PseudoVWSUBU_VV_MF8, VWSUBU_VV, 0x5, 0x0 }, // 10591 |
16583 | | { PseudoVWSUBU_VV_MF8_MASK, VWSUBU_VV, 0x5, 0x0 }, // 10592 |
16584 | | { PseudoVWSUBU_VV_MF4, VWSUBU_VV, 0x6, 0x0 }, // 10593 |
16585 | | { PseudoVWSUBU_VV_MF4_MASK, VWSUBU_VV, 0x6, 0x0 }, // 10594 |
16586 | | { PseudoVWSUBU_VV_MF2, VWSUBU_VV, 0x7, 0x0 }, // 10595 |
16587 | | { PseudoVWSUBU_VV_MF2_MASK, VWSUBU_VV, 0x7, 0x0 }, // 10596 |
16588 | | { PseudoVWSUBU_VX_M1, VWSUBU_VX, 0x0, 0x0 }, // 10597 |
16589 | | { PseudoVWSUBU_VX_M1_MASK, VWSUBU_VX, 0x0, 0x0 }, // 10598 |
16590 | | { PseudoVWSUBU_VX_M2, VWSUBU_VX, 0x1, 0x0 }, // 10599 |
16591 | | { PseudoVWSUBU_VX_M2_MASK, VWSUBU_VX, 0x1, 0x0 }, // 10600 |
16592 | | { PseudoVWSUBU_VX_M4, VWSUBU_VX, 0x2, 0x0 }, // 10601 |
16593 | | { PseudoVWSUBU_VX_M4_MASK, VWSUBU_VX, 0x2, 0x0 }, // 10602 |
16594 | | { PseudoVWSUBU_VX_MF8, VWSUBU_VX, 0x5, 0x0 }, // 10603 |
16595 | | { PseudoVWSUBU_VX_MF8_MASK, VWSUBU_VX, 0x5, 0x0 }, // 10604 |
16596 | | { PseudoVWSUBU_VX_MF4, VWSUBU_VX, 0x6, 0x0 }, // 10605 |
16597 | | { PseudoVWSUBU_VX_MF4_MASK, VWSUBU_VX, 0x6, 0x0 }, // 10606 |
16598 | | { PseudoVWSUBU_VX_MF2, VWSUBU_VX, 0x7, 0x0 }, // 10607 |
16599 | | { PseudoVWSUBU_VX_MF2_MASK, VWSUBU_VX, 0x7, 0x0 }, // 10608 |
16600 | | { PseudoVWSUBU_WV_M1, VWSUBU_WV, 0x0, 0x0 }, // 10609 |
16601 | | { PseudoVWSUBU_WV_M1_MASK, VWSUBU_WV, 0x0, 0x0 }, // 10610 |
16602 | | { PseudoVWSUBU_WV_M1_MASK_TIED, VWSUBU_WV, 0x0, 0x0 }, // 10611 |
16603 | | { PseudoVWSUBU_WV_M1_TIED, VWSUBU_WV, 0x0, 0x0 }, // 10612 |
16604 | | { PseudoVWSUBU_WV_M2, VWSUBU_WV, 0x1, 0x0 }, // 10613 |
16605 | | { PseudoVWSUBU_WV_M2_MASK, VWSUBU_WV, 0x1, 0x0 }, // 10614 |
16606 | | { PseudoVWSUBU_WV_M2_MASK_TIED, VWSUBU_WV, 0x1, 0x0 }, // 10615 |
16607 | | { PseudoVWSUBU_WV_M2_TIED, VWSUBU_WV, 0x1, 0x0 }, // 10616 |
16608 | | { PseudoVWSUBU_WV_M4, VWSUBU_WV, 0x2, 0x0 }, // 10617 |
16609 | | { PseudoVWSUBU_WV_M4_MASK, VWSUBU_WV, 0x2, 0x0 }, // 10618 |
16610 | | { PseudoVWSUBU_WV_M4_MASK_TIED, VWSUBU_WV, 0x2, 0x0 }, // 10619 |
16611 | | { PseudoVWSUBU_WV_M4_TIED, VWSUBU_WV, 0x2, 0x0 }, // 10620 |
16612 | | { PseudoVWSUBU_WV_MF8, VWSUBU_WV, 0x5, 0x0 }, // 10621 |
16613 | | { PseudoVWSUBU_WV_MF8_MASK, VWSUBU_WV, 0x5, 0x0 }, // 10622 |
16614 | | { PseudoVWSUBU_WV_MF8_MASK_TIED, VWSUBU_WV, 0x5, 0x0 }, // 10623 |
16615 | | { PseudoVWSUBU_WV_MF8_TIED, VWSUBU_WV, 0x5, 0x0 }, // 10624 |
16616 | | { PseudoVWSUBU_WV_MF4, VWSUBU_WV, 0x6, 0x0 }, // 10625 |
16617 | | { PseudoVWSUBU_WV_MF4_MASK, VWSUBU_WV, 0x6, 0x0 }, // 10626 |
16618 | | { PseudoVWSUBU_WV_MF4_MASK_TIED, VWSUBU_WV, 0x6, 0x0 }, // 10627 |
16619 | | { PseudoVWSUBU_WV_MF4_TIED, VWSUBU_WV, 0x6, 0x0 }, // 10628 |
16620 | | { PseudoVWSUBU_WV_MF2, VWSUBU_WV, 0x7, 0x0 }, // 10629 |
16621 | | { PseudoVWSUBU_WV_MF2_MASK, VWSUBU_WV, 0x7, 0x0 }, // 10630 |
16622 | | { PseudoVWSUBU_WV_MF2_MASK_TIED, VWSUBU_WV, 0x7, 0x0 }, // 10631 |
16623 | | { PseudoVWSUBU_WV_MF2_TIED, VWSUBU_WV, 0x7, 0x0 }, // 10632 |
16624 | | { PseudoVWSUBU_WX_M1, VWSUBU_WX, 0x0, 0x0 }, // 10633 |
16625 | | { PseudoVWSUBU_WX_M1_MASK, VWSUBU_WX, 0x0, 0x0 }, // 10634 |
16626 | | { PseudoVWSUBU_WX_M2, VWSUBU_WX, 0x1, 0x0 }, // 10635 |
16627 | | { PseudoVWSUBU_WX_M2_MASK, VWSUBU_WX, 0x1, 0x0 }, // 10636 |
16628 | | { PseudoVWSUBU_WX_M4, VWSUBU_WX, 0x2, 0x0 }, // 10637 |
16629 | | { PseudoVWSUBU_WX_M4_MASK, VWSUBU_WX, 0x2, 0x0 }, // 10638 |
16630 | | { PseudoVWSUBU_WX_MF8, VWSUBU_WX, 0x5, 0x0 }, // 10639 |
16631 | | { PseudoVWSUBU_WX_MF8_MASK, VWSUBU_WX, 0x5, 0x0 }, // 10640 |
16632 | | { PseudoVWSUBU_WX_MF4, VWSUBU_WX, 0x6, 0x0 }, // 10641 |
16633 | | { PseudoVWSUBU_WX_MF4_MASK, VWSUBU_WX, 0x6, 0x0 }, // 10642 |
16634 | | { PseudoVWSUBU_WX_MF2, VWSUBU_WX, 0x7, 0x0 }, // 10643 |
16635 | | { PseudoVWSUBU_WX_MF2_MASK, VWSUBU_WX, 0x7, 0x0 }, // 10644 |
16636 | | { PseudoVWSUB_VV_M1, VWSUB_VV, 0x0, 0x0 }, // 10645 |
16637 | | { PseudoVWSUB_VV_M1_MASK, VWSUB_VV, 0x0, 0x0 }, // 10646 |
16638 | | { PseudoVWSUB_VV_M2, VWSUB_VV, 0x1, 0x0 }, // 10647 |
16639 | | { PseudoVWSUB_VV_M2_MASK, VWSUB_VV, 0x1, 0x0 }, // 10648 |
16640 | | { PseudoVWSUB_VV_M4, VWSUB_VV, 0x2, 0x0 }, // 10649 |
16641 | | { PseudoVWSUB_VV_M4_MASK, VWSUB_VV, 0x2, 0x0 }, // 10650 |
16642 | | { PseudoVWSUB_VV_MF8, VWSUB_VV, 0x5, 0x0 }, // 10651 |
16643 | | { PseudoVWSUB_VV_MF8_MASK, VWSUB_VV, 0x5, 0x0 }, // 10652 |
16644 | | { PseudoVWSUB_VV_MF4, VWSUB_VV, 0x6, 0x0 }, // 10653 |
16645 | | { PseudoVWSUB_VV_MF4_MASK, VWSUB_VV, 0x6, 0x0 }, // 10654 |
16646 | | { PseudoVWSUB_VV_MF2, VWSUB_VV, 0x7, 0x0 }, // 10655 |
16647 | | { PseudoVWSUB_VV_MF2_MASK, VWSUB_VV, 0x7, 0x0 }, // 10656 |
16648 | | { PseudoVWSUB_VX_M1, VWSUB_VX, 0x0, 0x0 }, // 10657 |
16649 | | { PseudoVWSUB_VX_M1_MASK, VWSUB_VX, 0x0, 0x0 }, // 10658 |
16650 | | { PseudoVWSUB_VX_M2, VWSUB_VX, 0x1, 0x0 }, // 10659 |
16651 | | { PseudoVWSUB_VX_M2_MASK, VWSUB_VX, 0x1, 0x0 }, // 10660 |
16652 | | { PseudoVWSUB_VX_M4, VWSUB_VX, 0x2, 0x0 }, // 10661 |
16653 | | { PseudoVWSUB_VX_M4_MASK, VWSUB_VX, 0x2, 0x0 }, // 10662 |
16654 | | { PseudoVWSUB_VX_MF8, VWSUB_VX, 0x5, 0x0 }, // 10663 |
16655 | | { PseudoVWSUB_VX_MF8_MASK, VWSUB_VX, 0x5, 0x0 }, // 10664 |
16656 | | { PseudoVWSUB_VX_MF4, VWSUB_VX, 0x6, 0x0 }, // 10665 |
16657 | | { PseudoVWSUB_VX_MF4_MASK, VWSUB_VX, 0x6, 0x0 }, // 10666 |
16658 | | { PseudoVWSUB_VX_MF2, VWSUB_VX, 0x7, 0x0 }, // 10667 |
16659 | | { PseudoVWSUB_VX_MF2_MASK, VWSUB_VX, 0x7, 0x0 }, // 10668 |
16660 | | { PseudoVWSUB_WV_M1, VWSUB_WV, 0x0, 0x0 }, // 10669 |
16661 | | { PseudoVWSUB_WV_M1_MASK, VWSUB_WV, 0x0, 0x0 }, // 10670 |
16662 | | { PseudoVWSUB_WV_M1_MASK_TIED, VWSUB_WV, 0x0, 0x0 }, // 10671 |
16663 | | { PseudoVWSUB_WV_M1_TIED, VWSUB_WV, 0x0, 0x0 }, // 10672 |
16664 | | { PseudoVWSUB_WV_M2, VWSUB_WV, 0x1, 0x0 }, // 10673 |
16665 | | { PseudoVWSUB_WV_M2_MASK, VWSUB_WV, 0x1, 0x0 }, // 10674 |
16666 | | { PseudoVWSUB_WV_M2_MASK_TIED, VWSUB_WV, 0x1, 0x0 }, // 10675 |
16667 | | { PseudoVWSUB_WV_M2_TIED, VWSUB_WV, 0x1, 0x0 }, // 10676 |
16668 | | { PseudoVWSUB_WV_M4, VWSUB_WV, 0x2, 0x0 }, // 10677 |
16669 | | { PseudoVWSUB_WV_M4_MASK, VWSUB_WV, 0x2, 0x0 }, // 10678 |
16670 | | { PseudoVWSUB_WV_M4_MASK_TIED, VWSUB_WV, 0x2, 0x0 }, // 10679 |
16671 | | { PseudoVWSUB_WV_M4_TIED, VWSUB_WV, 0x2, 0x0 }, // 10680 |
16672 | | { PseudoVWSUB_WV_MF8, VWSUB_WV, 0x5, 0x0 }, // 10681 |
16673 | | { PseudoVWSUB_WV_MF8_MASK, VWSUB_WV, 0x5, 0x0 }, // 10682 |
16674 | | { PseudoVWSUB_WV_MF8_MASK_TIED, VWSUB_WV, 0x5, 0x0 }, // 10683 |
16675 | | { PseudoVWSUB_WV_MF8_TIED, VWSUB_WV, 0x5, 0x0 }, // 10684 |
16676 | | { PseudoVWSUB_WV_MF4, VWSUB_WV, 0x6, 0x0 }, // 10685 |
16677 | | { PseudoVWSUB_WV_MF4_MASK, VWSUB_WV, 0x6, 0x0 }, // 10686 |
16678 | | { PseudoVWSUB_WV_MF4_MASK_TIED, VWSUB_WV, 0x6, 0x0 }, // 10687 |
16679 | | { PseudoVWSUB_WV_MF4_TIED, VWSUB_WV, 0x6, 0x0 }, // 10688 |
16680 | | { PseudoVWSUB_WV_MF2, VWSUB_WV, 0x7, 0x0 }, // 10689 |
16681 | | { PseudoVWSUB_WV_MF2_MASK, VWSUB_WV, 0x7, 0x0 }, // 10690 |
16682 | | { PseudoVWSUB_WV_MF2_MASK_TIED, VWSUB_WV, 0x7, 0x0 }, // 10691 |
16683 | | { PseudoVWSUB_WV_MF2_TIED, VWSUB_WV, 0x7, 0x0 }, // 10692 |
16684 | | { PseudoVWSUB_WX_M1, VWSUB_WX, 0x0, 0x0 }, // 10693 |
16685 | | { PseudoVWSUB_WX_M1_MASK, VWSUB_WX, 0x0, 0x0 }, // 10694 |
16686 | | { PseudoVWSUB_WX_M2, VWSUB_WX, 0x1, 0x0 }, // 10695 |
16687 | | { PseudoVWSUB_WX_M2_MASK, VWSUB_WX, 0x1, 0x0 }, // 10696 |
16688 | | { PseudoVWSUB_WX_M4, VWSUB_WX, 0x2, 0x0 }, // 10697 |
16689 | | { PseudoVWSUB_WX_M4_MASK, VWSUB_WX, 0x2, 0x0 }, // 10698 |
16690 | | { PseudoVWSUB_WX_MF8, VWSUB_WX, 0x5, 0x0 }, // 10699 |
16691 | | { PseudoVWSUB_WX_MF8_MASK, VWSUB_WX, 0x5, 0x0 }, // 10700 |
16692 | | { PseudoVWSUB_WX_MF4, VWSUB_WX, 0x6, 0x0 }, // 10701 |
16693 | | { PseudoVWSUB_WX_MF4_MASK, VWSUB_WX, 0x6, 0x0 }, // 10702 |
16694 | | { PseudoVWSUB_WX_MF2, VWSUB_WX, 0x7, 0x0 }, // 10703 |
16695 | | { PseudoVWSUB_WX_MF2_MASK, VWSUB_WX, 0x7, 0x0 }, // 10704 |
16696 | | { PseudoVXOR_VI_M1, VXOR_VI, 0x0, 0x0 }, // 10705 |
16697 | | { PseudoVXOR_VI_M1_MASK, VXOR_VI, 0x0, 0x0 }, // 10706 |
16698 | | { PseudoVXOR_VI_M2, VXOR_VI, 0x1, 0x0 }, // 10707 |
16699 | | { PseudoVXOR_VI_M2_MASK, VXOR_VI, 0x1, 0x0 }, // 10708 |
16700 | | { PseudoVXOR_VI_M4, VXOR_VI, 0x2, 0x0 }, // 10709 |
16701 | | { PseudoVXOR_VI_M4_MASK, VXOR_VI, 0x2, 0x0 }, // 10710 |
16702 | | { PseudoVXOR_VI_M8, VXOR_VI, 0x3, 0x0 }, // 10711 |
16703 | | { PseudoVXOR_VI_M8_MASK, VXOR_VI, 0x3, 0x0 }, // 10712 |
16704 | | { PseudoVXOR_VI_MF8, VXOR_VI, 0x5, 0x0 }, // 10713 |
16705 | | { PseudoVXOR_VI_MF8_MASK, VXOR_VI, 0x5, 0x0 }, // 10714 |
16706 | | { PseudoVXOR_VI_MF4, VXOR_VI, 0x6, 0x0 }, // 10715 |
16707 | | { PseudoVXOR_VI_MF4_MASK, VXOR_VI, 0x6, 0x0 }, // 10716 |
16708 | | { PseudoVXOR_VI_MF2, VXOR_VI, 0x7, 0x0 }, // 10717 |
16709 | | { PseudoVXOR_VI_MF2_MASK, VXOR_VI, 0x7, 0x0 }, // 10718 |
16710 | | { PseudoVXOR_VV_M1, VXOR_VV, 0x0, 0x0 }, // 10719 |
16711 | | { PseudoVXOR_VV_M1_MASK, VXOR_VV, 0x0, 0x0 }, // 10720 |
16712 | | { PseudoVXOR_VV_M2, VXOR_VV, 0x1, 0x0 }, // 10721 |
16713 | | { PseudoVXOR_VV_M2_MASK, VXOR_VV, 0x1, 0x0 }, // 10722 |
16714 | | { PseudoVXOR_VV_M4, VXOR_VV, 0x2, 0x0 }, // 10723 |
16715 | | { PseudoVXOR_VV_M4_MASK, VXOR_VV, 0x2, 0x0 }, // 10724 |
16716 | | { PseudoVXOR_VV_M8, VXOR_VV, 0x3, 0x0 }, // 10725 |
16717 | | { PseudoVXOR_VV_M8_MASK, VXOR_VV, 0x3, 0x0 }, // 10726 |
16718 | | { PseudoVXOR_VV_MF8, VXOR_VV, 0x5, 0x0 }, // 10727 |
16719 | | { PseudoVXOR_VV_MF8_MASK, VXOR_VV, 0x5, 0x0 }, // 10728 |
16720 | | { PseudoVXOR_VV_MF4, VXOR_VV, 0x6, 0x0 }, // 10729 |
16721 | | { PseudoVXOR_VV_MF4_MASK, VXOR_VV, 0x6, 0x0 }, // 10730 |
16722 | | { PseudoVXOR_VV_MF2, VXOR_VV, 0x7, 0x0 }, // 10731 |
16723 | | { PseudoVXOR_VV_MF2_MASK, VXOR_VV, 0x7, 0x0 }, // 10732 |
16724 | | { PseudoVXOR_VX_M1, VXOR_VX, 0x0, 0x0 }, // 10733 |
16725 | | { PseudoVXOR_VX_M1_MASK, VXOR_VX, 0x0, 0x0 }, // 10734 |
16726 | | { PseudoVXOR_VX_M2, VXOR_VX, 0x1, 0x0 }, // 10735 |
16727 | | { PseudoVXOR_VX_M2_MASK, VXOR_VX, 0x1, 0x0 }, // 10736 |
16728 | | { PseudoVXOR_VX_M4, VXOR_VX, 0x2, 0x0 }, // 10737 |
16729 | | { PseudoVXOR_VX_M4_MASK, VXOR_VX, 0x2, 0x0 }, // 10738 |
16730 | | { PseudoVXOR_VX_M8, VXOR_VX, 0x3, 0x0 }, // 10739 |
16731 | | { PseudoVXOR_VX_M8_MASK, VXOR_VX, 0x3, 0x0 }, // 10740 |
16732 | | { PseudoVXOR_VX_MF8, VXOR_VX, 0x5, 0x0 }, // 10741 |
16733 | | { PseudoVXOR_VX_MF8_MASK, VXOR_VX, 0x5, 0x0 }, // 10742 |
16734 | | { PseudoVXOR_VX_MF4, VXOR_VX, 0x6, 0x0 }, // 10743 |
16735 | | { PseudoVXOR_VX_MF4_MASK, VXOR_VX, 0x6, 0x0 }, // 10744 |
16736 | | { PseudoVXOR_VX_MF2, VXOR_VX, 0x7, 0x0 }, // 10745 |
16737 | | { PseudoVXOR_VX_MF2_MASK, VXOR_VX, 0x7, 0x0 }, // 10746 |
16738 | | { PseudoVZEXT_VF2_M1, VZEXT_VF2, 0x0, 0x0 }, // 10747 |
16739 | | { PseudoVZEXT_VF2_M1_MASK, VZEXT_VF2, 0x0, 0x0 }, // 10748 |
16740 | | { PseudoVZEXT_VF2_M2, VZEXT_VF2, 0x1, 0x0 }, // 10749 |
16741 | | { PseudoVZEXT_VF2_M2_MASK, VZEXT_VF2, 0x1, 0x0 }, // 10750 |
16742 | | { PseudoVZEXT_VF2_M4, VZEXT_VF2, 0x2, 0x0 }, // 10751 |
16743 | | { PseudoVZEXT_VF2_M4_MASK, VZEXT_VF2, 0x2, 0x0 }, // 10752 |
16744 | | { PseudoVZEXT_VF2_M8, VZEXT_VF2, 0x3, 0x0 }, // 10753 |
16745 | | { PseudoVZEXT_VF2_M8_MASK, VZEXT_VF2, 0x3, 0x0 }, // 10754 |
16746 | | { PseudoVZEXT_VF2_MF4, VZEXT_VF2, 0x6, 0x0 }, // 10755 |
16747 | | { PseudoVZEXT_VF2_MF4_MASK, VZEXT_VF2, 0x6, 0x0 }, // 10756 |
16748 | | { PseudoVZEXT_VF2_MF2, VZEXT_VF2, 0x7, 0x0 }, // 10757 |
16749 | | { PseudoVZEXT_VF2_MF2_MASK, VZEXT_VF2, 0x7, 0x0 }, // 10758 |
16750 | | { PseudoVZEXT_VF4_M1, VZEXT_VF4, 0x0, 0x0 }, // 10759 |
16751 | | { PseudoVZEXT_VF4_M1_MASK, VZEXT_VF4, 0x0, 0x0 }, // 10760 |
16752 | | { PseudoVZEXT_VF4_M2, VZEXT_VF4, 0x1, 0x0 }, // 10761 |
16753 | | { PseudoVZEXT_VF4_M2_MASK, VZEXT_VF4, 0x1, 0x0 }, // 10762 |
16754 | | { PseudoVZEXT_VF4_M4, VZEXT_VF4, 0x2, 0x0 }, // 10763 |
16755 | | { PseudoVZEXT_VF4_M4_MASK, VZEXT_VF4, 0x2, 0x0 }, // 10764 |
16756 | | { PseudoVZEXT_VF4_M8, VZEXT_VF4, 0x3, 0x0 }, // 10765 |
16757 | | { PseudoVZEXT_VF4_M8_MASK, VZEXT_VF4, 0x3, 0x0 }, // 10766 |
16758 | | { PseudoVZEXT_VF4_MF2, VZEXT_VF4, 0x7, 0x0 }, // 10767 |
16759 | | { PseudoVZEXT_VF4_MF2_MASK, VZEXT_VF4, 0x7, 0x0 }, // 10768 |
16760 | | { PseudoVZEXT_VF8_M1, VZEXT_VF8, 0x0, 0x0 }, // 10769 |
16761 | | { PseudoVZEXT_VF8_M1_MASK, VZEXT_VF8, 0x0, 0x0 }, // 10770 |
16762 | | { PseudoVZEXT_VF8_M2, VZEXT_VF8, 0x1, 0x0 }, // 10771 |
16763 | | { PseudoVZEXT_VF8_M2_MASK, VZEXT_VF8, 0x1, 0x0 }, // 10772 |
16764 | | { PseudoVZEXT_VF8_M4, VZEXT_VF8, 0x2, 0x0 }, // 10773 |
16765 | | { PseudoVZEXT_VF8_M4_MASK, VZEXT_VF8, 0x2, 0x0 }, // 10774 |
16766 | | { PseudoVZEXT_VF8_M8, VZEXT_VF8, 0x3, 0x0 }, // 10775 |
16767 | | { PseudoVZEXT_VF8_M8_MASK, VZEXT_VF8, 0x3, 0x0 }, // 10776 |
16768 | | }; |
16769 | | |
16770 | | const RISCV_PseudoInfo *RISCV_getBaseInfo(unsigned BaseInstr, uint8_t VLMul, uint8_t SEW) { |
16771 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), BaseInstrVLMulSEW); |
16772 | | if (i == -1) |
16773 | | return NULL; |
16774 | | else |
16775 | | return &RISCVVInversePseudosTable[Index[i].index]; |
16776 | | } |
16777 | | |
16778 | | #endif |
16779 | | |
16780 | | #ifdef GET_RISCVVLETable_IMPL |
16781 | | static const RISCV_VLEPseudo RISCVVLETable[] = { |
16782 | | { 0x0, 0x0, 0x0, 0x0, 0x0, PseudoVLM_V_B8 }, // 0 |
16783 | | { 0x0, 0x0, 0x0, 0x0, 0x1, PseudoVLM_V_B16 }, // 1 |
16784 | | { 0x0, 0x0, 0x0, 0x0, 0x2, PseudoVLM_V_B32 }, // 2 |
16785 | | { 0x0, 0x0, 0x0, 0x0, 0x3, PseudoVLM_V_B64 }, // 3 |
16786 | | { 0x0, 0x0, 0x0, 0x0, 0x5, PseudoVLM_V_B1 }, // 4 |
16787 | | { 0x0, 0x0, 0x0, 0x0, 0x6, PseudoVLM_V_B2 }, // 5 |
16788 | | { 0x0, 0x0, 0x0, 0x0, 0x7, PseudoVLM_V_B4 }, // 6 |
16789 | | { 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLE8_V_M1 }, // 7 |
16790 | | { 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLE8_V_M2 }, // 8 |
16791 | | { 0x0, 0x0, 0x0, 0x3, 0x2, PseudoVLE8_V_M4 }, // 9 |
16792 | | { 0x0, 0x0, 0x0, 0x3, 0x3, PseudoVLE8_V_M8 }, // 10 |
16793 | | { 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLE8_V_MF8 }, // 11 |
16794 | | { 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLE8_V_MF4 }, // 12 |
16795 | | { 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLE8_V_MF2 }, // 13 |
16796 | | { 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLE16_V_M1 }, // 14 |
16797 | | { 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLE16_V_M2 }, // 15 |
16798 | | { 0x0, 0x0, 0x0, 0x4, 0x2, PseudoVLE16_V_M4 }, // 16 |
16799 | | { 0x0, 0x0, 0x0, 0x4, 0x3, PseudoVLE16_V_M8 }, // 17 |
16800 | | { 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLE16_V_MF4 }, // 18 |
16801 | | { 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLE16_V_MF2 }, // 19 |
16802 | | { 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLE32_V_M1 }, // 20 |
16803 | | { 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLE32_V_M2 }, // 21 |
16804 | | { 0x0, 0x0, 0x0, 0x5, 0x2, PseudoVLE32_V_M4 }, // 22 |
16805 | | { 0x0, 0x0, 0x0, 0x5, 0x3, PseudoVLE32_V_M8 }, // 23 |
16806 | | { 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLE32_V_MF2 }, // 24 |
16807 | | { 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLE64_V_M1 }, // 25 |
16808 | | { 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLE64_V_M2 }, // 26 |
16809 | | { 0x0, 0x0, 0x0, 0x6, 0x2, PseudoVLE64_V_M4 }, // 27 |
16810 | | { 0x0, 0x0, 0x0, 0x6, 0x3, PseudoVLE64_V_M8 }, // 28 |
16811 | | { 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLE8FF_V_M1 }, // 29 |
16812 | | { 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLE8FF_V_M2 }, // 30 |
16813 | | { 0x0, 0x0, 0x1, 0x3, 0x2, PseudoVLE8FF_V_M4 }, // 31 |
16814 | | { 0x0, 0x0, 0x1, 0x3, 0x3, PseudoVLE8FF_V_M8 }, // 32 |
16815 | | { 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLE8FF_V_MF8 }, // 33 |
16816 | | { 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLE8FF_V_MF4 }, // 34 |
16817 | | { 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLE8FF_V_MF2 }, // 35 |
16818 | | { 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLE16FF_V_M1 }, // 36 |
16819 | | { 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLE16FF_V_M2 }, // 37 |
16820 | | { 0x0, 0x0, 0x1, 0x4, 0x2, PseudoVLE16FF_V_M4 }, // 38 |
16821 | | { 0x0, 0x0, 0x1, 0x4, 0x3, PseudoVLE16FF_V_M8 }, // 39 |
16822 | | { 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLE16FF_V_MF4 }, // 40 |
16823 | | { 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLE16FF_V_MF2 }, // 41 |
16824 | | { 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLE32FF_V_M1 }, // 42 |
16825 | | { 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLE32FF_V_M2 }, // 43 |
16826 | | { 0x0, 0x0, 0x1, 0x5, 0x2, PseudoVLE32FF_V_M4 }, // 44 |
16827 | | { 0x0, 0x0, 0x1, 0x5, 0x3, PseudoVLE32FF_V_M8 }, // 45 |
16828 | | { 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLE32FF_V_MF2 }, // 46 |
16829 | | { 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLE64FF_V_M1 }, // 47 |
16830 | | { 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLE64FF_V_M2 }, // 48 |
16831 | | { 0x0, 0x0, 0x1, 0x6, 0x2, PseudoVLE64FF_V_M4 }, // 49 |
16832 | | { 0x0, 0x0, 0x1, 0x6, 0x3, PseudoVLE64FF_V_M8 }, // 50 |
16833 | | { 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSE8_V_M1 }, // 51 |
16834 | | { 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSE8_V_M2 }, // 52 |
16835 | | { 0x0, 0x1, 0x0, 0x3, 0x2, PseudoVLSE8_V_M4 }, // 53 |
16836 | | { 0x0, 0x1, 0x0, 0x3, 0x3, PseudoVLSE8_V_M8 }, // 54 |
16837 | | { 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSE8_V_MF8 }, // 55 |
16838 | | { 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSE8_V_MF4 }, // 56 |
16839 | | { 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSE8_V_MF2 }, // 57 |
16840 | | { 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSE16_V_M1 }, // 58 |
16841 | | { 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSE16_V_M2 }, // 59 |
16842 | | { 0x0, 0x1, 0x0, 0x4, 0x2, PseudoVLSE16_V_M4 }, // 60 |
16843 | | { 0x0, 0x1, 0x0, 0x4, 0x3, PseudoVLSE16_V_M8 }, // 61 |
16844 | | { 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSE16_V_MF4 }, // 62 |
16845 | | { 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSE16_V_MF2 }, // 63 |
16846 | | { 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSE32_V_M1 }, // 64 |
16847 | | { 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSE32_V_M2 }, // 65 |
16848 | | { 0x0, 0x1, 0x0, 0x5, 0x2, PseudoVLSE32_V_M4 }, // 66 |
16849 | | { 0x0, 0x1, 0x0, 0x5, 0x3, PseudoVLSE32_V_M8 }, // 67 |
16850 | | { 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSE32_V_MF2 }, // 68 |
16851 | | { 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSE64_V_M1 }, // 69 |
16852 | | { 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSE64_V_M2 }, // 70 |
16853 | | { 0x0, 0x1, 0x0, 0x6, 0x2, PseudoVLSE64_V_M4 }, // 71 |
16854 | | { 0x0, 0x1, 0x0, 0x6, 0x3, PseudoVLSE64_V_M8 }, // 72 |
16855 | | { 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLE8_V_M1_MASK }, // 73 |
16856 | | { 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLE8_V_M2_MASK }, // 74 |
16857 | | { 0x1, 0x0, 0x0, 0x3, 0x2, PseudoVLE8_V_M4_MASK }, // 75 |
16858 | | { 0x1, 0x0, 0x0, 0x3, 0x3, PseudoVLE8_V_M8_MASK }, // 76 |
16859 | | { 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLE8_V_MF8_MASK }, // 77 |
16860 | | { 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLE8_V_MF4_MASK }, // 78 |
16861 | | { 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLE8_V_MF2_MASK }, // 79 |
16862 | | { 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLE16_V_M1_MASK }, // 80 |
16863 | | { 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLE16_V_M2_MASK }, // 81 |
16864 | | { 0x1, 0x0, 0x0, 0x4, 0x2, PseudoVLE16_V_M4_MASK }, // 82 |
16865 | | { 0x1, 0x0, 0x0, 0x4, 0x3, PseudoVLE16_V_M8_MASK }, // 83 |
16866 | | { 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLE16_V_MF4_MASK }, // 84 |
16867 | | { 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLE16_V_MF2_MASK }, // 85 |
16868 | | { 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLE32_V_M1_MASK }, // 86 |
16869 | | { 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLE32_V_M2_MASK }, // 87 |
16870 | | { 0x1, 0x0, 0x0, 0x5, 0x2, PseudoVLE32_V_M4_MASK }, // 88 |
16871 | | { 0x1, 0x0, 0x0, 0x5, 0x3, PseudoVLE32_V_M8_MASK }, // 89 |
16872 | | { 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLE32_V_MF2_MASK }, // 90 |
16873 | | { 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLE64_V_M1_MASK }, // 91 |
16874 | | { 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLE64_V_M2_MASK }, // 92 |
16875 | | { 0x1, 0x0, 0x0, 0x6, 0x2, PseudoVLE64_V_M4_MASK }, // 93 |
16876 | | { 0x1, 0x0, 0x0, 0x6, 0x3, PseudoVLE64_V_M8_MASK }, // 94 |
16877 | | { 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLE8FF_V_M1_MASK }, // 95 |
16878 | | { 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLE8FF_V_M2_MASK }, // 96 |
16879 | | { 0x1, 0x0, 0x1, 0x3, 0x2, PseudoVLE8FF_V_M4_MASK }, // 97 |
16880 | | { 0x1, 0x0, 0x1, 0x3, 0x3, PseudoVLE8FF_V_M8_MASK }, // 98 |
16881 | | { 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLE8FF_V_MF8_MASK }, // 99 |
16882 | | { 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLE8FF_V_MF4_MASK }, // 100 |
16883 | | { 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLE8FF_V_MF2_MASK }, // 101 |
16884 | | { 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLE16FF_V_M1_MASK }, // 102 |
16885 | | { 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLE16FF_V_M2_MASK }, // 103 |
16886 | | { 0x1, 0x0, 0x1, 0x4, 0x2, PseudoVLE16FF_V_M4_MASK }, // 104 |
16887 | | { 0x1, 0x0, 0x1, 0x4, 0x3, PseudoVLE16FF_V_M8_MASK }, // 105 |
16888 | | { 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLE16FF_V_MF4_MASK }, // 106 |
16889 | | { 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLE16FF_V_MF2_MASK }, // 107 |
16890 | | { 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLE32FF_V_M1_MASK }, // 108 |
16891 | | { 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLE32FF_V_M2_MASK }, // 109 |
16892 | | { 0x1, 0x0, 0x1, 0x5, 0x2, PseudoVLE32FF_V_M4_MASK }, // 110 |
16893 | | { 0x1, 0x0, 0x1, 0x5, 0x3, PseudoVLE32FF_V_M8_MASK }, // 111 |
16894 | | { 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLE32FF_V_MF2_MASK }, // 112 |
16895 | | { 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLE64FF_V_M1_MASK }, // 113 |
16896 | | { 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLE64FF_V_M2_MASK }, // 114 |
16897 | | { 0x1, 0x0, 0x1, 0x6, 0x2, PseudoVLE64FF_V_M4_MASK }, // 115 |
16898 | | { 0x1, 0x0, 0x1, 0x6, 0x3, PseudoVLE64FF_V_M8_MASK }, // 116 |
16899 | | { 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSE8_V_M1_MASK }, // 117 |
16900 | | { 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSE8_V_M2_MASK }, // 118 |
16901 | | { 0x1, 0x1, 0x0, 0x3, 0x2, PseudoVLSE8_V_M4_MASK }, // 119 |
16902 | | { 0x1, 0x1, 0x0, 0x3, 0x3, PseudoVLSE8_V_M8_MASK }, // 120 |
16903 | | { 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSE8_V_MF8_MASK }, // 121 |
16904 | | { 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSE8_V_MF4_MASK }, // 122 |
16905 | | { 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSE8_V_MF2_MASK }, // 123 |
16906 | | { 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSE16_V_M1_MASK }, // 124 |
16907 | | { 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSE16_V_M2_MASK }, // 125 |
16908 | | { 0x1, 0x1, 0x0, 0x4, 0x2, PseudoVLSE16_V_M4_MASK }, // 126 |
16909 | | { 0x1, 0x1, 0x0, 0x4, 0x3, PseudoVLSE16_V_M8_MASK }, // 127 |
16910 | | { 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSE16_V_MF4_MASK }, // 128 |
16911 | | { 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSE16_V_MF2_MASK }, // 129 |
16912 | | { 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSE32_V_M1_MASK }, // 130 |
16913 | | { 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSE32_V_M2_MASK }, // 131 |
16914 | | { 0x1, 0x1, 0x0, 0x5, 0x2, PseudoVLSE32_V_M4_MASK }, // 132 |
16915 | | { 0x1, 0x1, 0x0, 0x5, 0x3, PseudoVLSE32_V_M8_MASK }, // 133 |
16916 | | { 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSE32_V_MF2_MASK }, // 134 |
16917 | | { 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSE64_V_M1_MASK }, // 135 |
16918 | | { 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSE64_V_M2_MASK }, // 136 |
16919 | | { 0x1, 0x1, 0x0, 0x6, 0x2, PseudoVLSE64_V_M4_MASK }, // 137 |
16920 | | { 0x1, 0x1, 0x0, 0x6, 0x3, PseudoVLSE64_V_M8_MASK }, // 138 |
16921 | | }; |
16922 | | |
16923 | | const RISCV_VLEPseudo *RISCV_getVLEPseudo(uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL) { |
16924 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), MaskedStridedFFLog2SEWLMUL); |
16925 | | if (i == -1) |
16926 | | return NULL; |
16927 | | else |
16928 | | return &RISCVVLETable[Index[i].index]; |
16929 | | } |
16930 | | |
16931 | | #endif |
16932 | | |
16933 | | #ifdef GET_RISCVVLSEGTable_IMPL |
16934 | | static const RISCV_VLSEGPseudo RISCVVLSEGTable[] = { |
16935 | | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG2E8_V_M1 }, // 0 |
16936 | | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG2E8_V_M2 }, // 1 |
16937 | | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x2, PseudoVLSEG2E8_V_M4 }, // 2 |
16938 | | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG2E8_V_MF8 }, // 3 |
16939 | | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG2E8_V_MF4 }, // 4 |
16940 | | { 0x2, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG2E8_V_MF2 }, // 5 |
16941 | | { 0x2, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG2E16_V_M1 }, // 6 |
16942 | | { 0x2, 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG2E16_V_M2 }, // 7 |
16943 | | { 0x2, 0x0, 0x0, 0x0, 0x4, 0x2, PseudoVLSEG2E16_V_M4 }, // 8 |
16944 | | { 0x2, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG2E16_V_MF4 }, // 9 |
16945 | | { 0x2, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG2E16_V_MF2 }, // 10 |
16946 | | { 0x2, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG2E32_V_M1 }, // 11 |
16947 | | { 0x2, 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG2E32_V_M2 }, // 12 |
16948 | | { 0x2, 0x0, 0x0, 0x0, 0x5, 0x2, PseudoVLSEG2E32_V_M4 }, // 13 |
16949 | | { 0x2, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG2E32_V_MF2 }, // 14 |
16950 | | { 0x2, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG2E64_V_M1 }, // 15 |
16951 | | { 0x2, 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG2E64_V_M2 }, // 16 |
16952 | | { 0x2, 0x0, 0x0, 0x0, 0x6, 0x2, PseudoVLSEG2E64_V_M4 }, // 17 |
16953 | | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG2E8FF_V_M1 }, // 18 |
16954 | | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG2E8FF_V_M2 }, // 19 |
16955 | | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x2, PseudoVLSEG2E8FF_V_M4 }, // 20 |
16956 | | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG2E8FF_V_MF8 }, // 21 |
16957 | | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG2E8FF_V_MF4 }, // 22 |
16958 | | { 0x2, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG2E8FF_V_MF2 }, // 23 |
16959 | | { 0x2, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG2E16FF_V_M1 }, // 24 |
16960 | | { 0x2, 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG2E16FF_V_M2 }, // 25 |
16961 | | { 0x2, 0x0, 0x0, 0x1, 0x4, 0x2, PseudoVLSEG2E16FF_V_M4 }, // 26 |
16962 | | { 0x2, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG2E16FF_V_MF4 }, // 27 |
16963 | | { 0x2, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG2E16FF_V_MF2 }, // 28 |
16964 | | { 0x2, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG2E32FF_V_M1 }, // 29 |
16965 | | { 0x2, 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG2E32FF_V_M2 }, // 30 |
16966 | | { 0x2, 0x0, 0x0, 0x1, 0x5, 0x2, PseudoVLSEG2E32FF_V_M4 }, // 31 |
16967 | | { 0x2, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG2E32FF_V_MF2 }, // 32 |
16968 | | { 0x2, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG2E64FF_V_M1 }, // 33 |
16969 | | { 0x2, 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG2E64FF_V_M2 }, // 34 |
16970 | | { 0x2, 0x0, 0x0, 0x1, 0x6, 0x2, PseudoVLSEG2E64FF_V_M4 }, // 35 |
16971 | | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG2E8_V_M1 }, // 36 |
16972 | | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG2E8_V_M2 }, // 37 |
16973 | | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x2, PseudoVLSSEG2E8_V_M4 }, // 38 |
16974 | | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG2E8_V_MF8 }, // 39 |
16975 | | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG2E8_V_MF4 }, // 40 |
16976 | | { 0x2, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG2E8_V_MF2 }, // 41 |
16977 | | { 0x2, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG2E16_V_M1 }, // 42 |
16978 | | { 0x2, 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG2E16_V_M2 }, // 43 |
16979 | | { 0x2, 0x0, 0x1, 0x0, 0x4, 0x2, PseudoVLSSEG2E16_V_M4 }, // 44 |
16980 | | { 0x2, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG2E16_V_MF4 }, // 45 |
16981 | | { 0x2, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG2E16_V_MF2 }, // 46 |
16982 | | { 0x2, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG2E32_V_M1 }, // 47 |
16983 | | { 0x2, 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG2E32_V_M2 }, // 48 |
16984 | | { 0x2, 0x0, 0x1, 0x0, 0x5, 0x2, PseudoVLSSEG2E32_V_M4 }, // 49 |
16985 | | { 0x2, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG2E32_V_MF2 }, // 50 |
16986 | | { 0x2, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG2E64_V_M1 }, // 51 |
16987 | | { 0x2, 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG2E64_V_M2 }, // 52 |
16988 | | { 0x2, 0x0, 0x1, 0x0, 0x6, 0x2, PseudoVLSSEG2E64_V_M4 }, // 53 |
16989 | | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG2E8_V_M1_MASK }, // 54 |
16990 | | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG2E8_V_M2_MASK }, // 55 |
16991 | | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x2, PseudoVLSEG2E8_V_M4_MASK }, // 56 |
16992 | | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG2E8_V_MF8_MASK }, // 57 |
16993 | | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG2E8_V_MF4_MASK }, // 58 |
16994 | | { 0x2, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG2E8_V_MF2_MASK }, // 59 |
16995 | | { 0x2, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG2E16_V_M1_MASK }, // 60 |
16996 | | { 0x2, 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG2E16_V_M2_MASK }, // 61 |
16997 | | { 0x2, 0x1, 0x0, 0x0, 0x4, 0x2, PseudoVLSEG2E16_V_M4_MASK }, // 62 |
16998 | | { 0x2, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG2E16_V_MF4_MASK }, // 63 |
16999 | | { 0x2, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG2E16_V_MF2_MASK }, // 64 |
17000 | | { 0x2, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG2E32_V_M1_MASK }, // 65 |
17001 | | { 0x2, 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG2E32_V_M2_MASK }, // 66 |
17002 | | { 0x2, 0x1, 0x0, 0x0, 0x5, 0x2, PseudoVLSEG2E32_V_M4_MASK }, // 67 |
17003 | | { 0x2, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG2E32_V_MF2_MASK }, // 68 |
17004 | | { 0x2, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG2E64_V_M1_MASK }, // 69 |
17005 | | { 0x2, 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG2E64_V_M2_MASK }, // 70 |
17006 | | { 0x2, 0x1, 0x0, 0x0, 0x6, 0x2, PseudoVLSEG2E64_V_M4_MASK }, // 71 |
17007 | | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG2E8FF_V_M1_MASK }, // 72 |
17008 | | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG2E8FF_V_M2_MASK }, // 73 |
17009 | | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x2, PseudoVLSEG2E8FF_V_M4_MASK }, // 74 |
17010 | | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG2E8FF_V_MF8_MASK }, // 75 |
17011 | | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG2E8FF_V_MF4_MASK }, // 76 |
17012 | | { 0x2, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG2E8FF_V_MF2_MASK }, // 77 |
17013 | | { 0x2, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG2E16FF_V_M1_MASK }, // 78 |
17014 | | { 0x2, 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG2E16FF_V_M2_MASK }, // 79 |
17015 | | { 0x2, 0x1, 0x0, 0x1, 0x4, 0x2, PseudoVLSEG2E16FF_V_M4_MASK }, // 80 |
17016 | | { 0x2, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG2E16FF_V_MF4_MASK }, // 81 |
17017 | | { 0x2, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG2E16FF_V_MF2_MASK }, // 82 |
17018 | | { 0x2, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG2E32FF_V_M1_MASK }, // 83 |
17019 | | { 0x2, 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG2E32FF_V_M2_MASK }, // 84 |
17020 | | { 0x2, 0x1, 0x0, 0x1, 0x5, 0x2, PseudoVLSEG2E32FF_V_M4_MASK }, // 85 |
17021 | | { 0x2, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG2E32FF_V_MF2_MASK }, // 86 |
17022 | | { 0x2, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG2E64FF_V_M1_MASK }, // 87 |
17023 | | { 0x2, 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG2E64FF_V_M2_MASK }, // 88 |
17024 | | { 0x2, 0x1, 0x0, 0x1, 0x6, 0x2, PseudoVLSEG2E64FF_V_M4_MASK }, // 89 |
17025 | | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG2E8_V_M1_MASK }, // 90 |
17026 | | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG2E8_V_M2_MASK }, // 91 |
17027 | | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x2, PseudoVLSSEG2E8_V_M4_MASK }, // 92 |
17028 | | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG2E8_V_MF8_MASK }, // 93 |
17029 | | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG2E8_V_MF4_MASK }, // 94 |
17030 | | { 0x2, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG2E8_V_MF2_MASK }, // 95 |
17031 | | { 0x2, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG2E16_V_M1_MASK }, // 96 |
17032 | | { 0x2, 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG2E16_V_M2_MASK }, // 97 |
17033 | | { 0x2, 0x1, 0x1, 0x0, 0x4, 0x2, PseudoVLSSEG2E16_V_M4_MASK }, // 98 |
17034 | | { 0x2, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG2E16_V_MF4_MASK }, // 99 |
17035 | | { 0x2, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG2E16_V_MF2_MASK }, // 100 |
17036 | | { 0x2, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG2E32_V_M1_MASK }, // 101 |
17037 | | { 0x2, 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG2E32_V_M2_MASK }, // 102 |
17038 | | { 0x2, 0x1, 0x1, 0x0, 0x5, 0x2, PseudoVLSSEG2E32_V_M4_MASK }, // 103 |
17039 | | { 0x2, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG2E32_V_MF2_MASK }, // 104 |
17040 | | { 0x2, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG2E64_V_M1_MASK }, // 105 |
17041 | | { 0x2, 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG2E64_V_M2_MASK }, // 106 |
17042 | | { 0x2, 0x1, 0x1, 0x0, 0x6, 0x2, PseudoVLSSEG2E64_V_M4_MASK }, // 107 |
17043 | | { 0x3, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG3E8_V_M1 }, // 108 |
17044 | | { 0x3, 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG3E8_V_M2 }, // 109 |
17045 | | { 0x3, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG3E8_V_MF8 }, // 110 |
17046 | | { 0x3, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG3E8_V_MF4 }, // 111 |
17047 | | { 0x3, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG3E8_V_MF2 }, // 112 |
17048 | | { 0x3, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG3E16_V_M1 }, // 113 |
17049 | | { 0x3, 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG3E16_V_M2 }, // 114 |
17050 | | { 0x3, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG3E16_V_MF4 }, // 115 |
17051 | | { 0x3, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG3E16_V_MF2 }, // 116 |
17052 | | { 0x3, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG3E32_V_M1 }, // 117 |
17053 | | { 0x3, 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG3E32_V_M2 }, // 118 |
17054 | | { 0x3, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG3E32_V_MF2 }, // 119 |
17055 | | { 0x3, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG3E64_V_M1 }, // 120 |
17056 | | { 0x3, 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG3E64_V_M2 }, // 121 |
17057 | | { 0x3, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG3E8FF_V_M1 }, // 122 |
17058 | | { 0x3, 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG3E8FF_V_M2 }, // 123 |
17059 | | { 0x3, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG3E8FF_V_MF8 }, // 124 |
17060 | | { 0x3, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG3E8FF_V_MF4 }, // 125 |
17061 | | { 0x3, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG3E8FF_V_MF2 }, // 126 |
17062 | | { 0x3, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG3E16FF_V_M1 }, // 127 |
17063 | | { 0x3, 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG3E16FF_V_M2 }, // 128 |
17064 | | { 0x3, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG3E16FF_V_MF4 }, // 129 |
17065 | | { 0x3, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG3E16FF_V_MF2 }, // 130 |
17066 | | { 0x3, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG3E32FF_V_M1 }, // 131 |
17067 | | { 0x3, 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG3E32FF_V_M2 }, // 132 |
17068 | | { 0x3, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG3E32FF_V_MF2 }, // 133 |
17069 | | { 0x3, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG3E64FF_V_M1 }, // 134 |
17070 | | { 0x3, 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG3E64FF_V_M2 }, // 135 |
17071 | | { 0x3, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG3E8_V_M1 }, // 136 |
17072 | | { 0x3, 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG3E8_V_M2 }, // 137 |
17073 | | { 0x3, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG3E8_V_MF8 }, // 138 |
17074 | | { 0x3, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG3E8_V_MF4 }, // 139 |
17075 | | { 0x3, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG3E8_V_MF2 }, // 140 |
17076 | | { 0x3, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG3E16_V_M1 }, // 141 |
17077 | | { 0x3, 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG3E16_V_M2 }, // 142 |
17078 | | { 0x3, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG3E16_V_MF4 }, // 143 |
17079 | | { 0x3, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG3E16_V_MF2 }, // 144 |
17080 | | { 0x3, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG3E32_V_M1 }, // 145 |
17081 | | { 0x3, 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG3E32_V_M2 }, // 146 |
17082 | | { 0x3, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG3E32_V_MF2 }, // 147 |
17083 | | { 0x3, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG3E64_V_M1 }, // 148 |
17084 | | { 0x3, 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG3E64_V_M2 }, // 149 |
17085 | | { 0x3, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG3E8_V_M1_MASK }, // 150 |
17086 | | { 0x3, 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG3E8_V_M2_MASK }, // 151 |
17087 | | { 0x3, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG3E8_V_MF8_MASK }, // 152 |
17088 | | { 0x3, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG3E8_V_MF4_MASK }, // 153 |
17089 | | { 0x3, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG3E8_V_MF2_MASK }, // 154 |
17090 | | { 0x3, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG3E16_V_M1_MASK }, // 155 |
17091 | | { 0x3, 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG3E16_V_M2_MASK }, // 156 |
17092 | | { 0x3, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG3E16_V_MF4_MASK }, // 157 |
17093 | | { 0x3, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG3E16_V_MF2_MASK }, // 158 |
17094 | | { 0x3, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG3E32_V_M1_MASK }, // 159 |
17095 | | { 0x3, 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG3E32_V_M2_MASK }, // 160 |
17096 | | { 0x3, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG3E32_V_MF2_MASK }, // 161 |
17097 | | { 0x3, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG3E64_V_M1_MASK }, // 162 |
17098 | | { 0x3, 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG3E64_V_M2_MASK }, // 163 |
17099 | | { 0x3, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG3E8FF_V_M1_MASK }, // 164 |
17100 | | { 0x3, 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG3E8FF_V_M2_MASK }, // 165 |
17101 | | { 0x3, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG3E8FF_V_MF8_MASK }, // 166 |
17102 | | { 0x3, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG3E8FF_V_MF4_MASK }, // 167 |
17103 | | { 0x3, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG3E8FF_V_MF2_MASK }, // 168 |
17104 | | { 0x3, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG3E16FF_V_M1_MASK }, // 169 |
17105 | | { 0x3, 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG3E16FF_V_M2_MASK }, // 170 |
17106 | | { 0x3, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG3E16FF_V_MF4_MASK }, // 171 |
17107 | | { 0x3, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG3E16FF_V_MF2_MASK }, // 172 |
17108 | | { 0x3, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG3E32FF_V_M1_MASK }, // 173 |
17109 | | { 0x3, 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG3E32FF_V_M2_MASK }, // 174 |
17110 | | { 0x3, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG3E32FF_V_MF2_MASK }, // 175 |
17111 | | { 0x3, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG3E64FF_V_M1_MASK }, // 176 |
17112 | | { 0x3, 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG3E64FF_V_M2_MASK }, // 177 |
17113 | | { 0x3, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG3E8_V_M1_MASK }, // 178 |
17114 | | { 0x3, 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG3E8_V_M2_MASK }, // 179 |
17115 | | { 0x3, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG3E8_V_MF8_MASK }, // 180 |
17116 | | { 0x3, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG3E8_V_MF4_MASK }, // 181 |
17117 | | { 0x3, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG3E8_V_MF2_MASK }, // 182 |
17118 | | { 0x3, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG3E16_V_M1_MASK }, // 183 |
17119 | | { 0x3, 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG3E16_V_M2_MASK }, // 184 |
17120 | | { 0x3, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG3E16_V_MF4_MASK }, // 185 |
17121 | | { 0x3, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG3E16_V_MF2_MASK }, // 186 |
17122 | | { 0x3, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG3E32_V_M1_MASK }, // 187 |
17123 | | { 0x3, 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG3E32_V_M2_MASK }, // 188 |
17124 | | { 0x3, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG3E32_V_MF2_MASK }, // 189 |
17125 | | { 0x3, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG3E64_V_M1_MASK }, // 190 |
17126 | | { 0x3, 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG3E64_V_M2_MASK }, // 191 |
17127 | | { 0x4, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG4E8_V_M1 }, // 192 |
17128 | | { 0x4, 0x0, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG4E8_V_M2 }, // 193 |
17129 | | { 0x4, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG4E8_V_MF8 }, // 194 |
17130 | | { 0x4, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG4E8_V_MF4 }, // 195 |
17131 | | { 0x4, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG4E8_V_MF2 }, // 196 |
17132 | | { 0x4, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG4E16_V_M1 }, // 197 |
17133 | | { 0x4, 0x0, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG4E16_V_M2 }, // 198 |
17134 | | { 0x4, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG4E16_V_MF4 }, // 199 |
17135 | | { 0x4, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG4E16_V_MF2 }, // 200 |
17136 | | { 0x4, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG4E32_V_M1 }, // 201 |
17137 | | { 0x4, 0x0, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG4E32_V_M2 }, // 202 |
17138 | | { 0x4, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG4E32_V_MF2 }, // 203 |
17139 | | { 0x4, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG4E64_V_M1 }, // 204 |
17140 | | { 0x4, 0x0, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG4E64_V_M2 }, // 205 |
17141 | | { 0x4, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG4E8FF_V_M1 }, // 206 |
17142 | | { 0x4, 0x0, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG4E8FF_V_M2 }, // 207 |
17143 | | { 0x4, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG4E8FF_V_MF8 }, // 208 |
17144 | | { 0x4, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG4E8FF_V_MF4 }, // 209 |
17145 | | { 0x4, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG4E8FF_V_MF2 }, // 210 |
17146 | | { 0x4, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG4E16FF_V_M1 }, // 211 |
17147 | | { 0x4, 0x0, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG4E16FF_V_M2 }, // 212 |
17148 | | { 0x4, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG4E16FF_V_MF4 }, // 213 |
17149 | | { 0x4, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG4E16FF_V_MF2 }, // 214 |
17150 | | { 0x4, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG4E32FF_V_M1 }, // 215 |
17151 | | { 0x4, 0x0, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG4E32FF_V_M2 }, // 216 |
17152 | | { 0x4, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG4E32FF_V_MF2 }, // 217 |
17153 | | { 0x4, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG4E64FF_V_M1 }, // 218 |
17154 | | { 0x4, 0x0, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG4E64FF_V_M2 }, // 219 |
17155 | | { 0x4, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG4E8_V_M1 }, // 220 |
17156 | | { 0x4, 0x0, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG4E8_V_M2 }, // 221 |
17157 | | { 0x4, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG4E8_V_MF8 }, // 222 |
17158 | | { 0x4, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG4E8_V_MF4 }, // 223 |
17159 | | { 0x4, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG4E8_V_MF2 }, // 224 |
17160 | | { 0x4, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG4E16_V_M1 }, // 225 |
17161 | | { 0x4, 0x0, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG4E16_V_M2 }, // 226 |
17162 | | { 0x4, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG4E16_V_MF4 }, // 227 |
17163 | | { 0x4, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG4E16_V_MF2 }, // 228 |
17164 | | { 0x4, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG4E32_V_M1 }, // 229 |
17165 | | { 0x4, 0x0, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG4E32_V_M2 }, // 230 |
17166 | | { 0x4, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG4E32_V_MF2 }, // 231 |
17167 | | { 0x4, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG4E64_V_M1 }, // 232 |
17168 | | { 0x4, 0x0, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG4E64_V_M2 }, // 233 |
17169 | | { 0x4, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG4E8_V_M1_MASK }, // 234 |
17170 | | { 0x4, 0x1, 0x0, 0x0, 0x3, 0x1, PseudoVLSEG4E8_V_M2_MASK }, // 235 |
17171 | | { 0x4, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG4E8_V_MF8_MASK }, // 236 |
17172 | | { 0x4, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG4E8_V_MF4_MASK }, // 237 |
17173 | | { 0x4, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG4E8_V_MF2_MASK }, // 238 |
17174 | | { 0x4, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG4E16_V_M1_MASK }, // 239 |
17175 | | { 0x4, 0x1, 0x0, 0x0, 0x4, 0x1, PseudoVLSEG4E16_V_M2_MASK }, // 240 |
17176 | | { 0x4, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG4E16_V_MF4_MASK }, // 241 |
17177 | | { 0x4, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG4E16_V_MF2_MASK }, // 242 |
17178 | | { 0x4, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG4E32_V_M1_MASK }, // 243 |
17179 | | { 0x4, 0x1, 0x0, 0x0, 0x5, 0x1, PseudoVLSEG4E32_V_M2_MASK }, // 244 |
17180 | | { 0x4, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG4E32_V_MF2_MASK }, // 245 |
17181 | | { 0x4, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG4E64_V_M1_MASK }, // 246 |
17182 | | { 0x4, 0x1, 0x0, 0x0, 0x6, 0x1, PseudoVLSEG4E64_V_M2_MASK }, // 247 |
17183 | | { 0x4, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG4E8FF_V_M1_MASK }, // 248 |
17184 | | { 0x4, 0x1, 0x0, 0x1, 0x3, 0x1, PseudoVLSEG4E8FF_V_M2_MASK }, // 249 |
17185 | | { 0x4, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG4E8FF_V_MF8_MASK }, // 250 |
17186 | | { 0x4, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG4E8FF_V_MF4_MASK }, // 251 |
17187 | | { 0x4, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG4E8FF_V_MF2_MASK }, // 252 |
17188 | | { 0x4, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG4E16FF_V_M1_MASK }, // 253 |
17189 | | { 0x4, 0x1, 0x0, 0x1, 0x4, 0x1, PseudoVLSEG4E16FF_V_M2_MASK }, // 254 |
17190 | | { 0x4, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG4E16FF_V_MF4_MASK }, // 255 |
17191 | | { 0x4, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG4E16FF_V_MF2_MASK }, // 256 |
17192 | | { 0x4, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG4E32FF_V_M1_MASK }, // 257 |
17193 | | { 0x4, 0x1, 0x0, 0x1, 0x5, 0x1, PseudoVLSEG4E32FF_V_M2_MASK }, // 258 |
17194 | | { 0x4, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG4E32FF_V_MF2_MASK }, // 259 |
17195 | | { 0x4, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG4E64FF_V_M1_MASK }, // 260 |
17196 | | { 0x4, 0x1, 0x0, 0x1, 0x6, 0x1, PseudoVLSEG4E64FF_V_M2_MASK }, // 261 |
17197 | | { 0x4, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG4E8_V_M1_MASK }, // 262 |
17198 | | { 0x4, 0x1, 0x1, 0x0, 0x3, 0x1, PseudoVLSSEG4E8_V_M2_MASK }, // 263 |
17199 | | { 0x4, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG4E8_V_MF8_MASK }, // 264 |
17200 | | { 0x4, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG4E8_V_MF4_MASK }, // 265 |
17201 | | { 0x4, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG4E8_V_MF2_MASK }, // 266 |
17202 | | { 0x4, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG4E16_V_M1_MASK }, // 267 |
17203 | | { 0x4, 0x1, 0x1, 0x0, 0x4, 0x1, PseudoVLSSEG4E16_V_M2_MASK }, // 268 |
17204 | | { 0x4, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG4E16_V_MF4_MASK }, // 269 |
17205 | | { 0x4, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG4E16_V_MF2_MASK }, // 270 |
17206 | | { 0x4, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG4E32_V_M1_MASK }, // 271 |
17207 | | { 0x4, 0x1, 0x1, 0x0, 0x5, 0x1, PseudoVLSSEG4E32_V_M2_MASK }, // 272 |
17208 | | { 0x4, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG4E32_V_MF2_MASK }, // 273 |
17209 | | { 0x4, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG4E64_V_M1_MASK }, // 274 |
17210 | | { 0x4, 0x1, 0x1, 0x0, 0x6, 0x1, PseudoVLSSEG4E64_V_M2_MASK }, // 275 |
17211 | | { 0x5, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG5E8_V_M1 }, // 276 |
17212 | | { 0x5, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG5E8_V_MF8 }, // 277 |
17213 | | { 0x5, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG5E8_V_MF4 }, // 278 |
17214 | | { 0x5, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG5E8_V_MF2 }, // 279 |
17215 | | { 0x5, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG5E16_V_M1 }, // 280 |
17216 | | { 0x5, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG5E16_V_MF4 }, // 281 |
17217 | | { 0x5, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG5E16_V_MF2 }, // 282 |
17218 | | { 0x5, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG5E32_V_M1 }, // 283 |
17219 | | { 0x5, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG5E32_V_MF2 }, // 284 |
17220 | | { 0x5, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG5E64_V_M1 }, // 285 |
17221 | | { 0x5, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG5E8FF_V_M1 }, // 286 |
17222 | | { 0x5, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG5E8FF_V_MF8 }, // 287 |
17223 | | { 0x5, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG5E8FF_V_MF4 }, // 288 |
17224 | | { 0x5, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG5E8FF_V_MF2 }, // 289 |
17225 | | { 0x5, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG5E16FF_V_M1 }, // 290 |
17226 | | { 0x5, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG5E16FF_V_MF4 }, // 291 |
17227 | | { 0x5, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG5E16FF_V_MF2 }, // 292 |
17228 | | { 0x5, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG5E32FF_V_M1 }, // 293 |
17229 | | { 0x5, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG5E32FF_V_MF2 }, // 294 |
17230 | | { 0x5, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG5E64FF_V_M1 }, // 295 |
17231 | | { 0x5, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG5E8_V_M1 }, // 296 |
17232 | | { 0x5, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG5E8_V_MF8 }, // 297 |
17233 | | { 0x5, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG5E8_V_MF4 }, // 298 |
17234 | | { 0x5, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG5E8_V_MF2 }, // 299 |
17235 | | { 0x5, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG5E16_V_M1 }, // 300 |
17236 | | { 0x5, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG5E16_V_MF4 }, // 301 |
17237 | | { 0x5, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG5E16_V_MF2 }, // 302 |
17238 | | { 0x5, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG5E32_V_M1 }, // 303 |
17239 | | { 0x5, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG5E32_V_MF2 }, // 304 |
17240 | | { 0x5, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG5E64_V_M1 }, // 305 |
17241 | | { 0x5, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG5E8_V_M1_MASK }, // 306 |
17242 | | { 0x5, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG5E8_V_MF8_MASK }, // 307 |
17243 | | { 0x5, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG5E8_V_MF4_MASK }, // 308 |
17244 | | { 0x5, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG5E8_V_MF2_MASK }, // 309 |
17245 | | { 0x5, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG5E16_V_M1_MASK }, // 310 |
17246 | | { 0x5, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG5E16_V_MF4_MASK }, // 311 |
17247 | | { 0x5, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG5E16_V_MF2_MASK }, // 312 |
17248 | | { 0x5, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG5E32_V_M1_MASK }, // 313 |
17249 | | { 0x5, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG5E32_V_MF2_MASK }, // 314 |
17250 | | { 0x5, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG5E64_V_M1_MASK }, // 315 |
17251 | | { 0x5, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG5E8FF_V_M1_MASK }, // 316 |
17252 | | { 0x5, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG5E8FF_V_MF8_MASK }, // 317 |
17253 | | { 0x5, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG5E8FF_V_MF4_MASK }, // 318 |
17254 | | { 0x5, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG5E8FF_V_MF2_MASK }, // 319 |
17255 | | { 0x5, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG5E16FF_V_M1_MASK }, // 320 |
17256 | | { 0x5, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG5E16FF_V_MF4_MASK }, // 321 |
17257 | | { 0x5, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG5E16FF_V_MF2_MASK }, // 322 |
17258 | | { 0x5, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG5E32FF_V_M1_MASK }, // 323 |
17259 | | { 0x5, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG5E32FF_V_MF2_MASK }, // 324 |
17260 | | { 0x5, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG5E64FF_V_M1_MASK }, // 325 |
17261 | | { 0x5, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG5E8_V_M1_MASK }, // 326 |
17262 | | { 0x5, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG5E8_V_MF8_MASK }, // 327 |
17263 | | { 0x5, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG5E8_V_MF4_MASK }, // 328 |
17264 | | { 0x5, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG5E8_V_MF2_MASK }, // 329 |
17265 | | { 0x5, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG5E16_V_M1_MASK }, // 330 |
17266 | | { 0x5, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG5E16_V_MF4_MASK }, // 331 |
17267 | | { 0x5, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG5E16_V_MF2_MASK }, // 332 |
17268 | | { 0x5, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG5E32_V_M1_MASK }, // 333 |
17269 | | { 0x5, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG5E32_V_MF2_MASK }, // 334 |
17270 | | { 0x5, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG5E64_V_M1_MASK }, // 335 |
17271 | | { 0x6, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG6E8_V_M1 }, // 336 |
17272 | | { 0x6, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG6E8_V_MF8 }, // 337 |
17273 | | { 0x6, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG6E8_V_MF4 }, // 338 |
17274 | | { 0x6, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG6E8_V_MF2 }, // 339 |
17275 | | { 0x6, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG6E16_V_M1 }, // 340 |
17276 | | { 0x6, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG6E16_V_MF4 }, // 341 |
17277 | | { 0x6, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG6E16_V_MF2 }, // 342 |
17278 | | { 0x6, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG6E32_V_M1 }, // 343 |
17279 | | { 0x6, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG6E32_V_MF2 }, // 344 |
17280 | | { 0x6, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG6E64_V_M1 }, // 345 |
17281 | | { 0x6, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG6E8FF_V_M1 }, // 346 |
17282 | | { 0x6, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG6E8FF_V_MF8 }, // 347 |
17283 | | { 0x6, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG6E8FF_V_MF4 }, // 348 |
17284 | | { 0x6, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG6E8FF_V_MF2 }, // 349 |
17285 | | { 0x6, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG6E16FF_V_M1 }, // 350 |
17286 | | { 0x6, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG6E16FF_V_MF4 }, // 351 |
17287 | | { 0x6, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG6E16FF_V_MF2 }, // 352 |
17288 | | { 0x6, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG6E32FF_V_M1 }, // 353 |
17289 | | { 0x6, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG6E32FF_V_MF2 }, // 354 |
17290 | | { 0x6, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG6E64FF_V_M1 }, // 355 |
17291 | | { 0x6, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG6E8_V_M1 }, // 356 |
17292 | | { 0x6, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG6E8_V_MF8 }, // 357 |
17293 | | { 0x6, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG6E8_V_MF4 }, // 358 |
17294 | | { 0x6, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG6E8_V_MF2 }, // 359 |
17295 | | { 0x6, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG6E16_V_M1 }, // 360 |
17296 | | { 0x6, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG6E16_V_MF4 }, // 361 |
17297 | | { 0x6, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG6E16_V_MF2 }, // 362 |
17298 | | { 0x6, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG6E32_V_M1 }, // 363 |
17299 | | { 0x6, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG6E32_V_MF2 }, // 364 |
17300 | | { 0x6, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG6E64_V_M1 }, // 365 |
17301 | | { 0x6, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG6E8_V_M1_MASK }, // 366 |
17302 | | { 0x6, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG6E8_V_MF8_MASK }, // 367 |
17303 | | { 0x6, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG6E8_V_MF4_MASK }, // 368 |
17304 | | { 0x6, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG6E8_V_MF2_MASK }, // 369 |
17305 | | { 0x6, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG6E16_V_M1_MASK }, // 370 |
17306 | | { 0x6, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG6E16_V_MF4_MASK }, // 371 |
17307 | | { 0x6, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG6E16_V_MF2_MASK }, // 372 |
17308 | | { 0x6, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG6E32_V_M1_MASK }, // 373 |
17309 | | { 0x6, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG6E32_V_MF2_MASK }, // 374 |
17310 | | { 0x6, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG6E64_V_M1_MASK }, // 375 |
17311 | | { 0x6, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG6E8FF_V_M1_MASK }, // 376 |
17312 | | { 0x6, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG6E8FF_V_MF8_MASK }, // 377 |
17313 | | { 0x6, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG6E8FF_V_MF4_MASK }, // 378 |
17314 | | { 0x6, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG6E8FF_V_MF2_MASK }, // 379 |
17315 | | { 0x6, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG6E16FF_V_M1_MASK }, // 380 |
17316 | | { 0x6, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG6E16FF_V_MF4_MASK }, // 381 |
17317 | | { 0x6, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG6E16FF_V_MF2_MASK }, // 382 |
17318 | | { 0x6, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG6E32FF_V_M1_MASK }, // 383 |
17319 | | { 0x6, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG6E32FF_V_MF2_MASK }, // 384 |
17320 | | { 0x6, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG6E64FF_V_M1_MASK }, // 385 |
17321 | | { 0x6, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG6E8_V_M1_MASK }, // 386 |
17322 | | { 0x6, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG6E8_V_MF8_MASK }, // 387 |
17323 | | { 0x6, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG6E8_V_MF4_MASK }, // 388 |
17324 | | { 0x6, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG6E8_V_MF2_MASK }, // 389 |
17325 | | { 0x6, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG6E16_V_M1_MASK }, // 390 |
17326 | | { 0x6, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG6E16_V_MF4_MASK }, // 391 |
17327 | | { 0x6, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG6E16_V_MF2_MASK }, // 392 |
17328 | | { 0x6, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG6E32_V_M1_MASK }, // 393 |
17329 | | { 0x6, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG6E32_V_MF2_MASK }, // 394 |
17330 | | { 0x6, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG6E64_V_M1_MASK }, // 395 |
17331 | | { 0x7, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG7E8_V_M1 }, // 396 |
17332 | | { 0x7, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG7E8_V_MF8 }, // 397 |
17333 | | { 0x7, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG7E8_V_MF4 }, // 398 |
17334 | | { 0x7, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG7E8_V_MF2 }, // 399 |
17335 | | { 0x7, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG7E16_V_M1 }, // 400 |
17336 | | { 0x7, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG7E16_V_MF4 }, // 401 |
17337 | | { 0x7, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG7E16_V_MF2 }, // 402 |
17338 | | { 0x7, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG7E32_V_M1 }, // 403 |
17339 | | { 0x7, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG7E32_V_MF2 }, // 404 |
17340 | | { 0x7, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG7E64_V_M1 }, // 405 |
17341 | | { 0x7, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG7E8FF_V_M1 }, // 406 |
17342 | | { 0x7, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG7E8FF_V_MF8 }, // 407 |
17343 | | { 0x7, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG7E8FF_V_MF4 }, // 408 |
17344 | | { 0x7, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG7E8FF_V_MF2 }, // 409 |
17345 | | { 0x7, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG7E16FF_V_M1 }, // 410 |
17346 | | { 0x7, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG7E16FF_V_MF4 }, // 411 |
17347 | | { 0x7, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG7E16FF_V_MF2 }, // 412 |
17348 | | { 0x7, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG7E32FF_V_M1 }, // 413 |
17349 | | { 0x7, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG7E32FF_V_MF2 }, // 414 |
17350 | | { 0x7, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG7E64FF_V_M1 }, // 415 |
17351 | | { 0x7, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG7E8_V_M1 }, // 416 |
17352 | | { 0x7, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG7E8_V_MF8 }, // 417 |
17353 | | { 0x7, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG7E8_V_MF4 }, // 418 |
17354 | | { 0x7, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG7E8_V_MF2 }, // 419 |
17355 | | { 0x7, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG7E16_V_M1 }, // 420 |
17356 | | { 0x7, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG7E16_V_MF4 }, // 421 |
17357 | | { 0x7, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG7E16_V_MF2 }, // 422 |
17358 | | { 0x7, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG7E32_V_M1 }, // 423 |
17359 | | { 0x7, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG7E32_V_MF2 }, // 424 |
17360 | | { 0x7, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG7E64_V_M1 }, // 425 |
17361 | | { 0x7, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG7E8_V_M1_MASK }, // 426 |
17362 | | { 0x7, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG7E8_V_MF8_MASK }, // 427 |
17363 | | { 0x7, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG7E8_V_MF4_MASK }, // 428 |
17364 | | { 0x7, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG7E8_V_MF2_MASK }, // 429 |
17365 | | { 0x7, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG7E16_V_M1_MASK }, // 430 |
17366 | | { 0x7, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG7E16_V_MF4_MASK }, // 431 |
17367 | | { 0x7, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG7E16_V_MF2_MASK }, // 432 |
17368 | | { 0x7, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG7E32_V_M1_MASK }, // 433 |
17369 | | { 0x7, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG7E32_V_MF2_MASK }, // 434 |
17370 | | { 0x7, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG7E64_V_M1_MASK }, // 435 |
17371 | | { 0x7, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG7E8FF_V_M1_MASK }, // 436 |
17372 | | { 0x7, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG7E8FF_V_MF8_MASK }, // 437 |
17373 | | { 0x7, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG7E8FF_V_MF4_MASK }, // 438 |
17374 | | { 0x7, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG7E8FF_V_MF2_MASK }, // 439 |
17375 | | { 0x7, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG7E16FF_V_M1_MASK }, // 440 |
17376 | | { 0x7, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG7E16FF_V_MF4_MASK }, // 441 |
17377 | | { 0x7, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG7E16FF_V_MF2_MASK }, // 442 |
17378 | | { 0x7, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG7E32FF_V_M1_MASK }, // 443 |
17379 | | { 0x7, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG7E32FF_V_MF2_MASK }, // 444 |
17380 | | { 0x7, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG7E64FF_V_M1_MASK }, // 445 |
17381 | | { 0x7, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG7E8_V_M1_MASK }, // 446 |
17382 | | { 0x7, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG7E8_V_MF8_MASK }, // 447 |
17383 | | { 0x7, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG7E8_V_MF4_MASK }, // 448 |
17384 | | { 0x7, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG7E8_V_MF2_MASK }, // 449 |
17385 | | { 0x7, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG7E16_V_M1_MASK }, // 450 |
17386 | | { 0x7, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG7E16_V_MF4_MASK }, // 451 |
17387 | | { 0x7, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG7E16_V_MF2_MASK }, // 452 |
17388 | | { 0x7, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG7E32_V_M1_MASK }, // 453 |
17389 | | { 0x7, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG7E32_V_MF2_MASK }, // 454 |
17390 | | { 0x7, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG7E64_V_M1_MASK }, // 455 |
17391 | | { 0x8, 0x0, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG8E8_V_M1 }, // 456 |
17392 | | { 0x8, 0x0, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG8E8_V_MF8 }, // 457 |
17393 | | { 0x8, 0x0, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG8E8_V_MF4 }, // 458 |
17394 | | { 0x8, 0x0, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG8E8_V_MF2 }, // 459 |
17395 | | { 0x8, 0x0, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG8E16_V_M1 }, // 460 |
17396 | | { 0x8, 0x0, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG8E16_V_MF4 }, // 461 |
17397 | | { 0x8, 0x0, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG8E16_V_MF2 }, // 462 |
17398 | | { 0x8, 0x0, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG8E32_V_M1 }, // 463 |
17399 | | { 0x8, 0x0, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG8E32_V_MF2 }, // 464 |
17400 | | { 0x8, 0x0, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG8E64_V_M1 }, // 465 |
17401 | | { 0x8, 0x0, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG8E8FF_V_M1 }, // 466 |
17402 | | { 0x8, 0x0, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG8E8FF_V_MF8 }, // 467 |
17403 | | { 0x8, 0x0, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG8E8FF_V_MF4 }, // 468 |
17404 | | { 0x8, 0x0, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG8E8FF_V_MF2 }, // 469 |
17405 | | { 0x8, 0x0, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG8E16FF_V_M1 }, // 470 |
17406 | | { 0x8, 0x0, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG8E16FF_V_MF4 }, // 471 |
17407 | | { 0x8, 0x0, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG8E16FF_V_MF2 }, // 472 |
17408 | | { 0x8, 0x0, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG8E32FF_V_M1 }, // 473 |
17409 | | { 0x8, 0x0, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG8E32FF_V_MF2 }, // 474 |
17410 | | { 0x8, 0x0, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG8E64FF_V_M1 }, // 475 |
17411 | | { 0x8, 0x0, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG8E8_V_M1 }, // 476 |
17412 | | { 0x8, 0x0, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG8E8_V_MF8 }, // 477 |
17413 | | { 0x8, 0x0, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG8E8_V_MF4 }, // 478 |
17414 | | { 0x8, 0x0, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG8E8_V_MF2 }, // 479 |
17415 | | { 0x8, 0x0, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG8E16_V_M1 }, // 480 |
17416 | | { 0x8, 0x0, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG8E16_V_MF4 }, // 481 |
17417 | | { 0x8, 0x0, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG8E16_V_MF2 }, // 482 |
17418 | | { 0x8, 0x0, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG8E32_V_M1 }, // 483 |
17419 | | { 0x8, 0x0, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG8E32_V_MF2 }, // 484 |
17420 | | { 0x8, 0x0, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG8E64_V_M1 }, // 485 |
17421 | | { 0x8, 0x1, 0x0, 0x0, 0x3, 0x0, PseudoVLSEG8E8_V_M1_MASK }, // 486 |
17422 | | { 0x8, 0x1, 0x0, 0x0, 0x3, 0x5, PseudoVLSEG8E8_V_MF8_MASK }, // 487 |
17423 | | { 0x8, 0x1, 0x0, 0x0, 0x3, 0x6, PseudoVLSEG8E8_V_MF4_MASK }, // 488 |
17424 | | { 0x8, 0x1, 0x0, 0x0, 0x3, 0x7, PseudoVLSEG8E8_V_MF2_MASK }, // 489 |
17425 | | { 0x8, 0x1, 0x0, 0x0, 0x4, 0x0, PseudoVLSEG8E16_V_M1_MASK }, // 490 |
17426 | | { 0x8, 0x1, 0x0, 0x0, 0x4, 0x6, PseudoVLSEG8E16_V_MF4_MASK }, // 491 |
17427 | | { 0x8, 0x1, 0x0, 0x0, 0x4, 0x7, PseudoVLSEG8E16_V_MF2_MASK }, // 492 |
17428 | | { 0x8, 0x1, 0x0, 0x0, 0x5, 0x0, PseudoVLSEG8E32_V_M1_MASK }, // 493 |
17429 | | { 0x8, 0x1, 0x0, 0x0, 0x5, 0x7, PseudoVLSEG8E32_V_MF2_MASK }, // 494 |
17430 | | { 0x8, 0x1, 0x0, 0x0, 0x6, 0x0, PseudoVLSEG8E64_V_M1_MASK }, // 495 |
17431 | | { 0x8, 0x1, 0x0, 0x1, 0x3, 0x0, PseudoVLSEG8E8FF_V_M1_MASK }, // 496 |
17432 | | { 0x8, 0x1, 0x0, 0x1, 0x3, 0x5, PseudoVLSEG8E8FF_V_MF8_MASK }, // 497 |
17433 | | { 0x8, 0x1, 0x0, 0x1, 0x3, 0x6, PseudoVLSEG8E8FF_V_MF4_MASK }, // 498 |
17434 | | { 0x8, 0x1, 0x0, 0x1, 0x3, 0x7, PseudoVLSEG8E8FF_V_MF2_MASK }, // 499 |
17435 | | { 0x8, 0x1, 0x0, 0x1, 0x4, 0x0, PseudoVLSEG8E16FF_V_M1_MASK }, // 500 |
17436 | | { 0x8, 0x1, 0x0, 0x1, 0x4, 0x6, PseudoVLSEG8E16FF_V_MF4_MASK }, // 501 |
17437 | | { 0x8, 0x1, 0x0, 0x1, 0x4, 0x7, PseudoVLSEG8E16FF_V_MF2_MASK }, // 502 |
17438 | | { 0x8, 0x1, 0x0, 0x1, 0x5, 0x0, PseudoVLSEG8E32FF_V_M1_MASK }, // 503 |
17439 | | { 0x8, 0x1, 0x0, 0x1, 0x5, 0x7, PseudoVLSEG8E32FF_V_MF2_MASK }, // 504 |
17440 | | { 0x8, 0x1, 0x0, 0x1, 0x6, 0x0, PseudoVLSEG8E64FF_V_M1_MASK }, // 505 |
17441 | | { 0x8, 0x1, 0x1, 0x0, 0x3, 0x0, PseudoVLSSEG8E8_V_M1_MASK }, // 506 |
17442 | | { 0x8, 0x1, 0x1, 0x0, 0x3, 0x5, PseudoVLSSEG8E8_V_MF8_MASK }, // 507 |
17443 | | { 0x8, 0x1, 0x1, 0x0, 0x3, 0x6, PseudoVLSSEG8E8_V_MF4_MASK }, // 508 |
17444 | | { 0x8, 0x1, 0x1, 0x0, 0x3, 0x7, PseudoVLSSEG8E8_V_MF2_MASK }, // 509 |
17445 | | { 0x8, 0x1, 0x1, 0x0, 0x4, 0x0, PseudoVLSSEG8E16_V_M1_MASK }, // 510 |
17446 | | { 0x8, 0x1, 0x1, 0x0, 0x4, 0x6, PseudoVLSSEG8E16_V_MF4_MASK }, // 511 |
17447 | | { 0x8, 0x1, 0x1, 0x0, 0x4, 0x7, PseudoVLSSEG8E16_V_MF2_MASK }, // 512 |
17448 | | { 0x8, 0x1, 0x1, 0x0, 0x5, 0x0, PseudoVLSSEG8E32_V_M1_MASK }, // 513 |
17449 | | { 0x8, 0x1, 0x1, 0x0, 0x5, 0x7, PseudoVLSSEG8E32_V_MF2_MASK }, // 514 |
17450 | | { 0x8, 0x1, 0x1, 0x0, 0x6, 0x0, PseudoVLSSEG8E64_V_M1_MASK }, // 515 |
17451 | | }; |
17452 | | |
17453 | | const RISCV_VLSEGPseudo *RISCV_getVLSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t FF, uint8_t Log2SEW, uint8_t LMUL) { |
17454 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), NFMaskedStridedFFLog2SEWLMUL); |
17455 | | if (i == -1) |
17456 | | return NULL; |
17457 | | else |
17458 | | return &RISCVVLSEGTable[Index[i].index]; |
17459 | | } |
17460 | | |
17461 | | #endif |
17462 | | |
17463 | | #ifdef GET_RISCVVLXSEGTable_IMPL |
17464 | | static const RISCV_VLXSEGPseudo RISCVVLXSEGTable[] = { |
17465 | | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG2EI8_V_M1_M1 }, // 0 |
17466 | | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG2EI8_V_MF8_M1 }, // 1 |
17467 | | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG2EI8_V_MF4_M1 }, // 2 |
17468 | | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG2EI8_V_MF2_M1 }, // 3 |
17469 | | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG2EI8_V_M1_M2 }, // 4 |
17470 | | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG2EI8_V_M2_M2 }, // 5 |
17471 | | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG2EI8_V_MF4_M2 }, // 6 |
17472 | | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG2EI8_V_MF2_M2 }, // 7 |
17473 | | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVLUXSEG2EI8_V_M1_M4 }, // 8 |
17474 | | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVLUXSEG2EI8_V_M2_M4 }, // 9 |
17475 | | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVLUXSEG2EI8_V_M4_M4 }, // 10 |
17476 | | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVLUXSEG2EI8_V_MF2_M4 }, // 11 |
17477 | | { 0x2, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF8 }, // 12 |
17478 | | { 0x2, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF4 }, // 13 |
17479 | | { 0x2, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF4 }, // 14 |
17480 | | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF2 }, // 15 |
17481 | | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF2 }, // 16 |
17482 | | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG2EI8_V_MF2_MF2 }, // 17 |
17483 | | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG2EI16_V_M1_M1 }, // 18 |
17484 | | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG2EI16_V_M2_M1 }, // 19 |
17485 | | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG2EI16_V_MF4_M1 }, // 20 |
17486 | | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG2EI16_V_MF2_M1 }, // 21 |
17487 | | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG2EI16_V_M1_M2 }, // 22 |
17488 | | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG2EI16_V_M2_M2 }, // 23 |
17489 | | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG2EI16_V_M4_M2 }, // 24 |
17490 | | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG2EI16_V_MF2_M2 }, // 25 |
17491 | | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVLUXSEG2EI16_V_M1_M4 }, // 26 |
17492 | | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVLUXSEG2EI16_V_M2_M4 }, // 27 |
17493 | | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVLUXSEG2EI16_V_M4_M4 }, // 28 |
17494 | | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVLUXSEG2EI16_V_M8_M4 }, // 29 |
17495 | | { 0x2, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF8 }, // 30 |
17496 | | { 0x2, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF4 }, // 31 |
17497 | | { 0x2, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF4 }, // 32 |
17498 | | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG2EI16_V_M1_MF2 }, // 33 |
17499 | | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF2 }, // 34 |
17500 | | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF2 }, // 35 |
17501 | | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG2EI32_V_M1_M1 }, // 36 |
17502 | | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG2EI32_V_M2_M1 }, // 37 |
17503 | | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG2EI32_V_M4_M1 }, // 38 |
17504 | | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG2EI32_V_MF2_M1 }, // 39 |
17505 | | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG2EI32_V_M1_M2 }, // 40 |
17506 | | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG2EI32_V_M2_M2 }, // 41 |
17507 | | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG2EI32_V_M4_M2 }, // 42 |
17508 | | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG2EI32_V_M8_M2 }, // 43 |
17509 | | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVLUXSEG2EI32_V_M2_M4 }, // 44 |
17510 | | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVLUXSEG2EI32_V_M4_M4 }, // 45 |
17511 | | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVLUXSEG2EI32_V_M8_M4 }, // 46 |
17512 | | { 0x2, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF8 }, // 47 |
17513 | | { 0x2, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG2EI32_V_M1_MF4 }, // 48 |
17514 | | { 0x2, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF4 }, // 49 |
17515 | | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG2EI32_V_M1_MF2 }, // 50 |
17516 | | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG2EI32_V_M2_MF2 }, // 51 |
17517 | | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF2 }, // 52 |
17518 | | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG2EI64_V_M1_M1 }, // 53 |
17519 | | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG2EI64_V_M2_M1 }, // 54 |
17520 | | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG2EI64_V_M4_M1 }, // 55 |
17521 | | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG2EI64_V_M8_M1 }, // 56 |
17522 | | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG2EI64_V_M2_M2 }, // 57 |
17523 | | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG2EI64_V_M4_M2 }, // 58 |
17524 | | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG2EI64_V_M8_M2 }, // 59 |
17525 | | { 0x2, 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVLUXSEG2EI64_V_M4_M4 }, // 60 |
17526 | | { 0x2, 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVLUXSEG2EI64_V_M8_M4 }, // 61 |
17527 | | { 0x2, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG2EI64_V_M1_MF8 }, // 62 |
17528 | | { 0x2, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG2EI64_V_M1_MF4 }, // 63 |
17529 | | { 0x2, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG2EI64_V_M2_MF4 }, // 64 |
17530 | | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG2EI64_V_M1_MF2 }, // 65 |
17531 | | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG2EI64_V_M2_MF2 }, // 66 |
17532 | | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG2EI64_V_M4_MF2 }, // 67 |
17533 | | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG2EI8_V_M1_M1 }, // 68 |
17534 | | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG2EI8_V_MF8_M1 }, // 69 |
17535 | | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG2EI8_V_MF4_M1 }, // 70 |
17536 | | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG2EI8_V_MF2_M1 }, // 71 |
17537 | | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG2EI8_V_M1_M2 }, // 72 |
17538 | | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG2EI8_V_M2_M2 }, // 73 |
17539 | | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG2EI8_V_MF4_M2 }, // 74 |
17540 | | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG2EI8_V_MF2_M2 }, // 75 |
17541 | | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVLOXSEG2EI8_V_M1_M4 }, // 76 |
17542 | | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVLOXSEG2EI8_V_M2_M4 }, // 77 |
17543 | | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVLOXSEG2EI8_V_M4_M4 }, // 78 |
17544 | | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVLOXSEG2EI8_V_MF2_M4 }, // 79 |
17545 | | { 0x2, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF8 }, // 80 |
17546 | | { 0x2, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF4 }, // 81 |
17547 | | { 0x2, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF4 }, // 82 |
17548 | | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF2 }, // 83 |
17549 | | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF2 }, // 84 |
17550 | | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG2EI8_V_MF2_MF2 }, // 85 |
17551 | | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG2EI16_V_M1_M1 }, // 86 |
17552 | | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG2EI16_V_M2_M1 }, // 87 |
17553 | | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG2EI16_V_MF4_M1 }, // 88 |
17554 | | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG2EI16_V_MF2_M1 }, // 89 |
17555 | | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG2EI16_V_M1_M2 }, // 90 |
17556 | | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG2EI16_V_M2_M2 }, // 91 |
17557 | | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG2EI16_V_M4_M2 }, // 92 |
17558 | | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG2EI16_V_MF2_M2 }, // 93 |
17559 | | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVLOXSEG2EI16_V_M1_M4 }, // 94 |
17560 | | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVLOXSEG2EI16_V_M2_M4 }, // 95 |
17561 | | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVLOXSEG2EI16_V_M4_M4 }, // 96 |
17562 | | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVLOXSEG2EI16_V_M8_M4 }, // 97 |
17563 | | { 0x2, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF8 }, // 98 |
17564 | | { 0x2, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF4 }, // 99 |
17565 | | { 0x2, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF4 }, // 100 |
17566 | | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG2EI16_V_M1_MF2 }, // 101 |
17567 | | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF2 }, // 102 |
17568 | | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF2 }, // 103 |
17569 | | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG2EI32_V_M1_M1 }, // 104 |
17570 | | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG2EI32_V_M2_M1 }, // 105 |
17571 | | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG2EI32_V_M4_M1 }, // 106 |
17572 | | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG2EI32_V_MF2_M1 }, // 107 |
17573 | | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG2EI32_V_M1_M2 }, // 108 |
17574 | | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG2EI32_V_M2_M2 }, // 109 |
17575 | | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG2EI32_V_M4_M2 }, // 110 |
17576 | | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG2EI32_V_M8_M2 }, // 111 |
17577 | | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVLOXSEG2EI32_V_M2_M4 }, // 112 |
17578 | | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVLOXSEG2EI32_V_M4_M4 }, // 113 |
17579 | | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVLOXSEG2EI32_V_M8_M4 }, // 114 |
17580 | | { 0x2, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF8 }, // 115 |
17581 | | { 0x2, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG2EI32_V_M1_MF4 }, // 116 |
17582 | | { 0x2, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF4 }, // 117 |
17583 | | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG2EI32_V_M1_MF2 }, // 118 |
17584 | | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG2EI32_V_M2_MF2 }, // 119 |
17585 | | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF2 }, // 120 |
17586 | | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG2EI64_V_M1_M1 }, // 121 |
17587 | | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG2EI64_V_M2_M1 }, // 122 |
17588 | | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG2EI64_V_M4_M1 }, // 123 |
17589 | | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG2EI64_V_M8_M1 }, // 124 |
17590 | | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG2EI64_V_M2_M2 }, // 125 |
17591 | | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG2EI64_V_M4_M2 }, // 126 |
17592 | | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG2EI64_V_M8_M2 }, // 127 |
17593 | | { 0x2, 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVLOXSEG2EI64_V_M4_M4 }, // 128 |
17594 | | { 0x2, 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVLOXSEG2EI64_V_M8_M4 }, // 129 |
17595 | | { 0x2, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG2EI64_V_M1_MF8 }, // 130 |
17596 | | { 0x2, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG2EI64_V_M1_MF4 }, // 131 |
17597 | | { 0x2, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG2EI64_V_M2_MF4 }, // 132 |
17598 | | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG2EI64_V_M1_MF2 }, // 133 |
17599 | | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG2EI64_V_M2_MF2 }, // 134 |
17600 | | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG2EI64_V_M4_MF2 }, // 135 |
17601 | | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG2EI8_V_M1_M1_MASK }, // 136 |
17602 | | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG2EI8_V_MF8_M1_MASK }, // 137 |
17603 | | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG2EI8_V_MF4_M1_MASK }, // 138 |
17604 | | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG2EI8_V_MF2_M1_MASK }, // 139 |
17605 | | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG2EI8_V_M1_M2_MASK }, // 140 |
17606 | | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG2EI8_V_M2_M2_MASK }, // 141 |
17607 | | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG2EI8_V_MF4_M2_MASK }, // 142 |
17608 | | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG2EI8_V_MF2_M2_MASK }, // 143 |
17609 | | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVLUXSEG2EI8_V_M1_M4_MASK }, // 144 |
17610 | | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVLUXSEG2EI8_V_M2_M4_MASK }, // 145 |
17611 | | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVLUXSEG2EI8_V_M4_M4_MASK }, // 146 |
17612 | | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVLUXSEG2EI8_V_MF2_M4_MASK }, // 147 |
17613 | | { 0x2, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF8_MASK }, // 148 |
17614 | | { 0x2, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF4_MASK }, // 149 |
17615 | | { 0x2, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF4_MASK }, // 150 |
17616 | | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG2EI8_V_MF8_MF2_MASK }, // 151 |
17617 | | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG2EI8_V_MF4_MF2_MASK }, // 152 |
17618 | | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG2EI8_V_MF2_MF2_MASK }, // 153 |
17619 | | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG2EI16_V_M1_M1_MASK }, // 154 |
17620 | | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG2EI16_V_M2_M1_MASK }, // 155 |
17621 | | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG2EI16_V_MF4_M1_MASK }, // 156 |
17622 | | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG2EI16_V_MF2_M1_MASK }, // 157 |
17623 | | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG2EI16_V_M1_M2_MASK }, // 158 |
17624 | | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG2EI16_V_M2_M2_MASK }, // 159 |
17625 | | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG2EI16_V_M4_M2_MASK }, // 160 |
17626 | | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG2EI16_V_MF2_M2_MASK }, // 161 |
17627 | | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVLUXSEG2EI16_V_M1_M4_MASK }, // 162 |
17628 | | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVLUXSEG2EI16_V_M2_M4_MASK }, // 163 |
17629 | | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVLUXSEG2EI16_V_M4_M4_MASK }, // 164 |
17630 | | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVLUXSEG2EI16_V_M8_M4_MASK }, // 165 |
17631 | | { 0x2, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF8_MASK }, // 166 |
17632 | | { 0x2, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF4_MASK }, // 167 |
17633 | | { 0x2, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF4_MASK }, // 168 |
17634 | | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG2EI16_V_M1_MF2_MASK }, // 169 |
17635 | | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG2EI16_V_MF4_MF2_MASK }, // 170 |
17636 | | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG2EI16_V_MF2_MF2_MASK }, // 171 |
17637 | | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG2EI32_V_M1_M1_MASK }, // 172 |
17638 | | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG2EI32_V_M2_M1_MASK }, // 173 |
17639 | | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG2EI32_V_M4_M1_MASK }, // 174 |
17640 | | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG2EI32_V_MF2_M1_MASK }, // 175 |
17641 | | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG2EI32_V_M1_M2_MASK }, // 176 |
17642 | | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG2EI32_V_M2_M2_MASK }, // 177 |
17643 | | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG2EI32_V_M4_M2_MASK }, // 178 |
17644 | | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG2EI32_V_M8_M2_MASK }, // 179 |
17645 | | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVLUXSEG2EI32_V_M2_M4_MASK }, // 180 |
17646 | | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVLUXSEG2EI32_V_M4_M4_MASK }, // 181 |
17647 | | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVLUXSEG2EI32_V_M8_M4_MASK }, // 182 |
17648 | | { 0x2, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF8_MASK }, // 183 |
17649 | | { 0x2, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG2EI32_V_M1_MF4_MASK }, // 184 |
17650 | | { 0x2, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF4_MASK }, // 185 |
17651 | | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG2EI32_V_M1_MF2_MASK }, // 186 |
17652 | | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG2EI32_V_M2_MF2_MASK }, // 187 |
17653 | | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG2EI32_V_MF2_MF2_MASK }, // 188 |
17654 | | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG2EI64_V_M1_M1_MASK }, // 189 |
17655 | | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG2EI64_V_M2_M1_MASK }, // 190 |
17656 | | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG2EI64_V_M4_M1_MASK }, // 191 |
17657 | | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG2EI64_V_M8_M1_MASK }, // 192 |
17658 | | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG2EI64_V_M2_M2_MASK }, // 193 |
17659 | | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG2EI64_V_M4_M2_MASK }, // 194 |
17660 | | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG2EI64_V_M8_M2_MASK }, // 195 |
17661 | | { 0x2, 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVLUXSEG2EI64_V_M4_M4_MASK }, // 196 |
17662 | | { 0x2, 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVLUXSEG2EI64_V_M8_M4_MASK }, // 197 |
17663 | | { 0x2, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG2EI64_V_M1_MF8_MASK }, // 198 |
17664 | | { 0x2, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG2EI64_V_M1_MF4_MASK }, // 199 |
17665 | | { 0x2, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG2EI64_V_M2_MF4_MASK }, // 200 |
17666 | | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG2EI64_V_M1_MF2_MASK }, // 201 |
17667 | | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG2EI64_V_M2_MF2_MASK }, // 202 |
17668 | | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG2EI64_V_M4_MF2_MASK }, // 203 |
17669 | | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG2EI8_V_M1_M1_MASK }, // 204 |
17670 | | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG2EI8_V_MF8_M1_MASK }, // 205 |
17671 | | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG2EI8_V_MF4_M1_MASK }, // 206 |
17672 | | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG2EI8_V_MF2_M1_MASK }, // 207 |
17673 | | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG2EI8_V_M1_M2_MASK }, // 208 |
17674 | | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG2EI8_V_M2_M2_MASK }, // 209 |
17675 | | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG2EI8_V_MF4_M2_MASK }, // 210 |
17676 | | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG2EI8_V_MF2_M2_MASK }, // 211 |
17677 | | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVLOXSEG2EI8_V_M1_M4_MASK }, // 212 |
17678 | | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVLOXSEG2EI8_V_M2_M4_MASK }, // 213 |
17679 | | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVLOXSEG2EI8_V_M4_M4_MASK }, // 214 |
17680 | | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVLOXSEG2EI8_V_MF2_M4_MASK }, // 215 |
17681 | | { 0x2, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF8_MASK }, // 216 |
17682 | | { 0x2, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF4_MASK }, // 217 |
17683 | | { 0x2, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF4_MASK }, // 218 |
17684 | | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG2EI8_V_MF8_MF2_MASK }, // 219 |
17685 | | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG2EI8_V_MF4_MF2_MASK }, // 220 |
17686 | | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG2EI8_V_MF2_MF2_MASK }, // 221 |
17687 | | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG2EI16_V_M1_M1_MASK }, // 222 |
17688 | | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG2EI16_V_M2_M1_MASK }, // 223 |
17689 | | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG2EI16_V_MF4_M1_MASK }, // 224 |
17690 | | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG2EI16_V_MF2_M1_MASK }, // 225 |
17691 | | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG2EI16_V_M1_M2_MASK }, // 226 |
17692 | | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG2EI16_V_M2_M2_MASK }, // 227 |
17693 | | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG2EI16_V_M4_M2_MASK }, // 228 |
17694 | | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG2EI16_V_MF2_M2_MASK }, // 229 |
17695 | | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVLOXSEG2EI16_V_M1_M4_MASK }, // 230 |
17696 | | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVLOXSEG2EI16_V_M2_M4_MASK }, // 231 |
17697 | | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVLOXSEG2EI16_V_M4_M4_MASK }, // 232 |
17698 | | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVLOXSEG2EI16_V_M8_M4_MASK }, // 233 |
17699 | | { 0x2, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF8_MASK }, // 234 |
17700 | | { 0x2, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF4_MASK }, // 235 |
17701 | | { 0x2, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF4_MASK }, // 236 |
17702 | | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG2EI16_V_M1_MF2_MASK }, // 237 |
17703 | | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG2EI16_V_MF4_MF2_MASK }, // 238 |
17704 | | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG2EI16_V_MF2_MF2_MASK }, // 239 |
17705 | | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG2EI32_V_M1_M1_MASK }, // 240 |
17706 | | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG2EI32_V_M2_M1_MASK }, // 241 |
17707 | | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG2EI32_V_M4_M1_MASK }, // 242 |
17708 | | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG2EI32_V_MF2_M1_MASK }, // 243 |
17709 | | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG2EI32_V_M1_M2_MASK }, // 244 |
17710 | | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG2EI32_V_M2_M2_MASK }, // 245 |
17711 | | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG2EI32_V_M4_M2_MASK }, // 246 |
17712 | | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG2EI32_V_M8_M2_MASK }, // 247 |
17713 | | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVLOXSEG2EI32_V_M2_M4_MASK }, // 248 |
17714 | | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVLOXSEG2EI32_V_M4_M4_MASK }, // 249 |
17715 | | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVLOXSEG2EI32_V_M8_M4_MASK }, // 250 |
17716 | | { 0x2, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF8_MASK }, // 251 |
17717 | | { 0x2, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG2EI32_V_M1_MF4_MASK }, // 252 |
17718 | | { 0x2, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF4_MASK }, // 253 |
17719 | | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG2EI32_V_M1_MF2_MASK }, // 254 |
17720 | | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG2EI32_V_M2_MF2_MASK }, // 255 |
17721 | | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG2EI32_V_MF2_MF2_MASK }, // 256 |
17722 | | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG2EI64_V_M1_M1_MASK }, // 257 |
17723 | | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG2EI64_V_M2_M1_MASK }, // 258 |
17724 | | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG2EI64_V_M4_M1_MASK }, // 259 |
17725 | | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG2EI64_V_M8_M1_MASK }, // 260 |
17726 | | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG2EI64_V_M2_M2_MASK }, // 261 |
17727 | | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG2EI64_V_M4_M2_MASK }, // 262 |
17728 | | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG2EI64_V_M8_M2_MASK }, // 263 |
17729 | | { 0x2, 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVLOXSEG2EI64_V_M4_M4_MASK }, // 264 |
17730 | | { 0x2, 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVLOXSEG2EI64_V_M8_M4_MASK }, // 265 |
17731 | | { 0x2, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG2EI64_V_M1_MF8_MASK }, // 266 |
17732 | | { 0x2, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG2EI64_V_M1_MF4_MASK }, // 267 |
17733 | | { 0x2, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG2EI64_V_M2_MF4_MASK }, // 268 |
17734 | | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG2EI64_V_M1_MF2_MASK }, // 269 |
17735 | | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG2EI64_V_M2_MF2_MASK }, // 270 |
17736 | | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG2EI64_V_M4_MF2_MASK }, // 271 |
17737 | | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG3EI8_V_M1_M1 }, // 272 |
17738 | | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG3EI8_V_MF8_M1 }, // 273 |
17739 | | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG3EI8_V_MF4_M1 }, // 274 |
17740 | | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG3EI8_V_MF2_M1 }, // 275 |
17741 | | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG3EI8_V_M1_M2 }, // 276 |
17742 | | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG3EI8_V_M2_M2 }, // 277 |
17743 | | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG3EI8_V_MF4_M2 }, // 278 |
17744 | | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG3EI8_V_MF2_M2 }, // 279 |
17745 | | { 0x3, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF8 }, // 280 |
17746 | | { 0x3, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF4 }, // 281 |
17747 | | { 0x3, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF4 }, // 282 |
17748 | | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF2 }, // 283 |
17749 | | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF2 }, // 284 |
17750 | | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG3EI8_V_MF2_MF2 }, // 285 |
17751 | | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG3EI16_V_M1_M1 }, // 286 |
17752 | | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG3EI16_V_M2_M1 }, // 287 |
17753 | | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG3EI16_V_MF4_M1 }, // 288 |
17754 | | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG3EI16_V_MF2_M1 }, // 289 |
17755 | | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG3EI16_V_M1_M2 }, // 290 |
17756 | | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG3EI16_V_M2_M2 }, // 291 |
17757 | | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG3EI16_V_M4_M2 }, // 292 |
17758 | | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG3EI16_V_MF2_M2 }, // 293 |
17759 | | { 0x3, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF8 }, // 294 |
17760 | | { 0x3, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF4 }, // 295 |
17761 | | { 0x3, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF4 }, // 296 |
17762 | | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG3EI16_V_M1_MF2 }, // 297 |
17763 | | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF2 }, // 298 |
17764 | | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF2 }, // 299 |
17765 | | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG3EI32_V_M1_M1 }, // 300 |
17766 | | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG3EI32_V_M2_M1 }, // 301 |
17767 | | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG3EI32_V_M4_M1 }, // 302 |
17768 | | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG3EI32_V_MF2_M1 }, // 303 |
17769 | | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG3EI32_V_M1_M2 }, // 304 |
17770 | | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG3EI32_V_M2_M2 }, // 305 |
17771 | | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG3EI32_V_M4_M2 }, // 306 |
17772 | | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG3EI32_V_M8_M2 }, // 307 |
17773 | | { 0x3, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF8 }, // 308 |
17774 | | { 0x3, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG3EI32_V_M1_MF4 }, // 309 |
17775 | | { 0x3, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF4 }, // 310 |
17776 | | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG3EI32_V_M1_MF2 }, // 311 |
17777 | | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG3EI32_V_M2_MF2 }, // 312 |
17778 | | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF2 }, // 313 |
17779 | | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG3EI64_V_M1_M1 }, // 314 |
17780 | | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG3EI64_V_M2_M1 }, // 315 |
17781 | | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG3EI64_V_M4_M1 }, // 316 |
17782 | | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG3EI64_V_M8_M1 }, // 317 |
17783 | | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG3EI64_V_M2_M2 }, // 318 |
17784 | | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG3EI64_V_M4_M2 }, // 319 |
17785 | | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG3EI64_V_M8_M2 }, // 320 |
17786 | | { 0x3, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG3EI64_V_M1_MF8 }, // 321 |
17787 | | { 0x3, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG3EI64_V_M1_MF4 }, // 322 |
17788 | | { 0x3, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG3EI64_V_M2_MF4 }, // 323 |
17789 | | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG3EI64_V_M1_MF2 }, // 324 |
17790 | | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG3EI64_V_M2_MF2 }, // 325 |
17791 | | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG3EI64_V_M4_MF2 }, // 326 |
17792 | | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG3EI8_V_M1_M1 }, // 327 |
17793 | | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG3EI8_V_MF8_M1 }, // 328 |
17794 | | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG3EI8_V_MF4_M1 }, // 329 |
17795 | | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG3EI8_V_MF2_M1 }, // 330 |
17796 | | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG3EI8_V_M1_M2 }, // 331 |
17797 | | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG3EI8_V_M2_M2 }, // 332 |
17798 | | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG3EI8_V_MF4_M2 }, // 333 |
17799 | | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG3EI8_V_MF2_M2 }, // 334 |
17800 | | { 0x3, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF8 }, // 335 |
17801 | | { 0x3, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF4 }, // 336 |
17802 | | { 0x3, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF4 }, // 337 |
17803 | | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF2 }, // 338 |
17804 | | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF2 }, // 339 |
17805 | | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG3EI8_V_MF2_MF2 }, // 340 |
17806 | | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG3EI16_V_M1_M1 }, // 341 |
17807 | | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG3EI16_V_M2_M1 }, // 342 |
17808 | | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG3EI16_V_MF4_M1 }, // 343 |
17809 | | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG3EI16_V_MF2_M1 }, // 344 |
17810 | | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG3EI16_V_M1_M2 }, // 345 |
17811 | | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG3EI16_V_M2_M2 }, // 346 |
17812 | | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG3EI16_V_M4_M2 }, // 347 |
17813 | | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG3EI16_V_MF2_M2 }, // 348 |
17814 | | { 0x3, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF8 }, // 349 |
17815 | | { 0x3, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF4 }, // 350 |
17816 | | { 0x3, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF4 }, // 351 |
17817 | | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG3EI16_V_M1_MF2 }, // 352 |
17818 | | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF2 }, // 353 |
17819 | | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF2 }, // 354 |
17820 | | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG3EI32_V_M1_M1 }, // 355 |
17821 | | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG3EI32_V_M2_M1 }, // 356 |
17822 | | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG3EI32_V_M4_M1 }, // 357 |
17823 | | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG3EI32_V_MF2_M1 }, // 358 |
17824 | | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG3EI32_V_M1_M2 }, // 359 |
17825 | | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG3EI32_V_M2_M2 }, // 360 |
17826 | | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG3EI32_V_M4_M2 }, // 361 |
17827 | | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG3EI32_V_M8_M2 }, // 362 |
17828 | | { 0x3, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF8 }, // 363 |
17829 | | { 0x3, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG3EI32_V_M1_MF4 }, // 364 |
17830 | | { 0x3, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF4 }, // 365 |
17831 | | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG3EI32_V_M1_MF2 }, // 366 |
17832 | | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG3EI32_V_M2_MF2 }, // 367 |
17833 | | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF2 }, // 368 |
17834 | | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG3EI64_V_M1_M1 }, // 369 |
17835 | | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG3EI64_V_M2_M1 }, // 370 |
17836 | | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG3EI64_V_M4_M1 }, // 371 |
17837 | | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG3EI64_V_M8_M1 }, // 372 |
17838 | | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG3EI64_V_M2_M2 }, // 373 |
17839 | | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG3EI64_V_M4_M2 }, // 374 |
17840 | | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG3EI64_V_M8_M2 }, // 375 |
17841 | | { 0x3, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG3EI64_V_M1_MF8 }, // 376 |
17842 | | { 0x3, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG3EI64_V_M1_MF4 }, // 377 |
17843 | | { 0x3, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG3EI64_V_M2_MF4 }, // 378 |
17844 | | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG3EI64_V_M1_MF2 }, // 379 |
17845 | | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG3EI64_V_M2_MF2 }, // 380 |
17846 | | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG3EI64_V_M4_MF2 }, // 381 |
17847 | | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG3EI8_V_M1_M1_MASK }, // 382 |
17848 | | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG3EI8_V_MF8_M1_MASK }, // 383 |
17849 | | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG3EI8_V_MF4_M1_MASK }, // 384 |
17850 | | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG3EI8_V_MF2_M1_MASK }, // 385 |
17851 | | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG3EI8_V_M1_M2_MASK }, // 386 |
17852 | | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG3EI8_V_M2_M2_MASK }, // 387 |
17853 | | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG3EI8_V_MF4_M2_MASK }, // 388 |
17854 | | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG3EI8_V_MF2_M2_MASK }, // 389 |
17855 | | { 0x3, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF8_MASK }, // 390 |
17856 | | { 0x3, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF4_MASK }, // 391 |
17857 | | { 0x3, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF4_MASK }, // 392 |
17858 | | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG3EI8_V_MF8_MF2_MASK }, // 393 |
17859 | | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG3EI8_V_MF4_MF2_MASK }, // 394 |
17860 | | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG3EI8_V_MF2_MF2_MASK }, // 395 |
17861 | | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG3EI16_V_M1_M1_MASK }, // 396 |
17862 | | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG3EI16_V_M2_M1_MASK }, // 397 |
17863 | | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG3EI16_V_MF4_M1_MASK }, // 398 |
17864 | | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG3EI16_V_MF2_M1_MASK }, // 399 |
17865 | | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG3EI16_V_M1_M2_MASK }, // 400 |
17866 | | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG3EI16_V_M2_M2_MASK }, // 401 |
17867 | | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG3EI16_V_M4_M2_MASK }, // 402 |
17868 | | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG3EI16_V_MF2_M2_MASK }, // 403 |
17869 | | { 0x3, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF8_MASK }, // 404 |
17870 | | { 0x3, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF4_MASK }, // 405 |
17871 | | { 0x3, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF4_MASK }, // 406 |
17872 | | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG3EI16_V_M1_MF2_MASK }, // 407 |
17873 | | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG3EI16_V_MF4_MF2_MASK }, // 408 |
17874 | | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG3EI16_V_MF2_MF2_MASK }, // 409 |
17875 | | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG3EI32_V_M1_M1_MASK }, // 410 |
17876 | | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG3EI32_V_M2_M1_MASK }, // 411 |
17877 | | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG3EI32_V_M4_M1_MASK }, // 412 |
17878 | | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG3EI32_V_MF2_M1_MASK }, // 413 |
17879 | | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG3EI32_V_M1_M2_MASK }, // 414 |
17880 | | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG3EI32_V_M2_M2_MASK }, // 415 |
17881 | | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG3EI32_V_M4_M2_MASK }, // 416 |
17882 | | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG3EI32_V_M8_M2_MASK }, // 417 |
17883 | | { 0x3, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF8_MASK }, // 418 |
17884 | | { 0x3, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG3EI32_V_M1_MF4_MASK }, // 419 |
17885 | | { 0x3, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF4_MASK }, // 420 |
17886 | | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG3EI32_V_M1_MF2_MASK }, // 421 |
17887 | | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG3EI32_V_M2_MF2_MASK }, // 422 |
17888 | | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG3EI32_V_MF2_MF2_MASK }, // 423 |
17889 | | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG3EI64_V_M1_M1_MASK }, // 424 |
17890 | | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG3EI64_V_M2_M1_MASK }, // 425 |
17891 | | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG3EI64_V_M4_M1_MASK }, // 426 |
17892 | | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG3EI64_V_M8_M1_MASK }, // 427 |
17893 | | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG3EI64_V_M2_M2_MASK }, // 428 |
17894 | | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG3EI64_V_M4_M2_MASK }, // 429 |
17895 | | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG3EI64_V_M8_M2_MASK }, // 430 |
17896 | | { 0x3, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG3EI64_V_M1_MF8_MASK }, // 431 |
17897 | | { 0x3, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG3EI64_V_M1_MF4_MASK }, // 432 |
17898 | | { 0x3, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG3EI64_V_M2_MF4_MASK }, // 433 |
17899 | | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG3EI64_V_M1_MF2_MASK }, // 434 |
17900 | | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG3EI64_V_M2_MF2_MASK }, // 435 |
17901 | | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG3EI64_V_M4_MF2_MASK }, // 436 |
17902 | | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG3EI8_V_M1_M1_MASK }, // 437 |
17903 | | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG3EI8_V_MF8_M1_MASK }, // 438 |
17904 | | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG3EI8_V_MF4_M1_MASK }, // 439 |
17905 | | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG3EI8_V_MF2_M1_MASK }, // 440 |
17906 | | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG3EI8_V_M1_M2_MASK }, // 441 |
17907 | | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG3EI8_V_M2_M2_MASK }, // 442 |
17908 | | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG3EI8_V_MF4_M2_MASK }, // 443 |
17909 | | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG3EI8_V_MF2_M2_MASK }, // 444 |
17910 | | { 0x3, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF8_MASK }, // 445 |
17911 | | { 0x3, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF4_MASK }, // 446 |
17912 | | { 0x3, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF4_MASK }, // 447 |
17913 | | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG3EI8_V_MF8_MF2_MASK }, // 448 |
17914 | | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG3EI8_V_MF4_MF2_MASK }, // 449 |
17915 | | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG3EI8_V_MF2_MF2_MASK }, // 450 |
17916 | | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG3EI16_V_M1_M1_MASK }, // 451 |
17917 | | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG3EI16_V_M2_M1_MASK }, // 452 |
17918 | | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG3EI16_V_MF4_M1_MASK }, // 453 |
17919 | | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG3EI16_V_MF2_M1_MASK }, // 454 |
17920 | | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG3EI16_V_M1_M2_MASK }, // 455 |
17921 | | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG3EI16_V_M2_M2_MASK }, // 456 |
17922 | | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG3EI16_V_M4_M2_MASK }, // 457 |
17923 | | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG3EI16_V_MF2_M2_MASK }, // 458 |
17924 | | { 0x3, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF8_MASK }, // 459 |
17925 | | { 0x3, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF4_MASK }, // 460 |
17926 | | { 0x3, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF4_MASK }, // 461 |
17927 | | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG3EI16_V_M1_MF2_MASK }, // 462 |
17928 | | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG3EI16_V_MF4_MF2_MASK }, // 463 |
17929 | | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG3EI16_V_MF2_MF2_MASK }, // 464 |
17930 | | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG3EI32_V_M1_M1_MASK }, // 465 |
17931 | | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG3EI32_V_M2_M1_MASK }, // 466 |
17932 | | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG3EI32_V_M4_M1_MASK }, // 467 |
17933 | | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG3EI32_V_MF2_M1_MASK }, // 468 |
17934 | | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG3EI32_V_M1_M2_MASK }, // 469 |
17935 | | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG3EI32_V_M2_M2_MASK }, // 470 |
17936 | | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG3EI32_V_M4_M2_MASK }, // 471 |
17937 | | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG3EI32_V_M8_M2_MASK }, // 472 |
17938 | | { 0x3, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF8_MASK }, // 473 |
17939 | | { 0x3, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG3EI32_V_M1_MF4_MASK }, // 474 |
17940 | | { 0x3, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF4_MASK }, // 475 |
17941 | | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG3EI32_V_M1_MF2_MASK }, // 476 |
17942 | | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG3EI32_V_M2_MF2_MASK }, // 477 |
17943 | | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG3EI32_V_MF2_MF2_MASK }, // 478 |
17944 | | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG3EI64_V_M1_M1_MASK }, // 479 |
17945 | | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG3EI64_V_M2_M1_MASK }, // 480 |
17946 | | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG3EI64_V_M4_M1_MASK }, // 481 |
17947 | | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG3EI64_V_M8_M1_MASK }, // 482 |
17948 | | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG3EI64_V_M2_M2_MASK }, // 483 |
17949 | | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG3EI64_V_M4_M2_MASK }, // 484 |
17950 | | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG3EI64_V_M8_M2_MASK }, // 485 |
17951 | | { 0x3, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG3EI64_V_M1_MF8_MASK }, // 486 |
17952 | | { 0x3, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG3EI64_V_M1_MF4_MASK }, // 487 |
17953 | | { 0x3, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG3EI64_V_M2_MF4_MASK }, // 488 |
17954 | | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG3EI64_V_M1_MF2_MASK }, // 489 |
17955 | | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG3EI64_V_M2_MF2_MASK }, // 490 |
17956 | | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG3EI64_V_M4_MF2_MASK }, // 491 |
17957 | | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG4EI8_V_M1_M1 }, // 492 |
17958 | | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG4EI8_V_MF8_M1 }, // 493 |
17959 | | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG4EI8_V_MF4_M1 }, // 494 |
17960 | | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG4EI8_V_MF2_M1 }, // 495 |
17961 | | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG4EI8_V_M1_M2 }, // 496 |
17962 | | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG4EI8_V_M2_M2 }, // 497 |
17963 | | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG4EI8_V_MF4_M2 }, // 498 |
17964 | | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG4EI8_V_MF2_M2 }, // 499 |
17965 | | { 0x4, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF8 }, // 500 |
17966 | | { 0x4, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF4 }, // 501 |
17967 | | { 0x4, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF4 }, // 502 |
17968 | | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF2 }, // 503 |
17969 | | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF2 }, // 504 |
17970 | | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG4EI8_V_MF2_MF2 }, // 505 |
17971 | | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG4EI16_V_M1_M1 }, // 506 |
17972 | | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG4EI16_V_M2_M1 }, // 507 |
17973 | | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG4EI16_V_MF4_M1 }, // 508 |
17974 | | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG4EI16_V_MF2_M1 }, // 509 |
17975 | | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG4EI16_V_M1_M2 }, // 510 |
17976 | | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG4EI16_V_M2_M2 }, // 511 |
17977 | | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG4EI16_V_M4_M2 }, // 512 |
17978 | | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG4EI16_V_MF2_M2 }, // 513 |
17979 | | { 0x4, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF8 }, // 514 |
17980 | | { 0x4, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF4 }, // 515 |
17981 | | { 0x4, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF4 }, // 516 |
17982 | | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG4EI16_V_M1_MF2 }, // 517 |
17983 | | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF2 }, // 518 |
17984 | | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF2 }, // 519 |
17985 | | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG4EI32_V_M1_M1 }, // 520 |
17986 | | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG4EI32_V_M2_M1 }, // 521 |
17987 | | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG4EI32_V_M4_M1 }, // 522 |
17988 | | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG4EI32_V_MF2_M1 }, // 523 |
17989 | | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG4EI32_V_M1_M2 }, // 524 |
17990 | | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG4EI32_V_M2_M2 }, // 525 |
17991 | | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG4EI32_V_M4_M2 }, // 526 |
17992 | | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG4EI32_V_M8_M2 }, // 527 |
17993 | | { 0x4, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF8 }, // 528 |
17994 | | { 0x4, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG4EI32_V_M1_MF4 }, // 529 |
17995 | | { 0x4, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF4 }, // 530 |
17996 | | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG4EI32_V_M1_MF2 }, // 531 |
17997 | | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG4EI32_V_M2_MF2 }, // 532 |
17998 | | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF2 }, // 533 |
17999 | | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG4EI64_V_M1_M1 }, // 534 |
18000 | | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG4EI64_V_M2_M1 }, // 535 |
18001 | | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG4EI64_V_M4_M1 }, // 536 |
18002 | | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG4EI64_V_M8_M1 }, // 537 |
18003 | | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG4EI64_V_M2_M2 }, // 538 |
18004 | | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG4EI64_V_M4_M2 }, // 539 |
18005 | | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG4EI64_V_M8_M2 }, // 540 |
18006 | | { 0x4, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG4EI64_V_M1_MF8 }, // 541 |
18007 | | { 0x4, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG4EI64_V_M1_MF4 }, // 542 |
18008 | | { 0x4, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG4EI64_V_M2_MF4 }, // 543 |
18009 | | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG4EI64_V_M1_MF2 }, // 544 |
18010 | | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG4EI64_V_M2_MF2 }, // 545 |
18011 | | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG4EI64_V_M4_MF2 }, // 546 |
18012 | | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG4EI8_V_M1_M1 }, // 547 |
18013 | | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG4EI8_V_MF8_M1 }, // 548 |
18014 | | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG4EI8_V_MF4_M1 }, // 549 |
18015 | | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG4EI8_V_MF2_M1 }, // 550 |
18016 | | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG4EI8_V_M1_M2 }, // 551 |
18017 | | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG4EI8_V_M2_M2 }, // 552 |
18018 | | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG4EI8_V_MF4_M2 }, // 553 |
18019 | | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG4EI8_V_MF2_M2 }, // 554 |
18020 | | { 0x4, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF8 }, // 555 |
18021 | | { 0x4, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF4 }, // 556 |
18022 | | { 0x4, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF4 }, // 557 |
18023 | | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF2 }, // 558 |
18024 | | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF2 }, // 559 |
18025 | | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG4EI8_V_MF2_MF2 }, // 560 |
18026 | | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG4EI16_V_M1_M1 }, // 561 |
18027 | | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG4EI16_V_M2_M1 }, // 562 |
18028 | | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG4EI16_V_MF4_M1 }, // 563 |
18029 | | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG4EI16_V_MF2_M1 }, // 564 |
18030 | | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG4EI16_V_M1_M2 }, // 565 |
18031 | | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG4EI16_V_M2_M2 }, // 566 |
18032 | | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG4EI16_V_M4_M2 }, // 567 |
18033 | | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG4EI16_V_MF2_M2 }, // 568 |
18034 | | { 0x4, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF8 }, // 569 |
18035 | | { 0x4, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF4 }, // 570 |
18036 | | { 0x4, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF4 }, // 571 |
18037 | | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG4EI16_V_M1_MF2 }, // 572 |
18038 | | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF2 }, // 573 |
18039 | | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF2 }, // 574 |
18040 | | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG4EI32_V_M1_M1 }, // 575 |
18041 | | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG4EI32_V_M2_M1 }, // 576 |
18042 | | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG4EI32_V_M4_M1 }, // 577 |
18043 | | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG4EI32_V_MF2_M1 }, // 578 |
18044 | | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG4EI32_V_M1_M2 }, // 579 |
18045 | | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG4EI32_V_M2_M2 }, // 580 |
18046 | | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG4EI32_V_M4_M2 }, // 581 |
18047 | | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG4EI32_V_M8_M2 }, // 582 |
18048 | | { 0x4, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF8 }, // 583 |
18049 | | { 0x4, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG4EI32_V_M1_MF4 }, // 584 |
18050 | | { 0x4, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF4 }, // 585 |
18051 | | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG4EI32_V_M1_MF2 }, // 586 |
18052 | | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG4EI32_V_M2_MF2 }, // 587 |
18053 | | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF2 }, // 588 |
18054 | | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG4EI64_V_M1_M1 }, // 589 |
18055 | | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG4EI64_V_M2_M1 }, // 590 |
18056 | | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG4EI64_V_M4_M1 }, // 591 |
18057 | | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG4EI64_V_M8_M1 }, // 592 |
18058 | | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG4EI64_V_M2_M2 }, // 593 |
18059 | | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG4EI64_V_M4_M2 }, // 594 |
18060 | | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG4EI64_V_M8_M2 }, // 595 |
18061 | | { 0x4, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG4EI64_V_M1_MF8 }, // 596 |
18062 | | { 0x4, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG4EI64_V_M1_MF4 }, // 597 |
18063 | | { 0x4, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG4EI64_V_M2_MF4 }, // 598 |
18064 | | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG4EI64_V_M1_MF2 }, // 599 |
18065 | | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG4EI64_V_M2_MF2 }, // 600 |
18066 | | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG4EI64_V_M4_MF2 }, // 601 |
18067 | | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG4EI8_V_M1_M1_MASK }, // 602 |
18068 | | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG4EI8_V_MF8_M1_MASK }, // 603 |
18069 | | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG4EI8_V_MF4_M1_MASK }, // 604 |
18070 | | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG4EI8_V_MF2_M1_MASK }, // 605 |
18071 | | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXSEG4EI8_V_M1_M2_MASK }, // 606 |
18072 | | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXSEG4EI8_V_M2_M2_MASK }, // 607 |
18073 | | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXSEG4EI8_V_MF4_M2_MASK }, // 608 |
18074 | | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXSEG4EI8_V_MF2_M2_MASK }, // 609 |
18075 | | { 0x4, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF8_MASK }, // 610 |
18076 | | { 0x4, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF4_MASK }, // 611 |
18077 | | { 0x4, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF4_MASK }, // 612 |
18078 | | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG4EI8_V_MF8_MF2_MASK }, // 613 |
18079 | | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG4EI8_V_MF4_MF2_MASK }, // 614 |
18080 | | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG4EI8_V_MF2_MF2_MASK }, // 615 |
18081 | | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG4EI16_V_M1_M1_MASK }, // 616 |
18082 | | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG4EI16_V_M2_M1_MASK }, // 617 |
18083 | | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG4EI16_V_MF4_M1_MASK }, // 618 |
18084 | | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG4EI16_V_MF2_M1_MASK }, // 619 |
18085 | | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXSEG4EI16_V_M1_M2_MASK }, // 620 |
18086 | | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXSEG4EI16_V_M2_M2_MASK }, // 621 |
18087 | | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXSEG4EI16_V_M4_M2_MASK }, // 622 |
18088 | | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXSEG4EI16_V_MF2_M2_MASK }, // 623 |
18089 | | { 0x4, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF8_MASK }, // 624 |
18090 | | { 0x4, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF4_MASK }, // 625 |
18091 | | { 0x4, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF4_MASK }, // 626 |
18092 | | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG4EI16_V_M1_MF2_MASK }, // 627 |
18093 | | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG4EI16_V_MF4_MF2_MASK }, // 628 |
18094 | | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG4EI16_V_MF2_MF2_MASK }, // 629 |
18095 | | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG4EI32_V_M1_M1_MASK }, // 630 |
18096 | | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG4EI32_V_M2_M1_MASK }, // 631 |
18097 | | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG4EI32_V_M4_M1_MASK }, // 632 |
18098 | | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG4EI32_V_MF2_M1_MASK }, // 633 |
18099 | | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXSEG4EI32_V_M1_M2_MASK }, // 634 |
18100 | | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXSEG4EI32_V_M2_M2_MASK }, // 635 |
18101 | | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXSEG4EI32_V_M4_M2_MASK }, // 636 |
18102 | | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXSEG4EI32_V_M8_M2_MASK }, // 637 |
18103 | | { 0x4, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF8_MASK }, // 638 |
18104 | | { 0x4, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG4EI32_V_M1_MF4_MASK }, // 639 |
18105 | | { 0x4, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF4_MASK }, // 640 |
18106 | | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG4EI32_V_M1_MF2_MASK }, // 641 |
18107 | | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG4EI32_V_M2_MF2_MASK }, // 642 |
18108 | | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG4EI32_V_MF2_MF2_MASK }, // 643 |
18109 | | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG4EI64_V_M1_M1_MASK }, // 644 |
18110 | | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG4EI64_V_M2_M1_MASK }, // 645 |
18111 | | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG4EI64_V_M4_M1_MASK }, // 646 |
18112 | | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG4EI64_V_M8_M1_MASK }, // 647 |
18113 | | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXSEG4EI64_V_M2_M2_MASK }, // 648 |
18114 | | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXSEG4EI64_V_M4_M2_MASK }, // 649 |
18115 | | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXSEG4EI64_V_M8_M2_MASK }, // 650 |
18116 | | { 0x4, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG4EI64_V_M1_MF8_MASK }, // 651 |
18117 | | { 0x4, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG4EI64_V_M1_MF4_MASK }, // 652 |
18118 | | { 0x4, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG4EI64_V_M2_MF4_MASK }, // 653 |
18119 | | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG4EI64_V_M1_MF2_MASK }, // 654 |
18120 | | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG4EI64_V_M2_MF2_MASK }, // 655 |
18121 | | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG4EI64_V_M4_MF2_MASK }, // 656 |
18122 | | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG4EI8_V_M1_M1_MASK }, // 657 |
18123 | | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG4EI8_V_MF8_M1_MASK }, // 658 |
18124 | | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG4EI8_V_MF4_M1_MASK }, // 659 |
18125 | | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG4EI8_V_MF2_M1_MASK }, // 660 |
18126 | | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXSEG4EI8_V_M1_M2_MASK }, // 661 |
18127 | | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXSEG4EI8_V_M2_M2_MASK }, // 662 |
18128 | | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXSEG4EI8_V_MF4_M2_MASK }, // 663 |
18129 | | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXSEG4EI8_V_MF2_M2_MASK }, // 664 |
18130 | | { 0x4, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF8_MASK }, // 665 |
18131 | | { 0x4, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF4_MASK }, // 666 |
18132 | | { 0x4, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF4_MASK }, // 667 |
18133 | | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG4EI8_V_MF8_MF2_MASK }, // 668 |
18134 | | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG4EI8_V_MF4_MF2_MASK }, // 669 |
18135 | | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG4EI8_V_MF2_MF2_MASK }, // 670 |
18136 | | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG4EI16_V_M1_M1_MASK }, // 671 |
18137 | | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG4EI16_V_M2_M1_MASK }, // 672 |
18138 | | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG4EI16_V_MF4_M1_MASK }, // 673 |
18139 | | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG4EI16_V_MF2_M1_MASK }, // 674 |
18140 | | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXSEG4EI16_V_M1_M2_MASK }, // 675 |
18141 | | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXSEG4EI16_V_M2_M2_MASK }, // 676 |
18142 | | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXSEG4EI16_V_M4_M2_MASK }, // 677 |
18143 | | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXSEG4EI16_V_MF2_M2_MASK }, // 678 |
18144 | | { 0x4, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF8_MASK }, // 679 |
18145 | | { 0x4, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF4_MASK }, // 680 |
18146 | | { 0x4, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF4_MASK }, // 681 |
18147 | | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG4EI16_V_M1_MF2_MASK }, // 682 |
18148 | | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG4EI16_V_MF4_MF2_MASK }, // 683 |
18149 | | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG4EI16_V_MF2_MF2_MASK }, // 684 |
18150 | | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG4EI32_V_M1_M1_MASK }, // 685 |
18151 | | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG4EI32_V_M2_M1_MASK }, // 686 |
18152 | | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG4EI32_V_M4_M1_MASK }, // 687 |
18153 | | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG4EI32_V_MF2_M1_MASK }, // 688 |
18154 | | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXSEG4EI32_V_M1_M2_MASK }, // 689 |
18155 | | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXSEG4EI32_V_M2_M2_MASK }, // 690 |
18156 | | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXSEG4EI32_V_M4_M2_MASK }, // 691 |
18157 | | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXSEG4EI32_V_M8_M2_MASK }, // 692 |
18158 | | { 0x4, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF8_MASK }, // 693 |
18159 | | { 0x4, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG4EI32_V_M1_MF4_MASK }, // 694 |
18160 | | { 0x4, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF4_MASK }, // 695 |
18161 | | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG4EI32_V_M1_MF2_MASK }, // 696 |
18162 | | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG4EI32_V_M2_MF2_MASK }, // 697 |
18163 | | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG4EI32_V_MF2_MF2_MASK }, // 698 |
18164 | | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG4EI64_V_M1_M1_MASK }, // 699 |
18165 | | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG4EI64_V_M2_M1_MASK }, // 700 |
18166 | | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG4EI64_V_M4_M1_MASK }, // 701 |
18167 | | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG4EI64_V_M8_M1_MASK }, // 702 |
18168 | | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXSEG4EI64_V_M2_M2_MASK }, // 703 |
18169 | | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXSEG4EI64_V_M4_M2_MASK }, // 704 |
18170 | | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXSEG4EI64_V_M8_M2_MASK }, // 705 |
18171 | | { 0x4, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG4EI64_V_M1_MF8_MASK }, // 706 |
18172 | | { 0x4, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG4EI64_V_M1_MF4_MASK }, // 707 |
18173 | | { 0x4, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG4EI64_V_M2_MF4_MASK }, // 708 |
18174 | | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG4EI64_V_M1_MF2_MASK }, // 709 |
18175 | | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG4EI64_V_M2_MF2_MASK }, // 710 |
18176 | | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG4EI64_V_M4_MF2_MASK }, // 711 |
18177 | | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG5EI8_V_M1_M1 }, // 712 |
18178 | | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG5EI8_V_MF8_M1 }, // 713 |
18179 | | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG5EI8_V_MF4_M1 }, // 714 |
18180 | | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG5EI8_V_MF2_M1 }, // 715 |
18181 | | { 0x5, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF8 }, // 716 |
18182 | | { 0x5, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF4 }, // 717 |
18183 | | { 0x5, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF4 }, // 718 |
18184 | | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF2 }, // 719 |
18185 | | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF2 }, // 720 |
18186 | | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG5EI8_V_MF2_MF2 }, // 721 |
18187 | | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG5EI16_V_M1_M1 }, // 722 |
18188 | | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG5EI16_V_M2_M1 }, // 723 |
18189 | | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG5EI16_V_MF4_M1 }, // 724 |
18190 | | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG5EI16_V_MF2_M1 }, // 725 |
18191 | | { 0x5, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF8 }, // 726 |
18192 | | { 0x5, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF4 }, // 727 |
18193 | | { 0x5, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF4 }, // 728 |
18194 | | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG5EI16_V_M1_MF2 }, // 729 |
18195 | | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF2 }, // 730 |
18196 | | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF2 }, // 731 |
18197 | | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG5EI32_V_M1_M1 }, // 732 |
18198 | | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG5EI32_V_M2_M1 }, // 733 |
18199 | | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG5EI32_V_M4_M1 }, // 734 |
18200 | | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG5EI32_V_MF2_M1 }, // 735 |
18201 | | { 0x5, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF8 }, // 736 |
18202 | | { 0x5, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG5EI32_V_M1_MF4 }, // 737 |
18203 | | { 0x5, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF4 }, // 738 |
18204 | | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG5EI32_V_M1_MF2 }, // 739 |
18205 | | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG5EI32_V_M2_MF2 }, // 740 |
18206 | | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF2 }, // 741 |
18207 | | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG5EI64_V_M1_M1 }, // 742 |
18208 | | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG5EI64_V_M2_M1 }, // 743 |
18209 | | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG5EI64_V_M4_M1 }, // 744 |
18210 | | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG5EI64_V_M8_M1 }, // 745 |
18211 | | { 0x5, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG5EI64_V_M1_MF8 }, // 746 |
18212 | | { 0x5, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG5EI64_V_M1_MF4 }, // 747 |
18213 | | { 0x5, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG5EI64_V_M2_MF4 }, // 748 |
18214 | | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG5EI64_V_M1_MF2 }, // 749 |
18215 | | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG5EI64_V_M2_MF2 }, // 750 |
18216 | | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG5EI64_V_M4_MF2 }, // 751 |
18217 | | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG5EI8_V_M1_M1 }, // 752 |
18218 | | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG5EI8_V_MF8_M1 }, // 753 |
18219 | | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG5EI8_V_MF4_M1 }, // 754 |
18220 | | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG5EI8_V_MF2_M1 }, // 755 |
18221 | | { 0x5, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF8 }, // 756 |
18222 | | { 0x5, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF4 }, // 757 |
18223 | | { 0x5, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF4 }, // 758 |
18224 | | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF2 }, // 759 |
18225 | | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF2 }, // 760 |
18226 | | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG5EI8_V_MF2_MF2 }, // 761 |
18227 | | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG5EI16_V_M1_M1 }, // 762 |
18228 | | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG5EI16_V_M2_M1 }, // 763 |
18229 | | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG5EI16_V_MF4_M1 }, // 764 |
18230 | | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG5EI16_V_MF2_M1 }, // 765 |
18231 | | { 0x5, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF8 }, // 766 |
18232 | | { 0x5, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF4 }, // 767 |
18233 | | { 0x5, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF4 }, // 768 |
18234 | | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG5EI16_V_M1_MF2 }, // 769 |
18235 | | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF2 }, // 770 |
18236 | | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF2 }, // 771 |
18237 | | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG5EI32_V_M1_M1 }, // 772 |
18238 | | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG5EI32_V_M2_M1 }, // 773 |
18239 | | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG5EI32_V_M4_M1 }, // 774 |
18240 | | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG5EI32_V_MF2_M1 }, // 775 |
18241 | | { 0x5, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF8 }, // 776 |
18242 | | { 0x5, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG5EI32_V_M1_MF4 }, // 777 |
18243 | | { 0x5, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF4 }, // 778 |
18244 | | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG5EI32_V_M1_MF2 }, // 779 |
18245 | | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG5EI32_V_M2_MF2 }, // 780 |
18246 | | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF2 }, // 781 |
18247 | | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG5EI64_V_M1_M1 }, // 782 |
18248 | | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG5EI64_V_M2_M1 }, // 783 |
18249 | | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG5EI64_V_M4_M1 }, // 784 |
18250 | | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG5EI64_V_M8_M1 }, // 785 |
18251 | | { 0x5, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG5EI64_V_M1_MF8 }, // 786 |
18252 | | { 0x5, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG5EI64_V_M1_MF4 }, // 787 |
18253 | | { 0x5, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG5EI64_V_M2_MF4 }, // 788 |
18254 | | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG5EI64_V_M1_MF2 }, // 789 |
18255 | | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG5EI64_V_M2_MF2 }, // 790 |
18256 | | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG5EI64_V_M4_MF2 }, // 791 |
18257 | | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG5EI8_V_M1_M1_MASK }, // 792 |
18258 | | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG5EI8_V_MF8_M1_MASK }, // 793 |
18259 | | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG5EI8_V_MF4_M1_MASK }, // 794 |
18260 | | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG5EI8_V_MF2_M1_MASK }, // 795 |
18261 | | { 0x5, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF8_MASK }, // 796 |
18262 | | { 0x5, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF4_MASK }, // 797 |
18263 | | { 0x5, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF4_MASK }, // 798 |
18264 | | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG5EI8_V_MF8_MF2_MASK }, // 799 |
18265 | | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG5EI8_V_MF4_MF2_MASK }, // 800 |
18266 | | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG5EI8_V_MF2_MF2_MASK }, // 801 |
18267 | | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG5EI16_V_M1_M1_MASK }, // 802 |
18268 | | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG5EI16_V_M2_M1_MASK }, // 803 |
18269 | | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG5EI16_V_MF4_M1_MASK }, // 804 |
18270 | | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG5EI16_V_MF2_M1_MASK }, // 805 |
18271 | | { 0x5, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF8_MASK }, // 806 |
18272 | | { 0x5, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF4_MASK }, // 807 |
18273 | | { 0x5, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF4_MASK }, // 808 |
18274 | | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG5EI16_V_M1_MF2_MASK }, // 809 |
18275 | | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG5EI16_V_MF4_MF2_MASK }, // 810 |
18276 | | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG5EI16_V_MF2_MF2_MASK }, // 811 |
18277 | | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG5EI32_V_M1_M1_MASK }, // 812 |
18278 | | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG5EI32_V_M2_M1_MASK }, // 813 |
18279 | | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG5EI32_V_M4_M1_MASK }, // 814 |
18280 | | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG5EI32_V_MF2_M1_MASK }, // 815 |
18281 | | { 0x5, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF8_MASK }, // 816 |
18282 | | { 0x5, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG5EI32_V_M1_MF4_MASK }, // 817 |
18283 | | { 0x5, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF4_MASK }, // 818 |
18284 | | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG5EI32_V_M1_MF2_MASK }, // 819 |
18285 | | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG5EI32_V_M2_MF2_MASK }, // 820 |
18286 | | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG5EI32_V_MF2_MF2_MASK }, // 821 |
18287 | | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG5EI64_V_M1_M1_MASK }, // 822 |
18288 | | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG5EI64_V_M2_M1_MASK }, // 823 |
18289 | | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG5EI64_V_M4_M1_MASK }, // 824 |
18290 | | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG5EI64_V_M8_M1_MASK }, // 825 |
18291 | | { 0x5, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG5EI64_V_M1_MF8_MASK }, // 826 |
18292 | | { 0x5, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG5EI64_V_M1_MF4_MASK }, // 827 |
18293 | | { 0x5, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG5EI64_V_M2_MF4_MASK }, // 828 |
18294 | | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG5EI64_V_M1_MF2_MASK }, // 829 |
18295 | | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG5EI64_V_M2_MF2_MASK }, // 830 |
18296 | | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG5EI64_V_M4_MF2_MASK }, // 831 |
18297 | | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG5EI8_V_M1_M1_MASK }, // 832 |
18298 | | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG5EI8_V_MF8_M1_MASK }, // 833 |
18299 | | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG5EI8_V_MF4_M1_MASK }, // 834 |
18300 | | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG5EI8_V_MF2_M1_MASK }, // 835 |
18301 | | { 0x5, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF8_MASK }, // 836 |
18302 | | { 0x5, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF4_MASK }, // 837 |
18303 | | { 0x5, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF4_MASK }, // 838 |
18304 | | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG5EI8_V_MF8_MF2_MASK }, // 839 |
18305 | | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG5EI8_V_MF4_MF2_MASK }, // 840 |
18306 | | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG5EI8_V_MF2_MF2_MASK }, // 841 |
18307 | | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG5EI16_V_M1_M1_MASK }, // 842 |
18308 | | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG5EI16_V_M2_M1_MASK }, // 843 |
18309 | | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG5EI16_V_MF4_M1_MASK }, // 844 |
18310 | | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG5EI16_V_MF2_M1_MASK }, // 845 |
18311 | | { 0x5, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF8_MASK }, // 846 |
18312 | | { 0x5, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF4_MASK }, // 847 |
18313 | | { 0x5, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF4_MASK }, // 848 |
18314 | | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG5EI16_V_M1_MF2_MASK }, // 849 |
18315 | | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG5EI16_V_MF4_MF2_MASK }, // 850 |
18316 | | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG5EI16_V_MF2_MF2_MASK }, // 851 |
18317 | | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG5EI32_V_M1_M1_MASK }, // 852 |
18318 | | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG5EI32_V_M2_M1_MASK }, // 853 |
18319 | | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG5EI32_V_M4_M1_MASK }, // 854 |
18320 | | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG5EI32_V_MF2_M1_MASK }, // 855 |
18321 | | { 0x5, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF8_MASK }, // 856 |
18322 | | { 0x5, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG5EI32_V_M1_MF4_MASK }, // 857 |
18323 | | { 0x5, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF4_MASK }, // 858 |
18324 | | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG5EI32_V_M1_MF2_MASK }, // 859 |
18325 | | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG5EI32_V_M2_MF2_MASK }, // 860 |
18326 | | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG5EI32_V_MF2_MF2_MASK }, // 861 |
18327 | | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG5EI64_V_M1_M1_MASK }, // 862 |
18328 | | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG5EI64_V_M2_M1_MASK }, // 863 |
18329 | | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG5EI64_V_M4_M1_MASK }, // 864 |
18330 | | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG5EI64_V_M8_M1_MASK }, // 865 |
18331 | | { 0x5, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG5EI64_V_M1_MF8_MASK }, // 866 |
18332 | | { 0x5, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG5EI64_V_M1_MF4_MASK }, // 867 |
18333 | | { 0x5, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG5EI64_V_M2_MF4_MASK }, // 868 |
18334 | | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG5EI64_V_M1_MF2_MASK }, // 869 |
18335 | | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG5EI64_V_M2_MF2_MASK }, // 870 |
18336 | | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG5EI64_V_M4_MF2_MASK }, // 871 |
18337 | | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG6EI8_V_M1_M1 }, // 872 |
18338 | | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG6EI8_V_MF8_M1 }, // 873 |
18339 | | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG6EI8_V_MF4_M1 }, // 874 |
18340 | | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG6EI8_V_MF2_M1 }, // 875 |
18341 | | { 0x6, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF8 }, // 876 |
18342 | | { 0x6, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF4 }, // 877 |
18343 | | { 0x6, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF4 }, // 878 |
18344 | | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF2 }, // 879 |
18345 | | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF2 }, // 880 |
18346 | | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG6EI8_V_MF2_MF2 }, // 881 |
18347 | | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG6EI16_V_M1_M1 }, // 882 |
18348 | | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG6EI16_V_M2_M1 }, // 883 |
18349 | | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG6EI16_V_MF4_M1 }, // 884 |
18350 | | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG6EI16_V_MF2_M1 }, // 885 |
18351 | | { 0x6, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF8 }, // 886 |
18352 | | { 0x6, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF4 }, // 887 |
18353 | | { 0x6, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF4 }, // 888 |
18354 | | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG6EI16_V_M1_MF2 }, // 889 |
18355 | | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF2 }, // 890 |
18356 | | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF2 }, // 891 |
18357 | | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG6EI32_V_M1_M1 }, // 892 |
18358 | | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG6EI32_V_M2_M1 }, // 893 |
18359 | | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG6EI32_V_M4_M1 }, // 894 |
18360 | | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG6EI32_V_MF2_M1 }, // 895 |
18361 | | { 0x6, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF8 }, // 896 |
18362 | | { 0x6, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG6EI32_V_M1_MF4 }, // 897 |
18363 | | { 0x6, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF4 }, // 898 |
18364 | | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG6EI32_V_M1_MF2 }, // 899 |
18365 | | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG6EI32_V_M2_MF2 }, // 900 |
18366 | | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF2 }, // 901 |
18367 | | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG6EI64_V_M1_M1 }, // 902 |
18368 | | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG6EI64_V_M2_M1 }, // 903 |
18369 | | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG6EI64_V_M4_M1 }, // 904 |
18370 | | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG6EI64_V_M8_M1 }, // 905 |
18371 | | { 0x6, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG6EI64_V_M1_MF8 }, // 906 |
18372 | | { 0x6, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG6EI64_V_M1_MF4 }, // 907 |
18373 | | { 0x6, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG6EI64_V_M2_MF4 }, // 908 |
18374 | | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG6EI64_V_M1_MF2 }, // 909 |
18375 | | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG6EI64_V_M2_MF2 }, // 910 |
18376 | | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG6EI64_V_M4_MF2 }, // 911 |
18377 | | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG6EI8_V_M1_M1 }, // 912 |
18378 | | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG6EI8_V_MF8_M1 }, // 913 |
18379 | | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG6EI8_V_MF4_M1 }, // 914 |
18380 | | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG6EI8_V_MF2_M1 }, // 915 |
18381 | | { 0x6, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF8 }, // 916 |
18382 | | { 0x6, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF4 }, // 917 |
18383 | | { 0x6, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF4 }, // 918 |
18384 | | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF2 }, // 919 |
18385 | | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF2 }, // 920 |
18386 | | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG6EI8_V_MF2_MF2 }, // 921 |
18387 | | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG6EI16_V_M1_M1 }, // 922 |
18388 | | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG6EI16_V_M2_M1 }, // 923 |
18389 | | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG6EI16_V_MF4_M1 }, // 924 |
18390 | | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG6EI16_V_MF2_M1 }, // 925 |
18391 | | { 0x6, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF8 }, // 926 |
18392 | | { 0x6, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF4 }, // 927 |
18393 | | { 0x6, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF4 }, // 928 |
18394 | | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG6EI16_V_M1_MF2 }, // 929 |
18395 | | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF2 }, // 930 |
18396 | | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF2 }, // 931 |
18397 | | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG6EI32_V_M1_M1 }, // 932 |
18398 | | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG6EI32_V_M2_M1 }, // 933 |
18399 | | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG6EI32_V_M4_M1 }, // 934 |
18400 | | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG6EI32_V_MF2_M1 }, // 935 |
18401 | | { 0x6, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF8 }, // 936 |
18402 | | { 0x6, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG6EI32_V_M1_MF4 }, // 937 |
18403 | | { 0x6, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF4 }, // 938 |
18404 | | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG6EI32_V_M1_MF2 }, // 939 |
18405 | | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG6EI32_V_M2_MF2 }, // 940 |
18406 | | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF2 }, // 941 |
18407 | | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG6EI64_V_M1_M1 }, // 942 |
18408 | | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG6EI64_V_M2_M1 }, // 943 |
18409 | | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG6EI64_V_M4_M1 }, // 944 |
18410 | | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG6EI64_V_M8_M1 }, // 945 |
18411 | | { 0x6, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG6EI64_V_M1_MF8 }, // 946 |
18412 | | { 0x6, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG6EI64_V_M1_MF4 }, // 947 |
18413 | | { 0x6, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG6EI64_V_M2_MF4 }, // 948 |
18414 | | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG6EI64_V_M1_MF2 }, // 949 |
18415 | | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG6EI64_V_M2_MF2 }, // 950 |
18416 | | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG6EI64_V_M4_MF2 }, // 951 |
18417 | | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG6EI8_V_M1_M1_MASK }, // 952 |
18418 | | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG6EI8_V_MF8_M1_MASK }, // 953 |
18419 | | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG6EI8_V_MF4_M1_MASK }, // 954 |
18420 | | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG6EI8_V_MF2_M1_MASK }, // 955 |
18421 | | { 0x6, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF8_MASK }, // 956 |
18422 | | { 0x6, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF4_MASK }, // 957 |
18423 | | { 0x6, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF4_MASK }, // 958 |
18424 | | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG6EI8_V_MF8_MF2_MASK }, // 959 |
18425 | | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG6EI8_V_MF4_MF2_MASK }, // 960 |
18426 | | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG6EI8_V_MF2_MF2_MASK }, // 961 |
18427 | | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG6EI16_V_M1_M1_MASK }, // 962 |
18428 | | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG6EI16_V_M2_M1_MASK }, // 963 |
18429 | | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG6EI16_V_MF4_M1_MASK }, // 964 |
18430 | | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG6EI16_V_MF2_M1_MASK }, // 965 |
18431 | | { 0x6, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF8_MASK }, // 966 |
18432 | | { 0x6, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF4_MASK }, // 967 |
18433 | | { 0x6, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF4_MASK }, // 968 |
18434 | | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG6EI16_V_M1_MF2_MASK }, // 969 |
18435 | | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG6EI16_V_MF4_MF2_MASK }, // 970 |
18436 | | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG6EI16_V_MF2_MF2_MASK }, // 971 |
18437 | | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG6EI32_V_M1_M1_MASK }, // 972 |
18438 | | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG6EI32_V_M2_M1_MASK }, // 973 |
18439 | | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG6EI32_V_M4_M1_MASK }, // 974 |
18440 | | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG6EI32_V_MF2_M1_MASK }, // 975 |
18441 | | { 0x6, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF8_MASK }, // 976 |
18442 | | { 0x6, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG6EI32_V_M1_MF4_MASK }, // 977 |
18443 | | { 0x6, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF4_MASK }, // 978 |
18444 | | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG6EI32_V_M1_MF2_MASK }, // 979 |
18445 | | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG6EI32_V_M2_MF2_MASK }, // 980 |
18446 | | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG6EI32_V_MF2_MF2_MASK }, // 981 |
18447 | | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG6EI64_V_M1_M1_MASK }, // 982 |
18448 | | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG6EI64_V_M2_M1_MASK }, // 983 |
18449 | | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG6EI64_V_M4_M1_MASK }, // 984 |
18450 | | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG6EI64_V_M8_M1_MASK }, // 985 |
18451 | | { 0x6, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG6EI64_V_M1_MF8_MASK }, // 986 |
18452 | | { 0x6, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG6EI64_V_M1_MF4_MASK }, // 987 |
18453 | | { 0x6, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG6EI64_V_M2_MF4_MASK }, // 988 |
18454 | | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG6EI64_V_M1_MF2_MASK }, // 989 |
18455 | | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG6EI64_V_M2_MF2_MASK }, // 990 |
18456 | | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG6EI64_V_M4_MF2_MASK }, // 991 |
18457 | | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG6EI8_V_M1_M1_MASK }, // 992 |
18458 | | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG6EI8_V_MF8_M1_MASK }, // 993 |
18459 | | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG6EI8_V_MF4_M1_MASK }, // 994 |
18460 | | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG6EI8_V_MF2_M1_MASK }, // 995 |
18461 | | { 0x6, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF8_MASK }, // 996 |
18462 | | { 0x6, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF4_MASK }, // 997 |
18463 | | { 0x6, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF4_MASK }, // 998 |
18464 | | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG6EI8_V_MF8_MF2_MASK }, // 999 |
18465 | | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG6EI8_V_MF4_MF2_MASK }, // 1000 |
18466 | | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG6EI8_V_MF2_MF2_MASK }, // 1001 |
18467 | | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG6EI16_V_M1_M1_MASK }, // 1002 |
18468 | | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG6EI16_V_M2_M1_MASK }, // 1003 |
18469 | | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG6EI16_V_MF4_M1_MASK }, // 1004 |
18470 | | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG6EI16_V_MF2_M1_MASK }, // 1005 |
18471 | | { 0x6, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF8_MASK }, // 1006 |
18472 | | { 0x6, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF4_MASK }, // 1007 |
18473 | | { 0x6, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF4_MASK }, // 1008 |
18474 | | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG6EI16_V_M1_MF2_MASK }, // 1009 |
18475 | | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG6EI16_V_MF4_MF2_MASK }, // 1010 |
18476 | | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG6EI16_V_MF2_MF2_MASK }, // 1011 |
18477 | | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG6EI32_V_M1_M1_MASK }, // 1012 |
18478 | | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG6EI32_V_M2_M1_MASK }, // 1013 |
18479 | | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG6EI32_V_M4_M1_MASK }, // 1014 |
18480 | | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG6EI32_V_MF2_M1_MASK }, // 1015 |
18481 | | { 0x6, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF8_MASK }, // 1016 |
18482 | | { 0x6, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG6EI32_V_M1_MF4_MASK }, // 1017 |
18483 | | { 0x6, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF4_MASK }, // 1018 |
18484 | | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG6EI32_V_M1_MF2_MASK }, // 1019 |
18485 | | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG6EI32_V_M2_MF2_MASK }, // 1020 |
18486 | | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG6EI32_V_MF2_MF2_MASK }, // 1021 |
18487 | | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG6EI64_V_M1_M1_MASK }, // 1022 |
18488 | | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG6EI64_V_M2_M1_MASK }, // 1023 |
18489 | | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG6EI64_V_M4_M1_MASK }, // 1024 |
18490 | | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG6EI64_V_M8_M1_MASK }, // 1025 |
18491 | | { 0x6, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG6EI64_V_M1_MF8_MASK }, // 1026 |
18492 | | { 0x6, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG6EI64_V_M1_MF4_MASK }, // 1027 |
18493 | | { 0x6, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG6EI64_V_M2_MF4_MASK }, // 1028 |
18494 | | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG6EI64_V_M1_MF2_MASK }, // 1029 |
18495 | | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG6EI64_V_M2_MF2_MASK }, // 1030 |
18496 | | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG6EI64_V_M4_MF2_MASK }, // 1031 |
18497 | | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG7EI8_V_M1_M1 }, // 1032 |
18498 | | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG7EI8_V_MF8_M1 }, // 1033 |
18499 | | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG7EI8_V_MF4_M1 }, // 1034 |
18500 | | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG7EI8_V_MF2_M1 }, // 1035 |
18501 | | { 0x7, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF8 }, // 1036 |
18502 | | { 0x7, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF4 }, // 1037 |
18503 | | { 0x7, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF4 }, // 1038 |
18504 | | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF2 }, // 1039 |
18505 | | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF2 }, // 1040 |
18506 | | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG7EI8_V_MF2_MF2 }, // 1041 |
18507 | | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG7EI16_V_M1_M1 }, // 1042 |
18508 | | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG7EI16_V_M2_M1 }, // 1043 |
18509 | | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG7EI16_V_MF4_M1 }, // 1044 |
18510 | | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG7EI16_V_MF2_M1 }, // 1045 |
18511 | | { 0x7, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF8 }, // 1046 |
18512 | | { 0x7, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF4 }, // 1047 |
18513 | | { 0x7, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF4 }, // 1048 |
18514 | | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG7EI16_V_M1_MF2 }, // 1049 |
18515 | | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF2 }, // 1050 |
18516 | | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF2 }, // 1051 |
18517 | | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG7EI32_V_M1_M1 }, // 1052 |
18518 | | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG7EI32_V_M2_M1 }, // 1053 |
18519 | | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG7EI32_V_M4_M1 }, // 1054 |
18520 | | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG7EI32_V_MF2_M1 }, // 1055 |
18521 | | { 0x7, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF8 }, // 1056 |
18522 | | { 0x7, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG7EI32_V_M1_MF4 }, // 1057 |
18523 | | { 0x7, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF4 }, // 1058 |
18524 | | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG7EI32_V_M1_MF2 }, // 1059 |
18525 | | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG7EI32_V_M2_MF2 }, // 1060 |
18526 | | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF2 }, // 1061 |
18527 | | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG7EI64_V_M1_M1 }, // 1062 |
18528 | | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG7EI64_V_M2_M1 }, // 1063 |
18529 | | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG7EI64_V_M4_M1 }, // 1064 |
18530 | | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG7EI64_V_M8_M1 }, // 1065 |
18531 | | { 0x7, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG7EI64_V_M1_MF8 }, // 1066 |
18532 | | { 0x7, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG7EI64_V_M1_MF4 }, // 1067 |
18533 | | { 0x7, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG7EI64_V_M2_MF4 }, // 1068 |
18534 | | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG7EI64_V_M1_MF2 }, // 1069 |
18535 | | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG7EI64_V_M2_MF2 }, // 1070 |
18536 | | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG7EI64_V_M4_MF2 }, // 1071 |
18537 | | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG7EI8_V_M1_M1 }, // 1072 |
18538 | | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG7EI8_V_MF8_M1 }, // 1073 |
18539 | | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG7EI8_V_MF4_M1 }, // 1074 |
18540 | | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG7EI8_V_MF2_M1 }, // 1075 |
18541 | | { 0x7, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF8 }, // 1076 |
18542 | | { 0x7, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF4 }, // 1077 |
18543 | | { 0x7, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF4 }, // 1078 |
18544 | | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF2 }, // 1079 |
18545 | | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF2 }, // 1080 |
18546 | | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG7EI8_V_MF2_MF2 }, // 1081 |
18547 | | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG7EI16_V_M1_M1 }, // 1082 |
18548 | | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG7EI16_V_M2_M1 }, // 1083 |
18549 | | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG7EI16_V_MF4_M1 }, // 1084 |
18550 | | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG7EI16_V_MF2_M1 }, // 1085 |
18551 | | { 0x7, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF8 }, // 1086 |
18552 | | { 0x7, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF4 }, // 1087 |
18553 | | { 0x7, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF4 }, // 1088 |
18554 | | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG7EI16_V_M1_MF2 }, // 1089 |
18555 | | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF2 }, // 1090 |
18556 | | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF2 }, // 1091 |
18557 | | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG7EI32_V_M1_M1 }, // 1092 |
18558 | | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG7EI32_V_M2_M1 }, // 1093 |
18559 | | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG7EI32_V_M4_M1 }, // 1094 |
18560 | | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG7EI32_V_MF2_M1 }, // 1095 |
18561 | | { 0x7, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF8 }, // 1096 |
18562 | | { 0x7, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG7EI32_V_M1_MF4 }, // 1097 |
18563 | | { 0x7, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF4 }, // 1098 |
18564 | | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG7EI32_V_M1_MF2 }, // 1099 |
18565 | | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG7EI32_V_M2_MF2 }, // 1100 |
18566 | | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF2 }, // 1101 |
18567 | | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG7EI64_V_M1_M1 }, // 1102 |
18568 | | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG7EI64_V_M2_M1 }, // 1103 |
18569 | | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG7EI64_V_M4_M1 }, // 1104 |
18570 | | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG7EI64_V_M8_M1 }, // 1105 |
18571 | | { 0x7, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG7EI64_V_M1_MF8 }, // 1106 |
18572 | | { 0x7, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG7EI64_V_M1_MF4 }, // 1107 |
18573 | | { 0x7, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG7EI64_V_M2_MF4 }, // 1108 |
18574 | | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG7EI64_V_M1_MF2 }, // 1109 |
18575 | | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG7EI64_V_M2_MF2 }, // 1110 |
18576 | | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG7EI64_V_M4_MF2 }, // 1111 |
18577 | | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG7EI8_V_M1_M1_MASK }, // 1112 |
18578 | | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG7EI8_V_MF8_M1_MASK }, // 1113 |
18579 | | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG7EI8_V_MF4_M1_MASK }, // 1114 |
18580 | | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG7EI8_V_MF2_M1_MASK }, // 1115 |
18581 | | { 0x7, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF8_MASK }, // 1116 |
18582 | | { 0x7, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF4_MASK }, // 1117 |
18583 | | { 0x7, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF4_MASK }, // 1118 |
18584 | | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG7EI8_V_MF8_MF2_MASK }, // 1119 |
18585 | | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG7EI8_V_MF4_MF2_MASK }, // 1120 |
18586 | | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG7EI8_V_MF2_MF2_MASK }, // 1121 |
18587 | | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG7EI16_V_M1_M1_MASK }, // 1122 |
18588 | | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG7EI16_V_M2_M1_MASK }, // 1123 |
18589 | | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG7EI16_V_MF4_M1_MASK }, // 1124 |
18590 | | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG7EI16_V_MF2_M1_MASK }, // 1125 |
18591 | | { 0x7, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF8_MASK }, // 1126 |
18592 | | { 0x7, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF4_MASK }, // 1127 |
18593 | | { 0x7, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF4_MASK }, // 1128 |
18594 | | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG7EI16_V_M1_MF2_MASK }, // 1129 |
18595 | | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG7EI16_V_MF4_MF2_MASK }, // 1130 |
18596 | | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG7EI16_V_MF2_MF2_MASK }, // 1131 |
18597 | | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG7EI32_V_M1_M1_MASK }, // 1132 |
18598 | | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG7EI32_V_M2_M1_MASK }, // 1133 |
18599 | | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG7EI32_V_M4_M1_MASK }, // 1134 |
18600 | | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG7EI32_V_MF2_M1_MASK }, // 1135 |
18601 | | { 0x7, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF8_MASK }, // 1136 |
18602 | | { 0x7, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG7EI32_V_M1_MF4_MASK }, // 1137 |
18603 | | { 0x7, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF4_MASK }, // 1138 |
18604 | | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG7EI32_V_M1_MF2_MASK }, // 1139 |
18605 | | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG7EI32_V_M2_MF2_MASK }, // 1140 |
18606 | | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG7EI32_V_MF2_MF2_MASK }, // 1141 |
18607 | | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG7EI64_V_M1_M1_MASK }, // 1142 |
18608 | | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG7EI64_V_M2_M1_MASK }, // 1143 |
18609 | | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG7EI64_V_M4_M1_MASK }, // 1144 |
18610 | | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG7EI64_V_M8_M1_MASK }, // 1145 |
18611 | | { 0x7, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG7EI64_V_M1_MF8_MASK }, // 1146 |
18612 | | { 0x7, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG7EI64_V_M1_MF4_MASK }, // 1147 |
18613 | | { 0x7, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG7EI64_V_M2_MF4_MASK }, // 1148 |
18614 | | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG7EI64_V_M1_MF2_MASK }, // 1149 |
18615 | | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG7EI64_V_M2_MF2_MASK }, // 1150 |
18616 | | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG7EI64_V_M4_MF2_MASK }, // 1151 |
18617 | | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG7EI8_V_M1_M1_MASK }, // 1152 |
18618 | | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG7EI8_V_MF8_M1_MASK }, // 1153 |
18619 | | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG7EI8_V_MF4_M1_MASK }, // 1154 |
18620 | | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG7EI8_V_MF2_M1_MASK }, // 1155 |
18621 | | { 0x7, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF8_MASK }, // 1156 |
18622 | | { 0x7, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF4_MASK }, // 1157 |
18623 | | { 0x7, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF4_MASK }, // 1158 |
18624 | | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG7EI8_V_MF8_MF2_MASK }, // 1159 |
18625 | | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG7EI8_V_MF4_MF2_MASK }, // 1160 |
18626 | | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG7EI8_V_MF2_MF2_MASK }, // 1161 |
18627 | | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG7EI16_V_M1_M1_MASK }, // 1162 |
18628 | | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG7EI16_V_M2_M1_MASK }, // 1163 |
18629 | | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG7EI16_V_MF4_M1_MASK }, // 1164 |
18630 | | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG7EI16_V_MF2_M1_MASK }, // 1165 |
18631 | | { 0x7, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF8_MASK }, // 1166 |
18632 | | { 0x7, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF4_MASK }, // 1167 |
18633 | | { 0x7, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF4_MASK }, // 1168 |
18634 | | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG7EI16_V_M1_MF2_MASK }, // 1169 |
18635 | | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG7EI16_V_MF4_MF2_MASK }, // 1170 |
18636 | | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG7EI16_V_MF2_MF2_MASK }, // 1171 |
18637 | | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG7EI32_V_M1_M1_MASK }, // 1172 |
18638 | | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG7EI32_V_M2_M1_MASK }, // 1173 |
18639 | | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG7EI32_V_M4_M1_MASK }, // 1174 |
18640 | | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG7EI32_V_MF2_M1_MASK }, // 1175 |
18641 | | { 0x7, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF8_MASK }, // 1176 |
18642 | | { 0x7, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG7EI32_V_M1_MF4_MASK }, // 1177 |
18643 | | { 0x7, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF4_MASK }, // 1178 |
18644 | | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG7EI32_V_M1_MF2_MASK }, // 1179 |
18645 | | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG7EI32_V_M2_MF2_MASK }, // 1180 |
18646 | | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG7EI32_V_MF2_MF2_MASK }, // 1181 |
18647 | | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG7EI64_V_M1_M1_MASK }, // 1182 |
18648 | | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG7EI64_V_M2_M1_MASK }, // 1183 |
18649 | | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG7EI64_V_M4_M1_MASK }, // 1184 |
18650 | | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG7EI64_V_M8_M1_MASK }, // 1185 |
18651 | | { 0x7, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG7EI64_V_M1_MF8_MASK }, // 1186 |
18652 | | { 0x7, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG7EI64_V_M1_MF4_MASK }, // 1187 |
18653 | | { 0x7, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG7EI64_V_M2_MF4_MASK }, // 1188 |
18654 | | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG7EI64_V_M1_MF2_MASK }, // 1189 |
18655 | | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG7EI64_V_M2_MF2_MASK }, // 1190 |
18656 | | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG7EI64_V_M4_MF2_MASK }, // 1191 |
18657 | | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG8EI8_V_M1_M1 }, // 1192 |
18658 | | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG8EI8_V_MF8_M1 }, // 1193 |
18659 | | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG8EI8_V_MF4_M1 }, // 1194 |
18660 | | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG8EI8_V_MF2_M1 }, // 1195 |
18661 | | { 0x8, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF8 }, // 1196 |
18662 | | { 0x8, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF4 }, // 1197 |
18663 | | { 0x8, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF4 }, // 1198 |
18664 | | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF2 }, // 1199 |
18665 | | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF2 }, // 1200 |
18666 | | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG8EI8_V_MF2_MF2 }, // 1201 |
18667 | | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG8EI16_V_M1_M1 }, // 1202 |
18668 | | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG8EI16_V_M2_M1 }, // 1203 |
18669 | | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG8EI16_V_MF4_M1 }, // 1204 |
18670 | | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG8EI16_V_MF2_M1 }, // 1205 |
18671 | | { 0x8, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF8 }, // 1206 |
18672 | | { 0x8, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF4 }, // 1207 |
18673 | | { 0x8, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF4 }, // 1208 |
18674 | | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG8EI16_V_M1_MF2 }, // 1209 |
18675 | | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF2 }, // 1210 |
18676 | | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF2 }, // 1211 |
18677 | | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG8EI32_V_M1_M1 }, // 1212 |
18678 | | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG8EI32_V_M2_M1 }, // 1213 |
18679 | | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG8EI32_V_M4_M1 }, // 1214 |
18680 | | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG8EI32_V_MF2_M1 }, // 1215 |
18681 | | { 0x8, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF8 }, // 1216 |
18682 | | { 0x8, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG8EI32_V_M1_MF4 }, // 1217 |
18683 | | { 0x8, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF4 }, // 1218 |
18684 | | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG8EI32_V_M1_MF2 }, // 1219 |
18685 | | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG8EI32_V_M2_MF2 }, // 1220 |
18686 | | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF2 }, // 1221 |
18687 | | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG8EI64_V_M1_M1 }, // 1222 |
18688 | | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG8EI64_V_M2_M1 }, // 1223 |
18689 | | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG8EI64_V_M4_M1 }, // 1224 |
18690 | | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG8EI64_V_M8_M1 }, // 1225 |
18691 | | { 0x8, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG8EI64_V_M1_MF8 }, // 1226 |
18692 | | { 0x8, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG8EI64_V_M1_MF4 }, // 1227 |
18693 | | { 0x8, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG8EI64_V_M2_MF4 }, // 1228 |
18694 | | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG8EI64_V_M1_MF2 }, // 1229 |
18695 | | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG8EI64_V_M2_MF2 }, // 1230 |
18696 | | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG8EI64_V_M4_MF2 }, // 1231 |
18697 | | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG8EI8_V_M1_M1 }, // 1232 |
18698 | | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG8EI8_V_MF8_M1 }, // 1233 |
18699 | | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG8EI8_V_MF4_M1 }, // 1234 |
18700 | | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG8EI8_V_MF2_M1 }, // 1235 |
18701 | | { 0x8, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF8 }, // 1236 |
18702 | | { 0x8, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF4 }, // 1237 |
18703 | | { 0x8, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF4 }, // 1238 |
18704 | | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF2 }, // 1239 |
18705 | | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF2 }, // 1240 |
18706 | | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG8EI8_V_MF2_MF2 }, // 1241 |
18707 | | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG8EI16_V_M1_M1 }, // 1242 |
18708 | | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG8EI16_V_M2_M1 }, // 1243 |
18709 | | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG8EI16_V_MF4_M1 }, // 1244 |
18710 | | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG8EI16_V_MF2_M1 }, // 1245 |
18711 | | { 0x8, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF8 }, // 1246 |
18712 | | { 0x8, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF4 }, // 1247 |
18713 | | { 0x8, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF4 }, // 1248 |
18714 | | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG8EI16_V_M1_MF2 }, // 1249 |
18715 | | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF2 }, // 1250 |
18716 | | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF2 }, // 1251 |
18717 | | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG8EI32_V_M1_M1 }, // 1252 |
18718 | | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG8EI32_V_M2_M1 }, // 1253 |
18719 | | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG8EI32_V_M4_M1 }, // 1254 |
18720 | | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG8EI32_V_MF2_M1 }, // 1255 |
18721 | | { 0x8, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF8 }, // 1256 |
18722 | | { 0x8, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG8EI32_V_M1_MF4 }, // 1257 |
18723 | | { 0x8, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF4 }, // 1258 |
18724 | | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG8EI32_V_M1_MF2 }, // 1259 |
18725 | | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG8EI32_V_M2_MF2 }, // 1260 |
18726 | | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF2 }, // 1261 |
18727 | | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG8EI64_V_M1_M1 }, // 1262 |
18728 | | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG8EI64_V_M2_M1 }, // 1263 |
18729 | | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG8EI64_V_M4_M1 }, // 1264 |
18730 | | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG8EI64_V_M8_M1 }, // 1265 |
18731 | | { 0x8, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG8EI64_V_M1_MF8 }, // 1266 |
18732 | | { 0x8, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG8EI64_V_M1_MF4 }, // 1267 |
18733 | | { 0x8, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG8EI64_V_M2_MF4 }, // 1268 |
18734 | | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG8EI64_V_M1_MF2 }, // 1269 |
18735 | | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG8EI64_V_M2_MF2 }, // 1270 |
18736 | | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG8EI64_V_M4_MF2 }, // 1271 |
18737 | | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXSEG8EI8_V_M1_M1_MASK }, // 1272 |
18738 | | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXSEG8EI8_V_MF8_M1_MASK }, // 1273 |
18739 | | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXSEG8EI8_V_MF4_M1_MASK }, // 1274 |
18740 | | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXSEG8EI8_V_MF2_M1_MASK }, // 1275 |
18741 | | { 0x8, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF8_MASK }, // 1276 |
18742 | | { 0x8, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF4_MASK }, // 1277 |
18743 | | { 0x8, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF4_MASK }, // 1278 |
18744 | | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXSEG8EI8_V_MF8_MF2_MASK }, // 1279 |
18745 | | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXSEG8EI8_V_MF4_MF2_MASK }, // 1280 |
18746 | | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXSEG8EI8_V_MF2_MF2_MASK }, // 1281 |
18747 | | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXSEG8EI16_V_M1_M1_MASK }, // 1282 |
18748 | | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXSEG8EI16_V_M2_M1_MASK }, // 1283 |
18749 | | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXSEG8EI16_V_MF4_M1_MASK }, // 1284 |
18750 | | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXSEG8EI16_V_MF2_M1_MASK }, // 1285 |
18751 | | { 0x8, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF8_MASK }, // 1286 |
18752 | | { 0x8, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF4_MASK }, // 1287 |
18753 | | { 0x8, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF4_MASK }, // 1288 |
18754 | | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXSEG8EI16_V_M1_MF2_MASK }, // 1289 |
18755 | | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXSEG8EI16_V_MF4_MF2_MASK }, // 1290 |
18756 | | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXSEG8EI16_V_MF2_MF2_MASK }, // 1291 |
18757 | | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXSEG8EI32_V_M1_M1_MASK }, // 1292 |
18758 | | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXSEG8EI32_V_M2_M1_MASK }, // 1293 |
18759 | | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXSEG8EI32_V_M4_M1_MASK }, // 1294 |
18760 | | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXSEG8EI32_V_MF2_M1_MASK }, // 1295 |
18761 | | { 0x8, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF8_MASK }, // 1296 |
18762 | | { 0x8, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXSEG8EI32_V_M1_MF4_MASK }, // 1297 |
18763 | | { 0x8, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF4_MASK }, // 1298 |
18764 | | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXSEG8EI32_V_M1_MF2_MASK }, // 1299 |
18765 | | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXSEG8EI32_V_M2_MF2_MASK }, // 1300 |
18766 | | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXSEG8EI32_V_MF2_MF2_MASK }, // 1301 |
18767 | | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXSEG8EI64_V_M1_M1_MASK }, // 1302 |
18768 | | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXSEG8EI64_V_M2_M1_MASK }, // 1303 |
18769 | | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXSEG8EI64_V_M4_M1_MASK }, // 1304 |
18770 | | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXSEG8EI64_V_M8_M1_MASK }, // 1305 |
18771 | | { 0x8, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXSEG8EI64_V_M1_MF8_MASK }, // 1306 |
18772 | | { 0x8, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXSEG8EI64_V_M1_MF4_MASK }, // 1307 |
18773 | | { 0x8, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXSEG8EI64_V_M2_MF4_MASK }, // 1308 |
18774 | | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXSEG8EI64_V_M1_MF2_MASK }, // 1309 |
18775 | | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXSEG8EI64_V_M2_MF2_MASK }, // 1310 |
18776 | | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXSEG8EI64_V_M4_MF2_MASK }, // 1311 |
18777 | | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXSEG8EI8_V_M1_M1_MASK }, // 1312 |
18778 | | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXSEG8EI8_V_MF8_M1_MASK }, // 1313 |
18779 | | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXSEG8EI8_V_MF4_M1_MASK }, // 1314 |
18780 | | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXSEG8EI8_V_MF2_M1_MASK }, // 1315 |
18781 | | { 0x8, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF8_MASK }, // 1316 |
18782 | | { 0x8, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF4_MASK }, // 1317 |
18783 | | { 0x8, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF4_MASK }, // 1318 |
18784 | | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXSEG8EI8_V_MF8_MF2_MASK }, // 1319 |
18785 | | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXSEG8EI8_V_MF4_MF2_MASK }, // 1320 |
18786 | | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXSEG8EI8_V_MF2_MF2_MASK }, // 1321 |
18787 | | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXSEG8EI16_V_M1_M1_MASK }, // 1322 |
18788 | | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXSEG8EI16_V_M2_M1_MASK }, // 1323 |
18789 | | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXSEG8EI16_V_MF4_M1_MASK }, // 1324 |
18790 | | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXSEG8EI16_V_MF2_M1_MASK }, // 1325 |
18791 | | { 0x8, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF8_MASK }, // 1326 |
18792 | | { 0x8, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF4_MASK }, // 1327 |
18793 | | { 0x8, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF4_MASK }, // 1328 |
18794 | | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXSEG8EI16_V_M1_MF2_MASK }, // 1329 |
18795 | | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXSEG8EI16_V_MF4_MF2_MASK }, // 1330 |
18796 | | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXSEG8EI16_V_MF2_MF2_MASK }, // 1331 |
18797 | | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXSEG8EI32_V_M1_M1_MASK }, // 1332 |
18798 | | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXSEG8EI32_V_M2_M1_MASK }, // 1333 |
18799 | | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXSEG8EI32_V_M4_M1_MASK }, // 1334 |
18800 | | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXSEG8EI32_V_MF2_M1_MASK }, // 1335 |
18801 | | { 0x8, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF8_MASK }, // 1336 |
18802 | | { 0x8, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXSEG8EI32_V_M1_MF4_MASK }, // 1337 |
18803 | | { 0x8, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF4_MASK }, // 1338 |
18804 | | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXSEG8EI32_V_M1_MF2_MASK }, // 1339 |
18805 | | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXSEG8EI32_V_M2_MF2_MASK }, // 1340 |
18806 | | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXSEG8EI32_V_MF2_MF2_MASK }, // 1341 |
18807 | | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXSEG8EI64_V_M1_M1_MASK }, // 1342 |
18808 | | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXSEG8EI64_V_M2_M1_MASK }, // 1343 |
18809 | | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXSEG8EI64_V_M4_M1_MASK }, // 1344 |
18810 | | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXSEG8EI64_V_M8_M1_MASK }, // 1345 |
18811 | | { 0x8, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXSEG8EI64_V_M1_MF8_MASK }, // 1346 |
18812 | | { 0x8, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXSEG8EI64_V_M1_MF4_MASK }, // 1347 |
18813 | | { 0x8, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXSEG8EI64_V_M2_MF4_MASK }, // 1348 |
18814 | | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXSEG8EI64_V_M1_MF2_MASK }, // 1349 |
18815 | | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXSEG8EI64_V_M2_MF2_MASK }, // 1350 |
18816 | | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXSEG8EI64_V_M4_MF2_MASK }, // 1351 |
18817 | | }; |
18818 | | |
18819 | | const RISCV_VLXSEGPseudo *RISCV_getVLXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) { |
18820 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), NFMaskedOrderedLog2SEWLMULIndexLMUL); |
18821 | | if (i == -1) |
18822 | | return NULL; |
18823 | | else |
18824 | | return &RISCVVLXSEGTable[Index[i].index]; |
18825 | | } |
18826 | | |
18827 | | #endif |
18828 | | |
18829 | | #ifdef GET_RISCVVLXTable_IMPL |
18830 | | static const RISCV_VLX_VSXPseudo RISCVVLXTable[] = { |
18831 | | { 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVLUXEI8_V_M1_M1 }, // 0 |
18832 | | { 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVLUXEI8_V_MF8_M1 }, // 1 |
18833 | | { 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVLUXEI8_V_MF4_M1 }, // 2 |
18834 | | { 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVLUXEI8_V_MF2_M1 }, // 3 |
18835 | | { 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVLUXEI8_V_M1_M2 }, // 4 |
18836 | | { 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVLUXEI8_V_M2_M2 }, // 5 |
18837 | | { 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVLUXEI8_V_MF4_M2 }, // 6 |
18838 | | { 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVLUXEI8_V_MF2_M2 }, // 7 |
18839 | | { 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVLUXEI8_V_M1_M4 }, // 8 |
18840 | | { 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVLUXEI8_V_M2_M4 }, // 9 |
18841 | | { 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVLUXEI8_V_M4_M4 }, // 10 |
18842 | | { 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVLUXEI8_V_MF2_M4 }, // 11 |
18843 | | { 0x0, 0x0, 0x3, 0x3, 0x0, PseudoVLUXEI8_V_M1_M8 }, // 12 |
18844 | | { 0x0, 0x0, 0x3, 0x3, 0x1, PseudoVLUXEI8_V_M2_M8 }, // 13 |
18845 | | { 0x0, 0x0, 0x3, 0x3, 0x2, PseudoVLUXEI8_V_M4_M8 }, // 14 |
18846 | | { 0x0, 0x0, 0x3, 0x3, 0x3, PseudoVLUXEI8_V_M8_M8 }, // 15 |
18847 | | { 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVLUXEI8_V_MF8_MF8 }, // 16 |
18848 | | { 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVLUXEI8_V_MF8_MF4 }, // 17 |
18849 | | { 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVLUXEI8_V_MF4_MF4 }, // 18 |
18850 | | { 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVLUXEI8_V_MF8_MF2 }, // 19 |
18851 | | { 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVLUXEI8_V_MF4_MF2 }, // 20 |
18852 | | { 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVLUXEI8_V_MF2_MF2 }, // 21 |
18853 | | { 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVLUXEI16_V_M1_M1 }, // 22 |
18854 | | { 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVLUXEI16_V_M2_M1 }, // 23 |
18855 | | { 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVLUXEI16_V_MF4_M1 }, // 24 |
18856 | | { 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVLUXEI16_V_MF2_M1 }, // 25 |
18857 | | { 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVLUXEI16_V_M1_M2 }, // 26 |
18858 | | { 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVLUXEI16_V_M2_M2 }, // 27 |
18859 | | { 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVLUXEI16_V_M4_M2 }, // 28 |
18860 | | { 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVLUXEI16_V_MF2_M2 }, // 29 |
18861 | | { 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVLUXEI16_V_M1_M4 }, // 30 |
18862 | | { 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVLUXEI16_V_M2_M4 }, // 31 |
18863 | | { 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVLUXEI16_V_M4_M4 }, // 32 |
18864 | | { 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVLUXEI16_V_M8_M4 }, // 33 |
18865 | | { 0x0, 0x0, 0x4, 0x3, 0x1, PseudoVLUXEI16_V_M2_M8 }, // 34 |
18866 | | { 0x0, 0x0, 0x4, 0x3, 0x2, PseudoVLUXEI16_V_M4_M8 }, // 35 |
18867 | | { 0x0, 0x0, 0x4, 0x3, 0x3, PseudoVLUXEI16_V_M8_M8 }, // 36 |
18868 | | { 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVLUXEI16_V_MF4_MF8 }, // 37 |
18869 | | { 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVLUXEI16_V_MF4_MF4 }, // 38 |
18870 | | { 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVLUXEI16_V_MF2_MF4 }, // 39 |
18871 | | { 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVLUXEI16_V_M1_MF2 }, // 40 |
18872 | | { 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVLUXEI16_V_MF4_MF2 }, // 41 |
18873 | | { 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVLUXEI16_V_MF2_MF2 }, // 42 |
18874 | | { 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVLUXEI32_V_M1_M1 }, // 43 |
18875 | | { 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVLUXEI32_V_M2_M1 }, // 44 |
18876 | | { 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVLUXEI32_V_M4_M1 }, // 45 |
18877 | | { 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVLUXEI32_V_MF2_M1 }, // 46 |
18878 | | { 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVLUXEI32_V_M1_M2 }, // 47 |
18879 | | { 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVLUXEI32_V_M2_M2 }, // 48 |
18880 | | { 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVLUXEI32_V_M4_M2 }, // 49 |
18881 | | { 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVLUXEI32_V_M8_M2 }, // 50 |
18882 | | { 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVLUXEI32_V_M2_M4 }, // 51 |
18883 | | { 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVLUXEI32_V_M4_M4 }, // 52 |
18884 | | { 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVLUXEI32_V_M8_M4 }, // 53 |
18885 | | { 0x0, 0x0, 0x5, 0x3, 0x2, PseudoVLUXEI32_V_M4_M8 }, // 54 |
18886 | | { 0x0, 0x0, 0x5, 0x3, 0x3, PseudoVLUXEI32_V_M8_M8 }, // 55 |
18887 | | { 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVLUXEI32_V_MF2_MF8 }, // 56 |
18888 | | { 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVLUXEI32_V_M1_MF4 }, // 57 |
18889 | | { 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVLUXEI32_V_MF2_MF4 }, // 58 |
18890 | | { 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVLUXEI32_V_M1_MF2 }, // 59 |
18891 | | { 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVLUXEI32_V_M2_MF2 }, // 60 |
18892 | | { 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVLUXEI32_V_MF2_MF2 }, // 61 |
18893 | | { 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVLUXEI64_V_M1_M1 }, // 62 |
18894 | | { 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVLUXEI64_V_M2_M1 }, // 63 |
18895 | | { 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVLUXEI64_V_M4_M1 }, // 64 |
18896 | | { 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVLUXEI64_V_M8_M1 }, // 65 |
18897 | | { 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVLUXEI64_V_M2_M2 }, // 66 |
18898 | | { 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVLUXEI64_V_M4_M2 }, // 67 |
18899 | | { 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVLUXEI64_V_M8_M2 }, // 68 |
18900 | | { 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVLUXEI64_V_M4_M4 }, // 69 |
18901 | | { 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVLUXEI64_V_M8_M4 }, // 70 |
18902 | | { 0x0, 0x0, 0x6, 0x3, 0x3, PseudoVLUXEI64_V_M8_M8 }, // 71 |
18903 | | { 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVLUXEI64_V_M1_MF8 }, // 72 |
18904 | | { 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVLUXEI64_V_M1_MF4 }, // 73 |
18905 | | { 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVLUXEI64_V_M2_MF4 }, // 74 |
18906 | | { 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVLUXEI64_V_M1_MF2 }, // 75 |
18907 | | { 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVLUXEI64_V_M2_MF2 }, // 76 |
18908 | | { 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVLUXEI64_V_M4_MF2 }, // 77 |
18909 | | { 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVLOXEI8_V_M1_M1 }, // 78 |
18910 | | { 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVLOXEI8_V_MF8_M1 }, // 79 |
18911 | | { 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVLOXEI8_V_MF4_M1 }, // 80 |
18912 | | { 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVLOXEI8_V_MF2_M1 }, // 81 |
18913 | | { 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVLOXEI8_V_M1_M2 }, // 82 |
18914 | | { 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVLOXEI8_V_M2_M2 }, // 83 |
18915 | | { 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVLOXEI8_V_MF4_M2 }, // 84 |
18916 | | { 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVLOXEI8_V_MF2_M2 }, // 85 |
18917 | | { 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVLOXEI8_V_M1_M4 }, // 86 |
18918 | | { 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVLOXEI8_V_M2_M4 }, // 87 |
18919 | | { 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVLOXEI8_V_M4_M4 }, // 88 |
18920 | | { 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVLOXEI8_V_MF2_M4 }, // 89 |
18921 | | { 0x0, 0x1, 0x3, 0x3, 0x0, PseudoVLOXEI8_V_M1_M8 }, // 90 |
18922 | | { 0x0, 0x1, 0x3, 0x3, 0x1, PseudoVLOXEI8_V_M2_M8 }, // 91 |
18923 | | { 0x0, 0x1, 0x3, 0x3, 0x2, PseudoVLOXEI8_V_M4_M8 }, // 92 |
18924 | | { 0x0, 0x1, 0x3, 0x3, 0x3, PseudoVLOXEI8_V_M8_M8 }, // 93 |
18925 | | { 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVLOXEI8_V_MF8_MF8 }, // 94 |
18926 | | { 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVLOXEI8_V_MF8_MF4 }, // 95 |
18927 | | { 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVLOXEI8_V_MF4_MF4 }, // 96 |
18928 | | { 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVLOXEI8_V_MF8_MF2 }, // 97 |
18929 | | { 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVLOXEI8_V_MF4_MF2 }, // 98 |
18930 | | { 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVLOXEI8_V_MF2_MF2 }, // 99 |
18931 | | { 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVLOXEI16_V_M1_M1 }, // 100 |
18932 | | { 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVLOXEI16_V_M2_M1 }, // 101 |
18933 | | { 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVLOXEI16_V_MF4_M1 }, // 102 |
18934 | | { 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVLOXEI16_V_MF2_M1 }, // 103 |
18935 | | { 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVLOXEI16_V_M1_M2 }, // 104 |
18936 | | { 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVLOXEI16_V_M2_M2 }, // 105 |
18937 | | { 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVLOXEI16_V_M4_M2 }, // 106 |
18938 | | { 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVLOXEI16_V_MF2_M2 }, // 107 |
18939 | | { 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVLOXEI16_V_M1_M4 }, // 108 |
18940 | | { 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVLOXEI16_V_M2_M4 }, // 109 |
18941 | | { 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVLOXEI16_V_M4_M4 }, // 110 |
18942 | | { 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVLOXEI16_V_M8_M4 }, // 111 |
18943 | | { 0x0, 0x1, 0x4, 0x3, 0x1, PseudoVLOXEI16_V_M2_M8 }, // 112 |
18944 | | { 0x0, 0x1, 0x4, 0x3, 0x2, PseudoVLOXEI16_V_M4_M8 }, // 113 |
18945 | | { 0x0, 0x1, 0x4, 0x3, 0x3, PseudoVLOXEI16_V_M8_M8 }, // 114 |
18946 | | { 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVLOXEI16_V_MF4_MF8 }, // 115 |
18947 | | { 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVLOXEI16_V_MF4_MF4 }, // 116 |
18948 | | { 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVLOXEI16_V_MF2_MF4 }, // 117 |
18949 | | { 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVLOXEI16_V_M1_MF2 }, // 118 |
18950 | | { 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVLOXEI16_V_MF4_MF2 }, // 119 |
18951 | | { 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVLOXEI16_V_MF2_MF2 }, // 120 |
18952 | | { 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVLOXEI32_V_M1_M1 }, // 121 |
18953 | | { 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVLOXEI32_V_M2_M1 }, // 122 |
18954 | | { 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVLOXEI32_V_M4_M1 }, // 123 |
18955 | | { 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVLOXEI32_V_MF2_M1 }, // 124 |
18956 | | { 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVLOXEI32_V_M1_M2 }, // 125 |
18957 | | { 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVLOXEI32_V_M2_M2 }, // 126 |
18958 | | { 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVLOXEI32_V_M4_M2 }, // 127 |
18959 | | { 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVLOXEI32_V_M8_M2 }, // 128 |
18960 | | { 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVLOXEI32_V_M2_M4 }, // 129 |
18961 | | { 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVLOXEI32_V_M4_M4 }, // 130 |
18962 | | { 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVLOXEI32_V_M8_M4 }, // 131 |
18963 | | { 0x0, 0x1, 0x5, 0x3, 0x2, PseudoVLOXEI32_V_M4_M8 }, // 132 |
18964 | | { 0x0, 0x1, 0x5, 0x3, 0x3, PseudoVLOXEI32_V_M8_M8 }, // 133 |
18965 | | { 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVLOXEI32_V_MF2_MF8 }, // 134 |
18966 | | { 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVLOXEI32_V_M1_MF4 }, // 135 |
18967 | | { 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVLOXEI32_V_MF2_MF4 }, // 136 |
18968 | | { 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVLOXEI32_V_M1_MF2 }, // 137 |
18969 | | { 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVLOXEI32_V_M2_MF2 }, // 138 |
18970 | | { 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVLOXEI32_V_MF2_MF2 }, // 139 |
18971 | | { 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVLOXEI64_V_M1_M1 }, // 140 |
18972 | | { 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVLOXEI64_V_M2_M1 }, // 141 |
18973 | | { 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVLOXEI64_V_M4_M1 }, // 142 |
18974 | | { 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVLOXEI64_V_M8_M1 }, // 143 |
18975 | | { 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVLOXEI64_V_M2_M2 }, // 144 |
18976 | | { 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVLOXEI64_V_M4_M2 }, // 145 |
18977 | | { 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVLOXEI64_V_M8_M2 }, // 146 |
18978 | | { 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVLOXEI64_V_M4_M4 }, // 147 |
18979 | | { 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVLOXEI64_V_M8_M4 }, // 148 |
18980 | | { 0x0, 0x1, 0x6, 0x3, 0x3, PseudoVLOXEI64_V_M8_M8 }, // 149 |
18981 | | { 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVLOXEI64_V_M1_MF8 }, // 150 |
18982 | | { 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVLOXEI64_V_M1_MF4 }, // 151 |
18983 | | { 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVLOXEI64_V_M2_MF4 }, // 152 |
18984 | | { 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVLOXEI64_V_M1_MF2 }, // 153 |
18985 | | { 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVLOXEI64_V_M2_MF2 }, // 154 |
18986 | | { 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVLOXEI64_V_M4_MF2 }, // 155 |
18987 | | { 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVLUXEI8_V_M1_M1_MASK }, // 156 |
18988 | | { 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVLUXEI8_V_MF8_M1_MASK }, // 157 |
18989 | | { 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVLUXEI8_V_MF4_M1_MASK }, // 158 |
18990 | | { 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVLUXEI8_V_MF2_M1_MASK }, // 159 |
18991 | | { 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVLUXEI8_V_M1_M2_MASK }, // 160 |
18992 | | { 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVLUXEI8_V_M2_M2_MASK }, // 161 |
18993 | | { 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVLUXEI8_V_MF4_M2_MASK }, // 162 |
18994 | | { 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVLUXEI8_V_MF2_M2_MASK }, // 163 |
18995 | | { 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVLUXEI8_V_M1_M4_MASK }, // 164 |
18996 | | { 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVLUXEI8_V_M2_M4_MASK }, // 165 |
18997 | | { 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVLUXEI8_V_M4_M4_MASK }, // 166 |
18998 | | { 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVLUXEI8_V_MF2_M4_MASK }, // 167 |
18999 | | { 0x1, 0x0, 0x3, 0x3, 0x0, PseudoVLUXEI8_V_M1_M8_MASK }, // 168 |
19000 | | { 0x1, 0x0, 0x3, 0x3, 0x1, PseudoVLUXEI8_V_M2_M8_MASK }, // 169 |
19001 | | { 0x1, 0x0, 0x3, 0x3, 0x2, PseudoVLUXEI8_V_M4_M8_MASK }, // 170 |
19002 | | { 0x1, 0x0, 0x3, 0x3, 0x3, PseudoVLUXEI8_V_M8_M8_MASK }, // 171 |
19003 | | { 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVLUXEI8_V_MF8_MF8_MASK }, // 172 |
19004 | | { 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVLUXEI8_V_MF8_MF4_MASK }, // 173 |
19005 | | { 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVLUXEI8_V_MF4_MF4_MASK }, // 174 |
19006 | | { 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVLUXEI8_V_MF8_MF2_MASK }, // 175 |
19007 | | { 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVLUXEI8_V_MF4_MF2_MASK }, // 176 |
19008 | | { 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVLUXEI8_V_MF2_MF2_MASK }, // 177 |
19009 | | { 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVLUXEI16_V_M1_M1_MASK }, // 178 |
19010 | | { 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVLUXEI16_V_M2_M1_MASK }, // 179 |
19011 | | { 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVLUXEI16_V_MF4_M1_MASK }, // 180 |
19012 | | { 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVLUXEI16_V_MF2_M1_MASK }, // 181 |
19013 | | { 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVLUXEI16_V_M1_M2_MASK }, // 182 |
19014 | | { 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVLUXEI16_V_M2_M2_MASK }, // 183 |
19015 | | { 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVLUXEI16_V_M4_M2_MASK }, // 184 |
19016 | | { 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVLUXEI16_V_MF2_M2_MASK }, // 185 |
19017 | | { 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVLUXEI16_V_M1_M4_MASK }, // 186 |
19018 | | { 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVLUXEI16_V_M2_M4_MASK }, // 187 |
19019 | | { 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVLUXEI16_V_M4_M4_MASK }, // 188 |
19020 | | { 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVLUXEI16_V_M8_M4_MASK }, // 189 |
19021 | | { 0x1, 0x0, 0x4, 0x3, 0x1, PseudoVLUXEI16_V_M2_M8_MASK }, // 190 |
19022 | | { 0x1, 0x0, 0x4, 0x3, 0x2, PseudoVLUXEI16_V_M4_M8_MASK }, // 191 |
19023 | | { 0x1, 0x0, 0x4, 0x3, 0x3, PseudoVLUXEI16_V_M8_M8_MASK }, // 192 |
19024 | | { 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVLUXEI16_V_MF4_MF8_MASK }, // 193 |
19025 | | { 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVLUXEI16_V_MF4_MF4_MASK }, // 194 |
19026 | | { 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVLUXEI16_V_MF2_MF4_MASK }, // 195 |
19027 | | { 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVLUXEI16_V_M1_MF2_MASK }, // 196 |
19028 | | { 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVLUXEI16_V_MF4_MF2_MASK }, // 197 |
19029 | | { 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVLUXEI16_V_MF2_MF2_MASK }, // 198 |
19030 | | { 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVLUXEI32_V_M1_M1_MASK }, // 199 |
19031 | | { 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVLUXEI32_V_M2_M1_MASK }, // 200 |
19032 | | { 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVLUXEI32_V_M4_M1_MASK }, // 201 |
19033 | | { 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVLUXEI32_V_MF2_M1_MASK }, // 202 |
19034 | | { 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVLUXEI32_V_M1_M2_MASK }, // 203 |
19035 | | { 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVLUXEI32_V_M2_M2_MASK }, // 204 |
19036 | | { 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVLUXEI32_V_M4_M2_MASK }, // 205 |
19037 | | { 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVLUXEI32_V_M8_M2_MASK }, // 206 |
19038 | | { 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVLUXEI32_V_M2_M4_MASK }, // 207 |
19039 | | { 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVLUXEI32_V_M4_M4_MASK }, // 208 |
19040 | | { 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVLUXEI32_V_M8_M4_MASK }, // 209 |
19041 | | { 0x1, 0x0, 0x5, 0x3, 0x2, PseudoVLUXEI32_V_M4_M8_MASK }, // 210 |
19042 | | { 0x1, 0x0, 0x5, 0x3, 0x3, PseudoVLUXEI32_V_M8_M8_MASK }, // 211 |
19043 | | { 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVLUXEI32_V_MF2_MF8_MASK }, // 212 |
19044 | | { 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVLUXEI32_V_M1_MF4_MASK }, // 213 |
19045 | | { 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVLUXEI32_V_MF2_MF4_MASK }, // 214 |
19046 | | { 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVLUXEI32_V_M1_MF2_MASK }, // 215 |
19047 | | { 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVLUXEI32_V_M2_MF2_MASK }, // 216 |
19048 | | { 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVLUXEI32_V_MF2_MF2_MASK }, // 217 |
19049 | | { 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVLUXEI64_V_M1_M1_MASK }, // 218 |
19050 | | { 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVLUXEI64_V_M2_M1_MASK }, // 219 |
19051 | | { 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVLUXEI64_V_M4_M1_MASK }, // 220 |
19052 | | { 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVLUXEI64_V_M8_M1_MASK }, // 221 |
19053 | | { 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVLUXEI64_V_M2_M2_MASK }, // 222 |
19054 | | { 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVLUXEI64_V_M4_M2_MASK }, // 223 |
19055 | | { 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVLUXEI64_V_M8_M2_MASK }, // 224 |
19056 | | { 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVLUXEI64_V_M4_M4_MASK }, // 225 |
19057 | | { 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVLUXEI64_V_M8_M4_MASK }, // 226 |
19058 | | { 0x1, 0x0, 0x6, 0x3, 0x3, PseudoVLUXEI64_V_M8_M8_MASK }, // 227 |
19059 | | { 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVLUXEI64_V_M1_MF8_MASK }, // 228 |
19060 | | { 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVLUXEI64_V_M1_MF4_MASK }, // 229 |
19061 | | { 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVLUXEI64_V_M2_MF4_MASK }, // 230 |
19062 | | { 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVLUXEI64_V_M1_MF2_MASK }, // 231 |
19063 | | { 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVLUXEI64_V_M2_MF2_MASK }, // 232 |
19064 | | { 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVLUXEI64_V_M4_MF2_MASK }, // 233 |
19065 | | { 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVLOXEI8_V_M1_M1_MASK }, // 234 |
19066 | | { 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVLOXEI8_V_MF8_M1_MASK }, // 235 |
19067 | | { 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVLOXEI8_V_MF4_M1_MASK }, // 236 |
19068 | | { 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVLOXEI8_V_MF2_M1_MASK }, // 237 |
19069 | | { 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVLOXEI8_V_M1_M2_MASK }, // 238 |
19070 | | { 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVLOXEI8_V_M2_M2_MASK }, // 239 |
19071 | | { 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVLOXEI8_V_MF4_M2_MASK }, // 240 |
19072 | | { 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVLOXEI8_V_MF2_M2_MASK }, // 241 |
19073 | | { 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVLOXEI8_V_M1_M4_MASK }, // 242 |
19074 | | { 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVLOXEI8_V_M2_M4_MASK }, // 243 |
19075 | | { 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVLOXEI8_V_M4_M4_MASK }, // 244 |
19076 | | { 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVLOXEI8_V_MF2_M4_MASK }, // 245 |
19077 | | { 0x1, 0x1, 0x3, 0x3, 0x0, PseudoVLOXEI8_V_M1_M8_MASK }, // 246 |
19078 | | { 0x1, 0x1, 0x3, 0x3, 0x1, PseudoVLOXEI8_V_M2_M8_MASK }, // 247 |
19079 | | { 0x1, 0x1, 0x3, 0x3, 0x2, PseudoVLOXEI8_V_M4_M8_MASK }, // 248 |
19080 | | { 0x1, 0x1, 0x3, 0x3, 0x3, PseudoVLOXEI8_V_M8_M8_MASK }, // 249 |
19081 | | { 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVLOXEI8_V_MF8_MF8_MASK }, // 250 |
19082 | | { 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVLOXEI8_V_MF8_MF4_MASK }, // 251 |
19083 | | { 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVLOXEI8_V_MF4_MF4_MASK }, // 252 |
19084 | | { 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVLOXEI8_V_MF8_MF2_MASK }, // 253 |
19085 | | { 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVLOXEI8_V_MF4_MF2_MASK }, // 254 |
19086 | | { 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVLOXEI8_V_MF2_MF2_MASK }, // 255 |
19087 | | { 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVLOXEI16_V_M1_M1_MASK }, // 256 |
19088 | | { 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVLOXEI16_V_M2_M1_MASK }, // 257 |
19089 | | { 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVLOXEI16_V_MF4_M1_MASK }, // 258 |
19090 | | { 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVLOXEI16_V_MF2_M1_MASK }, // 259 |
19091 | | { 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVLOXEI16_V_M1_M2_MASK }, // 260 |
19092 | | { 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVLOXEI16_V_M2_M2_MASK }, // 261 |
19093 | | { 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVLOXEI16_V_M4_M2_MASK }, // 262 |
19094 | | { 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVLOXEI16_V_MF2_M2_MASK }, // 263 |
19095 | | { 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVLOXEI16_V_M1_M4_MASK }, // 264 |
19096 | | { 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVLOXEI16_V_M2_M4_MASK }, // 265 |
19097 | | { 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVLOXEI16_V_M4_M4_MASK }, // 266 |
19098 | | { 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVLOXEI16_V_M8_M4_MASK }, // 267 |
19099 | | { 0x1, 0x1, 0x4, 0x3, 0x1, PseudoVLOXEI16_V_M2_M8_MASK }, // 268 |
19100 | | { 0x1, 0x1, 0x4, 0x3, 0x2, PseudoVLOXEI16_V_M4_M8_MASK }, // 269 |
19101 | | { 0x1, 0x1, 0x4, 0x3, 0x3, PseudoVLOXEI16_V_M8_M8_MASK }, // 270 |
19102 | | { 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVLOXEI16_V_MF4_MF8_MASK }, // 271 |
19103 | | { 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVLOXEI16_V_MF4_MF4_MASK }, // 272 |
19104 | | { 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVLOXEI16_V_MF2_MF4_MASK }, // 273 |
19105 | | { 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVLOXEI16_V_M1_MF2_MASK }, // 274 |
19106 | | { 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVLOXEI16_V_MF4_MF2_MASK }, // 275 |
19107 | | { 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVLOXEI16_V_MF2_MF2_MASK }, // 276 |
19108 | | { 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVLOXEI32_V_M1_M1_MASK }, // 277 |
19109 | | { 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVLOXEI32_V_M2_M1_MASK }, // 278 |
19110 | | { 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVLOXEI32_V_M4_M1_MASK }, // 279 |
19111 | | { 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVLOXEI32_V_MF2_M1_MASK }, // 280 |
19112 | | { 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVLOXEI32_V_M1_M2_MASK }, // 281 |
19113 | | { 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVLOXEI32_V_M2_M2_MASK }, // 282 |
19114 | | { 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVLOXEI32_V_M4_M2_MASK }, // 283 |
19115 | | { 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVLOXEI32_V_M8_M2_MASK }, // 284 |
19116 | | { 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVLOXEI32_V_M2_M4_MASK }, // 285 |
19117 | | { 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVLOXEI32_V_M4_M4_MASK }, // 286 |
19118 | | { 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVLOXEI32_V_M8_M4_MASK }, // 287 |
19119 | | { 0x1, 0x1, 0x5, 0x3, 0x2, PseudoVLOXEI32_V_M4_M8_MASK }, // 288 |
19120 | | { 0x1, 0x1, 0x5, 0x3, 0x3, PseudoVLOXEI32_V_M8_M8_MASK }, // 289 |
19121 | | { 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVLOXEI32_V_MF2_MF8_MASK }, // 290 |
19122 | | { 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVLOXEI32_V_M1_MF4_MASK }, // 291 |
19123 | | { 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVLOXEI32_V_MF2_MF4_MASK }, // 292 |
19124 | | { 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVLOXEI32_V_M1_MF2_MASK }, // 293 |
19125 | | { 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVLOXEI32_V_M2_MF2_MASK }, // 294 |
19126 | | { 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVLOXEI32_V_MF2_MF2_MASK }, // 295 |
19127 | | { 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVLOXEI64_V_M1_M1_MASK }, // 296 |
19128 | | { 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVLOXEI64_V_M2_M1_MASK }, // 297 |
19129 | | { 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVLOXEI64_V_M4_M1_MASK }, // 298 |
19130 | | { 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVLOXEI64_V_M8_M1_MASK }, // 299 |
19131 | | { 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVLOXEI64_V_M2_M2_MASK }, // 300 |
19132 | | { 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVLOXEI64_V_M4_M2_MASK }, // 301 |
19133 | | { 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVLOXEI64_V_M8_M2_MASK }, // 302 |
19134 | | { 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVLOXEI64_V_M4_M4_MASK }, // 303 |
19135 | | { 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVLOXEI64_V_M8_M4_MASK }, // 304 |
19136 | | { 0x1, 0x1, 0x6, 0x3, 0x3, PseudoVLOXEI64_V_M8_M8_MASK }, // 305 |
19137 | | { 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVLOXEI64_V_M1_MF8_MASK }, // 306 |
19138 | | { 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVLOXEI64_V_M1_MF4_MASK }, // 307 |
19139 | | { 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVLOXEI64_V_M2_MF4_MASK }, // 308 |
19140 | | { 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVLOXEI64_V_M1_MF2_MASK }, // 309 |
19141 | | { 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVLOXEI64_V_M2_MF2_MASK }, // 310 |
19142 | | { 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVLOXEI64_V_M4_MF2_MASK }, // 311 |
19143 | | }; |
19144 | | |
19145 | | const RISCV_VLX_VSXPseudo *RISCV_getVLXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) { |
19146 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), MaskedOrderedLog2SEWLMULIndexLMUL); |
19147 | | if (i == -1) |
19148 | | return NULL; |
19149 | | else |
19150 | | return &RISCVVLXTable[Index[i].index]; |
19151 | | } |
19152 | | |
19153 | | #endif |
19154 | | |
19155 | | #ifdef GET_RISCVVPseudosTable_IMPL |
19156 | | static const RISCV_PseudoInfo RISCVVPseudosTable[] = { |
19157 | | { PseudoTHVdotVMAQASU_VV_M1, THVdotVMAQASU_VV }, // 0 |
19158 | | { PseudoTHVdotVMAQASU_VV_M1_MASK, THVdotVMAQASU_VV }, // 1 |
19159 | | { PseudoTHVdotVMAQASU_VV_M2, THVdotVMAQASU_VV }, // 2 |
19160 | | { PseudoTHVdotVMAQASU_VV_M2_MASK, THVdotVMAQASU_VV }, // 3 |
19161 | | { PseudoTHVdotVMAQASU_VV_M4, THVdotVMAQASU_VV }, // 4 |
19162 | | { PseudoTHVdotVMAQASU_VV_M4_MASK, THVdotVMAQASU_VV }, // 5 |
19163 | | { PseudoTHVdotVMAQASU_VV_M8, THVdotVMAQASU_VV }, // 6 |
19164 | | { PseudoTHVdotVMAQASU_VV_M8_MASK, THVdotVMAQASU_VV }, // 7 |
19165 | | { PseudoTHVdotVMAQASU_VV_MF2, THVdotVMAQASU_VV }, // 8 |
19166 | | { PseudoTHVdotVMAQASU_VV_MF2_MASK, THVdotVMAQASU_VV }, // 9 |
19167 | | { PseudoTHVdotVMAQASU_VX_M1, THVdotVMAQASU_VX }, // 10 |
19168 | | { PseudoTHVdotVMAQASU_VX_M1_MASK, THVdotVMAQASU_VX }, // 11 |
19169 | | { PseudoTHVdotVMAQASU_VX_M2, THVdotVMAQASU_VX }, // 12 |
19170 | | { PseudoTHVdotVMAQASU_VX_M2_MASK, THVdotVMAQASU_VX }, // 13 |
19171 | | { PseudoTHVdotVMAQASU_VX_M4, THVdotVMAQASU_VX }, // 14 |
19172 | | { PseudoTHVdotVMAQASU_VX_M4_MASK, THVdotVMAQASU_VX }, // 15 |
19173 | | { PseudoTHVdotVMAQASU_VX_M8, THVdotVMAQASU_VX }, // 16 |
19174 | | { PseudoTHVdotVMAQASU_VX_M8_MASK, THVdotVMAQASU_VX }, // 17 |
19175 | | { PseudoTHVdotVMAQASU_VX_MF2, THVdotVMAQASU_VX }, // 18 |
19176 | | { PseudoTHVdotVMAQASU_VX_MF2_MASK, THVdotVMAQASU_VX }, // 19 |
19177 | | { PseudoTHVdotVMAQAUS_VX_M1, THVdotVMAQAUS_VX }, // 20 |
19178 | | { PseudoTHVdotVMAQAUS_VX_M1_MASK, THVdotVMAQAUS_VX }, // 21 |
19179 | | { PseudoTHVdotVMAQAUS_VX_M2, THVdotVMAQAUS_VX }, // 22 |
19180 | | { PseudoTHVdotVMAQAUS_VX_M2_MASK, THVdotVMAQAUS_VX }, // 23 |
19181 | | { PseudoTHVdotVMAQAUS_VX_M4, THVdotVMAQAUS_VX }, // 24 |
19182 | | { PseudoTHVdotVMAQAUS_VX_M4_MASK, THVdotVMAQAUS_VX }, // 25 |
19183 | | { PseudoTHVdotVMAQAUS_VX_M8, THVdotVMAQAUS_VX }, // 26 |
19184 | | { PseudoTHVdotVMAQAUS_VX_M8_MASK, THVdotVMAQAUS_VX }, // 27 |
19185 | | { PseudoTHVdotVMAQAUS_VX_MF2, THVdotVMAQAUS_VX }, // 28 |
19186 | | { PseudoTHVdotVMAQAUS_VX_MF2_MASK, THVdotVMAQAUS_VX }, // 29 |
19187 | | { PseudoTHVdotVMAQAU_VV_M1, THVdotVMAQAU_VV }, // 30 |
19188 | | { PseudoTHVdotVMAQAU_VV_M1_MASK, THVdotVMAQAU_VV }, // 31 |
19189 | | { PseudoTHVdotVMAQAU_VV_M2, THVdotVMAQAU_VV }, // 32 |
19190 | | { PseudoTHVdotVMAQAU_VV_M2_MASK, THVdotVMAQAU_VV }, // 33 |
19191 | | { PseudoTHVdotVMAQAU_VV_M4, THVdotVMAQAU_VV }, // 34 |
19192 | | { PseudoTHVdotVMAQAU_VV_M4_MASK, THVdotVMAQAU_VV }, // 35 |
19193 | | { PseudoTHVdotVMAQAU_VV_M8, THVdotVMAQAU_VV }, // 36 |
19194 | | { PseudoTHVdotVMAQAU_VV_M8_MASK, THVdotVMAQAU_VV }, // 37 |
19195 | | { PseudoTHVdotVMAQAU_VV_MF2, THVdotVMAQAU_VV }, // 38 |
19196 | | { PseudoTHVdotVMAQAU_VV_MF2_MASK, THVdotVMAQAU_VV }, // 39 |
19197 | | { PseudoTHVdotVMAQAU_VX_M1, THVdotVMAQAU_VX }, // 40 |
19198 | | { PseudoTHVdotVMAQAU_VX_M1_MASK, THVdotVMAQAU_VX }, // 41 |
19199 | | { PseudoTHVdotVMAQAU_VX_M2, THVdotVMAQAU_VX }, // 42 |
19200 | | { PseudoTHVdotVMAQAU_VX_M2_MASK, THVdotVMAQAU_VX }, // 43 |
19201 | | { PseudoTHVdotVMAQAU_VX_M4, THVdotVMAQAU_VX }, // 44 |
19202 | | { PseudoTHVdotVMAQAU_VX_M4_MASK, THVdotVMAQAU_VX }, // 45 |
19203 | | { PseudoTHVdotVMAQAU_VX_M8, THVdotVMAQAU_VX }, // 46 |
19204 | | { PseudoTHVdotVMAQAU_VX_M8_MASK, THVdotVMAQAU_VX }, // 47 |
19205 | | { PseudoTHVdotVMAQAU_VX_MF2, THVdotVMAQAU_VX }, // 48 |
19206 | | { PseudoTHVdotVMAQAU_VX_MF2_MASK, THVdotVMAQAU_VX }, // 49 |
19207 | | { PseudoTHVdotVMAQA_VV_M1, THVdotVMAQA_VV }, // 50 |
19208 | | { PseudoTHVdotVMAQA_VV_M1_MASK, THVdotVMAQA_VV }, // 51 |
19209 | | { PseudoTHVdotVMAQA_VV_M2, THVdotVMAQA_VV }, // 52 |
19210 | | { PseudoTHVdotVMAQA_VV_M2_MASK, THVdotVMAQA_VV }, // 53 |
19211 | | { PseudoTHVdotVMAQA_VV_M4, THVdotVMAQA_VV }, // 54 |
19212 | | { PseudoTHVdotVMAQA_VV_M4_MASK, THVdotVMAQA_VV }, // 55 |
19213 | | { PseudoTHVdotVMAQA_VV_M8, THVdotVMAQA_VV }, // 56 |
19214 | | { PseudoTHVdotVMAQA_VV_M8_MASK, THVdotVMAQA_VV }, // 57 |
19215 | | { PseudoTHVdotVMAQA_VV_MF2, THVdotVMAQA_VV }, // 58 |
19216 | | { PseudoTHVdotVMAQA_VV_MF2_MASK, THVdotVMAQA_VV }, // 59 |
19217 | | { PseudoTHVdotVMAQA_VX_M1, THVdotVMAQA_VX }, // 60 |
19218 | | { PseudoTHVdotVMAQA_VX_M1_MASK, THVdotVMAQA_VX }, // 61 |
19219 | | { PseudoTHVdotVMAQA_VX_M2, THVdotVMAQA_VX }, // 62 |
19220 | | { PseudoTHVdotVMAQA_VX_M2_MASK, THVdotVMAQA_VX }, // 63 |
19221 | | { PseudoTHVdotVMAQA_VX_M4, THVdotVMAQA_VX }, // 64 |
19222 | | { PseudoTHVdotVMAQA_VX_M4_MASK, THVdotVMAQA_VX }, // 65 |
19223 | | { PseudoTHVdotVMAQA_VX_M8, THVdotVMAQA_VX }, // 66 |
19224 | | { PseudoTHVdotVMAQA_VX_M8_MASK, THVdotVMAQA_VX }, // 67 |
19225 | | { PseudoTHVdotVMAQA_VX_MF2, THVdotVMAQA_VX }, // 68 |
19226 | | { PseudoTHVdotVMAQA_VX_MF2_MASK, THVdotVMAQA_VX }, // 69 |
19227 | | { PseudoVAADDU_VV_M1, VAADDU_VV }, // 70 |
19228 | | { PseudoVAADDU_VV_M1_MASK, VAADDU_VV }, // 71 |
19229 | | { PseudoVAADDU_VV_M2, VAADDU_VV }, // 72 |
19230 | | { PseudoVAADDU_VV_M2_MASK, VAADDU_VV }, // 73 |
19231 | | { PseudoVAADDU_VV_M4, VAADDU_VV }, // 74 |
19232 | | { PseudoVAADDU_VV_M4_MASK, VAADDU_VV }, // 75 |
19233 | | { PseudoVAADDU_VV_M8, VAADDU_VV }, // 76 |
19234 | | { PseudoVAADDU_VV_M8_MASK, VAADDU_VV }, // 77 |
19235 | | { PseudoVAADDU_VV_MF2, VAADDU_VV }, // 78 |
19236 | | { PseudoVAADDU_VV_MF2_MASK, VAADDU_VV }, // 79 |
19237 | | { PseudoVAADDU_VV_MF4, VAADDU_VV }, // 80 |
19238 | | { PseudoVAADDU_VV_MF4_MASK, VAADDU_VV }, // 81 |
19239 | | { PseudoVAADDU_VV_MF8, VAADDU_VV }, // 82 |
19240 | | { PseudoVAADDU_VV_MF8_MASK, VAADDU_VV }, // 83 |
19241 | | { PseudoVAADDU_VX_M1, VAADDU_VX }, // 84 |
19242 | | { PseudoVAADDU_VX_M1_MASK, VAADDU_VX }, // 85 |
19243 | | { PseudoVAADDU_VX_M2, VAADDU_VX }, // 86 |
19244 | | { PseudoVAADDU_VX_M2_MASK, VAADDU_VX }, // 87 |
19245 | | { PseudoVAADDU_VX_M4, VAADDU_VX }, // 88 |
19246 | | { PseudoVAADDU_VX_M4_MASK, VAADDU_VX }, // 89 |
19247 | | { PseudoVAADDU_VX_M8, VAADDU_VX }, // 90 |
19248 | | { PseudoVAADDU_VX_M8_MASK, VAADDU_VX }, // 91 |
19249 | | { PseudoVAADDU_VX_MF2, VAADDU_VX }, // 92 |
19250 | | { PseudoVAADDU_VX_MF2_MASK, VAADDU_VX }, // 93 |
19251 | | { PseudoVAADDU_VX_MF4, VAADDU_VX }, // 94 |
19252 | | { PseudoVAADDU_VX_MF4_MASK, VAADDU_VX }, // 95 |
19253 | | { PseudoVAADDU_VX_MF8, VAADDU_VX }, // 96 |
19254 | | { PseudoVAADDU_VX_MF8_MASK, VAADDU_VX }, // 97 |
19255 | | { PseudoVAADD_VV_M1, VAADD_VV }, // 98 |
19256 | | { PseudoVAADD_VV_M1_MASK, VAADD_VV }, // 99 |
19257 | | { PseudoVAADD_VV_M2, VAADD_VV }, // 100 |
19258 | | { PseudoVAADD_VV_M2_MASK, VAADD_VV }, // 101 |
19259 | | { PseudoVAADD_VV_M4, VAADD_VV }, // 102 |
19260 | | { PseudoVAADD_VV_M4_MASK, VAADD_VV }, // 103 |
19261 | | { PseudoVAADD_VV_M8, VAADD_VV }, // 104 |
19262 | | { PseudoVAADD_VV_M8_MASK, VAADD_VV }, // 105 |
19263 | | { PseudoVAADD_VV_MF2, VAADD_VV }, // 106 |
19264 | | { PseudoVAADD_VV_MF2_MASK, VAADD_VV }, // 107 |
19265 | | { PseudoVAADD_VV_MF4, VAADD_VV }, // 108 |
19266 | | { PseudoVAADD_VV_MF4_MASK, VAADD_VV }, // 109 |
19267 | | { PseudoVAADD_VV_MF8, VAADD_VV }, // 110 |
19268 | | { PseudoVAADD_VV_MF8_MASK, VAADD_VV }, // 111 |
19269 | | { PseudoVAADD_VX_M1, VAADD_VX }, // 112 |
19270 | | { PseudoVAADD_VX_M1_MASK, VAADD_VX }, // 113 |
19271 | | { PseudoVAADD_VX_M2, VAADD_VX }, // 114 |
19272 | | { PseudoVAADD_VX_M2_MASK, VAADD_VX }, // 115 |
19273 | | { PseudoVAADD_VX_M4, VAADD_VX }, // 116 |
19274 | | { PseudoVAADD_VX_M4_MASK, VAADD_VX }, // 117 |
19275 | | { PseudoVAADD_VX_M8, VAADD_VX }, // 118 |
19276 | | { PseudoVAADD_VX_M8_MASK, VAADD_VX }, // 119 |
19277 | | { PseudoVAADD_VX_MF2, VAADD_VX }, // 120 |
19278 | | { PseudoVAADD_VX_MF2_MASK, VAADD_VX }, // 121 |
19279 | | { PseudoVAADD_VX_MF4, VAADD_VX }, // 122 |
19280 | | { PseudoVAADD_VX_MF4_MASK, VAADD_VX }, // 123 |
19281 | | { PseudoVAADD_VX_MF8, VAADD_VX }, // 124 |
19282 | | { PseudoVAADD_VX_MF8_MASK, VAADD_VX }, // 125 |
19283 | | { PseudoVADC_VIM_M1, VADC_VIM }, // 126 |
19284 | | { PseudoVADC_VIM_M2, VADC_VIM }, // 127 |
19285 | | { PseudoVADC_VIM_M4, VADC_VIM }, // 128 |
19286 | | { PseudoVADC_VIM_M8, VADC_VIM }, // 129 |
19287 | | { PseudoVADC_VIM_MF2, VADC_VIM }, // 130 |
19288 | | { PseudoVADC_VIM_MF4, VADC_VIM }, // 131 |
19289 | | { PseudoVADC_VIM_MF8, VADC_VIM }, // 132 |
19290 | | { PseudoVADC_VVM_M1, VADC_VVM }, // 133 |
19291 | | { PseudoVADC_VVM_M2, VADC_VVM }, // 134 |
19292 | | { PseudoVADC_VVM_M4, VADC_VVM }, // 135 |
19293 | | { PseudoVADC_VVM_M8, VADC_VVM }, // 136 |
19294 | | { PseudoVADC_VVM_MF2, VADC_VVM }, // 137 |
19295 | | { PseudoVADC_VVM_MF4, VADC_VVM }, // 138 |
19296 | | { PseudoVADC_VVM_MF8, VADC_VVM }, // 139 |
19297 | | { PseudoVADC_VXM_M1, VADC_VXM }, // 140 |
19298 | | { PseudoVADC_VXM_M2, VADC_VXM }, // 141 |
19299 | | { PseudoVADC_VXM_M4, VADC_VXM }, // 142 |
19300 | | { PseudoVADC_VXM_M8, VADC_VXM }, // 143 |
19301 | | { PseudoVADC_VXM_MF2, VADC_VXM }, // 144 |
19302 | | { PseudoVADC_VXM_MF4, VADC_VXM }, // 145 |
19303 | | { PseudoVADC_VXM_MF8, VADC_VXM }, // 146 |
19304 | | { PseudoVADD_VI_M1, VADD_VI }, // 147 |
19305 | | { PseudoVADD_VI_M1_MASK, VADD_VI }, // 148 |
19306 | | { PseudoVADD_VI_M2, VADD_VI }, // 149 |
19307 | | { PseudoVADD_VI_M2_MASK, VADD_VI }, // 150 |
19308 | | { PseudoVADD_VI_M4, VADD_VI }, // 151 |
19309 | | { PseudoVADD_VI_M4_MASK, VADD_VI }, // 152 |
19310 | | { PseudoVADD_VI_M8, VADD_VI }, // 153 |
19311 | | { PseudoVADD_VI_M8_MASK, VADD_VI }, // 154 |
19312 | | { PseudoVADD_VI_MF2, VADD_VI }, // 155 |
19313 | | { PseudoVADD_VI_MF2_MASK, VADD_VI }, // 156 |
19314 | | { PseudoVADD_VI_MF4, VADD_VI }, // 157 |
19315 | | { PseudoVADD_VI_MF4_MASK, VADD_VI }, // 158 |
19316 | | { PseudoVADD_VI_MF8, VADD_VI }, // 159 |
19317 | | { PseudoVADD_VI_MF8_MASK, VADD_VI }, // 160 |
19318 | | { PseudoVADD_VV_M1, VADD_VV }, // 161 |
19319 | | { PseudoVADD_VV_M1_MASK, VADD_VV }, // 162 |
19320 | | { PseudoVADD_VV_M2, VADD_VV }, // 163 |
19321 | | { PseudoVADD_VV_M2_MASK, VADD_VV }, // 164 |
19322 | | { PseudoVADD_VV_M4, VADD_VV }, // 165 |
19323 | | { PseudoVADD_VV_M4_MASK, VADD_VV }, // 166 |
19324 | | { PseudoVADD_VV_M8, VADD_VV }, // 167 |
19325 | | { PseudoVADD_VV_M8_MASK, VADD_VV }, // 168 |
19326 | | { PseudoVADD_VV_MF2, VADD_VV }, // 169 |
19327 | | { PseudoVADD_VV_MF2_MASK, VADD_VV }, // 170 |
19328 | | { PseudoVADD_VV_MF4, VADD_VV }, // 171 |
19329 | | { PseudoVADD_VV_MF4_MASK, VADD_VV }, // 172 |
19330 | | { PseudoVADD_VV_MF8, VADD_VV }, // 173 |
19331 | | { PseudoVADD_VV_MF8_MASK, VADD_VV }, // 174 |
19332 | | { PseudoVADD_VX_M1, VADD_VX }, // 175 |
19333 | | { PseudoVADD_VX_M1_MASK, VADD_VX }, // 176 |
19334 | | { PseudoVADD_VX_M2, VADD_VX }, // 177 |
19335 | | { PseudoVADD_VX_M2_MASK, VADD_VX }, // 178 |
19336 | | { PseudoVADD_VX_M4, VADD_VX }, // 179 |
19337 | | { PseudoVADD_VX_M4_MASK, VADD_VX }, // 180 |
19338 | | { PseudoVADD_VX_M8, VADD_VX }, // 181 |
19339 | | { PseudoVADD_VX_M8_MASK, VADD_VX }, // 182 |
19340 | | { PseudoVADD_VX_MF2, VADD_VX }, // 183 |
19341 | | { PseudoVADD_VX_MF2_MASK, VADD_VX }, // 184 |
19342 | | { PseudoVADD_VX_MF4, VADD_VX }, // 185 |
19343 | | { PseudoVADD_VX_MF4_MASK, VADD_VX }, // 186 |
19344 | | { PseudoVADD_VX_MF8, VADD_VX }, // 187 |
19345 | | { PseudoVADD_VX_MF8_MASK, VADD_VX }, // 188 |
19346 | | { PseudoVAESDF_VS_M1_M1, VAESDF_VS }, // 189 |
19347 | | { PseudoVAESDF_VS_M1_MF2, VAESDF_VS }, // 190 |
19348 | | { PseudoVAESDF_VS_M1_MF4, VAESDF_VS }, // 191 |
19349 | | { PseudoVAESDF_VS_M1_MF8, VAESDF_VS }, // 192 |
19350 | | { PseudoVAESDF_VS_M2_M1, VAESDF_VS }, // 193 |
19351 | | { PseudoVAESDF_VS_M2_M2, VAESDF_VS }, // 194 |
19352 | | { PseudoVAESDF_VS_M2_MF2, VAESDF_VS }, // 195 |
19353 | | { PseudoVAESDF_VS_M2_MF4, VAESDF_VS }, // 196 |
19354 | | { PseudoVAESDF_VS_M2_MF8, VAESDF_VS }, // 197 |
19355 | | { PseudoVAESDF_VS_M4_M1, VAESDF_VS }, // 198 |
19356 | | { PseudoVAESDF_VS_M4_M2, VAESDF_VS }, // 199 |
19357 | | { PseudoVAESDF_VS_M4_M4, VAESDF_VS }, // 200 |
19358 | | { PseudoVAESDF_VS_M4_MF2, VAESDF_VS }, // 201 |
19359 | | { PseudoVAESDF_VS_M4_MF4, VAESDF_VS }, // 202 |
19360 | | { PseudoVAESDF_VS_M4_MF8, VAESDF_VS }, // 203 |
19361 | | { PseudoVAESDF_VS_M8_M1, VAESDF_VS }, // 204 |
19362 | | { PseudoVAESDF_VS_M8_M2, VAESDF_VS }, // 205 |
19363 | | { PseudoVAESDF_VS_M8_M4, VAESDF_VS }, // 206 |
19364 | | { PseudoVAESDF_VS_M8_MF2, VAESDF_VS }, // 207 |
19365 | | { PseudoVAESDF_VS_M8_MF4, VAESDF_VS }, // 208 |
19366 | | { PseudoVAESDF_VS_M8_MF8, VAESDF_VS }, // 209 |
19367 | | { PseudoVAESDF_VS_MF2_MF2, VAESDF_VS }, // 210 |
19368 | | { PseudoVAESDF_VS_MF2_MF4, VAESDF_VS }, // 211 |
19369 | | { PseudoVAESDF_VS_MF2_MF8, VAESDF_VS }, // 212 |
19370 | | { PseudoVAESDF_VV_M1, VAESDF_VV }, // 213 |
19371 | | { PseudoVAESDF_VV_M2, VAESDF_VV }, // 214 |
19372 | | { PseudoVAESDF_VV_M4, VAESDF_VV }, // 215 |
19373 | | { PseudoVAESDF_VV_M8, VAESDF_VV }, // 216 |
19374 | | { PseudoVAESDF_VV_MF2, VAESDF_VV }, // 217 |
19375 | | { PseudoVAESDM_VS_M1_M1, VAESDM_VS }, // 218 |
19376 | | { PseudoVAESDM_VS_M1_MF2, VAESDM_VS }, // 219 |
19377 | | { PseudoVAESDM_VS_M1_MF4, VAESDM_VS }, // 220 |
19378 | | { PseudoVAESDM_VS_M1_MF8, VAESDM_VS }, // 221 |
19379 | | { PseudoVAESDM_VS_M2_M1, VAESDM_VS }, // 222 |
19380 | | { PseudoVAESDM_VS_M2_M2, VAESDM_VS }, // 223 |
19381 | | { PseudoVAESDM_VS_M2_MF2, VAESDM_VS }, // 224 |
19382 | | { PseudoVAESDM_VS_M2_MF4, VAESDM_VS }, // 225 |
19383 | | { PseudoVAESDM_VS_M2_MF8, VAESDM_VS }, // 226 |
19384 | | { PseudoVAESDM_VS_M4_M1, VAESDM_VS }, // 227 |
19385 | | { PseudoVAESDM_VS_M4_M2, VAESDM_VS }, // 228 |
19386 | | { PseudoVAESDM_VS_M4_M4, VAESDM_VS }, // 229 |
19387 | | { PseudoVAESDM_VS_M4_MF2, VAESDM_VS }, // 230 |
19388 | | { PseudoVAESDM_VS_M4_MF4, VAESDM_VS }, // 231 |
19389 | | { PseudoVAESDM_VS_M4_MF8, VAESDM_VS }, // 232 |
19390 | | { PseudoVAESDM_VS_M8_M1, VAESDM_VS }, // 233 |
19391 | | { PseudoVAESDM_VS_M8_M2, VAESDM_VS }, // 234 |
19392 | | { PseudoVAESDM_VS_M8_M4, VAESDM_VS }, // 235 |
19393 | | { PseudoVAESDM_VS_M8_MF2, VAESDM_VS }, // 236 |
19394 | | { PseudoVAESDM_VS_M8_MF4, VAESDM_VS }, // 237 |
19395 | | { PseudoVAESDM_VS_M8_MF8, VAESDM_VS }, // 238 |
19396 | | { PseudoVAESDM_VS_MF2_MF2, VAESDM_VS }, // 239 |
19397 | | { PseudoVAESDM_VS_MF2_MF4, VAESDM_VS }, // 240 |
19398 | | { PseudoVAESDM_VS_MF2_MF8, VAESDM_VS }, // 241 |
19399 | | { PseudoVAESDM_VV_M1, VAESDM_VV }, // 242 |
19400 | | { PseudoVAESDM_VV_M2, VAESDM_VV }, // 243 |
19401 | | { PseudoVAESDM_VV_M4, VAESDM_VV }, // 244 |
19402 | | { PseudoVAESDM_VV_M8, VAESDM_VV }, // 245 |
19403 | | { PseudoVAESDM_VV_MF2, VAESDM_VV }, // 246 |
19404 | | { PseudoVAESEF_VS_M1_M1, VAESEF_VS }, // 247 |
19405 | | { PseudoVAESEF_VS_M1_MF2, VAESEF_VS }, // 248 |
19406 | | { PseudoVAESEF_VS_M1_MF4, VAESEF_VS }, // 249 |
19407 | | { PseudoVAESEF_VS_M1_MF8, VAESEF_VS }, // 250 |
19408 | | { PseudoVAESEF_VS_M2_M1, VAESEF_VS }, // 251 |
19409 | | { PseudoVAESEF_VS_M2_M2, VAESEF_VS }, // 252 |
19410 | | { PseudoVAESEF_VS_M2_MF2, VAESEF_VS }, // 253 |
19411 | | { PseudoVAESEF_VS_M2_MF4, VAESEF_VS }, // 254 |
19412 | | { PseudoVAESEF_VS_M2_MF8, VAESEF_VS }, // 255 |
19413 | | { PseudoVAESEF_VS_M4_M1, VAESEF_VS }, // 256 |
19414 | | { PseudoVAESEF_VS_M4_M2, VAESEF_VS }, // 257 |
19415 | | { PseudoVAESEF_VS_M4_M4, VAESEF_VS }, // 258 |
19416 | | { PseudoVAESEF_VS_M4_MF2, VAESEF_VS }, // 259 |
19417 | | { PseudoVAESEF_VS_M4_MF4, VAESEF_VS }, // 260 |
19418 | | { PseudoVAESEF_VS_M4_MF8, VAESEF_VS }, // 261 |
19419 | | { PseudoVAESEF_VS_M8_M1, VAESEF_VS }, // 262 |
19420 | | { PseudoVAESEF_VS_M8_M2, VAESEF_VS }, // 263 |
19421 | | { PseudoVAESEF_VS_M8_M4, VAESEF_VS }, // 264 |
19422 | | { PseudoVAESEF_VS_M8_MF2, VAESEF_VS }, // 265 |
19423 | | { PseudoVAESEF_VS_M8_MF4, VAESEF_VS }, // 266 |
19424 | | { PseudoVAESEF_VS_M8_MF8, VAESEF_VS }, // 267 |
19425 | | { PseudoVAESEF_VS_MF2_MF2, VAESEF_VS }, // 268 |
19426 | | { PseudoVAESEF_VS_MF2_MF4, VAESEF_VS }, // 269 |
19427 | | { PseudoVAESEF_VS_MF2_MF8, VAESEF_VS }, // 270 |
19428 | | { PseudoVAESEF_VV_M1, VAESEF_VV }, // 271 |
19429 | | { PseudoVAESEF_VV_M2, VAESEF_VV }, // 272 |
19430 | | { PseudoVAESEF_VV_M4, VAESEF_VV }, // 273 |
19431 | | { PseudoVAESEF_VV_M8, VAESEF_VV }, // 274 |
19432 | | { PseudoVAESEF_VV_MF2, VAESEF_VV }, // 275 |
19433 | | { PseudoVAESEM_VS_M1_M1, VAESEM_VS }, // 276 |
19434 | | { PseudoVAESEM_VS_M1_MF2, VAESEM_VS }, // 277 |
19435 | | { PseudoVAESEM_VS_M1_MF4, VAESEM_VS }, // 278 |
19436 | | { PseudoVAESEM_VS_M1_MF8, VAESEM_VS }, // 279 |
19437 | | { PseudoVAESEM_VS_M2_M1, VAESEM_VS }, // 280 |
19438 | | { PseudoVAESEM_VS_M2_M2, VAESEM_VS }, // 281 |
19439 | | { PseudoVAESEM_VS_M2_MF2, VAESEM_VS }, // 282 |
19440 | | { PseudoVAESEM_VS_M2_MF4, VAESEM_VS }, // 283 |
19441 | | { PseudoVAESEM_VS_M2_MF8, VAESEM_VS }, // 284 |
19442 | | { PseudoVAESEM_VS_M4_M1, VAESEM_VS }, // 285 |
19443 | | { PseudoVAESEM_VS_M4_M2, VAESEM_VS }, // 286 |
19444 | | { PseudoVAESEM_VS_M4_M4, VAESEM_VS }, // 287 |
19445 | | { PseudoVAESEM_VS_M4_MF2, VAESEM_VS }, // 288 |
19446 | | { PseudoVAESEM_VS_M4_MF4, VAESEM_VS }, // 289 |
19447 | | { PseudoVAESEM_VS_M4_MF8, VAESEM_VS }, // 290 |
19448 | | { PseudoVAESEM_VS_M8_M1, VAESEM_VS }, // 291 |
19449 | | { PseudoVAESEM_VS_M8_M2, VAESEM_VS }, // 292 |
19450 | | { PseudoVAESEM_VS_M8_M4, VAESEM_VS }, // 293 |
19451 | | { PseudoVAESEM_VS_M8_MF2, VAESEM_VS }, // 294 |
19452 | | { PseudoVAESEM_VS_M8_MF4, VAESEM_VS }, // 295 |
19453 | | { PseudoVAESEM_VS_M8_MF8, VAESEM_VS }, // 296 |
19454 | | { PseudoVAESEM_VS_MF2_MF2, VAESEM_VS }, // 297 |
19455 | | { PseudoVAESEM_VS_MF2_MF4, VAESEM_VS }, // 298 |
19456 | | { PseudoVAESEM_VS_MF2_MF8, VAESEM_VS }, // 299 |
19457 | | { PseudoVAESEM_VV_M1, VAESEM_VV }, // 300 |
19458 | | { PseudoVAESEM_VV_M2, VAESEM_VV }, // 301 |
19459 | | { PseudoVAESEM_VV_M4, VAESEM_VV }, // 302 |
19460 | | { PseudoVAESEM_VV_M8, VAESEM_VV }, // 303 |
19461 | | { PseudoVAESEM_VV_MF2, VAESEM_VV }, // 304 |
19462 | | { PseudoVAESKF1_VI_M1, VAESKF1_VI }, // 305 |
19463 | | { PseudoVAESKF1_VI_M2, VAESKF1_VI }, // 306 |
19464 | | { PseudoVAESKF1_VI_M4, VAESKF1_VI }, // 307 |
19465 | | { PseudoVAESKF1_VI_M8, VAESKF1_VI }, // 308 |
19466 | | { PseudoVAESKF1_VI_MF2, VAESKF1_VI }, // 309 |
19467 | | { PseudoVAESKF2_VI_M1, VAESKF2_VI }, // 310 |
19468 | | { PseudoVAESKF2_VI_M2, VAESKF2_VI }, // 311 |
19469 | | { PseudoVAESKF2_VI_M4, VAESKF2_VI }, // 312 |
19470 | | { PseudoVAESKF2_VI_M8, VAESKF2_VI }, // 313 |
19471 | | { PseudoVAESKF2_VI_MF2, VAESKF2_VI }, // 314 |
19472 | | { PseudoVAESZ_VS_M1_M1, VAESZ_VS }, // 315 |
19473 | | { PseudoVAESZ_VS_M1_MF2, VAESZ_VS }, // 316 |
19474 | | { PseudoVAESZ_VS_M1_MF4, VAESZ_VS }, // 317 |
19475 | | { PseudoVAESZ_VS_M1_MF8, VAESZ_VS }, // 318 |
19476 | | { PseudoVAESZ_VS_M2_M1, VAESZ_VS }, // 319 |
19477 | | { PseudoVAESZ_VS_M2_M2, VAESZ_VS }, // 320 |
19478 | | { PseudoVAESZ_VS_M2_MF2, VAESZ_VS }, // 321 |
19479 | | { PseudoVAESZ_VS_M2_MF4, VAESZ_VS }, // 322 |
19480 | | { PseudoVAESZ_VS_M2_MF8, VAESZ_VS }, // 323 |
19481 | | { PseudoVAESZ_VS_M4_M1, VAESZ_VS }, // 324 |
19482 | | { PseudoVAESZ_VS_M4_M2, VAESZ_VS }, // 325 |
19483 | | { PseudoVAESZ_VS_M4_M4, VAESZ_VS }, // 326 |
19484 | | { PseudoVAESZ_VS_M4_MF2, VAESZ_VS }, // 327 |
19485 | | { PseudoVAESZ_VS_M4_MF4, VAESZ_VS }, // 328 |
19486 | | { PseudoVAESZ_VS_M4_MF8, VAESZ_VS }, // 329 |
19487 | | { PseudoVAESZ_VS_M8_M1, VAESZ_VS }, // 330 |
19488 | | { PseudoVAESZ_VS_M8_M2, VAESZ_VS }, // 331 |
19489 | | { PseudoVAESZ_VS_M8_M4, VAESZ_VS }, // 332 |
19490 | | { PseudoVAESZ_VS_M8_MF2, VAESZ_VS }, // 333 |
19491 | | { PseudoVAESZ_VS_M8_MF4, VAESZ_VS }, // 334 |
19492 | | { PseudoVAESZ_VS_M8_MF8, VAESZ_VS }, // 335 |
19493 | | { PseudoVAESZ_VS_MF2_MF2, VAESZ_VS }, // 336 |
19494 | | { PseudoVAESZ_VS_MF2_MF4, VAESZ_VS }, // 337 |
19495 | | { PseudoVAESZ_VS_MF2_MF8, VAESZ_VS }, // 338 |
19496 | | { PseudoVANDN_VV_M1, VANDN_VV }, // 339 |
19497 | | { PseudoVANDN_VV_M1_MASK, VANDN_VV }, // 340 |
19498 | | { PseudoVANDN_VV_M2, VANDN_VV }, // 341 |
19499 | | { PseudoVANDN_VV_M2_MASK, VANDN_VV }, // 342 |
19500 | | { PseudoVANDN_VV_M4, VANDN_VV }, // 343 |
19501 | | { PseudoVANDN_VV_M4_MASK, VANDN_VV }, // 344 |
19502 | | { PseudoVANDN_VV_M8, VANDN_VV }, // 345 |
19503 | | { PseudoVANDN_VV_M8_MASK, VANDN_VV }, // 346 |
19504 | | { PseudoVANDN_VV_MF2, VANDN_VV }, // 347 |
19505 | | { PseudoVANDN_VV_MF2_MASK, VANDN_VV }, // 348 |
19506 | | { PseudoVANDN_VV_MF4, VANDN_VV }, // 349 |
19507 | | { PseudoVANDN_VV_MF4_MASK, VANDN_VV }, // 350 |
19508 | | { PseudoVANDN_VV_MF8, VANDN_VV }, // 351 |
19509 | | { PseudoVANDN_VV_MF8_MASK, VANDN_VV }, // 352 |
19510 | | { PseudoVANDN_VX_M1, VANDN_VX }, // 353 |
19511 | | { PseudoVANDN_VX_M1_MASK, VANDN_VX }, // 354 |
19512 | | { PseudoVANDN_VX_M2, VANDN_VX }, // 355 |
19513 | | { PseudoVANDN_VX_M2_MASK, VANDN_VX }, // 356 |
19514 | | { PseudoVANDN_VX_M4, VANDN_VX }, // 357 |
19515 | | { PseudoVANDN_VX_M4_MASK, VANDN_VX }, // 358 |
19516 | | { PseudoVANDN_VX_M8, VANDN_VX }, // 359 |
19517 | | { PseudoVANDN_VX_M8_MASK, VANDN_VX }, // 360 |
19518 | | { PseudoVANDN_VX_MF2, VANDN_VX }, // 361 |
19519 | | { PseudoVANDN_VX_MF2_MASK, VANDN_VX }, // 362 |
19520 | | { PseudoVANDN_VX_MF4, VANDN_VX }, // 363 |
19521 | | { PseudoVANDN_VX_MF4_MASK, VANDN_VX }, // 364 |
19522 | | { PseudoVANDN_VX_MF8, VANDN_VX }, // 365 |
19523 | | { PseudoVANDN_VX_MF8_MASK, VANDN_VX }, // 366 |
19524 | | { PseudoVAND_VI_M1, VAND_VI }, // 367 |
19525 | | { PseudoVAND_VI_M1_MASK, VAND_VI }, // 368 |
19526 | | { PseudoVAND_VI_M2, VAND_VI }, // 369 |
19527 | | { PseudoVAND_VI_M2_MASK, VAND_VI }, // 370 |
19528 | | { PseudoVAND_VI_M4, VAND_VI }, // 371 |
19529 | | { PseudoVAND_VI_M4_MASK, VAND_VI }, // 372 |
19530 | | { PseudoVAND_VI_M8, VAND_VI }, // 373 |
19531 | | { PseudoVAND_VI_M8_MASK, VAND_VI }, // 374 |
19532 | | { PseudoVAND_VI_MF2, VAND_VI }, // 375 |
19533 | | { PseudoVAND_VI_MF2_MASK, VAND_VI }, // 376 |
19534 | | { PseudoVAND_VI_MF4, VAND_VI }, // 377 |
19535 | | { PseudoVAND_VI_MF4_MASK, VAND_VI }, // 378 |
19536 | | { PseudoVAND_VI_MF8, VAND_VI }, // 379 |
19537 | | { PseudoVAND_VI_MF8_MASK, VAND_VI }, // 380 |
19538 | | { PseudoVAND_VV_M1, VAND_VV }, // 381 |
19539 | | { PseudoVAND_VV_M1_MASK, VAND_VV }, // 382 |
19540 | | { PseudoVAND_VV_M2, VAND_VV }, // 383 |
19541 | | { PseudoVAND_VV_M2_MASK, VAND_VV }, // 384 |
19542 | | { PseudoVAND_VV_M4, VAND_VV }, // 385 |
19543 | | { PseudoVAND_VV_M4_MASK, VAND_VV }, // 386 |
19544 | | { PseudoVAND_VV_M8, VAND_VV }, // 387 |
19545 | | { PseudoVAND_VV_M8_MASK, VAND_VV }, // 388 |
19546 | | { PseudoVAND_VV_MF2, VAND_VV }, // 389 |
19547 | | { PseudoVAND_VV_MF2_MASK, VAND_VV }, // 390 |
19548 | | { PseudoVAND_VV_MF4, VAND_VV }, // 391 |
19549 | | { PseudoVAND_VV_MF4_MASK, VAND_VV }, // 392 |
19550 | | { PseudoVAND_VV_MF8, VAND_VV }, // 393 |
19551 | | { PseudoVAND_VV_MF8_MASK, VAND_VV }, // 394 |
19552 | | { PseudoVAND_VX_M1, VAND_VX }, // 395 |
19553 | | { PseudoVAND_VX_M1_MASK, VAND_VX }, // 396 |
19554 | | { PseudoVAND_VX_M2, VAND_VX }, // 397 |
19555 | | { PseudoVAND_VX_M2_MASK, VAND_VX }, // 398 |
19556 | | { PseudoVAND_VX_M4, VAND_VX }, // 399 |
19557 | | { PseudoVAND_VX_M4_MASK, VAND_VX }, // 400 |
19558 | | { PseudoVAND_VX_M8, VAND_VX }, // 401 |
19559 | | { PseudoVAND_VX_M8_MASK, VAND_VX }, // 402 |
19560 | | { PseudoVAND_VX_MF2, VAND_VX }, // 403 |
19561 | | { PseudoVAND_VX_MF2_MASK, VAND_VX }, // 404 |
19562 | | { PseudoVAND_VX_MF4, VAND_VX }, // 405 |
19563 | | { PseudoVAND_VX_MF4_MASK, VAND_VX }, // 406 |
19564 | | { PseudoVAND_VX_MF8, VAND_VX }, // 407 |
19565 | | { PseudoVAND_VX_MF8_MASK, VAND_VX }, // 408 |
19566 | | { PseudoVASUBU_VV_M1, VASUBU_VV }, // 409 |
19567 | | { PseudoVASUBU_VV_M1_MASK, VASUBU_VV }, // 410 |
19568 | | { PseudoVASUBU_VV_M2, VASUBU_VV }, // 411 |
19569 | | { PseudoVASUBU_VV_M2_MASK, VASUBU_VV }, // 412 |
19570 | | { PseudoVASUBU_VV_M4, VASUBU_VV }, // 413 |
19571 | | { PseudoVASUBU_VV_M4_MASK, VASUBU_VV }, // 414 |
19572 | | { PseudoVASUBU_VV_M8, VASUBU_VV }, // 415 |
19573 | | { PseudoVASUBU_VV_M8_MASK, VASUBU_VV }, // 416 |
19574 | | { PseudoVASUBU_VV_MF2, VASUBU_VV }, // 417 |
19575 | | { PseudoVASUBU_VV_MF2_MASK, VASUBU_VV }, // 418 |
19576 | | { PseudoVASUBU_VV_MF4, VASUBU_VV }, // 419 |
19577 | | { PseudoVASUBU_VV_MF4_MASK, VASUBU_VV }, // 420 |
19578 | | { PseudoVASUBU_VV_MF8, VASUBU_VV }, // 421 |
19579 | | { PseudoVASUBU_VV_MF8_MASK, VASUBU_VV }, // 422 |
19580 | | { PseudoVASUBU_VX_M1, VASUBU_VX }, // 423 |
19581 | | { PseudoVASUBU_VX_M1_MASK, VASUBU_VX }, // 424 |
19582 | | { PseudoVASUBU_VX_M2, VASUBU_VX }, // 425 |
19583 | | { PseudoVASUBU_VX_M2_MASK, VASUBU_VX }, // 426 |
19584 | | { PseudoVASUBU_VX_M4, VASUBU_VX }, // 427 |
19585 | | { PseudoVASUBU_VX_M4_MASK, VASUBU_VX }, // 428 |
19586 | | { PseudoVASUBU_VX_M8, VASUBU_VX }, // 429 |
19587 | | { PseudoVASUBU_VX_M8_MASK, VASUBU_VX }, // 430 |
19588 | | { PseudoVASUBU_VX_MF2, VASUBU_VX }, // 431 |
19589 | | { PseudoVASUBU_VX_MF2_MASK, VASUBU_VX }, // 432 |
19590 | | { PseudoVASUBU_VX_MF4, VASUBU_VX }, // 433 |
19591 | | { PseudoVASUBU_VX_MF4_MASK, VASUBU_VX }, // 434 |
19592 | | { PseudoVASUBU_VX_MF8, VASUBU_VX }, // 435 |
19593 | | { PseudoVASUBU_VX_MF8_MASK, VASUBU_VX }, // 436 |
19594 | | { PseudoVASUB_VV_M1, VASUB_VV }, // 437 |
19595 | | { PseudoVASUB_VV_M1_MASK, VASUB_VV }, // 438 |
19596 | | { PseudoVASUB_VV_M2, VASUB_VV }, // 439 |
19597 | | { PseudoVASUB_VV_M2_MASK, VASUB_VV }, // 440 |
19598 | | { PseudoVASUB_VV_M4, VASUB_VV }, // 441 |
19599 | | { PseudoVASUB_VV_M4_MASK, VASUB_VV }, // 442 |
19600 | | { PseudoVASUB_VV_M8, VASUB_VV }, // 443 |
19601 | | { PseudoVASUB_VV_M8_MASK, VASUB_VV }, // 444 |
19602 | | { PseudoVASUB_VV_MF2, VASUB_VV }, // 445 |
19603 | | { PseudoVASUB_VV_MF2_MASK, VASUB_VV }, // 446 |
19604 | | { PseudoVASUB_VV_MF4, VASUB_VV }, // 447 |
19605 | | { PseudoVASUB_VV_MF4_MASK, VASUB_VV }, // 448 |
19606 | | { PseudoVASUB_VV_MF8, VASUB_VV }, // 449 |
19607 | | { PseudoVASUB_VV_MF8_MASK, VASUB_VV }, // 450 |
19608 | | { PseudoVASUB_VX_M1, VASUB_VX }, // 451 |
19609 | | { PseudoVASUB_VX_M1_MASK, VASUB_VX }, // 452 |
19610 | | { PseudoVASUB_VX_M2, VASUB_VX }, // 453 |
19611 | | { PseudoVASUB_VX_M2_MASK, VASUB_VX }, // 454 |
19612 | | { PseudoVASUB_VX_M4, VASUB_VX }, // 455 |
19613 | | { PseudoVASUB_VX_M4_MASK, VASUB_VX }, // 456 |
19614 | | { PseudoVASUB_VX_M8, VASUB_VX }, // 457 |
19615 | | { PseudoVASUB_VX_M8_MASK, VASUB_VX }, // 458 |
19616 | | { PseudoVASUB_VX_MF2, VASUB_VX }, // 459 |
19617 | | { PseudoVASUB_VX_MF2_MASK, VASUB_VX }, // 460 |
19618 | | { PseudoVASUB_VX_MF4, VASUB_VX }, // 461 |
19619 | | { PseudoVASUB_VX_MF4_MASK, VASUB_VX }, // 462 |
19620 | | { PseudoVASUB_VX_MF8, VASUB_VX }, // 463 |
19621 | | { PseudoVASUB_VX_MF8_MASK, VASUB_VX }, // 464 |
19622 | | { PseudoVBREV8_V_M1, VBREV8_V }, // 465 |
19623 | | { PseudoVBREV8_V_M1_MASK, VBREV8_V }, // 466 |
19624 | | { PseudoVBREV8_V_M2, VBREV8_V }, // 467 |
19625 | | { PseudoVBREV8_V_M2_MASK, VBREV8_V }, // 468 |
19626 | | { PseudoVBREV8_V_M4, VBREV8_V }, // 469 |
19627 | | { PseudoVBREV8_V_M4_MASK, VBREV8_V }, // 470 |
19628 | | { PseudoVBREV8_V_M8, VBREV8_V }, // 471 |
19629 | | { PseudoVBREV8_V_M8_MASK, VBREV8_V }, // 472 |
19630 | | { PseudoVBREV8_V_MF2, VBREV8_V }, // 473 |
19631 | | { PseudoVBREV8_V_MF2_MASK, VBREV8_V }, // 474 |
19632 | | { PseudoVBREV8_V_MF4, VBREV8_V }, // 475 |
19633 | | { PseudoVBREV8_V_MF4_MASK, VBREV8_V }, // 476 |
19634 | | { PseudoVBREV8_V_MF8, VBREV8_V }, // 477 |
19635 | | { PseudoVBREV8_V_MF8_MASK, VBREV8_V }, // 478 |
19636 | | { PseudoVBREV_V_M1, VBREV_V }, // 479 |
19637 | | { PseudoVBREV_V_M1_MASK, VBREV_V }, // 480 |
19638 | | { PseudoVBREV_V_M2, VBREV_V }, // 481 |
19639 | | { PseudoVBREV_V_M2_MASK, VBREV_V }, // 482 |
19640 | | { PseudoVBREV_V_M4, VBREV_V }, // 483 |
19641 | | { PseudoVBREV_V_M4_MASK, VBREV_V }, // 484 |
19642 | | { PseudoVBREV_V_M8, VBREV_V }, // 485 |
19643 | | { PseudoVBREV_V_M8_MASK, VBREV_V }, // 486 |
19644 | | { PseudoVBREV_V_MF2, VBREV_V }, // 487 |
19645 | | { PseudoVBREV_V_MF2_MASK, VBREV_V }, // 488 |
19646 | | { PseudoVBREV_V_MF4, VBREV_V }, // 489 |
19647 | | { PseudoVBREV_V_MF4_MASK, VBREV_V }, // 490 |
19648 | | { PseudoVBREV_V_MF8, VBREV_V }, // 491 |
19649 | | { PseudoVBREV_V_MF8_MASK, VBREV_V }, // 492 |
19650 | | { PseudoVCLMULH_VV_M1, VCLMULH_VV }, // 493 |
19651 | | { PseudoVCLMULH_VV_M1_MASK, VCLMULH_VV }, // 494 |
19652 | | { PseudoVCLMULH_VV_M2, VCLMULH_VV }, // 495 |
19653 | | { PseudoVCLMULH_VV_M2_MASK, VCLMULH_VV }, // 496 |
19654 | | { PseudoVCLMULH_VV_M4, VCLMULH_VV }, // 497 |
19655 | | { PseudoVCLMULH_VV_M4_MASK, VCLMULH_VV }, // 498 |
19656 | | { PseudoVCLMULH_VV_M8, VCLMULH_VV }, // 499 |
19657 | | { PseudoVCLMULH_VV_M8_MASK, VCLMULH_VV }, // 500 |
19658 | | { PseudoVCLMULH_VV_MF2, VCLMULH_VV }, // 501 |
19659 | | { PseudoVCLMULH_VV_MF2_MASK, VCLMULH_VV }, // 502 |
19660 | | { PseudoVCLMULH_VV_MF4, VCLMULH_VV }, // 503 |
19661 | | { PseudoVCLMULH_VV_MF4_MASK, VCLMULH_VV }, // 504 |
19662 | | { PseudoVCLMULH_VV_MF8, VCLMULH_VV }, // 505 |
19663 | | { PseudoVCLMULH_VV_MF8_MASK, VCLMULH_VV }, // 506 |
19664 | | { PseudoVCLMULH_VX_M1, VCLMULH_VX }, // 507 |
19665 | | { PseudoVCLMULH_VX_M1_MASK, VCLMULH_VX }, // 508 |
19666 | | { PseudoVCLMULH_VX_M2, VCLMULH_VX }, // 509 |
19667 | | { PseudoVCLMULH_VX_M2_MASK, VCLMULH_VX }, // 510 |
19668 | | { PseudoVCLMULH_VX_M4, VCLMULH_VX }, // 511 |
19669 | | { PseudoVCLMULH_VX_M4_MASK, VCLMULH_VX }, // 512 |
19670 | | { PseudoVCLMULH_VX_M8, VCLMULH_VX }, // 513 |
19671 | | { PseudoVCLMULH_VX_M8_MASK, VCLMULH_VX }, // 514 |
19672 | | { PseudoVCLMULH_VX_MF2, VCLMULH_VX }, // 515 |
19673 | | { PseudoVCLMULH_VX_MF2_MASK, VCLMULH_VX }, // 516 |
19674 | | { PseudoVCLMULH_VX_MF4, VCLMULH_VX }, // 517 |
19675 | | { PseudoVCLMULH_VX_MF4_MASK, VCLMULH_VX }, // 518 |
19676 | | { PseudoVCLMULH_VX_MF8, VCLMULH_VX }, // 519 |
19677 | | { PseudoVCLMULH_VX_MF8_MASK, VCLMULH_VX }, // 520 |
19678 | | { PseudoVCLMUL_VV_M1, VCLMUL_VV }, // 521 |
19679 | | { PseudoVCLMUL_VV_M1_MASK, VCLMUL_VV }, // 522 |
19680 | | { PseudoVCLMUL_VV_M2, VCLMUL_VV }, // 523 |
19681 | | { PseudoVCLMUL_VV_M2_MASK, VCLMUL_VV }, // 524 |
19682 | | { PseudoVCLMUL_VV_M4, VCLMUL_VV }, // 525 |
19683 | | { PseudoVCLMUL_VV_M4_MASK, VCLMUL_VV }, // 526 |
19684 | | { PseudoVCLMUL_VV_M8, VCLMUL_VV }, // 527 |
19685 | | { PseudoVCLMUL_VV_M8_MASK, VCLMUL_VV }, // 528 |
19686 | | { PseudoVCLMUL_VV_MF2, VCLMUL_VV }, // 529 |
19687 | | { PseudoVCLMUL_VV_MF2_MASK, VCLMUL_VV }, // 530 |
19688 | | { PseudoVCLMUL_VV_MF4, VCLMUL_VV }, // 531 |
19689 | | { PseudoVCLMUL_VV_MF4_MASK, VCLMUL_VV }, // 532 |
19690 | | { PseudoVCLMUL_VV_MF8, VCLMUL_VV }, // 533 |
19691 | | { PseudoVCLMUL_VV_MF8_MASK, VCLMUL_VV }, // 534 |
19692 | | { PseudoVCLMUL_VX_M1, VCLMUL_VX }, // 535 |
19693 | | { PseudoVCLMUL_VX_M1_MASK, VCLMUL_VX }, // 536 |
19694 | | { PseudoVCLMUL_VX_M2, VCLMUL_VX }, // 537 |
19695 | | { PseudoVCLMUL_VX_M2_MASK, VCLMUL_VX }, // 538 |
19696 | | { PseudoVCLMUL_VX_M4, VCLMUL_VX }, // 539 |
19697 | | { PseudoVCLMUL_VX_M4_MASK, VCLMUL_VX }, // 540 |
19698 | | { PseudoVCLMUL_VX_M8, VCLMUL_VX }, // 541 |
19699 | | { PseudoVCLMUL_VX_M8_MASK, VCLMUL_VX }, // 542 |
19700 | | { PseudoVCLMUL_VX_MF2, VCLMUL_VX }, // 543 |
19701 | | { PseudoVCLMUL_VX_MF2_MASK, VCLMUL_VX }, // 544 |
19702 | | { PseudoVCLMUL_VX_MF4, VCLMUL_VX }, // 545 |
19703 | | { PseudoVCLMUL_VX_MF4_MASK, VCLMUL_VX }, // 546 |
19704 | | { PseudoVCLMUL_VX_MF8, VCLMUL_VX }, // 547 |
19705 | | { PseudoVCLMUL_VX_MF8_MASK, VCLMUL_VX }, // 548 |
19706 | | { PseudoVCLZ_V_M1, VCLZ_V }, // 549 |
19707 | | { PseudoVCLZ_V_M1_MASK, VCLZ_V }, // 550 |
19708 | | { PseudoVCLZ_V_M2, VCLZ_V }, // 551 |
19709 | | { PseudoVCLZ_V_M2_MASK, VCLZ_V }, // 552 |
19710 | | { PseudoVCLZ_V_M4, VCLZ_V }, // 553 |
19711 | | { PseudoVCLZ_V_M4_MASK, VCLZ_V }, // 554 |
19712 | | { PseudoVCLZ_V_M8, VCLZ_V }, // 555 |
19713 | | { PseudoVCLZ_V_M8_MASK, VCLZ_V }, // 556 |
19714 | | { PseudoVCLZ_V_MF2, VCLZ_V }, // 557 |
19715 | | { PseudoVCLZ_V_MF2_MASK, VCLZ_V }, // 558 |
19716 | | { PseudoVCLZ_V_MF4, VCLZ_V }, // 559 |
19717 | | { PseudoVCLZ_V_MF4_MASK, VCLZ_V }, // 560 |
19718 | | { PseudoVCLZ_V_MF8, VCLZ_V }, // 561 |
19719 | | { PseudoVCLZ_V_MF8_MASK, VCLZ_V }, // 562 |
19720 | | { PseudoVCOMPRESS_VM_M1_E16, VCOMPRESS_VM }, // 563 |
19721 | | { PseudoVCOMPRESS_VM_M1_E32, VCOMPRESS_VM }, // 564 |
19722 | | { PseudoVCOMPRESS_VM_M1_E64, VCOMPRESS_VM }, // 565 |
19723 | | { PseudoVCOMPRESS_VM_M1_E8, VCOMPRESS_VM }, // 566 |
19724 | | { PseudoVCOMPRESS_VM_M2_E16, VCOMPRESS_VM }, // 567 |
19725 | | { PseudoVCOMPRESS_VM_M2_E32, VCOMPRESS_VM }, // 568 |
19726 | | { PseudoVCOMPRESS_VM_M2_E64, VCOMPRESS_VM }, // 569 |
19727 | | { PseudoVCOMPRESS_VM_M2_E8, VCOMPRESS_VM }, // 570 |
19728 | | { PseudoVCOMPRESS_VM_M4_E16, VCOMPRESS_VM }, // 571 |
19729 | | { PseudoVCOMPRESS_VM_M4_E32, VCOMPRESS_VM }, // 572 |
19730 | | { PseudoVCOMPRESS_VM_M4_E64, VCOMPRESS_VM }, // 573 |
19731 | | { PseudoVCOMPRESS_VM_M4_E8, VCOMPRESS_VM }, // 574 |
19732 | | { PseudoVCOMPRESS_VM_M8_E16, VCOMPRESS_VM }, // 575 |
19733 | | { PseudoVCOMPRESS_VM_M8_E32, VCOMPRESS_VM }, // 576 |
19734 | | { PseudoVCOMPRESS_VM_M8_E64, VCOMPRESS_VM }, // 577 |
19735 | | { PseudoVCOMPRESS_VM_M8_E8, VCOMPRESS_VM }, // 578 |
19736 | | { PseudoVCOMPRESS_VM_MF2_E16, VCOMPRESS_VM }, // 579 |
19737 | | { PseudoVCOMPRESS_VM_MF2_E32, VCOMPRESS_VM }, // 580 |
19738 | | { PseudoVCOMPRESS_VM_MF2_E8, VCOMPRESS_VM }, // 581 |
19739 | | { PseudoVCOMPRESS_VM_MF4_E16, VCOMPRESS_VM }, // 582 |
19740 | | { PseudoVCOMPRESS_VM_MF4_E8, VCOMPRESS_VM }, // 583 |
19741 | | { PseudoVCOMPRESS_VM_MF8_E8, VCOMPRESS_VM }, // 584 |
19742 | | { PseudoVCPOP_M_B1, VCPOP_M }, // 585 |
19743 | | { PseudoVCPOP_M_B16, VCPOP_M }, // 586 |
19744 | | { PseudoVCPOP_M_B16_MASK, VCPOP_M }, // 587 |
19745 | | { PseudoVCPOP_M_B1_MASK, VCPOP_M }, // 588 |
19746 | | { PseudoVCPOP_M_B2, VCPOP_M }, // 589 |
19747 | | { PseudoVCPOP_M_B2_MASK, VCPOP_M }, // 590 |
19748 | | { PseudoVCPOP_M_B32, VCPOP_M }, // 591 |
19749 | | { PseudoVCPOP_M_B32_MASK, VCPOP_M }, // 592 |
19750 | | { PseudoVCPOP_M_B4, VCPOP_M }, // 593 |
19751 | | { PseudoVCPOP_M_B4_MASK, VCPOP_M }, // 594 |
19752 | | { PseudoVCPOP_M_B64, VCPOP_M }, // 595 |
19753 | | { PseudoVCPOP_M_B64_MASK, VCPOP_M }, // 596 |
19754 | | { PseudoVCPOP_M_B8, VCPOP_M }, // 597 |
19755 | | { PseudoVCPOP_M_B8_MASK, VCPOP_M }, // 598 |
19756 | | { PseudoVCPOP_V_M1, VCPOP_V }, // 599 |
19757 | | { PseudoVCPOP_V_M1_MASK, VCPOP_V }, // 600 |
19758 | | { PseudoVCPOP_V_M2, VCPOP_V }, // 601 |
19759 | | { PseudoVCPOP_V_M2_MASK, VCPOP_V }, // 602 |
19760 | | { PseudoVCPOP_V_M4, VCPOP_V }, // 603 |
19761 | | { PseudoVCPOP_V_M4_MASK, VCPOP_V }, // 604 |
19762 | | { PseudoVCPOP_V_M8, VCPOP_V }, // 605 |
19763 | | { PseudoVCPOP_V_M8_MASK, VCPOP_V }, // 606 |
19764 | | { PseudoVCPOP_V_MF2, VCPOP_V }, // 607 |
19765 | | { PseudoVCPOP_V_MF2_MASK, VCPOP_V }, // 608 |
19766 | | { PseudoVCPOP_V_MF4, VCPOP_V }, // 609 |
19767 | | { PseudoVCPOP_V_MF4_MASK, VCPOP_V }, // 610 |
19768 | | { PseudoVCPOP_V_MF8, VCPOP_V }, // 611 |
19769 | | { PseudoVCPOP_V_MF8_MASK, VCPOP_V }, // 612 |
19770 | | { PseudoVCTZ_V_M1, VCTZ_V }, // 613 |
19771 | | { PseudoVCTZ_V_M1_MASK, VCTZ_V }, // 614 |
19772 | | { PseudoVCTZ_V_M2, VCTZ_V }, // 615 |
19773 | | { PseudoVCTZ_V_M2_MASK, VCTZ_V }, // 616 |
19774 | | { PseudoVCTZ_V_M4, VCTZ_V }, // 617 |
19775 | | { PseudoVCTZ_V_M4_MASK, VCTZ_V }, // 618 |
19776 | | { PseudoVCTZ_V_M8, VCTZ_V }, // 619 |
19777 | | { PseudoVCTZ_V_M8_MASK, VCTZ_V }, // 620 |
19778 | | { PseudoVCTZ_V_MF2, VCTZ_V }, // 621 |
19779 | | { PseudoVCTZ_V_MF2_MASK, VCTZ_V }, // 622 |
19780 | | { PseudoVCTZ_V_MF4, VCTZ_V }, // 623 |
19781 | | { PseudoVCTZ_V_MF4_MASK, VCTZ_V }, // 624 |
19782 | | { PseudoVCTZ_V_MF8, VCTZ_V }, // 625 |
19783 | | { PseudoVCTZ_V_MF8_MASK, VCTZ_V }, // 626 |
19784 | | { PseudoVC_FPR16VV_SE_M1, VC_FVV }, // 627 |
19785 | | { PseudoVC_FPR16VV_SE_M2, VC_FVV }, // 628 |
19786 | | { PseudoVC_FPR16VV_SE_M4, VC_FVV }, // 629 |
19787 | | { PseudoVC_FPR16VV_SE_M8, VC_FVV }, // 630 |
19788 | | { PseudoVC_FPR16VV_SE_MF2, VC_FVV }, // 631 |
19789 | | { PseudoVC_FPR16VV_SE_MF4, VC_FVV }, // 632 |
19790 | | { PseudoVC_FPR16VW_SE_M1, VC_FVW }, // 633 |
19791 | | { PseudoVC_FPR16VW_SE_M2, VC_FVW }, // 634 |
19792 | | { PseudoVC_FPR16VW_SE_M4, VC_FVW }, // 635 |
19793 | | { PseudoVC_FPR16VW_SE_M8, VC_FVW }, // 636 |
19794 | | { PseudoVC_FPR16VW_SE_MF2, VC_FVW }, // 637 |
19795 | | { PseudoVC_FPR16VW_SE_MF4, VC_FVW }, // 638 |
19796 | | { PseudoVC_FPR16V_SE_M1, VC_FV }, // 639 |
19797 | | { PseudoVC_FPR16V_SE_M2, VC_FV }, // 640 |
19798 | | { PseudoVC_FPR16V_SE_M4, VC_FV }, // 641 |
19799 | | { PseudoVC_FPR16V_SE_M8, VC_FV }, // 642 |
19800 | | { PseudoVC_FPR16V_SE_MF2, VC_FV }, // 643 |
19801 | | { PseudoVC_FPR16V_SE_MF4, VC_FV }, // 644 |
19802 | | { PseudoVC_FPR32VV_SE_M1, VC_FVV }, // 645 |
19803 | | { PseudoVC_FPR32VV_SE_M2, VC_FVV }, // 646 |
19804 | | { PseudoVC_FPR32VV_SE_M4, VC_FVV }, // 647 |
19805 | | { PseudoVC_FPR32VV_SE_M8, VC_FVV }, // 648 |
19806 | | { PseudoVC_FPR32VV_SE_MF2, VC_FVV }, // 649 |
19807 | | { PseudoVC_FPR32VW_SE_M1, VC_FVW }, // 650 |
19808 | | { PseudoVC_FPR32VW_SE_M2, VC_FVW }, // 651 |
19809 | | { PseudoVC_FPR32VW_SE_M4, VC_FVW }, // 652 |
19810 | | { PseudoVC_FPR32VW_SE_M8, VC_FVW }, // 653 |
19811 | | { PseudoVC_FPR32VW_SE_MF2, VC_FVW }, // 654 |
19812 | | { PseudoVC_FPR32V_SE_M1, VC_FV }, // 655 |
19813 | | { PseudoVC_FPR32V_SE_M2, VC_FV }, // 656 |
19814 | | { PseudoVC_FPR32V_SE_M4, VC_FV }, // 657 |
19815 | | { PseudoVC_FPR32V_SE_M8, VC_FV }, // 658 |
19816 | | { PseudoVC_FPR32V_SE_MF2, VC_FV }, // 659 |
19817 | | { PseudoVC_FPR64VV_SE_M1, VC_FVV }, // 660 |
19818 | | { PseudoVC_FPR64VV_SE_M2, VC_FVV }, // 661 |
19819 | | { PseudoVC_FPR64VV_SE_M4, VC_FVV }, // 662 |
19820 | | { PseudoVC_FPR64VV_SE_M8, VC_FVV }, // 663 |
19821 | | { PseudoVC_FPR64V_SE_M1, VC_FV }, // 664 |
19822 | | { PseudoVC_FPR64V_SE_M2, VC_FV }, // 665 |
19823 | | { PseudoVC_FPR64V_SE_M4, VC_FV }, // 666 |
19824 | | { PseudoVC_FPR64V_SE_M8, VC_FV }, // 667 |
19825 | | { PseudoVC_IVV_SE_M1, VC_IVV }, // 668 |
19826 | | { PseudoVC_IVV_SE_M2, VC_IVV }, // 669 |
19827 | | { PseudoVC_IVV_SE_M4, VC_IVV }, // 670 |
19828 | | { PseudoVC_IVV_SE_M8, VC_IVV }, // 671 |
19829 | | { PseudoVC_IVV_SE_MF2, VC_IVV }, // 672 |
19830 | | { PseudoVC_IVV_SE_MF4, VC_IVV }, // 673 |
19831 | | { PseudoVC_IVV_SE_MF8, VC_IVV }, // 674 |
19832 | | { PseudoVC_IVW_SE_M1, VC_IVW }, // 675 |
19833 | | { PseudoVC_IVW_SE_M2, VC_IVW }, // 676 |
19834 | | { PseudoVC_IVW_SE_M4, VC_IVW }, // 677 |
19835 | | { PseudoVC_IVW_SE_MF2, VC_IVW }, // 678 |
19836 | | { PseudoVC_IVW_SE_MF4, VC_IVW }, // 679 |
19837 | | { PseudoVC_IVW_SE_MF8, VC_IVW }, // 680 |
19838 | | { PseudoVC_IV_SE_M1, VC_IV }, // 681 |
19839 | | { PseudoVC_IV_SE_M2, VC_IV }, // 682 |
19840 | | { PseudoVC_IV_SE_M4, VC_IV }, // 683 |
19841 | | { PseudoVC_IV_SE_M8, VC_IV }, // 684 |
19842 | | { PseudoVC_IV_SE_MF2, VC_IV }, // 685 |
19843 | | { PseudoVC_IV_SE_MF4, VC_IV }, // 686 |
19844 | | { PseudoVC_IV_SE_MF8, VC_IV }, // 687 |
19845 | | { PseudoVC_I_SE_M1, VC_I }, // 688 |
19846 | | { PseudoVC_I_SE_M2, VC_I }, // 689 |
19847 | | { PseudoVC_I_SE_M4, VC_I }, // 690 |
19848 | | { PseudoVC_I_SE_M8, VC_I }, // 691 |
19849 | | { PseudoVC_I_SE_MF2, VC_I }, // 692 |
19850 | | { PseudoVC_I_SE_MF4, VC_I }, // 693 |
19851 | | { PseudoVC_I_SE_MF8, VC_I }, // 694 |
19852 | | { PseudoVC_VVV_SE_M1, VC_VVV }, // 695 |
19853 | | { PseudoVC_VVV_SE_M2, VC_VVV }, // 696 |
19854 | | { PseudoVC_VVV_SE_M4, VC_VVV }, // 697 |
19855 | | { PseudoVC_VVV_SE_M8, VC_VVV }, // 698 |
19856 | | { PseudoVC_VVV_SE_MF2, VC_VVV }, // 699 |
19857 | | { PseudoVC_VVV_SE_MF4, VC_VVV }, // 700 |
19858 | | { PseudoVC_VVV_SE_MF8, VC_VVV }, // 701 |
19859 | | { PseudoVC_VVW_SE_M1, VC_VVW }, // 702 |
19860 | | { PseudoVC_VVW_SE_M2, VC_VVW }, // 703 |
19861 | | { PseudoVC_VVW_SE_M4, VC_VVW }, // 704 |
19862 | | { PseudoVC_VVW_SE_MF2, VC_VVW }, // 705 |
19863 | | { PseudoVC_VVW_SE_MF4, VC_VVW }, // 706 |
19864 | | { PseudoVC_VVW_SE_MF8, VC_VVW }, // 707 |
19865 | | { PseudoVC_VV_SE_M1, VC_VV }, // 708 |
19866 | | { PseudoVC_VV_SE_M2, VC_VV }, // 709 |
19867 | | { PseudoVC_VV_SE_M4, VC_VV }, // 710 |
19868 | | { PseudoVC_VV_SE_M8, VC_VV }, // 711 |
19869 | | { PseudoVC_VV_SE_MF2, VC_VV }, // 712 |
19870 | | { PseudoVC_VV_SE_MF4, VC_VV }, // 713 |
19871 | | { PseudoVC_VV_SE_MF8, VC_VV }, // 714 |
19872 | | { PseudoVC_V_FPR16VV_M1, VC_V_FVV }, // 715 |
19873 | | { PseudoVC_V_FPR16VV_M2, VC_V_FVV }, // 716 |
19874 | | { PseudoVC_V_FPR16VV_M4, VC_V_FVV }, // 717 |
19875 | | { PseudoVC_V_FPR16VV_M8, VC_V_FVV }, // 718 |
19876 | | { PseudoVC_V_FPR16VV_MF2, VC_V_FVV }, // 719 |
19877 | | { PseudoVC_V_FPR16VV_MF4, VC_V_FVV }, // 720 |
19878 | | { PseudoVC_V_FPR16VV_SE_M1, VC_V_FVV }, // 721 |
19879 | | { PseudoVC_V_FPR16VV_SE_M2, VC_V_FVV }, // 722 |
19880 | | { PseudoVC_V_FPR16VV_SE_M4, VC_V_FVV }, // 723 |
19881 | | { PseudoVC_V_FPR16VV_SE_M8, VC_V_FVV }, // 724 |
19882 | | { PseudoVC_V_FPR16VV_SE_MF2, VC_V_FVV }, // 725 |
19883 | | { PseudoVC_V_FPR16VV_SE_MF4, VC_V_FVV }, // 726 |
19884 | | { PseudoVC_V_FPR16VW_M1, VC_V_FVW }, // 727 |
19885 | | { PseudoVC_V_FPR16VW_M2, VC_V_FVW }, // 728 |
19886 | | { PseudoVC_V_FPR16VW_M4, VC_V_FVW }, // 729 |
19887 | | { PseudoVC_V_FPR16VW_M8, VC_V_FVW }, // 730 |
19888 | | { PseudoVC_V_FPR16VW_MF2, VC_V_FVW }, // 731 |
19889 | | { PseudoVC_V_FPR16VW_MF4, VC_V_FVW }, // 732 |
19890 | | { PseudoVC_V_FPR16VW_SE_M1, VC_V_FVW }, // 733 |
19891 | | { PseudoVC_V_FPR16VW_SE_M2, VC_V_FVW }, // 734 |
19892 | | { PseudoVC_V_FPR16VW_SE_M4, VC_V_FVW }, // 735 |
19893 | | { PseudoVC_V_FPR16VW_SE_M8, VC_V_FVW }, // 736 |
19894 | | { PseudoVC_V_FPR16VW_SE_MF2, VC_V_FVW }, // 737 |
19895 | | { PseudoVC_V_FPR16VW_SE_MF4, VC_V_FVW }, // 738 |
19896 | | { PseudoVC_V_FPR16V_M1, VC_V_FV }, // 739 |
19897 | | { PseudoVC_V_FPR16V_M2, VC_V_FV }, // 740 |
19898 | | { PseudoVC_V_FPR16V_M4, VC_V_FV }, // 741 |
19899 | | { PseudoVC_V_FPR16V_M8, VC_V_FV }, // 742 |
19900 | | { PseudoVC_V_FPR16V_MF2, VC_V_FV }, // 743 |
19901 | | { PseudoVC_V_FPR16V_MF4, VC_V_FV }, // 744 |
19902 | | { PseudoVC_V_FPR16V_SE_M1, VC_V_FV }, // 745 |
19903 | | { PseudoVC_V_FPR16V_SE_M2, VC_V_FV }, // 746 |
19904 | | { PseudoVC_V_FPR16V_SE_M4, VC_V_FV }, // 747 |
19905 | | { PseudoVC_V_FPR16V_SE_M8, VC_V_FV }, // 748 |
19906 | | { PseudoVC_V_FPR16V_SE_MF2, VC_V_FV }, // 749 |
19907 | | { PseudoVC_V_FPR16V_SE_MF4, VC_V_FV }, // 750 |
19908 | | { PseudoVC_V_FPR32VV_M1, VC_V_FVV }, // 751 |
19909 | | { PseudoVC_V_FPR32VV_M2, VC_V_FVV }, // 752 |
19910 | | { PseudoVC_V_FPR32VV_M4, VC_V_FVV }, // 753 |
19911 | | { PseudoVC_V_FPR32VV_M8, VC_V_FVV }, // 754 |
19912 | | { PseudoVC_V_FPR32VV_MF2, VC_V_FVV }, // 755 |
19913 | | { PseudoVC_V_FPR32VV_SE_M1, VC_V_FVV }, // 756 |
19914 | | { PseudoVC_V_FPR32VV_SE_M2, VC_V_FVV }, // 757 |
19915 | | { PseudoVC_V_FPR32VV_SE_M4, VC_V_FVV }, // 758 |
19916 | | { PseudoVC_V_FPR32VV_SE_M8, VC_V_FVV }, // 759 |
19917 | | { PseudoVC_V_FPR32VV_SE_MF2, VC_V_FVV }, // 760 |
19918 | | { PseudoVC_V_FPR32VW_M1, VC_V_FVW }, // 761 |
19919 | | { PseudoVC_V_FPR32VW_M2, VC_V_FVW }, // 762 |
19920 | | { PseudoVC_V_FPR32VW_M4, VC_V_FVW }, // 763 |
19921 | | { PseudoVC_V_FPR32VW_M8, VC_V_FVW }, // 764 |
19922 | | { PseudoVC_V_FPR32VW_MF2, VC_V_FVW }, // 765 |
19923 | | { PseudoVC_V_FPR32VW_SE_M1, VC_V_FVW }, // 766 |
19924 | | { PseudoVC_V_FPR32VW_SE_M2, VC_V_FVW }, // 767 |
19925 | | { PseudoVC_V_FPR32VW_SE_M4, VC_V_FVW }, // 768 |
19926 | | { PseudoVC_V_FPR32VW_SE_M8, VC_V_FVW }, // 769 |
19927 | | { PseudoVC_V_FPR32VW_SE_MF2, VC_V_FVW }, // 770 |
19928 | | { PseudoVC_V_FPR32V_M1, VC_V_FV }, // 771 |
19929 | | { PseudoVC_V_FPR32V_M2, VC_V_FV }, // 772 |
19930 | | { PseudoVC_V_FPR32V_M4, VC_V_FV }, // 773 |
19931 | | { PseudoVC_V_FPR32V_M8, VC_V_FV }, // 774 |
19932 | | { PseudoVC_V_FPR32V_MF2, VC_V_FV }, // 775 |
19933 | | { PseudoVC_V_FPR32V_SE_M1, VC_V_FV }, // 776 |
19934 | | { PseudoVC_V_FPR32V_SE_M2, VC_V_FV }, // 777 |
19935 | | { PseudoVC_V_FPR32V_SE_M4, VC_V_FV }, // 778 |
19936 | | { PseudoVC_V_FPR32V_SE_M8, VC_V_FV }, // 779 |
19937 | | { PseudoVC_V_FPR32V_SE_MF2, VC_V_FV }, // 780 |
19938 | | { PseudoVC_V_FPR64VV_M1, VC_V_FVV }, // 781 |
19939 | | { PseudoVC_V_FPR64VV_M2, VC_V_FVV }, // 782 |
19940 | | { PseudoVC_V_FPR64VV_M4, VC_V_FVV }, // 783 |
19941 | | { PseudoVC_V_FPR64VV_M8, VC_V_FVV }, // 784 |
19942 | | { PseudoVC_V_FPR64VV_SE_M1, VC_V_FVV }, // 785 |
19943 | | { PseudoVC_V_FPR64VV_SE_M2, VC_V_FVV }, // 786 |
19944 | | { PseudoVC_V_FPR64VV_SE_M4, VC_V_FVV }, // 787 |
19945 | | { PseudoVC_V_FPR64VV_SE_M8, VC_V_FVV }, // 788 |
19946 | | { PseudoVC_V_FPR64V_M1, VC_V_FV }, // 789 |
19947 | | { PseudoVC_V_FPR64V_M2, VC_V_FV }, // 790 |
19948 | | { PseudoVC_V_FPR64V_M4, VC_V_FV }, // 791 |
19949 | | { PseudoVC_V_FPR64V_M8, VC_V_FV }, // 792 |
19950 | | { PseudoVC_V_FPR64V_SE_M1, VC_V_FV }, // 793 |
19951 | | { PseudoVC_V_FPR64V_SE_M2, VC_V_FV }, // 794 |
19952 | | { PseudoVC_V_FPR64V_SE_M4, VC_V_FV }, // 795 |
19953 | | { PseudoVC_V_FPR64V_SE_M8, VC_V_FV }, // 796 |
19954 | | { PseudoVC_V_IVV_M1, VC_V_IVV }, // 797 |
19955 | | { PseudoVC_V_IVV_M2, VC_V_IVV }, // 798 |
19956 | | { PseudoVC_V_IVV_M4, VC_V_IVV }, // 799 |
19957 | | { PseudoVC_V_IVV_M8, VC_V_IVV }, // 800 |
19958 | | { PseudoVC_V_IVV_MF2, VC_V_IVV }, // 801 |
19959 | | { PseudoVC_V_IVV_MF4, VC_V_IVV }, // 802 |
19960 | | { PseudoVC_V_IVV_MF8, VC_V_IVV }, // 803 |
19961 | | { PseudoVC_V_IVV_SE_M1, VC_V_IVV }, // 804 |
19962 | | { PseudoVC_V_IVV_SE_M2, VC_V_IVV }, // 805 |
19963 | | { PseudoVC_V_IVV_SE_M4, VC_V_IVV }, // 806 |
19964 | | { PseudoVC_V_IVV_SE_M8, VC_V_IVV }, // 807 |
19965 | | { PseudoVC_V_IVV_SE_MF2, VC_V_IVV }, // 808 |
19966 | | { PseudoVC_V_IVV_SE_MF4, VC_V_IVV }, // 809 |
19967 | | { PseudoVC_V_IVV_SE_MF8, VC_V_IVV }, // 810 |
19968 | | { PseudoVC_V_IVW_M1, VC_V_IVW }, // 811 |
19969 | | { PseudoVC_V_IVW_M2, VC_V_IVW }, // 812 |
19970 | | { PseudoVC_V_IVW_M4, VC_V_IVW }, // 813 |
19971 | | { PseudoVC_V_IVW_MF2, VC_V_IVW }, // 814 |
19972 | | { PseudoVC_V_IVW_MF4, VC_V_IVW }, // 815 |
19973 | | { PseudoVC_V_IVW_MF8, VC_V_IVW }, // 816 |
19974 | | { PseudoVC_V_IVW_SE_M1, VC_V_IVW }, // 817 |
19975 | | { PseudoVC_V_IVW_SE_M2, VC_V_IVW }, // 818 |
19976 | | { PseudoVC_V_IVW_SE_M4, VC_V_IVW }, // 819 |
19977 | | { PseudoVC_V_IVW_SE_MF2, VC_V_IVW }, // 820 |
19978 | | { PseudoVC_V_IVW_SE_MF4, VC_V_IVW }, // 821 |
19979 | | { PseudoVC_V_IVW_SE_MF8, VC_V_IVW }, // 822 |
19980 | | { PseudoVC_V_IV_M1, VC_V_IV }, // 823 |
19981 | | { PseudoVC_V_IV_M2, VC_V_IV }, // 824 |
19982 | | { PseudoVC_V_IV_M4, VC_V_IV }, // 825 |
19983 | | { PseudoVC_V_IV_M8, VC_V_IV }, // 826 |
19984 | | { PseudoVC_V_IV_MF2, VC_V_IV }, // 827 |
19985 | | { PseudoVC_V_IV_MF4, VC_V_IV }, // 828 |
19986 | | { PseudoVC_V_IV_MF8, VC_V_IV }, // 829 |
19987 | | { PseudoVC_V_IV_SE_M1, VC_V_IV }, // 830 |
19988 | | { PseudoVC_V_IV_SE_M2, VC_V_IV }, // 831 |
19989 | | { PseudoVC_V_IV_SE_M4, VC_V_IV }, // 832 |
19990 | | { PseudoVC_V_IV_SE_M8, VC_V_IV }, // 833 |
19991 | | { PseudoVC_V_IV_SE_MF2, VC_V_IV }, // 834 |
19992 | | { PseudoVC_V_IV_SE_MF4, VC_V_IV }, // 835 |
19993 | | { PseudoVC_V_IV_SE_MF8, VC_V_IV }, // 836 |
19994 | | { PseudoVC_V_I_M1, VC_V_I }, // 837 |
19995 | | { PseudoVC_V_I_M2, VC_V_I }, // 838 |
19996 | | { PseudoVC_V_I_M4, VC_V_I }, // 839 |
19997 | | { PseudoVC_V_I_M8, VC_V_I }, // 840 |
19998 | | { PseudoVC_V_I_MF2, VC_V_I }, // 841 |
19999 | | { PseudoVC_V_I_MF4, VC_V_I }, // 842 |
20000 | | { PseudoVC_V_I_MF8, VC_V_I }, // 843 |
20001 | | { PseudoVC_V_I_SE_M1, VC_V_I }, // 844 |
20002 | | { PseudoVC_V_I_SE_M2, VC_V_I }, // 845 |
20003 | | { PseudoVC_V_I_SE_M4, VC_V_I }, // 846 |
20004 | | { PseudoVC_V_I_SE_M8, VC_V_I }, // 847 |
20005 | | { PseudoVC_V_I_SE_MF2, VC_V_I }, // 848 |
20006 | | { PseudoVC_V_I_SE_MF4, VC_V_I }, // 849 |
20007 | | { PseudoVC_V_I_SE_MF8, VC_V_I }, // 850 |
20008 | | { PseudoVC_V_VVV_M1, VC_V_VVV }, // 851 |
20009 | | { PseudoVC_V_VVV_M2, VC_V_VVV }, // 852 |
20010 | | { PseudoVC_V_VVV_M4, VC_V_VVV }, // 853 |
20011 | | { PseudoVC_V_VVV_M8, VC_V_VVV }, // 854 |
20012 | | { PseudoVC_V_VVV_MF2, VC_V_VVV }, // 855 |
20013 | | { PseudoVC_V_VVV_MF4, VC_V_VVV }, // 856 |
20014 | | { PseudoVC_V_VVV_MF8, VC_V_VVV }, // 857 |
20015 | | { PseudoVC_V_VVV_SE_M1, VC_V_VVV }, // 858 |
20016 | | { PseudoVC_V_VVV_SE_M2, VC_V_VVV }, // 859 |
20017 | | { PseudoVC_V_VVV_SE_M4, VC_V_VVV }, // 860 |
20018 | | { PseudoVC_V_VVV_SE_M8, VC_V_VVV }, // 861 |
20019 | | { PseudoVC_V_VVV_SE_MF2, VC_V_VVV }, // 862 |
20020 | | { PseudoVC_V_VVV_SE_MF4, VC_V_VVV }, // 863 |
20021 | | { PseudoVC_V_VVV_SE_MF8, VC_V_VVV }, // 864 |
20022 | | { PseudoVC_V_VVW_M1, VC_V_VVW }, // 865 |
20023 | | { PseudoVC_V_VVW_M2, VC_V_VVW }, // 866 |
20024 | | { PseudoVC_V_VVW_M4, VC_V_VVW }, // 867 |
20025 | | { PseudoVC_V_VVW_MF2, VC_V_VVW }, // 868 |
20026 | | { PseudoVC_V_VVW_MF4, VC_V_VVW }, // 869 |
20027 | | { PseudoVC_V_VVW_MF8, VC_V_VVW }, // 870 |
20028 | | { PseudoVC_V_VVW_SE_M1, VC_V_VVW }, // 871 |
20029 | | { PseudoVC_V_VVW_SE_M2, VC_V_VVW }, // 872 |
20030 | | { PseudoVC_V_VVW_SE_M4, VC_V_VVW }, // 873 |
20031 | | { PseudoVC_V_VVW_SE_MF2, VC_V_VVW }, // 874 |
20032 | | { PseudoVC_V_VVW_SE_MF4, VC_V_VVW }, // 875 |
20033 | | { PseudoVC_V_VVW_SE_MF8, VC_V_VVW }, // 876 |
20034 | | { PseudoVC_V_VV_M1, VC_V_VV }, // 877 |
20035 | | { PseudoVC_V_VV_M2, VC_V_VV }, // 878 |
20036 | | { PseudoVC_V_VV_M4, VC_V_VV }, // 879 |
20037 | | { PseudoVC_V_VV_M8, VC_V_VV }, // 880 |
20038 | | { PseudoVC_V_VV_MF2, VC_V_VV }, // 881 |
20039 | | { PseudoVC_V_VV_MF4, VC_V_VV }, // 882 |
20040 | | { PseudoVC_V_VV_MF8, VC_V_VV }, // 883 |
20041 | | { PseudoVC_V_VV_SE_M1, VC_V_VV }, // 884 |
20042 | | { PseudoVC_V_VV_SE_M2, VC_V_VV }, // 885 |
20043 | | { PseudoVC_V_VV_SE_M4, VC_V_VV }, // 886 |
20044 | | { PseudoVC_V_VV_SE_M8, VC_V_VV }, // 887 |
20045 | | { PseudoVC_V_VV_SE_MF2, VC_V_VV }, // 888 |
20046 | | { PseudoVC_V_VV_SE_MF4, VC_V_VV }, // 889 |
20047 | | { PseudoVC_V_VV_SE_MF8, VC_V_VV }, // 890 |
20048 | | { PseudoVC_V_XVV_M1, VC_V_XVV }, // 891 |
20049 | | { PseudoVC_V_XVV_M2, VC_V_XVV }, // 892 |
20050 | | { PseudoVC_V_XVV_M4, VC_V_XVV }, // 893 |
20051 | | { PseudoVC_V_XVV_M8, VC_V_XVV }, // 894 |
20052 | | { PseudoVC_V_XVV_MF2, VC_V_XVV }, // 895 |
20053 | | { PseudoVC_V_XVV_MF4, VC_V_XVV }, // 896 |
20054 | | { PseudoVC_V_XVV_MF8, VC_V_XVV }, // 897 |
20055 | | { PseudoVC_V_XVV_SE_M1, VC_V_XVV }, // 898 |
20056 | | { PseudoVC_V_XVV_SE_M2, VC_V_XVV }, // 899 |
20057 | | { PseudoVC_V_XVV_SE_M4, VC_V_XVV }, // 900 |
20058 | | { PseudoVC_V_XVV_SE_M8, VC_V_XVV }, // 901 |
20059 | | { PseudoVC_V_XVV_SE_MF2, VC_V_XVV }, // 902 |
20060 | | { PseudoVC_V_XVV_SE_MF4, VC_V_XVV }, // 903 |
20061 | | { PseudoVC_V_XVV_SE_MF8, VC_V_XVV }, // 904 |
20062 | | { PseudoVC_V_XVW_M1, VC_V_XVW }, // 905 |
20063 | | { PseudoVC_V_XVW_M2, VC_V_XVW }, // 906 |
20064 | | { PseudoVC_V_XVW_M4, VC_V_XVW }, // 907 |
20065 | | { PseudoVC_V_XVW_MF2, VC_V_XVW }, // 908 |
20066 | | { PseudoVC_V_XVW_MF4, VC_V_XVW }, // 909 |
20067 | | { PseudoVC_V_XVW_MF8, VC_V_XVW }, // 910 |
20068 | | { PseudoVC_V_XVW_SE_M1, VC_V_XVW }, // 911 |
20069 | | { PseudoVC_V_XVW_SE_M2, VC_V_XVW }, // 912 |
20070 | | { PseudoVC_V_XVW_SE_M4, VC_V_XVW }, // 913 |
20071 | | { PseudoVC_V_XVW_SE_MF2, VC_V_XVW }, // 914 |
20072 | | { PseudoVC_V_XVW_SE_MF4, VC_V_XVW }, // 915 |
20073 | | { PseudoVC_V_XVW_SE_MF8, VC_V_XVW }, // 916 |
20074 | | { PseudoVC_V_XV_M1, VC_V_XV }, // 917 |
20075 | | { PseudoVC_V_XV_M2, VC_V_XV }, // 918 |
20076 | | { PseudoVC_V_XV_M4, VC_V_XV }, // 919 |
20077 | | { PseudoVC_V_XV_M8, VC_V_XV }, // 920 |
20078 | | { PseudoVC_V_XV_MF2, VC_V_XV }, // 921 |
20079 | | { PseudoVC_V_XV_MF4, VC_V_XV }, // 922 |
20080 | | { PseudoVC_V_XV_MF8, VC_V_XV }, // 923 |
20081 | | { PseudoVC_V_XV_SE_M1, VC_V_XV }, // 924 |
20082 | | { PseudoVC_V_XV_SE_M2, VC_V_XV }, // 925 |
20083 | | { PseudoVC_V_XV_SE_M4, VC_V_XV }, // 926 |
20084 | | { PseudoVC_V_XV_SE_M8, VC_V_XV }, // 927 |
20085 | | { PseudoVC_V_XV_SE_MF2, VC_V_XV }, // 928 |
20086 | | { PseudoVC_V_XV_SE_MF4, VC_V_XV }, // 929 |
20087 | | { PseudoVC_V_XV_SE_MF8, VC_V_XV }, // 930 |
20088 | | { PseudoVC_V_X_M1, VC_V_X }, // 931 |
20089 | | { PseudoVC_V_X_M2, VC_V_X }, // 932 |
20090 | | { PseudoVC_V_X_M4, VC_V_X }, // 933 |
20091 | | { PseudoVC_V_X_M8, VC_V_X }, // 934 |
20092 | | { PseudoVC_V_X_MF2, VC_V_X }, // 935 |
20093 | | { PseudoVC_V_X_MF4, VC_V_X }, // 936 |
20094 | | { PseudoVC_V_X_MF8, VC_V_X }, // 937 |
20095 | | { PseudoVC_V_X_SE_M1, VC_V_X }, // 938 |
20096 | | { PseudoVC_V_X_SE_M2, VC_V_X }, // 939 |
20097 | | { PseudoVC_V_X_SE_M4, VC_V_X }, // 940 |
20098 | | { PseudoVC_V_X_SE_M8, VC_V_X }, // 941 |
20099 | | { PseudoVC_V_X_SE_MF2, VC_V_X }, // 942 |
20100 | | { PseudoVC_V_X_SE_MF4, VC_V_X }, // 943 |
20101 | | { PseudoVC_V_X_SE_MF8, VC_V_X }, // 944 |
20102 | | { PseudoVC_XVV_SE_M1, VC_XVV }, // 945 |
20103 | | { PseudoVC_XVV_SE_M2, VC_XVV }, // 946 |
20104 | | { PseudoVC_XVV_SE_M4, VC_XVV }, // 947 |
20105 | | { PseudoVC_XVV_SE_M8, VC_XVV }, // 948 |
20106 | | { PseudoVC_XVV_SE_MF2, VC_XVV }, // 949 |
20107 | | { PseudoVC_XVV_SE_MF4, VC_XVV }, // 950 |
20108 | | { PseudoVC_XVV_SE_MF8, VC_XVV }, // 951 |
20109 | | { PseudoVC_XVW_SE_M1, VC_XVW }, // 952 |
20110 | | { PseudoVC_XVW_SE_M2, VC_XVW }, // 953 |
20111 | | { PseudoVC_XVW_SE_M4, VC_XVW }, // 954 |
20112 | | { PseudoVC_XVW_SE_MF2, VC_XVW }, // 955 |
20113 | | { PseudoVC_XVW_SE_MF4, VC_XVW }, // 956 |
20114 | | { PseudoVC_XVW_SE_MF8, VC_XVW }, // 957 |
20115 | | { PseudoVC_XV_SE_M1, VC_XV }, // 958 |
20116 | | { PseudoVC_XV_SE_M2, VC_XV }, // 959 |
20117 | | { PseudoVC_XV_SE_M4, VC_XV }, // 960 |
20118 | | { PseudoVC_XV_SE_M8, VC_XV }, // 961 |
20119 | | { PseudoVC_XV_SE_MF2, VC_XV }, // 962 |
20120 | | { PseudoVC_XV_SE_MF4, VC_XV }, // 963 |
20121 | | { PseudoVC_XV_SE_MF8, VC_XV }, // 964 |
20122 | | { PseudoVC_X_SE_M1, VC_X }, // 965 |
20123 | | { PseudoVC_X_SE_M2, VC_X }, // 966 |
20124 | | { PseudoVC_X_SE_M4, VC_X }, // 967 |
20125 | | { PseudoVC_X_SE_M8, VC_X }, // 968 |
20126 | | { PseudoVC_X_SE_MF2, VC_X }, // 969 |
20127 | | { PseudoVC_X_SE_MF4, VC_X }, // 970 |
20128 | | { PseudoVC_X_SE_MF8, VC_X }, // 971 |
20129 | | { PseudoVDIVU_VV_M1_E16, VDIVU_VV }, // 972 |
20130 | | { PseudoVDIVU_VV_M1_E16_MASK, VDIVU_VV }, // 973 |
20131 | | { PseudoVDIVU_VV_M1_E32, VDIVU_VV }, // 974 |
20132 | | { PseudoVDIVU_VV_M1_E32_MASK, VDIVU_VV }, // 975 |
20133 | | { PseudoVDIVU_VV_M1_E64, VDIVU_VV }, // 976 |
20134 | | { PseudoVDIVU_VV_M1_E64_MASK, VDIVU_VV }, // 977 |
20135 | | { PseudoVDIVU_VV_M1_E8, VDIVU_VV }, // 978 |
20136 | | { PseudoVDIVU_VV_M1_E8_MASK, VDIVU_VV }, // 979 |
20137 | | { PseudoVDIVU_VV_M2_E16, VDIVU_VV }, // 980 |
20138 | | { PseudoVDIVU_VV_M2_E16_MASK, VDIVU_VV }, // 981 |
20139 | | { PseudoVDIVU_VV_M2_E32, VDIVU_VV }, // 982 |
20140 | | { PseudoVDIVU_VV_M2_E32_MASK, VDIVU_VV }, // 983 |
20141 | | { PseudoVDIVU_VV_M2_E64, VDIVU_VV }, // 984 |
20142 | | { PseudoVDIVU_VV_M2_E64_MASK, VDIVU_VV }, // 985 |
20143 | | { PseudoVDIVU_VV_M2_E8, VDIVU_VV }, // 986 |
20144 | | { PseudoVDIVU_VV_M2_E8_MASK, VDIVU_VV }, // 987 |
20145 | | { PseudoVDIVU_VV_M4_E16, VDIVU_VV }, // 988 |
20146 | | { PseudoVDIVU_VV_M4_E16_MASK, VDIVU_VV }, // 989 |
20147 | | { PseudoVDIVU_VV_M4_E32, VDIVU_VV }, // 990 |
20148 | | { PseudoVDIVU_VV_M4_E32_MASK, VDIVU_VV }, // 991 |
20149 | | { PseudoVDIVU_VV_M4_E64, VDIVU_VV }, // 992 |
20150 | | { PseudoVDIVU_VV_M4_E64_MASK, VDIVU_VV }, // 993 |
20151 | | { PseudoVDIVU_VV_M4_E8, VDIVU_VV }, // 994 |
20152 | | { PseudoVDIVU_VV_M4_E8_MASK, VDIVU_VV }, // 995 |
20153 | | { PseudoVDIVU_VV_M8_E16, VDIVU_VV }, // 996 |
20154 | | { PseudoVDIVU_VV_M8_E16_MASK, VDIVU_VV }, // 997 |
20155 | | { PseudoVDIVU_VV_M8_E32, VDIVU_VV }, // 998 |
20156 | | { PseudoVDIVU_VV_M8_E32_MASK, VDIVU_VV }, // 999 |
20157 | | { PseudoVDIVU_VV_M8_E64, VDIVU_VV }, // 1000 |
20158 | | { PseudoVDIVU_VV_M8_E64_MASK, VDIVU_VV }, // 1001 |
20159 | | { PseudoVDIVU_VV_M8_E8, VDIVU_VV }, // 1002 |
20160 | | { PseudoVDIVU_VV_M8_E8_MASK, VDIVU_VV }, // 1003 |
20161 | | { PseudoVDIVU_VV_MF2_E16, VDIVU_VV }, // 1004 |
20162 | | { PseudoVDIVU_VV_MF2_E16_MASK, VDIVU_VV }, // 1005 |
20163 | | { PseudoVDIVU_VV_MF2_E32, VDIVU_VV }, // 1006 |
20164 | | { PseudoVDIVU_VV_MF2_E32_MASK, VDIVU_VV }, // 1007 |
20165 | | { PseudoVDIVU_VV_MF2_E8, VDIVU_VV }, // 1008 |
20166 | | { PseudoVDIVU_VV_MF2_E8_MASK, VDIVU_VV }, // 1009 |
20167 | | { PseudoVDIVU_VV_MF4_E16, VDIVU_VV }, // 1010 |
20168 | | { PseudoVDIVU_VV_MF4_E16_MASK, VDIVU_VV }, // 1011 |
20169 | | { PseudoVDIVU_VV_MF4_E8, VDIVU_VV }, // 1012 |
20170 | | { PseudoVDIVU_VV_MF4_E8_MASK, VDIVU_VV }, // 1013 |
20171 | | { PseudoVDIVU_VV_MF8_E8, VDIVU_VV }, // 1014 |
20172 | | { PseudoVDIVU_VV_MF8_E8_MASK, VDIVU_VV }, // 1015 |
20173 | | { PseudoVDIVU_VX_M1_E16, VDIVU_VX }, // 1016 |
20174 | | { PseudoVDIVU_VX_M1_E16_MASK, VDIVU_VX }, // 1017 |
20175 | | { PseudoVDIVU_VX_M1_E32, VDIVU_VX }, // 1018 |
20176 | | { PseudoVDIVU_VX_M1_E32_MASK, VDIVU_VX }, // 1019 |
20177 | | { PseudoVDIVU_VX_M1_E64, VDIVU_VX }, // 1020 |
20178 | | { PseudoVDIVU_VX_M1_E64_MASK, VDIVU_VX }, // 1021 |
20179 | | { PseudoVDIVU_VX_M1_E8, VDIVU_VX }, // 1022 |
20180 | | { PseudoVDIVU_VX_M1_E8_MASK, VDIVU_VX }, // 1023 |
20181 | | { PseudoVDIVU_VX_M2_E16, VDIVU_VX }, // 1024 |
20182 | | { PseudoVDIVU_VX_M2_E16_MASK, VDIVU_VX }, // 1025 |
20183 | | { PseudoVDIVU_VX_M2_E32, VDIVU_VX }, // 1026 |
20184 | | { PseudoVDIVU_VX_M2_E32_MASK, VDIVU_VX }, // 1027 |
20185 | | { PseudoVDIVU_VX_M2_E64, VDIVU_VX }, // 1028 |
20186 | | { PseudoVDIVU_VX_M2_E64_MASK, VDIVU_VX }, // 1029 |
20187 | | { PseudoVDIVU_VX_M2_E8, VDIVU_VX }, // 1030 |
20188 | | { PseudoVDIVU_VX_M2_E8_MASK, VDIVU_VX }, // 1031 |
20189 | | { PseudoVDIVU_VX_M4_E16, VDIVU_VX }, // 1032 |
20190 | | { PseudoVDIVU_VX_M4_E16_MASK, VDIVU_VX }, // 1033 |
20191 | | { PseudoVDIVU_VX_M4_E32, VDIVU_VX }, // 1034 |
20192 | | { PseudoVDIVU_VX_M4_E32_MASK, VDIVU_VX }, // 1035 |
20193 | | { PseudoVDIVU_VX_M4_E64, VDIVU_VX }, // 1036 |
20194 | | { PseudoVDIVU_VX_M4_E64_MASK, VDIVU_VX }, // 1037 |
20195 | | { PseudoVDIVU_VX_M4_E8, VDIVU_VX }, // 1038 |
20196 | | { PseudoVDIVU_VX_M4_E8_MASK, VDIVU_VX }, // 1039 |
20197 | | { PseudoVDIVU_VX_M8_E16, VDIVU_VX }, // 1040 |
20198 | | { PseudoVDIVU_VX_M8_E16_MASK, VDIVU_VX }, // 1041 |
20199 | | { PseudoVDIVU_VX_M8_E32, VDIVU_VX }, // 1042 |
20200 | | { PseudoVDIVU_VX_M8_E32_MASK, VDIVU_VX }, // 1043 |
20201 | | { PseudoVDIVU_VX_M8_E64, VDIVU_VX }, // 1044 |
20202 | | { PseudoVDIVU_VX_M8_E64_MASK, VDIVU_VX }, // 1045 |
20203 | | { PseudoVDIVU_VX_M8_E8, VDIVU_VX }, // 1046 |
20204 | | { PseudoVDIVU_VX_M8_E8_MASK, VDIVU_VX }, // 1047 |
20205 | | { PseudoVDIVU_VX_MF2_E16, VDIVU_VX }, // 1048 |
20206 | | { PseudoVDIVU_VX_MF2_E16_MASK, VDIVU_VX }, // 1049 |
20207 | | { PseudoVDIVU_VX_MF2_E32, VDIVU_VX }, // 1050 |
20208 | | { PseudoVDIVU_VX_MF2_E32_MASK, VDIVU_VX }, // 1051 |
20209 | | { PseudoVDIVU_VX_MF2_E8, VDIVU_VX }, // 1052 |
20210 | | { PseudoVDIVU_VX_MF2_E8_MASK, VDIVU_VX }, // 1053 |
20211 | | { PseudoVDIVU_VX_MF4_E16, VDIVU_VX }, // 1054 |
20212 | | { PseudoVDIVU_VX_MF4_E16_MASK, VDIVU_VX }, // 1055 |
20213 | | { PseudoVDIVU_VX_MF4_E8, VDIVU_VX }, // 1056 |
20214 | | { PseudoVDIVU_VX_MF4_E8_MASK, VDIVU_VX }, // 1057 |
20215 | | { PseudoVDIVU_VX_MF8_E8, VDIVU_VX }, // 1058 |
20216 | | { PseudoVDIVU_VX_MF8_E8_MASK, VDIVU_VX }, // 1059 |
20217 | | { PseudoVDIV_VV_M1_E16, VDIV_VV }, // 1060 |
20218 | | { PseudoVDIV_VV_M1_E16_MASK, VDIV_VV }, // 1061 |
20219 | | { PseudoVDIV_VV_M1_E32, VDIV_VV }, // 1062 |
20220 | | { PseudoVDIV_VV_M1_E32_MASK, VDIV_VV }, // 1063 |
20221 | | { PseudoVDIV_VV_M1_E64, VDIV_VV }, // 1064 |
20222 | | { PseudoVDIV_VV_M1_E64_MASK, VDIV_VV }, // 1065 |
20223 | | { PseudoVDIV_VV_M1_E8, VDIV_VV }, // 1066 |
20224 | | { PseudoVDIV_VV_M1_E8_MASK, VDIV_VV }, // 1067 |
20225 | | { PseudoVDIV_VV_M2_E16, VDIV_VV }, // 1068 |
20226 | | { PseudoVDIV_VV_M2_E16_MASK, VDIV_VV }, // 1069 |
20227 | | { PseudoVDIV_VV_M2_E32, VDIV_VV }, // 1070 |
20228 | | { PseudoVDIV_VV_M2_E32_MASK, VDIV_VV }, // 1071 |
20229 | | { PseudoVDIV_VV_M2_E64, VDIV_VV }, // 1072 |
20230 | | { PseudoVDIV_VV_M2_E64_MASK, VDIV_VV }, // 1073 |
20231 | | { PseudoVDIV_VV_M2_E8, VDIV_VV }, // 1074 |
20232 | | { PseudoVDIV_VV_M2_E8_MASK, VDIV_VV }, // 1075 |
20233 | | { PseudoVDIV_VV_M4_E16, VDIV_VV }, // 1076 |
20234 | | { PseudoVDIV_VV_M4_E16_MASK, VDIV_VV }, // 1077 |
20235 | | { PseudoVDIV_VV_M4_E32, VDIV_VV }, // 1078 |
20236 | | { PseudoVDIV_VV_M4_E32_MASK, VDIV_VV }, // 1079 |
20237 | | { PseudoVDIV_VV_M4_E64, VDIV_VV }, // 1080 |
20238 | | { PseudoVDIV_VV_M4_E64_MASK, VDIV_VV }, // 1081 |
20239 | | { PseudoVDIV_VV_M4_E8, VDIV_VV }, // 1082 |
20240 | | { PseudoVDIV_VV_M4_E8_MASK, VDIV_VV }, // 1083 |
20241 | | { PseudoVDIV_VV_M8_E16, VDIV_VV }, // 1084 |
20242 | | { PseudoVDIV_VV_M8_E16_MASK, VDIV_VV }, // 1085 |
20243 | | { PseudoVDIV_VV_M8_E32, VDIV_VV }, // 1086 |
20244 | | { PseudoVDIV_VV_M8_E32_MASK, VDIV_VV }, // 1087 |
20245 | | { PseudoVDIV_VV_M8_E64, VDIV_VV }, // 1088 |
20246 | | { PseudoVDIV_VV_M8_E64_MASK, VDIV_VV }, // 1089 |
20247 | | { PseudoVDIV_VV_M8_E8, VDIV_VV }, // 1090 |
20248 | | { PseudoVDIV_VV_M8_E8_MASK, VDIV_VV }, // 1091 |
20249 | | { PseudoVDIV_VV_MF2_E16, VDIV_VV }, // 1092 |
20250 | | { PseudoVDIV_VV_MF2_E16_MASK, VDIV_VV }, // 1093 |
20251 | | { PseudoVDIV_VV_MF2_E32, VDIV_VV }, // 1094 |
20252 | | { PseudoVDIV_VV_MF2_E32_MASK, VDIV_VV }, // 1095 |
20253 | | { PseudoVDIV_VV_MF2_E8, VDIV_VV }, // 1096 |
20254 | | { PseudoVDIV_VV_MF2_E8_MASK, VDIV_VV }, // 1097 |
20255 | | { PseudoVDIV_VV_MF4_E16, VDIV_VV }, // 1098 |
20256 | | { PseudoVDIV_VV_MF4_E16_MASK, VDIV_VV }, // 1099 |
20257 | | { PseudoVDIV_VV_MF4_E8, VDIV_VV }, // 1100 |
20258 | | { PseudoVDIV_VV_MF4_E8_MASK, VDIV_VV }, // 1101 |
20259 | | { PseudoVDIV_VV_MF8_E8, VDIV_VV }, // 1102 |
20260 | | { PseudoVDIV_VV_MF8_E8_MASK, VDIV_VV }, // 1103 |
20261 | | { PseudoVDIV_VX_M1_E16, VDIV_VX }, // 1104 |
20262 | | { PseudoVDIV_VX_M1_E16_MASK, VDIV_VX }, // 1105 |
20263 | | { PseudoVDIV_VX_M1_E32, VDIV_VX }, // 1106 |
20264 | | { PseudoVDIV_VX_M1_E32_MASK, VDIV_VX }, // 1107 |
20265 | | { PseudoVDIV_VX_M1_E64, VDIV_VX }, // 1108 |
20266 | | { PseudoVDIV_VX_M1_E64_MASK, VDIV_VX }, // 1109 |
20267 | | { PseudoVDIV_VX_M1_E8, VDIV_VX }, // 1110 |
20268 | | { PseudoVDIV_VX_M1_E8_MASK, VDIV_VX }, // 1111 |
20269 | | { PseudoVDIV_VX_M2_E16, VDIV_VX }, // 1112 |
20270 | | { PseudoVDIV_VX_M2_E16_MASK, VDIV_VX }, // 1113 |
20271 | | { PseudoVDIV_VX_M2_E32, VDIV_VX }, // 1114 |
20272 | | { PseudoVDIV_VX_M2_E32_MASK, VDIV_VX }, // 1115 |
20273 | | { PseudoVDIV_VX_M2_E64, VDIV_VX }, // 1116 |
20274 | | { PseudoVDIV_VX_M2_E64_MASK, VDIV_VX }, // 1117 |
20275 | | { PseudoVDIV_VX_M2_E8, VDIV_VX }, // 1118 |
20276 | | { PseudoVDIV_VX_M2_E8_MASK, VDIV_VX }, // 1119 |
20277 | | { PseudoVDIV_VX_M4_E16, VDIV_VX }, // 1120 |
20278 | | { PseudoVDIV_VX_M4_E16_MASK, VDIV_VX }, // 1121 |
20279 | | { PseudoVDIV_VX_M4_E32, VDIV_VX }, // 1122 |
20280 | | { PseudoVDIV_VX_M4_E32_MASK, VDIV_VX }, // 1123 |
20281 | | { PseudoVDIV_VX_M4_E64, VDIV_VX }, // 1124 |
20282 | | { PseudoVDIV_VX_M4_E64_MASK, VDIV_VX }, // 1125 |
20283 | | { PseudoVDIV_VX_M4_E8, VDIV_VX }, // 1126 |
20284 | | { PseudoVDIV_VX_M4_E8_MASK, VDIV_VX }, // 1127 |
20285 | | { PseudoVDIV_VX_M8_E16, VDIV_VX }, // 1128 |
20286 | | { PseudoVDIV_VX_M8_E16_MASK, VDIV_VX }, // 1129 |
20287 | | { PseudoVDIV_VX_M8_E32, VDIV_VX }, // 1130 |
20288 | | { PseudoVDIV_VX_M8_E32_MASK, VDIV_VX }, // 1131 |
20289 | | { PseudoVDIV_VX_M8_E64, VDIV_VX }, // 1132 |
20290 | | { PseudoVDIV_VX_M8_E64_MASK, VDIV_VX }, // 1133 |
20291 | | { PseudoVDIV_VX_M8_E8, VDIV_VX }, // 1134 |
20292 | | { PseudoVDIV_VX_M8_E8_MASK, VDIV_VX }, // 1135 |
20293 | | { PseudoVDIV_VX_MF2_E16, VDIV_VX }, // 1136 |
20294 | | { PseudoVDIV_VX_MF2_E16_MASK, VDIV_VX }, // 1137 |
20295 | | { PseudoVDIV_VX_MF2_E32, VDIV_VX }, // 1138 |
20296 | | { PseudoVDIV_VX_MF2_E32_MASK, VDIV_VX }, // 1139 |
20297 | | { PseudoVDIV_VX_MF2_E8, VDIV_VX }, // 1140 |
20298 | | { PseudoVDIV_VX_MF2_E8_MASK, VDIV_VX }, // 1141 |
20299 | | { PseudoVDIV_VX_MF4_E16, VDIV_VX }, // 1142 |
20300 | | { PseudoVDIV_VX_MF4_E16_MASK, VDIV_VX }, // 1143 |
20301 | | { PseudoVDIV_VX_MF4_E8, VDIV_VX }, // 1144 |
20302 | | { PseudoVDIV_VX_MF4_E8_MASK, VDIV_VX }, // 1145 |
20303 | | { PseudoVDIV_VX_MF8_E8, VDIV_VX }, // 1146 |
20304 | | { PseudoVDIV_VX_MF8_E8_MASK, VDIV_VX }, // 1147 |
20305 | | { PseudoVFADD_VFPR16_M1, VFADD_VF }, // 1148 |
20306 | | { PseudoVFADD_VFPR16_M1_MASK, VFADD_VF }, // 1149 |
20307 | | { PseudoVFADD_VFPR16_M2, VFADD_VF }, // 1150 |
20308 | | { PseudoVFADD_VFPR16_M2_MASK, VFADD_VF }, // 1151 |
20309 | | { PseudoVFADD_VFPR16_M4, VFADD_VF }, // 1152 |
20310 | | { PseudoVFADD_VFPR16_M4_MASK, VFADD_VF }, // 1153 |
20311 | | { PseudoVFADD_VFPR16_M8, VFADD_VF }, // 1154 |
20312 | | { PseudoVFADD_VFPR16_M8_MASK, VFADD_VF }, // 1155 |
20313 | | { PseudoVFADD_VFPR16_MF2, VFADD_VF }, // 1156 |
20314 | | { PseudoVFADD_VFPR16_MF2_MASK, VFADD_VF }, // 1157 |
20315 | | { PseudoVFADD_VFPR16_MF4, VFADD_VF }, // 1158 |
20316 | | { PseudoVFADD_VFPR16_MF4_MASK, VFADD_VF }, // 1159 |
20317 | | { PseudoVFADD_VFPR32_M1, VFADD_VF }, // 1160 |
20318 | | { PseudoVFADD_VFPR32_M1_MASK, VFADD_VF }, // 1161 |
20319 | | { PseudoVFADD_VFPR32_M2, VFADD_VF }, // 1162 |
20320 | | { PseudoVFADD_VFPR32_M2_MASK, VFADD_VF }, // 1163 |
20321 | | { PseudoVFADD_VFPR32_M4, VFADD_VF }, // 1164 |
20322 | | { PseudoVFADD_VFPR32_M4_MASK, VFADD_VF }, // 1165 |
20323 | | { PseudoVFADD_VFPR32_M8, VFADD_VF }, // 1166 |
20324 | | { PseudoVFADD_VFPR32_M8_MASK, VFADD_VF }, // 1167 |
20325 | | { PseudoVFADD_VFPR32_MF2, VFADD_VF }, // 1168 |
20326 | | { PseudoVFADD_VFPR32_MF2_MASK, VFADD_VF }, // 1169 |
20327 | | { PseudoVFADD_VFPR64_M1, VFADD_VF }, // 1170 |
20328 | | { PseudoVFADD_VFPR64_M1_MASK, VFADD_VF }, // 1171 |
20329 | | { PseudoVFADD_VFPR64_M2, VFADD_VF }, // 1172 |
20330 | | { PseudoVFADD_VFPR64_M2_MASK, VFADD_VF }, // 1173 |
20331 | | { PseudoVFADD_VFPR64_M4, VFADD_VF }, // 1174 |
20332 | | { PseudoVFADD_VFPR64_M4_MASK, VFADD_VF }, // 1175 |
20333 | | { PseudoVFADD_VFPR64_M8, VFADD_VF }, // 1176 |
20334 | | { PseudoVFADD_VFPR64_M8_MASK, VFADD_VF }, // 1177 |
20335 | | { PseudoVFADD_VV_M1, VFADD_VV }, // 1178 |
20336 | | { PseudoVFADD_VV_M1_MASK, VFADD_VV }, // 1179 |
20337 | | { PseudoVFADD_VV_M2, VFADD_VV }, // 1180 |
20338 | | { PseudoVFADD_VV_M2_MASK, VFADD_VV }, // 1181 |
20339 | | { PseudoVFADD_VV_M4, VFADD_VV }, // 1182 |
20340 | | { PseudoVFADD_VV_M4_MASK, VFADD_VV }, // 1183 |
20341 | | { PseudoVFADD_VV_M8, VFADD_VV }, // 1184 |
20342 | | { PseudoVFADD_VV_M8_MASK, VFADD_VV }, // 1185 |
20343 | | { PseudoVFADD_VV_MF2, VFADD_VV }, // 1186 |
20344 | | { PseudoVFADD_VV_MF2_MASK, VFADD_VV }, // 1187 |
20345 | | { PseudoVFADD_VV_MF4, VFADD_VV }, // 1188 |
20346 | | { PseudoVFADD_VV_MF4_MASK, VFADD_VV }, // 1189 |
20347 | | { PseudoVFCLASS_V_M1, VFCLASS_V }, // 1190 |
20348 | | { PseudoVFCLASS_V_M1_MASK, VFCLASS_V }, // 1191 |
20349 | | { PseudoVFCLASS_V_M2, VFCLASS_V }, // 1192 |
20350 | | { PseudoVFCLASS_V_M2_MASK, VFCLASS_V }, // 1193 |
20351 | | { PseudoVFCLASS_V_M4, VFCLASS_V }, // 1194 |
20352 | | { PseudoVFCLASS_V_M4_MASK, VFCLASS_V }, // 1195 |
20353 | | { PseudoVFCLASS_V_M8, VFCLASS_V }, // 1196 |
20354 | | { PseudoVFCLASS_V_M8_MASK, VFCLASS_V }, // 1197 |
20355 | | { PseudoVFCLASS_V_MF2, VFCLASS_V }, // 1198 |
20356 | | { PseudoVFCLASS_V_MF2_MASK, VFCLASS_V }, // 1199 |
20357 | | { PseudoVFCLASS_V_MF4, VFCLASS_V }, // 1200 |
20358 | | { PseudoVFCLASS_V_MF4_MASK, VFCLASS_V }, // 1201 |
20359 | | { PseudoVFCVT_F_XU_V_M1, VFCVT_F_XU_V }, // 1202 |
20360 | | { PseudoVFCVT_F_XU_V_M1_MASK, VFCVT_F_XU_V }, // 1203 |
20361 | | { PseudoVFCVT_F_XU_V_M2, VFCVT_F_XU_V }, // 1204 |
20362 | | { PseudoVFCVT_F_XU_V_M2_MASK, VFCVT_F_XU_V }, // 1205 |
20363 | | { PseudoVFCVT_F_XU_V_M4, VFCVT_F_XU_V }, // 1206 |
20364 | | { PseudoVFCVT_F_XU_V_M4_MASK, VFCVT_F_XU_V }, // 1207 |
20365 | | { PseudoVFCVT_F_XU_V_M8, VFCVT_F_XU_V }, // 1208 |
20366 | | { PseudoVFCVT_F_XU_V_M8_MASK, VFCVT_F_XU_V }, // 1209 |
20367 | | { PseudoVFCVT_F_XU_V_MF2, VFCVT_F_XU_V }, // 1210 |
20368 | | { PseudoVFCVT_F_XU_V_MF2_MASK, VFCVT_F_XU_V }, // 1211 |
20369 | | { PseudoVFCVT_F_XU_V_MF4, VFCVT_F_XU_V }, // 1212 |
20370 | | { PseudoVFCVT_F_XU_V_MF4_MASK, VFCVT_F_XU_V }, // 1213 |
20371 | | { PseudoVFCVT_F_X_V_M1, VFCVT_F_X_V }, // 1214 |
20372 | | { PseudoVFCVT_F_X_V_M1_MASK, VFCVT_F_X_V }, // 1215 |
20373 | | { PseudoVFCVT_F_X_V_M2, VFCVT_F_X_V }, // 1216 |
20374 | | { PseudoVFCVT_F_X_V_M2_MASK, VFCVT_F_X_V }, // 1217 |
20375 | | { PseudoVFCVT_F_X_V_M4, VFCVT_F_X_V }, // 1218 |
20376 | | { PseudoVFCVT_F_X_V_M4_MASK, VFCVT_F_X_V }, // 1219 |
20377 | | { PseudoVFCVT_F_X_V_M8, VFCVT_F_X_V }, // 1220 |
20378 | | { PseudoVFCVT_F_X_V_M8_MASK, VFCVT_F_X_V }, // 1221 |
20379 | | { PseudoVFCVT_F_X_V_MF2, VFCVT_F_X_V }, // 1222 |
20380 | | { PseudoVFCVT_F_X_V_MF2_MASK, VFCVT_F_X_V }, // 1223 |
20381 | | { PseudoVFCVT_F_X_V_MF4, VFCVT_F_X_V }, // 1224 |
20382 | | { PseudoVFCVT_F_X_V_MF4_MASK, VFCVT_F_X_V }, // 1225 |
20383 | | { PseudoVFCVT_RM_F_XU_V_M1, VFCVT_F_XU_V }, // 1226 |
20384 | | { PseudoVFCVT_RM_F_XU_V_M1_MASK, VFCVT_F_XU_V }, // 1227 |
20385 | | { PseudoVFCVT_RM_F_XU_V_M2, VFCVT_F_XU_V }, // 1228 |
20386 | | { PseudoVFCVT_RM_F_XU_V_M2_MASK, VFCVT_F_XU_V }, // 1229 |
20387 | | { PseudoVFCVT_RM_F_XU_V_M4, VFCVT_F_XU_V }, // 1230 |
20388 | | { PseudoVFCVT_RM_F_XU_V_M4_MASK, VFCVT_F_XU_V }, // 1231 |
20389 | | { PseudoVFCVT_RM_F_XU_V_M8, VFCVT_F_XU_V }, // 1232 |
20390 | | { PseudoVFCVT_RM_F_XU_V_M8_MASK, VFCVT_F_XU_V }, // 1233 |
20391 | | { PseudoVFCVT_RM_F_XU_V_MF2, VFCVT_F_XU_V }, // 1234 |
20392 | | { PseudoVFCVT_RM_F_XU_V_MF2_MASK, VFCVT_F_XU_V }, // 1235 |
20393 | | { PseudoVFCVT_RM_F_XU_V_MF4, VFCVT_F_XU_V }, // 1236 |
20394 | | { PseudoVFCVT_RM_F_XU_V_MF4_MASK, VFCVT_F_XU_V }, // 1237 |
20395 | | { PseudoVFCVT_RM_F_X_V_M1, VFCVT_F_X_V }, // 1238 |
20396 | | { PseudoVFCVT_RM_F_X_V_M1_MASK, VFCVT_F_X_V }, // 1239 |
20397 | | { PseudoVFCVT_RM_F_X_V_M2, VFCVT_F_X_V }, // 1240 |
20398 | | { PseudoVFCVT_RM_F_X_V_M2_MASK, VFCVT_F_X_V }, // 1241 |
20399 | | { PseudoVFCVT_RM_F_X_V_M4, VFCVT_F_X_V }, // 1242 |
20400 | | { PseudoVFCVT_RM_F_X_V_M4_MASK, VFCVT_F_X_V }, // 1243 |
20401 | | { PseudoVFCVT_RM_F_X_V_M8, VFCVT_F_X_V }, // 1244 |
20402 | | { PseudoVFCVT_RM_F_X_V_M8_MASK, VFCVT_F_X_V }, // 1245 |
20403 | | { PseudoVFCVT_RM_F_X_V_MF2, VFCVT_F_X_V }, // 1246 |
20404 | | { PseudoVFCVT_RM_F_X_V_MF2_MASK, VFCVT_F_X_V }, // 1247 |
20405 | | { PseudoVFCVT_RM_F_X_V_MF4, VFCVT_F_X_V }, // 1248 |
20406 | | { PseudoVFCVT_RM_F_X_V_MF4_MASK, VFCVT_F_X_V }, // 1249 |
20407 | | { PseudoVFCVT_RM_XU_F_V_M1, VFCVT_XU_F_V }, // 1250 |
20408 | | { PseudoVFCVT_RM_XU_F_V_M1_MASK, VFCVT_XU_F_V }, // 1251 |
20409 | | { PseudoVFCVT_RM_XU_F_V_M2, VFCVT_XU_F_V }, // 1252 |
20410 | | { PseudoVFCVT_RM_XU_F_V_M2_MASK, VFCVT_XU_F_V }, // 1253 |
20411 | | { PseudoVFCVT_RM_XU_F_V_M4, VFCVT_XU_F_V }, // 1254 |
20412 | | { PseudoVFCVT_RM_XU_F_V_M4_MASK, VFCVT_XU_F_V }, // 1255 |
20413 | | { PseudoVFCVT_RM_XU_F_V_M8, VFCVT_XU_F_V }, // 1256 |
20414 | | { PseudoVFCVT_RM_XU_F_V_M8_MASK, VFCVT_XU_F_V }, // 1257 |
20415 | | { PseudoVFCVT_RM_XU_F_V_MF2, VFCVT_XU_F_V }, // 1258 |
20416 | | { PseudoVFCVT_RM_XU_F_V_MF2_MASK, VFCVT_XU_F_V }, // 1259 |
20417 | | { PseudoVFCVT_RM_XU_F_V_MF4, VFCVT_XU_F_V }, // 1260 |
20418 | | { PseudoVFCVT_RM_XU_F_V_MF4_MASK, VFCVT_XU_F_V }, // 1261 |
20419 | | { PseudoVFCVT_RM_X_F_V_M1, VFCVT_X_F_V }, // 1262 |
20420 | | { PseudoVFCVT_RM_X_F_V_M1_MASK, VFCVT_X_F_V }, // 1263 |
20421 | | { PseudoVFCVT_RM_X_F_V_M2, VFCVT_X_F_V }, // 1264 |
20422 | | { PseudoVFCVT_RM_X_F_V_M2_MASK, VFCVT_X_F_V }, // 1265 |
20423 | | { PseudoVFCVT_RM_X_F_V_M4, VFCVT_X_F_V }, // 1266 |
20424 | | { PseudoVFCVT_RM_X_F_V_M4_MASK, VFCVT_X_F_V }, // 1267 |
20425 | | { PseudoVFCVT_RM_X_F_V_M8, VFCVT_X_F_V }, // 1268 |
20426 | | { PseudoVFCVT_RM_X_F_V_M8_MASK, VFCVT_X_F_V }, // 1269 |
20427 | | { PseudoVFCVT_RM_X_F_V_MF2, VFCVT_X_F_V }, // 1270 |
20428 | | { PseudoVFCVT_RM_X_F_V_MF2_MASK, VFCVT_X_F_V }, // 1271 |
20429 | | { PseudoVFCVT_RM_X_F_V_MF4, VFCVT_X_F_V }, // 1272 |
20430 | | { PseudoVFCVT_RM_X_F_V_MF4_MASK, VFCVT_X_F_V }, // 1273 |
20431 | | { PseudoVFCVT_RTZ_XU_F_V_M1, VFCVT_RTZ_XU_F_V }, // 1274 |
20432 | | { PseudoVFCVT_RTZ_XU_F_V_M1_MASK, VFCVT_RTZ_XU_F_V }, // 1275 |
20433 | | { PseudoVFCVT_RTZ_XU_F_V_M2, VFCVT_RTZ_XU_F_V }, // 1276 |
20434 | | { PseudoVFCVT_RTZ_XU_F_V_M2_MASK, VFCVT_RTZ_XU_F_V }, // 1277 |
20435 | | { PseudoVFCVT_RTZ_XU_F_V_M4, VFCVT_RTZ_XU_F_V }, // 1278 |
20436 | | { PseudoVFCVT_RTZ_XU_F_V_M4_MASK, VFCVT_RTZ_XU_F_V }, // 1279 |
20437 | | { PseudoVFCVT_RTZ_XU_F_V_M8, VFCVT_RTZ_XU_F_V }, // 1280 |
20438 | | { PseudoVFCVT_RTZ_XU_F_V_M8_MASK, VFCVT_RTZ_XU_F_V }, // 1281 |
20439 | | { PseudoVFCVT_RTZ_XU_F_V_MF2, VFCVT_RTZ_XU_F_V }, // 1282 |
20440 | | { PseudoVFCVT_RTZ_XU_F_V_MF2_MASK, VFCVT_RTZ_XU_F_V }, // 1283 |
20441 | | { PseudoVFCVT_RTZ_XU_F_V_MF4, VFCVT_RTZ_XU_F_V }, // 1284 |
20442 | | { PseudoVFCVT_RTZ_XU_F_V_MF4_MASK, VFCVT_RTZ_XU_F_V }, // 1285 |
20443 | | { PseudoVFCVT_RTZ_X_F_V_M1, VFCVT_RTZ_X_F_V }, // 1286 |
20444 | | { PseudoVFCVT_RTZ_X_F_V_M1_MASK, VFCVT_RTZ_X_F_V }, // 1287 |
20445 | | { PseudoVFCVT_RTZ_X_F_V_M2, VFCVT_RTZ_X_F_V }, // 1288 |
20446 | | { PseudoVFCVT_RTZ_X_F_V_M2_MASK, VFCVT_RTZ_X_F_V }, // 1289 |
20447 | | { PseudoVFCVT_RTZ_X_F_V_M4, VFCVT_RTZ_X_F_V }, // 1290 |
20448 | | { PseudoVFCVT_RTZ_X_F_V_M4_MASK, VFCVT_RTZ_X_F_V }, // 1291 |
20449 | | { PseudoVFCVT_RTZ_X_F_V_M8, VFCVT_RTZ_X_F_V }, // 1292 |
20450 | | { PseudoVFCVT_RTZ_X_F_V_M8_MASK, VFCVT_RTZ_X_F_V }, // 1293 |
20451 | | { PseudoVFCVT_RTZ_X_F_V_MF2, VFCVT_RTZ_X_F_V }, // 1294 |
20452 | | { PseudoVFCVT_RTZ_X_F_V_MF2_MASK, VFCVT_RTZ_X_F_V }, // 1295 |
20453 | | { PseudoVFCVT_RTZ_X_F_V_MF4, VFCVT_RTZ_X_F_V }, // 1296 |
20454 | | { PseudoVFCVT_RTZ_X_F_V_MF4_MASK, VFCVT_RTZ_X_F_V }, // 1297 |
20455 | | { PseudoVFCVT_XU_F_V_M1, VFCVT_XU_F_V }, // 1298 |
20456 | | { PseudoVFCVT_XU_F_V_M1_MASK, VFCVT_XU_F_V }, // 1299 |
20457 | | { PseudoVFCVT_XU_F_V_M2, VFCVT_XU_F_V }, // 1300 |
20458 | | { PseudoVFCVT_XU_F_V_M2_MASK, VFCVT_XU_F_V }, // 1301 |
20459 | | { PseudoVFCVT_XU_F_V_M4, VFCVT_XU_F_V }, // 1302 |
20460 | | { PseudoVFCVT_XU_F_V_M4_MASK, VFCVT_XU_F_V }, // 1303 |
20461 | | { PseudoVFCVT_XU_F_V_M8, VFCVT_XU_F_V }, // 1304 |
20462 | | { PseudoVFCVT_XU_F_V_M8_MASK, VFCVT_XU_F_V }, // 1305 |
20463 | | { PseudoVFCVT_XU_F_V_MF2, VFCVT_XU_F_V }, // 1306 |
20464 | | { PseudoVFCVT_XU_F_V_MF2_MASK, VFCVT_XU_F_V }, // 1307 |
20465 | | { PseudoVFCVT_XU_F_V_MF4, VFCVT_XU_F_V }, // 1308 |
20466 | | { PseudoVFCVT_XU_F_V_MF4_MASK, VFCVT_XU_F_V }, // 1309 |
20467 | | { PseudoVFCVT_X_F_V_M1, VFCVT_X_F_V }, // 1310 |
20468 | | { PseudoVFCVT_X_F_V_M1_MASK, VFCVT_X_F_V }, // 1311 |
20469 | | { PseudoVFCVT_X_F_V_M2, VFCVT_X_F_V }, // 1312 |
20470 | | { PseudoVFCVT_X_F_V_M2_MASK, VFCVT_X_F_V }, // 1313 |
20471 | | { PseudoVFCVT_X_F_V_M4, VFCVT_X_F_V }, // 1314 |
20472 | | { PseudoVFCVT_X_F_V_M4_MASK, VFCVT_X_F_V }, // 1315 |
20473 | | { PseudoVFCVT_X_F_V_M8, VFCVT_X_F_V }, // 1316 |
20474 | | { PseudoVFCVT_X_F_V_M8_MASK, VFCVT_X_F_V }, // 1317 |
20475 | | { PseudoVFCVT_X_F_V_MF2, VFCVT_X_F_V }, // 1318 |
20476 | | { PseudoVFCVT_X_F_V_MF2_MASK, VFCVT_X_F_V }, // 1319 |
20477 | | { PseudoVFCVT_X_F_V_MF4, VFCVT_X_F_V }, // 1320 |
20478 | | { PseudoVFCVT_X_F_V_MF4_MASK, VFCVT_X_F_V }, // 1321 |
20479 | | { PseudoVFDIV_VFPR16_M1_E16, VFDIV_VF }, // 1322 |
20480 | | { PseudoVFDIV_VFPR16_M1_E16_MASK, VFDIV_VF }, // 1323 |
20481 | | { PseudoVFDIV_VFPR16_M2_E16, VFDIV_VF }, // 1324 |
20482 | | { PseudoVFDIV_VFPR16_M2_E16_MASK, VFDIV_VF }, // 1325 |
20483 | | { PseudoVFDIV_VFPR16_M4_E16, VFDIV_VF }, // 1326 |
20484 | | { PseudoVFDIV_VFPR16_M4_E16_MASK, VFDIV_VF }, // 1327 |
20485 | | { PseudoVFDIV_VFPR16_M8_E16, VFDIV_VF }, // 1328 |
20486 | | { PseudoVFDIV_VFPR16_M8_E16_MASK, VFDIV_VF }, // 1329 |
20487 | | { PseudoVFDIV_VFPR16_MF2_E16, VFDIV_VF }, // 1330 |
20488 | | { PseudoVFDIV_VFPR16_MF2_E16_MASK, VFDIV_VF }, // 1331 |
20489 | | { PseudoVFDIV_VFPR16_MF4_E16, VFDIV_VF }, // 1332 |
20490 | | { PseudoVFDIV_VFPR16_MF4_E16_MASK, VFDIV_VF }, // 1333 |
20491 | | { PseudoVFDIV_VFPR32_M1_E32, VFDIV_VF }, // 1334 |
20492 | | { PseudoVFDIV_VFPR32_M1_E32_MASK, VFDIV_VF }, // 1335 |
20493 | | { PseudoVFDIV_VFPR32_M2_E32, VFDIV_VF }, // 1336 |
20494 | | { PseudoVFDIV_VFPR32_M2_E32_MASK, VFDIV_VF }, // 1337 |
20495 | | { PseudoVFDIV_VFPR32_M4_E32, VFDIV_VF }, // 1338 |
20496 | | { PseudoVFDIV_VFPR32_M4_E32_MASK, VFDIV_VF }, // 1339 |
20497 | | { PseudoVFDIV_VFPR32_M8_E32, VFDIV_VF }, // 1340 |
20498 | | { PseudoVFDIV_VFPR32_M8_E32_MASK, VFDIV_VF }, // 1341 |
20499 | | { PseudoVFDIV_VFPR32_MF2_E32, VFDIV_VF }, // 1342 |
20500 | | { PseudoVFDIV_VFPR32_MF2_E32_MASK, VFDIV_VF }, // 1343 |
20501 | | { PseudoVFDIV_VFPR64_M1_E64, VFDIV_VF }, // 1344 |
20502 | | { PseudoVFDIV_VFPR64_M1_E64_MASK, VFDIV_VF }, // 1345 |
20503 | | { PseudoVFDIV_VFPR64_M2_E64, VFDIV_VF }, // 1346 |
20504 | | { PseudoVFDIV_VFPR64_M2_E64_MASK, VFDIV_VF }, // 1347 |
20505 | | { PseudoVFDIV_VFPR64_M4_E64, VFDIV_VF }, // 1348 |
20506 | | { PseudoVFDIV_VFPR64_M4_E64_MASK, VFDIV_VF }, // 1349 |
20507 | | { PseudoVFDIV_VFPR64_M8_E64, VFDIV_VF }, // 1350 |
20508 | | { PseudoVFDIV_VFPR64_M8_E64_MASK, VFDIV_VF }, // 1351 |
20509 | | { PseudoVFDIV_VV_M1_E16, VFDIV_VV }, // 1352 |
20510 | | { PseudoVFDIV_VV_M1_E16_MASK, VFDIV_VV }, // 1353 |
20511 | | { PseudoVFDIV_VV_M1_E32, VFDIV_VV }, // 1354 |
20512 | | { PseudoVFDIV_VV_M1_E32_MASK, VFDIV_VV }, // 1355 |
20513 | | { PseudoVFDIV_VV_M1_E64, VFDIV_VV }, // 1356 |
20514 | | { PseudoVFDIV_VV_M1_E64_MASK, VFDIV_VV }, // 1357 |
20515 | | { PseudoVFDIV_VV_M2_E16, VFDIV_VV }, // 1358 |
20516 | | { PseudoVFDIV_VV_M2_E16_MASK, VFDIV_VV }, // 1359 |
20517 | | { PseudoVFDIV_VV_M2_E32, VFDIV_VV }, // 1360 |
20518 | | { PseudoVFDIV_VV_M2_E32_MASK, VFDIV_VV }, // 1361 |
20519 | | { PseudoVFDIV_VV_M2_E64, VFDIV_VV }, // 1362 |
20520 | | { PseudoVFDIV_VV_M2_E64_MASK, VFDIV_VV }, // 1363 |
20521 | | { PseudoVFDIV_VV_M4_E16, VFDIV_VV }, // 1364 |
20522 | | { PseudoVFDIV_VV_M4_E16_MASK, VFDIV_VV }, // 1365 |
20523 | | { PseudoVFDIV_VV_M4_E32, VFDIV_VV }, // 1366 |
20524 | | { PseudoVFDIV_VV_M4_E32_MASK, VFDIV_VV }, // 1367 |
20525 | | { PseudoVFDIV_VV_M4_E64, VFDIV_VV }, // 1368 |
20526 | | { PseudoVFDIV_VV_M4_E64_MASK, VFDIV_VV }, // 1369 |
20527 | | { PseudoVFDIV_VV_M8_E16, VFDIV_VV }, // 1370 |
20528 | | { PseudoVFDIV_VV_M8_E16_MASK, VFDIV_VV }, // 1371 |
20529 | | { PseudoVFDIV_VV_M8_E32, VFDIV_VV }, // 1372 |
20530 | | { PseudoVFDIV_VV_M8_E32_MASK, VFDIV_VV }, // 1373 |
20531 | | { PseudoVFDIV_VV_M8_E64, VFDIV_VV }, // 1374 |
20532 | | { PseudoVFDIV_VV_M8_E64_MASK, VFDIV_VV }, // 1375 |
20533 | | { PseudoVFDIV_VV_MF2_E16, VFDIV_VV }, // 1376 |
20534 | | { PseudoVFDIV_VV_MF2_E16_MASK, VFDIV_VV }, // 1377 |
20535 | | { PseudoVFDIV_VV_MF2_E32, VFDIV_VV }, // 1378 |
20536 | | { PseudoVFDIV_VV_MF2_E32_MASK, VFDIV_VV }, // 1379 |
20537 | | { PseudoVFDIV_VV_MF4_E16, VFDIV_VV }, // 1380 |
20538 | | { PseudoVFDIV_VV_MF4_E16_MASK, VFDIV_VV }, // 1381 |
20539 | | { PseudoVFIRST_M_B1, VFIRST_M }, // 1382 |
20540 | | { PseudoVFIRST_M_B16, VFIRST_M }, // 1383 |
20541 | | { PseudoVFIRST_M_B16_MASK, VFIRST_M }, // 1384 |
20542 | | { PseudoVFIRST_M_B1_MASK, VFIRST_M }, // 1385 |
20543 | | { PseudoVFIRST_M_B2, VFIRST_M }, // 1386 |
20544 | | { PseudoVFIRST_M_B2_MASK, VFIRST_M }, // 1387 |
20545 | | { PseudoVFIRST_M_B32, VFIRST_M }, // 1388 |
20546 | | { PseudoVFIRST_M_B32_MASK, VFIRST_M }, // 1389 |
20547 | | { PseudoVFIRST_M_B4, VFIRST_M }, // 1390 |
20548 | | { PseudoVFIRST_M_B4_MASK, VFIRST_M }, // 1391 |
20549 | | { PseudoVFIRST_M_B64, VFIRST_M }, // 1392 |
20550 | | { PseudoVFIRST_M_B64_MASK, VFIRST_M }, // 1393 |
20551 | | { PseudoVFIRST_M_B8, VFIRST_M }, // 1394 |
20552 | | { PseudoVFIRST_M_B8_MASK, VFIRST_M }, // 1395 |
20553 | | { PseudoVFMACC_VFPR16_M1, VFMACC_VF }, // 1396 |
20554 | | { PseudoVFMACC_VFPR16_M1_MASK, VFMACC_VF }, // 1397 |
20555 | | { PseudoVFMACC_VFPR16_M2, VFMACC_VF }, // 1398 |
20556 | | { PseudoVFMACC_VFPR16_M2_MASK, VFMACC_VF }, // 1399 |
20557 | | { PseudoVFMACC_VFPR16_M4, VFMACC_VF }, // 1400 |
20558 | | { PseudoVFMACC_VFPR16_M4_MASK, VFMACC_VF }, // 1401 |
20559 | | { PseudoVFMACC_VFPR16_M8, VFMACC_VF }, // 1402 |
20560 | | { PseudoVFMACC_VFPR16_M8_MASK, VFMACC_VF }, // 1403 |
20561 | | { PseudoVFMACC_VFPR16_MF2, VFMACC_VF }, // 1404 |
20562 | | { PseudoVFMACC_VFPR16_MF2_MASK, VFMACC_VF }, // 1405 |
20563 | | { PseudoVFMACC_VFPR16_MF4, VFMACC_VF }, // 1406 |
20564 | | { PseudoVFMACC_VFPR16_MF4_MASK, VFMACC_VF }, // 1407 |
20565 | | { PseudoVFMACC_VFPR32_M1, VFMACC_VF }, // 1408 |
20566 | | { PseudoVFMACC_VFPR32_M1_MASK, VFMACC_VF }, // 1409 |
20567 | | { PseudoVFMACC_VFPR32_M2, VFMACC_VF }, // 1410 |
20568 | | { PseudoVFMACC_VFPR32_M2_MASK, VFMACC_VF }, // 1411 |
20569 | | { PseudoVFMACC_VFPR32_M4, VFMACC_VF }, // 1412 |
20570 | | { PseudoVFMACC_VFPR32_M4_MASK, VFMACC_VF }, // 1413 |
20571 | | { PseudoVFMACC_VFPR32_M8, VFMACC_VF }, // 1414 |
20572 | | { PseudoVFMACC_VFPR32_M8_MASK, VFMACC_VF }, // 1415 |
20573 | | { PseudoVFMACC_VFPR32_MF2, VFMACC_VF }, // 1416 |
20574 | | { PseudoVFMACC_VFPR32_MF2_MASK, VFMACC_VF }, // 1417 |
20575 | | { PseudoVFMACC_VFPR64_M1, VFMACC_VF }, // 1418 |
20576 | | { PseudoVFMACC_VFPR64_M1_MASK, VFMACC_VF }, // 1419 |
20577 | | { PseudoVFMACC_VFPR64_M2, VFMACC_VF }, // 1420 |
20578 | | { PseudoVFMACC_VFPR64_M2_MASK, VFMACC_VF }, // 1421 |
20579 | | { PseudoVFMACC_VFPR64_M4, VFMACC_VF }, // 1422 |
20580 | | { PseudoVFMACC_VFPR64_M4_MASK, VFMACC_VF }, // 1423 |
20581 | | { PseudoVFMACC_VFPR64_M8, VFMACC_VF }, // 1424 |
20582 | | { PseudoVFMACC_VFPR64_M8_MASK, VFMACC_VF }, // 1425 |
20583 | | { PseudoVFMACC_VV_M1, VFMACC_VV }, // 1426 |
20584 | | { PseudoVFMACC_VV_M1_MASK, VFMACC_VV }, // 1427 |
20585 | | { PseudoVFMACC_VV_M2, VFMACC_VV }, // 1428 |
20586 | | { PseudoVFMACC_VV_M2_MASK, VFMACC_VV }, // 1429 |
20587 | | { PseudoVFMACC_VV_M4, VFMACC_VV }, // 1430 |
20588 | | { PseudoVFMACC_VV_M4_MASK, VFMACC_VV }, // 1431 |
20589 | | { PseudoVFMACC_VV_M8, VFMACC_VV }, // 1432 |
20590 | | { PseudoVFMACC_VV_M8_MASK, VFMACC_VV }, // 1433 |
20591 | | { PseudoVFMACC_VV_MF2, VFMACC_VV }, // 1434 |
20592 | | { PseudoVFMACC_VV_MF2_MASK, VFMACC_VV }, // 1435 |
20593 | | { PseudoVFMACC_VV_MF4, VFMACC_VV }, // 1436 |
20594 | | { PseudoVFMACC_VV_MF4_MASK, VFMACC_VV }, // 1437 |
20595 | | { PseudoVFMADD_VFPR16_M1, VFMADD_VF }, // 1438 |
20596 | | { PseudoVFMADD_VFPR16_M1_MASK, VFMADD_VF }, // 1439 |
20597 | | { PseudoVFMADD_VFPR16_M2, VFMADD_VF }, // 1440 |
20598 | | { PseudoVFMADD_VFPR16_M2_MASK, VFMADD_VF }, // 1441 |
20599 | | { PseudoVFMADD_VFPR16_M4, VFMADD_VF }, // 1442 |
20600 | | { PseudoVFMADD_VFPR16_M4_MASK, VFMADD_VF }, // 1443 |
20601 | | { PseudoVFMADD_VFPR16_M8, VFMADD_VF }, // 1444 |
20602 | | { PseudoVFMADD_VFPR16_M8_MASK, VFMADD_VF }, // 1445 |
20603 | | { PseudoVFMADD_VFPR16_MF2, VFMADD_VF }, // 1446 |
20604 | | { PseudoVFMADD_VFPR16_MF2_MASK, VFMADD_VF }, // 1447 |
20605 | | { PseudoVFMADD_VFPR16_MF4, VFMADD_VF }, // 1448 |
20606 | | { PseudoVFMADD_VFPR16_MF4_MASK, VFMADD_VF }, // 1449 |
20607 | | { PseudoVFMADD_VFPR32_M1, VFMADD_VF }, // 1450 |
20608 | | { PseudoVFMADD_VFPR32_M1_MASK, VFMADD_VF }, // 1451 |
20609 | | { PseudoVFMADD_VFPR32_M2, VFMADD_VF }, // 1452 |
20610 | | { PseudoVFMADD_VFPR32_M2_MASK, VFMADD_VF }, // 1453 |
20611 | | { PseudoVFMADD_VFPR32_M4, VFMADD_VF }, // 1454 |
20612 | | { PseudoVFMADD_VFPR32_M4_MASK, VFMADD_VF }, // 1455 |
20613 | | { PseudoVFMADD_VFPR32_M8, VFMADD_VF }, // 1456 |
20614 | | { PseudoVFMADD_VFPR32_M8_MASK, VFMADD_VF }, // 1457 |
20615 | | { PseudoVFMADD_VFPR32_MF2, VFMADD_VF }, // 1458 |
20616 | | { PseudoVFMADD_VFPR32_MF2_MASK, VFMADD_VF }, // 1459 |
20617 | | { PseudoVFMADD_VFPR64_M1, VFMADD_VF }, // 1460 |
20618 | | { PseudoVFMADD_VFPR64_M1_MASK, VFMADD_VF }, // 1461 |
20619 | | { PseudoVFMADD_VFPR64_M2, VFMADD_VF }, // 1462 |
20620 | | { PseudoVFMADD_VFPR64_M2_MASK, VFMADD_VF }, // 1463 |
20621 | | { PseudoVFMADD_VFPR64_M4, VFMADD_VF }, // 1464 |
20622 | | { PseudoVFMADD_VFPR64_M4_MASK, VFMADD_VF }, // 1465 |
20623 | | { PseudoVFMADD_VFPR64_M8, VFMADD_VF }, // 1466 |
20624 | | { PseudoVFMADD_VFPR64_M8_MASK, VFMADD_VF }, // 1467 |
20625 | | { PseudoVFMADD_VV_M1, VFMADD_VV }, // 1468 |
20626 | | { PseudoVFMADD_VV_M1_MASK, VFMADD_VV }, // 1469 |
20627 | | { PseudoVFMADD_VV_M2, VFMADD_VV }, // 1470 |
20628 | | { PseudoVFMADD_VV_M2_MASK, VFMADD_VV }, // 1471 |
20629 | | { PseudoVFMADD_VV_M4, VFMADD_VV }, // 1472 |
20630 | | { PseudoVFMADD_VV_M4_MASK, VFMADD_VV }, // 1473 |
20631 | | { PseudoVFMADD_VV_M8, VFMADD_VV }, // 1474 |
20632 | | { PseudoVFMADD_VV_M8_MASK, VFMADD_VV }, // 1475 |
20633 | | { PseudoVFMADD_VV_MF2, VFMADD_VV }, // 1476 |
20634 | | { PseudoVFMADD_VV_MF2_MASK, VFMADD_VV }, // 1477 |
20635 | | { PseudoVFMADD_VV_MF4, VFMADD_VV }, // 1478 |
20636 | | { PseudoVFMADD_VV_MF4_MASK, VFMADD_VV }, // 1479 |
20637 | | { PseudoVFMAX_VFPR16_M1, VFMAX_VF }, // 1480 |
20638 | | { PseudoVFMAX_VFPR16_M1_MASK, VFMAX_VF }, // 1481 |
20639 | | { PseudoVFMAX_VFPR16_M2, VFMAX_VF }, // 1482 |
20640 | | { PseudoVFMAX_VFPR16_M2_MASK, VFMAX_VF }, // 1483 |
20641 | | { PseudoVFMAX_VFPR16_M4, VFMAX_VF }, // 1484 |
20642 | | { PseudoVFMAX_VFPR16_M4_MASK, VFMAX_VF }, // 1485 |
20643 | | { PseudoVFMAX_VFPR16_M8, VFMAX_VF }, // 1486 |
20644 | | { PseudoVFMAX_VFPR16_M8_MASK, VFMAX_VF }, // 1487 |
20645 | | { PseudoVFMAX_VFPR16_MF2, VFMAX_VF }, // 1488 |
20646 | | { PseudoVFMAX_VFPR16_MF2_MASK, VFMAX_VF }, // 1489 |
20647 | | { PseudoVFMAX_VFPR16_MF4, VFMAX_VF }, // 1490 |
20648 | | { PseudoVFMAX_VFPR16_MF4_MASK, VFMAX_VF }, // 1491 |
20649 | | { PseudoVFMAX_VFPR32_M1, VFMAX_VF }, // 1492 |
20650 | | { PseudoVFMAX_VFPR32_M1_MASK, VFMAX_VF }, // 1493 |
20651 | | { PseudoVFMAX_VFPR32_M2, VFMAX_VF }, // 1494 |
20652 | | { PseudoVFMAX_VFPR32_M2_MASK, VFMAX_VF }, // 1495 |
20653 | | { PseudoVFMAX_VFPR32_M4, VFMAX_VF }, // 1496 |
20654 | | { PseudoVFMAX_VFPR32_M4_MASK, VFMAX_VF }, // 1497 |
20655 | | { PseudoVFMAX_VFPR32_M8, VFMAX_VF }, // 1498 |
20656 | | { PseudoVFMAX_VFPR32_M8_MASK, VFMAX_VF }, // 1499 |
20657 | | { PseudoVFMAX_VFPR32_MF2, VFMAX_VF }, // 1500 |
20658 | | { PseudoVFMAX_VFPR32_MF2_MASK, VFMAX_VF }, // 1501 |
20659 | | { PseudoVFMAX_VFPR64_M1, VFMAX_VF }, // 1502 |
20660 | | { PseudoVFMAX_VFPR64_M1_MASK, VFMAX_VF }, // 1503 |
20661 | | { PseudoVFMAX_VFPR64_M2, VFMAX_VF }, // 1504 |
20662 | | { PseudoVFMAX_VFPR64_M2_MASK, VFMAX_VF }, // 1505 |
20663 | | { PseudoVFMAX_VFPR64_M4, VFMAX_VF }, // 1506 |
20664 | | { PseudoVFMAX_VFPR64_M4_MASK, VFMAX_VF }, // 1507 |
20665 | | { PseudoVFMAX_VFPR64_M8, VFMAX_VF }, // 1508 |
20666 | | { PseudoVFMAX_VFPR64_M8_MASK, VFMAX_VF }, // 1509 |
20667 | | { PseudoVFMAX_VV_M1, VFMAX_VV }, // 1510 |
20668 | | { PseudoVFMAX_VV_M1_MASK, VFMAX_VV }, // 1511 |
20669 | | { PseudoVFMAX_VV_M2, VFMAX_VV }, // 1512 |
20670 | | { PseudoVFMAX_VV_M2_MASK, VFMAX_VV }, // 1513 |
20671 | | { PseudoVFMAX_VV_M4, VFMAX_VV }, // 1514 |
20672 | | { PseudoVFMAX_VV_M4_MASK, VFMAX_VV }, // 1515 |
20673 | | { PseudoVFMAX_VV_M8, VFMAX_VV }, // 1516 |
20674 | | { PseudoVFMAX_VV_M8_MASK, VFMAX_VV }, // 1517 |
20675 | | { PseudoVFMAX_VV_MF2, VFMAX_VV }, // 1518 |
20676 | | { PseudoVFMAX_VV_MF2_MASK, VFMAX_VV }, // 1519 |
20677 | | { PseudoVFMAX_VV_MF4, VFMAX_VV }, // 1520 |
20678 | | { PseudoVFMAX_VV_MF4_MASK, VFMAX_VV }, // 1521 |
20679 | | { PseudoVFMERGE_VFPR16M_M1, VFMERGE_VFM }, // 1522 |
20680 | | { PseudoVFMERGE_VFPR16M_M2, VFMERGE_VFM }, // 1523 |
20681 | | { PseudoVFMERGE_VFPR16M_M4, VFMERGE_VFM }, // 1524 |
20682 | | { PseudoVFMERGE_VFPR16M_M8, VFMERGE_VFM }, // 1525 |
20683 | | { PseudoVFMERGE_VFPR16M_MF2, VFMERGE_VFM }, // 1526 |
20684 | | { PseudoVFMERGE_VFPR16M_MF4, VFMERGE_VFM }, // 1527 |
20685 | | { PseudoVFMERGE_VFPR32M_M1, VFMERGE_VFM }, // 1528 |
20686 | | { PseudoVFMERGE_VFPR32M_M2, VFMERGE_VFM }, // 1529 |
20687 | | { PseudoVFMERGE_VFPR32M_M4, VFMERGE_VFM }, // 1530 |
20688 | | { PseudoVFMERGE_VFPR32M_M8, VFMERGE_VFM }, // 1531 |
20689 | | { PseudoVFMERGE_VFPR32M_MF2, VFMERGE_VFM }, // 1532 |
20690 | | { PseudoVFMERGE_VFPR64M_M1, VFMERGE_VFM }, // 1533 |
20691 | | { PseudoVFMERGE_VFPR64M_M2, VFMERGE_VFM }, // 1534 |
20692 | | { PseudoVFMERGE_VFPR64M_M4, VFMERGE_VFM }, // 1535 |
20693 | | { PseudoVFMERGE_VFPR64M_M8, VFMERGE_VFM }, // 1536 |
20694 | | { PseudoVFMIN_VFPR16_M1, VFMIN_VF }, // 1537 |
20695 | | { PseudoVFMIN_VFPR16_M1_MASK, VFMIN_VF }, // 1538 |
20696 | | { PseudoVFMIN_VFPR16_M2, VFMIN_VF }, // 1539 |
20697 | | { PseudoVFMIN_VFPR16_M2_MASK, VFMIN_VF }, // 1540 |
20698 | | { PseudoVFMIN_VFPR16_M4, VFMIN_VF }, // 1541 |
20699 | | { PseudoVFMIN_VFPR16_M4_MASK, VFMIN_VF }, // 1542 |
20700 | | { PseudoVFMIN_VFPR16_M8, VFMIN_VF }, // 1543 |
20701 | | { PseudoVFMIN_VFPR16_M8_MASK, VFMIN_VF }, // 1544 |
20702 | | { PseudoVFMIN_VFPR16_MF2, VFMIN_VF }, // 1545 |
20703 | | { PseudoVFMIN_VFPR16_MF2_MASK, VFMIN_VF }, // 1546 |
20704 | | { PseudoVFMIN_VFPR16_MF4, VFMIN_VF }, // 1547 |
20705 | | { PseudoVFMIN_VFPR16_MF4_MASK, VFMIN_VF }, // 1548 |
20706 | | { PseudoVFMIN_VFPR32_M1, VFMIN_VF }, // 1549 |
20707 | | { PseudoVFMIN_VFPR32_M1_MASK, VFMIN_VF }, // 1550 |
20708 | | { PseudoVFMIN_VFPR32_M2, VFMIN_VF }, // 1551 |
20709 | | { PseudoVFMIN_VFPR32_M2_MASK, VFMIN_VF }, // 1552 |
20710 | | { PseudoVFMIN_VFPR32_M4, VFMIN_VF }, // 1553 |
20711 | | { PseudoVFMIN_VFPR32_M4_MASK, VFMIN_VF }, // 1554 |
20712 | | { PseudoVFMIN_VFPR32_M8, VFMIN_VF }, // 1555 |
20713 | | { PseudoVFMIN_VFPR32_M8_MASK, VFMIN_VF }, // 1556 |
20714 | | { PseudoVFMIN_VFPR32_MF2, VFMIN_VF }, // 1557 |
20715 | | { PseudoVFMIN_VFPR32_MF2_MASK, VFMIN_VF }, // 1558 |
20716 | | { PseudoVFMIN_VFPR64_M1, VFMIN_VF }, // 1559 |
20717 | | { PseudoVFMIN_VFPR64_M1_MASK, VFMIN_VF }, // 1560 |
20718 | | { PseudoVFMIN_VFPR64_M2, VFMIN_VF }, // 1561 |
20719 | | { PseudoVFMIN_VFPR64_M2_MASK, VFMIN_VF }, // 1562 |
20720 | | { PseudoVFMIN_VFPR64_M4, VFMIN_VF }, // 1563 |
20721 | | { PseudoVFMIN_VFPR64_M4_MASK, VFMIN_VF }, // 1564 |
20722 | | { PseudoVFMIN_VFPR64_M8, VFMIN_VF }, // 1565 |
20723 | | { PseudoVFMIN_VFPR64_M8_MASK, VFMIN_VF }, // 1566 |
20724 | | { PseudoVFMIN_VV_M1, VFMIN_VV }, // 1567 |
20725 | | { PseudoVFMIN_VV_M1_MASK, VFMIN_VV }, // 1568 |
20726 | | { PseudoVFMIN_VV_M2, VFMIN_VV }, // 1569 |
20727 | | { PseudoVFMIN_VV_M2_MASK, VFMIN_VV }, // 1570 |
20728 | | { PseudoVFMIN_VV_M4, VFMIN_VV }, // 1571 |
20729 | | { PseudoVFMIN_VV_M4_MASK, VFMIN_VV }, // 1572 |
20730 | | { PseudoVFMIN_VV_M8, VFMIN_VV }, // 1573 |
20731 | | { PseudoVFMIN_VV_M8_MASK, VFMIN_VV }, // 1574 |
20732 | | { PseudoVFMIN_VV_MF2, VFMIN_VV }, // 1575 |
20733 | | { PseudoVFMIN_VV_MF2_MASK, VFMIN_VV }, // 1576 |
20734 | | { PseudoVFMIN_VV_MF4, VFMIN_VV }, // 1577 |
20735 | | { PseudoVFMIN_VV_MF4_MASK, VFMIN_VV }, // 1578 |
20736 | | { PseudoVFMSAC_VFPR16_M1, VFMSAC_VF }, // 1579 |
20737 | | { PseudoVFMSAC_VFPR16_M1_MASK, VFMSAC_VF }, // 1580 |
20738 | | { PseudoVFMSAC_VFPR16_M2, VFMSAC_VF }, // 1581 |
20739 | | { PseudoVFMSAC_VFPR16_M2_MASK, VFMSAC_VF }, // 1582 |
20740 | | { PseudoVFMSAC_VFPR16_M4, VFMSAC_VF }, // 1583 |
20741 | | { PseudoVFMSAC_VFPR16_M4_MASK, VFMSAC_VF }, // 1584 |
20742 | | { PseudoVFMSAC_VFPR16_M8, VFMSAC_VF }, // 1585 |
20743 | | { PseudoVFMSAC_VFPR16_M8_MASK, VFMSAC_VF }, // 1586 |
20744 | | { PseudoVFMSAC_VFPR16_MF2, VFMSAC_VF }, // 1587 |
20745 | | { PseudoVFMSAC_VFPR16_MF2_MASK, VFMSAC_VF }, // 1588 |
20746 | | { PseudoVFMSAC_VFPR16_MF4, VFMSAC_VF }, // 1589 |
20747 | | { PseudoVFMSAC_VFPR16_MF4_MASK, VFMSAC_VF }, // 1590 |
20748 | | { PseudoVFMSAC_VFPR32_M1, VFMSAC_VF }, // 1591 |
20749 | | { PseudoVFMSAC_VFPR32_M1_MASK, VFMSAC_VF }, // 1592 |
20750 | | { PseudoVFMSAC_VFPR32_M2, VFMSAC_VF }, // 1593 |
20751 | | { PseudoVFMSAC_VFPR32_M2_MASK, VFMSAC_VF }, // 1594 |
20752 | | { PseudoVFMSAC_VFPR32_M4, VFMSAC_VF }, // 1595 |
20753 | | { PseudoVFMSAC_VFPR32_M4_MASK, VFMSAC_VF }, // 1596 |
20754 | | { PseudoVFMSAC_VFPR32_M8, VFMSAC_VF }, // 1597 |
20755 | | { PseudoVFMSAC_VFPR32_M8_MASK, VFMSAC_VF }, // 1598 |
20756 | | { PseudoVFMSAC_VFPR32_MF2, VFMSAC_VF }, // 1599 |
20757 | | { PseudoVFMSAC_VFPR32_MF2_MASK, VFMSAC_VF }, // 1600 |
20758 | | { PseudoVFMSAC_VFPR64_M1, VFMSAC_VF }, // 1601 |
20759 | | { PseudoVFMSAC_VFPR64_M1_MASK, VFMSAC_VF }, // 1602 |
20760 | | { PseudoVFMSAC_VFPR64_M2, VFMSAC_VF }, // 1603 |
20761 | | { PseudoVFMSAC_VFPR64_M2_MASK, VFMSAC_VF }, // 1604 |
20762 | | { PseudoVFMSAC_VFPR64_M4, VFMSAC_VF }, // 1605 |
20763 | | { PseudoVFMSAC_VFPR64_M4_MASK, VFMSAC_VF }, // 1606 |
20764 | | { PseudoVFMSAC_VFPR64_M8, VFMSAC_VF }, // 1607 |
20765 | | { PseudoVFMSAC_VFPR64_M8_MASK, VFMSAC_VF }, // 1608 |
20766 | | { PseudoVFMSAC_VV_M1, VFMSAC_VV }, // 1609 |
20767 | | { PseudoVFMSAC_VV_M1_MASK, VFMSAC_VV }, // 1610 |
20768 | | { PseudoVFMSAC_VV_M2, VFMSAC_VV }, // 1611 |
20769 | | { PseudoVFMSAC_VV_M2_MASK, VFMSAC_VV }, // 1612 |
20770 | | { PseudoVFMSAC_VV_M4, VFMSAC_VV }, // 1613 |
20771 | | { PseudoVFMSAC_VV_M4_MASK, VFMSAC_VV }, // 1614 |
20772 | | { PseudoVFMSAC_VV_M8, VFMSAC_VV }, // 1615 |
20773 | | { PseudoVFMSAC_VV_M8_MASK, VFMSAC_VV }, // 1616 |
20774 | | { PseudoVFMSAC_VV_MF2, VFMSAC_VV }, // 1617 |
20775 | | { PseudoVFMSAC_VV_MF2_MASK, VFMSAC_VV }, // 1618 |
20776 | | { PseudoVFMSAC_VV_MF4, VFMSAC_VV }, // 1619 |
20777 | | { PseudoVFMSAC_VV_MF4_MASK, VFMSAC_VV }, // 1620 |
20778 | | { PseudoVFMSUB_VFPR16_M1, VFMSUB_VF }, // 1621 |
20779 | | { PseudoVFMSUB_VFPR16_M1_MASK, VFMSUB_VF }, // 1622 |
20780 | | { PseudoVFMSUB_VFPR16_M2, VFMSUB_VF }, // 1623 |
20781 | | { PseudoVFMSUB_VFPR16_M2_MASK, VFMSUB_VF }, // 1624 |
20782 | | { PseudoVFMSUB_VFPR16_M4, VFMSUB_VF }, // 1625 |
20783 | | { PseudoVFMSUB_VFPR16_M4_MASK, VFMSUB_VF }, // 1626 |
20784 | | { PseudoVFMSUB_VFPR16_M8, VFMSUB_VF }, // 1627 |
20785 | | { PseudoVFMSUB_VFPR16_M8_MASK, VFMSUB_VF }, // 1628 |
20786 | | { PseudoVFMSUB_VFPR16_MF2, VFMSUB_VF }, // 1629 |
20787 | | { PseudoVFMSUB_VFPR16_MF2_MASK, VFMSUB_VF }, // 1630 |
20788 | | { PseudoVFMSUB_VFPR16_MF4, VFMSUB_VF }, // 1631 |
20789 | | { PseudoVFMSUB_VFPR16_MF4_MASK, VFMSUB_VF }, // 1632 |
20790 | | { PseudoVFMSUB_VFPR32_M1, VFMSUB_VF }, // 1633 |
20791 | | { PseudoVFMSUB_VFPR32_M1_MASK, VFMSUB_VF }, // 1634 |
20792 | | { PseudoVFMSUB_VFPR32_M2, VFMSUB_VF }, // 1635 |
20793 | | { PseudoVFMSUB_VFPR32_M2_MASK, VFMSUB_VF }, // 1636 |
20794 | | { PseudoVFMSUB_VFPR32_M4, VFMSUB_VF }, // 1637 |
20795 | | { PseudoVFMSUB_VFPR32_M4_MASK, VFMSUB_VF }, // 1638 |
20796 | | { PseudoVFMSUB_VFPR32_M8, VFMSUB_VF }, // 1639 |
20797 | | { PseudoVFMSUB_VFPR32_M8_MASK, VFMSUB_VF }, // 1640 |
20798 | | { PseudoVFMSUB_VFPR32_MF2, VFMSUB_VF }, // 1641 |
20799 | | { PseudoVFMSUB_VFPR32_MF2_MASK, VFMSUB_VF }, // 1642 |
20800 | | { PseudoVFMSUB_VFPR64_M1, VFMSUB_VF }, // 1643 |
20801 | | { PseudoVFMSUB_VFPR64_M1_MASK, VFMSUB_VF }, // 1644 |
20802 | | { PseudoVFMSUB_VFPR64_M2, VFMSUB_VF }, // 1645 |
20803 | | { PseudoVFMSUB_VFPR64_M2_MASK, VFMSUB_VF }, // 1646 |
20804 | | { PseudoVFMSUB_VFPR64_M4, VFMSUB_VF }, // 1647 |
20805 | | { PseudoVFMSUB_VFPR64_M4_MASK, VFMSUB_VF }, // 1648 |
20806 | | { PseudoVFMSUB_VFPR64_M8, VFMSUB_VF }, // 1649 |
20807 | | { PseudoVFMSUB_VFPR64_M8_MASK, VFMSUB_VF }, // 1650 |
20808 | | { PseudoVFMSUB_VV_M1, VFMSUB_VV }, // 1651 |
20809 | | { PseudoVFMSUB_VV_M1_MASK, VFMSUB_VV }, // 1652 |
20810 | | { PseudoVFMSUB_VV_M2, VFMSUB_VV }, // 1653 |
20811 | | { PseudoVFMSUB_VV_M2_MASK, VFMSUB_VV }, // 1654 |
20812 | | { PseudoVFMSUB_VV_M4, VFMSUB_VV }, // 1655 |
20813 | | { PseudoVFMSUB_VV_M4_MASK, VFMSUB_VV }, // 1656 |
20814 | | { PseudoVFMSUB_VV_M8, VFMSUB_VV }, // 1657 |
20815 | | { PseudoVFMSUB_VV_M8_MASK, VFMSUB_VV }, // 1658 |
20816 | | { PseudoVFMSUB_VV_MF2, VFMSUB_VV }, // 1659 |
20817 | | { PseudoVFMSUB_VV_MF2_MASK, VFMSUB_VV }, // 1660 |
20818 | | { PseudoVFMSUB_VV_MF4, VFMSUB_VV }, // 1661 |
20819 | | { PseudoVFMSUB_VV_MF4_MASK, VFMSUB_VV }, // 1662 |
20820 | | { PseudoVFMUL_VFPR16_M1, VFMUL_VF }, // 1663 |
20821 | | { PseudoVFMUL_VFPR16_M1_MASK, VFMUL_VF }, // 1664 |
20822 | | { PseudoVFMUL_VFPR16_M2, VFMUL_VF }, // 1665 |
20823 | | { PseudoVFMUL_VFPR16_M2_MASK, VFMUL_VF }, // 1666 |
20824 | | { PseudoVFMUL_VFPR16_M4, VFMUL_VF }, // 1667 |
20825 | | { PseudoVFMUL_VFPR16_M4_MASK, VFMUL_VF }, // 1668 |
20826 | | { PseudoVFMUL_VFPR16_M8, VFMUL_VF }, // 1669 |
20827 | | { PseudoVFMUL_VFPR16_M8_MASK, VFMUL_VF }, // 1670 |
20828 | | { PseudoVFMUL_VFPR16_MF2, VFMUL_VF }, // 1671 |
20829 | | { PseudoVFMUL_VFPR16_MF2_MASK, VFMUL_VF }, // 1672 |
20830 | | { PseudoVFMUL_VFPR16_MF4, VFMUL_VF }, // 1673 |
20831 | | { PseudoVFMUL_VFPR16_MF4_MASK, VFMUL_VF }, // 1674 |
20832 | | { PseudoVFMUL_VFPR32_M1, VFMUL_VF }, // 1675 |
20833 | | { PseudoVFMUL_VFPR32_M1_MASK, VFMUL_VF }, // 1676 |
20834 | | { PseudoVFMUL_VFPR32_M2, VFMUL_VF }, // 1677 |
20835 | | { PseudoVFMUL_VFPR32_M2_MASK, VFMUL_VF }, // 1678 |
20836 | | { PseudoVFMUL_VFPR32_M4, VFMUL_VF }, // 1679 |
20837 | | { PseudoVFMUL_VFPR32_M4_MASK, VFMUL_VF }, // 1680 |
20838 | | { PseudoVFMUL_VFPR32_M8, VFMUL_VF }, // 1681 |
20839 | | { PseudoVFMUL_VFPR32_M8_MASK, VFMUL_VF }, // 1682 |
20840 | | { PseudoVFMUL_VFPR32_MF2, VFMUL_VF }, // 1683 |
20841 | | { PseudoVFMUL_VFPR32_MF2_MASK, VFMUL_VF }, // 1684 |
20842 | | { PseudoVFMUL_VFPR64_M1, VFMUL_VF }, // 1685 |
20843 | | { PseudoVFMUL_VFPR64_M1_MASK, VFMUL_VF }, // 1686 |
20844 | | { PseudoVFMUL_VFPR64_M2, VFMUL_VF }, // 1687 |
20845 | | { PseudoVFMUL_VFPR64_M2_MASK, VFMUL_VF }, // 1688 |
20846 | | { PseudoVFMUL_VFPR64_M4, VFMUL_VF }, // 1689 |
20847 | | { PseudoVFMUL_VFPR64_M4_MASK, VFMUL_VF }, // 1690 |
20848 | | { PseudoVFMUL_VFPR64_M8, VFMUL_VF }, // 1691 |
20849 | | { PseudoVFMUL_VFPR64_M8_MASK, VFMUL_VF }, // 1692 |
20850 | | { PseudoVFMUL_VV_M1, VFMUL_VV }, // 1693 |
20851 | | { PseudoVFMUL_VV_M1_MASK, VFMUL_VV }, // 1694 |
20852 | | { PseudoVFMUL_VV_M2, VFMUL_VV }, // 1695 |
20853 | | { PseudoVFMUL_VV_M2_MASK, VFMUL_VV }, // 1696 |
20854 | | { PseudoVFMUL_VV_M4, VFMUL_VV }, // 1697 |
20855 | | { PseudoVFMUL_VV_M4_MASK, VFMUL_VV }, // 1698 |
20856 | | { PseudoVFMUL_VV_M8, VFMUL_VV }, // 1699 |
20857 | | { PseudoVFMUL_VV_M8_MASK, VFMUL_VV }, // 1700 |
20858 | | { PseudoVFMUL_VV_MF2, VFMUL_VV }, // 1701 |
20859 | | { PseudoVFMUL_VV_MF2_MASK, VFMUL_VV }, // 1702 |
20860 | | { PseudoVFMUL_VV_MF4, VFMUL_VV }, // 1703 |
20861 | | { PseudoVFMUL_VV_MF4_MASK, VFMUL_VV }, // 1704 |
20862 | | { PseudoVFMV_FPR16_S_M1, VFMV_F_S }, // 1705 |
20863 | | { PseudoVFMV_FPR16_S_M2, VFMV_F_S }, // 1706 |
20864 | | { PseudoVFMV_FPR16_S_M4, VFMV_F_S }, // 1707 |
20865 | | { PseudoVFMV_FPR16_S_M8, VFMV_F_S }, // 1708 |
20866 | | { PseudoVFMV_FPR16_S_MF2, VFMV_F_S }, // 1709 |
20867 | | { PseudoVFMV_FPR16_S_MF4, VFMV_F_S }, // 1710 |
20868 | | { PseudoVFMV_FPR32_S_M1, VFMV_F_S }, // 1711 |
20869 | | { PseudoVFMV_FPR32_S_M2, VFMV_F_S }, // 1712 |
20870 | | { PseudoVFMV_FPR32_S_M4, VFMV_F_S }, // 1713 |
20871 | | { PseudoVFMV_FPR32_S_M8, VFMV_F_S }, // 1714 |
20872 | | { PseudoVFMV_FPR32_S_MF2, VFMV_F_S }, // 1715 |
20873 | | { PseudoVFMV_FPR64_S_M1, VFMV_F_S }, // 1716 |
20874 | | { PseudoVFMV_FPR64_S_M2, VFMV_F_S }, // 1717 |
20875 | | { PseudoVFMV_FPR64_S_M4, VFMV_F_S }, // 1718 |
20876 | | { PseudoVFMV_FPR64_S_M8, VFMV_F_S }, // 1719 |
20877 | | { PseudoVFMV_S_FPR16_M1, VFMV_S_F }, // 1720 |
20878 | | { PseudoVFMV_S_FPR16_M2, VFMV_S_F }, // 1721 |
20879 | | { PseudoVFMV_S_FPR16_M4, VFMV_S_F }, // 1722 |
20880 | | { PseudoVFMV_S_FPR16_M8, VFMV_S_F }, // 1723 |
20881 | | { PseudoVFMV_S_FPR16_MF2, VFMV_S_F }, // 1724 |
20882 | | { PseudoVFMV_S_FPR16_MF4, VFMV_S_F }, // 1725 |
20883 | | { PseudoVFMV_S_FPR32_M1, VFMV_S_F }, // 1726 |
20884 | | { PseudoVFMV_S_FPR32_M2, VFMV_S_F }, // 1727 |
20885 | | { PseudoVFMV_S_FPR32_M4, VFMV_S_F }, // 1728 |
20886 | | { PseudoVFMV_S_FPR32_M8, VFMV_S_F }, // 1729 |
20887 | | { PseudoVFMV_S_FPR32_MF2, VFMV_S_F }, // 1730 |
20888 | | { PseudoVFMV_S_FPR64_M1, VFMV_S_F }, // 1731 |
20889 | | { PseudoVFMV_S_FPR64_M2, VFMV_S_F }, // 1732 |
20890 | | { PseudoVFMV_S_FPR64_M4, VFMV_S_F }, // 1733 |
20891 | | { PseudoVFMV_S_FPR64_M8, VFMV_S_F }, // 1734 |
20892 | | { PseudoVFMV_V_FPR16_M1, VFMV_V_F }, // 1735 |
20893 | | { PseudoVFMV_V_FPR16_M2, VFMV_V_F }, // 1736 |
20894 | | { PseudoVFMV_V_FPR16_M4, VFMV_V_F }, // 1737 |
20895 | | { PseudoVFMV_V_FPR16_M8, VFMV_V_F }, // 1738 |
20896 | | { PseudoVFMV_V_FPR16_MF2, VFMV_V_F }, // 1739 |
20897 | | { PseudoVFMV_V_FPR16_MF4, VFMV_V_F }, // 1740 |
20898 | | { PseudoVFMV_V_FPR32_M1, VFMV_V_F }, // 1741 |
20899 | | { PseudoVFMV_V_FPR32_M2, VFMV_V_F }, // 1742 |
20900 | | { PseudoVFMV_V_FPR32_M4, VFMV_V_F }, // 1743 |
20901 | | { PseudoVFMV_V_FPR32_M8, VFMV_V_F }, // 1744 |
20902 | | { PseudoVFMV_V_FPR32_MF2, VFMV_V_F }, // 1745 |
20903 | | { PseudoVFMV_V_FPR64_M1, VFMV_V_F }, // 1746 |
20904 | | { PseudoVFMV_V_FPR64_M2, VFMV_V_F }, // 1747 |
20905 | | { PseudoVFMV_V_FPR64_M4, VFMV_V_F }, // 1748 |
20906 | | { PseudoVFMV_V_FPR64_M8, VFMV_V_F }, // 1749 |
20907 | | { PseudoVFNCVTBF16_F_F_W_M1, VFNCVTBF16_F_F_W }, // 1750 |
20908 | | { PseudoVFNCVTBF16_F_F_W_M1_MASK, VFNCVTBF16_F_F_W }, // 1751 |
20909 | | { PseudoVFNCVTBF16_F_F_W_M2, VFNCVTBF16_F_F_W }, // 1752 |
20910 | | { PseudoVFNCVTBF16_F_F_W_M2_MASK, VFNCVTBF16_F_F_W }, // 1753 |
20911 | | { PseudoVFNCVTBF16_F_F_W_M4, VFNCVTBF16_F_F_W }, // 1754 |
20912 | | { PseudoVFNCVTBF16_F_F_W_M4_MASK, VFNCVTBF16_F_F_W }, // 1755 |
20913 | | { PseudoVFNCVTBF16_F_F_W_MF2, VFNCVTBF16_F_F_W }, // 1756 |
20914 | | { PseudoVFNCVTBF16_F_F_W_MF2_MASK, VFNCVTBF16_F_F_W }, // 1757 |
20915 | | { PseudoVFNCVTBF16_F_F_W_MF4, VFNCVTBF16_F_F_W }, // 1758 |
20916 | | { PseudoVFNCVTBF16_F_F_W_MF4_MASK, VFNCVTBF16_F_F_W }, // 1759 |
20917 | | { PseudoVFNCVT_F_F_W_M1, VFNCVT_F_F_W }, // 1760 |
20918 | | { PseudoVFNCVT_F_F_W_M1_MASK, VFNCVT_F_F_W }, // 1761 |
20919 | | { PseudoVFNCVT_F_F_W_M2, VFNCVT_F_F_W }, // 1762 |
20920 | | { PseudoVFNCVT_F_F_W_M2_MASK, VFNCVT_F_F_W }, // 1763 |
20921 | | { PseudoVFNCVT_F_F_W_M4, VFNCVT_F_F_W }, // 1764 |
20922 | | { PseudoVFNCVT_F_F_W_M4_MASK, VFNCVT_F_F_W }, // 1765 |
20923 | | { PseudoVFNCVT_F_F_W_MF2, VFNCVT_F_F_W }, // 1766 |
20924 | | { PseudoVFNCVT_F_F_W_MF2_MASK, VFNCVT_F_F_W }, // 1767 |
20925 | | { PseudoVFNCVT_F_F_W_MF4, VFNCVT_F_F_W }, // 1768 |
20926 | | { PseudoVFNCVT_F_F_W_MF4_MASK, VFNCVT_F_F_W }, // 1769 |
20927 | | { PseudoVFNCVT_F_XU_W_M1, VFNCVT_F_XU_W }, // 1770 |
20928 | | { PseudoVFNCVT_F_XU_W_M1_MASK, VFNCVT_F_XU_W }, // 1771 |
20929 | | { PseudoVFNCVT_F_XU_W_M2, VFNCVT_F_XU_W }, // 1772 |
20930 | | { PseudoVFNCVT_F_XU_W_M2_MASK, VFNCVT_F_XU_W }, // 1773 |
20931 | | { PseudoVFNCVT_F_XU_W_M4, VFNCVT_F_XU_W }, // 1774 |
20932 | | { PseudoVFNCVT_F_XU_W_M4_MASK, VFNCVT_F_XU_W }, // 1775 |
20933 | | { PseudoVFNCVT_F_XU_W_MF2, VFNCVT_F_XU_W }, // 1776 |
20934 | | { PseudoVFNCVT_F_XU_W_MF2_MASK, VFNCVT_F_XU_W }, // 1777 |
20935 | | { PseudoVFNCVT_F_XU_W_MF4, VFNCVT_F_XU_W }, // 1778 |
20936 | | { PseudoVFNCVT_F_XU_W_MF4_MASK, VFNCVT_F_XU_W }, // 1779 |
20937 | | { PseudoVFNCVT_F_X_W_M1, VFNCVT_F_X_W }, // 1780 |
20938 | | { PseudoVFNCVT_F_X_W_M1_MASK, VFNCVT_F_X_W }, // 1781 |
20939 | | { PseudoVFNCVT_F_X_W_M2, VFNCVT_F_X_W }, // 1782 |
20940 | | { PseudoVFNCVT_F_X_W_M2_MASK, VFNCVT_F_X_W }, // 1783 |
20941 | | { PseudoVFNCVT_F_X_W_M4, VFNCVT_F_X_W }, // 1784 |
20942 | | { PseudoVFNCVT_F_X_W_M4_MASK, VFNCVT_F_X_W }, // 1785 |
20943 | | { PseudoVFNCVT_F_X_W_MF2, VFNCVT_F_X_W }, // 1786 |
20944 | | { PseudoVFNCVT_F_X_W_MF2_MASK, VFNCVT_F_X_W }, // 1787 |
20945 | | { PseudoVFNCVT_F_X_W_MF4, VFNCVT_F_X_W }, // 1788 |
20946 | | { PseudoVFNCVT_F_X_W_MF4_MASK, VFNCVT_F_X_W }, // 1789 |
20947 | | { PseudoVFNCVT_RM_F_XU_W_M1, VFNCVT_F_XU_W }, // 1790 |
20948 | | { PseudoVFNCVT_RM_F_XU_W_M1_MASK, VFNCVT_F_XU_W }, // 1791 |
20949 | | { PseudoVFNCVT_RM_F_XU_W_M2, VFNCVT_F_XU_W }, // 1792 |
20950 | | { PseudoVFNCVT_RM_F_XU_W_M2_MASK, VFNCVT_F_XU_W }, // 1793 |
20951 | | { PseudoVFNCVT_RM_F_XU_W_M4, VFNCVT_F_XU_W }, // 1794 |
20952 | | { PseudoVFNCVT_RM_F_XU_W_M4_MASK, VFNCVT_F_XU_W }, // 1795 |
20953 | | { PseudoVFNCVT_RM_F_XU_W_MF2, VFNCVT_F_XU_W }, // 1796 |
20954 | | { PseudoVFNCVT_RM_F_XU_W_MF2_MASK, VFNCVT_F_XU_W }, // 1797 |
20955 | | { PseudoVFNCVT_RM_F_XU_W_MF4, VFNCVT_F_XU_W }, // 1798 |
20956 | | { PseudoVFNCVT_RM_F_XU_W_MF4_MASK, VFNCVT_F_XU_W }, // 1799 |
20957 | | { PseudoVFNCVT_RM_F_X_W_M1, VFNCVT_F_X_W }, // 1800 |
20958 | | { PseudoVFNCVT_RM_F_X_W_M1_MASK, VFNCVT_F_X_W }, // 1801 |
20959 | | { PseudoVFNCVT_RM_F_X_W_M2, VFNCVT_F_X_W }, // 1802 |
20960 | | { PseudoVFNCVT_RM_F_X_W_M2_MASK, VFNCVT_F_X_W }, // 1803 |
20961 | | { PseudoVFNCVT_RM_F_X_W_M4, VFNCVT_F_X_W }, // 1804 |
20962 | | { PseudoVFNCVT_RM_F_X_W_M4_MASK, VFNCVT_F_X_W }, // 1805 |
20963 | | { PseudoVFNCVT_RM_F_X_W_MF2, VFNCVT_F_X_W }, // 1806 |
20964 | | { PseudoVFNCVT_RM_F_X_W_MF2_MASK, VFNCVT_F_X_W }, // 1807 |
20965 | | { PseudoVFNCVT_RM_F_X_W_MF4, VFNCVT_F_X_W }, // 1808 |
20966 | | { PseudoVFNCVT_RM_F_X_W_MF4_MASK, VFNCVT_F_X_W }, // 1809 |
20967 | | { PseudoVFNCVT_RM_XU_F_W_M1, VFNCVT_XU_F_W }, // 1810 |
20968 | | { PseudoVFNCVT_RM_XU_F_W_M1_MASK, VFNCVT_XU_F_W }, // 1811 |
20969 | | { PseudoVFNCVT_RM_XU_F_W_M2, VFNCVT_XU_F_W }, // 1812 |
20970 | | { PseudoVFNCVT_RM_XU_F_W_M2_MASK, VFNCVT_XU_F_W }, // 1813 |
20971 | | { PseudoVFNCVT_RM_XU_F_W_M4, VFNCVT_XU_F_W }, // 1814 |
20972 | | { PseudoVFNCVT_RM_XU_F_W_M4_MASK, VFNCVT_XU_F_W }, // 1815 |
20973 | | { PseudoVFNCVT_RM_XU_F_W_MF2, VFNCVT_XU_F_W }, // 1816 |
20974 | | { PseudoVFNCVT_RM_XU_F_W_MF2_MASK, VFNCVT_XU_F_W }, // 1817 |
20975 | | { PseudoVFNCVT_RM_XU_F_W_MF4, VFNCVT_XU_F_W }, // 1818 |
20976 | | { PseudoVFNCVT_RM_XU_F_W_MF4_MASK, VFNCVT_XU_F_W }, // 1819 |
20977 | | { PseudoVFNCVT_RM_XU_F_W_MF8, VFNCVT_XU_F_W }, // 1820 |
20978 | | { PseudoVFNCVT_RM_XU_F_W_MF8_MASK, VFNCVT_XU_F_W }, // 1821 |
20979 | | { PseudoVFNCVT_RM_X_F_W_M1, VFNCVT_X_F_W }, // 1822 |
20980 | | { PseudoVFNCVT_RM_X_F_W_M1_MASK, VFNCVT_X_F_W }, // 1823 |
20981 | | { PseudoVFNCVT_RM_X_F_W_M2, VFNCVT_X_F_W }, // 1824 |
20982 | | { PseudoVFNCVT_RM_X_F_W_M2_MASK, VFNCVT_X_F_W }, // 1825 |
20983 | | { PseudoVFNCVT_RM_X_F_W_M4, VFNCVT_X_F_W }, // 1826 |
20984 | | { PseudoVFNCVT_RM_X_F_W_M4_MASK, VFNCVT_X_F_W }, // 1827 |
20985 | | { PseudoVFNCVT_RM_X_F_W_MF2, VFNCVT_X_F_W }, // 1828 |
20986 | | { PseudoVFNCVT_RM_X_F_W_MF2_MASK, VFNCVT_X_F_W }, // 1829 |
20987 | | { PseudoVFNCVT_RM_X_F_W_MF4, VFNCVT_X_F_W }, // 1830 |
20988 | | { PseudoVFNCVT_RM_X_F_W_MF4_MASK, VFNCVT_X_F_W }, // 1831 |
20989 | | { PseudoVFNCVT_RM_X_F_W_MF8, VFNCVT_X_F_W }, // 1832 |
20990 | | { PseudoVFNCVT_RM_X_F_W_MF8_MASK, VFNCVT_X_F_W }, // 1833 |
20991 | | { PseudoVFNCVT_ROD_F_F_W_M1, VFNCVT_ROD_F_F_W }, // 1834 |
20992 | | { PseudoVFNCVT_ROD_F_F_W_M1_MASK, VFNCVT_ROD_F_F_W }, // 1835 |
20993 | | { PseudoVFNCVT_ROD_F_F_W_M2, VFNCVT_ROD_F_F_W }, // 1836 |
20994 | | { PseudoVFNCVT_ROD_F_F_W_M2_MASK, VFNCVT_ROD_F_F_W }, // 1837 |
20995 | | { PseudoVFNCVT_ROD_F_F_W_M4, VFNCVT_ROD_F_F_W }, // 1838 |
20996 | | { PseudoVFNCVT_ROD_F_F_W_M4_MASK, VFNCVT_ROD_F_F_W }, // 1839 |
20997 | | { PseudoVFNCVT_ROD_F_F_W_MF2, VFNCVT_ROD_F_F_W }, // 1840 |
20998 | | { PseudoVFNCVT_ROD_F_F_W_MF2_MASK, VFNCVT_ROD_F_F_W }, // 1841 |
20999 | | { PseudoVFNCVT_ROD_F_F_W_MF4, VFNCVT_ROD_F_F_W }, // 1842 |
21000 | | { PseudoVFNCVT_ROD_F_F_W_MF4_MASK, VFNCVT_ROD_F_F_W }, // 1843 |
21001 | | { PseudoVFNCVT_RTZ_XU_F_W_M1, VFNCVT_RTZ_XU_F_W }, // 1844 |
21002 | | { PseudoVFNCVT_RTZ_XU_F_W_M1_MASK, VFNCVT_RTZ_XU_F_W }, // 1845 |
21003 | | { PseudoVFNCVT_RTZ_XU_F_W_M2, VFNCVT_RTZ_XU_F_W }, // 1846 |
21004 | | { PseudoVFNCVT_RTZ_XU_F_W_M2_MASK, VFNCVT_RTZ_XU_F_W }, // 1847 |
21005 | | { PseudoVFNCVT_RTZ_XU_F_W_M4, VFNCVT_RTZ_XU_F_W }, // 1848 |
21006 | | { PseudoVFNCVT_RTZ_XU_F_W_M4_MASK, VFNCVT_RTZ_XU_F_W }, // 1849 |
21007 | | { PseudoVFNCVT_RTZ_XU_F_W_MF2, VFNCVT_RTZ_XU_F_W }, // 1850 |
21008 | | { PseudoVFNCVT_RTZ_XU_F_W_MF2_MASK, VFNCVT_RTZ_XU_F_W }, // 1851 |
21009 | | { PseudoVFNCVT_RTZ_XU_F_W_MF4, VFNCVT_RTZ_XU_F_W }, // 1852 |
21010 | | { PseudoVFNCVT_RTZ_XU_F_W_MF4_MASK, VFNCVT_RTZ_XU_F_W }, // 1853 |
21011 | | { PseudoVFNCVT_RTZ_XU_F_W_MF8, VFNCVT_RTZ_XU_F_W }, // 1854 |
21012 | | { PseudoVFNCVT_RTZ_XU_F_W_MF8_MASK, VFNCVT_RTZ_XU_F_W }, // 1855 |
21013 | | { PseudoVFNCVT_RTZ_X_F_W_M1, VFNCVT_RTZ_X_F_W }, // 1856 |
21014 | | { PseudoVFNCVT_RTZ_X_F_W_M1_MASK, VFNCVT_RTZ_X_F_W }, // 1857 |
21015 | | { PseudoVFNCVT_RTZ_X_F_W_M2, VFNCVT_RTZ_X_F_W }, // 1858 |
21016 | | { PseudoVFNCVT_RTZ_X_F_W_M2_MASK, VFNCVT_RTZ_X_F_W }, // 1859 |
21017 | | { PseudoVFNCVT_RTZ_X_F_W_M4, VFNCVT_RTZ_X_F_W }, // 1860 |
21018 | | { PseudoVFNCVT_RTZ_X_F_W_M4_MASK, VFNCVT_RTZ_X_F_W }, // 1861 |
21019 | | { PseudoVFNCVT_RTZ_X_F_W_MF2, VFNCVT_RTZ_X_F_W }, // 1862 |
21020 | | { PseudoVFNCVT_RTZ_X_F_W_MF2_MASK, VFNCVT_RTZ_X_F_W }, // 1863 |
21021 | | { PseudoVFNCVT_RTZ_X_F_W_MF4, VFNCVT_RTZ_X_F_W }, // 1864 |
21022 | | { PseudoVFNCVT_RTZ_X_F_W_MF4_MASK, VFNCVT_RTZ_X_F_W }, // 1865 |
21023 | | { PseudoVFNCVT_RTZ_X_F_W_MF8, VFNCVT_RTZ_X_F_W }, // 1866 |
21024 | | { PseudoVFNCVT_RTZ_X_F_W_MF8_MASK, VFNCVT_RTZ_X_F_W }, // 1867 |
21025 | | { PseudoVFNCVT_XU_F_W_M1, VFNCVT_XU_F_W }, // 1868 |
21026 | | { PseudoVFNCVT_XU_F_W_M1_MASK, VFNCVT_XU_F_W }, // 1869 |
21027 | | { PseudoVFNCVT_XU_F_W_M2, VFNCVT_XU_F_W }, // 1870 |
21028 | | { PseudoVFNCVT_XU_F_W_M2_MASK, VFNCVT_XU_F_W }, // 1871 |
21029 | | { PseudoVFNCVT_XU_F_W_M4, VFNCVT_XU_F_W }, // 1872 |
21030 | | { PseudoVFNCVT_XU_F_W_M4_MASK, VFNCVT_XU_F_W }, // 1873 |
21031 | | { PseudoVFNCVT_XU_F_W_MF2, VFNCVT_XU_F_W }, // 1874 |
21032 | | { PseudoVFNCVT_XU_F_W_MF2_MASK, VFNCVT_XU_F_W }, // 1875 |
21033 | | { PseudoVFNCVT_XU_F_W_MF4, VFNCVT_XU_F_W }, // 1876 |
21034 | | { PseudoVFNCVT_XU_F_W_MF4_MASK, VFNCVT_XU_F_W }, // 1877 |
21035 | | { PseudoVFNCVT_XU_F_W_MF8, VFNCVT_XU_F_W }, // 1878 |
21036 | | { PseudoVFNCVT_XU_F_W_MF8_MASK, VFNCVT_XU_F_W }, // 1879 |
21037 | | { PseudoVFNCVT_X_F_W_M1, VFNCVT_X_F_W }, // 1880 |
21038 | | { PseudoVFNCVT_X_F_W_M1_MASK, VFNCVT_X_F_W }, // 1881 |
21039 | | { PseudoVFNCVT_X_F_W_M2, VFNCVT_X_F_W }, // 1882 |
21040 | | { PseudoVFNCVT_X_F_W_M2_MASK, VFNCVT_X_F_W }, // 1883 |
21041 | | { PseudoVFNCVT_X_F_W_M4, VFNCVT_X_F_W }, // 1884 |
21042 | | { PseudoVFNCVT_X_F_W_M4_MASK, VFNCVT_X_F_W }, // 1885 |
21043 | | { PseudoVFNCVT_X_F_W_MF2, VFNCVT_X_F_W }, // 1886 |
21044 | | { PseudoVFNCVT_X_F_W_MF2_MASK, VFNCVT_X_F_W }, // 1887 |
21045 | | { PseudoVFNCVT_X_F_W_MF4, VFNCVT_X_F_W }, // 1888 |
21046 | | { PseudoVFNCVT_X_F_W_MF4_MASK, VFNCVT_X_F_W }, // 1889 |
21047 | | { PseudoVFNCVT_X_F_W_MF8, VFNCVT_X_F_W }, // 1890 |
21048 | | { PseudoVFNCVT_X_F_W_MF8_MASK, VFNCVT_X_F_W }, // 1891 |
21049 | | { PseudoVFNMACC_VFPR16_M1, VFNMACC_VF }, // 1892 |
21050 | | { PseudoVFNMACC_VFPR16_M1_MASK, VFNMACC_VF }, // 1893 |
21051 | | { PseudoVFNMACC_VFPR16_M2, VFNMACC_VF }, // 1894 |
21052 | | { PseudoVFNMACC_VFPR16_M2_MASK, VFNMACC_VF }, // 1895 |
21053 | | { PseudoVFNMACC_VFPR16_M4, VFNMACC_VF }, // 1896 |
21054 | | { PseudoVFNMACC_VFPR16_M4_MASK, VFNMACC_VF }, // 1897 |
21055 | | { PseudoVFNMACC_VFPR16_M8, VFNMACC_VF }, // 1898 |
21056 | | { PseudoVFNMACC_VFPR16_M8_MASK, VFNMACC_VF }, // 1899 |
21057 | | { PseudoVFNMACC_VFPR16_MF2, VFNMACC_VF }, // 1900 |
21058 | | { PseudoVFNMACC_VFPR16_MF2_MASK, VFNMACC_VF }, // 1901 |
21059 | | { PseudoVFNMACC_VFPR16_MF4, VFNMACC_VF }, // 1902 |
21060 | | { PseudoVFNMACC_VFPR16_MF4_MASK, VFNMACC_VF }, // 1903 |
21061 | | { PseudoVFNMACC_VFPR32_M1, VFNMACC_VF }, // 1904 |
21062 | | { PseudoVFNMACC_VFPR32_M1_MASK, VFNMACC_VF }, // 1905 |
21063 | | { PseudoVFNMACC_VFPR32_M2, VFNMACC_VF }, // 1906 |
21064 | | { PseudoVFNMACC_VFPR32_M2_MASK, VFNMACC_VF }, // 1907 |
21065 | | { PseudoVFNMACC_VFPR32_M4, VFNMACC_VF }, // 1908 |
21066 | | { PseudoVFNMACC_VFPR32_M4_MASK, VFNMACC_VF }, // 1909 |
21067 | | { PseudoVFNMACC_VFPR32_M8, VFNMACC_VF }, // 1910 |
21068 | | { PseudoVFNMACC_VFPR32_M8_MASK, VFNMACC_VF }, // 1911 |
21069 | | { PseudoVFNMACC_VFPR32_MF2, VFNMACC_VF }, // 1912 |
21070 | | { PseudoVFNMACC_VFPR32_MF2_MASK, VFNMACC_VF }, // 1913 |
21071 | | { PseudoVFNMACC_VFPR64_M1, VFNMACC_VF }, // 1914 |
21072 | | { PseudoVFNMACC_VFPR64_M1_MASK, VFNMACC_VF }, // 1915 |
21073 | | { PseudoVFNMACC_VFPR64_M2, VFNMACC_VF }, // 1916 |
21074 | | { PseudoVFNMACC_VFPR64_M2_MASK, VFNMACC_VF }, // 1917 |
21075 | | { PseudoVFNMACC_VFPR64_M4, VFNMACC_VF }, // 1918 |
21076 | | { PseudoVFNMACC_VFPR64_M4_MASK, VFNMACC_VF }, // 1919 |
21077 | | { PseudoVFNMACC_VFPR64_M8, VFNMACC_VF }, // 1920 |
21078 | | { PseudoVFNMACC_VFPR64_M8_MASK, VFNMACC_VF }, // 1921 |
21079 | | { PseudoVFNMACC_VV_M1, VFNMACC_VV }, // 1922 |
21080 | | { PseudoVFNMACC_VV_M1_MASK, VFNMACC_VV }, // 1923 |
21081 | | { PseudoVFNMACC_VV_M2, VFNMACC_VV }, // 1924 |
21082 | | { PseudoVFNMACC_VV_M2_MASK, VFNMACC_VV }, // 1925 |
21083 | | { PseudoVFNMACC_VV_M4, VFNMACC_VV }, // 1926 |
21084 | | { PseudoVFNMACC_VV_M4_MASK, VFNMACC_VV }, // 1927 |
21085 | | { PseudoVFNMACC_VV_M8, VFNMACC_VV }, // 1928 |
21086 | | { PseudoVFNMACC_VV_M8_MASK, VFNMACC_VV }, // 1929 |
21087 | | { PseudoVFNMACC_VV_MF2, VFNMACC_VV }, // 1930 |
21088 | | { PseudoVFNMACC_VV_MF2_MASK, VFNMACC_VV }, // 1931 |
21089 | | { PseudoVFNMACC_VV_MF4, VFNMACC_VV }, // 1932 |
21090 | | { PseudoVFNMACC_VV_MF4_MASK, VFNMACC_VV }, // 1933 |
21091 | | { PseudoVFNMADD_VFPR16_M1, VFNMADD_VF }, // 1934 |
21092 | | { PseudoVFNMADD_VFPR16_M1_MASK, VFNMADD_VF }, // 1935 |
21093 | | { PseudoVFNMADD_VFPR16_M2, VFNMADD_VF }, // 1936 |
21094 | | { PseudoVFNMADD_VFPR16_M2_MASK, VFNMADD_VF }, // 1937 |
21095 | | { PseudoVFNMADD_VFPR16_M4, VFNMADD_VF }, // 1938 |
21096 | | { PseudoVFNMADD_VFPR16_M4_MASK, VFNMADD_VF }, // 1939 |
21097 | | { PseudoVFNMADD_VFPR16_M8, VFNMADD_VF }, // 1940 |
21098 | | { PseudoVFNMADD_VFPR16_M8_MASK, VFNMADD_VF }, // 1941 |
21099 | | { PseudoVFNMADD_VFPR16_MF2, VFNMADD_VF }, // 1942 |
21100 | | { PseudoVFNMADD_VFPR16_MF2_MASK, VFNMADD_VF }, // 1943 |
21101 | | { PseudoVFNMADD_VFPR16_MF4, VFNMADD_VF }, // 1944 |
21102 | | { PseudoVFNMADD_VFPR16_MF4_MASK, VFNMADD_VF }, // 1945 |
21103 | | { PseudoVFNMADD_VFPR32_M1, VFNMADD_VF }, // 1946 |
21104 | | { PseudoVFNMADD_VFPR32_M1_MASK, VFNMADD_VF }, // 1947 |
21105 | | { PseudoVFNMADD_VFPR32_M2, VFNMADD_VF }, // 1948 |
21106 | | { PseudoVFNMADD_VFPR32_M2_MASK, VFNMADD_VF }, // 1949 |
21107 | | { PseudoVFNMADD_VFPR32_M4, VFNMADD_VF }, // 1950 |
21108 | | { PseudoVFNMADD_VFPR32_M4_MASK, VFNMADD_VF }, // 1951 |
21109 | | { PseudoVFNMADD_VFPR32_M8, VFNMADD_VF }, // 1952 |
21110 | | { PseudoVFNMADD_VFPR32_M8_MASK, VFNMADD_VF }, // 1953 |
21111 | | { PseudoVFNMADD_VFPR32_MF2, VFNMADD_VF }, // 1954 |
21112 | | { PseudoVFNMADD_VFPR32_MF2_MASK, VFNMADD_VF }, // 1955 |
21113 | | { PseudoVFNMADD_VFPR64_M1, VFNMADD_VF }, // 1956 |
21114 | | { PseudoVFNMADD_VFPR64_M1_MASK, VFNMADD_VF }, // 1957 |
21115 | | { PseudoVFNMADD_VFPR64_M2, VFNMADD_VF }, // 1958 |
21116 | | { PseudoVFNMADD_VFPR64_M2_MASK, VFNMADD_VF }, // 1959 |
21117 | | { PseudoVFNMADD_VFPR64_M4, VFNMADD_VF }, // 1960 |
21118 | | { PseudoVFNMADD_VFPR64_M4_MASK, VFNMADD_VF }, // 1961 |
21119 | | { PseudoVFNMADD_VFPR64_M8, VFNMADD_VF }, // 1962 |
21120 | | { PseudoVFNMADD_VFPR64_M8_MASK, VFNMADD_VF }, // 1963 |
21121 | | { PseudoVFNMADD_VV_M1, VFNMADD_VV }, // 1964 |
21122 | | { PseudoVFNMADD_VV_M1_MASK, VFNMADD_VV }, // 1965 |
21123 | | { PseudoVFNMADD_VV_M2, VFNMADD_VV }, // 1966 |
21124 | | { PseudoVFNMADD_VV_M2_MASK, VFNMADD_VV }, // 1967 |
21125 | | { PseudoVFNMADD_VV_M4, VFNMADD_VV }, // 1968 |
21126 | | { PseudoVFNMADD_VV_M4_MASK, VFNMADD_VV }, // 1969 |
21127 | | { PseudoVFNMADD_VV_M8, VFNMADD_VV }, // 1970 |
21128 | | { PseudoVFNMADD_VV_M8_MASK, VFNMADD_VV }, // 1971 |
21129 | | { PseudoVFNMADD_VV_MF2, VFNMADD_VV }, // 1972 |
21130 | | { PseudoVFNMADD_VV_MF2_MASK, VFNMADD_VV }, // 1973 |
21131 | | { PseudoVFNMADD_VV_MF4, VFNMADD_VV }, // 1974 |
21132 | | { PseudoVFNMADD_VV_MF4_MASK, VFNMADD_VV }, // 1975 |
21133 | | { PseudoVFNMSAC_VFPR16_M1, VFNMSAC_VF }, // 1976 |
21134 | | { PseudoVFNMSAC_VFPR16_M1_MASK, VFNMSAC_VF }, // 1977 |
21135 | | { PseudoVFNMSAC_VFPR16_M2, VFNMSAC_VF }, // 1978 |
21136 | | { PseudoVFNMSAC_VFPR16_M2_MASK, VFNMSAC_VF }, // 1979 |
21137 | | { PseudoVFNMSAC_VFPR16_M4, VFNMSAC_VF }, // 1980 |
21138 | | { PseudoVFNMSAC_VFPR16_M4_MASK, VFNMSAC_VF }, // 1981 |
21139 | | { PseudoVFNMSAC_VFPR16_M8, VFNMSAC_VF }, // 1982 |
21140 | | { PseudoVFNMSAC_VFPR16_M8_MASK, VFNMSAC_VF }, // 1983 |
21141 | | { PseudoVFNMSAC_VFPR16_MF2, VFNMSAC_VF }, // 1984 |
21142 | | { PseudoVFNMSAC_VFPR16_MF2_MASK, VFNMSAC_VF }, // 1985 |
21143 | | { PseudoVFNMSAC_VFPR16_MF4, VFNMSAC_VF }, // 1986 |
21144 | | { PseudoVFNMSAC_VFPR16_MF4_MASK, VFNMSAC_VF }, // 1987 |
21145 | | { PseudoVFNMSAC_VFPR32_M1, VFNMSAC_VF }, // 1988 |
21146 | | { PseudoVFNMSAC_VFPR32_M1_MASK, VFNMSAC_VF }, // 1989 |
21147 | | { PseudoVFNMSAC_VFPR32_M2, VFNMSAC_VF }, // 1990 |
21148 | | { PseudoVFNMSAC_VFPR32_M2_MASK, VFNMSAC_VF }, // 1991 |
21149 | | { PseudoVFNMSAC_VFPR32_M4, VFNMSAC_VF }, // 1992 |
21150 | | { PseudoVFNMSAC_VFPR32_M4_MASK, VFNMSAC_VF }, // 1993 |
21151 | | { PseudoVFNMSAC_VFPR32_M8, VFNMSAC_VF }, // 1994 |
21152 | | { PseudoVFNMSAC_VFPR32_M8_MASK, VFNMSAC_VF }, // 1995 |
21153 | | { PseudoVFNMSAC_VFPR32_MF2, VFNMSAC_VF }, // 1996 |
21154 | | { PseudoVFNMSAC_VFPR32_MF2_MASK, VFNMSAC_VF }, // 1997 |
21155 | | { PseudoVFNMSAC_VFPR64_M1, VFNMSAC_VF }, // 1998 |
21156 | | { PseudoVFNMSAC_VFPR64_M1_MASK, VFNMSAC_VF }, // 1999 |
21157 | | { PseudoVFNMSAC_VFPR64_M2, VFNMSAC_VF }, // 2000 |
21158 | | { PseudoVFNMSAC_VFPR64_M2_MASK, VFNMSAC_VF }, // 2001 |
21159 | | { PseudoVFNMSAC_VFPR64_M4, VFNMSAC_VF }, // 2002 |
21160 | | { PseudoVFNMSAC_VFPR64_M4_MASK, VFNMSAC_VF }, // 2003 |
21161 | | { PseudoVFNMSAC_VFPR64_M8, VFNMSAC_VF }, // 2004 |
21162 | | { PseudoVFNMSAC_VFPR64_M8_MASK, VFNMSAC_VF }, // 2005 |
21163 | | { PseudoVFNMSAC_VV_M1, VFNMSAC_VV }, // 2006 |
21164 | | { PseudoVFNMSAC_VV_M1_MASK, VFNMSAC_VV }, // 2007 |
21165 | | { PseudoVFNMSAC_VV_M2, VFNMSAC_VV }, // 2008 |
21166 | | { PseudoVFNMSAC_VV_M2_MASK, VFNMSAC_VV }, // 2009 |
21167 | | { PseudoVFNMSAC_VV_M4, VFNMSAC_VV }, // 2010 |
21168 | | { PseudoVFNMSAC_VV_M4_MASK, VFNMSAC_VV }, // 2011 |
21169 | | { PseudoVFNMSAC_VV_M8, VFNMSAC_VV }, // 2012 |
21170 | | { PseudoVFNMSAC_VV_M8_MASK, VFNMSAC_VV }, // 2013 |
21171 | | { PseudoVFNMSAC_VV_MF2, VFNMSAC_VV }, // 2014 |
21172 | | { PseudoVFNMSAC_VV_MF2_MASK, VFNMSAC_VV }, // 2015 |
21173 | | { PseudoVFNMSAC_VV_MF4, VFNMSAC_VV }, // 2016 |
21174 | | { PseudoVFNMSAC_VV_MF4_MASK, VFNMSAC_VV }, // 2017 |
21175 | | { PseudoVFNMSUB_VFPR16_M1, VFNMSUB_VF }, // 2018 |
21176 | | { PseudoVFNMSUB_VFPR16_M1_MASK, VFNMSUB_VF }, // 2019 |
21177 | | { PseudoVFNMSUB_VFPR16_M2, VFNMSUB_VF }, // 2020 |
21178 | | { PseudoVFNMSUB_VFPR16_M2_MASK, VFNMSUB_VF }, // 2021 |
21179 | | { PseudoVFNMSUB_VFPR16_M4, VFNMSUB_VF }, // 2022 |
21180 | | { PseudoVFNMSUB_VFPR16_M4_MASK, VFNMSUB_VF }, // 2023 |
21181 | | { PseudoVFNMSUB_VFPR16_M8, VFNMSUB_VF }, // 2024 |
21182 | | { PseudoVFNMSUB_VFPR16_M8_MASK, VFNMSUB_VF }, // 2025 |
21183 | | { PseudoVFNMSUB_VFPR16_MF2, VFNMSUB_VF }, // 2026 |
21184 | | { PseudoVFNMSUB_VFPR16_MF2_MASK, VFNMSUB_VF }, // 2027 |
21185 | | { PseudoVFNMSUB_VFPR16_MF4, VFNMSUB_VF }, // 2028 |
21186 | | { PseudoVFNMSUB_VFPR16_MF4_MASK, VFNMSUB_VF }, // 2029 |
21187 | | { PseudoVFNMSUB_VFPR32_M1, VFNMSUB_VF }, // 2030 |
21188 | | { PseudoVFNMSUB_VFPR32_M1_MASK, VFNMSUB_VF }, // 2031 |
21189 | | { PseudoVFNMSUB_VFPR32_M2, VFNMSUB_VF }, // 2032 |
21190 | | { PseudoVFNMSUB_VFPR32_M2_MASK, VFNMSUB_VF }, // 2033 |
21191 | | { PseudoVFNMSUB_VFPR32_M4, VFNMSUB_VF }, // 2034 |
21192 | | { PseudoVFNMSUB_VFPR32_M4_MASK, VFNMSUB_VF }, // 2035 |
21193 | | { PseudoVFNMSUB_VFPR32_M8, VFNMSUB_VF }, // 2036 |
21194 | | { PseudoVFNMSUB_VFPR32_M8_MASK, VFNMSUB_VF }, // 2037 |
21195 | | { PseudoVFNMSUB_VFPR32_MF2, VFNMSUB_VF }, // 2038 |
21196 | | { PseudoVFNMSUB_VFPR32_MF2_MASK, VFNMSUB_VF }, // 2039 |
21197 | | { PseudoVFNMSUB_VFPR64_M1, VFNMSUB_VF }, // 2040 |
21198 | | { PseudoVFNMSUB_VFPR64_M1_MASK, VFNMSUB_VF }, // 2041 |
21199 | | { PseudoVFNMSUB_VFPR64_M2, VFNMSUB_VF }, // 2042 |
21200 | | { PseudoVFNMSUB_VFPR64_M2_MASK, VFNMSUB_VF }, // 2043 |
21201 | | { PseudoVFNMSUB_VFPR64_M4, VFNMSUB_VF }, // 2044 |
21202 | | { PseudoVFNMSUB_VFPR64_M4_MASK, VFNMSUB_VF }, // 2045 |
21203 | | { PseudoVFNMSUB_VFPR64_M8, VFNMSUB_VF }, // 2046 |
21204 | | { PseudoVFNMSUB_VFPR64_M8_MASK, VFNMSUB_VF }, // 2047 |
21205 | | { PseudoVFNMSUB_VV_M1, VFNMSUB_VV }, // 2048 |
21206 | | { PseudoVFNMSUB_VV_M1_MASK, VFNMSUB_VV }, // 2049 |
21207 | | { PseudoVFNMSUB_VV_M2, VFNMSUB_VV }, // 2050 |
21208 | | { PseudoVFNMSUB_VV_M2_MASK, VFNMSUB_VV }, // 2051 |
21209 | | { PseudoVFNMSUB_VV_M4, VFNMSUB_VV }, // 2052 |
21210 | | { PseudoVFNMSUB_VV_M4_MASK, VFNMSUB_VV }, // 2053 |
21211 | | { PseudoVFNMSUB_VV_M8, VFNMSUB_VV }, // 2054 |
21212 | | { PseudoVFNMSUB_VV_M8_MASK, VFNMSUB_VV }, // 2055 |
21213 | | { PseudoVFNMSUB_VV_MF2, VFNMSUB_VV }, // 2056 |
21214 | | { PseudoVFNMSUB_VV_MF2_MASK, VFNMSUB_VV }, // 2057 |
21215 | | { PseudoVFNMSUB_VV_MF4, VFNMSUB_VV }, // 2058 |
21216 | | { PseudoVFNMSUB_VV_MF4_MASK, VFNMSUB_VV }, // 2059 |
21217 | | { PseudoVFNRCLIP_XU_F_QF_M1, VFNRCLIP_XU_F_QF }, // 2060 |
21218 | | { PseudoVFNRCLIP_XU_F_QF_M1_MASK, VFNRCLIP_XU_F_QF }, // 2061 |
21219 | | { PseudoVFNRCLIP_XU_F_QF_M2, VFNRCLIP_XU_F_QF }, // 2062 |
21220 | | { PseudoVFNRCLIP_XU_F_QF_M2_MASK, VFNRCLIP_XU_F_QF }, // 2063 |
21221 | | { PseudoVFNRCLIP_XU_F_QF_MF2, VFNRCLIP_XU_F_QF }, // 2064 |
21222 | | { PseudoVFNRCLIP_XU_F_QF_MF2_MASK, VFNRCLIP_XU_F_QF }, // 2065 |
21223 | | { PseudoVFNRCLIP_XU_F_QF_MF4, VFNRCLIP_XU_F_QF }, // 2066 |
21224 | | { PseudoVFNRCLIP_XU_F_QF_MF4_MASK, VFNRCLIP_XU_F_QF }, // 2067 |
21225 | | { PseudoVFNRCLIP_XU_F_QF_MF8, VFNRCLIP_XU_F_QF }, // 2068 |
21226 | | { PseudoVFNRCLIP_XU_F_QF_MF8_MASK, VFNRCLIP_XU_F_QF }, // 2069 |
21227 | | { PseudoVFNRCLIP_X_F_QF_M1, VFNRCLIP_X_F_QF }, // 2070 |
21228 | | { PseudoVFNRCLIP_X_F_QF_M1_MASK, VFNRCLIP_X_F_QF }, // 2071 |
21229 | | { PseudoVFNRCLIP_X_F_QF_M2, VFNRCLIP_X_F_QF }, // 2072 |
21230 | | { PseudoVFNRCLIP_X_F_QF_M2_MASK, VFNRCLIP_X_F_QF }, // 2073 |
21231 | | { PseudoVFNRCLIP_X_F_QF_MF2, VFNRCLIP_X_F_QF }, // 2074 |
21232 | | { PseudoVFNRCLIP_X_F_QF_MF2_MASK, VFNRCLIP_X_F_QF }, // 2075 |
21233 | | { PseudoVFNRCLIP_X_F_QF_MF4, VFNRCLIP_X_F_QF }, // 2076 |
21234 | | { PseudoVFNRCLIP_X_F_QF_MF4_MASK, VFNRCLIP_X_F_QF }, // 2077 |
21235 | | { PseudoVFNRCLIP_X_F_QF_MF8, VFNRCLIP_X_F_QF }, // 2078 |
21236 | | { PseudoVFNRCLIP_X_F_QF_MF8_MASK, VFNRCLIP_X_F_QF }, // 2079 |
21237 | | { PseudoVFRDIV_VFPR16_M1_E16, VFRDIV_VF }, // 2080 |
21238 | | { PseudoVFRDIV_VFPR16_M1_E16_MASK, VFRDIV_VF }, // 2081 |
21239 | | { PseudoVFRDIV_VFPR16_M2_E16, VFRDIV_VF }, // 2082 |
21240 | | { PseudoVFRDIV_VFPR16_M2_E16_MASK, VFRDIV_VF }, // 2083 |
21241 | | { PseudoVFRDIV_VFPR16_M4_E16, VFRDIV_VF }, // 2084 |
21242 | | { PseudoVFRDIV_VFPR16_M4_E16_MASK, VFRDIV_VF }, // 2085 |
21243 | | { PseudoVFRDIV_VFPR16_M8_E16, VFRDIV_VF }, // 2086 |
21244 | | { PseudoVFRDIV_VFPR16_M8_E16_MASK, VFRDIV_VF }, // 2087 |
21245 | | { PseudoVFRDIV_VFPR16_MF2_E16, VFRDIV_VF }, // 2088 |
21246 | | { PseudoVFRDIV_VFPR16_MF2_E16_MASK, VFRDIV_VF }, // 2089 |
21247 | | { PseudoVFRDIV_VFPR16_MF4_E16, VFRDIV_VF }, // 2090 |
21248 | | { PseudoVFRDIV_VFPR16_MF4_E16_MASK, VFRDIV_VF }, // 2091 |
21249 | | { PseudoVFRDIV_VFPR32_M1_E32, VFRDIV_VF }, // 2092 |
21250 | | { PseudoVFRDIV_VFPR32_M1_E32_MASK, VFRDIV_VF }, // 2093 |
21251 | | { PseudoVFRDIV_VFPR32_M2_E32, VFRDIV_VF }, // 2094 |
21252 | | { PseudoVFRDIV_VFPR32_M2_E32_MASK, VFRDIV_VF }, // 2095 |
21253 | | { PseudoVFRDIV_VFPR32_M4_E32, VFRDIV_VF }, // 2096 |
21254 | | { PseudoVFRDIV_VFPR32_M4_E32_MASK, VFRDIV_VF }, // 2097 |
21255 | | { PseudoVFRDIV_VFPR32_M8_E32, VFRDIV_VF }, // 2098 |
21256 | | { PseudoVFRDIV_VFPR32_M8_E32_MASK, VFRDIV_VF }, // 2099 |
21257 | | { PseudoVFRDIV_VFPR32_MF2_E32, VFRDIV_VF }, // 2100 |
21258 | | { PseudoVFRDIV_VFPR32_MF2_E32_MASK, VFRDIV_VF }, // 2101 |
21259 | | { PseudoVFRDIV_VFPR64_M1_E64, VFRDIV_VF }, // 2102 |
21260 | | { PseudoVFRDIV_VFPR64_M1_E64_MASK, VFRDIV_VF }, // 2103 |
21261 | | { PseudoVFRDIV_VFPR64_M2_E64, VFRDIV_VF }, // 2104 |
21262 | | { PseudoVFRDIV_VFPR64_M2_E64_MASK, VFRDIV_VF }, // 2105 |
21263 | | { PseudoVFRDIV_VFPR64_M4_E64, VFRDIV_VF }, // 2106 |
21264 | | { PseudoVFRDIV_VFPR64_M4_E64_MASK, VFRDIV_VF }, // 2107 |
21265 | | { PseudoVFRDIV_VFPR64_M8_E64, VFRDIV_VF }, // 2108 |
21266 | | { PseudoVFRDIV_VFPR64_M8_E64_MASK, VFRDIV_VF }, // 2109 |
21267 | | { PseudoVFREC7_V_M1, VFREC7_V }, // 2110 |
21268 | | { PseudoVFREC7_V_M1_MASK, VFREC7_V }, // 2111 |
21269 | | { PseudoVFREC7_V_M2, VFREC7_V }, // 2112 |
21270 | | { PseudoVFREC7_V_M2_MASK, VFREC7_V }, // 2113 |
21271 | | { PseudoVFREC7_V_M4, VFREC7_V }, // 2114 |
21272 | | { PseudoVFREC7_V_M4_MASK, VFREC7_V }, // 2115 |
21273 | | { PseudoVFREC7_V_M8, VFREC7_V }, // 2116 |
21274 | | { PseudoVFREC7_V_M8_MASK, VFREC7_V }, // 2117 |
21275 | | { PseudoVFREC7_V_MF2, VFREC7_V }, // 2118 |
21276 | | { PseudoVFREC7_V_MF2_MASK, VFREC7_V }, // 2119 |
21277 | | { PseudoVFREC7_V_MF4, VFREC7_V }, // 2120 |
21278 | | { PseudoVFREC7_V_MF4_MASK, VFREC7_V }, // 2121 |
21279 | | { PseudoVFREDMAX_VS_M1_E16, VFREDMAX_VS }, // 2122 |
21280 | | { PseudoVFREDMAX_VS_M1_E16_MASK, VFREDMAX_VS }, // 2123 |
21281 | | { PseudoVFREDMAX_VS_M1_E32, VFREDMAX_VS }, // 2124 |
21282 | | { PseudoVFREDMAX_VS_M1_E32_MASK, VFREDMAX_VS }, // 2125 |
21283 | | { PseudoVFREDMAX_VS_M1_E64, VFREDMAX_VS }, // 2126 |
21284 | | { PseudoVFREDMAX_VS_M1_E64_MASK, VFREDMAX_VS }, // 2127 |
21285 | | { PseudoVFREDMAX_VS_M2_E16, VFREDMAX_VS }, // 2128 |
21286 | | { PseudoVFREDMAX_VS_M2_E16_MASK, VFREDMAX_VS }, // 2129 |
21287 | | { PseudoVFREDMAX_VS_M2_E32, VFREDMAX_VS }, // 2130 |
21288 | | { PseudoVFREDMAX_VS_M2_E32_MASK, VFREDMAX_VS }, // 2131 |
21289 | | { PseudoVFREDMAX_VS_M2_E64, VFREDMAX_VS }, // 2132 |
21290 | | { PseudoVFREDMAX_VS_M2_E64_MASK, VFREDMAX_VS }, // 2133 |
21291 | | { PseudoVFREDMAX_VS_M4_E16, VFREDMAX_VS }, // 2134 |
21292 | | { PseudoVFREDMAX_VS_M4_E16_MASK, VFREDMAX_VS }, // 2135 |
21293 | | { PseudoVFREDMAX_VS_M4_E32, VFREDMAX_VS }, // 2136 |
21294 | | { PseudoVFREDMAX_VS_M4_E32_MASK, VFREDMAX_VS }, // 2137 |
21295 | | { PseudoVFREDMAX_VS_M4_E64, VFREDMAX_VS }, // 2138 |
21296 | | { PseudoVFREDMAX_VS_M4_E64_MASK, VFREDMAX_VS }, // 2139 |
21297 | | { PseudoVFREDMAX_VS_M8_E16, VFREDMAX_VS }, // 2140 |
21298 | | { PseudoVFREDMAX_VS_M8_E16_MASK, VFREDMAX_VS }, // 2141 |
21299 | | { PseudoVFREDMAX_VS_M8_E32, VFREDMAX_VS }, // 2142 |
21300 | | { PseudoVFREDMAX_VS_M8_E32_MASK, VFREDMAX_VS }, // 2143 |
21301 | | { PseudoVFREDMAX_VS_M8_E64, VFREDMAX_VS }, // 2144 |
21302 | | { PseudoVFREDMAX_VS_M8_E64_MASK, VFREDMAX_VS }, // 2145 |
21303 | | { PseudoVFREDMAX_VS_MF2_E16, VFREDMAX_VS }, // 2146 |
21304 | | { PseudoVFREDMAX_VS_MF2_E16_MASK, VFREDMAX_VS }, // 2147 |
21305 | | { PseudoVFREDMAX_VS_MF2_E32, VFREDMAX_VS }, // 2148 |
21306 | | { PseudoVFREDMAX_VS_MF2_E32_MASK, VFREDMAX_VS }, // 2149 |
21307 | | { PseudoVFREDMAX_VS_MF4_E16, VFREDMAX_VS }, // 2150 |
21308 | | { PseudoVFREDMAX_VS_MF4_E16_MASK, VFREDMAX_VS }, // 2151 |
21309 | | { PseudoVFREDMIN_VS_M1_E16, VFREDMIN_VS }, // 2152 |
21310 | | { PseudoVFREDMIN_VS_M1_E16_MASK, VFREDMIN_VS }, // 2153 |
21311 | | { PseudoVFREDMIN_VS_M1_E32, VFREDMIN_VS }, // 2154 |
21312 | | { PseudoVFREDMIN_VS_M1_E32_MASK, VFREDMIN_VS }, // 2155 |
21313 | | { PseudoVFREDMIN_VS_M1_E64, VFREDMIN_VS }, // 2156 |
21314 | | { PseudoVFREDMIN_VS_M1_E64_MASK, VFREDMIN_VS }, // 2157 |
21315 | | { PseudoVFREDMIN_VS_M2_E16, VFREDMIN_VS }, // 2158 |
21316 | | { PseudoVFREDMIN_VS_M2_E16_MASK, VFREDMIN_VS }, // 2159 |
21317 | | { PseudoVFREDMIN_VS_M2_E32, VFREDMIN_VS }, // 2160 |
21318 | | { PseudoVFREDMIN_VS_M2_E32_MASK, VFREDMIN_VS }, // 2161 |
21319 | | { PseudoVFREDMIN_VS_M2_E64, VFREDMIN_VS }, // 2162 |
21320 | | { PseudoVFREDMIN_VS_M2_E64_MASK, VFREDMIN_VS }, // 2163 |
21321 | | { PseudoVFREDMIN_VS_M4_E16, VFREDMIN_VS }, // 2164 |
21322 | | { PseudoVFREDMIN_VS_M4_E16_MASK, VFREDMIN_VS }, // 2165 |
21323 | | { PseudoVFREDMIN_VS_M4_E32, VFREDMIN_VS }, // 2166 |
21324 | | { PseudoVFREDMIN_VS_M4_E32_MASK, VFREDMIN_VS }, // 2167 |
21325 | | { PseudoVFREDMIN_VS_M4_E64, VFREDMIN_VS }, // 2168 |
21326 | | { PseudoVFREDMIN_VS_M4_E64_MASK, VFREDMIN_VS }, // 2169 |
21327 | | { PseudoVFREDMIN_VS_M8_E16, VFREDMIN_VS }, // 2170 |
21328 | | { PseudoVFREDMIN_VS_M8_E16_MASK, VFREDMIN_VS }, // 2171 |
21329 | | { PseudoVFREDMIN_VS_M8_E32, VFREDMIN_VS }, // 2172 |
21330 | | { PseudoVFREDMIN_VS_M8_E32_MASK, VFREDMIN_VS }, // 2173 |
21331 | | { PseudoVFREDMIN_VS_M8_E64, VFREDMIN_VS }, // 2174 |
21332 | | { PseudoVFREDMIN_VS_M8_E64_MASK, VFREDMIN_VS }, // 2175 |
21333 | | { PseudoVFREDMIN_VS_MF2_E16, VFREDMIN_VS }, // 2176 |
21334 | | { PseudoVFREDMIN_VS_MF2_E16_MASK, VFREDMIN_VS }, // 2177 |
21335 | | { PseudoVFREDMIN_VS_MF2_E32, VFREDMIN_VS }, // 2178 |
21336 | | { PseudoVFREDMIN_VS_MF2_E32_MASK, VFREDMIN_VS }, // 2179 |
21337 | | { PseudoVFREDMIN_VS_MF4_E16, VFREDMIN_VS }, // 2180 |
21338 | | { PseudoVFREDMIN_VS_MF4_E16_MASK, VFREDMIN_VS }, // 2181 |
21339 | | { PseudoVFREDOSUM_VS_M1_E16, VFREDOSUM_VS }, // 2182 |
21340 | | { PseudoVFREDOSUM_VS_M1_E16_MASK, VFREDOSUM_VS }, // 2183 |
21341 | | { PseudoVFREDOSUM_VS_M1_E32, VFREDOSUM_VS }, // 2184 |
21342 | | { PseudoVFREDOSUM_VS_M1_E32_MASK, VFREDOSUM_VS }, // 2185 |
21343 | | { PseudoVFREDOSUM_VS_M1_E64, VFREDOSUM_VS }, // 2186 |
21344 | | { PseudoVFREDOSUM_VS_M1_E64_MASK, VFREDOSUM_VS }, // 2187 |
21345 | | { PseudoVFREDOSUM_VS_M2_E16, VFREDOSUM_VS }, // 2188 |
21346 | | { PseudoVFREDOSUM_VS_M2_E16_MASK, VFREDOSUM_VS }, // 2189 |
21347 | | { PseudoVFREDOSUM_VS_M2_E32, VFREDOSUM_VS }, // 2190 |
21348 | | { PseudoVFREDOSUM_VS_M2_E32_MASK, VFREDOSUM_VS }, // 2191 |
21349 | | { PseudoVFREDOSUM_VS_M2_E64, VFREDOSUM_VS }, // 2192 |
21350 | | { PseudoVFREDOSUM_VS_M2_E64_MASK, VFREDOSUM_VS }, // 2193 |
21351 | | { PseudoVFREDOSUM_VS_M4_E16, VFREDOSUM_VS }, // 2194 |
21352 | | { PseudoVFREDOSUM_VS_M4_E16_MASK, VFREDOSUM_VS }, // 2195 |
21353 | | { PseudoVFREDOSUM_VS_M4_E32, VFREDOSUM_VS }, // 2196 |
21354 | | { PseudoVFREDOSUM_VS_M4_E32_MASK, VFREDOSUM_VS }, // 2197 |
21355 | | { PseudoVFREDOSUM_VS_M4_E64, VFREDOSUM_VS }, // 2198 |
21356 | | { PseudoVFREDOSUM_VS_M4_E64_MASK, VFREDOSUM_VS }, // 2199 |
21357 | | { PseudoVFREDOSUM_VS_M8_E16, VFREDOSUM_VS }, // 2200 |
21358 | | { PseudoVFREDOSUM_VS_M8_E16_MASK, VFREDOSUM_VS }, // 2201 |
21359 | | { PseudoVFREDOSUM_VS_M8_E32, VFREDOSUM_VS }, // 2202 |
21360 | | { PseudoVFREDOSUM_VS_M8_E32_MASK, VFREDOSUM_VS }, // 2203 |
21361 | | { PseudoVFREDOSUM_VS_M8_E64, VFREDOSUM_VS }, // 2204 |
21362 | | { PseudoVFREDOSUM_VS_M8_E64_MASK, VFREDOSUM_VS }, // 2205 |
21363 | | { PseudoVFREDOSUM_VS_MF2_E16, VFREDOSUM_VS }, // 2206 |
21364 | | { PseudoVFREDOSUM_VS_MF2_E16_MASK, VFREDOSUM_VS }, // 2207 |
21365 | | { PseudoVFREDOSUM_VS_MF2_E32, VFREDOSUM_VS }, // 2208 |
21366 | | { PseudoVFREDOSUM_VS_MF2_E32_MASK, VFREDOSUM_VS }, // 2209 |
21367 | | { PseudoVFREDOSUM_VS_MF4_E16, VFREDOSUM_VS }, // 2210 |
21368 | | { PseudoVFREDOSUM_VS_MF4_E16_MASK, VFREDOSUM_VS }, // 2211 |
21369 | | { PseudoVFREDUSUM_VS_M1_E16, VFREDUSUM_VS }, // 2212 |
21370 | | { PseudoVFREDUSUM_VS_M1_E16_MASK, VFREDUSUM_VS }, // 2213 |
21371 | | { PseudoVFREDUSUM_VS_M1_E32, VFREDUSUM_VS }, // 2214 |
21372 | | { PseudoVFREDUSUM_VS_M1_E32_MASK, VFREDUSUM_VS }, // 2215 |
21373 | | { PseudoVFREDUSUM_VS_M1_E64, VFREDUSUM_VS }, // 2216 |
21374 | | { PseudoVFREDUSUM_VS_M1_E64_MASK, VFREDUSUM_VS }, // 2217 |
21375 | | { PseudoVFREDUSUM_VS_M2_E16, VFREDUSUM_VS }, // 2218 |
21376 | | { PseudoVFREDUSUM_VS_M2_E16_MASK, VFREDUSUM_VS }, // 2219 |
21377 | | { PseudoVFREDUSUM_VS_M2_E32, VFREDUSUM_VS }, // 2220 |
21378 | | { PseudoVFREDUSUM_VS_M2_E32_MASK, VFREDUSUM_VS }, // 2221 |
21379 | | { PseudoVFREDUSUM_VS_M2_E64, VFREDUSUM_VS }, // 2222 |
21380 | | { PseudoVFREDUSUM_VS_M2_E64_MASK, VFREDUSUM_VS }, // 2223 |
21381 | | { PseudoVFREDUSUM_VS_M4_E16, VFREDUSUM_VS }, // 2224 |
21382 | | { PseudoVFREDUSUM_VS_M4_E16_MASK, VFREDUSUM_VS }, // 2225 |
21383 | | { PseudoVFREDUSUM_VS_M4_E32, VFREDUSUM_VS }, // 2226 |
21384 | | { PseudoVFREDUSUM_VS_M4_E32_MASK, VFREDUSUM_VS }, // 2227 |
21385 | | { PseudoVFREDUSUM_VS_M4_E64, VFREDUSUM_VS }, // 2228 |
21386 | | { PseudoVFREDUSUM_VS_M4_E64_MASK, VFREDUSUM_VS }, // 2229 |
21387 | | { PseudoVFREDUSUM_VS_M8_E16, VFREDUSUM_VS }, // 2230 |
21388 | | { PseudoVFREDUSUM_VS_M8_E16_MASK, VFREDUSUM_VS }, // 2231 |
21389 | | { PseudoVFREDUSUM_VS_M8_E32, VFREDUSUM_VS }, // 2232 |
21390 | | { PseudoVFREDUSUM_VS_M8_E32_MASK, VFREDUSUM_VS }, // 2233 |
21391 | | { PseudoVFREDUSUM_VS_M8_E64, VFREDUSUM_VS }, // 2234 |
21392 | | { PseudoVFREDUSUM_VS_M8_E64_MASK, VFREDUSUM_VS }, // 2235 |
21393 | | { PseudoVFREDUSUM_VS_MF2_E16, VFREDUSUM_VS }, // 2236 |
21394 | | { PseudoVFREDUSUM_VS_MF2_E16_MASK, VFREDUSUM_VS }, // 2237 |
21395 | | { PseudoVFREDUSUM_VS_MF2_E32, VFREDUSUM_VS }, // 2238 |
21396 | | { PseudoVFREDUSUM_VS_MF2_E32_MASK, VFREDUSUM_VS }, // 2239 |
21397 | | { PseudoVFREDUSUM_VS_MF4_E16, VFREDUSUM_VS }, // 2240 |
21398 | | { PseudoVFREDUSUM_VS_MF4_E16_MASK, VFREDUSUM_VS }, // 2241 |
21399 | | { PseudoVFRSQRT7_V_M1, VFRSQRT7_V }, // 2242 |
21400 | | { PseudoVFRSQRT7_V_M1_MASK, VFRSQRT7_V }, // 2243 |
21401 | | { PseudoVFRSQRT7_V_M2, VFRSQRT7_V }, // 2244 |
21402 | | { PseudoVFRSQRT7_V_M2_MASK, VFRSQRT7_V }, // 2245 |
21403 | | { PseudoVFRSQRT7_V_M4, VFRSQRT7_V }, // 2246 |
21404 | | { PseudoVFRSQRT7_V_M4_MASK, VFRSQRT7_V }, // 2247 |
21405 | | { PseudoVFRSQRT7_V_M8, VFRSQRT7_V }, // 2248 |
21406 | | { PseudoVFRSQRT7_V_M8_MASK, VFRSQRT7_V }, // 2249 |
21407 | | { PseudoVFRSQRT7_V_MF2, VFRSQRT7_V }, // 2250 |
21408 | | { PseudoVFRSQRT7_V_MF2_MASK, VFRSQRT7_V }, // 2251 |
21409 | | { PseudoVFRSQRT7_V_MF4, VFRSQRT7_V }, // 2252 |
21410 | | { PseudoVFRSQRT7_V_MF4_MASK, VFRSQRT7_V }, // 2253 |
21411 | | { PseudoVFRSUB_VFPR16_M1, VFRSUB_VF }, // 2254 |
21412 | | { PseudoVFRSUB_VFPR16_M1_MASK, VFRSUB_VF }, // 2255 |
21413 | | { PseudoVFRSUB_VFPR16_M2, VFRSUB_VF }, // 2256 |
21414 | | { PseudoVFRSUB_VFPR16_M2_MASK, VFRSUB_VF }, // 2257 |
21415 | | { PseudoVFRSUB_VFPR16_M4, VFRSUB_VF }, // 2258 |
21416 | | { PseudoVFRSUB_VFPR16_M4_MASK, VFRSUB_VF }, // 2259 |
21417 | | { PseudoVFRSUB_VFPR16_M8, VFRSUB_VF }, // 2260 |
21418 | | { PseudoVFRSUB_VFPR16_M8_MASK, VFRSUB_VF }, // 2261 |
21419 | | { PseudoVFRSUB_VFPR16_MF2, VFRSUB_VF }, // 2262 |
21420 | | { PseudoVFRSUB_VFPR16_MF2_MASK, VFRSUB_VF }, // 2263 |
21421 | | { PseudoVFRSUB_VFPR16_MF4, VFRSUB_VF }, // 2264 |
21422 | | { PseudoVFRSUB_VFPR16_MF4_MASK, VFRSUB_VF }, // 2265 |
21423 | | { PseudoVFRSUB_VFPR32_M1, VFRSUB_VF }, // 2266 |
21424 | | { PseudoVFRSUB_VFPR32_M1_MASK, VFRSUB_VF }, // 2267 |
21425 | | { PseudoVFRSUB_VFPR32_M2, VFRSUB_VF }, // 2268 |
21426 | | { PseudoVFRSUB_VFPR32_M2_MASK, VFRSUB_VF }, // 2269 |
21427 | | { PseudoVFRSUB_VFPR32_M4, VFRSUB_VF }, // 2270 |
21428 | | { PseudoVFRSUB_VFPR32_M4_MASK, VFRSUB_VF }, // 2271 |
21429 | | { PseudoVFRSUB_VFPR32_M8, VFRSUB_VF }, // 2272 |
21430 | | { PseudoVFRSUB_VFPR32_M8_MASK, VFRSUB_VF }, // 2273 |
21431 | | { PseudoVFRSUB_VFPR32_MF2, VFRSUB_VF }, // 2274 |
21432 | | { PseudoVFRSUB_VFPR32_MF2_MASK, VFRSUB_VF }, // 2275 |
21433 | | { PseudoVFRSUB_VFPR64_M1, VFRSUB_VF }, // 2276 |
21434 | | { PseudoVFRSUB_VFPR64_M1_MASK, VFRSUB_VF }, // 2277 |
21435 | | { PseudoVFRSUB_VFPR64_M2, VFRSUB_VF }, // 2278 |
21436 | | { PseudoVFRSUB_VFPR64_M2_MASK, VFRSUB_VF }, // 2279 |
21437 | | { PseudoVFRSUB_VFPR64_M4, VFRSUB_VF }, // 2280 |
21438 | | { PseudoVFRSUB_VFPR64_M4_MASK, VFRSUB_VF }, // 2281 |
21439 | | { PseudoVFRSUB_VFPR64_M8, VFRSUB_VF }, // 2282 |
21440 | | { PseudoVFRSUB_VFPR64_M8_MASK, VFRSUB_VF }, // 2283 |
21441 | | { PseudoVFSGNJN_VFPR16_M1, VFSGNJN_VF }, // 2284 |
21442 | | { PseudoVFSGNJN_VFPR16_M1_MASK, VFSGNJN_VF }, // 2285 |
21443 | | { PseudoVFSGNJN_VFPR16_M2, VFSGNJN_VF }, // 2286 |
21444 | | { PseudoVFSGNJN_VFPR16_M2_MASK, VFSGNJN_VF }, // 2287 |
21445 | | { PseudoVFSGNJN_VFPR16_M4, VFSGNJN_VF }, // 2288 |
21446 | | { PseudoVFSGNJN_VFPR16_M4_MASK, VFSGNJN_VF }, // 2289 |
21447 | | { PseudoVFSGNJN_VFPR16_M8, VFSGNJN_VF }, // 2290 |
21448 | | { PseudoVFSGNJN_VFPR16_M8_MASK, VFSGNJN_VF }, // 2291 |
21449 | | { PseudoVFSGNJN_VFPR16_MF2, VFSGNJN_VF }, // 2292 |
21450 | | { PseudoVFSGNJN_VFPR16_MF2_MASK, VFSGNJN_VF }, // 2293 |
21451 | | { PseudoVFSGNJN_VFPR16_MF4, VFSGNJN_VF }, // 2294 |
21452 | | { PseudoVFSGNJN_VFPR16_MF4_MASK, VFSGNJN_VF }, // 2295 |
21453 | | { PseudoVFSGNJN_VFPR32_M1, VFSGNJN_VF }, // 2296 |
21454 | | { PseudoVFSGNJN_VFPR32_M1_MASK, VFSGNJN_VF }, // 2297 |
21455 | | { PseudoVFSGNJN_VFPR32_M2, VFSGNJN_VF }, // 2298 |
21456 | | { PseudoVFSGNJN_VFPR32_M2_MASK, VFSGNJN_VF }, // 2299 |
21457 | | { PseudoVFSGNJN_VFPR32_M4, VFSGNJN_VF }, // 2300 |
21458 | | { PseudoVFSGNJN_VFPR32_M4_MASK, VFSGNJN_VF }, // 2301 |
21459 | | { PseudoVFSGNJN_VFPR32_M8, VFSGNJN_VF }, // 2302 |
21460 | | { PseudoVFSGNJN_VFPR32_M8_MASK, VFSGNJN_VF }, // 2303 |
21461 | | { PseudoVFSGNJN_VFPR32_MF2, VFSGNJN_VF }, // 2304 |
21462 | | { PseudoVFSGNJN_VFPR32_MF2_MASK, VFSGNJN_VF }, // 2305 |
21463 | | { PseudoVFSGNJN_VFPR64_M1, VFSGNJN_VF }, // 2306 |
21464 | | { PseudoVFSGNJN_VFPR64_M1_MASK, VFSGNJN_VF }, // 2307 |
21465 | | { PseudoVFSGNJN_VFPR64_M2, VFSGNJN_VF }, // 2308 |
21466 | | { PseudoVFSGNJN_VFPR64_M2_MASK, VFSGNJN_VF }, // 2309 |
21467 | | { PseudoVFSGNJN_VFPR64_M4, VFSGNJN_VF }, // 2310 |
21468 | | { PseudoVFSGNJN_VFPR64_M4_MASK, VFSGNJN_VF }, // 2311 |
21469 | | { PseudoVFSGNJN_VFPR64_M8, VFSGNJN_VF }, // 2312 |
21470 | | { PseudoVFSGNJN_VFPR64_M8_MASK, VFSGNJN_VF }, // 2313 |
21471 | | { PseudoVFSGNJN_VV_M1, VFSGNJN_VV }, // 2314 |
21472 | | { PseudoVFSGNJN_VV_M1_MASK, VFSGNJN_VV }, // 2315 |
21473 | | { PseudoVFSGNJN_VV_M2, VFSGNJN_VV }, // 2316 |
21474 | | { PseudoVFSGNJN_VV_M2_MASK, VFSGNJN_VV }, // 2317 |
21475 | | { PseudoVFSGNJN_VV_M4, VFSGNJN_VV }, // 2318 |
21476 | | { PseudoVFSGNJN_VV_M4_MASK, VFSGNJN_VV }, // 2319 |
21477 | | { PseudoVFSGNJN_VV_M8, VFSGNJN_VV }, // 2320 |
21478 | | { PseudoVFSGNJN_VV_M8_MASK, VFSGNJN_VV }, // 2321 |
21479 | | { PseudoVFSGNJN_VV_MF2, VFSGNJN_VV }, // 2322 |
21480 | | { PseudoVFSGNJN_VV_MF2_MASK, VFSGNJN_VV }, // 2323 |
21481 | | { PseudoVFSGNJN_VV_MF4, VFSGNJN_VV }, // 2324 |
21482 | | { PseudoVFSGNJN_VV_MF4_MASK, VFSGNJN_VV }, // 2325 |
21483 | | { PseudoVFSGNJX_VFPR16_M1, VFSGNJX_VF }, // 2326 |
21484 | | { PseudoVFSGNJX_VFPR16_M1_MASK, VFSGNJX_VF }, // 2327 |
21485 | | { PseudoVFSGNJX_VFPR16_M2, VFSGNJX_VF }, // 2328 |
21486 | | { PseudoVFSGNJX_VFPR16_M2_MASK, VFSGNJX_VF }, // 2329 |
21487 | | { PseudoVFSGNJX_VFPR16_M4, VFSGNJX_VF }, // 2330 |
21488 | | { PseudoVFSGNJX_VFPR16_M4_MASK, VFSGNJX_VF }, // 2331 |
21489 | | { PseudoVFSGNJX_VFPR16_M8, VFSGNJX_VF }, // 2332 |
21490 | | { PseudoVFSGNJX_VFPR16_M8_MASK, VFSGNJX_VF }, // 2333 |
21491 | | { PseudoVFSGNJX_VFPR16_MF2, VFSGNJX_VF }, // 2334 |
21492 | | { PseudoVFSGNJX_VFPR16_MF2_MASK, VFSGNJX_VF }, // 2335 |
21493 | | { PseudoVFSGNJX_VFPR16_MF4, VFSGNJX_VF }, // 2336 |
21494 | | { PseudoVFSGNJX_VFPR16_MF4_MASK, VFSGNJX_VF }, // 2337 |
21495 | | { PseudoVFSGNJX_VFPR32_M1, VFSGNJX_VF }, // 2338 |
21496 | | { PseudoVFSGNJX_VFPR32_M1_MASK, VFSGNJX_VF }, // 2339 |
21497 | | { PseudoVFSGNJX_VFPR32_M2, VFSGNJX_VF }, // 2340 |
21498 | | { PseudoVFSGNJX_VFPR32_M2_MASK, VFSGNJX_VF }, // 2341 |
21499 | | { PseudoVFSGNJX_VFPR32_M4, VFSGNJX_VF }, // 2342 |
21500 | | { PseudoVFSGNJX_VFPR32_M4_MASK, VFSGNJX_VF }, // 2343 |
21501 | | { PseudoVFSGNJX_VFPR32_M8, VFSGNJX_VF }, // 2344 |
21502 | | { PseudoVFSGNJX_VFPR32_M8_MASK, VFSGNJX_VF }, // 2345 |
21503 | | { PseudoVFSGNJX_VFPR32_MF2, VFSGNJX_VF }, // 2346 |
21504 | | { PseudoVFSGNJX_VFPR32_MF2_MASK, VFSGNJX_VF }, // 2347 |
21505 | | { PseudoVFSGNJX_VFPR64_M1, VFSGNJX_VF }, // 2348 |
21506 | | { PseudoVFSGNJX_VFPR64_M1_MASK, VFSGNJX_VF }, // 2349 |
21507 | | { PseudoVFSGNJX_VFPR64_M2, VFSGNJX_VF }, // 2350 |
21508 | | { PseudoVFSGNJX_VFPR64_M2_MASK, VFSGNJX_VF }, // 2351 |
21509 | | { PseudoVFSGNJX_VFPR64_M4, VFSGNJX_VF }, // 2352 |
21510 | | { PseudoVFSGNJX_VFPR64_M4_MASK, VFSGNJX_VF }, // 2353 |
21511 | | { PseudoVFSGNJX_VFPR64_M8, VFSGNJX_VF }, // 2354 |
21512 | | { PseudoVFSGNJX_VFPR64_M8_MASK, VFSGNJX_VF }, // 2355 |
21513 | | { PseudoVFSGNJX_VV_M1, VFSGNJX_VV }, // 2356 |
21514 | | { PseudoVFSGNJX_VV_M1_MASK, VFSGNJX_VV }, // 2357 |
21515 | | { PseudoVFSGNJX_VV_M2, VFSGNJX_VV }, // 2358 |
21516 | | { PseudoVFSGNJX_VV_M2_MASK, VFSGNJX_VV }, // 2359 |
21517 | | { PseudoVFSGNJX_VV_M4, VFSGNJX_VV }, // 2360 |
21518 | | { PseudoVFSGNJX_VV_M4_MASK, VFSGNJX_VV }, // 2361 |
21519 | | { PseudoVFSGNJX_VV_M8, VFSGNJX_VV }, // 2362 |
21520 | | { PseudoVFSGNJX_VV_M8_MASK, VFSGNJX_VV }, // 2363 |
21521 | | { PseudoVFSGNJX_VV_MF2, VFSGNJX_VV }, // 2364 |
21522 | | { PseudoVFSGNJX_VV_MF2_MASK, VFSGNJX_VV }, // 2365 |
21523 | | { PseudoVFSGNJX_VV_MF4, VFSGNJX_VV }, // 2366 |
21524 | | { PseudoVFSGNJX_VV_MF4_MASK, VFSGNJX_VV }, // 2367 |
21525 | | { PseudoVFSGNJ_VFPR16_M1, VFSGNJ_VF }, // 2368 |
21526 | | { PseudoVFSGNJ_VFPR16_M1_MASK, VFSGNJ_VF }, // 2369 |
21527 | | { PseudoVFSGNJ_VFPR16_M2, VFSGNJ_VF }, // 2370 |
21528 | | { PseudoVFSGNJ_VFPR16_M2_MASK, VFSGNJ_VF }, // 2371 |
21529 | | { PseudoVFSGNJ_VFPR16_M4, VFSGNJ_VF }, // 2372 |
21530 | | { PseudoVFSGNJ_VFPR16_M4_MASK, VFSGNJ_VF }, // 2373 |
21531 | | { PseudoVFSGNJ_VFPR16_M8, VFSGNJ_VF }, // 2374 |
21532 | | { PseudoVFSGNJ_VFPR16_M8_MASK, VFSGNJ_VF }, // 2375 |
21533 | | { PseudoVFSGNJ_VFPR16_MF2, VFSGNJ_VF }, // 2376 |
21534 | | { PseudoVFSGNJ_VFPR16_MF2_MASK, VFSGNJ_VF }, // 2377 |
21535 | | { PseudoVFSGNJ_VFPR16_MF4, VFSGNJ_VF }, // 2378 |
21536 | | { PseudoVFSGNJ_VFPR16_MF4_MASK, VFSGNJ_VF }, // 2379 |
21537 | | { PseudoVFSGNJ_VFPR32_M1, VFSGNJ_VF }, // 2380 |
21538 | | { PseudoVFSGNJ_VFPR32_M1_MASK, VFSGNJ_VF }, // 2381 |
21539 | | { PseudoVFSGNJ_VFPR32_M2, VFSGNJ_VF }, // 2382 |
21540 | | { PseudoVFSGNJ_VFPR32_M2_MASK, VFSGNJ_VF }, // 2383 |
21541 | | { PseudoVFSGNJ_VFPR32_M4, VFSGNJ_VF }, // 2384 |
21542 | | { PseudoVFSGNJ_VFPR32_M4_MASK, VFSGNJ_VF }, // 2385 |
21543 | | { PseudoVFSGNJ_VFPR32_M8, VFSGNJ_VF }, // 2386 |
21544 | | { PseudoVFSGNJ_VFPR32_M8_MASK, VFSGNJ_VF }, // 2387 |
21545 | | { PseudoVFSGNJ_VFPR32_MF2, VFSGNJ_VF }, // 2388 |
21546 | | { PseudoVFSGNJ_VFPR32_MF2_MASK, VFSGNJ_VF }, // 2389 |
21547 | | { PseudoVFSGNJ_VFPR64_M1, VFSGNJ_VF }, // 2390 |
21548 | | { PseudoVFSGNJ_VFPR64_M1_MASK, VFSGNJ_VF }, // 2391 |
21549 | | { PseudoVFSGNJ_VFPR64_M2, VFSGNJ_VF }, // 2392 |
21550 | | { PseudoVFSGNJ_VFPR64_M2_MASK, VFSGNJ_VF }, // 2393 |
21551 | | { PseudoVFSGNJ_VFPR64_M4, VFSGNJ_VF }, // 2394 |
21552 | | { PseudoVFSGNJ_VFPR64_M4_MASK, VFSGNJ_VF }, // 2395 |
21553 | | { PseudoVFSGNJ_VFPR64_M8, VFSGNJ_VF }, // 2396 |
21554 | | { PseudoVFSGNJ_VFPR64_M8_MASK, VFSGNJ_VF }, // 2397 |
21555 | | { PseudoVFSGNJ_VV_M1, VFSGNJ_VV }, // 2398 |
21556 | | { PseudoVFSGNJ_VV_M1_MASK, VFSGNJ_VV }, // 2399 |
21557 | | { PseudoVFSGNJ_VV_M2, VFSGNJ_VV }, // 2400 |
21558 | | { PseudoVFSGNJ_VV_M2_MASK, VFSGNJ_VV }, // 2401 |
21559 | | { PseudoVFSGNJ_VV_M4, VFSGNJ_VV }, // 2402 |
21560 | | { PseudoVFSGNJ_VV_M4_MASK, VFSGNJ_VV }, // 2403 |
21561 | | { PseudoVFSGNJ_VV_M8, VFSGNJ_VV }, // 2404 |
21562 | | { PseudoVFSGNJ_VV_M8_MASK, VFSGNJ_VV }, // 2405 |
21563 | | { PseudoVFSGNJ_VV_MF2, VFSGNJ_VV }, // 2406 |
21564 | | { PseudoVFSGNJ_VV_MF2_MASK, VFSGNJ_VV }, // 2407 |
21565 | | { PseudoVFSGNJ_VV_MF4, VFSGNJ_VV }, // 2408 |
21566 | | { PseudoVFSGNJ_VV_MF4_MASK, VFSGNJ_VV }, // 2409 |
21567 | | { PseudoVFSLIDE1DOWN_VFPR16_M1, VFSLIDE1DOWN_VF }, // 2410 |
21568 | | { PseudoVFSLIDE1DOWN_VFPR16_M1_MASK, VFSLIDE1DOWN_VF }, // 2411 |
21569 | | { PseudoVFSLIDE1DOWN_VFPR16_M2, VFSLIDE1DOWN_VF }, // 2412 |
21570 | | { PseudoVFSLIDE1DOWN_VFPR16_M2_MASK, VFSLIDE1DOWN_VF }, // 2413 |
21571 | | { PseudoVFSLIDE1DOWN_VFPR16_M4, VFSLIDE1DOWN_VF }, // 2414 |
21572 | | { PseudoVFSLIDE1DOWN_VFPR16_M4_MASK, VFSLIDE1DOWN_VF }, // 2415 |
21573 | | { PseudoVFSLIDE1DOWN_VFPR16_M8, VFSLIDE1DOWN_VF }, // 2416 |
21574 | | { PseudoVFSLIDE1DOWN_VFPR16_M8_MASK, VFSLIDE1DOWN_VF }, // 2417 |
21575 | | { PseudoVFSLIDE1DOWN_VFPR16_MF2, VFSLIDE1DOWN_VF }, // 2418 |
21576 | | { PseudoVFSLIDE1DOWN_VFPR16_MF2_MASK, VFSLIDE1DOWN_VF }, // 2419 |
21577 | | { PseudoVFSLIDE1DOWN_VFPR16_MF4, VFSLIDE1DOWN_VF }, // 2420 |
21578 | | { PseudoVFSLIDE1DOWN_VFPR16_MF4_MASK, VFSLIDE1DOWN_VF }, // 2421 |
21579 | | { PseudoVFSLIDE1DOWN_VFPR32_M1, VFSLIDE1DOWN_VF }, // 2422 |
21580 | | { PseudoVFSLIDE1DOWN_VFPR32_M1_MASK, VFSLIDE1DOWN_VF }, // 2423 |
21581 | | { PseudoVFSLIDE1DOWN_VFPR32_M2, VFSLIDE1DOWN_VF }, // 2424 |
21582 | | { PseudoVFSLIDE1DOWN_VFPR32_M2_MASK, VFSLIDE1DOWN_VF }, // 2425 |
21583 | | { PseudoVFSLIDE1DOWN_VFPR32_M4, VFSLIDE1DOWN_VF }, // 2426 |
21584 | | { PseudoVFSLIDE1DOWN_VFPR32_M4_MASK, VFSLIDE1DOWN_VF }, // 2427 |
21585 | | { PseudoVFSLIDE1DOWN_VFPR32_M8, VFSLIDE1DOWN_VF }, // 2428 |
21586 | | { PseudoVFSLIDE1DOWN_VFPR32_M8_MASK, VFSLIDE1DOWN_VF }, // 2429 |
21587 | | { PseudoVFSLIDE1DOWN_VFPR32_MF2, VFSLIDE1DOWN_VF }, // 2430 |
21588 | | { PseudoVFSLIDE1DOWN_VFPR32_MF2_MASK, VFSLIDE1DOWN_VF }, // 2431 |
21589 | | { PseudoVFSLIDE1DOWN_VFPR64_M1, VFSLIDE1DOWN_VF }, // 2432 |
21590 | | { PseudoVFSLIDE1DOWN_VFPR64_M1_MASK, VFSLIDE1DOWN_VF }, // 2433 |
21591 | | { PseudoVFSLIDE1DOWN_VFPR64_M2, VFSLIDE1DOWN_VF }, // 2434 |
21592 | | { PseudoVFSLIDE1DOWN_VFPR64_M2_MASK, VFSLIDE1DOWN_VF }, // 2435 |
21593 | | { PseudoVFSLIDE1DOWN_VFPR64_M4, VFSLIDE1DOWN_VF }, // 2436 |
21594 | | { PseudoVFSLIDE1DOWN_VFPR64_M4_MASK, VFSLIDE1DOWN_VF }, // 2437 |
21595 | | { PseudoVFSLIDE1DOWN_VFPR64_M8, VFSLIDE1DOWN_VF }, // 2438 |
21596 | | { PseudoVFSLIDE1DOWN_VFPR64_M8_MASK, VFSLIDE1DOWN_VF }, // 2439 |
21597 | | { PseudoVFSLIDE1UP_VFPR16_M1, VFSLIDE1UP_VF }, // 2440 |
21598 | | { PseudoVFSLIDE1UP_VFPR16_M1_MASK, VFSLIDE1UP_VF }, // 2441 |
21599 | | { PseudoVFSLIDE1UP_VFPR16_M2, VFSLIDE1UP_VF }, // 2442 |
21600 | | { PseudoVFSLIDE1UP_VFPR16_M2_MASK, VFSLIDE1UP_VF }, // 2443 |
21601 | | { PseudoVFSLIDE1UP_VFPR16_M4, VFSLIDE1UP_VF }, // 2444 |
21602 | | { PseudoVFSLIDE1UP_VFPR16_M4_MASK, VFSLIDE1UP_VF }, // 2445 |
21603 | | { PseudoVFSLIDE1UP_VFPR16_M8, VFSLIDE1UP_VF }, // 2446 |
21604 | | { PseudoVFSLIDE1UP_VFPR16_M8_MASK, VFSLIDE1UP_VF }, // 2447 |
21605 | | { PseudoVFSLIDE1UP_VFPR16_MF2, VFSLIDE1UP_VF }, // 2448 |
21606 | | { PseudoVFSLIDE1UP_VFPR16_MF2_MASK, VFSLIDE1UP_VF }, // 2449 |
21607 | | { PseudoVFSLIDE1UP_VFPR16_MF4, VFSLIDE1UP_VF }, // 2450 |
21608 | | { PseudoVFSLIDE1UP_VFPR16_MF4_MASK, VFSLIDE1UP_VF }, // 2451 |
21609 | | { PseudoVFSLIDE1UP_VFPR32_M1, VFSLIDE1UP_VF }, // 2452 |
21610 | | { PseudoVFSLIDE1UP_VFPR32_M1_MASK, VFSLIDE1UP_VF }, // 2453 |
21611 | | { PseudoVFSLIDE1UP_VFPR32_M2, VFSLIDE1UP_VF }, // 2454 |
21612 | | { PseudoVFSLIDE1UP_VFPR32_M2_MASK, VFSLIDE1UP_VF }, // 2455 |
21613 | | { PseudoVFSLIDE1UP_VFPR32_M4, VFSLIDE1UP_VF }, // 2456 |
21614 | | { PseudoVFSLIDE1UP_VFPR32_M4_MASK, VFSLIDE1UP_VF }, // 2457 |
21615 | | { PseudoVFSLIDE1UP_VFPR32_M8, VFSLIDE1UP_VF }, // 2458 |
21616 | | { PseudoVFSLIDE1UP_VFPR32_M8_MASK, VFSLIDE1UP_VF }, // 2459 |
21617 | | { PseudoVFSLIDE1UP_VFPR32_MF2, VFSLIDE1UP_VF }, // 2460 |
21618 | | { PseudoVFSLIDE1UP_VFPR32_MF2_MASK, VFSLIDE1UP_VF }, // 2461 |
21619 | | { PseudoVFSLIDE1UP_VFPR64_M1, VFSLIDE1UP_VF }, // 2462 |
21620 | | { PseudoVFSLIDE1UP_VFPR64_M1_MASK, VFSLIDE1UP_VF }, // 2463 |
21621 | | { PseudoVFSLIDE1UP_VFPR64_M2, VFSLIDE1UP_VF }, // 2464 |
21622 | | { PseudoVFSLIDE1UP_VFPR64_M2_MASK, VFSLIDE1UP_VF }, // 2465 |
21623 | | { PseudoVFSLIDE1UP_VFPR64_M4, VFSLIDE1UP_VF }, // 2466 |
21624 | | { PseudoVFSLIDE1UP_VFPR64_M4_MASK, VFSLIDE1UP_VF }, // 2467 |
21625 | | { PseudoVFSLIDE1UP_VFPR64_M8, VFSLIDE1UP_VF }, // 2468 |
21626 | | { PseudoVFSLIDE1UP_VFPR64_M8_MASK, VFSLIDE1UP_VF }, // 2469 |
21627 | | { PseudoVFSQRT_V_M1_E16, VFSQRT_V }, // 2470 |
21628 | | { PseudoVFSQRT_V_M1_E16_MASK, VFSQRT_V }, // 2471 |
21629 | | { PseudoVFSQRT_V_M1_E32, VFSQRT_V }, // 2472 |
21630 | | { PseudoVFSQRT_V_M1_E32_MASK, VFSQRT_V }, // 2473 |
21631 | | { PseudoVFSQRT_V_M1_E64, VFSQRT_V }, // 2474 |
21632 | | { PseudoVFSQRT_V_M1_E64_MASK, VFSQRT_V }, // 2475 |
21633 | | { PseudoVFSQRT_V_M2_E16, VFSQRT_V }, // 2476 |
21634 | | { PseudoVFSQRT_V_M2_E16_MASK, VFSQRT_V }, // 2477 |
21635 | | { PseudoVFSQRT_V_M2_E32, VFSQRT_V }, // 2478 |
21636 | | { PseudoVFSQRT_V_M2_E32_MASK, VFSQRT_V }, // 2479 |
21637 | | { PseudoVFSQRT_V_M2_E64, VFSQRT_V }, // 2480 |
21638 | | { PseudoVFSQRT_V_M2_E64_MASK, VFSQRT_V }, // 2481 |
21639 | | { PseudoVFSQRT_V_M4_E16, VFSQRT_V }, // 2482 |
21640 | | { PseudoVFSQRT_V_M4_E16_MASK, VFSQRT_V }, // 2483 |
21641 | | { PseudoVFSQRT_V_M4_E32, VFSQRT_V }, // 2484 |
21642 | | { PseudoVFSQRT_V_M4_E32_MASK, VFSQRT_V }, // 2485 |
21643 | | { PseudoVFSQRT_V_M4_E64, VFSQRT_V }, // 2486 |
21644 | | { PseudoVFSQRT_V_M4_E64_MASK, VFSQRT_V }, // 2487 |
21645 | | { PseudoVFSQRT_V_M8_E16, VFSQRT_V }, // 2488 |
21646 | | { PseudoVFSQRT_V_M8_E16_MASK, VFSQRT_V }, // 2489 |
21647 | | { PseudoVFSQRT_V_M8_E32, VFSQRT_V }, // 2490 |
21648 | | { PseudoVFSQRT_V_M8_E32_MASK, VFSQRT_V }, // 2491 |
21649 | | { PseudoVFSQRT_V_M8_E64, VFSQRT_V }, // 2492 |
21650 | | { PseudoVFSQRT_V_M8_E64_MASK, VFSQRT_V }, // 2493 |
21651 | | { PseudoVFSQRT_V_MF2_E16, VFSQRT_V }, // 2494 |
21652 | | { PseudoVFSQRT_V_MF2_E16_MASK, VFSQRT_V }, // 2495 |
21653 | | { PseudoVFSQRT_V_MF2_E32, VFSQRT_V }, // 2496 |
21654 | | { PseudoVFSQRT_V_MF2_E32_MASK, VFSQRT_V }, // 2497 |
21655 | | { PseudoVFSQRT_V_MF4_E16, VFSQRT_V }, // 2498 |
21656 | | { PseudoVFSQRT_V_MF4_E16_MASK, VFSQRT_V }, // 2499 |
21657 | | { PseudoVFSUB_VFPR16_M1, VFSUB_VF }, // 2500 |
21658 | | { PseudoVFSUB_VFPR16_M1_MASK, VFSUB_VF }, // 2501 |
21659 | | { PseudoVFSUB_VFPR16_M2, VFSUB_VF }, // 2502 |
21660 | | { PseudoVFSUB_VFPR16_M2_MASK, VFSUB_VF }, // 2503 |
21661 | | { PseudoVFSUB_VFPR16_M4, VFSUB_VF }, // 2504 |
21662 | | { PseudoVFSUB_VFPR16_M4_MASK, VFSUB_VF }, // 2505 |
21663 | | { PseudoVFSUB_VFPR16_M8, VFSUB_VF }, // 2506 |
21664 | | { PseudoVFSUB_VFPR16_M8_MASK, VFSUB_VF }, // 2507 |
21665 | | { PseudoVFSUB_VFPR16_MF2, VFSUB_VF }, // 2508 |
21666 | | { PseudoVFSUB_VFPR16_MF2_MASK, VFSUB_VF }, // 2509 |
21667 | | { PseudoVFSUB_VFPR16_MF4, VFSUB_VF }, // 2510 |
21668 | | { PseudoVFSUB_VFPR16_MF4_MASK, VFSUB_VF }, // 2511 |
21669 | | { PseudoVFSUB_VFPR32_M1, VFSUB_VF }, // 2512 |
21670 | | { PseudoVFSUB_VFPR32_M1_MASK, VFSUB_VF }, // 2513 |
21671 | | { PseudoVFSUB_VFPR32_M2, VFSUB_VF }, // 2514 |
21672 | | { PseudoVFSUB_VFPR32_M2_MASK, VFSUB_VF }, // 2515 |
21673 | | { PseudoVFSUB_VFPR32_M4, VFSUB_VF }, // 2516 |
21674 | | { PseudoVFSUB_VFPR32_M4_MASK, VFSUB_VF }, // 2517 |
21675 | | { PseudoVFSUB_VFPR32_M8, VFSUB_VF }, // 2518 |
21676 | | { PseudoVFSUB_VFPR32_M8_MASK, VFSUB_VF }, // 2519 |
21677 | | { PseudoVFSUB_VFPR32_MF2, VFSUB_VF }, // 2520 |
21678 | | { PseudoVFSUB_VFPR32_MF2_MASK, VFSUB_VF }, // 2521 |
21679 | | { PseudoVFSUB_VFPR64_M1, VFSUB_VF }, // 2522 |
21680 | | { PseudoVFSUB_VFPR64_M1_MASK, VFSUB_VF }, // 2523 |
21681 | | { PseudoVFSUB_VFPR64_M2, VFSUB_VF }, // 2524 |
21682 | | { PseudoVFSUB_VFPR64_M2_MASK, VFSUB_VF }, // 2525 |
21683 | | { PseudoVFSUB_VFPR64_M4, VFSUB_VF }, // 2526 |
21684 | | { PseudoVFSUB_VFPR64_M4_MASK, VFSUB_VF }, // 2527 |
21685 | | { PseudoVFSUB_VFPR64_M8, VFSUB_VF }, // 2528 |
21686 | | { PseudoVFSUB_VFPR64_M8_MASK, VFSUB_VF }, // 2529 |
21687 | | { PseudoVFSUB_VV_M1, VFSUB_VV }, // 2530 |
21688 | | { PseudoVFSUB_VV_M1_MASK, VFSUB_VV }, // 2531 |
21689 | | { PseudoVFSUB_VV_M2, VFSUB_VV }, // 2532 |
21690 | | { PseudoVFSUB_VV_M2_MASK, VFSUB_VV }, // 2533 |
21691 | | { PseudoVFSUB_VV_M4, VFSUB_VV }, // 2534 |
21692 | | { PseudoVFSUB_VV_M4_MASK, VFSUB_VV }, // 2535 |
21693 | | { PseudoVFSUB_VV_M8, VFSUB_VV }, // 2536 |
21694 | | { PseudoVFSUB_VV_M8_MASK, VFSUB_VV }, // 2537 |
21695 | | { PseudoVFSUB_VV_MF2, VFSUB_VV }, // 2538 |
21696 | | { PseudoVFSUB_VV_MF2_MASK, VFSUB_VV }, // 2539 |
21697 | | { PseudoVFSUB_VV_MF4, VFSUB_VV }, // 2540 |
21698 | | { PseudoVFSUB_VV_MF4_MASK, VFSUB_VV }, // 2541 |
21699 | | { PseudoVFWADD_VFPR16_M1, VFWADD_VF }, // 2542 |
21700 | | { PseudoVFWADD_VFPR16_M1_MASK, VFWADD_VF }, // 2543 |
21701 | | { PseudoVFWADD_VFPR16_M2, VFWADD_VF }, // 2544 |
21702 | | { PseudoVFWADD_VFPR16_M2_MASK, VFWADD_VF }, // 2545 |
21703 | | { PseudoVFWADD_VFPR16_M4, VFWADD_VF }, // 2546 |
21704 | | { PseudoVFWADD_VFPR16_M4_MASK, VFWADD_VF }, // 2547 |
21705 | | { PseudoVFWADD_VFPR16_MF2, VFWADD_VF }, // 2548 |
21706 | | { PseudoVFWADD_VFPR16_MF2_MASK, VFWADD_VF }, // 2549 |
21707 | | { PseudoVFWADD_VFPR16_MF4, VFWADD_VF }, // 2550 |
21708 | | { PseudoVFWADD_VFPR16_MF4_MASK, VFWADD_VF }, // 2551 |
21709 | | { PseudoVFWADD_VFPR32_M1, VFWADD_VF }, // 2552 |
21710 | | { PseudoVFWADD_VFPR32_M1_MASK, VFWADD_VF }, // 2553 |
21711 | | { PseudoVFWADD_VFPR32_M2, VFWADD_VF }, // 2554 |
21712 | | { PseudoVFWADD_VFPR32_M2_MASK, VFWADD_VF }, // 2555 |
21713 | | { PseudoVFWADD_VFPR32_M4, VFWADD_VF }, // 2556 |
21714 | | { PseudoVFWADD_VFPR32_M4_MASK, VFWADD_VF }, // 2557 |
21715 | | { PseudoVFWADD_VFPR32_MF2, VFWADD_VF }, // 2558 |
21716 | | { PseudoVFWADD_VFPR32_MF2_MASK, VFWADD_VF }, // 2559 |
21717 | | { PseudoVFWADD_VV_M1, VFWADD_VV }, // 2560 |
21718 | | { PseudoVFWADD_VV_M1_MASK, VFWADD_VV }, // 2561 |
21719 | | { PseudoVFWADD_VV_M2, VFWADD_VV }, // 2562 |
21720 | | { PseudoVFWADD_VV_M2_MASK, VFWADD_VV }, // 2563 |
21721 | | { PseudoVFWADD_VV_M4, VFWADD_VV }, // 2564 |
21722 | | { PseudoVFWADD_VV_M4_MASK, VFWADD_VV }, // 2565 |
21723 | | { PseudoVFWADD_VV_MF2, VFWADD_VV }, // 2566 |
21724 | | { PseudoVFWADD_VV_MF2_MASK, VFWADD_VV }, // 2567 |
21725 | | { PseudoVFWADD_VV_MF4, VFWADD_VV }, // 2568 |
21726 | | { PseudoVFWADD_VV_MF4_MASK, VFWADD_VV }, // 2569 |
21727 | | { PseudoVFWADD_WFPR16_M1, VFWADD_WF }, // 2570 |
21728 | | { PseudoVFWADD_WFPR16_M1_MASK, VFWADD_WF }, // 2571 |
21729 | | { PseudoVFWADD_WFPR16_M2, VFWADD_WF }, // 2572 |
21730 | | { PseudoVFWADD_WFPR16_M2_MASK, VFWADD_WF }, // 2573 |
21731 | | { PseudoVFWADD_WFPR16_M4, VFWADD_WF }, // 2574 |
21732 | | { PseudoVFWADD_WFPR16_M4_MASK, VFWADD_WF }, // 2575 |
21733 | | { PseudoVFWADD_WFPR16_MF2, VFWADD_WF }, // 2576 |
21734 | | { PseudoVFWADD_WFPR16_MF2_MASK, VFWADD_WF }, // 2577 |
21735 | | { PseudoVFWADD_WFPR16_MF4, VFWADD_WF }, // 2578 |
21736 | | { PseudoVFWADD_WFPR16_MF4_MASK, VFWADD_WF }, // 2579 |
21737 | | { PseudoVFWADD_WFPR32_M1, VFWADD_WF }, // 2580 |
21738 | | { PseudoVFWADD_WFPR32_M1_MASK, VFWADD_WF }, // 2581 |
21739 | | { PseudoVFWADD_WFPR32_M2, VFWADD_WF }, // 2582 |
21740 | | { PseudoVFWADD_WFPR32_M2_MASK, VFWADD_WF }, // 2583 |
21741 | | { PseudoVFWADD_WFPR32_M4, VFWADD_WF }, // 2584 |
21742 | | { PseudoVFWADD_WFPR32_M4_MASK, VFWADD_WF }, // 2585 |
21743 | | { PseudoVFWADD_WFPR32_MF2, VFWADD_WF }, // 2586 |
21744 | | { PseudoVFWADD_WFPR32_MF2_MASK, VFWADD_WF }, // 2587 |
21745 | | { PseudoVFWADD_WV_M1, VFWADD_WV }, // 2588 |
21746 | | { PseudoVFWADD_WV_M1_MASK, VFWADD_WV }, // 2589 |
21747 | | { PseudoVFWADD_WV_M1_MASK_TIED, VFWADD_WV }, // 2590 |
21748 | | { PseudoVFWADD_WV_M1_TIED, VFWADD_WV }, // 2591 |
21749 | | { PseudoVFWADD_WV_M2, VFWADD_WV }, // 2592 |
21750 | | { PseudoVFWADD_WV_M2_MASK, VFWADD_WV }, // 2593 |
21751 | | { PseudoVFWADD_WV_M2_MASK_TIED, VFWADD_WV }, // 2594 |
21752 | | { PseudoVFWADD_WV_M2_TIED, VFWADD_WV }, // 2595 |
21753 | | { PseudoVFWADD_WV_M4, VFWADD_WV }, // 2596 |
21754 | | { PseudoVFWADD_WV_M4_MASK, VFWADD_WV }, // 2597 |
21755 | | { PseudoVFWADD_WV_M4_MASK_TIED, VFWADD_WV }, // 2598 |
21756 | | { PseudoVFWADD_WV_M4_TIED, VFWADD_WV }, // 2599 |
21757 | | { PseudoVFWADD_WV_MF2, VFWADD_WV }, // 2600 |
21758 | | { PseudoVFWADD_WV_MF2_MASK, VFWADD_WV }, // 2601 |
21759 | | { PseudoVFWADD_WV_MF2_MASK_TIED, VFWADD_WV }, // 2602 |
21760 | | { PseudoVFWADD_WV_MF2_TIED, VFWADD_WV }, // 2603 |
21761 | | { PseudoVFWADD_WV_MF4, VFWADD_WV }, // 2604 |
21762 | | { PseudoVFWADD_WV_MF4_MASK, VFWADD_WV }, // 2605 |
21763 | | { PseudoVFWADD_WV_MF4_MASK_TIED, VFWADD_WV }, // 2606 |
21764 | | { PseudoVFWADD_WV_MF4_TIED, VFWADD_WV }, // 2607 |
21765 | | { PseudoVFWCVTBF16_F_F_V_M1, VFWCVTBF16_F_F_V }, // 2608 |
21766 | | { PseudoVFWCVTBF16_F_F_V_M1_MASK, VFWCVTBF16_F_F_V }, // 2609 |
21767 | | { PseudoVFWCVTBF16_F_F_V_M2, VFWCVTBF16_F_F_V }, // 2610 |
21768 | | { PseudoVFWCVTBF16_F_F_V_M2_MASK, VFWCVTBF16_F_F_V }, // 2611 |
21769 | | { PseudoVFWCVTBF16_F_F_V_M4, VFWCVTBF16_F_F_V }, // 2612 |
21770 | | { PseudoVFWCVTBF16_F_F_V_M4_MASK, VFWCVTBF16_F_F_V }, // 2613 |
21771 | | { PseudoVFWCVTBF16_F_F_V_MF2, VFWCVTBF16_F_F_V }, // 2614 |
21772 | | { PseudoVFWCVTBF16_F_F_V_MF2_MASK, VFWCVTBF16_F_F_V }, // 2615 |
21773 | | { PseudoVFWCVTBF16_F_F_V_MF4, VFWCVTBF16_F_F_V }, // 2616 |
21774 | | { PseudoVFWCVTBF16_F_F_V_MF4_MASK, VFWCVTBF16_F_F_V }, // 2617 |
21775 | | { PseudoVFWCVT_F_F_V_M1, VFWCVT_F_F_V }, // 2618 |
21776 | | { PseudoVFWCVT_F_F_V_M1_MASK, VFWCVT_F_F_V }, // 2619 |
21777 | | { PseudoVFWCVT_F_F_V_M2, VFWCVT_F_F_V }, // 2620 |
21778 | | { PseudoVFWCVT_F_F_V_M2_MASK, VFWCVT_F_F_V }, // 2621 |
21779 | | { PseudoVFWCVT_F_F_V_M4, VFWCVT_F_F_V }, // 2622 |
21780 | | { PseudoVFWCVT_F_F_V_M4_MASK, VFWCVT_F_F_V }, // 2623 |
21781 | | { PseudoVFWCVT_F_F_V_MF2, VFWCVT_F_F_V }, // 2624 |
21782 | | { PseudoVFWCVT_F_F_V_MF2_MASK, VFWCVT_F_F_V }, // 2625 |
21783 | | { PseudoVFWCVT_F_F_V_MF4, VFWCVT_F_F_V }, // 2626 |
21784 | | { PseudoVFWCVT_F_F_V_MF4_MASK, VFWCVT_F_F_V }, // 2627 |
21785 | | { PseudoVFWCVT_F_XU_V_M1, VFWCVT_F_XU_V }, // 2628 |
21786 | | { PseudoVFWCVT_F_XU_V_M1_MASK, VFWCVT_F_XU_V }, // 2629 |
21787 | | { PseudoVFWCVT_F_XU_V_M2, VFWCVT_F_XU_V }, // 2630 |
21788 | | { PseudoVFWCVT_F_XU_V_M2_MASK, VFWCVT_F_XU_V }, // 2631 |
21789 | | { PseudoVFWCVT_F_XU_V_M4, VFWCVT_F_XU_V }, // 2632 |
21790 | | { PseudoVFWCVT_F_XU_V_M4_MASK, VFWCVT_F_XU_V }, // 2633 |
21791 | | { PseudoVFWCVT_F_XU_V_MF2, VFWCVT_F_XU_V }, // 2634 |
21792 | | { PseudoVFWCVT_F_XU_V_MF2_MASK, VFWCVT_F_XU_V }, // 2635 |
21793 | | { PseudoVFWCVT_F_XU_V_MF4, VFWCVT_F_XU_V }, // 2636 |
21794 | | { PseudoVFWCVT_F_XU_V_MF4_MASK, VFWCVT_F_XU_V }, // 2637 |
21795 | | { PseudoVFWCVT_F_XU_V_MF8, VFWCVT_F_XU_V }, // 2638 |
21796 | | { PseudoVFWCVT_F_XU_V_MF8_MASK, VFWCVT_F_XU_V }, // 2639 |
21797 | | { PseudoVFWCVT_F_X_V_M1, VFWCVT_F_X_V }, // 2640 |
21798 | | { PseudoVFWCVT_F_X_V_M1_MASK, VFWCVT_F_X_V }, // 2641 |
21799 | | { PseudoVFWCVT_F_X_V_M2, VFWCVT_F_X_V }, // 2642 |
21800 | | { PseudoVFWCVT_F_X_V_M2_MASK, VFWCVT_F_X_V }, // 2643 |
21801 | | { PseudoVFWCVT_F_X_V_M4, VFWCVT_F_X_V }, // 2644 |
21802 | | { PseudoVFWCVT_F_X_V_M4_MASK, VFWCVT_F_X_V }, // 2645 |
21803 | | { PseudoVFWCVT_F_X_V_MF2, VFWCVT_F_X_V }, // 2646 |
21804 | | { PseudoVFWCVT_F_X_V_MF2_MASK, VFWCVT_F_X_V }, // 2647 |
21805 | | { PseudoVFWCVT_F_X_V_MF4, VFWCVT_F_X_V }, // 2648 |
21806 | | { PseudoVFWCVT_F_X_V_MF4_MASK, VFWCVT_F_X_V }, // 2649 |
21807 | | { PseudoVFWCVT_F_X_V_MF8, VFWCVT_F_X_V }, // 2650 |
21808 | | { PseudoVFWCVT_F_X_V_MF8_MASK, VFWCVT_F_X_V }, // 2651 |
21809 | | { PseudoVFWCVT_RM_XU_F_V_M1, VFWCVT_XU_F_V }, // 2652 |
21810 | | { PseudoVFWCVT_RM_XU_F_V_M1_MASK, VFWCVT_XU_F_V }, // 2653 |
21811 | | { PseudoVFWCVT_RM_XU_F_V_M2, VFWCVT_XU_F_V }, // 2654 |
21812 | | { PseudoVFWCVT_RM_XU_F_V_M2_MASK, VFWCVT_XU_F_V }, // 2655 |
21813 | | { PseudoVFWCVT_RM_XU_F_V_M4, VFWCVT_XU_F_V }, // 2656 |
21814 | | { PseudoVFWCVT_RM_XU_F_V_M4_MASK, VFWCVT_XU_F_V }, // 2657 |
21815 | | { PseudoVFWCVT_RM_XU_F_V_MF2, VFWCVT_XU_F_V }, // 2658 |
21816 | | { PseudoVFWCVT_RM_XU_F_V_MF2_MASK, VFWCVT_XU_F_V }, // 2659 |
21817 | | { PseudoVFWCVT_RM_XU_F_V_MF4, VFWCVT_XU_F_V }, // 2660 |
21818 | | { PseudoVFWCVT_RM_XU_F_V_MF4_MASK, VFWCVT_XU_F_V }, // 2661 |
21819 | | { PseudoVFWCVT_RM_X_F_V_M1, VFWCVT_X_F_V }, // 2662 |
21820 | | { PseudoVFWCVT_RM_X_F_V_M1_MASK, VFWCVT_X_F_V }, // 2663 |
21821 | | { PseudoVFWCVT_RM_X_F_V_M2, VFWCVT_X_F_V }, // 2664 |
21822 | | { PseudoVFWCVT_RM_X_F_V_M2_MASK, VFWCVT_X_F_V }, // 2665 |
21823 | | { PseudoVFWCVT_RM_X_F_V_M4, VFWCVT_X_F_V }, // 2666 |
21824 | | { PseudoVFWCVT_RM_X_F_V_M4_MASK, VFWCVT_X_F_V }, // 2667 |
21825 | | { PseudoVFWCVT_RM_X_F_V_MF2, VFWCVT_X_F_V }, // 2668 |
21826 | | { PseudoVFWCVT_RM_X_F_V_MF2_MASK, VFWCVT_X_F_V }, // 2669 |
21827 | | { PseudoVFWCVT_RM_X_F_V_MF4, VFWCVT_X_F_V }, // 2670 |
21828 | | { PseudoVFWCVT_RM_X_F_V_MF4_MASK, VFWCVT_X_F_V }, // 2671 |
21829 | | { PseudoVFWCVT_RTZ_XU_F_V_M1, VFWCVT_RTZ_XU_F_V }, // 2672 |
21830 | | { PseudoVFWCVT_RTZ_XU_F_V_M1_MASK, VFWCVT_RTZ_XU_F_V }, // 2673 |
21831 | | { PseudoVFWCVT_RTZ_XU_F_V_M2, VFWCVT_RTZ_XU_F_V }, // 2674 |
21832 | | { PseudoVFWCVT_RTZ_XU_F_V_M2_MASK, VFWCVT_RTZ_XU_F_V }, // 2675 |
21833 | | { PseudoVFWCVT_RTZ_XU_F_V_M4, VFWCVT_RTZ_XU_F_V }, // 2676 |
21834 | | { PseudoVFWCVT_RTZ_XU_F_V_M4_MASK, VFWCVT_RTZ_XU_F_V }, // 2677 |
21835 | | { PseudoVFWCVT_RTZ_XU_F_V_MF2, VFWCVT_RTZ_XU_F_V }, // 2678 |
21836 | | { PseudoVFWCVT_RTZ_XU_F_V_MF2_MASK, VFWCVT_RTZ_XU_F_V }, // 2679 |
21837 | | { PseudoVFWCVT_RTZ_XU_F_V_MF4, VFWCVT_RTZ_XU_F_V }, // 2680 |
21838 | | { PseudoVFWCVT_RTZ_XU_F_V_MF4_MASK, VFWCVT_RTZ_XU_F_V }, // 2681 |
21839 | | { PseudoVFWCVT_RTZ_X_F_V_M1, VFWCVT_RTZ_X_F_V }, // 2682 |
21840 | | { PseudoVFWCVT_RTZ_X_F_V_M1_MASK, VFWCVT_RTZ_X_F_V }, // 2683 |
21841 | | { PseudoVFWCVT_RTZ_X_F_V_M2, VFWCVT_RTZ_X_F_V }, // 2684 |
21842 | | { PseudoVFWCVT_RTZ_X_F_V_M2_MASK, VFWCVT_RTZ_X_F_V }, // 2685 |
21843 | | { PseudoVFWCVT_RTZ_X_F_V_M4, VFWCVT_RTZ_X_F_V }, // 2686 |
21844 | | { PseudoVFWCVT_RTZ_X_F_V_M4_MASK, VFWCVT_RTZ_X_F_V }, // 2687 |
21845 | | { PseudoVFWCVT_RTZ_X_F_V_MF2, VFWCVT_RTZ_X_F_V }, // 2688 |
21846 | | { PseudoVFWCVT_RTZ_X_F_V_MF2_MASK, VFWCVT_RTZ_X_F_V }, // 2689 |
21847 | | { PseudoVFWCVT_RTZ_X_F_V_MF4, VFWCVT_RTZ_X_F_V }, // 2690 |
21848 | | { PseudoVFWCVT_RTZ_X_F_V_MF4_MASK, VFWCVT_RTZ_X_F_V }, // 2691 |
21849 | | { PseudoVFWCVT_XU_F_V_M1, VFWCVT_XU_F_V }, // 2692 |
21850 | | { PseudoVFWCVT_XU_F_V_M1_MASK, VFWCVT_XU_F_V }, // 2693 |
21851 | | { PseudoVFWCVT_XU_F_V_M2, VFWCVT_XU_F_V }, // 2694 |
21852 | | { PseudoVFWCVT_XU_F_V_M2_MASK, VFWCVT_XU_F_V }, // 2695 |
21853 | | { PseudoVFWCVT_XU_F_V_M4, VFWCVT_XU_F_V }, // 2696 |
21854 | | { PseudoVFWCVT_XU_F_V_M4_MASK, VFWCVT_XU_F_V }, // 2697 |
21855 | | { PseudoVFWCVT_XU_F_V_MF2, VFWCVT_XU_F_V }, // 2698 |
21856 | | { PseudoVFWCVT_XU_F_V_MF2_MASK, VFWCVT_XU_F_V }, // 2699 |
21857 | | { PseudoVFWCVT_XU_F_V_MF4, VFWCVT_XU_F_V }, // 2700 |
21858 | | { PseudoVFWCVT_XU_F_V_MF4_MASK, VFWCVT_XU_F_V }, // 2701 |
21859 | | { PseudoVFWCVT_X_F_V_M1, VFWCVT_X_F_V }, // 2702 |
21860 | | { PseudoVFWCVT_X_F_V_M1_MASK, VFWCVT_X_F_V }, // 2703 |
21861 | | { PseudoVFWCVT_X_F_V_M2, VFWCVT_X_F_V }, // 2704 |
21862 | | { PseudoVFWCVT_X_F_V_M2_MASK, VFWCVT_X_F_V }, // 2705 |
21863 | | { PseudoVFWCVT_X_F_V_M4, VFWCVT_X_F_V }, // 2706 |
21864 | | { PseudoVFWCVT_X_F_V_M4_MASK, VFWCVT_X_F_V }, // 2707 |
21865 | | { PseudoVFWCVT_X_F_V_MF2, VFWCVT_X_F_V }, // 2708 |
21866 | | { PseudoVFWCVT_X_F_V_MF2_MASK, VFWCVT_X_F_V }, // 2709 |
21867 | | { PseudoVFWCVT_X_F_V_MF4, VFWCVT_X_F_V }, // 2710 |
21868 | | { PseudoVFWCVT_X_F_V_MF4_MASK, VFWCVT_X_F_V }, // 2711 |
21869 | | { PseudoVFWMACCBF16_VFPR16_M1, VFWMACCBF16_VF }, // 2712 |
21870 | | { PseudoVFWMACCBF16_VFPR16_M1_MASK, VFWMACCBF16_VF }, // 2713 |
21871 | | { PseudoVFWMACCBF16_VFPR16_M2, VFWMACCBF16_VF }, // 2714 |
21872 | | { PseudoVFWMACCBF16_VFPR16_M2_MASK, VFWMACCBF16_VF }, // 2715 |
21873 | | { PseudoVFWMACCBF16_VFPR16_M4, VFWMACCBF16_VF }, // 2716 |
21874 | | { PseudoVFWMACCBF16_VFPR16_M4_MASK, VFWMACCBF16_VF }, // 2717 |
21875 | | { PseudoVFWMACCBF16_VFPR16_MF2, VFWMACCBF16_VF }, // 2718 |
21876 | | { PseudoVFWMACCBF16_VFPR16_MF2_MASK, VFWMACCBF16_VF }, // 2719 |
21877 | | { PseudoVFWMACCBF16_VFPR16_MF4, VFWMACCBF16_VF }, // 2720 |
21878 | | { PseudoVFWMACCBF16_VFPR16_MF4_MASK, VFWMACCBF16_VF }, // 2721 |
21879 | | { PseudoVFWMACCBF16_VV_M1, VFWMACCBF16_VV }, // 2722 |
21880 | | { PseudoVFWMACCBF16_VV_M1_MASK, VFWMACCBF16_VV }, // 2723 |
21881 | | { PseudoVFWMACCBF16_VV_M2, VFWMACCBF16_VV }, // 2724 |
21882 | | { PseudoVFWMACCBF16_VV_M2_MASK, VFWMACCBF16_VV }, // 2725 |
21883 | | { PseudoVFWMACCBF16_VV_M4, VFWMACCBF16_VV }, // 2726 |
21884 | | { PseudoVFWMACCBF16_VV_M4_MASK, VFWMACCBF16_VV }, // 2727 |
21885 | | { PseudoVFWMACCBF16_VV_MF2, VFWMACCBF16_VV }, // 2728 |
21886 | | { PseudoVFWMACCBF16_VV_MF2_MASK, VFWMACCBF16_VV }, // 2729 |
21887 | | { PseudoVFWMACCBF16_VV_MF4, VFWMACCBF16_VV }, // 2730 |
21888 | | { PseudoVFWMACCBF16_VV_MF4_MASK, VFWMACCBF16_VV }, // 2731 |
21889 | | { PseudoVFWMACC_4x4x4_M1, VFWMACC_4x4x4 }, // 2732 |
21890 | | { PseudoVFWMACC_4x4x4_M2, VFWMACC_4x4x4 }, // 2733 |
21891 | | { PseudoVFWMACC_4x4x4_M4, VFWMACC_4x4x4 }, // 2734 |
21892 | | { PseudoVFWMACC_4x4x4_M8, VFWMACC_4x4x4 }, // 2735 |
21893 | | { PseudoVFWMACC_4x4x4_MF2, VFWMACC_4x4x4 }, // 2736 |
21894 | | { PseudoVFWMACC_4x4x4_MF4, VFWMACC_4x4x4 }, // 2737 |
21895 | | { PseudoVFWMACC_VFPR16_M1, VFWMACC_VF }, // 2738 |
21896 | | { PseudoVFWMACC_VFPR16_M1_MASK, VFWMACC_VF }, // 2739 |
21897 | | { PseudoVFWMACC_VFPR16_M2, VFWMACC_VF }, // 2740 |
21898 | | { PseudoVFWMACC_VFPR16_M2_MASK, VFWMACC_VF }, // 2741 |
21899 | | { PseudoVFWMACC_VFPR16_M4, VFWMACC_VF }, // 2742 |
21900 | | { PseudoVFWMACC_VFPR16_M4_MASK, VFWMACC_VF }, // 2743 |
21901 | | { PseudoVFWMACC_VFPR16_MF2, VFWMACC_VF }, // 2744 |
21902 | | { PseudoVFWMACC_VFPR16_MF2_MASK, VFWMACC_VF }, // 2745 |
21903 | | { PseudoVFWMACC_VFPR16_MF4, VFWMACC_VF }, // 2746 |
21904 | | { PseudoVFWMACC_VFPR16_MF4_MASK, VFWMACC_VF }, // 2747 |
21905 | | { PseudoVFWMACC_VFPR32_M1, VFWMACC_VF }, // 2748 |
21906 | | { PseudoVFWMACC_VFPR32_M1_MASK, VFWMACC_VF }, // 2749 |
21907 | | { PseudoVFWMACC_VFPR32_M2, VFWMACC_VF }, // 2750 |
21908 | | { PseudoVFWMACC_VFPR32_M2_MASK, VFWMACC_VF }, // 2751 |
21909 | | { PseudoVFWMACC_VFPR32_M4, VFWMACC_VF }, // 2752 |
21910 | | { PseudoVFWMACC_VFPR32_M4_MASK, VFWMACC_VF }, // 2753 |
21911 | | { PseudoVFWMACC_VFPR32_MF2, VFWMACC_VF }, // 2754 |
21912 | | { PseudoVFWMACC_VFPR32_MF2_MASK, VFWMACC_VF }, // 2755 |
21913 | | { PseudoVFWMACC_VV_M1, VFWMACC_VV }, // 2756 |
21914 | | { PseudoVFWMACC_VV_M1_MASK, VFWMACC_VV }, // 2757 |
21915 | | { PseudoVFWMACC_VV_M2, VFWMACC_VV }, // 2758 |
21916 | | { PseudoVFWMACC_VV_M2_MASK, VFWMACC_VV }, // 2759 |
21917 | | { PseudoVFWMACC_VV_M4, VFWMACC_VV }, // 2760 |
21918 | | { PseudoVFWMACC_VV_M4_MASK, VFWMACC_VV }, // 2761 |
21919 | | { PseudoVFWMACC_VV_MF2, VFWMACC_VV }, // 2762 |
21920 | | { PseudoVFWMACC_VV_MF2_MASK, VFWMACC_VV }, // 2763 |
21921 | | { PseudoVFWMACC_VV_MF4, VFWMACC_VV }, // 2764 |
21922 | | { PseudoVFWMACC_VV_MF4_MASK, VFWMACC_VV }, // 2765 |
21923 | | { PseudoVFWMSAC_VFPR16_M1, VFWMSAC_VF }, // 2766 |
21924 | | { PseudoVFWMSAC_VFPR16_M1_MASK, VFWMSAC_VF }, // 2767 |
21925 | | { PseudoVFWMSAC_VFPR16_M2, VFWMSAC_VF }, // 2768 |
21926 | | { PseudoVFWMSAC_VFPR16_M2_MASK, VFWMSAC_VF }, // 2769 |
21927 | | { PseudoVFWMSAC_VFPR16_M4, VFWMSAC_VF }, // 2770 |
21928 | | { PseudoVFWMSAC_VFPR16_M4_MASK, VFWMSAC_VF }, // 2771 |
21929 | | { PseudoVFWMSAC_VFPR16_MF2, VFWMSAC_VF }, // 2772 |
21930 | | { PseudoVFWMSAC_VFPR16_MF2_MASK, VFWMSAC_VF }, // 2773 |
21931 | | { PseudoVFWMSAC_VFPR16_MF4, VFWMSAC_VF }, // 2774 |
21932 | | { PseudoVFWMSAC_VFPR16_MF4_MASK, VFWMSAC_VF }, // 2775 |
21933 | | { PseudoVFWMSAC_VFPR32_M1, VFWMSAC_VF }, // 2776 |
21934 | | { PseudoVFWMSAC_VFPR32_M1_MASK, VFWMSAC_VF }, // 2777 |
21935 | | { PseudoVFWMSAC_VFPR32_M2, VFWMSAC_VF }, // 2778 |
21936 | | { PseudoVFWMSAC_VFPR32_M2_MASK, VFWMSAC_VF }, // 2779 |
21937 | | { PseudoVFWMSAC_VFPR32_M4, VFWMSAC_VF }, // 2780 |
21938 | | { PseudoVFWMSAC_VFPR32_M4_MASK, VFWMSAC_VF }, // 2781 |
21939 | | { PseudoVFWMSAC_VFPR32_MF2, VFWMSAC_VF }, // 2782 |
21940 | | { PseudoVFWMSAC_VFPR32_MF2_MASK, VFWMSAC_VF }, // 2783 |
21941 | | { PseudoVFWMSAC_VV_M1, VFWMSAC_VV }, // 2784 |
21942 | | { PseudoVFWMSAC_VV_M1_MASK, VFWMSAC_VV }, // 2785 |
21943 | | { PseudoVFWMSAC_VV_M2, VFWMSAC_VV }, // 2786 |
21944 | | { PseudoVFWMSAC_VV_M2_MASK, VFWMSAC_VV }, // 2787 |
21945 | | { PseudoVFWMSAC_VV_M4, VFWMSAC_VV }, // 2788 |
21946 | | { PseudoVFWMSAC_VV_M4_MASK, VFWMSAC_VV }, // 2789 |
21947 | | { PseudoVFWMSAC_VV_MF2, VFWMSAC_VV }, // 2790 |
21948 | | { PseudoVFWMSAC_VV_MF2_MASK, VFWMSAC_VV }, // 2791 |
21949 | | { PseudoVFWMSAC_VV_MF4, VFWMSAC_VV }, // 2792 |
21950 | | { PseudoVFWMSAC_VV_MF4_MASK, VFWMSAC_VV }, // 2793 |
21951 | | { PseudoVFWMUL_VFPR16_M1, VFWMUL_VF }, // 2794 |
21952 | | { PseudoVFWMUL_VFPR16_M1_MASK, VFWMUL_VF }, // 2795 |
21953 | | { PseudoVFWMUL_VFPR16_M2, VFWMUL_VF }, // 2796 |
21954 | | { PseudoVFWMUL_VFPR16_M2_MASK, VFWMUL_VF }, // 2797 |
21955 | | { PseudoVFWMUL_VFPR16_M4, VFWMUL_VF }, // 2798 |
21956 | | { PseudoVFWMUL_VFPR16_M4_MASK, VFWMUL_VF }, // 2799 |
21957 | | { PseudoVFWMUL_VFPR16_MF2, VFWMUL_VF }, // 2800 |
21958 | | { PseudoVFWMUL_VFPR16_MF2_MASK, VFWMUL_VF }, // 2801 |
21959 | | { PseudoVFWMUL_VFPR16_MF4, VFWMUL_VF }, // 2802 |
21960 | | { PseudoVFWMUL_VFPR16_MF4_MASK, VFWMUL_VF }, // 2803 |
21961 | | { PseudoVFWMUL_VFPR32_M1, VFWMUL_VF }, // 2804 |
21962 | | { PseudoVFWMUL_VFPR32_M1_MASK, VFWMUL_VF }, // 2805 |
21963 | | { PseudoVFWMUL_VFPR32_M2, VFWMUL_VF }, // 2806 |
21964 | | { PseudoVFWMUL_VFPR32_M2_MASK, VFWMUL_VF }, // 2807 |
21965 | | { PseudoVFWMUL_VFPR32_M4, VFWMUL_VF }, // 2808 |
21966 | | { PseudoVFWMUL_VFPR32_M4_MASK, VFWMUL_VF }, // 2809 |
21967 | | { PseudoVFWMUL_VFPR32_MF2, VFWMUL_VF }, // 2810 |
21968 | | { PseudoVFWMUL_VFPR32_MF2_MASK, VFWMUL_VF }, // 2811 |
21969 | | { PseudoVFWMUL_VV_M1, VFWMUL_VV }, // 2812 |
21970 | | { PseudoVFWMUL_VV_M1_MASK, VFWMUL_VV }, // 2813 |
21971 | | { PseudoVFWMUL_VV_M2, VFWMUL_VV }, // 2814 |
21972 | | { PseudoVFWMUL_VV_M2_MASK, VFWMUL_VV }, // 2815 |
21973 | | { PseudoVFWMUL_VV_M4, VFWMUL_VV }, // 2816 |
21974 | | { PseudoVFWMUL_VV_M4_MASK, VFWMUL_VV }, // 2817 |
21975 | | { PseudoVFWMUL_VV_MF2, VFWMUL_VV }, // 2818 |
21976 | | { PseudoVFWMUL_VV_MF2_MASK, VFWMUL_VV }, // 2819 |
21977 | | { PseudoVFWMUL_VV_MF4, VFWMUL_VV }, // 2820 |
21978 | | { PseudoVFWMUL_VV_MF4_MASK, VFWMUL_VV }, // 2821 |
21979 | | { PseudoVFWNMACC_VFPR16_M1, VFWNMACC_VF }, // 2822 |
21980 | | { PseudoVFWNMACC_VFPR16_M1_MASK, VFWNMACC_VF }, // 2823 |
21981 | | { PseudoVFWNMACC_VFPR16_M2, VFWNMACC_VF }, // 2824 |
21982 | | { PseudoVFWNMACC_VFPR16_M2_MASK, VFWNMACC_VF }, // 2825 |
21983 | | { PseudoVFWNMACC_VFPR16_M4, VFWNMACC_VF }, // 2826 |
21984 | | { PseudoVFWNMACC_VFPR16_M4_MASK, VFWNMACC_VF }, // 2827 |
21985 | | { PseudoVFWNMACC_VFPR16_MF2, VFWNMACC_VF }, // 2828 |
21986 | | { PseudoVFWNMACC_VFPR16_MF2_MASK, VFWNMACC_VF }, // 2829 |
21987 | | { PseudoVFWNMACC_VFPR16_MF4, VFWNMACC_VF }, // 2830 |
21988 | | { PseudoVFWNMACC_VFPR16_MF4_MASK, VFWNMACC_VF }, // 2831 |
21989 | | { PseudoVFWNMACC_VFPR32_M1, VFWNMACC_VF }, // 2832 |
21990 | | { PseudoVFWNMACC_VFPR32_M1_MASK, VFWNMACC_VF }, // 2833 |
21991 | | { PseudoVFWNMACC_VFPR32_M2, VFWNMACC_VF }, // 2834 |
21992 | | { PseudoVFWNMACC_VFPR32_M2_MASK, VFWNMACC_VF }, // 2835 |
21993 | | { PseudoVFWNMACC_VFPR32_M4, VFWNMACC_VF }, // 2836 |
21994 | | { PseudoVFWNMACC_VFPR32_M4_MASK, VFWNMACC_VF }, // 2837 |
21995 | | { PseudoVFWNMACC_VFPR32_MF2, VFWNMACC_VF }, // 2838 |
21996 | | { PseudoVFWNMACC_VFPR32_MF2_MASK, VFWNMACC_VF }, // 2839 |
21997 | | { PseudoVFWNMACC_VV_M1, VFWNMACC_VV }, // 2840 |
21998 | | { PseudoVFWNMACC_VV_M1_MASK, VFWNMACC_VV }, // 2841 |
21999 | | { PseudoVFWNMACC_VV_M2, VFWNMACC_VV }, // 2842 |
22000 | | { PseudoVFWNMACC_VV_M2_MASK, VFWNMACC_VV }, // 2843 |
22001 | | { PseudoVFWNMACC_VV_M4, VFWNMACC_VV }, // 2844 |
22002 | | { PseudoVFWNMACC_VV_M4_MASK, VFWNMACC_VV }, // 2845 |
22003 | | { PseudoVFWNMACC_VV_MF2, VFWNMACC_VV }, // 2846 |
22004 | | { PseudoVFWNMACC_VV_MF2_MASK, VFWNMACC_VV }, // 2847 |
22005 | | { PseudoVFWNMACC_VV_MF4, VFWNMACC_VV }, // 2848 |
22006 | | { PseudoVFWNMACC_VV_MF4_MASK, VFWNMACC_VV }, // 2849 |
22007 | | { PseudoVFWNMSAC_VFPR16_M1, VFWNMSAC_VF }, // 2850 |
22008 | | { PseudoVFWNMSAC_VFPR16_M1_MASK, VFWNMSAC_VF }, // 2851 |
22009 | | { PseudoVFWNMSAC_VFPR16_M2, VFWNMSAC_VF }, // 2852 |
22010 | | { PseudoVFWNMSAC_VFPR16_M2_MASK, VFWNMSAC_VF }, // 2853 |
22011 | | { PseudoVFWNMSAC_VFPR16_M4, VFWNMSAC_VF }, // 2854 |
22012 | | { PseudoVFWNMSAC_VFPR16_M4_MASK, VFWNMSAC_VF }, // 2855 |
22013 | | { PseudoVFWNMSAC_VFPR16_MF2, VFWNMSAC_VF }, // 2856 |
22014 | | { PseudoVFWNMSAC_VFPR16_MF2_MASK, VFWNMSAC_VF }, // 2857 |
22015 | | { PseudoVFWNMSAC_VFPR16_MF4, VFWNMSAC_VF }, // 2858 |
22016 | | { PseudoVFWNMSAC_VFPR16_MF4_MASK, VFWNMSAC_VF }, // 2859 |
22017 | | { PseudoVFWNMSAC_VFPR32_M1, VFWNMSAC_VF }, // 2860 |
22018 | | { PseudoVFWNMSAC_VFPR32_M1_MASK, VFWNMSAC_VF }, // 2861 |
22019 | | { PseudoVFWNMSAC_VFPR32_M2, VFWNMSAC_VF }, // 2862 |
22020 | | { PseudoVFWNMSAC_VFPR32_M2_MASK, VFWNMSAC_VF }, // 2863 |
22021 | | { PseudoVFWNMSAC_VFPR32_M4, VFWNMSAC_VF }, // 2864 |
22022 | | { PseudoVFWNMSAC_VFPR32_M4_MASK, VFWNMSAC_VF }, // 2865 |
22023 | | { PseudoVFWNMSAC_VFPR32_MF2, VFWNMSAC_VF }, // 2866 |
22024 | | { PseudoVFWNMSAC_VFPR32_MF2_MASK, VFWNMSAC_VF }, // 2867 |
22025 | | { PseudoVFWNMSAC_VV_M1, VFWNMSAC_VV }, // 2868 |
22026 | | { PseudoVFWNMSAC_VV_M1_MASK, VFWNMSAC_VV }, // 2869 |
22027 | | { PseudoVFWNMSAC_VV_M2, VFWNMSAC_VV }, // 2870 |
22028 | | { PseudoVFWNMSAC_VV_M2_MASK, VFWNMSAC_VV }, // 2871 |
22029 | | { PseudoVFWNMSAC_VV_M4, VFWNMSAC_VV }, // 2872 |
22030 | | { PseudoVFWNMSAC_VV_M4_MASK, VFWNMSAC_VV }, // 2873 |
22031 | | { PseudoVFWNMSAC_VV_MF2, VFWNMSAC_VV }, // 2874 |
22032 | | { PseudoVFWNMSAC_VV_MF2_MASK, VFWNMSAC_VV }, // 2875 |
22033 | | { PseudoVFWNMSAC_VV_MF4, VFWNMSAC_VV }, // 2876 |
22034 | | { PseudoVFWNMSAC_VV_MF4_MASK, VFWNMSAC_VV }, // 2877 |
22035 | | { PseudoVFWREDOSUM_VS_M1_E16, VFWREDOSUM_VS }, // 2878 |
22036 | | { PseudoVFWREDOSUM_VS_M1_E16_MASK, VFWREDOSUM_VS }, // 2879 |
22037 | | { PseudoVFWREDOSUM_VS_M1_E32, VFWREDOSUM_VS }, // 2880 |
22038 | | { PseudoVFWREDOSUM_VS_M1_E32_MASK, VFWREDOSUM_VS }, // 2881 |
22039 | | { PseudoVFWREDOSUM_VS_M2_E16, VFWREDOSUM_VS }, // 2882 |
22040 | | { PseudoVFWREDOSUM_VS_M2_E16_MASK, VFWREDOSUM_VS }, // 2883 |
22041 | | { PseudoVFWREDOSUM_VS_M2_E32, VFWREDOSUM_VS }, // 2884 |
22042 | | { PseudoVFWREDOSUM_VS_M2_E32_MASK, VFWREDOSUM_VS }, // 2885 |
22043 | | { PseudoVFWREDOSUM_VS_M4_E16, VFWREDOSUM_VS }, // 2886 |
22044 | | { PseudoVFWREDOSUM_VS_M4_E16_MASK, VFWREDOSUM_VS }, // 2887 |
22045 | | { PseudoVFWREDOSUM_VS_M4_E32, VFWREDOSUM_VS }, // 2888 |
22046 | | { PseudoVFWREDOSUM_VS_M4_E32_MASK, VFWREDOSUM_VS }, // 2889 |
22047 | | { PseudoVFWREDOSUM_VS_M8_E16, VFWREDOSUM_VS }, // 2890 |
22048 | | { PseudoVFWREDOSUM_VS_M8_E16_MASK, VFWREDOSUM_VS }, // 2891 |
22049 | | { PseudoVFWREDOSUM_VS_M8_E32, VFWREDOSUM_VS }, // 2892 |
22050 | | { PseudoVFWREDOSUM_VS_M8_E32_MASK, VFWREDOSUM_VS }, // 2893 |
22051 | | { PseudoVFWREDOSUM_VS_MF2_E16, VFWREDOSUM_VS }, // 2894 |
22052 | | { PseudoVFWREDOSUM_VS_MF2_E16_MASK, VFWREDOSUM_VS }, // 2895 |
22053 | | { PseudoVFWREDOSUM_VS_MF2_E32, VFWREDOSUM_VS }, // 2896 |
22054 | | { PseudoVFWREDOSUM_VS_MF2_E32_MASK, VFWREDOSUM_VS }, // 2897 |
22055 | | { PseudoVFWREDOSUM_VS_MF4_E16, VFWREDOSUM_VS }, // 2898 |
22056 | | { PseudoVFWREDOSUM_VS_MF4_E16_MASK, VFWREDOSUM_VS }, // 2899 |
22057 | | { PseudoVFWREDUSUM_VS_M1_E16, VFWREDUSUM_VS }, // 2900 |
22058 | | { PseudoVFWREDUSUM_VS_M1_E16_MASK, VFWREDUSUM_VS }, // 2901 |
22059 | | { PseudoVFWREDUSUM_VS_M1_E32, VFWREDUSUM_VS }, // 2902 |
22060 | | { PseudoVFWREDUSUM_VS_M1_E32_MASK, VFWREDUSUM_VS }, // 2903 |
22061 | | { PseudoVFWREDUSUM_VS_M2_E16, VFWREDUSUM_VS }, // 2904 |
22062 | | { PseudoVFWREDUSUM_VS_M2_E16_MASK, VFWREDUSUM_VS }, // 2905 |
22063 | | { PseudoVFWREDUSUM_VS_M2_E32, VFWREDUSUM_VS }, // 2906 |
22064 | | { PseudoVFWREDUSUM_VS_M2_E32_MASK, VFWREDUSUM_VS }, // 2907 |
22065 | | { PseudoVFWREDUSUM_VS_M4_E16, VFWREDUSUM_VS }, // 2908 |
22066 | | { PseudoVFWREDUSUM_VS_M4_E16_MASK, VFWREDUSUM_VS }, // 2909 |
22067 | | { PseudoVFWREDUSUM_VS_M4_E32, VFWREDUSUM_VS }, // 2910 |
22068 | | { PseudoVFWREDUSUM_VS_M4_E32_MASK, VFWREDUSUM_VS }, // 2911 |
22069 | | { PseudoVFWREDUSUM_VS_M8_E16, VFWREDUSUM_VS }, // 2912 |
22070 | | { PseudoVFWREDUSUM_VS_M8_E16_MASK, VFWREDUSUM_VS }, // 2913 |
22071 | | { PseudoVFWREDUSUM_VS_M8_E32, VFWREDUSUM_VS }, // 2914 |
22072 | | { PseudoVFWREDUSUM_VS_M8_E32_MASK, VFWREDUSUM_VS }, // 2915 |
22073 | | { PseudoVFWREDUSUM_VS_MF2_E16, VFWREDUSUM_VS }, // 2916 |
22074 | | { PseudoVFWREDUSUM_VS_MF2_E16_MASK, VFWREDUSUM_VS }, // 2917 |
22075 | | { PseudoVFWREDUSUM_VS_MF2_E32, VFWREDUSUM_VS }, // 2918 |
22076 | | { PseudoVFWREDUSUM_VS_MF2_E32_MASK, VFWREDUSUM_VS }, // 2919 |
22077 | | { PseudoVFWREDUSUM_VS_MF4_E16, VFWREDUSUM_VS }, // 2920 |
22078 | | { PseudoVFWREDUSUM_VS_MF4_E16_MASK, VFWREDUSUM_VS }, // 2921 |
22079 | | { PseudoVFWSUB_VFPR16_M1, VFWSUB_VF }, // 2922 |
22080 | | { PseudoVFWSUB_VFPR16_M1_MASK, VFWSUB_VF }, // 2923 |
22081 | | { PseudoVFWSUB_VFPR16_M2, VFWSUB_VF }, // 2924 |
22082 | | { PseudoVFWSUB_VFPR16_M2_MASK, VFWSUB_VF }, // 2925 |
22083 | | { PseudoVFWSUB_VFPR16_M4, VFWSUB_VF }, // 2926 |
22084 | | { PseudoVFWSUB_VFPR16_M4_MASK, VFWSUB_VF }, // 2927 |
22085 | | { PseudoVFWSUB_VFPR16_MF2, VFWSUB_VF }, // 2928 |
22086 | | { PseudoVFWSUB_VFPR16_MF2_MASK, VFWSUB_VF }, // 2929 |
22087 | | { PseudoVFWSUB_VFPR16_MF4, VFWSUB_VF }, // 2930 |
22088 | | { PseudoVFWSUB_VFPR16_MF4_MASK, VFWSUB_VF }, // 2931 |
22089 | | { PseudoVFWSUB_VFPR32_M1, VFWSUB_VF }, // 2932 |
22090 | | { PseudoVFWSUB_VFPR32_M1_MASK, VFWSUB_VF }, // 2933 |
22091 | | { PseudoVFWSUB_VFPR32_M2, VFWSUB_VF }, // 2934 |
22092 | | { PseudoVFWSUB_VFPR32_M2_MASK, VFWSUB_VF }, // 2935 |
22093 | | { PseudoVFWSUB_VFPR32_M4, VFWSUB_VF }, // 2936 |
22094 | | { PseudoVFWSUB_VFPR32_M4_MASK, VFWSUB_VF }, // 2937 |
22095 | | { PseudoVFWSUB_VFPR32_MF2, VFWSUB_VF }, // 2938 |
22096 | | { PseudoVFWSUB_VFPR32_MF2_MASK, VFWSUB_VF }, // 2939 |
22097 | | { PseudoVFWSUB_VV_M1, VFWSUB_VV }, // 2940 |
22098 | | { PseudoVFWSUB_VV_M1_MASK, VFWSUB_VV }, // 2941 |
22099 | | { PseudoVFWSUB_VV_M2, VFWSUB_VV }, // 2942 |
22100 | | { PseudoVFWSUB_VV_M2_MASK, VFWSUB_VV }, // 2943 |
22101 | | { PseudoVFWSUB_VV_M4, VFWSUB_VV }, // 2944 |
22102 | | { PseudoVFWSUB_VV_M4_MASK, VFWSUB_VV }, // 2945 |
22103 | | { PseudoVFWSUB_VV_MF2, VFWSUB_VV }, // 2946 |
22104 | | { PseudoVFWSUB_VV_MF2_MASK, VFWSUB_VV }, // 2947 |
22105 | | { PseudoVFWSUB_VV_MF4, VFWSUB_VV }, // 2948 |
22106 | | { PseudoVFWSUB_VV_MF4_MASK, VFWSUB_VV }, // 2949 |
22107 | | { PseudoVFWSUB_WFPR16_M1, VFWSUB_WF }, // 2950 |
22108 | | { PseudoVFWSUB_WFPR16_M1_MASK, VFWSUB_WF }, // 2951 |
22109 | | { PseudoVFWSUB_WFPR16_M2, VFWSUB_WF }, // 2952 |
22110 | | { PseudoVFWSUB_WFPR16_M2_MASK, VFWSUB_WF }, // 2953 |
22111 | | { PseudoVFWSUB_WFPR16_M4, VFWSUB_WF }, // 2954 |
22112 | | { PseudoVFWSUB_WFPR16_M4_MASK, VFWSUB_WF }, // 2955 |
22113 | | { PseudoVFWSUB_WFPR16_MF2, VFWSUB_WF }, // 2956 |
22114 | | { PseudoVFWSUB_WFPR16_MF2_MASK, VFWSUB_WF }, // 2957 |
22115 | | { PseudoVFWSUB_WFPR16_MF4, VFWSUB_WF }, // 2958 |
22116 | | { PseudoVFWSUB_WFPR16_MF4_MASK, VFWSUB_WF }, // 2959 |
22117 | | { PseudoVFWSUB_WFPR32_M1, VFWSUB_WF }, // 2960 |
22118 | | { PseudoVFWSUB_WFPR32_M1_MASK, VFWSUB_WF }, // 2961 |
22119 | | { PseudoVFWSUB_WFPR32_M2, VFWSUB_WF }, // 2962 |
22120 | | { PseudoVFWSUB_WFPR32_M2_MASK, VFWSUB_WF }, // 2963 |
22121 | | { PseudoVFWSUB_WFPR32_M4, VFWSUB_WF }, // 2964 |
22122 | | { PseudoVFWSUB_WFPR32_M4_MASK, VFWSUB_WF }, // 2965 |
22123 | | { PseudoVFWSUB_WFPR32_MF2, VFWSUB_WF }, // 2966 |
22124 | | { PseudoVFWSUB_WFPR32_MF2_MASK, VFWSUB_WF }, // 2967 |
22125 | | { PseudoVFWSUB_WV_M1, VFWSUB_WV }, // 2968 |
22126 | | { PseudoVFWSUB_WV_M1_MASK, VFWSUB_WV }, // 2969 |
22127 | | { PseudoVFWSUB_WV_M1_MASK_TIED, VFWSUB_WV }, // 2970 |
22128 | | { PseudoVFWSUB_WV_M1_TIED, VFWSUB_WV }, // 2971 |
22129 | | { PseudoVFWSUB_WV_M2, VFWSUB_WV }, // 2972 |
22130 | | { PseudoVFWSUB_WV_M2_MASK, VFWSUB_WV }, // 2973 |
22131 | | { PseudoVFWSUB_WV_M2_MASK_TIED, VFWSUB_WV }, // 2974 |
22132 | | { PseudoVFWSUB_WV_M2_TIED, VFWSUB_WV }, // 2975 |
22133 | | { PseudoVFWSUB_WV_M4, VFWSUB_WV }, // 2976 |
22134 | | { PseudoVFWSUB_WV_M4_MASK, VFWSUB_WV }, // 2977 |
22135 | | { PseudoVFWSUB_WV_M4_MASK_TIED, VFWSUB_WV }, // 2978 |
22136 | | { PseudoVFWSUB_WV_M4_TIED, VFWSUB_WV }, // 2979 |
22137 | | { PseudoVFWSUB_WV_MF2, VFWSUB_WV }, // 2980 |
22138 | | { PseudoVFWSUB_WV_MF2_MASK, VFWSUB_WV }, // 2981 |
22139 | | { PseudoVFWSUB_WV_MF2_MASK_TIED, VFWSUB_WV }, // 2982 |
22140 | | { PseudoVFWSUB_WV_MF2_TIED, VFWSUB_WV }, // 2983 |
22141 | | { PseudoVFWSUB_WV_MF4, VFWSUB_WV }, // 2984 |
22142 | | { PseudoVFWSUB_WV_MF4_MASK, VFWSUB_WV }, // 2985 |
22143 | | { PseudoVFWSUB_WV_MF4_MASK_TIED, VFWSUB_WV }, // 2986 |
22144 | | { PseudoVFWSUB_WV_MF4_TIED, VFWSUB_WV }, // 2987 |
22145 | | { PseudoVGHSH_VV_M1, VGHSH_VV }, // 2988 |
22146 | | { PseudoVGHSH_VV_M2, VGHSH_VV }, // 2989 |
22147 | | { PseudoVGHSH_VV_M4, VGHSH_VV }, // 2990 |
22148 | | { PseudoVGHSH_VV_M8, VGHSH_VV }, // 2991 |
22149 | | { PseudoVGHSH_VV_MF2, VGHSH_VV }, // 2992 |
22150 | | { PseudoVGMUL_VV_M1, VGMUL_VV }, // 2993 |
22151 | | { PseudoVGMUL_VV_M2, VGMUL_VV }, // 2994 |
22152 | | { PseudoVGMUL_VV_M4, VGMUL_VV }, // 2995 |
22153 | | { PseudoVGMUL_VV_M8, VGMUL_VV }, // 2996 |
22154 | | { PseudoVGMUL_VV_MF2, VGMUL_VV }, // 2997 |
22155 | | { PseudoVID_V_M1, VID_V }, // 2998 |
22156 | | { PseudoVID_V_M1_MASK, VID_V }, // 2999 |
22157 | | { PseudoVID_V_M2, VID_V }, // 3000 |
22158 | | { PseudoVID_V_M2_MASK, VID_V }, // 3001 |
22159 | | { PseudoVID_V_M4, VID_V }, // 3002 |
22160 | | { PseudoVID_V_M4_MASK, VID_V }, // 3003 |
22161 | | { PseudoVID_V_M8, VID_V }, // 3004 |
22162 | | { PseudoVID_V_M8_MASK, VID_V }, // 3005 |
22163 | | { PseudoVID_V_MF2, VID_V }, // 3006 |
22164 | | { PseudoVID_V_MF2_MASK, VID_V }, // 3007 |
22165 | | { PseudoVID_V_MF4, VID_V }, // 3008 |
22166 | | { PseudoVID_V_MF4_MASK, VID_V }, // 3009 |
22167 | | { PseudoVID_V_MF8, VID_V }, // 3010 |
22168 | | { PseudoVID_V_MF8_MASK, VID_V }, // 3011 |
22169 | | { PseudoVIOTA_M_M1, VIOTA_M }, // 3012 |
22170 | | { PseudoVIOTA_M_M1_MASK, VIOTA_M }, // 3013 |
22171 | | { PseudoVIOTA_M_M2, VIOTA_M }, // 3014 |
22172 | | { PseudoVIOTA_M_M2_MASK, VIOTA_M }, // 3015 |
22173 | | { PseudoVIOTA_M_M4, VIOTA_M }, // 3016 |
22174 | | { PseudoVIOTA_M_M4_MASK, VIOTA_M }, // 3017 |
22175 | | { PseudoVIOTA_M_M8, VIOTA_M }, // 3018 |
22176 | | { PseudoVIOTA_M_M8_MASK, VIOTA_M }, // 3019 |
22177 | | { PseudoVIOTA_M_MF2, VIOTA_M }, // 3020 |
22178 | | { PseudoVIOTA_M_MF2_MASK, VIOTA_M }, // 3021 |
22179 | | { PseudoVIOTA_M_MF4, VIOTA_M }, // 3022 |
22180 | | { PseudoVIOTA_M_MF4_MASK, VIOTA_M }, // 3023 |
22181 | | { PseudoVIOTA_M_MF8, VIOTA_M }, // 3024 |
22182 | | { PseudoVIOTA_M_MF8_MASK, VIOTA_M }, // 3025 |
22183 | | { PseudoVLE16FF_V_M1, VLE16FF_V }, // 3026 |
22184 | | { PseudoVLE16FF_V_M1_MASK, VLE16FF_V }, // 3027 |
22185 | | { PseudoVLE16FF_V_M2, VLE16FF_V }, // 3028 |
22186 | | { PseudoVLE16FF_V_M2_MASK, VLE16FF_V }, // 3029 |
22187 | | { PseudoVLE16FF_V_M4, VLE16FF_V }, // 3030 |
22188 | | { PseudoVLE16FF_V_M4_MASK, VLE16FF_V }, // 3031 |
22189 | | { PseudoVLE16FF_V_M8, VLE16FF_V }, // 3032 |
22190 | | { PseudoVLE16FF_V_M8_MASK, VLE16FF_V }, // 3033 |
22191 | | { PseudoVLE16FF_V_MF2, VLE16FF_V }, // 3034 |
22192 | | { PseudoVLE16FF_V_MF2_MASK, VLE16FF_V }, // 3035 |
22193 | | { PseudoVLE16FF_V_MF4, VLE16FF_V }, // 3036 |
22194 | | { PseudoVLE16FF_V_MF4_MASK, VLE16FF_V }, // 3037 |
22195 | | { PseudoVLE16_V_M1, VLE16_V }, // 3038 |
22196 | | { PseudoVLE16_V_M1_MASK, VLE16_V }, // 3039 |
22197 | | { PseudoVLE16_V_M2, VLE16_V }, // 3040 |
22198 | | { PseudoVLE16_V_M2_MASK, VLE16_V }, // 3041 |
22199 | | { PseudoVLE16_V_M4, VLE16_V }, // 3042 |
22200 | | { PseudoVLE16_V_M4_MASK, VLE16_V }, // 3043 |
22201 | | { PseudoVLE16_V_M8, VLE16_V }, // 3044 |
22202 | | { PseudoVLE16_V_M8_MASK, VLE16_V }, // 3045 |
22203 | | { PseudoVLE16_V_MF2, VLE16_V }, // 3046 |
22204 | | { PseudoVLE16_V_MF2_MASK, VLE16_V }, // 3047 |
22205 | | { PseudoVLE16_V_MF4, VLE16_V }, // 3048 |
22206 | | { PseudoVLE16_V_MF4_MASK, VLE16_V }, // 3049 |
22207 | | { PseudoVLE32FF_V_M1, VLE32FF_V }, // 3050 |
22208 | | { PseudoVLE32FF_V_M1_MASK, VLE32FF_V }, // 3051 |
22209 | | { PseudoVLE32FF_V_M2, VLE32FF_V }, // 3052 |
22210 | | { PseudoVLE32FF_V_M2_MASK, VLE32FF_V }, // 3053 |
22211 | | { PseudoVLE32FF_V_M4, VLE32FF_V }, // 3054 |
22212 | | { PseudoVLE32FF_V_M4_MASK, VLE32FF_V }, // 3055 |
22213 | | { PseudoVLE32FF_V_M8, VLE32FF_V }, // 3056 |
22214 | | { PseudoVLE32FF_V_M8_MASK, VLE32FF_V }, // 3057 |
22215 | | { PseudoVLE32FF_V_MF2, VLE32FF_V }, // 3058 |
22216 | | { PseudoVLE32FF_V_MF2_MASK, VLE32FF_V }, // 3059 |
22217 | | { PseudoVLE32_V_M1, VLE32_V }, // 3060 |
22218 | | { PseudoVLE32_V_M1_MASK, VLE32_V }, // 3061 |
22219 | | { PseudoVLE32_V_M2, VLE32_V }, // 3062 |
22220 | | { PseudoVLE32_V_M2_MASK, VLE32_V }, // 3063 |
22221 | | { PseudoVLE32_V_M4, VLE32_V }, // 3064 |
22222 | | { PseudoVLE32_V_M4_MASK, VLE32_V }, // 3065 |
22223 | | { PseudoVLE32_V_M8, VLE32_V }, // 3066 |
22224 | | { PseudoVLE32_V_M8_MASK, VLE32_V }, // 3067 |
22225 | | { PseudoVLE32_V_MF2, VLE32_V }, // 3068 |
22226 | | { PseudoVLE32_V_MF2_MASK, VLE32_V }, // 3069 |
22227 | | { PseudoVLE64FF_V_M1, VLE64FF_V }, // 3070 |
22228 | | { PseudoVLE64FF_V_M1_MASK, VLE64FF_V }, // 3071 |
22229 | | { PseudoVLE64FF_V_M2, VLE64FF_V }, // 3072 |
22230 | | { PseudoVLE64FF_V_M2_MASK, VLE64FF_V }, // 3073 |
22231 | | { PseudoVLE64FF_V_M4, VLE64FF_V }, // 3074 |
22232 | | { PseudoVLE64FF_V_M4_MASK, VLE64FF_V }, // 3075 |
22233 | | { PseudoVLE64FF_V_M8, VLE64FF_V }, // 3076 |
22234 | | { PseudoVLE64FF_V_M8_MASK, VLE64FF_V }, // 3077 |
22235 | | { PseudoVLE64_V_M1, VLE64_V }, // 3078 |
22236 | | { PseudoVLE64_V_M1_MASK, VLE64_V }, // 3079 |
22237 | | { PseudoVLE64_V_M2, VLE64_V }, // 3080 |
22238 | | { PseudoVLE64_V_M2_MASK, VLE64_V }, // 3081 |
22239 | | { PseudoVLE64_V_M4, VLE64_V }, // 3082 |
22240 | | { PseudoVLE64_V_M4_MASK, VLE64_V }, // 3083 |
22241 | | { PseudoVLE64_V_M8, VLE64_V }, // 3084 |
22242 | | { PseudoVLE64_V_M8_MASK, VLE64_V }, // 3085 |
22243 | | { PseudoVLE8FF_V_M1, VLE8FF_V }, // 3086 |
22244 | | { PseudoVLE8FF_V_M1_MASK, VLE8FF_V }, // 3087 |
22245 | | { PseudoVLE8FF_V_M2, VLE8FF_V }, // 3088 |
22246 | | { PseudoVLE8FF_V_M2_MASK, VLE8FF_V }, // 3089 |
22247 | | { PseudoVLE8FF_V_M4, VLE8FF_V }, // 3090 |
22248 | | { PseudoVLE8FF_V_M4_MASK, VLE8FF_V }, // 3091 |
22249 | | { PseudoVLE8FF_V_M8, VLE8FF_V }, // 3092 |
22250 | | { PseudoVLE8FF_V_M8_MASK, VLE8FF_V }, // 3093 |
22251 | | { PseudoVLE8FF_V_MF2, VLE8FF_V }, // 3094 |
22252 | | { PseudoVLE8FF_V_MF2_MASK, VLE8FF_V }, // 3095 |
22253 | | { PseudoVLE8FF_V_MF4, VLE8FF_V }, // 3096 |
22254 | | { PseudoVLE8FF_V_MF4_MASK, VLE8FF_V }, // 3097 |
22255 | | { PseudoVLE8FF_V_MF8, VLE8FF_V }, // 3098 |
22256 | | { PseudoVLE8FF_V_MF8_MASK, VLE8FF_V }, // 3099 |
22257 | | { PseudoVLE8_V_M1, VLE8_V }, // 3100 |
22258 | | { PseudoVLE8_V_M1_MASK, VLE8_V }, // 3101 |
22259 | | { PseudoVLE8_V_M2, VLE8_V }, // 3102 |
22260 | | { PseudoVLE8_V_M2_MASK, VLE8_V }, // 3103 |
22261 | | { PseudoVLE8_V_M4, VLE8_V }, // 3104 |
22262 | | { PseudoVLE8_V_M4_MASK, VLE8_V }, // 3105 |
22263 | | { PseudoVLE8_V_M8, VLE8_V }, // 3106 |
22264 | | { PseudoVLE8_V_M8_MASK, VLE8_V }, // 3107 |
22265 | | { PseudoVLE8_V_MF2, VLE8_V }, // 3108 |
22266 | | { PseudoVLE8_V_MF2_MASK, VLE8_V }, // 3109 |
22267 | | { PseudoVLE8_V_MF4, VLE8_V }, // 3110 |
22268 | | { PseudoVLE8_V_MF4_MASK, VLE8_V }, // 3111 |
22269 | | { PseudoVLE8_V_MF8, VLE8_V }, // 3112 |
22270 | | { PseudoVLE8_V_MF8_MASK, VLE8_V }, // 3113 |
22271 | | { PseudoVLM_V_B1, VLM_V }, // 3114 |
22272 | | { PseudoVLM_V_B16, VLM_V }, // 3115 |
22273 | | { PseudoVLM_V_B2, VLM_V }, // 3116 |
22274 | | { PseudoVLM_V_B32, VLM_V }, // 3117 |
22275 | | { PseudoVLM_V_B4, VLM_V }, // 3118 |
22276 | | { PseudoVLM_V_B64, VLM_V }, // 3119 |
22277 | | { PseudoVLM_V_B8, VLM_V }, // 3120 |
22278 | | { PseudoVLOXEI16_V_M1_M1, VLOXEI16_V }, // 3121 |
22279 | | { PseudoVLOXEI16_V_M1_M1_MASK, VLOXEI16_V }, // 3122 |
22280 | | { PseudoVLOXEI16_V_M1_M2, VLOXEI16_V }, // 3123 |
22281 | | { PseudoVLOXEI16_V_M1_M2_MASK, VLOXEI16_V }, // 3124 |
22282 | | { PseudoVLOXEI16_V_M1_M4, VLOXEI16_V }, // 3125 |
22283 | | { PseudoVLOXEI16_V_M1_M4_MASK, VLOXEI16_V }, // 3126 |
22284 | | { PseudoVLOXEI16_V_M1_MF2, VLOXEI16_V }, // 3127 |
22285 | | { PseudoVLOXEI16_V_M1_MF2_MASK, VLOXEI16_V }, // 3128 |
22286 | | { PseudoVLOXEI16_V_M2_M1, VLOXEI16_V }, // 3129 |
22287 | | { PseudoVLOXEI16_V_M2_M1_MASK, VLOXEI16_V }, // 3130 |
22288 | | { PseudoVLOXEI16_V_M2_M2, VLOXEI16_V }, // 3131 |
22289 | | { PseudoVLOXEI16_V_M2_M2_MASK, VLOXEI16_V }, // 3132 |
22290 | | { PseudoVLOXEI16_V_M2_M4, VLOXEI16_V }, // 3133 |
22291 | | { PseudoVLOXEI16_V_M2_M4_MASK, VLOXEI16_V }, // 3134 |
22292 | | { PseudoVLOXEI16_V_M2_M8, VLOXEI16_V }, // 3135 |
22293 | | { PseudoVLOXEI16_V_M2_M8_MASK, VLOXEI16_V }, // 3136 |
22294 | | { PseudoVLOXEI16_V_M4_M2, VLOXEI16_V }, // 3137 |
22295 | | { PseudoVLOXEI16_V_M4_M2_MASK, VLOXEI16_V }, // 3138 |
22296 | | { PseudoVLOXEI16_V_M4_M4, VLOXEI16_V }, // 3139 |
22297 | | { PseudoVLOXEI16_V_M4_M4_MASK, VLOXEI16_V }, // 3140 |
22298 | | { PseudoVLOXEI16_V_M4_M8, VLOXEI16_V }, // 3141 |
22299 | | { PseudoVLOXEI16_V_M4_M8_MASK, VLOXEI16_V }, // 3142 |
22300 | | { PseudoVLOXEI16_V_M8_M4, VLOXEI16_V }, // 3143 |
22301 | | { PseudoVLOXEI16_V_M8_M4_MASK, VLOXEI16_V }, // 3144 |
22302 | | { PseudoVLOXEI16_V_M8_M8, VLOXEI16_V }, // 3145 |
22303 | | { PseudoVLOXEI16_V_M8_M8_MASK, VLOXEI16_V }, // 3146 |
22304 | | { PseudoVLOXEI16_V_MF2_M1, VLOXEI16_V }, // 3147 |
22305 | | { PseudoVLOXEI16_V_MF2_M1_MASK, VLOXEI16_V }, // 3148 |
22306 | | { PseudoVLOXEI16_V_MF2_M2, VLOXEI16_V }, // 3149 |
22307 | | { PseudoVLOXEI16_V_MF2_M2_MASK, VLOXEI16_V }, // 3150 |
22308 | | { PseudoVLOXEI16_V_MF2_MF2, VLOXEI16_V }, // 3151 |
22309 | | { PseudoVLOXEI16_V_MF2_MF2_MASK, VLOXEI16_V }, // 3152 |
22310 | | { PseudoVLOXEI16_V_MF2_MF4, VLOXEI16_V }, // 3153 |
22311 | | { PseudoVLOXEI16_V_MF2_MF4_MASK, VLOXEI16_V }, // 3154 |
22312 | | { PseudoVLOXEI16_V_MF4_M1, VLOXEI16_V }, // 3155 |
22313 | | { PseudoVLOXEI16_V_MF4_M1_MASK, VLOXEI16_V }, // 3156 |
22314 | | { PseudoVLOXEI16_V_MF4_MF2, VLOXEI16_V }, // 3157 |
22315 | | { PseudoVLOXEI16_V_MF4_MF2_MASK, VLOXEI16_V }, // 3158 |
22316 | | { PseudoVLOXEI16_V_MF4_MF4, VLOXEI16_V }, // 3159 |
22317 | | { PseudoVLOXEI16_V_MF4_MF4_MASK, VLOXEI16_V }, // 3160 |
22318 | | { PseudoVLOXEI16_V_MF4_MF8, VLOXEI16_V }, // 3161 |
22319 | | { PseudoVLOXEI16_V_MF4_MF8_MASK, VLOXEI16_V }, // 3162 |
22320 | | { PseudoVLOXEI32_V_M1_M1, VLOXEI32_V }, // 3163 |
22321 | | { PseudoVLOXEI32_V_M1_M1_MASK, VLOXEI32_V }, // 3164 |
22322 | | { PseudoVLOXEI32_V_M1_M2, VLOXEI32_V }, // 3165 |
22323 | | { PseudoVLOXEI32_V_M1_M2_MASK, VLOXEI32_V }, // 3166 |
22324 | | { PseudoVLOXEI32_V_M1_MF2, VLOXEI32_V }, // 3167 |
22325 | | { PseudoVLOXEI32_V_M1_MF2_MASK, VLOXEI32_V }, // 3168 |
22326 | | { PseudoVLOXEI32_V_M1_MF4, VLOXEI32_V }, // 3169 |
22327 | | { PseudoVLOXEI32_V_M1_MF4_MASK, VLOXEI32_V }, // 3170 |
22328 | | { PseudoVLOXEI32_V_M2_M1, VLOXEI32_V }, // 3171 |
22329 | | { PseudoVLOXEI32_V_M2_M1_MASK, VLOXEI32_V }, // 3172 |
22330 | | { PseudoVLOXEI32_V_M2_M2, VLOXEI32_V }, // 3173 |
22331 | | { PseudoVLOXEI32_V_M2_M2_MASK, VLOXEI32_V }, // 3174 |
22332 | | { PseudoVLOXEI32_V_M2_M4, VLOXEI32_V }, // 3175 |
22333 | | { PseudoVLOXEI32_V_M2_M4_MASK, VLOXEI32_V }, // 3176 |
22334 | | { PseudoVLOXEI32_V_M2_MF2, VLOXEI32_V }, // 3177 |
22335 | | { PseudoVLOXEI32_V_M2_MF2_MASK, VLOXEI32_V }, // 3178 |
22336 | | { PseudoVLOXEI32_V_M4_M1, VLOXEI32_V }, // 3179 |
22337 | | { PseudoVLOXEI32_V_M4_M1_MASK, VLOXEI32_V }, // 3180 |
22338 | | { PseudoVLOXEI32_V_M4_M2, VLOXEI32_V }, // 3181 |
22339 | | { PseudoVLOXEI32_V_M4_M2_MASK, VLOXEI32_V }, // 3182 |
22340 | | { PseudoVLOXEI32_V_M4_M4, VLOXEI32_V }, // 3183 |
22341 | | { PseudoVLOXEI32_V_M4_M4_MASK, VLOXEI32_V }, // 3184 |
22342 | | { PseudoVLOXEI32_V_M4_M8, VLOXEI32_V }, // 3185 |
22343 | | { PseudoVLOXEI32_V_M4_M8_MASK, VLOXEI32_V }, // 3186 |
22344 | | { PseudoVLOXEI32_V_M8_M2, VLOXEI32_V }, // 3187 |
22345 | | { PseudoVLOXEI32_V_M8_M2_MASK, VLOXEI32_V }, // 3188 |
22346 | | { PseudoVLOXEI32_V_M8_M4, VLOXEI32_V }, // 3189 |
22347 | | { PseudoVLOXEI32_V_M8_M4_MASK, VLOXEI32_V }, // 3190 |
22348 | | { PseudoVLOXEI32_V_M8_M8, VLOXEI32_V }, // 3191 |
22349 | | { PseudoVLOXEI32_V_M8_M8_MASK, VLOXEI32_V }, // 3192 |
22350 | | { PseudoVLOXEI32_V_MF2_M1, VLOXEI32_V }, // 3193 |
22351 | | { PseudoVLOXEI32_V_MF2_M1_MASK, VLOXEI32_V }, // 3194 |
22352 | | { PseudoVLOXEI32_V_MF2_MF2, VLOXEI32_V }, // 3195 |
22353 | | { PseudoVLOXEI32_V_MF2_MF2_MASK, VLOXEI32_V }, // 3196 |
22354 | | { PseudoVLOXEI32_V_MF2_MF4, VLOXEI32_V }, // 3197 |
22355 | | { PseudoVLOXEI32_V_MF2_MF4_MASK, VLOXEI32_V }, // 3198 |
22356 | | { PseudoVLOXEI32_V_MF2_MF8, VLOXEI32_V }, // 3199 |
22357 | | { PseudoVLOXEI32_V_MF2_MF8_MASK, VLOXEI32_V }, // 3200 |
22358 | | { PseudoVLOXEI64_V_M1_M1, VLOXEI64_V }, // 3201 |
22359 | | { PseudoVLOXEI64_V_M1_M1_MASK, VLOXEI64_V }, // 3202 |
22360 | | { PseudoVLOXEI64_V_M1_MF2, VLOXEI64_V }, // 3203 |
22361 | | { PseudoVLOXEI64_V_M1_MF2_MASK, VLOXEI64_V }, // 3204 |
22362 | | { PseudoVLOXEI64_V_M1_MF4, VLOXEI64_V }, // 3205 |
22363 | | { PseudoVLOXEI64_V_M1_MF4_MASK, VLOXEI64_V }, // 3206 |
22364 | | { PseudoVLOXEI64_V_M1_MF8, VLOXEI64_V }, // 3207 |
22365 | | { PseudoVLOXEI64_V_M1_MF8_MASK, VLOXEI64_V }, // 3208 |
22366 | | { PseudoVLOXEI64_V_M2_M1, VLOXEI64_V }, // 3209 |
22367 | | { PseudoVLOXEI64_V_M2_M1_MASK, VLOXEI64_V }, // 3210 |
22368 | | { PseudoVLOXEI64_V_M2_M2, VLOXEI64_V }, // 3211 |
22369 | | { PseudoVLOXEI64_V_M2_M2_MASK, VLOXEI64_V }, // 3212 |
22370 | | { PseudoVLOXEI64_V_M2_MF2, VLOXEI64_V }, // 3213 |
22371 | | { PseudoVLOXEI64_V_M2_MF2_MASK, VLOXEI64_V }, // 3214 |
22372 | | { PseudoVLOXEI64_V_M2_MF4, VLOXEI64_V }, // 3215 |
22373 | | { PseudoVLOXEI64_V_M2_MF4_MASK, VLOXEI64_V }, // 3216 |
22374 | | { PseudoVLOXEI64_V_M4_M1, VLOXEI64_V }, // 3217 |
22375 | | { PseudoVLOXEI64_V_M4_M1_MASK, VLOXEI64_V }, // 3218 |
22376 | | { PseudoVLOXEI64_V_M4_M2, VLOXEI64_V }, // 3219 |
22377 | | { PseudoVLOXEI64_V_M4_M2_MASK, VLOXEI64_V }, // 3220 |
22378 | | { PseudoVLOXEI64_V_M4_M4, VLOXEI64_V }, // 3221 |
22379 | | { PseudoVLOXEI64_V_M4_M4_MASK, VLOXEI64_V }, // 3222 |
22380 | | { PseudoVLOXEI64_V_M4_MF2, VLOXEI64_V }, // 3223 |
22381 | | { PseudoVLOXEI64_V_M4_MF2_MASK, VLOXEI64_V }, // 3224 |
22382 | | { PseudoVLOXEI64_V_M8_M1, VLOXEI64_V }, // 3225 |
22383 | | { PseudoVLOXEI64_V_M8_M1_MASK, VLOXEI64_V }, // 3226 |
22384 | | { PseudoVLOXEI64_V_M8_M2, VLOXEI64_V }, // 3227 |
22385 | | { PseudoVLOXEI64_V_M8_M2_MASK, VLOXEI64_V }, // 3228 |
22386 | | { PseudoVLOXEI64_V_M8_M4, VLOXEI64_V }, // 3229 |
22387 | | { PseudoVLOXEI64_V_M8_M4_MASK, VLOXEI64_V }, // 3230 |
22388 | | { PseudoVLOXEI64_V_M8_M8, VLOXEI64_V }, // 3231 |
22389 | | { PseudoVLOXEI64_V_M8_M8_MASK, VLOXEI64_V }, // 3232 |
22390 | | { PseudoVLOXEI8_V_M1_M1, VLOXEI8_V }, // 3233 |
22391 | | { PseudoVLOXEI8_V_M1_M1_MASK, VLOXEI8_V }, // 3234 |
22392 | | { PseudoVLOXEI8_V_M1_M2, VLOXEI8_V }, // 3235 |
22393 | | { PseudoVLOXEI8_V_M1_M2_MASK, VLOXEI8_V }, // 3236 |
22394 | | { PseudoVLOXEI8_V_M1_M4, VLOXEI8_V }, // 3237 |
22395 | | { PseudoVLOXEI8_V_M1_M4_MASK, VLOXEI8_V }, // 3238 |
22396 | | { PseudoVLOXEI8_V_M1_M8, VLOXEI8_V }, // 3239 |
22397 | | { PseudoVLOXEI8_V_M1_M8_MASK, VLOXEI8_V }, // 3240 |
22398 | | { PseudoVLOXEI8_V_M2_M2, VLOXEI8_V }, // 3241 |
22399 | | { PseudoVLOXEI8_V_M2_M2_MASK, VLOXEI8_V }, // 3242 |
22400 | | { PseudoVLOXEI8_V_M2_M4, VLOXEI8_V }, // 3243 |
22401 | | { PseudoVLOXEI8_V_M2_M4_MASK, VLOXEI8_V }, // 3244 |
22402 | | { PseudoVLOXEI8_V_M2_M8, VLOXEI8_V }, // 3245 |
22403 | | { PseudoVLOXEI8_V_M2_M8_MASK, VLOXEI8_V }, // 3246 |
22404 | | { PseudoVLOXEI8_V_M4_M4, VLOXEI8_V }, // 3247 |
22405 | | { PseudoVLOXEI8_V_M4_M4_MASK, VLOXEI8_V }, // 3248 |
22406 | | { PseudoVLOXEI8_V_M4_M8, VLOXEI8_V }, // 3249 |
22407 | | { PseudoVLOXEI8_V_M4_M8_MASK, VLOXEI8_V }, // 3250 |
22408 | | { PseudoVLOXEI8_V_M8_M8, VLOXEI8_V }, // 3251 |
22409 | | { PseudoVLOXEI8_V_M8_M8_MASK, VLOXEI8_V }, // 3252 |
22410 | | { PseudoVLOXEI8_V_MF2_M1, VLOXEI8_V }, // 3253 |
22411 | | { PseudoVLOXEI8_V_MF2_M1_MASK, VLOXEI8_V }, // 3254 |
22412 | | { PseudoVLOXEI8_V_MF2_M2, VLOXEI8_V }, // 3255 |
22413 | | { PseudoVLOXEI8_V_MF2_M2_MASK, VLOXEI8_V }, // 3256 |
22414 | | { PseudoVLOXEI8_V_MF2_M4, VLOXEI8_V }, // 3257 |
22415 | | { PseudoVLOXEI8_V_MF2_M4_MASK, VLOXEI8_V }, // 3258 |
22416 | | { PseudoVLOXEI8_V_MF2_MF2, VLOXEI8_V }, // 3259 |
22417 | | { PseudoVLOXEI8_V_MF2_MF2_MASK, VLOXEI8_V }, // 3260 |
22418 | | { PseudoVLOXEI8_V_MF4_M1, VLOXEI8_V }, // 3261 |
22419 | | { PseudoVLOXEI8_V_MF4_M1_MASK, VLOXEI8_V }, // 3262 |
22420 | | { PseudoVLOXEI8_V_MF4_M2, VLOXEI8_V }, // 3263 |
22421 | | { PseudoVLOXEI8_V_MF4_M2_MASK, VLOXEI8_V }, // 3264 |
22422 | | { PseudoVLOXEI8_V_MF4_MF2, VLOXEI8_V }, // 3265 |
22423 | | { PseudoVLOXEI8_V_MF4_MF2_MASK, VLOXEI8_V }, // 3266 |
22424 | | { PseudoVLOXEI8_V_MF4_MF4, VLOXEI8_V }, // 3267 |
22425 | | { PseudoVLOXEI8_V_MF4_MF4_MASK, VLOXEI8_V }, // 3268 |
22426 | | { PseudoVLOXEI8_V_MF8_M1, VLOXEI8_V }, // 3269 |
22427 | | { PseudoVLOXEI8_V_MF8_M1_MASK, VLOXEI8_V }, // 3270 |
22428 | | { PseudoVLOXEI8_V_MF8_MF2, VLOXEI8_V }, // 3271 |
22429 | | { PseudoVLOXEI8_V_MF8_MF2_MASK, VLOXEI8_V }, // 3272 |
22430 | | { PseudoVLOXEI8_V_MF8_MF4, VLOXEI8_V }, // 3273 |
22431 | | { PseudoVLOXEI8_V_MF8_MF4_MASK, VLOXEI8_V }, // 3274 |
22432 | | { PseudoVLOXEI8_V_MF8_MF8, VLOXEI8_V }, // 3275 |
22433 | | { PseudoVLOXEI8_V_MF8_MF8_MASK, VLOXEI8_V }, // 3276 |
22434 | | { PseudoVLOXSEG2EI16_V_M1_M1, VLOXSEG2EI16_V }, // 3277 |
22435 | | { PseudoVLOXSEG2EI16_V_M1_M1_MASK, VLOXSEG2EI16_V }, // 3278 |
22436 | | { PseudoVLOXSEG2EI16_V_M1_M2, VLOXSEG2EI16_V }, // 3279 |
22437 | | { PseudoVLOXSEG2EI16_V_M1_M2_MASK, VLOXSEG2EI16_V }, // 3280 |
22438 | | { PseudoVLOXSEG2EI16_V_M1_M4, VLOXSEG2EI16_V }, // 3281 |
22439 | | { PseudoVLOXSEG2EI16_V_M1_M4_MASK, VLOXSEG2EI16_V }, // 3282 |
22440 | | { PseudoVLOXSEG2EI16_V_M1_MF2, VLOXSEG2EI16_V }, // 3283 |
22441 | | { PseudoVLOXSEG2EI16_V_M1_MF2_MASK, VLOXSEG2EI16_V }, // 3284 |
22442 | | { PseudoVLOXSEG2EI16_V_M2_M1, VLOXSEG2EI16_V }, // 3285 |
22443 | | { PseudoVLOXSEG2EI16_V_M2_M1_MASK, VLOXSEG2EI16_V }, // 3286 |
22444 | | { PseudoVLOXSEG2EI16_V_M2_M2, VLOXSEG2EI16_V }, // 3287 |
22445 | | { PseudoVLOXSEG2EI16_V_M2_M2_MASK, VLOXSEG2EI16_V }, // 3288 |
22446 | | { PseudoVLOXSEG2EI16_V_M2_M4, VLOXSEG2EI16_V }, // 3289 |
22447 | | { PseudoVLOXSEG2EI16_V_M2_M4_MASK, VLOXSEG2EI16_V }, // 3290 |
22448 | | { PseudoVLOXSEG2EI16_V_M4_M2, VLOXSEG2EI16_V }, // 3291 |
22449 | | { PseudoVLOXSEG2EI16_V_M4_M2_MASK, VLOXSEG2EI16_V }, // 3292 |
22450 | | { PseudoVLOXSEG2EI16_V_M4_M4, VLOXSEG2EI16_V }, // 3293 |
22451 | | { PseudoVLOXSEG2EI16_V_M4_M4_MASK, VLOXSEG2EI16_V }, // 3294 |
22452 | | { PseudoVLOXSEG2EI16_V_M8_M4, VLOXSEG2EI16_V }, // 3295 |
22453 | | { PseudoVLOXSEG2EI16_V_M8_M4_MASK, VLOXSEG2EI16_V }, // 3296 |
22454 | | { PseudoVLOXSEG2EI16_V_MF2_M1, VLOXSEG2EI16_V }, // 3297 |
22455 | | { PseudoVLOXSEG2EI16_V_MF2_M1_MASK, VLOXSEG2EI16_V }, // 3298 |
22456 | | { PseudoVLOXSEG2EI16_V_MF2_M2, VLOXSEG2EI16_V }, // 3299 |
22457 | | { PseudoVLOXSEG2EI16_V_MF2_M2_MASK, VLOXSEG2EI16_V }, // 3300 |
22458 | | { PseudoVLOXSEG2EI16_V_MF2_MF2, VLOXSEG2EI16_V }, // 3301 |
22459 | | { PseudoVLOXSEG2EI16_V_MF2_MF2_MASK, VLOXSEG2EI16_V }, // 3302 |
22460 | | { PseudoVLOXSEG2EI16_V_MF2_MF4, VLOXSEG2EI16_V }, // 3303 |
22461 | | { PseudoVLOXSEG2EI16_V_MF2_MF4_MASK, VLOXSEG2EI16_V }, // 3304 |
22462 | | { PseudoVLOXSEG2EI16_V_MF4_M1, VLOXSEG2EI16_V }, // 3305 |
22463 | | { PseudoVLOXSEG2EI16_V_MF4_M1_MASK, VLOXSEG2EI16_V }, // 3306 |
22464 | | { PseudoVLOXSEG2EI16_V_MF4_MF2, VLOXSEG2EI16_V }, // 3307 |
22465 | | { PseudoVLOXSEG2EI16_V_MF4_MF2_MASK, VLOXSEG2EI16_V }, // 3308 |
22466 | | { PseudoVLOXSEG2EI16_V_MF4_MF4, VLOXSEG2EI16_V }, // 3309 |
22467 | | { PseudoVLOXSEG2EI16_V_MF4_MF4_MASK, VLOXSEG2EI16_V }, // 3310 |
22468 | | { PseudoVLOXSEG2EI16_V_MF4_MF8, VLOXSEG2EI16_V }, // 3311 |
22469 | | { PseudoVLOXSEG2EI16_V_MF4_MF8_MASK, VLOXSEG2EI16_V }, // 3312 |
22470 | | { PseudoVLOXSEG2EI32_V_M1_M1, VLOXSEG2EI32_V }, // 3313 |
22471 | | { PseudoVLOXSEG2EI32_V_M1_M1_MASK, VLOXSEG2EI32_V }, // 3314 |
22472 | | { PseudoVLOXSEG2EI32_V_M1_M2, VLOXSEG2EI32_V }, // 3315 |
22473 | | { PseudoVLOXSEG2EI32_V_M1_M2_MASK, VLOXSEG2EI32_V }, // 3316 |
22474 | | { PseudoVLOXSEG2EI32_V_M1_MF2, VLOXSEG2EI32_V }, // 3317 |
22475 | | { PseudoVLOXSEG2EI32_V_M1_MF2_MASK, VLOXSEG2EI32_V }, // 3318 |
22476 | | { PseudoVLOXSEG2EI32_V_M1_MF4, VLOXSEG2EI32_V }, // 3319 |
22477 | | { PseudoVLOXSEG2EI32_V_M1_MF4_MASK, VLOXSEG2EI32_V }, // 3320 |
22478 | | { PseudoVLOXSEG2EI32_V_M2_M1, VLOXSEG2EI32_V }, // 3321 |
22479 | | { PseudoVLOXSEG2EI32_V_M2_M1_MASK, VLOXSEG2EI32_V }, // 3322 |
22480 | | { PseudoVLOXSEG2EI32_V_M2_M2, VLOXSEG2EI32_V }, // 3323 |
22481 | | { PseudoVLOXSEG2EI32_V_M2_M2_MASK, VLOXSEG2EI32_V }, // 3324 |
22482 | | { PseudoVLOXSEG2EI32_V_M2_M4, VLOXSEG2EI32_V }, // 3325 |
22483 | | { PseudoVLOXSEG2EI32_V_M2_M4_MASK, VLOXSEG2EI32_V }, // 3326 |
22484 | | { PseudoVLOXSEG2EI32_V_M2_MF2, VLOXSEG2EI32_V }, // 3327 |
22485 | | { PseudoVLOXSEG2EI32_V_M2_MF2_MASK, VLOXSEG2EI32_V }, // 3328 |
22486 | | { PseudoVLOXSEG2EI32_V_M4_M1, VLOXSEG2EI32_V }, // 3329 |
22487 | | { PseudoVLOXSEG2EI32_V_M4_M1_MASK, VLOXSEG2EI32_V }, // 3330 |
22488 | | { PseudoVLOXSEG2EI32_V_M4_M2, VLOXSEG2EI32_V }, // 3331 |
22489 | | { PseudoVLOXSEG2EI32_V_M4_M2_MASK, VLOXSEG2EI32_V }, // 3332 |
22490 | | { PseudoVLOXSEG2EI32_V_M4_M4, VLOXSEG2EI32_V }, // 3333 |
22491 | | { PseudoVLOXSEG2EI32_V_M4_M4_MASK, VLOXSEG2EI32_V }, // 3334 |
22492 | | { PseudoVLOXSEG2EI32_V_M8_M2, VLOXSEG2EI32_V }, // 3335 |
22493 | | { PseudoVLOXSEG2EI32_V_M8_M2_MASK, VLOXSEG2EI32_V }, // 3336 |
22494 | | { PseudoVLOXSEG2EI32_V_M8_M4, VLOXSEG2EI32_V }, // 3337 |
22495 | | { PseudoVLOXSEG2EI32_V_M8_M4_MASK, VLOXSEG2EI32_V }, // 3338 |
22496 | | { PseudoVLOXSEG2EI32_V_MF2_M1, VLOXSEG2EI32_V }, // 3339 |
22497 | | { PseudoVLOXSEG2EI32_V_MF2_M1_MASK, VLOXSEG2EI32_V }, // 3340 |
22498 | | { PseudoVLOXSEG2EI32_V_MF2_MF2, VLOXSEG2EI32_V }, // 3341 |
22499 | | { PseudoVLOXSEG2EI32_V_MF2_MF2_MASK, VLOXSEG2EI32_V }, // 3342 |
22500 | | { PseudoVLOXSEG2EI32_V_MF2_MF4, VLOXSEG2EI32_V }, // 3343 |
22501 | | { PseudoVLOXSEG2EI32_V_MF2_MF4_MASK, VLOXSEG2EI32_V }, // 3344 |
22502 | | { PseudoVLOXSEG2EI32_V_MF2_MF8, VLOXSEG2EI32_V }, // 3345 |
22503 | | { PseudoVLOXSEG2EI32_V_MF2_MF8_MASK, VLOXSEG2EI32_V }, // 3346 |
22504 | | { PseudoVLOXSEG2EI64_V_M1_M1, VLOXSEG2EI64_V }, // 3347 |
22505 | | { PseudoVLOXSEG2EI64_V_M1_M1_MASK, VLOXSEG2EI64_V }, // 3348 |
22506 | | { PseudoVLOXSEG2EI64_V_M1_MF2, VLOXSEG2EI64_V }, // 3349 |
22507 | | { PseudoVLOXSEG2EI64_V_M1_MF2_MASK, VLOXSEG2EI64_V }, // 3350 |
22508 | | { PseudoVLOXSEG2EI64_V_M1_MF4, VLOXSEG2EI64_V }, // 3351 |
22509 | | { PseudoVLOXSEG2EI64_V_M1_MF4_MASK, VLOXSEG2EI64_V }, // 3352 |
22510 | | { PseudoVLOXSEG2EI64_V_M1_MF8, VLOXSEG2EI64_V }, // 3353 |
22511 | | { PseudoVLOXSEG2EI64_V_M1_MF8_MASK, VLOXSEG2EI64_V }, // 3354 |
22512 | | { PseudoVLOXSEG2EI64_V_M2_M1, VLOXSEG2EI64_V }, // 3355 |
22513 | | { PseudoVLOXSEG2EI64_V_M2_M1_MASK, VLOXSEG2EI64_V }, // 3356 |
22514 | | { PseudoVLOXSEG2EI64_V_M2_M2, VLOXSEG2EI64_V }, // 3357 |
22515 | | { PseudoVLOXSEG2EI64_V_M2_M2_MASK, VLOXSEG2EI64_V }, // 3358 |
22516 | | { PseudoVLOXSEG2EI64_V_M2_MF2, VLOXSEG2EI64_V }, // 3359 |
22517 | | { PseudoVLOXSEG2EI64_V_M2_MF2_MASK, VLOXSEG2EI64_V }, // 3360 |
22518 | | { PseudoVLOXSEG2EI64_V_M2_MF4, VLOXSEG2EI64_V }, // 3361 |
22519 | | { PseudoVLOXSEG2EI64_V_M2_MF4_MASK, VLOXSEG2EI64_V }, // 3362 |
22520 | | { PseudoVLOXSEG2EI64_V_M4_M1, VLOXSEG2EI64_V }, // 3363 |
22521 | | { PseudoVLOXSEG2EI64_V_M4_M1_MASK, VLOXSEG2EI64_V }, // 3364 |
22522 | | { PseudoVLOXSEG2EI64_V_M4_M2, VLOXSEG2EI64_V }, // 3365 |
22523 | | { PseudoVLOXSEG2EI64_V_M4_M2_MASK, VLOXSEG2EI64_V }, // 3366 |
22524 | | { PseudoVLOXSEG2EI64_V_M4_M4, VLOXSEG2EI64_V }, // 3367 |
22525 | | { PseudoVLOXSEG2EI64_V_M4_M4_MASK, VLOXSEG2EI64_V }, // 3368 |
22526 | | { PseudoVLOXSEG2EI64_V_M4_MF2, VLOXSEG2EI64_V }, // 3369 |
22527 | | { PseudoVLOXSEG2EI64_V_M4_MF2_MASK, VLOXSEG2EI64_V }, // 3370 |
22528 | | { PseudoVLOXSEG2EI64_V_M8_M1, VLOXSEG2EI64_V }, // 3371 |
22529 | | { PseudoVLOXSEG2EI64_V_M8_M1_MASK, VLOXSEG2EI64_V }, // 3372 |
22530 | | { PseudoVLOXSEG2EI64_V_M8_M2, VLOXSEG2EI64_V }, // 3373 |
22531 | | { PseudoVLOXSEG2EI64_V_M8_M2_MASK, VLOXSEG2EI64_V }, // 3374 |
22532 | | { PseudoVLOXSEG2EI64_V_M8_M4, VLOXSEG2EI64_V }, // 3375 |
22533 | | { PseudoVLOXSEG2EI64_V_M8_M4_MASK, VLOXSEG2EI64_V }, // 3376 |
22534 | | { PseudoVLOXSEG2EI8_V_M1_M1, VLOXSEG2EI8_V }, // 3377 |
22535 | | { PseudoVLOXSEG2EI8_V_M1_M1_MASK, VLOXSEG2EI8_V }, // 3378 |
22536 | | { PseudoVLOXSEG2EI8_V_M1_M2, VLOXSEG2EI8_V }, // 3379 |
22537 | | { PseudoVLOXSEG2EI8_V_M1_M2_MASK, VLOXSEG2EI8_V }, // 3380 |
22538 | | { PseudoVLOXSEG2EI8_V_M1_M4, VLOXSEG2EI8_V }, // 3381 |
22539 | | { PseudoVLOXSEG2EI8_V_M1_M4_MASK, VLOXSEG2EI8_V }, // 3382 |
22540 | | { PseudoVLOXSEG2EI8_V_M2_M2, VLOXSEG2EI8_V }, // 3383 |
22541 | | { PseudoVLOXSEG2EI8_V_M2_M2_MASK, VLOXSEG2EI8_V }, // 3384 |
22542 | | { PseudoVLOXSEG2EI8_V_M2_M4, VLOXSEG2EI8_V }, // 3385 |
22543 | | { PseudoVLOXSEG2EI8_V_M2_M4_MASK, VLOXSEG2EI8_V }, // 3386 |
22544 | | { PseudoVLOXSEG2EI8_V_M4_M4, VLOXSEG2EI8_V }, // 3387 |
22545 | | { PseudoVLOXSEG2EI8_V_M4_M4_MASK, VLOXSEG2EI8_V }, // 3388 |
22546 | | { PseudoVLOXSEG2EI8_V_MF2_M1, VLOXSEG2EI8_V }, // 3389 |
22547 | | { PseudoVLOXSEG2EI8_V_MF2_M1_MASK, VLOXSEG2EI8_V }, // 3390 |
22548 | | { PseudoVLOXSEG2EI8_V_MF2_M2, VLOXSEG2EI8_V }, // 3391 |
22549 | | { PseudoVLOXSEG2EI8_V_MF2_M2_MASK, VLOXSEG2EI8_V }, // 3392 |
22550 | | { PseudoVLOXSEG2EI8_V_MF2_M4, VLOXSEG2EI8_V }, // 3393 |
22551 | | { PseudoVLOXSEG2EI8_V_MF2_M4_MASK, VLOXSEG2EI8_V }, // 3394 |
22552 | | { PseudoVLOXSEG2EI8_V_MF2_MF2, VLOXSEG2EI8_V }, // 3395 |
22553 | | { PseudoVLOXSEG2EI8_V_MF2_MF2_MASK, VLOXSEG2EI8_V }, // 3396 |
22554 | | { PseudoVLOXSEG2EI8_V_MF4_M1, VLOXSEG2EI8_V }, // 3397 |
22555 | | { PseudoVLOXSEG2EI8_V_MF4_M1_MASK, VLOXSEG2EI8_V }, // 3398 |
22556 | | { PseudoVLOXSEG2EI8_V_MF4_M2, VLOXSEG2EI8_V }, // 3399 |
22557 | | { PseudoVLOXSEG2EI8_V_MF4_M2_MASK, VLOXSEG2EI8_V }, // 3400 |
22558 | | { PseudoVLOXSEG2EI8_V_MF4_MF2, VLOXSEG2EI8_V }, // 3401 |
22559 | | { PseudoVLOXSEG2EI8_V_MF4_MF2_MASK, VLOXSEG2EI8_V }, // 3402 |
22560 | | { PseudoVLOXSEG2EI8_V_MF4_MF4, VLOXSEG2EI8_V }, // 3403 |
22561 | | { PseudoVLOXSEG2EI8_V_MF4_MF4_MASK, VLOXSEG2EI8_V }, // 3404 |
22562 | | { PseudoVLOXSEG2EI8_V_MF8_M1, VLOXSEG2EI8_V }, // 3405 |
22563 | | { PseudoVLOXSEG2EI8_V_MF8_M1_MASK, VLOXSEG2EI8_V }, // 3406 |
22564 | | { PseudoVLOXSEG2EI8_V_MF8_MF2, VLOXSEG2EI8_V }, // 3407 |
22565 | | { PseudoVLOXSEG2EI8_V_MF8_MF2_MASK, VLOXSEG2EI8_V }, // 3408 |
22566 | | { PseudoVLOXSEG2EI8_V_MF8_MF4, VLOXSEG2EI8_V }, // 3409 |
22567 | | { PseudoVLOXSEG2EI8_V_MF8_MF4_MASK, VLOXSEG2EI8_V }, // 3410 |
22568 | | { PseudoVLOXSEG2EI8_V_MF8_MF8, VLOXSEG2EI8_V }, // 3411 |
22569 | | { PseudoVLOXSEG2EI8_V_MF8_MF8_MASK, VLOXSEG2EI8_V }, // 3412 |
22570 | | { PseudoVLOXSEG3EI16_V_M1_M1, VLOXSEG3EI16_V }, // 3413 |
22571 | | { PseudoVLOXSEG3EI16_V_M1_M1_MASK, VLOXSEG3EI16_V }, // 3414 |
22572 | | { PseudoVLOXSEG3EI16_V_M1_M2, VLOXSEG3EI16_V }, // 3415 |
22573 | | { PseudoVLOXSEG3EI16_V_M1_M2_MASK, VLOXSEG3EI16_V }, // 3416 |
22574 | | { PseudoVLOXSEG3EI16_V_M1_MF2, VLOXSEG3EI16_V }, // 3417 |
22575 | | { PseudoVLOXSEG3EI16_V_M1_MF2_MASK, VLOXSEG3EI16_V }, // 3418 |
22576 | | { PseudoVLOXSEG3EI16_V_M2_M1, VLOXSEG3EI16_V }, // 3419 |
22577 | | { PseudoVLOXSEG3EI16_V_M2_M1_MASK, VLOXSEG3EI16_V }, // 3420 |
22578 | | { PseudoVLOXSEG3EI16_V_M2_M2, VLOXSEG3EI16_V }, // 3421 |
22579 | | { PseudoVLOXSEG3EI16_V_M2_M2_MASK, VLOXSEG3EI16_V }, // 3422 |
22580 | | { PseudoVLOXSEG3EI16_V_M4_M2, VLOXSEG3EI16_V }, // 3423 |
22581 | | { PseudoVLOXSEG3EI16_V_M4_M2_MASK, VLOXSEG3EI16_V }, // 3424 |
22582 | | { PseudoVLOXSEG3EI16_V_MF2_M1, VLOXSEG3EI16_V }, // 3425 |
22583 | | { PseudoVLOXSEG3EI16_V_MF2_M1_MASK, VLOXSEG3EI16_V }, // 3426 |
22584 | | { PseudoVLOXSEG3EI16_V_MF2_M2, VLOXSEG3EI16_V }, // 3427 |
22585 | | { PseudoVLOXSEG3EI16_V_MF2_M2_MASK, VLOXSEG3EI16_V }, // 3428 |
22586 | | { PseudoVLOXSEG3EI16_V_MF2_MF2, VLOXSEG3EI16_V }, // 3429 |
22587 | | { PseudoVLOXSEG3EI16_V_MF2_MF2_MASK, VLOXSEG3EI16_V }, // 3430 |
22588 | | { PseudoVLOXSEG3EI16_V_MF2_MF4, VLOXSEG3EI16_V }, // 3431 |
22589 | | { PseudoVLOXSEG3EI16_V_MF2_MF4_MASK, VLOXSEG3EI16_V }, // 3432 |
22590 | | { PseudoVLOXSEG3EI16_V_MF4_M1, VLOXSEG3EI16_V }, // 3433 |
22591 | | { PseudoVLOXSEG3EI16_V_MF4_M1_MASK, VLOXSEG3EI16_V }, // 3434 |
22592 | | { PseudoVLOXSEG3EI16_V_MF4_MF2, VLOXSEG3EI16_V }, // 3435 |
22593 | | { PseudoVLOXSEG3EI16_V_MF4_MF2_MASK, VLOXSEG3EI16_V }, // 3436 |
22594 | | { PseudoVLOXSEG3EI16_V_MF4_MF4, VLOXSEG3EI16_V }, // 3437 |
22595 | | { PseudoVLOXSEG3EI16_V_MF4_MF4_MASK, VLOXSEG3EI16_V }, // 3438 |
22596 | | { PseudoVLOXSEG3EI16_V_MF4_MF8, VLOXSEG3EI16_V }, // 3439 |
22597 | | { PseudoVLOXSEG3EI16_V_MF4_MF8_MASK, VLOXSEG3EI16_V }, // 3440 |
22598 | | { PseudoVLOXSEG3EI32_V_M1_M1, VLOXSEG3EI32_V }, // 3441 |
22599 | | { PseudoVLOXSEG3EI32_V_M1_M1_MASK, VLOXSEG3EI32_V }, // 3442 |
22600 | | { PseudoVLOXSEG3EI32_V_M1_M2, VLOXSEG3EI32_V }, // 3443 |
22601 | | { PseudoVLOXSEG3EI32_V_M1_M2_MASK, VLOXSEG3EI32_V }, // 3444 |
22602 | | { PseudoVLOXSEG3EI32_V_M1_MF2, VLOXSEG3EI32_V }, // 3445 |
22603 | | { PseudoVLOXSEG3EI32_V_M1_MF2_MASK, VLOXSEG3EI32_V }, // 3446 |
22604 | | { PseudoVLOXSEG3EI32_V_M1_MF4, VLOXSEG3EI32_V }, // 3447 |
22605 | | { PseudoVLOXSEG3EI32_V_M1_MF4_MASK, VLOXSEG3EI32_V }, // 3448 |
22606 | | { PseudoVLOXSEG3EI32_V_M2_M1, VLOXSEG3EI32_V }, // 3449 |
22607 | | { PseudoVLOXSEG3EI32_V_M2_M1_MASK, VLOXSEG3EI32_V }, // 3450 |
22608 | | { PseudoVLOXSEG3EI32_V_M2_M2, VLOXSEG3EI32_V }, // 3451 |
22609 | | { PseudoVLOXSEG3EI32_V_M2_M2_MASK, VLOXSEG3EI32_V }, // 3452 |
22610 | | { PseudoVLOXSEG3EI32_V_M2_MF2, VLOXSEG3EI32_V }, // 3453 |
22611 | | { PseudoVLOXSEG3EI32_V_M2_MF2_MASK, VLOXSEG3EI32_V }, // 3454 |
22612 | | { PseudoVLOXSEG3EI32_V_M4_M1, VLOXSEG3EI32_V }, // 3455 |
22613 | | { PseudoVLOXSEG3EI32_V_M4_M1_MASK, VLOXSEG3EI32_V }, // 3456 |
22614 | | { PseudoVLOXSEG3EI32_V_M4_M2, VLOXSEG3EI32_V }, // 3457 |
22615 | | { PseudoVLOXSEG3EI32_V_M4_M2_MASK, VLOXSEG3EI32_V }, // 3458 |
22616 | | { PseudoVLOXSEG3EI32_V_M8_M2, VLOXSEG3EI32_V }, // 3459 |
22617 | | { PseudoVLOXSEG3EI32_V_M8_M2_MASK, VLOXSEG3EI32_V }, // 3460 |
22618 | | { PseudoVLOXSEG3EI32_V_MF2_M1, VLOXSEG3EI32_V }, // 3461 |
22619 | | { PseudoVLOXSEG3EI32_V_MF2_M1_MASK, VLOXSEG3EI32_V }, // 3462 |
22620 | | { PseudoVLOXSEG3EI32_V_MF2_MF2, VLOXSEG3EI32_V }, // 3463 |
22621 | | { PseudoVLOXSEG3EI32_V_MF2_MF2_MASK, VLOXSEG3EI32_V }, // 3464 |
22622 | | { PseudoVLOXSEG3EI32_V_MF2_MF4, VLOXSEG3EI32_V }, // 3465 |
22623 | | { PseudoVLOXSEG3EI32_V_MF2_MF4_MASK, VLOXSEG3EI32_V }, // 3466 |
22624 | | { PseudoVLOXSEG3EI32_V_MF2_MF8, VLOXSEG3EI32_V }, // 3467 |
22625 | | { PseudoVLOXSEG3EI32_V_MF2_MF8_MASK, VLOXSEG3EI32_V }, // 3468 |
22626 | | { PseudoVLOXSEG3EI64_V_M1_M1, VLOXSEG3EI64_V }, // 3469 |
22627 | | { PseudoVLOXSEG3EI64_V_M1_M1_MASK, VLOXSEG3EI64_V }, // 3470 |
22628 | | { PseudoVLOXSEG3EI64_V_M1_MF2, VLOXSEG3EI64_V }, // 3471 |
22629 | | { PseudoVLOXSEG3EI64_V_M1_MF2_MASK, VLOXSEG3EI64_V }, // 3472 |
22630 | | { PseudoVLOXSEG3EI64_V_M1_MF4, VLOXSEG3EI64_V }, // 3473 |
22631 | | { PseudoVLOXSEG3EI64_V_M1_MF4_MASK, VLOXSEG3EI64_V }, // 3474 |
22632 | | { PseudoVLOXSEG3EI64_V_M1_MF8, VLOXSEG3EI64_V }, // 3475 |
22633 | | { PseudoVLOXSEG3EI64_V_M1_MF8_MASK, VLOXSEG3EI64_V }, // 3476 |
22634 | | { PseudoVLOXSEG3EI64_V_M2_M1, VLOXSEG3EI64_V }, // 3477 |
22635 | | { PseudoVLOXSEG3EI64_V_M2_M1_MASK, VLOXSEG3EI64_V }, // 3478 |
22636 | | { PseudoVLOXSEG3EI64_V_M2_M2, VLOXSEG3EI64_V }, // 3479 |
22637 | | { PseudoVLOXSEG3EI64_V_M2_M2_MASK, VLOXSEG3EI64_V }, // 3480 |
22638 | | { PseudoVLOXSEG3EI64_V_M2_MF2, VLOXSEG3EI64_V }, // 3481 |
22639 | | { PseudoVLOXSEG3EI64_V_M2_MF2_MASK, VLOXSEG3EI64_V }, // 3482 |
22640 | | { PseudoVLOXSEG3EI64_V_M2_MF4, VLOXSEG3EI64_V }, // 3483 |
22641 | | { PseudoVLOXSEG3EI64_V_M2_MF4_MASK, VLOXSEG3EI64_V }, // 3484 |
22642 | | { PseudoVLOXSEG3EI64_V_M4_M1, VLOXSEG3EI64_V }, // 3485 |
22643 | | { PseudoVLOXSEG3EI64_V_M4_M1_MASK, VLOXSEG3EI64_V }, // 3486 |
22644 | | { PseudoVLOXSEG3EI64_V_M4_M2, VLOXSEG3EI64_V }, // 3487 |
22645 | | { PseudoVLOXSEG3EI64_V_M4_M2_MASK, VLOXSEG3EI64_V }, // 3488 |
22646 | | { PseudoVLOXSEG3EI64_V_M4_MF2, VLOXSEG3EI64_V }, // 3489 |
22647 | | { PseudoVLOXSEG3EI64_V_M4_MF2_MASK, VLOXSEG3EI64_V }, // 3490 |
22648 | | { PseudoVLOXSEG3EI64_V_M8_M1, VLOXSEG3EI64_V }, // 3491 |
22649 | | { PseudoVLOXSEG3EI64_V_M8_M1_MASK, VLOXSEG3EI64_V }, // 3492 |
22650 | | { PseudoVLOXSEG3EI64_V_M8_M2, VLOXSEG3EI64_V }, // 3493 |
22651 | | { PseudoVLOXSEG3EI64_V_M8_M2_MASK, VLOXSEG3EI64_V }, // 3494 |
22652 | | { PseudoVLOXSEG3EI8_V_M1_M1, VLOXSEG3EI8_V }, // 3495 |
22653 | | { PseudoVLOXSEG3EI8_V_M1_M1_MASK, VLOXSEG3EI8_V }, // 3496 |
22654 | | { PseudoVLOXSEG3EI8_V_M1_M2, VLOXSEG3EI8_V }, // 3497 |
22655 | | { PseudoVLOXSEG3EI8_V_M1_M2_MASK, VLOXSEG3EI8_V }, // 3498 |
22656 | | { PseudoVLOXSEG3EI8_V_M2_M2, VLOXSEG3EI8_V }, // 3499 |
22657 | | { PseudoVLOXSEG3EI8_V_M2_M2_MASK, VLOXSEG3EI8_V }, // 3500 |
22658 | | { PseudoVLOXSEG3EI8_V_MF2_M1, VLOXSEG3EI8_V }, // 3501 |
22659 | | { PseudoVLOXSEG3EI8_V_MF2_M1_MASK, VLOXSEG3EI8_V }, // 3502 |
22660 | | { PseudoVLOXSEG3EI8_V_MF2_M2, VLOXSEG3EI8_V }, // 3503 |
22661 | | { PseudoVLOXSEG3EI8_V_MF2_M2_MASK, VLOXSEG3EI8_V }, // 3504 |
22662 | | { PseudoVLOXSEG3EI8_V_MF2_MF2, VLOXSEG3EI8_V }, // 3505 |
22663 | | { PseudoVLOXSEG3EI8_V_MF2_MF2_MASK, VLOXSEG3EI8_V }, // 3506 |
22664 | | { PseudoVLOXSEG3EI8_V_MF4_M1, VLOXSEG3EI8_V }, // 3507 |
22665 | | { PseudoVLOXSEG3EI8_V_MF4_M1_MASK, VLOXSEG3EI8_V }, // 3508 |
22666 | | { PseudoVLOXSEG3EI8_V_MF4_M2, VLOXSEG3EI8_V }, // 3509 |
22667 | | { PseudoVLOXSEG3EI8_V_MF4_M2_MASK, VLOXSEG3EI8_V }, // 3510 |
22668 | | { PseudoVLOXSEG3EI8_V_MF4_MF2, VLOXSEG3EI8_V }, // 3511 |
22669 | | { PseudoVLOXSEG3EI8_V_MF4_MF2_MASK, VLOXSEG3EI8_V }, // 3512 |
22670 | | { PseudoVLOXSEG3EI8_V_MF4_MF4, VLOXSEG3EI8_V }, // 3513 |
22671 | | { PseudoVLOXSEG3EI8_V_MF4_MF4_MASK, VLOXSEG3EI8_V }, // 3514 |
22672 | | { PseudoVLOXSEG3EI8_V_MF8_M1, VLOXSEG3EI8_V }, // 3515 |
22673 | | { PseudoVLOXSEG3EI8_V_MF8_M1_MASK, VLOXSEG3EI8_V }, // 3516 |
22674 | | { PseudoVLOXSEG3EI8_V_MF8_MF2, VLOXSEG3EI8_V }, // 3517 |
22675 | | { PseudoVLOXSEG3EI8_V_MF8_MF2_MASK, VLOXSEG3EI8_V }, // 3518 |
22676 | | { PseudoVLOXSEG3EI8_V_MF8_MF4, VLOXSEG3EI8_V }, // 3519 |
22677 | | { PseudoVLOXSEG3EI8_V_MF8_MF4_MASK, VLOXSEG3EI8_V }, // 3520 |
22678 | | { PseudoVLOXSEG3EI8_V_MF8_MF8, VLOXSEG3EI8_V }, // 3521 |
22679 | | { PseudoVLOXSEG3EI8_V_MF8_MF8_MASK, VLOXSEG3EI8_V }, // 3522 |
22680 | | { PseudoVLOXSEG4EI16_V_M1_M1, VLOXSEG4EI16_V }, // 3523 |
22681 | | { PseudoVLOXSEG4EI16_V_M1_M1_MASK, VLOXSEG4EI16_V }, // 3524 |
22682 | | { PseudoVLOXSEG4EI16_V_M1_M2, VLOXSEG4EI16_V }, // 3525 |
22683 | | { PseudoVLOXSEG4EI16_V_M1_M2_MASK, VLOXSEG4EI16_V }, // 3526 |
22684 | | { PseudoVLOXSEG4EI16_V_M1_MF2, VLOXSEG4EI16_V }, // 3527 |
22685 | | { PseudoVLOXSEG4EI16_V_M1_MF2_MASK, VLOXSEG4EI16_V }, // 3528 |
22686 | | { PseudoVLOXSEG4EI16_V_M2_M1, VLOXSEG4EI16_V }, // 3529 |
22687 | | { PseudoVLOXSEG4EI16_V_M2_M1_MASK, VLOXSEG4EI16_V }, // 3530 |
22688 | | { PseudoVLOXSEG4EI16_V_M2_M2, VLOXSEG4EI16_V }, // 3531 |
22689 | | { PseudoVLOXSEG4EI16_V_M2_M2_MASK, VLOXSEG4EI16_V }, // 3532 |
22690 | | { PseudoVLOXSEG4EI16_V_M4_M2, VLOXSEG4EI16_V }, // 3533 |
22691 | | { PseudoVLOXSEG4EI16_V_M4_M2_MASK, VLOXSEG4EI16_V }, // 3534 |
22692 | | { PseudoVLOXSEG4EI16_V_MF2_M1, VLOXSEG4EI16_V }, // 3535 |
22693 | | { PseudoVLOXSEG4EI16_V_MF2_M1_MASK, VLOXSEG4EI16_V }, // 3536 |
22694 | | { PseudoVLOXSEG4EI16_V_MF2_M2, VLOXSEG4EI16_V }, // 3537 |
22695 | | { PseudoVLOXSEG4EI16_V_MF2_M2_MASK, VLOXSEG4EI16_V }, // 3538 |
22696 | | { PseudoVLOXSEG4EI16_V_MF2_MF2, VLOXSEG4EI16_V }, // 3539 |
22697 | | { PseudoVLOXSEG4EI16_V_MF2_MF2_MASK, VLOXSEG4EI16_V }, // 3540 |
22698 | | { PseudoVLOXSEG4EI16_V_MF2_MF4, VLOXSEG4EI16_V }, // 3541 |
22699 | | { PseudoVLOXSEG4EI16_V_MF2_MF4_MASK, VLOXSEG4EI16_V }, // 3542 |
22700 | | { PseudoVLOXSEG4EI16_V_MF4_M1, VLOXSEG4EI16_V }, // 3543 |
22701 | | { PseudoVLOXSEG4EI16_V_MF4_M1_MASK, VLOXSEG4EI16_V }, // 3544 |
22702 | | { PseudoVLOXSEG4EI16_V_MF4_MF2, VLOXSEG4EI16_V }, // 3545 |
22703 | | { PseudoVLOXSEG4EI16_V_MF4_MF2_MASK, VLOXSEG4EI16_V }, // 3546 |
22704 | | { PseudoVLOXSEG4EI16_V_MF4_MF4, VLOXSEG4EI16_V }, // 3547 |
22705 | | { PseudoVLOXSEG4EI16_V_MF4_MF4_MASK, VLOXSEG4EI16_V }, // 3548 |
22706 | | { PseudoVLOXSEG4EI16_V_MF4_MF8, VLOXSEG4EI16_V }, // 3549 |
22707 | | { PseudoVLOXSEG4EI16_V_MF4_MF8_MASK, VLOXSEG4EI16_V }, // 3550 |
22708 | | { PseudoVLOXSEG4EI32_V_M1_M1, VLOXSEG4EI32_V }, // 3551 |
22709 | | { PseudoVLOXSEG4EI32_V_M1_M1_MASK, VLOXSEG4EI32_V }, // 3552 |
22710 | | { PseudoVLOXSEG4EI32_V_M1_M2, VLOXSEG4EI32_V }, // 3553 |
22711 | | { PseudoVLOXSEG4EI32_V_M1_M2_MASK, VLOXSEG4EI32_V }, // 3554 |
22712 | | { PseudoVLOXSEG4EI32_V_M1_MF2, VLOXSEG4EI32_V }, // 3555 |
22713 | | { PseudoVLOXSEG4EI32_V_M1_MF2_MASK, VLOXSEG4EI32_V }, // 3556 |
22714 | | { PseudoVLOXSEG4EI32_V_M1_MF4, VLOXSEG4EI32_V }, // 3557 |
22715 | | { PseudoVLOXSEG4EI32_V_M1_MF4_MASK, VLOXSEG4EI32_V }, // 3558 |
22716 | | { PseudoVLOXSEG4EI32_V_M2_M1, VLOXSEG4EI32_V }, // 3559 |
22717 | | { PseudoVLOXSEG4EI32_V_M2_M1_MASK, VLOXSEG4EI32_V }, // 3560 |
22718 | | { PseudoVLOXSEG4EI32_V_M2_M2, VLOXSEG4EI32_V }, // 3561 |
22719 | | { PseudoVLOXSEG4EI32_V_M2_M2_MASK, VLOXSEG4EI32_V }, // 3562 |
22720 | | { PseudoVLOXSEG4EI32_V_M2_MF2, VLOXSEG4EI32_V }, // 3563 |
22721 | | { PseudoVLOXSEG4EI32_V_M2_MF2_MASK, VLOXSEG4EI32_V }, // 3564 |
22722 | | { PseudoVLOXSEG4EI32_V_M4_M1, VLOXSEG4EI32_V }, // 3565 |
22723 | | { PseudoVLOXSEG4EI32_V_M4_M1_MASK, VLOXSEG4EI32_V }, // 3566 |
22724 | | { PseudoVLOXSEG4EI32_V_M4_M2, VLOXSEG4EI32_V }, // 3567 |
22725 | | { PseudoVLOXSEG4EI32_V_M4_M2_MASK, VLOXSEG4EI32_V }, // 3568 |
22726 | | { PseudoVLOXSEG4EI32_V_M8_M2, VLOXSEG4EI32_V }, // 3569 |
22727 | | { PseudoVLOXSEG4EI32_V_M8_M2_MASK, VLOXSEG4EI32_V }, // 3570 |
22728 | | { PseudoVLOXSEG4EI32_V_MF2_M1, VLOXSEG4EI32_V }, // 3571 |
22729 | | { PseudoVLOXSEG4EI32_V_MF2_M1_MASK, VLOXSEG4EI32_V }, // 3572 |
22730 | | { PseudoVLOXSEG4EI32_V_MF2_MF2, VLOXSEG4EI32_V }, // 3573 |
22731 | | { PseudoVLOXSEG4EI32_V_MF2_MF2_MASK, VLOXSEG4EI32_V }, // 3574 |
22732 | | { PseudoVLOXSEG4EI32_V_MF2_MF4, VLOXSEG4EI32_V }, // 3575 |
22733 | | { PseudoVLOXSEG4EI32_V_MF2_MF4_MASK, VLOXSEG4EI32_V }, // 3576 |
22734 | | { PseudoVLOXSEG4EI32_V_MF2_MF8, VLOXSEG4EI32_V }, // 3577 |
22735 | | { PseudoVLOXSEG4EI32_V_MF2_MF8_MASK, VLOXSEG4EI32_V }, // 3578 |
22736 | | { PseudoVLOXSEG4EI64_V_M1_M1, VLOXSEG4EI64_V }, // 3579 |
22737 | | { PseudoVLOXSEG4EI64_V_M1_M1_MASK, VLOXSEG4EI64_V }, // 3580 |
22738 | | { PseudoVLOXSEG4EI64_V_M1_MF2, VLOXSEG4EI64_V }, // 3581 |
22739 | | { PseudoVLOXSEG4EI64_V_M1_MF2_MASK, VLOXSEG4EI64_V }, // 3582 |
22740 | | { PseudoVLOXSEG4EI64_V_M1_MF4, VLOXSEG4EI64_V }, // 3583 |
22741 | | { PseudoVLOXSEG4EI64_V_M1_MF4_MASK, VLOXSEG4EI64_V }, // 3584 |
22742 | | { PseudoVLOXSEG4EI64_V_M1_MF8, VLOXSEG4EI64_V }, // 3585 |
22743 | | { PseudoVLOXSEG4EI64_V_M1_MF8_MASK, VLOXSEG4EI64_V }, // 3586 |
22744 | | { PseudoVLOXSEG4EI64_V_M2_M1, VLOXSEG4EI64_V }, // 3587 |
22745 | | { PseudoVLOXSEG4EI64_V_M2_M1_MASK, VLOXSEG4EI64_V }, // 3588 |
22746 | | { PseudoVLOXSEG4EI64_V_M2_M2, VLOXSEG4EI64_V }, // 3589 |
22747 | | { PseudoVLOXSEG4EI64_V_M2_M2_MASK, VLOXSEG4EI64_V }, // 3590 |
22748 | | { PseudoVLOXSEG4EI64_V_M2_MF2, VLOXSEG4EI64_V }, // 3591 |
22749 | | { PseudoVLOXSEG4EI64_V_M2_MF2_MASK, VLOXSEG4EI64_V }, // 3592 |
22750 | | { PseudoVLOXSEG4EI64_V_M2_MF4, VLOXSEG4EI64_V }, // 3593 |
22751 | | { PseudoVLOXSEG4EI64_V_M2_MF4_MASK, VLOXSEG4EI64_V }, // 3594 |
22752 | | { PseudoVLOXSEG4EI64_V_M4_M1, VLOXSEG4EI64_V }, // 3595 |
22753 | | { PseudoVLOXSEG4EI64_V_M4_M1_MASK, VLOXSEG4EI64_V }, // 3596 |
22754 | | { PseudoVLOXSEG4EI64_V_M4_M2, VLOXSEG4EI64_V }, // 3597 |
22755 | | { PseudoVLOXSEG4EI64_V_M4_M2_MASK, VLOXSEG4EI64_V }, // 3598 |
22756 | | { PseudoVLOXSEG4EI64_V_M4_MF2, VLOXSEG4EI64_V }, // 3599 |
22757 | | { PseudoVLOXSEG4EI64_V_M4_MF2_MASK, VLOXSEG4EI64_V }, // 3600 |
22758 | | { PseudoVLOXSEG4EI64_V_M8_M1, VLOXSEG4EI64_V }, // 3601 |
22759 | | { PseudoVLOXSEG4EI64_V_M8_M1_MASK, VLOXSEG4EI64_V }, // 3602 |
22760 | | { PseudoVLOXSEG4EI64_V_M8_M2, VLOXSEG4EI64_V }, // 3603 |
22761 | | { PseudoVLOXSEG4EI64_V_M8_M2_MASK, VLOXSEG4EI64_V }, // 3604 |
22762 | | { PseudoVLOXSEG4EI8_V_M1_M1, VLOXSEG4EI8_V }, // 3605 |
22763 | | { PseudoVLOXSEG4EI8_V_M1_M1_MASK, VLOXSEG4EI8_V }, // 3606 |
22764 | | { PseudoVLOXSEG4EI8_V_M1_M2, VLOXSEG4EI8_V }, // 3607 |
22765 | | { PseudoVLOXSEG4EI8_V_M1_M2_MASK, VLOXSEG4EI8_V }, // 3608 |
22766 | | { PseudoVLOXSEG4EI8_V_M2_M2, VLOXSEG4EI8_V }, // 3609 |
22767 | | { PseudoVLOXSEG4EI8_V_M2_M2_MASK, VLOXSEG4EI8_V }, // 3610 |
22768 | | { PseudoVLOXSEG4EI8_V_MF2_M1, VLOXSEG4EI8_V }, // 3611 |
22769 | | { PseudoVLOXSEG4EI8_V_MF2_M1_MASK, VLOXSEG4EI8_V }, // 3612 |
22770 | | { PseudoVLOXSEG4EI8_V_MF2_M2, VLOXSEG4EI8_V }, // 3613 |
22771 | | { PseudoVLOXSEG4EI8_V_MF2_M2_MASK, VLOXSEG4EI8_V }, // 3614 |
22772 | | { PseudoVLOXSEG4EI8_V_MF2_MF2, VLOXSEG4EI8_V }, // 3615 |
22773 | | { PseudoVLOXSEG4EI8_V_MF2_MF2_MASK, VLOXSEG4EI8_V }, // 3616 |
22774 | | { PseudoVLOXSEG4EI8_V_MF4_M1, VLOXSEG4EI8_V }, // 3617 |
22775 | | { PseudoVLOXSEG4EI8_V_MF4_M1_MASK, VLOXSEG4EI8_V }, // 3618 |
22776 | | { PseudoVLOXSEG4EI8_V_MF4_M2, VLOXSEG4EI8_V }, // 3619 |
22777 | | { PseudoVLOXSEG4EI8_V_MF4_M2_MASK, VLOXSEG4EI8_V }, // 3620 |
22778 | | { PseudoVLOXSEG4EI8_V_MF4_MF2, VLOXSEG4EI8_V }, // 3621 |
22779 | | { PseudoVLOXSEG4EI8_V_MF4_MF2_MASK, VLOXSEG4EI8_V }, // 3622 |
22780 | | { PseudoVLOXSEG4EI8_V_MF4_MF4, VLOXSEG4EI8_V }, // 3623 |
22781 | | { PseudoVLOXSEG4EI8_V_MF4_MF4_MASK, VLOXSEG4EI8_V }, // 3624 |
22782 | | { PseudoVLOXSEG4EI8_V_MF8_M1, VLOXSEG4EI8_V }, // 3625 |
22783 | | { PseudoVLOXSEG4EI8_V_MF8_M1_MASK, VLOXSEG4EI8_V }, // 3626 |
22784 | | { PseudoVLOXSEG4EI8_V_MF8_MF2, VLOXSEG4EI8_V }, // 3627 |
22785 | | { PseudoVLOXSEG4EI8_V_MF8_MF2_MASK, VLOXSEG4EI8_V }, // 3628 |
22786 | | { PseudoVLOXSEG4EI8_V_MF8_MF4, VLOXSEG4EI8_V }, // 3629 |
22787 | | { PseudoVLOXSEG4EI8_V_MF8_MF4_MASK, VLOXSEG4EI8_V }, // 3630 |
22788 | | { PseudoVLOXSEG4EI8_V_MF8_MF8, VLOXSEG4EI8_V }, // 3631 |
22789 | | { PseudoVLOXSEG4EI8_V_MF8_MF8_MASK, VLOXSEG4EI8_V }, // 3632 |
22790 | | { PseudoVLOXSEG5EI16_V_M1_M1, VLOXSEG5EI16_V }, // 3633 |
22791 | | { PseudoVLOXSEG5EI16_V_M1_M1_MASK, VLOXSEG5EI16_V }, // 3634 |
22792 | | { PseudoVLOXSEG5EI16_V_M1_MF2, VLOXSEG5EI16_V }, // 3635 |
22793 | | { PseudoVLOXSEG5EI16_V_M1_MF2_MASK, VLOXSEG5EI16_V }, // 3636 |
22794 | | { PseudoVLOXSEG5EI16_V_M2_M1, VLOXSEG5EI16_V }, // 3637 |
22795 | | { PseudoVLOXSEG5EI16_V_M2_M1_MASK, VLOXSEG5EI16_V }, // 3638 |
22796 | | { PseudoVLOXSEG5EI16_V_MF2_M1, VLOXSEG5EI16_V }, // 3639 |
22797 | | { PseudoVLOXSEG5EI16_V_MF2_M1_MASK, VLOXSEG5EI16_V }, // 3640 |
22798 | | { PseudoVLOXSEG5EI16_V_MF2_MF2, VLOXSEG5EI16_V }, // 3641 |
22799 | | { PseudoVLOXSEG5EI16_V_MF2_MF2_MASK, VLOXSEG5EI16_V }, // 3642 |
22800 | | { PseudoVLOXSEG5EI16_V_MF2_MF4, VLOXSEG5EI16_V }, // 3643 |
22801 | | { PseudoVLOXSEG5EI16_V_MF2_MF4_MASK, VLOXSEG5EI16_V }, // 3644 |
22802 | | { PseudoVLOXSEG5EI16_V_MF4_M1, VLOXSEG5EI16_V }, // 3645 |
22803 | | { PseudoVLOXSEG5EI16_V_MF4_M1_MASK, VLOXSEG5EI16_V }, // 3646 |
22804 | | { PseudoVLOXSEG5EI16_V_MF4_MF2, VLOXSEG5EI16_V }, // 3647 |
22805 | | { PseudoVLOXSEG5EI16_V_MF4_MF2_MASK, VLOXSEG5EI16_V }, // 3648 |
22806 | | { PseudoVLOXSEG5EI16_V_MF4_MF4, VLOXSEG5EI16_V }, // 3649 |
22807 | | { PseudoVLOXSEG5EI16_V_MF4_MF4_MASK, VLOXSEG5EI16_V }, // 3650 |
22808 | | { PseudoVLOXSEG5EI16_V_MF4_MF8, VLOXSEG5EI16_V }, // 3651 |
22809 | | { PseudoVLOXSEG5EI16_V_MF4_MF8_MASK, VLOXSEG5EI16_V }, // 3652 |
22810 | | { PseudoVLOXSEG5EI32_V_M1_M1, VLOXSEG5EI32_V }, // 3653 |
22811 | | { PseudoVLOXSEG5EI32_V_M1_M1_MASK, VLOXSEG5EI32_V }, // 3654 |
22812 | | { PseudoVLOXSEG5EI32_V_M1_MF2, VLOXSEG5EI32_V }, // 3655 |
22813 | | { PseudoVLOXSEG5EI32_V_M1_MF2_MASK, VLOXSEG5EI32_V }, // 3656 |
22814 | | { PseudoVLOXSEG5EI32_V_M1_MF4, VLOXSEG5EI32_V }, // 3657 |
22815 | | { PseudoVLOXSEG5EI32_V_M1_MF4_MASK, VLOXSEG5EI32_V }, // 3658 |
22816 | | { PseudoVLOXSEG5EI32_V_M2_M1, VLOXSEG5EI32_V }, // 3659 |
22817 | | { PseudoVLOXSEG5EI32_V_M2_M1_MASK, VLOXSEG5EI32_V }, // 3660 |
22818 | | { PseudoVLOXSEG5EI32_V_M2_MF2, VLOXSEG5EI32_V }, // 3661 |
22819 | | { PseudoVLOXSEG5EI32_V_M2_MF2_MASK, VLOXSEG5EI32_V }, // 3662 |
22820 | | { PseudoVLOXSEG5EI32_V_M4_M1, VLOXSEG5EI32_V }, // 3663 |
22821 | | { PseudoVLOXSEG5EI32_V_M4_M1_MASK, VLOXSEG5EI32_V }, // 3664 |
22822 | | { PseudoVLOXSEG5EI32_V_MF2_M1, VLOXSEG5EI32_V }, // 3665 |
22823 | | { PseudoVLOXSEG5EI32_V_MF2_M1_MASK, VLOXSEG5EI32_V }, // 3666 |
22824 | | { PseudoVLOXSEG5EI32_V_MF2_MF2, VLOXSEG5EI32_V }, // 3667 |
22825 | | { PseudoVLOXSEG5EI32_V_MF2_MF2_MASK, VLOXSEG5EI32_V }, // 3668 |
22826 | | { PseudoVLOXSEG5EI32_V_MF2_MF4, VLOXSEG5EI32_V }, // 3669 |
22827 | | { PseudoVLOXSEG5EI32_V_MF2_MF4_MASK, VLOXSEG5EI32_V }, // 3670 |
22828 | | { PseudoVLOXSEG5EI32_V_MF2_MF8, VLOXSEG5EI32_V }, // 3671 |
22829 | | { PseudoVLOXSEG5EI32_V_MF2_MF8_MASK, VLOXSEG5EI32_V }, // 3672 |
22830 | | { PseudoVLOXSEG5EI64_V_M1_M1, VLOXSEG5EI64_V }, // 3673 |
22831 | | { PseudoVLOXSEG5EI64_V_M1_M1_MASK, VLOXSEG5EI64_V }, // 3674 |
22832 | | { PseudoVLOXSEG5EI64_V_M1_MF2, VLOXSEG5EI64_V }, // 3675 |
22833 | | { PseudoVLOXSEG5EI64_V_M1_MF2_MASK, VLOXSEG5EI64_V }, // 3676 |
22834 | | { PseudoVLOXSEG5EI64_V_M1_MF4, VLOXSEG5EI64_V }, // 3677 |
22835 | | { PseudoVLOXSEG5EI64_V_M1_MF4_MASK, VLOXSEG5EI64_V }, // 3678 |
22836 | | { PseudoVLOXSEG5EI64_V_M1_MF8, VLOXSEG5EI64_V }, // 3679 |
22837 | | { PseudoVLOXSEG5EI64_V_M1_MF8_MASK, VLOXSEG5EI64_V }, // 3680 |
22838 | | { PseudoVLOXSEG5EI64_V_M2_M1, VLOXSEG5EI64_V }, // 3681 |
22839 | | { PseudoVLOXSEG5EI64_V_M2_M1_MASK, VLOXSEG5EI64_V }, // 3682 |
22840 | | { PseudoVLOXSEG5EI64_V_M2_MF2, VLOXSEG5EI64_V }, // 3683 |
22841 | | { PseudoVLOXSEG5EI64_V_M2_MF2_MASK, VLOXSEG5EI64_V }, // 3684 |
22842 | | { PseudoVLOXSEG5EI64_V_M2_MF4, VLOXSEG5EI64_V }, // 3685 |
22843 | | { PseudoVLOXSEG5EI64_V_M2_MF4_MASK, VLOXSEG5EI64_V }, // 3686 |
22844 | | { PseudoVLOXSEG5EI64_V_M4_M1, VLOXSEG5EI64_V }, // 3687 |
22845 | | { PseudoVLOXSEG5EI64_V_M4_M1_MASK, VLOXSEG5EI64_V }, // 3688 |
22846 | | { PseudoVLOXSEG5EI64_V_M4_MF2, VLOXSEG5EI64_V }, // 3689 |
22847 | | { PseudoVLOXSEG5EI64_V_M4_MF2_MASK, VLOXSEG5EI64_V }, // 3690 |
22848 | | { PseudoVLOXSEG5EI64_V_M8_M1, VLOXSEG5EI64_V }, // 3691 |
22849 | | { PseudoVLOXSEG5EI64_V_M8_M1_MASK, VLOXSEG5EI64_V }, // 3692 |
22850 | | { PseudoVLOXSEG5EI8_V_M1_M1, VLOXSEG5EI8_V }, // 3693 |
22851 | | { PseudoVLOXSEG5EI8_V_M1_M1_MASK, VLOXSEG5EI8_V }, // 3694 |
22852 | | { PseudoVLOXSEG5EI8_V_MF2_M1, VLOXSEG5EI8_V }, // 3695 |
22853 | | { PseudoVLOXSEG5EI8_V_MF2_M1_MASK, VLOXSEG5EI8_V }, // 3696 |
22854 | | { PseudoVLOXSEG5EI8_V_MF2_MF2, VLOXSEG5EI8_V }, // 3697 |
22855 | | { PseudoVLOXSEG5EI8_V_MF2_MF2_MASK, VLOXSEG5EI8_V }, // 3698 |
22856 | | { PseudoVLOXSEG5EI8_V_MF4_M1, VLOXSEG5EI8_V }, // 3699 |
22857 | | { PseudoVLOXSEG5EI8_V_MF4_M1_MASK, VLOXSEG5EI8_V }, // 3700 |
22858 | | { PseudoVLOXSEG5EI8_V_MF4_MF2, VLOXSEG5EI8_V }, // 3701 |
22859 | | { PseudoVLOXSEG5EI8_V_MF4_MF2_MASK, VLOXSEG5EI8_V }, // 3702 |
22860 | | { PseudoVLOXSEG5EI8_V_MF4_MF4, VLOXSEG5EI8_V }, // 3703 |
22861 | | { PseudoVLOXSEG5EI8_V_MF4_MF4_MASK, VLOXSEG5EI8_V }, // 3704 |
22862 | | { PseudoVLOXSEG5EI8_V_MF8_M1, VLOXSEG5EI8_V }, // 3705 |
22863 | | { PseudoVLOXSEG5EI8_V_MF8_M1_MASK, VLOXSEG5EI8_V }, // 3706 |
22864 | | { PseudoVLOXSEG5EI8_V_MF8_MF2, VLOXSEG5EI8_V }, // 3707 |
22865 | | { PseudoVLOXSEG5EI8_V_MF8_MF2_MASK, VLOXSEG5EI8_V }, // 3708 |
22866 | | { PseudoVLOXSEG5EI8_V_MF8_MF4, VLOXSEG5EI8_V }, // 3709 |
22867 | | { PseudoVLOXSEG5EI8_V_MF8_MF4_MASK, VLOXSEG5EI8_V }, // 3710 |
22868 | | { PseudoVLOXSEG5EI8_V_MF8_MF8, VLOXSEG5EI8_V }, // 3711 |
22869 | | { PseudoVLOXSEG5EI8_V_MF8_MF8_MASK, VLOXSEG5EI8_V }, // 3712 |
22870 | | { PseudoVLOXSEG6EI16_V_M1_M1, VLOXSEG6EI16_V }, // 3713 |
22871 | | { PseudoVLOXSEG6EI16_V_M1_M1_MASK, VLOXSEG6EI16_V }, // 3714 |
22872 | | { PseudoVLOXSEG6EI16_V_M1_MF2, VLOXSEG6EI16_V }, // 3715 |
22873 | | { PseudoVLOXSEG6EI16_V_M1_MF2_MASK, VLOXSEG6EI16_V }, // 3716 |
22874 | | { PseudoVLOXSEG6EI16_V_M2_M1, VLOXSEG6EI16_V }, // 3717 |
22875 | | { PseudoVLOXSEG6EI16_V_M2_M1_MASK, VLOXSEG6EI16_V }, // 3718 |
22876 | | { PseudoVLOXSEG6EI16_V_MF2_M1, VLOXSEG6EI16_V }, // 3719 |
22877 | | { PseudoVLOXSEG6EI16_V_MF2_M1_MASK, VLOXSEG6EI16_V }, // 3720 |
22878 | | { PseudoVLOXSEG6EI16_V_MF2_MF2, VLOXSEG6EI16_V }, // 3721 |
22879 | | { PseudoVLOXSEG6EI16_V_MF2_MF2_MASK, VLOXSEG6EI16_V }, // 3722 |
22880 | | { PseudoVLOXSEG6EI16_V_MF2_MF4, VLOXSEG6EI16_V }, // 3723 |
22881 | | { PseudoVLOXSEG6EI16_V_MF2_MF4_MASK, VLOXSEG6EI16_V }, // 3724 |
22882 | | { PseudoVLOXSEG6EI16_V_MF4_M1, VLOXSEG6EI16_V }, // 3725 |
22883 | | { PseudoVLOXSEG6EI16_V_MF4_M1_MASK, VLOXSEG6EI16_V }, // 3726 |
22884 | | { PseudoVLOXSEG6EI16_V_MF4_MF2, VLOXSEG6EI16_V }, // 3727 |
22885 | | { PseudoVLOXSEG6EI16_V_MF4_MF2_MASK, VLOXSEG6EI16_V }, // 3728 |
22886 | | { PseudoVLOXSEG6EI16_V_MF4_MF4, VLOXSEG6EI16_V }, // 3729 |
22887 | | { PseudoVLOXSEG6EI16_V_MF4_MF4_MASK, VLOXSEG6EI16_V }, // 3730 |
22888 | | { PseudoVLOXSEG6EI16_V_MF4_MF8, VLOXSEG6EI16_V }, // 3731 |
22889 | | { PseudoVLOXSEG6EI16_V_MF4_MF8_MASK, VLOXSEG6EI16_V }, // 3732 |
22890 | | { PseudoVLOXSEG6EI32_V_M1_M1, VLOXSEG6EI32_V }, // 3733 |
22891 | | { PseudoVLOXSEG6EI32_V_M1_M1_MASK, VLOXSEG6EI32_V }, // 3734 |
22892 | | { PseudoVLOXSEG6EI32_V_M1_MF2, VLOXSEG6EI32_V }, // 3735 |
22893 | | { PseudoVLOXSEG6EI32_V_M1_MF2_MASK, VLOXSEG6EI32_V }, // 3736 |
22894 | | { PseudoVLOXSEG6EI32_V_M1_MF4, VLOXSEG6EI32_V }, // 3737 |
22895 | | { PseudoVLOXSEG6EI32_V_M1_MF4_MASK, VLOXSEG6EI32_V }, // 3738 |
22896 | | { PseudoVLOXSEG6EI32_V_M2_M1, VLOXSEG6EI32_V }, // 3739 |
22897 | | { PseudoVLOXSEG6EI32_V_M2_M1_MASK, VLOXSEG6EI32_V }, // 3740 |
22898 | | { PseudoVLOXSEG6EI32_V_M2_MF2, VLOXSEG6EI32_V }, // 3741 |
22899 | | { PseudoVLOXSEG6EI32_V_M2_MF2_MASK, VLOXSEG6EI32_V }, // 3742 |
22900 | | { PseudoVLOXSEG6EI32_V_M4_M1, VLOXSEG6EI32_V }, // 3743 |
22901 | | { PseudoVLOXSEG6EI32_V_M4_M1_MASK, VLOXSEG6EI32_V }, // 3744 |
22902 | | { PseudoVLOXSEG6EI32_V_MF2_M1, VLOXSEG6EI32_V }, // 3745 |
22903 | | { PseudoVLOXSEG6EI32_V_MF2_M1_MASK, VLOXSEG6EI32_V }, // 3746 |
22904 | | { PseudoVLOXSEG6EI32_V_MF2_MF2, VLOXSEG6EI32_V }, // 3747 |
22905 | | { PseudoVLOXSEG6EI32_V_MF2_MF2_MASK, VLOXSEG6EI32_V }, // 3748 |
22906 | | { PseudoVLOXSEG6EI32_V_MF2_MF4, VLOXSEG6EI32_V }, // 3749 |
22907 | | { PseudoVLOXSEG6EI32_V_MF2_MF4_MASK, VLOXSEG6EI32_V }, // 3750 |
22908 | | { PseudoVLOXSEG6EI32_V_MF2_MF8, VLOXSEG6EI32_V }, // 3751 |
22909 | | { PseudoVLOXSEG6EI32_V_MF2_MF8_MASK, VLOXSEG6EI32_V }, // 3752 |
22910 | | { PseudoVLOXSEG6EI64_V_M1_M1, VLOXSEG6EI64_V }, // 3753 |
22911 | | { PseudoVLOXSEG6EI64_V_M1_M1_MASK, VLOXSEG6EI64_V }, // 3754 |
22912 | | { PseudoVLOXSEG6EI64_V_M1_MF2, VLOXSEG6EI64_V }, // 3755 |
22913 | | { PseudoVLOXSEG6EI64_V_M1_MF2_MASK, VLOXSEG6EI64_V }, // 3756 |
22914 | | { PseudoVLOXSEG6EI64_V_M1_MF4, VLOXSEG6EI64_V }, // 3757 |
22915 | | { PseudoVLOXSEG6EI64_V_M1_MF4_MASK, VLOXSEG6EI64_V }, // 3758 |
22916 | | { PseudoVLOXSEG6EI64_V_M1_MF8, VLOXSEG6EI64_V }, // 3759 |
22917 | | { PseudoVLOXSEG6EI64_V_M1_MF8_MASK, VLOXSEG6EI64_V }, // 3760 |
22918 | | { PseudoVLOXSEG6EI64_V_M2_M1, VLOXSEG6EI64_V }, // 3761 |
22919 | | { PseudoVLOXSEG6EI64_V_M2_M1_MASK, VLOXSEG6EI64_V }, // 3762 |
22920 | | { PseudoVLOXSEG6EI64_V_M2_MF2, VLOXSEG6EI64_V }, // 3763 |
22921 | | { PseudoVLOXSEG6EI64_V_M2_MF2_MASK, VLOXSEG6EI64_V }, // 3764 |
22922 | | { PseudoVLOXSEG6EI64_V_M2_MF4, VLOXSEG6EI64_V }, // 3765 |
22923 | | { PseudoVLOXSEG6EI64_V_M2_MF4_MASK, VLOXSEG6EI64_V }, // 3766 |
22924 | | { PseudoVLOXSEG6EI64_V_M4_M1, VLOXSEG6EI64_V }, // 3767 |
22925 | | { PseudoVLOXSEG6EI64_V_M4_M1_MASK, VLOXSEG6EI64_V }, // 3768 |
22926 | | { PseudoVLOXSEG6EI64_V_M4_MF2, VLOXSEG6EI64_V }, // 3769 |
22927 | | { PseudoVLOXSEG6EI64_V_M4_MF2_MASK, VLOXSEG6EI64_V }, // 3770 |
22928 | | { PseudoVLOXSEG6EI64_V_M8_M1, VLOXSEG6EI64_V }, // 3771 |
22929 | | { PseudoVLOXSEG6EI64_V_M8_M1_MASK, VLOXSEG6EI64_V }, // 3772 |
22930 | | { PseudoVLOXSEG6EI8_V_M1_M1, VLOXSEG6EI8_V }, // 3773 |
22931 | | { PseudoVLOXSEG6EI8_V_M1_M1_MASK, VLOXSEG6EI8_V }, // 3774 |
22932 | | { PseudoVLOXSEG6EI8_V_MF2_M1, VLOXSEG6EI8_V }, // 3775 |
22933 | | { PseudoVLOXSEG6EI8_V_MF2_M1_MASK, VLOXSEG6EI8_V }, // 3776 |
22934 | | { PseudoVLOXSEG6EI8_V_MF2_MF2, VLOXSEG6EI8_V }, // 3777 |
22935 | | { PseudoVLOXSEG6EI8_V_MF2_MF2_MASK, VLOXSEG6EI8_V }, // 3778 |
22936 | | { PseudoVLOXSEG6EI8_V_MF4_M1, VLOXSEG6EI8_V }, // 3779 |
22937 | | { PseudoVLOXSEG6EI8_V_MF4_M1_MASK, VLOXSEG6EI8_V }, // 3780 |
22938 | | { PseudoVLOXSEG6EI8_V_MF4_MF2, VLOXSEG6EI8_V }, // 3781 |
22939 | | { PseudoVLOXSEG6EI8_V_MF4_MF2_MASK, VLOXSEG6EI8_V }, // 3782 |
22940 | | { PseudoVLOXSEG6EI8_V_MF4_MF4, VLOXSEG6EI8_V }, // 3783 |
22941 | | { PseudoVLOXSEG6EI8_V_MF4_MF4_MASK, VLOXSEG6EI8_V }, // 3784 |
22942 | | { PseudoVLOXSEG6EI8_V_MF8_M1, VLOXSEG6EI8_V }, // 3785 |
22943 | | { PseudoVLOXSEG6EI8_V_MF8_M1_MASK, VLOXSEG6EI8_V }, // 3786 |
22944 | | { PseudoVLOXSEG6EI8_V_MF8_MF2, VLOXSEG6EI8_V }, // 3787 |
22945 | | { PseudoVLOXSEG6EI8_V_MF8_MF2_MASK, VLOXSEG6EI8_V }, // 3788 |
22946 | | { PseudoVLOXSEG6EI8_V_MF8_MF4, VLOXSEG6EI8_V }, // 3789 |
22947 | | { PseudoVLOXSEG6EI8_V_MF8_MF4_MASK, VLOXSEG6EI8_V }, // 3790 |
22948 | | { PseudoVLOXSEG6EI8_V_MF8_MF8, VLOXSEG6EI8_V }, // 3791 |
22949 | | { PseudoVLOXSEG6EI8_V_MF8_MF8_MASK, VLOXSEG6EI8_V }, // 3792 |
22950 | | { PseudoVLOXSEG7EI16_V_M1_M1, VLOXSEG7EI16_V }, // 3793 |
22951 | | { PseudoVLOXSEG7EI16_V_M1_M1_MASK, VLOXSEG7EI16_V }, // 3794 |
22952 | | { PseudoVLOXSEG7EI16_V_M1_MF2, VLOXSEG7EI16_V }, // 3795 |
22953 | | { PseudoVLOXSEG7EI16_V_M1_MF2_MASK, VLOXSEG7EI16_V }, // 3796 |
22954 | | { PseudoVLOXSEG7EI16_V_M2_M1, VLOXSEG7EI16_V }, // 3797 |
22955 | | { PseudoVLOXSEG7EI16_V_M2_M1_MASK, VLOXSEG7EI16_V }, // 3798 |
22956 | | { PseudoVLOXSEG7EI16_V_MF2_M1, VLOXSEG7EI16_V }, // 3799 |
22957 | | { PseudoVLOXSEG7EI16_V_MF2_M1_MASK, VLOXSEG7EI16_V }, // 3800 |
22958 | | { PseudoVLOXSEG7EI16_V_MF2_MF2, VLOXSEG7EI16_V }, // 3801 |
22959 | | { PseudoVLOXSEG7EI16_V_MF2_MF2_MASK, VLOXSEG7EI16_V }, // 3802 |
22960 | | { PseudoVLOXSEG7EI16_V_MF2_MF4, VLOXSEG7EI16_V }, // 3803 |
22961 | | { PseudoVLOXSEG7EI16_V_MF2_MF4_MASK, VLOXSEG7EI16_V }, // 3804 |
22962 | | { PseudoVLOXSEG7EI16_V_MF4_M1, VLOXSEG7EI16_V }, // 3805 |
22963 | | { PseudoVLOXSEG7EI16_V_MF4_M1_MASK, VLOXSEG7EI16_V }, // 3806 |
22964 | | { PseudoVLOXSEG7EI16_V_MF4_MF2, VLOXSEG7EI16_V }, // 3807 |
22965 | | { PseudoVLOXSEG7EI16_V_MF4_MF2_MASK, VLOXSEG7EI16_V }, // 3808 |
22966 | | { PseudoVLOXSEG7EI16_V_MF4_MF4, VLOXSEG7EI16_V }, // 3809 |
22967 | | { PseudoVLOXSEG7EI16_V_MF4_MF4_MASK, VLOXSEG7EI16_V }, // 3810 |
22968 | | { PseudoVLOXSEG7EI16_V_MF4_MF8, VLOXSEG7EI16_V }, // 3811 |
22969 | | { PseudoVLOXSEG7EI16_V_MF4_MF8_MASK, VLOXSEG7EI16_V }, // 3812 |
22970 | | { PseudoVLOXSEG7EI32_V_M1_M1, VLOXSEG7EI32_V }, // 3813 |
22971 | | { PseudoVLOXSEG7EI32_V_M1_M1_MASK, VLOXSEG7EI32_V }, // 3814 |
22972 | | { PseudoVLOXSEG7EI32_V_M1_MF2, VLOXSEG7EI32_V }, // 3815 |
22973 | | { PseudoVLOXSEG7EI32_V_M1_MF2_MASK, VLOXSEG7EI32_V }, // 3816 |
22974 | | { PseudoVLOXSEG7EI32_V_M1_MF4, VLOXSEG7EI32_V }, // 3817 |
22975 | | { PseudoVLOXSEG7EI32_V_M1_MF4_MASK, VLOXSEG7EI32_V }, // 3818 |
22976 | | { PseudoVLOXSEG7EI32_V_M2_M1, VLOXSEG7EI32_V }, // 3819 |
22977 | | { PseudoVLOXSEG7EI32_V_M2_M1_MASK, VLOXSEG7EI32_V }, // 3820 |
22978 | | { PseudoVLOXSEG7EI32_V_M2_MF2, VLOXSEG7EI32_V }, // 3821 |
22979 | | { PseudoVLOXSEG7EI32_V_M2_MF2_MASK, VLOXSEG7EI32_V }, // 3822 |
22980 | | { PseudoVLOXSEG7EI32_V_M4_M1, VLOXSEG7EI32_V }, // 3823 |
22981 | | { PseudoVLOXSEG7EI32_V_M4_M1_MASK, VLOXSEG7EI32_V }, // 3824 |
22982 | | { PseudoVLOXSEG7EI32_V_MF2_M1, VLOXSEG7EI32_V }, // 3825 |
22983 | | { PseudoVLOXSEG7EI32_V_MF2_M1_MASK, VLOXSEG7EI32_V }, // 3826 |
22984 | | { PseudoVLOXSEG7EI32_V_MF2_MF2, VLOXSEG7EI32_V }, // 3827 |
22985 | | { PseudoVLOXSEG7EI32_V_MF2_MF2_MASK, VLOXSEG7EI32_V }, // 3828 |
22986 | | { PseudoVLOXSEG7EI32_V_MF2_MF4, VLOXSEG7EI32_V }, // 3829 |
22987 | | { PseudoVLOXSEG7EI32_V_MF2_MF4_MASK, VLOXSEG7EI32_V }, // 3830 |
22988 | | { PseudoVLOXSEG7EI32_V_MF2_MF8, VLOXSEG7EI32_V }, // 3831 |
22989 | | { PseudoVLOXSEG7EI32_V_MF2_MF8_MASK, VLOXSEG7EI32_V }, // 3832 |
22990 | | { PseudoVLOXSEG7EI64_V_M1_M1, VLOXSEG7EI64_V }, // 3833 |
22991 | | { PseudoVLOXSEG7EI64_V_M1_M1_MASK, VLOXSEG7EI64_V }, // 3834 |
22992 | | { PseudoVLOXSEG7EI64_V_M1_MF2, VLOXSEG7EI64_V }, // 3835 |
22993 | | { PseudoVLOXSEG7EI64_V_M1_MF2_MASK, VLOXSEG7EI64_V }, // 3836 |
22994 | | { PseudoVLOXSEG7EI64_V_M1_MF4, VLOXSEG7EI64_V }, // 3837 |
22995 | | { PseudoVLOXSEG7EI64_V_M1_MF4_MASK, VLOXSEG7EI64_V }, // 3838 |
22996 | | { PseudoVLOXSEG7EI64_V_M1_MF8, VLOXSEG7EI64_V }, // 3839 |
22997 | | { PseudoVLOXSEG7EI64_V_M1_MF8_MASK, VLOXSEG7EI64_V }, // 3840 |
22998 | | { PseudoVLOXSEG7EI64_V_M2_M1, VLOXSEG7EI64_V }, // 3841 |
22999 | | { PseudoVLOXSEG7EI64_V_M2_M1_MASK, VLOXSEG7EI64_V }, // 3842 |
23000 | | { PseudoVLOXSEG7EI64_V_M2_MF2, VLOXSEG7EI64_V }, // 3843 |
23001 | | { PseudoVLOXSEG7EI64_V_M2_MF2_MASK, VLOXSEG7EI64_V }, // 3844 |
23002 | | { PseudoVLOXSEG7EI64_V_M2_MF4, VLOXSEG7EI64_V }, // 3845 |
23003 | | { PseudoVLOXSEG7EI64_V_M2_MF4_MASK, VLOXSEG7EI64_V }, // 3846 |
23004 | | { PseudoVLOXSEG7EI64_V_M4_M1, VLOXSEG7EI64_V }, // 3847 |
23005 | | { PseudoVLOXSEG7EI64_V_M4_M1_MASK, VLOXSEG7EI64_V }, // 3848 |
23006 | | { PseudoVLOXSEG7EI64_V_M4_MF2, VLOXSEG7EI64_V }, // 3849 |
23007 | | { PseudoVLOXSEG7EI64_V_M4_MF2_MASK, VLOXSEG7EI64_V }, // 3850 |
23008 | | { PseudoVLOXSEG7EI64_V_M8_M1, VLOXSEG7EI64_V }, // 3851 |
23009 | | { PseudoVLOXSEG7EI64_V_M8_M1_MASK, VLOXSEG7EI64_V }, // 3852 |
23010 | | { PseudoVLOXSEG7EI8_V_M1_M1, VLOXSEG7EI8_V }, // 3853 |
23011 | | { PseudoVLOXSEG7EI8_V_M1_M1_MASK, VLOXSEG7EI8_V }, // 3854 |
23012 | | { PseudoVLOXSEG7EI8_V_MF2_M1, VLOXSEG7EI8_V }, // 3855 |
23013 | | { PseudoVLOXSEG7EI8_V_MF2_M1_MASK, VLOXSEG7EI8_V }, // 3856 |
23014 | | { PseudoVLOXSEG7EI8_V_MF2_MF2, VLOXSEG7EI8_V }, // 3857 |
23015 | | { PseudoVLOXSEG7EI8_V_MF2_MF2_MASK, VLOXSEG7EI8_V }, // 3858 |
23016 | | { PseudoVLOXSEG7EI8_V_MF4_M1, VLOXSEG7EI8_V }, // 3859 |
23017 | | { PseudoVLOXSEG7EI8_V_MF4_M1_MASK, VLOXSEG7EI8_V }, // 3860 |
23018 | | { PseudoVLOXSEG7EI8_V_MF4_MF2, VLOXSEG7EI8_V }, // 3861 |
23019 | | { PseudoVLOXSEG7EI8_V_MF4_MF2_MASK, VLOXSEG7EI8_V }, // 3862 |
23020 | | { PseudoVLOXSEG7EI8_V_MF4_MF4, VLOXSEG7EI8_V }, // 3863 |
23021 | | { PseudoVLOXSEG7EI8_V_MF4_MF4_MASK, VLOXSEG7EI8_V }, // 3864 |
23022 | | { PseudoVLOXSEG7EI8_V_MF8_M1, VLOXSEG7EI8_V }, // 3865 |
23023 | | { PseudoVLOXSEG7EI8_V_MF8_M1_MASK, VLOXSEG7EI8_V }, // 3866 |
23024 | | { PseudoVLOXSEG7EI8_V_MF8_MF2, VLOXSEG7EI8_V }, // 3867 |
23025 | | { PseudoVLOXSEG7EI8_V_MF8_MF2_MASK, VLOXSEG7EI8_V }, // 3868 |
23026 | | { PseudoVLOXSEG7EI8_V_MF8_MF4, VLOXSEG7EI8_V }, // 3869 |
23027 | | { PseudoVLOXSEG7EI8_V_MF8_MF4_MASK, VLOXSEG7EI8_V }, // 3870 |
23028 | | { PseudoVLOXSEG7EI8_V_MF8_MF8, VLOXSEG7EI8_V }, // 3871 |
23029 | | { PseudoVLOXSEG7EI8_V_MF8_MF8_MASK, VLOXSEG7EI8_V }, // 3872 |
23030 | | { PseudoVLOXSEG8EI16_V_M1_M1, VLOXSEG8EI16_V }, // 3873 |
23031 | | { PseudoVLOXSEG8EI16_V_M1_M1_MASK, VLOXSEG8EI16_V }, // 3874 |
23032 | | { PseudoVLOXSEG8EI16_V_M1_MF2, VLOXSEG8EI16_V }, // 3875 |
23033 | | { PseudoVLOXSEG8EI16_V_M1_MF2_MASK, VLOXSEG8EI16_V }, // 3876 |
23034 | | { PseudoVLOXSEG8EI16_V_M2_M1, VLOXSEG8EI16_V }, // 3877 |
23035 | | { PseudoVLOXSEG8EI16_V_M2_M1_MASK, VLOXSEG8EI16_V }, // 3878 |
23036 | | { PseudoVLOXSEG8EI16_V_MF2_M1, VLOXSEG8EI16_V }, // 3879 |
23037 | | { PseudoVLOXSEG8EI16_V_MF2_M1_MASK, VLOXSEG8EI16_V }, // 3880 |
23038 | | { PseudoVLOXSEG8EI16_V_MF2_MF2, VLOXSEG8EI16_V }, // 3881 |
23039 | | { PseudoVLOXSEG8EI16_V_MF2_MF2_MASK, VLOXSEG8EI16_V }, // 3882 |
23040 | | { PseudoVLOXSEG8EI16_V_MF2_MF4, VLOXSEG8EI16_V }, // 3883 |
23041 | | { PseudoVLOXSEG8EI16_V_MF2_MF4_MASK, VLOXSEG8EI16_V }, // 3884 |
23042 | | { PseudoVLOXSEG8EI16_V_MF4_M1, VLOXSEG8EI16_V }, // 3885 |
23043 | | { PseudoVLOXSEG8EI16_V_MF4_M1_MASK, VLOXSEG8EI16_V }, // 3886 |
23044 | | { PseudoVLOXSEG8EI16_V_MF4_MF2, VLOXSEG8EI16_V }, // 3887 |
23045 | | { PseudoVLOXSEG8EI16_V_MF4_MF2_MASK, VLOXSEG8EI16_V }, // 3888 |
23046 | | { PseudoVLOXSEG8EI16_V_MF4_MF4, VLOXSEG8EI16_V }, // 3889 |
23047 | | { PseudoVLOXSEG8EI16_V_MF4_MF4_MASK, VLOXSEG8EI16_V }, // 3890 |
23048 | | { PseudoVLOXSEG8EI16_V_MF4_MF8, VLOXSEG8EI16_V }, // 3891 |
23049 | | { PseudoVLOXSEG8EI16_V_MF4_MF8_MASK, VLOXSEG8EI16_V }, // 3892 |
23050 | | { PseudoVLOXSEG8EI32_V_M1_M1, VLOXSEG8EI32_V }, // 3893 |
23051 | | { PseudoVLOXSEG8EI32_V_M1_M1_MASK, VLOXSEG8EI32_V }, // 3894 |
23052 | | { PseudoVLOXSEG8EI32_V_M1_MF2, VLOXSEG8EI32_V }, // 3895 |
23053 | | { PseudoVLOXSEG8EI32_V_M1_MF2_MASK, VLOXSEG8EI32_V }, // 3896 |
23054 | | { PseudoVLOXSEG8EI32_V_M1_MF4, VLOXSEG8EI32_V }, // 3897 |
23055 | | { PseudoVLOXSEG8EI32_V_M1_MF4_MASK, VLOXSEG8EI32_V }, // 3898 |
23056 | | { PseudoVLOXSEG8EI32_V_M2_M1, VLOXSEG8EI32_V }, // 3899 |
23057 | | { PseudoVLOXSEG8EI32_V_M2_M1_MASK, VLOXSEG8EI32_V }, // 3900 |
23058 | | { PseudoVLOXSEG8EI32_V_M2_MF2, VLOXSEG8EI32_V }, // 3901 |
23059 | | { PseudoVLOXSEG8EI32_V_M2_MF2_MASK, VLOXSEG8EI32_V }, // 3902 |
23060 | | { PseudoVLOXSEG8EI32_V_M4_M1, VLOXSEG8EI32_V }, // 3903 |
23061 | | { PseudoVLOXSEG8EI32_V_M4_M1_MASK, VLOXSEG8EI32_V }, // 3904 |
23062 | | { PseudoVLOXSEG8EI32_V_MF2_M1, VLOXSEG8EI32_V }, // 3905 |
23063 | | { PseudoVLOXSEG8EI32_V_MF2_M1_MASK, VLOXSEG8EI32_V }, // 3906 |
23064 | | { PseudoVLOXSEG8EI32_V_MF2_MF2, VLOXSEG8EI32_V }, // 3907 |
23065 | | { PseudoVLOXSEG8EI32_V_MF2_MF2_MASK, VLOXSEG8EI32_V }, // 3908 |
23066 | | { PseudoVLOXSEG8EI32_V_MF2_MF4, VLOXSEG8EI32_V }, // 3909 |
23067 | | { PseudoVLOXSEG8EI32_V_MF2_MF4_MASK, VLOXSEG8EI32_V }, // 3910 |
23068 | | { PseudoVLOXSEG8EI32_V_MF2_MF8, VLOXSEG8EI32_V }, // 3911 |
23069 | | { PseudoVLOXSEG8EI32_V_MF2_MF8_MASK, VLOXSEG8EI32_V }, // 3912 |
23070 | | { PseudoVLOXSEG8EI64_V_M1_M1, VLOXSEG8EI64_V }, // 3913 |
23071 | | { PseudoVLOXSEG8EI64_V_M1_M1_MASK, VLOXSEG8EI64_V }, // 3914 |
23072 | | { PseudoVLOXSEG8EI64_V_M1_MF2, VLOXSEG8EI64_V }, // 3915 |
23073 | | { PseudoVLOXSEG8EI64_V_M1_MF2_MASK, VLOXSEG8EI64_V }, // 3916 |
23074 | | { PseudoVLOXSEG8EI64_V_M1_MF4, VLOXSEG8EI64_V }, // 3917 |
23075 | | { PseudoVLOXSEG8EI64_V_M1_MF4_MASK, VLOXSEG8EI64_V }, // 3918 |
23076 | | { PseudoVLOXSEG8EI64_V_M1_MF8, VLOXSEG8EI64_V }, // 3919 |
23077 | | { PseudoVLOXSEG8EI64_V_M1_MF8_MASK, VLOXSEG8EI64_V }, // 3920 |
23078 | | { PseudoVLOXSEG8EI64_V_M2_M1, VLOXSEG8EI64_V }, // 3921 |
23079 | | { PseudoVLOXSEG8EI64_V_M2_M1_MASK, VLOXSEG8EI64_V }, // 3922 |
23080 | | { PseudoVLOXSEG8EI64_V_M2_MF2, VLOXSEG8EI64_V }, // 3923 |
23081 | | { PseudoVLOXSEG8EI64_V_M2_MF2_MASK, VLOXSEG8EI64_V }, // 3924 |
23082 | | { PseudoVLOXSEG8EI64_V_M2_MF4, VLOXSEG8EI64_V }, // 3925 |
23083 | | { PseudoVLOXSEG8EI64_V_M2_MF4_MASK, VLOXSEG8EI64_V }, // 3926 |
23084 | | { PseudoVLOXSEG8EI64_V_M4_M1, VLOXSEG8EI64_V }, // 3927 |
23085 | | { PseudoVLOXSEG8EI64_V_M4_M1_MASK, VLOXSEG8EI64_V }, // 3928 |
23086 | | { PseudoVLOXSEG8EI64_V_M4_MF2, VLOXSEG8EI64_V }, // 3929 |
23087 | | { PseudoVLOXSEG8EI64_V_M4_MF2_MASK, VLOXSEG8EI64_V }, // 3930 |
23088 | | { PseudoVLOXSEG8EI64_V_M8_M1, VLOXSEG8EI64_V }, // 3931 |
23089 | | { PseudoVLOXSEG8EI64_V_M8_M1_MASK, VLOXSEG8EI64_V }, // 3932 |
23090 | | { PseudoVLOXSEG8EI8_V_M1_M1, VLOXSEG8EI8_V }, // 3933 |
23091 | | { PseudoVLOXSEG8EI8_V_M1_M1_MASK, VLOXSEG8EI8_V }, // 3934 |
23092 | | { PseudoVLOXSEG8EI8_V_MF2_M1, VLOXSEG8EI8_V }, // 3935 |
23093 | | { PseudoVLOXSEG8EI8_V_MF2_M1_MASK, VLOXSEG8EI8_V }, // 3936 |
23094 | | { PseudoVLOXSEG8EI8_V_MF2_MF2, VLOXSEG8EI8_V }, // 3937 |
23095 | | { PseudoVLOXSEG8EI8_V_MF2_MF2_MASK, VLOXSEG8EI8_V }, // 3938 |
23096 | | { PseudoVLOXSEG8EI8_V_MF4_M1, VLOXSEG8EI8_V }, // 3939 |
23097 | | { PseudoVLOXSEG8EI8_V_MF4_M1_MASK, VLOXSEG8EI8_V }, // 3940 |
23098 | | { PseudoVLOXSEG8EI8_V_MF4_MF2, VLOXSEG8EI8_V }, // 3941 |
23099 | | { PseudoVLOXSEG8EI8_V_MF4_MF2_MASK, VLOXSEG8EI8_V }, // 3942 |
23100 | | { PseudoVLOXSEG8EI8_V_MF4_MF4, VLOXSEG8EI8_V }, // 3943 |
23101 | | { PseudoVLOXSEG8EI8_V_MF4_MF4_MASK, VLOXSEG8EI8_V }, // 3944 |
23102 | | { PseudoVLOXSEG8EI8_V_MF8_M1, VLOXSEG8EI8_V }, // 3945 |
23103 | | { PseudoVLOXSEG8EI8_V_MF8_M1_MASK, VLOXSEG8EI8_V }, // 3946 |
23104 | | { PseudoVLOXSEG8EI8_V_MF8_MF2, VLOXSEG8EI8_V }, // 3947 |
23105 | | { PseudoVLOXSEG8EI8_V_MF8_MF2_MASK, VLOXSEG8EI8_V }, // 3948 |
23106 | | { PseudoVLOXSEG8EI8_V_MF8_MF4, VLOXSEG8EI8_V }, // 3949 |
23107 | | { PseudoVLOXSEG8EI8_V_MF8_MF4_MASK, VLOXSEG8EI8_V }, // 3950 |
23108 | | { PseudoVLOXSEG8EI8_V_MF8_MF8, VLOXSEG8EI8_V }, // 3951 |
23109 | | { PseudoVLOXSEG8EI8_V_MF8_MF8_MASK, VLOXSEG8EI8_V }, // 3952 |
23110 | | { PseudoVLSE16_V_M1, VLSE16_V }, // 3953 |
23111 | | { PseudoVLSE16_V_M1_MASK, VLSE16_V }, // 3954 |
23112 | | { PseudoVLSE16_V_M2, VLSE16_V }, // 3955 |
23113 | | { PseudoVLSE16_V_M2_MASK, VLSE16_V }, // 3956 |
23114 | | { PseudoVLSE16_V_M4, VLSE16_V }, // 3957 |
23115 | | { PseudoVLSE16_V_M4_MASK, VLSE16_V }, // 3958 |
23116 | | { PseudoVLSE16_V_M8, VLSE16_V }, // 3959 |
23117 | | { PseudoVLSE16_V_M8_MASK, VLSE16_V }, // 3960 |
23118 | | { PseudoVLSE16_V_MF2, VLSE16_V }, // 3961 |
23119 | | { PseudoVLSE16_V_MF2_MASK, VLSE16_V }, // 3962 |
23120 | | { PseudoVLSE16_V_MF4, VLSE16_V }, // 3963 |
23121 | | { PseudoVLSE16_V_MF4_MASK, VLSE16_V }, // 3964 |
23122 | | { PseudoVLSE32_V_M1, VLSE32_V }, // 3965 |
23123 | | { PseudoVLSE32_V_M1_MASK, VLSE32_V }, // 3966 |
23124 | | { PseudoVLSE32_V_M2, VLSE32_V }, // 3967 |
23125 | | { PseudoVLSE32_V_M2_MASK, VLSE32_V }, // 3968 |
23126 | | { PseudoVLSE32_V_M4, VLSE32_V }, // 3969 |
23127 | | { PseudoVLSE32_V_M4_MASK, VLSE32_V }, // 3970 |
23128 | | { PseudoVLSE32_V_M8, VLSE32_V }, // 3971 |
23129 | | { PseudoVLSE32_V_M8_MASK, VLSE32_V }, // 3972 |
23130 | | { PseudoVLSE32_V_MF2, VLSE32_V }, // 3973 |
23131 | | { PseudoVLSE32_V_MF2_MASK, VLSE32_V }, // 3974 |
23132 | | { PseudoVLSE64_V_M1, VLSE64_V }, // 3975 |
23133 | | { PseudoVLSE64_V_M1_MASK, VLSE64_V }, // 3976 |
23134 | | { PseudoVLSE64_V_M2, VLSE64_V }, // 3977 |
23135 | | { PseudoVLSE64_V_M2_MASK, VLSE64_V }, // 3978 |
23136 | | { PseudoVLSE64_V_M4, VLSE64_V }, // 3979 |
23137 | | { PseudoVLSE64_V_M4_MASK, VLSE64_V }, // 3980 |
23138 | | { PseudoVLSE64_V_M8, VLSE64_V }, // 3981 |
23139 | | { PseudoVLSE64_V_M8_MASK, VLSE64_V }, // 3982 |
23140 | | { PseudoVLSE8_V_M1, VLSE8_V }, // 3983 |
23141 | | { PseudoVLSE8_V_M1_MASK, VLSE8_V }, // 3984 |
23142 | | { PseudoVLSE8_V_M2, VLSE8_V }, // 3985 |
23143 | | { PseudoVLSE8_V_M2_MASK, VLSE8_V }, // 3986 |
23144 | | { PseudoVLSE8_V_M4, VLSE8_V }, // 3987 |
23145 | | { PseudoVLSE8_V_M4_MASK, VLSE8_V }, // 3988 |
23146 | | { PseudoVLSE8_V_M8, VLSE8_V }, // 3989 |
23147 | | { PseudoVLSE8_V_M8_MASK, VLSE8_V }, // 3990 |
23148 | | { PseudoVLSE8_V_MF2, VLSE8_V }, // 3991 |
23149 | | { PseudoVLSE8_V_MF2_MASK, VLSE8_V }, // 3992 |
23150 | | { PseudoVLSE8_V_MF4, VLSE8_V }, // 3993 |
23151 | | { PseudoVLSE8_V_MF4_MASK, VLSE8_V }, // 3994 |
23152 | | { PseudoVLSE8_V_MF8, VLSE8_V }, // 3995 |
23153 | | { PseudoVLSE8_V_MF8_MASK, VLSE8_V }, // 3996 |
23154 | | { PseudoVLSEG2E16FF_V_M1, VLSEG2E16FF_V }, // 3997 |
23155 | | { PseudoVLSEG2E16FF_V_M1_MASK, VLSEG2E16FF_V }, // 3998 |
23156 | | { PseudoVLSEG2E16FF_V_M2, VLSEG2E16FF_V }, // 3999 |
23157 | | { PseudoVLSEG2E16FF_V_M2_MASK, VLSEG2E16FF_V }, // 4000 |
23158 | | { PseudoVLSEG2E16FF_V_M4, VLSEG2E16FF_V }, // 4001 |
23159 | | { PseudoVLSEG2E16FF_V_M4_MASK, VLSEG2E16FF_V }, // 4002 |
23160 | | { PseudoVLSEG2E16FF_V_MF2, VLSEG2E16FF_V }, // 4003 |
23161 | | { PseudoVLSEG2E16FF_V_MF2_MASK, VLSEG2E16FF_V }, // 4004 |
23162 | | { PseudoVLSEG2E16FF_V_MF4, VLSEG2E16FF_V }, // 4005 |
23163 | | { PseudoVLSEG2E16FF_V_MF4_MASK, VLSEG2E16FF_V }, // 4006 |
23164 | | { PseudoVLSEG2E16_V_M1, VLSEG2E16_V }, // 4007 |
23165 | | { PseudoVLSEG2E16_V_M1_MASK, VLSEG2E16_V }, // 4008 |
23166 | | { PseudoVLSEG2E16_V_M2, VLSEG2E16_V }, // 4009 |
23167 | | { PseudoVLSEG2E16_V_M2_MASK, VLSEG2E16_V }, // 4010 |
23168 | | { PseudoVLSEG2E16_V_M4, VLSEG2E16_V }, // 4011 |
23169 | | { PseudoVLSEG2E16_V_M4_MASK, VLSEG2E16_V }, // 4012 |
23170 | | { PseudoVLSEG2E16_V_MF2, VLSEG2E16_V }, // 4013 |
23171 | | { PseudoVLSEG2E16_V_MF2_MASK, VLSEG2E16_V }, // 4014 |
23172 | | { PseudoVLSEG2E16_V_MF4, VLSEG2E16_V }, // 4015 |
23173 | | { PseudoVLSEG2E16_V_MF4_MASK, VLSEG2E16_V }, // 4016 |
23174 | | { PseudoVLSEG2E32FF_V_M1, VLSEG2E32FF_V }, // 4017 |
23175 | | { PseudoVLSEG2E32FF_V_M1_MASK, VLSEG2E32FF_V }, // 4018 |
23176 | | { PseudoVLSEG2E32FF_V_M2, VLSEG2E32FF_V }, // 4019 |
23177 | | { PseudoVLSEG2E32FF_V_M2_MASK, VLSEG2E32FF_V }, // 4020 |
23178 | | { PseudoVLSEG2E32FF_V_M4, VLSEG2E32FF_V }, // 4021 |
23179 | | { PseudoVLSEG2E32FF_V_M4_MASK, VLSEG2E32FF_V }, // 4022 |
23180 | | { PseudoVLSEG2E32FF_V_MF2, VLSEG2E32FF_V }, // 4023 |
23181 | | { PseudoVLSEG2E32FF_V_MF2_MASK, VLSEG2E32FF_V }, // 4024 |
23182 | | { PseudoVLSEG2E32_V_M1, VLSEG2E32_V }, // 4025 |
23183 | | { PseudoVLSEG2E32_V_M1_MASK, VLSEG2E32_V }, // 4026 |
23184 | | { PseudoVLSEG2E32_V_M2, VLSEG2E32_V }, // 4027 |
23185 | | { PseudoVLSEG2E32_V_M2_MASK, VLSEG2E32_V }, // 4028 |
23186 | | { PseudoVLSEG2E32_V_M4, VLSEG2E32_V }, // 4029 |
23187 | | { PseudoVLSEG2E32_V_M4_MASK, VLSEG2E32_V }, // 4030 |
23188 | | { PseudoVLSEG2E32_V_MF2, VLSEG2E32_V }, // 4031 |
23189 | | { PseudoVLSEG2E32_V_MF2_MASK, VLSEG2E32_V }, // 4032 |
23190 | | { PseudoVLSEG2E64FF_V_M1, VLSEG2E64FF_V }, // 4033 |
23191 | | { PseudoVLSEG2E64FF_V_M1_MASK, VLSEG2E64FF_V }, // 4034 |
23192 | | { PseudoVLSEG2E64FF_V_M2, VLSEG2E64FF_V }, // 4035 |
23193 | | { PseudoVLSEG2E64FF_V_M2_MASK, VLSEG2E64FF_V }, // 4036 |
23194 | | { PseudoVLSEG2E64FF_V_M4, VLSEG2E64FF_V }, // 4037 |
23195 | | { PseudoVLSEG2E64FF_V_M4_MASK, VLSEG2E64FF_V }, // 4038 |
23196 | | { PseudoVLSEG2E64_V_M1, VLSEG2E64_V }, // 4039 |
23197 | | { PseudoVLSEG2E64_V_M1_MASK, VLSEG2E64_V }, // 4040 |
23198 | | { PseudoVLSEG2E64_V_M2, VLSEG2E64_V }, // 4041 |
23199 | | { PseudoVLSEG2E64_V_M2_MASK, VLSEG2E64_V }, // 4042 |
23200 | | { PseudoVLSEG2E64_V_M4, VLSEG2E64_V }, // 4043 |
23201 | | { PseudoVLSEG2E64_V_M4_MASK, VLSEG2E64_V }, // 4044 |
23202 | | { PseudoVLSEG2E8FF_V_M1, VLSEG2E8FF_V }, // 4045 |
23203 | | { PseudoVLSEG2E8FF_V_M1_MASK, VLSEG2E8FF_V }, // 4046 |
23204 | | { PseudoVLSEG2E8FF_V_M2, VLSEG2E8FF_V }, // 4047 |
23205 | | { PseudoVLSEG2E8FF_V_M2_MASK, VLSEG2E8FF_V }, // 4048 |
23206 | | { PseudoVLSEG2E8FF_V_M4, VLSEG2E8FF_V }, // 4049 |
23207 | | { PseudoVLSEG2E8FF_V_M4_MASK, VLSEG2E8FF_V }, // 4050 |
23208 | | { PseudoVLSEG2E8FF_V_MF2, VLSEG2E8FF_V }, // 4051 |
23209 | | { PseudoVLSEG2E8FF_V_MF2_MASK, VLSEG2E8FF_V }, // 4052 |
23210 | | { PseudoVLSEG2E8FF_V_MF4, VLSEG2E8FF_V }, // 4053 |
23211 | | { PseudoVLSEG2E8FF_V_MF4_MASK, VLSEG2E8FF_V }, // 4054 |
23212 | | { PseudoVLSEG2E8FF_V_MF8, VLSEG2E8FF_V }, // 4055 |
23213 | | { PseudoVLSEG2E8FF_V_MF8_MASK, VLSEG2E8FF_V }, // 4056 |
23214 | | { PseudoVLSEG2E8_V_M1, VLSEG2E8_V }, // 4057 |
23215 | | { PseudoVLSEG2E8_V_M1_MASK, VLSEG2E8_V }, // 4058 |
23216 | | { PseudoVLSEG2E8_V_M2, VLSEG2E8_V }, // 4059 |
23217 | | { PseudoVLSEG2E8_V_M2_MASK, VLSEG2E8_V }, // 4060 |
23218 | | { PseudoVLSEG2E8_V_M4, VLSEG2E8_V }, // 4061 |
23219 | | { PseudoVLSEG2E8_V_M4_MASK, VLSEG2E8_V }, // 4062 |
23220 | | { PseudoVLSEG2E8_V_MF2, VLSEG2E8_V }, // 4063 |
23221 | | { PseudoVLSEG2E8_V_MF2_MASK, VLSEG2E8_V }, // 4064 |
23222 | | { PseudoVLSEG2E8_V_MF4, VLSEG2E8_V }, // 4065 |
23223 | | { PseudoVLSEG2E8_V_MF4_MASK, VLSEG2E8_V }, // 4066 |
23224 | | { PseudoVLSEG2E8_V_MF8, VLSEG2E8_V }, // 4067 |
23225 | | { PseudoVLSEG2E8_V_MF8_MASK, VLSEG2E8_V }, // 4068 |
23226 | | { PseudoVLSEG3E16FF_V_M1, VLSEG3E16FF_V }, // 4069 |
23227 | | { PseudoVLSEG3E16FF_V_M1_MASK, VLSEG3E16FF_V }, // 4070 |
23228 | | { PseudoVLSEG3E16FF_V_M2, VLSEG3E16FF_V }, // 4071 |
23229 | | { PseudoVLSEG3E16FF_V_M2_MASK, VLSEG3E16FF_V }, // 4072 |
23230 | | { PseudoVLSEG3E16FF_V_MF2, VLSEG3E16FF_V }, // 4073 |
23231 | | { PseudoVLSEG3E16FF_V_MF2_MASK, VLSEG3E16FF_V }, // 4074 |
23232 | | { PseudoVLSEG3E16FF_V_MF4, VLSEG3E16FF_V }, // 4075 |
23233 | | { PseudoVLSEG3E16FF_V_MF4_MASK, VLSEG3E16FF_V }, // 4076 |
23234 | | { PseudoVLSEG3E16_V_M1, VLSEG3E16_V }, // 4077 |
23235 | | { PseudoVLSEG3E16_V_M1_MASK, VLSEG3E16_V }, // 4078 |
23236 | | { PseudoVLSEG3E16_V_M2, VLSEG3E16_V }, // 4079 |
23237 | | { PseudoVLSEG3E16_V_M2_MASK, VLSEG3E16_V }, // 4080 |
23238 | | { PseudoVLSEG3E16_V_MF2, VLSEG3E16_V }, // 4081 |
23239 | | { PseudoVLSEG3E16_V_MF2_MASK, VLSEG3E16_V }, // 4082 |
23240 | | { PseudoVLSEG3E16_V_MF4, VLSEG3E16_V }, // 4083 |
23241 | | { PseudoVLSEG3E16_V_MF4_MASK, VLSEG3E16_V }, // 4084 |
23242 | | { PseudoVLSEG3E32FF_V_M1, VLSEG3E32FF_V }, // 4085 |
23243 | | { PseudoVLSEG3E32FF_V_M1_MASK, VLSEG3E32FF_V }, // 4086 |
23244 | | { PseudoVLSEG3E32FF_V_M2, VLSEG3E32FF_V }, // 4087 |
23245 | | { PseudoVLSEG3E32FF_V_M2_MASK, VLSEG3E32FF_V }, // 4088 |
23246 | | { PseudoVLSEG3E32FF_V_MF2, VLSEG3E32FF_V }, // 4089 |
23247 | | { PseudoVLSEG3E32FF_V_MF2_MASK, VLSEG3E32FF_V }, // 4090 |
23248 | | { PseudoVLSEG3E32_V_M1, VLSEG3E32_V }, // 4091 |
23249 | | { PseudoVLSEG3E32_V_M1_MASK, VLSEG3E32_V }, // 4092 |
23250 | | { PseudoVLSEG3E32_V_M2, VLSEG3E32_V }, // 4093 |
23251 | | { PseudoVLSEG3E32_V_M2_MASK, VLSEG3E32_V }, // 4094 |
23252 | | { PseudoVLSEG3E32_V_MF2, VLSEG3E32_V }, // 4095 |
23253 | | { PseudoVLSEG3E32_V_MF2_MASK, VLSEG3E32_V }, // 4096 |
23254 | | { PseudoVLSEG3E64FF_V_M1, VLSEG3E64FF_V }, // 4097 |
23255 | | { PseudoVLSEG3E64FF_V_M1_MASK, VLSEG3E64FF_V }, // 4098 |
23256 | | { PseudoVLSEG3E64FF_V_M2, VLSEG3E64FF_V }, // 4099 |
23257 | | { PseudoVLSEG3E64FF_V_M2_MASK, VLSEG3E64FF_V }, // 4100 |
23258 | | { PseudoVLSEG3E64_V_M1, VLSEG3E64_V }, // 4101 |
23259 | | { PseudoVLSEG3E64_V_M1_MASK, VLSEG3E64_V }, // 4102 |
23260 | | { PseudoVLSEG3E64_V_M2, VLSEG3E64_V }, // 4103 |
23261 | | { PseudoVLSEG3E64_V_M2_MASK, VLSEG3E64_V }, // 4104 |
23262 | | { PseudoVLSEG3E8FF_V_M1, VLSEG3E8FF_V }, // 4105 |
23263 | | { PseudoVLSEG3E8FF_V_M1_MASK, VLSEG3E8FF_V }, // 4106 |
23264 | | { PseudoVLSEG3E8FF_V_M2, VLSEG3E8FF_V }, // 4107 |
23265 | | { PseudoVLSEG3E8FF_V_M2_MASK, VLSEG3E8FF_V }, // 4108 |
23266 | | { PseudoVLSEG3E8FF_V_MF2, VLSEG3E8FF_V }, // 4109 |
23267 | | { PseudoVLSEG3E8FF_V_MF2_MASK, VLSEG3E8FF_V }, // 4110 |
23268 | | { PseudoVLSEG3E8FF_V_MF4, VLSEG3E8FF_V }, // 4111 |
23269 | | { PseudoVLSEG3E8FF_V_MF4_MASK, VLSEG3E8FF_V }, // 4112 |
23270 | | { PseudoVLSEG3E8FF_V_MF8, VLSEG3E8FF_V }, // 4113 |
23271 | | { PseudoVLSEG3E8FF_V_MF8_MASK, VLSEG3E8FF_V }, // 4114 |
23272 | | { PseudoVLSEG3E8_V_M1, VLSEG3E8_V }, // 4115 |
23273 | | { PseudoVLSEG3E8_V_M1_MASK, VLSEG3E8_V }, // 4116 |
23274 | | { PseudoVLSEG3E8_V_M2, VLSEG3E8_V }, // 4117 |
23275 | | { PseudoVLSEG3E8_V_M2_MASK, VLSEG3E8_V }, // 4118 |
23276 | | { PseudoVLSEG3E8_V_MF2, VLSEG3E8_V }, // 4119 |
23277 | | { PseudoVLSEG3E8_V_MF2_MASK, VLSEG3E8_V }, // 4120 |
23278 | | { PseudoVLSEG3E8_V_MF4, VLSEG3E8_V }, // 4121 |
23279 | | { PseudoVLSEG3E8_V_MF4_MASK, VLSEG3E8_V }, // 4122 |
23280 | | { PseudoVLSEG3E8_V_MF8, VLSEG3E8_V }, // 4123 |
23281 | | { PseudoVLSEG3E8_V_MF8_MASK, VLSEG3E8_V }, // 4124 |
23282 | | { PseudoVLSEG4E16FF_V_M1, VLSEG4E16FF_V }, // 4125 |
23283 | | { PseudoVLSEG4E16FF_V_M1_MASK, VLSEG4E16FF_V }, // 4126 |
23284 | | { PseudoVLSEG4E16FF_V_M2, VLSEG4E16FF_V }, // 4127 |
23285 | | { PseudoVLSEG4E16FF_V_M2_MASK, VLSEG4E16FF_V }, // 4128 |
23286 | | { PseudoVLSEG4E16FF_V_MF2, VLSEG4E16FF_V }, // 4129 |
23287 | | { PseudoVLSEG4E16FF_V_MF2_MASK, VLSEG4E16FF_V }, // 4130 |
23288 | | { PseudoVLSEG4E16FF_V_MF4, VLSEG4E16FF_V }, // 4131 |
23289 | | { PseudoVLSEG4E16FF_V_MF4_MASK, VLSEG4E16FF_V }, // 4132 |
23290 | | { PseudoVLSEG4E16_V_M1, VLSEG4E16_V }, // 4133 |
23291 | | { PseudoVLSEG4E16_V_M1_MASK, VLSEG4E16_V }, // 4134 |
23292 | | { PseudoVLSEG4E16_V_M2, VLSEG4E16_V }, // 4135 |
23293 | | { PseudoVLSEG4E16_V_M2_MASK, VLSEG4E16_V }, // 4136 |
23294 | | { PseudoVLSEG4E16_V_MF2, VLSEG4E16_V }, // 4137 |
23295 | | { PseudoVLSEG4E16_V_MF2_MASK, VLSEG4E16_V }, // 4138 |
23296 | | { PseudoVLSEG4E16_V_MF4, VLSEG4E16_V }, // 4139 |
23297 | | { PseudoVLSEG4E16_V_MF4_MASK, VLSEG4E16_V }, // 4140 |
23298 | | { PseudoVLSEG4E32FF_V_M1, VLSEG4E32FF_V }, // 4141 |
23299 | | { PseudoVLSEG4E32FF_V_M1_MASK, VLSEG4E32FF_V }, // 4142 |
23300 | | { PseudoVLSEG4E32FF_V_M2, VLSEG4E32FF_V }, // 4143 |
23301 | | { PseudoVLSEG4E32FF_V_M2_MASK, VLSEG4E32FF_V }, // 4144 |
23302 | | { PseudoVLSEG4E32FF_V_MF2, VLSEG4E32FF_V }, // 4145 |
23303 | | { PseudoVLSEG4E32FF_V_MF2_MASK, VLSEG4E32FF_V }, // 4146 |
23304 | | { PseudoVLSEG4E32_V_M1, VLSEG4E32_V }, // 4147 |
23305 | | { PseudoVLSEG4E32_V_M1_MASK, VLSEG4E32_V }, // 4148 |
23306 | | { PseudoVLSEG4E32_V_M2, VLSEG4E32_V }, // 4149 |
23307 | | { PseudoVLSEG4E32_V_M2_MASK, VLSEG4E32_V }, // 4150 |
23308 | | { PseudoVLSEG4E32_V_MF2, VLSEG4E32_V }, // 4151 |
23309 | | { PseudoVLSEG4E32_V_MF2_MASK, VLSEG4E32_V }, // 4152 |
23310 | | { PseudoVLSEG4E64FF_V_M1, VLSEG4E64FF_V }, // 4153 |
23311 | | { PseudoVLSEG4E64FF_V_M1_MASK, VLSEG4E64FF_V }, // 4154 |
23312 | | { PseudoVLSEG4E64FF_V_M2, VLSEG4E64FF_V }, // 4155 |
23313 | | { PseudoVLSEG4E64FF_V_M2_MASK, VLSEG4E64FF_V }, // 4156 |
23314 | | { PseudoVLSEG4E64_V_M1, VLSEG4E64_V }, // 4157 |
23315 | | { PseudoVLSEG4E64_V_M1_MASK, VLSEG4E64_V }, // 4158 |
23316 | | { PseudoVLSEG4E64_V_M2, VLSEG4E64_V }, // 4159 |
23317 | | { PseudoVLSEG4E64_V_M2_MASK, VLSEG4E64_V }, // 4160 |
23318 | | { PseudoVLSEG4E8FF_V_M1, VLSEG4E8FF_V }, // 4161 |
23319 | | { PseudoVLSEG4E8FF_V_M1_MASK, VLSEG4E8FF_V }, // 4162 |
23320 | | { PseudoVLSEG4E8FF_V_M2, VLSEG4E8FF_V }, // 4163 |
23321 | | { PseudoVLSEG4E8FF_V_M2_MASK, VLSEG4E8FF_V }, // 4164 |
23322 | | { PseudoVLSEG4E8FF_V_MF2, VLSEG4E8FF_V }, // 4165 |
23323 | | { PseudoVLSEG4E8FF_V_MF2_MASK, VLSEG4E8FF_V }, // 4166 |
23324 | | { PseudoVLSEG4E8FF_V_MF4, VLSEG4E8FF_V }, // 4167 |
23325 | | { PseudoVLSEG4E8FF_V_MF4_MASK, VLSEG4E8FF_V }, // 4168 |
23326 | | { PseudoVLSEG4E8FF_V_MF8, VLSEG4E8FF_V }, // 4169 |
23327 | | { PseudoVLSEG4E8FF_V_MF8_MASK, VLSEG4E8FF_V }, // 4170 |
23328 | | { PseudoVLSEG4E8_V_M1, VLSEG4E8_V }, // 4171 |
23329 | | { PseudoVLSEG4E8_V_M1_MASK, VLSEG4E8_V }, // 4172 |
23330 | | { PseudoVLSEG4E8_V_M2, VLSEG4E8_V }, // 4173 |
23331 | | { PseudoVLSEG4E8_V_M2_MASK, VLSEG4E8_V }, // 4174 |
23332 | | { PseudoVLSEG4E8_V_MF2, VLSEG4E8_V }, // 4175 |
23333 | | { PseudoVLSEG4E8_V_MF2_MASK, VLSEG4E8_V }, // 4176 |
23334 | | { PseudoVLSEG4E8_V_MF4, VLSEG4E8_V }, // 4177 |
23335 | | { PseudoVLSEG4E8_V_MF4_MASK, VLSEG4E8_V }, // 4178 |
23336 | | { PseudoVLSEG4E8_V_MF8, VLSEG4E8_V }, // 4179 |
23337 | | { PseudoVLSEG4E8_V_MF8_MASK, VLSEG4E8_V }, // 4180 |
23338 | | { PseudoVLSEG5E16FF_V_M1, VLSEG5E16FF_V }, // 4181 |
23339 | | { PseudoVLSEG5E16FF_V_M1_MASK, VLSEG5E16FF_V }, // 4182 |
23340 | | { PseudoVLSEG5E16FF_V_MF2, VLSEG5E16FF_V }, // 4183 |
23341 | | { PseudoVLSEG5E16FF_V_MF2_MASK, VLSEG5E16FF_V }, // 4184 |
23342 | | { PseudoVLSEG5E16FF_V_MF4, VLSEG5E16FF_V }, // 4185 |
23343 | | { PseudoVLSEG5E16FF_V_MF4_MASK, VLSEG5E16FF_V }, // 4186 |
23344 | | { PseudoVLSEG5E16_V_M1, VLSEG5E16_V }, // 4187 |
23345 | | { PseudoVLSEG5E16_V_M1_MASK, VLSEG5E16_V }, // 4188 |
23346 | | { PseudoVLSEG5E16_V_MF2, VLSEG5E16_V }, // 4189 |
23347 | | { PseudoVLSEG5E16_V_MF2_MASK, VLSEG5E16_V }, // 4190 |
23348 | | { PseudoVLSEG5E16_V_MF4, VLSEG5E16_V }, // 4191 |
23349 | | { PseudoVLSEG5E16_V_MF4_MASK, VLSEG5E16_V }, // 4192 |
23350 | | { PseudoVLSEG5E32FF_V_M1, VLSEG5E32FF_V }, // 4193 |
23351 | | { PseudoVLSEG5E32FF_V_M1_MASK, VLSEG5E32FF_V }, // 4194 |
23352 | | { PseudoVLSEG5E32FF_V_MF2, VLSEG5E32FF_V }, // 4195 |
23353 | | { PseudoVLSEG5E32FF_V_MF2_MASK, VLSEG5E32FF_V }, // 4196 |
23354 | | { PseudoVLSEG5E32_V_M1, VLSEG5E32_V }, // 4197 |
23355 | | { PseudoVLSEG5E32_V_M1_MASK, VLSEG5E32_V }, // 4198 |
23356 | | { PseudoVLSEG5E32_V_MF2, VLSEG5E32_V }, // 4199 |
23357 | | { PseudoVLSEG5E32_V_MF2_MASK, VLSEG5E32_V }, // 4200 |
23358 | | { PseudoVLSEG5E64FF_V_M1, VLSEG5E64FF_V }, // 4201 |
23359 | | { PseudoVLSEG5E64FF_V_M1_MASK, VLSEG5E64FF_V }, // 4202 |
23360 | | { PseudoVLSEG5E64_V_M1, VLSEG5E64_V }, // 4203 |
23361 | | { PseudoVLSEG5E64_V_M1_MASK, VLSEG5E64_V }, // 4204 |
23362 | | { PseudoVLSEG5E8FF_V_M1, VLSEG5E8FF_V }, // 4205 |
23363 | | { PseudoVLSEG5E8FF_V_M1_MASK, VLSEG5E8FF_V }, // 4206 |
23364 | | { PseudoVLSEG5E8FF_V_MF2, VLSEG5E8FF_V }, // 4207 |
23365 | | { PseudoVLSEG5E8FF_V_MF2_MASK, VLSEG5E8FF_V }, // 4208 |
23366 | | { PseudoVLSEG5E8FF_V_MF4, VLSEG5E8FF_V }, // 4209 |
23367 | | { PseudoVLSEG5E8FF_V_MF4_MASK, VLSEG5E8FF_V }, // 4210 |
23368 | | { PseudoVLSEG5E8FF_V_MF8, VLSEG5E8FF_V }, // 4211 |
23369 | | { PseudoVLSEG5E8FF_V_MF8_MASK, VLSEG5E8FF_V }, // 4212 |
23370 | | { PseudoVLSEG5E8_V_M1, VLSEG5E8_V }, // 4213 |
23371 | | { PseudoVLSEG5E8_V_M1_MASK, VLSEG5E8_V }, // 4214 |
23372 | | { PseudoVLSEG5E8_V_MF2, VLSEG5E8_V }, // 4215 |
23373 | | { PseudoVLSEG5E8_V_MF2_MASK, VLSEG5E8_V }, // 4216 |
23374 | | { PseudoVLSEG5E8_V_MF4, VLSEG5E8_V }, // 4217 |
23375 | | { PseudoVLSEG5E8_V_MF4_MASK, VLSEG5E8_V }, // 4218 |
23376 | | { PseudoVLSEG5E8_V_MF8, VLSEG5E8_V }, // 4219 |
23377 | | { PseudoVLSEG5E8_V_MF8_MASK, VLSEG5E8_V }, // 4220 |
23378 | | { PseudoVLSEG6E16FF_V_M1, VLSEG6E16FF_V }, // 4221 |
23379 | | { PseudoVLSEG6E16FF_V_M1_MASK, VLSEG6E16FF_V }, // 4222 |
23380 | | { PseudoVLSEG6E16FF_V_MF2, VLSEG6E16FF_V }, // 4223 |
23381 | | { PseudoVLSEG6E16FF_V_MF2_MASK, VLSEG6E16FF_V }, // 4224 |
23382 | | { PseudoVLSEG6E16FF_V_MF4, VLSEG6E16FF_V }, // 4225 |
23383 | | { PseudoVLSEG6E16FF_V_MF4_MASK, VLSEG6E16FF_V }, // 4226 |
23384 | | { PseudoVLSEG6E16_V_M1, VLSEG6E16_V }, // 4227 |
23385 | | { PseudoVLSEG6E16_V_M1_MASK, VLSEG6E16_V }, // 4228 |
23386 | | { PseudoVLSEG6E16_V_MF2, VLSEG6E16_V }, // 4229 |
23387 | | { PseudoVLSEG6E16_V_MF2_MASK, VLSEG6E16_V }, // 4230 |
23388 | | { PseudoVLSEG6E16_V_MF4, VLSEG6E16_V }, // 4231 |
23389 | | { PseudoVLSEG6E16_V_MF4_MASK, VLSEG6E16_V }, // 4232 |
23390 | | { PseudoVLSEG6E32FF_V_M1, VLSEG6E32FF_V }, // 4233 |
23391 | | { PseudoVLSEG6E32FF_V_M1_MASK, VLSEG6E32FF_V }, // 4234 |
23392 | | { PseudoVLSEG6E32FF_V_MF2, VLSEG6E32FF_V }, // 4235 |
23393 | | { PseudoVLSEG6E32FF_V_MF2_MASK, VLSEG6E32FF_V }, // 4236 |
23394 | | { PseudoVLSEG6E32_V_M1, VLSEG6E32_V }, // 4237 |
23395 | | { PseudoVLSEG6E32_V_M1_MASK, VLSEG6E32_V }, // 4238 |
23396 | | { PseudoVLSEG6E32_V_MF2, VLSEG6E32_V }, // 4239 |
23397 | | { PseudoVLSEG6E32_V_MF2_MASK, VLSEG6E32_V }, // 4240 |
23398 | | { PseudoVLSEG6E64FF_V_M1, VLSEG6E64FF_V }, // 4241 |
23399 | | { PseudoVLSEG6E64FF_V_M1_MASK, VLSEG6E64FF_V }, // 4242 |
23400 | | { PseudoVLSEG6E64_V_M1, VLSEG6E64_V }, // 4243 |
23401 | | { PseudoVLSEG6E64_V_M1_MASK, VLSEG6E64_V }, // 4244 |
23402 | | { PseudoVLSEG6E8FF_V_M1, VLSEG6E8FF_V }, // 4245 |
23403 | | { PseudoVLSEG6E8FF_V_M1_MASK, VLSEG6E8FF_V }, // 4246 |
23404 | | { PseudoVLSEG6E8FF_V_MF2, VLSEG6E8FF_V }, // 4247 |
23405 | | { PseudoVLSEG6E8FF_V_MF2_MASK, VLSEG6E8FF_V }, // 4248 |
23406 | | { PseudoVLSEG6E8FF_V_MF4, VLSEG6E8FF_V }, // 4249 |
23407 | | { PseudoVLSEG6E8FF_V_MF4_MASK, VLSEG6E8FF_V }, // 4250 |
23408 | | { PseudoVLSEG6E8FF_V_MF8, VLSEG6E8FF_V }, // 4251 |
23409 | | { PseudoVLSEG6E8FF_V_MF8_MASK, VLSEG6E8FF_V }, // 4252 |
23410 | | { PseudoVLSEG6E8_V_M1, VLSEG6E8_V }, // 4253 |
23411 | | { PseudoVLSEG6E8_V_M1_MASK, VLSEG6E8_V }, // 4254 |
23412 | | { PseudoVLSEG6E8_V_MF2, VLSEG6E8_V }, // 4255 |
23413 | | { PseudoVLSEG6E8_V_MF2_MASK, VLSEG6E8_V }, // 4256 |
23414 | | { PseudoVLSEG6E8_V_MF4, VLSEG6E8_V }, // 4257 |
23415 | | { PseudoVLSEG6E8_V_MF4_MASK, VLSEG6E8_V }, // 4258 |
23416 | | { PseudoVLSEG6E8_V_MF8, VLSEG6E8_V }, // 4259 |
23417 | | { PseudoVLSEG6E8_V_MF8_MASK, VLSEG6E8_V }, // 4260 |
23418 | | { PseudoVLSEG7E16FF_V_M1, VLSEG7E16FF_V }, // 4261 |
23419 | | { PseudoVLSEG7E16FF_V_M1_MASK, VLSEG7E16FF_V }, // 4262 |
23420 | | { PseudoVLSEG7E16FF_V_MF2, VLSEG7E16FF_V }, // 4263 |
23421 | | { PseudoVLSEG7E16FF_V_MF2_MASK, VLSEG7E16FF_V }, // 4264 |
23422 | | { PseudoVLSEG7E16FF_V_MF4, VLSEG7E16FF_V }, // 4265 |
23423 | | { PseudoVLSEG7E16FF_V_MF4_MASK, VLSEG7E16FF_V }, // 4266 |
23424 | | { PseudoVLSEG7E16_V_M1, VLSEG7E16_V }, // 4267 |
23425 | | { PseudoVLSEG7E16_V_M1_MASK, VLSEG7E16_V }, // 4268 |
23426 | | { PseudoVLSEG7E16_V_MF2, VLSEG7E16_V }, // 4269 |
23427 | | { PseudoVLSEG7E16_V_MF2_MASK, VLSEG7E16_V }, // 4270 |
23428 | | { PseudoVLSEG7E16_V_MF4, VLSEG7E16_V }, // 4271 |
23429 | | { PseudoVLSEG7E16_V_MF4_MASK, VLSEG7E16_V }, // 4272 |
23430 | | { PseudoVLSEG7E32FF_V_M1, VLSEG7E32FF_V }, // 4273 |
23431 | | { PseudoVLSEG7E32FF_V_M1_MASK, VLSEG7E32FF_V }, // 4274 |
23432 | | { PseudoVLSEG7E32FF_V_MF2, VLSEG7E32FF_V }, // 4275 |
23433 | | { PseudoVLSEG7E32FF_V_MF2_MASK, VLSEG7E32FF_V }, // 4276 |
23434 | | { PseudoVLSEG7E32_V_M1, VLSEG7E32_V }, // 4277 |
23435 | | { PseudoVLSEG7E32_V_M1_MASK, VLSEG7E32_V }, // 4278 |
23436 | | { PseudoVLSEG7E32_V_MF2, VLSEG7E32_V }, // 4279 |
23437 | | { PseudoVLSEG7E32_V_MF2_MASK, VLSEG7E32_V }, // 4280 |
23438 | | { PseudoVLSEG7E64FF_V_M1, VLSEG7E64FF_V }, // 4281 |
23439 | | { PseudoVLSEG7E64FF_V_M1_MASK, VLSEG7E64FF_V }, // 4282 |
23440 | | { PseudoVLSEG7E64_V_M1, VLSEG7E64_V }, // 4283 |
23441 | | { PseudoVLSEG7E64_V_M1_MASK, VLSEG7E64_V }, // 4284 |
23442 | | { PseudoVLSEG7E8FF_V_M1, VLSEG7E8FF_V }, // 4285 |
23443 | | { PseudoVLSEG7E8FF_V_M1_MASK, VLSEG7E8FF_V }, // 4286 |
23444 | | { PseudoVLSEG7E8FF_V_MF2, VLSEG7E8FF_V }, // 4287 |
23445 | | { PseudoVLSEG7E8FF_V_MF2_MASK, VLSEG7E8FF_V }, // 4288 |
23446 | | { PseudoVLSEG7E8FF_V_MF4, VLSEG7E8FF_V }, // 4289 |
23447 | | { PseudoVLSEG7E8FF_V_MF4_MASK, VLSEG7E8FF_V }, // 4290 |
23448 | | { PseudoVLSEG7E8FF_V_MF8, VLSEG7E8FF_V }, // 4291 |
23449 | | { PseudoVLSEG7E8FF_V_MF8_MASK, VLSEG7E8FF_V }, // 4292 |
23450 | | { PseudoVLSEG7E8_V_M1, VLSEG7E8_V }, // 4293 |
23451 | | { PseudoVLSEG7E8_V_M1_MASK, VLSEG7E8_V }, // 4294 |
23452 | | { PseudoVLSEG7E8_V_MF2, VLSEG7E8_V }, // 4295 |
23453 | | { PseudoVLSEG7E8_V_MF2_MASK, VLSEG7E8_V }, // 4296 |
23454 | | { PseudoVLSEG7E8_V_MF4, VLSEG7E8_V }, // 4297 |
23455 | | { PseudoVLSEG7E8_V_MF4_MASK, VLSEG7E8_V }, // 4298 |
23456 | | { PseudoVLSEG7E8_V_MF8, VLSEG7E8_V }, // 4299 |
23457 | | { PseudoVLSEG7E8_V_MF8_MASK, VLSEG7E8_V }, // 4300 |
23458 | | { PseudoVLSEG8E16FF_V_M1, VLSEG8E16FF_V }, // 4301 |
23459 | | { PseudoVLSEG8E16FF_V_M1_MASK, VLSEG8E16FF_V }, // 4302 |
23460 | | { PseudoVLSEG8E16FF_V_MF2, VLSEG8E16FF_V }, // 4303 |
23461 | | { PseudoVLSEG8E16FF_V_MF2_MASK, VLSEG8E16FF_V }, // 4304 |
23462 | | { PseudoVLSEG8E16FF_V_MF4, VLSEG8E16FF_V }, // 4305 |
23463 | | { PseudoVLSEG8E16FF_V_MF4_MASK, VLSEG8E16FF_V }, // 4306 |
23464 | | { PseudoVLSEG8E16_V_M1, VLSEG8E16_V }, // 4307 |
23465 | | { PseudoVLSEG8E16_V_M1_MASK, VLSEG8E16_V }, // 4308 |
23466 | | { PseudoVLSEG8E16_V_MF2, VLSEG8E16_V }, // 4309 |
23467 | | { PseudoVLSEG8E16_V_MF2_MASK, VLSEG8E16_V }, // 4310 |
23468 | | { PseudoVLSEG8E16_V_MF4, VLSEG8E16_V }, // 4311 |
23469 | | { PseudoVLSEG8E16_V_MF4_MASK, VLSEG8E16_V }, // 4312 |
23470 | | { PseudoVLSEG8E32FF_V_M1, VLSEG8E32FF_V }, // 4313 |
23471 | | { PseudoVLSEG8E32FF_V_M1_MASK, VLSEG8E32FF_V }, // 4314 |
23472 | | { PseudoVLSEG8E32FF_V_MF2, VLSEG8E32FF_V }, // 4315 |
23473 | | { PseudoVLSEG8E32FF_V_MF2_MASK, VLSEG8E32FF_V }, // 4316 |
23474 | | { PseudoVLSEG8E32_V_M1, VLSEG8E32_V }, // 4317 |
23475 | | { PseudoVLSEG8E32_V_M1_MASK, VLSEG8E32_V }, // 4318 |
23476 | | { PseudoVLSEG8E32_V_MF2, VLSEG8E32_V }, // 4319 |
23477 | | { PseudoVLSEG8E32_V_MF2_MASK, VLSEG8E32_V }, // 4320 |
23478 | | { PseudoVLSEG8E64FF_V_M1, VLSEG8E64FF_V }, // 4321 |
23479 | | { PseudoVLSEG8E64FF_V_M1_MASK, VLSEG8E64FF_V }, // 4322 |
23480 | | { PseudoVLSEG8E64_V_M1, VLSEG8E64_V }, // 4323 |
23481 | | { PseudoVLSEG8E64_V_M1_MASK, VLSEG8E64_V }, // 4324 |
23482 | | { PseudoVLSEG8E8FF_V_M1, VLSEG8E8FF_V }, // 4325 |
23483 | | { PseudoVLSEG8E8FF_V_M1_MASK, VLSEG8E8FF_V }, // 4326 |
23484 | | { PseudoVLSEG8E8FF_V_MF2, VLSEG8E8FF_V }, // 4327 |
23485 | | { PseudoVLSEG8E8FF_V_MF2_MASK, VLSEG8E8FF_V }, // 4328 |
23486 | | { PseudoVLSEG8E8FF_V_MF4, VLSEG8E8FF_V }, // 4329 |
23487 | | { PseudoVLSEG8E8FF_V_MF4_MASK, VLSEG8E8FF_V }, // 4330 |
23488 | | { PseudoVLSEG8E8FF_V_MF8, VLSEG8E8FF_V }, // 4331 |
23489 | | { PseudoVLSEG8E8FF_V_MF8_MASK, VLSEG8E8FF_V }, // 4332 |
23490 | | { PseudoVLSEG8E8_V_M1, VLSEG8E8_V }, // 4333 |
23491 | | { PseudoVLSEG8E8_V_M1_MASK, VLSEG8E8_V }, // 4334 |
23492 | | { PseudoVLSEG8E8_V_MF2, VLSEG8E8_V }, // 4335 |
23493 | | { PseudoVLSEG8E8_V_MF2_MASK, VLSEG8E8_V }, // 4336 |
23494 | | { PseudoVLSEG8E8_V_MF4, VLSEG8E8_V }, // 4337 |
23495 | | { PseudoVLSEG8E8_V_MF4_MASK, VLSEG8E8_V }, // 4338 |
23496 | | { PseudoVLSEG8E8_V_MF8, VLSEG8E8_V }, // 4339 |
23497 | | { PseudoVLSEG8E8_V_MF8_MASK, VLSEG8E8_V }, // 4340 |
23498 | | { PseudoVLSSEG2E16_V_M1, VLSSEG2E16_V }, // 4341 |
23499 | | { PseudoVLSSEG2E16_V_M1_MASK, VLSSEG2E16_V }, // 4342 |
23500 | | { PseudoVLSSEG2E16_V_M2, VLSSEG2E16_V }, // 4343 |
23501 | | { PseudoVLSSEG2E16_V_M2_MASK, VLSSEG2E16_V }, // 4344 |
23502 | | { PseudoVLSSEG2E16_V_M4, VLSSEG2E16_V }, // 4345 |
23503 | | { PseudoVLSSEG2E16_V_M4_MASK, VLSSEG2E16_V }, // 4346 |
23504 | | { PseudoVLSSEG2E16_V_MF2, VLSSEG2E16_V }, // 4347 |
23505 | | { PseudoVLSSEG2E16_V_MF2_MASK, VLSSEG2E16_V }, // 4348 |
23506 | | { PseudoVLSSEG2E16_V_MF4, VLSSEG2E16_V }, // 4349 |
23507 | | { PseudoVLSSEG2E16_V_MF4_MASK, VLSSEG2E16_V }, // 4350 |
23508 | | { PseudoVLSSEG2E32_V_M1, VLSSEG2E32_V }, // 4351 |
23509 | | { PseudoVLSSEG2E32_V_M1_MASK, VLSSEG2E32_V }, // 4352 |
23510 | | { PseudoVLSSEG2E32_V_M2, VLSSEG2E32_V }, // 4353 |
23511 | | { PseudoVLSSEG2E32_V_M2_MASK, VLSSEG2E32_V }, // 4354 |
23512 | | { PseudoVLSSEG2E32_V_M4, VLSSEG2E32_V }, // 4355 |
23513 | | { PseudoVLSSEG2E32_V_M4_MASK, VLSSEG2E32_V }, // 4356 |
23514 | | { PseudoVLSSEG2E32_V_MF2, VLSSEG2E32_V }, // 4357 |
23515 | | { PseudoVLSSEG2E32_V_MF2_MASK, VLSSEG2E32_V }, // 4358 |
23516 | | { PseudoVLSSEG2E64_V_M1, VLSSEG2E64_V }, // 4359 |
23517 | | { PseudoVLSSEG2E64_V_M1_MASK, VLSSEG2E64_V }, // 4360 |
23518 | | { PseudoVLSSEG2E64_V_M2, VLSSEG2E64_V }, // 4361 |
23519 | | { PseudoVLSSEG2E64_V_M2_MASK, VLSSEG2E64_V }, // 4362 |
23520 | | { PseudoVLSSEG2E64_V_M4, VLSSEG2E64_V }, // 4363 |
23521 | | { PseudoVLSSEG2E64_V_M4_MASK, VLSSEG2E64_V }, // 4364 |
23522 | | { PseudoVLSSEG2E8_V_M1, VLSSEG2E8_V }, // 4365 |
23523 | | { PseudoVLSSEG2E8_V_M1_MASK, VLSSEG2E8_V }, // 4366 |
23524 | | { PseudoVLSSEG2E8_V_M2, VLSSEG2E8_V }, // 4367 |
23525 | | { PseudoVLSSEG2E8_V_M2_MASK, VLSSEG2E8_V }, // 4368 |
23526 | | { PseudoVLSSEG2E8_V_M4, VLSSEG2E8_V }, // 4369 |
23527 | | { PseudoVLSSEG2E8_V_M4_MASK, VLSSEG2E8_V }, // 4370 |
23528 | | { PseudoVLSSEG2E8_V_MF2, VLSSEG2E8_V }, // 4371 |
23529 | | { PseudoVLSSEG2E8_V_MF2_MASK, VLSSEG2E8_V }, // 4372 |
23530 | | { PseudoVLSSEG2E8_V_MF4, VLSSEG2E8_V }, // 4373 |
23531 | | { PseudoVLSSEG2E8_V_MF4_MASK, VLSSEG2E8_V }, // 4374 |
23532 | | { PseudoVLSSEG2E8_V_MF8, VLSSEG2E8_V }, // 4375 |
23533 | | { PseudoVLSSEG2E8_V_MF8_MASK, VLSSEG2E8_V }, // 4376 |
23534 | | { PseudoVLSSEG3E16_V_M1, VLSSEG3E16_V }, // 4377 |
23535 | | { PseudoVLSSEG3E16_V_M1_MASK, VLSSEG3E16_V }, // 4378 |
23536 | | { PseudoVLSSEG3E16_V_M2, VLSSEG3E16_V }, // 4379 |
23537 | | { PseudoVLSSEG3E16_V_M2_MASK, VLSSEG3E16_V }, // 4380 |
23538 | | { PseudoVLSSEG3E16_V_MF2, VLSSEG3E16_V }, // 4381 |
23539 | | { PseudoVLSSEG3E16_V_MF2_MASK, VLSSEG3E16_V }, // 4382 |
23540 | | { PseudoVLSSEG3E16_V_MF4, VLSSEG3E16_V }, // 4383 |
23541 | | { PseudoVLSSEG3E16_V_MF4_MASK, VLSSEG3E16_V }, // 4384 |
23542 | | { PseudoVLSSEG3E32_V_M1, VLSSEG3E32_V }, // 4385 |
23543 | | { PseudoVLSSEG3E32_V_M1_MASK, VLSSEG3E32_V }, // 4386 |
23544 | | { PseudoVLSSEG3E32_V_M2, VLSSEG3E32_V }, // 4387 |
23545 | | { PseudoVLSSEG3E32_V_M2_MASK, VLSSEG3E32_V }, // 4388 |
23546 | | { PseudoVLSSEG3E32_V_MF2, VLSSEG3E32_V }, // 4389 |
23547 | | { PseudoVLSSEG3E32_V_MF2_MASK, VLSSEG3E32_V }, // 4390 |
23548 | | { PseudoVLSSEG3E64_V_M1, VLSSEG3E64_V }, // 4391 |
23549 | | { PseudoVLSSEG3E64_V_M1_MASK, VLSSEG3E64_V }, // 4392 |
23550 | | { PseudoVLSSEG3E64_V_M2, VLSSEG3E64_V }, // 4393 |
23551 | | { PseudoVLSSEG3E64_V_M2_MASK, VLSSEG3E64_V }, // 4394 |
23552 | | { PseudoVLSSEG3E8_V_M1, VLSSEG3E8_V }, // 4395 |
23553 | | { PseudoVLSSEG3E8_V_M1_MASK, VLSSEG3E8_V }, // 4396 |
23554 | | { PseudoVLSSEG3E8_V_M2, VLSSEG3E8_V }, // 4397 |
23555 | | { PseudoVLSSEG3E8_V_M2_MASK, VLSSEG3E8_V }, // 4398 |
23556 | | { PseudoVLSSEG3E8_V_MF2, VLSSEG3E8_V }, // 4399 |
23557 | | { PseudoVLSSEG3E8_V_MF2_MASK, VLSSEG3E8_V }, // 4400 |
23558 | | { PseudoVLSSEG3E8_V_MF4, VLSSEG3E8_V }, // 4401 |
23559 | | { PseudoVLSSEG3E8_V_MF4_MASK, VLSSEG3E8_V }, // 4402 |
23560 | | { PseudoVLSSEG3E8_V_MF8, VLSSEG3E8_V }, // 4403 |
23561 | | { PseudoVLSSEG3E8_V_MF8_MASK, VLSSEG3E8_V }, // 4404 |
23562 | | { PseudoVLSSEG4E16_V_M1, VLSSEG4E16_V }, // 4405 |
23563 | | { PseudoVLSSEG4E16_V_M1_MASK, VLSSEG4E16_V }, // 4406 |
23564 | | { PseudoVLSSEG4E16_V_M2, VLSSEG4E16_V }, // 4407 |
23565 | | { PseudoVLSSEG4E16_V_M2_MASK, VLSSEG4E16_V }, // 4408 |
23566 | | { PseudoVLSSEG4E16_V_MF2, VLSSEG4E16_V }, // 4409 |
23567 | | { PseudoVLSSEG4E16_V_MF2_MASK, VLSSEG4E16_V }, // 4410 |
23568 | | { PseudoVLSSEG4E16_V_MF4, VLSSEG4E16_V }, // 4411 |
23569 | | { PseudoVLSSEG4E16_V_MF4_MASK, VLSSEG4E16_V }, // 4412 |
23570 | | { PseudoVLSSEG4E32_V_M1, VLSSEG4E32_V }, // 4413 |
23571 | | { PseudoVLSSEG4E32_V_M1_MASK, VLSSEG4E32_V }, // 4414 |
23572 | | { PseudoVLSSEG4E32_V_M2, VLSSEG4E32_V }, // 4415 |
23573 | | { PseudoVLSSEG4E32_V_M2_MASK, VLSSEG4E32_V }, // 4416 |
23574 | | { PseudoVLSSEG4E32_V_MF2, VLSSEG4E32_V }, // 4417 |
23575 | | { PseudoVLSSEG4E32_V_MF2_MASK, VLSSEG4E32_V }, // 4418 |
23576 | | { PseudoVLSSEG4E64_V_M1, VLSSEG4E64_V }, // 4419 |
23577 | | { PseudoVLSSEG4E64_V_M1_MASK, VLSSEG4E64_V }, // 4420 |
23578 | | { PseudoVLSSEG4E64_V_M2, VLSSEG4E64_V }, // 4421 |
23579 | | { PseudoVLSSEG4E64_V_M2_MASK, VLSSEG4E64_V }, // 4422 |
23580 | | { PseudoVLSSEG4E8_V_M1, VLSSEG4E8_V }, // 4423 |
23581 | | { PseudoVLSSEG4E8_V_M1_MASK, VLSSEG4E8_V }, // 4424 |
23582 | | { PseudoVLSSEG4E8_V_M2, VLSSEG4E8_V }, // 4425 |
23583 | | { PseudoVLSSEG4E8_V_M2_MASK, VLSSEG4E8_V }, // 4426 |
23584 | | { PseudoVLSSEG4E8_V_MF2, VLSSEG4E8_V }, // 4427 |
23585 | | { PseudoVLSSEG4E8_V_MF2_MASK, VLSSEG4E8_V }, // 4428 |
23586 | | { PseudoVLSSEG4E8_V_MF4, VLSSEG4E8_V }, // 4429 |
23587 | | { PseudoVLSSEG4E8_V_MF4_MASK, VLSSEG4E8_V }, // 4430 |
23588 | | { PseudoVLSSEG4E8_V_MF8, VLSSEG4E8_V }, // 4431 |
23589 | | { PseudoVLSSEG4E8_V_MF8_MASK, VLSSEG4E8_V }, // 4432 |
23590 | | { PseudoVLSSEG5E16_V_M1, VLSSEG5E16_V }, // 4433 |
23591 | | { PseudoVLSSEG5E16_V_M1_MASK, VLSSEG5E16_V }, // 4434 |
23592 | | { PseudoVLSSEG5E16_V_MF2, VLSSEG5E16_V }, // 4435 |
23593 | | { PseudoVLSSEG5E16_V_MF2_MASK, VLSSEG5E16_V }, // 4436 |
23594 | | { PseudoVLSSEG5E16_V_MF4, VLSSEG5E16_V }, // 4437 |
23595 | | { PseudoVLSSEG5E16_V_MF4_MASK, VLSSEG5E16_V }, // 4438 |
23596 | | { PseudoVLSSEG5E32_V_M1, VLSSEG5E32_V }, // 4439 |
23597 | | { PseudoVLSSEG5E32_V_M1_MASK, VLSSEG5E32_V }, // 4440 |
23598 | | { PseudoVLSSEG5E32_V_MF2, VLSSEG5E32_V }, // 4441 |
23599 | | { PseudoVLSSEG5E32_V_MF2_MASK, VLSSEG5E32_V }, // 4442 |
23600 | | { PseudoVLSSEG5E64_V_M1, VLSSEG5E64_V }, // 4443 |
23601 | | { PseudoVLSSEG5E64_V_M1_MASK, VLSSEG5E64_V }, // 4444 |
23602 | | { PseudoVLSSEG5E8_V_M1, VLSSEG5E8_V }, // 4445 |
23603 | | { PseudoVLSSEG5E8_V_M1_MASK, VLSSEG5E8_V }, // 4446 |
23604 | | { PseudoVLSSEG5E8_V_MF2, VLSSEG5E8_V }, // 4447 |
23605 | | { PseudoVLSSEG5E8_V_MF2_MASK, VLSSEG5E8_V }, // 4448 |
23606 | | { PseudoVLSSEG5E8_V_MF4, VLSSEG5E8_V }, // 4449 |
23607 | | { PseudoVLSSEG5E8_V_MF4_MASK, VLSSEG5E8_V }, // 4450 |
23608 | | { PseudoVLSSEG5E8_V_MF8, VLSSEG5E8_V }, // 4451 |
23609 | | { PseudoVLSSEG5E8_V_MF8_MASK, VLSSEG5E8_V }, // 4452 |
23610 | | { PseudoVLSSEG6E16_V_M1, VLSSEG6E16_V }, // 4453 |
23611 | | { PseudoVLSSEG6E16_V_M1_MASK, VLSSEG6E16_V }, // 4454 |
23612 | | { PseudoVLSSEG6E16_V_MF2, VLSSEG6E16_V }, // 4455 |
23613 | | { PseudoVLSSEG6E16_V_MF2_MASK, VLSSEG6E16_V }, // 4456 |
23614 | | { PseudoVLSSEG6E16_V_MF4, VLSSEG6E16_V }, // 4457 |
23615 | | { PseudoVLSSEG6E16_V_MF4_MASK, VLSSEG6E16_V }, // 4458 |
23616 | | { PseudoVLSSEG6E32_V_M1, VLSSEG6E32_V }, // 4459 |
23617 | | { PseudoVLSSEG6E32_V_M1_MASK, VLSSEG6E32_V }, // 4460 |
23618 | | { PseudoVLSSEG6E32_V_MF2, VLSSEG6E32_V }, // 4461 |
23619 | | { PseudoVLSSEG6E32_V_MF2_MASK, VLSSEG6E32_V }, // 4462 |
23620 | | { PseudoVLSSEG6E64_V_M1, VLSSEG6E64_V }, // 4463 |
23621 | | { PseudoVLSSEG6E64_V_M1_MASK, VLSSEG6E64_V }, // 4464 |
23622 | | { PseudoVLSSEG6E8_V_M1, VLSSEG6E8_V }, // 4465 |
23623 | | { PseudoVLSSEG6E8_V_M1_MASK, VLSSEG6E8_V }, // 4466 |
23624 | | { PseudoVLSSEG6E8_V_MF2, VLSSEG6E8_V }, // 4467 |
23625 | | { PseudoVLSSEG6E8_V_MF2_MASK, VLSSEG6E8_V }, // 4468 |
23626 | | { PseudoVLSSEG6E8_V_MF4, VLSSEG6E8_V }, // 4469 |
23627 | | { PseudoVLSSEG6E8_V_MF4_MASK, VLSSEG6E8_V }, // 4470 |
23628 | | { PseudoVLSSEG6E8_V_MF8, VLSSEG6E8_V }, // 4471 |
23629 | | { PseudoVLSSEG6E8_V_MF8_MASK, VLSSEG6E8_V }, // 4472 |
23630 | | { PseudoVLSSEG7E16_V_M1, VLSSEG7E16_V }, // 4473 |
23631 | | { PseudoVLSSEG7E16_V_M1_MASK, VLSSEG7E16_V }, // 4474 |
23632 | | { PseudoVLSSEG7E16_V_MF2, VLSSEG7E16_V }, // 4475 |
23633 | | { PseudoVLSSEG7E16_V_MF2_MASK, VLSSEG7E16_V }, // 4476 |
23634 | | { PseudoVLSSEG7E16_V_MF4, VLSSEG7E16_V }, // 4477 |
23635 | | { PseudoVLSSEG7E16_V_MF4_MASK, VLSSEG7E16_V }, // 4478 |
23636 | | { PseudoVLSSEG7E32_V_M1, VLSSEG7E32_V }, // 4479 |
23637 | | { PseudoVLSSEG7E32_V_M1_MASK, VLSSEG7E32_V }, // 4480 |
23638 | | { PseudoVLSSEG7E32_V_MF2, VLSSEG7E32_V }, // 4481 |
23639 | | { PseudoVLSSEG7E32_V_MF2_MASK, VLSSEG7E32_V }, // 4482 |
23640 | | { PseudoVLSSEG7E64_V_M1, VLSSEG7E64_V }, // 4483 |
23641 | | { PseudoVLSSEG7E64_V_M1_MASK, VLSSEG7E64_V }, // 4484 |
23642 | | { PseudoVLSSEG7E8_V_M1, VLSSEG7E8_V }, // 4485 |
23643 | | { PseudoVLSSEG7E8_V_M1_MASK, VLSSEG7E8_V }, // 4486 |
23644 | | { PseudoVLSSEG7E8_V_MF2, VLSSEG7E8_V }, // 4487 |
23645 | | { PseudoVLSSEG7E8_V_MF2_MASK, VLSSEG7E8_V }, // 4488 |
23646 | | { PseudoVLSSEG7E8_V_MF4, VLSSEG7E8_V }, // 4489 |
23647 | | { PseudoVLSSEG7E8_V_MF4_MASK, VLSSEG7E8_V }, // 4490 |
23648 | | { PseudoVLSSEG7E8_V_MF8, VLSSEG7E8_V }, // 4491 |
23649 | | { PseudoVLSSEG7E8_V_MF8_MASK, VLSSEG7E8_V }, // 4492 |
23650 | | { PseudoVLSSEG8E16_V_M1, VLSSEG8E16_V }, // 4493 |
23651 | | { PseudoVLSSEG8E16_V_M1_MASK, VLSSEG8E16_V }, // 4494 |
23652 | | { PseudoVLSSEG8E16_V_MF2, VLSSEG8E16_V }, // 4495 |
23653 | | { PseudoVLSSEG8E16_V_MF2_MASK, VLSSEG8E16_V }, // 4496 |
23654 | | { PseudoVLSSEG8E16_V_MF4, VLSSEG8E16_V }, // 4497 |
23655 | | { PseudoVLSSEG8E16_V_MF4_MASK, VLSSEG8E16_V }, // 4498 |
23656 | | { PseudoVLSSEG8E32_V_M1, VLSSEG8E32_V }, // 4499 |
23657 | | { PseudoVLSSEG8E32_V_M1_MASK, VLSSEG8E32_V }, // 4500 |
23658 | | { PseudoVLSSEG8E32_V_MF2, VLSSEG8E32_V }, // 4501 |
23659 | | { PseudoVLSSEG8E32_V_MF2_MASK, VLSSEG8E32_V }, // 4502 |
23660 | | { PseudoVLSSEG8E64_V_M1, VLSSEG8E64_V }, // 4503 |
23661 | | { PseudoVLSSEG8E64_V_M1_MASK, VLSSEG8E64_V }, // 4504 |
23662 | | { PseudoVLSSEG8E8_V_M1, VLSSEG8E8_V }, // 4505 |
23663 | | { PseudoVLSSEG8E8_V_M1_MASK, VLSSEG8E8_V }, // 4506 |
23664 | | { PseudoVLSSEG8E8_V_MF2, VLSSEG8E8_V }, // 4507 |
23665 | | { PseudoVLSSEG8E8_V_MF2_MASK, VLSSEG8E8_V }, // 4508 |
23666 | | { PseudoVLSSEG8E8_V_MF4, VLSSEG8E8_V }, // 4509 |
23667 | | { PseudoVLSSEG8E8_V_MF4_MASK, VLSSEG8E8_V }, // 4510 |
23668 | | { PseudoVLSSEG8E8_V_MF8, VLSSEG8E8_V }, // 4511 |
23669 | | { PseudoVLSSEG8E8_V_MF8_MASK, VLSSEG8E8_V }, // 4512 |
23670 | | { PseudoVLUXEI16_V_M1_M1, VLUXEI16_V }, // 4513 |
23671 | | { PseudoVLUXEI16_V_M1_M1_MASK, VLUXEI16_V }, // 4514 |
23672 | | { PseudoVLUXEI16_V_M1_M2, VLUXEI16_V }, // 4515 |
23673 | | { PseudoVLUXEI16_V_M1_M2_MASK, VLUXEI16_V }, // 4516 |
23674 | | { PseudoVLUXEI16_V_M1_M4, VLUXEI16_V }, // 4517 |
23675 | | { PseudoVLUXEI16_V_M1_M4_MASK, VLUXEI16_V }, // 4518 |
23676 | | { PseudoVLUXEI16_V_M1_MF2, VLUXEI16_V }, // 4519 |
23677 | | { PseudoVLUXEI16_V_M1_MF2_MASK, VLUXEI16_V }, // 4520 |
23678 | | { PseudoVLUXEI16_V_M2_M1, VLUXEI16_V }, // 4521 |
23679 | | { PseudoVLUXEI16_V_M2_M1_MASK, VLUXEI16_V }, // 4522 |
23680 | | { PseudoVLUXEI16_V_M2_M2, VLUXEI16_V }, // 4523 |
23681 | | { PseudoVLUXEI16_V_M2_M2_MASK, VLUXEI16_V }, // 4524 |
23682 | | { PseudoVLUXEI16_V_M2_M4, VLUXEI16_V }, // 4525 |
23683 | | { PseudoVLUXEI16_V_M2_M4_MASK, VLUXEI16_V }, // 4526 |
23684 | | { PseudoVLUXEI16_V_M2_M8, VLUXEI16_V }, // 4527 |
23685 | | { PseudoVLUXEI16_V_M2_M8_MASK, VLUXEI16_V }, // 4528 |
23686 | | { PseudoVLUXEI16_V_M4_M2, VLUXEI16_V }, // 4529 |
23687 | | { PseudoVLUXEI16_V_M4_M2_MASK, VLUXEI16_V }, // 4530 |
23688 | | { PseudoVLUXEI16_V_M4_M4, VLUXEI16_V }, // 4531 |
23689 | | { PseudoVLUXEI16_V_M4_M4_MASK, VLUXEI16_V }, // 4532 |
23690 | | { PseudoVLUXEI16_V_M4_M8, VLUXEI16_V }, // 4533 |
23691 | | { PseudoVLUXEI16_V_M4_M8_MASK, VLUXEI16_V }, // 4534 |
23692 | | { PseudoVLUXEI16_V_M8_M4, VLUXEI16_V }, // 4535 |
23693 | | { PseudoVLUXEI16_V_M8_M4_MASK, VLUXEI16_V }, // 4536 |
23694 | | { PseudoVLUXEI16_V_M8_M8, VLUXEI16_V }, // 4537 |
23695 | | { PseudoVLUXEI16_V_M8_M8_MASK, VLUXEI16_V }, // 4538 |
23696 | | { PseudoVLUXEI16_V_MF2_M1, VLUXEI16_V }, // 4539 |
23697 | | { PseudoVLUXEI16_V_MF2_M1_MASK, VLUXEI16_V }, // 4540 |
23698 | | { PseudoVLUXEI16_V_MF2_M2, VLUXEI16_V }, // 4541 |
23699 | | { PseudoVLUXEI16_V_MF2_M2_MASK, VLUXEI16_V }, // 4542 |
23700 | | { PseudoVLUXEI16_V_MF2_MF2, VLUXEI16_V }, // 4543 |
23701 | | { PseudoVLUXEI16_V_MF2_MF2_MASK, VLUXEI16_V }, // 4544 |
23702 | | { PseudoVLUXEI16_V_MF2_MF4, VLUXEI16_V }, // 4545 |
23703 | | { PseudoVLUXEI16_V_MF2_MF4_MASK, VLUXEI16_V }, // 4546 |
23704 | | { PseudoVLUXEI16_V_MF4_M1, VLUXEI16_V }, // 4547 |
23705 | | { PseudoVLUXEI16_V_MF4_M1_MASK, VLUXEI16_V }, // 4548 |
23706 | | { PseudoVLUXEI16_V_MF4_MF2, VLUXEI16_V }, // 4549 |
23707 | | { PseudoVLUXEI16_V_MF4_MF2_MASK, VLUXEI16_V }, // 4550 |
23708 | | { PseudoVLUXEI16_V_MF4_MF4, VLUXEI16_V }, // 4551 |
23709 | | { PseudoVLUXEI16_V_MF4_MF4_MASK, VLUXEI16_V }, // 4552 |
23710 | | { PseudoVLUXEI16_V_MF4_MF8, VLUXEI16_V }, // 4553 |
23711 | | { PseudoVLUXEI16_V_MF4_MF8_MASK, VLUXEI16_V }, // 4554 |
23712 | | { PseudoVLUXEI32_V_M1_M1, VLUXEI32_V }, // 4555 |
23713 | | { PseudoVLUXEI32_V_M1_M1_MASK, VLUXEI32_V }, // 4556 |
23714 | | { PseudoVLUXEI32_V_M1_M2, VLUXEI32_V }, // 4557 |
23715 | | { PseudoVLUXEI32_V_M1_M2_MASK, VLUXEI32_V }, // 4558 |
23716 | | { PseudoVLUXEI32_V_M1_MF2, VLUXEI32_V }, // 4559 |
23717 | | { PseudoVLUXEI32_V_M1_MF2_MASK, VLUXEI32_V }, // 4560 |
23718 | | { PseudoVLUXEI32_V_M1_MF4, VLUXEI32_V }, // 4561 |
23719 | | { PseudoVLUXEI32_V_M1_MF4_MASK, VLUXEI32_V }, // 4562 |
23720 | | { PseudoVLUXEI32_V_M2_M1, VLUXEI32_V }, // 4563 |
23721 | | { PseudoVLUXEI32_V_M2_M1_MASK, VLUXEI32_V }, // 4564 |
23722 | | { PseudoVLUXEI32_V_M2_M2, VLUXEI32_V }, // 4565 |
23723 | | { PseudoVLUXEI32_V_M2_M2_MASK, VLUXEI32_V }, // 4566 |
23724 | | { PseudoVLUXEI32_V_M2_M4, VLUXEI32_V }, // 4567 |
23725 | | { PseudoVLUXEI32_V_M2_M4_MASK, VLUXEI32_V }, // 4568 |
23726 | | { PseudoVLUXEI32_V_M2_MF2, VLUXEI32_V }, // 4569 |
23727 | | { PseudoVLUXEI32_V_M2_MF2_MASK, VLUXEI32_V }, // 4570 |
23728 | | { PseudoVLUXEI32_V_M4_M1, VLUXEI32_V }, // 4571 |
23729 | | { PseudoVLUXEI32_V_M4_M1_MASK, VLUXEI32_V }, // 4572 |
23730 | | { PseudoVLUXEI32_V_M4_M2, VLUXEI32_V }, // 4573 |
23731 | | { PseudoVLUXEI32_V_M4_M2_MASK, VLUXEI32_V }, // 4574 |
23732 | | { PseudoVLUXEI32_V_M4_M4, VLUXEI32_V }, // 4575 |
23733 | | { PseudoVLUXEI32_V_M4_M4_MASK, VLUXEI32_V }, // 4576 |
23734 | | { PseudoVLUXEI32_V_M4_M8, VLUXEI32_V }, // 4577 |
23735 | | { PseudoVLUXEI32_V_M4_M8_MASK, VLUXEI32_V }, // 4578 |
23736 | | { PseudoVLUXEI32_V_M8_M2, VLUXEI32_V }, // 4579 |
23737 | | { PseudoVLUXEI32_V_M8_M2_MASK, VLUXEI32_V }, // 4580 |
23738 | | { PseudoVLUXEI32_V_M8_M4, VLUXEI32_V }, // 4581 |
23739 | | { PseudoVLUXEI32_V_M8_M4_MASK, VLUXEI32_V }, // 4582 |
23740 | | { PseudoVLUXEI32_V_M8_M8, VLUXEI32_V }, // 4583 |
23741 | | { PseudoVLUXEI32_V_M8_M8_MASK, VLUXEI32_V }, // 4584 |
23742 | | { PseudoVLUXEI32_V_MF2_M1, VLUXEI32_V }, // 4585 |
23743 | | { PseudoVLUXEI32_V_MF2_M1_MASK, VLUXEI32_V }, // 4586 |
23744 | | { PseudoVLUXEI32_V_MF2_MF2, VLUXEI32_V }, // 4587 |
23745 | | { PseudoVLUXEI32_V_MF2_MF2_MASK, VLUXEI32_V }, // 4588 |
23746 | | { PseudoVLUXEI32_V_MF2_MF4, VLUXEI32_V }, // 4589 |
23747 | | { PseudoVLUXEI32_V_MF2_MF4_MASK, VLUXEI32_V }, // 4590 |
23748 | | { PseudoVLUXEI32_V_MF2_MF8, VLUXEI32_V }, // 4591 |
23749 | | { PseudoVLUXEI32_V_MF2_MF8_MASK, VLUXEI32_V }, // 4592 |
23750 | | { PseudoVLUXEI64_V_M1_M1, VLUXEI64_V }, // 4593 |
23751 | | { PseudoVLUXEI64_V_M1_M1_MASK, VLUXEI64_V }, // 4594 |
23752 | | { PseudoVLUXEI64_V_M1_MF2, VLUXEI64_V }, // 4595 |
23753 | | { PseudoVLUXEI64_V_M1_MF2_MASK, VLUXEI64_V }, // 4596 |
23754 | | { PseudoVLUXEI64_V_M1_MF4, VLUXEI64_V }, // 4597 |
23755 | | { PseudoVLUXEI64_V_M1_MF4_MASK, VLUXEI64_V }, // 4598 |
23756 | | { PseudoVLUXEI64_V_M1_MF8, VLUXEI64_V }, // 4599 |
23757 | | { PseudoVLUXEI64_V_M1_MF8_MASK, VLUXEI64_V }, // 4600 |
23758 | | { PseudoVLUXEI64_V_M2_M1, VLUXEI64_V }, // 4601 |
23759 | | { PseudoVLUXEI64_V_M2_M1_MASK, VLUXEI64_V }, // 4602 |
23760 | | { PseudoVLUXEI64_V_M2_M2, VLUXEI64_V }, // 4603 |
23761 | | { PseudoVLUXEI64_V_M2_M2_MASK, VLUXEI64_V }, // 4604 |
23762 | | { PseudoVLUXEI64_V_M2_MF2, VLUXEI64_V }, // 4605 |
23763 | | { PseudoVLUXEI64_V_M2_MF2_MASK, VLUXEI64_V }, // 4606 |
23764 | | { PseudoVLUXEI64_V_M2_MF4, VLUXEI64_V }, // 4607 |
23765 | | { PseudoVLUXEI64_V_M2_MF4_MASK, VLUXEI64_V }, // 4608 |
23766 | | { PseudoVLUXEI64_V_M4_M1, VLUXEI64_V }, // 4609 |
23767 | | { PseudoVLUXEI64_V_M4_M1_MASK, VLUXEI64_V }, // 4610 |
23768 | | { PseudoVLUXEI64_V_M4_M2, VLUXEI64_V }, // 4611 |
23769 | | { PseudoVLUXEI64_V_M4_M2_MASK, VLUXEI64_V }, // 4612 |
23770 | | { PseudoVLUXEI64_V_M4_M4, VLUXEI64_V }, // 4613 |
23771 | | { PseudoVLUXEI64_V_M4_M4_MASK, VLUXEI64_V }, // 4614 |
23772 | | { PseudoVLUXEI64_V_M4_MF2, VLUXEI64_V }, // 4615 |
23773 | | { PseudoVLUXEI64_V_M4_MF2_MASK, VLUXEI64_V }, // 4616 |
23774 | | { PseudoVLUXEI64_V_M8_M1, VLUXEI64_V }, // 4617 |
23775 | | { PseudoVLUXEI64_V_M8_M1_MASK, VLUXEI64_V }, // 4618 |
23776 | | { PseudoVLUXEI64_V_M8_M2, VLUXEI64_V }, // 4619 |
23777 | | { PseudoVLUXEI64_V_M8_M2_MASK, VLUXEI64_V }, // 4620 |
23778 | | { PseudoVLUXEI64_V_M8_M4, VLUXEI64_V }, // 4621 |
23779 | | { PseudoVLUXEI64_V_M8_M4_MASK, VLUXEI64_V }, // 4622 |
23780 | | { PseudoVLUXEI64_V_M8_M8, VLUXEI64_V }, // 4623 |
23781 | | { PseudoVLUXEI64_V_M8_M8_MASK, VLUXEI64_V }, // 4624 |
23782 | | { PseudoVLUXEI8_V_M1_M1, VLUXEI8_V }, // 4625 |
23783 | | { PseudoVLUXEI8_V_M1_M1_MASK, VLUXEI8_V }, // 4626 |
23784 | | { PseudoVLUXEI8_V_M1_M2, VLUXEI8_V }, // 4627 |
23785 | | { PseudoVLUXEI8_V_M1_M2_MASK, VLUXEI8_V }, // 4628 |
23786 | | { PseudoVLUXEI8_V_M1_M4, VLUXEI8_V }, // 4629 |
23787 | | { PseudoVLUXEI8_V_M1_M4_MASK, VLUXEI8_V }, // 4630 |
23788 | | { PseudoVLUXEI8_V_M1_M8, VLUXEI8_V }, // 4631 |
23789 | | { PseudoVLUXEI8_V_M1_M8_MASK, VLUXEI8_V }, // 4632 |
23790 | | { PseudoVLUXEI8_V_M2_M2, VLUXEI8_V }, // 4633 |
23791 | | { PseudoVLUXEI8_V_M2_M2_MASK, VLUXEI8_V }, // 4634 |
23792 | | { PseudoVLUXEI8_V_M2_M4, VLUXEI8_V }, // 4635 |
23793 | | { PseudoVLUXEI8_V_M2_M4_MASK, VLUXEI8_V }, // 4636 |
23794 | | { PseudoVLUXEI8_V_M2_M8, VLUXEI8_V }, // 4637 |
23795 | | { PseudoVLUXEI8_V_M2_M8_MASK, VLUXEI8_V }, // 4638 |
23796 | | { PseudoVLUXEI8_V_M4_M4, VLUXEI8_V }, // 4639 |
23797 | | { PseudoVLUXEI8_V_M4_M4_MASK, VLUXEI8_V }, // 4640 |
23798 | | { PseudoVLUXEI8_V_M4_M8, VLUXEI8_V }, // 4641 |
23799 | | { PseudoVLUXEI8_V_M4_M8_MASK, VLUXEI8_V }, // 4642 |
23800 | | { PseudoVLUXEI8_V_M8_M8, VLUXEI8_V }, // 4643 |
23801 | | { PseudoVLUXEI8_V_M8_M8_MASK, VLUXEI8_V }, // 4644 |
23802 | | { PseudoVLUXEI8_V_MF2_M1, VLUXEI8_V }, // 4645 |
23803 | | { PseudoVLUXEI8_V_MF2_M1_MASK, VLUXEI8_V }, // 4646 |
23804 | | { PseudoVLUXEI8_V_MF2_M2, VLUXEI8_V }, // 4647 |
23805 | | { PseudoVLUXEI8_V_MF2_M2_MASK, VLUXEI8_V }, // 4648 |
23806 | | { PseudoVLUXEI8_V_MF2_M4, VLUXEI8_V }, // 4649 |
23807 | | { PseudoVLUXEI8_V_MF2_M4_MASK, VLUXEI8_V }, // 4650 |
23808 | | { PseudoVLUXEI8_V_MF2_MF2, VLUXEI8_V }, // 4651 |
23809 | | { PseudoVLUXEI8_V_MF2_MF2_MASK, VLUXEI8_V }, // 4652 |
23810 | | { PseudoVLUXEI8_V_MF4_M1, VLUXEI8_V }, // 4653 |
23811 | | { PseudoVLUXEI8_V_MF4_M1_MASK, VLUXEI8_V }, // 4654 |
23812 | | { PseudoVLUXEI8_V_MF4_M2, VLUXEI8_V }, // 4655 |
23813 | | { PseudoVLUXEI8_V_MF4_M2_MASK, VLUXEI8_V }, // 4656 |
23814 | | { PseudoVLUXEI8_V_MF4_MF2, VLUXEI8_V }, // 4657 |
23815 | | { PseudoVLUXEI8_V_MF4_MF2_MASK, VLUXEI8_V }, // 4658 |
23816 | | { PseudoVLUXEI8_V_MF4_MF4, VLUXEI8_V }, // 4659 |
23817 | | { PseudoVLUXEI8_V_MF4_MF4_MASK, VLUXEI8_V }, // 4660 |
23818 | | { PseudoVLUXEI8_V_MF8_M1, VLUXEI8_V }, // 4661 |
23819 | | { PseudoVLUXEI8_V_MF8_M1_MASK, VLUXEI8_V }, // 4662 |
23820 | | { PseudoVLUXEI8_V_MF8_MF2, VLUXEI8_V }, // 4663 |
23821 | | { PseudoVLUXEI8_V_MF8_MF2_MASK, VLUXEI8_V }, // 4664 |
23822 | | { PseudoVLUXEI8_V_MF8_MF4, VLUXEI8_V }, // 4665 |
23823 | | { PseudoVLUXEI8_V_MF8_MF4_MASK, VLUXEI8_V }, // 4666 |
23824 | | { PseudoVLUXEI8_V_MF8_MF8, VLUXEI8_V }, // 4667 |
23825 | | { PseudoVLUXEI8_V_MF8_MF8_MASK, VLUXEI8_V }, // 4668 |
23826 | | { PseudoVLUXSEG2EI16_V_M1_M1, VLUXSEG2EI16_V }, // 4669 |
23827 | | { PseudoVLUXSEG2EI16_V_M1_M1_MASK, VLUXSEG2EI16_V }, // 4670 |
23828 | | { PseudoVLUXSEG2EI16_V_M1_M2, VLUXSEG2EI16_V }, // 4671 |
23829 | | { PseudoVLUXSEG2EI16_V_M1_M2_MASK, VLUXSEG2EI16_V }, // 4672 |
23830 | | { PseudoVLUXSEG2EI16_V_M1_M4, VLUXSEG2EI16_V }, // 4673 |
23831 | | { PseudoVLUXSEG2EI16_V_M1_M4_MASK, VLUXSEG2EI16_V }, // 4674 |
23832 | | { PseudoVLUXSEG2EI16_V_M1_MF2, VLUXSEG2EI16_V }, // 4675 |
23833 | | { PseudoVLUXSEG2EI16_V_M1_MF2_MASK, VLUXSEG2EI16_V }, // 4676 |
23834 | | { PseudoVLUXSEG2EI16_V_M2_M1, VLUXSEG2EI16_V }, // 4677 |
23835 | | { PseudoVLUXSEG2EI16_V_M2_M1_MASK, VLUXSEG2EI16_V }, // 4678 |
23836 | | { PseudoVLUXSEG2EI16_V_M2_M2, VLUXSEG2EI16_V }, // 4679 |
23837 | | { PseudoVLUXSEG2EI16_V_M2_M2_MASK, VLUXSEG2EI16_V }, // 4680 |
23838 | | { PseudoVLUXSEG2EI16_V_M2_M4, VLUXSEG2EI16_V }, // 4681 |
23839 | | { PseudoVLUXSEG2EI16_V_M2_M4_MASK, VLUXSEG2EI16_V }, // 4682 |
23840 | | { PseudoVLUXSEG2EI16_V_M4_M2, VLUXSEG2EI16_V }, // 4683 |
23841 | | { PseudoVLUXSEG2EI16_V_M4_M2_MASK, VLUXSEG2EI16_V }, // 4684 |
23842 | | { PseudoVLUXSEG2EI16_V_M4_M4, VLUXSEG2EI16_V }, // 4685 |
23843 | | { PseudoVLUXSEG2EI16_V_M4_M4_MASK, VLUXSEG2EI16_V }, // 4686 |
23844 | | { PseudoVLUXSEG2EI16_V_M8_M4, VLUXSEG2EI16_V }, // 4687 |
23845 | | { PseudoVLUXSEG2EI16_V_M8_M4_MASK, VLUXSEG2EI16_V }, // 4688 |
23846 | | { PseudoVLUXSEG2EI16_V_MF2_M1, VLUXSEG2EI16_V }, // 4689 |
23847 | | { PseudoVLUXSEG2EI16_V_MF2_M1_MASK, VLUXSEG2EI16_V }, // 4690 |
23848 | | { PseudoVLUXSEG2EI16_V_MF2_M2, VLUXSEG2EI16_V }, // 4691 |
23849 | | { PseudoVLUXSEG2EI16_V_MF2_M2_MASK, VLUXSEG2EI16_V }, // 4692 |
23850 | | { PseudoVLUXSEG2EI16_V_MF2_MF2, VLUXSEG2EI16_V }, // 4693 |
23851 | | { PseudoVLUXSEG2EI16_V_MF2_MF2_MASK, VLUXSEG2EI16_V }, // 4694 |
23852 | | { PseudoVLUXSEG2EI16_V_MF2_MF4, VLUXSEG2EI16_V }, // 4695 |
23853 | | { PseudoVLUXSEG2EI16_V_MF2_MF4_MASK, VLUXSEG2EI16_V }, // 4696 |
23854 | | { PseudoVLUXSEG2EI16_V_MF4_M1, VLUXSEG2EI16_V }, // 4697 |
23855 | | { PseudoVLUXSEG2EI16_V_MF4_M1_MASK, VLUXSEG2EI16_V }, // 4698 |
23856 | | { PseudoVLUXSEG2EI16_V_MF4_MF2, VLUXSEG2EI16_V }, // 4699 |
23857 | | { PseudoVLUXSEG2EI16_V_MF4_MF2_MASK, VLUXSEG2EI16_V }, // 4700 |
23858 | | { PseudoVLUXSEG2EI16_V_MF4_MF4, VLUXSEG2EI16_V }, // 4701 |
23859 | | { PseudoVLUXSEG2EI16_V_MF4_MF4_MASK, VLUXSEG2EI16_V }, // 4702 |
23860 | | { PseudoVLUXSEG2EI16_V_MF4_MF8, VLUXSEG2EI16_V }, // 4703 |
23861 | | { PseudoVLUXSEG2EI16_V_MF4_MF8_MASK, VLUXSEG2EI16_V }, // 4704 |
23862 | | { PseudoVLUXSEG2EI32_V_M1_M1, VLUXSEG2EI32_V }, // 4705 |
23863 | | { PseudoVLUXSEG2EI32_V_M1_M1_MASK, VLUXSEG2EI32_V }, // 4706 |
23864 | | { PseudoVLUXSEG2EI32_V_M1_M2, VLUXSEG2EI32_V }, // 4707 |
23865 | | { PseudoVLUXSEG2EI32_V_M1_M2_MASK, VLUXSEG2EI32_V }, // 4708 |
23866 | | { PseudoVLUXSEG2EI32_V_M1_MF2, VLUXSEG2EI32_V }, // 4709 |
23867 | | { PseudoVLUXSEG2EI32_V_M1_MF2_MASK, VLUXSEG2EI32_V }, // 4710 |
23868 | | { PseudoVLUXSEG2EI32_V_M1_MF4, VLUXSEG2EI32_V }, // 4711 |
23869 | | { PseudoVLUXSEG2EI32_V_M1_MF4_MASK, VLUXSEG2EI32_V }, // 4712 |
23870 | | { PseudoVLUXSEG2EI32_V_M2_M1, VLUXSEG2EI32_V }, // 4713 |
23871 | | { PseudoVLUXSEG2EI32_V_M2_M1_MASK, VLUXSEG2EI32_V }, // 4714 |
23872 | | { PseudoVLUXSEG2EI32_V_M2_M2, VLUXSEG2EI32_V }, // 4715 |
23873 | | { PseudoVLUXSEG2EI32_V_M2_M2_MASK, VLUXSEG2EI32_V }, // 4716 |
23874 | | { PseudoVLUXSEG2EI32_V_M2_M4, VLUXSEG2EI32_V }, // 4717 |
23875 | | { PseudoVLUXSEG2EI32_V_M2_M4_MASK, VLUXSEG2EI32_V }, // 4718 |
23876 | | { PseudoVLUXSEG2EI32_V_M2_MF2, VLUXSEG2EI32_V }, // 4719 |
23877 | | { PseudoVLUXSEG2EI32_V_M2_MF2_MASK, VLUXSEG2EI32_V }, // 4720 |
23878 | | { PseudoVLUXSEG2EI32_V_M4_M1, VLUXSEG2EI32_V }, // 4721 |
23879 | | { PseudoVLUXSEG2EI32_V_M4_M1_MASK, VLUXSEG2EI32_V }, // 4722 |
23880 | | { PseudoVLUXSEG2EI32_V_M4_M2, VLUXSEG2EI32_V }, // 4723 |
23881 | | { PseudoVLUXSEG2EI32_V_M4_M2_MASK, VLUXSEG2EI32_V }, // 4724 |
23882 | | { PseudoVLUXSEG2EI32_V_M4_M4, VLUXSEG2EI32_V }, // 4725 |
23883 | | { PseudoVLUXSEG2EI32_V_M4_M4_MASK, VLUXSEG2EI32_V }, // 4726 |
23884 | | { PseudoVLUXSEG2EI32_V_M8_M2, VLUXSEG2EI32_V }, // 4727 |
23885 | | { PseudoVLUXSEG2EI32_V_M8_M2_MASK, VLUXSEG2EI32_V }, // 4728 |
23886 | | { PseudoVLUXSEG2EI32_V_M8_M4, VLUXSEG2EI32_V }, // 4729 |
23887 | | { PseudoVLUXSEG2EI32_V_M8_M4_MASK, VLUXSEG2EI32_V }, // 4730 |
23888 | | { PseudoVLUXSEG2EI32_V_MF2_M1, VLUXSEG2EI32_V }, // 4731 |
23889 | | { PseudoVLUXSEG2EI32_V_MF2_M1_MASK, VLUXSEG2EI32_V }, // 4732 |
23890 | | { PseudoVLUXSEG2EI32_V_MF2_MF2, VLUXSEG2EI32_V }, // 4733 |
23891 | | { PseudoVLUXSEG2EI32_V_MF2_MF2_MASK, VLUXSEG2EI32_V }, // 4734 |
23892 | | { PseudoVLUXSEG2EI32_V_MF2_MF4, VLUXSEG2EI32_V }, // 4735 |
23893 | | { PseudoVLUXSEG2EI32_V_MF2_MF4_MASK, VLUXSEG2EI32_V }, // 4736 |
23894 | | { PseudoVLUXSEG2EI32_V_MF2_MF8, VLUXSEG2EI32_V }, // 4737 |
23895 | | { PseudoVLUXSEG2EI32_V_MF2_MF8_MASK, VLUXSEG2EI32_V }, // 4738 |
23896 | | { PseudoVLUXSEG2EI64_V_M1_M1, VLUXSEG2EI64_V }, // 4739 |
23897 | | { PseudoVLUXSEG2EI64_V_M1_M1_MASK, VLUXSEG2EI64_V }, // 4740 |
23898 | | { PseudoVLUXSEG2EI64_V_M1_MF2, VLUXSEG2EI64_V }, // 4741 |
23899 | | { PseudoVLUXSEG2EI64_V_M1_MF2_MASK, VLUXSEG2EI64_V }, // 4742 |
23900 | | { PseudoVLUXSEG2EI64_V_M1_MF4, VLUXSEG2EI64_V }, // 4743 |
23901 | | { PseudoVLUXSEG2EI64_V_M1_MF4_MASK, VLUXSEG2EI64_V }, // 4744 |
23902 | | { PseudoVLUXSEG2EI64_V_M1_MF8, VLUXSEG2EI64_V }, // 4745 |
23903 | | { PseudoVLUXSEG2EI64_V_M1_MF8_MASK, VLUXSEG2EI64_V }, // 4746 |
23904 | | { PseudoVLUXSEG2EI64_V_M2_M1, VLUXSEG2EI64_V }, // 4747 |
23905 | | { PseudoVLUXSEG2EI64_V_M2_M1_MASK, VLUXSEG2EI64_V }, // 4748 |
23906 | | { PseudoVLUXSEG2EI64_V_M2_M2, VLUXSEG2EI64_V }, // 4749 |
23907 | | { PseudoVLUXSEG2EI64_V_M2_M2_MASK, VLUXSEG2EI64_V }, // 4750 |
23908 | | { PseudoVLUXSEG2EI64_V_M2_MF2, VLUXSEG2EI64_V }, // 4751 |
23909 | | { PseudoVLUXSEG2EI64_V_M2_MF2_MASK, VLUXSEG2EI64_V }, // 4752 |
23910 | | { PseudoVLUXSEG2EI64_V_M2_MF4, VLUXSEG2EI64_V }, // 4753 |
23911 | | { PseudoVLUXSEG2EI64_V_M2_MF4_MASK, VLUXSEG2EI64_V }, // 4754 |
23912 | | { PseudoVLUXSEG2EI64_V_M4_M1, VLUXSEG2EI64_V }, // 4755 |
23913 | | { PseudoVLUXSEG2EI64_V_M4_M1_MASK, VLUXSEG2EI64_V }, // 4756 |
23914 | | { PseudoVLUXSEG2EI64_V_M4_M2, VLUXSEG2EI64_V }, // 4757 |
23915 | | { PseudoVLUXSEG2EI64_V_M4_M2_MASK, VLUXSEG2EI64_V }, // 4758 |
23916 | | { PseudoVLUXSEG2EI64_V_M4_M4, VLUXSEG2EI64_V }, // 4759 |
23917 | | { PseudoVLUXSEG2EI64_V_M4_M4_MASK, VLUXSEG2EI64_V }, // 4760 |
23918 | | { PseudoVLUXSEG2EI64_V_M4_MF2, VLUXSEG2EI64_V }, // 4761 |
23919 | | { PseudoVLUXSEG2EI64_V_M4_MF2_MASK, VLUXSEG2EI64_V }, // 4762 |
23920 | | { PseudoVLUXSEG2EI64_V_M8_M1, VLUXSEG2EI64_V }, // 4763 |
23921 | | { PseudoVLUXSEG2EI64_V_M8_M1_MASK, VLUXSEG2EI64_V }, // 4764 |
23922 | | { PseudoVLUXSEG2EI64_V_M8_M2, VLUXSEG2EI64_V }, // 4765 |
23923 | | { PseudoVLUXSEG2EI64_V_M8_M2_MASK, VLUXSEG2EI64_V }, // 4766 |
23924 | | { PseudoVLUXSEG2EI64_V_M8_M4, VLUXSEG2EI64_V }, // 4767 |
23925 | | { PseudoVLUXSEG2EI64_V_M8_M4_MASK, VLUXSEG2EI64_V }, // 4768 |
23926 | | { PseudoVLUXSEG2EI8_V_M1_M1, VLUXSEG2EI8_V }, // 4769 |
23927 | | { PseudoVLUXSEG2EI8_V_M1_M1_MASK, VLUXSEG2EI8_V }, // 4770 |
23928 | | { PseudoVLUXSEG2EI8_V_M1_M2, VLUXSEG2EI8_V }, // 4771 |
23929 | | { PseudoVLUXSEG2EI8_V_M1_M2_MASK, VLUXSEG2EI8_V }, // 4772 |
23930 | | { PseudoVLUXSEG2EI8_V_M1_M4, VLUXSEG2EI8_V }, // 4773 |
23931 | | { PseudoVLUXSEG2EI8_V_M1_M4_MASK, VLUXSEG2EI8_V }, // 4774 |
23932 | | { PseudoVLUXSEG2EI8_V_M2_M2, VLUXSEG2EI8_V }, // 4775 |
23933 | | { PseudoVLUXSEG2EI8_V_M2_M2_MASK, VLUXSEG2EI8_V }, // 4776 |
23934 | | { PseudoVLUXSEG2EI8_V_M2_M4, VLUXSEG2EI8_V }, // 4777 |
23935 | | { PseudoVLUXSEG2EI8_V_M2_M4_MASK, VLUXSEG2EI8_V }, // 4778 |
23936 | | { PseudoVLUXSEG2EI8_V_M4_M4, VLUXSEG2EI8_V }, // 4779 |
23937 | | { PseudoVLUXSEG2EI8_V_M4_M4_MASK, VLUXSEG2EI8_V }, // 4780 |
23938 | | { PseudoVLUXSEG2EI8_V_MF2_M1, VLUXSEG2EI8_V }, // 4781 |
23939 | | { PseudoVLUXSEG2EI8_V_MF2_M1_MASK, VLUXSEG2EI8_V }, // 4782 |
23940 | | { PseudoVLUXSEG2EI8_V_MF2_M2, VLUXSEG2EI8_V }, // 4783 |
23941 | | { PseudoVLUXSEG2EI8_V_MF2_M2_MASK, VLUXSEG2EI8_V }, // 4784 |
23942 | | { PseudoVLUXSEG2EI8_V_MF2_M4, VLUXSEG2EI8_V }, // 4785 |
23943 | | { PseudoVLUXSEG2EI8_V_MF2_M4_MASK, VLUXSEG2EI8_V }, // 4786 |
23944 | | { PseudoVLUXSEG2EI8_V_MF2_MF2, VLUXSEG2EI8_V }, // 4787 |
23945 | | { PseudoVLUXSEG2EI8_V_MF2_MF2_MASK, VLUXSEG2EI8_V }, // 4788 |
23946 | | { PseudoVLUXSEG2EI8_V_MF4_M1, VLUXSEG2EI8_V }, // 4789 |
23947 | | { PseudoVLUXSEG2EI8_V_MF4_M1_MASK, VLUXSEG2EI8_V }, // 4790 |
23948 | | { PseudoVLUXSEG2EI8_V_MF4_M2, VLUXSEG2EI8_V }, // 4791 |
23949 | | { PseudoVLUXSEG2EI8_V_MF4_M2_MASK, VLUXSEG2EI8_V }, // 4792 |
23950 | | { PseudoVLUXSEG2EI8_V_MF4_MF2, VLUXSEG2EI8_V }, // 4793 |
23951 | | { PseudoVLUXSEG2EI8_V_MF4_MF2_MASK, VLUXSEG2EI8_V }, // 4794 |
23952 | | { PseudoVLUXSEG2EI8_V_MF4_MF4, VLUXSEG2EI8_V }, // 4795 |
23953 | | { PseudoVLUXSEG2EI8_V_MF4_MF4_MASK, VLUXSEG2EI8_V }, // 4796 |
23954 | | { PseudoVLUXSEG2EI8_V_MF8_M1, VLUXSEG2EI8_V }, // 4797 |
23955 | | { PseudoVLUXSEG2EI8_V_MF8_M1_MASK, VLUXSEG2EI8_V }, // 4798 |
23956 | | { PseudoVLUXSEG2EI8_V_MF8_MF2, VLUXSEG2EI8_V }, // 4799 |
23957 | | { PseudoVLUXSEG2EI8_V_MF8_MF2_MASK, VLUXSEG2EI8_V }, // 4800 |
23958 | | { PseudoVLUXSEG2EI8_V_MF8_MF4, VLUXSEG2EI8_V }, // 4801 |
23959 | | { PseudoVLUXSEG2EI8_V_MF8_MF4_MASK, VLUXSEG2EI8_V }, // 4802 |
23960 | | { PseudoVLUXSEG2EI8_V_MF8_MF8, VLUXSEG2EI8_V }, // 4803 |
23961 | | { PseudoVLUXSEG2EI8_V_MF8_MF8_MASK, VLUXSEG2EI8_V }, // 4804 |
23962 | | { PseudoVLUXSEG3EI16_V_M1_M1, VLUXSEG3EI16_V }, // 4805 |
23963 | | { PseudoVLUXSEG3EI16_V_M1_M1_MASK, VLUXSEG3EI16_V }, // 4806 |
23964 | | { PseudoVLUXSEG3EI16_V_M1_M2, VLUXSEG3EI16_V }, // 4807 |
23965 | | { PseudoVLUXSEG3EI16_V_M1_M2_MASK, VLUXSEG3EI16_V }, // 4808 |
23966 | | { PseudoVLUXSEG3EI16_V_M1_MF2, VLUXSEG3EI16_V }, // 4809 |
23967 | | { PseudoVLUXSEG3EI16_V_M1_MF2_MASK, VLUXSEG3EI16_V }, // 4810 |
23968 | | { PseudoVLUXSEG3EI16_V_M2_M1, VLUXSEG3EI16_V }, // 4811 |
23969 | | { PseudoVLUXSEG3EI16_V_M2_M1_MASK, VLUXSEG3EI16_V }, // 4812 |
23970 | | { PseudoVLUXSEG3EI16_V_M2_M2, VLUXSEG3EI16_V }, // 4813 |
23971 | | { PseudoVLUXSEG3EI16_V_M2_M2_MASK, VLUXSEG3EI16_V }, // 4814 |
23972 | | { PseudoVLUXSEG3EI16_V_M4_M2, VLUXSEG3EI16_V }, // 4815 |
23973 | | { PseudoVLUXSEG3EI16_V_M4_M2_MASK, VLUXSEG3EI16_V }, // 4816 |
23974 | | { PseudoVLUXSEG3EI16_V_MF2_M1, VLUXSEG3EI16_V }, // 4817 |
23975 | | { PseudoVLUXSEG3EI16_V_MF2_M1_MASK, VLUXSEG3EI16_V }, // 4818 |
23976 | | { PseudoVLUXSEG3EI16_V_MF2_M2, VLUXSEG3EI16_V }, // 4819 |
23977 | | { PseudoVLUXSEG3EI16_V_MF2_M2_MASK, VLUXSEG3EI16_V }, // 4820 |
23978 | | { PseudoVLUXSEG3EI16_V_MF2_MF2, VLUXSEG3EI16_V }, // 4821 |
23979 | | { PseudoVLUXSEG3EI16_V_MF2_MF2_MASK, VLUXSEG3EI16_V }, // 4822 |
23980 | | { PseudoVLUXSEG3EI16_V_MF2_MF4, VLUXSEG3EI16_V }, // 4823 |
23981 | | { PseudoVLUXSEG3EI16_V_MF2_MF4_MASK, VLUXSEG3EI16_V }, // 4824 |
23982 | | { PseudoVLUXSEG3EI16_V_MF4_M1, VLUXSEG3EI16_V }, // 4825 |
23983 | | { PseudoVLUXSEG3EI16_V_MF4_M1_MASK, VLUXSEG3EI16_V }, // 4826 |
23984 | | { PseudoVLUXSEG3EI16_V_MF4_MF2, VLUXSEG3EI16_V }, // 4827 |
23985 | | { PseudoVLUXSEG3EI16_V_MF4_MF2_MASK, VLUXSEG3EI16_V }, // 4828 |
23986 | | { PseudoVLUXSEG3EI16_V_MF4_MF4, VLUXSEG3EI16_V }, // 4829 |
23987 | | { PseudoVLUXSEG3EI16_V_MF4_MF4_MASK, VLUXSEG3EI16_V }, // 4830 |
23988 | | { PseudoVLUXSEG3EI16_V_MF4_MF8, VLUXSEG3EI16_V }, // 4831 |
23989 | | { PseudoVLUXSEG3EI16_V_MF4_MF8_MASK, VLUXSEG3EI16_V }, // 4832 |
23990 | | { PseudoVLUXSEG3EI32_V_M1_M1, VLUXSEG3EI32_V }, // 4833 |
23991 | | { PseudoVLUXSEG3EI32_V_M1_M1_MASK, VLUXSEG3EI32_V }, // 4834 |
23992 | | { PseudoVLUXSEG3EI32_V_M1_M2, VLUXSEG3EI32_V }, // 4835 |
23993 | | { PseudoVLUXSEG3EI32_V_M1_M2_MASK, VLUXSEG3EI32_V }, // 4836 |
23994 | | { PseudoVLUXSEG3EI32_V_M1_MF2, VLUXSEG3EI32_V }, // 4837 |
23995 | | { PseudoVLUXSEG3EI32_V_M1_MF2_MASK, VLUXSEG3EI32_V }, // 4838 |
23996 | | { PseudoVLUXSEG3EI32_V_M1_MF4, VLUXSEG3EI32_V }, // 4839 |
23997 | | { PseudoVLUXSEG3EI32_V_M1_MF4_MASK, VLUXSEG3EI32_V }, // 4840 |
23998 | | { PseudoVLUXSEG3EI32_V_M2_M1, VLUXSEG3EI32_V }, // 4841 |
23999 | | { PseudoVLUXSEG3EI32_V_M2_M1_MASK, VLUXSEG3EI32_V }, // 4842 |
24000 | | { PseudoVLUXSEG3EI32_V_M2_M2, VLUXSEG3EI32_V }, // 4843 |
24001 | | { PseudoVLUXSEG3EI32_V_M2_M2_MASK, VLUXSEG3EI32_V }, // 4844 |
24002 | | { PseudoVLUXSEG3EI32_V_M2_MF2, VLUXSEG3EI32_V }, // 4845 |
24003 | | { PseudoVLUXSEG3EI32_V_M2_MF2_MASK, VLUXSEG3EI32_V }, // 4846 |
24004 | | { PseudoVLUXSEG3EI32_V_M4_M1, VLUXSEG3EI32_V }, // 4847 |
24005 | | { PseudoVLUXSEG3EI32_V_M4_M1_MASK, VLUXSEG3EI32_V }, // 4848 |
24006 | | { PseudoVLUXSEG3EI32_V_M4_M2, VLUXSEG3EI32_V }, // 4849 |
24007 | | { PseudoVLUXSEG3EI32_V_M4_M2_MASK, VLUXSEG3EI32_V }, // 4850 |
24008 | | { PseudoVLUXSEG3EI32_V_M8_M2, VLUXSEG3EI32_V }, // 4851 |
24009 | | { PseudoVLUXSEG3EI32_V_M8_M2_MASK, VLUXSEG3EI32_V }, // 4852 |
24010 | | { PseudoVLUXSEG3EI32_V_MF2_M1, VLUXSEG3EI32_V }, // 4853 |
24011 | | { PseudoVLUXSEG3EI32_V_MF2_M1_MASK, VLUXSEG3EI32_V }, // 4854 |
24012 | | { PseudoVLUXSEG3EI32_V_MF2_MF2, VLUXSEG3EI32_V }, // 4855 |
24013 | | { PseudoVLUXSEG3EI32_V_MF2_MF2_MASK, VLUXSEG3EI32_V }, // 4856 |
24014 | | { PseudoVLUXSEG3EI32_V_MF2_MF4, VLUXSEG3EI32_V }, // 4857 |
24015 | | { PseudoVLUXSEG3EI32_V_MF2_MF4_MASK, VLUXSEG3EI32_V }, // 4858 |
24016 | | { PseudoVLUXSEG3EI32_V_MF2_MF8, VLUXSEG3EI32_V }, // 4859 |
24017 | | { PseudoVLUXSEG3EI32_V_MF2_MF8_MASK, VLUXSEG3EI32_V }, // 4860 |
24018 | | { PseudoVLUXSEG3EI64_V_M1_M1, VLUXSEG3EI64_V }, // 4861 |
24019 | | { PseudoVLUXSEG3EI64_V_M1_M1_MASK, VLUXSEG3EI64_V }, // 4862 |
24020 | | { PseudoVLUXSEG3EI64_V_M1_MF2, VLUXSEG3EI64_V }, // 4863 |
24021 | | { PseudoVLUXSEG3EI64_V_M1_MF2_MASK, VLUXSEG3EI64_V }, // 4864 |
24022 | | { PseudoVLUXSEG3EI64_V_M1_MF4, VLUXSEG3EI64_V }, // 4865 |
24023 | | { PseudoVLUXSEG3EI64_V_M1_MF4_MASK, VLUXSEG3EI64_V }, // 4866 |
24024 | | { PseudoVLUXSEG3EI64_V_M1_MF8, VLUXSEG3EI64_V }, // 4867 |
24025 | | { PseudoVLUXSEG3EI64_V_M1_MF8_MASK, VLUXSEG3EI64_V }, // 4868 |
24026 | | { PseudoVLUXSEG3EI64_V_M2_M1, VLUXSEG3EI64_V }, // 4869 |
24027 | | { PseudoVLUXSEG3EI64_V_M2_M1_MASK, VLUXSEG3EI64_V }, // 4870 |
24028 | | { PseudoVLUXSEG3EI64_V_M2_M2, VLUXSEG3EI64_V }, // 4871 |
24029 | | { PseudoVLUXSEG3EI64_V_M2_M2_MASK, VLUXSEG3EI64_V }, // 4872 |
24030 | | { PseudoVLUXSEG3EI64_V_M2_MF2, VLUXSEG3EI64_V }, // 4873 |
24031 | | { PseudoVLUXSEG3EI64_V_M2_MF2_MASK, VLUXSEG3EI64_V }, // 4874 |
24032 | | { PseudoVLUXSEG3EI64_V_M2_MF4, VLUXSEG3EI64_V }, // 4875 |
24033 | | { PseudoVLUXSEG3EI64_V_M2_MF4_MASK, VLUXSEG3EI64_V }, // 4876 |
24034 | | { PseudoVLUXSEG3EI64_V_M4_M1, VLUXSEG3EI64_V }, // 4877 |
24035 | | { PseudoVLUXSEG3EI64_V_M4_M1_MASK, VLUXSEG3EI64_V }, // 4878 |
24036 | | { PseudoVLUXSEG3EI64_V_M4_M2, VLUXSEG3EI64_V }, // 4879 |
24037 | | { PseudoVLUXSEG3EI64_V_M4_M2_MASK, VLUXSEG3EI64_V }, // 4880 |
24038 | | { PseudoVLUXSEG3EI64_V_M4_MF2, VLUXSEG3EI64_V }, // 4881 |
24039 | | { PseudoVLUXSEG3EI64_V_M4_MF2_MASK, VLUXSEG3EI64_V }, // 4882 |
24040 | | { PseudoVLUXSEG3EI64_V_M8_M1, VLUXSEG3EI64_V }, // 4883 |
24041 | | { PseudoVLUXSEG3EI64_V_M8_M1_MASK, VLUXSEG3EI64_V }, // 4884 |
24042 | | { PseudoVLUXSEG3EI64_V_M8_M2, VLUXSEG3EI64_V }, // 4885 |
24043 | | { PseudoVLUXSEG3EI64_V_M8_M2_MASK, VLUXSEG3EI64_V }, // 4886 |
24044 | | { PseudoVLUXSEG3EI8_V_M1_M1, VLUXSEG3EI8_V }, // 4887 |
24045 | | { PseudoVLUXSEG3EI8_V_M1_M1_MASK, VLUXSEG3EI8_V }, // 4888 |
24046 | | { PseudoVLUXSEG3EI8_V_M1_M2, VLUXSEG3EI8_V }, // 4889 |
24047 | | { PseudoVLUXSEG3EI8_V_M1_M2_MASK, VLUXSEG3EI8_V }, // 4890 |
24048 | | { PseudoVLUXSEG3EI8_V_M2_M2, VLUXSEG3EI8_V }, // 4891 |
24049 | | { PseudoVLUXSEG3EI8_V_M2_M2_MASK, VLUXSEG3EI8_V }, // 4892 |
24050 | | { PseudoVLUXSEG3EI8_V_MF2_M1, VLUXSEG3EI8_V }, // 4893 |
24051 | | { PseudoVLUXSEG3EI8_V_MF2_M1_MASK, VLUXSEG3EI8_V }, // 4894 |
24052 | | { PseudoVLUXSEG3EI8_V_MF2_M2, VLUXSEG3EI8_V }, // 4895 |
24053 | | { PseudoVLUXSEG3EI8_V_MF2_M2_MASK, VLUXSEG3EI8_V }, // 4896 |
24054 | | { PseudoVLUXSEG3EI8_V_MF2_MF2, VLUXSEG3EI8_V }, // 4897 |
24055 | | { PseudoVLUXSEG3EI8_V_MF2_MF2_MASK, VLUXSEG3EI8_V }, // 4898 |
24056 | | { PseudoVLUXSEG3EI8_V_MF4_M1, VLUXSEG3EI8_V }, // 4899 |
24057 | | { PseudoVLUXSEG3EI8_V_MF4_M1_MASK, VLUXSEG3EI8_V }, // 4900 |
24058 | | { PseudoVLUXSEG3EI8_V_MF4_M2, VLUXSEG3EI8_V }, // 4901 |
24059 | | { PseudoVLUXSEG3EI8_V_MF4_M2_MASK, VLUXSEG3EI8_V }, // 4902 |
24060 | | { PseudoVLUXSEG3EI8_V_MF4_MF2, VLUXSEG3EI8_V }, // 4903 |
24061 | | { PseudoVLUXSEG3EI8_V_MF4_MF2_MASK, VLUXSEG3EI8_V }, // 4904 |
24062 | | { PseudoVLUXSEG3EI8_V_MF4_MF4, VLUXSEG3EI8_V }, // 4905 |
24063 | | { PseudoVLUXSEG3EI8_V_MF4_MF4_MASK, VLUXSEG3EI8_V }, // 4906 |
24064 | | { PseudoVLUXSEG3EI8_V_MF8_M1, VLUXSEG3EI8_V }, // 4907 |
24065 | | { PseudoVLUXSEG3EI8_V_MF8_M1_MASK, VLUXSEG3EI8_V }, // 4908 |
24066 | | { PseudoVLUXSEG3EI8_V_MF8_MF2, VLUXSEG3EI8_V }, // 4909 |
24067 | | { PseudoVLUXSEG3EI8_V_MF8_MF2_MASK, VLUXSEG3EI8_V }, // 4910 |
24068 | | { PseudoVLUXSEG3EI8_V_MF8_MF4, VLUXSEG3EI8_V }, // 4911 |
24069 | | { PseudoVLUXSEG3EI8_V_MF8_MF4_MASK, VLUXSEG3EI8_V }, // 4912 |
24070 | | { PseudoVLUXSEG3EI8_V_MF8_MF8, VLUXSEG3EI8_V }, // 4913 |
24071 | | { PseudoVLUXSEG3EI8_V_MF8_MF8_MASK, VLUXSEG3EI8_V }, // 4914 |
24072 | | { PseudoVLUXSEG4EI16_V_M1_M1, VLUXSEG4EI16_V }, // 4915 |
24073 | | { PseudoVLUXSEG4EI16_V_M1_M1_MASK, VLUXSEG4EI16_V }, // 4916 |
24074 | | { PseudoVLUXSEG4EI16_V_M1_M2, VLUXSEG4EI16_V }, // 4917 |
24075 | | { PseudoVLUXSEG4EI16_V_M1_M2_MASK, VLUXSEG4EI16_V }, // 4918 |
24076 | | { PseudoVLUXSEG4EI16_V_M1_MF2, VLUXSEG4EI16_V }, // 4919 |
24077 | | { PseudoVLUXSEG4EI16_V_M1_MF2_MASK, VLUXSEG4EI16_V }, // 4920 |
24078 | | { PseudoVLUXSEG4EI16_V_M2_M1, VLUXSEG4EI16_V }, // 4921 |
24079 | | { PseudoVLUXSEG4EI16_V_M2_M1_MASK, VLUXSEG4EI16_V }, // 4922 |
24080 | | { PseudoVLUXSEG4EI16_V_M2_M2, VLUXSEG4EI16_V }, // 4923 |
24081 | | { PseudoVLUXSEG4EI16_V_M2_M2_MASK, VLUXSEG4EI16_V }, // 4924 |
24082 | | { PseudoVLUXSEG4EI16_V_M4_M2, VLUXSEG4EI16_V }, // 4925 |
24083 | | { PseudoVLUXSEG4EI16_V_M4_M2_MASK, VLUXSEG4EI16_V }, // 4926 |
24084 | | { PseudoVLUXSEG4EI16_V_MF2_M1, VLUXSEG4EI16_V }, // 4927 |
24085 | | { PseudoVLUXSEG4EI16_V_MF2_M1_MASK, VLUXSEG4EI16_V }, // 4928 |
24086 | | { PseudoVLUXSEG4EI16_V_MF2_M2, VLUXSEG4EI16_V }, // 4929 |
24087 | | { PseudoVLUXSEG4EI16_V_MF2_M2_MASK, VLUXSEG4EI16_V }, // 4930 |
24088 | | { PseudoVLUXSEG4EI16_V_MF2_MF2, VLUXSEG4EI16_V }, // 4931 |
24089 | | { PseudoVLUXSEG4EI16_V_MF2_MF2_MASK, VLUXSEG4EI16_V }, // 4932 |
24090 | | { PseudoVLUXSEG4EI16_V_MF2_MF4, VLUXSEG4EI16_V }, // 4933 |
24091 | | { PseudoVLUXSEG4EI16_V_MF2_MF4_MASK, VLUXSEG4EI16_V }, // 4934 |
24092 | | { PseudoVLUXSEG4EI16_V_MF4_M1, VLUXSEG4EI16_V }, // 4935 |
24093 | | { PseudoVLUXSEG4EI16_V_MF4_M1_MASK, VLUXSEG4EI16_V }, // 4936 |
24094 | | { PseudoVLUXSEG4EI16_V_MF4_MF2, VLUXSEG4EI16_V }, // 4937 |
24095 | | { PseudoVLUXSEG4EI16_V_MF4_MF2_MASK, VLUXSEG4EI16_V }, // 4938 |
24096 | | { PseudoVLUXSEG4EI16_V_MF4_MF4, VLUXSEG4EI16_V }, // 4939 |
24097 | | { PseudoVLUXSEG4EI16_V_MF4_MF4_MASK, VLUXSEG4EI16_V }, // 4940 |
24098 | | { PseudoVLUXSEG4EI16_V_MF4_MF8, VLUXSEG4EI16_V }, // 4941 |
24099 | | { PseudoVLUXSEG4EI16_V_MF4_MF8_MASK, VLUXSEG4EI16_V }, // 4942 |
24100 | | { PseudoVLUXSEG4EI32_V_M1_M1, VLUXSEG4EI32_V }, // 4943 |
24101 | | { PseudoVLUXSEG4EI32_V_M1_M1_MASK, VLUXSEG4EI32_V }, // 4944 |
24102 | | { PseudoVLUXSEG4EI32_V_M1_M2, VLUXSEG4EI32_V }, // 4945 |
24103 | | { PseudoVLUXSEG4EI32_V_M1_M2_MASK, VLUXSEG4EI32_V }, // 4946 |
24104 | | { PseudoVLUXSEG4EI32_V_M1_MF2, VLUXSEG4EI32_V }, // 4947 |
24105 | | { PseudoVLUXSEG4EI32_V_M1_MF2_MASK, VLUXSEG4EI32_V }, // 4948 |
24106 | | { PseudoVLUXSEG4EI32_V_M1_MF4, VLUXSEG4EI32_V }, // 4949 |
24107 | | { PseudoVLUXSEG4EI32_V_M1_MF4_MASK, VLUXSEG4EI32_V }, // 4950 |
24108 | | { PseudoVLUXSEG4EI32_V_M2_M1, VLUXSEG4EI32_V }, // 4951 |
24109 | | { PseudoVLUXSEG4EI32_V_M2_M1_MASK, VLUXSEG4EI32_V }, // 4952 |
24110 | | { PseudoVLUXSEG4EI32_V_M2_M2, VLUXSEG4EI32_V }, // 4953 |
24111 | | { PseudoVLUXSEG4EI32_V_M2_M2_MASK, VLUXSEG4EI32_V }, // 4954 |
24112 | | { PseudoVLUXSEG4EI32_V_M2_MF2, VLUXSEG4EI32_V }, // 4955 |
24113 | | { PseudoVLUXSEG4EI32_V_M2_MF2_MASK, VLUXSEG4EI32_V }, // 4956 |
24114 | | { PseudoVLUXSEG4EI32_V_M4_M1, VLUXSEG4EI32_V }, // 4957 |
24115 | | { PseudoVLUXSEG4EI32_V_M4_M1_MASK, VLUXSEG4EI32_V }, // 4958 |
24116 | | { PseudoVLUXSEG4EI32_V_M4_M2, VLUXSEG4EI32_V }, // 4959 |
24117 | | { PseudoVLUXSEG4EI32_V_M4_M2_MASK, VLUXSEG4EI32_V }, // 4960 |
24118 | | { PseudoVLUXSEG4EI32_V_M8_M2, VLUXSEG4EI32_V }, // 4961 |
24119 | | { PseudoVLUXSEG4EI32_V_M8_M2_MASK, VLUXSEG4EI32_V }, // 4962 |
24120 | | { PseudoVLUXSEG4EI32_V_MF2_M1, VLUXSEG4EI32_V }, // 4963 |
24121 | | { PseudoVLUXSEG4EI32_V_MF2_M1_MASK, VLUXSEG4EI32_V }, // 4964 |
24122 | | { PseudoVLUXSEG4EI32_V_MF2_MF2, VLUXSEG4EI32_V }, // 4965 |
24123 | | { PseudoVLUXSEG4EI32_V_MF2_MF2_MASK, VLUXSEG4EI32_V }, // 4966 |
24124 | | { PseudoVLUXSEG4EI32_V_MF2_MF4, VLUXSEG4EI32_V }, // 4967 |
24125 | | { PseudoVLUXSEG4EI32_V_MF2_MF4_MASK, VLUXSEG4EI32_V }, // 4968 |
24126 | | { PseudoVLUXSEG4EI32_V_MF2_MF8, VLUXSEG4EI32_V }, // 4969 |
24127 | | { PseudoVLUXSEG4EI32_V_MF2_MF8_MASK, VLUXSEG4EI32_V }, // 4970 |
24128 | | { PseudoVLUXSEG4EI64_V_M1_M1, VLUXSEG4EI64_V }, // 4971 |
24129 | | { PseudoVLUXSEG4EI64_V_M1_M1_MASK, VLUXSEG4EI64_V }, // 4972 |
24130 | | { PseudoVLUXSEG4EI64_V_M1_MF2, VLUXSEG4EI64_V }, // 4973 |
24131 | | { PseudoVLUXSEG4EI64_V_M1_MF2_MASK, VLUXSEG4EI64_V }, // 4974 |
24132 | | { PseudoVLUXSEG4EI64_V_M1_MF4, VLUXSEG4EI64_V }, // 4975 |
24133 | | { PseudoVLUXSEG4EI64_V_M1_MF4_MASK, VLUXSEG4EI64_V }, // 4976 |
24134 | | { PseudoVLUXSEG4EI64_V_M1_MF8, VLUXSEG4EI64_V }, // 4977 |
24135 | | { PseudoVLUXSEG4EI64_V_M1_MF8_MASK, VLUXSEG4EI64_V }, // 4978 |
24136 | | { PseudoVLUXSEG4EI64_V_M2_M1, VLUXSEG4EI64_V }, // 4979 |
24137 | | { PseudoVLUXSEG4EI64_V_M2_M1_MASK, VLUXSEG4EI64_V }, // 4980 |
24138 | | { PseudoVLUXSEG4EI64_V_M2_M2, VLUXSEG4EI64_V }, // 4981 |
24139 | | { PseudoVLUXSEG4EI64_V_M2_M2_MASK, VLUXSEG4EI64_V }, // 4982 |
24140 | | { PseudoVLUXSEG4EI64_V_M2_MF2, VLUXSEG4EI64_V }, // 4983 |
24141 | | { PseudoVLUXSEG4EI64_V_M2_MF2_MASK, VLUXSEG4EI64_V }, // 4984 |
24142 | | { PseudoVLUXSEG4EI64_V_M2_MF4, VLUXSEG4EI64_V }, // 4985 |
24143 | | { PseudoVLUXSEG4EI64_V_M2_MF4_MASK, VLUXSEG4EI64_V }, // 4986 |
24144 | | { PseudoVLUXSEG4EI64_V_M4_M1, VLUXSEG4EI64_V }, // 4987 |
24145 | | { PseudoVLUXSEG4EI64_V_M4_M1_MASK, VLUXSEG4EI64_V }, // 4988 |
24146 | | { PseudoVLUXSEG4EI64_V_M4_M2, VLUXSEG4EI64_V }, // 4989 |
24147 | | { PseudoVLUXSEG4EI64_V_M4_M2_MASK, VLUXSEG4EI64_V }, // 4990 |
24148 | | { PseudoVLUXSEG4EI64_V_M4_MF2, VLUXSEG4EI64_V }, // 4991 |
24149 | | { PseudoVLUXSEG4EI64_V_M4_MF2_MASK, VLUXSEG4EI64_V }, // 4992 |
24150 | | { PseudoVLUXSEG4EI64_V_M8_M1, VLUXSEG4EI64_V }, // 4993 |
24151 | | { PseudoVLUXSEG4EI64_V_M8_M1_MASK, VLUXSEG4EI64_V }, // 4994 |
24152 | | { PseudoVLUXSEG4EI64_V_M8_M2, VLUXSEG4EI64_V }, // 4995 |
24153 | | { PseudoVLUXSEG4EI64_V_M8_M2_MASK, VLUXSEG4EI64_V }, // 4996 |
24154 | | { PseudoVLUXSEG4EI8_V_M1_M1, VLUXSEG4EI8_V }, // 4997 |
24155 | | { PseudoVLUXSEG4EI8_V_M1_M1_MASK, VLUXSEG4EI8_V }, // 4998 |
24156 | | { PseudoVLUXSEG4EI8_V_M1_M2, VLUXSEG4EI8_V }, // 4999 |
24157 | | { PseudoVLUXSEG4EI8_V_M1_M2_MASK, VLUXSEG4EI8_V }, // 5000 |
24158 | | { PseudoVLUXSEG4EI8_V_M2_M2, VLUXSEG4EI8_V }, // 5001 |
24159 | | { PseudoVLUXSEG4EI8_V_M2_M2_MASK, VLUXSEG4EI8_V }, // 5002 |
24160 | | { PseudoVLUXSEG4EI8_V_MF2_M1, VLUXSEG4EI8_V }, // 5003 |
24161 | | { PseudoVLUXSEG4EI8_V_MF2_M1_MASK, VLUXSEG4EI8_V }, // 5004 |
24162 | | { PseudoVLUXSEG4EI8_V_MF2_M2, VLUXSEG4EI8_V }, // 5005 |
24163 | | { PseudoVLUXSEG4EI8_V_MF2_M2_MASK, VLUXSEG4EI8_V }, // 5006 |
24164 | | { PseudoVLUXSEG4EI8_V_MF2_MF2, VLUXSEG4EI8_V }, // 5007 |
24165 | | { PseudoVLUXSEG4EI8_V_MF2_MF2_MASK, VLUXSEG4EI8_V }, // 5008 |
24166 | | { PseudoVLUXSEG4EI8_V_MF4_M1, VLUXSEG4EI8_V }, // 5009 |
24167 | | { PseudoVLUXSEG4EI8_V_MF4_M1_MASK, VLUXSEG4EI8_V }, // 5010 |
24168 | | { PseudoVLUXSEG4EI8_V_MF4_M2, VLUXSEG4EI8_V }, // 5011 |
24169 | | { PseudoVLUXSEG4EI8_V_MF4_M2_MASK, VLUXSEG4EI8_V }, // 5012 |
24170 | | { PseudoVLUXSEG4EI8_V_MF4_MF2, VLUXSEG4EI8_V }, // 5013 |
24171 | | { PseudoVLUXSEG4EI8_V_MF4_MF2_MASK, VLUXSEG4EI8_V }, // 5014 |
24172 | | { PseudoVLUXSEG4EI8_V_MF4_MF4, VLUXSEG4EI8_V }, // 5015 |
24173 | | { PseudoVLUXSEG4EI8_V_MF4_MF4_MASK, VLUXSEG4EI8_V }, // 5016 |
24174 | | { PseudoVLUXSEG4EI8_V_MF8_M1, VLUXSEG4EI8_V }, // 5017 |
24175 | | { PseudoVLUXSEG4EI8_V_MF8_M1_MASK, VLUXSEG4EI8_V }, // 5018 |
24176 | | { PseudoVLUXSEG4EI8_V_MF8_MF2, VLUXSEG4EI8_V }, // 5019 |
24177 | | { PseudoVLUXSEG4EI8_V_MF8_MF2_MASK, VLUXSEG4EI8_V }, // 5020 |
24178 | | { PseudoVLUXSEG4EI8_V_MF8_MF4, VLUXSEG4EI8_V }, // 5021 |
24179 | | { PseudoVLUXSEG4EI8_V_MF8_MF4_MASK, VLUXSEG4EI8_V }, // 5022 |
24180 | | { PseudoVLUXSEG4EI8_V_MF8_MF8, VLUXSEG4EI8_V }, // 5023 |
24181 | | { PseudoVLUXSEG4EI8_V_MF8_MF8_MASK, VLUXSEG4EI8_V }, // 5024 |
24182 | | { PseudoVLUXSEG5EI16_V_M1_M1, VLUXSEG5EI16_V }, // 5025 |
24183 | | { PseudoVLUXSEG5EI16_V_M1_M1_MASK, VLUXSEG5EI16_V }, // 5026 |
24184 | | { PseudoVLUXSEG5EI16_V_M1_MF2, VLUXSEG5EI16_V }, // 5027 |
24185 | | { PseudoVLUXSEG5EI16_V_M1_MF2_MASK, VLUXSEG5EI16_V }, // 5028 |
24186 | | { PseudoVLUXSEG5EI16_V_M2_M1, VLUXSEG5EI16_V }, // 5029 |
24187 | | { PseudoVLUXSEG5EI16_V_M2_M1_MASK, VLUXSEG5EI16_V }, // 5030 |
24188 | | { PseudoVLUXSEG5EI16_V_MF2_M1, VLUXSEG5EI16_V }, // 5031 |
24189 | | { PseudoVLUXSEG5EI16_V_MF2_M1_MASK, VLUXSEG5EI16_V }, // 5032 |
24190 | | { PseudoVLUXSEG5EI16_V_MF2_MF2, VLUXSEG5EI16_V }, // 5033 |
24191 | | { PseudoVLUXSEG5EI16_V_MF2_MF2_MASK, VLUXSEG5EI16_V }, // 5034 |
24192 | | { PseudoVLUXSEG5EI16_V_MF2_MF4, VLUXSEG5EI16_V }, // 5035 |
24193 | | { PseudoVLUXSEG5EI16_V_MF2_MF4_MASK, VLUXSEG5EI16_V }, // 5036 |
24194 | | { PseudoVLUXSEG5EI16_V_MF4_M1, VLUXSEG5EI16_V }, // 5037 |
24195 | | { PseudoVLUXSEG5EI16_V_MF4_M1_MASK, VLUXSEG5EI16_V }, // 5038 |
24196 | | { PseudoVLUXSEG5EI16_V_MF4_MF2, VLUXSEG5EI16_V }, // 5039 |
24197 | | { PseudoVLUXSEG5EI16_V_MF4_MF2_MASK, VLUXSEG5EI16_V }, // 5040 |
24198 | | { PseudoVLUXSEG5EI16_V_MF4_MF4, VLUXSEG5EI16_V }, // 5041 |
24199 | | { PseudoVLUXSEG5EI16_V_MF4_MF4_MASK, VLUXSEG5EI16_V }, // 5042 |
24200 | | { PseudoVLUXSEG5EI16_V_MF4_MF8, VLUXSEG5EI16_V }, // 5043 |
24201 | | { PseudoVLUXSEG5EI16_V_MF4_MF8_MASK, VLUXSEG5EI16_V }, // 5044 |
24202 | | { PseudoVLUXSEG5EI32_V_M1_M1, VLUXSEG5EI32_V }, // 5045 |
24203 | | { PseudoVLUXSEG5EI32_V_M1_M1_MASK, VLUXSEG5EI32_V }, // 5046 |
24204 | | { PseudoVLUXSEG5EI32_V_M1_MF2, VLUXSEG5EI32_V }, // 5047 |
24205 | | { PseudoVLUXSEG5EI32_V_M1_MF2_MASK, VLUXSEG5EI32_V }, // 5048 |
24206 | | { PseudoVLUXSEG5EI32_V_M1_MF4, VLUXSEG5EI32_V }, // 5049 |
24207 | | { PseudoVLUXSEG5EI32_V_M1_MF4_MASK, VLUXSEG5EI32_V }, // 5050 |
24208 | | { PseudoVLUXSEG5EI32_V_M2_M1, VLUXSEG5EI32_V }, // 5051 |
24209 | | { PseudoVLUXSEG5EI32_V_M2_M1_MASK, VLUXSEG5EI32_V }, // 5052 |
24210 | | { PseudoVLUXSEG5EI32_V_M2_MF2, VLUXSEG5EI32_V }, // 5053 |
24211 | | { PseudoVLUXSEG5EI32_V_M2_MF2_MASK, VLUXSEG5EI32_V }, // 5054 |
24212 | | { PseudoVLUXSEG5EI32_V_M4_M1, VLUXSEG5EI32_V }, // 5055 |
24213 | | { PseudoVLUXSEG5EI32_V_M4_M1_MASK, VLUXSEG5EI32_V }, // 5056 |
24214 | | { PseudoVLUXSEG5EI32_V_MF2_M1, VLUXSEG5EI32_V }, // 5057 |
24215 | | { PseudoVLUXSEG5EI32_V_MF2_M1_MASK, VLUXSEG5EI32_V }, // 5058 |
24216 | | { PseudoVLUXSEG5EI32_V_MF2_MF2, VLUXSEG5EI32_V }, // 5059 |
24217 | | { PseudoVLUXSEG5EI32_V_MF2_MF2_MASK, VLUXSEG5EI32_V }, // 5060 |
24218 | | { PseudoVLUXSEG5EI32_V_MF2_MF4, VLUXSEG5EI32_V }, // 5061 |
24219 | | { PseudoVLUXSEG5EI32_V_MF2_MF4_MASK, VLUXSEG5EI32_V }, // 5062 |
24220 | | { PseudoVLUXSEG5EI32_V_MF2_MF8, VLUXSEG5EI32_V }, // 5063 |
24221 | | { PseudoVLUXSEG5EI32_V_MF2_MF8_MASK, VLUXSEG5EI32_V }, // 5064 |
24222 | | { PseudoVLUXSEG5EI64_V_M1_M1, VLUXSEG5EI64_V }, // 5065 |
24223 | | { PseudoVLUXSEG5EI64_V_M1_M1_MASK, VLUXSEG5EI64_V }, // 5066 |
24224 | | { PseudoVLUXSEG5EI64_V_M1_MF2, VLUXSEG5EI64_V }, // 5067 |
24225 | | { PseudoVLUXSEG5EI64_V_M1_MF2_MASK, VLUXSEG5EI64_V }, // 5068 |
24226 | | { PseudoVLUXSEG5EI64_V_M1_MF4, VLUXSEG5EI64_V }, // 5069 |
24227 | | { PseudoVLUXSEG5EI64_V_M1_MF4_MASK, VLUXSEG5EI64_V }, // 5070 |
24228 | | { PseudoVLUXSEG5EI64_V_M1_MF8, VLUXSEG5EI64_V }, // 5071 |
24229 | | { PseudoVLUXSEG5EI64_V_M1_MF8_MASK, VLUXSEG5EI64_V }, // 5072 |
24230 | | { PseudoVLUXSEG5EI64_V_M2_M1, VLUXSEG5EI64_V }, // 5073 |
24231 | | { PseudoVLUXSEG5EI64_V_M2_M1_MASK, VLUXSEG5EI64_V }, // 5074 |
24232 | | { PseudoVLUXSEG5EI64_V_M2_MF2, VLUXSEG5EI64_V }, // 5075 |
24233 | | { PseudoVLUXSEG5EI64_V_M2_MF2_MASK, VLUXSEG5EI64_V }, // 5076 |
24234 | | { PseudoVLUXSEG5EI64_V_M2_MF4, VLUXSEG5EI64_V }, // 5077 |
24235 | | { PseudoVLUXSEG5EI64_V_M2_MF4_MASK, VLUXSEG5EI64_V }, // 5078 |
24236 | | { PseudoVLUXSEG5EI64_V_M4_M1, VLUXSEG5EI64_V }, // 5079 |
24237 | | { PseudoVLUXSEG5EI64_V_M4_M1_MASK, VLUXSEG5EI64_V }, // 5080 |
24238 | | { PseudoVLUXSEG5EI64_V_M4_MF2, VLUXSEG5EI64_V }, // 5081 |
24239 | | { PseudoVLUXSEG5EI64_V_M4_MF2_MASK, VLUXSEG5EI64_V }, // 5082 |
24240 | | { PseudoVLUXSEG5EI64_V_M8_M1, VLUXSEG5EI64_V }, // 5083 |
24241 | | { PseudoVLUXSEG5EI64_V_M8_M1_MASK, VLUXSEG5EI64_V }, // 5084 |
24242 | | { PseudoVLUXSEG5EI8_V_M1_M1, VLUXSEG5EI8_V }, // 5085 |
24243 | | { PseudoVLUXSEG5EI8_V_M1_M1_MASK, VLUXSEG5EI8_V }, // 5086 |
24244 | | { PseudoVLUXSEG5EI8_V_MF2_M1, VLUXSEG5EI8_V }, // 5087 |
24245 | | { PseudoVLUXSEG5EI8_V_MF2_M1_MASK, VLUXSEG5EI8_V }, // 5088 |
24246 | | { PseudoVLUXSEG5EI8_V_MF2_MF2, VLUXSEG5EI8_V }, // 5089 |
24247 | | { PseudoVLUXSEG5EI8_V_MF2_MF2_MASK, VLUXSEG5EI8_V }, // 5090 |
24248 | | { PseudoVLUXSEG5EI8_V_MF4_M1, VLUXSEG5EI8_V }, // 5091 |
24249 | | { PseudoVLUXSEG5EI8_V_MF4_M1_MASK, VLUXSEG5EI8_V }, // 5092 |
24250 | | { PseudoVLUXSEG5EI8_V_MF4_MF2, VLUXSEG5EI8_V }, // 5093 |
24251 | | { PseudoVLUXSEG5EI8_V_MF4_MF2_MASK, VLUXSEG5EI8_V }, // 5094 |
24252 | | { PseudoVLUXSEG5EI8_V_MF4_MF4, VLUXSEG5EI8_V }, // 5095 |
24253 | | { PseudoVLUXSEG5EI8_V_MF4_MF4_MASK, VLUXSEG5EI8_V }, // 5096 |
24254 | | { PseudoVLUXSEG5EI8_V_MF8_M1, VLUXSEG5EI8_V }, // 5097 |
24255 | | { PseudoVLUXSEG5EI8_V_MF8_M1_MASK, VLUXSEG5EI8_V }, // 5098 |
24256 | | { PseudoVLUXSEG5EI8_V_MF8_MF2, VLUXSEG5EI8_V }, // 5099 |
24257 | | { PseudoVLUXSEG5EI8_V_MF8_MF2_MASK, VLUXSEG5EI8_V }, // 5100 |
24258 | | { PseudoVLUXSEG5EI8_V_MF8_MF4, VLUXSEG5EI8_V }, // 5101 |
24259 | | { PseudoVLUXSEG5EI8_V_MF8_MF4_MASK, VLUXSEG5EI8_V }, // 5102 |
24260 | | { PseudoVLUXSEG5EI8_V_MF8_MF8, VLUXSEG5EI8_V }, // 5103 |
24261 | | { PseudoVLUXSEG5EI8_V_MF8_MF8_MASK, VLUXSEG5EI8_V }, // 5104 |
24262 | | { PseudoVLUXSEG6EI16_V_M1_M1, VLUXSEG6EI16_V }, // 5105 |
24263 | | { PseudoVLUXSEG6EI16_V_M1_M1_MASK, VLUXSEG6EI16_V }, // 5106 |
24264 | | { PseudoVLUXSEG6EI16_V_M1_MF2, VLUXSEG6EI16_V }, // 5107 |
24265 | | { PseudoVLUXSEG6EI16_V_M1_MF2_MASK, VLUXSEG6EI16_V }, // 5108 |
24266 | | { PseudoVLUXSEG6EI16_V_M2_M1, VLUXSEG6EI16_V }, // 5109 |
24267 | | { PseudoVLUXSEG6EI16_V_M2_M1_MASK, VLUXSEG6EI16_V }, // 5110 |
24268 | | { PseudoVLUXSEG6EI16_V_MF2_M1, VLUXSEG6EI16_V }, // 5111 |
24269 | | { PseudoVLUXSEG6EI16_V_MF2_M1_MASK, VLUXSEG6EI16_V }, // 5112 |
24270 | | { PseudoVLUXSEG6EI16_V_MF2_MF2, VLUXSEG6EI16_V }, // 5113 |
24271 | | { PseudoVLUXSEG6EI16_V_MF2_MF2_MASK, VLUXSEG6EI16_V }, // 5114 |
24272 | | { PseudoVLUXSEG6EI16_V_MF2_MF4, VLUXSEG6EI16_V }, // 5115 |
24273 | | { PseudoVLUXSEG6EI16_V_MF2_MF4_MASK, VLUXSEG6EI16_V }, // 5116 |
24274 | | { PseudoVLUXSEG6EI16_V_MF4_M1, VLUXSEG6EI16_V }, // 5117 |
24275 | | { PseudoVLUXSEG6EI16_V_MF4_M1_MASK, VLUXSEG6EI16_V }, // 5118 |
24276 | | { PseudoVLUXSEG6EI16_V_MF4_MF2, VLUXSEG6EI16_V }, // 5119 |
24277 | | { PseudoVLUXSEG6EI16_V_MF4_MF2_MASK, VLUXSEG6EI16_V }, // 5120 |
24278 | | { PseudoVLUXSEG6EI16_V_MF4_MF4, VLUXSEG6EI16_V }, // 5121 |
24279 | | { PseudoVLUXSEG6EI16_V_MF4_MF4_MASK, VLUXSEG6EI16_V }, // 5122 |
24280 | | { PseudoVLUXSEG6EI16_V_MF4_MF8, VLUXSEG6EI16_V }, // 5123 |
24281 | | { PseudoVLUXSEG6EI16_V_MF4_MF8_MASK, VLUXSEG6EI16_V }, // 5124 |
24282 | | { PseudoVLUXSEG6EI32_V_M1_M1, VLUXSEG6EI32_V }, // 5125 |
24283 | | { PseudoVLUXSEG6EI32_V_M1_M1_MASK, VLUXSEG6EI32_V }, // 5126 |
24284 | | { PseudoVLUXSEG6EI32_V_M1_MF2, VLUXSEG6EI32_V }, // 5127 |
24285 | | { PseudoVLUXSEG6EI32_V_M1_MF2_MASK, VLUXSEG6EI32_V }, // 5128 |
24286 | | { PseudoVLUXSEG6EI32_V_M1_MF4, VLUXSEG6EI32_V }, // 5129 |
24287 | | { PseudoVLUXSEG6EI32_V_M1_MF4_MASK, VLUXSEG6EI32_V }, // 5130 |
24288 | | { PseudoVLUXSEG6EI32_V_M2_M1, VLUXSEG6EI32_V }, // 5131 |
24289 | | { PseudoVLUXSEG6EI32_V_M2_M1_MASK, VLUXSEG6EI32_V }, // 5132 |
24290 | | { PseudoVLUXSEG6EI32_V_M2_MF2, VLUXSEG6EI32_V }, // 5133 |
24291 | | { PseudoVLUXSEG6EI32_V_M2_MF2_MASK, VLUXSEG6EI32_V }, // 5134 |
24292 | | { PseudoVLUXSEG6EI32_V_M4_M1, VLUXSEG6EI32_V }, // 5135 |
24293 | | { PseudoVLUXSEG6EI32_V_M4_M1_MASK, VLUXSEG6EI32_V }, // 5136 |
24294 | | { PseudoVLUXSEG6EI32_V_MF2_M1, VLUXSEG6EI32_V }, // 5137 |
24295 | | { PseudoVLUXSEG6EI32_V_MF2_M1_MASK, VLUXSEG6EI32_V }, // 5138 |
24296 | | { PseudoVLUXSEG6EI32_V_MF2_MF2, VLUXSEG6EI32_V }, // 5139 |
24297 | | { PseudoVLUXSEG6EI32_V_MF2_MF2_MASK, VLUXSEG6EI32_V }, // 5140 |
24298 | | { PseudoVLUXSEG6EI32_V_MF2_MF4, VLUXSEG6EI32_V }, // 5141 |
24299 | | { PseudoVLUXSEG6EI32_V_MF2_MF4_MASK, VLUXSEG6EI32_V }, // 5142 |
24300 | | { PseudoVLUXSEG6EI32_V_MF2_MF8, VLUXSEG6EI32_V }, // 5143 |
24301 | | { PseudoVLUXSEG6EI32_V_MF2_MF8_MASK, VLUXSEG6EI32_V }, // 5144 |
24302 | | { PseudoVLUXSEG6EI64_V_M1_M1, VLUXSEG6EI64_V }, // 5145 |
24303 | | { PseudoVLUXSEG6EI64_V_M1_M1_MASK, VLUXSEG6EI64_V }, // 5146 |
24304 | | { PseudoVLUXSEG6EI64_V_M1_MF2, VLUXSEG6EI64_V }, // 5147 |
24305 | | { PseudoVLUXSEG6EI64_V_M1_MF2_MASK, VLUXSEG6EI64_V }, // 5148 |
24306 | | { PseudoVLUXSEG6EI64_V_M1_MF4, VLUXSEG6EI64_V }, // 5149 |
24307 | | { PseudoVLUXSEG6EI64_V_M1_MF4_MASK, VLUXSEG6EI64_V }, // 5150 |
24308 | | { PseudoVLUXSEG6EI64_V_M1_MF8, VLUXSEG6EI64_V }, // 5151 |
24309 | | { PseudoVLUXSEG6EI64_V_M1_MF8_MASK, VLUXSEG6EI64_V }, // 5152 |
24310 | | { PseudoVLUXSEG6EI64_V_M2_M1, VLUXSEG6EI64_V }, // 5153 |
24311 | | { PseudoVLUXSEG6EI64_V_M2_M1_MASK, VLUXSEG6EI64_V }, // 5154 |
24312 | | { PseudoVLUXSEG6EI64_V_M2_MF2, VLUXSEG6EI64_V }, // 5155 |
24313 | | { PseudoVLUXSEG6EI64_V_M2_MF2_MASK, VLUXSEG6EI64_V }, // 5156 |
24314 | | { PseudoVLUXSEG6EI64_V_M2_MF4, VLUXSEG6EI64_V }, // 5157 |
24315 | | { PseudoVLUXSEG6EI64_V_M2_MF4_MASK, VLUXSEG6EI64_V }, // 5158 |
24316 | | { PseudoVLUXSEG6EI64_V_M4_M1, VLUXSEG6EI64_V }, // 5159 |
24317 | | { PseudoVLUXSEG6EI64_V_M4_M1_MASK, VLUXSEG6EI64_V }, // 5160 |
24318 | | { PseudoVLUXSEG6EI64_V_M4_MF2, VLUXSEG6EI64_V }, // 5161 |
24319 | | { PseudoVLUXSEG6EI64_V_M4_MF2_MASK, VLUXSEG6EI64_V }, // 5162 |
24320 | | { PseudoVLUXSEG6EI64_V_M8_M1, VLUXSEG6EI64_V }, // 5163 |
24321 | | { PseudoVLUXSEG6EI64_V_M8_M1_MASK, VLUXSEG6EI64_V }, // 5164 |
24322 | | { PseudoVLUXSEG6EI8_V_M1_M1, VLUXSEG6EI8_V }, // 5165 |
24323 | | { PseudoVLUXSEG6EI8_V_M1_M1_MASK, VLUXSEG6EI8_V }, // 5166 |
24324 | | { PseudoVLUXSEG6EI8_V_MF2_M1, VLUXSEG6EI8_V }, // 5167 |
24325 | | { PseudoVLUXSEG6EI8_V_MF2_M1_MASK, VLUXSEG6EI8_V }, // 5168 |
24326 | | { PseudoVLUXSEG6EI8_V_MF2_MF2, VLUXSEG6EI8_V }, // 5169 |
24327 | | { PseudoVLUXSEG6EI8_V_MF2_MF2_MASK, VLUXSEG6EI8_V }, // 5170 |
24328 | | { PseudoVLUXSEG6EI8_V_MF4_M1, VLUXSEG6EI8_V }, // 5171 |
24329 | | { PseudoVLUXSEG6EI8_V_MF4_M1_MASK, VLUXSEG6EI8_V }, // 5172 |
24330 | | { PseudoVLUXSEG6EI8_V_MF4_MF2, VLUXSEG6EI8_V }, // 5173 |
24331 | | { PseudoVLUXSEG6EI8_V_MF4_MF2_MASK, VLUXSEG6EI8_V }, // 5174 |
24332 | | { PseudoVLUXSEG6EI8_V_MF4_MF4, VLUXSEG6EI8_V }, // 5175 |
24333 | | { PseudoVLUXSEG6EI8_V_MF4_MF4_MASK, VLUXSEG6EI8_V }, // 5176 |
24334 | | { PseudoVLUXSEG6EI8_V_MF8_M1, VLUXSEG6EI8_V }, // 5177 |
24335 | | { PseudoVLUXSEG6EI8_V_MF8_M1_MASK, VLUXSEG6EI8_V }, // 5178 |
24336 | | { PseudoVLUXSEG6EI8_V_MF8_MF2, VLUXSEG6EI8_V }, // 5179 |
24337 | | { PseudoVLUXSEG6EI8_V_MF8_MF2_MASK, VLUXSEG6EI8_V }, // 5180 |
24338 | | { PseudoVLUXSEG6EI8_V_MF8_MF4, VLUXSEG6EI8_V }, // 5181 |
24339 | | { PseudoVLUXSEG6EI8_V_MF8_MF4_MASK, VLUXSEG6EI8_V }, // 5182 |
24340 | | { PseudoVLUXSEG6EI8_V_MF8_MF8, VLUXSEG6EI8_V }, // 5183 |
24341 | | { PseudoVLUXSEG6EI8_V_MF8_MF8_MASK, VLUXSEG6EI8_V }, // 5184 |
24342 | | { PseudoVLUXSEG7EI16_V_M1_M1, VLUXSEG7EI16_V }, // 5185 |
24343 | | { PseudoVLUXSEG7EI16_V_M1_M1_MASK, VLUXSEG7EI16_V }, // 5186 |
24344 | | { PseudoVLUXSEG7EI16_V_M1_MF2, VLUXSEG7EI16_V }, // 5187 |
24345 | | { PseudoVLUXSEG7EI16_V_M1_MF2_MASK, VLUXSEG7EI16_V }, // 5188 |
24346 | | { PseudoVLUXSEG7EI16_V_M2_M1, VLUXSEG7EI16_V }, // 5189 |
24347 | | { PseudoVLUXSEG7EI16_V_M2_M1_MASK, VLUXSEG7EI16_V }, // 5190 |
24348 | | { PseudoVLUXSEG7EI16_V_MF2_M1, VLUXSEG7EI16_V }, // 5191 |
24349 | | { PseudoVLUXSEG7EI16_V_MF2_M1_MASK, VLUXSEG7EI16_V }, // 5192 |
24350 | | { PseudoVLUXSEG7EI16_V_MF2_MF2, VLUXSEG7EI16_V }, // 5193 |
24351 | | { PseudoVLUXSEG7EI16_V_MF2_MF2_MASK, VLUXSEG7EI16_V }, // 5194 |
24352 | | { PseudoVLUXSEG7EI16_V_MF2_MF4, VLUXSEG7EI16_V }, // 5195 |
24353 | | { PseudoVLUXSEG7EI16_V_MF2_MF4_MASK, VLUXSEG7EI16_V }, // 5196 |
24354 | | { PseudoVLUXSEG7EI16_V_MF4_M1, VLUXSEG7EI16_V }, // 5197 |
24355 | | { PseudoVLUXSEG7EI16_V_MF4_M1_MASK, VLUXSEG7EI16_V }, // 5198 |
24356 | | { PseudoVLUXSEG7EI16_V_MF4_MF2, VLUXSEG7EI16_V }, // 5199 |
24357 | | { PseudoVLUXSEG7EI16_V_MF4_MF2_MASK, VLUXSEG7EI16_V }, // 5200 |
24358 | | { PseudoVLUXSEG7EI16_V_MF4_MF4, VLUXSEG7EI16_V }, // 5201 |
24359 | | { PseudoVLUXSEG7EI16_V_MF4_MF4_MASK, VLUXSEG7EI16_V }, // 5202 |
24360 | | { PseudoVLUXSEG7EI16_V_MF4_MF8, VLUXSEG7EI16_V }, // 5203 |
24361 | | { PseudoVLUXSEG7EI16_V_MF4_MF8_MASK, VLUXSEG7EI16_V }, // 5204 |
24362 | | { PseudoVLUXSEG7EI32_V_M1_M1, VLUXSEG7EI32_V }, // 5205 |
24363 | | { PseudoVLUXSEG7EI32_V_M1_M1_MASK, VLUXSEG7EI32_V }, // 5206 |
24364 | | { PseudoVLUXSEG7EI32_V_M1_MF2, VLUXSEG7EI32_V }, // 5207 |
24365 | | { PseudoVLUXSEG7EI32_V_M1_MF2_MASK, VLUXSEG7EI32_V }, // 5208 |
24366 | | { PseudoVLUXSEG7EI32_V_M1_MF4, VLUXSEG7EI32_V }, // 5209 |
24367 | | { PseudoVLUXSEG7EI32_V_M1_MF4_MASK, VLUXSEG7EI32_V }, // 5210 |
24368 | | { PseudoVLUXSEG7EI32_V_M2_M1, VLUXSEG7EI32_V }, // 5211 |
24369 | | { PseudoVLUXSEG7EI32_V_M2_M1_MASK, VLUXSEG7EI32_V }, // 5212 |
24370 | | { PseudoVLUXSEG7EI32_V_M2_MF2, VLUXSEG7EI32_V }, // 5213 |
24371 | | { PseudoVLUXSEG7EI32_V_M2_MF2_MASK, VLUXSEG7EI32_V }, // 5214 |
24372 | | { PseudoVLUXSEG7EI32_V_M4_M1, VLUXSEG7EI32_V }, // 5215 |
24373 | | { PseudoVLUXSEG7EI32_V_M4_M1_MASK, VLUXSEG7EI32_V }, // 5216 |
24374 | | { PseudoVLUXSEG7EI32_V_MF2_M1, VLUXSEG7EI32_V }, // 5217 |
24375 | | { PseudoVLUXSEG7EI32_V_MF2_M1_MASK, VLUXSEG7EI32_V }, // 5218 |
24376 | | { PseudoVLUXSEG7EI32_V_MF2_MF2, VLUXSEG7EI32_V }, // 5219 |
24377 | | { PseudoVLUXSEG7EI32_V_MF2_MF2_MASK, VLUXSEG7EI32_V }, // 5220 |
24378 | | { PseudoVLUXSEG7EI32_V_MF2_MF4, VLUXSEG7EI32_V }, // 5221 |
24379 | | { PseudoVLUXSEG7EI32_V_MF2_MF4_MASK, VLUXSEG7EI32_V }, // 5222 |
24380 | | { PseudoVLUXSEG7EI32_V_MF2_MF8, VLUXSEG7EI32_V }, // 5223 |
24381 | | { PseudoVLUXSEG7EI32_V_MF2_MF8_MASK, VLUXSEG7EI32_V }, // 5224 |
24382 | | { PseudoVLUXSEG7EI64_V_M1_M1, VLUXSEG7EI64_V }, // 5225 |
24383 | | { PseudoVLUXSEG7EI64_V_M1_M1_MASK, VLUXSEG7EI64_V }, // 5226 |
24384 | | { PseudoVLUXSEG7EI64_V_M1_MF2, VLUXSEG7EI64_V }, // 5227 |
24385 | | { PseudoVLUXSEG7EI64_V_M1_MF2_MASK, VLUXSEG7EI64_V }, // 5228 |
24386 | | { PseudoVLUXSEG7EI64_V_M1_MF4, VLUXSEG7EI64_V }, // 5229 |
24387 | | { PseudoVLUXSEG7EI64_V_M1_MF4_MASK, VLUXSEG7EI64_V }, // 5230 |
24388 | | { PseudoVLUXSEG7EI64_V_M1_MF8, VLUXSEG7EI64_V }, // 5231 |
24389 | | { PseudoVLUXSEG7EI64_V_M1_MF8_MASK, VLUXSEG7EI64_V }, // 5232 |
24390 | | { PseudoVLUXSEG7EI64_V_M2_M1, VLUXSEG7EI64_V }, // 5233 |
24391 | | { PseudoVLUXSEG7EI64_V_M2_M1_MASK, VLUXSEG7EI64_V }, // 5234 |
24392 | | { PseudoVLUXSEG7EI64_V_M2_MF2, VLUXSEG7EI64_V }, // 5235 |
24393 | | { PseudoVLUXSEG7EI64_V_M2_MF2_MASK, VLUXSEG7EI64_V }, // 5236 |
24394 | | { PseudoVLUXSEG7EI64_V_M2_MF4, VLUXSEG7EI64_V }, // 5237 |
24395 | | { PseudoVLUXSEG7EI64_V_M2_MF4_MASK, VLUXSEG7EI64_V }, // 5238 |
24396 | | { PseudoVLUXSEG7EI64_V_M4_M1, VLUXSEG7EI64_V }, // 5239 |
24397 | | { PseudoVLUXSEG7EI64_V_M4_M1_MASK, VLUXSEG7EI64_V }, // 5240 |
24398 | | { PseudoVLUXSEG7EI64_V_M4_MF2, VLUXSEG7EI64_V }, // 5241 |
24399 | | { PseudoVLUXSEG7EI64_V_M4_MF2_MASK, VLUXSEG7EI64_V }, // 5242 |
24400 | | { PseudoVLUXSEG7EI64_V_M8_M1, VLUXSEG7EI64_V }, // 5243 |
24401 | | { PseudoVLUXSEG7EI64_V_M8_M1_MASK, VLUXSEG7EI64_V }, // 5244 |
24402 | | { PseudoVLUXSEG7EI8_V_M1_M1, VLUXSEG7EI8_V }, // 5245 |
24403 | | { PseudoVLUXSEG7EI8_V_M1_M1_MASK, VLUXSEG7EI8_V }, // 5246 |
24404 | | { PseudoVLUXSEG7EI8_V_MF2_M1, VLUXSEG7EI8_V }, // 5247 |
24405 | | { PseudoVLUXSEG7EI8_V_MF2_M1_MASK, VLUXSEG7EI8_V }, // 5248 |
24406 | | { PseudoVLUXSEG7EI8_V_MF2_MF2, VLUXSEG7EI8_V }, // 5249 |
24407 | | { PseudoVLUXSEG7EI8_V_MF2_MF2_MASK, VLUXSEG7EI8_V }, // 5250 |
24408 | | { PseudoVLUXSEG7EI8_V_MF4_M1, VLUXSEG7EI8_V }, // 5251 |
24409 | | { PseudoVLUXSEG7EI8_V_MF4_M1_MASK, VLUXSEG7EI8_V }, // 5252 |
24410 | | { PseudoVLUXSEG7EI8_V_MF4_MF2, VLUXSEG7EI8_V }, // 5253 |
24411 | | { PseudoVLUXSEG7EI8_V_MF4_MF2_MASK, VLUXSEG7EI8_V }, // 5254 |
24412 | | { PseudoVLUXSEG7EI8_V_MF4_MF4, VLUXSEG7EI8_V }, // 5255 |
24413 | | { PseudoVLUXSEG7EI8_V_MF4_MF4_MASK, VLUXSEG7EI8_V }, // 5256 |
24414 | | { PseudoVLUXSEG7EI8_V_MF8_M1, VLUXSEG7EI8_V }, // 5257 |
24415 | | { PseudoVLUXSEG7EI8_V_MF8_M1_MASK, VLUXSEG7EI8_V }, // 5258 |
24416 | | { PseudoVLUXSEG7EI8_V_MF8_MF2, VLUXSEG7EI8_V }, // 5259 |
24417 | | { PseudoVLUXSEG7EI8_V_MF8_MF2_MASK, VLUXSEG7EI8_V }, // 5260 |
24418 | | { PseudoVLUXSEG7EI8_V_MF8_MF4, VLUXSEG7EI8_V }, // 5261 |
24419 | | { PseudoVLUXSEG7EI8_V_MF8_MF4_MASK, VLUXSEG7EI8_V }, // 5262 |
24420 | | { PseudoVLUXSEG7EI8_V_MF8_MF8, VLUXSEG7EI8_V }, // 5263 |
24421 | | { PseudoVLUXSEG7EI8_V_MF8_MF8_MASK, VLUXSEG7EI8_V }, // 5264 |
24422 | | { PseudoVLUXSEG8EI16_V_M1_M1, VLUXSEG8EI16_V }, // 5265 |
24423 | | { PseudoVLUXSEG8EI16_V_M1_M1_MASK, VLUXSEG8EI16_V }, // 5266 |
24424 | | { PseudoVLUXSEG8EI16_V_M1_MF2, VLUXSEG8EI16_V }, // 5267 |
24425 | | { PseudoVLUXSEG8EI16_V_M1_MF2_MASK, VLUXSEG8EI16_V }, // 5268 |
24426 | | { PseudoVLUXSEG8EI16_V_M2_M1, VLUXSEG8EI16_V }, // 5269 |
24427 | | { PseudoVLUXSEG8EI16_V_M2_M1_MASK, VLUXSEG8EI16_V }, // 5270 |
24428 | | { PseudoVLUXSEG8EI16_V_MF2_M1, VLUXSEG8EI16_V }, // 5271 |
24429 | | { PseudoVLUXSEG8EI16_V_MF2_M1_MASK, VLUXSEG8EI16_V }, // 5272 |
24430 | | { PseudoVLUXSEG8EI16_V_MF2_MF2, VLUXSEG8EI16_V }, // 5273 |
24431 | | { PseudoVLUXSEG8EI16_V_MF2_MF2_MASK, VLUXSEG8EI16_V }, // 5274 |
24432 | | { PseudoVLUXSEG8EI16_V_MF2_MF4, VLUXSEG8EI16_V }, // 5275 |
24433 | | { PseudoVLUXSEG8EI16_V_MF2_MF4_MASK, VLUXSEG8EI16_V }, // 5276 |
24434 | | { PseudoVLUXSEG8EI16_V_MF4_M1, VLUXSEG8EI16_V }, // 5277 |
24435 | | { PseudoVLUXSEG8EI16_V_MF4_M1_MASK, VLUXSEG8EI16_V }, // 5278 |
24436 | | { PseudoVLUXSEG8EI16_V_MF4_MF2, VLUXSEG8EI16_V }, // 5279 |
24437 | | { PseudoVLUXSEG8EI16_V_MF4_MF2_MASK, VLUXSEG8EI16_V }, // 5280 |
24438 | | { PseudoVLUXSEG8EI16_V_MF4_MF4, VLUXSEG8EI16_V }, // 5281 |
24439 | | { PseudoVLUXSEG8EI16_V_MF4_MF4_MASK, VLUXSEG8EI16_V }, // 5282 |
24440 | | { PseudoVLUXSEG8EI16_V_MF4_MF8, VLUXSEG8EI16_V }, // 5283 |
24441 | | { PseudoVLUXSEG8EI16_V_MF4_MF8_MASK, VLUXSEG8EI16_V }, // 5284 |
24442 | | { PseudoVLUXSEG8EI32_V_M1_M1, VLUXSEG8EI32_V }, // 5285 |
24443 | | { PseudoVLUXSEG8EI32_V_M1_M1_MASK, VLUXSEG8EI32_V }, // 5286 |
24444 | | { PseudoVLUXSEG8EI32_V_M1_MF2, VLUXSEG8EI32_V }, // 5287 |
24445 | | { PseudoVLUXSEG8EI32_V_M1_MF2_MASK, VLUXSEG8EI32_V }, // 5288 |
24446 | | { PseudoVLUXSEG8EI32_V_M1_MF4, VLUXSEG8EI32_V }, // 5289 |
24447 | | { PseudoVLUXSEG8EI32_V_M1_MF4_MASK, VLUXSEG8EI32_V }, // 5290 |
24448 | | { PseudoVLUXSEG8EI32_V_M2_M1, VLUXSEG8EI32_V }, // 5291 |
24449 | | { PseudoVLUXSEG8EI32_V_M2_M1_MASK, VLUXSEG8EI32_V }, // 5292 |
24450 | | { PseudoVLUXSEG8EI32_V_M2_MF2, VLUXSEG8EI32_V }, // 5293 |
24451 | | { PseudoVLUXSEG8EI32_V_M2_MF2_MASK, VLUXSEG8EI32_V }, // 5294 |
24452 | | { PseudoVLUXSEG8EI32_V_M4_M1, VLUXSEG8EI32_V }, // 5295 |
24453 | | { PseudoVLUXSEG8EI32_V_M4_M1_MASK, VLUXSEG8EI32_V }, // 5296 |
24454 | | { PseudoVLUXSEG8EI32_V_MF2_M1, VLUXSEG8EI32_V }, // 5297 |
24455 | | { PseudoVLUXSEG8EI32_V_MF2_M1_MASK, VLUXSEG8EI32_V }, // 5298 |
24456 | | { PseudoVLUXSEG8EI32_V_MF2_MF2, VLUXSEG8EI32_V }, // 5299 |
24457 | | { PseudoVLUXSEG8EI32_V_MF2_MF2_MASK, VLUXSEG8EI32_V }, // 5300 |
24458 | | { PseudoVLUXSEG8EI32_V_MF2_MF4, VLUXSEG8EI32_V }, // 5301 |
24459 | | { PseudoVLUXSEG8EI32_V_MF2_MF4_MASK, VLUXSEG8EI32_V }, // 5302 |
24460 | | { PseudoVLUXSEG8EI32_V_MF2_MF8, VLUXSEG8EI32_V }, // 5303 |
24461 | | { PseudoVLUXSEG8EI32_V_MF2_MF8_MASK, VLUXSEG8EI32_V }, // 5304 |
24462 | | { PseudoVLUXSEG8EI64_V_M1_M1, VLUXSEG8EI64_V }, // 5305 |
24463 | | { PseudoVLUXSEG8EI64_V_M1_M1_MASK, VLUXSEG8EI64_V }, // 5306 |
24464 | | { PseudoVLUXSEG8EI64_V_M1_MF2, VLUXSEG8EI64_V }, // 5307 |
24465 | | { PseudoVLUXSEG8EI64_V_M1_MF2_MASK, VLUXSEG8EI64_V }, // 5308 |
24466 | | { PseudoVLUXSEG8EI64_V_M1_MF4, VLUXSEG8EI64_V }, // 5309 |
24467 | | { PseudoVLUXSEG8EI64_V_M1_MF4_MASK, VLUXSEG8EI64_V }, // 5310 |
24468 | | { PseudoVLUXSEG8EI64_V_M1_MF8, VLUXSEG8EI64_V }, // 5311 |
24469 | | { PseudoVLUXSEG8EI64_V_M1_MF8_MASK, VLUXSEG8EI64_V }, // 5312 |
24470 | | { PseudoVLUXSEG8EI64_V_M2_M1, VLUXSEG8EI64_V }, // 5313 |
24471 | | { PseudoVLUXSEG8EI64_V_M2_M1_MASK, VLUXSEG8EI64_V }, // 5314 |
24472 | | { PseudoVLUXSEG8EI64_V_M2_MF2, VLUXSEG8EI64_V }, // 5315 |
24473 | | { PseudoVLUXSEG8EI64_V_M2_MF2_MASK, VLUXSEG8EI64_V }, // 5316 |
24474 | | { PseudoVLUXSEG8EI64_V_M2_MF4, VLUXSEG8EI64_V }, // 5317 |
24475 | | { PseudoVLUXSEG8EI64_V_M2_MF4_MASK, VLUXSEG8EI64_V }, // 5318 |
24476 | | { PseudoVLUXSEG8EI64_V_M4_M1, VLUXSEG8EI64_V }, // 5319 |
24477 | | { PseudoVLUXSEG8EI64_V_M4_M1_MASK, VLUXSEG8EI64_V }, // 5320 |
24478 | | { PseudoVLUXSEG8EI64_V_M4_MF2, VLUXSEG8EI64_V }, // 5321 |
24479 | | { PseudoVLUXSEG8EI64_V_M4_MF2_MASK, VLUXSEG8EI64_V }, // 5322 |
24480 | | { PseudoVLUXSEG8EI64_V_M8_M1, VLUXSEG8EI64_V }, // 5323 |
24481 | | { PseudoVLUXSEG8EI64_V_M8_M1_MASK, VLUXSEG8EI64_V }, // 5324 |
24482 | | { PseudoVLUXSEG8EI8_V_M1_M1, VLUXSEG8EI8_V }, // 5325 |
24483 | | { PseudoVLUXSEG8EI8_V_M1_M1_MASK, VLUXSEG8EI8_V }, // 5326 |
24484 | | { PseudoVLUXSEG8EI8_V_MF2_M1, VLUXSEG8EI8_V }, // 5327 |
24485 | | { PseudoVLUXSEG8EI8_V_MF2_M1_MASK, VLUXSEG8EI8_V }, // 5328 |
24486 | | { PseudoVLUXSEG8EI8_V_MF2_MF2, VLUXSEG8EI8_V }, // 5329 |
24487 | | { PseudoVLUXSEG8EI8_V_MF2_MF2_MASK, VLUXSEG8EI8_V }, // 5330 |
24488 | | { PseudoVLUXSEG8EI8_V_MF4_M1, VLUXSEG8EI8_V }, // 5331 |
24489 | | { PseudoVLUXSEG8EI8_V_MF4_M1_MASK, VLUXSEG8EI8_V }, // 5332 |
24490 | | { PseudoVLUXSEG8EI8_V_MF4_MF2, VLUXSEG8EI8_V }, // 5333 |
24491 | | { PseudoVLUXSEG8EI8_V_MF4_MF2_MASK, VLUXSEG8EI8_V }, // 5334 |
24492 | | { PseudoVLUXSEG8EI8_V_MF4_MF4, VLUXSEG8EI8_V }, // 5335 |
24493 | | { PseudoVLUXSEG8EI8_V_MF4_MF4_MASK, VLUXSEG8EI8_V }, // 5336 |
24494 | | { PseudoVLUXSEG8EI8_V_MF8_M1, VLUXSEG8EI8_V }, // 5337 |
24495 | | { PseudoVLUXSEG8EI8_V_MF8_M1_MASK, VLUXSEG8EI8_V }, // 5338 |
24496 | | { PseudoVLUXSEG8EI8_V_MF8_MF2, VLUXSEG8EI8_V }, // 5339 |
24497 | | { PseudoVLUXSEG8EI8_V_MF8_MF2_MASK, VLUXSEG8EI8_V }, // 5340 |
24498 | | { PseudoVLUXSEG8EI8_V_MF8_MF4, VLUXSEG8EI8_V }, // 5341 |
24499 | | { PseudoVLUXSEG8EI8_V_MF8_MF4_MASK, VLUXSEG8EI8_V }, // 5342 |
24500 | | { PseudoVLUXSEG8EI8_V_MF8_MF8, VLUXSEG8EI8_V }, // 5343 |
24501 | | { PseudoVLUXSEG8EI8_V_MF8_MF8_MASK, VLUXSEG8EI8_V }, // 5344 |
24502 | | { PseudoVMACC_VV_M1, VMACC_VV }, // 5345 |
24503 | | { PseudoVMACC_VV_M1_MASK, VMACC_VV }, // 5346 |
24504 | | { PseudoVMACC_VV_M2, VMACC_VV }, // 5347 |
24505 | | { PseudoVMACC_VV_M2_MASK, VMACC_VV }, // 5348 |
24506 | | { PseudoVMACC_VV_M4, VMACC_VV }, // 5349 |
24507 | | { PseudoVMACC_VV_M4_MASK, VMACC_VV }, // 5350 |
24508 | | { PseudoVMACC_VV_M8, VMACC_VV }, // 5351 |
24509 | | { PseudoVMACC_VV_M8_MASK, VMACC_VV }, // 5352 |
24510 | | { PseudoVMACC_VV_MF2, VMACC_VV }, // 5353 |
24511 | | { PseudoVMACC_VV_MF2_MASK, VMACC_VV }, // 5354 |
24512 | | { PseudoVMACC_VV_MF4, VMACC_VV }, // 5355 |
24513 | | { PseudoVMACC_VV_MF4_MASK, VMACC_VV }, // 5356 |
24514 | | { PseudoVMACC_VV_MF8, VMACC_VV }, // 5357 |
24515 | | { PseudoVMACC_VV_MF8_MASK, VMACC_VV }, // 5358 |
24516 | | { PseudoVMACC_VX_M1, VMACC_VX }, // 5359 |
24517 | | { PseudoVMACC_VX_M1_MASK, VMACC_VX }, // 5360 |
24518 | | { PseudoVMACC_VX_M2, VMACC_VX }, // 5361 |
24519 | | { PseudoVMACC_VX_M2_MASK, VMACC_VX }, // 5362 |
24520 | | { PseudoVMACC_VX_M4, VMACC_VX }, // 5363 |
24521 | | { PseudoVMACC_VX_M4_MASK, VMACC_VX }, // 5364 |
24522 | | { PseudoVMACC_VX_M8, VMACC_VX }, // 5365 |
24523 | | { PseudoVMACC_VX_M8_MASK, VMACC_VX }, // 5366 |
24524 | | { PseudoVMACC_VX_MF2, VMACC_VX }, // 5367 |
24525 | | { PseudoVMACC_VX_MF2_MASK, VMACC_VX }, // 5368 |
24526 | | { PseudoVMACC_VX_MF4, VMACC_VX }, // 5369 |
24527 | | { PseudoVMACC_VX_MF4_MASK, VMACC_VX }, // 5370 |
24528 | | { PseudoVMACC_VX_MF8, VMACC_VX }, // 5371 |
24529 | | { PseudoVMACC_VX_MF8_MASK, VMACC_VX }, // 5372 |
24530 | | { PseudoVMADC_VIM_M1, VMADC_VIM }, // 5373 |
24531 | | { PseudoVMADC_VIM_M2, VMADC_VIM }, // 5374 |
24532 | | { PseudoVMADC_VIM_M4, VMADC_VIM }, // 5375 |
24533 | | { PseudoVMADC_VIM_M8, VMADC_VIM }, // 5376 |
24534 | | { PseudoVMADC_VIM_MF2, VMADC_VIM }, // 5377 |
24535 | | { PseudoVMADC_VIM_MF4, VMADC_VIM }, // 5378 |
24536 | | { PseudoVMADC_VIM_MF8, VMADC_VIM }, // 5379 |
24537 | | { PseudoVMADC_VI_M1, VMADC_VI }, // 5380 |
24538 | | { PseudoVMADC_VI_M2, VMADC_VI }, // 5381 |
24539 | | { PseudoVMADC_VI_M4, VMADC_VI }, // 5382 |
24540 | | { PseudoVMADC_VI_M8, VMADC_VI }, // 5383 |
24541 | | { PseudoVMADC_VI_MF2, VMADC_VI }, // 5384 |
24542 | | { PseudoVMADC_VI_MF4, VMADC_VI }, // 5385 |
24543 | | { PseudoVMADC_VI_MF8, VMADC_VI }, // 5386 |
24544 | | { PseudoVMADC_VVM_M1, VMADC_VVM }, // 5387 |
24545 | | { PseudoVMADC_VVM_M2, VMADC_VVM }, // 5388 |
24546 | | { PseudoVMADC_VVM_M4, VMADC_VVM }, // 5389 |
24547 | | { PseudoVMADC_VVM_M8, VMADC_VVM }, // 5390 |
24548 | | { PseudoVMADC_VVM_MF2, VMADC_VVM }, // 5391 |
24549 | | { PseudoVMADC_VVM_MF4, VMADC_VVM }, // 5392 |
24550 | | { PseudoVMADC_VVM_MF8, VMADC_VVM }, // 5393 |
24551 | | { PseudoVMADC_VV_M1, VMADC_VV }, // 5394 |
24552 | | { PseudoVMADC_VV_M2, VMADC_VV }, // 5395 |
24553 | | { PseudoVMADC_VV_M4, VMADC_VV }, // 5396 |
24554 | | { PseudoVMADC_VV_M8, VMADC_VV }, // 5397 |
24555 | | { PseudoVMADC_VV_MF2, VMADC_VV }, // 5398 |
24556 | | { PseudoVMADC_VV_MF4, VMADC_VV }, // 5399 |
24557 | | { PseudoVMADC_VV_MF8, VMADC_VV }, // 5400 |
24558 | | { PseudoVMADC_VXM_M1, VMADC_VXM }, // 5401 |
24559 | | { PseudoVMADC_VXM_M2, VMADC_VXM }, // 5402 |
24560 | | { PseudoVMADC_VXM_M4, VMADC_VXM }, // 5403 |
24561 | | { PseudoVMADC_VXM_M8, VMADC_VXM }, // 5404 |
24562 | | { PseudoVMADC_VXM_MF2, VMADC_VXM }, // 5405 |
24563 | | { PseudoVMADC_VXM_MF4, VMADC_VXM }, // 5406 |
24564 | | { PseudoVMADC_VXM_MF8, VMADC_VXM }, // 5407 |
24565 | | { PseudoVMADC_VX_M1, VMADC_VX }, // 5408 |
24566 | | { PseudoVMADC_VX_M2, VMADC_VX }, // 5409 |
24567 | | { PseudoVMADC_VX_M4, VMADC_VX }, // 5410 |
24568 | | { PseudoVMADC_VX_M8, VMADC_VX }, // 5411 |
24569 | | { PseudoVMADC_VX_MF2, VMADC_VX }, // 5412 |
24570 | | { PseudoVMADC_VX_MF4, VMADC_VX }, // 5413 |
24571 | | { PseudoVMADC_VX_MF8, VMADC_VX }, // 5414 |
24572 | | { PseudoVMADD_VV_M1, VMADD_VV }, // 5415 |
24573 | | { PseudoVMADD_VV_M1_MASK, VMADD_VV }, // 5416 |
24574 | | { PseudoVMADD_VV_M2, VMADD_VV }, // 5417 |
24575 | | { PseudoVMADD_VV_M2_MASK, VMADD_VV }, // 5418 |
24576 | | { PseudoVMADD_VV_M4, VMADD_VV }, // 5419 |
24577 | | { PseudoVMADD_VV_M4_MASK, VMADD_VV }, // 5420 |
24578 | | { PseudoVMADD_VV_M8, VMADD_VV }, // 5421 |
24579 | | { PseudoVMADD_VV_M8_MASK, VMADD_VV }, // 5422 |
24580 | | { PseudoVMADD_VV_MF2, VMADD_VV }, // 5423 |
24581 | | { PseudoVMADD_VV_MF2_MASK, VMADD_VV }, // 5424 |
24582 | | { PseudoVMADD_VV_MF4, VMADD_VV }, // 5425 |
24583 | | { PseudoVMADD_VV_MF4_MASK, VMADD_VV }, // 5426 |
24584 | | { PseudoVMADD_VV_MF8, VMADD_VV }, // 5427 |
24585 | | { PseudoVMADD_VV_MF8_MASK, VMADD_VV }, // 5428 |
24586 | | { PseudoVMADD_VX_M1, VMADD_VX }, // 5429 |
24587 | | { PseudoVMADD_VX_M1_MASK, VMADD_VX }, // 5430 |
24588 | | { PseudoVMADD_VX_M2, VMADD_VX }, // 5431 |
24589 | | { PseudoVMADD_VX_M2_MASK, VMADD_VX }, // 5432 |
24590 | | { PseudoVMADD_VX_M4, VMADD_VX }, // 5433 |
24591 | | { PseudoVMADD_VX_M4_MASK, VMADD_VX }, // 5434 |
24592 | | { PseudoVMADD_VX_M8, VMADD_VX }, // 5435 |
24593 | | { PseudoVMADD_VX_M8_MASK, VMADD_VX }, // 5436 |
24594 | | { PseudoVMADD_VX_MF2, VMADD_VX }, // 5437 |
24595 | | { PseudoVMADD_VX_MF2_MASK, VMADD_VX }, // 5438 |
24596 | | { PseudoVMADD_VX_MF4, VMADD_VX }, // 5439 |
24597 | | { PseudoVMADD_VX_MF4_MASK, VMADD_VX }, // 5440 |
24598 | | { PseudoVMADD_VX_MF8, VMADD_VX }, // 5441 |
24599 | | { PseudoVMADD_VX_MF8_MASK, VMADD_VX }, // 5442 |
24600 | | { PseudoVMANDN_MM_M1, VMANDN_MM }, // 5443 |
24601 | | { PseudoVMANDN_MM_M2, VMANDN_MM }, // 5444 |
24602 | | { PseudoVMANDN_MM_M4, VMANDN_MM }, // 5445 |
24603 | | { PseudoVMANDN_MM_M8, VMANDN_MM }, // 5446 |
24604 | | { PseudoVMANDN_MM_MF2, VMANDN_MM }, // 5447 |
24605 | | { PseudoVMANDN_MM_MF4, VMANDN_MM }, // 5448 |
24606 | | { PseudoVMANDN_MM_MF8, VMANDN_MM }, // 5449 |
24607 | | { PseudoVMAND_MM_M1, VMAND_MM }, // 5450 |
24608 | | { PseudoVMAND_MM_M2, VMAND_MM }, // 5451 |
24609 | | { PseudoVMAND_MM_M4, VMAND_MM }, // 5452 |
24610 | | { PseudoVMAND_MM_M8, VMAND_MM }, // 5453 |
24611 | | { PseudoVMAND_MM_MF2, VMAND_MM }, // 5454 |
24612 | | { PseudoVMAND_MM_MF4, VMAND_MM }, // 5455 |
24613 | | { PseudoVMAND_MM_MF8, VMAND_MM }, // 5456 |
24614 | | { PseudoVMAXU_VV_M1, VMAXU_VV }, // 5457 |
24615 | | { PseudoVMAXU_VV_M1_MASK, VMAXU_VV }, // 5458 |
24616 | | { PseudoVMAXU_VV_M2, VMAXU_VV }, // 5459 |
24617 | | { PseudoVMAXU_VV_M2_MASK, VMAXU_VV }, // 5460 |
24618 | | { PseudoVMAXU_VV_M4, VMAXU_VV }, // 5461 |
24619 | | { PseudoVMAXU_VV_M4_MASK, VMAXU_VV }, // 5462 |
24620 | | { PseudoVMAXU_VV_M8, VMAXU_VV }, // 5463 |
24621 | | { PseudoVMAXU_VV_M8_MASK, VMAXU_VV }, // 5464 |
24622 | | { PseudoVMAXU_VV_MF2, VMAXU_VV }, // 5465 |
24623 | | { PseudoVMAXU_VV_MF2_MASK, VMAXU_VV }, // 5466 |
24624 | | { PseudoVMAXU_VV_MF4, VMAXU_VV }, // 5467 |
24625 | | { PseudoVMAXU_VV_MF4_MASK, VMAXU_VV }, // 5468 |
24626 | | { PseudoVMAXU_VV_MF8, VMAXU_VV }, // 5469 |
24627 | | { PseudoVMAXU_VV_MF8_MASK, VMAXU_VV }, // 5470 |
24628 | | { PseudoVMAXU_VX_M1, VMAXU_VX }, // 5471 |
24629 | | { PseudoVMAXU_VX_M1_MASK, VMAXU_VX }, // 5472 |
24630 | | { PseudoVMAXU_VX_M2, VMAXU_VX }, // 5473 |
24631 | | { PseudoVMAXU_VX_M2_MASK, VMAXU_VX }, // 5474 |
24632 | | { PseudoVMAXU_VX_M4, VMAXU_VX }, // 5475 |
24633 | | { PseudoVMAXU_VX_M4_MASK, VMAXU_VX }, // 5476 |
24634 | | { PseudoVMAXU_VX_M8, VMAXU_VX }, // 5477 |
24635 | | { PseudoVMAXU_VX_M8_MASK, VMAXU_VX }, // 5478 |
24636 | | { PseudoVMAXU_VX_MF2, VMAXU_VX }, // 5479 |
24637 | | { PseudoVMAXU_VX_MF2_MASK, VMAXU_VX }, // 5480 |
24638 | | { PseudoVMAXU_VX_MF4, VMAXU_VX }, // 5481 |
24639 | | { PseudoVMAXU_VX_MF4_MASK, VMAXU_VX }, // 5482 |
24640 | | { PseudoVMAXU_VX_MF8, VMAXU_VX }, // 5483 |
24641 | | { PseudoVMAXU_VX_MF8_MASK, VMAXU_VX }, // 5484 |
24642 | | { PseudoVMAX_VV_M1, VMAX_VV }, // 5485 |
24643 | | { PseudoVMAX_VV_M1_MASK, VMAX_VV }, // 5486 |
24644 | | { PseudoVMAX_VV_M2, VMAX_VV }, // 5487 |
24645 | | { PseudoVMAX_VV_M2_MASK, VMAX_VV }, // 5488 |
24646 | | { PseudoVMAX_VV_M4, VMAX_VV }, // 5489 |
24647 | | { PseudoVMAX_VV_M4_MASK, VMAX_VV }, // 5490 |
24648 | | { PseudoVMAX_VV_M8, VMAX_VV }, // 5491 |
24649 | | { PseudoVMAX_VV_M8_MASK, VMAX_VV }, // 5492 |
24650 | | { PseudoVMAX_VV_MF2, VMAX_VV }, // 5493 |
24651 | | { PseudoVMAX_VV_MF2_MASK, VMAX_VV }, // 5494 |
24652 | | { PseudoVMAX_VV_MF4, VMAX_VV }, // 5495 |
24653 | | { PseudoVMAX_VV_MF4_MASK, VMAX_VV }, // 5496 |
24654 | | { PseudoVMAX_VV_MF8, VMAX_VV }, // 5497 |
24655 | | { PseudoVMAX_VV_MF8_MASK, VMAX_VV }, // 5498 |
24656 | | { PseudoVMAX_VX_M1, VMAX_VX }, // 5499 |
24657 | | { PseudoVMAX_VX_M1_MASK, VMAX_VX }, // 5500 |
24658 | | { PseudoVMAX_VX_M2, VMAX_VX }, // 5501 |
24659 | | { PseudoVMAX_VX_M2_MASK, VMAX_VX }, // 5502 |
24660 | | { PseudoVMAX_VX_M4, VMAX_VX }, // 5503 |
24661 | | { PseudoVMAX_VX_M4_MASK, VMAX_VX }, // 5504 |
24662 | | { PseudoVMAX_VX_M8, VMAX_VX }, // 5505 |
24663 | | { PseudoVMAX_VX_M8_MASK, VMAX_VX }, // 5506 |
24664 | | { PseudoVMAX_VX_MF2, VMAX_VX }, // 5507 |
24665 | | { PseudoVMAX_VX_MF2_MASK, VMAX_VX }, // 5508 |
24666 | | { PseudoVMAX_VX_MF4, VMAX_VX }, // 5509 |
24667 | | { PseudoVMAX_VX_MF4_MASK, VMAX_VX }, // 5510 |
24668 | | { PseudoVMAX_VX_MF8, VMAX_VX }, // 5511 |
24669 | | { PseudoVMAX_VX_MF8_MASK, VMAX_VX }, // 5512 |
24670 | | { PseudoVMERGE_VIM_M1, VMERGE_VIM }, // 5513 |
24671 | | { PseudoVMERGE_VIM_M2, VMERGE_VIM }, // 5514 |
24672 | | { PseudoVMERGE_VIM_M4, VMERGE_VIM }, // 5515 |
24673 | | { PseudoVMERGE_VIM_M8, VMERGE_VIM }, // 5516 |
24674 | | { PseudoVMERGE_VIM_MF2, VMERGE_VIM }, // 5517 |
24675 | | { PseudoVMERGE_VIM_MF4, VMERGE_VIM }, // 5518 |
24676 | | { PseudoVMERGE_VIM_MF8, VMERGE_VIM }, // 5519 |
24677 | | { PseudoVMERGE_VVM_M1, VMERGE_VVM }, // 5520 |
24678 | | { PseudoVMERGE_VVM_M2, VMERGE_VVM }, // 5521 |
24679 | | { PseudoVMERGE_VVM_M4, VMERGE_VVM }, // 5522 |
24680 | | { PseudoVMERGE_VVM_M8, VMERGE_VVM }, // 5523 |
24681 | | { PseudoVMERGE_VVM_MF2, VMERGE_VVM }, // 5524 |
24682 | | { PseudoVMERGE_VVM_MF4, VMERGE_VVM }, // 5525 |
24683 | | { PseudoVMERGE_VVM_MF8, VMERGE_VVM }, // 5526 |
24684 | | { PseudoVMERGE_VXM_M1, VMERGE_VXM }, // 5527 |
24685 | | { PseudoVMERGE_VXM_M2, VMERGE_VXM }, // 5528 |
24686 | | { PseudoVMERGE_VXM_M4, VMERGE_VXM }, // 5529 |
24687 | | { PseudoVMERGE_VXM_M8, VMERGE_VXM }, // 5530 |
24688 | | { PseudoVMERGE_VXM_MF2, VMERGE_VXM }, // 5531 |
24689 | | { PseudoVMERGE_VXM_MF4, VMERGE_VXM }, // 5532 |
24690 | | { PseudoVMERGE_VXM_MF8, VMERGE_VXM }, // 5533 |
24691 | | { PseudoVMFEQ_VFPR16_M1, VMFEQ_VF }, // 5534 |
24692 | | { PseudoVMFEQ_VFPR16_M1_MASK, VMFEQ_VF }, // 5535 |
24693 | | { PseudoVMFEQ_VFPR16_M2, VMFEQ_VF }, // 5536 |
24694 | | { PseudoVMFEQ_VFPR16_M2_MASK, VMFEQ_VF }, // 5537 |
24695 | | { PseudoVMFEQ_VFPR16_M4, VMFEQ_VF }, // 5538 |
24696 | | { PseudoVMFEQ_VFPR16_M4_MASK, VMFEQ_VF }, // 5539 |
24697 | | { PseudoVMFEQ_VFPR16_M8, VMFEQ_VF }, // 5540 |
24698 | | { PseudoVMFEQ_VFPR16_M8_MASK, VMFEQ_VF }, // 5541 |
24699 | | { PseudoVMFEQ_VFPR16_MF2, VMFEQ_VF }, // 5542 |
24700 | | { PseudoVMFEQ_VFPR16_MF2_MASK, VMFEQ_VF }, // 5543 |
24701 | | { PseudoVMFEQ_VFPR16_MF4, VMFEQ_VF }, // 5544 |
24702 | | { PseudoVMFEQ_VFPR16_MF4_MASK, VMFEQ_VF }, // 5545 |
24703 | | { PseudoVMFEQ_VFPR32_M1, VMFEQ_VF }, // 5546 |
24704 | | { PseudoVMFEQ_VFPR32_M1_MASK, VMFEQ_VF }, // 5547 |
24705 | | { PseudoVMFEQ_VFPR32_M2, VMFEQ_VF }, // 5548 |
24706 | | { PseudoVMFEQ_VFPR32_M2_MASK, VMFEQ_VF }, // 5549 |
24707 | | { PseudoVMFEQ_VFPR32_M4, VMFEQ_VF }, // 5550 |
24708 | | { PseudoVMFEQ_VFPR32_M4_MASK, VMFEQ_VF }, // 5551 |
24709 | | { PseudoVMFEQ_VFPR32_M8, VMFEQ_VF }, // 5552 |
24710 | | { PseudoVMFEQ_VFPR32_M8_MASK, VMFEQ_VF }, // 5553 |
24711 | | { PseudoVMFEQ_VFPR32_MF2, VMFEQ_VF }, // 5554 |
24712 | | { PseudoVMFEQ_VFPR32_MF2_MASK, VMFEQ_VF }, // 5555 |
24713 | | { PseudoVMFEQ_VFPR64_M1, VMFEQ_VF }, // 5556 |
24714 | | { PseudoVMFEQ_VFPR64_M1_MASK, VMFEQ_VF }, // 5557 |
24715 | | { PseudoVMFEQ_VFPR64_M2, VMFEQ_VF }, // 5558 |
24716 | | { PseudoVMFEQ_VFPR64_M2_MASK, VMFEQ_VF }, // 5559 |
24717 | | { PseudoVMFEQ_VFPR64_M4, VMFEQ_VF }, // 5560 |
24718 | | { PseudoVMFEQ_VFPR64_M4_MASK, VMFEQ_VF }, // 5561 |
24719 | | { PseudoVMFEQ_VFPR64_M8, VMFEQ_VF }, // 5562 |
24720 | | { PseudoVMFEQ_VFPR64_M8_MASK, VMFEQ_VF }, // 5563 |
24721 | | { PseudoVMFEQ_VV_M1, VMFEQ_VV }, // 5564 |
24722 | | { PseudoVMFEQ_VV_M1_MASK, VMFEQ_VV }, // 5565 |
24723 | | { PseudoVMFEQ_VV_M2, VMFEQ_VV }, // 5566 |
24724 | | { PseudoVMFEQ_VV_M2_MASK, VMFEQ_VV }, // 5567 |
24725 | | { PseudoVMFEQ_VV_M4, VMFEQ_VV }, // 5568 |
24726 | | { PseudoVMFEQ_VV_M4_MASK, VMFEQ_VV }, // 5569 |
24727 | | { PseudoVMFEQ_VV_M8, VMFEQ_VV }, // 5570 |
24728 | | { PseudoVMFEQ_VV_M8_MASK, VMFEQ_VV }, // 5571 |
24729 | | { PseudoVMFEQ_VV_MF2, VMFEQ_VV }, // 5572 |
24730 | | { PseudoVMFEQ_VV_MF2_MASK, VMFEQ_VV }, // 5573 |
24731 | | { PseudoVMFEQ_VV_MF4, VMFEQ_VV }, // 5574 |
24732 | | { PseudoVMFEQ_VV_MF4_MASK, VMFEQ_VV }, // 5575 |
24733 | | { PseudoVMFGE_VFPR16_M1, VMFGE_VF }, // 5576 |
24734 | | { PseudoVMFGE_VFPR16_M1_MASK, VMFGE_VF }, // 5577 |
24735 | | { PseudoVMFGE_VFPR16_M2, VMFGE_VF }, // 5578 |
24736 | | { PseudoVMFGE_VFPR16_M2_MASK, VMFGE_VF }, // 5579 |
24737 | | { PseudoVMFGE_VFPR16_M4, VMFGE_VF }, // 5580 |
24738 | | { PseudoVMFGE_VFPR16_M4_MASK, VMFGE_VF }, // 5581 |
24739 | | { PseudoVMFGE_VFPR16_M8, VMFGE_VF }, // 5582 |
24740 | | { PseudoVMFGE_VFPR16_M8_MASK, VMFGE_VF }, // 5583 |
24741 | | { PseudoVMFGE_VFPR16_MF2, VMFGE_VF }, // 5584 |
24742 | | { PseudoVMFGE_VFPR16_MF2_MASK, VMFGE_VF }, // 5585 |
24743 | | { PseudoVMFGE_VFPR16_MF4, VMFGE_VF }, // 5586 |
24744 | | { PseudoVMFGE_VFPR16_MF4_MASK, VMFGE_VF }, // 5587 |
24745 | | { PseudoVMFGE_VFPR32_M1, VMFGE_VF }, // 5588 |
24746 | | { PseudoVMFGE_VFPR32_M1_MASK, VMFGE_VF }, // 5589 |
24747 | | { PseudoVMFGE_VFPR32_M2, VMFGE_VF }, // 5590 |
24748 | | { PseudoVMFGE_VFPR32_M2_MASK, VMFGE_VF }, // 5591 |
24749 | | { PseudoVMFGE_VFPR32_M4, VMFGE_VF }, // 5592 |
24750 | | { PseudoVMFGE_VFPR32_M4_MASK, VMFGE_VF }, // 5593 |
24751 | | { PseudoVMFGE_VFPR32_M8, VMFGE_VF }, // 5594 |
24752 | | { PseudoVMFGE_VFPR32_M8_MASK, VMFGE_VF }, // 5595 |
24753 | | { PseudoVMFGE_VFPR32_MF2, VMFGE_VF }, // 5596 |
24754 | | { PseudoVMFGE_VFPR32_MF2_MASK, VMFGE_VF }, // 5597 |
24755 | | { PseudoVMFGE_VFPR64_M1, VMFGE_VF }, // 5598 |
24756 | | { PseudoVMFGE_VFPR64_M1_MASK, VMFGE_VF }, // 5599 |
24757 | | { PseudoVMFGE_VFPR64_M2, VMFGE_VF }, // 5600 |
24758 | | { PseudoVMFGE_VFPR64_M2_MASK, VMFGE_VF }, // 5601 |
24759 | | { PseudoVMFGE_VFPR64_M4, VMFGE_VF }, // 5602 |
24760 | | { PseudoVMFGE_VFPR64_M4_MASK, VMFGE_VF }, // 5603 |
24761 | | { PseudoVMFGE_VFPR64_M8, VMFGE_VF }, // 5604 |
24762 | | { PseudoVMFGE_VFPR64_M8_MASK, VMFGE_VF }, // 5605 |
24763 | | { PseudoVMFGT_VFPR16_M1, VMFGT_VF }, // 5606 |
24764 | | { PseudoVMFGT_VFPR16_M1_MASK, VMFGT_VF }, // 5607 |
24765 | | { PseudoVMFGT_VFPR16_M2, VMFGT_VF }, // 5608 |
24766 | | { PseudoVMFGT_VFPR16_M2_MASK, VMFGT_VF }, // 5609 |
24767 | | { PseudoVMFGT_VFPR16_M4, VMFGT_VF }, // 5610 |
24768 | | { PseudoVMFGT_VFPR16_M4_MASK, VMFGT_VF }, // 5611 |
24769 | | { PseudoVMFGT_VFPR16_M8, VMFGT_VF }, // 5612 |
24770 | | { PseudoVMFGT_VFPR16_M8_MASK, VMFGT_VF }, // 5613 |
24771 | | { PseudoVMFGT_VFPR16_MF2, VMFGT_VF }, // 5614 |
24772 | | { PseudoVMFGT_VFPR16_MF2_MASK, VMFGT_VF }, // 5615 |
24773 | | { PseudoVMFGT_VFPR16_MF4, VMFGT_VF }, // 5616 |
24774 | | { PseudoVMFGT_VFPR16_MF4_MASK, VMFGT_VF }, // 5617 |
24775 | | { PseudoVMFGT_VFPR32_M1, VMFGT_VF }, // 5618 |
24776 | | { PseudoVMFGT_VFPR32_M1_MASK, VMFGT_VF }, // 5619 |
24777 | | { PseudoVMFGT_VFPR32_M2, VMFGT_VF }, // 5620 |
24778 | | { PseudoVMFGT_VFPR32_M2_MASK, VMFGT_VF }, // 5621 |
24779 | | { PseudoVMFGT_VFPR32_M4, VMFGT_VF }, // 5622 |
24780 | | { PseudoVMFGT_VFPR32_M4_MASK, VMFGT_VF }, // 5623 |
24781 | | { PseudoVMFGT_VFPR32_M8, VMFGT_VF }, // 5624 |
24782 | | { PseudoVMFGT_VFPR32_M8_MASK, VMFGT_VF }, // 5625 |
24783 | | { PseudoVMFGT_VFPR32_MF2, VMFGT_VF }, // 5626 |
24784 | | { PseudoVMFGT_VFPR32_MF2_MASK, VMFGT_VF }, // 5627 |
24785 | | { PseudoVMFGT_VFPR64_M1, VMFGT_VF }, // 5628 |
24786 | | { PseudoVMFGT_VFPR64_M1_MASK, VMFGT_VF }, // 5629 |
24787 | | { PseudoVMFGT_VFPR64_M2, VMFGT_VF }, // 5630 |
24788 | | { PseudoVMFGT_VFPR64_M2_MASK, VMFGT_VF }, // 5631 |
24789 | | { PseudoVMFGT_VFPR64_M4, VMFGT_VF }, // 5632 |
24790 | | { PseudoVMFGT_VFPR64_M4_MASK, VMFGT_VF }, // 5633 |
24791 | | { PseudoVMFGT_VFPR64_M8, VMFGT_VF }, // 5634 |
24792 | | { PseudoVMFGT_VFPR64_M8_MASK, VMFGT_VF }, // 5635 |
24793 | | { PseudoVMFLE_VFPR16_M1, VMFLE_VF }, // 5636 |
24794 | | { PseudoVMFLE_VFPR16_M1_MASK, VMFLE_VF }, // 5637 |
24795 | | { PseudoVMFLE_VFPR16_M2, VMFLE_VF }, // 5638 |
24796 | | { PseudoVMFLE_VFPR16_M2_MASK, VMFLE_VF }, // 5639 |
24797 | | { PseudoVMFLE_VFPR16_M4, VMFLE_VF }, // 5640 |
24798 | | { PseudoVMFLE_VFPR16_M4_MASK, VMFLE_VF }, // 5641 |
24799 | | { PseudoVMFLE_VFPR16_M8, VMFLE_VF }, // 5642 |
24800 | | { PseudoVMFLE_VFPR16_M8_MASK, VMFLE_VF }, // 5643 |
24801 | | { PseudoVMFLE_VFPR16_MF2, VMFLE_VF }, // 5644 |
24802 | | { PseudoVMFLE_VFPR16_MF2_MASK, VMFLE_VF }, // 5645 |
24803 | | { PseudoVMFLE_VFPR16_MF4, VMFLE_VF }, // 5646 |
24804 | | { PseudoVMFLE_VFPR16_MF4_MASK, VMFLE_VF }, // 5647 |
24805 | | { PseudoVMFLE_VFPR32_M1, VMFLE_VF }, // 5648 |
24806 | | { PseudoVMFLE_VFPR32_M1_MASK, VMFLE_VF }, // 5649 |
24807 | | { PseudoVMFLE_VFPR32_M2, VMFLE_VF }, // 5650 |
24808 | | { PseudoVMFLE_VFPR32_M2_MASK, VMFLE_VF }, // 5651 |
24809 | | { PseudoVMFLE_VFPR32_M4, VMFLE_VF }, // 5652 |
24810 | | { PseudoVMFLE_VFPR32_M4_MASK, VMFLE_VF }, // 5653 |
24811 | | { PseudoVMFLE_VFPR32_M8, VMFLE_VF }, // 5654 |
24812 | | { PseudoVMFLE_VFPR32_M8_MASK, VMFLE_VF }, // 5655 |
24813 | | { PseudoVMFLE_VFPR32_MF2, VMFLE_VF }, // 5656 |
24814 | | { PseudoVMFLE_VFPR32_MF2_MASK, VMFLE_VF }, // 5657 |
24815 | | { PseudoVMFLE_VFPR64_M1, VMFLE_VF }, // 5658 |
24816 | | { PseudoVMFLE_VFPR64_M1_MASK, VMFLE_VF }, // 5659 |
24817 | | { PseudoVMFLE_VFPR64_M2, VMFLE_VF }, // 5660 |
24818 | | { PseudoVMFLE_VFPR64_M2_MASK, VMFLE_VF }, // 5661 |
24819 | | { PseudoVMFLE_VFPR64_M4, VMFLE_VF }, // 5662 |
24820 | | { PseudoVMFLE_VFPR64_M4_MASK, VMFLE_VF }, // 5663 |
24821 | | { PseudoVMFLE_VFPR64_M8, VMFLE_VF }, // 5664 |
24822 | | { PseudoVMFLE_VFPR64_M8_MASK, VMFLE_VF }, // 5665 |
24823 | | { PseudoVMFLE_VV_M1, VMFLE_VV }, // 5666 |
24824 | | { PseudoVMFLE_VV_M1_MASK, VMFLE_VV }, // 5667 |
24825 | | { PseudoVMFLE_VV_M2, VMFLE_VV }, // 5668 |
24826 | | { PseudoVMFLE_VV_M2_MASK, VMFLE_VV }, // 5669 |
24827 | | { PseudoVMFLE_VV_M4, VMFLE_VV }, // 5670 |
24828 | | { PseudoVMFLE_VV_M4_MASK, VMFLE_VV }, // 5671 |
24829 | | { PseudoVMFLE_VV_M8, VMFLE_VV }, // 5672 |
24830 | | { PseudoVMFLE_VV_M8_MASK, VMFLE_VV }, // 5673 |
24831 | | { PseudoVMFLE_VV_MF2, VMFLE_VV }, // 5674 |
24832 | | { PseudoVMFLE_VV_MF2_MASK, VMFLE_VV }, // 5675 |
24833 | | { PseudoVMFLE_VV_MF4, VMFLE_VV }, // 5676 |
24834 | | { PseudoVMFLE_VV_MF4_MASK, VMFLE_VV }, // 5677 |
24835 | | { PseudoVMFLT_VFPR16_M1, VMFLT_VF }, // 5678 |
24836 | | { PseudoVMFLT_VFPR16_M1_MASK, VMFLT_VF }, // 5679 |
24837 | | { PseudoVMFLT_VFPR16_M2, VMFLT_VF }, // 5680 |
24838 | | { PseudoVMFLT_VFPR16_M2_MASK, VMFLT_VF }, // 5681 |
24839 | | { PseudoVMFLT_VFPR16_M4, VMFLT_VF }, // 5682 |
24840 | | { PseudoVMFLT_VFPR16_M4_MASK, VMFLT_VF }, // 5683 |
24841 | | { PseudoVMFLT_VFPR16_M8, VMFLT_VF }, // 5684 |
24842 | | { PseudoVMFLT_VFPR16_M8_MASK, VMFLT_VF }, // 5685 |
24843 | | { PseudoVMFLT_VFPR16_MF2, VMFLT_VF }, // 5686 |
24844 | | { PseudoVMFLT_VFPR16_MF2_MASK, VMFLT_VF }, // 5687 |
24845 | | { PseudoVMFLT_VFPR16_MF4, VMFLT_VF }, // 5688 |
24846 | | { PseudoVMFLT_VFPR16_MF4_MASK, VMFLT_VF }, // 5689 |
24847 | | { PseudoVMFLT_VFPR32_M1, VMFLT_VF }, // 5690 |
24848 | | { PseudoVMFLT_VFPR32_M1_MASK, VMFLT_VF }, // 5691 |
24849 | | { PseudoVMFLT_VFPR32_M2, VMFLT_VF }, // 5692 |
24850 | | { PseudoVMFLT_VFPR32_M2_MASK, VMFLT_VF }, // 5693 |
24851 | | { PseudoVMFLT_VFPR32_M4, VMFLT_VF }, // 5694 |
24852 | | { PseudoVMFLT_VFPR32_M4_MASK, VMFLT_VF }, // 5695 |
24853 | | { PseudoVMFLT_VFPR32_M8, VMFLT_VF }, // 5696 |
24854 | | { PseudoVMFLT_VFPR32_M8_MASK, VMFLT_VF }, // 5697 |
24855 | | { PseudoVMFLT_VFPR32_MF2, VMFLT_VF }, // 5698 |
24856 | | { PseudoVMFLT_VFPR32_MF2_MASK, VMFLT_VF }, // 5699 |
24857 | | { PseudoVMFLT_VFPR64_M1, VMFLT_VF }, // 5700 |
24858 | | { PseudoVMFLT_VFPR64_M1_MASK, VMFLT_VF }, // 5701 |
24859 | | { PseudoVMFLT_VFPR64_M2, VMFLT_VF }, // 5702 |
24860 | | { PseudoVMFLT_VFPR64_M2_MASK, VMFLT_VF }, // 5703 |
24861 | | { PseudoVMFLT_VFPR64_M4, VMFLT_VF }, // 5704 |
24862 | | { PseudoVMFLT_VFPR64_M4_MASK, VMFLT_VF }, // 5705 |
24863 | | { PseudoVMFLT_VFPR64_M8, VMFLT_VF }, // 5706 |
24864 | | { PseudoVMFLT_VFPR64_M8_MASK, VMFLT_VF }, // 5707 |
24865 | | { PseudoVMFLT_VV_M1, VMFLT_VV }, // 5708 |
24866 | | { PseudoVMFLT_VV_M1_MASK, VMFLT_VV }, // 5709 |
24867 | | { PseudoVMFLT_VV_M2, VMFLT_VV }, // 5710 |
24868 | | { PseudoVMFLT_VV_M2_MASK, VMFLT_VV }, // 5711 |
24869 | | { PseudoVMFLT_VV_M4, VMFLT_VV }, // 5712 |
24870 | | { PseudoVMFLT_VV_M4_MASK, VMFLT_VV }, // 5713 |
24871 | | { PseudoVMFLT_VV_M8, VMFLT_VV }, // 5714 |
24872 | | { PseudoVMFLT_VV_M8_MASK, VMFLT_VV }, // 5715 |
24873 | | { PseudoVMFLT_VV_MF2, VMFLT_VV }, // 5716 |
24874 | | { PseudoVMFLT_VV_MF2_MASK, VMFLT_VV }, // 5717 |
24875 | | { PseudoVMFLT_VV_MF4, VMFLT_VV }, // 5718 |
24876 | | { PseudoVMFLT_VV_MF4_MASK, VMFLT_VV }, // 5719 |
24877 | | { PseudoVMFNE_VFPR16_M1, VMFNE_VF }, // 5720 |
24878 | | { PseudoVMFNE_VFPR16_M1_MASK, VMFNE_VF }, // 5721 |
24879 | | { PseudoVMFNE_VFPR16_M2, VMFNE_VF }, // 5722 |
24880 | | { PseudoVMFNE_VFPR16_M2_MASK, VMFNE_VF }, // 5723 |
24881 | | { PseudoVMFNE_VFPR16_M4, VMFNE_VF }, // 5724 |
24882 | | { PseudoVMFNE_VFPR16_M4_MASK, VMFNE_VF }, // 5725 |
24883 | | { PseudoVMFNE_VFPR16_M8, VMFNE_VF }, // 5726 |
24884 | | { PseudoVMFNE_VFPR16_M8_MASK, VMFNE_VF }, // 5727 |
24885 | | { PseudoVMFNE_VFPR16_MF2, VMFNE_VF }, // 5728 |
24886 | | { PseudoVMFNE_VFPR16_MF2_MASK, VMFNE_VF }, // 5729 |
24887 | | { PseudoVMFNE_VFPR16_MF4, VMFNE_VF }, // 5730 |
24888 | | { PseudoVMFNE_VFPR16_MF4_MASK, VMFNE_VF }, // 5731 |
24889 | | { PseudoVMFNE_VFPR32_M1, VMFNE_VF }, // 5732 |
24890 | | { PseudoVMFNE_VFPR32_M1_MASK, VMFNE_VF }, // 5733 |
24891 | | { PseudoVMFNE_VFPR32_M2, VMFNE_VF }, // 5734 |
24892 | | { PseudoVMFNE_VFPR32_M2_MASK, VMFNE_VF }, // 5735 |
24893 | | { PseudoVMFNE_VFPR32_M4, VMFNE_VF }, // 5736 |
24894 | | { PseudoVMFNE_VFPR32_M4_MASK, VMFNE_VF }, // 5737 |
24895 | | { PseudoVMFNE_VFPR32_M8, VMFNE_VF }, // 5738 |
24896 | | { PseudoVMFNE_VFPR32_M8_MASK, VMFNE_VF }, // 5739 |
24897 | | { PseudoVMFNE_VFPR32_MF2, VMFNE_VF }, // 5740 |
24898 | | { PseudoVMFNE_VFPR32_MF2_MASK, VMFNE_VF }, // 5741 |
24899 | | { PseudoVMFNE_VFPR64_M1, VMFNE_VF }, // 5742 |
24900 | | { PseudoVMFNE_VFPR64_M1_MASK, VMFNE_VF }, // 5743 |
24901 | | { PseudoVMFNE_VFPR64_M2, VMFNE_VF }, // 5744 |
24902 | | { PseudoVMFNE_VFPR64_M2_MASK, VMFNE_VF }, // 5745 |
24903 | | { PseudoVMFNE_VFPR64_M4, VMFNE_VF }, // 5746 |
24904 | | { PseudoVMFNE_VFPR64_M4_MASK, VMFNE_VF }, // 5747 |
24905 | | { PseudoVMFNE_VFPR64_M8, VMFNE_VF }, // 5748 |
24906 | | { PseudoVMFNE_VFPR64_M8_MASK, VMFNE_VF }, // 5749 |
24907 | | { PseudoVMFNE_VV_M1, VMFNE_VV }, // 5750 |
24908 | | { PseudoVMFNE_VV_M1_MASK, VMFNE_VV }, // 5751 |
24909 | | { PseudoVMFNE_VV_M2, VMFNE_VV }, // 5752 |
24910 | | { PseudoVMFNE_VV_M2_MASK, VMFNE_VV }, // 5753 |
24911 | | { PseudoVMFNE_VV_M4, VMFNE_VV }, // 5754 |
24912 | | { PseudoVMFNE_VV_M4_MASK, VMFNE_VV }, // 5755 |
24913 | | { PseudoVMFNE_VV_M8, VMFNE_VV }, // 5756 |
24914 | | { PseudoVMFNE_VV_M8_MASK, VMFNE_VV }, // 5757 |
24915 | | { PseudoVMFNE_VV_MF2, VMFNE_VV }, // 5758 |
24916 | | { PseudoVMFNE_VV_MF2_MASK, VMFNE_VV }, // 5759 |
24917 | | { PseudoVMFNE_VV_MF4, VMFNE_VV }, // 5760 |
24918 | | { PseudoVMFNE_VV_MF4_MASK, VMFNE_VV }, // 5761 |
24919 | | { PseudoVMINU_VV_M1, VMINU_VV }, // 5762 |
24920 | | { PseudoVMINU_VV_M1_MASK, VMINU_VV }, // 5763 |
24921 | | { PseudoVMINU_VV_M2, VMINU_VV }, // 5764 |
24922 | | { PseudoVMINU_VV_M2_MASK, VMINU_VV }, // 5765 |
24923 | | { PseudoVMINU_VV_M4, VMINU_VV }, // 5766 |
24924 | | { PseudoVMINU_VV_M4_MASK, VMINU_VV }, // 5767 |
24925 | | { PseudoVMINU_VV_M8, VMINU_VV }, // 5768 |
24926 | | { PseudoVMINU_VV_M8_MASK, VMINU_VV }, // 5769 |
24927 | | { PseudoVMINU_VV_MF2, VMINU_VV }, // 5770 |
24928 | | { PseudoVMINU_VV_MF2_MASK, VMINU_VV }, // 5771 |
24929 | | { PseudoVMINU_VV_MF4, VMINU_VV }, // 5772 |
24930 | | { PseudoVMINU_VV_MF4_MASK, VMINU_VV }, // 5773 |
24931 | | { PseudoVMINU_VV_MF8, VMINU_VV }, // 5774 |
24932 | | { PseudoVMINU_VV_MF8_MASK, VMINU_VV }, // 5775 |
24933 | | { PseudoVMINU_VX_M1, VMINU_VX }, // 5776 |
24934 | | { PseudoVMINU_VX_M1_MASK, VMINU_VX }, // 5777 |
24935 | | { PseudoVMINU_VX_M2, VMINU_VX }, // 5778 |
24936 | | { PseudoVMINU_VX_M2_MASK, VMINU_VX }, // 5779 |
24937 | | { PseudoVMINU_VX_M4, VMINU_VX }, // 5780 |
24938 | | { PseudoVMINU_VX_M4_MASK, VMINU_VX }, // 5781 |
24939 | | { PseudoVMINU_VX_M8, VMINU_VX }, // 5782 |
24940 | | { PseudoVMINU_VX_M8_MASK, VMINU_VX }, // 5783 |
24941 | | { PseudoVMINU_VX_MF2, VMINU_VX }, // 5784 |
24942 | | { PseudoVMINU_VX_MF2_MASK, VMINU_VX }, // 5785 |
24943 | | { PseudoVMINU_VX_MF4, VMINU_VX }, // 5786 |
24944 | | { PseudoVMINU_VX_MF4_MASK, VMINU_VX }, // 5787 |
24945 | | { PseudoVMINU_VX_MF8, VMINU_VX }, // 5788 |
24946 | | { PseudoVMINU_VX_MF8_MASK, VMINU_VX }, // 5789 |
24947 | | { PseudoVMIN_VV_M1, VMIN_VV }, // 5790 |
24948 | | { PseudoVMIN_VV_M1_MASK, VMIN_VV }, // 5791 |
24949 | | { PseudoVMIN_VV_M2, VMIN_VV }, // 5792 |
24950 | | { PseudoVMIN_VV_M2_MASK, VMIN_VV }, // 5793 |
24951 | | { PseudoVMIN_VV_M4, VMIN_VV }, // 5794 |
24952 | | { PseudoVMIN_VV_M4_MASK, VMIN_VV }, // 5795 |
24953 | | { PseudoVMIN_VV_M8, VMIN_VV }, // 5796 |
24954 | | { PseudoVMIN_VV_M8_MASK, VMIN_VV }, // 5797 |
24955 | | { PseudoVMIN_VV_MF2, VMIN_VV }, // 5798 |
24956 | | { PseudoVMIN_VV_MF2_MASK, VMIN_VV }, // 5799 |
24957 | | { PseudoVMIN_VV_MF4, VMIN_VV }, // 5800 |
24958 | | { PseudoVMIN_VV_MF4_MASK, VMIN_VV }, // 5801 |
24959 | | { PseudoVMIN_VV_MF8, VMIN_VV }, // 5802 |
24960 | | { PseudoVMIN_VV_MF8_MASK, VMIN_VV }, // 5803 |
24961 | | { PseudoVMIN_VX_M1, VMIN_VX }, // 5804 |
24962 | | { PseudoVMIN_VX_M1_MASK, VMIN_VX }, // 5805 |
24963 | | { PseudoVMIN_VX_M2, VMIN_VX }, // 5806 |
24964 | | { PseudoVMIN_VX_M2_MASK, VMIN_VX }, // 5807 |
24965 | | { PseudoVMIN_VX_M4, VMIN_VX }, // 5808 |
24966 | | { PseudoVMIN_VX_M4_MASK, VMIN_VX }, // 5809 |
24967 | | { PseudoVMIN_VX_M8, VMIN_VX }, // 5810 |
24968 | | { PseudoVMIN_VX_M8_MASK, VMIN_VX }, // 5811 |
24969 | | { PseudoVMIN_VX_MF2, VMIN_VX }, // 5812 |
24970 | | { PseudoVMIN_VX_MF2_MASK, VMIN_VX }, // 5813 |
24971 | | { PseudoVMIN_VX_MF4, VMIN_VX }, // 5814 |
24972 | | { PseudoVMIN_VX_MF4_MASK, VMIN_VX }, // 5815 |
24973 | | { PseudoVMIN_VX_MF8, VMIN_VX }, // 5816 |
24974 | | { PseudoVMIN_VX_MF8_MASK, VMIN_VX }, // 5817 |
24975 | | { PseudoVMNAND_MM_M1, VMNAND_MM }, // 5818 |
24976 | | { PseudoVMNAND_MM_M2, VMNAND_MM }, // 5819 |
24977 | | { PseudoVMNAND_MM_M4, VMNAND_MM }, // 5820 |
24978 | | { PseudoVMNAND_MM_M8, VMNAND_MM }, // 5821 |
24979 | | { PseudoVMNAND_MM_MF2, VMNAND_MM }, // 5822 |
24980 | | { PseudoVMNAND_MM_MF4, VMNAND_MM }, // 5823 |
24981 | | { PseudoVMNAND_MM_MF8, VMNAND_MM }, // 5824 |
24982 | | { PseudoVMNOR_MM_M1, VMNOR_MM }, // 5825 |
24983 | | { PseudoVMNOR_MM_M2, VMNOR_MM }, // 5826 |
24984 | | { PseudoVMNOR_MM_M4, VMNOR_MM }, // 5827 |
24985 | | { PseudoVMNOR_MM_M8, VMNOR_MM }, // 5828 |
24986 | | { PseudoVMNOR_MM_MF2, VMNOR_MM }, // 5829 |
24987 | | { PseudoVMNOR_MM_MF4, VMNOR_MM }, // 5830 |
24988 | | { PseudoVMNOR_MM_MF8, VMNOR_MM }, // 5831 |
24989 | | { PseudoVMORN_MM_M1, VMORN_MM }, // 5832 |
24990 | | { PseudoVMORN_MM_M2, VMORN_MM }, // 5833 |
24991 | | { PseudoVMORN_MM_M4, VMORN_MM }, // 5834 |
24992 | | { PseudoVMORN_MM_M8, VMORN_MM }, // 5835 |
24993 | | { PseudoVMORN_MM_MF2, VMORN_MM }, // 5836 |
24994 | | { PseudoVMORN_MM_MF4, VMORN_MM }, // 5837 |
24995 | | { PseudoVMORN_MM_MF8, VMORN_MM }, // 5838 |
24996 | | { PseudoVMOR_MM_M1, VMOR_MM }, // 5839 |
24997 | | { PseudoVMOR_MM_M2, VMOR_MM }, // 5840 |
24998 | | { PseudoVMOR_MM_M4, VMOR_MM }, // 5841 |
24999 | | { PseudoVMOR_MM_M8, VMOR_MM }, // 5842 |
25000 | | { PseudoVMOR_MM_MF2, VMOR_MM }, // 5843 |
25001 | | { PseudoVMOR_MM_MF4, VMOR_MM }, // 5844 |
25002 | | { PseudoVMOR_MM_MF8, VMOR_MM }, // 5845 |
25003 | | { PseudoVMSBC_VVM_M1, VMSBC_VVM }, // 5846 |
25004 | | { PseudoVMSBC_VVM_M2, VMSBC_VVM }, // 5847 |
25005 | | { PseudoVMSBC_VVM_M4, VMSBC_VVM }, // 5848 |
25006 | | { PseudoVMSBC_VVM_M8, VMSBC_VVM }, // 5849 |
25007 | | { PseudoVMSBC_VVM_MF2, VMSBC_VVM }, // 5850 |
25008 | | { PseudoVMSBC_VVM_MF4, VMSBC_VVM }, // 5851 |
25009 | | { PseudoVMSBC_VVM_MF8, VMSBC_VVM }, // 5852 |
25010 | | { PseudoVMSBC_VV_M1, VMSBC_VV }, // 5853 |
25011 | | { PseudoVMSBC_VV_M2, VMSBC_VV }, // 5854 |
25012 | | { PseudoVMSBC_VV_M4, VMSBC_VV }, // 5855 |
25013 | | { PseudoVMSBC_VV_M8, VMSBC_VV }, // 5856 |
25014 | | { PseudoVMSBC_VV_MF2, VMSBC_VV }, // 5857 |
25015 | | { PseudoVMSBC_VV_MF4, VMSBC_VV }, // 5858 |
25016 | | { PseudoVMSBC_VV_MF8, VMSBC_VV }, // 5859 |
25017 | | { PseudoVMSBC_VXM_M1, VMSBC_VXM }, // 5860 |
25018 | | { PseudoVMSBC_VXM_M2, VMSBC_VXM }, // 5861 |
25019 | | { PseudoVMSBC_VXM_M4, VMSBC_VXM }, // 5862 |
25020 | | { PseudoVMSBC_VXM_M8, VMSBC_VXM }, // 5863 |
25021 | | { PseudoVMSBC_VXM_MF2, VMSBC_VXM }, // 5864 |
25022 | | { PseudoVMSBC_VXM_MF4, VMSBC_VXM }, // 5865 |
25023 | | { PseudoVMSBC_VXM_MF8, VMSBC_VXM }, // 5866 |
25024 | | { PseudoVMSBC_VX_M1, VMSBC_VX }, // 5867 |
25025 | | { PseudoVMSBC_VX_M2, VMSBC_VX }, // 5868 |
25026 | | { PseudoVMSBC_VX_M4, VMSBC_VX }, // 5869 |
25027 | | { PseudoVMSBC_VX_M8, VMSBC_VX }, // 5870 |
25028 | | { PseudoVMSBC_VX_MF2, VMSBC_VX }, // 5871 |
25029 | | { PseudoVMSBC_VX_MF4, VMSBC_VX }, // 5872 |
25030 | | { PseudoVMSBC_VX_MF8, VMSBC_VX }, // 5873 |
25031 | | { PseudoVMSBF_M_B1, VMSBF_M }, // 5874 |
25032 | | { PseudoVMSBF_M_B16, VMSBF_M }, // 5875 |
25033 | | { PseudoVMSBF_M_B16_MASK, VMSBF_M }, // 5876 |
25034 | | { PseudoVMSBF_M_B1_MASK, VMSBF_M }, // 5877 |
25035 | | { PseudoVMSBF_M_B2, VMSBF_M }, // 5878 |
25036 | | { PseudoVMSBF_M_B2_MASK, VMSBF_M }, // 5879 |
25037 | | { PseudoVMSBF_M_B32, VMSBF_M }, // 5880 |
25038 | | { PseudoVMSBF_M_B32_MASK, VMSBF_M }, // 5881 |
25039 | | { PseudoVMSBF_M_B4, VMSBF_M }, // 5882 |
25040 | | { PseudoVMSBF_M_B4_MASK, VMSBF_M }, // 5883 |
25041 | | { PseudoVMSBF_M_B64, VMSBF_M }, // 5884 |
25042 | | { PseudoVMSBF_M_B64_MASK, VMSBF_M }, // 5885 |
25043 | | { PseudoVMSBF_M_B8, VMSBF_M }, // 5886 |
25044 | | { PseudoVMSBF_M_B8_MASK, VMSBF_M }, // 5887 |
25045 | | { PseudoVMSEQ_VI_M1, VMSEQ_VI }, // 5888 |
25046 | | { PseudoVMSEQ_VI_M1_MASK, VMSEQ_VI }, // 5889 |
25047 | | { PseudoVMSEQ_VI_M2, VMSEQ_VI }, // 5890 |
25048 | | { PseudoVMSEQ_VI_M2_MASK, VMSEQ_VI }, // 5891 |
25049 | | { PseudoVMSEQ_VI_M4, VMSEQ_VI }, // 5892 |
25050 | | { PseudoVMSEQ_VI_M4_MASK, VMSEQ_VI }, // 5893 |
25051 | | { PseudoVMSEQ_VI_M8, VMSEQ_VI }, // 5894 |
25052 | | { PseudoVMSEQ_VI_M8_MASK, VMSEQ_VI }, // 5895 |
25053 | | { PseudoVMSEQ_VI_MF2, VMSEQ_VI }, // 5896 |
25054 | | { PseudoVMSEQ_VI_MF2_MASK, VMSEQ_VI }, // 5897 |
25055 | | { PseudoVMSEQ_VI_MF4, VMSEQ_VI }, // 5898 |
25056 | | { PseudoVMSEQ_VI_MF4_MASK, VMSEQ_VI }, // 5899 |
25057 | | { PseudoVMSEQ_VI_MF8, VMSEQ_VI }, // 5900 |
25058 | | { PseudoVMSEQ_VI_MF8_MASK, VMSEQ_VI }, // 5901 |
25059 | | { PseudoVMSEQ_VV_M1, VMSEQ_VV }, // 5902 |
25060 | | { PseudoVMSEQ_VV_M1_MASK, VMSEQ_VV }, // 5903 |
25061 | | { PseudoVMSEQ_VV_M2, VMSEQ_VV }, // 5904 |
25062 | | { PseudoVMSEQ_VV_M2_MASK, VMSEQ_VV }, // 5905 |
25063 | | { PseudoVMSEQ_VV_M4, VMSEQ_VV }, // 5906 |
25064 | | { PseudoVMSEQ_VV_M4_MASK, VMSEQ_VV }, // 5907 |
25065 | | { PseudoVMSEQ_VV_M8, VMSEQ_VV }, // 5908 |
25066 | | { PseudoVMSEQ_VV_M8_MASK, VMSEQ_VV }, // 5909 |
25067 | | { PseudoVMSEQ_VV_MF2, VMSEQ_VV }, // 5910 |
25068 | | { PseudoVMSEQ_VV_MF2_MASK, VMSEQ_VV }, // 5911 |
25069 | | { PseudoVMSEQ_VV_MF4, VMSEQ_VV }, // 5912 |
25070 | | { PseudoVMSEQ_VV_MF4_MASK, VMSEQ_VV }, // 5913 |
25071 | | { PseudoVMSEQ_VV_MF8, VMSEQ_VV }, // 5914 |
25072 | | { PseudoVMSEQ_VV_MF8_MASK, VMSEQ_VV }, // 5915 |
25073 | | { PseudoVMSEQ_VX_M1, VMSEQ_VX }, // 5916 |
25074 | | { PseudoVMSEQ_VX_M1_MASK, VMSEQ_VX }, // 5917 |
25075 | | { PseudoVMSEQ_VX_M2, VMSEQ_VX }, // 5918 |
25076 | | { PseudoVMSEQ_VX_M2_MASK, VMSEQ_VX }, // 5919 |
25077 | | { PseudoVMSEQ_VX_M4, VMSEQ_VX }, // 5920 |
25078 | | { PseudoVMSEQ_VX_M4_MASK, VMSEQ_VX }, // 5921 |
25079 | | { PseudoVMSEQ_VX_M8, VMSEQ_VX }, // 5922 |
25080 | | { PseudoVMSEQ_VX_M8_MASK, VMSEQ_VX }, // 5923 |
25081 | | { PseudoVMSEQ_VX_MF2, VMSEQ_VX }, // 5924 |
25082 | | { PseudoVMSEQ_VX_MF2_MASK, VMSEQ_VX }, // 5925 |
25083 | | { PseudoVMSEQ_VX_MF4, VMSEQ_VX }, // 5926 |
25084 | | { PseudoVMSEQ_VX_MF4_MASK, VMSEQ_VX }, // 5927 |
25085 | | { PseudoVMSEQ_VX_MF8, VMSEQ_VX }, // 5928 |
25086 | | { PseudoVMSEQ_VX_MF8_MASK, VMSEQ_VX }, // 5929 |
25087 | | { PseudoVMSGTU_VI_M1, VMSGTU_VI }, // 5930 |
25088 | | { PseudoVMSGTU_VI_M1_MASK, VMSGTU_VI }, // 5931 |
25089 | | { PseudoVMSGTU_VI_M2, VMSGTU_VI }, // 5932 |
25090 | | { PseudoVMSGTU_VI_M2_MASK, VMSGTU_VI }, // 5933 |
25091 | | { PseudoVMSGTU_VI_M4, VMSGTU_VI }, // 5934 |
25092 | | { PseudoVMSGTU_VI_M4_MASK, VMSGTU_VI }, // 5935 |
25093 | | { PseudoVMSGTU_VI_M8, VMSGTU_VI }, // 5936 |
25094 | | { PseudoVMSGTU_VI_M8_MASK, VMSGTU_VI }, // 5937 |
25095 | | { PseudoVMSGTU_VI_MF2, VMSGTU_VI }, // 5938 |
25096 | | { PseudoVMSGTU_VI_MF2_MASK, VMSGTU_VI }, // 5939 |
25097 | | { PseudoVMSGTU_VI_MF4, VMSGTU_VI }, // 5940 |
25098 | | { PseudoVMSGTU_VI_MF4_MASK, VMSGTU_VI }, // 5941 |
25099 | | { PseudoVMSGTU_VI_MF8, VMSGTU_VI }, // 5942 |
25100 | | { PseudoVMSGTU_VI_MF8_MASK, VMSGTU_VI }, // 5943 |
25101 | | { PseudoVMSGTU_VX_M1, VMSGTU_VX }, // 5944 |
25102 | | { PseudoVMSGTU_VX_M1_MASK, VMSGTU_VX }, // 5945 |
25103 | | { PseudoVMSGTU_VX_M2, VMSGTU_VX }, // 5946 |
25104 | | { PseudoVMSGTU_VX_M2_MASK, VMSGTU_VX }, // 5947 |
25105 | | { PseudoVMSGTU_VX_M4, VMSGTU_VX }, // 5948 |
25106 | | { PseudoVMSGTU_VX_M4_MASK, VMSGTU_VX }, // 5949 |
25107 | | { PseudoVMSGTU_VX_M8, VMSGTU_VX }, // 5950 |
25108 | | { PseudoVMSGTU_VX_M8_MASK, VMSGTU_VX }, // 5951 |
25109 | | { PseudoVMSGTU_VX_MF2, VMSGTU_VX }, // 5952 |
25110 | | { PseudoVMSGTU_VX_MF2_MASK, VMSGTU_VX }, // 5953 |
25111 | | { PseudoVMSGTU_VX_MF4, VMSGTU_VX }, // 5954 |
25112 | | { PseudoVMSGTU_VX_MF4_MASK, VMSGTU_VX }, // 5955 |
25113 | | { PseudoVMSGTU_VX_MF8, VMSGTU_VX }, // 5956 |
25114 | | { PseudoVMSGTU_VX_MF8_MASK, VMSGTU_VX }, // 5957 |
25115 | | { PseudoVMSGT_VI_M1, VMSGT_VI }, // 5958 |
25116 | | { PseudoVMSGT_VI_M1_MASK, VMSGT_VI }, // 5959 |
25117 | | { PseudoVMSGT_VI_M2, VMSGT_VI }, // 5960 |
25118 | | { PseudoVMSGT_VI_M2_MASK, VMSGT_VI }, // 5961 |
25119 | | { PseudoVMSGT_VI_M4, VMSGT_VI }, // 5962 |
25120 | | { PseudoVMSGT_VI_M4_MASK, VMSGT_VI }, // 5963 |
25121 | | { PseudoVMSGT_VI_M8, VMSGT_VI }, // 5964 |
25122 | | { PseudoVMSGT_VI_M8_MASK, VMSGT_VI }, // 5965 |
25123 | | { PseudoVMSGT_VI_MF2, VMSGT_VI }, // 5966 |
25124 | | { PseudoVMSGT_VI_MF2_MASK, VMSGT_VI }, // 5967 |
25125 | | { PseudoVMSGT_VI_MF4, VMSGT_VI }, // 5968 |
25126 | | { PseudoVMSGT_VI_MF4_MASK, VMSGT_VI }, // 5969 |
25127 | | { PseudoVMSGT_VI_MF8, VMSGT_VI }, // 5970 |
25128 | | { PseudoVMSGT_VI_MF8_MASK, VMSGT_VI }, // 5971 |
25129 | | { PseudoVMSGT_VX_M1, VMSGT_VX }, // 5972 |
25130 | | { PseudoVMSGT_VX_M1_MASK, VMSGT_VX }, // 5973 |
25131 | | { PseudoVMSGT_VX_M2, VMSGT_VX }, // 5974 |
25132 | | { PseudoVMSGT_VX_M2_MASK, VMSGT_VX }, // 5975 |
25133 | | { PseudoVMSGT_VX_M4, VMSGT_VX }, // 5976 |
25134 | | { PseudoVMSGT_VX_M4_MASK, VMSGT_VX }, // 5977 |
25135 | | { PseudoVMSGT_VX_M8, VMSGT_VX }, // 5978 |
25136 | | { PseudoVMSGT_VX_M8_MASK, VMSGT_VX }, // 5979 |
25137 | | { PseudoVMSGT_VX_MF2, VMSGT_VX }, // 5980 |
25138 | | { PseudoVMSGT_VX_MF2_MASK, VMSGT_VX }, // 5981 |
25139 | | { PseudoVMSGT_VX_MF4, VMSGT_VX }, // 5982 |
25140 | | { PseudoVMSGT_VX_MF4_MASK, VMSGT_VX }, // 5983 |
25141 | | { PseudoVMSGT_VX_MF8, VMSGT_VX }, // 5984 |
25142 | | { PseudoVMSGT_VX_MF8_MASK, VMSGT_VX }, // 5985 |
25143 | | { PseudoVMSIF_M_B1, VMSIF_M }, // 5986 |
25144 | | { PseudoVMSIF_M_B16, VMSIF_M }, // 5987 |
25145 | | { PseudoVMSIF_M_B16_MASK, VMSIF_M }, // 5988 |
25146 | | { PseudoVMSIF_M_B1_MASK, VMSIF_M }, // 5989 |
25147 | | { PseudoVMSIF_M_B2, VMSIF_M }, // 5990 |
25148 | | { PseudoVMSIF_M_B2_MASK, VMSIF_M }, // 5991 |
25149 | | { PseudoVMSIF_M_B32, VMSIF_M }, // 5992 |
25150 | | { PseudoVMSIF_M_B32_MASK, VMSIF_M }, // 5993 |
25151 | | { PseudoVMSIF_M_B4, VMSIF_M }, // 5994 |
25152 | | { PseudoVMSIF_M_B4_MASK, VMSIF_M }, // 5995 |
25153 | | { PseudoVMSIF_M_B64, VMSIF_M }, // 5996 |
25154 | | { PseudoVMSIF_M_B64_MASK, VMSIF_M }, // 5997 |
25155 | | { PseudoVMSIF_M_B8, VMSIF_M }, // 5998 |
25156 | | { PseudoVMSIF_M_B8_MASK, VMSIF_M }, // 5999 |
25157 | | { PseudoVMSLEU_VI_M1, VMSLEU_VI }, // 6000 |
25158 | | { PseudoVMSLEU_VI_M1_MASK, VMSLEU_VI }, // 6001 |
25159 | | { PseudoVMSLEU_VI_M2, VMSLEU_VI }, // 6002 |
25160 | | { PseudoVMSLEU_VI_M2_MASK, VMSLEU_VI }, // 6003 |
25161 | | { PseudoVMSLEU_VI_M4, VMSLEU_VI }, // 6004 |
25162 | | { PseudoVMSLEU_VI_M4_MASK, VMSLEU_VI }, // 6005 |
25163 | | { PseudoVMSLEU_VI_M8, VMSLEU_VI }, // 6006 |
25164 | | { PseudoVMSLEU_VI_M8_MASK, VMSLEU_VI }, // 6007 |
25165 | | { PseudoVMSLEU_VI_MF2, VMSLEU_VI }, // 6008 |
25166 | | { PseudoVMSLEU_VI_MF2_MASK, VMSLEU_VI }, // 6009 |
25167 | | { PseudoVMSLEU_VI_MF4, VMSLEU_VI }, // 6010 |
25168 | | { PseudoVMSLEU_VI_MF4_MASK, VMSLEU_VI }, // 6011 |
25169 | | { PseudoVMSLEU_VI_MF8, VMSLEU_VI }, // 6012 |
25170 | | { PseudoVMSLEU_VI_MF8_MASK, VMSLEU_VI }, // 6013 |
25171 | | { PseudoVMSLEU_VV_M1, VMSLEU_VV }, // 6014 |
25172 | | { PseudoVMSLEU_VV_M1_MASK, VMSLEU_VV }, // 6015 |
25173 | | { PseudoVMSLEU_VV_M2, VMSLEU_VV }, // 6016 |
25174 | | { PseudoVMSLEU_VV_M2_MASK, VMSLEU_VV }, // 6017 |
25175 | | { PseudoVMSLEU_VV_M4, VMSLEU_VV }, // 6018 |
25176 | | { PseudoVMSLEU_VV_M4_MASK, VMSLEU_VV }, // 6019 |
25177 | | { PseudoVMSLEU_VV_M8, VMSLEU_VV }, // 6020 |
25178 | | { PseudoVMSLEU_VV_M8_MASK, VMSLEU_VV }, // 6021 |
25179 | | { PseudoVMSLEU_VV_MF2, VMSLEU_VV }, // 6022 |
25180 | | { PseudoVMSLEU_VV_MF2_MASK, VMSLEU_VV }, // 6023 |
25181 | | { PseudoVMSLEU_VV_MF4, VMSLEU_VV }, // 6024 |
25182 | | { PseudoVMSLEU_VV_MF4_MASK, VMSLEU_VV }, // 6025 |
25183 | | { PseudoVMSLEU_VV_MF8, VMSLEU_VV }, // 6026 |
25184 | | { PseudoVMSLEU_VV_MF8_MASK, VMSLEU_VV }, // 6027 |
25185 | | { PseudoVMSLEU_VX_M1, VMSLEU_VX }, // 6028 |
25186 | | { PseudoVMSLEU_VX_M1_MASK, VMSLEU_VX }, // 6029 |
25187 | | { PseudoVMSLEU_VX_M2, VMSLEU_VX }, // 6030 |
25188 | | { PseudoVMSLEU_VX_M2_MASK, VMSLEU_VX }, // 6031 |
25189 | | { PseudoVMSLEU_VX_M4, VMSLEU_VX }, // 6032 |
25190 | | { PseudoVMSLEU_VX_M4_MASK, VMSLEU_VX }, // 6033 |
25191 | | { PseudoVMSLEU_VX_M8, VMSLEU_VX }, // 6034 |
25192 | | { PseudoVMSLEU_VX_M8_MASK, VMSLEU_VX }, // 6035 |
25193 | | { PseudoVMSLEU_VX_MF2, VMSLEU_VX }, // 6036 |
25194 | | { PseudoVMSLEU_VX_MF2_MASK, VMSLEU_VX }, // 6037 |
25195 | | { PseudoVMSLEU_VX_MF4, VMSLEU_VX }, // 6038 |
25196 | | { PseudoVMSLEU_VX_MF4_MASK, VMSLEU_VX }, // 6039 |
25197 | | { PseudoVMSLEU_VX_MF8, VMSLEU_VX }, // 6040 |
25198 | | { PseudoVMSLEU_VX_MF8_MASK, VMSLEU_VX }, // 6041 |
25199 | | { PseudoVMSLE_VI_M1, VMSLE_VI }, // 6042 |
25200 | | { PseudoVMSLE_VI_M1_MASK, VMSLE_VI }, // 6043 |
25201 | | { PseudoVMSLE_VI_M2, VMSLE_VI }, // 6044 |
25202 | | { PseudoVMSLE_VI_M2_MASK, VMSLE_VI }, // 6045 |
25203 | | { PseudoVMSLE_VI_M4, VMSLE_VI }, // 6046 |
25204 | | { PseudoVMSLE_VI_M4_MASK, VMSLE_VI }, // 6047 |
25205 | | { PseudoVMSLE_VI_M8, VMSLE_VI }, // 6048 |
25206 | | { PseudoVMSLE_VI_M8_MASK, VMSLE_VI }, // 6049 |
25207 | | { PseudoVMSLE_VI_MF2, VMSLE_VI }, // 6050 |
25208 | | { PseudoVMSLE_VI_MF2_MASK, VMSLE_VI }, // 6051 |
25209 | | { PseudoVMSLE_VI_MF4, VMSLE_VI }, // 6052 |
25210 | | { PseudoVMSLE_VI_MF4_MASK, VMSLE_VI }, // 6053 |
25211 | | { PseudoVMSLE_VI_MF8, VMSLE_VI }, // 6054 |
25212 | | { PseudoVMSLE_VI_MF8_MASK, VMSLE_VI }, // 6055 |
25213 | | { PseudoVMSLE_VV_M1, VMSLE_VV }, // 6056 |
25214 | | { PseudoVMSLE_VV_M1_MASK, VMSLE_VV }, // 6057 |
25215 | | { PseudoVMSLE_VV_M2, VMSLE_VV }, // 6058 |
25216 | | { PseudoVMSLE_VV_M2_MASK, VMSLE_VV }, // 6059 |
25217 | | { PseudoVMSLE_VV_M4, VMSLE_VV }, // 6060 |
25218 | | { PseudoVMSLE_VV_M4_MASK, VMSLE_VV }, // 6061 |
25219 | | { PseudoVMSLE_VV_M8, VMSLE_VV }, // 6062 |
25220 | | { PseudoVMSLE_VV_M8_MASK, VMSLE_VV }, // 6063 |
25221 | | { PseudoVMSLE_VV_MF2, VMSLE_VV }, // 6064 |
25222 | | { PseudoVMSLE_VV_MF2_MASK, VMSLE_VV }, // 6065 |
25223 | | { PseudoVMSLE_VV_MF4, VMSLE_VV }, // 6066 |
25224 | | { PseudoVMSLE_VV_MF4_MASK, VMSLE_VV }, // 6067 |
25225 | | { PseudoVMSLE_VV_MF8, VMSLE_VV }, // 6068 |
25226 | | { PseudoVMSLE_VV_MF8_MASK, VMSLE_VV }, // 6069 |
25227 | | { PseudoVMSLE_VX_M1, VMSLE_VX }, // 6070 |
25228 | | { PseudoVMSLE_VX_M1_MASK, VMSLE_VX }, // 6071 |
25229 | | { PseudoVMSLE_VX_M2, VMSLE_VX }, // 6072 |
25230 | | { PseudoVMSLE_VX_M2_MASK, VMSLE_VX }, // 6073 |
25231 | | { PseudoVMSLE_VX_M4, VMSLE_VX }, // 6074 |
25232 | | { PseudoVMSLE_VX_M4_MASK, VMSLE_VX }, // 6075 |
25233 | | { PseudoVMSLE_VX_M8, VMSLE_VX }, // 6076 |
25234 | | { PseudoVMSLE_VX_M8_MASK, VMSLE_VX }, // 6077 |
25235 | | { PseudoVMSLE_VX_MF2, VMSLE_VX }, // 6078 |
25236 | | { PseudoVMSLE_VX_MF2_MASK, VMSLE_VX }, // 6079 |
25237 | | { PseudoVMSLE_VX_MF4, VMSLE_VX }, // 6080 |
25238 | | { PseudoVMSLE_VX_MF4_MASK, VMSLE_VX }, // 6081 |
25239 | | { PseudoVMSLE_VX_MF8, VMSLE_VX }, // 6082 |
25240 | | { PseudoVMSLE_VX_MF8_MASK, VMSLE_VX }, // 6083 |
25241 | | { PseudoVMSLTU_VV_M1, VMSLTU_VV }, // 6084 |
25242 | | { PseudoVMSLTU_VV_M1_MASK, VMSLTU_VV }, // 6085 |
25243 | | { PseudoVMSLTU_VV_M2, VMSLTU_VV }, // 6086 |
25244 | | { PseudoVMSLTU_VV_M2_MASK, VMSLTU_VV }, // 6087 |
25245 | | { PseudoVMSLTU_VV_M4, VMSLTU_VV }, // 6088 |
25246 | | { PseudoVMSLTU_VV_M4_MASK, VMSLTU_VV }, // 6089 |
25247 | | { PseudoVMSLTU_VV_M8, VMSLTU_VV }, // 6090 |
25248 | | { PseudoVMSLTU_VV_M8_MASK, VMSLTU_VV }, // 6091 |
25249 | | { PseudoVMSLTU_VV_MF2, VMSLTU_VV }, // 6092 |
25250 | | { PseudoVMSLTU_VV_MF2_MASK, VMSLTU_VV }, // 6093 |
25251 | | { PseudoVMSLTU_VV_MF4, VMSLTU_VV }, // 6094 |
25252 | | { PseudoVMSLTU_VV_MF4_MASK, VMSLTU_VV }, // 6095 |
25253 | | { PseudoVMSLTU_VV_MF8, VMSLTU_VV }, // 6096 |
25254 | | { PseudoVMSLTU_VV_MF8_MASK, VMSLTU_VV }, // 6097 |
25255 | | { PseudoVMSLTU_VX_M1, VMSLTU_VX }, // 6098 |
25256 | | { PseudoVMSLTU_VX_M1_MASK, VMSLTU_VX }, // 6099 |
25257 | | { PseudoVMSLTU_VX_M2, VMSLTU_VX }, // 6100 |
25258 | | { PseudoVMSLTU_VX_M2_MASK, VMSLTU_VX }, // 6101 |
25259 | | { PseudoVMSLTU_VX_M4, VMSLTU_VX }, // 6102 |
25260 | | { PseudoVMSLTU_VX_M4_MASK, VMSLTU_VX }, // 6103 |
25261 | | { PseudoVMSLTU_VX_M8, VMSLTU_VX }, // 6104 |
25262 | | { PseudoVMSLTU_VX_M8_MASK, VMSLTU_VX }, // 6105 |
25263 | | { PseudoVMSLTU_VX_MF2, VMSLTU_VX }, // 6106 |
25264 | | { PseudoVMSLTU_VX_MF2_MASK, VMSLTU_VX }, // 6107 |
25265 | | { PseudoVMSLTU_VX_MF4, VMSLTU_VX }, // 6108 |
25266 | | { PseudoVMSLTU_VX_MF4_MASK, VMSLTU_VX }, // 6109 |
25267 | | { PseudoVMSLTU_VX_MF8, VMSLTU_VX }, // 6110 |
25268 | | { PseudoVMSLTU_VX_MF8_MASK, VMSLTU_VX }, // 6111 |
25269 | | { PseudoVMSLT_VV_M1, VMSLT_VV }, // 6112 |
25270 | | { PseudoVMSLT_VV_M1_MASK, VMSLT_VV }, // 6113 |
25271 | | { PseudoVMSLT_VV_M2, VMSLT_VV }, // 6114 |
25272 | | { PseudoVMSLT_VV_M2_MASK, VMSLT_VV }, // 6115 |
25273 | | { PseudoVMSLT_VV_M4, VMSLT_VV }, // 6116 |
25274 | | { PseudoVMSLT_VV_M4_MASK, VMSLT_VV }, // 6117 |
25275 | | { PseudoVMSLT_VV_M8, VMSLT_VV }, // 6118 |
25276 | | { PseudoVMSLT_VV_M8_MASK, VMSLT_VV }, // 6119 |
25277 | | { PseudoVMSLT_VV_MF2, VMSLT_VV }, // 6120 |
25278 | | { PseudoVMSLT_VV_MF2_MASK, VMSLT_VV }, // 6121 |
25279 | | { PseudoVMSLT_VV_MF4, VMSLT_VV }, // 6122 |
25280 | | { PseudoVMSLT_VV_MF4_MASK, VMSLT_VV }, // 6123 |
25281 | | { PseudoVMSLT_VV_MF8, VMSLT_VV }, // 6124 |
25282 | | { PseudoVMSLT_VV_MF8_MASK, VMSLT_VV }, // 6125 |
25283 | | { PseudoVMSLT_VX_M1, VMSLT_VX }, // 6126 |
25284 | | { PseudoVMSLT_VX_M1_MASK, VMSLT_VX }, // 6127 |
25285 | | { PseudoVMSLT_VX_M2, VMSLT_VX }, // 6128 |
25286 | | { PseudoVMSLT_VX_M2_MASK, VMSLT_VX }, // 6129 |
25287 | | { PseudoVMSLT_VX_M4, VMSLT_VX }, // 6130 |
25288 | | { PseudoVMSLT_VX_M4_MASK, VMSLT_VX }, // 6131 |
25289 | | { PseudoVMSLT_VX_M8, VMSLT_VX }, // 6132 |
25290 | | { PseudoVMSLT_VX_M8_MASK, VMSLT_VX }, // 6133 |
25291 | | { PseudoVMSLT_VX_MF2, VMSLT_VX }, // 6134 |
25292 | | { PseudoVMSLT_VX_MF2_MASK, VMSLT_VX }, // 6135 |
25293 | | { PseudoVMSLT_VX_MF4, VMSLT_VX }, // 6136 |
25294 | | { PseudoVMSLT_VX_MF4_MASK, VMSLT_VX }, // 6137 |
25295 | | { PseudoVMSLT_VX_MF8, VMSLT_VX }, // 6138 |
25296 | | { PseudoVMSLT_VX_MF8_MASK, VMSLT_VX }, // 6139 |
25297 | | { PseudoVMSNE_VI_M1, VMSNE_VI }, // 6140 |
25298 | | { PseudoVMSNE_VI_M1_MASK, VMSNE_VI }, // 6141 |
25299 | | { PseudoVMSNE_VI_M2, VMSNE_VI }, // 6142 |
25300 | | { PseudoVMSNE_VI_M2_MASK, VMSNE_VI }, // 6143 |
25301 | | { PseudoVMSNE_VI_M4, VMSNE_VI }, // 6144 |
25302 | | { PseudoVMSNE_VI_M4_MASK, VMSNE_VI }, // 6145 |
25303 | | { PseudoVMSNE_VI_M8, VMSNE_VI }, // 6146 |
25304 | | { PseudoVMSNE_VI_M8_MASK, VMSNE_VI }, // 6147 |
25305 | | { PseudoVMSNE_VI_MF2, VMSNE_VI }, // 6148 |
25306 | | { PseudoVMSNE_VI_MF2_MASK, VMSNE_VI }, // 6149 |
25307 | | { PseudoVMSNE_VI_MF4, VMSNE_VI }, // 6150 |
25308 | | { PseudoVMSNE_VI_MF4_MASK, VMSNE_VI }, // 6151 |
25309 | | { PseudoVMSNE_VI_MF8, VMSNE_VI }, // 6152 |
25310 | | { PseudoVMSNE_VI_MF8_MASK, VMSNE_VI }, // 6153 |
25311 | | { PseudoVMSNE_VV_M1, VMSNE_VV }, // 6154 |
25312 | | { PseudoVMSNE_VV_M1_MASK, VMSNE_VV }, // 6155 |
25313 | | { PseudoVMSNE_VV_M2, VMSNE_VV }, // 6156 |
25314 | | { PseudoVMSNE_VV_M2_MASK, VMSNE_VV }, // 6157 |
25315 | | { PseudoVMSNE_VV_M4, VMSNE_VV }, // 6158 |
25316 | | { PseudoVMSNE_VV_M4_MASK, VMSNE_VV }, // 6159 |
25317 | | { PseudoVMSNE_VV_M8, VMSNE_VV }, // 6160 |
25318 | | { PseudoVMSNE_VV_M8_MASK, VMSNE_VV }, // 6161 |
25319 | | { PseudoVMSNE_VV_MF2, VMSNE_VV }, // 6162 |
25320 | | { PseudoVMSNE_VV_MF2_MASK, VMSNE_VV }, // 6163 |
25321 | | { PseudoVMSNE_VV_MF4, VMSNE_VV }, // 6164 |
25322 | | { PseudoVMSNE_VV_MF4_MASK, VMSNE_VV }, // 6165 |
25323 | | { PseudoVMSNE_VV_MF8, VMSNE_VV }, // 6166 |
25324 | | { PseudoVMSNE_VV_MF8_MASK, VMSNE_VV }, // 6167 |
25325 | | { PseudoVMSNE_VX_M1, VMSNE_VX }, // 6168 |
25326 | | { PseudoVMSNE_VX_M1_MASK, VMSNE_VX }, // 6169 |
25327 | | { PseudoVMSNE_VX_M2, VMSNE_VX }, // 6170 |
25328 | | { PseudoVMSNE_VX_M2_MASK, VMSNE_VX }, // 6171 |
25329 | | { PseudoVMSNE_VX_M4, VMSNE_VX }, // 6172 |
25330 | | { PseudoVMSNE_VX_M4_MASK, VMSNE_VX }, // 6173 |
25331 | | { PseudoVMSNE_VX_M8, VMSNE_VX }, // 6174 |
25332 | | { PseudoVMSNE_VX_M8_MASK, VMSNE_VX }, // 6175 |
25333 | | { PseudoVMSNE_VX_MF2, VMSNE_VX }, // 6176 |
25334 | | { PseudoVMSNE_VX_MF2_MASK, VMSNE_VX }, // 6177 |
25335 | | { PseudoVMSNE_VX_MF4, VMSNE_VX }, // 6178 |
25336 | | { PseudoVMSNE_VX_MF4_MASK, VMSNE_VX }, // 6179 |
25337 | | { PseudoVMSNE_VX_MF8, VMSNE_VX }, // 6180 |
25338 | | { PseudoVMSNE_VX_MF8_MASK, VMSNE_VX }, // 6181 |
25339 | | { PseudoVMSOF_M_B1, VMSOF_M }, // 6182 |
25340 | | { PseudoVMSOF_M_B16, VMSOF_M }, // 6183 |
25341 | | { PseudoVMSOF_M_B16_MASK, VMSOF_M }, // 6184 |
25342 | | { PseudoVMSOF_M_B1_MASK, VMSOF_M }, // 6185 |
25343 | | { PseudoVMSOF_M_B2, VMSOF_M }, // 6186 |
25344 | | { PseudoVMSOF_M_B2_MASK, VMSOF_M }, // 6187 |
25345 | | { PseudoVMSOF_M_B32, VMSOF_M }, // 6188 |
25346 | | { PseudoVMSOF_M_B32_MASK, VMSOF_M }, // 6189 |
25347 | | { PseudoVMSOF_M_B4, VMSOF_M }, // 6190 |
25348 | | { PseudoVMSOF_M_B4_MASK, VMSOF_M }, // 6191 |
25349 | | { PseudoVMSOF_M_B64, VMSOF_M }, // 6192 |
25350 | | { PseudoVMSOF_M_B64_MASK, VMSOF_M }, // 6193 |
25351 | | { PseudoVMSOF_M_B8, VMSOF_M }, // 6194 |
25352 | | { PseudoVMSOF_M_B8_MASK, VMSOF_M }, // 6195 |
25353 | | { PseudoVMULHSU_VV_M1, VMULHSU_VV }, // 6196 |
25354 | | { PseudoVMULHSU_VV_M1_MASK, VMULHSU_VV }, // 6197 |
25355 | | { PseudoVMULHSU_VV_M2, VMULHSU_VV }, // 6198 |
25356 | | { PseudoVMULHSU_VV_M2_MASK, VMULHSU_VV }, // 6199 |
25357 | | { PseudoVMULHSU_VV_M4, VMULHSU_VV }, // 6200 |
25358 | | { PseudoVMULHSU_VV_M4_MASK, VMULHSU_VV }, // 6201 |
25359 | | { PseudoVMULHSU_VV_M8, VMULHSU_VV }, // 6202 |
25360 | | { PseudoVMULHSU_VV_M8_MASK, VMULHSU_VV }, // 6203 |
25361 | | { PseudoVMULHSU_VV_MF2, VMULHSU_VV }, // 6204 |
25362 | | { PseudoVMULHSU_VV_MF2_MASK, VMULHSU_VV }, // 6205 |
25363 | | { PseudoVMULHSU_VV_MF4, VMULHSU_VV }, // 6206 |
25364 | | { PseudoVMULHSU_VV_MF4_MASK, VMULHSU_VV }, // 6207 |
25365 | | { PseudoVMULHSU_VV_MF8, VMULHSU_VV }, // 6208 |
25366 | | { PseudoVMULHSU_VV_MF8_MASK, VMULHSU_VV }, // 6209 |
25367 | | { PseudoVMULHSU_VX_M1, VMULHSU_VX }, // 6210 |
25368 | | { PseudoVMULHSU_VX_M1_MASK, VMULHSU_VX }, // 6211 |
25369 | | { PseudoVMULHSU_VX_M2, VMULHSU_VX }, // 6212 |
25370 | | { PseudoVMULHSU_VX_M2_MASK, VMULHSU_VX }, // 6213 |
25371 | | { PseudoVMULHSU_VX_M4, VMULHSU_VX }, // 6214 |
25372 | | { PseudoVMULHSU_VX_M4_MASK, VMULHSU_VX }, // 6215 |
25373 | | { PseudoVMULHSU_VX_M8, VMULHSU_VX }, // 6216 |
25374 | | { PseudoVMULHSU_VX_M8_MASK, VMULHSU_VX }, // 6217 |
25375 | | { PseudoVMULHSU_VX_MF2, VMULHSU_VX }, // 6218 |
25376 | | { PseudoVMULHSU_VX_MF2_MASK, VMULHSU_VX }, // 6219 |
25377 | | { PseudoVMULHSU_VX_MF4, VMULHSU_VX }, // 6220 |
25378 | | { PseudoVMULHSU_VX_MF4_MASK, VMULHSU_VX }, // 6221 |
25379 | | { PseudoVMULHSU_VX_MF8, VMULHSU_VX }, // 6222 |
25380 | | { PseudoVMULHSU_VX_MF8_MASK, VMULHSU_VX }, // 6223 |
25381 | | { PseudoVMULHU_VV_M1, VMULHU_VV }, // 6224 |
25382 | | { PseudoVMULHU_VV_M1_MASK, VMULHU_VV }, // 6225 |
25383 | | { PseudoVMULHU_VV_M2, VMULHU_VV }, // 6226 |
25384 | | { PseudoVMULHU_VV_M2_MASK, VMULHU_VV }, // 6227 |
25385 | | { PseudoVMULHU_VV_M4, VMULHU_VV }, // 6228 |
25386 | | { PseudoVMULHU_VV_M4_MASK, VMULHU_VV }, // 6229 |
25387 | | { PseudoVMULHU_VV_M8, VMULHU_VV }, // 6230 |
25388 | | { PseudoVMULHU_VV_M8_MASK, VMULHU_VV }, // 6231 |
25389 | | { PseudoVMULHU_VV_MF2, VMULHU_VV }, // 6232 |
25390 | | { PseudoVMULHU_VV_MF2_MASK, VMULHU_VV }, // 6233 |
25391 | | { PseudoVMULHU_VV_MF4, VMULHU_VV }, // 6234 |
25392 | | { PseudoVMULHU_VV_MF4_MASK, VMULHU_VV }, // 6235 |
25393 | | { PseudoVMULHU_VV_MF8, VMULHU_VV }, // 6236 |
25394 | | { PseudoVMULHU_VV_MF8_MASK, VMULHU_VV }, // 6237 |
25395 | | { PseudoVMULHU_VX_M1, VMULHU_VX }, // 6238 |
25396 | | { PseudoVMULHU_VX_M1_MASK, VMULHU_VX }, // 6239 |
25397 | | { PseudoVMULHU_VX_M2, VMULHU_VX }, // 6240 |
25398 | | { PseudoVMULHU_VX_M2_MASK, VMULHU_VX }, // 6241 |
25399 | | { PseudoVMULHU_VX_M4, VMULHU_VX }, // 6242 |
25400 | | { PseudoVMULHU_VX_M4_MASK, VMULHU_VX }, // 6243 |
25401 | | { PseudoVMULHU_VX_M8, VMULHU_VX }, // 6244 |
25402 | | { PseudoVMULHU_VX_M8_MASK, VMULHU_VX }, // 6245 |
25403 | | { PseudoVMULHU_VX_MF2, VMULHU_VX }, // 6246 |
25404 | | { PseudoVMULHU_VX_MF2_MASK, VMULHU_VX }, // 6247 |
25405 | | { PseudoVMULHU_VX_MF4, VMULHU_VX }, // 6248 |
25406 | | { PseudoVMULHU_VX_MF4_MASK, VMULHU_VX }, // 6249 |
25407 | | { PseudoVMULHU_VX_MF8, VMULHU_VX }, // 6250 |
25408 | | { PseudoVMULHU_VX_MF8_MASK, VMULHU_VX }, // 6251 |
25409 | | { PseudoVMULH_VV_M1, VMULH_VV }, // 6252 |
25410 | | { PseudoVMULH_VV_M1_MASK, VMULH_VV }, // 6253 |
25411 | | { PseudoVMULH_VV_M2, VMULH_VV }, // 6254 |
25412 | | { PseudoVMULH_VV_M2_MASK, VMULH_VV }, // 6255 |
25413 | | { PseudoVMULH_VV_M4, VMULH_VV }, // 6256 |
25414 | | { PseudoVMULH_VV_M4_MASK, VMULH_VV }, // 6257 |
25415 | | { PseudoVMULH_VV_M8, VMULH_VV }, // 6258 |
25416 | | { PseudoVMULH_VV_M8_MASK, VMULH_VV }, // 6259 |
25417 | | { PseudoVMULH_VV_MF2, VMULH_VV }, // 6260 |
25418 | | { PseudoVMULH_VV_MF2_MASK, VMULH_VV }, // 6261 |
25419 | | { PseudoVMULH_VV_MF4, VMULH_VV }, // 6262 |
25420 | | { PseudoVMULH_VV_MF4_MASK, VMULH_VV }, // 6263 |
25421 | | { PseudoVMULH_VV_MF8, VMULH_VV }, // 6264 |
25422 | | { PseudoVMULH_VV_MF8_MASK, VMULH_VV }, // 6265 |
25423 | | { PseudoVMULH_VX_M1, VMULH_VX }, // 6266 |
25424 | | { PseudoVMULH_VX_M1_MASK, VMULH_VX }, // 6267 |
25425 | | { PseudoVMULH_VX_M2, VMULH_VX }, // 6268 |
25426 | | { PseudoVMULH_VX_M2_MASK, VMULH_VX }, // 6269 |
25427 | | { PseudoVMULH_VX_M4, VMULH_VX }, // 6270 |
25428 | | { PseudoVMULH_VX_M4_MASK, VMULH_VX }, // 6271 |
25429 | | { PseudoVMULH_VX_M8, VMULH_VX }, // 6272 |
25430 | | { PseudoVMULH_VX_M8_MASK, VMULH_VX }, // 6273 |
25431 | | { PseudoVMULH_VX_MF2, VMULH_VX }, // 6274 |
25432 | | { PseudoVMULH_VX_MF2_MASK, VMULH_VX }, // 6275 |
25433 | | { PseudoVMULH_VX_MF4, VMULH_VX }, // 6276 |
25434 | | { PseudoVMULH_VX_MF4_MASK, VMULH_VX }, // 6277 |
25435 | | { PseudoVMULH_VX_MF8, VMULH_VX }, // 6278 |
25436 | | { PseudoVMULH_VX_MF8_MASK, VMULH_VX }, // 6279 |
25437 | | { PseudoVMUL_VV_M1, VMUL_VV }, // 6280 |
25438 | | { PseudoVMUL_VV_M1_MASK, VMUL_VV }, // 6281 |
25439 | | { PseudoVMUL_VV_M2, VMUL_VV }, // 6282 |
25440 | | { PseudoVMUL_VV_M2_MASK, VMUL_VV }, // 6283 |
25441 | | { PseudoVMUL_VV_M4, VMUL_VV }, // 6284 |
25442 | | { PseudoVMUL_VV_M4_MASK, VMUL_VV }, // 6285 |
25443 | | { PseudoVMUL_VV_M8, VMUL_VV }, // 6286 |
25444 | | { PseudoVMUL_VV_M8_MASK, VMUL_VV }, // 6287 |
25445 | | { PseudoVMUL_VV_MF2, VMUL_VV }, // 6288 |
25446 | | { PseudoVMUL_VV_MF2_MASK, VMUL_VV }, // 6289 |
25447 | | { PseudoVMUL_VV_MF4, VMUL_VV }, // 6290 |
25448 | | { PseudoVMUL_VV_MF4_MASK, VMUL_VV }, // 6291 |
25449 | | { PseudoVMUL_VV_MF8, VMUL_VV }, // 6292 |
25450 | | { PseudoVMUL_VV_MF8_MASK, VMUL_VV }, // 6293 |
25451 | | { PseudoVMUL_VX_M1, VMUL_VX }, // 6294 |
25452 | | { PseudoVMUL_VX_M1_MASK, VMUL_VX }, // 6295 |
25453 | | { PseudoVMUL_VX_M2, VMUL_VX }, // 6296 |
25454 | | { PseudoVMUL_VX_M2_MASK, VMUL_VX }, // 6297 |
25455 | | { PseudoVMUL_VX_M4, VMUL_VX }, // 6298 |
25456 | | { PseudoVMUL_VX_M4_MASK, VMUL_VX }, // 6299 |
25457 | | { PseudoVMUL_VX_M8, VMUL_VX }, // 6300 |
25458 | | { PseudoVMUL_VX_M8_MASK, VMUL_VX }, // 6301 |
25459 | | { PseudoVMUL_VX_MF2, VMUL_VX }, // 6302 |
25460 | | { PseudoVMUL_VX_MF2_MASK, VMUL_VX }, // 6303 |
25461 | | { PseudoVMUL_VX_MF4, VMUL_VX }, // 6304 |
25462 | | { PseudoVMUL_VX_MF4_MASK, VMUL_VX }, // 6305 |
25463 | | { PseudoVMUL_VX_MF8, VMUL_VX }, // 6306 |
25464 | | { PseudoVMUL_VX_MF8_MASK, VMUL_VX }, // 6307 |
25465 | | { PseudoVMV_S_X, VMV_S_X }, // 6308 |
25466 | | { PseudoVMV_V_I_M1, VMV_V_I }, // 6309 |
25467 | | { PseudoVMV_V_I_M2, VMV_V_I }, // 6310 |
25468 | | { PseudoVMV_V_I_M4, VMV_V_I }, // 6311 |
25469 | | { PseudoVMV_V_I_M8, VMV_V_I }, // 6312 |
25470 | | { PseudoVMV_V_I_MF2, VMV_V_I }, // 6313 |
25471 | | { PseudoVMV_V_I_MF4, VMV_V_I }, // 6314 |
25472 | | { PseudoVMV_V_I_MF8, VMV_V_I }, // 6315 |
25473 | | { PseudoVMV_V_V_M1, VMV_V_V }, // 6316 |
25474 | | { PseudoVMV_V_V_M2, VMV_V_V }, // 6317 |
25475 | | { PseudoVMV_V_V_M4, VMV_V_V }, // 6318 |
25476 | | { PseudoVMV_V_V_M8, VMV_V_V }, // 6319 |
25477 | | { PseudoVMV_V_V_MF2, VMV_V_V }, // 6320 |
25478 | | { PseudoVMV_V_V_MF4, VMV_V_V }, // 6321 |
25479 | | { PseudoVMV_V_V_MF8, VMV_V_V }, // 6322 |
25480 | | { PseudoVMV_V_X_M1, VMV_V_X }, // 6323 |
25481 | | { PseudoVMV_V_X_M2, VMV_V_X }, // 6324 |
25482 | | { PseudoVMV_V_X_M4, VMV_V_X }, // 6325 |
25483 | | { PseudoVMV_V_X_M8, VMV_V_X }, // 6326 |
25484 | | { PseudoVMV_V_X_MF2, VMV_V_X }, // 6327 |
25485 | | { PseudoVMV_V_X_MF4, VMV_V_X }, // 6328 |
25486 | | { PseudoVMV_V_X_MF8, VMV_V_X }, // 6329 |
25487 | | { PseudoVMV_X_S, VMV_X_S }, // 6330 |
25488 | | { PseudoVMXNOR_MM_M1, VMXNOR_MM }, // 6331 |
25489 | | { PseudoVMXNOR_MM_M2, VMXNOR_MM }, // 6332 |
25490 | | { PseudoVMXNOR_MM_M4, VMXNOR_MM }, // 6333 |
25491 | | { PseudoVMXNOR_MM_M8, VMXNOR_MM }, // 6334 |
25492 | | { PseudoVMXNOR_MM_MF2, VMXNOR_MM }, // 6335 |
25493 | | { PseudoVMXNOR_MM_MF4, VMXNOR_MM }, // 6336 |
25494 | | { PseudoVMXNOR_MM_MF8, VMXNOR_MM }, // 6337 |
25495 | | { PseudoVMXOR_MM_M1, VMXOR_MM }, // 6338 |
25496 | | { PseudoVMXOR_MM_M2, VMXOR_MM }, // 6339 |
25497 | | { PseudoVMXOR_MM_M4, VMXOR_MM }, // 6340 |
25498 | | { PseudoVMXOR_MM_M8, VMXOR_MM }, // 6341 |
25499 | | { PseudoVMXOR_MM_MF2, VMXOR_MM }, // 6342 |
25500 | | { PseudoVMXOR_MM_MF4, VMXOR_MM }, // 6343 |
25501 | | { PseudoVMXOR_MM_MF8, VMXOR_MM }, // 6344 |
25502 | | { PseudoVNCLIPU_WI_M1, VNCLIPU_WI }, // 6345 |
25503 | | { PseudoVNCLIPU_WI_M1_MASK, VNCLIPU_WI }, // 6346 |
25504 | | { PseudoVNCLIPU_WI_M2, VNCLIPU_WI }, // 6347 |
25505 | | { PseudoVNCLIPU_WI_M2_MASK, VNCLIPU_WI }, // 6348 |
25506 | | { PseudoVNCLIPU_WI_M4, VNCLIPU_WI }, // 6349 |
25507 | | { PseudoVNCLIPU_WI_M4_MASK, VNCLIPU_WI }, // 6350 |
25508 | | { PseudoVNCLIPU_WI_MF2, VNCLIPU_WI }, // 6351 |
25509 | | { PseudoVNCLIPU_WI_MF2_MASK, VNCLIPU_WI }, // 6352 |
25510 | | { PseudoVNCLIPU_WI_MF4, VNCLIPU_WI }, // 6353 |
25511 | | { PseudoVNCLIPU_WI_MF4_MASK, VNCLIPU_WI }, // 6354 |
25512 | | { PseudoVNCLIPU_WI_MF8, VNCLIPU_WI }, // 6355 |
25513 | | { PseudoVNCLIPU_WI_MF8_MASK, VNCLIPU_WI }, // 6356 |
25514 | | { PseudoVNCLIPU_WV_M1, VNCLIPU_WV }, // 6357 |
25515 | | { PseudoVNCLIPU_WV_M1_MASK, VNCLIPU_WV }, // 6358 |
25516 | | { PseudoVNCLIPU_WV_M2, VNCLIPU_WV }, // 6359 |
25517 | | { PseudoVNCLIPU_WV_M2_MASK, VNCLIPU_WV }, // 6360 |
25518 | | { PseudoVNCLIPU_WV_M4, VNCLIPU_WV }, // 6361 |
25519 | | { PseudoVNCLIPU_WV_M4_MASK, VNCLIPU_WV }, // 6362 |
25520 | | { PseudoVNCLIPU_WV_MF2, VNCLIPU_WV }, // 6363 |
25521 | | { PseudoVNCLIPU_WV_MF2_MASK, VNCLIPU_WV }, // 6364 |
25522 | | { PseudoVNCLIPU_WV_MF4, VNCLIPU_WV }, // 6365 |
25523 | | { PseudoVNCLIPU_WV_MF4_MASK, VNCLIPU_WV }, // 6366 |
25524 | | { PseudoVNCLIPU_WV_MF8, VNCLIPU_WV }, // 6367 |
25525 | | { PseudoVNCLIPU_WV_MF8_MASK, VNCLIPU_WV }, // 6368 |
25526 | | { PseudoVNCLIPU_WX_M1, VNCLIPU_WX }, // 6369 |
25527 | | { PseudoVNCLIPU_WX_M1_MASK, VNCLIPU_WX }, // 6370 |
25528 | | { PseudoVNCLIPU_WX_M2, VNCLIPU_WX }, // 6371 |
25529 | | { PseudoVNCLIPU_WX_M2_MASK, VNCLIPU_WX }, // 6372 |
25530 | | { PseudoVNCLIPU_WX_M4, VNCLIPU_WX }, // 6373 |
25531 | | { PseudoVNCLIPU_WX_M4_MASK, VNCLIPU_WX }, // 6374 |
25532 | | { PseudoVNCLIPU_WX_MF2, VNCLIPU_WX }, // 6375 |
25533 | | { PseudoVNCLIPU_WX_MF2_MASK, VNCLIPU_WX }, // 6376 |
25534 | | { PseudoVNCLIPU_WX_MF4, VNCLIPU_WX }, // 6377 |
25535 | | { PseudoVNCLIPU_WX_MF4_MASK, VNCLIPU_WX }, // 6378 |
25536 | | { PseudoVNCLIPU_WX_MF8, VNCLIPU_WX }, // 6379 |
25537 | | { PseudoVNCLIPU_WX_MF8_MASK, VNCLIPU_WX }, // 6380 |
25538 | | { PseudoVNCLIP_WI_M1, VNCLIP_WI }, // 6381 |
25539 | | { PseudoVNCLIP_WI_M1_MASK, VNCLIP_WI }, // 6382 |
25540 | | { PseudoVNCLIP_WI_M2, VNCLIP_WI }, // 6383 |
25541 | | { PseudoVNCLIP_WI_M2_MASK, VNCLIP_WI }, // 6384 |
25542 | | { PseudoVNCLIP_WI_M4, VNCLIP_WI }, // 6385 |
25543 | | { PseudoVNCLIP_WI_M4_MASK, VNCLIP_WI }, // 6386 |
25544 | | { PseudoVNCLIP_WI_MF2, VNCLIP_WI }, // 6387 |
25545 | | { PseudoVNCLIP_WI_MF2_MASK, VNCLIP_WI }, // 6388 |
25546 | | { PseudoVNCLIP_WI_MF4, VNCLIP_WI }, // 6389 |
25547 | | { PseudoVNCLIP_WI_MF4_MASK, VNCLIP_WI }, // 6390 |
25548 | | { PseudoVNCLIP_WI_MF8, VNCLIP_WI }, // 6391 |
25549 | | { PseudoVNCLIP_WI_MF8_MASK, VNCLIP_WI }, // 6392 |
25550 | | { PseudoVNCLIP_WV_M1, VNCLIP_WV }, // 6393 |
25551 | | { PseudoVNCLIP_WV_M1_MASK, VNCLIP_WV }, // 6394 |
25552 | | { PseudoVNCLIP_WV_M2, VNCLIP_WV }, // 6395 |
25553 | | { PseudoVNCLIP_WV_M2_MASK, VNCLIP_WV }, // 6396 |
25554 | | { PseudoVNCLIP_WV_M4, VNCLIP_WV }, // 6397 |
25555 | | { PseudoVNCLIP_WV_M4_MASK, VNCLIP_WV }, // 6398 |
25556 | | { PseudoVNCLIP_WV_MF2, VNCLIP_WV }, // 6399 |
25557 | | { PseudoVNCLIP_WV_MF2_MASK, VNCLIP_WV }, // 6400 |
25558 | | { PseudoVNCLIP_WV_MF4, VNCLIP_WV }, // 6401 |
25559 | | { PseudoVNCLIP_WV_MF4_MASK, VNCLIP_WV }, // 6402 |
25560 | | { PseudoVNCLIP_WV_MF8, VNCLIP_WV }, // 6403 |
25561 | | { PseudoVNCLIP_WV_MF8_MASK, VNCLIP_WV }, // 6404 |
25562 | | { PseudoVNCLIP_WX_M1, VNCLIP_WX }, // 6405 |
25563 | | { PseudoVNCLIP_WX_M1_MASK, VNCLIP_WX }, // 6406 |
25564 | | { PseudoVNCLIP_WX_M2, VNCLIP_WX }, // 6407 |
25565 | | { PseudoVNCLIP_WX_M2_MASK, VNCLIP_WX }, // 6408 |
25566 | | { PseudoVNCLIP_WX_M4, VNCLIP_WX }, // 6409 |
25567 | | { PseudoVNCLIP_WX_M4_MASK, VNCLIP_WX }, // 6410 |
25568 | | { PseudoVNCLIP_WX_MF2, VNCLIP_WX }, // 6411 |
25569 | | { PseudoVNCLIP_WX_MF2_MASK, VNCLIP_WX }, // 6412 |
25570 | | { PseudoVNCLIP_WX_MF4, VNCLIP_WX }, // 6413 |
25571 | | { PseudoVNCLIP_WX_MF4_MASK, VNCLIP_WX }, // 6414 |
25572 | | { PseudoVNCLIP_WX_MF8, VNCLIP_WX }, // 6415 |
25573 | | { PseudoVNCLIP_WX_MF8_MASK, VNCLIP_WX }, // 6416 |
25574 | | { PseudoVNMSAC_VV_M1, VNMSAC_VV }, // 6417 |
25575 | | { PseudoVNMSAC_VV_M1_MASK, VNMSAC_VV }, // 6418 |
25576 | | { PseudoVNMSAC_VV_M2, VNMSAC_VV }, // 6419 |
25577 | | { PseudoVNMSAC_VV_M2_MASK, VNMSAC_VV }, // 6420 |
25578 | | { PseudoVNMSAC_VV_M4, VNMSAC_VV }, // 6421 |
25579 | | { PseudoVNMSAC_VV_M4_MASK, VNMSAC_VV }, // 6422 |
25580 | | { PseudoVNMSAC_VV_M8, VNMSAC_VV }, // 6423 |
25581 | | { PseudoVNMSAC_VV_M8_MASK, VNMSAC_VV }, // 6424 |
25582 | | { PseudoVNMSAC_VV_MF2, VNMSAC_VV }, // 6425 |
25583 | | { PseudoVNMSAC_VV_MF2_MASK, VNMSAC_VV }, // 6426 |
25584 | | { PseudoVNMSAC_VV_MF4, VNMSAC_VV }, // 6427 |
25585 | | { PseudoVNMSAC_VV_MF4_MASK, VNMSAC_VV }, // 6428 |
25586 | | { PseudoVNMSAC_VV_MF8, VNMSAC_VV }, // 6429 |
25587 | | { PseudoVNMSAC_VV_MF8_MASK, VNMSAC_VV }, // 6430 |
25588 | | { PseudoVNMSAC_VX_M1, VNMSAC_VX }, // 6431 |
25589 | | { PseudoVNMSAC_VX_M1_MASK, VNMSAC_VX }, // 6432 |
25590 | | { PseudoVNMSAC_VX_M2, VNMSAC_VX }, // 6433 |
25591 | | { PseudoVNMSAC_VX_M2_MASK, VNMSAC_VX }, // 6434 |
25592 | | { PseudoVNMSAC_VX_M4, VNMSAC_VX }, // 6435 |
25593 | | { PseudoVNMSAC_VX_M4_MASK, VNMSAC_VX }, // 6436 |
25594 | | { PseudoVNMSAC_VX_M8, VNMSAC_VX }, // 6437 |
25595 | | { PseudoVNMSAC_VX_M8_MASK, VNMSAC_VX }, // 6438 |
25596 | | { PseudoVNMSAC_VX_MF2, VNMSAC_VX }, // 6439 |
25597 | | { PseudoVNMSAC_VX_MF2_MASK, VNMSAC_VX }, // 6440 |
25598 | | { PseudoVNMSAC_VX_MF4, VNMSAC_VX }, // 6441 |
25599 | | { PseudoVNMSAC_VX_MF4_MASK, VNMSAC_VX }, // 6442 |
25600 | | { PseudoVNMSAC_VX_MF8, VNMSAC_VX }, // 6443 |
25601 | | { PseudoVNMSAC_VX_MF8_MASK, VNMSAC_VX }, // 6444 |
25602 | | { PseudoVNMSUB_VV_M1, VNMSUB_VV }, // 6445 |
25603 | | { PseudoVNMSUB_VV_M1_MASK, VNMSUB_VV }, // 6446 |
25604 | | { PseudoVNMSUB_VV_M2, VNMSUB_VV }, // 6447 |
25605 | | { PseudoVNMSUB_VV_M2_MASK, VNMSUB_VV }, // 6448 |
25606 | | { PseudoVNMSUB_VV_M4, VNMSUB_VV }, // 6449 |
25607 | | { PseudoVNMSUB_VV_M4_MASK, VNMSUB_VV }, // 6450 |
25608 | | { PseudoVNMSUB_VV_M8, VNMSUB_VV }, // 6451 |
25609 | | { PseudoVNMSUB_VV_M8_MASK, VNMSUB_VV }, // 6452 |
25610 | | { PseudoVNMSUB_VV_MF2, VNMSUB_VV }, // 6453 |
25611 | | { PseudoVNMSUB_VV_MF2_MASK, VNMSUB_VV }, // 6454 |
25612 | | { PseudoVNMSUB_VV_MF4, VNMSUB_VV }, // 6455 |
25613 | | { PseudoVNMSUB_VV_MF4_MASK, VNMSUB_VV }, // 6456 |
25614 | | { PseudoVNMSUB_VV_MF8, VNMSUB_VV }, // 6457 |
25615 | | { PseudoVNMSUB_VV_MF8_MASK, VNMSUB_VV }, // 6458 |
25616 | | { PseudoVNMSUB_VX_M1, VNMSUB_VX }, // 6459 |
25617 | | { PseudoVNMSUB_VX_M1_MASK, VNMSUB_VX }, // 6460 |
25618 | | { PseudoVNMSUB_VX_M2, VNMSUB_VX }, // 6461 |
25619 | | { PseudoVNMSUB_VX_M2_MASK, VNMSUB_VX }, // 6462 |
25620 | | { PseudoVNMSUB_VX_M4, VNMSUB_VX }, // 6463 |
25621 | | { PseudoVNMSUB_VX_M4_MASK, VNMSUB_VX }, // 6464 |
25622 | | { PseudoVNMSUB_VX_M8, VNMSUB_VX }, // 6465 |
25623 | | { PseudoVNMSUB_VX_M8_MASK, VNMSUB_VX }, // 6466 |
25624 | | { PseudoVNMSUB_VX_MF2, VNMSUB_VX }, // 6467 |
25625 | | { PseudoVNMSUB_VX_MF2_MASK, VNMSUB_VX }, // 6468 |
25626 | | { PseudoVNMSUB_VX_MF4, VNMSUB_VX }, // 6469 |
25627 | | { PseudoVNMSUB_VX_MF4_MASK, VNMSUB_VX }, // 6470 |
25628 | | { PseudoVNMSUB_VX_MF8, VNMSUB_VX }, // 6471 |
25629 | | { PseudoVNMSUB_VX_MF8_MASK, VNMSUB_VX }, // 6472 |
25630 | | { PseudoVNSRA_WI_M1, VNSRA_WI }, // 6473 |
25631 | | { PseudoVNSRA_WI_M1_MASK, VNSRA_WI }, // 6474 |
25632 | | { PseudoVNSRA_WI_M2, VNSRA_WI }, // 6475 |
25633 | | { PseudoVNSRA_WI_M2_MASK, VNSRA_WI }, // 6476 |
25634 | | { PseudoVNSRA_WI_M4, VNSRA_WI }, // 6477 |
25635 | | { PseudoVNSRA_WI_M4_MASK, VNSRA_WI }, // 6478 |
25636 | | { PseudoVNSRA_WI_MF2, VNSRA_WI }, // 6479 |
25637 | | { PseudoVNSRA_WI_MF2_MASK, VNSRA_WI }, // 6480 |
25638 | | { PseudoVNSRA_WI_MF4, VNSRA_WI }, // 6481 |
25639 | | { PseudoVNSRA_WI_MF4_MASK, VNSRA_WI }, // 6482 |
25640 | | { PseudoVNSRA_WI_MF8, VNSRA_WI }, // 6483 |
25641 | | { PseudoVNSRA_WI_MF8_MASK, VNSRA_WI }, // 6484 |
25642 | | { PseudoVNSRA_WV_M1, VNSRA_WV }, // 6485 |
25643 | | { PseudoVNSRA_WV_M1_MASK, VNSRA_WV }, // 6486 |
25644 | | { PseudoVNSRA_WV_M2, VNSRA_WV }, // 6487 |
25645 | | { PseudoVNSRA_WV_M2_MASK, VNSRA_WV }, // 6488 |
25646 | | { PseudoVNSRA_WV_M4, VNSRA_WV }, // 6489 |
25647 | | { PseudoVNSRA_WV_M4_MASK, VNSRA_WV }, // 6490 |
25648 | | { PseudoVNSRA_WV_MF2, VNSRA_WV }, // 6491 |
25649 | | { PseudoVNSRA_WV_MF2_MASK, VNSRA_WV }, // 6492 |
25650 | | { PseudoVNSRA_WV_MF4, VNSRA_WV }, // 6493 |
25651 | | { PseudoVNSRA_WV_MF4_MASK, VNSRA_WV }, // 6494 |
25652 | | { PseudoVNSRA_WV_MF8, VNSRA_WV }, // 6495 |
25653 | | { PseudoVNSRA_WV_MF8_MASK, VNSRA_WV }, // 6496 |
25654 | | { PseudoVNSRA_WX_M1, VNSRA_WX }, // 6497 |
25655 | | { PseudoVNSRA_WX_M1_MASK, VNSRA_WX }, // 6498 |
25656 | | { PseudoVNSRA_WX_M2, VNSRA_WX }, // 6499 |
25657 | | { PseudoVNSRA_WX_M2_MASK, VNSRA_WX }, // 6500 |
25658 | | { PseudoVNSRA_WX_M4, VNSRA_WX }, // 6501 |
25659 | | { PseudoVNSRA_WX_M4_MASK, VNSRA_WX }, // 6502 |
25660 | | { PseudoVNSRA_WX_MF2, VNSRA_WX }, // 6503 |
25661 | | { PseudoVNSRA_WX_MF2_MASK, VNSRA_WX }, // 6504 |
25662 | | { PseudoVNSRA_WX_MF4, VNSRA_WX }, // 6505 |
25663 | | { PseudoVNSRA_WX_MF4_MASK, VNSRA_WX }, // 6506 |
25664 | | { PseudoVNSRA_WX_MF8, VNSRA_WX }, // 6507 |
25665 | | { PseudoVNSRA_WX_MF8_MASK, VNSRA_WX }, // 6508 |
25666 | | { PseudoVNSRL_WI_M1, VNSRL_WI }, // 6509 |
25667 | | { PseudoVNSRL_WI_M1_MASK, VNSRL_WI }, // 6510 |
25668 | | { PseudoVNSRL_WI_M2, VNSRL_WI }, // 6511 |
25669 | | { PseudoVNSRL_WI_M2_MASK, VNSRL_WI }, // 6512 |
25670 | | { PseudoVNSRL_WI_M4, VNSRL_WI }, // 6513 |
25671 | | { PseudoVNSRL_WI_M4_MASK, VNSRL_WI }, // 6514 |
25672 | | { PseudoVNSRL_WI_MF2, VNSRL_WI }, // 6515 |
25673 | | { PseudoVNSRL_WI_MF2_MASK, VNSRL_WI }, // 6516 |
25674 | | { PseudoVNSRL_WI_MF4, VNSRL_WI }, // 6517 |
25675 | | { PseudoVNSRL_WI_MF4_MASK, VNSRL_WI }, // 6518 |
25676 | | { PseudoVNSRL_WI_MF8, VNSRL_WI }, // 6519 |
25677 | | { PseudoVNSRL_WI_MF8_MASK, VNSRL_WI }, // 6520 |
25678 | | { PseudoVNSRL_WV_M1, VNSRL_WV }, // 6521 |
25679 | | { PseudoVNSRL_WV_M1_MASK, VNSRL_WV }, // 6522 |
25680 | | { PseudoVNSRL_WV_M2, VNSRL_WV }, // 6523 |
25681 | | { PseudoVNSRL_WV_M2_MASK, VNSRL_WV }, // 6524 |
25682 | | { PseudoVNSRL_WV_M4, VNSRL_WV }, // 6525 |
25683 | | { PseudoVNSRL_WV_M4_MASK, VNSRL_WV }, // 6526 |
25684 | | { PseudoVNSRL_WV_MF2, VNSRL_WV }, // 6527 |
25685 | | { PseudoVNSRL_WV_MF2_MASK, VNSRL_WV }, // 6528 |
25686 | | { PseudoVNSRL_WV_MF4, VNSRL_WV }, // 6529 |
25687 | | { PseudoVNSRL_WV_MF4_MASK, VNSRL_WV }, // 6530 |
25688 | | { PseudoVNSRL_WV_MF8, VNSRL_WV }, // 6531 |
25689 | | { PseudoVNSRL_WV_MF8_MASK, VNSRL_WV }, // 6532 |
25690 | | { PseudoVNSRL_WX_M1, VNSRL_WX }, // 6533 |
25691 | | { PseudoVNSRL_WX_M1_MASK, VNSRL_WX }, // 6534 |
25692 | | { PseudoVNSRL_WX_M2, VNSRL_WX }, // 6535 |
25693 | | { PseudoVNSRL_WX_M2_MASK, VNSRL_WX }, // 6536 |
25694 | | { PseudoVNSRL_WX_M4, VNSRL_WX }, // 6537 |
25695 | | { PseudoVNSRL_WX_M4_MASK, VNSRL_WX }, // 6538 |
25696 | | { PseudoVNSRL_WX_MF2, VNSRL_WX }, // 6539 |
25697 | | { PseudoVNSRL_WX_MF2_MASK, VNSRL_WX }, // 6540 |
25698 | | { PseudoVNSRL_WX_MF4, VNSRL_WX }, // 6541 |
25699 | | { PseudoVNSRL_WX_MF4_MASK, VNSRL_WX }, // 6542 |
25700 | | { PseudoVNSRL_WX_MF8, VNSRL_WX }, // 6543 |
25701 | | { PseudoVNSRL_WX_MF8_MASK, VNSRL_WX }, // 6544 |
25702 | | { PseudoVOR_VI_M1, VOR_VI }, // 6545 |
25703 | | { PseudoVOR_VI_M1_MASK, VOR_VI }, // 6546 |
25704 | | { PseudoVOR_VI_M2, VOR_VI }, // 6547 |
25705 | | { PseudoVOR_VI_M2_MASK, VOR_VI }, // 6548 |
25706 | | { PseudoVOR_VI_M4, VOR_VI }, // 6549 |
25707 | | { PseudoVOR_VI_M4_MASK, VOR_VI }, // 6550 |
25708 | | { PseudoVOR_VI_M8, VOR_VI }, // 6551 |
25709 | | { PseudoVOR_VI_M8_MASK, VOR_VI }, // 6552 |
25710 | | { PseudoVOR_VI_MF2, VOR_VI }, // 6553 |
25711 | | { PseudoVOR_VI_MF2_MASK, VOR_VI }, // 6554 |
25712 | | { PseudoVOR_VI_MF4, VOR_VI }, // 6555 |
25713 | | { PseudoVOR_VI_MF4_MASK, VOR_VI }, // 6556 |
25714 | | { PseudoVOR_VI_MF8, VOR_VI }, // 6557 |
25715 | | { PseudoVOR_VI_MF8_MASK, VOR_VI }, // 6558 |
25716 | | { PseudoVOR_VV_M1, VOR_VV }, // 6559 |
25717 | | { PseudoVOR_VV_M1_MASK, VOR_VV }, // 6560 |
25718 | | { PseudoVOR_VV_M2, VOR_VV }, // 6561 |
25719 | | { PseudoVOR_VV_M2_MASK, VOR_VV }, // 6562 |
25720 | | { PseudoVOR_VV_M4, VOR_VV }, // 6563 |
25721 | | { PseudoVOR_VV_M4_MASK, VOR_VV }, // 6564 |
25722 | | { PseudoVOR_VV_M8, VOR_VV }, // 6565 |
25723 | | { PseudoVOR_VV_M8_MASK, VOR_VV }, // 6566 |
25724 | | { PseudoVOR_VV_MF2, VOR_VV }, // 6567 |
25725 | | { PseudoVOR_VV_MF2_MASK, VOR_VV }, // 6568 |
25726 | | { PseudoVOR_VV_MF4, VOR_VV }, // 6569 |
25727 | | { PseudoVOR_VV_MF4_MASK, VOR_VV }, // 6570 |
25728 | | { PseudoVOR_VV_MF8, VOR_VV }, // 6571 |
25729 | | { PseudoVOR_VV_MF8_MASK, VOR_VV }, // 6572 |
25730 | | { PseudoVOR_VX_M1, VOR_VX }, // 6573 |
25731 | | { PseudoVOR_VX_M1_MASK, VOR_VX }, // 6574 |
25732 | | { PseudoVOR_VX_M2, VOR_VX }, // 6575 |
25733 | | { PseudoVOR_VX_M2_MASK, VOR_VX }, // 6576 |
25734 | | { PseudoVOR_VX_M4, VOR_VX }, // 6577 |
25735 | | { PseudoVOR_VX_M4_MASK, VOR_VX }, // 6578 |
25736 | | { PseudoVOR_VX_M8, VOR_VX }, // 6579 |
25737 | | { PseudoVOR_VX_M8_MASK, VOR_VX }, // 6580 |
25738 | | { PseudoVOR_VX_MF2, VOR_VX }, // 6581 |
25739 | | { PseudoVOR_VX_MF2_MASK, VOR_VX }, // 6582 |
25740 | | { PseudoVOR_VX_MF4, VOR_VX }, // 6583 |
25741 | | { PseudoVOR_VX_MF4_MASK, VOR_VX }, // 6584 |
25742 | | { PseudoVOR_VX_MF8, VOR_VX }, // 6585 |
25743 | | { PseudoVOR_VX_MF8_MASK, VOR_VX }, // 6586 |
25744 | | { PseudoVQMACCSU_2x8x2_M1, VQMACCSU_2x8x2 }, // 6587 |
25745 | | { PseudoVQMACCSU_2x8x2_M2, VQMACCSU_2x8x2 }, // 6588 |
25746 | | { PseudoVQMACCSU_2x8x2_M4, VQMACCSU_2x8x2 }, // 6589 |
25747 | | { PseudoVQMACCSU_2x8x2_M8, VQMACCSU_2x8x2 }, // 6590 |
25748 | | { PseudoVQMACCSU_4x8x4_M1, VQMACCSU_4x8x4 }, // 6591 |
25749 | | { PseudoVQMACCSU_4x8x4_M2, VQMACCSU_4x8x4 }, // 6592 |
25750 | | { PseudoVQMACCSU_4x8x4_M4, VQMACCSU_4x8x4 }, // 6593 |
25751 | | { PseudoVQMACCSU_4x8x4_MF2, VQMACCSU_4x8x4 }, // 6594 |
25752 | | { PseudoVQMACCUS_2x8x2_M1, VQMACCUS_2x8x2 }, // 6595 |
25753 | | { PseudoVQMACCUS_2x8x2_M2, VQMACCUS_2x8x2 }, // 6596 |
25754 | | { PseudoVQMACCUS_2x8x2_M4, VQMACCUS_2x8x2 }, // 6597 |
25755 | | { PseudoVQMACCUS_2x8x2_M8, VQMACCUS_2x8x2 }, // 6598 |
25756 | | { PseudoVQMACCUS_4x8x4_M1, VQMACCUS_4x8x4 }, // 6599 |
25757 | | { PseudoVQMACCUS_4x8x4_M2, VQMACCUS_4x8x4 }, // 6600 |
25758 | | { PseudoVQMACCUS_4x8x4_M4, VQMACCUS_4x8x4 }, // 6601 |
25759 | | { PseudoVQMACCUS_4x8x4_MF2, VQMACCUS_4x8x4 }, // 6602 |
25760 | | { PseudoVQMACCU_2x8x2_M1, VQMACCU_2x8x2 }, // 6603 |
25761 | | { PseudoVQMACCU_2x8x2_M2, VQMACCU_2x8x2 }, // 6604 |
25762 | | { PseudoVQMACCU_2x8x2_M4, VQMACCU_2x8x2 }, // 6605 |
25763 | | { PseudoVQMACCU_2x8x2_M8, VQMACCU_2x8x2 }, // 6606 |
25764 | | { PseudoVQMACCU_4x8x4_M1, VQMACCU_4x8x4 }, // 6607 |
25765 | | { PseudoVQMACCU_4x8x4_M2, VQMACCU_4x8x4 }, // 6608 |
25766 | | { PseudoVQMACCU_4x8x4_M4, VQMACCU_4x8x4 }, // 6609 |
25767 | | { PseudoVQMACCU_4x8x4_MF2, VQMACCU_4x8x4 }, // 6610 |
25768 | | { PseudoVQMACC_2x8x2_M1, VQMACC_2x8x2 }, // 6611 |
25769 | | { PseudoVQMACC_2x8x2_M2, VQMACC_2x8x2 }, // 6612 |
25770 | | { PseudoVQMACC_2x8x2_M4, VQMACC_2x8x2 }, // 6613 |
25771 | | { PseudoVQMACC_2x8x2_M8, VQMACC_2x8x2 }, // 6614 |
25772 | | { PseudoVQMACC_4x8x4_M1, VQMACC_4x8x4 }, // 6615 |
25773 | | { PseudoVQMACC_4x8x4_M2, VQMACC_4x8x4 }, // 6616 |
25774 | | { PseudoVQMACC_4x8x4_M4, VQMACC_4x8x4 }, // 6617 |
25775 | | { PseudoVQMACC_4x8x4_MF2, VQMACC_4x8x4 }, // 6618 |
25776 | | { PseudoVREDAND_VS_M1_E16, VREDAND_VS }, // 6619 |
25777 | | { PseudoVREDAND_VS_M1_E16_MASK, VREDAND_VS }, // 6620 |
25778 | | { PseudoVREDAND_VS_M1_E32, VREDAND_VS }, // 6621 |
25779 | | { PseudoVREDAND_VS_M1_E32_MASK, VREDAND_VS }, // 6622 |
25780 | | { PseudoVREDAND_VS_M1_E64, VREDAND_VS }, // 6623 |
25781 | | { PseudoVREDAND_VS_M1_E64_MASK, VREDAND_VS }, // 6624 |
25782 | | { PseudoVREDAND_VS_M1_E8, VREDAND_VS }, // 6625 |
25783 | | { PseudoVREDAND_VS_M1_E8_MASK, VREDAND_VS }, // 6626 |
25784 | | { PseudoVREDAND_VS_M2_E16, VREDAND_VS }, // 6627 |
25785 | | { PseudoVREDAND_VS_M2_E16_MASK, VREDAND_VS }, // 6628 |
25786 | | { PseudoVREDAND_VS_M2_E32, VREDAND_VS }, // 6629 |
25787 | | { PseudoVREDAND_VS_M2_E32_MASK, VREDAND_VS }, // 6630 |
25788 | | { PseudoVREDAND_VS_M2_E64, VREDAND_VS }, // 6631 |
25789 | | { PseudoVREDAND_VS_M2_E64_MASK, VREDAND_VS }, // 6632 |
25790 | | { PseudoVREDAND_VS_M2_E8, VREDAND_VS }, // 6633 |
25791 | | { PseudoVREDAND_VS_M2_E8_MASK, VREDAND_VS }, // 6634 |
25792 | | { PseudoVREDAND_VS_M4_E16, VREDAND_VS }, // 6635 |
25793 | | { PseudoVREDAND_VS_M4_E16_MASK, VREDAND_VS }, // 6636 |
25794 | | { PseudoVREDAND_VS_M4_E32, VREDAND_VS }, // 6637 |
25795 | | { PseudoVREDAND_VS_M4_E32_MASK, VREDAND_VS }, // 6638 |
25796 | | { PseudoVREDAND_VS_M4_E64, VREDAND_VS }, // 6639 |
25797 | | { PseudoVREDAND_VS_M4_E64_MASK, VREDAND_VS }, // 6640 |
25798 | | { PseudoVREDAND_VS_M4_E8, VREDAND_VS }, // 6641 |
25799 | | { PseudoVREDAND_VS_M4_E8_MASK, VREDAND_VS }, // 6642 |
25800 | | { PseudoVREDAND_VS_M8_E16, VREDAND_VS }, // 6643 |
25801 | | { PseudoVREDAND_VS_M8_E16_MASK, VREDAND_VS }, // 6644 |
25802 | | { PseudoVREDAND_VS_M8_E32, VREDAND_VS }, // 6645 |
25803 | | { PseudoVREDAND_VS_M8_E32_MASK, VREDAND_VS }, // 6646 |
25804 | | { PseudoVREDAND_VS_M8_E64, VREDAND_VS }, // 6647 |
25805 | | { PseudoVREDAND_VS_M8_E64_MASK, VREDAND_VS }, // 6648 |
25806 | | { PseudoVREDAND_VS_M8_E8, VREDAND_VS }, // 6649 |
25807 | | { PseudoVREDAND_VS_M8_E8_MASK, VREDAND_VS }, // 6650 |
25808 | | { PseudoVREDAND_VS_MF2_E16, VREDAND_VS }, // 6651 |
25809 | | { PseudoVREDAND_VS_MF2_E16_MASK, VREDAND_VS }, // 6652 |
25810 | | { PseudoVREDAND_VS_MF2_E32, VREDAND_VS }, // 6653 |
25811 | | { PseudoVREDAND_VS_MF2_E32_MASK, VREDAND_VS }, // 6654 |
25812 | | { PseudoVREDAND_VS_MF2_E8, VREDAND_VS }, // 6655 |
25813 | | { PseudoVREDAND_VS_MF2_E8_MASK, VREDAND_VS }, // 6656 |
25814 | | { PseudoVREDAND_VS_MF4_E16, VREDAND_VS }, // 6657 |
25815 | | { PseudoVREDAND_VS_MF4_E16_MASK, VREDAND_VS }, // 6658 |
25816 | | { PseudoVREDAND_VS_MF4_E8, VREDAND_VS }, // 6659 |
25817 | | { PseudoVREDAND_VS_MF4_E8_MASK, VREDAND_VS }, // 6660 |
25818 | | { PseudoVREDAND_VS_MF8_E8, VREDAND_VS }, // 6661 |
25819 | | { PseudoVREDAND_VS_MF8_E8_MASK, VREDAND_VS }, // 6662 |
25820 | | { PseudoVREDMAXU_VS_M1_E16, VREDMAXU_VS }, // 6663 |
25821 | | { PseudoVREDMAXU_VS_M1_E16_MASK, VREDMAXU_VS }, // 6664 |
25822 | | { PseudoVREDMAXU_VS_M1_E32, VREDMAXU_VS }, // 6665 |
25823 | | { PseudoVREDMAXU_VS_M1_E32_MASK, VREDMAXU_VS }, // 6666 |
25824 | | { PseudoVREDMAXU_VS_M1_E64, VREDMAXU_VS }, // 6667 |
25825 | | { PseudoVREDMAXU_VS_M1_E64_MASK, VREDMAXU_VS }, // 6668 |
25826 | | { PseudoVREDMAXU_VS_M1_E8, VREDMAXU_VS }, // 6669 |
25827 | | { PseudoVREDMAXU_VS_M1_E8_MASK, VREDMAXU_VS }, // 6670 |
25828 | | { PseudoVREDMAXU_VS_M2_E16, VREDMAXU_VS }, // 6671 |
25829 | | { PseudoVREDMAXU_VS_M2_E16_MASK, VREDMAXU_VS }, // 6672 |
25830 | | { PseudoVREDMAXU_VS_M2_E32, VREDMAXU_VS }, // 6673 |
25831 | | { PseudoVREDMAXU_VS_M2_E32_MASK, VREDMAXU_VS }, // 6674 |
25832 | | { PseudoVREDMAXU_VS_M2_E64, VREDMAXU_VS }, // 6675 |
25833 | | { PseudoVREDMAXU_VS_M2_E64_MASK, VREDMAXU_VS }, // 6676 |
25834 | | { PseudoVREDMAXU_VS_M2_E8, VREDMAXU_VS }, // 6677 |
25835 | | { PseudoVREDMAXU_VS_M2_E8_MASK, VREDMAXU_VS }, // 6678 |
25836 | | { PseudoVREDMAXU_VS_M4_E16, VREDMAXU_VS }, // 6679 |
25837 | | { PseudoVREDMAXU_VS_M4_E16_MASK, VREDMAXU_VS }, // 6680 |
25838 | | { PseudoVREDMAXU_VS_M4_E32, VREDMAXU_VS }, // 6681 |
25839 | | { PseudoVREDMAXU_VS_M4_E32_MASK, VREDMAXU_VS }, // 6682 |
25840 | | { PseudoVREDMAXU_VS_M4_E64, VREDMAXU_VS }, // 6683 |
25841 | | { PseudoVREDMAXU_VS_M4_E64_MASK, VREDMAXU_VS }, // 6684 |
25842 | | { PseudoVREDMAXU_VS_M4_E8, VREDMAXU_VS }, // 6685 |
25843 | | { PseudoVREDMAXU_VS_M4_E8_MASK, VREDMAXU_VS }, // 6686 |
25844 | | { PseudoVREDMAXU_VS_M8_E16, VREDMAXU_VS }, // 6687 |
25845 | | { PseudoVREDMAXU_VS_M8_E16_MASK, VREDMAXU_VS }, // 6688 |
25846 | | { PseudoVREDMAXU_VS_M8_E32, VREDMAXU_VS }, // 6689 |
25847 | | { PseudoVREDMAXU_VS_M8_E32_MASK, VREDMAXU_VS }, // 6690 |
25848 | | { PseudoVREDMAXU_VS_M8_E64, VREDMAXU_VS }, // 6691 |
25849 | | { PseudoVREDMAXU_VS_M8_E64_MASK, VREDMAXU_VS }, // 6692 |
25850 | | { PseudoVREDMAXU_VS_M8_E8, VREDMAXU_VS }, // 6693 |
25851 | | { PseudoVREDMAXU_VS_M8_E8_MASK, VREDMAXU_VS }, // 6694 |
25852 | | { PseudoVREDMAXU_VS_MF2_E16, VREDMAXU_VS }, // 6695 |
25853 | | { PseudoVREDMAXU_VS_MF2_E16_MASK, VREDMAXU_VS }, // 6696 |
25854 | | { PseudoVREDMAXU_VS_MF2_E32, VREDMAXU_VS }, // 6697 |
25855 | | { PseudoVREDMAXU_VS_MF2_E32_MASK, VREDMAXU_VS }, // 6698 |
25856 | | { PseudoVREDMAXU_VS_MF2_E8, VREDMAXU_VS }, // 6699 |
25857 | | { PseudoVREDMAXU_VS_MF2_E8_MASK, VREDMAXU_VS }, // 6700 |
25858 | | { PseudoVREDMAXU_VS_MF4_E16, VREDMAXU_VS }, // 6701 |
25859 | | { PseudoVREDMAXU_VS_MF4_E16_MASK, VREDMAXU_VS }, // 6702 |
25860 | | { PseudoVREDMAXU_VS_MF4_E8, VREDMAXU_VS }, // 6703 |
25861 | | { PseudoVREDMAXU_VS_MF4_E8_MASK, VREDMAXU_VS }, // 6704 |
25862 | | { PseudoVREDMAXU_VS_MF8_E8, VREDMAXU_VS }, // 6705 |
25863 | | { PseudoVREDMAXU_VS_MF8_E8_MASK, VREDMAXU_VS }, // 6706 |
25864 | | { PseudoVREDMAX_VS_M1_E16, VREDMAX_VS }, // 6707 |
25865 | | { PseudoVREDMAX_VS_M1_E16_MASK, VREDMAX_VS }, // 6708 |
25866 | | { PseudoVREDMAX_VS_M1_E32, VREDMAX_VS }, // 6709 |
25867 | | { PseudoVREDMAX_VS_M1_E32_MASK, VREDMAX_VS }, // 6710 |
25868 | | { PseudoVREDMAX_VS_M1_E64, VREDMAX_VS }, // 6711 |
25869 | | { PseudoVREDMAX_VS_M1_E64_MASK, VREDMAX_VS }, // 6712 |
25870 | | { PseudoVREDMAX_VS_M1_E8, VREDMAX_VS }, // 6713 |
25871 | | { PseudoVREDMAX_VS_M1_E8_MASK, VREDMAX_VS }, // 6714 |
25872 | | { PseudoVREDMAX_VS_M2_E16, VREDMAX_VS }, // 6715 |
25873 | | { PseudoVREDMAX_VS_M2_E16_MASK, VREDMAX_VS }, // 6716 |
25874 | | { PseudoVREDMAX_VS_M2_E32, VREDMAX_VS }, // 6717 |
25875 | | { PseudoVREDMAX_VS_M2_E32_MASK, VREDMAX_VS }, // 6718 |
25876 | | { PseudoVREDMAX_VS_M2_E64, VREDMAX_VS }, // 6719 |
25877 | | { PseudoVREDMAX_VS_M2_E64_MASK, VREDMAX_VS }, // 6720 |
25878 | | { PseudoVREDMAX_VS_M2_E8, VREDMAX_VS }, // 6721 |
25879 | | { PseudoVREDMAX_VS_M2_E8_MASK, VREDMAX_VS }, // 6722 |
25880 | | { PseudoVREDMAX_VS_M4_E16, VREDMAX_VS }, // 6723 |
25881 | | { PseudoVREDMAX_VS_M4_E16_MASK, VREDMAX_VS }, // 6724 |
25882 | | { PseudoVREDMAX_VS_M4_E32, VREDMAX_VS }, // 6725 |
25883 | | { PseudoVREDMAX_VS_M4_E32_MASK, VREDMAX_VS }, // 6726 |
25884 | | { PseudoVREDMAX_VS_M4_E64, VREDMAX_VS }, // 6727 |
25885 | | { PseudoVREDMAX_VS_M4_E64_MASK, VREDMAX_VS }, // 6728 |
25886 | | { PseudoVREDMAX_VS_M4_E8, VREDMAX_VS }, // 6729 |
25887 | | { PseudoVREDMAX_VS_M4_E8_MASK, VREDMAX_VS }, // 6730 |
25888 | | { PseudoVREDMAX_VS_M8_E16, VREDMAX_VS }, // 6731 |
25889 | | { PseudoVREDMAX_VS_M8_E16_MASK, VREDMAX_VS }, // 6732 |
25890 | | { PseudoVREDMAX_VS_M8_E32, VREDMAX_VS }, // 6733 |
25891 | | { PseudoVREDMAX_VS_M8_E32_MASK, VREDMAX_VS }, // 6734 |
25892 | | { PseudoVREDMAX_VS_M8_E64, VREDMAX_VS }, // 6735 |
25893 | | { PseudoVREDMAX_VS_M8_E64_MASK, VREDMAX_VS }, // 6736 |
25894 | | { PseudoVREDMAX_VS_M8_E8, VREDMAX_VS }, // 6737 |
25895 | | { PseudoVREDMAX_VS_M8_E8_MASK, VREDMAX_VS }, // 6738 |
25896 | | { PseudoVREDMAX_VS_MF2_E16, VREDMAX_VS }, // 6739 |
25897 | | { PseudoVREDMAX_VS_MF2_E16_MASK, VREDMAX_VS }, // 6740 |
25898 | | { PseudoVREDMAX_VS_MF2_E32, VREDMAX_VS }, // 6741 |
25899 | | { PseudoVREDMAX_VS_MF2_E32_MASK, VREDMAX_VS }, // 6742 |
25900 | | { PseudoVREDMAX_VS_MF2_E8, VREDMAX_VS }, // 6743 |
25901 | | { PseudoVREDMAX_VS_MF2_E8_MASK, VREDMAX_VS }, // 6744 |
25902 | | { PseudoVREDMAX_VS_MF4_E16, VREDMAX_VS }, // 6745 |
25903 | | { PseudoVREDMAX_VS_MF4_E16_MASK, VREDMAX_VS }, // 6746 |
25904 | | { PseudoVREDMAX_VS_MF4_E8, VREDMAX_VS }, // 6747 |
25905 | | { PseudoVREDMAX_VS_MF4_E8_MASK, VREDMAX_VS }, // 6748 |
25906 | | { PseudoVREDMAX_VS_MF8_E8, VREDMAX_VS }, // 6749 |
25907 | | { PseudoVREDMAX_VS_MF8_E8_MASK, VREDMAX_VS }, // 6750 |
25908 | | { PseudoVREDMINU_VS_M1_E16, VREDMINU_VS }, // 6751 |
25909 | | { PseudoVREDMINU_VS_M1_E16_MASK, VREDMINU_VS }, // 6752 |
25910 | | { PseudoVREDMINU_VS_M1_E32, VREDMINU_VS }, // 6753 |
25911 | | { PseudoVREDMINU_VS_M1_E32_MASK, VREDMINU_VS }, // 6754 |
25912 | | { PseudoVREDMINU_VS_M1_E64, VREDMINU_VS }, // 6755 |
25913 | | { PseudoVREDMINU_VS_M1_E64_MASK, VREDMINU_VS }, // 6756 |
25914 | | { PseudoVREDMINU_VS_M1_E8, VREDMINU_VS }, // 6757 |
25915 | | { PseudoVREDMINU_VS_M1_E8_MASK, VREDMINU_VS }, // 6758 |
25916 | | { PseudoVREDMINU_VS_M2_E16, VREDMINU_VS }, // 6759 |
25917 | | { PseudoVREDMINU_VS_M2_E16_MASK, VREDMINU_VS }, // 6760 |
25918 | | { PseudoVREDMINU_VS_M2_E32, VREDMINU_VS }, // 6761 |
25919 | | { PseudoVREDMINU_VS_M2_E32_MASK, VREDMINU_VS }, // 6762 |
25920 | | { PseudoVREDMINU_VS_M2_E64, VREDMINU_VS }, // 6763 |
25921 | | { PseudoVREDMINU_VS_M2_E64_MASK, VREDMINU_VS }, // 6764 |
25922 | | { PseudoVREDMINU_VS_M2_E8, VREDMINU_VS }, // 6765 |
25923 | | { PseudoVREDMINU_VS_M2_E8_MASK, VREDMINU_VS }, // 6766 |
25924 | | { PseudoVREDMINU_VS_M4_E16, VREDMINU_VS }, // 6767 |
25925 | | { PseudoVREDMINU_VS_M4_E16_MASK, VREDMINU_VS }, // 6768 |
25926 | | { PseudoVREDMINU_VS_M4_E32, VREDMINU_VS }, // 6769 |
25927 | | { PseudoVREDMINU_VS_M4_E32_MASK, VREDMINU_VS }, // 6770 |
25928 | | { PseudoVREDMINU_VS_M4_E64, VREDMINU_VS }, // 6771 |
25929 | | { PseudoVREDMINU_VS_M4_E64_MASK, VREDMINU_VS }, // 6772 |
25930 | | { PseudoVREDMINU_VS_M4_E8, VREDMINU_VS }, // 6773 |
25931 | | { PseudoVREDMINU_VS_M4_E8_MASK, VREDMINU_VS }, // 6774 |
25932 | | { PseudoVREDMINU_VS_M8_E16, VREDMINU_VS }, // 6775 |
25933 | | { PseudoVREDMINU_VS_M8_E16_MASK, VREDMINU_VS }, // 6776 |
25934 | | { PseudoVREDMINU_VS_M8_E32, VREDMINU_VS }, // 6777 |
25935 | | { PseudoVREDMINU_VS_M8_E32_MASK, VREDMINU_VS }, // 6778 |
25936 | | { PseudoVREDMINU_VS_M8_E64, VREDMINU_VS }, // 6779 |
25937 | | { PseudoVREDMINU_VS_M8_E64_MASK, VREDMINU_VS }, // 6780 |
25938 | | { PseudoVREDMINU_VS_M8_E8, VREDMINU_VS }, // 6781 |
25939 | | { PseudoVREDMINU_VS_M8_E8_MASK, VREDMINU_VS }, // 6782 |
25940 | | { PseudoVREDMINU_VS_MF2_E16, VREDMINU_VS }, // 6783 |
25941 | | { PseudoVREDMINU_VS_MF2_E16_MASK, VREDMINU_VS }, // 6784 |
25942 | | { PseudoVREDMINU_VS_MF2_E32, VREDMINU_VS }, // 6785 |
25943 | | { PseudoVREDMINU_VS_MF2_E32_MASK, VREDMINU_VS }, // 6786 |
25944 | | { PseudoVREDMINU_VS_MF2_E8, VREDMINU_VS }, // 6787 |
25945 | | { PseudoVREDMINU_VS_MF2_E8_MASK, VREDMINU_VS }, // 6788 |
25946 | | { PseudoVREDMINU_VS_MF4_E16, VREDMINU_VS }, // 6789 |
25947 | | { PseudoVREDMINU_VS_MF4_E16_MASK, VREDMINU_VS }, // 6790 |
25948 | | { PseudoVREDMINU_VS_MF4_E8, VREDMINU_VS }, // 6791 |
25949 | | { PseudoVREDMINU_VS_MF4_E8_MASK, VREDMINU_VS }, // 6792 |
25950 | | { PseudoVREDMINU_VS_MF8_E8, VREDMINU_VS }, // 6793 |
25951 | | { PseudoVREDMINU_VS_MF8_E8_MASK, VREDMINU_VS }, // 6794 |
25952 | | { PseudoVREDMIN_VS_M1_E16, VREDMIN_VS }, // 6795 |
25953 | | { PseudoVREDMIN_VS_M1_E16_MASK, VREDMIN_VS }, // 6796 |
25954 | | { PseudoVREDMIN_VS_M1_E32, VREDMIN_VS }, // 6797 |
25955 | | { PseudoVREDMIN_VS_M1_E32_MASK, VREDMIN_VS }, // 6798 |
25956 | | { PseudoVREDMIN_VS_M1_E64, VREDMIN_VS }, // 6799 |
25957 | | { PseudoVREDMIN_VS_M1_E64_MASK, VREDMIN_VS }, // 6800 |
25958 | | { PseudoVREDMIN_VS_M1_E8, VREDMIN_VS }, // 6801 |
25959 | | { PseudoVREDMIN_VS_M1_E8_MASK, VREDMIN_VS }, // 6802 |
25960 | | { PseudoVREDMIN_VS_M2_E16, VREDMIN_VS }, // 6803 |
25961 | | { PseudoVREDMIN_VS_M2_E16_MASK, VREDMIN_VS }, // 6804 |
25962 | | { PseudoVREDMIN_VS_M2_E32, VREDMIN_VS }, // 6805 |
25963 | | { PseudoVREDMIN_VS_M2_E32_MASK, VREDMIN_VS }, // 6806 |
25964 | | { PseudoVREDMIN_VS_M2_E64, VREDMIN_VS }, // 6807 |
25965 | | { PseudoVREDMIN_VS_M2_E64_MASK, VREDMIN_VS }, // 6808 |
25966 | | { PseudoVREDMIN_VS_M2_E8, VREDMIN_VS }, // 6809 |
25967 | | { PseudoVREDMIN_VS_M2_E8_MASK, VREDMIN_VS }, // 6810 |
25968 | | { PseudoVREDMIN_VS_M4_E16, VREDMIN_VS }, // 6811 |
25969 | | { PseudoVREDMIN_VS_M4_E16_MASK, VREDMIN_VS }, // 6812 |
25970 | | { PseudoVREDMIN_VS_M4_E32, VREDMIN_VS }, // 6813 |
25971 | | { PseudoVREDMIN_VS_M4_E32_MASK, VREDMIN_VS }, // 6814 |
25972 | | { PseudoVREDMIN_VS_M4_E64, VREDMIN_VS }, // 6815 |
25973 | | { PseudoVREDMIN_VS_M4_E64_MASK, VREDMIN_VS }, // 6816 |
25974 | | { PseudoVREDMIN_VS_M4_E8, VREDMIN_VS }, // 6817 |
25975 | | { PseudoVREDMIN_VS_M4_E8_MASK, VREDMIN_VS }, // 6818 |
25976 | | { PseudoVREDMIN_VS_M8_E16, VREDMIN_VS }, // 6819 |
25977 | | { PseudoVREDMIN_VS_M8_E16_MASK, VREDMIN_VS }, // 6820 |
25978 | | { PseudoVREDMIN_VS_M8_E32, VREDMIN_VS }, // 6821 |
25979 | | { PseudoVREDMIN_VS_M8_E32_MASK, VREDMIN_VS }, // 6822 |
25980 | | { PseudoVREDMIN_VS_M8_E64, VREDMIN_VS }, // 6823 |
25981 | | { PseudoVREDMIN_VS_M8_E64_MASK, VREDMIN_VS }, // 6824 |
25982 | | { PseudoVREDMIN_VS_M8_E8, VREDMIN_VS }, // 6825 |
25983 | | { PseudoVREDMIN_VS_M8_E8_MASK, VREDMIN_VS }, // 6826 |
25984 | | { PseudoVREDMIN_VS_MF2_E16, VREDMIN_VS }, // 6827 |
25985 | | { PseudoVREDMIN_VS_MF2_E16_MASK, VREDMIN_VS }, // 6828 |
25986 | | { PseudoVREDMIN_VS_MF2_E32, VREDMIN_VS }, // 6829 |
25987 | | { PseudoVREDMIN_VS_MF2_E32_MASK, VREDMIN_VS }, // 6830 |
25988 | | { PseudoVREDMIN_VS_MF2_E8, VREDMIN_VS }, // 6831 |
25989 | | { PseudoVREDMIN_VS_MF2_E8_MASK, VREDMIN_VS }, // 6832 |
25990 | | { PseudoVREDMIN_VS_MF4_E16, VREDMIN_VS }, // 6833 |
25991 | | { PseudoVREDMIN_VS_MF4_E16_MASK, VREDMIN_VS }, // 6834 |
25992 | | { PseudoVREDMIN_VS_MF4_E8, VREDMIN_VS }, // 6835 |
25993 | | { PseudoVREDMIN_VS_MF4_E8_MASK, VREDMIN_VS }, // 6836 |
25994 | | { PseudoVREDMIN_VS_MF8_E8, VREDMIN_VS }, // 6837 |
25995 | | { PseudoVREDMIN_VS_MF8_E8_MASK, VREDMIN_VS }, // 6838 |
25996 | | { PseudoVREDOR_VS_M1_E16, VREDOR_VS }, // 6839 |
25997 | | { PseudoVREDOR_VS_M1_E16_MASK, VREDOR_VS }, // 6840 |
25998 | | { PseudoVREDOR_VS_M1_E32, VREDOR_VS }, // 6841 |
25999 | | { PseudoVREDOR_VS_M1_E32_MASK, VREDOR_VS }, // 6842 |
26000 | | { PseudoVREDOR_VS_M1_E64, VREDOR_VS }, // 6843 |
26001 | | { PseudoVREDOR_VS_M1_E64_MASK, VREDOR_VS }, // 6844 |
26002 | | { PseudoVREDOR_VS_M1_E8, VREDOR_VS }, // 6845 |
26003 | | { PseudoVREDOR_VS_M1_E8_MASK, VREDOR_VS }, // 6846 |
26004 | | { PseudoVREDOR_VS_M2_E16, VREDOR_VS }, // 6847 |
26005 | | { PseudoVREDOR_VS_M2_E16_MASK, VREDOR_VS }, // 6848 |
26006 | | { PseudoVREDOR_VS_M2_E32, VREDOR_VS }, // 6849 |
26007 | | { PseudoVREDOR_VS_M2_E32_MASK, VREDOR_VS }, // 6850 |
26008 | | { PseudoVREDOR_VS_M2_E64, VREDOR_VS }, // 6851 |
26009 | | { PseudoVREDOR_VS_M2_E64_MASK, VREDOR_VS }, // 6852 |
26010 | | { PseudoVREDOR_VS_M2_E8, VREDOR_VS }, // 6853 |
26011 | | { PseudoVREDOR_VS_M2_E8_MASK, VREDOR_VS }, // 6854 |
26012 | | { PseudoVREDOR_VS_M4_E16, VREDOR_VS }, // 6855 |
26013 | | { PseudoVREDOR_VS_M4_E16_MASK, VREDOR_VS }, // 6856 |
26014 | | { PseudoVREDOR_VS_M4_E32, VREDOR_VS }, // 6857 |
26015 | | { PseudoVREDOR_VS_M4_E32_MASK, VREDOR_VS }, // 6858 |
26016 | | { PseudoVREDOR_VS_M4_E64, VREDOR_VS }, // 6859 |
26017 | | { PseudoVREDOR_VS_M4_E64_MASK, VREDOR_VS }, // 6860 |
26018 | | { PseudoVREDOR_VS_M4_E8, VREDOR_VS }, // 6861 |
26019 | | { PseudoVREDOR_VS_M4_E8_MASK, VREDOR_VS }, // 6862 |
26020 | | { PseudoVREDOR_VS_M8_E16, VREDOR_VS }, // 6863 |
26021 | | { PseudoVREDOR_VS_M8_E16_MASK, VREDOR_VS }, // 6864 |
26022 | | { PseudoVREDOR_VS_M8_E32, VREDOR_VS }, // 6865 |
26023 | | { PseudoVREDOR_VS_M8_E32_MASK, VREDOR_VS }, // 6866 |
26024 | | { PseudoVREDOR_VS_M8_E64, VREDOR_VS }, // 6867 |
26025 | | { PseudoVREDOR_VS_M8_E64_MASK, VREDOR_VS }, // 6868 |
26026 | | { PseudoVREDOR_VS_M8_E8, VREDOR_VS }, // 6869 |
26027 | | { PseudoVREDOR_VS_M8_E8_MASK, VREDOR_VS }, // 6870 |
26028 | | { PseudoVREDOR_VS_MF2_E16, VREDOR_VS }, // 6871 |
26029 | | { PseudoVREDOR_VS_MF2_E16_MASK, VREDOR_VS }, // 6872 |
26030 | | { PseudoVREDOR_VS_MF2_E32, VREDOR_VS }, // 6873 |
26031 | | { PseudoVREDOR_VS_MF2_E32_MASK, VREDOR_VS }, // 6874 |
26032 | | { PseudoVREDOR_VS_MF2_E8, VREDOR_VS }, // 6875 |
26033 | | { PseudoVREDOR_VS_MF2_E8_MASK, VREDOR_VS }, // 6876 |
26034 | | { PseudoVREDOR_VS_MF4_E16, VREDOR_VS }, // 6877 |
26035 | | { PseudoVREDOR_VS_MF4_E16_MASK, VREDOR_VS }, // 6878 |
26036 | | { PseudoVREDOR_VS_MF4_E8, VREDOR_VS }, // 6879 |
26037 | | { PseudoVREDOR_VS_MF4_E8_MASK, VREDOR_VS }, // 6880 |
26038 | | { PseudoVREDOR_VS_MF8_E8, VREDOR_VS }, // 6881 |
26039 | | { PseudoVREDOR_VS_MF8_E8_MASK, VREDOR_VS }, // 6882 |
26040 | | { PseudoVREDSUM_VS_M1_E16, VREDSUM_VS }, // 6883 |
26041 | | { PseudoVREDSUM_VS_M1_E16_MASK, VREDSUM_VS }, // 6884 |
26042 | | { PseudoVREDSUM_VS_M1_E32, VREDSUM_VS }, // 6885 |
26043 | | { PseudoVREDSUM_VS_M1_E32_MASK, VREDSUM_VS }, // 6886 |
26044 | | { PseudoVREDSUM_VS_M1_E64, VREDSUM_VS }, // 6887 |
26045 | | { PseudoVREDSUM_VS_M1_E64_MASK, VREDSUM_VS }, // 6888 |
26046 | | { PseudoVREDSUM_VS_M1_E8, VREDSUM_VS }, // 6889 |
26047 | | { PseudoVREDSUM_VS_M1_E8_MASK, VREDSUM_VS }, // 6890 |
26048 | | { PseudoVREDSUM_VS_M2_E16, VREDSUM_VS }, // 6891 |
26049 | | { PseudoVREDSUM_VS_M2_E16_MASK, VREDSUM_VS }, // 6892 |
26050 | | { PseudoVREDSUM_VS_M2_E32, VREDSUM_VS }, // 6893 |
26051 | | { PseudoVREDSUM_VS_M2_E32_MASK, VREDSUM_VS }, // 6894 |
26052 | | { PseudoVREDSUM_VS_M2_E64, VREDSUM_VS }, // 6895 |
26053 | | { PseudoVREDSUM_VS_M2_E64_MASK, VREDSUM_VS }, // 6896 |
26054 | | { PseudoVREDSUM_VS_M2_E8, VREDSUM_VS }, // 6897 |
26055 | | { PseudoVREDSUM_VS_M2_E8_MASK, VREDSUM_VS }, // 6898 |
26056 | | { PseudoVREDSUM_VS_M4_E16, VREDSUM_VS }, // 6899 |
26057 | | { PseudoVREDSUM_VS_M4_E16_MASK, VREDSUM_VS }, // 6900 |
26058 | | { PseudoVREDSUM_VS_M4_E32, VREDSUM_VS }, // 6901 |
26059 | | { PseudoVREDSUM_VS_M4_E32_MASK, VREDSUM_VS }, // 6902 |
26060 | | { PseudoVREDSUM_VS_M4_E64, VREDSUM_VS }, // 6903 |
26061 | | { PseudoVREDSUM_VS_M4_E64_MASK, VREDSUM_VS }, // 6904 |
26062 | | { PseudoVREDSUM_VS_M4_E8, VREDSUM_VS }, // 6905 |
26063 | | { PseudoVREDSUM_VS_M4_E8_MASK, VREDSUM_VS }, // 6906 |
26064 | | { PseudoVREDSUM_VS_M8_E16, VREDSUM_VS }, // 6907 |
26065 | | { PseudoVREDSUM_VS_M8_E16_MASK, VREDSUM_VS }, // 6908 |
26066 | | { PseudoVREDSUM_VS_M8_E32, VREDSUM_VS }, // 6909 |
26067 | | { PseudoVREDSUM_VS_M8_E32_MASK, VREDSUM_VS }, // 6910 |
26068 | | { PseudoVREDSUM_VS_M8_E64, VREDSUM_VS }, // 6911 |
26069 | | { PseudoVREDSUM_VS_M8_E64_MASK, VREDSUM_VS }, // 6912 |
26070 | | { PseudoVREDSUM_VS_M8_E8, VREDSUM_VS }, // 6913 |
26071 | | { PseudoVREDSUM_VS_M8_E8_MASK, VREDSUM_VS }, // 6914 |
26072 | | { PseudoVREDSUM_VS_MF2_E16, VREDSUM_VS }, // 6915 |
26073 | | { PseudoVREDSUM_VS_MF2_E16_MASK, VREDSUM_VS }, // 6916 |
26074 | | { PseudoVREDSUM_VS_MF2_E32, VREDSUM_VS }, // 6917 |
26075 | | { PseudoVREDSUM_VS_MF2_E32_MASK, VREDSUM_VS }, // 6918 |
26076 | | { PseudoVREDSUM_VS_MF2_E8, VREDSUM_VS }, // 6919 |
26077 | | { PseudoVREDSUM_VS_MF2_E8_MASK, VREDSUM_VS }, // 6920 |
26078 | | { PseudoVREDSUM_VS_MF4_E16, VREDSUM_VS }, // 6921 |
26079 | | { PseudoVREDSUM_VS_MF4_E16_MASK, VREDSUM_VS }, // 6922 |
26080 | | { PseudoVREDSUM_VS_MF4_E8, VREDSUM_VS }, // 6923 |
26081 | | { PseudoVREDSUM_VS_MF4_E8_MASK, VREDSUM_VS }, // 6924 |
26082 | | { PseudoVREDSUM_VS_MF8_E8, VREDSUM_VS }, // 6925 |
26083 | | { PseudoVREDSUM_VS_MF8_E8_MASK, VREDSUM_VS }, // 6926 |
26084 | | { PseudoVREDXOR_VS_M1_E16, VREDXOR_VS }, // 6927 |
26085 | | { PseudoVREDXOR_VS_M1_E16_MASK, VREDXOR_VS }, // 6928 |
26086 | | { PseudoVREDXOR_VS_M1_E32, VREDXOR_VS }, // 6929 |
26087 | | { PseudoVREDXOR_VS_M1_E32_MASK, VREDXOR_VS }, // 6930 |
26088 | | { PseudoVREDXOR_VS_M1_E64, VREDXOR_VS }, // 6931 |
26089 | | { PseudoVREDXOR_VS_M1_E64_MASK, VREDXOR_VS }, // 6932 |
26090 | | { PseudoVREDXOR_VS_M1_E8, VREDXOR_VS }, // 6933 |
26091 | | { PseudoVREDXOR_VS_M1_E8_MASK, VREDXOR_VS }, // 6934 |
26092 | | { PseudoVREDXOR_VS_M2_E16, VREDXOR_VS }, // 6935 |
26093 | | { PseudoVREDXOR_VS_M2_E16_MASK, VREDXOR_VS }, // 6936 |
26094 | | { PseudoVREDXOR_VS_M2_E32, VREDXOR_VS }, // 6937 |
26095 | | { PseudoVREDXOR_VS_M2_E32_MASK, VREDXOR_VS }, // 6938 |
26096 | | { PseudoVREDXOR_VS_M2_E64, VREDXOR_VS }, // 6939 |
26097 | | { PseudoVREDXOR_VS_M2_E64_MASK, VREDXOR_VS }, // 6940 |
26098 | | { PseudoVREDXOR_VS_M2_E8, VREDXOR_VS }, // 6941 |
26099 | | { PseudoVREDXOR_VS_M2_E8_MASK, VREDXOR_VS }, // 6942 |
26100 | | { PseudoVREDXOR_VS_M4_E16, VREDXOR_VS }, // 6943 |
26101 | | { PseudoVREDXOR_VS_M4_E16_MASK, VREDXOR_VS }, // 6944 |
26102 | | { PseudoVREDXOR_VS_M4_E32, VREDXOR_VS }, // 6945 |
26103 | | { PseudoVREDXOR_VS_M4_E32_MASK, VREDXOR_VS }, // 6946 |
26104 | | { PseudoVREDXOR_VS_M4_E64, VREDXOR_VS }, // 6947 |
26105 | | { PseudoVREDXOR_VS_M4_E64_MASK, VREDXOR_VS }, // 6948 |
26106 | | { PseudoVREDXOR_VS_M4_E8, VREDXOR_VS }, // 6949 |
26107 | | { PseudoVREDXOR_VS_M4_E8_MASK, VREDXOR_VS }, // 6950 |
26108 | | { PseudoVREDXOR_VS_M8_E16, VREDXOR_VS }, // 6951 |
26109 | | { PseudoVREDXOR_VS_M8_E16_MASK, VREDXOR_VS }, // 6952 |
26110 | | { PseudoVREDXOR_VS_M8_E32, VREDXOR_VS }, // 6953 |
26111 | | { PseudoVREDXOR_VS_M8_E32_MASK, VREDXOR_VS }, // 6954 |
26112 | | { PseudoVREDXOR_VS_M8_E64, VREDXOR_VS }, // 6955 |
26113 | | { PseudoVREDXOR_VS_M8_E64_MASK, VREDXOR_VS }, // 6956 |
26114 | | { PseudoVREDXOR_VS_M8_E8, VREDXOR_VS }, // 6957 |
26115 | | { PseudoVREDXOR_VS_M8_E8_MASK, VREDXOR_VS }, // 6958 |
26116 | | { PseudoVREDXOR_VS_MF2_E16, VREDXOR_VS }, // 6959 |
26117 | | { PseudoVREDXOR_VS_MF2_E16_MASK, VREDXOR_VS }, // 6960 |
26118 | | { PseudoVREDXOR_VS_MF2_E32, VREDXOR_VS }, // 6961 |
26119 | | { PseudoVREDXOR_VS_MF2_E32_MASK, VREDXOR_VS }, // 6962 |
26120 | | { PseudoVREDXOR_VS_MF2_E8, VREDXOR_VS }, // 6963 |
26121 | | { PseudoVREDXOR_VS_MF2_E8_MASK, VREDXOR_VS }, // 6964 |
26122 | | { PseudoVREDXOR_VS_MF4_E16, VREDXOR_VS }, // 6965 |
26123 | | { PseudoVREDXOR_VS_MF4_E16_MASK, VREDXOR_VS }, // 6966 |
26124 | | { PseudoVREDXOR_VS_MF4_E8, VREDXOR_VS }, // 6967 |
26125 | | { PseudoVREDXOR_VS_MF4_E8_MASK, VREDXOR_VS }, // 6968 |
26126 | | { PseudoVREDXOR_VS_MF8_E8, VREDXOR_VS }, // 6969 |
26127 | | { PseudoVREDXOR_VS_MF8_E8_MASK, VREDXOR_VS }, // 6970 |
26128 | | { PseudoVREMU_VV_M1_E16, VREMU_VV }, // 6971 |
26129 | | { PseudoVREMU_VV_M1_E16_MASK, VREMU_VV }, // 6972 |
26130 | | { PseudoVREMU_VV_M1_E32, VREMU_VV }, // 6973 |
26131 | | { PseudoVREMU_VV_M1_E32_MASK, VREMU_VV }, // 6974 |
26132 | | { PseudoVREMU_VV_M1_E64, VREMU_VV }, // 6975 |
26133 | | { PseudoVREMU_VV_M1_E64_MASK, VREMU_VV }, // 6976 |
26134 | | { PseudoVREMU_VV_M1_E8, VREMU_VV }, // 6977 |
26135 | | { PseudoVREMU_VV_M1_E8_MASK, VREMU_VV }, // 6978 |
26136 | | { PseudoVREMU_VV_M2_E16, VREMU_VV }, // 6979 |
26137 | | { PseudoVREMU_VV_M2_E16_MASK, VREMU_VV }, // 6980 |
26138 | | { PseudoVREMU_VV_M2_E32, VREMU_VV }, // 6981 |
26139 | | { PseudoVREMU_VV_M2_E32_MASK, VREMU_VV }, // 6982 |
26140 | | { PseudoVREMU_VV_M2_E64, VREMU_VV }, // 6983 |
26141 | | { PseudoVREMU_VV_M2_E64_MASK, VREMU_VV }, // 6984 |
26142 | | { PseudoVREMU_VV_M2_E8, VREMU_VV }, // 6985 |
26143 | | { PseudoVREMU_VV_M2_E8_MASK, VREMU_VV }, // 6986 |
26144 | | { PseudoVREMU_VV_M4_E16, VREMU_VV }, // 6987 |
26145 | | { PseudoVREMU_VV_M4_E16_MASK, VREMU_VV }, // 6988 |
26146 | | { PseudoVREMU_VV_M4_E32, VREMU_VV }, // 6989 |
26147 | | { PseudoVREMU_VV_M4_E32_MASK, VREMU_VV }, // 6990 |
26148 | | { PseudoVREMU_VV_M4_E64, VREMU_VV }, // 6991 |
26149 | | { PseudoVREMU_VV_M4_E64_MASK, VREMU_VV }, // 6992 |
26150 | | { PseudoVREMU_VV_M4_E8, VREMU_VV }, // 6993 |
26151 | | { PseudoVREMU_VV_M4_E8_MASK, VREMU_VV }, // 6994 |
26152 | | { PseudoVREMU_VV_M8_E16, VREMU_VV }, // 6995 |
26153 | | { PseudoVREMU_VV_M8_E16_MASK, VREMU_VV }, // 6996 |
26154 | | { PseudoVREMU_VV_M8_E32, VREMU_VV }, // 6997 |
26155 | | { PseudoVREMU_VV_M8_E32_MASK, VREMU_VV }, // 6998 |
26156 | | { PseudoVREMU_VV_M8_E64, VREMU_VV }, // 6999 |
26157 | | { PseudoVREMU_VV_M8_E64_MASK, VREMU_VV }, // 7000 |
26158 | | { PseudoVREMU_VV_M8_E8, VREMU_VV }, // 7001 |
26159 | | { PseudoVREMU_VV_M8_E8_MASK, VREMU_VV }, // 7002 |
26160 | | { PseudoVREMU_VV_MF2_E16, VREMU_VV }, // 7003 |
26161 | | { PseudoVREMU_VV_MF2_E16_MASK, VREMU_VV }, // 7004 |
26162 | | { PseudoVREMU_VV_MF2_E32, VREMU_VV }, // 7005 |
26163 | | { PseudoVREMU_VV_MF2_E32_MASK, VREMU_VV }, // 7006 |
26164 | | { PseudoVREMU_VV_MF2_E8, VREMU_VV }, // 7007 |
26165 | | { PseudoVREMU_VV_MF2_E8_MASK, VREMU_VV }, // 7008 |
26166 | | { PseudoVREMU_VV_MF4_E16, VREMU_VV }, // 7009 |
26167 | | { PseudoVREMU_VV_MF4_E16_MASK, VREMU_VV }, // 7010 |
26168 | | { PseudoVREMU_VV_MF4_E8, VREMU_VV }, // 7011 |
26169 | | { PseudoVREMU_VV_MF4_E8_MASK, VREMU_VV }, // 7012 |
26170 | | { PseudoVREMU_VV_MF8_E8, VREMU_VV }, // 7013 |
26171 | | { PseudoVREMU_VV_MF8_E8_MASK, VREMU_VV }, // 7014 |
26172 | | { PseudoVREMU_VX_M1_E16, VREMU_VX }, // 7015 |
26173 | | { PseudoVREMU_VX_M1_E16_MASK, VREMU_VX }, // 7016 |
26174 | | { PseudoVREMU_VX_M1_E32, VREMU_VX }, // 7017 |
26175 | | { PseudoVREMU_VX_M1_E32_MASK, VREMU_VX }, // 7018 |
26176 | | { PseudoVREMU_VX_M1_E64, VREMU_VX }, // 7019 |
26177 | | { PseudoVREMU_VX_M1_E64_MASK, VREMU_VX }, // 7020 |
26178 | | { PseudoVREMU_VX_M1_E8, VREMU_VX }, // 7021 |
26179 | | { PseudoVREMU_VX_M1_E8_MASK, VREMU_VX }, // 7022 |
26180 | | { PseudoVREMU_VX_M2_E16, VREMU_VX }, // 7023 |
26181 | | { PseudoVREMU_VX_M2_E16_MASK, VREMU_VX }, // 7024 |
26182 | | { PseudoVREMU_VX_M2_E32, VREMU_VX }, // 7025 |
26183 | | { PseudoVREMU_VX_M2_E32_MASK, VREMU_VX }, // 7026 |
26184 | | { PseudoVREMU_VX_M2_E64, VREMU_VX }, // 7027 |
26185 | | { PseudoVREMU_VX_M2_E64_MASK, VREMU_VX }, // 7028 |
26186 | | { PseudoVREMU_VX_M2_E8, VREMU_VX }, // 7029 |
26187 | | { PseudoVREMU_VX_M2_E8_MASK, VREMU_VX }, // 7030 |
26188 | | { PseudoVREMU_VX_M4_E16, VREMU_VX }, // 7031 |
26189 | | { PseudoVREMU_VX_M4_E16_MASK, VREMU_VX }, // 7032 |
26190 | | { PseudoVREMU_VX_M4_E32, VREMU_VX }, // 7033 |
26191 | | { PseudoVREMU_VX_M4_E32_MASK, VREMU_VX }, // 7034 |
26192 | | { PseudoVREMU_VX_M4_E64, VREMU_VX }, // 7035 |
26193 | | { PseudoVREMU_VX_M4_E64_MASK, VREMU_VX }, // 7036 |
26194 | | { PseudoVREMU_VX_M4_E8, VREMU_VX }, // 7037 |
26195 | | { PseudoVREMU_VX_M4_E8_MASK, VREMU_VX }, // 7038 |
26196 | | { PseudoVREMU_VX_M8_E16, VREMU_VX }, // 7039 |
26197 | | { PseudoVREMU_VX_M8_E16_MASK, VREMU_VX }, // 7040 |
26198 | | { PseudoVREMU_VX_M8_E32, VREMU_VX }, // 7041 |
26199 | | { PseudoVREMU_VX_M8_E32_MASK, VREMU_VX }, // 7042 |
26200 | | { PseudoVREMU_VX_M8_E64, VREMU_VX }, // 7043 |
26201 | | { PseudoVREMU_VX_M8_E64_MASK, VREMU_VX }, // 7044 |
26202 | | { PseudoVREMU_VX_M8_E8, VREMU_VX }, // 7045 |
26203 | | { PseudoVREMU_VX_M8_E8_MASK, VREMU_VX }, // 7046 |
26204 | | { PseudoVREMU_VX_MF2_E16, VREMU_VX }, // 7047 |
26205 | | { PseudoVREMU_VX_MF2_E16_MASK, VREMU_VX }, // 7048 |
26206 | | { PseudoVREMU_VX_MF2_E32, VREMU_VX }, // 7049 |
26207 | | { PseudoVREMU_VX_MF2_E32_MASK, VREMU_VX }, // 7050 |
26208 | | { PseudoVREMU_VX_MF2_E8, VREMU_VX }, // 7051 |
26209 | | { PseudoVREMU_VX_MF2_E8_MASK, VREMU_VX }, // 7052 |
26210 | | { PseudoVREMU_VX_MF4_E16, VREMU_VX }, // 7053 |
26211 | | { PseudoVREMU_VX_MF4_E16_MASK, VREMU_VX }, // 7054 |
26212 | | { PseudoVREMU_VX_MF4_E8, VREMU_VX }, // 7055 |
26213 | | { PseudoVREMU_VX_MF4_E8_MASK, VREMU_VX }, // 7056 |
26214 | | { PseudoVREMU_VX_MF8_E8, VREMU_VX }, // 7057 |
26215 | | { PseudoVREMU_VX_MF8_E8_MASK, VREMU_VX }, // 7058 |
26216 | | { PseudoVREM_VV_M1_E16, VREM_VV }, // 7059 |
26217 | | { PseudoVREM_VV_M1_E16_MASK, VREM_VV }, // 7060 |
26218 | | { PseudoVREM_VV_M1_E32, VREM_VV }, // 7061 |
26219 | | { PseudoVREM_VV_M1_E32_MASK, VREM_VV }, // 7062 |
26220 | | { PseudoVREM_VV_M1_E64, VREM_VV }, // 7063 |
26221 | | { PseudoVREM_VV_M1_E64_MASK, VREM_VV }, // 7064 |
26222 | | { PseudoVREM_VV_M1_E8, VREM_VV }, // 7065 |
26223 | | { PseudoVREM_VV_M1_E8_MASK, VREM_VV }, // 7066 |
26224 | | { PseudoVREM_VV_M2_E16, VREM_VV }, // 7067 |
26225 | | { PseudoVREM_VV_M2_E16_MASK, VREM_VV }, // 7068 |
26226 | | { PseudoVREM_VV_M2_E32, VREM_VV }, // 7069 |
26227 | | { PseudoVREM_VV_M2_E32_MASK, VREM_VV }, // 7070 |
26228 | | { PseudoVREM_VV_M2_E64, VREM_VV }, // 7071 |
26229 | | { PseudoVREM_VV_M2_E64_MASK, VREM_VV }, // 7072 |
26230 | | { PseudoVREM_VV_M2_E8, VREM_VV }, // 7073 |
26231 | | { PseudoVREM_VV_M2_E8_MASK, VREM_VV }, // 7074 |
26232 | | { PseudoVREM_VV_M4_E16, VREM_VV }, // 7075 |
26233 | | { PseudoVREM_VV_M4_E16_MASK, VREM_VV }, // 7076 |
26234 | | { PseudoVREM_VV_M4_E32, VREM_VV }, // 7077 |
26235 | | { PseudoVREM_VV_M4_E32_MASK, VREM_VV }, // 7078 |
26236 | | { PseudoVREM_VV_M4_E64, VREM_VV }, // 7079 |
26237 | | { PseudoVREM_VV_M4_E64_MASK, VREM_VV }, // 7080 |
26238 | | { PseudoVREM_VV_M4_E8, VREM_VV }, // 7081 |
26239 | | { PseudoVREM_VV_M4_E8_MASK, VREM_VV }, // 7082 |
26240 | | { PseudoVREM_VV_M8_E16, VREM_VV }, // 7083 |
26241 | | { PseudoVREM_VV_M8_E16_MASK, VREM_VV }, // 7084 |
26242 | | { PseudoVREM_VV_M8_E32, VREM_VV }, // 7085 |
26243 | | { PseudoVREM_VV_M8_E32_MASK, VREM_VV }, // 7086 |
26244 | | { PseudoVREM_VV_M8_E64, VREM_VV }, // 7087 |
26245 | | { PseudoVREM_VV_M8_E64_MASK, VREM_VV }, // 7088 |
26246 | | { PseudoVREM_VV_M8_E8, VREM_VV }, // 7089 |
26247 | | { PseudoVREM_VV_M8_E8_MASK, VREM_VV }, // 7090 |
26248 | | { PseudoVREM_VV_MF2_E16, VREM_VV }, // 7091 |
26249 | | { PseudoVREM_VV_MF2_E16_MASK, VREM_VV }, // 7092 |
26250 | | { PseudoVREM_VV_MF2_E32, VREM_VV }, // 7093 |
26251 | | { PseudoVREM_VV_MF2_E32_MASK, VREM_VV }, // 7094 |
26252 | | { PseudoVREM_VV_MF2_E8, VREM_VV }, // 7095 |
26253 | | { PseudoVREM_VV_MF2_E8_MASK, VREM_VV }, // 7096 |
26254 | | { PseudoVREM_VV_MF4_E16, VREM_VV }, // 7097 |
26255 | | { PseudoVREM_VV_MF4_E16_MASK, VREM_VV }, // 7098 |
26256 | | { PseudoVREM_VV_MF4_E8, VREM_VV }, // 7099 |
26257 | | { PseudoVREM_VV_MF4_E8_MASK, VREM_VV }, // 7100 |
26258 | | { PseudoVREM_VV_MF8_E8, VREM_VV }, // 7101 |
26259 | | { PseudoVREM_VV_MF8_E8_MASK, VREM_VV }, // 7102 |
26260 | | { PseudoVREM_VX_M1_E16, VREM_VX }, // 7103 |
26261 | | { PseudoVREM_VX_M1_E16_MASK, VREM_VX }, // 7104 |
26262 | | { PseudoVREM_VX_M1_E32, VREM_VX }, // 7105 |
26263 | | { PseudoVREM_VX_M1_E32_MASK, VREM_VX }, // 7106 |
26264 | | { PseudoVREM_VX_M1_E64, VREM_VX }, // 7107 |
26265 | | { PseudoVREM_VX_M1_E64_MASK, VREM_VX }, // 7108 |
26266 | | { PseudoVREM_VX_M1_E8, VREM_VX }, // 7109 |
26267 | | { PseudoVREM_VX_M1_E8_MASK, VREM_VX }, // 7110 |
26268 | | { PseudoVREM_VX_M2_E16, VREM_VX }, // 7111 |
26269 | | { PseudoVREM_VX_M2_E16_MASK, VREM_VX }, // 7112 |
26270 | | { PseudoVREM_VX_M2_E32, VREM_VX }, // 7113 |
26271 | | { PseudoVREM_VX_M2_E32_MASK, VREM_VX }, // 7114 |
26272 | | { PseudoVREM_VX_M2_E64, VREM_VX }, // 7115 |
26273 | | { PseudoVREM_VX_M2_E64_MASK, VREM_VX }, // 7116 |
26274 | | { PseudoVREM_VX_M2_E8, VREM_VX }, // 7117 |
26275 | | { PseudoVREM_VX_M2_E8_MASK, VREM_VX }, // 7118 |
26276 | | { PseudoVREM_VX_M4_E16, VREM_VX }, // 7119 |
26277 | | { PseudoVREM_VX_M4_E16_MASK, VREM_VX }, // 7120 |
26278 | | { PseudoVREM_VX_M4_E32, VREM_VX }, // 7121 |
26279 | | { PseudoVREM_VX_M4_E32_MASK, VREM_VX }, // 7122 |
26280 | | { PseudoVREM_VX_M4_E64, VREM_VX }, // 7123 |
26281 | | { PseudoVREM_VX_M4_E64_MASK, VREM_VX }, // 7124 |
26282 | | { PseudoVREM_VX_M4_E8, VREM_VX }, // 7125 |
26283 | | { PseudoVREM_VX_M4_E8_MASK, VREM_VX }, // 7126 |
26284 | | { PseudoVREM_VX_M8_E16, VREM_VX }, // 7127 |
26285 | | { PseudoVREM_VX_M8_E16_MASK, VREM_VX }, // 7128 |
26286 | | { PseudoVREM_VX_M8_E32, VREM_VX }, // 7129 |
26287 | | { PseudoVREM_VX_M8_E32_MASK, VREM_VX }, // 7130 |
26288 | | { PseudoVREM_VX_M8_E64, VREM_VX }, // 7131 |
26289 | | { PseudoVREM_VX_M8_E64_MASK, VREM_VX }, // 7132 |
26290 | | { PseudoVREM_VX_M8_E8, VREM_VX }, // 7133 |
26291 | | { PseudoVREM_VX_M8_E8_MASK, VREM_VX }, // 7134 |
26292 | | { PseudoVREM_VX_MF2_E16, VREM_VX }, // 7135 |
26293 | | { PseudoVREM_VX_MF2_E16_MASK, VREM_VX }, // 7136 |
26294 | | { PseudoVREM_VX_MF2_E32, VREM_VX }, // 7137 |
26295 | | { PseudoVREM_VX_MF2_E32_MASK, VREM_VX }, // 7138 |
26296 | | { PseudoVREM_VX_MF2_E8, VREM_VX }, // 7139 |
26297 | | { PseudoVREM_VX_MF2_E8_MASK, VREM_VX }, // 7140 |
26298 | | { PseudoVREM_VX_MF4_E16, VREM_VX }, // 7141 |
26299 | | { PseudoVREM_VX_MF4_E16_MASK, VREM_VX }, // 7142 |
26300 | | { PseudoVREM_VX_MF4_E8, VREM_VX }, // 7143 |
26301 | | { PseudoVREM_VX_MF4_E8_MASK, VREM_VX }, // 7144 |
26302 | | { PseudoVREM_VX_MF8_E8, VREM_VX }, // 7145 |
26303 | | { PseudoVREM_VX_MF8_E8_MASK, VREM_VX }, // 7146 |
26304 | | { PseudoVREV8_V_M1, VREV8_V }, // 7147 |
26305 | | { PseudoVREV8_V_M1_MASK, VREV8_V }, // 7148 |
26306 | | { PseudoVREV8_V_M2, VREV8_V }, // 7149 |
26307 | | { PseudoVREV8_V_M2_MASK, VREV8_V }, // 7150 |
26308 | | { PseudoVREV8_V_M4, VREV8_V }, // 7151 |
26309 | | { PseudoVREV8_V_M4_MASK, VREV8_V }, // 7152 |
26310 | | { PseudoVREV8_V_M8, VREV8_V }, // 7153 |
26311 | | { PseudoVREV8_V_M8_MASK, VREV8_V }, // 7154 |
26312 | | { PseudoVREV8_V_MF2, VREV8_V }, // 7155 |
26313 | | { PseudoVREV8_V_MF2_MASK, VREV8_V }, // 7156 |
26314 | | { PseudoVREV8_V_MF4, VREV8_V }, // 7157 |
26315 | | { PseudoVREV8_V_MF4_MASK, VREV8_V }, // 7158 |
26316 | | { PseudoVREV8_V_MF8, VREV8_V }, // 7159 |
26317 | | { PseudoVREV8_V_MF8_MASK, VREV8_V }, // 7160 |
26318 | | { PseudoVRGATHEREI16_VV_M1_E16_M1, VRGATHEREI16_VV }, // 7161 |
26319 | | { PseudoVRGATHEREI16_VV_M1_E16_M1_MASK, VRGATHEREI16_VV }, // 7162 |
26320 | | { PseudoVRGATHEREI16_VV_M1_E16_M2, VRGATHEREI16_VV }, // 7163 |
26321 | | { PseudoVRGATHEREI16_VV_M1_E16_M2_MASK, VRGATHEREI16_VV }, // 7164 |
26322 | | { PseudoVRGATHEREI16_VV_M1_E16_MF2, VRGATHEREI16_VV }, // 7165 |
26323 | | { PseudoVRGATHEREI16_VV_M1_E16_MF2_MASK, VRGATHEREI16_VV }, // 7166 |
26324 | | { PseudoVRGATHEREI16_VV_M1_E16_MF4, VRGATHEREI16_VV }, // 7167 |
26325 | | { PseudoVRGATHEREI16_VV_M1_E16_MF4_MASK, VRGATHEREI16_VV }, // 7168 |
26326 | | { PseudoVRGATHEREI16_VV_M1_E32_M1, VRGATHEREI16_VV }, // 7169 |
26327 | | { PseudoVRGATHEREI16_VV_M1_E32_M1_MASK, VRGATHEREI16_VV }, // 7170 |
26328 | | { PseudoVRGATHEREI16_VV_M1_E32_M2, VRGATHEREI16_VV }, // 7171 |
26329 | | { PseudoVRGATHEREI16_VV_M1_E32_M2_MASK, VRGATHEREI16_VV }, // 7172 |
26330 | | { PseudoVRGATHEREI16_VV_M1_E32_MF2, VRGATHEREI16_VV }, // 7173 |
26331 | | { PseudoVRGATHEREI16_VV_M1_E32_MF2_MASK, VRGATHEREI16_VV }, // 7174 |
26332 | | { PseudoVRGATHEREI16_VV_M1_E32_MF4, VRGATHEREI16_VV }, // 7175 |
26333 | | { PseudoVRGATHEREI16_VV_M1_E32_MF4_MASK, VRGATHEREI16_VV }, // 7176 |
26334 | | { PseudoVRGATHEREI16_VV_M1_E64_M1, VRGATHEREI16_VV }, // 7177 |
26335 | | { PseudoVRGATHEREI16_VV_M1_E64_M1_MASK, VRGATHEREI16_VV }, // 7178 |
26336 | | { PseudoVRGATHEREI16_VV_M1_E64_M2, VRGATHEREI16_VV }, // 7179 |
26337 | | { PseudoVRGATHEREI16_VV_M1_E64_M2_MASK, VRGATHEREI16_VV }, // 7180 |
26338 | | { PseudoVRGATHEREI16_VV_M1_E64_MF2, VRGATHEREI16_VV }, // 7181 |
26339 | | { PseudoVRGATHEREI16_VV_M1_E64_MF2_MASK, VRGATHEREI16_VV }, // 7182 |
26340 | | { PseudoVRGATHEREI16_VV_M1_E64_MF4, VRGATHEREI16_VV }, // 7183 |
26341 | | { PseudoVRGATHEREI16_VV_M1_E64_MF4_MASK, VRGATHEREI16_VV }, // 7184 |
26342 | | { PseudoVRGATHEREI16_VV_M1_E8_M1, VRGATHEREI16_VV }, // 7185 |
26343 | | { PseudoVRGATHEREI16_VV_M1_E8_M1_MASK, VRGATHEREI16_VV }, // 7186 |
26344 | | { PseudoVRGATHEREI16_VV_M1_E8_M2, VRGATHEREI16_VV }, // 7187 |
26345 | | { PseudoVRGATHEREI16_VV_M1_E8_M2_MASK, VRGATHEREI16_VV }, // 7188 |
26346 | | { PseudoVRGATHEREI16_VV_M1_E8_MF2, VRGATHEREI16_VV }, // 7189 |
26347 | | { PseudoVRGATHEREI16_VV_M1_E8_MF2_MASK, VRGATHEREI16_VV }, // 7190 |
26348 | | { PseudoVRGATHEREI16_VV_M1_E8_MF4, VRGATHEREI16_VV }, // 7191 |
26349 | | { PseudoVRGATHEREI16_VV_M1_E8_MF4_MASK, VRGATHEREI16_VV }, // 7192 |
26350 | | { PseudoVRGATHEREI16_VV_M2_E16_M1, VRGATHEREI16_VV }, // 7193 |
26351 | | { PseudoVRGATHEREI16_VV_M2_E16_M1_MASK, VRGATHEREI16_VV }, // 7194 |
26352 | | { PseudoVRGATHEREI16_VV_M2_E16_M2, VRGATHEREI16_VV }, // 7195 |
26353 | | { PseudoVRGATHEREI16_VV_M2_E16_M2_MASK, VRGATHEREI16_VV }, // 7196 |
26354 | | { PseudoVRGATHEREI16_VV_M2_E16_M4, VRGATHEREI16_VV }, // 7197 |
26355 | | { PseudoVRGATHEREI16_VV_M2_E16_M4_MASK, VRGATHEREI16_VV }, // 7198 |
26356 | | { PseudoVRGATHEREI16_VV_M2_E16_MF2, VRGATHEREI16_VV }, // 7199 |
26357 | | { PseudoVRGATHEREI16_VV_M2_E16_MF2_MASK, VRGATHEREI16_VV }, // 7200 |
26358 | | { PseudoVRGATHEREI16_VV_M2_E32_M1, VRGATHEREI16_VV }, // 7201 |
26359 | | { PseudoVRGATHEREI16_VV_M2_E32_M1_MASK, VRGATHEREI16_VV }, // 7202 |
26360 | | { PseudoVRGATHEREI16_VV_M2_E32_M2, VRGATHEREI16_VV }, // 7203 |
26361 | | { PseudoVRGATHEREI16_VV_M2_E32_M2_MASK, VRGATHEREI16_VV }, // 7204 |
26362 | | { PseudoVRGATHEREI16_VV_M2_E32_M4, VRGATHEREI16_VV }, // 7205 |
26363 | | { PseudoVRGATHEREI16_VV_M2_E32_M4_MASK, VRGATHEREI16_VV }, // 7206 |
26364 | | { PseudoVRGATHEREI16_VV_M2_E32_MF2, VRGATHEREI16_VV }, // 7207 |
26365 | | { PseudoVRGATHEREI16_VV_M2_E32_MF2_MASK, VRGATHEREI16_VV }, // 7208 |
26366 | | { PseudoVRGATHEREI16_VV_M2_E64_M1, VRGATHEREI16_VV }, // 7209 |
26367 | | { PseudoVRGATHEREI16_VV_M2_E64_M1_MASK, VRGATHEREI16_VV }, // 7210 |
26368 | | { PseudoVRGATHEREI16_VV_M2_E64_M2, VRGATHEREI16_VV }, // 7211 |
26369 | | { PseudoVRGATHEREI16_VV_M2_E64_M2_MASK, VRGATHEREI16_VV }, // 7212 |
26370 | | { PseudoVRGATHEREI16_VV_M2_E64_M4, VRGATHEREI16_VV }, // 7213 |
26371 | | { PseudoVRGATHEREI16_VV_M2_E64_M4_MASK, VRGATHEREI16_VV }, // 7214 |
26372 | | { PseudoVRGATHEREI16_VV_M2_E64_MF2, VRGATHEREI16_VV }, // 7215 |
26373 | | { PseudoVRGATHEREI16_VV_M2_E64_MF2_MASK, VRGATHEREI16_VV }, // 7216 |
26374 | | { PseudoVRGATHEREI16_VV_M2_E8_M1, VRGATHEREI16_VV }, // 7217 |
26375 | | { PseudoVRGATHEREI16_VV_M2_E8_M1_MASK, VRGATHEREI16_VV }, // 7218 |
26376 | | { PseudoVRGATHEREI16_VV_M2_E8_M2, VRGATHEREI16_VV }, // 7219 |
26377 | | { PseudoVRGATHEREI16_VV_M2_E8_M2_MASK, VRGATHEREI16_VV }, // 7220 |
26378 | | { PseudoVRGATHEREI16_VV_M2_E8_M4, VRGATHEREI16_VV }, // 7221 |
26379 | | { PseudoVRGATHEREI16_VV_M2_E8_M4_MASK, VRGATHEREI16_VV }, // 7222 |
26380 | | { PseudoVRGATHEREI16_VV_M2_E8_MF2, VRGATHEREI16_VV }, // 7223 |
26381 | | { PseudoVRGATHEREI16_VV_M2_E8_MF2_MASK, VRGATHEREI16_VV }, // 7224 |
26382 | | { PseudoVRGATHEREI16_VV_M4_E16_M1, VRGATHEREI16_VV }, // 7225 |
26383 | | { PseudoVRGATHEREI16_VV_M4_E16_M1_MASK, VRGATHEREI16_VV }, // 7226 |
26384 | | { PseudoVRGATHEREI16_VV_M4_E16_M2, VRGATHEREI16_VV }, // 7227 |
26385 | | { PseudoVRGATHEREI16_VV_M4_E16_M2_MASK, VRGATHEREI16_VV }, // 7228 |
26386 | | { PseudoVRGATHEREI16_VV_M4_E16_M4, VRGATHEREI16_VV }, // 7229 |
26387 | | { PseudoVRGATHEREI16_VV_M4_E16_M4_MASK, VRGATHEREI16_VV }, // 7230 |
26388 | | { PseudoVRGATHEREI16_VV_M4_E16_M8, VRGATHEREI16_VV }, // 7231 |
26389 | | { PseudoVRGATHEREI16_VV_M4_E16_M8_MASK, VRGATHEREI16_VV }, // 7232 |
26390 | | { PseudoVRGATHEREI16_VV_M4_E32_M1, VRGATHEREI16_VV }, // 7233 |
26391 | | { PseudoVRGATHEREI16_VV_M4_E32_M1_MASK, VRGATHEREI16_VV }, // 7234 |
26392 | | { PseudoVRGATHEREI16_VV_M4_E32_M2, VRGATHEREI16_VV }, // 7235 |
26393 | | { PseudoVRGATHEREI16_VV_M4_E32_M2_MASK, VRGATHEREI16_VV }, // 7236 |
26394 | | { PseudoVRGATHEREI16_VV_M4_E32_M4, VRGATHEREI16_VV }, // 7237 |
26395 | | { PseudoVRGATHEREI16_VV_M4_E32_M4_MASK, VRGATHEREI16_VV }, // 7238 |
26396 | | { PseudoVRGATHEREI16_VV_M4_E32_M8, VRGATHEREI16_VV }, // 7239 |
26397 | | { PseudoVRGATHEREI16_VV_M4_E32_M8_MASK, VRGATHEREI16_VV }, // 7240 |
26398 | | { PseudoVRGATHEREI16_VV_M4_E64_M1, VRGATHEREI16_VV }, // 7241 |
26399 | | { PseudoVRGATHEREI16_VV_M4_E64_M1_MASK, VRGATHEREI16_VV }, // 7242 |
26400 | | { PseudoVRGATHEREI16_VV_M4_E64_M2, VRGATHEREI16_VV }, // 7243 |
26401 | | { PseudoVRGATHEREI16_VV_M4_E64_M2_MASK, VRGATHEREI16_VV }, // 7244 |
26402 | | { PseudoVRGATHEREI16_VV_M4_E64_M4, VRGATHEREI16_VV }, // 7245 |
26403 | | { PseudoVRGATHEREI16_VV_M4_E64_M4_MASK, VRGATHEREI16_VV }, // 7246 |
26404 | | { PseudoVRGATHEREI16_VV_M4_E64_M8, VRGATHEREI16_VV }, // 7247 |
26405 | | { PseudoVRGATHEREI16_VV_M4_E64_M8_MASK, VRGATHEREI16_VV }, // 7248 |
26406 | | { PseudoVRGATHEREI16_VV_M4_E8_M1, VRGATHEREI16_VV }, // 7249 |
26407 | | { PseudoVRGATHEREI16_VV_M4_E8_M1_MASK, VRGATHEREI16_VV }, // 7250 |
26408 | | { PseudoVRGATHEREI16_VV_M4_E8_M2, VRGATHEREI16_VV }, // 7251 |
26409 | | { PseudoVRGATHEREI16_VV_M4_E8_M2_MASK, VRGATHEREI16_VV }, // 7252 |
26410 | | { PseudoVRGATHEREI16_VV_M4_E8_M4, VRGATHEREI16_VV }, // 7253 |
26411 | | { PseudoVRGATHEREI16_VV_M4_E8_M4_MASK, VRGATHEREI16_VV }, // 7254 |
26412 | | { PseudoVRGATHEREI16_VV_M4_E8_M8, VRGATHEREI16_VV }, // 7255 |
26413 | | { PseudoVRGATHEREI16_VV_M4_E8_M8_MASK, VRGATHEREI16_VV }, // 7256 |
26414 | | { PseudoVRGATHEREI16_VV_M8_E16_M2, VRGATHEREI16_VV }, // 7257 |
26415 | | { PseudoVRGATHEREI16_VV_M8_E16_M2_MASK, VRGATHEREI16_VV }, // 7258 |
26416 | | { PseudoVRGATHEREI16_VV_M8_E16_M4, VRGATHEREI16_VV }, // 7259 |
26417 | | { PseudoVRGATHEREI16_VV_M8_E16_M4_MASK, VRGATHEREI16_VV }, // 7260 |
26418 | | { PseudoVRGATHEREI16_VV_M8_E16_M8, VRGATHEREI16_VV }, // 7261 |
26419 | | { PseudoVRGATHEREI16_VV_M8_E16_M8_MASK, VRGATHEREI16_VV }, // 7262 |
26420 | | { PseudoVRGATHEREI16_VV_M8_E32_M2, VRGATHEREI16_VV }, // 7263 |
26421 | | { PseudoVRGATHEREI16_VV_M8_E32_M2_MASK, VRGATHEREI16_VV }, // 7264 |
26422 | | { PseudoVRGATHEREI16_VV_M8_E32_M4, VRGATHEREI16_VV }, // 7265 |
26423 | | { PseudoVRGATHEREI16_VV_M8_E32_M4_MASK, VRGATHEREI16_VV }, // 7266 |
26424 | | { PseudoVRGATHEREI16_VV_M8_E32_M8, VRGATHEREI16_VV }, // 7267 |
26425 | | { PseudoVRGATHEREI16_VV_M8_E32_M8_MASK, VRGATHEREI16_VV }, // 7268 |
26426 | | { PseudoVRGATHEREI16_VV_M8_E64_M2, VRGATHEREI16_VV }, // 7269 |
26427 | | { PseudoVRGATHEREI16_VV_M8_E64_M2_MASK, VRGATHEREI16_VV }, // 7270 |
26428 | | { PseudoVRGATHEREI16_VV_M8_E64_M4, VRGATHEREI16_VV }, // 7271 |
26429 | | { PseudoVRGATHEREI16_VV_M8_E64_M4_MASK, VRGATHEREI16_VV }, // 7272 |
26430 | | { PseudoVRGATHEREI16_VV_M8_E64_M8, VRGATHEREI16_VV }, // 7273 |
26431 | | { PseudoVRGATHEREI16_VV_M8_E64_M8_MASK, VRGATHEREI16_VV }, // 7274 |
26432 | | { PseudoVRGATHEREI16_VV_M8_E8_M2, VRGATHEREI16_VV }, // 7275 |
26433 | | { PseudoVRGATHEREI16_VV_M8_E8_M2_MASK, VRGATHEREI16_VV }, // 7276 |
26434 | | { PseudoVRGATHEREI16_VV_M8_E8_M4, VRGATHEREI16_VV }, // 7277 |
26435 | | { PseudoVRGATHEREI16_VV_M8_E8_M4_MASK, VRGATHEREI16_VV }, // 7278 |
26436 | | { PseudoVRGATHEREI16_VV_M8_E8_M8, VRGATHEREI16_VV }, // 7279 |
26437 | | { PseudoVRGATHEREI16_VV_M8_E8_M8_MASK, VRGATHEREI16_VV }, // 7280 |
26438 | | { PseudoVRGATHEREI16_VV_MF2_E16_M1, VRGATHEREI16_VV }, // 7281 |
26439 | | { PseudoVRGATHEREI16_VV_MF2_E16_M1_MASK, VRGATHEREI16_VV }, // 7282 |
26440 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF2, VRGATHEREI16_VV }, // 7283 |
26441 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF2_MASK, VRGATHEREI16_VV }, // 7284 |
26442 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF4, VRGATHEREI16_VV }, // 7285 |
26443 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF4_MASK, VRGATHEREI16_VV }, // 7286 |
26444 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF8, VRGATHEREI16_VV }, // 7287 |
26445 | | { PseudoVRGATHEREI16_VV_MF2_E16_MF8_MASK, VRGATHEREI16_VV }, // 7288 |
26446 | | { PseudoVRGATHEREI16_VV_MF2_E32_M1, VRGATHEREI16_VV }, // 7289 |
26447 | | { PseudoVRGATHEREI16_VV_MF2_E32_M1_MASK, VRGATHEREI16_VV }, // 7290 |
26448 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF2, VRGATHEREI16_VV }, // 7291 |
26449 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF2_MASK, VRGATHEREI16_VV }, // 7292 |
26450 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF4, VRGATHEREI16_VV }, // 7293 |
26451 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF4_MASK, VRGATHEREI16_VV }, // 7294 |
26452 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF8, VRGATHEREI16_VV }, // 7295 |
26453 | | { PseudoVRGATHEREI16_VV_MF2_E32_MF8_MASK, VRGATHEREI16_VV }, // 7296 |
26454 | | { PseudoVRGATHEREI16_VV_MF2_E8_M1, VRGATHEREI16_VV }, // 7297 |
26455 | | { PseudoVRGATHEREI16_VV_MF2_E8_M1_MASK, VRGATHEREI16_VV }, // 7298 |
26456 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF2, VRGATHEREI16_VV }, // 7299 |
26457 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF2_MASK, VRGATHEREI16_VV }, // 7300 |
26458 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF4, VRGATHEREI16_VV }, // 7301 |
26459 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF4_MASK, VRGATHEREI16_VV }, // 7302 |
26460 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF8, VRGATHEREI16_VV }, // 7303 |
26461 | | { PseudoVRGATHEREI16_VV_MF2_E8_MF8_MASK, VRGATHEREI16_VV }, // 7304 |
26462 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF2, VRGATHEREI16_VV }, // 7305 |
26463 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF2_MASK, VRGATHEREI16_VV }, // 7306 |
26464 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF4, VRGATHEREI16_VV }, // 7307 |
26465 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF4_MASK, VRGATHEREI16_VV }, // 7308 |
26466 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF8, VRGATHEREI16_VV }, // 7309 |
26467 | | { PseudoVRGATHEREI16_VV_MF4_E16_MF8_MASK, VRGATHEREI16_VV }, // 7310 |
26468 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF2, VRGATHEREI16_VV }, // 7311 |
26469 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF2_MASK, VRGATHEREI16_VV }, // 7312 |
26470 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF4, VRGATHEREI16_VV }, // 7313 |
26471 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF4_MASK, VRGATHEREI16_VV }, // 7314 |
26472 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF8, VRGATHEREI16_VV }, // 7315 |
26473 | | { PseudoVRGATHEREI16_VV_MF4_E8_MF8_MASK, VRGATHEREI16_VV }, // 7316 |
26474 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF4, VRGATHEREI16_VV }, // 7317 |
26475 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF4_MASK, VRGATHEREI16_VV }, // 7318 |
26476 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF8, VRGATHEREI16_VV }, // 7319 |
26477 | | { PseudoVRGATHEREI16_VV_MF8_E8_MF8_MASK, VRGATHEREI16_VV }, // 7320 |
26478 | | { PseudoVRGATHER_VI_M1, VRGATHER_VI }, // 7321 |
26479 | | { PseudoVRGATHER_VI_M1_MASK, VRGATHER_VI }, // 7322 |
26480 | | { PseudoVRGATHER_VI_M2, VRGATHER_VI }, // 7323 |
26481 | | { PseudoVRGATHER_VI_M2_MASK, VRGATHER_VI }, // 7324 |
26482 | | { PseudoVRGATHER_VI_M4, VRGATHER_VI }, // 7325 |
26483 | | { PseudoVRGATHER_VI_M4_MASK, VRGATHER_VI }, // 7326 |
26484 | | { PseudoVRGATHER_VI_M8, VRGATHER_VI }, // 7327 |
26485 | | { PseudoVRGATHER_VI_M8_MASK, VRGATHER_VI }, // 7328 |
26486 | | { PseudoVRGATHER_VI_MF2, VRGATHER_VI }, // 7329 |
26487 | | { PseudoVRGATHER_VI_MF2_MASK, VRGATHER_VI }, // 7330 |
26488 | | { PseudoVRGATHER_VI_MF4, VRGATHER_VI }, // 7331 |
26489 | | { PseudoVRGATHER_VI_MF4_MASK, VRGATHER_VI }, // 7332 |
26490 | | { PseudoVRGATHER_VI_MF8, VRGATHER_VI }, // 7333 |
26491 | | { PseudoVRGATHER_VI_MF8_MASK, VRGATHER_VI }, // 7334 |
26492 | | { PseudoVRGATHER_VV_M1_E16, VRGATHER_VV }, // 7335 |
26493 | | { PseudoVRGATHER_VV_M1_E16_MASK, VRGATHER_VV }, // 7336 |
26494 | | { PseudoVRGATHER_VV_M1_E32, VRGATHER_VV }, // 7337 |
26495 | | { PseudoVRGATHER_VV_M1_E32_MASK, VRGATHER_VV }, // 7338 |
26496 | | { PseudoVRGATHER_VV_M1_E64, VRGATHER_VV }, // 7339 |
26497 | | { PseudoVRGATHER_VV_M1_E64_MASK, VRGATHER_VV }, // 7340 |
26498 | | { PseudoVRGATHER_VV_M1_E8, VRGATHER_VV }, // 7341 |
26499 | | { PseudoVRGATHER_VV_M1_E8_MASK, VRGATHER_VV }, // 7342 |
26500 | | { PseudoVRGATHER_VV_M2_E16, VRGATHER_VV }, // 7343 |
26501 | | { PseudoVRGATHER_VV_M2_E16_MASK, VRGATHER_VV }, // 7344 |
26502 | | { PseudoVRGATHER_VV_M2_E32, VRGATHER_VV }, // 7345 |
26503 | | { PseudoVRGATHER_VV_M2_E32_MASK, VRGATHER_VV }, // 7346 |
26504 | | { PseudoVRGATHER_VV_M2_E64, VRGATHER_VV }, // 7347 |
26505 | | { PseudoVRGATHER_VV_M2_E64_MASK, VRGATHER_VV }, // 7348 |
26506 | | { PseudoVRGATHER_VV_M2_E8, VRGATHER_VV }, // 7349 |
26507 | | { PseudoVRGATHER_VV_M2_E8_MASK, VRGATHER_VV }, // 7350 |
26508 | | { PseudoVRGATHER_VV_M4_E16, VRGATHER_VV }, // 7351 |
26509 | | { PseudoVRGATHER_VV_M4_E16_MASK, VRGATHER_VV }, // 7352 |
26510 | | { PseudoVRGATHER_VV_M4_E32, VRGATHER_VV }, // 7353 |
26511 | | { PseudoVRGATHER_VV_M4_E32_MASK, VRGATHER_VV }, // 7354 |
26512 | | { PseudoVRGATHER_VV_M4_E64, VRGATHER_VV }, // 7355 |
26513 | | { PseudoVRGATHER_VV_M4_E64_MASK, VRGATHER_VV }, // 7356 |
26514 | | { PseudoVRGATHER_VV_M4_E8, VRGATHER_VV }, // 7357 |
26515 | | { PseudoVRGATHER_VV_M4_E8_MASK, VRGATHER_VV }, // 7358 |
26516 | | { PseudoVRGATHER_VV_M8_E16, VRGATHER_VV }, // 7359 |
26517 | | { PseudoVRGATHER_VV_M8_E16_MASK, VRGATHER_VV }, // 7360 |
26518 | | { PseudoVRGATHER_VV_M8_E32, VRGATHER_VV }, // 7361 |
26519 | | { PseudoVRGATHER_VV_M8_E32_MASK, VRGATHER_VV }, // 7362 |
26520 | | { PseudoVRGATHER_VV_M8_E64, VRGATHER_VV }, // 7363 |
26521 | | { PseudoVRGATHER_VV_M8_E64_MASK, VRGATHER_VV }, // 7364 |
26522 | | { PseudoVRGATHER_VV_M8_E8, VRGATHER_VV }, // 7365 |
26523 | | { PseudoVRGATHER_VV_M8_E8_MASK, VRGATHER_VV }, // 7366 |
26524 | | { PseudoVRGATHER_VV_MF2_E16, VRGATHER_VV }, // 7367 |
26525 | | { PseudoVRGATHER_VV_MF2_E16_MASK, VRGATHER_VV }, // 7368 |
26526 | | { PseudoVRGATHER_VV_MF2_E32, VRGATHER_VV }, // 7369 |
26527 | | { PseudoVRGATHER_VV_MF2_E32_MASK, VRGATHER_VV }, // 7370 |
26528 | | { PseudoVRGATHER_VV_MF2_E8, VRGATHER_VV }, // 7371 |
26529 | | { PseudoVRGATHER_VV_MF2_E8_MASK, VRGATHER_VV }, // 7372 |
26530 | | { PseudoVRGATHER_VV_MF4_E16, VRGATHER_VV }, // 7373 |
26531 | | { PseudoVRGATHER_VV_MF4_E16_MASK, VRGATHER_VV }, // 7374 |
26532 | | { PseudoVRGATHER_VV_MF4_E8, VRGATHER_VV }, // 7375 |
26533 | | { PseudoVRGATHER_VV_MF4_E8_MASK, VRGATHER_VV }, // 7376 |
26534 | | { PseudoVRGATHER_VV_MF8_E8, VRGATHER_VV }, // 7377 |
26535 | | { PseudoVRGATHER_VV_MF8_E8_MASK, VRGATHER_VV }, // 7378 |
26536 | | { PseudoVRGATHER_VX_M1, VRGATHER_VX }, // 7379 |
26537 | | { PseudoVRGATHER_VX_M1_MASK, VRGATHER_VX }, // 7380 |
26538 | | { PseudoVRGATHER_VX_M2, VRGATHER_VX }, // 7381 |
26539 | | { PseudoVRGATHER_VX_M2_MASK, VRGATHER_VX }, // 7382 |
26540 | | { PseudoVRGATHER_VX_M4, VRGATHER_VX }, // 7383 |
26541 | | { PseudoVRGATHER_VX_M4_MASK, VRGATHER_VX }, // 7384 |
26542 | | { PseudoVRGATHER_VX_M8, VRGATHER_VX }, // 7385 |
26543 | | { PseudoVRGATHER_VX_M8_MASK, VRGATHER_VX }, // 7386 |
26544 | | { PseudoVRGATHER_VX_MF2, VRGATHER_VX }, // 7387 |
26545 | | { PseudoVRGATHER_VX_MF2_MASK, VRGATHER_VX }, // 7388 |
26546 | | { PseudoVRGATHER_VX_MF4, VRGATHER_VX }, // 7389 |
26547 | | { PseudoVRGATHER_VX_MF4_MASK, VRGATHER_VX }, // 7390 |
26548 | | { PseudoVRGATHER_VX_MF8, VRGATHER_VX }, // 7391 |
26549 | | { PseudoVRGATHER_VX_MF8_MASK, VRGATHER_VX }, // 7392 |
26550 | | { PseudoVROL_VV_M1, VROL_VV }, // 7393 |
26551 | | { PseudoVROL_VV_M1_MASK, VROL_VV }, // 7394 |
26552 | | { PseudoVROL_VV_M2, VROL_VV }, // 7395 |
26553 | | { PseudoVROL_VV_M2_MASK, VROL_VV }, // 7396 |
26554 | | { PseudoVROL_VV_M4, VROL_VV }, // 7397 |
26555 | | { PseudoVROL_VV_M4_MASK, VROL_VV }, // 7398 |
26556 | | { PseudoVROL_VV_M8, VROL_VV }, // 7399 |
26557 | | { PseudoVROL_VV_M8_MASK, VROL_VV }, // 7400 |
26558 | | { PseudoVROL_VV_MF2, VROL_VV }, // 7401 |
26559 | | { PseudoVROL_VV_MF2_MASK, VROL_VV }, // 7402 |
26560 | | { PseudoVROL_VV_MF4, VROL_VV }, // 7403 |
26561 | | { PseudoVROL_VV_MF4_MASK, VROL_VV }, // 7404 |
26562 | | { PseudoVROL_VV_MF8, VROL_VV }, // 7405 |
26563 | | { PseudoVROL_VV_MF8_MASK, VROL_VV }, // 7406 |
26564 | | { PseudoVROL_VX_M1, VROL_VX }, // 7407 |
26565 | | { PseudoVROL_VX_M1_MASK, VROL_VX }, // 7408 |
26566 | | { PseudoVROL_VX_M2, VROL_VX }, // 7409 |
26567 | | { PseudoVROL_VX_M2_MASK, VROL_VX }, // 7410 |
26568 | | { PseudoVROL_VX_M4, VROL_VX }, // 7411 |
26569 | | { PseudoVROL_VX_M4_MASK, VROL_VX }, // 7412 |
26570 | | { PseudoVROL_VX_M8, VROL_VX }, // 7413 |
26571 | | { PseudoVROL_VX_M8_MASK, VROL_VX }, // 7414 |
26572 | | { PseudoVROL_VX_MF2, VROL_VX }, // 7415 |
26573 | | { PseudoVROL_VX_MF2_MASK, VROL_VX }, // 7416 |
26574 | | { PseudoVROL_VX_MF4, VROL_VX }, // 7417 |
26575 | | { PseudoVROL_VX_MF4_MASK, VROL_VX }, // 7418 |
26576 | | { PseudoVROL_VX_MF8, VROL_VX }, // 7419 |
26577 | | { PseudoVROL_VX_MF8_MASK, VROL_VX }, // 7420 |
26578 | | { PseudoVROR_VI_M1, VROR_VI }, // 7421 |
26579 | | { PseudoVROR_VI_M1_MASK, VROR_VI }, // 7422 |
26580 | | { PseudoVROR_VI_M2, VROR_VI }, // 7423 |
26581 | | { PseudoVROR_VI_M2_MASK, VROR_VI }, // 7424 |
26582 | | { PseudoVROR_VI_M4, VROR_VI }, // 7425 |
26583 | | { PseudoVROR_VI_M4_MASK, VROR_VI }, // 7426 |
26584 | | { PseudoVROR_VI_M8, VROR_VI }, // 7427 |
26585 | | { PseudoVROR_VI_M8_MASK, VROR_VI }, // 7428 |
26586 | | { PseudoVROR_VI_MF2, VROR_VI }, // 7429 |
26587 | | { PseudoVROR_VI_MF2_MASK, VROR_VI }, // 7430 |
26588 | | { PseudoVROR_VI_MF4, VROR_VI }, // 7431 |
26589 | | { PseudoVROR_VI_MF4_MASK, VROR_VI }, // 7432 |
26590 | | { PseudoVROR_VI_MF8, VROR_VI }, // 7433 |
26591 | | { PseudoVROR_VI_MF8_MASK, VROR_VI }, // 7434 |
26592 | | { PseudoVROR_VV_M1, VROR_VV }, // 7435 |
26593 | | { PseudoVROR_VV_M1_MASK, VROR_VV }, // 7436 |
26594 | | { PseudoVROR_VV_M2, VROR_VV }, // 7437 |
26595 | | { PseudoVROR_VV_M2_MASK, VROR_VV }, // 7438 |
26596 | | { PseudoVROR_VV_M4, VROR_VV }, // 7439 |
26597 | | { PseudoVROR_VV_M4_MASK, VROR_VV }, // 7440 |
26598 | | { PseudoVROR_VV_M8, VROR_VV }, // 7441 |
26599 | | { PseudoVROR_VV_M8_MASK, VROR_VV }, // 7442 |
26600 | | { PseudoVROR_VV_MF2, VROR_VV }, // 7443 |
26601 | | { PseudoVROR_VV_MF2_MASK, VROR_VV }, // 7444 |
26602 | | { PseudoVROR_VV_MF4, VROR_VV }, // 7445 |
26603 | | { PseudoVROR_VV_MF4_MASK, VROR_VV }, // 7446 |
26604 | | { PseudoVROR_VV_MF8, VROR_VV }, // 7447 |
26605 | | { PseudoVROR_VV_MF8_MASK, VROR_VV }, // 7448 |
26606 | | { PseudoVROR_VX_M1, VROR_VX }, // 7449 |
26607 | | { PseudoVROR_VX_M1_MASK, VROR_VX }, // 7450 |
26608 | | { PseudoVROR_VX_M2, VROR_VX }, // 7451 |
26609 | | { PseudoVROR_VX_M2_MASK, VROR_VX }, // 7452 |
26610 | | { PseudoVROR_VX_M4, VROR_VX }, // 7453 |
26611 | | { PseudoVROR_VX_M4_MASK, VROR_VX }, // 7454 |
26612 | | { PseudoVROR_VX_M8, VROR_VX }, // 7455 |
26613 | | { PseudoVROR_VX_M8_MASK, VROR_VX }, // 7456 |
26614 | | { PseudoVROR_VX_MF2, VROR_VX }, // 7457 |
26615 | | { PseudoVROR_VX_MF2_MASK, VROR_VX }, // 7458 |
26616 | | { PseudoVROR_VX_MF4, VROR_VX }, // 7459 |
26617 | | { PseudoVROR_VX_MF4_MASK, VROR_VX }, // 7460 |
26618 | | { PseudoVROR_VX_MF8, VROR_VX }, // 7461 |
26619 | | { PseudoVROR_VX_MF8_MASK, VROR_VX }, // 7462 |
26620 | | { PseudoVRSUB_VI_M1, VRSUB_VI }, // 7463 |
26621 | | { PseudoVRSUB_VI_M1_MASK, VRSUB_VI }, // 7464 |
26622 | | { PseudoVRSUB_VI_M2, VRSUB_VI }, // 7465 |
26623 | | { PseudoVRSUB_VI_M2_MASK, VRSUB_VI }, // 7466 |
26624 | | { PseudoVRSUB_VI_M4, VRSUB_VI }, // 7467 |
26625 | | { PseudoVRSUB_VI_M4_MASK, VRSUB_VI }, // 7468 |
26626 | | { PseudoVRSUB_VI_M8, VRSUB_VI }, // 7469 |
26627 | | { PseudoVRSUB_VI_M8_MASK, VRSUB_VI }, // 7470 |
26628 | | { PseudoVRSUB_VI_MF2, VRSUB_VI }, // 7471 |
26629 | | { PseudoVRSUB_VI_MF2_MASK, VRSUB_VI }, // 7472 |
26630 | | { PseudoVRSUB_VI_MF4, VRSUB_VI }, // 7473 |
26631 | | { PseudoVRSUB_VI_MF4_MASK, VRSUB_VI }, // 7474 |
26632 | | { PseudoVRSUB_VI_MF8, VRSUB_VI }, // 7475 |
26633 | | { PseudoVRSUB_VI_MF8_MASK, VRSUB_VI }, // 7476 |
26634 | | { PseudoVRSUB_VX_M1, VRSUB_VX }, // 7477 |
26635 | | { PseudoVRSUB_VX_M1_MASK, VRSUB_VX }, // 7478 |
26636 | | { PseudoVRSUB_VX_M2, VRSUB_VX }, // 7479 |
26637 | | { PseudoVRSUB_VX_M2_MASK, VRSUB_VX }, // 7480 |
26638 | | { PseudoVRSUB_VX_M4, VRSUB_VX }, // 7481 |
26639 | | { PseudoVRSUB_VX_M4_MASK, VRSUB_VX }, // 7482 |
26640 | | { PseudoVRSUB_VX_M8, VRSUB_VX }, // 7483 |
26641 | | { PseudoVRSUB_VX_M8_MASK, VRSUB_VX }, // 7484 |
26642 | | { PseudoVRSUB_VX_MF2, VRSUB_VX }, // 7485 |
26643 | | { PseudoVRSUB_VX_MF2_MASK, VRSUB_VX }, // 7486 |
26644 | | { PseudoVRSUB_VX_MF4, VRSUB_VX }, // 7487 |
26645 | | { PseudoVRSUB_VX_MF4_MASK, VRSUB_VX }, // 7488 |
26646 | | { PseudoVRSUB_VX_MF8, VRSUB_VX }, // 7489 |
26647 | | { PseudoVRSUB_VX_MF8_MASK, VRSUB_VX }, // 7490 |
26648 | | { PseudoVSADDU_VI_M1, VSADDU_VI }, // 7491 |
26649 | | { PseudoVSADDU_VI_M1_MASK, VSADDU_VI }, // 7492 |
26650 | | { PseudoVSADDU_VI_M2, VSADDU_VI }, // 7493 |
26651 | | { PseudoVSADDU_VI_M2_MASK, VSADDU_VI }, // 7494 |
26652 | | { PseudoVSADDU_VI_M4, VSADDU_VI }, // 7495 |
26653 | | { PseudoVSADDU_VI_M4_MASK, VSADDU_VI }, // 7496 |
26654 | | { PseudoVSADDU_VI_M8, VSADDU_VI }, // 7497 |
26655 | | { PseudoVSADDU_VI_M8_MASK, VSADDU_VI }, // 7498 |
26656 | | { PseudoVSADDU_VI_MF2, VSADDU_VI }, // 7499 |
26657 | | { PseudoVSADDU_VI_MF2_MASK, VSADDU_VI }, // 7500 |
26658 | | { PseudoVSADDU_VI_MF4, VSADDU_VI }, // 7501 |
26659 | | { PseudoVSADDU_VI_MF4_MASK, VSADDU_VI }, // 7502 |
26660 | | { PseudoVSADDU_VI_MF8, VSADDU_VI }, // 7503 |
26661 | | { PseudoVSADDU_VI_MF8_MASK, VSADDU_VI }, // 7504 |
26662 | | { PseudoVSADDU_VV_M1, VSADDU_VV }, // 7505 |
26663 | | { PseudoVSADDU_VV_M1_MASK, VSADDU_VV }, // 7506 |
26664 | | { PseudoVSADDU_VV_M2, VSADDU_VV }, // 7507 |
26665 | | { PseudoVSADDU_VV_M2_MASK, VSADDU_VV }, // 7508 |
26666 | | { PseudoVSADDU_VV_M4, VSADDU_VV }, // 7509 |
26667 | | { PseudoVSADDU_VV_M4_MASK, VSADDU_VV }, // 7510 |
26668 | | { PseudoVSADDU_VV_M8, VSADDU_VV }, // 7511 |
26669 | | { PseudoVSADDU_VV_M8_MASK, VSADDU_VV }, // 7512 |
26670 | | { PseudoVSADDU_VV_MF2, VSADDU_VV }, // 7513 |
26671 | | { PseudoVSADDU_VV_MF2_MASK, VSADDU_VV }, // 7514 |
26672 | | { PseudoVSADDU_VV_MF4, VSADDU_VV }, // 7515 |
26673 | | { PseudoVSADDU_VV_MF4_MASK, VSADDU_VV }, // 7516 |
26674 | | { PseudoVSADDU_VV_MF8, VSADDU_VV }, // 7517 |
26675 | | { PseudoVSADDU_VV_MF8_MASK, VSADDU_VV }, // 7518 |
26676 | | { PseudoVSADDU_VX_M1, VSADDU_VX }, // 7519 |
26677 | | { PseudoVSADDU_VX_M1_MASK, VSADDU_VX }, // 7520 |
26678 | | { PseudoVSADDU_VX_M2, VSADDU_VX }, // 7521 |
26679 | | { PseudoVSADDU_VX_M2_MASK, VSADDU_VX }, // 7522 |
26680 | | { PseudoVSADDU_VX_M4, VSADDU_VX }, // 7523 |
26681 | | { PseudoVSADDU_VX_M4_MASK, VSADDU_VX }, // 7524 |
26682 | | { PseudoVSADDU_VX_M8, VSADDU_VX }, // 7525 |
26683 | | { PseudoVSADDU_VX_M8_MASK, VSADDU_VX }, // 7526 |
26684 | | { PseudoVSADDU_VX_MF2, VSADDU_VX }, // 7527 |
26685 | | { PseudoVSADDU_VX_MF2_MASK, VSADDU_VX }, // 7528 |
26686 | | { PseudoVSADDU_VX_MF4, VSADDU_VX }, // 7529 |
26687 | | { PseudoVSADDU_VX_MF4_MASK, VSADDU_VX }, // 7530 |
26688 | | { PseudoVSADDU_VX_MF8, VSADDU_VX }, // 7531 |
26689 | | { PseudoVSADDU_VX_MF8_MASK, VSADDU_VX }, // 7532 |
26690 | | { PseudoVSADD_VI_M1, VSADD_VI }, // 7533 |
26691 | | { PseudoVSADD_VI_M1_MASK, VSADD_VI }, // 7534 |
26692 | | { PseudoVSADD_VI_M2, VSADD_VI }, // 7535 |
26693 | | { PseudoVSADD_VI_M2_MASK, VSADD_VI }, // 7536 |
26694 | | { PseudoVSADD_VI_M4, VSADD_VI }, // 7537 |
26695 | | { PseudoVSADD_VI_M4_MASK, VSADD_VI }, // 7538 |
26696 | | { PseudoVSADD_VI_M8, VSADD_VI }, // 7539 |
26697 | | { PseudoVSADD_VI_M8_MASK, VSADD_VI }, // 7540 |
26698 | | { PseudoVSADD_VI_MF2, VSADD_VI }, // 7541 |
26699 | | { PseudoVSADD_VI_MF2_MASK, VSADD_VI }, // 7542 |
26700 | | { PseudoVSADD_VI_MF4, VSADD_VI }, // 7543 |
26701 | | { PseudoVSADD_VI_MF4_MASK, VSADD_VI }, // 7544 |
26702 | | { PseudoVSADD_VI_MF8, VSADD_VI }, // 7545 |
26703 | | { PseudoVSADD_VI_MF8_MASK, VSADD_VI }, // 7546 |
26704 | | { PseudoVSADD_VV_M1, VSADD_VV }, // 7547 |
26705 | | { PseudoVSADD_VV_M1_MASK, VSADD_VV }, // 7548 |
26706 | | { PseudoVSADD_VV_M2, VSADD_VV }, // 7549 |
26707 | | { PseudoVSADD_VV_M2_MASK, VSADD_VV }, // 7550 |
26708 | | { PseudoVSADD_VV_M4, VSADD_VV }, // 7551 |
26709 | | { PseudoVSADD_VV_M4_MASK, VSADD_VV }, // 7552 |
26710 | | { PseudoVSADD_VV_M8, VSADD_VV }, // 7553 |
26711 | | { PseudoVSADD_VV_M8_MASK, VSADD_VV }, // 7554 |
26712 | | { PseudoVSADD_VV_MF2, VSADD_VV }, // 7555 |
26713 | | { PseudoVSADD_VV_MF2_MASK, VSADD_VV }, // 7556 |
26714 | | { PseudoVSADD_VV_MF4, VSADD_VV }, // 7557 |
26715 | | { PseudoVSADD_VV_MF4_MASK, VSADD_VV }, // 7558 |
26716 | | { PseudoVSADD_VV_MF8, VSADD_VV }, // 7559 |
26717 | | { PseudoVSADD_VV_MF8_MASK, VSADD_VV }, // 7560 |
26718 | | { PseudoVSADD_VX_M1, VSADD_VX }, // 7561 |
26719 | | { PseudoVSADD_VX_M1_MASK, VSADD_VX }, // 7562 |
26720 | | { PseudoVSADD_VX_M2, VSADD_VX }, // 7563 |
26721 | | { PseudoVSADD_VX_M2_MASK, VSADD_VX }, // 7564 |
26722 | | { PseudoVSADD_VX_M4, VSADD_VX }, // 7565 |
26723 | | { PseudoVSADD_VX_M4_MASK, VSADD_VX }, // 7566 |
26724 | | { PseudoVSADD_VX_M8, VSADD_VX }, // 7567 |
26725 | | { PseudoVSADD_VX_M8_MASK, VSADD_VX }, // 7568 |
26726 | | { PseudoVSADD_VX_MF2, VSADD_VX }, // 7569 |
26727 | | { PseudoVSADD_VX_MF2_MASK, VSADD_VX }, // 7570 |
26728 | | { PseudoVSADD_VX_MF4, VSADD_VX }, // 7571 |
26729 | | { PseudoVSADD_VX_MF4_MASK, VSADD_VX }, // 7572 |
26730 | | { PseudoVSADD_VX_MF8, VSADD_VX }, // 7573 |
26731 | | { PseudoVSADD_VX_MF8_MASK, VSADD_VX }, // 7574 |
26732 | | { PseudoVSBC_VVM_M1, VSBC_VVM }, // 7575 |
26733 | | { PseudoVSBC_VVM_M2, VSBC_VVM }, // 7576 |
26734 | | { PseudoVSBC_VVM_M4, VSBC_VVM }, // 7577 |
26735 | | { PseudoVSBC_VVM_M8, VSBC_VVM }, // 7578 |
26736 | | { PseudoVSBC_VVM_MF2, VSBC_VVM }, // 7579 |
26737 | | { PseudoVSBC_VVM_MF4, VSBC_VVM }, // 7580 |
26738 | | { PseudoVSBC_VVM_MF8, VSBC_VVM }, // 7581 |
26739 | | { PseudoVSBC_VXM_M1, VSBC_VXM }, // 7582 |
26740 | | { PseudoVSBC_VXM_M2, VSBC_VXM }, // 7583 |
26741 | | { PseudoVSBC_VXM_M4, VSBC_VXM }, // 7584 |
26742 | | { PseudoVSBC_VXM_M8, VSBC_VXM }, // 7585 |
26743 | | { PseudoVSBC_VXM_MF2, VSBC_VXM }, // 7586 |
26744 | | { PseudoVSBC_VXM_MF4, VSBC_VXM }, // 7587 |
26745 | | { PseudoVSBC_VXM_MF8, VSBC_VXM }, // 7588 |
26746 | | { PseudoVSE16_V_M1, VSE16_V }, // 7589 |
26747 | | { PseudoVSE16_V_M1_MASK, VSE16_V }, // 7590 |
26748 | | { PseudoVSE16_V_M2, VSE16_V }, // 7591 |
26749 | | { PseudoVSE16_V_M2_MASK, VSE16_V }, // 7592 |
26750 | | { PseudoVSE16_V_M4, VSE16_V }, // 7593 |
26751 | | { PseudoVSE16_V_M4_MASK, VSE16_V }, // 7594 |
26752 | | { PseudoVSE16_V_M8, VSE16_V }, // 7595 |
26753 | | { PseudoVSE16_V_M8_MASK, VSE16_V }, // 7596 |
26754 | | { PseudoVSE16_V_MF2, VSE16_V }, // 7597 |
26755 | | { PseudoVSE16_V_MF2_MASK, VSE16_V }, // 7598 |
26756 | | { PseudoVSE16_V_MF4, VSE16_V }, // 7599 |
26757 | | { PseudoVSE16_V_MF4_MASK, VSE16_V }, // 7600 |
26758 | | { PseudoVSE32_V_M1, VSE32_V }, // 7601 |
26759 | | { PseudoVSE32_V_M1_MASK, VSE32_V }, // 7602 |
26760 | | { PseudoVSE32_V_M2, VSE32_V }, // 7603 |
26761 | | { PseudoVSE32_V_M2_MASK, VSE32_V }, // 7604 |
26762 | | { PseudoVSE32_V_M4, VSE32_V }, // 7605 |
26763 | | { PseudoVSE32_V_M4_MASK, VSE32_V }, // 7606 |
26764 | | { PseudoVSE32_V_M8, VSE32_V }, // 7607 |
26765 | | { PseudoVSE32_V_M8_MASK, VSE32_V }, // 7608 |
26766 | | { PseudoVSE32_V_MF2, VSE32_V }, // 7609 |
26767 | | { PseudoVSE32_V_MF2_MASK, VSE32_V }, // 7610 |
26768 | | { PseudoVSE64_V_M1, VSE64_V }, // 7611 |
26769 | | { PseudoVSE64_V_M1_MASK, VSE64_V }, // 7612 |
26770 | | { PseudoVSE64_V_M2, VSE64_V }, // 7613 |
26771 | | { PseudoVSE64_V_M2_MASK, VSE64_V }, // 7614 |
26772 | | { PseudoVSE64_V_M4, VSE64_V }, // 7615 |
26773 | | { PseudoVSE64_V_M4_MASK, VSE64_V }, // 7616 |
26774 | | { PseudoVSE64_V_M8, VSE64_V }, // 7617 |
26775 | | { PseudoVSE64_V_M8_MASK, VSE64_V }, // 7618 |
26776 | | { PseudoVSE8_V_M1, VSE8_V }, // 7619 |
26777 | | { PseudoVSE8_V_M1_MASK, VSE8_V }, // 7620 |
26778 | | { PseudoVSE8_V_M2, VSE8_V }, // 7621 |
26779 | | { PseudoVSE8_V_M2_MASK, VSE8_V }, // 7622 |
26780 | | { PseudoVSE8_V_M4, VSE8_V }, // 7623 |
26781 | | { PseudoVSE8_V_M4_MASK, VSE8_V }, // 7624 |
26782 | | { PseudoVSE8_V_M8, VSE8_V }, // 7625 |
26783 | | { PseudoVSE8_V_M8_MASK, VSE8_V }, // 7626 |
26784 | | { PseudoVSE8_V_MF2, VSE8_V }, // 7627 |
26785 | | { PseudoVSE8_V_MF2_MASK, VSE8_V }, // 7628 |
26786 | | { PseudoVSE8_V_MF4, VSE8_V }, // 7629 |
26787 | | { PseudoVSE8_V_MF4_MASK, VSE8_V }, // 7630 |
26788 | | { PseudoVSE8_V_MF8, VSE8_V }, // 7631 |
26789 | | { PseudoVSE8_V_MF8_MASK, VSE8_V }, // 7632 |
26790 | | { PseudoVSEXT_VF2_M1, VSEXT_VF2 }, // 7633 |
26791 | | { PseudoVSEXT_VF2_M1_MASK, VSEXT_VF2 }, // 7634 |
26792 | | { PseudoVSEXT_VF2_M2, VSEXT_VF2 }, // 7635 |
26793 | | { PseudoVSEXT_VF2_M2_MASK, VSEXT_VF2 }, // 7636 |
26794 | | { PseudoVSEXT_VF2_M4, VSEXT_VF2 }, // 7637 |
26795 | | { PseudoVSEXT_VF2_M4_MASK, VSEXT_VF2 }, // 7638 |
26796 | | { PseudoVSEXT_VF2_M8, VSEXT_VF2 }, // 7639 |
26797 | | { PseudoVSEXT_VF2_M8_MASK, VSEXT_VF2 }, // 7640 |
26798 | | { PseudoVSEXT_VF2_MF2, VSEXT_VF2 }, // 7641 |
26799 | | { PseudoVSEXT_VF2_MF2_MASK, VSEXT_VF2 }, // 7642 |
26800 | | { PseudoVSEXT_VF2_MF4, VSEXT_VF2 }, // 7643 |
26801 | | { PseudoVSEXT_VF2_MF4_MASK, VSEXT_VF2 }, // 7644 |
26802 | | { PseudoVSEXT_VF4_M1, VSEXT_VF4 }, // 7645 |
26803 | | { PseudoVSEXT_VF4_M1_MASK, VSEXT_VF4 }, // 7646 |
26804 | | { PseudoVSEXT_VF4_M2, VSEXT_VF4 }, // 7647 |
26805 | | { PseudoVSEXT_VF4_M2_MASK, VSEXT_VF4 }, // 7648 |
26806 | | { PseudoVSEXT_VF4_M4, VSEXT_VF4 }, // 7649 |
26807 | | { PseudoVSEXT_VF4_M4_MASK, VSEXT_VF4 }, // 7650 |
26808 | | { PseudoVSEXT_VF4_M8, VSEXT_VF4 }, // 7651 |
26809 | | { PseudoVSEXT_VF4_M8_MASK, VSEXT_VF4 }, // 7652 |
26810 | | { PseudoVSEXT_VF4_MF2, VSEXT_VF4 }, // 7653 |
26811 | | { PseudoVSEXT_VF4_MF2_MASK, VSEXT_VF4 }, // 7654 |
26812 | | { PseudoVSEXT_VF8_M1, VSEXT_VF8 }, // 7655 |
26813 | | { PseudoVSEXT_VF8_M1_MASK, VSEXT_VF8 }, // 7656 |
26814 | | { PseudoVSEXT_VF8_M2, VSEXT_VF8 }, // 7657 |
26815 | | { PseudoVSEXT_VF8_M2_MASK, VSEXT_VF8 }, // 7658 |
26816 | | { PseudoVSEXT_VF8_M4, VSEXT_VF8 }, // 7659 |
26817 | | { PseudoVSEXT_VF8_M4_MASK, VSEXT_VF8 }, // 7660 |
26818 | | { PseudoVSEXT_VF8_M8, VSEXT_VF8 }, // 7661 |
26819 | | { PseudoVSEXT_VF8_M8_MASK, VSEXT_VF8 }, // 7662 |
26820 | | { PseudoVSHA2CH_VV_M1, VSHA2CH_VV }, // 7663 |
26821 | | { PseudoVSHA2CH_VV_M2, VSHA2CH_VV }, // 7664 |
26822 | | { PseudoVSHA2CH_VV_M4, VSHA2CH_VV }, // 7665 |
26823 | | { PseudoVSHA2CH_VV_M8, VSHA2CH_VV }, // 7666 |
26824 | | { PseudoVSHA2CH_VV_MF2, VSHA2CH_VV }, // 7667 |
26825 | | { PseudoVSHA2CL_VV_M1, VSHA2CL_VV }, // 7668 |
26826 | | { PseudoVSHA2CL_VV_M2, VSHA2CL_VV }, // 7669 |
26827 | | { PseudoVSHA2CL_VV_M4, VSHA2CL_VV }, // 7670 |
26828 | | { PseudoVSHA2CL_VV_M8, VSHA2CL_VV }, // 7671 |
26829 | | { PseudoVSHA2CL_VV_MF2, VSHA2CL_VV }, // 7672 |
26830 | | { PseudoVSHA2MS_VV_M1, VSHA2MS_VV }, // 7673 |
26831 | | { PseudoVSHA2MS_VV_M2, VSHA2MS_VV }, // 7674 |
26832 | | { PseudoVSHA2MS_VV_M4, VSHA2MS_VV }, // 7675 |
26833 | | { PseudoVSHA2MS_VV_M8, VSHA2MS_VV }, // 7676 |
26834 | | { PseudoVSHA2MS_VV_MF2, VSHA2MS_VV }, // 7677 |
26835 | | { PseudoVSLIDE1DOWN_VX_M1, VSLIDE1DOWN_VX }, // 7678 |
26836 | | { PseudoVSLIDE1DOWN_VX_M1_MASK, VSLIDE1DOWN_VX }, // 7679 |
26837 | | { PseudoVSLIDE1DOWN_VX_M2, VSLIDE1DOWN_VX }, // 7680 |
26838 | | { PseudoVSLIDE1DOWN_VX_M2_MASK, VSLIDE1DOWN_VX }, // 7681 |
26839 | | { PseudoVSLIDE1DOWN_VX_M4, VSLIDE1DOWN_VX }, // 7682 |
26840 | | { PseudoVSLIDE1DOWN_VX_M4_MASK, VSLIDE1DOWN_VX }, // 7683 |
26841 | | { PseudoVSLIDE1DOWN_VX_M8, VSLIDE1DOWN_VX }, // 7684 |
26842 | | { PseudoVSLIDE1DOWN_VX_M8_MASK, VSLIDE1DOWN_VX }, // 7685 |
26843 | | { PseudoVSLIDE1DOWN_VX_MF2, VSLIDE1DOWN_VX }, // 7686 |
26844 | | { PseudoVSLIDE1DOWN_VX_MF2_MASK, VSLIDE1DOWN_VX }, // 7687 |
26845 | | { PseudoVSLIDE1DOWN_VX_MF4, VSLIDE1DOWN_VX }, // 7688 |
26846 | | { PseudoVSLIDE1DOWN_VX_MF4_MASK, VSLIDE1DOWN_VX }, // 7689 |
26847 | | { PseudoVSLIDE1DOWN_VX_MF8, VSLIDE1DOWN_VX }, // 7690 |
26848 | | { PseudoVSLIDE1DOWN_VX_MF8_MASK, VSLIDE1DOWN_VX }, // 7691 |
26849 | | { PseudoVSLIDE1UP_VX_M1, VSLIDE1UP_VX }, // 7692 |
26850 | | { PseudoVSLIDE1UP_VX_M1_MASK, VSLIDE1UP_VX }, // 7693 |
26851 | | { PseudoVSLIDE1UP_VX_M2, VSLIDE1UP_VX }, // 7694 |
26852 | | { PseudoVSLIDE1UP_VX_M2_MASK, VSLIDE1UP_VX }, // 7695 |
26853 | | { PseudoVSLIDE1UP_VX_M4, VSLIDE1UP_VX }, // 7696 |
26854 | | { PseudoVSLIDE1UP_VX_M4_MASK, VSLIDE1UP_VX }, // 7697 |
26855 | | { PseudoVSLIDE1UP_VX_M8, VSLIDE1UP_VX }, // 7698 |
26856 | | { PseudoVSLIDE1UP_VX_M8_MASK, VSLIDE1UP_VX }, // 7699 |
26857 | | { PseudoVSLIDE1UP_VX_MF2, VSLIDE1UP_VX }, // 7700 |
26858 | | { PseudoVSLIDE1UP_VX_MF2_MASK, VSLIDE1UP_VX }, // 7701 |
26859 | | { PseudoVSLIDE1UP_VX_MF4, VSLIDE1UP_VX }, // 7702 |
26860 | | { PseudoVSLIDE1UP_VX_MF4_MASK, VSLIDE1UP_VX }, // 7703 |
26861 | | { PseudoVSLIDE1UP_VX_MF8, VSLIDE1UP_VX }, // 7704 |
26862 | | { PseudoVSLIDE1UP_VX_MF8_MASK, VSLIDE1UP_VX }, // 7705 |
26863 | | { PseudoVSLIDEDOWN_VI_M1, VSLIDEDOWN_VI }, // 7706 |
26864 | | { PseudoVSLIDEDOWN_VI_M1_MASK, VSLIDEDOWN_VI }, // 7707 |
26865 | | { PseudoVSLIDEDOWN_VI_M2, VSLIDEDOWN_VI }, // 7708 |
26866 | | { PseudoVSLIDEDOWN_VI_M2_MASK, VSLIDEDOWN_VI }, // 7709 |
26867 | | { PseudoVSLIDEDOWN_VI_M4, VSLIDEDOWN_VI }, // 7710 |
26868 | | { PseudoVSLIDEDOWN_VI_M4_MASK, VSLIDEDOWN_VI }, // 7711 |
26869 | | { PseudoVSLIDEDOWN_VI_M8, VSLIDEDOWN_VI }, // 7712 |
26870 | | { PseudoVSLIDEDOWN_VI_M8_MASK, VSLIDEDOWN_VI }, // 7713 |
26871 | | { PseudoVSLIDEDOWN_VI_MF2, VSLIDEDOWN_VI }, // 7714 |
26872 | | { PseudoVSLIDEDOWN_VI_MF2_MASK, VSLIDEDOWN_VI }, // 7715 |
26873 | | { PseudoVSLIDEDOWN_VI_MF4, VSLIDEDOWN_VI }, // 7716 |
26874 | | { PseudoVSLIDEDOWN_VI_MF4_MASK, VSLIDEDOWN_VI }, // 7717 |
26875 | | { PseudoVSLIDEDOWN_VI_MF8, VSLIDEDOWN_VI }, // 7718 |
26876 | | { PseudoVSLIDEDOWN_VI_MF8_MASK, VSLIDEDOWN_VI }, // 7719 |
26877 | | { PseudoVSLIDEDOWN_VX_M1, VSLIDEDOWN_VX }, // 7720 |
26878 | | { PseudoVSLIDEDOWN_VX_M1_MASK, VSLIDEDOWN_VX }, // 7721 |
26879 | | { PseudoVSLIDEDOWN_VX_M2, VSLIDEDOWN_VX }, // 7722 |
26880 | | { PseudoVSLIDEDOWN_VX_M2_MASK, VSLIDEDOWN_VX }, // 7723 |
26881 | | { PseudoVSLIDEDOWN_VX_M4, VSLIDEDOWN_VX }, // 7724 |
26882 | | { PseudoVSLIDEDOWN_VX_M4_MASK, VSLIDEDOWN_VX }, // 7725 |
26883 | | { PseudoVSLIDEDOWN_VX_M8, VSLIDEDOWN_VX }, // 7726 |
26884 | | { PseudoVSLIDEDOWN_VX_M8_MASK, VSLIDEDOWN_VX }, // 7727 |
26885 | | { PseudoVSLIDEDOWN_VX_MF2, VSLIDEDOWN_VX }, // 7728 |
26886 | | { PseudoVSLIDEDOWN_VX_MF2_MASK, VSLIDEDOWN_VX }, // 7729 |
26887 | | { PseudoVSLIDEDOWN_VX_MF4, VSLIDEDOWN_VX }, // 7730 |
26888 | | { PseudoVSLIDEDOWN_VX_MF4_MASK, VSLIDEDOWN_VX }, // 7731 |
26889 | | { PseudoVSLIDEDOWN_VX_MF8, VSLIDEDOWN_VX }, // 7732 |
26890 | | { PseudoVSLIDEDOWN_VX_MF8_MASK, VSLIDEDOWN_VX }, // 7733 |
26891 | | { PseudoVSLIDEUP_VI_M1, VSLIDEUP_VI }, // 7734 |
26892 | | { PseudoVSLIDEUP_VI_M1_MASK, VSLIDEUP_VI }, // 7735 |
26893 | | { PseudoVSLIDEUP_VI_M2, VSLIDEUP_VI }, // 7736 |
26894 | | { PseudoVSLIDEUP_VI_M2_MASK, VSLIDEUP_VI }, // 7737 |
26895 | | { PseudoVSLIDEUP_VI_M4, VSLIDEUP_VI }, // 7738 |
26896 | | { PseudoVSLIDEUP_VI_M4_MASK, VSLIDEUP_VI }, // 7739 |
26897 | | { PseudoVSLIDEUP_VI_M8, VSLIDEUP_VI }, // 7740 |
26898 | | { PseudoVSLIDEUP_VI_M8_MASK, VSLIDEUP_VI }, // 7741 |
26899 | | { PseudoVSLIDEUP_VI_MF2, VSLIDEUP_VI }, // 7742 |
26900 | | { PseudoVSLIDEUP_VI_MF2_MASK, VSLIDEUP_VI }, // 7743 |
26901 | | { PseudoVSLIDEUP_VI_MF4, VSLIDEUP_VI }, // 7744 |
26902 | | { PseudoVSLIDEUP_VI_MF4_MASK, VSLIDEUP_VI }, // 7745 |
26903 | | { PseudoVSLIDEUP_VI_MF8, VSLIDEUP_VI }, // 7746 |
26904 | | { PseudoVSLIDEUP_VI_MF8_MASK, VSLIDEUP_VI }, // 7747 |
26905 | | { PseudoVSLIDEUP_VX_M1, VSLIDEUP_VX }, // 7748 |
26906 | | { PseudoVSLIDEUP_VX_M1_MASK, VSLIDEUP_VX }, // 7749 |
26907 | | { PseudoVSLIDEUP_VX_M2, VSLIDEUP_VX }, // 7750 |
26908 | | { PseudoVSLIDEUP_VX_M2_MASK, VSLIDEUP_VX }, // 7751 |
26909 | | { PseudoVSLIDEUP_VX_M4, VSLIDEUP_VX }, // 7752 |
26910 | | { PseudoVSLIDEUP_VX_M4_MASK, VSLIDEUP_VX }, // 7753 |
26911 | | { PseudoVSLIDEUP_VX_M8, VSLIDEUP_VX }, // 7754 |
26912 | | { PseudoVSLIDEUP_VX_M8_MASK, VSLIDEUP_VX }, // 7755 |
26913 | | { PseudoVSLIDEUP_VX_MF2, VSLIDEUP_VX }, // 7756 |
26914 | | { PseudoVSLIDEUP_VX_MF2_MASK, VSLIDEUP_VX }, // 7757 |
26915 | | { PseudoVSLIDEUP_VX_MF4, VSLIDEUP_VX }, // 7758 |
26916 | | { PseudoVSLIDEUP_VX_MF4_MASK, VSLIDEUP_VX }, // 7759 |
26917 | | { PseudoVSLIDEUP_VX_MF8, VSLIDEUP_VX }, // 7760 |
26918 | | { PseudoVSLIDEUP_VX_MF8_MASK, VSLIDEUP_VX }, // 7761 |
26919 | | { PseudoVSLL_VI_M1, VSLL_VI }, // 7762 |
26920 | | { PseudoVSLL_VI_M1_MASK, VSLL_VI }, // 7763 |
26921 | | { PseudoVSLL_VI_M2, VSLL_VI }, // 7764 |
26922 | | { PseudoVSLL_VI_M2_MASK, VSLL_VI }, // 7765 |
26923 | | { PseudoVSLL_VI_M4, VSLL_VI }, // 7766 |
26924 | | { PseudoVSLL_VI_M4_MASK, VSLL_VI }, // 7767 |
26925 | | { PseudoVSLL_VI_M8, VSLL_VI }, // 7768 |
26926 | | { PseudoVSLL_VI_M8_MASK, VSLL_VI }, // 7769 |
26927 | | { PseudoVSLL_VI_MF2, VSLL_VI }, // 7770 |
26928 | | { PseudoVSLL_VI_MF2_MASK, VSLL_VI }, // 7771 |
26929 | | { PseudoVSLL_VI_MF4, VSLL_VI }, // 7772 |
26930 | | { PseudoVSLL_VI_MF4_MASK, VSLL_VI }, // 7773 |
26931 | | { PseudoVSLL_VI_MF8, VSLL_VI }, // 7774 |
26932 | | { PseudoVSLL_VI_MF8_MASK, VSLL_VI }, // 7775 |
26933 | | { PseudoVSLL_VV_M1, VSLL_VV }, // 7776 |
26934 | | { PseudoVSLL_VV_M1_MASK, VSLL_VV }, // 7777 |
26935 | | { PseudoVSLL_VV_M2, VSLL_VV }, // 7778 |
26936 | | { PseudoVSLL_VV_M2_MASK, VSLL_VV }, // 7779 |
26937 | | { PseudoVSLL_VV_M4, VSLL_VV }, // 7780 |
26938 | | { PseudoVSLL_VV_M4_MASK, VSLL_VV }, // 7781 |
26939 | | { PseudoVSLL_VV_M8, VSLL_VV }, // 7782 |
26940 | | { PseudoVSLL_VV_M8_MASK, VSLL_VV }, // 7783 |
26941 | | { PseudoVSLL_VV_MF2, VSLL_VV }, // 7784 |
26942 | | { PseudoVSLL_VV_MF2_MASK, VSLL_VV }, // 7785 |
26943 | | { PseudoVSLL_VV_MF4, VSLL_VV }, // 7786 |
26944 | | { PseudoVSLL_VV_MF4_MASK, VSLL_VV }, // 7787 |
26945 | | { PseudoVSLL_VV_MF8, VSLL_VV }, // 7788 |
26946 | | { PseudoVSLL_VV_MF8_MASK, VSLL_VV }, // 7789 |
26947 | | { PseudoVSLL_VX_M1, VSLL_VX }, // 7790 |
26948 | | { PseudoVSLL_VX_M1_MASK, VSLL_VX }, // 7791 |
26949 | | { PseudoVSLL_VX_M2, VSLL_VX }, // 7792 |
26950 | | { PseudoVSLL_VX_M2_MASK, VSLL_VX }, // 7793 |
26951 | | { PseudoVSLL_VX_M4, VSLL_VX }, // 7794 |
26952 | | { PseudoVSLL_VX_M4_MASK, VSLL_VX }, // 7795 |
26953 | | { PseudoVSLL_VX_M8, VSLL_VX }, // 7796 |
26954 | | { PseudoVSLL_VX_M8_MASK, VSLL_VX }, // 7797 |
26955 | | { PseudoVSLL_VX_MF2, VSLL_VX }, // 7798 |
26956 | | { PseudoVSLL_VX_MF2_MASK, VSLL_VX }, // 7799 |
26957 | | { PseudoVSLL_VX_MF4, VSLL_VX }, // 7800 |
26958 | | { PseudoVSLL_VX_MF4_MASK, VSLL_VX }, // 7801 |
26959 | | { PseudoVSLL_VX_MF8, VSLL_VX }, // 7802 |
26960 | | { PseudoVSLL_VX_MF8_MASK, VSLL_VX }, // 7803 |
26961 | | { PseudoVSM3C_VI_M1, VSM3C_VI }, // 7804 |
26962 | | { PseudoVSM3C_VI_M2, VSM3C_VI }, // 7805 |
26963 | | { PseudoVSM3C_VI_M4, VSM3C_VI }, // 7806 |
26964 | | { PseudoVSM3C_VI_M8, VSM3C_VI }, // 7807 |
26965 | | { PseudoVSM3C_VI_MF2, VSM3C_VI }, // 7808 |
26966 | | { PseudoVSM3ME_VV_M1, VSM3ME_VV }, // 7809 |
26967 | | { PseudoVSM3ME_VV_M2, VSM3ME_VV }, // 7810 |
26968 | | { PseudoVSM3ME_VV_M4, VSM3ME_VV }, // 7811 |
26969 | | { PseudoVSM3ME_VV_M8, VSM3ME_VV }, // 7812 |
26970 | | { PseudoVSM3ME_VV_MF2, VSM3ME_VV }, // 7813 |
26971 | | { PseudoVSM4K_VI_M1, VSM4K_VI }, // 7814 |
26972 | | { PseudoVSM4K_VI_M2, VSM4K_VI }, // 7815 |
26973 | | { PseudoVSM4K_VI_M4, VSM4K_VI }, // 7816 |
26974 | | { PseudoVSM4K_VI_M8, VSM4K_VI }, // 7817 |
26975 | | { PseudoVSM4K_VI_MF2, VSM4K_VI }, // 7818 |
26976 | | { PseudoVSM4R_VS_M1_M1, VSM4R_VS }, // 7819 |
26977 | | { PseudoVSM4R_VS_M1_MF2, VSM4R_VS }, // 7820 |
26978 | | { PseudoVSM4R_VS_M1_MF4, VSM4R_VS }, // 7821 |
26979 | | { PseudoVSM4R_VS_M1_MF8, VSM4R_VS }, // 7822 |
26980 | | { PseudoVSM4R_VS_M2_M1, VSM4R_VS }, // 7823 |
26981 | | { PseudoVSM4R_VS_M2_M2, VSM4R_VS }, // 7824 |
26982 | | { PseudoVSM4R_VS_M2_MF2, VSM4R_VS }, // 7825 |
26983 | | { PseudoVSM4R_VS_M2_MF4, VSM4R_VS }, // 7826 |
26984 | | { PseudoVSM4R_VS_M2_MF8, VSM4R_VS }, // 7827 |
26985 | | { PseudoVSM4R_VS_M4_M1, VSM4R_VS }, // 7828 |
26986 | | { PseudoVSM4R_VS_M4_M2, VSM4R_VS }, // 7829 |
26987 | | { PseudoVSM4R_VS_M4_M4, VSM4R_VS }, // 7830 |
26988 | | { PseudoVSM4R_VS_M4_MF2, VSM4R_VS }, // 7831 |
26989 | | { PseudoVSM4R_VS_M4_MF4, VSM4R_VS }, // 7832 |
26990 | | { PseudoVSM4R_VS_M4_MF8, VSM4R_VS }, // 7833 |
26991 | | { PseudoVSM4R_VS_M8_M1, VSM4R_VS }, // 7834 |
26992 | | { PseudoVSM4R_VS_M8_M2, VSM4R_VS }, // 7835 |
26993 | | { PseudoVSM4R_VS_M8_M4, VSM4R_VS }, // 7836 |
26994 | | { PseudoVSM4R_VS_M8_MF2, VSM4R_VS }, // 7837 |
26995 | | { PseudoVSM4R_VS_M8_MF4, VSM4R_VS }, // 7838 |
26996 | | { PseudoVSM4R_VS_M8_MF8, VSM4R_VS }, // 7839 |
26997 | | { PseudoVSM4R_VS_MF2_MF2, VSM4R_VS }, // 7840 |
26998 | | { PseudoVSM4R_VS_MF2_MF4, VSM4R_VS }, // 7841 |
26999 | | { PseudoVSM4R_VS_MF2_MF8, VSM4R_VS }, // 7842 |
27000 | | { PseudoVSM4R_VV_M1, VSM4R_VV }, // 7843 |
27001 | | { PseudoVSM4R_VV_M2, VSM4R_VV }, // 7844 |
27002 | | { PseudoVSM4R_VV_M4, VSM4R_VV }, // 7845 |
27003 | | { PseudoVSM4R_VV_M8, VSM4R_VV }, // 7846 |
27004 | | { PseudoVSM4R_VV_MF2, VSM4R_VV }, // 7847 |
27005 | | { PseudoVSMUL_VV_M1, VSMUL_VV }, // 7848 |
27006 | | { PseudoVSMUL_VV_M1_MASK, VSMUL_VV }, // 7849 |
27007 | | { PseudoVSMUL_VV_M2, VSMUL_VV }, // 7850 |
27008 | | { PseudoVSMUL_VV_M2_MASK, VSMUL_VV }, // 7851 |
27009 | | { PseudoVSMUL_VV_M4, VSMUL_VV }, // 7852 |
27010 | | { PseudoVSMUL_VV_M4_MASK, VSMUL_VV }, // 7853 |
27011 | | { PseudoVSMUL_VV_M8, VSMUL_VV }, // 7854 |
27012 | | { PseudoVSMUL_VV_M8_MASK, VSMUL_VV }, // 7855 |
27013 | | { PseudoVSMUL_VV_MF2, VSMUL_VV }, // 7856 |
27014 | | { PseudoVSMUL_VV_MF2_MASK, VSMUL_VV }, // 7857 |
27015 | | { PseudoVSMUL_VV_MF4, VSMUL_VV }, // 7858 |
27016 | | { PseudoVSMUL_VV_MF4_MASK, VSMUL_VV }, // 7859 |
27017 | | { PseudoVSMUL_VV_MF8, VSMUL_VV }, // 7860 |
27018 | | { PseudoVSMUL_VV_MF8_MASK, VSMUL_VV }, // 7861 |
27019 | | { PseudoVSMUL_VX_M1, VSMUL_VX }, // 7862 |
27020 | | { PseudoVSMUL_VX_M1_MASK, VSMUL_VX }, // 7863 |
27021 | | { PseudoVSMUL_VX_M2, VSMUL_VX }, // 7864 |
27022 | | { PseudoVSMUL_VX_M2_MASK, VSMUL_VX }, // 7865 |
27023 | | { PseudoVSMUL_VX_M4, VSMUL_VX }, // 7866 |
27024 | | { PseudoVSMUL_VX_M4_MASK, VSMUL_VX }, // 7867 |
27025 | | { PseudoVSMUL_VX_M8, VSMUL_VX }, // 7868 |
27026 | | { PseudoVSMUL_VX_M8_MASK, VSMUL_VX }, // 7869 |
27027 | | { PseudoVSMUL_VX_MF2, VSMUL_VX }, // 7870 |
27028 | | { PseudoVSMUL_VX_MF2_MASK, VSMUL_VX }, // 7871 |
27029 | | { PseudoVSMUL_VX_MF4, VSMUL_VX }, // 7872 |
27030 | | { PseudoVSMUL_VX_MF4_MASK, VSMUL_VX }, // 7873 |
27031 | | { PseudoVSMUL_VX_MF8, VSMUL_VX }, // 7874 |
27032 | | { PseudoVSMUL_VX_MF8_MASK, VSMUL_VX }, // 7875 |
27033 | | { PseudoVSM_V_B1, VSM_V }, // 7876 |
27034 | | { PseudoVSM_V_B16, VSM_V }, // 7877 |
27035 | | { PseudoVSM_V_B2, VSM_V }, // 7878 |
27036 | | { PseudoVSM_V_B32, VSM_V }, // 7879 |
27037 | | { PseudoVSM_V_B4, VSM_V }, // 7880 |
27038 | | { PseudoVSM_V_B64, VSM_V }, // 7881 |
27039 | | { PseudoVSM_V_B8, VSM_V }, // 7882 |
27040 | | { PseudoVSOXEI16_V_M1_M1, VSOXEI16_V }, // 7883 |
27041 | | { PseudoVSOXEI16_V_M1_M1_MASK, VSOXEI16_V }, // 7884 |
27042 | | { PseudoVSOXEI16_V_M1_M2, VSOXEI16_V }, // 7885 |
27043 | | { PseudoVSOXEI16_V_M1_M2_MASK, VSOXEI16_V }, // 7886 |
27044 | | { PseudoVSOXEI16_V_M1_M4, VSOXEI16_V }, // 7887 |
27045 | | { PseudoVSOXEI16_V_M1_M4_MASK, VSOXEI16_V }, // 7888 |
27046 | | { PseudoVSOXEI16_V_M1_MF2, VSOXEI16_V }, // 7889 |
27047 | | { PseudoVSOXEI16_V_M1_MF2_MASK, VSOXEI16_V }, // 7890 |
27048 | | { PseudoVSOXEI16_V_M2_M1, VSOXEI16_V }, // 7891 |
27049 | | { PseudoVSOXEI16_V_M2_M1_MASK, VSOXEI16_V }, // 7892 |
27050 | | { PseudoVSOXEI16_V_M2_M2, VSOXEI16_V }, // 7893 |
27051 | | { PseudoVSOXEI16_V_M2_M2_MASK, VSOXEI16_V }, // 7894 |
27052 | | { PseudoVSOXEI16_V_M2_M4, VSOXEI16_V }, // 7895 |
27053 | | { PseudoVSOXEI16_V_M2_M4_MASK, VSOXEI16_V }, // 7896 |
27054 | | { PseudoVSOXEI16_V_M2_M8, VSOXEI16_V }, // 7897 |
27055 | | { PseudoVSOXEI16_V_M2_M8_MASK, VSOXEI16_V }, // 7898 |
27056 | | { PseudoVSOXEI16_V_M4_M2, VSOXEI16_V }, // 7899 |
27057 | | { PseudoVSOXEI16_V_M4_M2_MASK, VSOXEI16_V }, // 7900 |
27058 | | { PseudoVSOXEI16_V_M4_M4, VSOXEI16_V }, // 7901 |
27059 | | { PseudoVSOXEI16_V_M4_M4_MASK, VSOXEI16_V }, // 7902 |
27060 | | { PseudoVSOXEI16_V_M4_M8, VSOXEI16_V }, // 7903 |
27061 | | { PseudoVSOXEI16_V_M4_M8_MASK, VSOXEI16_V }, // 7904 |
27062 | | { PseudoVSOXEI16_V_M8_M4, VSOXEI16_V }, // 7905 |
27063 | | { PseudoVSOXEI16_V_M8_M4_MASK, VSOXEI16_V }, // 7906 |
27064 | | { PseudoVSOXEI16_V_M8_M8, VSOXEI16_V }, // 7907 |
27065 | | { PseudoVSOXEI16_V_M8_M8_MASK, VSOXEI16_V }, // 7908 |
27066 | | { PseudoVSOXEI16_V_MF2_M1, VSOXEI16_V }, // 7909 |
27067 | | { PseudoVSOXEI16_V_MF2_M1_MASK, VSOXEI16_V }, // 7910 |
27068 | | { PseudoVSOXEI16_V_MF2_M2, VSOXEI16_V }, // 7911 |
27069 | | { PseudoVSOXEI16_V_MF2_M2_MASK, VSOXEI16_V }, // 7912 |
27070 | | { PseudoVSOXEI16_V_MF2_MF2, VSOXEI16_V }, // 7913 |
27071 | | { PseudoVSOXEI16_V_MF2_MF2_MASK, VSOXEI16_V }, // 7914 |
27072 | | { PseudoVSOXEI16_V_MF2_MF4, VSOXEI16_V }, // 7915 |
27073 | | { PseudoVSOXEI16_V_MF2_MF4_MASK, VSOXEI16_V }, // 7916 |
27074 | | { PseudoVSOXEI16_V_MF4_M1, VSOXEI16_V }, // 7917 |
27075 | | { PseudoVSOXEI16_V_MF4_M1_MASK, VSOXEI16_V }, // 7918 |
27076 | | { PseudoVSOXEI16_V_MF4_MF2, VSOXEI16_V }, // 7919 |
27077 | | { PseudoVSOXEI16_V_MF4_MF2_MASK, VSOXEI16_V }, // 7920 |
27078 | | { PseudoVSOXEI16_V_MF4_MF4, VSOXEI16_V }, // 7921 |
27079 | | { PseudoVSOXEI16_V_MF4_MF4_MASK, VSOXEI16_V }, // 7922 |
27080 | | { PseudoVSOXEI16_V_MF4_MF8, VSOXEI16_V }, // 7923 |
27081 | | { PseudoVSOXEI16_V_MF4_MF8_MASK, VSOXEI16_V }, // 7924 |
27082 | | { PseudoVSOXEI32_V_M1_M1, VSOXEI32_V }, // 7925 |
27083 | | { PseudoVSOXEI32_V_M1_M1_MASK, VSOXEI32_V }, // 7926 |
27084 | | { PseudoVSOXEI32_V_M1_M2, VSOXEI32_V }, // 7927 |
27085 | | { PseudoVSOXEI32_V_M1_M2_MASK, VSOXEI32_V }, // 7928 |
27086 | | { PseudoVSOXEI32_V_M1_MF2, VSOXEI32_V }, // 7929 |
27087 | | { PseudoVSOXEI32_V_M1_MF2_MASK, VSOXEI32_V }, // 7930 |
27088 | | { PseudoVSOXEI32_V_M1_MF4, VSOXEI32_V }, // 7931 |
27089 | | { PseudoVSOXEI32_V_M1_MF4_MASK, VSOXEI32_V }, // 7932 |
27090 | | { PseudoVSOXEI32_V_M2_M1, VSOXEI32_V }, // 7933 |
27091 | | { PseudoVSOXEI32_V_M2_M1_MASK, VSOXEI32_V }, // 7934 |
27092 | | { PseudoVSOXEI32_V_M2_M2, VSOXEI32_V }, // 7935 |
27093 | | { PseudoVSOXEI32_V_M2_M2_MASK, VSOXEI32_V }, // 7936 |
27094 | | { PseudoVSOXEI32_V_M2_M4, VSOXEI32_V }, // 7937 |
27095 | | { PseudoVSOXEI32_V_M2_M4_MASK, VSOXEI32_V }, // 7938 |
27096 | | { PseudoVSOXEI32_V_M2_MF2, VSOXEI32_V }, // 7939 |
27097 | | { PseudoVSOXEI32_V_M2_MF2_MASK, VSOXEI32_V }, // 7940 |
27098 | | { PseudoVSOXEI32_V_M4_M1, VSOXEI32_V }, // 7941 |
27099 | | { PseudoVSOXEI32_V_M4_M1_MASK, VSOXEI32_V }, // 7942 |
27100 | | { PseudoVSOXEI32_V_M4_M2, VSOXEI32_V }, // 7943 |
27101 | | { PseudoVSOXEI32_V_M4_M2_MASK, VSOXEI32_V }, // 7944 |
27102 | | { PseudoVSOXEI32_V_M4_M4, VSOXEI32_V }, // 7945 |
27103 | | { PseudoVSOXEI32_V_M4_M4_MASK, VSOXEI32_V }, // 7946 |
27104 | | { PseudoVSOXEI32_V_M4_M8, VSOXEI32_V }, // 7947 |
27105 | | { PseudoVSOXEI32_V_M4_M8_MASK, VSOXEI32_V }, // 7948 |
27106 | | { PseudoVSOXEI32_V_M8_M2, VSOXEI32_V }, // 7949 |
27107 | | { PseudoVSOXEI32_V_M8_M2_MASK, VSOXEI32_V }, // 7950 |
27108 | | { PseudoVSOXEI32_V_M8_M4, VSOXEI32_V }, // 7951 |
27109 | | { PseudoVSOXEI32_V_M8_M4_MASK, VSOXEI32_V }, // 7952 |
27110 | | { PseudoVSOXEI32_V_M8_M8, VSOXEI32_V }, // 7953 |
27111 | | { PseudoVSOXEI32_V_M8_M8_MASK, VSOXEI32_V }, // 7954 |
27112 | | { PseudoVSOXEI32_V_MF2_M1, VSOXEI32_V }, // 7955 |
27113 | | { PseudoVSOXEI32_V_MF2_M1_MASK, VSOXEI32_V }, // 7956 |
27114 | | { PseudoVSOXEI32_V_MF2_MF2, VSOXEI32_V }, // 7957 |
27115 | | { PseudoVSOXEI32_V_MF2_MF2_MASK, VSOXEI32_V }, // 7958 |
27116 | | { PseudoVSOXEI32_V_MF2_MF4, VSOXEI32_V }, // 7959 |
27117 | | { PseudoVSOXEI32_V_MF2_MF4_MASK, VSOXEI32_V }, // 7960 |
27118 | | { PseudoVSOXEI32_V_MF2_MF8, VSOXEI32_V }, // 7961 |
27119 | | { PseudoVSOXEI32_V_MF2_MF8_MASK, VSOXEI32_V }, // 7962 |
27120 | | { PseudoVSOXEI64_V_M1_M1, VSOXEI64_V }, // 7963 |
27121 | | { PseudoVSOXEI64_V_M1_M1_MASK, VSOXEI64_V }, // 7964 |
27122 | | { PseudoVSOXEI64_V_M1_MF2, VSOXEI64_V }, // 7965 |
27123 | | { PseudoVSOXEI64_V_M1_MF2_MASK, VSOXEI64_V }, // 7966 |
27124 | | { PseudoVSOXEI64_V_M1_MF4, VSOXEI64_V }, // 7967 |
27125 | | { PseudoVSOXEI64_V_M1_MF4_MASK, VSOXEI64_V }, // 7968 |
27126 | | { PseudoVSOXEI64_V_M1_MF8, VSOXEI64_V }, // 7969 |
27127 | | { PseudoVSOXEI64_V_M1_MF8_MASK, VSOXEI64_V }, // 7970 |
27128 | | { PseudoVSOXEI64_V_M2_M1, VSOXEI64_V }, // 7971 |
27129 | | { PseudoVSOXEI64_V_M2_M1_MASK, VSOXEI64_V }, // 7972 |
27130 | | { PseudoVSOXEI64_V_M2_M2, VSOXEI64_V }, // 7973 |
27131 | | { PseudoVSOXEI64_V_M2_M2_MASK, VSOXEI64_V }, // 7974 |
27132 | | { PseudoVSOXEI64_V_M2_MF2, VSOXEI64_V }, // 7975 |
27133 | | { PseudoVSOXEI64_V_M2_MF2_MASK, VSOXEI64_V }, // 7976 |
27134 | | { PseudoVSOXEI64_V_M2_MF4, VSOXEI64_V }, // 7977 |
27135 | | { PseudoVSOXEI64_V_M2_MF4_MASK, VSOXEI64_V }, // 7978 |
27136 | | { PseudoVSOXEI64_V_M4_M1, VSOXEI64_V }, // 7979 |
27137 | | { PseudoVSOXEI64_V_M4_M1_MASK, VSOXEI64_V }, // 7980 |
27138 | | { PseudoVSOXEI64_V_M4_M2, VSOXEI64_V }, // 7981 |
27139 | | { PseudoVSOXEI64_V_M4_M2_MASK, VSOXEI64_V }, // 7982 |
27140 | | { PseudoVSOXEI64_V_M4_M4, VSOXEI64_V }, // 7983 |
27141 | | { PseudoVSOXEI64_V_M4_M4_MASK, VSOXEI64_V }, // 7984 |
27142 | | { PseudoVSOXEI64_V_M4_MF2, VSOXEI64_V }, // 7985 |
27143 | | { PseudoVSOXEI64_V_M4_MF2_MASK, VSOXEI64_V }, // 7986 |
27144 | | { PseudoVSOXEI64_V_M8_M1, VSOXEI64_V }, // 7987 |
27145 | | { PseudoVSOXEI64_V_M8_M1_MASK, VSOXEI64_V }, // 7988 |
27146 | | { PseudoVSOXEI64_V_M8_M2, VSOXEI64_V }, // 7989 |
27147 | | { PseudoVSOXEI64_V_M8_M2_MASK, VSOXEI64_V }, // 7990 |
27148 | | { PseudoVSOXEI64_V_M8_M4, VSOXEI64_V }, // 7991 |
27149 | | { PseudoVSOXEI64_V_M8_M4_MASK, VSOXEI64_V }, // 7992 |
27150 | | { PseudoVSOXEI64_V_M8_M8, VSOXEI64_V }, // 7993 |
27151 | | { PseudoVSOXEI64_V_M8_M8_MASK, VSOXEI64_V }, // 7994 |
27152 | | { PseudoVSOXEI8_V_M1_M1, VSOXEI8_V }, // 7995 |
27153 | | { PseudoVSOXEI8_V_M1_M1_MASK, VSOXEI8_V }, // 7996 |
27154 | | { PseudoVSOXEI8_V_M1_M2, VSOXEI8_V }, // 7997 |
27155 | | { PseudoVSOXEI8_V_M1_M2_MASK, VSOXEI8_V }, // 7998 |
27156 | | { PseudoVSOXEI8_V_M1_M4, VSOXEI8_V }, // 7999 |
27157 | | { PseudoVSOXEI8_V_M1_M4_MASK, VSOXEI8_V }, // 8000 |
27158 | | { PseudoVSOXEI8_V_M1_M8, VSOXEI8_V }, // 8001 |
27159 | | { PseudoVSOXEI8_V_M1_M8_MASK, VSOXEI8_V }, // 8002 |
27160 | | { PseudoVSOXEI8_V_M2_M2, VSOXEI8_V }, // 8003 |
27161 | | { PseudoVSOXEI8_V_M2_M2_MASK, VSOXEI8_V }, // 8004 |
27162 | | { PseudoVSOXEI8_V_M2_M4, VSOXEI8_V }, // 8005 |
27163 | | { PseudoVSOXEI8_V_M2_M4_MASK, VSOXEI8_V }, // 8006 |
27164 | | { PseudoVSOXEI8_V_M2_M8, VSOXEI8_V }, // 8007 |
27165 | | { PseudoVSOXEI8_V_M2_M8_MASK, VSOXEI8_V }, // 8008 |
27166 | | { PseudoVSOXEI8_V_M4_M4, VSOXEI8_V }, // 8009 |
27167 | | { PseudoVSOXEI8_V_M4_M4_MASK, VSOXEI8_V }, // 8010 |
27168 | | { PseudoVSOXEI8_V_M4_M8, VSOXEI8_V }, // 8011 |
27169 | | { PseudoVSOXEI8_V_M4_M8_MASK, VSOXEI8_V }, // 8012 |
27170 | | { PseudoVSOXEI8_V_M8_M8, VSOXEI8_V }, // 8013 |
27171 | | { PseudoVSOXEI8_V_M8_M8_MASK, VSOXEI8_V }, // 8014 |
27172 | | { PseudoVSOXEI8_V_MF2_M1, VSOXEI8_V }, // 8015 |
27173 | | { PseudoVSOXEI8_V_MF2_M1_MASK, VSOXEI8_V }, // 8016 |
27174 | | { PseudoVSOXEI8_V_MF2_M2, VSOXEI8_V }, // 8017 |
27175 | | { PseudoVSOXEI8_V_MF2_M2_MASK, VSOXEI8_V }, // 8018 |
27176 | | { PseudoVSOXEI8_V_MF2_M4, VSOXEI8_V }, // 8019 |
27177 | | { PseudoVSOXEI8_V_MF2_M4_MASK, VSOXEI8_V }, // 8020 |
27178 | | { PseudoVSOXEI8_V_MF2_MF2, VSOXEI8_V }, // 8021 |
27179 | | { PseudoVSOXEI8_V_MF2_MF2_MASK, VSOXEI8_V }, // 8022 |
27180 | | { PseudoVSOXEI8_V_MF4_M1, VSOXEI8_V }, // 8023 |
27181 | | { PseudoVSOXEI8_V_MF4_M1_MASK, VSOXEI8_V }, // 8024 |
27182 | | { PseudoVSOXEI8_V_MF4_M2, VSOXEI8_V }, // 8025 |
27183 | | { PseudoVSOXEI8_V_MF4_M2_MASK, VSOXEI8_V }, // 8026 |
27184 | | { PseudoVSOXEI8_V_MF4_MF2, VSOXEI8_V }, // 8027 |
27185 | | { PseudoVSOXEI8_V_MF4_MF2_MASK, VSOXEI8_V }, // 8028 |
27186 | | { PseudoVSOXEI8_V_MF4_MF4, VSOXEI8_V }, // 8029 |
27187 | | { PseudoVSOXEI8_V_MF4_MF4_MASK, VSOXEI8_V }, // 8030 |
27188 | | { PseudoVSOXEI8_V_MF8_M1, VSOXEI8_V }, // 8031 |
27189 | | { PseudoVSOXEI8_V_MF8_M1_MASK, VSOXEI8_V }, // 8032 |
27190 | | { PseudoVSOXEI8_V_MF8_MF2, VSOXEI8_V }, // 8033 |
27191 | | { PseudoVSOXEI8_V_MF8_MF2_MASK, VSOXEI8_V }, // 8034 |
27192 | | { PseudoVSOXEI8_V_MF8_MF4, VSOXEI8_V }, // 8035 |
27193 | | { PseudoVSOXEI8_V_MF8_MF4_MASK, VSOXEI8_V }, // 8036 |
27194 | | { PseudoVSOXEI8_V_MF8_MF8, VSOXEI8_V }, // 8037 |
27195 | | { PseudoVSOXEI8_V_MF8_MF8_MASK, VSOXEI8_V }, // 8038 |
27196 | | { PseudoVSOXSEG2EI16_V_M1_M1, VSOXSEG2EI16_V }, // 8039 |
27197 | | { PseudoVSOXSEG2EI16_V_M1_M1_MASK, VSOXSEG2EI16_V }, // 8040 |
27198 | | { PseudoVSOXSEG2EI16_V_M1_M2, VSOXSEG2EI16_V }, // 8041 |
27199 | | { PseudoVSOXSEG2EI16_V_M1_M2_MASK, VSOXSEG2EI16_V }, // 8042 |
27200 | | { PseudoVSOXSEG2EI16_V_M1_M4, VSOXSEG2EI16_V }, // 8043 |
27201 | | { PseudoVSOXSEG2EI16_V_M1_M4_MASK, VSOXSEG2EI16_V }, // 8044 |
27202 | | { PseudoVSOXSEG2EI16_V_M1_MF2, VSOXSEG2EI16_V }, // 8045 |
27203 | | { PseudoVSOXSEG2EI16_V_M1_MF2_MASK, VSOXSEG2EI16_V }, // 8046 |
27204 | | { PseudoVSOXSEG2EI16_V_M2_M1, VSOXSEG2EI16_V }, // 8047 |
27205 | | { PseudoVSOXSEG2EI16_V_M2_M1_MASK, VSOXSEG2EI16_V }, // 8048 |
27206 | | { PseudoVSOXSEG2EI16_V_M2_M2, VSOXSEG2EI16_V }, // 8049 |
27207 | | { PseudoVSOXSEG2EI16_V_M2_M2_MASK, VSOXSEG2EI16_V }, // 8050 |
27208 | | { PseudoVSOXSEG2EI16_V_M2_M4, VSOXSEG2EI16_V }, // 8051 |
27209 | | { PseudoVSOXSEG2EI16_V_M2_M4_MASK, VSOXSEG2EI16_V }, // 8052 |
27210 | | { PseudoVSOXSEG2EI16_V_M4_M2, VSOXSEG2EI16_V }, // 8053 |
27211 | | { PseudoVSOXSEG2EI16_V_M4_M2_MASK, VSOXSEG2EI16_V }, // 8054 |
27212 | | { PseudoVSOXSEG2EI16_V_M4_M4, VSOXSEG2EI16_V }, // 8055 |
27213 | | { PseudoVSOXSEG2EI16_V_M4_M4_MASK, VSOXSEG2EI16_V }, // 8056 |
27214 | | { PseudoVSOXSEG2EI16_V_M8_M4, VSOXSEG2EI16_V }, // 8057 |
27215 | | { PseudoVSOXSEG2EI16_V_M8_M4_MASK, VSOXSEG2EI16_V }, // 8058 |
27216 | | { PseudoVSOXSEG2EI16_V_MF2_M1, VSOXSEG2EI16_V }, // 8059 |
27217 | | { PseudoVSOXSEG2EI16_V_MF2_M1_MASK, VSOXSEG2EI16_V }, // 8060 |
27218 | | { PseudoVSOXSEG2EI16_V_MF2_M2, VSOXSEG2EI16_V }, // 8061 |
27219 | | { PseudoVSOXSEG2EI16_V_MF2_M2_MASK, VSOXSEG2EI16_V }, // 8062 |
27220 | | { PseudoVSOXSEG2EI16_V_MF2_MF2, VSOXSEG2EI16_V }, // 8063 |
27221 | | { PseudoVSOXSEG2EI16_V_MF2_MF2_MASK, VSOXSEG2EI16_V }, // 8064 |
27222 | | { PseudoVSOXSEG2EI16_V_MF2_MF4, VSOXSEG2EI16_V }, // 8065 |
27223 | | { PseudoVSOXSEG2EI16_V_MF2_MF4_MASK, VSOXSEG2EI16_V }, // 8066 |
27224 | | { PseudoVSOXSEG2EI16_V_MF4_M1, VSOXSEG2EI16_V }, // 8067 |
27225 | | { PseudoVSOXSEG2EI16_V_MF4_M1_MASK, VSOXSEG2EI16_V }, // 8068 |
27226 | | { PseudoVSOXSEG2EI16_V_MF4_MF2, VSOXSEG2EI16_V }, // 8069 |
27227 | | { PseudoVSOXSEG2EI16_V_MF4_MF2_MASK, VSOXSEG2EI16_V }, // 8070 |
27228 | | { PseudoVSOXSEG2EI16_V_MF4_MF4, VSOXSEG2EI16_V }, // 8071 |
27229 | | { PseudoVSOXSEG2EI16_V_MF4_MF4_MASK, VSOXSEG2EI16_V }, // 8072 |
27230 | | { PseudoVSOXSEG2EI16_V_MF4_MF8, VSOXSEG2EI16_V }, // 8073 |
27231 | | { PseudoVSOXSEG2EI16_V_MF4_MF8_MASK, VSOXSEG2EI16_V }, // 8074 |
27232 | | { PseudoVSOXSEG2EI32_V_M1_M1, VSOXSEG2EI32_V }, // 8075 |
27233 | | { PseudoVSOXSEG2EI32_V_M1_M1_MASK, VSOXSEG2EI32_V }, // 8076 |
27234 | | { PseudoVSOXSEG2EI32_V_M1_M2, VSOXSEG2EI32_V }, // 8077 |
27235 | | { PseudoVSOXSEG2EI32_V_M1_M2_MASK, VSOXSEG2EI32_V }, // 8078 |
27236 | | { PseudoVSOXSEG2EI32_V_M1_MF2, VSOXSEG2EI32_V }, // 8079 |
27237 | | { PseudoVSOXSEG2EI32_V_M1_MF2_MASK, VSOXSEG2EI32_V }, // 8080 |
27238 | | { PseudoVSOXSEG2EI32_V_M1_MF4, VSOXSEG2EI32_V }, // 8081 |
27239 | | { PseudoVSOXSEG2EI32_V_M1_MF4_MASK, VSOXSEG2EI32_V }, // 8082 |
27240 | | { PseudoVSOXSEG2EI32_V_M2_M1, VSOXSEG2EI32_V }, // 8083 |
27241 | | { PseudoVSOXSEG2EI32_V_M2_M1_MASK, VSOXSEG2EI32_V }, // 8084 |
27242 | | { PseudoVSOXSEG2EI32_V_M2_M2, VSOXSEG2EI32_V }, // 8085 |
27243 | | { PseudoVSOXSEG2EI32_V_M2_M2_MASK, VSOXSEG2EI32_V }, // 8086 |
27244 | | { PseudoVSOXSEG2EI32_V_M2_M4, VSOXSEG2EI32_V }, // 8087 |
27245 | | { PseudoVSOXSEG2EI32_V_M2_M4_MASK, VSOXSEG2EI32_V }, // 8088 |
27246 | | { PseudoVSOXSEG2EI32_V_M2_MF2, VSOXSEG2EI32_V }, // 8089 |
27247 | | { PseudoVSOXSEG2EI32_V_M2_MF2_MASK, VSOXSEG2EI32_V }, // 8090 |
27248 | | { PseudoVSOXSEG2EI32_V_M4_M1, VSOXSEG2EI32_V }, // 8091 |
27249 | | { PseudoVSOXSEG2EI32_V_M4_M1_MASK, VSOXSEG2EI32_V }, // 8092 |
27250 | | { PseudoVSOXSEG2EI32_V_M4_M2, VSOXSEG2EI32_V }, // 8093 |
27251 | | { PseudoVSOXSEG2EI32_V_M4_M2_MASK, VSOXSEG2EI32_V }, // 8094 |
27252 | | { PseudoVSOXSEG2EI32_V_M4_M4, VSOXSEG2EI32_V }, // 8095 |
27253 | | { PseudoVSOXSEG2EI32_V_M4_M4_MASK, VSOXSEG2EI32_V }, // 8096 |
27254 | | { PseudoVSOXSEG2EI32_V_M8_M2, VSOXSEG2EI32_V }, // 8097 |
27255 | | { PseudoVSOXSEG2EI32_V_M8_M2_MASK, VSOXSEG2EI32_V }, // 8098 |
27256 | | { PseudoVSOXSEG2EI32_V_M8_M4, VSOXSEG2EI32_V }, // 8099 |
27257 | | { PseudoVSOXSEG2EI32_V_M8_M4_MASK, VSOXSEG2EI32_V }, // 8100 |
27258 | | { PseudoVSOXSEG2EI32_V_MF2_M1, VSOXSEG2EI32_V }, // 8101 |
27259 | | { PseudoVSOXSEG2EI32_V_MF2_M1_MASK, VSOXSEG2EI32_V }, // 8102 |
27260 | | { PseudoVSOXSEG2EI32_V_MF2_MF2, VSOXSEG2EI32_V }, // 8103 |
27261 | | { PseudoVSOXSEG2EI32_V_MF2_MF2_MASK, VSOXSEG2EI32_V }, // 8104 |
27262 | | { PseudoVSOXSEG2EI32_V_MF2_MF4, VSOXSEG2EI32_V }, // 8105 |
27263 | | { PseudoVSOXSEG2EI32_V_MF2_MF4_MASK, VSOXSEG2EI32_V }, // 8106 |
27264 | | { PseudoVSOXSEG2EI32_V_MF2_MF8, VSOXSEG2EI32_V }, // 8107 |
27265 | | { PseudoVSOXSEG2EI32_V_MF2_MF8_MASK, VSOXSEG2EI32_V }, // 8108 |
27266 | | { PseudoVSOXSEG2EI64_V_M1_M1, VSOXSEG2EI64_V }, // 8109 |
27267 | | { PseudoVSOXSEG2EI64_V_M1_M1_MASK, VSOXSEG2EI64_V }, // 8110 |
27268 | | { PseudoVSOXSEG2EI64_V_M1_MF2, VSOXSEG2EI64_V }, // 8111 |
27269 | | { PseudoVSOXSEG2EI64_V_M1_MF2_MASK, VSOXSEG2EI64_V }, // 8112 |
27270 | | { PseudoVSOXSEG2EI64_V_M1_MF4, VSOXSEG2EI64_V }, // 8113 |
27271 | | { PseudoVSOXSEG2EI64_V_M1_MF4_MASK, VSOXSEG2EI64_V }, // 8114 |
27272 | | { PseudoVSOXSEG2EI64_V_M1_MF8, VSOXSEG2EI64_V }, // 8115 |
27273 | | { PseudoVSOXSEG2EI64_V_M1_MF8_MASK, VSOXSEG2EI64_V }, // 8116 |
27274 | | { PseudoVSOXSEG2EI64_V_M2_M1, VSOXSEG2EI64_V }, // 8117 |
27275 | | { PseudoVSOXSEG2EI64_V_M2_M1_MASK, VSOXSEG2EI64_V }, // 8118 |
27276 | | { PseudoVSOXSEG2EI64_V_M2_M2, VSOXSEG2EI64_V }, // 8119 |
27277 | | { PseudoVSOXSEG2EI64_V_M2_M2_MASK, VSOXSEG2EI64_V }, // 8120 |
27278 | | { PseudoVSOXSEG2EI64_V_M2_MF2, VSOXSEG2EI64_V }, // 8121 |
27279 | | { PseudoVSOXSEG2EI64_V_M2_MF2_MASK, VSOXSEG2EI64_V }, // 8122 |
27280 | | { PseudoVSOXSEG2EI64_V_M2_MF4, VSOXSEG2EI64_V }, // 8123 |
27281 | | { PseudoVSOXSEG2EI64_V_M2_MF4_MASK, VSOXSEG2EI64_V }, // 8124 |
27282 | | { PseudoVSOXSEG2EI64_V_M4_M1, VSOXSEG2EI64_V }, // 8125 |
27283 | | { PseudoVSOXSEG2EI64_V_M4_M1_MASK, VSOXSEG2EI64_V }, // 8126 |
27284 | | { PseudoVSOXSEG2EI64_V_M4_M2, VSOXSEG2EI64_V }, // 8127 |
27285 | | { PseudoVSOXSEG2EI64_V_M4_M2_MASK, VSOXSEG2EI64_V }, // 8128 |
27286 | | { PseudoVSOXSEG2EI64_V_M4_M4, VSOXSEG2EI64_V }, // 8129 |
27287 | | { PseudoVSOXSEG2EI64_V_M4_M4_MASK, VSOXSEG2EI64_V }, // 8130 |
27288 | | { PseudoVSOXSEG2EI64_V_M4_MF2, VSOXSEG2EI64_V }, // 8131 |
27289 | | { PseudoVSOXSEG2EI64_V_M4_MF2_MASK, VSOXSEG2EI64_V }, // 8132 |
27290 | | { PseudoVSOXSEG2EI64_V_M8_M1, VSOXSEG2EI64_V }, // 8133 |
27291 | | { PseudoVSOXSEG2EI64_V_M8_M1_MASK, VSOXSEG2EI64_V }, // 8134 |
27292 | | { PseudoVSOXSEG2EI64_V_M8_M2, VSOXSEG2EI64_V }, // 8135 |
27293 | | { PseudoVSOXSEG2EI64_V_M8_M2_MASK, VSOXSEG2EI64_V }, // 8136 |
27294 | | { PseudoVSOXSEG2EI64_V_M8_M4, VSOXSEG2EI64_V }, // 8137 |
27295 | | { PseudoVSOXSEG2EI64_V_M8_M4_MASK, VSOXSEG2EI64_V }, // 8138 |
27296 | | { PseudoVSOXSEG2EI8_V_M1_M1, VSOXSEG2EI8_V }, // 8139 |
27297 | | { PseudoVSOXSEG2EI8_V_M1_M1_MASK, VSOXSEG2EI8_V }, // 8140 |
27298 | | { PseudoVSOXSEG2EI8_V_M1_M2, VSOXSEG2EI8_V }, // 8141 |
27299 | | { PseudoVSOXSEG2EI8_V_M1_M2_MASK, VSOXSEG2EI8_V }, // 8142 |
27300 | | { PseudoVSOXSEG2EI8_V_M1_M4, VSOXSEG2EI8_V }, // 8143 |
27301 | | { PseudoVSOXSEG2EI8_V_M1_M4_MASK, VSOXSEG2EI8_V }, // 8144 |
27302 | | { PseudoVSOXSEG2EI8_V_M2_M2, VSOXSEG2EI8_V }, // 8145 |
27303 | | { PseudoVSOXSEG2EI8_V_M2_M2_MASK, VSOXSEG2EI8_V }, // 8146 |
27304 | | { PseudoVSOXSEG2EI8_V_M2_M4, VSOXSEG2EI8_V }, // 8147 |
27305 | | { PseudoVSOXSEG2EI8_V_M2_M4_MASK, VSOXSEG2EI8_V }, // 8148 |
27306 | | { PseudoVSOXSEG2EI8_V_M4_M4, VSOXSEG2EI8_V }, // 8149 |
27307 | | { PseudoVSOXSEG2EI8_V_M4_M4_MASK, VSOXSEG2EI8_V }, // 8150 |
27308 | | { PseudoVSOXSEG2EI8_V_MF2_M1, VSOXSEG2EI8_V }, // 8151 |
27309 | | { PseudoVSOXSEG2EI8_V_MF2_M1_MASK, VSOXSEG2EI8_V }, // 8152 |
27310 | | { PseudoVSOXSEG2EI8_V_MF2_M2, VSOXSEG2EI8_V }, // 8153 |
27311 | | { PseudoVSOXSEG2EI8_V_MF2_M2_MASK, VSOXSEG2EI8_V }, // 8154 |
27312 | | { PseudoVSOXSEG2EI8_V_MF2_M4, VSOXSEG2EI8_V }, // 8155 |
27313 | | { PseudoVSOXSEG2EI8_V_MF2_M4_MASK, VSOXSEG2EI8_V }, // 8156 |
27314 | | { PseudoVSOXSEG2EI8_V_MF2_MF2, VSOXSEG2EI8_V }, // 8157 |
27315 | | { PseudoVSOXSEG2EI8_V_MF2_MF2_MASK, VSOXSEG2EI8_V }, // 8158 |
27316 | | { PseudoVSOXSEG2EI8_V_MF4_M1, VSOXSEG2EI8_V }, // 8159 |
27317 | | { PseudoVSOXSEG2EI8_V_MF4_M1_MASK, VSOXSEG2EI8_V }, // 8160 |
27318 | | { PseudoVSOXSEG2EI8_V_MF4_M2, VSOXSEG2EI8_V }, // 8161 |
27319 | | { PseudoVSOXSEG2EI8_V_MF4_M2_MASK, VSOXSEG2EI8_V }, // 8162 |
27320 | | { PseudoVSOXSEG2EI8_V_MF4_MF2, VSOXSEG2EI8_V }, // 8163 |
27321 | | { PseudoVSOXSEG2EI8_V_MF4_MF2_MASK, VSOXSEG2EI8_V }, // 8164 |
27322 | | { PseudoVSOXSEG2EI8_V_MF4_MF4, VSOXSEG2EI8_V }, // 8165 |
27323 | | { PseudoVSOXSEG2EI8_V_MF4_MF4_MASK, VSOXSEG2EI8_V }, // 8166 |
27324 | | { PseudoVSOXSEG2EI8_V_MF8_M1, VSOXSEG2EI8_V }, // 8167 |
27325 | | { PseudoVSOXSEG2EI8_V_MF8_M1_MASK, VSOXSEG2EI8_V }, // 8168 |
27326 | | { PseudoVSOXSEG2EI8_V_MF8_MF2, VSOXSEG2EI8_V }, // 8169 |
27327 | | { PseudoVSOXSEG2EI8_V_MF8_MF2_MASK, VSOXSEG2EI8_V }, // 8170 |
27328 | | { PseudoVSOXSEG2EI8_V_MF8_MF4, VSOXSEG2EI8_V }, // 8171 |
27329 | | { PseudoVSOXSEG2EI8_V_MF8_MF4_MASK, VSOXSEG2EI8_V }, // 8172 |
27330 | | { PseudoVSOXSEG2EI8_V_MF8_MF8, VSOXSEG2EI8_V }, // 8173 |
27331 | | { PseudoVSOXSEG2EI8_V_MF8_MF8_MASK, VSOXSEG2EI8_V }, // 8174 |
27332 | | { PseudoVSOXSEG3EI16_V_M1_M1, VSOXSEG3EI16_V }, // 8175 |
27333 | | { PseudoVSOXSEG3EI16_V_M1_M1_MASK, VSOXSEG3EI16_V }, // 8176 |
27334 | | { PseudoVSOXSEG3EI16_V_M1_M2, VSOXSEG3EI16_V }, // 8177 |
27335 | | { PseudoVSOXSEG3EI16_V_M1_M2_MASK, VSOXSEG3EI16_V }, // 8178 |
27336 | | { PseudoVSOXSEG3EI16_V_M1_MF2, VSOXSEG3EI16_V }, // 8179 |
27337 | | { PseudoVSOXSEG3EI16_V_M1_MF2_MASK, VSOXSEG3EI16_V }, // 8180 |
27338 | | { PseudoVSOXSEG3EI16_V_M2_M1, VSOXSEG3EI16_V }, // 8181 |
27339 | | { PseudoVSOXSEG3EI16_V_M2_M1_MASK, VSOXSEG3EI16_V }, // 8182 |
27340 | | { PseudoVSOXSEG3EI16_V_M2_M2, VSOXSEG3EI16_V }, // 8183 |
27341 | | { PseudoVSOXSEG3EI16_V_M2_M2_MASK, VSOXSEG3EI16_V }, // 8184 |
27342 | | { PseudoVSOXSEG3EI16_V_M4_M2, VSOXSEG3EI16_V }, // 8185 |
27343 | | { PseudoVSOXSEG3EI16_V_M4_M2_MASK, VSOXSEG3EI16_V }, // 8186 |
27344 | | { PseudoVSOXSEG3EI16_V_MF2_M1, VSOXSEG3EI16_V }, // 8187 |
27345 | | { PseudoVSOXSEG3EI16_V_MF2_M1_MASK, VSOXSEG3EI16_V }, // 8188 |
27346 | | { PseudoVSOXSEG3EI16_V_MF2_M2, VSOXSEG3EI16_V }, // 8189 |
27347 | | { PseudoVSOXSEG3EI16_V_MF2_M2_MASK, VSOXSEG3EI16_V }, // 8190 |
27348 | | { PseudoVSOXSEG3EI16_V_MF2_MF2, VSOXSEG3EI16_V }, // 8191 |
27349 | | { PseudoVSOXSEG3EI16_V_MF2_MF2_MASK, VSOXSEG3EI16_V }, // 8192 |
27350 | | { PseudoVSOXSEG3EI16_V_MF2_MF4, VSOXSEG3EI16_V }, // 8193 |
27351 | | { PseudoVSOXSEG3EI16_V_MF2_MF4_MASK, VSOXSEG3EI16_V }, // 8194 |
27352 | | { PseudoVSOXSEG3EI16_V_MF4_M1, VSOXSEG3EI16_V }, // 8195 |
27353 | | { PseudoVSOXSEG3EI16_V_MF4_M1_MASK, VSOXSEG3EI16_V }, // 8196 |
27354 | | { PseudoVSOXSEG3EI16_V_MF4_MF2, VSOXSEG3EI16_V }, // 8197 |
27355 | | { PseudoVSOXSEG3EI16_V_MF4_MF2_MASK, VSOXSEG3EI16_V }, // 8198 |
27356 | | { PseudoVSOXSEG3EI16_V_MF4_MF4, VSOXSEG3EI16_V }, // 8199 |
27357 | | { PseudoVSOXSEG3EI16_V_MF4_MF4_MASK, VSOXSEG3EI16_V }, // 8200 |
27358 | | { PseudoVSOXSEG3EI16_V_MF4_MF8, VSOXSEG3EI16_V }, // 8201 |
27359 | | { PseudoVSOXSEG3EI16_V_MF4_MF8_MASK, VSOXSEG3EI16_V }, // 8202 |
27360 | | { PseudoVSOXSEG3EI32_V_M1_M1, VSOXSEG3EI32_V }, // 8203 |
27361 | | { PseudoVSOXSEG3EI32_V_M1_M1_MASK, VSOXSEG3EI32_V }, // 8204 |
27362 | | { PseudoVSOXSEG3EI32_V_M1_M2, VSOXSEG3EI32_V }, // 8205 |
27363 | | { PseudoVSOXSEG3EI32_V_M1_M2_MASK, VSOXSEG3EI32_V }, // 8206 |
27364 | | { PseudoVSOXSEG3EI32_V_M1_MF2, VSOXSEG3EI32_V }, // 8207 |
27365 | | { PseudoVSOXSEG3EI32_V_M1_MF2_MASK, VSOXSEG3EI32_V }, // 8208 |
27366 | | { PseudoVSOXSEG3EI32_V_M1_MF4, VSOXSEG3EI32_V }, // 8209 |
27367 | | { PseudoVSOXSEG3EI32_V_M1_MF4_MASK, VSOXSEG3EI32_V }, // 8210 |
27368 | | { PseudoVSOXSEG3EI32_V_M2_M1, VSOXSEG3EI32_V }, // 8211 |
27369 | | { PseudoVSOXSEG3EI32_V_M2_M1_MASK, VSOXSEG3EI32_V }, // 8212 |
27370 | | { PseudoVSOXSEG3EI32_V_M2_M2, VSOXSEG3EI32_V }, // 8213 |
27371 | | { PseudoVSOXSEG3EI32_V_M2_M2_MASK, VSOXSEG3EI32_V }, // 8214 |
27372 | | { PseudoVSOXSEG3EI32_V_M2_MF2, VSOXSEG3EI32_V }, // 8215 |
27373 | | { PseudoVSOXSEG3EI32_V_M2_MF2_MASK, VSOXSEG3EI32_V }, // 8216 |
27374 | | { PseudoVSOXSEG3EI32_V_M4_M1, VSOXSEG3EI32_V }, // 8217 |
27375 | | { PseudoVSOXSEG3EI32_V_M4_M1_MASK, VSOXSEG3EI32_V }, // 8218 |
27376 | | { PseudoVSOXSEG3EI32_V_M4_M2, VSOXSEG3EI32_V }, // 8219 |
27377 | | { PseudoVSOXSEG3EI32_V_M4_M2_MASK, VSOXSEG3EI32_V }, // 8220 |
27378 | | { PseudoVSOXSEG3EI32_V_M8_M2, VSOXSEG3EI32_V }, // 8221 |
27379 | | { PseudoVSOXSEG3EI32_V_M8_M2_MASK, VSOXSEG3EI32_V }, // 8222 |
27380 | | { PseudoVSOXSEG3EI32_V_MF2_M1, VSOXSEG3EI32_V }, // 8223 |
27381 | | { PseudoVSOXSEG3EI32_V_MF2_M1_MASK, VSOXSEG3EI32_V }, // 8224 |
27382 | | { PseudoVSOXSEG3EI32_V_MF2_MF2, VSOXSEG3EI32_V }, // 8225 |
27383 | | { PseudoVSOXSEG3EI32_V_MF2_MF2_MASK, VSOXSEG3EI32_V }, // 8226 |
27384 | | { PseudoVSOXSEG3EI32_V_MF2_MF4, VSOXSEG3EI32_V }, // 8227 |
27385 | | { PseudoVSOXSEG3EI32_V_MF2_MF4_MASK, VSOXSEG3EI32_V }, // 8228 |
27386 | | { PseudoVSOXSEG3EI32_V_MF2_MF8, VSOXSEG3EI32_V }, // 8229 |
27387 | | { PseudoVSOXSEG3EI32_V_MF2_MF8_MASK, VSOXSEG3EI32_V }, // 8230 |
27388 | | { PseudoVSOXSEG3EI64_V_M1_M1, VSOXSEG3EI64_V }, // 8231 |
27389 | | { PseudoVSOXSEG3EI64_V_M1_M1_MASK, VSOXSEG3EI64_V }, // 8232 |
27390 | | { PseudoVSOXSEG3EI64_V_M1_MF2, VSOXSEG3EI64_V }, // 8233 |
27391 | | { PseudoVSOXSEG3EI64_V_M1_MF2_MASK, VSOXSEG3EI64_V }, // 8234 |
27392 | | { PseudoVSOXSEG3EI64_V_M1_MF4, VSOXSEG3EI64_V }, // 8235 |
27393 | | { PseudoVSOXSEG3EI64_V_M1_MF4_MASK, VSOXSEG3EI64_V }, // 8236 |
27394 | | { PseudoVSOXSEG3EI64_V_M1_MF8, VSOXSEG3EI64_V }, // 8237 |
27395 | | { PseudoVSOXSEG3EI64_V_M1_MF8_MASK, VSOXSEG3EI64_V }, // 8238 |
27396 | | { PseudoVSOXSEG3EI64_V_M2_M1, VSOXSEG3EI64_V }, // 8239 |
27397 | | { PseudoVSOXSEG3EI64_V_M2_M1_MASK, VSOXSEG3EI64_V }, // 8240 |
27398 | | { PseudoVSOXSEG3EI64_V_M2_M2, VSOXSEG3EI64_V }, // 8241 |
27399 | | { PseudoVSOXSEG3EI64_V_M2_M2_MASK, VSOXSEG3EI64_V }, // 8242 |
27400 | | { PseudoVSOXSEG3EI64_V_M2_MF2, VSOXSEG3EI64_V }, // 8243 |
27401 | | { PseudoVSOXSEG3EI64_V_M2_MF2_MASK, VSOXSEG3EI64_V }, // 8244 |
27402 | | { PseudoVSOXSEG3EI64_V_M2_MF4, VSOXSEG3EI64_V }, // 8245 |
27403 | | { PseudoVSOXSEG3EI64_V_M2_MF4_MASK, VSOXSEG3EI64_V }, // 8246 |
27404 | | { PseudoVSOXSEG3EI64_V_M4_M1, VSOXSEG3EI64_V }, // 8247 |
27405 | | { PseudoVSOXSEG3EI64_V_M4_M1_MASK, VSOXSEG3EI64_V }, // 8248 |
27406 | | { PseudoVSOXSEG3EI64_V_M4_M2, VSOXSEG3EI64_V }, // 8249 |
27407 | | { PseudoVSOXSEG3EI64_V_M4_M2_MASK, VSOXSEG3EI64_V }, // 8250 |
27408 | | { PseudoVSOXSEG3EI64_V_M4_MF2, VSOXSEG3EI64_V }, // 8251 |
27409 | | { PseudoVSOXSEG3EI64_V_M4_MF2_MASK, VSOXSEG3EI64_V }, // 8252 |
27410 | | { PseudoVSOXSEG3EI64_V_M8_M1, VSOXSEG3EI64_V }, // 8253 |
27411 | | { PseudoVSOXSEG3EI64_V_M8_M1_MASK, VSOXSEG3EI64_V }, // 8254 |
27412 | | { PseudoVSOXSEG3EI64_V_M8_M2, VSOXSEG3EI64_V }, // 8255 |
27413 | | { PseudoVSOXSEG3EI64_V_M8_M2_MASK, VSOXSEG3EI64_V }, // 8256 |
27414 | | { PseudoVSOXSEG3EI8_V_M1_M1, VSOXSEG3EI8_V }, // 8257 |
27415 | | { PseudoVSOXSEG3EI8_V_M1_M1_MASK, VSOXSEG3EI8_V }, // 8258 |
27416 | | { PseudoVSOXSEG3EI8_V_M1_M2, VSOXSEG3EI8_V }, // 8259 |
27417 | | { PseudoVSOXSEG3EI8_V_M1_M2_MASK, VSOXSEG3EI8_V }, // 8260 |
27418 | | { PseudoVSOXSEG3EI8_V_M2_M2, VSOXSEG3EI8_V }, // 8261 |
27419 | | { PseudoVSOXSEG3EI8_V_M2_M2_MASK, VSOXSEG3EI8_V }, // 8262 |
27420 | | { PseudoVSOXSEG3EI8_V_MF2_M1, VSOXSEG3EI8_V }, // 8263 |
27421 | | { PseudoVSOXSEG3EI8_V_MF2_M1_MASK, VSOXSEG3EI8_V }, // 8264 |
27422 | | { PseudoVSOXSEG3EI8_V_MF2_M2, VSOXSEG3EI8_V }, // 8265 |
27423 | | { PseudoVSOXSEG3EI8_V_MF2_M2_MASK, VSOXSEG3EI8_V }, // 8266 |
27424 | | { PseudoVSOXSEG3EI8_V_MF2_MF2, VSOXSEG3EI8_V }, // 8267 |
27425 | | { PseudoVSOXSEG3EI8_V_MF2_MF2_MASK, VSOXSEG3EI8_V }, // 8268 |
27426 | | { PseudoVSOXSEG3EI8_V_MF4_M1, VSOXSEG3EI8_V }, // 8269 |
27427 | | { PseudoVSOXSEG3EI8_V_MF4_M1_MASK, VSOXSEG3EI8_V }, // 8270 |
27428 | | { PseudoVSOXSEG3EI8_V_MF4_M2, VSOXSEG3EI8_V }, // 8271 |
27429 | | { PseudoVSOXSEG3EI8_V_MF4_M2_MASK, VSOXSEG3EI8_V }, // 8272 |
27430 | | { PseudoVSOXSEG3EI8_V_MF4_MF2, VSOXSEG3EI8_V }, // 8273 |
27431 | | { PseudoVSOXSEG3EI8_V_MF4_MF2_MASK, VSOXSEG3EI8_V }, // 8274 |
27432 | | { PseudoVSOXSEG3EI8_V_MF4_MF4, VSOXSEG3EI8_V }, // 8275 |
27433 | | { PseudoVSOXSEG3EI8_V_MF4_MF4_MASK, VSOXSEG3EI8_V }, // 8276 |
27434 | | { PseudoVSOXSEG3EI8_V_MF8_M1, VSOXSEG3EI8_V }, // 8277 |
27435 | | { PseudoVSOXSEG3EI8_V_MF8_M1_MASK, VSOXSEG3EI8_V }, // 8278 |
27436 | | { PseudoVSOXSEG3EI8_V_MF8_MF2, VSOXSEG3EI8_V }, // 8279 |
27437 | | { PseudoVSOXSEG3EI8_V_MF8_MF2_MASK, VSOXSEG3EI8_V }, // 8280 |
27438 | | { PseudoVSOXSEG3EI8_V_MF8_MF4, VSOXSEG3EI8_V }, // 8281 |
27439 | | { PseudoVSOXSEG3EI8_V_MF8_MF4_MASK, VSOXSEG3EI8_V }, // 8282 |
27440 | | { PseudoVSOXSEG3EI8_V_MF8_MF8, VSOXSEG3EI8_V }, // 8283 |
27441 | | { PseudoVSOXSEG3EI8_V_MF8_MF8_MASK, VSOXSEG3EI8_V }, // 8284 |
27442 | | { PseudoVSOXSEG4EI16_V_M1_M1, VSOXSEG4EI16_V }, // 8285 |
27443 | | { PseudoVSOXSEG4EI16_V_M1_M1_MASK, VSOXSEG4EI16_V }, // 8286 |
27444 | | { PseudoVSOXSEG4EI16_V_M1_M2, VSOXSEG4EI16_V }, // 8287 |
27445 | | { PseudoVSOXSEG4EI16_V_M1_M2_MASK, VSOXSEG4EI16_V }, // 8288 |
27446 | | { PseudoVSOXSEG4EI16_V_M1_MF2, VSOXSEG4EI16_V }, // 8289 |
27447 | | { PseudoVSOXSEG4EI16_V_M1_MF2_MASK, VSOXSEG4EI16_V }, // 8290 |
27448 | | { PseudoVSOXSEG4EI16_V_M2_M1, VSOXSEG4EI16_V }, // 8291 |
27449 | | { PseudoVSOXSEG4EI16_V_M2_M1_MASK, VSOXSEG4EI16_V }, // 8292 |
27450 | | { PseudoVSOXSEG4EI16_V_M2_M2, VSOXSEG4EI16_V }, // 8293 |
27451 | | { PseudoVSOXSEG4EI16_V_M2_M2_MASK, VSOXSEG4EI16_V }, // 8294 |
27452 | | { PseudoVSOXSEG4EI16_V_M4_M2, VSOXSEG4EI16_V }, // 8295 |
27453 | | { PseudoVSOXSEG4EI16_V_M4_M2_MASK, VSOXSEG4EI16_V }, // 8296 |
27454 | | { PseudoVSOXSEG4EI16_V_MF2_M1, VSOXSEG4EI16_V }, // 8297 |
27455 | | { PseudoVSOXSEG4EI16_V_MF2_M1_MASK, VSOXSEG4EI16_V }, // 8298 |
27456 | | { PseudoVSOXSEG4EI16_V_MF2_M2, VSOXSEG4EI16_V }, // 8299 |
27457 | | { PseudoVSOXSEG4EI16_V_MF2_M2_MASK, VSOXSEG4EI16_V }, // 8300 |
27458 | | { PseudoVSOXSEG4EI16_V_MF2_MF2, VSOXSEG4EI16_V }, // 8301 |
27459 | | { PseudoVSOXSEG4EI16_V_MF2_MF2_MASK, VSOXSEG4EI16_V }, // 8302 |
27460 | | { PseudoVSOXSEG4EI16_V_MF2_MF4, VSOXSEG4EI16_V }, // 8303 |
27461 | | { PseudoVSOXSEG4EI16_V_MF2_MF4_MASK, VSOXSEG4EI16_V }, // 8304 |
27462 | | { PseudoVSOXSEG4EI16_V_MF4_M1, VSOXSEG4EI16_V }, // 8305 |
27463 | | { PseudoVSOXSEG4EI16_V_MF4_M1_MASK, VSOXSEG4EI16_V }, // 8306 |
27464 | | { PseudoVSOXSEG4EI16_V_MF4_MF2, VSOXSEG4EI16_V }, // 8307 |
27465 | | { PseudoVSOXSEG4EI16_V_MF4_MF2_MASK, VSOXSEG4EI16_V }, // 8308 |
27466 | | { PseudoVSOXSEG4EI16_V_MF4_MF4, VSOXSEG4EI16_V }, // 8309 |
27467 | | { PseudoVSOXSEG4EI16_V_MF4_MF4_MASK, VSOXSEG4EI16_V }, // 8310 |
27468 | | { PseudoVSOXSEG4EI16_V_MF4_MF8, VSOXSEG4EI16_V }, // 8311 |
27469 | | { PseudoVSOXSEG4EI16_V_MF4_MF8_MASK, VSOXSEG4EI16_V }, // 8312 |
27470 | | { PseudoVSOXSEG4EI32_V_M1_M1, VSOXSEG4EI32_V }, // 8313 |
27471 | | { PseudoVSOXSEG4EI32_V_M1_M1_MASK, VSOXSEG4EI32_V }, // 8314 |
27472 | | { PseudoVSOXSEG4EI32_V_M1_M2, VSOXSEG4EI32_V }, // 8315 |
27473 | | { PseudoVSOXSEG4EI32_V_M1_M2_MASK, VSOXSEG4EI32_V }, // 8316 |
27474 | | { PseudoVSOXSEG4EI32_V_M1_MF2, VSOXSEG4EI32_V }, // 8317 |
27475 | | { PseudoVSOXSEG4EI32_V_M1_MF2_MASK, VSOXSEG4EI32_V }, // 8318 |
27476 | | { PseudoVSOXSEG4EI32_V_M1_MF4, VSOXSEG4EI32_V }, // 8319 |
27477 | | { PseudoVSOXSEG4EI32_V_M1_MF4_MASK, VSOXSEG4EI32_V }, // 8320 |
27478 | | { PseudoVSOXSEG4EI32_V_M2_M1, VSOXSEG4EI32_V }, // 8321 |
27479 | | { PseudoVSOXSEG4EI32_V_M2_M1_MASK, VSOXSEG4EI32_V }, // 8322 |
27480 | | { PseudoVSOXSEG4EI32_V_M2_M2, VSOXSEG4EI32_V }, // 8323 |
27481 | | { PseudoVSOXSEG4EI32_V_M2_M2_MASK, VSOXSEG4EI32_V }, // 8324 |
27482 | | { PseudoVSOXSEG4EI32_V_M2_MF2, VSOXSEG4EI32_V }, // 8325 |
27483 | | { PseudoVSOXSEG4EI32_V_M2_MF2_MASK, VSOXSEG4EI32_V }, // 8326 |
27484 | | { PseudoVSOXSEG4EI32_V_M4_M1, VSOXSEG4EI32_V }, // 8327 |
27485 | | { PseudoVSOXSEG4EI32_V_M4_M1_MASK, VSOXSEG4EI32_V }, // 8328 |
27486 | | { PseudoVSOXSEG4EI32_V_M4_M2, VSOXSEG4EI32_V }, // 8329 |
27487 | | { PseudoVSOXSEG4EI32_V_M4_M2_MASK, VSOXSEG4EI32_V }, // 8330 |
27488 | | { PseudoVSOXSEG4EI32_V_M8_M2, VSOXSEG4EI32_V }, // 8331 |
27489 | | { PseudoVSOXSEG4EI32_V_M8_M2_MASK, VSOXSEG4EI32_V }, // 8332 |
27490 | | { PseudoVSOXSEG4EI32_V_MF2_M1, VSOXSEG4EI32_V }, // 8333 |
27491 | | { PseudoVSOXSEG4EI32_V_MF2_M1_MASK, VSOXSEG4EI32_V }, // 8334 |
27492 | | { PseudoVSOXSEG4EI32_V_MF2_MF2, VSOXSEG4EI32_V }, // 8335 |
27493 | | { PseudoVSOXSEG4EI32_V_MF2_MF2_MASK, VSOXSEG4EI32_V }, // 8336 |
27494 | | { PseudoVSOXSEG4EI32_V_MF2_MF4, VSOXSEG4EI32_V }, // 8337 |
27495 | | { PseudoVSOXSEG4EI32_V_MF2_MF4_MASK, VSOXSEG4EI32_V }, // 8338 |
27496 | | { PseudoVSOXSEG4EI32_V_MF2_MF8, VSOXSEG4EI32_V }, // 8339 |
27497 | | { PseudoVSOXSEG4EI32_V_MF2_MF8_MASK, VSOXSEG4EI32_V }, // 8340 |
27498 | | { PseudoVSOXSEG4EI64_V_M1_M1, VSOXSEG4EI64_V }, // 8341 |
27499 | | { PseudoVSOXSEG4EI64_V_M1_M1_MASK, VSOXSEG4EI64_V }, // 8342 |
27500 | | { PseudoVSOXSEG4EI64_V_M1_MF2, VSOXSEG4EI64_V }, // 8343 |
27501 | | { PseudoVSOXSEG4EI64_V_M1_MF2_MASK, VSOXSEG4EI64_V }, // 8344 |
27502 | | { PseudoVSOXSEG4EI64_V_M1_MF4, VSOXSEG4EI64_V }, // 8345 |
27503 | | { PseudoVSOXSEG4EI64_V_M1_MF4_MASK, VSOXSEG4EI64_V }, // 8346 |
27504 | | { PseudoVSOXSEG4EI64_V_M1_MF8, VSOXSEG4EI64_V }, // 8347 |
27505 | | { PseudoVSOXSEG4EI64_V_M1_MF8_MASK, VSOXSEG4EI64_V }, // 8348 |
27506 | | { PseudoVSOXSEG4EI64_V_M2_M1, VSOXSEG4EI64_V }, // 8349 |
27507 | | { PseudoVSOXSEG4EI64_V_M2_M1_MASK, VSOXSEG4EI64_V }, // 8350 |
27508 | | { PseudoVSOXSEG4EI64_V_M2_M2, VSOXSEG4EI64_V }, // 8351 |
27509 | | { PseudoVSOXSEG4EI64_V_M2_M2_MASK, VSOXSEG4EI64_V }, // 8352 |
27510 | | { PseudoVSOXSEG4EI64_V_M2_MF2, VSOXSEG4EI64_V }, // 8353 |
27511 | | { PseudoVSOXSEG4EI64_V_M2_MF2_MASK, VSOXSEG4EI64_V }, // 8354 |
27512 | | { PseudoVSOXSEG4EI64_V_M2_MF4, VSOXSEG4EI64_V }, // 8355 |
27513 | | { PseudoVSOXSEG4EI64_V_M2_MF4_MASK, VSOXSEG4EI64_V }, // 8356 |
27514 | | { PseudoVSOXSEG4EI64_V_M4_M1, VSOXSEG4EI64_V }, // 8357 |
27515 | | { PseudoVSOXSEG4EI64_V_M4_M1_MASK, VSOXSEG4EI64_V }, // 8358 |
27516 | | { PseudoVSOXSEG4EI64_V_M4_M2, VSOXSEG4EI64_V }, // 8359 |
27517 | | { PseudoVSOXSEG4EI64_V_M4_M2_MASK, VSOXSEG4EI64_V }, // 8360 |
27518 | | { PseudoVSOXSEG4EI64_V_M4_MF2, VSOXSEG4EI64_V }, // 8361 |
27519 | | { PseudoVSOXSEG4EI64_V_M4_MF2_MASK, VSOXSEG4EI64_V }, // 8362 |
27520 | | { PseudoVSOXSEG4EI64_V_M8_M1, VSOXSEG4EI64_V }, // 8363 |
27521 | | { PseudoVSOXSEG4EI64_V_M8_M1_MASK, VSOXSEG4EI64_V }, // 8364 |
27522 | | { PseudoVSOXSEG4EI64_V_M8_M2, VSOXSEG4EI64_V }, // 8365 |
27523 | | { PseudoVSOXSEG4EI64_V_M8_M2_MASK, VSOXSEG4EI64_V }, // 8366 |
27524 | | { PseudoVSOXSEG4EI8_V_M1_M1, VSOXSEG4EI8_V }, // 8367 |
27525 | | { PseudoVSOXSEG4EI8_V_M1_M1_MASK, VSOXSEG4EI8_V }, // 8368 |
27526 | | { PseudoVSOXSEG4EI8_V_M1_M2, VSOXSEG4EI8_V }, // 8369 |
27527 | | { PseudoVSOXSEG4EI8_V_M1_M2_MASK, VSOXSEG4EI8_V }, // 8370 |
27528 | | { PseudoVSOXSEG4EI8_V_M2_M2, VSOXSEG4EI8_V }, // 8371 |
27529 | | { PseudoVSOXSEG4EI8_V_M2_M2_MASK, VSOXSEG4EI8_V }, // 8372 |
27530 | | { PseudoVSOXSEG4EI8_V_MF2_M1, VSOXSEG4EI8_V }, // 8373 |
27531 | | { PseudoVSOXSEG4EI8_V_MF2_M1_MASK, VSOXSEG4EI8_V }, // 8374 |
27532 | | { PseudoVSOXSEG4EI8_V_MF2_M2, VSOXSEG4EI8_V }, // 8375 |
27533 | | { PseudoVSOXSEG4EI8_V_MF2_M2_MASK, VSOXSEG4EI8_V }, // 8376 |
27534 | | { PseudoVSOXSEG4EI8_V_MF2_MF2, VSOXSEG4EI8_V }, // 8377 |
27535 | | { PseudoVSOXSEG4EI8_V_MF2_MF2_MASK, VSOXSEG4EI8_V }, // 8378 |
27536 | | { PseudoVSOXSEG4EI8_V_MF4_M1, VSOXSEG4EI8_V }, // 8379 |
27537 | | { PseudoVSOXSEG4EI8_V_MF4_M1_MASK, VSOXSEG4EI8_V }, // 8380 |
27538 | | { PseudoVSOXSEG4EI8_V_MF4_M2, VSOXSEG4EI8_V }, // 8381 |
27539 | | { PseudoVSOXSEG4EI8_V_MF4_M2_MASK, VSOXSEG4EI8_V }, // 8382 |
27540 | | { PseudoVSOXSEG4EI8_V_MF4_MF2, VSOXSEG4EI8_V }, // 8383 |
27541 | | { PseudoVSOXSEG4EI8_V_MF4_MF2_MASK, VSOXSEG4EI8_V }, // 8384 |
27542 | | { PseudoVSOXSEG4EI8_V_MF4_MF4, VSOXSEG4EI8_V }, // 8385 |
27543 | | { PseudoVSOXSEG4EI8_V_MF4_MF4_MASK, VSOXSEG4EI8_V }, // 8386 |
27544 | | { PseudoVSOXSEG4EI8_V_MF8_M1, VSOXSEG4EI8_V }, // 8387 |
27545 | | { PseudoVSOXSEG4EI8_V_MF8_M1_MASK, VSOXSEG4EI8_V }, // 8388 |
27546 | | { PseudoVSOXSEG4EI8_V_MF8_MF2, VSOXSEG4EI8_V }, // 8389 |
27547 | | { PseudoVSOXSEG4EI8_V_MF8_MF2_MASK, VSOXSEG4EI8_V }, // 8390 |
27548 | | { PseudoVSOXSEG4EI8_V_MF8_MF4, VSOXSEG4EI8_V }, // 8391 |
27549 | | { PseudoVSOXSEG4EI8_V_MF8_MF4_MASK, VSOXSEG4EI8_V }, // 8392 |
27550 | | { PseudoVSOXSEG4EI8_V_MF8_MF8, VSOXSEG4EI8_V }, // 8393 |
27551 | | { PseudoVSOXSEG4EI8_V_MF8_MF8_MASK, VSOXSEG4EI8_V }, // 8394 |
27552 | | { PseudoVSOXSEG5EI16_V_M1_M1, VSOXSEG5EI16_V }, // 8395 |
27553 | | { PseudoVSOXSEG5EI16_V_M1_M1_MASK, VSOXSEG5EI16_V }, // 8396 |
27554 | | { PseudoVSOXSEG5EI16_V_M1_MF2, VSOXSEG5EI16_V }, // 8397 |
27555 | | { PseudoVSOXSEG5EI16_V_M1_MF2_MASK, VSOXSEG5EI16_V }, // 8398 |
27556 | | { PseudoVSOXSEG5EI16_V_M2_M1, VSOXSEG5EI16_V }, // 8399 |
27557 | | { PseudoVSOXSEG5EI16_V_M2_M1_MASK, VSOXSEG5EI16_V }, // 8400 |
27558 | | { PseudoVSOXSEG5EI16_V_MF2_M1, VSOXSEG5EI16_V }, // 8401 |
27559 | | { PseudoVSOXSEG5EI16_V_MF2_M1_MASK, VSOXSEG5EI16_V }, // 8402 |
27560 | | { PseudoVSOXSEG5EI16_V_MF2_MF2, VSOXSEG5EI16_V }, // 8403 |
27561 | | { PseudoVSOXSEG5EI16_V_MF2_MF2_MASK, VSOXSEG5EI16_V }, // 8404 |
27562 | | { PseudoVSOXSEG5EI16_V_MF2_MF4, VSOXSEG5EI16_V }, // 8405 |
27563 | | { PseudoVSOXSEG5EI16_V_MF2_MF4_MASK, VSOXSEG5EI16_V }, // 8406 |
27564 | | { PseudoVSOXSEG5EI16_V_MF4_M1, VSOXSEG5EI16_V }, // 8407 |
27565 | | { PseudoVSOXSEG5EI16_V_MF4_M1_MASK, VSOXSEG5EI16_V }, // 8408 |
27566 | | { PseudoVSOXSEG5EI16_V_MF4_MF2, VSOXSEG5EI16_V }, // 8409 |
27567 | | { PseudoVSOXSEG5EI16_V_MF4_MF2_MASK, VSOXSEG5EI16_V }, // 8410 |
27568 | | { PseudoVSOXSEG5EI16_V_MF4_MF4, VSOXSEG5EI16_V }, // 8411 |
27569 | | { PseudoVSOXSEG5EI16_V_MF4_MF4_MASK, VSOXSEG5EI16_V }, // 8412 |
27570 | | { PseudoVSOXSEG5EI16_V_MF4_MF8, VSOXSEG5EI16_V }, // 8413 |
27571 | | { PseudoVSOXSEG5EI16_V_MF4_MF8_MASK, VSOXSEG5EI16_V }, // 8414 |
27572 | | { PseudoVSOXSEG5EI32_V_M1_M1, VSOXSEG5EI32_V }, // 8415 |
27573 | | { PseudoVSOXSEG5EI32_V_M1_M1_MASK, VSOXSEG5EI32_V }, // 8416 |
27574 | | { PseudoVSOXSEG5EI32_V_M1_MF2, VSOXSEG5EI32_V }, // 8417 |
27575 | | { PseudoVSOXSEG5EI32_V_M1_MF2_MASK, VSOXSEG5EI32_V }, // 8418 |
27576 | | { PseudoVSOXSEG5EI32_V_M1_MF4, VSOXSEG5EI32_V }, // 8419 |
27577 | | { PseudoVSOXSEG5EI32_V_M1_MF4_MASK, VSOXSEG5EI32_V }, // 8420 |
27578 | | { PseudoVSOXSEG5EI32_V_M2_M1, VSOXSEG5EI32_V }, // 8421 |
27579 | | { PseudoVSOXSEG5EI32_V_M2_M1_MASK, VSOXSEG5EI32_V }, // 8422 |
27580 | | { PseudoVSOXSEG5EI32_V_M2_MF2, VSOXSEG5EI32_V }, // 8423 |
27581 | | { PseudoVSOXSEG5EI32_V_M2_MF2_MASK, VSOXSEG5EI32_V }, // 8424 |
27582 | | { PseudoVSOXSEG5EI32_V_M4_M1, VSOXSEG5EI32_V }, // 8425 |
27583 | | { PseudoVSOXSEG5EI32_V_M4_M1_MASK, VSOXSEG5EI32_V }, // 8426 |
27584 | | { PseudoVSOXSEG5EI32_V_MF2_M1, VSOXSEG5EI32_V }, // 8427 |
27585 | | { PseudoVSOXSEG5EI32_V_MF2_M1_MASK, VSOXSEG5EI32_V }, // 8428 |
27586 | | { PseudoVSOXSEG5EI32_V_MF2_MF2, VSOXSEG5EI32_V }, // 8429 |
27587 | | { PseudoVSOXSEG5EI32_V_MF2_MF2_MASK, VSOXSEG5EI32_V }, // 8430 |
27588 | | { PseudoVSOXSEG5EI32_V_MF2_MF4, VSOXSEG5EI32_V }, // 8431 |
27589 | | { PseudoVSOXSEG5EI32_V_MF2_MF4_MASK, VSOXSEG5EI32_V }, // 8432 |
27590 | | { PseudoVSOXSEG5EI32_V_MF2_MF8, VSOXSEG5EI32_V }, // 8433 |
27591 | | { PseudoVSOXSEG5EI32_V_MF2_MF8_MASK, VSOXSEG5EI32_V }, // 8434 |
27592 | | { PseudoVSOXSEG5EI64_V_M1_M1, VSOXSEG5EI64_V }, // 8435 |
27593 | | { PseudoVSOXSEG5EI64_V_M1_M1_MASK, VSOXSEG5EI64_V }, // 8436 |
27594 | | { PseudoVSOXSEG5EI64_V_M1_MF2, VSOXSEG5EI64_V }, // 8437 |
27595 | | { PseudoVSOXSEG5EI64_V_M1_MF2_MASK, VSOXSEG5EI64_V }, // 8438 |
27596 | | { PseudoVSOXSEG5EI64_V_M1_MF4, VSOXSEG5EI64_V }, // 8439 |
27597 | | { PseudoVSOXSEG5EI64_V_M1_MF4_MASK, VSOXSEG5EI64_V }, // 8440 |
27598 | | { PseudoVSOXSEG5EI64_V_M1_MF8, VSOXSEG5EI64_V }, // 8441 |
27599 | | { PseudoVSOXSEG5EI64_V_M1_MF8_MASK, VSOXSEG5EI64_V }, // 8442 |
27600 | | { PseudoVSOXSEG5EI64_V_M2_M1, VSOXSEG5EI64_V }, // 8443 |
27601 | | { PseudoVSOXSEG5EI64_V_M2_M1_MASK, VSOXSEG5EI64_V }, // 8444 |
27602 | | { PseudoVSOXSEG5EI64_V_M2_MF2, VSOXSEG5EI64_V }, // 8445 |
27603 | | { PseudoVSOXSEG5EI64_V_M2_MF2_MASK, VSOXSEG5EI64_V }, // 8446 |
27604 | | { PseudoVSOXSEG5EI64_V_M2_MF4, VSOXSEG5EI64_V }, // 8447 |
27605 | | { PseudoVSOXSEG5EI64_V_M2_MF4_MASK, VSOXSEG5EI64_V }, // 8448 |
27606 | | { PseudoVSOXSEG5EI64_V_M4_M1, VSOXSEG5EI64_V }, // 8449 |
27607 | | { PseudoVSOXSEG5EI64_V_M4_M1_MASK, VSOXSEG5EI64_V }, // 8450 |
27608 | | { PseudoVSOXSEG5EI64_V_M4_MF2, VSOXSEG5EI64_V }, // 8451 |
27609 | | { PseudoVSOXSEG5EI64_V_M4_MF2_MASK, VSOXSEG5EI64_V }, // 8452 |
27610 | | { PseudoVSOXSEG5EI64_V_M8_M1, VSOXSEG5EI64_V }, // 8453 |
27611 | | { PseudoVSOXSEG5EI64_V_M8_M1_MASK, VSOXSEG5EI64_V }, // 8454 |
27612 | | { PseudoVSOXSEG5EI8_V_M1_M1, VSOXSEG5EI8_V }, // 8455 |
27613 | | { PseudoVSOXSEG5EI8_V_M1_M1_MASK, VSOXSEG5EI8_V }, // 8456 |
27614 | | { PseudoVSOXSEG5EI8_V_MF2_M1, VSOXSEG5EI8_V }, // 8457 |
27615 | | { PseudoVSOXSEG5EI8_V_MF2_M1_MASK, VSOXSEG5EI8_V }, // 8458 |
27616 | | { PseudoVSOXSEG5EI8_V_MF2_MF2, VSOXSEG5EI8_V }, // 8459 |
27617 | | { PseudoVSOXSEG5EI8_V_MF2_MF2_MASK, VSOXSEG5EI8_V }, // 8460 |
27618 | | { PseudoVSOXSEG5EI8_V_MF4_M1, VSOXSEG5EI8_V }, // 8461 |
27619 | | { PseudoVSOXSEG5EI8_V_MF4_M1_MASK, VSOXSEG5EI8_V }, // 8462 |
27620 | | { PseudoVSOXSEG5EI8_V_MF4_MF2, VSOXSEG5EI8_V }, // 8463 |
27621 | | { PseudoVSOXSEG5EI8_V_MF4_MF2_MASK, VSOXSEG5EI8_V }, // 8464 |
27622 | | { PseudoVSOXSEG5EI8_V_MF4_MF4, VSOXSEG5EI8_V }, // 8465 |
27623 | | { PseudoVSOXSEG5EI8_V_MF4_MF4_MASK, VSOXSEG5EI8_V }, // 8466 |
27624 | | { PseudoVSOXSEG5EI8_V_MF8_M1, VSOXSEG5EI8_V }, // 8467 |
27625 | | { PseudoVSOXSEG5EI8_V_MF8_M1_MASK, VSOXSEG5EI8_V }, // 8468 |
27626 | | { PseudoVSOXSEG5EI8_V_MF8_MF2, VSOXSEG5EI8_V }, // 8469 |
27627 | | { PseudoVSOXSEG5EI8_V_MF8_MF2_MASK, VSOXSEG5EI8_V }, // 8470 |
27628 | | { PseudoVSOXSEG5EI8_V_MF8_MF4, VSOXSEG5EI8_V }, // 8471 |
27629 | | { PseudoVSOXSEG5EI8_V_MF8_MF4_MASK, VSOXSEG5EI8_V }, // 8472 |
27630 | | { PseudoVSOXSEG5EI8_V_MF8_MF8, VSOXSEG5EI8_V }, // 8473 |
27631 | | { PseudoVSOXSEG5EI8_V_MF8_MF8_MASK, VSOXSEG5EI8_V }, // 8474 |
27632 | | { PseudoVSOXSEG6EI16_V_M1_M1, VSOXSEG6EI16_V }, // 8475 |
27633 | | { PseudoVSOXSEG6EI16_V_M1_M1_MASK, VSOXSEG6EI16_V }, // 8476 |
27634 | | { PseudoVSOXSEG6EI16_V_M1_MF2, VSOXSEG6EI16_V }, // 8477 |
27635 | | { PseudoVSOXSEG6EI16_V_M1_MF2_MASK, VSOXSEG6EI16_V }, // 8478 |
27636 | | { PseudoVSOXSEG6EI16_V_M2_M1, VSOXSEG6EI16_V }, // 8479 |
27637 | | { PseudoVSOXSEG6EI16_V_M2_M1_MASK, VSOXSEG6EI16_V }, // 8480 |
27638 | | { PseudoVSOXSEG6EI16_V_MF2_M1, VSOXSEG6EI16_V }, // 8481 |
27639 | | { PseudoVSOXSEG6EI16_V_MF2_M1_MASK, VSOXSEG6EI16_V }, // 8482 |
27640 | | { PseudoVSOXSEG6EI16_V_MF2_MF2, VSOXSEG6EI16_V }, // 8483 |
27641 | | { PseudoVSOXSEG6EI16_V_MF2_MF2_MASK, VSOXSEG6EI16_V }, // 8484 |
27642 | | { PseudoVSOXSEG6EI16_V_MF2_MF4, VSOXSEG6EI16_V }, // 8485 |
27643 | | { PseudoVSOXSEG6EI16_V_MF2_MF4_MASK, VSOXSEG6EI16_V }, // 8486 |
27644 | | { PseudoVSOXSEG6EI16_V_MF4_M1, VSOXSEG6EI16_V }, // 8487 |
27645 | | { PseudoVSOXSEG6EI16_V_MF4_M1_MASK, VSOXSEG6EI16_V }, // 8488 |
27646 | | { PseudoVSOXSEG6EI16_V_MF4_MF2, VSOXSEG6EI16_V }, // 8489 |
27647 | | { PseudoVSOXSEG6EI16_V_MF4_MF2_MASK, VSOXSEG6EI16_V }, // 8490 |
27648 | | { PseudoVSOXSEG6EI16_V_MF4_MF4, VSOXSEG6EI16_V }, // 8491 |
27649 | | { PseudoVSOXSEG6EI16_V_MF4_MF4_MASK, VSOXSEG6EI16_V }, // 8492 |
27650 | | { PseudoVSOXSEG6EI16_V_MF4_MF8, VSOXSEG6EI16_V }, // 8493 |
27651 | | { PseudoVSOXSEG6EI16_V_MF4_MF8_MASK, VSOXSEG6EI16_V }, // 8494 |
27652 | | { PseudoVSOXSEG6EI32_V_M1_M1, VSOXSEG6EI32_V }, // 8495 |
27653 | | { PseudoVSOXSEG6EI32_V_M1_M1_MASK, VSOXSEG6EI32_V }, // 8496 |
27654 | | { PseudoVSOXSEG6EI32_V_M1_MF2, VSOXSEG6EI32_V }, // 8497 |
27655 | | { PseudoVSOXSEG6EI32_V_M1_MF2_MASK, VSOXSEG6EI32_V }, // 8498 |
27656 | | { PseudoVSOXSEG6EI32_V_M1_MF4, VSOXSEG6EI32_V }, // 8499 |
27657 | | { PseudoVSOXSEG6EI32_V_M1_MF4_MASK, VSOXSEG6EI32_V }, // 8500 |
27658 | | { PseudoVSOXSEG6EI32_V_M2_M1, VSOXSEG6EI32_V }, // 8501 |
27659 | | { PseudoVSOXSEG6EI32_V_M2_M1_MASK, VSOXSEG6EI32_V }, // 8502 |
27660 | | { PseudoVSOXSEG6EI32_V_M2_MF2, VSOXSEG6EI32_V }, // 8503 |
27661 | | { PseudoVSOXSEG6EI32_V_M2_MF2_MASK, VSOXSEG6EI32_V }, // 8504 |
27662 | | { PseudoVSOXSEG6EI32_V_M4_M1, VSOXSEG6EI32_V }, // 8505 |
27663 | | { PseudoVSOXSEG6EI32_V_M4_M1_MASK, VSOXSEG6EI32_V }, // 8506 |
27664 | | { PseudoVSOXSEG6EI32_V_MF2_M1, VSOXSEG6EI32_V }, // 8507 |
27665 | | { PseudoVSOXSEG6EI32_V_MF2_M1_MASK, VSOXSEG6EI32_V }, // 8508 |
27666 | | { PseudoVSOXSEG6EI32_V_MF2_MF2, VSOXSEG6EI32_V }, // 8509 |
27667 | | { PseudoVSOXSEG6EI32_V_MF2_MF2_MASK, VSOXSEG6EI32_V }, // 8510 |
27668 | | { PseudoVSOXSEG6EI32_V_MF2_MF4, VSOXSEG6EI32_V }, // 8511 |
27669 | | { PseudoVSOXSEG6EI32_V_MF2_MF4_MASK, VSOXSEG6EI32_V }, // 8512 |
27670 | | { PseudoVSOXSEG6EI32_V_MF2_MF8, VSOXSEG6EI32_V }, // 8513 |
27671 | | { PseudoVSOXSEG6EI32_V_MF2_MF8_MASK, VSOXSEG6EI32_V }, // 8514 |
27672 | | { PseudoVSOXSEG6EI64_V_M1_M1, VSOXSEG6EI64_V }, // 8515 |
27673 | | { PseudoVSOXSEG6EI64_V_M1_M1_MASK, VSOXSEG6EI64_V }, // 8516 |
27674 | | { PseudoVSOXSEG6EI64_V_M1_MF2, VSOXSEG6EI64_V }, // 8517 |
27675 | | { PseudoVSOXSEG6EI64_V_M1_MF2_MASK, VSOXSEG6EI64_V }, // 8518 |
27676 | | { PseudoVSOXSEG6EI64_V_M1_MF4, VSOXSEG6EI64_V }, // 8519 |
27677 | | { PseudoVSOXSEG6EI64_V_M1_MF4_MASK, VSOXSEG6EI64_V }, // 8520 |
27678 | | { PseudoVSOXSEG6EI64_V_M1_MF8, VSOXSEG6EI64_V }, // 8521 |
27679 | | { PseudoVSOXSEG6EI64_V_M1_MF8_MASK, VSOXSEG6EI64_V }, // 8522 |
27680 | | { PseudoVSOXSEG6EI64_V_M2_M1, VSOXSEG6EI64_V }, // 8523 |
27681 | | { PseudoVSOXSEG6EI64_V_M2_M1_MASK, VSOXSEG6EI64_V }, // 8524 |
27682 | | { PseudoVSOXSEG6EI64_V_M2_MF2, VSOXSEG6EI64_V }, // 8525 |
27683 | | { PseudoVSOXSEG6EI64_V_M2_MF2_MASK, VSOXSEG6EI64_V }, // 8526 |
27684 | | { PseudoVSOXSEG6EI64_V_M2_MF4, VSOXSEG6EI64_V }, // 8527 |
27685 | | { PseudoVSOXSEG6EI64_V_M2_MF4_MASK, VSOXSEG6EI64_V }, // 8528 |
27686 | | { PseudoVSOXSEG6EI64_V_M4_M1, VSOXSEG6EI64_V }, // 8529 |
27687 | | { PseudoVSOXSEG6EI64_V_M4_M1_MASK, VSOXSEG6EI64_V }, // 8530 |
27688 | | { PseudoVSOXSEG6EI64_V_M4_MF2, VSOXSEG6EI64_V }, // 8531 |
27689 | | { PseudoVSOXSEG6EI64_V_M4_MF2_MASK, VSOXSEG6EI64_V }, // 8532 |
27690 | | { PseudoVSOXSEG6EI64_V_M8_M1, VSOXSEG6EI64_V }, // 8533 |
27691 | | { PseudoVSOXSEG6EI64_V_M8_M1_MASK, VSOXSEG6EI64_V }, // 8534 |
27692 | | { PseudoVSOXSEG6EI8_V_M1_M1, VSOXSEG6EI8_V }, // 8535 |
27693 | | { PseudoVSOXSEG6EI8_V_M1_M1_MASK, VSOXSEG6EI8_V }, // 8536 |
27694 | | { PseudoVSOXSEG6EI8_V_MF2_M1, VSOXSEG6EI8_V }, // 8537 |
27695 | | { PseudoVSOXSEG6EI8_V_MF2_M1_MASK, VSOXSEG6EI8_V }, // 8538 |
27696 | | { PseudoVSOXSEG6EI8_V_MF2_MF2, VSOXSEG6EI8_V }, // 8539 |
27697 | | { PseudoVSOXSEG6EI8_V_MF2_MF2_MASK, VSOXSEG6EI8_V }, // 8540 |
27698 | | { PseudoVSOXSEG6EI8_V_MF4_M1, VSOXSEG6EI8_V }, // 8541 |
27699 | | { PseudoVSOXSEG6EI8_V_MF4_M1_MASK, VSOXSEG6EI8_V }, // 8542 |
27700 | | { PseudoVSOXSEG6EI8_V_MF4_MF2, VSOXSEG6EI8_V }, // 8543 |
27701 | | { PseudoVSOXSEG6EI8_V_MF4_MF2_MASK, VSOXSEG6EI8_V }, // 8544 |
27702 | | { PseudoVSOXSEG6EI8_V_MF4_MF4, VSOXSEG6EI8_V }, // 8545 |
27703 | | { PseudoVSOXSEG6EI8_V_MF4_MF4_MASK, VSOXSEG6EI8_V }, // 8546 |
27704 | | { PseudoVSOXSEG6EI8_V_MF8_M1, VSOXSEG6EI8_V }, // 8547 |
27705 | | { PseudoVSOXSEG6EI8_V_MF8_M1_MASK, VSOXSEG6EI8_V }, // 8548 |
27706 | | { PseudoVSOXSEG6EI8_V_MF8_MF2, VSOXSEG6EI8_V }, // 8549 |
27707 | | { PseudoVSOXSEG6EI8_V_MF8_MF2_MASK, VSOXSEG6EI8_V }, // 8550 |
27708 | | { PseudoVSOXSEG6EI8_V_MF8_MF4, VSOXSEG6EI8_V }, // 8551 |
27709 | | { PseudoVSOXSEG6EI8_V_MF8_MF4_MASK, VSOXSEG6EI8_V }, // 8552 |
27710 | | { PseudoVSOXSEG6EI8_V_MF8_MF8, VSOXSEG6EI8_V }, // 8553 |
27711 | | { PseudoVSOXSEG6EI8_V_MF8_MF8_MASK, VSOXSEG6EI8_V }, // 8554 |
27712 | | { PseudoVSOXSEG7EI16_V_M1_M1, VSOXSEG7EI16_V }, // 8555 |
27713 | | { PseudoVSOXSEG7EI16_V_M1_M1_MASK, VSOXSEG7EI16_V }, // 8556 |
27714 | | { PseudoVSOXSEG7EI16_V_M1_MF2, VSOXSEG7EI16_V }, // 8557 |
27715 | | { PseudoVSOXSEG7EI16_V_M1_MF2_MASK, VSOXSEG7EI16_V }, // 8558 |
27716 | | { PseudoVSOXSEG7EI16_V_M2_M1, VSOXSEG7EI16_V }, // 8559 |
27717 | | { PseudoVSOXSEG7EI16_V_M2_M1_MASK, VSOXSEG7EI16_V }, // 8560 |
27718 | | { PseudoVSOXSEG7EI16_V_MF2_M1, VSOXSEG7EI16_V }, // 8561 |
27719 | | { PseudoVSOXSEG7EI16_V_MF2_M1_MASK, VSOXSEG7EI16_V }, // 8562 |
27720 | | { PseudoVSOXSEG7EI16_V_MF2_MF2, VSOXSEG7EI16_V }, // 8563 |
27721 | | { PseudoVSOXSEG7EI16_V_MF2_MF2_MASK, VSOXSEG7EI16_V }, // 8564 |
27722 | | { PseudoVSOXSEG7EI16_V_MF2_MF4, VSOXSEG7EI16_V }, // 8565 |
27723 | | { PseudoVSOXSEG7EI16_V_MF2_MF4_MASK, VSOXSEG7EI16_V }, // 8566 |
27724 | | { PseudoVSOXSEG7EI16_V_MF4_M1, VSOXSEG7EI16_V }, // 8567 |
27725 | | { PseudoVSOXSEG7EI16_V_MF4_M1_MASK, VSOXSEG7EI16_V }, // 8568 |
27726 | | { PseudoVSOXSEG7EI16_V_MF4_MF2, VSOXSEG7EI16_V }, // 8569 |
27727 | | { PseudoVSOXSEG7EI16_V_MF4_MF2_MASK, VSOXSEG7EI16_V }, // 8570 |
27728 | | { PseudoVSOXSEG7EI16_V_MF4_MF4, VSOXSEG7EI16_V }, // 8571 |
27729 | | { PseudoVSOXSEG7EI16_V_MF4_MF4_MASK, VSOXSEG7EI16_V }, // 8572 |
27730 | | { PseudoVSOXSEG7EI16_V_MF4_MF8, VSOXSEG7EI16_V }, // 8573 |
27731 | | { PseudoVSOXSEG7EI16_V_MF4_MF8_MASK, VSOXSEG7EI16_V }, // 8574 |
27732 | | { PseudoVSOXSEG7EI32_V_M1_M1, VSOXSEG7EI32_V }, // 8575 |
27733 | | { PseudoVSOXSEG7EI32_V_M1_M1_MASK, VSOXSEG7EI32_V }, // 8576 |
27734 | | { PseudoVSOXSEG7EI32_V_M1_MF2, VSOXSEG7EI32_V }, // 8577 |
27735 | | { PseudoVSOXSEG7EI32_V_M1_MF2_MASK, VSOXSEG7EI32_V }, // 8578 |
27736 | | { PseudoVSOXSEG7EI32_V_M1_MF4, VSOXSEG7EI32_V }, // 8579 |
27737 | | { PseudoVSOXSEG7EI32_V_M1_MF4_MASK, VSOXSEG7EI32_V }, // 8580 |
27738 | | { PseudoVSOXSEG7EI32_V_M2_M1, VSOXSEG7EI32_V }, // 8581 |
27739 | | { PseudoVSOXSEG7EI32_V_M2_M1_MASK, VSOXSEG7EI32_V }, // 8582 |
27740 | | { PseudoVSOXSEG7EI32_V_M2_MF2, VSOXSEG7EI32_V }, // 8583 |
27741 | | { PseudoVSOXSEG7EI32_V_M2_MF2_MASK, VSOXSEG7EI32_V }, // 8584 |
27742 | | { PseudoVSOXSEG7EI32_V_M4_M1, VSOXSEG7EI32_V }, // 8585 |
27743 | | { PseudoVSOXSEG7EI32_V_M4_M1_MASK, VSOXSEG7EI32_V }, // 8586 |
27744 | | { PseudoVSOXSEG7EI32_V_MF2_M1, VSOXSEG7EI32_V }, // 8587 |
27745 | | { PseudoVSOXSEG7EI32_V_MF2_M1_MASK, VSOXSEG7EI32_V }, // 8588 |
27746 | | { PseudoVSOXSEG7EI32_V_MF2_MF2, VSOXSEG7EI32_V }, // 8589 |
27747 | | { PseudoVSOXSEG7EI32_V_MF2_MF2_MASK, VSOXSEG7EI32_V }, // 8590 |
27748 | | { PseudoVSOXSEG7EI32_V_MF2_MF4, VSOXSEG7EI32_V }, // 8591 |
27749 | | { PseudoVSOXSEG7EI32_V_MF2_MF4_MASK, VSOXSEG7EI32_V }, // 8592 |
27750 | | { PseudoVSOXSEG7EI32_V_MF2_MF8, VSOXSEG7EI32_V }, // 8593 |
27751 | | { PseudoVSOXSEG7EI32_V_MF2_MF8_MASK, VSOXSEG7EI32_V }, // 8594 |
27752 | | { PseudoVSOXSEG7EI64_V_M1_M1, VSOXSEG7EI64_V }, // 8595 |
27753 | | { PseudoVSOXSEG7EI64_V_M1_M1_MASK, VSOXSEG7EI64_V }, // 8596 |
27754 | | { PseudoVSOXSEG7EI64_V_M1_MF2, VSOXSEG7EI64_V }, // 8597 |
27755 | | { PseudoVSOXSEG7EI64_V_M1_MF2_MASK, VSOXSEG7EI64_V }, // 8598 |
27756 | | { PseudoVSOXSEG7EI64_V_M1_MF4, VSOXSEG7EI64_V }, // 8599 |
27757 | | { PseudoVSOXSEG7EI64_V_M1_MF4_MASK, VSOXSEG7EI64_V }, // 8600 |
27758 | | { PseudoVSOXSEG7EI64_V_M1_MF8, VSOXSEG7EI64_V }, // 8601 |
27759 | | { PseudoVSOXSEG7EI64_V_M1_MF8_MASK, VSOXSEG7EI64_V }, // 8602 |
27760 | | { PseudoVSOXSEG7EI64_V_M2_M1, VSOXSEG7EI64_V }, // 8603 |
27761 | | { PseudoVSOXSEG7EI64_V_M2_M1_MASK, VSOXSEG7EI64_V }, // 8604 |
27762 | | { PseudoVSOXSEG7EI64_V_M2_MF2, VSOXSEG7EI64_V }, // 8605 |
27763 | | { PseudoVSOXSEG7EI64_V_M2_MF2_MASK, VSOXSEG7EI64_V }, // 8606 |
27764 | | { PseudoVSOXSEG7EI64_V_M2_MF4, VSOXSEG7EI64_V }, // 8607 |
27765 | | { PseudoVSOXSEG7EI64_V_M2_MF4_MASK, VSOXSEG7EI64_V }, // 8608 |
27766 | | { PseudoVSOXSEG7EI64_V_M4_M1, VSOXSEG7EI64_V }, // 8609 |
27767 | | { PseudoVSOXSEG7EI64_V_M4_M1_MASK, VSOXSEG7EI64_V }, // 8610 |
27768 | | { PseudoVSOXSEG7EI64_V_M4_MF2, VSOXSEG7EI64_V }, // 8611 |
27769 | | { PseudoVSOXSEG7EI64_V_M4_MF2_MASK, VSOXSEG7EI64_V }, // 8612 |
27770 | | { PseudoVSOXSEG7EI64_V_M8_M1, VSOXSEG7EI64_V }, // 8613 |
27771 | | { PseudoVSOXSEG7EI64_V_M8_M1_MASK, VSOXSEG7EI64_V }, // 8614 |
27772 | | { PseudoVSOXSEG7EI8_V_M1_M1, VSOXSEG7EI8_V }, // 8615 |
27773 | | { PseudoVSOXSEG7EI8_V_M1_M1_MASK, VSOXSEG7EI8_V }, // 8616 |
27774 | | { PseudoVSOXSEG7EI8_V_MF2_M1, VSOXSEG7EI8_V }, // 8617 |
27775 | | { PseudoVSOXSEG7EI8_V_MF2_M1_MASK, VSOXSEG7EI8_V }, // 8618 |
27776 | | { PseudoVSOXSEG7EI8_V_MF2_MF2, VSOXSEG7EI8_V }, // 8619 |
27777 | | { PseudoVSOXSEG7EI8_V_MF2_MF2_MASK, VSOXSEG7EI8_V }, // 8620 |
27778 | | { PseudoVSOXSEG7EI8_V_MF4_M1, VSOXSEG7EI8_V }, // 8621 |
27779 | | { PseudoVSOXSEG7EI8_V_MF4_M1_MASK, VSOXSEG7EI8_V }, // 8622 |
27780 | | { PseudoVSOXSEG7EI8_V_MF4_MF2, VSOXSEG7EI8_V }, // 8623 |
27781 | | { PseudoVSOXSEG7EI8_V_MF4_MF2_MASK, VSOXSEG7EI8_V }, // 8624 |
27782 | | { PseudoVSOXSEG7EI8_V_MF4_MF4, VSOXSEG7EI8_V }, // 8625 |
27783 | | { PseudoVSOXSEG7EI8_V_MF4_MF4_MASK, VSOXSEG7EI8_V }, // 8626 |
27784 | | { PseudoVSOXSEG7EI8_V_MF8_M1, VSOXSEG7EI8_V }, // 8627 |
27785 | | { PseudoVSOXSEG7EI8_V_MF8_M1_MASK, VSOXSEG7EI8_V }, // 8628 |
27786 | | { PseudoVSOXSEG7EI8_V_MF8_MF2, VSOXSEG7EI8_V }, // 8629 |
27787 | | { PseudoVSOXSEG7EI8_V_MF8_MF2_MASK, VSOXSEG7EI8_V }, // 8630 |
27788 | | { PseudoVSOXSEG7EI8_V_MF8_MF4, VSOXSEG7EI8_V }, // 8631 |
27789 | | { PseudoVSOXSEG7EI8_V_MF8_MF4_MASK, VSOXSEG7EI8_V }, // 8632 |
27790 | | { PseudoVSOXSEG7EI8_V_MF8_MF8, VSOXSEG7EI8_V }, // 8633 |
27791 | | { PseudoVSOXSEG7EI8_V_MF8_MF8_MASK, VSOXSEG7EI8_V }, // 8634 |
27792 | | { PseudoVSOXSEG8EI16_V_M1_M1, VSOXSEG8EI16_V }, // 8635 |
27793 | | { PseudoVSOXSEG8EI16_V_M1_M1_MASK, VSOXSEG8EI16_V }, // 8636 |
27794 | | { PseudoVSOXSEG8EI16_V_M1_MF2, VSOXSEG8EI16_V }, // 8637 |
27795 | | { PseudoVSOXSEG8EI16_V_M1_MF2_MASK, VSOXSEG8EI16_V }, // 8638 |
27796 | | { PseudoVSOXSEG8EI16_V_M2_M1, VSOXSEG8EI16_V }, // 8639 |
27797 | | { PseudoVSOXSEG8EI16_V_M2_M1_MASK, VSOXSEG8EI16_V }, // 8640 |
27798 | | { PseudoVSOXSEG8EI16_V_MF2_M1, VSOXSEG8EI16_V }, // 8641 |
27799 | | { PseudoVSOXSEG8EI16_V_MF2_M1_MASK, VSOXSEG8EI16_V }, // 8642 |
27800 | | { PseudoVSOXSEG8EI16_V_MF2_MF2, VSOXSEG8EI16_V }, // 8643 |
27801 | | { PseudoVSOXSEG8EI16_V_MF2_MF2_MASK, VSOXSEG8EI16_V }, // 8644 |
27802 | | { PseudoVSOXSEG8EI16_V_MF2_MF4, VSOXSEG8EI16_V }, // 8645 |
27803 | | { PseudoVSOXSEG8EI16_V_MF2_MF4_MASK, VSOXSEG8EI16_V }, // 8646 |
27804 | | { PseudoVSOXSEG8EI16_V_MF4_M1, VSOXSEG8EI16_V }, // 8647 |
27805 | | { PseudoVSOXSEG8EI16_V_MF4_M1_MASK, VSOXSEG8EI16_V }, // 8648 |
27806 | | { PseudoVSOXSEG8EI16_V_MF4_MF2, VSOXSEG8EI16_V }, // 8649 |
27807 | | { PseudoVSOXSEG8EI16_V_MF4_MF2_MASK, VSOXSEG8EI16_V }, // 8650 |
27808 | | { PseudoVSOXSEG8EI16_V_MF4_MF4, VSOXSEG8EI16_V }, // 8651 |
27809 | | { PseudoVSOXSEG8EI16_V_MF4_MF4_MASK, VSOXSEG8EI16_V }, // 8652 |
27810 | | { PseudoVSOXSEG8EI16_V_MF4_MF8, VSOXSEG8EI16_V }, // 8653 |
27811 | | { PseudoVSOXSEG8EI16_V_MF4_MF8_MASK, VSOXSEG8EI16_V }, // 8654 |
27812 | | { PseudoVSOXSEG8EI32_V_M1_M1, VSOXSEG8EI32_V }, // 8655 |
27813 | | { PseudoVSOXSEG8EI32_V_M1_M1_MASK, VSOXSEG8EI32_V }, // 8656 |
27814 | | { PseudoVSOXSEG8EI32_V_M1_MF2, VSOXSEG8EI32_V }, // 8657 |
27815 | | { PseudoVSOXSEG8EI32_V_M1_MF2_MASK, VSOXSEG8EI32_V }, // 8658 |
27816 | | { PseudoVSOXSEG8EI32_V_M1_MF4, VSOXSEG8EI32_V }, // 8659 |
27817 | | { PseudoVSOXSEG8EI32_V_M1_MF4_MASK, VSOXSEG8EI32_V }, // 8660 |
27818 | | { PseudoVSOXSEG8EI32_V_M2_M1, VSOXSEG8EI32_V }, // 8661 |
27819 | | { PseudoVSOXSEG8EI32_V_M2_M1_MASK, VSOXSEG8EI32_V }, // 8662 |
27820 | | { PseudoVSOXSEG8EI32_V_M2_MF2, VSOXSEG8EI32_V }, // 8663 |
27821 | | { PseudoVSOXSEG8EI32_V_M2_MF2_MASK, VSOXSEG8EI32_V }, // 8664 |
27822 | | { PseudoVSOXSEG8EI32_V_M4_M1, VSOXSEG8EI32_V }, // 8665 |
27823 | | { PseudoVSOXSEG8EI32_V_M4_M1_MASK, VSOXSEG8EI32_V }, // 8666 |
27824 | | { PseudoVSOXSEG8EI32_V_MF2_M1, VSOXSEG8EI32_V }, // 8667 |
27825 | | { PseudoVSOXSEG8EI32_V_MF2_M1_MASK, VSOXSEG8EI32_V }, // 8668 |
27826 | | { PseudoVSOXSEG8EI32_V_MF2_MF2, VSOXSEG8EI32_V }, // 8669 |
27827 | | { PseudoVSOXSEG8EI32_V_MF2_MF2_MASK, VSOXSEG8EI32_V }, // 8670 |
27828 | | { PseudoVSOXSEG8EI32_V_MF2_MF4, VSOXSEG8EI32_V }, // 8671 |
27829 | | { PseudoVSOXSEG8EI32_V_MF2_MF4_MASK, VSOXSEG8EI32_V }, // 8672 |
27830 | | { PseudoVSOXSEG8EI32_V_MF2_MF8, VSOXSEG8EI32_V }, // 8673 |
27831 | | { PseudoVSOXSEG8EI32_V_MF2_MF8_MASK, VSOXSEG8EI32_V }, // 8674 |
27832 | | { PseudoVSOXSEG8EI64_V_M1_M1, VSOXSEG8EI64_V }, // 8675 |
27833 | | { PseudoVSOXSEG8EI64_V_M1_M1_MASK, VSOXSEG8EI64_V }, // 8676 |
27834 | | { PseudoVSOXSEG8EI64_V_M1_MF2, VSOXSEG8EI64_V }, // 8677 |
27835 | | { PseudoVSOXSEG8EI64_V_M1_MF2_MASK, VSOXSEG8EI64_V }, // 8678 |
27836 | | { PseudoVSOXSEG8EI64_V_M1_MF4, VSOXSEG8EI64_V }, // 8679 |
27837 | | { PseudoVSOXSEG8EI64_V_M1_MF4_MASK, VSOXSEG8EI64_V }, // 8680 |
27838 | | { PseudoVSOXSEG8EI64_V_M1_MF8, VSOXSEG8EI64_V }, // 8681 |
27839 | | { PseudoVSOXSEG8EI64_V_M1_MF8_MASK, VSOXSEG8EI64_V }, // 8682 |
27840 | | { PseudoVSOXSEG8EI64_V_M2_M1, VSOXSEG8EI64_V }, // 8683 |
27841 | | { PseudoVSOXSEG8EI64_V_M2_M1_MASK, VSOXSEG8EI64_V }, // 8684 |
27842 | | { PseudoVSOXSEG8EI64_V_M2_MF2, VSOXSEG8EI64_V }, // 8685 |
27843 | | { PseudoVSOXSEG8EI64_V_M2_MF2_MASK, VSOXSEG8EI64_V }, // 8686 |
27844 | | { PseudoVSOXSEG8EI64_V_M2_MF4, VSOXSEG8EI64_V }, // 8687 |
27845 | | { PseudoVSOXSEG8EI64_V_M2_MF4_MASK, VSOXSEG8EI64_V }, // 8688 |
27846 | | { PseudoVSOXSEG8EI64_V_M4_M1, VSOXSEG8EI64_V }, // 8689 |
27847 | | { PseudoVSOXSEG8EI64_V_M4_M1_MASK, VSOXSEG8EI64_V }, // 8690 |
27848 | | { PseudoVSOXSEG8EI64_V_M4_MF2, VSOXSEG8EI64_V }, // 8691 |
27849 | | { PseudoVSOXSEG8EI64_V_M4_MF2_MASK, VSOXSEG8EI64_V }, // 8692 |
27850 | | { PseudoVSOXSEG8EI64_V_M8_M1, VSOXSEG8EI64_V }, // 8693 |
27851 | | { PseudoVSOXSEG8EI64_V_M8_M1_MASK, VSOXSEG8EI64_V }, // 8694 |
27852 | | { PseudoVSOXSEG8EI8_V_M1_M1, VSOXSEG8EI8_V }, // 8695 |
27853 | | { PseudoVSOXSEG8EI8_V_M1_M1_MASK, VSOXSEG8EI8_V }, // 8696 |
27854 | | { PseudoVSOXSEG8EI8_V_MF2_M1, VSOXSEG8EI8_V }, // 8697 |
27855 | | { PseudoVSOXSEG8EI8_V_MF2_M1_MASK, VSOXSEG8EI8_V }, // 8698 |
27856 | | { PseudoVSOXSEG8EI8_V_MF2_MF2, VSOXSEG8EI8_V }, // 8699 |
27857 | | { PseudoVSOXSEG8EI8_V_MF2_MF2_MASK, VSOXSEG8EI8_V }, // 8700 |
27858 | | { PseudoVSOXSEG8EI8_V_MF4_M1, VSOXSEG8EI8_V }, // 8701 |
27859 | | { PseudoVSOXSEG8EI8_V_MF4_M1_MASK, VSOXSEG8EI8_V }, // 8702 |
27860 | | { PseudoVSOXSEG8EI8_V_MF4_MF2, VSOXSEG8EI8_V }, // 8703 |
27861 | | { PseudoVSOXSEG8EI8_V_MF4_MF2_MASK, VSOXSEG8EI8_V }, // 8704 |
27862 | | { PseudoVSOXSEG8EI8_V_MF4_MF4, VSOXSEG8EI8_V }, // 8705 |
27863 | | { PseudoVSOXSEG8EI8_V_MF4_MF4_MASK, VSOXSEG8EI8_V }, // 8706 |
27864 | | { PseudoVSOXSEG8EI8_V_MF8_M1, VSOXSEG8EI8_V }, // 8707 |
27865 | | { PseudoVSOXSEG8EI8_V_MF8_M1_MASK, VSOXSEG8EI8_V }, // 8708 |
27866 | | { PseudoVSOXSEG8EI8_V_MF8_MF2, VSOXSEG8EI8_V }, // 8709 |
27867 | | { PseudoVSOXSEG8EI8_V_MF8_MF2_MASK, VSOXSEG8EI8_V }, // 8710 |
27868 | | { PseudoVSOXSEG8EI8_V_MF8_MF4, VSOXSEG8EI8_V }, // 8711 |
27869 | | { PseudoVSOXSEG8EI8_V_MF8_MF4_MASK, VSOXSEG8EI8_V }, // 8712 |
27870 | | { PseudoVSOXSEG8EI8_V_MF8_MF8, VSOXSEG8EI8_V }, // 8713 |
27871 | | { PseudoVSOXSEG8EI8_V_MF8_MF8_MASK, VSOXSEG8EI8_V }, // 8714 |
27872 | | { PseudoVSRA_VI_M1, VSRA_VI }, // 8715 |
27873 | | { PseudoVSRA_VI_M1_MASK, VSRA_VI }, // 8716 |
27874 | | { PseudoVSRA_VI_M2, VSRA_VI }, // 8717 |
27875 | | { PseudoVSRA_VI_M2_MASK, VSRA_VI }, // 8718 |
27876 | | { PseudoVSRA_VI_M4, VSRA_VI }, // 8719 |
27877 | | { PseudoVSRA_VI_M4_MASK, VSRA_VI }, // 8720 |
27878 | | { PseudoVSRA_VI_M8, VSRA_VI }, // 8721 |
27879 | | { PseudoVSRA_VI_M8_MASK, VSRA_VI }, // 8722 |
27880 | | { PseudoVSRA_VI_MF2, VSRA_VI }, // 8723 |
27881 | | { PseudoVSRA_VI_MF2_MASK, VSRA_VI }, // 8724 |
27882 | | { PseudoVSRA_VI_MF4, VSRA_VI }, // 8725 |
27883 | | { PseudoVSRA_VI_MF4_MASK, VSRA_VI }, // 8726 |
27884 | | { PseudoVSRA_VI_MF8, VSRA_VI }, // 8727 |
27885 | | { PseudoVSRA_VI_MF8_MASK, VSRA_VI }, // 8728 |
27886 | | { PseudoVSRA_VV_M1, VSRA_VV }, // 8729 |
27887 | | { PseudoVSRA_VV_M1_MASK, VSRA_VV }, // 8730 |
27888 | | { PseudoVSRA_VV_M2, VSRA_VV }, // 8731 |
27889 | | { PseudoVSRA_VV_M2_MASK, VSRA_VV }, // 8732 |
27890 | | { PseudoVSRA_VV_M4, VSRA_VV }, // 8733 |
27891 | | { PseudoVSRA_VV_M4_MASK, VSRA_VV }, // 8734 |
27892 | | { PseudoVSRA_VV_M8, VSRA_VV }, // 8735 |
27893 | | { PseudoVSRA_VV_M8_MASK, VSRA_VV }, // 8736 |
27894 | | { PseudoVSRA_VV_MF2, VSRA_VV }, // 8737 |
27895 | | { PseudoVSRA_VV_MF2_MASK, VSRA_VV }, // 8738 |
27896 | | { PseudoVSRA_VV_MF4, VSRA_VV }, // 8739 |
27897 | | { PseudoVSRA_VV_MF4_MASK, VSRA_VV }, // 8740 |
27898 | | { PseudoVSRA_VV_MF8, VSRA_VV }, // 8741 |
27899 | | { PseudoVSRA_VV_MF8_MASK, VSRA_VV }, // 8742 |
27900 | | { PseudoVSRA_VX_M1, VSRA_VX }, // 8743 |
27901 | | { PseudoVSRA_VX_M1_MASK, VSRA_VX }, // 8744 |
27902 | | { PseudoVSRA_VX_M2, VSRA_VX }, // 8745 |
27903 | | { PseudoVSRA_VX_M2_MASK, VSRA_VX }, // 8746 |
27904 | | { PseudoVSRA_VX_M4, VSRA_VX }, // 8747 |
27905 | | { PseudoVSRA_VX_M4_MASK, VSRA_VX }, // 8748 |
27906 | | { PseudoVSRA_VX_M8, VSRA_VX }, // 8749 |
27907 | | { PseudoVSRA_VX_M8_MASK, VSRA_VX }, // 8750 |
27908 | | { PseudoVSRA_VX_MF2, VSRA_VX }, // 8751 |
27909 | | { PseudoVSRA_VX_MF2_MASK, VSRA_VX }, // 8752 |
27910 | | { PseudoVSRA_VX_MF4, VSRA_VX }, // 8753 |
27911 | | { PseudoVSRA_VX_MF4_MASK, VSRA_VX }, // 8754 |
27912 | | { PseudoVSRA_VX_MF8, VSRA_VX }, // 8755 |
27913 | | { PseudoVSRA_VX_MF8_MASK, VSRA_VX }, // 8756 |
27914 | | { PseudoVSRL_VI_M1, VSRL_VI }, // 8757 |
27915 | | { PseudoVSRL_VI_M1_MASK, VSRL_VI }, // 8758 |
27916 | | { PseudoVSRL_VI_M2, VSRL_VI }, // 8759 |
27917 | | { PseudoVSRL_VI_M2_MASK, VSRL_VI }, // 8760 |
27918 | | { PseudoVSRL_VI_M4, VSRL_VI }, // 8761 |
27919 | | { PseudoVSRL_VI_M4_MASK, VSRL_VI }, // 8762 |
27920 | | { PseudoVSRL_VI_M8, VSRL_VI }, // 8763 |
27921 | | { PseudoVSRL_VI_M8_MASK, VSRL_VI }, // 8764 |
27922 | | { PseudoVSRL_VI_MF2, VSRL_VI }, // 8765 |
27923 | | { PseudoVSRL_VI_MF2_MASK, VSRL_VI }, // 8766 |
27924 | | { PseudoVSRL_VI_MF4, VSRL_VI }, // 8767 |
27925 | | { PseudoVSRL_VI_MF4_MASK, VSRL_VI }, // 8768 |
27926 | | { PseudoVSRL_VI_MF8, VSRL_VI }, // 8769 |
27927 | | { PseudoVSRL_VI_MF8_MASK, VSRL_VI }, // 8770 |
27928 | | { PseudoVSRL_VV_M1, VSRL_VV }, // 8771 |
27929 | | { PseudoVSRL_VV_M1_MASK, VSRL_VV }, // 8772 |
27930 | | { PseudoVSRL_VV_M2, VSRL_VV }, // 8773 |
27931 | | { PseudoVSRL_VV_M2_MASK, VSRL_VV }, // 8774 |
27932 | | { PseudoVSRL_VV_M4, VSRL_VV }, // 8775 |
27933 | | { PseudoVSRL_VV_M4_MASK, VSRL_VV }, // 8776 |
27934 | | { PseudoVSRL_VV_M8, VSRL_VV }, // 8777 |
27935 | | { PseudoVSRL_VV_M8_MASK, VSRL_VV }, // 8778 |
27936 | | { PseudoVSRL_VV_MF2, VSRL_VV }, // 8779 |
27937 | | { PseudoVSRL_VV_MF2_MASK, VSRL_VV }, // 8780 |
27938 | | { PseudoVSRL_VV_MF4, VSRL_VV }, // 8781 |
27939 | | { PseudoVSRL_VV_MF4_MASK, VSRL_VV }, // 8782 |
27940 | | { PseudoVSRL_VV_MF8, VSRL_VV }, // 8783 |
27941 | | { PseudoVSRL_VV_MF8_MASK, VSRL_VV }, // 8784 |
27942 | | { PseudoVSRL_VX_M1, VSRL_VX }, // 8785 |
27943 | | { PseudoVSRL_VX_M1_MASK, VSRL_VX }, // 8786 |
27944 | | { PseudoVSRL_VX_M2, VSRL_VX }, // 8787 |
27945 | | { PseudoVSRL_VX_M2_MASK, VSRL_VX }, // 8788 |
27946 | | { PseudoVSRL_VX_M4, VSRL_VX }, // 8789 |
27947 | | { PseudoVSRL_VX_M4_MASK, VSRL_VX }, // 8790 |
27948 | | { PseudoVSRL_VX_M8, VSRL_VX }, // 8791 |
27949 | | { PseudoVSRL_VX_M8_MASK, VSRL_VX }, // 8792 |
27950 | | { PseudoVSRL_VX_MF2, VSRL_VX }, // 8793 |
27951 | | { PseudoVSRL_VX_MF2_MASK, VSRL_VX }, // 8794 |
27952 | | { PseudoVSRL_VX_MF4, VSRL_VX }, // 8795 |
27953 | | { PseudoVSRL_VX_MF4_MASK, VSRL_VX }, // 8796 |
27954 | | { PseudoVSRL_VX_MF8, VSRL_VX }, // 8797 |
27955 | | { PseudoVSRL_VX_MF8_MASK, VSRL_VX }, // 8798 |
27956 | | { PseudoVSSE16_V_M1, VSSE16_V }, // 8799 |
27957 | | { PseudoVSSE16_V_M1_MASK, VSSE16_V }, // 8800 |
27958 | | { PseudoVSSE16_V_M2, VSSE16_V }, // 8801 |
27959 | | { PseudoVSSE16_V_M2_MASK, VSSE16_V }, // 8802 |
27960 | | { PseudoVSSE16_V_M4, VSSE16_V }, // 8803 |
27961 | | { PseudoVSSE16_V_M4_MASK, VSSE16_V }, // 8804 |
27962 | | { PseudoVSSE16_V_M8, VSSE16_V }, // 8805 |
27963 | | { PseudoVSSE16_V_M8_MASK, VSSE16_V }, // 8806 |
27964 | | { PseudoVSSE16_V_MF2, VSSE16_V }, // 8807 |
27965 | | { PseudoVSSE16_V_MF2_MASK, VSSE16_V }, // 8808 |
27966 | | { PseudoVSSE16_V_MF4, VSSE16_V }, // 8809 |
27967 | | { PseudoVSSE16_V_MF4_MASK, VSSE16_V }, // 8810 |
27968 | | { PseudoVSSE32_V_M1, VSSE32_V }, // 8811 |
27969 | | { PseudoVSSE32_V_M1_MASK, VSSE32_V }, // 8812 |
27970 | | { PseudoVSSE32_V_M2, VSSE32_V }, // 8813 |
27971 | | { PseudoVSSE32_V_M2_MASK, VSSE32_V }, // 8814 |
27972 | | { PseudoVSSE32_V_M4, VSSE32_V }, // 8815 |
27973 | | { PseudoVSSE32_V_M4_MASK, VSSE32_V }, // 8816 |
27974 | | { PseudoVSSE32_V_M8, VSSE32_V }, // 8817 |
27975 | | { PseudoVSSE32_V_M8_MASK, VSSE32_V }, // 8818 |
27976 | | { PseudoVSSE32_V_MF2, VSSE32_V }, // 8819 |
27977 | | { PseudoVSSE32_V_MF2_MASK, VSSE32_V }, // 8820 |
27978 | | { PseudoVSSE64_V_M1, VSSE64_V }, // 8821 |
27979 | | { PseudoVSSE64_V_M1_MASK, VSSE64_V }, // 8822 |
27980 | | { PseudoVSSE64_V_M2, VSSE64_V }, // 8823 |
27981 | | { PseudoVSSE64_V_M2_MASK, VSSE64_V }, // 8824 |
27982 | | { PseudoVSSE64_V_M4, VSSE64_V }, // 8825 |
27983 | | { PseudoVSSE64_V_M4_MASK, VSSE64_V }, // 8826 |
27984 | | { PseudoVSSE64_V_M8, VSSE64_V }, // 8827 |
27985 | | { PseudoVSSE64_V_M8_MASK, VSSE64_V }, // 8828 |
27986 | | { PseudoVSSE8_V_M1, VSSE8_V }, // 8829 |
27987 | | { PseudoVSSE8_V_M1_MASK, VSSE8_V }, // 8830 |
27988 | | { PseudoVSSE8_V_M2, VSSE8_V }, // 8831 |
27989 | | { PseudoVSSE8_V_M2_MASK, VSSE8_V }, // 8832 |
27990 | | { PseudoVSSE8_V_M4, VSSE8_V }, // 8833 |
27991 | | { PseudoVSSE8_V_M4_MASK, VSSE8_V }, // 8834 |
27992 | | { PseudoVSSE8_V_M8, VSSE8_V }, // 8835 |
27993 | | { PseudoVSSE8_V_M8_MASK, VSSE8_V }, // 8836 |
27994 | | { PseudoVSSE8_V_MF2, VSSE8_V }, // 8837 |
27995 | | { PseudoVSSE8_V_MF2_MASK, VSSE8_V }, // 8838 |
27996 | | { PseudoVSSE8_V_MF4, VSSE8_V }, // 8839 |
27997 | | { PseudoVSSE8_V_MF4_MASK, VSSE8_V }, // 8840 |
27998 | | { PseudoVSSE8_V_MF8, VSSE8_V }, // 8841 |
27999 | | { PseudoVSSE8_V_MF8_MASK, VSSE8_V }, // 8842 |
28000 | | { PseudoVSSEG2E16_V_M1, VSSEG2E16_V }, // 8843 |
28001 | | { PseudoVSSEG2E16_V_M1_MASK, VSSEG2E16_V }, // 8844 |
28002 | | { PseudoVSSEG2E16_V_M2, VSSEG2E16_V }, // 8845 |
28003 | | { PseudoVSSEG2E16_V_M2_MASK, VSSEG2E16_V }, // 8846 |
28004 | | { PseudoVSSEG2E16_V_M4, VSSEG2E16_V }, // 8847 |
28005 | | { PseudoVSSEG2E16_V_M4_MASK, VSSEG2E16_V }, // 8848 |
28006 | | { PseudoVSSEG2E16_V_MF2, VSSEG2E16_V }, // 8849 |
28007 | | { PseudoVSSEG2E16_V_MF2_MASK, VSSEG2E16_V }, // 8850 |
28008 | | { PseudoVSSEG2E16_V_MF4, VSSEG2E16_V }, // 8851 |
28009 | | { PseudoVSSEG2E16_V_MF4_MASK, VSSEG2E16_V }, // 8852 |
28010 | | { PseudoVSSEG2E32_V_M1, VSSEG2E32_V }, // 8853 |
28011 | | { PseudoVSSEG2E32_V_M1_MASK, VSSEG2E32_V }, // 8854 |
28012 | | { PseudoVSSEG2E32_V_M2, VSSEG2E32_V }, // 8855 |
28013 | | { PseudoVSSEG2E32_V_M2_MASK, VSSEG2E32_V }, // 8856 |
28014 | | { PseudoVSSEG2E32_V_M4, VSSEG2E32_V }, // 8857 |
28015 | | { PseudoVSSEG2E32_V_M4_MASK, VSSEG2E32_V }, // 8858 |
28016 | | { PseudoVSSEG2E32_V_MF2, VSSEG2E32_V }, // 8859 |
28017 | | { PseudoVSSEG2E32_V_MF2_MASK, VSSEG2E32_V }, // 8860 |
28018 | | { PseudoVSSEG2E64_V_M1, VSSEG2E64_V }, // 8861 |
28019 | | { PseudoVSSEG2E64_V_M1_MASK, VSSEG2E64_V }, // 8862 |
28020 | | { PseudoVSSEG2E64_V_M2, VSSEG2E64_V }, // 8863 |
28021 | | { PseudoVSSEG2E64_V_M2_MASK, VSSEG2E64_V }, // 8864 |
28022 | | { PseudoVSSEG2E64_V_M4, VSSEG2E64_V }, // 8865 |
28023 | | { PseudoVSSEG2E64_V_M4_MASK, VSSEG2E64_V }, // 8866 |
28024 | | { PseudoVSSEG2E8_V_M1, VSSEG2E8_V }, // 8867 |
28025 | | { PseudoVSSEG2E8_V_M1_MASK, VSSEG2E8_V }, // 8868 |
28026 | | { PseudoVSSEG2E8_V_M2, VSSEG2E8_V }, // 8869 |
28027 | | { PseudoVSSEG2E8_V_M2_MASK, VSSEG2E8_V }, // 8870 |
28028 | | { PseudoVSSEG2E8_V_M4, VSSEG2E8_V }, // 8871 |
28029 | | { PseudoVSSEG2E8_V_M4_MASK, VSSEG2E8_V }, // 8872 |
28030 | | { PseudoVSSEG2E8_V_MF2, VSSEG2E8_V }, // 8873 |
28031 | | { PseudoVSSEG2E8_V_MF2_MASK, VSSEG2E8_V }, // 8874 |
28032 | | { PseudoVSSEG2E8_V_MF4, VSSEG2E8_V }, // 8875 |
28033 | | { PseudoVSSEG2E8_V_MF4_MASK, VSSEG2E8_V }, // 8876 |
28034 | | { PseudoVSSEG2E8_V_MF8, VSSEG2E8_V }, // 8877 |
28035 | | { PseudoVSSEG2E8_V_MF8_MASK, VSSEG2E8_V }, // 8878 |
28036 | | { PseudoVSSEG3E16_V_M1, VSSEG3E16_V }, // 8879 |
28037 | | { PseudoVSSEG3E16_V_M1_MASK, VSSEG3E16_V }, // 8880 |
28038 | | { PseudoVSSEG3E16_V_M2, VSSEG3E16_V }, // 8881 |
28039 | | { PseudoVSSEG3E16_V_M2_MASK, VSSEG3E16_V }, // 8882 |
28040 | | { PseudoVSSEG3E16_V_MF2, VSSEG3E16_V }, // 8883 |
28041 | | { PseudoVSSEG3E16_V_MF2_MASK, VSSEG3E16_V }, // 8884 |
28042 | | { PseudoVSSEG3E16_V_MF4, VSSEG3E16_V }, // 8885 |
28043 | | { PseudoVSSEG3E16_V_MF4_MASK, VSSEG3E16_V }, // 8886 |
28044 | | { PseudoVSSEG3E32_V_M1, VSSEG3E32_V }, // 8887 |
28045 | | { PseudoVSSEG3E32_V_M1_MASK, VSSEG3E32_V }, // 8888 |
28046 | | { PseudoVSSEG3E32_V_M2, VSSEG3E32_V }, // 8889 |
28047 | | { PseudoVSSEG3E32_V_M2_MASK, VSSEG3E32_V }, // 8890 |
28048 | | { PseudoVSSEG3E32_V_MF2, VSSEG3E32_V }, // 8891 |
28049 | | { PseudoVSSEG3E32_V_MF2_MASK, VSSEG3E32_V }, // 8892 |
28050 | | { PseudoVSSEG3E64_V_M1, VSSEG3E64_V }, // 8893 |
28051 | | { PseudoVSSEG3E64_V_M1_MASK, VSSEG3E64_V }, // 8894 |
28052 | | { PseudoVSSEG3E64_V_M2, VSSEG3E64_V }, // 8895 |
28053 | | { PseudoVSSEG3E64_V_M2_MASK, VSSEG3E64_V }, // 8896 |
28054 | | { PseudoVSSEG3E8_V_M1, VSSEG3E8_V }, // 8897 |
28055 | | { PseudoVSSEG3E8_V_M1_MASK, VSSEG3E8_V }, // 8898 |
28056 | | { PseudoVSSEG3E8_V_M2, VSSEG3E8_V }, // 8899 |
28057 | | { PseudoVSSEG3E8_V_M2_MASK, VSSEG3E8_V }, // 8900 |
28058 | | { PseudoVSSEG3E8_V_MF2, VSSEG3E8_V }, // 8901 |
28059 | | { PseudoVSSEG3E8_V_MF2_MASK, VSSEG3E8_V }, // 8902 |
28060 | | { PseudoVSSEG3E8_V_MF4, VSSEG3E8_V }, // 8903 |
28061 | | { PseudoVSSEG3E8_V_MF4_MASK, VSSEG3E8_V }, // 8904 |
28062 | | { PseudoVSSEG3E8_V_MF8, VSSEG3E8_V }, // 8905 |
28063 | | { PseudoVSSEG3E8_V_MF8_MASK, VSSEG3E8_V }, // 8906 |
28064 | | { PseudoVSSEG4E16_V_M1, VSSEG4E16_V }, // 8907 |
28065 | | { PseudoVSSEG4E16_V_M1_MASK, VSSEG4E16_V }, // 8908 |
28066 | | { PseudoVSSEG4E16_V_M2, VSSEG4E16_V }, // 8909 |
28067 | | { PseudoVSSEG4E16_V_M2_MASK, VSSEG4E16_V }, // 8910 |
28068 | | { PseudoVSSEG4E16_V_MF2, VSSEG4E16_V }, // 8911 |
28069 | | { PseudoVSSEG4E16_V_MF2_MASK, VSSEG4E16_V }, // 8912 |
28070 | | { PseudoVSSEG4E16_V_MF4, VSSEG4E16_V }, // 8913 |
28071 | | { PseudoVSSEG4E16_V_MF4_MASK, VSSEG4E16_V }, // 8914 |
28072 | | { PseudoVSSEG4E32_V_M1, VSSEG4E32_V }, // 8915 |
28073 | | { PseudoVSSEG4E32_V_M1_MASK, VSSEG4E32_V }, // 8916 |
28074 | | { PseudoVSSEG4E32_V_M2, VSSEG4E32_V }, // 8917 |
28075 | | { PseudoVSSEG4E32_V_M2_MASK, VSSEG4E32_V }, // 8918 |
28076 | | { PseudoVSSEG4E32_V_MF2, VSSEG4E32_V }, // 8919 |
28077 | | { PseudoVSSEG4E32_V_MF2_MASK, VSSEG4E32_V }, // 8920 |
28078 | | { PseudoVSSEG4E64_V_M1, VSSEG4E64_V }, // 8921 |
28079 | | { PseudoVSSEG4E64_V_M1_MASK, VSSEG4E64_V }, // 8922 |
28080 | | { PseudoVSSEG4E64_V_M2, VSSEG4E64_V }, // 8923 |
28081 | | { PseudoVSSEG4E64_V_M2_MASK, VSSEG4E64_V }, // 8924 |
28082 | | { PseudoVSSEG4E8_V_M1, VSSEG4E8_V }, // 8925 |
28083 | | { PseudoVSSEG4E8_V_M1_MASK, VSSEG4E8_V }, // 8926 |
28084 | | { PseudoVSSEG4E8_V_M2, VSSEG4E8_V }, // 8927 |
28085 | | { PseudoVSSEG4E8_V_M2_MASK, VSSEG4E8_V }, // 8928 |
28086 | | { PseudoVSSEG4E8_V_MF2, VSSEG4E8_V }, // 8929 |
28087 | | { PseudoVSSEG4E8_V_MF2_MASK, VSSEG4E8_V }, // 8930 |
28088 | | { PseudoVSSEG4E8_V_MF4, VSSEG4E8_V }, // 8931 |
28089 | | { PseudoVSSEG4E8_V_MF4_MASK, VSSEG4E8_V }, // 8932 |
28090 | | { PseudoVSSEG4E8_V_MF8, VSSEG4E8_V }, // 8933 |
28091 | | { PseudoVSSEG4E8_V_MF8_MASK, VSSEG4E8_V }, // 8934 |
28092 | | { PseudoVSSEG5E16_V_M1, VSSEG5E16_V }, // 8935 |
28093 | | { PseudoVSSEG5E16_V_M1_MASK, VSSEG5E16_V }, // 8936 |
28094 | | { PseudoVSSEG5E16_V_MF2, VSSEG5E16_V }, // 8937 |
28095 | | { PseudoVSSEG5E16_V_MF2_MASK, VSSEG5E16_V }, // 8938 |
28096 | | { PseudoVSSEG5E16_V_MF4, VSSEG5E16_V }, // 8939 |
28097 | | { PseudoVSSEG5E16_V_MF4_MASK, VSSEG5E16_V }, // 8940 |
28098 | | { PseudoVSSEG5E32_V_M1, VSSEG5E32_V }, // 8941 |
28099 | | { PseudoVSSEG5E32_V_M1_MASK, VSSEG5E32_V }, // 8942 |
28100 | | { PseudoVSSEG5E32_V_MF2, VSSEG5E32_V }, // 8943 |
28101 | | { PseudoVSSEG5E32_V_MF2_MASK, VSSEG5E32_V }, // 8944 |
28102 | | { PseudoVSSEG5E64_V_M1, VSSEG5E64_V }, // 8945 |
28103 | | { PseudoVSSEG5E64_V_M1_MASK, VSSEG5E64_V }, // 8946 |
28104 | | { PseudoVSSEG5E8_V_M1, VSSEG5E8_V }, // 8947 |
28105 | | { PseudoVSSEG5E8_V_M1_MASK, VSSEG5E8_V }, // 8948 |
28106 | | { PseudoVSSEG5E8_V_MF2, VSSEG5E8_V }, // 8949 |
28107 | | { PseudoVSSEG5E8_V_MF2_MASK, VSSEG5E8_V }, // 8950 |
28108 | | { PseudoVSSEG5E8_V_MF4, VSSEG5E8_V }, // 8951 |
28109 | | { PseudoVSSEG5E8_V_MF4_MASK, VSSEG5E8_V }, // 8952 |
28110 | | { PseudoVSSEG5E8_V_MF8, VSSEG5E8_V }, // 8953 |
28111 | | { PseudoVSSEG5E8_V_MF8_MASK, VSSEG5E8_V }, // 8954 |
28112 | | { PseudoVSSEG6E16_V_M1, VSSEG6E16_V }, // 8955 |
28113 | | { PseudoVSSEG6E16_V_M1_MASK, VSSEG6E16_V }, // 8956 |
28114 | | { PseudoVSSEG6E16_V_MF2, VSSEG6E16_V }, // 8957 |
28115 | | { PseudoVSSEG6E16_V_MF2_MASK, VSSEG6E16_V }, // 8958 |
28116 | | { PseudoVSSEG6E16_V_MF4, VSSEG6E16_V }, // 8959 |
28117 | | { PseudoVSSEG6E16_V_MF4_MASK, VSSEG6E16_V }, // 8960 |
28118 | | { PseudoVSSEG6E32_V_M1, VSSEG6E32_V }, // 8961 |
28119 | | { PseudoVSSEG6E32_V_M1_MASK, VSSEG6E32_V }, // 8962 |
28120 | | { PseudoVSSEG6E32_V_MF2, VSSEG6E32_V }, // 8963 |
28121 | | { PseudoVSSEG6E32_V_MF2_MASK, VSSEG6E32_V }, // 8964 |
28122 | | { PseudoVSSEG6E64_V_M1, VSSEG6E64_V }, // 8965 |
28123 | | { PseudoVSSEG6E64_V_M1_MASK, VSSEG6E64_V }, // 8966 |
28124 | | { PseudoVSSEG6E8_V_M1, VSSEG6E8_V }, // 8967 |
28125 | | { PseudoVSSEG6E8_V_M1_MASK, VSSEG6E8_V }, // 8968 |
28126 | | { PseudoVSSEG6E8_V_MF2, VSSEG6E8_V }, // 8969 |
28127 | | { PseudoVSSEG6E8_V_MF2_MASK, VSSEG6E8_V }, // 8970 |
28128 | | { PseudoVSSEG6E8_V_MF4, VSSEG6E8_V }, // 8971 |
28129 | | { PseudoVSSEG6E8_V_MF4_MASK, VSSEG6E8_V }, // 8972 |
28130 | | { PseudoVSSEG6E8_V_MF8, VSSEG6E8_V }, // 8973 |
28131 | | { PseudoVSSEG6E8_V_MF8_MASK, VSSEG6E8_V }, // 8974 |
28132 | | { PseudoVSSEG7E16_V_M1, VSSEG7E16_V }, // 8975 |
28133 | | { PseudoVSSEG7E16_V_M1_MASK, VSSEG7E16_V }, // 8976 |
28134 | | { PseudoVSSEG7E16_V_MF2, VSSEG7E16_V }, // 8977 |
28135 | | { PseudoVSSEG7E16_V_MF2_MASK, VSSEG7E16_V }, // 8978 |
28136 | | { PseudoVSSEG7E16_V_MF4, VSSEG7E16_V }, // 8979 |
28137 | | { PseudoVSSEG7E16_V_MF4_MASK, VSSEG7E16_V }, // 8980 |
28138 | | { PseudoVSSEG7E32_V_M1, VSSEG7E32_V }, // 8981 |
28139 | | { PseudoVSSEG7E32_V_M1_MASK, VSSEG7E32_V }, // 8982 |
28140 | | { PseudoVSSEG7E32_V_MF2, VSSEG7E32_V }, // 8983 |
28141 | | { PseudoVSSEG7E32_V_MF2_MASK, VSSEG7E32_V }, // 8984 |
28142 | | { PseudoVSSEG7E64_V_M1, VSSEG7E64_V }, // 8985 |
28143 | | { PseudoVSSEG7E64_V_M1_MASK, VSSEG7E64_V }, // 8986 |
28144 | | { PseudoVSSEG7E8_V_M1, VSSEG7E8_V }, // 8987 |
28145 | | { PseudoVSSEG7E8_V_M1_MASK, VSSEG7E8_V }, // 8988 |
28146 | | { PseudoVSSEG7E8_V_MF2, VSSEG7E8_V }, // 8989 |
28147 | | { PseudoVSSEG7E8_V_MF2_MASK, VSSEG7E8_V }, // 8990 |
28148 | | { PseudoVSSEG7E8_V_MF4, VSSEG7E8_V }, // 8991 |
28149 | | { PseudoVSSEG7E8_V_MF4_MASK, VSSEG7E8_V }, // 8992 |
28150 | | { PseudoVSSEG7E8_V_MF8, VSSEG7E8_V }, // 8993 |
28151 | | { PseudoVSSEG7E8_V_MF8_MASK, VSSEG7E8_V }, // 8994 |
28152 | | { PseudoVSSEG8E16_V_M1, VSSEG8E16_V }, // 8995 |
28153 | | { PseudoVSSEG8E16_V_M1_MASK, VSSEG8E16_V }, // 8996 |
28154 | | { PseudoVSSEG8E16_V_MF2, VSSEG8E16_V }, // 8997 |
28155 | | { PseudoVSSEG8E16_V_MF2_MASK, VSSEG8E16_V }, // 8998 |
28156 | | { PseudoVSSEG8E16_V_MF4, VSSEG8E16_V }, // 8999 |
28157 | | { PseudoVSSEG8E16_V_MF4_MASK, VSSEG8E16_V }, // 9000 |
28158 | | { PseudoVSSEG8E32_V_M1, VSSEG8E32_V }, // 9001 |
28159 | | { PseudoVSSEG8E32_V_M1_MASK, VSSEG8E32_V }, // 9002 |
28160 | | { PseudoVSSEG8E32_V_MF2, VSSEG8E32_V }, // 9003 |
28161 | | { PseudoVSSEG8E32_V_MF2_MASK, VSSEG8E32_V }, // 9004 |
28162 | | { PseudoVSSEG8E64_V_M1, VSSEG8E64_V }, // 9005 |
28163 | | { PseudoVSSEG8E64_V_M1_MASK, VSSEG8E64_V }, // 9006 |
28164 | | { PseudoVSSEG8E8_V_M1, VSSEG8E8_V }, // 9007 |
28165 | | { PseudoVSSEG8E8_V_M1_MASK, VSSEG8E8_V }, // 9008 |
28166 | | { PseudoVSSEG8E8_V_MF2, VSSEG8E8_V }, // 9009 |
28167 | | { PseudoVSSEG8E8_V_MF2_MASK, VSSEG8E8_V }, // 9010 |
28168 | | { PseudoVSSEG8E8_V_MF4, VSSEG8E8_V }, // 9011 |
28169 | | { PseudoVSSEG8E8_V_MF4_MASK, VSSEG8E8_V }, // 9012 |
28170 | | { PseudoVSSEG8E8_V_MF8, VSSEG8E8_V }, // 9013 |
28171 | | { PseudoVSSEG8E8_V_MF8_MASK, VSSEG8E8_V }, // 9014 |
28172 | | { PseudoVSSRA_VI_M1, VSSRA_VI }, // 9015 |
28173 | | { PseudoVSSRA_VI_M1_MASK, VSSRA_VI }, // 9016 |
28174 | | { PseudoVSSRA_VI_M2, VSSRA_VI }, // 9017 |
28175 | | { PseudoVSSRA_VI_M2_MASK, VSSRA_VI }, // 9018 |
28176 | | { PseudoVSSRA_VI_M4, VSSRA_VI }, // 9019 |
28177 | | { PseudoVSSRA_VI_M4_MASK, VSSRA_VI }, // 9020 |
28178 | | { PseudoVSSRA_VI_M8, VSSRA_VI }, // 9021 |
28179 | | { PseudoVSSRA_VI_M8_MASK, VSSRA_VI }, // 9022 |
28180 | | { PseudoVSSRA_VI_MF2, VSSRA_VI }, // 9023 |
28181 | | { PseudoVSSRA_VI_MF2_MASK, VSSRA_VI }, // 9024 |
28182 | | { PseudoVSSRA_VI_MF4, VSSRA_VI }, // 9025 |
28183 | | { PseudoVSSRA_VI_MF4_MASK, VSSRA_VI }, // 9026 |
28184 | | { PseudoVSSRA_VI_MF8, VSSRA_VI }, // 9027 |
28185 | | { PseudoVSSRA_VI_MF8_MASK, VSSRA_VI }, // 9028 |
28186 | | { PseudoVSSRA_VV_M1, VSSRA_VV }, // 9029 |
28187 | | { PseudoVSSRA_VV_M1_MASK, VSSRA_VV }, // 9030 |
28188 | | { PseudoVSSRA_VV_M2, VSSRA_VV }, // 9031 |
28189 | | { PseudoVSSRA_VV_M2_MASK, VSSRA_VV }, // 9032 |
28190 | | { PseudoVSSRA_VV_M4, VSSRA_VV }, // 9033 |
28191 | | { PseudoVSSRA_VV_M4_MASK, VSSRA_VV }, // 9034 |
28192 | | { PseudoVSSRA_VV_M8, VSSRA_VV }, // 9035 |
28193 | | { PseudoVSSRA_VV_M8_MASK, VSSRA_VV }, // 9036 |
28194 | | { PseudoVSSRA_VV_MF2, VSSRA_VV }, // 9037 |
28195 | | { PseudoVSSRA_VV_MF2_MASK, VSSRA_VV }, // 9038 |
28196 | | { PseudoVSSRA_VV_MF4, VSSRA_VV }, // 9039 |
28197 | | { PseudoVSSRA_VV_MF4_MASK, VSSRA_VV }, // 9040 |
28198 | | { PseudoVSSRA_VV_MF8, VSSRA_VV }, // 9041 |
28199 | | { PseudoVSSRA_VV_MF8_MASK, VSSRA_VV }, // 9042 |
28200 | | { PseudoVSSRA_VX_M1, VSSRA_VX }, // 9043 |
28201 | | { PseudoVSSRA_VX_M1_MASK, VSSRA_VX }, // 9044 |
28202 | | { PseudoVSSRA_VX_M2, VSSRA_VX }, // 9045 |
28203 | | { PseudoVSSRA_VX_M2_MASK, VSSRA_VX }, // 9046 |
28204 | | { PseudoVSSRA_VX_M4, VSSRA_VX }, // 9047 |
28205 | | { PseudoVSSRA_VX_M4_MASK, VSSRA_VX }, // 9048 |
28206 | | { PseudoVSSRA_VX_M8, VSSRA_VX }, // 9049 |
28207 | | { PseudoVSSRA_VX_M8_MASK, VSSRA_VX }, // 9050 |
28208 | | { PseudoVSSRA_VX_MF2, VSSRA_VX }, // 9051 |
28209 | | { PseudoVSSRA_VX_MF2_MASK, VSSRA_VX }, // 9052 |
28210 | | { PseudoVSSRA_VX_MF4, VSSRA_VX }, // 9053 |
28211 | | { PseudoVSSRA_VX_MF4_MASK, VSSRA_VX }, // 9054 |
28212 | | { PseudoVSSRA_VX_MF8, VSSRA_VX }, // 9055 |
28213 | | { PseudoVSSRA_VX_MF8_MASK, VSSRA_VX }, // 9056 |
28214 | | { PseudoVSSRL_VI_M1, VSSRL_VI }, // 9057 |
28215 | | { PseudoVSSRL_VI_M1_MASK, VSSRL_VI }, // 9058 |
28216 | | { PseudoVSSRL_VI_M2, VSSRL_VI }, // 9059 |
28217 | | { PseudoVSSRL_VI_M2_MASK, VSSRL_VI }, // 9060 |
28218 | | { PseudoVSSRL_VI_M4, VSSRL_VI }, // 9061 |
28219 | | { PseudoVSSRL_VI_M4_MASK, VSSRL_VI }, // 9062 |
28220 | | { PseudoVSSRL_VI_M8, VSSRL_VI }, // 9063 |
28221 | | { PseudoVSSRL_VI_M8_MASK, VSSRL_VI }, // 9064 |
28222 | | { PseudoVSSRL_VI_MF2, VSSRL_VI }, // 9065 |
28223 | | { PseudoVSSRL_VI_MF2_MASK, VSSRL_VI }, // 9066 |
28224 | | { PseudoVSSRL_VI_MF4, VSSRL_VI }, // 9067 |
28225 | | { PseudoVSSRL_VI_MF4_MASK, VSSRL_VI }, // 9068 |
28226 | | { PseudoVSSRL_VI_MF8, VSSRL_VI }, // 9069 |
28227 | | { PseudoVSSRL_VI_MF8_MASK, VSSRL_VI }, // 9070 |
28228 | | { PseudoVSSRL_VV_M1, VSSRL_VV }, // 9071 |
28229 | | { PseudoVSSRL_VV_M1_MASK, VSSRL_VV }, // 9072 |
28230 | | { PseudoVSSRL_VV_M2, VSSRL_VV }, // 9073 |
28231 | | { PseudoVSSRL_VV_M2_MASK, VSSRL_VV }, // 9074 |
28232 | | { PseudoVSSRL_VV_M4, VSSRL_VV }, // 9075 |
28233 | | { PseudoVSSRL_VV_M4_MASK, VSSRL_VV }, // 9076 |
28234 | | { PseudoVSSRL_VV_M8, VSSRL_VV }, // 9077 |
28235 | | { PseudoVSSRL_VV_M8_MASK, VSSRL_VV }, // 9078 |
28236 | | { PseudoVSSRL_VV_MF2, VSSRL_VV }, // 9079 |
28237 | | { PseudoVSSRL_VV_MF2_MASK, VSSRL_VV }, // 9080 |
28238 | | { PseudoVSSRL_VV_MF4, VSSRL_VV }, // 9081 |
28239 | | { PseudoVSSRL_VV_MF4_MASK, VSSRL_VV }, // 9082 |
28240 | | { PseudoVSSRL_VV_MF8, VSSRL_VV }, // 9083 |
28241 | | { PseudoVSSRL_VV_MF8_MASK, VSSRL_VV }, // 9084 |
28242 | | { PseudoVSSRL_VX_M1, VSSRL_VX }, // 9085 |
28243 | | { PseudoVSSRL_VX_M1_MASK, VSSRL_VX }, // 9086 |
28244 | | { PseudoVSSRL_VX_M2, VSSRL_VX }, // 9087 |
28245 | | { PseudoVSSRL_VX_M2_MASK, VSSRL_VX }, // 9088 |
28246 | | { PseudoVSSRL_VX_M4, VSSRL_VX }, // 9089 |
28247 | | { PseudoVSSRL_VX_M4_MASK, VSSRL_VX }, // 9090 |
28248 | | { PseudoVSSRL_VX_M8, VSSRL_VX }, // 9091 |
28249 | | { PseudoVSSRL_VX_M8_MASK, VSSRL_VX }, // 9092 |
28250 | | { PseudoVSSRL_VX_MF2, VSSRL_VX }, // 9093 |
28251 | | { PseudoVSSRL_VX_MF2_MASK, VSSRL_VX }, // 9094 |
28252 | | { PseudoVSSRL_VX_MF4, VSSRL_VX }, // 9095 |
28253 | | { PseudoVSSRL_VX_MF4_MASK, VSSRL_VX }, // 9096 |
28254 | | { PseudoVSSRL_VX_MF8, VSSRL_VX }, // 9097 |
28255 | | { PseudoVSSRL_VX_MF8_MASK, VSSRL_VX }, // 9098 |
28256 | | { PseudoVSSSEG2E16_V_M1, VSSSEG2E16_V }, // 9099 |
28257 | | { PseudoVSSSEG2E16_V_M1_MASK, VSSSEG2E16_V }, // 9100 |
28258 | | { PseudoVSSSEG2E16_V_M2, VSSSEG2E16_V }, // 9101 |
28259 | | { PseudoVSSSEG2E16_V_M2_MASK, VSSSEG2E16_V }, // 9102 |
28260 | | { PseudoVSSSEG2E16_V_M4, VSSSEG2E16_V }, // 9103 |
28261 | | { PseudoVSSSEG2E16_V_M4_MASK, VSSSEG2E16_V }, // 9104 |
28262 | | { PseudoVSSSEG2E16_V_MF2, VSSSEG2E16_V }, // 9105 |
28263 | | { PseudoVSSSEG2E16_V_MF2_MASK, VSSSEG2E16_V }, // 9106 |
28264 | | { PseudoVSSSEG2E16_V_MF4, VSSSEG2E16_V }, // 9107 |
28265 | | { PseudoVSSSEG2E16_V_MF4_MASK, VSSSEG2E16_V }, // 9108 |
28266 | | { PseudoVSSSEG2E32_V_M1, VSSSEG2E32_V }, // 9109 |
28267 | | { PseudoVSSSEG2E32_V_M1_MASK, VSSSEG2E32_V }, // 9110 |
28268 | | { PseudoVSSSEG2E32_V_M2, VSSSEG2E32_V }, // 9111 |
28269 | | { PseudoVSSSEG2E32_V_M2_MASK, VSSSEG2E32_V }, // 9112 |
28270 | | { PseudoVSSSEG2E32_V_M4, VSSSEG2E32_V }, // 9113 |
28271 | | { PseudoVSSSEG2E32_V_M4_MASK, VSSSEG2E32_V }, // 9114 |
28272 | | { PseudoVSSSEG2E32_V_MF2, VSSSEG2E32_V }, // 9115 |
28273 | | { PseudoVSSSEG2E32_V_MF2_MASK, VSSSEG2E32_V }, // 9116 |
28274 | | { PseudoVSSSEG2E64_V_M1, VSSSEG2E64_V }, // 9117 |
28275 | | { PseudoVSSSEG2E64_V_M1_MASK, VSSSEG2E64_V }, // 9118 |
28276 | | { PseudoVSSSEG2E64_V_M2, VSSSEG2E64_V }, // 9119 |
28277 | | { PseudoVSSSEG2E64_V_M2_MASK, VSSSEG2E64_V }, // 9120 |
28278 | | { PseudoVSSSEG2E64_V_M4, VSSSEG2E64_V }, // 9121 |
28279 | | { PseudoVSSSEG2E64_V_M4_MASK, VSSSEG2E64_V }, // 9122 |
28280 | | { PseudoVSSSEG2E8_V_M1, VSSSEG2E8_V }, // 9123 |
28281 | | { PseudoVSSSEG2E8_V_M1_MASK, VSSSEG2E8_V }, // 9124 |
28282 | | { PseudoVSSSEG2E8_V_M2, VSSSEG2E8_V }, // 9125 |
28283 | | { PseudoVSSSEG2E8_V_M2_MASK, VSSSEG2E8_V }, // 9126 |
28284 | | { PseudoVSSSEG2E8_V_M4, VSSSEG2E8_V }, // 9127 |
28285 | | { PseudoVSSSEG2E8_V_M4_MASK, VSSSEG2E8_V }, // 9128 |
28286 | | { PseudoVSSSEG2E8_V_MF2, VSSSEG2E8_V }, // 9129 |
28287 | | { PseudoVSSSEG2E8_V_MF2_MASK, VSSSEG2E8_V }, // 9130 |
28288 | | { PseudoVSSSEG2E8_V_MF4, VSSSEG2E8_V }, // 9131 |
28289 | | { PseudoVSSSEG2E8_V_MF4_MASK, VSSSEG2E8_V }, // 9132 |
28290 | | { PseudoVSSSEG2E8_V_MF8, VSSSEG2E8_V }, // 9133 |
28291 | | { PseudoVSSSEG2E8_V_MF8_MASK, VSSSEG2E8_V }, // 9134 |
28292 | | { PseudoVSSSEG3E16_V_M1, VSSSEG3E16_V }, // 9135 |
28293 | | { PseudoVSSSEG3E16_V_M1_MASK, VSSSEG3E16_V }, // 9136 |
28294 | | { PseudoVSSSEG3E16_V_M2, VSSSEG3E16_V }, // 9137 |
28295 | | { PseudoVSSSEG3E16_V_M2_MASK, VSSSEG3E16_V }, // 9138 |
28296 | | { PseudoVSSSEG3E16_V_MF2, VSSSEG3E16_V }, // 9139 |
28297 | | { PseudoVSSSEG3E16_V_MF2_MASK, VSSSEG3E16_V }, // 9140 |
28298 | | { PseudoVSSSEG3E16_V_MF4, VSSSEG3E16_V }, // 9141 |
28299 | | { PseudoVSSSEG3E16_V_MF4_MASK, VSSSEG3E16_V }, // 9142 |
28300 | | { PseudoVSSSEG3E32_V_M1, VSSSEG3E32_V }, // 9143 |
28301 | | { PseudoVSSSEG3E32_V_M1_MASK, VSSSEG3E32_V }, // 9144 |
28302 | | { PseudoVSSSEG3E32_V_M2, VSSSEG3E32_V }, // 9145 |
28303 | | { PseudoVSSSEG3E32_V_M2_MASK, VSSSEG3E32_V }, // 9146 |
28304 | | { PseudoVSSSEG3E32_V_MF2, VSSSEG3E32_V }, // 9147 |
28305 | | { PseudoVSSSEG3E32_V_MF2_MASK, VSSSEG3E32_V }, // 9148 |
28306 | | { PseudoVSSSEG3E64_V_M1, VSSSEG3E64_V }, // 9149 |
28307 | | { PseudoVSSSEG3E64_V_M1_MASK, VSSSEG3E64_V }, // 9150 |
28308 | | { PseudoVSSSEG3E64_V_M2, VSSSEG3E64_V }, // 9151 |
28309 | | { PseudoVSSSEG3E64_V_M2_MASK, VSSSEG3E64_V }, // 9152 |
28310 | | { PseudoVSSSEG3E8_V_M1, VSSSEG3E8_V }, // 9153 |
28311 | | { PseudoVSSSEG3E8_V_M1_MASK, VSSSEG3E8_V }, // 9154 |
28312 | | { PseudoVSSSEG3E8_V_M2, VSSSEG3E8_V }, // 9155 |
28313 | | { PseudoVSSSEG3E8_V_M2_MASK, VSSSEG3E8_V }, // 9156 |
28314 | | { PseudoVSSSEG3E8_V_MF2, VSSSEG3E8_V }, // 9157 |
28315 | | { PseudoVSSSEG3E8_V_MF2_MASK, VSSSEG3E8_V }, // 9158 |
28316 | | { PseudoVSSSEG3E8_V_MF4, VSSSEG3E8_V }, // 9159 |
28317 | | { PseudoVSSSEG3E8_V_MF4_MASK, VSSSEG3E8_V }, // 9160 |
28318 | | { PseudoVSSSEG3E8_V_MF8, VSSSEG3E8_V }, // 9161 |
28319 | | { PseudoVSSSEG3E8_V_MF8_MASK, VSSSEG3E8_V }, // 9162 |
28320 | | { PseudoVSSSEG4E16_V_M1, VSSSEG4E16_V }, // 9163 |
28321 | | { PseudoVSSSEG4E16_V_M1_MASK, VSSSEG4E16_V }, // 9164 |
28322 | | { PseudoVSSSEG4E16_V_M2, VSSSEG4E16_V }, // 9165 |
28323 | | { PseudoVSSSEG4E16_V_M2_MASK, VSSSEG4E16_V }, // 9166 |
28324 | | { PseudoVSSSEG4E16_V_MF2, VSSSEG4E16_V }, // 9167 |
28325 | | { PseudoVSSSEG4E16_V_MF2_MASK, VSSSEG4E16_V }, // 9168 |
28326 | | { PseudoVSSSEG4E16_V_MF4, VSSSEG4E16_V }, // 9169 |
28327 | | { PseudoVSSSEG4E16_V_MF4_MASK, VSSSEG4E16_V }, // 9170 |
28328 | | { PseudoVSSSEG4E32_V_M1, VSSSEG4E32_V }, // 9171 |
28329 | | { PseudoVSSSEG4E32_V_M1_MASK, VSSSEG4E32_V }, // 9172 |
28330 | | { PseudoVSSSEG4E32_V_M2, VSSSEG4E32_V }, // 9173 |
28331 | | { PseudoVSSSEG4E32_V_M2_MASK, VSSSEG4E32_V }, // 9174 |
28332 | | { PseudoVSSSEG4E32_V_MF2, VSSSEG4E32_V }, // 9175 |
28333 | | { PseudoVSSSEG4E32_V_MF2_MASK, VSSSEG4E32_V }, // 9176 |
28334 | | { PseudoVSSSEG4E64_V_M1, VSSSEG4E64_V }, // 9177 |
28335 | | { PseudoVSSSEG4E64_V_M1_MASK, VSSSEG4E64_V }, // 9178 |
28336 | | { PseudoVSSSEG4E64_V_M2, VSSSEG4E64_V }, // 9179 |
28337 | | { PseudoVSSSEG4E64_V_M2_MASK, VSSSEG4E64_V }, // 9180 |
28338 | | { PseudoVSSSEG4E8_V_M1, VSSSEG4E8_V }, // 9181 |
28339 | | { PseudoVSSSEG4E8_V_M1_MASK, VSSSEG4E8_V }, // 9182 |
28340 | | { PseudoVSSSEG4E8_V_M2, VSSSEG4E8_V }, // 9183 |
28341 | | { PseudoVSSSEG4E8_V_M2_MASK, VSSSEG4E8_V }, // 9184 |
28342 | | { PseudoVSSSEG4E8_V_MF2, VSSSEG4E8_V }, // 9185 |
28343 | | { PseudoVSSSEG4E8_V_MF2_MASK, VSSSEG4E8_V }, // 9186 |
28344 | | { PseudoVSSSEG4E8_V_MF4, VSSSEG4E8_V }, // 9187 |
28345 | | { PseudoVSSSEG4E8_V_MF4_MASK, VSSSEG4E8_V }, // 9188 |
28346 | | { PseudoVSSSEG4E8_V_MF8, VSSSEG4E8_V }, // 9189 |
28347 | | { PseudoVSSSEG4E8_V_MF8_MASK, VSSSEG4E8_V }, // 9190 |
28348 | | { PseudoVSSSEG5E16_V_M1, VSSSEG5E16_V }, // 9191 |
28349 | | { PseudoVSSSEG5E16_V_M1_MASK, VSSSEG5E16_V }, // 9192 |
28350 | | { PseudoVSSSEG5E16_V_MF2, VSSSEG5E16_V }, // 9193 |
28351 | | { PseudoVSSSEG5E16_V_MF2_MASK, VSSSEG5E16_V }, // 9194 |
28352 | | { PseudoVSSSEG5E16_V_MF4, VSSSEG5E16_V }, // 9195 |
28353 | | { PseudoVSSSEG5E16_V_MF4_MASK, VSSSEG5E16_V }, // 9196 |
28354 | | { PseudoVSSSEG5E32_V_M1, VSSSEG5E32_V }, // 9197 |
28355 | | { PseudoVSSSEG5E32_V_M1_MASK, VSSSEG5E32_V }, // 9198 |
28356 | | { PseudoVSSSEG5E32_V_MF2, VSSSEG5E32_V }, // 9199 |
28357 | | { PseudoVSSSEG5E32_V_MF2_MASK, VSSSEG5E32_V }, // 9200 |
28358 | | { PseudoVSSSEG5E64_V_M1, VSSSEG5E64_V }, // 9201 |
28359 | | { PseudoVSSSEG5E64_V_M1_MASK, VSSSEG5E64_V }, // 9202 |
28360 | | { PseudoVSSSEG5E8_V_M1, VSSSEG5E8_V }, // 9203 |
28361 | | { PseudoVSSSEG5E8_V_M1_MASK, VSSSEG5E8_V }, // 9204 |
28362 | | { PseudoVSSSEG5E8_V_MF2, VSSSEG5E8_V }, // 9205 |
28363 | | { PseudoVSSSEG5E8_V_MF2_MASK, VSSSEG5E8_V }, // 9206 |
28364 | | { PseudoVSSSEG5E8_V_MF4, VSSSEG5E8_V }, // 9207 |
28365 | | { PseudoVSSSEG5E8_V_MF4_MASK, VSSSEG5E8_V }, // 9208 |
28366 | | { PseudoVSSSEG5E8_V_MF8, VSSSEG5E8_V }, // 9209 |
28367 | | { PseudoVSSSEG5E8_V_MF8_MASK, VSSSEG5E8_V }, // 9210 |
28368 | | { PseudoVSSSEG6E16_V_M1, VSSSEG6E16_V }, // 9211 |
28369 | | { PseudoVSSSEG6E16_V_M1_MASK, VSSSEG6E16_V }, // 9212 |
28370 | | { PseudoVSSSEG6E16_V_MF2, VSSSEG6E16_V }, // 9213 |
28371 | | { PseudoVSSSEG6E16_V_MF2_MASK, VSSSEG6E16_V }, // 9214 |
28372 | | { PseudoVSSSEG6E16_V_MF4, VSSSEG6E16_V }, // 9215 |
28373 | | { PseudoVSSSEG6E16_V_MF4_MASK, VSSSEG6E16_V }, // 9216 |
28374 | | { PseudoVSSSEG6E32_V_M1, VSSSEG6E32_V }, // 9217 |
28375 | | { PseudoVSSSEG6E32_V_M1_MASK, VSSSEG6E32_V }, // 9218 |
28376 | | { PseudoVSSSEG6E32_V_MF2, VSSSEG6E32_V }, // 9219 |
28377 | | { PseudoVSSSEG6E32_V_MF2_MASK, VSSSEG6E32_V }, // 9220 |
28378 | | { PseudoVSSSEG6E64_V_M1, VSSSEG6E64_V }, // 9221 |
28379 | | { PseudoVSSSEG6E64_V_M1_MASK, VSSSEG6E64_V }, // 9222 |
28380 | | { PseudoVSSSEG6E8_V_M1, VSSSEG6E8_V }, // 9223 |
28381 | | { PseudoVSSSEG6E8_V_M1_MASK, VSSSEG6E8_V }, // 9224 |
28382 | | { PseudoVSSSEG6E8_V_MF2, VSSSEG6E8_V }, // 9225 |
28383 | | { PseudoVSSSEG6E8_V_MF2_MASK, VSSSEG6E8_V }, // 9226 |
28384 | | { PseudoVSSSEG6E8_V_MF4, VSSSEG6E8_V }, // 9227 |
28385 | | { PseudoVSSSEG6E8_V_MF4_MASK, VSSSEG6E8_V }, // 9228 |
28386 | | { PseudoVSSSEG6E8_V_MF8, VSSSEG6E8_V }, // 9229 |
28387 | | { PseudoVSSSEG6E8_V_MF8_MASK, VSSSEG6E8_V }, // 9230 |
28388 | | { PseudoVSSSEG7E16_V_M1, VSSSEG7E16_V }, // 9231 |
28389 | | { PseudoVSSSEG7E16_V_M1_MASK, VSSSEG7E16_V }, // 9232 |
28390 | | { PseudoVSSSEG7E16_V_MF2, VSSSEG7E16_V }, // 9233 |
28391 | | { PseudoVSSSEG7E16_V_MF2_MASK, VSSSEG7E16_V }, // 9234 |
28392 | | { PseudoVSSSEG7E16_V_MF4, VSSSEG7E16_V }, // 9235 |
28393 | | { PseudoVSSSEG7E16_V_MF4_MASK, VSSSEG7E16_V }, // 9236 |
28394 | | { PseudoVSSSEG7E32_V_M1, VSSSEG7E32_V }, // 9237 |
28395 | | { PseudoVSSSEG7E32_V_M1_MASK, VSSSEG7E32_V }, // 9238 |
28396 | | { PseudoVSSSEG7E32_V_MF2, VSSSEG7E32_V }, // 9239 |
28397 | | { PseudoVSSSEG7E32_V_MF2_MASK, VSSSEG7E32_V }, // 9240 |
28398 | | { PseudoVSSSEG7E64_V_M1, VSSSEG7E64_V }, // 9241 |
28399 | | { PseudoVSSSEG7E64_V_M1_MASK, VSSSEG7E64_V }, // 9242 |
28400 | | { PseudoVSSSEG7E8_V_M1, VSSSEG7E8_V }, // 9243 |
28401 | | { PseudoVSSSEG7E8_V_M1_MASK, VSSSEG7E8_V }, // 9244 |
28402 | | { PseudoVSSSEG7E8_V_MF2, VSSSEG7E8_V }, // 9245 |
28403 | | { PseudoVSSSEG7E8_V_MF2_MASK, VSSSEG7E8_V }, // 9246 |
28404 | | { PseudoVSSSEG7E8_V_MF4, VSSSEG7E8_V }, // 9247 |
28405 | | { PseudoVSSSEG7E8_V_MF4_MASK, VSSSEG7E8_V }, // 9248 |
28406 | | { PseudoVSSSEG7E8_V_MF8, VSSSEG7E8_V }, // 9249 |
28407 | | { PseudoVSSSEG7E8_V_MF8_MASK, VSSSEG7E8_V }, // 9250 |
28408 | | { PseudoVSSSEG8E16_V_M1, VSSSEG8E16_V }, // 9251 |
28409 | | { PseudoVSSSEG8E16_V_M1_MASK, VSSSEG8E16_V }, // 9252 |
28410 | | { PseudoVSSSEG8E16_V_MF2, VSSSEG8E16_V }, // 9253 |
28411 | | { PseudoVSSSEG8E16_V_MF2_MASK, VSSSEG8E16_V }, // 9254 |
28412 | | { PseudoVSSSEG8E16_V_MF4, VSSSEG8E16_V }, // 9255 |
28413 | | { PseudoVSSSEG8E16_V_MF4_MASK, VSSSEG8E16_V }, // 9256 |
28414 | | { PseudoVSSSEG8E32_V_M1, VSSSEG8E32_V }, // 9257 |
28415 | | { PseudoVSSSEG8E32_V_M1_MASK, VSSSEG8E32_V }, // 9258 |
28416 | | { PseudoVSSSEG8E32_V_MF2, VSSSEG8E32_V }, // 9259 |
28417 | | { PseudoVSSSEG8E32_V_MF2_MASK, VSSSEG8E32_V }, // 9260 |
28418 | | { PseudoVSSSEG8E64_V_M1, VSSSEG8E64_V }, // 9261 |
28419 | | { PseudoVSSSEG8E64_V_M1_MASK, VSSSEG8E64_V }, // 9262 |
28420 | | { PseudoVSSSEG8E8_V_M1, VSSSEG8E8_V }, // 9263 |
28421 | | { PseudoVSSSEG8E8_V_M1_MASK, VSSSEG8E8_V }, // 9264 |
28422 | | { PseudoVSSSEG8E8_V_MF2, VSSSEG8E8_V }, // 9265 |
28423 | | { PseudoVSSSEG8E8_V_MF2_MASK, VSSSEG8E8_V }, // 9266 |
28424 | | { PseudoVSSSEG8E8_V_MF4, VSSSEG8E8_V }, // 9267 |
28425 | | { PseudoVSSSEG8E8_V_MF4_MASK, VSSSEG8E8_V }, // 9268 |
28426 | | { PseudoVSSSEG8E8_V_MF8, VSSSEG8E8_V }, // 9269 |
28427 | | { PseudoVSSSEG8E8_V_MF8_MASK, VSSSEG8E8_V }, // 9270 |
28428 | | { PseudoVSSUBU_VV_M1, VSSUBU_VV }, // 9271 |
28429 | | { PseudoVSSUBU_VV_M1_MASK, VSSUBU_VV }, // 9272 |
28430 | | { PseudoVSSUBU_VV_M2, VSSUBU_VV }, // 9273 |
28431 | | { PseudoVSSUBU_VV_M2_MASK, VSSUBU_VV }, // 9274 |
28432 | | { PseudoVSSUBU_VV_M4, VSSUBU_VV }, // 9275 |
28433 | | { PseudoVSSUBU_VV_M4_MASK, VSSUBU_VV }, // 9276 |
28434 | | { PseudoVSSUBU_VV_M8, VSSUBU_VV }, // 9277 |
28435 | | { PseudoVSSUBU_VV_M8_MASK, VSSUBU_VV }, // 9278 |
28436 | | { PseudoVSSUBU_VV_MF2, VSSUBU_VV }, // 9279 |
28437 | | { PseudoVSSUBU_VV_MF2_MASK, VSSUBU_VV }, // 9280 |
28438 | | { PseudoVSSUBU_VV_MF4, VSSUBU_VV }, // 9281 |
28439 | | { PseudoVSSUBU_VV_MF4_MASK, VSSUBU_VV }, // 9282 |
28440 | | { PseudoVSSUBU_VV_MF8, VSSUBU_VV }, // 9283 |
28441 | | { PseudoVSSUBU_VV_MF8_MASK, VSSUBU_VV }, // 9284 |
28442 | | { PseudoVSSUBU_VX_M1, VSSUBU_VX }, // 9285 |
28443 | | { PseudoVSSUBU_VX_M1_MASK, VSSUBU_VX }, // 9286 |
28444 | | { PseudoVSSUBU_VX_M2, VSSUBU_VX }, // 9287 |
28445 | | { PseudoVSSUBU_VX_M2_MASK, VSSUBU_VX }, // 9288 |
28446 | | { PseudoVSSUBU_VX_M4, VSSUBU_VX }, // 9289 |
28447 | | { PseudoVSSUBU_VX_M4_MASK, VSSUBU_VX }, // 9290 |
28448 | | { PseudoVSSUBU_VX_M8, VSSUBU_VX }, // 9291 |
28449 | | { PseudoVSSUBU_VX_M8_MASK, VSSUBU_VX }, // 9292 |
28450 | | { PseudoVSSUBU_VX_MF2, VSSUBU_VX }, // 9293 |
28451 | | { PseudoVSSUBU_VX_MF2_MASK, VSSUBU_VX }, // 9294 |
28452 | | { PseudoVSSUBU_VX_MF4, VSSUBU_VX }, // 9295 |
28453 | | { PseudoVSSUBU_VX_MF4_MASK, VSSUBU_VX }, // 9296 |
28454 | | { PseudoVSSUBU_VX_MF8, VSSUBU_VX }, // 9297 |
28455 | | { PseudoVSSUBU_VX_MF8_MASK, VSSUBU_VX }, // 9298 |
28456 | | { PseudoVSSUB_VV_M1, VSSUB_VV }, // 9299 |
28457 | | { PseudoVSSUB_VV_M1_MASK, VSSUB_VV }, // 9300 |
28458 | | { PseudoVSSUB_VV_M2, VSSUB_VV }, // 9301 |
28459 | | { PseudoVSSUB_VV_M2_MASK, VSSUB_VV }, // 9302 |
28460 | | { PseudoVSSUB_VV_M4, VSSUB_VV }, // 9303 |
28461 | | { PseudoVSSUB_VV_M4_MASK, VSSUB_VV }, // 9304 |
28462 | | { PseudoVSSUB_VV_M8, VSSUB_VV }, // 9305 |
28463 | | { PseudoVSSUB_VV_M8_MASK, VSSUB_VV }, // 9306 |
28464 | | { PseudoVSSUB_VV_MF2, VSSUB_VV }, // 9307 |
28465 | | { PseudoVSSUB_VV_MF2_MASK, VSSUB_VV }, // 9308 |
28466 | | { PseudoVSSUB_VV_MF4, VSSUB_VV }, // 9309 |
28467 | | { PseudoVSSUB_VV_MF4_MASK, VSSUB_VV }, // 9310 |
28468 | | { PseudoVSSUB_VV_MF8, VSSUB_VV }, // 9311 |
28469 | | { PseudoVSSUB_VV_MF8_MASK, VSSUB_VV }, // 9312 |
28470 | | { PseudoVSSUB_VX_M1, VSSUB_VX }, // 9313 |
28471 | | { PseudoVSSUB_VX_M1_MASK, VSSUB_VX }, // 9314 |
28472 | | { PseudoVSSUB_VX_M2, VSSUB_VX }, // 9315 |
28473 | | { PseudoVSSUB_VX_M2_MASK, VSSUB_VX }, // 9316 |
28474 | | { PseudoVSSUB_VX_M4, VSSUB_VX }, // 9317 |
28475 | | { PseudoVSSUB_VX_M4_MASK, VSSUB_VX }, // 9318 |
28476 | | { PseudoVSSUB_VX_M8, VSSUB_VX }, // 9319 |
28477 | | { PseudoVSSUB_VX_M8_MASK, VSSUB_VX }, // 9320 |
28478 | | { PseudoVSSUB_VX_MF2, VSSUB_VX }, // 9321 |
28479 | | { PseudoVSSUB_VX_MF2_MASK, VSSUB_VX }, // 9322 |
28480 | | { PseudoVSSUB_VX_MF4, VSSUB_VX }, // 9323 |
28481 | | { PseudoVSSUB_VX_MF4_MASK, VSSUB_VX }, // 9324 |
28482 | | { PseudoVSSUB_VX_MF8, VSSUB_VX }, // 9325 |
28483 | | { PseudoVSSUB_VX_MF8_MASK, VSSUB_VX }, // 9326 |
28484 | | { PseudoVSUB_VV_M1, VSUB_VV }, // 9327 |
28485 | | { PseudoVSUB_VV_M1_MASK, VSUB_VV }, // 9328 |
28486 | | { PseudoVSUB_VV_M2, VSUB_VV }, // 9329 |
28487 | | { PseudoVSUB_VV_M2_MASK, VSUB_VV }, // 9330 |
28488 | | { PseudoVSUB_VV_M4, VSUB_VV }, // 9331 |
28489 | | { PseudoVSUB_VV_M4_MASK, VSUB_VV }, // 9332 |
28490 | | { PseudoVSUB_VV_M8, VSUB_VV }, // 9333 |
28491 | | { PseudoVSUB_VV_M8_MASK, VSUB_VV }, // 9334 |
28492 | | { PseudoVSUB_VV_MF2, VSUB_VV }, // 9335 |
28493 | | { PseudoVSUB_VV_MF2_MASK, VSUB_VV }, // 9336 |
28494 | | { PseudoVSUB_VV_MF4, VSUB_VV }, // 9337 |
28495 | | { PseudoVSUB_VV_MF4_MASK, VSUB_VV }, // 9338 |
28496 | | { PseudoVSUB_VV_MF8, VSUB_VV }, // 9339 |
28497 | | { PseudoVSUB_VV_MF8_MASK, VSUB_VV }, // 9340 |
28498 | | { PseudoVSUB_VX_M1, VSUB_VX }, // 9341 |
28499 | | { PseudoVSUB_VX_M1_MASK, VSUB_VX }, // 9342 |
28500 | | { PseudoVSUB_VX_M2, VSUB_VX }, // 9343 |
28501 | | { PseudoVSUB_VX_M2_MASK, VSUB_VX }, // 9344 |
28502 | | { PseudoVSUB_VX_M4, VSUB_VX }, // 9345 |
28503 | | { PseudoVSUB_VX_M4_MASK, VSUB_VX }, // 9346 |
28504 | | { PseudoVSUB_VX_M8, VSUB_VX }, // 9347 |
28505 | | { PseudoVSUB_VX_M8_MASK, VSUB_VX }, // 9348 |
28506 | | { PseudoVSUB_VX_MF2, VSUB_VX }, // 9349 |
28507 | | { PseudoVSUB_VX_MF2_MASK, VSUB_VX }, // 9350 |
28508 | | { PseudoVSUB_VX_MF4, VSUB_VX }, // 9351 |
28509 | | { PseudoVSUB_VX_MF4_MASK, VSUB_VX }, // 9352 |
28510 | | { PseudoVSUB_VX_MF8, VSUB_VX }, // 9353 |
28511 | | { PseudoVSUB_VX_MF8_MASK, VSUB_VX }, // 9354 |
28512 | | { PseudoVSUXEI16_V_M1_M1, VSUXEI16_V }, // 9355 |
28513 | | { PseudoVSUXEI16_V_M1_M1_MASK, VSUXEI16_V }, // 9356 |
28514 | | { PseudoVSUXEI16_V_M1_M2, VSUXEI16_V }, // 9357 |
28515 | | { PseudoVSUXEI16_V_M1_M2_MASK, VSUXEI16_V }, // 9358 |
28516 | | { PseudoVSUXEI16_V_M1_M4, VSUXEI16_V }, // 9359 |
28517 | | { PseudoVSUXEI16_V_M1_M4_MASK, VSUXEI16_V }, // 9360 |
28518 | | { PseudoVSUXEI16_V_M1_MF2, VSUXEI16_V }, // 9361 |
28519 | | { PseudoVSUXEI16_V_M1_MF2_MASK, VSUXEI16_V }, // 9362 |
28520 | | { PseudoVSUXEI16_V_M2_M1, VSUXEI16_V }, // 9363 |
28521 | | { PseudoVSUXEI16_V_M2_M1_MASK, VSUXEI16_V }, // 9364 |
28522 | | { PseudoVSUXEI16_V_M2_M2, VSUXEI16_V }, // 9365 |
28523 | | { PseudoVSUXEI16_V_M2_M2_MASK, VSUXEI16_V }, // 9366 |
28524 | | { PseudoVSUXEI16_V_M2_M4, VSUXEI16_V }, // 9367 |
28525 | | { PseudoVSUXEI16_V_M2_M4_MASK, VSUXEI16_V }, // 9368 |
28526 | | { PseudoVSUXEI16_V_M2_M8, VSUXEI16_V }, // 9369 |
28527 | | { PseudoVSUXEI16_V_M2_M8_MASK, VSUXEI16_V }, // 9370 |
28528 | | { PseudoVSUXEI16_V_M4_M2, VSUXEI16_V }, // 9371 |
28529 | | { PseudoVSUXEI16_V_M4_M2_MASK, VSUXEI16_V }, // 9372 |
28530 | | { PseudoVSUXEI16_V_M4_M4, VSUXEI16_V }, // 9373 |
28531 | | { PseudoVSUXEI16_V_M4_M4_MASK, VSUXEI16_V }, // 9374 |
28532 | | { PseudoVSUXEI16_V_M4_M8, VSUXEI16_V }, // 9375 |
28533 | | { PseudoVSUXEI16_V_M4_M8_MASK, VSUXEI16_V }, // 9376 |
28534 | | { PseudoVSUXEI16_V_M8_M4, VSUXEI16_V }, // 9377 |
28535 | | { PseudoVSUXEI16_V_M8_M4_MASK, VSUXEI16_V }, // 9378 |
28536 | | { PseudoVSUXEI16_V_M8_M8, VSUXEI16_V }, // 9379 |
28537 | | { PseudoVSUXEI16_V_M8_M8_MASK, VSUXEI16_V }, // 9380 |
28538 | | { PseudoVSUXEI16_V_MF2_M1, VSUXEI16_V }, // 9381 |
28539 | | { PseudoVSUXEI16_V_MF2_M1_MASK, VSUXEI16_V }, // 9382 |
28540 | | { PseudoVSUXEI16_V_MF2_M2, VSUXEI16_V }, // 9383 |
28541 | | { PseudoVSUXEI16_V_MF2_M2_MASK, VSUXEI16_V }, // 9384 |
28542 | | { PseudoVSUXEI16_V_MF2_MF2, VSUXEI16_V }, // 9385 |
28543 | | { PseudoVSUXEI16_V_MF2_MF2_MASK, VSUXEI16_V }, // 9386 |
28544 | | { PseudoVSUXEI16_V_MF2_MF4, VSUXEI16_V }, // 9387 |
28545 | | { PseudoVSUXEI16_V_MF2_MF4_MASK, VSUXEI16_V }, // 9388 |
28546 | | { PseudoVSUXEI16_V_MF4_M1, VSUXEI16_V }, // 9389 |
28547 | | { PseudoVSUXEI16_V_MF4_M1_MASK, VSUXEI16_V }, // 9390 |
28548 | | { PseudoVSUXEI16_V_MF4_MF2, VSUXEI16_V }, // 9391 |
28549 | | { PseudoVSUXEI16_V_MF4_MF2_MASK, VSUXEI16_V }, // 9392 |
28550 | | { PseudoVSUXEI16_V_MF4_MF4, VSUXEI16_V }, // 9393 |
28551 | | { PseudoVSUXEI16_V_MF4_MF4_MASK, VSUXEI16_V }, // 9394 |
28552 | | { PseudoVSUXEI16_V_MF4_MF8, VSUXEI16_V }, // 9395 |
28553 | | { PseudoVSUXEI16_V_MF4_MF8_MASK, VSUXEI16_V }, // 9396 |
28554 | | { PseudoVSUXEI32_V_M1_M1, VSUXEI32_V }, // 9397 |
28555 | | { PseudoVSUXEI32_V_M1_M1_MASK, VSUXEI32_V }, // 9398 |
28556 | | { PseudoVSUXEI32_V_M1_M2, VSUXEI32_V }, // 9399 |
28557 | | { PseudoVSUXEI32_V_M1_M2_MASK, VSUXEI32_V }, // 9400 |
28558 | | { PseudoVSUXEI32_V_M1_MF2, VSUXEI32_V }, // 9401 |
28559 | | { PseudoVSUXEI32_V_M1_MF2_MASK, VSUXEI32_V }, // 9402 |
28560 | | { PseudoVSUXEI32_V_M1_MF4, VSUXEI32_V }, // 9403 |
28561 | | { PseudoVSUXEI32_V_M1_MF4_MASK, VSUXEI32_V }, // 9404 |
28562 | | { PseudoVSUXEI32_V_M2_M1, VSUXEI32_V }, // 9405 |
28563 | | { PseudoVSUXEI32_V_M2_M1_MASK, VSUXEI32_V }, // 9406 |
28564 | | { PseudoVSUXEI32_V_M2_M2, VSUXEI32_V }, // 9407 |
28565 | | { PseudoVSUXEI32_V_M2_M2_MASK, VSUXEI32_V }, // 9408 |
28566 | | { PseudoVSUXEI32_V_M2_M4, VSUXEI32_V }, // 9409 |
28567 | | { PseudoVSUXEI32_V_M2_M4_MASK, VSUXEI32_V }, // 9410 |
28568 | | { PseudoVSUXEI32_V_M2_MF2, VSUXEI32_V }, // 9411 |
28569 | | { PseudoVSUXEI32_V_M2_MF2_MASK, VSUXEI32_V }, // 9412 |
28570 | | { PseudoVSUXEI32_V_M4_M1, VSUXEI32_V }, // 9413 |
28571 | | { PseudoVSUXEI32_V_M4_M1_MASK, VSUXEI32_V }, // 9414 |
28572 | | { PseudoVSUXEI32_V_M4_M2, VSUXEI32_V }, // 9415 |
28573 | | { PseudoVSUXEI32_V_M4_M2_MASK, VSUXEI32_V }, // 9416 |
28574 | | { PseudoVSUXEI32_V_M4_M4, VSUXEI32_V }, // 9417 |
28575 | | { PseudoVSUXEI32_V_M4_M4_MASK, VSUXEI32_V }, // 9418 |
28576 | | { PseudoVSUXEI32_V_M4_M8, VSUXEI32_V }, // 9419 |
28577 | | { PseudoVSUXEI32_V_M4_M8_MASK, VSUXEI32_V }, // 9420 |
28578 | | { PseudoVSUXEI32_V_M8_M2, VSUXEI32_V }, // 9421 |
28579 | | { PseudoVSUXEI32_V_M8_M2_MASK, VSUXEI32_V }, // 9422 |
28580 | | { PseudoVSUXEI32_V_M8_M4, VSUXEI32_V }, // 9423 |
28581 | | { PseudoVSUXEI32_V_M8_M4_MASK, VSUXEI32_V }, // 9424 |
28582 | | { PseudoVSUXEI32_V_M8_M8, VSUXEI32_V }, // 9425 |
28583 | | { PseudoVSUXEI32_V_M8_M8_MASK, VSUXEI32_V }, // 9426 |
28584 | | { PseudoVSUXEI32_V_MF2_M1, VSUXEI32_V }, // 9427 |
28585 | | { PseudoVSUXEI32_V_MF2_M1_MASK, VSUXEI32_V }, // 9428 |
28586 | | { PseudoVSUXEI32_V_MF2_MF2, VSUXEI32_V }, // 9429 |
28587 | | { PseudoVSUXEI32_V_MF2_MF2_MASK, VSUXEI32_V }, // 9430 |
28588 | | { PseudoVSUXEI32_V_MF2_MF4, VSUXEI32_V }, // 9431 |
28589 | | { PseudoVSUXEI32_V_MF2_MF4_MASK, VSUXEI32_V }, // 9432 |
28590 | | { PseudoVSUXEI32_V_MF2_MF8, VSUXEI32_V }, // 9433 |
28591 | | { PseudoVSUXEI32_V_MF2_MF8_MASK, VSUXEI32_V }, // 9434 |
28592 | | { PseudoVSUXEI64_V_M1_M1, VSUXEI64_V }, // 9435 |
28593 | | { PseudoVSUXEI64_V_M1_M1_MASK, VSUXEI64_V }, // 9436 |
28594 | | { PseudoVSUXEI64_V_M1_MF2, VSUXEI64_V }, // 9437 |
28595 | | { PseudoVSUXEI64_V_M1_MF2_MASK, VSUXEI64_V }, // 9438 |
28596 | | { PseudoVSUXEI64_V_M1_MF4, VSUXEI64_V }, // 9439 |
28597 | | { PseudoVSUXEI64_V_M1_MF4_MASK, VSUXEI64_V }, // 9440 |
28598 | | { PseudoVSUXEI64_V_M1_MF8, VSUXEI64_V }, // 9441 |
28599 | | { PseudoVSUXEI64_V_M1_MF8_MASK, VSUXEI64_V }, // 9442 |
28600 | | { PseudoVSUXEI64_V_M2_M1, VSUXEI64_V }, // 9443 |
28601 | | { PseudoVSUXEI64_V_M2_M1_MASK, VSUXEI64_V }, // 9444 |
28602 | | { PseudoVSUXEI64_V_M2_M2, VSUXEI64_V }, // 9445 |
28603 | | { PseudoVSUXEI64_V_M2_M2_MASK, VSUXEI64_V }, // 9446 |
28604 | | { PseudoVSUXEI64_V_M2_MF2, VSUXEI64_V }, // 9447 |
28605 | | { PseudoVSUXEI64_V_M2_MF2_MASK, VSUXEI64_V }, // 9448 |
28606 | | { PseudoVSUXEI64_V_M2_MF4, VSUXEI64_V }, // 9449 |
28607 | | { PseudoVSUXEI64_V_M2_MF4_MASK, VSUXEI64_V }, // 9450 |
28608 | | { PseudoVSUXEI64_V_M4_M1, VSUXEI64_V }, // 9451 |
28609 | | { PseudoVSUXEI64_V_M4_M1_MASK, VSUXEI64_V }, // 9452 |
28610 | | { PseudoVSUXEI64_V_M4_M2, VSUXEI64_V }, // 9453 |
28611 | | { PseudoVSUXEI64_V_M4_M2_MASK, VSUXEI64_V }, // 9454 |
28612 | | { PseudoVSUXEI64_V_M4_M4, VSUXEI64_V }, // 9455 |
28613 | | { PseudoVSUXEI64_V_M4_M4_MASK, VSUXEI64_V }, // 9456 |
28614 | | { PseudoVSUXEI64_V_M4_MF2, VSUXEI64_V }, // 9457 |
28615 | | { PseudoVSUXEI64_V_M4_MF2_MASK, VSUXEI64_V }, // 9458 |
28616 | | { PseudoVSUXEI64_V_M8_M1, VSUXEI64_V }, // 9459 |
28617 | | { PseudoVSUXEI64_V_M8_M1_MASK, VSUXEI64_V }, // 9460 |
28618 | | { PseudoVSUXEI64_V_M8_M2, VSUXEI64_V }, // 9461 |
28619 | | { PseudoVSUXEI64_V_M8_M2_MASK, VSUXEI64_V }, // 9462 |
28620 | | { PseudoVSUXEI64_V_M8_M4, VSUXEI64_V }, // 9463 |
28621 | | { PseudoVSUXEI64_V_M8_M4_MASK, VSUXEI64_V }, // 9464 |
28622 | | { PseudoVSUXEI64_V_M8_M8, VSUXEI64_V }, // 9465 |
28623 | | { PseudoVSUXEI64_V_M8_M8_MASK, VSUXEI64_V }, // 9466 |
28624 | | { PseudoVSUXEI8_V_M1_M1, VSUXEI8_V }, // 9467 |
28625 | | { PseudoVSUXEI8_V_M1_M1_MASK, VSUXEI8_V }, // 9468 |
28626 | | { PseudoVSUXEI8_V_M1_M2, VSUXEI8_V }, // 9469 |
28627 | | { PseudoVSUXEI8_V_M1_M2_MASK, VSUXEI8_V }, // 9470 |
28628 | | { PseudoVSUXEI8_V_M1_M4, VSUXEI8_V }, // 9471 |
28629 | | { PseudoVSUXEI8_V_M1_M4_MASK, VSUXEI8_V }, // 9472 |
28630 | | { PseudoVSUXEI8_V_M1_M8, VSUXEI8_V }, // 9473 |
28631 | | { PseudoVSUXEI8_V_M1_M8_MASK, VSUXEI8_V }, // 9474 |
28632 | | { PseudoVSUXEI8_V_M2_M2, VSUXEI8_V }, // 9475 |
28633 | | { PseudoVSUXEI8_V_M2_M2_MASK, VSUXEI8_V }, // 9476 |
28634 | | { PseudoVSUXEI8_V_M2_M4, VSUXEI8_V }, // 9477 |
28635 | | { PseudoVSUXEI8_V_M2_M4_MASK, VSUXEI8_V }, // 9478 |
28636 | | { PseudoVSUXEI8_V_M2_M8, VSUXEI8_V }, // 9479 |
28637 | | { PseudoVSUXEI8_V_M2_M8_MASK, VSUXEI8_V }, // 9480 |
28638 | | { PseudoVSUXEI8_V_M4_M4, VSUXEI8_V }, // 9481 |
28639 | | { PseudoVSUXEI8_V_M4_M4_MASK, VSUXEI8_V }, // 9482 |
28640 | | { PseudoVSUXEI8_V_M4_M8, VSUXEI8_V }, // 9483 |
28641 | | { PseudoVSUXEI8_V_M4_M8_MASK, VSUXEI8_V }, // 9484 |
28642 | | { PseudoVSUXEI8_V_M8_M8, VSUXEI8_V }, // 9485 |
28643 | | { PseudoVSUXEI8_V_M8_M8_MASK, VSUXEI8_V }, // 9486 |
28644 | | { PseudoVSUXEI8_V_MF2_M1, VSUXEI8_V }, // 9487 |
28645 | | { PseudoVSUXEI8_V_MF2_M1_MASK, VSUXEI8_V }, // 9488 |
28646 | | { PseudoVSUXEI8_V_MF2_M2, VSUXEI8_V }, // 9489 |
28647 | | { PseudoVSUXEI8_V_MF2_M2_MASK, VSUXEI8_V }, // 9490 |
28648 | | { PseudoVSUXEI8_V_MF2_M4, VSUXEI8_V }, // 9491 |
28649 | | { PseudoVSUXEI8_V_MF2_M4_MASK, VSUXEI8_V }, // 9492 |
28650 | | { PseudoVSUXEI8_V_MF2_MF2, VSUXEI8_V }, // 9493 |
28651 | | { PseudoVSUXEI8_V_MF2_MF2_MASK, VSUXEI8_V }, // 9494 |
28652 | | { PseudoVSUXEI8_V_MF4_M1, VSUXEI8_V }, // 9495 |
28653 | | { PseudoVSUXEI8_V_MF4_M1_MASK, VSUXEI8_V }, // 9496 |
28654 | | { PseudoVSUXEI8_V_MF4_M2, VSUXEI8_V }, // 9497 |
28655 | | { PseudoVSUXEI8_V_MF4_M2_MASK, VSUXEI8_V }, // 9498 |
28656 | | { PseudoVSUXEI8_V_MF4_MF2, VSUXEI8_V }, // 9499 |
28657 | | { PseudoVSUXEI8_V_MF4_MF2_MASK, VSUXEI8_V }, // 9500 |
28658 | | { PseudoVSUXEI8_V_MF4_MF4, VSUXEI8_V }, // 9501 |
28659 | | { PseudoVSUXEI8_V_MF4_MF4_MASK, VSUXEI8_V }, // 9502 |
28660 | | { PseudoVSUXEI8_V_MF8_M1, VSUXEI8_V }, // 9503 |
28661 | | { PseudoVSUXEI8_V_MF8_M1_MASK, VSUXEI8_V }, // 9504 |
28662 | | { PseudoVSUXEI8_V_MF8_MF2, VSUXEI8_V }, // 9505 |
28663 | | { PseudoVSUXEI8_V_MF8_MF2_MASK, VSUXEI8_V }, // 9506 |
28664 | | { PseudoVSUXEI8_V_MF8_MF4, VSUXEI8_V }, // 9507 |
28665 | | { PseudoVSUXEI8_V_MF8_MF4_MASK, VSUXEI8_V }, // 9508 |
28666 | | { PseudoVSUXEI8_V_MF8_MF8, VSUXEI8_V }, // 9509 |
28667 | | { PseudoVSUXEI8_V_MF8_MF8_MASK, VSUXEI8_V }, // 9510 |
28668 | | { PseudoVSUXSEG2EI16_V_M1_M1, VSUXSEG2EI16_V }, // 9511 |
28669 | | { PseudoVSUXSEG2EI16_V_M1_M1_MASK, VSUXSEG2EI16_V }, // 9512 |
28670 | | { PseudoVSUXSEG2EI16_V_M1_M2, VSUXSEG2EI16_V }, // 9513 |
28671 | | { PseudoVSUXSEG2EI16_V_M1_M2_MASK, VSUXSEG2EI16_V }, // 9514 |
28672 | | { PseudoVSUXSEG2EI16_V_M1_M4, VSUXSEG2EI16_V }, // 9515 |
28673 | | { PseudoVSUXSEG2EI16_V_M1_M4_MASK, VSUXSEG2EI16_V }, // 9516 |
28674 | | { PseudoVSUXSEG2EI16_V_M1_MF2, VSUXSEG2EI16_V }, // 9517 |
28675 | | { PseudoVSUXSEG2EI16_V_M1_MF2_MASK, VSUXSEG2EI16_V }, // 9518 |
28676 | | { PseudoVSUXSEG2EI16_V_M2_M1, VSUXSEG2EI16_V }, // 9519 |
28677 | | { PseudoVSUXSEG2EI16_V_M2_M1_MASK, VSUXSEG2EI16_V }, // 9520 |
28678 | | { PseudoVSUXSEG2EI16_V_M2_M2, VSUXSEG2EI16_V }, // 9521 |
28679 | | { PseudoVSUXSEG2EI16_V_M2_M2_MASK, VSUXSEG2EI16_V }, // 9522 |
28680 | | { PseudoVSUXSEG2EI16_V_M2_M4, VSUXSEG2EI16_V }, // 9523 |
28681 | | { PseudoVSUXSEG2EI16_V_M2_M4_MASK, VSUXSEG2EI16_V }, // 9524 |
28682 | | { PseudoVSUXSEG2EI16_V_M4_M2, VSUXSEG2EI16_V }, // 9525 |
28683 | | { PseudoVSUXSEG2EI16_V_M4_M2_MASK, VSUXSEG2EI16_V }, // 9526 |
28684 | | { PseudoVSUXSEG2EI16_V_M4_M4, VSUXSEG2EI16_V }, // 9527 |
28685 | | { PseudoVSUXSEG2EI16_V_M4_M4_MASK, VSUXSEG2EI16_V }, // 9528 |
28686 | | { PseudoVSUXSEG2EI16_V_M8_M4, VSUXSEG2EI16_V }, // 9529 |
28687 | | { PseudoVSUXSEG2EI16_V_M8_M4_MASK, VSUXSEG2EI16_V }, // 9530 |
28688 | | { PseudoVSUXSEG2EI16_V_MF2_M1, VSUXSEG2EI16_V }, // 9531 |
28689 | | { PseudoVSUXSEG2EI16_V_MF2_M1_MASK, VSUXSEG2EI16_V }, // 9532 |
28690 | | { PseudoVSUXSEG2EI16_V_MF2_M2, VSUXSEG2EI16_V }, // 9533 |
28691 | | { PseudoVSUXSEG2EI16_V_MF2_M2_MASK, VSUXSEG2EI16_V }, // 9534 |
28692 | | { PseudoVSUXSEG2EI16_V_MF2_MF2, VSUXSEG2EI16_V }, // 9535 |
28693 | | { PseudoVSUXSEG2EI16_V_MF2_MF2_MASK, VSUXSEG2EI16_V }, // 9536 |
28694 | | { PseudoVSUXSEG2EI16_V_MF2_MF4, VSUXSEG2EI16_V }, // 9537 |
28695 | | { PseudoVSUXSEG2EI16_V_MF2_MF4_MASK, VSUXSEG2EI16_V }, // 9538 |
28696 | | { PseudoVSUXSEG2EI16_V_MF4_M1, VSUXSEG2EI16_V }, // 9539 |
28697 | | { PseudoVSUXSEG2EI16_V_MF4_M1_MASK, VSUXSEG2EI16_V }, // 9540 |
28698 | | { PseudoVSUXSEG2EI16_V_MF4_MF2, VSUXSEG2EI16_V }, // 9541 |
28699 | | { PseudoVSUXSEG2EI16_V_MF4_MF2_MASK, VSUXSEG2EI16_V }, // 9542 |
28700 | | { PseudoVSUXSEG2EI16_V_MF4_MF4, VSUXSEG2EI16_V }, // 9543 |
28701 | | { PseudoVSUXSEG2EI16_V_MF4_MF4_MASK, VSUXSEG2EI16_V }, // 9544 |
28702 | | { PseudoVSUXSEG2EI16_V_MF4_MF8, VSUXSEG2EI16_V }, // 9545 |
28703 | | { PseudoVSUXSEG2EI16_V_MF4_MF8_MASK, VSUXSEG2EI16_V }, // 9546 |
28704 | | { PseudoVSUXSEG2EI32_V_M1_M1, VSUXSEG2EI32_V }, // 9547 |
28705 | | { PseudoVSUXSEG2EI32_V_M1_M1_MASK, VSUXSEG2EI32_V }, // 9548 |
28706 | | { PseudoVSUXSEG2EI32_V_M1_M2, VSUXSEG2EI32_V }, // 9549 |
28707 | | { PseudoVSUXSEG2EI32_V_M1_M2_MASK, VSUXSEG2EI32_V }, // 9550 |
28708 | | { PseudoVSUXSEG2EI32_V_M1_MF2, VSUXSEG2EI32_V }, // 9551 |
28709 | | { PseudoVSUXSEG2EI32_V_M1_MF2_MASK, VSUXSEG2EI32_V }, // 9552 |
28710 | | { PseudoVSUXSEG2EI32_V_M1_MF4, VSUXSEG2EI32_V }, // 9553 |
28711 | | { PseudoVSUXSEG2EI32_V_M1_MF4_MASK, VSUXSEG2EI32_V }, // 9554 |
28712 | | { PseudoVSUXSEG2EI32_V_M2_M1, VSUXSEG2EI32_V }, // 9555 |
28713 | | { PseudoVSUXSEG2EI32_V_M2_M1_MASK, VSUXSEG2EI32_V }, // 9556 |
28714 | | { PseudoVSUXSEG2EI32_V_M2_M2, VSUXSEG2EI32_V }, // 9557 |
28715 | | { PseudoVSUXSEG2EI32_V_M2_M2_MASK, VSUXSEG2EI32_V }, // 9558 |
28716 | | { PseudoVSUXSEG2EI32_V_M2_M4, VSUXSEG2EI32_V }, // 9559 |
28717 | | { PseudoVSUXSEG2EI32_V_M2_M4_MASK, VSUXSEG2EI32_V }, // 9560 |
28718 | | { PseudoVSUXSEG2EI32_V_M2_MF2, VSUXSEG2EI32_V }, // 9561 |
28719 | | { PseudoVSUXSEG2EI32_V_M2_MF2_MASK, VSUXSEG2EI32_V }, // 9562 |
28720 | | { PseudoVSUXSEG2EI32_V_M4_M1, VSUXSEG2EI32_V }, // 9563 |
28721 | | { PseudoVSUXSEG2EI32_V_M4_M1_MASK, VSUXSEG2EI32_V }, // 9564 |
28722 | | { PseudoVSUXSEG2EI32_V_M4_M2, VSUXSEG2EI32_V }, // 9565 |
28723 | | { PseudoVSUXSEG2EI32_V_M4_M2_MASK, VSUXSEG2EI32_V }, // 9566 |
28724 | | { PseudoVSUXSEG2EI32_V_M4_M4, VSUXSEG2EI32_V }, // 9567 |
28725 | | { PseudoVSUXSEG2EI32_V_M4_M4_MASK, VSUXSEG2EI32_V }, // 9568 |
28726 | | { PseudoVSUXSEG2EI32_V_M8_M2, VSUXSEG2EI32_V }, // 9569 |
28727 | | { PseudoVSUXSEG2EI32_V_M8_M2_MASK, VSUXSEG2EI32_V }, // 9570 |
28728 | | { PseudoVSUXSEG2EI32_V_M8_M4, VSUXSEG2EI32_V }, // 9571 |
28729 | | { PseudoVSUXSEG2EI32_V_M8_M4_MASK, VSUXSEG2EI32_V }, // 9572 |
28730 | | { PseudoVSUXSEG2EI32_V_MF2_M1, VSUXSEG2EI32_V }, // 9573 |
28731 | | { PseudoVSUXSEG2EI32_V_MF2_M1_MASK, VSUXSEG2EI32_V }, // 9574 |
28732 | | { PseudoVSUXSEG2EI32_V_MF2_MF2, VSUXSEG2EI32_V }, // 9575 |
28733 | | { PseudoVSUXSEG2EI32_V_MF2_MF2_MASK, VSUXSEG2EI32_V }, // 9576 |
28734 | | { PseudoVSUXSEG2EI32_V_MF2_MF4, VSUXSEG2EI32_V }, // 9577 |
28735 | | { PseudoVSUXSEG2EI32_V_MF2_MF4_MASK, VSUXSEG2EI32_V }, // 9578 |
28736 | | { PseudoVSUXSEG2EI32_V_MF2_MF8, VSUXSEG2EI32_V }, // 9579 |
28737 | | { PseudoVSUXSEG2EI32_V_MF2_MF8_MASK, VSUXSEG2EI32_V }, // 9580 |
28738 | | { PseudoVSUXSEG2EI64_V_M1_M1, VSUXSEG2EI64_V }, // 9581 |
28739 | | { PseudoVSUXSEG2EI64_V_M1_M1_MASK, VSUXSEG2EI64_V }, // 9582 |
28740 | | { PseudoVSUXSEG2EI64_V_M1_MF2, VSUXSEG2EI64_V }, // 9583 |
28741 | | { PseudoVSUXSEG2EI64_V_M1_MF2_MASK, VSUXSEG2EI64_V }, // 9584 |
28742 | | { PseudoVSUXSEG2EI64_V_M1_MF4, VSUXSEG2EI64_V }, // 9585 |
28743 | | { PseudoVSUXSEG2EI64_V_M1_MF4_MASK, VSUXSEG2EI64_V }, // 9586 |
28744 | | { PseudoVSUXSEG2EI64_V_M1_MF8, VSUXSEG2EI64_V }, // 9587 |
28745 | | { PseudoVSUXSEG2EI64_V_M1_MF8_MASK, VSUXSEG2EI64_V }, // 9588 |
28746 | | { PseudoVSUXSEG2EI64_V_M2_M1, VSUXSEG2EI64_V }, // 9589 |
28747 | | { PseudoVSUXSEG2EI64_V_M2_M1_MASK, VSUXSEG2EI64_V }, // 9590 |
28748 | | { PseudoVSUXSEG2EI64_V_M2_M2, VSUXSEG2EI64_V }, // 9591 |
28749 | | { PseudoVSUXSEG2EI64_V_M2_M2_MASK, VSUXSEG2EI64_V }, // 9592 |
28750 | | { PseudoVSUXSEG2EI64_V_M2_MF2, VSUXSEG2EI64_V }, // 9593 |
28751 | | { PseudoVSUXSEG2EI64_V_M2_MF2_MASK, VSUXSEG2EI64_V }, // 9594 |
28752 | | { PseudoVSUXSEG2EI64_V_M2_MF4, VSUXSEG2EI64_V }, // 9595 |
28753 | | { PseudoVSUXSEG2EI64_V_M2_MF4_MASK, VSUXSEG2EI64_V }, // 9596 |
28754 | | { PseudoVSUXSEG2EI64_V_M4_M1, VSUXSEG2EI64_V }, // 9597 |
28755 | | { PseudoVSUXSEG2EI64_V_M4_M1_MASK, VSUXSEG2EI64_V }, // 9598 |
28756 | | { PseudoVSUXSEG2EI64_V_M4_M2, VSUXSEG2EI64_V }, // 9599 |
28757 | | { PseudoVSUXSEG2EI64_V_M4_M2_MASK, VSUXSEG2EI64_V }, // 9600 |
28758 | | { PseudoVSUXSEG2EI64_V_M4_M4, VSUXSEG2EI64_V }, // 9601 |
28759 | | { PseudoVSUXSEG2EI64_V_M4_M4_MASK, VSUXSEG2EI64_V }, // 9602 |
28760 | | { PseudoVSUXSEG2EI64_V_M4_MF2, VSUXSEG2EI64_V }, // 9603 |
28761 | | { PseudoVSUXSEG2EI64_V_M4_MF2_MASK, VSUXSEG2EI64_V }, // 9604 |
28762 | | { PseudoVSUXSEG2EI64_V_M8_M1, VSUXSEG2EI64_V }, // 9605 |
28763 | | { PseudoVSUXSEG2EI64_V_M8_M1_MASK, VSUXSEG2EI64_V }, // 9606 |
28764 | | { PseudoVSUXSEG2EI64_V_M8_M2, VSUXSEG2EI64_V }, // 9607 |
28765 | | { PseudoVSUXSEG2EI64_V_M8_M2_MASK, VSUXSEG2EI64_V }, // 9608 |
28766 | | { PseudoVSUXSEG2EI64_V_M8_M4, VSUXSEG2EI64_V }, // 9609 |
28767 | | { PseudoVSUXSEG2EI64_V_M8_M4_MASK, VSUXSEG2EI64_V }, // 9610 |
28768 | | { PseudoVSUXSEG2EI8_V_M1_M1, VSUXSEG2EI8_V }, // 9611 |
28769 | | { PseudoVSUXSEG2EI8_V_M1_M1_MASK, VSUXSEG2EI8_V }, // 9612 |
28770 | | { PseudoVSUXSEG2EI8_V_M1_M2, VSUXSEG2EI8_V }, // 9613 |
28771 | | { PseudoVSUXSEG2EI8_V_M1_M2_MASK, VSUXSEG2EI8_V }, // 9614 |
28772 | | { PseudoVSUXSEG2EI8_V_M1_M4, VSUXSEG2EI8_V }, // 9615 |
28773 | | { PseudoVSUXSEG2EI8_V_M1_M4_MASK, VSUXSEG2EI8_V }, // 9616 |
28774 | | { PseudoVSUXSEG2EI8_V_M2_M2, VSUXSEG2EI8_V }, // 9617 |
28775 | | { PseudoVSUXSEG2EI8_V_M2_M2_MASK, VSUXSEG2EI8_V }, // 9618 |
28776 | | { PseudoVSUXSEG2EI8_V_M2_M4, VSUXSEG2EI8_V }, // 9619 |
28777 | | { PseudoVSUXSEG2EI8_V_M2_M4_MASK, VSUXSEG2EI8_V }, // 9620 |
28778 | | { PseudoVSUXSEG2EI8_V_M4_M4, VSUXSEG2EI8_V }, // 9621 |
28779 | | { PseudoVSUXSEG2EI8_V_M4_M4_MASK, VSUXSEG2EI8_V }, // 9622 |
28780 | | { PseudoVSUXSEG2EI8_V_MF2_M1, VSUXSEG2EI8_V }, // 9623 |
28781 | | { PseudoVSUXSEG2EI8_V_MF2_M1_MASK, VSUXSEG2EI8_V }, // 9624 |
28782 | | { PseudoVSUXSEG2EI8_V_MF2_M2, VSUXSEG2EI8_V }, // 9625 |
28783 | | { PseudoVSUXSEG2EI8_V_MF2_M2_MASK, VSUXSEG2EI8_V }, // 9626 |
28784 | | { PseudoVSUXSEG2EI8_V_MF2_M4, VSUXSEG2EI8_V }, // 9627 |
28785 | | { PseudoVSUXSEG2EI8_V_MF2_M4_MASK, VSUXSEG2EI8_V }, // 9628 |
28786 | | { PseudoVSUXSEG2EI8_V_MF2_MF2, VSUXSEG2EI8_V }, // 9629 |
28787 | | { PseudoVSUXSEG2EI8_V_MF2_MF2_MASK, VSUXSEG2EI8_V }, // 9630 |
28788 | | { PseudoVSUXSEG2EI8_V_MF4_M1, VSUXSEG2EI8_V }, // 9631 |
28789 | | { PseudoVSUXSEG2EI8_V_MF4_M1_MASK, VSUXSEG2EI8_V }, // 9632 |
28790 | | { PseudoVSUXSEG2EI8_V_MF4_M2, VSUXSEG2EI8_V }, // 9633 |
28791 | | { PseudoVSUXSEG2EI8_V_MF4_M2_MASK, VSUXSEG2EI8_V }, // 9634 |
28792 | | { PseudoVSUXSEG2EI8_V_MF4_MF2, VSUXSEG2EI8_V }, // 9635 |
28793 | | { PseudoVSUXSEG2EI8_V_MF4_MF2_MASK, VSUXSEG2EI8_V }, // 9636 |
28794 | | { PseudoVSUXSEG2EI8_V_MF4_MF4, VSUXSEG2EI8_V }, // 9637 |
28795 | | { PseudoVSUXSEG2EI8_V_MF4_MF4_MASK, VSUXSEG2EI8_V }, // 9638 |
28796 | | { PseudoVSUXSEG2EI8_V_MF8_M1, VSUXSEG2EI8_V }, // 9639 |
28797 | | { PseudoVSUXSEG2EI8_V_MF8_M1_MASK, VSUXSEG2EI8_V }, // 9640 |
28798 | | { PseudoVSUXSEG2EI8_V_MF8_MF2, VSUXSEG2EI8_V }, // 9641 |
28799 | | { PseudoVSUXSEG2EI8_V_MF8_MF2_MASK, VSUXSEG2EI8_V }, // 9642 |
28800 | | { PseudoVSUXSEG2EI8_V_MF8_MF4, VSUXSEG2EI8_V }, // 9643 |
28801 | | { PseudoVSUXSEG2EI8_V_MF8_MF4_MASK, VSUXSEG2EI8_V }, // 9644 |
28802 | | { PseudoVSUXSEG2EI8_V_MF8_MF8, VSUXSEG2EI8_V }, // 9645 |
28803 | | { PseudoVSUXSEG2EI8_V_MF8_MF8_MASK, VSUXSEG2EI8_V }, // 9646 |
28804 | | { PseudoVSUXSEG3EI16_V_M1_M1, VSUXSEG3EI16_V }, // 9647 |
28805 | | { PseudoVSUXSEG3EI16_V_M1_M1_MASK, VSUXSEG3EI16_V }, // 9648 |
28806 | | { PseudoVSUXSEG3EI16_V_M1_M2, VSUXSEG3EI16_V }, // 9649 |
28807 | | { PseudoVSUXSEG3EI16_V_M1_M2_MASK, VSUXSEG3EI16_V }, // 9650 |
28808 | | { PseudoVSUXSEG3EI16_V_M1_MF2, VSUXSEG3EI16_V }, // 9651 |
28809 | | { PseudoVSUXSEG3EI16_V_M1_MF2_MASK, VSUXSEG3EI16_V }, // 9652 |
28810 | | { PseudoVSUXSEG3EI16_V_M2_M1, VSUXSEG3EI16_V }, // 9653 |
28811 | | { PseudoVSUXSEG3EI16_V_M2_M1_MASK, VSUXSEG3EI16_V }, // 9654 |
28812 | | { PseudoVSUXSEG3EI16_V_M2_M2, VSUXSEG3EI16_V }, // 9655 |
28813 | | { PseudoVSUXSEG3EI16_V_M2_M2_MASK, VSUXSEG3EI16_V }, // 9656 |
28814 | | { PseudoVSUXSEG3EI16_V_M4_M2, VSUXSEG3EI16_V }, // 9657 |
28815 | | { PseudoVSUXSEG3EI16_V_M4_M2_MASK, VSUXSEG3EI16_V }, // 9658 |
28816 | | { PseudoVSUXSEG3EI16_V_MF2_M1, VSUXSEG3EI16_V }, // 9659 |
28817 | | { PseudoVSUXSEG3EI16_V_MF2_M1_MASK, VSUXSEG3EI16_V }, // 9660 |
28818 | | { PseudoVSUXSEG3EI16_V_MF2_M2, VSUXSEG3EI16_V }, // 9661 |
28819 | | { PseudoVSUXSEG3EI16_V_MF2_M2_MASK, VSUXSEG3EI16_V }, // 9662 |
28820 | | { PseudoVSUXSEG3EI16_V_MF2_MF2, VSUXSEG3EI16_V }, // 9663 |
28821 | | { PseudoVSUXSEG3EI16_V_MF2_MF2_MASK, VSUXSEG3EI16_V }, // 9664 |
28822 | | { PseudoVSUXSEG3EI16_V_MF2_MF4, VSUXSEG3EI16_V }, // 9665 |
28823 | | { PseudoVSUXSEG3EI16_V_MF2_MF4_MASK, VSUXSEG3EI16_V }, // 9666 |
28824 | | { PseudoVSUXSEG3EI16_V_MF4_M1, VSUXSEG3EI16_V }, // 9667 |
28825 | | { PseudoVSUXSEG3EI16_V_MF4_M1_MASK, VSUXSEG3EI16_V }, // 9668 |
28826 | | { PseudoVSUXSEG3EI16_V_MF4_MF2, VSUXSEG3EI16_V }, // 9669 |
28827 | | { PseudoVSUXSEG3EI16_V_MF4_MF2_MASK, VSUXSEG3EI16_V }, // 9670 |
28828 | | { PseudoVSUXSEG3EI16_V_MF4_MF4, VSUXSEG3EI16_V }, // 9671 |
28829 | | { PseudoVSUXSEG3EI16_V_MF4_MF4_MASK, VSUXSEG3EI16_V }, // 9672 |
28830 | | { PseudoVSUXSEG3EI16_V_MF4_MF8, VSUXSEG3EI16_V }, // 9673 |
28831 | | { PseudoVSUXSEG3EI16_V_MF4_MF8_MASK, VSUXSEG3EI16_V }, // 9674 |
28832 | | { PseudoVSUXSEG3EI32_V_M1_M1, VSUXSEG3EI32_V }, // 9675 |
28833 | | { PseudoVSUXSEG3EI32_V_M1_M1_MASK, VSUXSEG3EI32_V }, // 9676 |
28834 | | { PseudoVSUXSEG3EI32_V_M1_M2, VSUXSEG3EI32_V }, // 9677 |
28835 | | { PseudoVSUXSEG3EI32_V_M1_M2_MASK, VSUXSEG3EI32_V }, // 9678 |
28836 | | { PseudoVSUXSEG3EI32_V_M1_MF2, VSUXSEG3EI32_V }, // 9679 |
28837 | | { PseudoVSUXSEG3EI32_V_M1_MF2_MASK, VSUXSEG3EI32_V }, // 9680 |
28838 | | { PseudoVSUXSEG3EI32_V_M1_MF4, VSUXSEG3EI32_V }, // 9681 |
28839 | | { PseudoVSUXSEG3EI32_V_M1_MF4_MASK, VSUXSEG3EI32_V }, // 9682 |
28840 | | { PseudoVSUXSEG3EI32_V_M2_M1, VSUXSEG3EI32_V }, // 9683 |
28841 | | { PseudoVSUXSEG3EI32_V_M2_M1_MASK, VSUXSEG3EI32_V }, // 9684 |
28842 | | { PseudoVSUXSEG3EI32_V_M2_M2, VSUXSEG3EI32_V }, // 9685 |
28843 | | { PseudoVSUXSEG3EI32_V_M2_M2_MASK, VSUXSEG3EI32_V }, // 9686 |
28844 | | { PseudoVSUXSEG3EI32_V_M2_MF2, VSUXSEG3EI32_V }, // 9687 |
28845 | | { PseudoVSUXSEG3EI32_V_M2_MF2_MASK, VSUXSEG3EI32_V }, // 9688 |
28846 | | { PseudoVSUXSEG3EI32_V_M4_M1, VSUXSEG3EI32_V }, // 9689 |
28847 | | { PseudoVSUXSEG3EI32_V_M4_M1_MASK, VSUXSEG3EI32_V }, // 9690 |
28848 | | { PseudoVSUXSEG3EI32_V_M4_M2, VSUXSEG3EI32_V }, // 9691 |
28849 | | { PseudoVSUXSEG3EI32_V_M4_M2_MASK, VSUXSEG3EI32_V }, // 9692 |
28850 | | { PseudoVSUXSEG3EI32_V_M8_M2, VSUXSEG3EI32_V }, // 9693 |
28851 | | { PseudoVSUXSEG3EI32_V_M8_M2_MASK, VSUXSEG3EI32_V }, // 9694 |
28852 | | { PseudoVSUXSEG3EI32_V_MF2_M1, VSUXSEG3EI32_V }, // 9695 |
28853 | | { PseudoVSUXSEG3EI32_V_MF2_M1_MASK, VSUXSEG3EI32_V }, // 9696 |
28854 | | { PseudoVSUXSEG3EI32_V_MF2_MF2, VSUXSEG3EI32_V }, // 9697 |
28855 | | { PseudoVSUXSEG3EI32_V_MF2_MF2_MASK, VSUXSEG3EI32_V }, // 9698 |
28856 | | { PseudoVSUXSEG3EI32_V_MF2_MF4, VSUXSEG3EI32_V }, // 9699 |
28857 | | { PseudoVSUXSEG3EI32_V_MF2_MF4_MASK, VSUXSEG3EI32_V }, // 9700 |
28858 | | { PseudoVSUXSEG3EI32_V_MF2_MF8, VSUXSEG3EI32_V }, // 9701 |
28859 | | { PseudoVSUXSEG3EI32_V_MF2_MF8_MASK, VSUXSEG3EI32_V }, // 9702 |
28860 | | { PseudoVSUXSEG3EI64_V_M1_M1, VSUXSEG3EI64_V }, // 9703 |
28861 | | { PseudoVSUXSEG3EI64_V_M1_M1_MASK, VSUXSEG3EI64_V }, // 9704 |
28862 | | { PseudoVSUXSEG3EI64_V_M1_MF2, VSUXSEG3EI64_V }, // 9705 |
28863 | | { PseudoVSUXSEG3EI64_V_M1_MF2_MASK, VSUXSEG3EI64_V }, // 9706 |
28864 | | { PseudoVSUXSEG3EI64_V_M1_MF4, VSUXSEG3EI64_V }, // 9707 |
28865 | | { PseudoVSUXSEG3EI64_V_M1_MF4_MASK, VSUXSEG3EI64_V }, // 9708 |
28866 | | { PseudoVSUXSEG3EI64_V_M1_MF8, VSUXSEG3EI64_V }, // 9709 |
28867 | | { PseudoVSUXSEG3EI64_V_M1_MF8_MASK, VSUXSEG3EI64_V }, // 9710 |
28868 | | { PseudoVSUXSEG3EI64_V_M2_M1, VSUXSEG3EI64_V }, // 9711 |
28869 | | { PseudoVSUXSEG3EI64_V_M2_M1_MASK, VSUXSEG3EI64_V }, // 9712 |
28870 | | { PseudoVSUXSEG3EI64_V_M2_M2, VSUXSEG3EI64_V }, // 9713 |
28871 | | { PseudoVSUXSEG3EI64_V_M2_M2_MASK, VSUXSEG3EI64_V }, // 9714 |
28872 | | { PseudoVSUXSEG3EI64_V_M2_MF2, VSUXSEG3EI64_V }, // 9715 |
28873 | | { PseudoVSUXSEG3EI64_V_M2_MF2_MASK, VSUXSEG3EI64_V }, // 9716 |
28874 | | { PseudoVSUXSEG3EI64_V_M2_MF4, VSUXSEG3EI64_V }, // 9717 |
28875 | | { PseudoVSUXSEG3EI64_V_M2_MF4_MASK, VSUXSEG3EI64_V }, // 9718 |
28876 | | { PseudoVSUXSEG3EI64_V_M4_M1, VSUXSEG3EI64_V }, // 9719 |
28877 | | { PseudoVSUXSEG3EI64_V_M4_M1_MASK, VSUXSEG3EI64_V }, // 9720 |
28878 | | { PseudoVSUXSEG3EI64_V_M4_M2, VSUXSEG3EI64_V }, // 9721 |
28879 | | { PseudoVSUXSEG3EI64_V_M4_M2_MASK, VSUXSEG3EI64_V }, // 9722 |
28880 | | { PseudoVSUXSEG3EI64_V_M4_MF2, VSUXSEG3EI64_V }, // 9723 |
28881 | | { PseudoVSUXSEG3EI64_V_M4_MF2_MASK, VSUXSEG3EI64_V }, // 9724 |
28882 | | { PseudoVSUXSEG3EI64_V_M8_M1, VSUXSEG3EI64_V }, // 9725 |
28883 | | { PseudoVSUXSEG3EI64_V_M8_M1_MASK, VSUXSEG3EI64_V }, // 9726 |
28884 | | { PseudoVSUXSEG3EI64_V_M8_M2, VSUXSEG3EI64_V }, // 9727 |
28885 | | { PseudoVSUXSEG3EI64_V_M8_M2_MASK, VSUXSEG3EI64_V }, // 9728 |
28886 | | { PseudoVSUXSEG3EI8_V_M1_M1, VSUXSEG3EI8_V }, // 9729 |
28887 | | { PseudoVSUXSEG3EI8_V_M1_M1_MASK, VSUXSEG3EI8_V }, // 9730 |
28888 | | { PseudoVSUXSEG3EI8_V_M1_M2, VSUXSEG3EI8_V }, // 9731 |
28889 | | { PseudoVSUXSEG3EI8_V_M1_M2_MASK, VSUXSEG3EI8_V }, // 9732 |
28890 | | { PseudoVSUXSEG3EI8_V_M2_M2, VSUXSEG3EI8_V }, // 9733 |
28891 | | { PseudoVSUXSEG3EI8_V_M2_M2_MASK, VSUXSEG3EI8_V }, // 9734 |
28892 | | { PseudoVSUXSEG3EI8_V_MF2_M1, VSUXSEG3EI8_V }, // 9735 |
28893 | | { PseudoVSUXSEG3EI8_V_MF2_M1_MASK, VSUXSEG3EI8_V }, // 9736 |
28894 | | { PseudoVSUXSEG3EI8_V_MF2_M2, VSUXSEG3EI8_V }, // 9737 |
28895 | | { PseudoVSUXSEG3EI8_V_MF2_M2_MASK, VSUXSEG3EI8_V }, // 9738 |
28896 | | { PseudoVSUXSEG3EI8_V_MF2_MF2, VSUXSEG3EI8_V }, // 9739 |
28897 | | { PseudoVSUXSEG3EI8_V_MF2_MF2_MASK, VSUXSEG3EI8_V }, // 9740 |
28898 | | { PseudoVSUXSEG3EI8_V_MF4_M1, VSUXSEG3EI8_V }, // 9741 |
28899 | | { PseudoVSUXSEG3EI8_V_MF4_M1_MASK, VSUXSEG3EI8_V }, // 9742 |
28900 | | { PseudoVSUXSEG3EI8_V_MF4_M2, VSUXSEG3EI8_V }, // 9743 |
28901 | | { PseudoVSUXSEG3EI8_V_MF4_M2_MASK, VSUXSEG3EI8_V }, // 9744 |
28902 | | { PseudoVSUXSEG3EI8_V_MF4_MF2, VSUXSEG3EI8_V }, // 9745 |
28903 | | { PseudoVSUXSEG3EI8_V_MF4_MF2_MASK, VSUXSEG3EI8_V }, // 9746 |
28904 | | { PseudoVSUXSEG3EI8_V_MF4_MF4, VSUXSEG3EI8_V }, // 9747 |
28905 | | { PseudoVSUXSEG3EI8_V_MF4_MF4_MASK, VSUXSEG3EI8_V }, // 9748 |
28906 | | { PseudoVSUXSEG3EI8_V_MF8_M1, VSUXSEG3EI8_V }, // 9749 |
28907 | | { PseudoVSUXSEG3EI8_V_MF8_M1_MASK, VSUXSEG3EI8_V }, // 9750 |
28908 | | { PseudoVSUXSEG3EI8_V_MF8_MF2, VSUXSEG3EI8_V }, // 9751 |
28909 | | { PseudoVSUXSEG3EI8_V_MF8_MF2_MASK, VSUXSEG3EI8_V }, // 9752 |
28910 | | { PseudoVSUXSEG3EI8_V_MF8_MF4, VSUXSEG3EI8_V }, // 9753 |
28911 | | { PseudoVSUXSEG3EI8_V_MF8_MF4_MASK, VSUXSEG3EI8_V }, // 9754 |
28912 | | { PseudoVSUXSEG3EI8_V_MF8_MF8, VSUXSEG3EI8_V }, // 9755 |
28913 | | { PseudoVSUXSEG3EI8_V_MF8_MF8_MASK, VSUXSEG3EI8_V }, // 9756 |
28914 | | { PseudoVSUXSEG4EI16_V_M1_M1, VSUXSEG4EI16_V }, // 9757 |
28915 | | { PseudoVSUXSEG4EI16_V_M1_M1_MASK, VSUXSEG4EI16_V }, // 9758 |
28916 | | { PseudoVSUXSEG4EI16_V_M1_M2, VSUXSEG4EI16_V }, // 9759 |
28917 | | { PseudoVSUXSEG4EI16_V_M1_M2_MASK, VSUXSEG4EI16_V }, // 9760 |
28918 | | { PseudoVSUXSEG4EI16_V_M1_MF2, VSUXSEG4EI16_V }, // 9761 |
28919 | | { PseudoVSUXSEG4EI16_V_M1_MF2_MASK, VSUXSEG4EI16_V }, // 9762 |
28920 | | { PseudoVSUXSEG4EI16_V_M2_M1, VSUXSEG4EI16_V }, // 9763 |
28921 | | { PseudoVSUXSEG4EI16_V_M2_M1_MASK, VSUXSEG4EI16_V }, // 9764 |
28922 | | { PseudoVSUXSEG4EI16_V_M2_M2, VSUXSEG4EI16_V }, // 9765 |
28923 | | { PseudoVSUXSEG4EI16_V_M2_M2_MASK, VSUXSEG4EI16_V }, // 9766 |
28924 | | { PseudoVSUXSEG4EI16_V_M4_M2, VSUXSEG4EI16_V }, // 9767 |
28925 | | { PseudoVSUXSEG4EI16_V_M4_M2_MASK, VSUXSEG4EI16_V }, // 9768 |
28926 | | { PseudoVSUXSEG4EI16_V_MF2_M1, VSUXSEG4EI16_V }, // 9769 |
28927 | | { PseudoVSUXSEG4EI16_V_MF2_M1_MASK, VSUXSEG4EI16_V }, // 9770 |
28928 | | { PseudoVSUXSEG4EI16_V_MF2_M2, VSUXSEG4EI16_V }, // 9771 |
28929 | | { PseudoVSUXSEG4EI16_V_MF2_M2_MASK, VSUXSEG4EI16_V }, // 9772 |
28930 | | { PseudoVSUXSEG4EI16_V_MF2_MF2, VSUXSEG4EI16_V }, // 9773 |
28931 | | { PseudoVSUXSEG4EI16_V_MF2_MF2_MASK, VSUXSEG4EI16_V }, // 9774 |
28932 | | { PseudoVSUXSEG4EI16_V_MF2_MF4, VSUXSEG4EI16_V }, // 9775 |
28933 | | { PseudoVSUXSEG4EI16_V_MF2_MF4_MASK, VSUXSEG4EI16_V }, // 9776 |
28934 | | { PseudoVSUXSEG4EI16_V_MF4_M1, VSUXSEG4EI16_V }, // 9777 |
28935 | | { PseudoVSUXSEG4EI16_V_MF4_M1_MASK, VSUXSEG4EI16_V }, // 9778 |
28936 | | { PseudoVSUXSEG4EI16_V_MF4_MF2, VSUXSEG4EI16_V }, // 9779 |
28937 | | { PseudoVSUXSEG4EI16_V_MF4_MF2_MASK, VSUXSEG4EI16_V }, // 9780 |
28938 | | { PseudoVSUXSEG4EI16_V_MF4_MF4, VSUXSEG4EI16_V }, // 9781 |
28939 | | { PseudoVSUXSEG4EI16_V_MF4_MF4_MASK, VSUXSEG4EI16_V }, // 9782 |
28940 | | { PseudoVSUXSEG4EI16_V_MF4_MF8, VSUXSEG4EI16_V }, // 9783 |
28941 | | { PseudoVSUXSEG4EI16_V_MF4_MF8_MASK, VSUXSEG4EI16_V }, // 9784 |
28942 | | { PseudoVSUXSEG4EI32_V_M1_M1, VSUXSEG4EI32_V }, // 9785 |
28943 | | { PseudoVSUXSEG4EI32_V_M1_M1_MASK, VSUXSEG4EI32_V }, // 9786 |
28944 | | { PseudoVSUXSEG4EI32_V_M1_M2, VSUXSEG4EI32_V }, // 9787 |
28945 | | { PseudoVSUXSEG4EI32_V_M1_M2_MASK, VSUXSEG4EI32_V }, // 9788 |
28946 | | { PseudoVSUXSEG4EI32_V_M1_MF2, VSUXSEG4EI32_V }, // 9789 |
28947 | | { PseudoVSUXSEG4EI32_V_M1_MF2_MASK, VSUXSEG4EI32_V }, // 9790 |
28948 | | { PseudoVSUXSEG4EI32_V_M1_MF4, VSUXSEG4EI32_V }, // 9791 |
28949 | | { PseudoVSUXSEG4EI32_V_M1_MF4_MASK, VSUXSEG4EI32_V }, // 9792 |
28950 | | { PseudoVSUXSEG4EI32_V_M2_M1, VSUXSEG4EI32_V }, // 9793 |
28951 | | { PseudoVSUXSEG4EI32_V_M2_M1_MASK, VSUXSEG4EI32_V }, // 9794 |
28952 | | { PseudoVSUXSEG4EI32_V_M2_M2, VSUXSEG4EI32_V }, // 9795 |
28953 | | { PseudoVSUXSEG4EI32_V_M2_M2_MASK, VSUXSEG4EI32_V }, // 9796 |
28954 | | { PseudoVSUXSEG4EI32_V_M2_MF2, VSUXSEG4EI32_V }, // 9797 |
28955 | | { PseudoVSUXSEG4EI32_V_M2_MF2_MASK, VSUXSEG4EI32_V }, // 9798 |
28956 | | { PseudoVSUXSEG4EI32_V_M4_M1, VSUXSEG4EI32_V }, // 9799 |
28957 | | { PseudoVSUXSEG4EI32_V_M4_M1_MASK, VSUXSEG4EI32_V }, // 9800 |
28958 | | { PseudoVSUXSEG4EI32_V_M4_M2, VSUXSEG4EI32_V }, // 9801 |
28959 | | { PseudoVSUXSEG4EI32_V_M4_M2_MASK, VSUXSEG4EI32_V }, // 9802 |
28960 | | { PseudoVSUXSEG4EI32_V_M8_M2, VSUXSEG4EI32_V }, // 9803 |
28961 | | { PseudoVSUXSEG4EI32_V_M8_M2_MASK, VSUXSEG4EI32_V }, // 9804 |
28962 | | { PseudoVSUXSEG4EI32_V_MF2_M1, VSUXSEG4EI32_V }, // 9805 |
28963 | | { PseudoVSUXSEG4EI32_V_MF2_M1_MASK, VSUXSEG4EI32_V }, // 9806 |
28964 | | { PseudoVSUXSEG4EI32_V_MF2_MF2, VSUXSEG4EI32_V }, // 9807 |
28965 | | { PseudoVSUXSEG4EI32_V_MF2_MF2_MASK, VSUXSEG4EI32_V }, // 9808 |
28966 | | { PseudoVSUXSEG4EI32_V_MF2_MF4, VSUXSEG4EI32_V }, // 9809 |
28967 | | { PseudoVSUXSEG4EI32_V_MF2_MF4_MASK, VSUXSEG4EI32_V }, // 9810 |
28968 | | { PseudoVSUXSEG4EI32_V_MF2_MF8, VSUXSEG4EI32_V }, // 9811 |
28969 | | { PseudoVSUXSEG4EI32_V_MF2_MF8_MASK, VSUXSEG4EI32_V }, // 9812 |
28970 | | { PseudoVSUXSEG4EI64_V_M1_M1, VSUXSEG4EI64_V }, // 9813 |
28971 | | { PseudoVSUXSEG4EI64_V_M1_M1_MASK, VSUXSEG4EI64_V }, // 9814 |
28972 | | { PseudoVSUXSEG4EI64_V_M1_MF2, VSUXSEG4EI64_V }, // 9815 |
28973 | | { PseudoVSUXSEG4EI64_V_M1_MF2_MASK, VSUXSEG4EI64_V }, // 9816 |
28974 | | { PseudoVSUXSEG4EI64_V_M1_MF4, VSUXSEG4EI64_V }, // 9817 |
28975 | | { PseudoVSUXSEG4EI64_V_M1_MF4_MASK, VSUXSEG4EI64_V }, // 9818 |
28976 | | { PseudoVSUXSEG4EI64_V_M1_MF8, VSUXSEG4EI64_V }, // 9819 |
28977 | | { PseudoVSUXSEG4EI64_V_M1_MF8_MASK, VSUXSEG4EI64_V }, // 9820 |
28978 | | { PseudoVSUXSEG4EI64_V_M2_M1, VSUXSEG4EI64_V }, // 9821 |
28979 | | { PseudoVSUXSEG4EI64_V_M2_M1_MASK, VSUXSEG4EI64_V }, // 9822 |
28980 | | { PseudoVSUXSEG4EI64_V_M2_M2, VSUXSEG4EI64_V }, // 9823 |
28981 | | { PseudoVSUXSEG4EI64_V_M2_M2_MASK, VSUXSEG4EI64_V }, // 9824 |
28982 | | { PseudoVSUXSEG4EI64_V_M2_MF2, VSUXSEG4EI64_V }, // 9825 |
28983 | | { PseudoVSUXSEG4EI64_V_M2_MF2_MASK, VSUXSEG4EI64_V }, // 9826 |
28984 | | { PseudoVSUXSEG4EI64_V_M2_MF4, VSUXSEG4EI64_V }, // 9827 |
28985 | | { PseudoVSUXSEG4EI64_V_M2_MF4_MASK, VSUXSEG4EI64_V }, // 9828 |
28986 | | { PseudoVSUXSEG4EI64_V_M4_M1, VSUXSEG4EI64_V }, // 9829 |
28987 | | { PseudoVSUXSEG4EI64_V_M4_M1_MASK, VSUXSEG4EI64_V }, // 9830 |
28988 | | { PseudoVSUXSEG4EI64_V_M4_M2, VSUXSEG4EI64_V }, // 9831 |
28989 | | { PseudoVSUXSEG4EI64_V_M4_M2_MASK, VSUXSEG4EI64_V }, // 9832 |
28990 | | { PseudoVSUXSEG4EI64_V_M4_MF2, VSUXSEG4EI64_V }, // 9833 |
28991 | | { PseudoVSUXSEG4EI64_V_M4_MF2_MASK, VSUXSEG4EI64_V }, // 9834 |
28992 | | { PseudoVSUXSEG4EI64_V_M8_M1, VSUXSEG4EI64_V }, // 9835 |
28993 | | { PseudoVSUXSEG4EI64_V_M8_M1_MASK, VSUXSEG4EI64_V }, // 9836 |
28994 | | { PseudoVSUXSEG4EI64_V_M8_M2, VSUXSEG4EI64_V }, // 9837 |
28995 | | { PseudoVSUXSEG4EI64_V_M8_M2_MASK, VSUXSEG4EI64_V }, // 9838 |
28996 | | { PseudoVSUXSEG4EI8_V_M1_M1, VSUXSEG4EI8_V }, // 9839 |
28997 | | { PseudoVSUXSEG4EI8_V_M1_M1_MASK, VSUXSEG4EI8_V }, // 9840 |
28998 | | { PseudoVSUXSEG4EI8_V_M1_M2, VSUXSEG4EI8_V }, // 9841 |
28999 | | { PseudoVSUXSEG4EI8_V_M1_M2_MASK, VSUXSEG4EI8_V }, // 9842 |
29000 | | { PseudoVSUXSEG4EI8_V_M2_M2, VSUXSEG4EI8_V }, // 9843 |
29001 | | { PseudoVSUXSEG4EI8_V_M2_M2_MASK, VSUXSEG4EI8_V }, // 9844 |
29002 | | { PseudoVSUXSEG4EI8_V_MF2_M1, VSUXSEG4EI8_V }, // 9845 |
29003 | | { PseudoVSUXSEG4EI8_V_MF2_M1_MASK, VSUXSEG4EI8_V }, // 9846 |
29004 | | { PseudoVSUXSEG4EI8_V_MF2_M2, VSUXSEG4EI8_V }, // 9847 |
29005 | | { PseudoVSUXSEG4EI8_V_MF2_M2_MASK, VSUXSEG4EI8_V }, // 9848 |
29006 | | { PseudoVSUXSEG4EI8_V_MF2_MF2, VSUXSEG4EI8_V }, // 9849 |
29007 | | { PseudoVSUXSEG4EI8_V_MF2_MF2_MASK, VSUXSEG4EI8_V }, // 9850 |
29008 | | { PseudoVSUXSEG4EI8_V_MF4_M1, VSUXSEG4EI8_V }, // 9851 |
29009 | | { PseudoVSUXSEG4EI8_V_MF4_M1_MASK, VSUXSEG4EI8_V }, // 9852 |
29010 | | { PseudoVSUXSEG4EI8_V_MF4_M2, VSUXSEG4EI8_V }, // 9853 |
29011 | | { PseudoVSUXSEG4EI8_V_MF4_M2_MASK, VSUXSEG4EI8_V }, // 9854 |
29012 | | { PseudoVSUXSEG4EI8_V_MF4_MF2, VSUXSEG4EI8_V }, // 9855 |
29013 | | { PseudoVSUXSEG4EI8_V_MF4_MF2_MASK, VSUXSEG4EI8_V }, // 9856 |
29014 | | { PseudoVSUXSEG4EI8_V_MF4_MF4, VSUXSEG4EI8_V }, // 9857 |
29015 | | { PseudoVSUXSEG4EI8_V_MF4_MF4_MASK, VSUXSEG4EI8_V }, // 9858 |
29016 | | { PseudoVSUXSEG4EI8_V_MF8_M1, VSUXSEG4EI8_V }, // 9859 |
29017 | | { PseudoVSUXSEG4EI8_V_MF8_M1_MASK, VSUXSEG4EI8_V }, // 9860 |
29018 | | { PseudoVSUXSEG4EI8_V_MF8_MF2, VSUXSEG4EI8_V }, // 9861 |
29019 | | { PseudoVSUXSEG4EI8_V_MF8_MF2_MASK, VSUXSEG4EI8_V }, // 9862 |
29020 | | { PseudoVSUXSEG4EI8_V_MF8_MF4, VSUXSEG4EI8_V }, // 9863 |
29021 | | { PseudoVSUXSEG4EI8_V_MF8_MF4_MASK, VSUXSEG4EI8_V }, // 9864 |
29022 | | { PseudoVSUXSEG4EI8_V_MF8_MF8, VSUXSEG4EI8_V }, // 9865 |
29023 | | { PseudoVSUXSEG4EI8_V_MF8_MF8_MASK, VSUXSEG4EI8_V }, // 9866 |
29024 | | { PseudoVSUXSEG5EI16_V_M1_M1, VSUXSEG5EI16_V }, // 9867 |
29025 | | { PseudoVSUXSEG5EI16_V_M1_M1_MASK, VSUXSEG5EI16_V }, // 9868 |
29026 | | { PseudoVSUXSEG5EI16_V_M1_MF2, VSUXSEG5EI16_V }, // 9869 |
29027 | | { PseudoVSUXSEG5EI16_V_M1_MF2_MASK, VSUXSEG5EI16_V }, // 9870 |
29028 | | { PseudoVSUXSEG5EI16_V_M2_M1, VSUXSEG5EI16_V }, // 9871 |
29029 | | { PseudoVSUXSEG5EI16_V_M2_M1_MASK, VSUXSEG5EI16_V }, // 9872 |
29030 | | { PseudoVSUXSEG5EI16_V_MF2_M1, VSUXSEG5EI16_V }, // 9873 |
29031 | | { PseudoVSUXSEG5EI16_V_MF2_M1_MASK, VSUXSEG5EI16_V }, // 9874 |
29032 | | { PseudoVSUXSEG5EI16_V_MF2_MF2, VSUXSEG5EI16_V }, // 9875 |
29033 | | { PseudoVSUXSEG5EI16_V_MF2_MF2_MASK, VSUXSEG5EI16_V }, // 9876 |
29034 | | { PseudoVSUXSEG5EI16_V_MF2_MF4, VSUXSEG5EI16_V }, // 9877 |
29035 | | { PseudoVSUXSEG5EI16_V_MF2_MF4_MASK, VSUXSEG5EI16_V }, // 9878 |
29036 | | { PseudoVSUXSEG5EI16_V_MF4_M1, VSUXSEG5EI16_V }, // 9879 |
29037 | | { PseudoVSUXSEG5EI16_V_MF4_M1_MASK, VSUXSEG5EI16_V }, // 9880 |
29038 | | { PseudoVSUXSEG5EI16_V_MF4_MF2, VSUXSEG5EI16_V }, // 9881 |
29039 | | { PseudoVSUXSEG5EI16_V_MF4_MF2_MASK, VSUXSEG5EI16_V }, // 9882 |
29040 | | { PseudoVSUXSEG5EI16_V_MF4_MF4, VSUXSEG5EI16_V }, // 9883 |
29041 | | { PseudoVSUXSEG5EI16_V_MF4_MF4_MASK, VSUXSEG5EI16_V }, // 9884 |
29042 | | { PseudoVSUXSEG5EI16_V_MF4_MF8, VSUXSEG5EI16_V }, // 9885 |
29043 | | { PseudoVSUXSEG5EI16_V_MF4_MF8_MASK, VSUXSEG5EI16_V }, // 9886 |
29044 | | { PseudoVSUXSEG5EI32_V_M1_M1, VSUXSEG5EI32_V }, // 9887 |
29045 | | { PseudoVSUXSEG5EI32_V_M1_M1_MASK, VSUXSEG5EI32_V }, // 9888 |
29046 | | { PseudoVSUXSEG5EI32_V_M1_MF2, VSUXSEG5EI32_V }, // 9889 |
29047 | | { PseudoVSUXSEG5EI32_V_M1_MF2_MASK, VSUXSEG5EI32_V }, // 9890 |
29048 | | { PseudoVSUXSEG5EI32_V_M1_MF4, VSUXSEG5EI32_V }, // 9891 |
29049 | | { PseudoVSUXSEG5EI32_V_M1_MF4_MASK, VSUXSEG5EI32_V }, // 9892 |
29050 | | { PseudoVSUXSEG5EI32_V_M2_M1, VSUXSEG5EI32_V }, // 9893 |
29051 | | { PseudoVSUXSEG5EI32_V_M2_M1_MASK, VSUXSEG5EI32_V }, // 9894 |
29052 | | { PseudoVSUXSEG5EI32_V_M2_MF2, VSUXSEG5EI32_V }, // 9895 |
29053 | | { PseudoVSUXSEG5EI32_V_M2_MF2_MASK, VSUXSEG5EI32_V }, // 9896 |
29054 | | { PseudoVSUXSEG5EI32_V_M4_M1, VSUXSEG5EI32_V }, // 9897 |
29055 | | { PseudoVSUXSEG5EI32_V_M4_M1_MASK, VSUXSEG5EI32_V }, // 9898 |
29056 | | { PseudoVSUXSEG5EI32_V_MF2_M1, VSUXSEG5EI32_V }, // 9899 |
29057 | | { PseudoVSUXSEG5EI32_V_MF2_M1_MASK, VSUXSEG5EI32_V }, // 9900 |
29058 | | { PseudoVSUXSEG5EI32_V_MF2_MF2, VSUXSEG5EI32_V }, // 9901 |
29059 | | { PseudoVSUXSEG5EI32_V_MF2_MF2_MASK, VSUXSEG5EI32_V }, // 9902 |
29060 | | { PseudoVSUXSEG5EI32_V_MF2_MF4, VSUXSEG5EI32_V }, // 9903 |
29061 | | { PseudoVSUXSEG5EI32_V_MF2_MF4_MASK, VSUXSEG5EI32_V }, // 9904 |
29062 | | { PseudoVSUXSEG5EI32_V_MF2_MF8, VSUXSEG5EI32_V }, // 9905 |
29063 | | { PseudoVSUXSEG5EI32_V_MF2_MF8_MASK, VSUXSEG5EI32_V }, // 9906 |
29064 | | { PseudoVSUXSEG5EI64_V_M1_M1, VSUXSEG5EI64_V }, // 9907 |
29065 | | { PseudoVSUXSEG5EI64_V_M1_M1_MASK, VSUXSEG5EI64_V }, // 9908 |
29066 | | { PseudoVSUXSEG5EI64_V_M1_MF2, VSUXSEG5EI64_V }, // 9909 |
29067 | | { PseudoVSUXSEG5EI64_V_M1_MF2_MASK, VSUXSEG5EI64_V }, // 9910 |
29068 | | { PseudoVSUXSEG5EI64_V_M1_MF4, VSUXSEG5EI64_V }, // 9911 |
29069 | | { PseudoVSUXSEG5EI64_V_M1_MF4_MASK, VSUXSEG5EI64_V }, // 9912 |
29070 | | { PseudoVSUXSEG5EI64_V_M1_MF8, VSUXSEG5EI64_V }, // 9913 |
29071 | | { PseudoVSUXSEG5EI64_V_M1_MF8_MASK, VSUXSEG5EI64_V }, // 9914 |
29072 | | { PseudoVSUXSEG5EI64_V_M2_M1, VSUXSEG5EI64_V }, // 9915 |
29073 | | { PseudoVSUXSEG5EI64_V_M2_M1_MASK, VSUXSEG5EI64_V }, // 9916 |
29074 | | { PseudoVSUXSEG5EI64_V_M2_MF2, VSUXSEG5EI64_V }, // 9917 |
29075 | | { PseudoVSUXSEG5EI64_V_M2_MF2_MASK, VSUXSEG5EI64_V }, // 9918 |
29076 | | { PseudoVSUXSEG5EI64_V_M2_MF4, VSUXSEG5EI64_V }, // 9919 |
29077 | | { PseudoVSUXSEG5EI64_V_M2_MF4_MASK, VSUXSEG5EI64_V }, // 9920 |
29078 | | { PseudoVSUXSEG5EI64_V_M4_M1, VSUXSEG5EI64_V }, // 9921 |
29079 | | { PseudoVSUXSEG5EI64_V_M4_M1_MASK, VSUXSEG5EI64_V }, // 9922 |
29080 | | { PseudoVSUXSEG5EI64_V_M4_MF2, VSUXSEG5EI64_V }, // 9923 |
29081 | | { PseudoVSUXSEG5EI64_V_M4_MF2_MASK, VSUXSEG5EI64_V }, // 9924 |
29082 | | { PseudoVSUXSEG5EI64_V_M8_M1, VSUXSEG5EI64_V }, // 9925 |
29083 | | { PseudoVSUXSEG5EI64_V_M8_M1_MASK, VSUXSEG5EI64_V }, // 9926 |
29084 | | { PseudoVSUXSEG5EI8_V_M1_M1, VSUXSEG5EI8_V }, // 9927 |
29085 | | { PseudoVSUXSEG5EI8_V_M1_M1_MASK, VSUXSEG5EI8_V }, // 9928 |
29086 | | { PseudoVSUXSEG5EI8_V_MF2_M1, VSUXSEG5EI8_V }, // 9929 |
29087 | | { PseudoVSUXSEG5EI8_V_MF2_M1_MASK, VSUXSEG5EI8_V }, // 9930 |
29088 | | { PseudoVSUXSEG5EI8_V_MF2_MF2, VSUXSEG5EI8_V }, // 9931 |
29089 | | { PseudoVSUXSEG5EI8_V_MF2_MF2_MASK, VSUXSEG5EI8_V }, // 9932 |
29090 | | { PseudoVSUXSEG5EI8_V_MF4_M1, VSUXSEG5EI8_V }, // 9933 |
29091 | | { PseudoVSUXSEG5EI8_V_MF4_M1_MASK, VSUXSEG5EI8_V }, // 9934 |
29092 | | { PseudoVSUXSEG5EI8_V_MF4_MF2, VSUXSEG5EI8_V }, // 9935 |
29093 | | { PseudoVSUXSEG5EI8_V_MF4_MF2_MASK, VSUXSEG5EI8_V }, // 9936 |
29094 | | { PseudoVSUXSEG5EI8_V_MF4_MF4, VSUXSEG5EI8_V }, // 9937 |
29095 | | { PseudoVSUXSEG5EI8_V_MF4_MF4_MASK, VSUXSEG5EI8_V }, // 9938 |
29096 | | { PseudoVSUXSEG5EI8_V_MF8_M1, VSUXSEG5EI8_V }, // 9939 |
29097 | | { PseudoVSUXSEG5EI8_V_MF8_M1_MASK, VSUXSEG5EI8_V }, // 9940 |
29098 | | { PseudoVSUXSEG5EI8_V_MF8_MF2, VSUXSEG5EI8_V }, // 9941 |
29099 | | { PseudoVSUXSEG5EI8_V_MF8_MF2_MASK, VSUXSEG5EI8_V }, // 9942 |
29100 | | { PseudoVSUXSEG5EI8_V_MF8_MF4, VSUXSEG5EI8_V }, // 9943 |
29101 | | { PseudoVSUXSEG5EI8_V_MF8_MF4_MASK, VSUXSEG5EI8_V }, // 9944 |
29102 | | { PseudoVSUXSEG5EI8_V_MF8_MF8, VSUXSEG5EI8_V }, // 9945 |
29103 | | { PseudoVSUXSEG5EI8_V_MF8_MF8_MASK, VSUXSEG5EI8_V }, // 9946 |
29104 | | { PseudoVSUXSEG6EI16_V_M1_M1, VSUXSEG6EI16_V }, // 9947 |
29105 | | { PseudoVSUXSEG6EI16_V_M1_M1_MASK, VSUXSEG6EI16_V }, // 9948 |
29106 | | { PseudoVSUXSEG6EI16_V_M1_MF2, VSUXSEG6EI16_V }, // 9949 |
29107 | | { PseudoVSUXSEG6EI16_V_M1_MF2_MASK, VSUXSEG6EI16_V }, // 9950 |
29108 | | { PseudoVSUXSEG6EI16_V_M2_M1, VSUXSEG6EI16_V }, // 9951 |
29109 | | { PseudoVSUXSEG6EI16_V_M2_M1_MASK, VSUXSEG6EI16_V }, // 9952 |
29110 | | { PseudoVSUXSEG6EI16_V_MF2_M1, VSUXSEG6EI16_V }, // 9953 |
29111 | | { PseudoVSUXSEG6EI16_V_MF2_M1_MASK, VSUXSEG6EI16_V }, // 9954 |
29112 | | { PseudoVSUXSEG6EI16_V_MF2_MF2, VSUXSEG6EI16_V }, // 9955 |
29113 | | { PseudoVSUXSEG6EI16_V_MF2_MF2_MASK, VSUXSEG6EI16_V }, // 9956 |
29114 | | { PseudoVSUXSEG6EI16_V_MF2_MF4, VSUXSEG6EI16_V }, // 9957 |
29115 | | { PseudoVSUXSEG6EI16_V_MF2_MF4_MASK, VSUXSEG6EI16_V }, // 9958 |
29116 | | { PseudoVSUXSEG6EI16_V_MF4_M1, VSUXSEG6EI16_V }, // 9959 |
29117 | | { PseudoVSUXSEG6EI16_V_MF4_M1_MASK, VSUXSEG6EI16_V }, // 9960 |
29118 | | { PseudoVSUXSEG6EI16_V_MF4_MF2, VSUXSEG6EI16_V }, // 9961 |
29119 | | { PseudoVSUXSEG6EI16_V_MF4_MF2_MASK, VSUXSEG6EI16_V }, // 9962 |
29120 | | { PseudoVSUXSEG6EI16_V_MF4_MF4, VSUXSEG6EI16_V }, // 9963 |
29121 | | { PseudoVSUXSEG6EI16_V_MF4_MF4_MASK, VSUXSEG6EI16_V }, // 9964 |
29122 | | { PseudoVSUXSEG6EI16_V_MF4_MF8, VSUXSEG6EI16_V }, // 9965 |
29123 | | { PseudoVSUXSEG6EI16_V_MF4_MF8_MASK, VSUXSEG6EI16_V }, // 9966 |
29124 | | { PseudoVSUXSEG6EI32_V_M1_M1, VSUXSEG6EI32_V }, // 9967 |
29125 | | { PseudoVSUXSEG6EI32_V_M1_M1_MASK, VSUXSEG6EI32_V }, // 9968 |
29126 | | { PseudoVSUXSEG6EI32_V_M1_MF2, VSUXSEG6EI32_V }, // 9969 |
29127 | | { PseudoVSUXSEG6EI32_V_M1_MF2_MASK, VSUXSEG6EI32_V }, // 9970 |
29128 | | { PseudoVSUXSEG6EI32_V_M1_MF4, VSUXSEG6EI32_V }, // 9971 |
29129 | | { PseudoVSUXSEG6EI32_V_M1_MF4_MASK, VSUXSEG6EI32_V }, // 9972 |
29130 | | { PseudoVSUXSEG6EI32_V_M2_M1, VSUXSEG6EI32_V }, // 9973 |
29131 | | { PseudoVSUXSEG6EI32_V_M2_M1_MASK, VSUXSEG6EI32_V }, // 9974 |
29132 | | { PseudoVSUXSEG6EI32_V_M2_MF2, VSUXSEG6EI32_V }, // 9975 |
29133 | | { PseudoVSUXSEG6EI32_V_M2_MF2_MASK, VSUXSEG6EI32_V }, // 9976 |
29134 | | { PseudoVSUXSEG6EI32_V_M4_M1, VSUXSEG6EI32_V }, // 9977 |
29135 | | { PseudoVSUXSEG6EI32_V_M4_M1_MASK, VSUXSEG6EI32_V }, // 9978 |
29136 | | { PseudoVSUXSEG6EI32_V_MF2_M1, VSUXSEG6EI32_V }, // 9979 |
29137 | | { PseudoVSUXSEG6EI32_V_MF2_M1_MASK, VSUXSEG6EI32_V }, // 9980 |
29138 | | { PseudoVSUXSEG6EI32_V_MF2_MF2, VSUXSEG6EI32_V }, // 9981 |
29139 | | { PseudoVSUXSEG6EI32_V_MF2_MF2_MASK, VSUXSEG6EI32_V }, // 9982 |
29140 | | { PseudoVSUXSEG6EI32_V_MF2_MF4, VSUXSEG6EI32_V }, // 9983 |
29141 | | { PseudoVSUXSEG6EI32_V_MF2_MF4_MASK, VSUXSEG6EI32_V }, // 9984 |
29142 | | { PseudoVSUXSEG6EI32_V_MF2_MF8, VSUXSEG6EI32_V }, // 9985 |
29143 | | { PseudoVSUXSEG6EI32_V_MF2_MF8_MASK, VSUXSEG6EI32_V }, // 9986 |
29144 | | { PseudoVSUXSEG6EI64_V_M1_M1, VSUXSEG6EI64_V }, // 9987 |
29145 | | { PseudoVSUXSEG6EI64_V_M1_M1_MASK, VSUXSEG6EI64_V }, // 9988 |
29146 | | { PseudoVSUXSEG6EI64_V_M1_MF2, VSUXSEG6EI64_V }, // 9989 |
29147 | | { PseudoVSUXSEG6EI64_V_M1_MF2_MASK, VSUXSEG6EI64_V }, // 9990 |
29148 | | { PseudoVSUXSEG6EI64_V_M1_MF4, VSUXSEG6EI64_V }, // 9991 |
29149 | | { PseudoVSUXSEG6EI64_V_M1_MF4_MASK, VSUXSEG6EI64_V }, // 9992 |
29150 | | { PseudoVSUXSEG6EI64_V_M1_MF8, VSUXSEG6EI64_V }, // 9993 |
29151 | | { PseudoVSUXSEG6EI64_V_M1_MF8_MASK, VSUXSEG6EI64_V }, // 9994 |
29152 | | { PseudoVSUXSEG6EI64_V_M2_M1, VSUXSEG6EI64_V }, // 9995 |
29153 | | { PseudoVSUXSEG6EI64_V_M2_M1_MASK, VSUXSEG6EI64_V }, // 9996 |
29154 | | { PseudoVSUXSEG6EI64_V_M2_MF2, VSUXSEG6EI64_V }, // 9997 |
29155 | | { PseudoVSUXSEG6EI64_V_M2_MF2_MASK, VSUXSEG6EI64_V }, // 9998 |
29156 | | { PseudoVSUXSEG6EI64_V_M2_MF4, VSUXSEG6EI64_V }, // 9999 |
29157 | | { PseudoVSUXSEG6EI64_V_M2_MF4_MASK, VSUXSEG6EI64_V }, // 10000 |
29158 | | { PseudoVSUXSEG6EI64_V_M4_M1, VSUXSEG6EI64_V }, // 10001 |
29159 | | { PseudoVSUXSEG6EI64_V_M4_M1_MASK, VSUXSEG6EI64_V }, // 10002 |
29160 | | { PseudoVSUXSEG6EI64_V_M4_MF2, VSUXSEG6EI64_V }, // 10003 |
29161 | | { PseudoVSUXSEG6EI64_V_M4_MF2_MASK, VSUXSEG6EI64_V }, // 10004 |
29162 | | { PseudoVSUXSEG6EI64_V_M8_M1, VSUXSEG6EI64_V }, // 10005 |
29163 | | { PseudoVSUXSEG6EI64_V_M8_M1_MASK, VSUXSEG6EI64_V }, // 10006 |
29164 | | { PseudoVSUXSEG6EI8_V_M1_M1, VSUXSEG6EI8_V }, // 10007 |
29165 | | { PseudoVSUXSEG6EI8_V_M1_M1_MASK, VSUXSEG6EI8_V }, // 10008 |
29166 | | { PseudoVSUXSEG6EI8_V_MF2_M1, VSUXSEG6EI8_V }, // 10009 |
29167 | | { PseudoVSUXSEG6EI8_V_MF2_M1_MASK, VSUXSEG6EI8_V }, // 10010 |
29168 | | { PseudoVSUXSEG6EI8_V_MF2_MF2, VSUXSEG6EI8_V }, // 10011 |
29169 | | { PseudoVSUXSEG6EI8_V_MF2_MF2_MASK, VSUXSEG6EI8_V }, // 10012 |
29170 | | { PseudoVSUXSEG6EI8_V_MF4_M1, VSUXSEG6EI8_V }, // 10013 |
29171 | | { PseudoVSUXSEG6EI8_V_MF4_M1_MASK, VSUXSEG6EI8_V }, // 10014 |
29172 | | { PseudoVSUXSEG6EI8_V_MF4_MF2, VSUXSEG6EI8_V }, // 10015 |
29173 | | { PseudoVSUXSEG6EI8_V_MF4_MF2_MASK, VSUXSEG6EI8_V }, // 10016 |
29174 | | { PseudoVSUXSEG6EI8_V_MF4_MF4, VSUXSEG6EI8_V }, // 10017 |
29175 | | { PseudoVSUXSEG6EI8_V_MF4_MF4_MASK, VSUXSEG6EI8_V }, // 10018 |
29176 | | { PseudoVSUXSEG6EI8_V_MF8_M1, VSUXSEG6EI8_V }, // 10019 |
29177 | | { PseudoVSUXSEG6EI8_V_MF8_M1_MASK, VSUXSEG6EI8_V }, // 10020 |
29178 | | { PseudoVSUXSEG6EI8_V_MF8_MF2, VSUXSEG6EI8_V }, // 10021 |
29179 | | { PseudoVSUXSEG6EI8_V_MF8_MF2_MASK, VSUXSEG6EI8_V }, // 10022 |
29180 | | { PseudoVSUXSEG6EI8_V_MF8_MF4, VSUXSEG6EI8_V }, // 10023 |
29181 | | { PseudoVSUXSEG6EI8_V_MF8_MF4_MASK, VSUXSEG6EI8_V }, // 10024 |
29182 | | { PseudoVSUXSEG6EI8_V_MF8_MF8, VSUXSEG6EI8_V }, // 10025 |
29183 | | { PseudoVSUXSEG6EI8_V_MF8_MF8_MASK, VSUXSEG6EI8_V }, // 10026 |
29184 | | { PseudoVSUXSEG7EI16_V_M1_M1, VSUXSEG7EI16_V }, // 10027 |
29185 | | { PseudoVSUXSEG7EI16_V_M1_M1_MASK, VSUXSEG7EI16_V }, // 10028 |
29186 | | { PseudoVSUXSEG7EI16_V_M1_MF2, VSUXSEG7EI16_V }, // 10029 |
29187 | | { PseudoVSUXSEG7EI16_V_M1_MF2_MASK, VSUXSEG7EI16_V }, // 10030 |
29188 | | { PseudoVSUXSEG7EI16_V_M2_M1, VSUXSEG7EI16_V }, // 10031 |
29189 | | { PseudoVSUXSEG7EI16_V_M2_M1_MASK, VSUXSEG7EI16_V }, // 10032 |
29190 | | { PseudoVSUXSEG7EI16_V_MF2_M1, VSUXSEG7EI16_V }, // 10033 |
29191 | | { PseudoVSUXSEG7EI16_V_MF2_M1_MASK, VSUXSEG7EI16_V }, // 10034 |
29192 | | { PseudoVSUXSEG7EI16_V_MF2_MF2, VSUXSEG7EI16_V }, // 10035 |
29193 | | { PseudoVSUXSEG7EI16_V_MF2_MF2_MASK, VSUXSEG7EI16_V }, // 10036 |
29194 | | { PseudoVSUXSEG7EI16_V_MF2_MF4, VSUXSEG7EI16_V }, // 10037 |
29195 | | { PseudoVSUXSEG7EI16_V_MF2_MF4_MASK, VSUXSEG7EI16_V }, // 10038 |
29196 | | { PseudoVSUXSEG7EI16_V_MF4_M1, VSUXSEG7EI16_V }, // 10039 |
29197 | | { PseudoVSUXSEG7EI16_V_MF4_M1_MASK, VSUXSEG7EI16_V }, // 10040 |
29198 | | { PseudoVSUXSEG7EI16_V_MF4_MF2, VSUXSEG7EI16_V }, // 10041 |
29199 | | { PseudoVSUXSEG7EI16_V_MF4_MF2_MASK, VSUXSEG7EI16_V }, // 10042 |
29200 | | { PseudoVSUXSEG7EI16_V_MF4_MF4, VSUXSEG7EI16_V }, // 10043 |
29201 | | { PseudoVSUXSEG7EI16_V_MF4_MF4_MASK, VSUXSEG7EI16_V }, // 10044 |
29202 | | { PseudoVSUXSEG7EI16_V_MF4_MF8, VSUXSEG7EI16_V }, // 10045 |
29203 | | { PseudoVSUXSEG7EI16_V_MF4_MF8_MASK, VSUXSEG7EI16_V }, // 10046 |
29204 | | { PseudoVSUXSEG7EI32_V_M1_M1, VSUXSEG7EI32_V }, // 10047 |
29205 | | { PseudoVSUXSEG7EI32_V_M1_M1_MASK, VSUXSEG7EI32_V }, // 10048 |
29206 | | { PseudoVSUXSEG7EI32_V_M1_MF2, VSUXSEG7EI32_V }, // 10049 |
29207 | | { PseudoVSUXSEG7EI32_V_M1_MF2_MASK, VSUXSEG7EI32_V }, // 10050 |
29208 | | { PseudoVSUXSEG7EI32_V_M1_MF4, VSUXSEG7EI32_V }, // 10051 |
29209 | | { PseudoVSUXSEG7EI32_V_M1_MF4_MASK, VSUXSEG7EI32_V }, // 10052 |
29210 | | { PseudoVSUXSEG7EI32_V_M2_M1, VSUXSEG7EI32_V }, // 10053 |
29211 | | { PseudoVSUXSEG7EI32_V_M2_M1_MASK, VSUXSEG7EI32_V }, // 10054 |
29212 | | { PseudoVSUXSEG7EI32_V_M2_MF2, VSUXSEG7EI32_V }, // 10055 |
29213 | | { PseudoVSUXSEG7EI32_V_M2_MF2_MASK, VSUXSEG7EI32_V }, // 10056 |
29214 | | { PseudoVSUXSEG7EI32_V_M4_M1, VSUXSEG7EI32_V }, // 10057 |
29215 | | { PseudoVSUXSEG7EI32_V_M4_M1_MASK, VSUXSEG7EI32_V }, // 10058 |
29216 | | { PseudoVSUXSEG7EI32_V_MF2_M1, VSUXSEG7EI32_V }, // 10059 |
29217 | | { PseudoVSUXSEG7EI32_V_MF2_M1_MASK, VSUXSEG7EI32_V }, // 10060 |
29218 | | { PseudoVSUXSEG7EI32_V_MF2_MF2, VSUXSEG7EI32_V }, // 10061 |
29219 | | { PseudoVSUXSEG7EI32_V_MF2_MF2_MASK, VSUXSEG7EI32_V }, // 10062 |
29220 | | { PseudoVSUXSEG7EI32_V_MF2_MF4, VSUXSEG7EI32_V }, // 10063 |
29221 | | { PseudoVSUXSEG7EI32_V_MF2_MF4_MASK, VSUXSEG7EI32_V }, // 10064 |
29222 | | { PseudoVSUXSEG7EI32_V_MF2_MF8, VSUXSEG7EI32_V }, // 10065 |
29223 | | { PseudoVSUXSEG7EI32_V_MF2_MF8_MASK, VSUXSEG7EI32_V }, // 10066 |
29224 | | { PseudoVSUXSEG7EI64_V_M1_M1, VSUXSEG7EI64_V }, // 10067 |
29225 | | { PseudoVSUXSEG7EI64_V_M1_M1_MASK, VSUXSEG7EI64_V }, // 10068 |
29226 | | { PseudoVSUXSEG7EI64_V_M1_MF2, VSUXSEG7EI64_V }, // 10069 |
29227 | | { PseudoVSUXSEG7EI64_V_M1_MF2_MASK, VSUXSEG7EI64_V }, // 10070 |
29228 | | { PseudoVSUXSEG7EI64_V_M1_MF4, VSUXSEG7EI64_V }, // 10071 |
29229 | | { PseudoVSUXSEG7EI64_V_M1_MF4_MASK, VSUXSEG7EI64_V }, // 10072 |
29230 | | { PseudoVSUXSEG7EI64_V_M1_MF8, VSUXSEG7EI64_V }, // 10073 |
29231 | | { PseudoVSUXSEG7EI64_V_M1_MF8_MASK, VSUXSEG7EI64_V }, // 10074 |
29232 | | { PseudoVSUXSEG7EI64_V_M2_M1, VSUXSEG7EI64_V }, // 10075 |
29233 | | { PseudoVSUXSEG7EI64_V_M2_M1_MASK, VSUXSEG7EI64_V }, // 10076 |
29234 | | { PseudoVSUXSEG7EI64_V_M2_MF2, VSUXSEG7EI64_V }, // 10077 |
29235 | | { PseudoVSUXSEG7EI64_V_M2_MF2_MASK, VSUXSEG7EI64_V }, // 10078 |
29236 | | { PseudoVSUXSEG7EI64_V_M2_MF4, VSUXSEG7EI64_V }, // 10079 |
29237 | | { PseudoVSUXSEG7EI64_V_M2_MF4_MASK, VSUXSEG7EI64_V }, // 10080 |
29238 | | { PseudoVSUXSEG7EI64_V_M4_M1, VSUXSEG7EI64_V }, // 10081 |
29239 | | { PseudoVSUXSEG7EI64_V_M4_M1_MASK, VSUXSEG7EI64_V }, // 10082 |
29240 | | { PseudoVSUXSEG7EI64_V_M4_MF2, VSUXSEG7EI64_V }, // 10083 |
29241 | | { PseudoVSUXSEG7EI64_V_M4_MF2_MASK, VSUXSEG7EI64_V }, // 10084 |
29242 | | { PseudoVSUXSEG7EI64_V_M8_M1, VSUXSEG7EI64_V }, // 10085 |
29243 | | { PseudoVSUXSEG7EI64_V_M8_M1_MASK, VSUXSEG7EI64_V }, // 10086 |
29244 | | { PseudoVSUXSEG7EI8_V_M1_M1, VSUXSEG7EI8_V }, // 10087 |
29245 | | { PseudoVSUXSEG7EI8_V_M1_M1_MASK, VSUXSEG7EI8_V }, // 10088 |
29246 | | { PseudoVSUXSEG7EI8_V_MF2_M1, VSUXSEG7EI8_V }, // 10089 |
29247 | | { PseudoVSUXSEG7EI8_V_MF2_M1_MASK, VSUXSEG7EI8_V }, // 10090 |
29248 | | { PseudoVSUXSEG7EI8_V_MF2_MF2, VSUXSEG7EI8_V }, // 10091 |
29249 | | { PseudoVSUXSEG7EI8_V_MF2_MF2_MASK, VSUXSEG7EI8_V }, // 10092 |
29250 | | { PseudoVSUXSEG7EI8_V_MF4_M1, VSUXSEG7EI8_V }, // 10093 |
29251 | | { PseudoVSUXSEG7EI8_V_MF4_M1_MASK, VSUXSEG7EI8_V }, // 10094 |
29252 | | { PseudoVSUXSEG7EI8_V_MF4_MF2, VSUXSEG7EI8_V }, // 10095 |
29253 | | { PseudoVSUXSEG7EI8_V_MF4_MF2_MASK, VSUXSEG7EI8_V }, // 10096 |
29254 | | { PseudoVSUXSEG7EI8_V_MF4_MF4, VSUXSEG7EI8_V }, // 10097 |
29255 | | { PseudoVSUXSEG7EI8_V_MF4_MF4_MASK, VSUXSEG7EI8_V }, // 10098 |
29256 | | { PseudoVSUXSEG7EI8_V_MF8_M1, VSUXSEG7EI8_V }, // 10099 |
29257 | | { PseudoVSUXSEG7EI8_V_MF8_M1_MASK, VSUXSEG7EI8_V }, // 10100 |
29258 | | { PseudoVSUXSEG7EI8_V_MF8_MF2, VSUXSEG7EI8_V }, // 10101 |
29259 | | { PseudoVSUXSEG7EI8_V_MF8_MF2_MASK, VSUXSEG7EI8_V }, // 10102 |
29260 | | { PseudoVSUXSEG7EI8_V_MF8_MF4, VSUXSEG7EI8_V }, // 10103 |
29261 | | { PseudoVSUXSEG7EI8_V_MF8_MF4_MASK, VSUXSEG7EI8_V }, // 10104 |
29262 | | { PseudoVSUXSEG7EI8_V_MF8_MF8, VSUXSEG7EI8_V }, // 10105 |
29263 | | { PseudoVSUXSEG7EI8_V_MF8_MF8_MASK, VSUXSEG7EI8_V }, // 10106 |
29264 | | { PseudoVSUXSEG8EI16_V_M1_M1, VSUXSEG8EI16_V }, // 10107 |
29265 | | { PseudoVSUXSEG8EI16_V_M1_M1_MASK, VSUXSEG8EI16_V }, // 10108 |
29266 | | { PseudoVSUXSEG8EI16_V_M1_MF2, VSUXSEG8EI16_V }, // 10109 |
29267 | | { PseudoVSUXSEG8EI16_V_M1_MF2_MASK, VSUXSEG8EI16_V }, // 10110 |
29268 | | { PseudoVSUXSEG8EI16_V_M2_M1, VSUXSEG8EI16_V }, // 10111 |
29269 | | { PseudoVSUXSEG8EI16_V_M2_M1_MASK, VSUXSEG8EI16_V }, // 10112 |
29270 | | { PseudoVSUXSEG8EI16_V_MF2_M1, VSUXSEG8EI16_V }, // 10113 |
29271 | | { PseudoVSUXSEG8EI16_V_MF2_M1_MASK, VSUXSEG8EI16_V }, // 10114 |
29272 | | { PseudoVSUXSEG8EI16_V_MF2_MF2, VSUXSEG8EI16_V }, // 10115 |
29273 | | { PseudoVSUXSEG8EI16_V_MF2_MF2_MASK, VSUXSEG8EI16_V }, // 10116 |
29274 | | { PseudoVSUXSEG8EI16_V_MF2_MF4, VSUXSEG8EI16_V }, // 10117 |
29275 | | { PseudoVSUXSEG8EI16_V_MF2_MF4_MASK, VSUXSEG8EI16_V }, // 10118 |
29276 | | { PseudoVSUXSEG8EI16_V_MF4_M1, VSUXSEG8EI16_V }, // 10119 |
29277 | | { PseudoVSUXSEG8EI16_V_MF4_M1_MASK, VSUXSEG8EI16_V }, // 10120 |
29278 | | { PseudoVSUXSEG8EI16_V_MF4_MF2, VSUXSEG8EI16_V }, // 10121 |
29279 | | { PseudoVSUXSEG8EI16_V_MF4_MF2_MASK, VSUXSEG8EI16_V }, // 10122 |
29280 | | { PseudoVSUXSEG8EI16_V_MF4_MF4, VSUXSEG8EI16_V }, // 10123 |
29281 | | { PseudoVSUXSEG8EI16_V_MF4_MF4_MASK, VSUXSEG8EI16_V }, // 10124 |
29282 | | { PseudoVSUXSEG8EI16_V_MF4_MF8, VSUXSEG8EI16_V }, // 10125 |
29283 | | { PseudoVSUXSEG8EI16_V_MF4_MF8_MASK, VSUXSEG8EI16_V }, // 10126 |
29284 | | { PseudoVSUXSEG8EI32_V_M1_M1, VSUXSEG8EI32_V }, // 10127 |
29285 | | { PseudoVSUXSEG8EI32_V_M1_M1_MASK, VSUXSEG8EI32_V }, // 10128 |
29286 | | { PseudoVSUXSEG8EI32_V_M1_MF2, VSUXSEG8EI32_V }, // 10129 |
29287 | | { PseudoVSUXSEG8EI32_V_M1_MF2_MASK, VSUXSEG8EI32_V }, // 10130 |
29288 | | { PseudoVSUXSEG8EI32_V_M1_MF4, VSUXSEG8EI32_V }, // 10131 |
29289 | | { PseudoVSUXSEG8EI32_V_M1_MF4_MASK, VSUXSEG8EI32_V }, // 10132 |
29290 | | { PseudoVSUXSEG8EI32_V_M2_M1, VSUXSEG8EI32_V }, // 10133 |
29291 | | { PseudoVSUXSEG8EI32_V_M2_M1_MASK, VSUXSEG8EI32_V }, // 10134 |
29292 | | { PseudoVSUXSEG8EI32_V_M2_MF2, VSUXSEG8EI32_V }, // 10135 |
29293 | | { PseudoVSUXSEG8EI32_V_M2_MF2_MASK, VSUXSEG8EI32_V }, // 10136 |
29294 | | { PseudoVSUXSEG8EI32_V_M4_M1, VSUXSEG8EI32_V }, // 10137 |
29295 | | { PseudoVSUXSEG8EI32_V_M4_M1_MASK, VSUXSEG8EI32_V }, // 10138 |
29296 | | { PseudoVSUXSEG8EI32_V_MF2_M1, VSUXSEG8EI32_V }, // 10139 |
29297 | | { PseudoVSUXSEG8EI32_V_MF2_M1_MASK, VSUXSEG8EI32_V }, // 10140 |
29298 | | { PseudoVSUXSEG8EI32_V_MF2_MF2, VSUXSEG8EI32_V }, // 10141 |
29299 | | { PseudoVSUXSEG8EI32_V_MF2_MF2_MASK, VSUXSEG8EI32_V }, // 10142 |
29300 | | { PseudoVSUXSEG8EI32_V_MF2_MF4, VSUXSEG8EI32_V }, // 10143 |
29301 | | { PseudoVSUXSEG8EI32_V_MF2_MF4_MASK, VSUXSEG8EI32_V }, // 10144 |
29302 | | { PseudoVSUXSEG8EI32_V_MF2_MF8, VSUXSEG8EI32_V }, // 10145 |
29303 | | { PseudoVSUXSEG8EI32_V_MF2_MF8_MASK, VSUXSEG8EI32_V }, // 10146 |
29304 | | { PseudoVSUXSEG8EI64_V_M1_M1, VSUXSEG8EI64_V }, // 10147 |
29305 | | { PseudoVSUXSEG8EI64_V_M1_M1_MASK, VSUXSEG8EI64_V }, // 10148 |
29306 | | { PseudoVSUXSEG8EI64_V_M1_MF2, VSUXSEG8EI64_V }, // 10149 |
29307 | | { PseudoVSUXSEG8EI64_V_M1_MF2_MASK, VSUXSEG8EI64_V }, // 10150 |
29308 | | { PseudoVSUXSEG8EI64_V_M1_MF4, VSUXSEG8EI64_V }, // 10151 |
29309 | | { PseudoVSUXSEG8EI64_V_M1_MF4_MASK, VSUXSEG8EI64_V }, // 10152 |
29310 | | { PseudoVSUXSEG8EI64_V_M1_MF8, VSUXSEG8EI64_V }, // 10153 |
29311 | | { PseudoVSUXSEG8EI64_V_M1_MF8_MASK, VSUXSEG8EI64_V }, // 10154 |
29312 | | { PseudoVSUXSEG8EI64_V_M2_M1, VSUXSEG8EI64_V }, // 10155 |
29313 | | { PseudoVSUXSEG8EI64_V_M2_M1_MASK, VSUXSEG8EI64_V }, // 10156 |
29314 | | { PseudoVSUXSEG8EI64_V_M2_MF2, VSUXSEG8EI64_V }, // 10157 |
29315 | | { PseudoVSUXSEG8EI64_V_M2_MF2_MASK, VSUXSEG8EI64_V }, // 10158 |
29316 | | { PseudoVSUXSEG8EI64_V_M2_MF4, VSUXSEG8EI64_V }, // 10159 |
29317 | | { PseudoVSUXSEG8EI64_V_M2_MF4_MASK, VSUXSEG8EI64_V }, // 10160 |
29318 | | { PseudoVSUXSEG8EI64_V_M4_M1, VSUXSEG8EI64_V }, // 10161 |
29319 | | { PseudoVSUXSEG8EI64_V_M4_M1_MASK, VSUXSEG8EI64_V }, // 10162 |
29320 | | { PseudoVSUXSEG8EI64_V_M4_MF2, VSUXSEG8EI64_V }, // 10163 |
29321 | | { PseudoVSUXSEG8EI64_V_M4_MF2_MASK, VSUXSEG8EI64_V }, // 10164 |
29322 | | { PseudoVSUXSEG8EI64_V_M8_M1, VSUXSEG8EI64_V }, // 10165 |
29323 | | { PseudoVSUXSEG8EI64_V_M8_M1_MASK, VSUXSEG8EI64_V }, // 10166 |
29324 | | { PseudoVSUXSEG8EI8_V_M1_M1, VSUXSEG8EI8_V }, // 10167 |
29325 | | { PseudoVSUXSEG8EI8_V_M1_M1_MASK, VSUXSEG8EI8_V }, // 10168 |
29326 | | { PseudoVSUXSEG8EI8_V_MF2_M1, VSUXSEG8EI8_V }, // 10169 |
29327 | | { PseudoVSUXSEG8EI8_V_MF2_M1_MASK, VSUXSEG8EI8_V }, // 10170 |
29328 | | { PseudoVSUXSEG8EI8_V_MF2_MF2, VSUXSEG8EI8_V }, // 10171 |
29329 | | { PseudoVSUXSEG8EI8_V_MF2_MF2_MASK, VSUXSEG8EI8_V }, // 10172 |
29330 | | { PseudoVSUXSEG8EI8_V_MF4_M1, VSUXSEG8EI8_V }, // 10173 |
29331 | | { PseudoVSUXSEG8EI8_V_MF4_M1_MASK, VSUXSEG8EI8_V }, // 10174 |
29332 | | { PseudoVSUXSEG8EI8_V_MF4_MF2, VSUXSEG8EI8_V }, // 10175 |
29333 | | { PseudoVSUXSEG8EI8_V_MF4_MF2_MASK, VSUXSEG8EI8_V }, // 10176 |
29334 | | { PseudoVSUXSEG8EI8_V_MF4_MF4, VSUXSEG8EI8_V }, // 10177 |
29335 | | { PseudoVSUXSEG8EI8_V_MF4_MF4_MASK, VSUXSEG8EI8_V }, // 10178 |
29336 | | { PseudoVSUXSEG8EI8_V_MF8_M1, VSUXSEG8EI8_V }, // 10179 |
29337 | | { PseudoVSUXSEG8EI8_V_MF8_M1_MASK, VSUXSEG8EI8_V }, // 10180 |
29338 | | { PseudoVSUXSEG8EI8_V_MF8_MF2, VSUXSEG8EI8_V }, // 10181 |
29339 | | { PseudoVSUXSEG8EI8_V_MF8_MF2_MASK, VSUXSEG8EI8_V }, // 10182 |
29340 | | { PseudoVSUXSEG8EI8_V_MF8_MF4, VSUXSEG8EI8_V }, // 10183 |
29341 | | { PseudoVSUXSEG8EI8_V_MF8_MF4_MASK, VSUXSEG8EI8_V }, // 10184 |
29342 | | { PseudoVSUXSEG8EI8_V_MF8_MF8, VSUXSEG8EI8_V }, // 10185 |
29343 | | { PseudoVSUXSEG8EI8_V_MF8_MF8_MASK, VSUXSEG8EI8_V }, // 10186 |
29344 | | { PseudoVWADDU_VV_M1, VWADDU_VV }, // 10187 |
29345 | | { PseudoVWADDU_VV_M1_MASK, VWADDU_VV }, // 10188 |
29346 | | { PseudoVWADDU_VV_M2, VWADDU_VV }, // 10189 |
29347 | | { PseudoVWADDU_VV_M2_MASK, VWADDU_VV }, // 10190 |
29348 | | { PseudoVWADDU_VV_M4, VWADDU_VV }, // 10191 |
29349 | | { PseudoVWADDU_VV_M4_MASK, VWADDU_VV }, // 10192 |
29350 | | { PseudoVWADDU_VV_MF2, VWADDU_VV }, // 10193 |
29351 | | { PseudoVWADDU_VV_MF2_MASK, VWADDU_VV }, // 10194 |
29352 | | { PseudoVWADDU_VV_MF4, VWADDU_VV }, // 10195 |
29353 | | { PseudoVWADDU_VV_MF4_MASK, VWADDU_VV }, // 10196 |
29354 | | { PseudoVWADDU_VV_MF8, VWADDU_VV }, // 10197 |
29355 | | { PseudoVWADDU_VV_MF8_MASK, VWADDU_VV }, // 10198 |
29356 | | { PseudoVWADDU_VX_M1, VWADDU_VX }, // 10199 |
29357 | | { PseudoVWADDU_VX_M1_MASK, VWADDU_VX }, // 10200 |
29358 | | { PseudoVWADDU_VX_M2, VWADDU_VX }, // 10201 |
29359 | | { PseudoVWADDU_VX_M2_MASK, VWADDU_VX }, // 10202 |
29360 | | { PseudoVWADDU_VX_M4, VWADDU_VX }, // 10203 |
29361 | | { PseudoVWADDU_VX_M4_MASK, VWADDU_VX }, // 10204 |
29362 | | { PseudoVWADDU_VX_MF2, VWADDU_VX }, // 10205 |
29363 | | { PseudoVWADDU_VX_MF2_MASK, VWADDU_VX }, // 10206 |
29364 | | { PseudoVWADDU_VX_MF4, VWADDU_VX }, // 10207 |
29365 | | { PseudoVWADDU_VX_MF4_MASK, VWADDU_VX }, // 10208 |
29366 | | { PseudoVWADDU_VX_MF8, VWADDU_VX }, // 10209 |
29367 | | { PseudoVWADDU_VX_MF8_MASK, VWADDU_VX }, // 10210 |
29368 | | { PseudoVWADDU_WV_M1, VWADDU_WV }, // 10211 |
29369 | | { PseudoVWADDU_WV_M1_MASK, VWADDU_WV }, // 10212 |
29370 | | { PseudoVWADDU_WV_M1_MASK_TIED, VWADDU_WV }, // 10213 |
29371 | | { PseudoVWADDU_WV_M1_TIED, VWADDU_WV }, // 10214 |
29372 | | { PseudoVWADDU_WV_M2, VWADDU_WV }, // 10215 |
29373 | | { PseudoVWADDU_WV_M2_MASK, VWADDU_WV }, // 10216 |
29374 | | { PseudoVWADDU_WV_M2_MASK_TIED, VWADDU_WV }, // 10217 |
29375 | | { PseudoVWADDU_WV_M2_TIED, VWADDU_WV }, // 10218 |
29376 | | { PseudoVWADDU_WV_M4, VWADDU_WV }, // 10219 |
29377 | | { PseudoVWADDU_WV_M4_MASK, VWADDU_WV }, // 10220 |
29378 | | { PseudoVWADDU_WV_M4_MASK_TIED, VWADDU_WV }, // 10221 |
29379 | | { PseudoVWADDU_WV_M4_TIED, VWADDU_WV }, // 10222 |
29380 | | { PseudoVWADDU_WV_MF2, VWADDU_WV }, // 10223 |
29381 | | { PseudoVWADDU_WV_MF2_MASK, VWADDU_WV }, // 10224 |
29382 | | { PseudoVWADDU_WV_MF2_MASK_TIED, VWADDU_WV }, // 10225 |
29383 | | { PseudoVWADDU_WV_MF2_TIED, VWADDU_WV }, // 10226 |
29384 | | { PseudoVWADDU_WV_MF4, VWADDU_WV }, // 10227 |
29385 | | { PseudoVWADDU_WV_MF4_MASK, VWADDU_WV }, // 10228 |
29386 | | { PseudoVWADDU_WV_MF4_MASK_TIED, VWADDU_WV }, // 10229 |
29387 | | { PseudoVWADDU_WV_MF4_TIED, VWADDU_WV }, // 10230 |
29388 | | { PseudoVWADDU_WV_MF8, VWADDU_WV }, // 10231 |
29389 | | { PseudoVWADDU_WV_MF8_MASK, VWADDU_WV }, // 10232 |
29390 | | { PseudoVWADDU_WV_MF8_MASK_TIED, VWADDU_WV }, // 10233 |
29391 | | { PseudoVWADDU_WV_MF8_TIED, VWADDU_WV }, // 10234 |
29392 | | { PseudoVWADDU_WX_M1, VWADDU_WX }, // 10235 |
29393 | | { PseudoVWADDU_WX_M1_MASK, VWADDU_WX }, // 10236 |
29394 | | { PseudoVWADDU_WX_M2, VWADDU_WX }, // 10237 |
29395 | | { PseudoVWADDU_WX_M2_MASK, VWADDU_WX }, // 10238 |
29396 | | { PseudoVWADDU_WX_M4, VWADDU_WX }, // 10239 |
29397 | | { PseudoVWADDU_WX_M4_MASK, VWADDU_WX }, // 10240 |
29398 | | { PseudoVWADDU_WX_MF2, VWADDU_WX }, // 10241 |
29399 | | { PseudoVWADDU_WX_MF2_MASK, VWADDU_WX }, // 10242 |
29400 | | { PseudoVWADDU_WX_MF4, VWADDU_WX }, // 10243 |
29401 | | { PseudoVWADDU_WX_MF4_MASK, VWADDU_WX }, // 10244 |
29402 | | { PseudoVWADDU_WX_MF8, VWADDU_WX }, // 10245 |
29403 | | { PseudoVWADDU_WX_MF8_MASK, VWADDU_WX }, // 10246 |
29404 | | { PseudoVWADD_VV_M1, VWADD_VV }, // 10247 |
29405 | | { PseudoVWADD_VV_M1_MASK, VWADD_VV }, // 10248 |
29406 | | { PseudoVWADD_VV_M2, VWADD_VV }, // 10249 |
29407 | | { PseudoVWADD_VV_M2_MASK, VWADD_VV }, // 10250 |
29408 | | { PseudoVWADD_VV_M4, VWADD_VV }, // 10251 |
29409 | | { PseudoVWADD_VV_M4_MASK, VWADD_VV }, // 10252 |
29410 | | { PseudoVWADD_VV_MF2, VWADD_VV }, // 10253 |
29411 | | { PseudoVWADD_VV_MF2_MASK, VWADD_VV }, // 10254 |
29412 | | { PseudoVWADD_VV_MF4, VWADD_VV }, // 10255 |
29413 | | { PseudoVWADD_VV_MF4_MASK, VWADD_VV }, // 10256 |
29414 | | { PseudoVWADD_VV_MF8, VWADD_VV }, // 10257 |
29415 | | { PseudoVWADD_VV_MF8_MASK, VWADD_VV }, // 10258 |
29416 | | { PseudoVWADD_VX_M1, VWADD_VX }, // 10259 |
29417 | | { PseudoVWADD_VX_M1_MASK, VWADD_VX }, // 10260 |
29418 | | { PseudoVWADD_VX_M2, VWADD_VX }, // 10261 |
29419 | | { PseudoVWADD_VX_M2_MASK, VWADD_VX }, // 10262 |
29420 | | { PseudoVWADD_VX_M4, VWADD_VX }, // 10263 |
29421 | | { PseudoVWADD_VX_M4_MASK, VWADD_VX }, // 10264 |
29422 | | { PseudoVWADD_VX_MF2, VWADD_VX }, // 10265 |
29423 | | { PseudoVWADD_VX_MF2_MASK, VWADD_VX }, // 10266 |
29424 | | { PseudoVWADD_VX_MF4, VWADD_VX }, // 10267 |
29425 | | { PseudoVWADD_VX_MF4_MASK, VWADD_VX }, // 10268 |
29426 | | { PseudoVWADD_VX_MF8, VWADD_VX }, // 10269 |
29427 | | { PseudoVWADD_VX_MF8_MASK, VWADD_VX }, // 10270 |
29428 | | { PseudoVWADD_WV_M1, VWADD_WV }, // 10271 |
29429 | | { PseudoVWADD_WV_M1_MASK, VWADD_WV }, // 10272 |
29430 | | { PseudoVWADD_WV_M1_MASK_TIED, VWADD_WV }, // 10273 |
29431 | | { PseudoVWADD_WV_M1_TIED, VWADD_WV }, // 10274 |
29432 | | { PseudoVWADD_WV_M2, VWADD_WV }, // 10275 |
29433 | | { PseudoVWADD_WV_M2_MASK, VWADD_WV }, // 10276 |
29434 | | { PseudoVWADD_WV_M2_MASK_TIED, VWADD_WV }, // 10277 |
29435 | | { PseudoVWADD_WV_M2_TIED, VWADD_WV }, // 10278 |
29436 | | { PseudoVWADD_WV_M4, VWADD_WV }, // 10279 |
29437 | | { PseudoVWADD_WV_M4_MASK, VWADD_WV }, // 10280 |
29438 | | { PseudoVWADD_WV_M4_MASK_TIED, VWADD_WV }, // 10281 |
29439 | | { PseudoVWADD_WV_M4_TIED, VWADD_WV }, // 10282 |
29440 | | { PseudoVWADD_WV_MF2, VWADD_WV }, // 10283 |
29441 | | { PseudoVWADD_WV_MF2_MASK, VWADD_WV }, // 10284 |
29442 | | { PseudoVWADD_WV_MF2_MASK_TIED, VWADD_WV }, // 10285 |
29443 | | { PseudoVWADD_WV_MF2_TIED, VWADD_WV }, // 10286 |
29444 | | { PseudoVWADD_WV_MF4, VWADD_WV }, // 10287 |
29445 | | { PseudoVWADD_WV_MF4_MASK, VWADD_WV }, // 10288 |
29446 | | { PseudoVWADD_WV_MF4_MASK_TIED, VWADD_WV }, // 10289 |
29447 | | { PseudoVWADD_WV_MF4_TIED, VWADD_WV }, // 10290 |
29448 | | { PseudoVWADD_WV_MF8, VWADD_WV }, // 10291 |
29449 | | { PseudoVWADD_WV_MF8_MASK, VWADD_WV }, // 10292 |
29450 | | { PseudoVWADD_WV_MF8_MASK_TIED, VWADD_WV }, // 10293 |
29451 | | { PseudoVWADD_WV_MF8_TIED, VWADD_WV }, // 10294 |
29452 | | { PseudoVWADD_WX_M1, VWADD_WX }, // 10295 |
29453 | | { PseudoVWADD_WX_M1_MASK, VWADD_WX }, // 10296 |
29454 | | { PseudoVWADD_WX_M2, VWADD_WX }, // 10297 |
29455 | | { PseudoVWADD_WX_M2_MASK, VWADD_WX }, // 10298 |
29456 | | { PseudoVWADD_WX_M4, VWADD_WX }, // 10299 |
29457 | | { PseudoVWADD_WX_M4_MASK, VWADD_WX }, // 10300 |
29458 | | { PseudoVWADD_WX_MF2, VWADD_WX }, // 10301 |
29459 | | { PseudoVWADD_WX_MF2_MASK, VWADD_WX }, // 10302 |
29460 | | { PseudoVWADD_WX_MF4, VWADD_WX }, // 10303 |
29461 | | { PseudoVWADD_WX_MF4_MASK, VWADD_WX }, // 10304 |
29462 | | { PseudoVWADD_WX_MF8, VWADD_WX }, // 10305 |
29463 | | { PseudoVWADD_WX_MF8_MASK, VWADD_WX }, // 10306 |
29464 | | { PseudoVWMACCSU_VV_M1, VWMACCSU_VV }, // 10307 |
29465 | | { PseudoVWMACCSU_VV_M1_MASK, VWMACCSU_VV }, // 10308 |
29466 | | { PseudoVWMACCSU_VV_M2, VWMACCSU_VV }, // 10309 |
29467 | | { PseudoVWMACCSU_VV_M2_MASK, VWMACCSU_VV }, // 10310 |
29468 | | { PseudoVWMACCSU_VV_M4, VWMACCSU_VV }, // 10311 |
29469 | | { PseudoVWMACCSU_VV_M4_MASK, VWMACCSU_VV }, // 10312 |
29470 | | { PseudoVWMACCSU_VV_MF2, VWMACCSU_VV }, // 10313 |
29471 | | { PseudoVWMACCSU_VV_MF2_MASK, VWMACCSU_VV }, // 10314 |
29472 | | { PseudoVWMACCSU_VV_MF4, VWMACCSU_VV }, // 10315 |
29473 | | { PseudoVWMACCSU_VV_MF4_MASK, VWMACCSU_VV }, // 10316 |
29474 | | { PseudoVWMACCSU_VV_MF8, VWMACCSU_VV }, // 10317 |
29475 | | { PseudoVWMACCSU_VV_MF8_MASK, VWMACCSU_VV }, // 10318 |
29476 | | { PseudoVWMACCSU_VX_M1, VWMACCSU_VX }, // 10319 |
29477 | | { PseudoVWMACCSU_VX_M1_MASK, VWMACCSU_VX }, // 10320 |
29478 | | { PseudoVWMACCSU_VX_M2, VWMACCSU_VX }, // 10321 |
29479 | | { PseudoVWMACCSU_VX_M2_MASK, VWMACCSU_VX }, // 10322 |
29480 | | { PseudoVWMACCSU_VX_M4, VWMACCSU_VX }, // 10323 |
29481 | | { PseudoVWMACCSU_VX_M4_MASK, VWMACCSU_VX }, // 10324 |
29482 | | { PseudoVWMACCSU_VX_MF2, VWMACCSU_VX }, // 10325 |
29483 | | { PseudoVWMACCSU_VX_MF2_MASK, VWMACCSU_VX }, // 10326 |
29484 | | { PseudoVWMACCSU_VX_MF4, VWMACCSU_VX }, // 10327 |
29485 | | { PseudoVWMACCSU_VX_MF4_MASK, VWMACCSU_VX }, // 10328 |
29486 | | { PseudoVWMACCSU_VX_MF8, VWMACCSU_VX }, // 10329 |
29487 | | { PseudoVWMACCSU_VX_MF8_MASK, VWMACCSU_VX }, // 10330 |
29488 | | { PseudoVWMACCUS_VX_M1, VWMACCUS_VX }, // 10331 |
29489 | | { PseudoVWMACCUS_VX_M1_MASK, VWMACCUS_VX }, // 10332 |
29490 | | { PseudoVWMACCUS_VX_M2, VWMACCUS_VX }, // 10333 |
29491 | | { PseudoVWMACCUS_VX_M2_MASK, VWMACCUS_VX }, // 10334 |
29492 | | { PseudoVWMACCUS_VX_M4, VWMACCUS_VX }, // 10335 |
29493 | | { PseudoVWMACCUS_VX_M4_MASK, VWMACCUS_VX }, // 10336 |
29494 | | { PseudoVWMACCUS_VX_MF2, VWMACCUS_VX }, // 10337 |
29495 | | { PseudoVWMACCUS_VX_MF2_MASK, VWMACCUS_VX }, // 10338 |
29496 | | { PseudoVWMACCUS_VX_MF4, VWMACCUS_VX }, // 10339 |
29497 | | { PseudoVWMACCUS_VX_MF4_MASK, VWMACCUS_VX }, // 10340 |
29498 | | { PseudoVWMACCUS_VX_MF8, VWMACCUS_VX }, // 10341 |
29499 | | { PseudoVWMACCUS_VX_MF8_MASK, VWMACCUS_VX }, // 10342 |
29500 | | { PseudoVWMACCU_VV_M1, VWMACCU_VV }, // 10343 |
29501 | | { PseudoVWMACCU_VV_M1_MASK, VWMACCU_VV }, // 10344 |
29502 | | { PseudoVWMACCU_VV_M2, VWMACCU_VV }, // 10345 |
29503 | | { PseudoVWMACCU_VV_M2_MASK, VWMACCU_VV }, // 10346 |
29504 | | { PseudoVWMACCU_VV_M4, VWMACCU_VV }, // 10347 |
29505 | | { PseudoVWMACCU_VV_M4_MASK, VWMACCU_VV }, // 10348 |
29506 | | { PseudoVWMACCU_VV_MF2, VWMACCU_VV }, // 10349 |
29507 | | { PseudoVWMACCU_VV_MF2_MASK, VWMACCU_VV }, // 10350 |
29508 | | { PseudoVWMACCU_VV_MF4, VWMACCU_VV }, // 10351 |
29509 | | { PseudoVWMACCU_VV_MF4_MASK, VWMACCU_VV }, // 10352 |
29510 | | { PseudoVWMACCU_VV_MF8, VWMACCU_VV }, // 10353 |
29511 | | { PseudoVWMACCU_VV_MF8_MASK, VWMACCU_VV }, // 10354 |
29512 | | { PseudoVWMACCU_VX_M1, VWMACCU_VX }, // 10355 |
29513 | | { PseudoVWMACCU_VX_M1_MASK, VWMACCU_VX }, // 10356 |
29514 | | { PseudoVWMACCU_VX_M2, VWMACCU_VX }, // 10357 |
29515 | | { PseudoVWMACCU_VX_M2_MASK, VWMACCU_VX }, // 10358 |
29516 | | { PseudoVWMACCU_VX_M4, VWMACCU_VX }, // 10359 |
29517 | | { PseudoVWMACCU_VX_M4_MASK, VWMACCU_VX }, // 10360 |
29518 | | { PseudoVWMACCU_VX_MF2, VWMACCU_VX }, // 10361 |
29519 | | { PseudoVWMACCU_VX_MF2_MASK, VWMACCU_VX }, // 10362 |
29520 | | { PseudoVWMACCU_VX_MF4, VWMACCU_VX }, // 10363 |
29521 | | { PseudoVWMACCU_VX_MF4_MASK, VWMACCU_VX }, // 10364 |
29522 | | { PseudoVWMACCU_VX_MF8, VWMACCU_VX }, // 10365 |
29523 | | { PseudoVWMACCU_VX_MF8_MASK, VWMACCU_VX }, // 10366 |
29524 | | { PseudoVWMACC_VV_M1, VWMACC_VV }, // 10367 |
29525 | | { PseudoVWMACC_VV_M1_MASK, VWMACC_VV }, // 10368 |
29526 | | { PseudoVWMACC_VV_M2, VWMACC_VV }, // 10369 |
29527 | | { PseudoVWMACC_VV_M2_MASK, VWMACC_VV }, // 10370 |
29528 | | { PseudoVWMACC_VV_M4, VWMACC_VV }, // 10371 |
29529 | | { PseudoVWMACC_VV_M4_MASK, VWMACC_VV }, // 10372 |
29530 | | { PseudoVWMACC_VV_MF2, VWMACC_VV }, // 10373 |
29531 | | { PseudoVWMACC_VV_MF2_MASK, VWMACC_VV }, // 10374 |
29532 | | { PseudoVWMACC_VV_MF4, VWMACC_VV }, // 10375 |
29533 | | { PseudoVWMACC_VV_MF4_MASK, VWMACC_VV }, // 10376 |
29534 | | { PseudoVWMACC_VV_MF8, VWMACC_VV }, // 10377 |
29535 | | { PseudoVWMACC_VV_MF8_MASK, VWMACC_VV }, // 10378 |
29536 | | { PseudoVWMACC_VX_M1, VWMACC_VX }, // 10379 |
29537 | | { PseudoVWMACC_VX_M1_MASK, VWMACC_VX }, // 10380 |
29538 | | { PseudoVWMACC_VX_M2, VWMACC_VX }, // 10381 |
29539 | | { PseudoVWMACC_VX_M2_MASK, VWMACC_VX }, // 10382 |
29540 | | { PseudoVWMACC_VX_M4, VWMACC_VX }, // 10383 |
29541 | | { PseudoVWMACC_VX_M4_MASK, VWMACC_VX }, // 10384 |
29542 | | { PseudoVWMACC_VX_MF2, VWMACC_VX }, // 10385 |
29543 | | { PseudoVWMACC_VX_MF2_MASK, VWMACC_VX }, // 10386 |
29544 | | { PseudoVWMACC_VX_MF4, VWMACC_VX }, // 10387 |
29545 | | { PseudoVWMACC_VX_MF4_MASK, VWMACC_VX }, // 10388 |
29546 | | { PseudoVWMACC_VX_MF8, VWMACC_VX }, // 10389 |
29547 | | { PseudoVWMACC_VX_MF8_MASK, VWMACC_VX }, // 10390 |
29548 | | { PseudoVWMULSU_VV_M1, VWMULSU_VV }, // 10391 |
29549 | | { PseudoVWMULSU_VV_M1_MASK, VWMULSU_VV }, // 10392 |
29550 | | { PseudoVWMULSU_VV_M2, VWMULSU_VV }, // 10393 |
29551 | | { PseudoVWMULSU_VV_M2_MASK, VWMULSU_VV }, // 10394 |
29552 | | { PseudoVWMULSU_VV_M4, VWMULSU_VV }, // 10395 |
29553 | | { PseudoVWMULSU_VV_M4_MASK, VWMULSU_VV }, // 10396 |
29554 | | { PseudoVWMULSU_VV_MF2, VWMULSU_VV }, // 10397 |
29555 | | { PseudoVWMULSU_VV_MF2_MASK, VWMULSU_VV }, // 10398 |
29556 | | { PseudoVWMULSU_VV_MF4, VWMULSU_VV }, // 10399 |
29557 | | { PseudoVWMULSU_VV_MF4_MASK, VWMULSU_VV }, // 10400 |
29558 | | { PseudoVWMULSU_VV_MF8, VWMULSU_VV }, // 10401 |
29559 | | { PseudoVWMULSU_VV_MF8_MASK, VWMULSU_VV }, // 10402 |
29560 | | { PseudoVWMULSU_VX_M1, VWMULSU_VX }, // 10403 |
29561 | | { PseudoVWMULSU_VX_M1_MASK, VWMULSU_VX }, // 10404 |
29562 | | { PseudoVWMULSU_VX_M2, VWMULSU_VX }, // 10405 |
29563 | | { PseudoVWMULSU_VX_M2_MASK, VWMULSU_VX }, // 10406 |
29564 | | { PseudoVWMULSU_VX_M4, VWMULSU_VX }, // 10407 |
29565 | | { PseudoVWMULSU_VX_M4_MASK, VWMULSU_VX }, // 10408 |
29566 | | { PseudoVWMULSU_VX_MF2, VWMULSU_VX }, // 10409 |
29567 | | { PseudoVWMULSU_VX_MF2_MASK, VWMULSU_VX }, // 10410 |
29568 | | { PseudoVWMULSU_VX_MF4, VWMULSU_VX }, // 10411 |
29569 | | { PseudoVWMULSU_VX_MF4_MASK, VWMULSU_VX }, // 10412 |
29570 | | { PseudoVWMULSU_VX_MF8, VWMULSU_VX }, // 10413 |
29571 | | { PseudoVWMULSU_VX_MF8_MASK, VWMULSU_VX }, // 10414 |
29572 | | { PseudoVWMULU_VV_M1, VWMULU_VV }, // 10415 |
29573 | | { PseudoVWMULU_VV_M1_MASK, VWMULU_VV }, // 10416 |
29574 | | { PseudoVWMULU_VV_M2, VWMULU_VV }, // 10417 |
29575 | | { PseudoVWMULU_VV_M2_MASK, VWMULU_VV }, // 10418 |
29576 | | { PseudoVWMULU_VV_M4, VWMULU_VV }, // 10419 |
29577 | | { PseudoVWMULU_VV_M4_MASK, VWMULU_VV }, // 10420 |
29578 | | { PseudoVWMULU_VV_MF2, VWMULU_VV }, // 10421 |
29579 | | { PseudoVWMULU_VV_MF2_MASK, VWMULU_VV }, // 10422 |
29580 | | { PseudoVWMULU_VV_MF4, VWMULU_VV }, // 10423 |
29581 | | { PseudoVWMULU_VV_MF4_MASK, VWMULU_VV }, // 10424 |
29582 | | { PseudoVWMULU_VV_MF8, VWMULU_VV }, // 10425 |
29583 | | { PseudoVWMULU_VV_MF8_MASK, VWMULU_VV }, // 10426 |
29584 | | { PseudoVWMULU_VX_M1, VWMULU_VX }, // 10427 |
29585 | | { PseudoVWMULU_VX_M1_MASK, VWMULU_VX }, // 10428 |
29586 | | { PseudoVWMULU_VX_M2, VWMULU_VX }, // 10429 |
29587 | | { PseudoVWMULU_VX_M2_MASK, VWMULU_VX }, // 10430 |
29588 | | { PseudoVWMULU_VX_M4, VWMULU_VX }, // 10431 |
29589 | | { PseudoVWMULU_VX_M4_MASK, VWMULU_VX }, // 10432 |
29590 | | { PseudoVWMULU_VX_MF2, VWMULU_VX }, // 10433 |
29591 | | { PseudoVWMULU_VX_MF2_MASK, VWMULU_VX }, // 10434 |
29592 | | { PseudoVWMULU_VX_MF4, VWMULU_VX }, // 10435 |
29593 | | { PseudoVWMULU_VX_MF4_MASK, VWMULU_VX }, // 10436 |
29594 | | { PseudoVWMULU_VX_MF8, VWMULU_VX }, // 10437 |
29595 | | { PseudoVWMULU_VX_MF8_MASK, VWMULU_VX }, // 10438 |
29596 | | { PseudoVWMUL_VV_M1, VWMUL_VV }, // 10439 |
29597 | | { PseudoVWMUL_VV_M1_MASK, VWMUL_VV }, // 10440 |
29598 | | { PseudoVWMUL_VV_M2, VWMUL_VV }, // 10441 |
29599 | | { PseudoVWMUL_VV_M2_MASK, VWMUL_VV }, // 10442 |
29600 | | { PseudoVWMUL_VV_M4, VWMUL_VV }, // 10443 |
29601 | | { PseudoVWMUL_VV_M4_MASK, VWMUL_VV }, // 10444 |
29602 | | { PseudoVWMUL_VV_MF2, VWMUL_VV }, // 10445 |
29603 | | { PseudoVWMUL_VV_MF2_MASK, VWMUL_VV }, // 10446 |
29604 | | { PseudoVWMUL_VV_MF4, VWMUL_VV }, // 10447 |
29605 | | { PseudoVWMUL_VV_MF4_MASK, VWMUL_VV }, // 10448 |
29606 | | { PseudoVWMUL_VV_MF8, VWMUL_VV }, // 10449 |
29607 | | { PseudoVWMUL_VV_MF8_MASK, VWMUL_VV }, // 10450 |
29608 | | { PseudoVWMUL_VX_M1, VWMUL_VX }, // 10451 |
29609 | | { PseudoVWMUL_VX_M1_MASK, VWMUL_VX }, // 10452 |
29610 | | { PseudoVWMUL_VX_M2, VWMUL_VX }, // 10453 |
29611 | | { PseudoVWMUL_VX_M2_MASK, VWMUL_VX }, // 10454 |
29612 | | { PseudoVWMUL_VX_M4, VWMUL_VX }, // 10455 |
29613 | | { PseudoVWMUL_VX_M4_MASK, VWMUL_VX }, // 10456 |
29614 | | { PseudoVWMUL_VX_MF2, VWMUL_VX }, // 10457 |
29615 | | { PseudoVWMUL_VX_MF2_MASK, VWMUL_VX }, // 10458 |
29616 | | { PseudoVWMUL_VX_MF4, VWMUL_VX }, // 10459 |
29617 | | { PseudoVWMUL_VX_MF4_MASK, VWMUL_VX }, // 10460 |
29618 | | { PseudoVWMUL_VX_MF8, VWMUL_VX }, // 10461 |
29619 | | { PseudoVWMUL_VX_MF8_MASK, VWMUL_VX }, // 10462 |
29620 | | { PseudoVWREDSUMU_VS_M1_E16, VWREDSUMU_VS }, // 10463 |
29621 | | { PseudoVWREDSUMU_VS_M1_E16_MASK, VWREDSUMU_VS }, // 10464 |
29622 | | { PseudoVWREDSUMU_VS_M1_E32, VWREDSUMU_VS }, // 10465 |
29623 | | { PseudoVWREDSUMU_VS_M1_E32_MASK, VWREDSUMU_VS }, // 10466 |
29624 | | { PseudoVWREDSUMU_VS_M1_E8, VWREDSUMU_VS }, // 10467 |
29625 | | { PseudoVWREDSUMU_VS_M1_E8_MASK, VWREDSUMU_VS }, // 10468 |
29626 | | { PseudoVWREDSUMU_VS_M2_E16, VWREDSUMU_VS }, // 10469 |
29627 | | { PseudoVWREDSUMU_VS_M2_E16_MASK, VWREDSUMU_VS }, // 10470 |
29628 | | { PseudoVWREDSUMU_VS_M2_E32, VWREDSUMU_VS }, // 10471 |
29629 | | { PseudoVWREDSUMU_VS_M2_E32_MASK, VWREDSUMU_VS }, // 10472 |
29630 | | { PseudoVWREDSUMU_VS_M2_E8, VWREDSUMU_VS }, // 10473 |
29631 | | { PseudoVWREDSUMU_VS_M2_E8_MASK, VWREDSUMU_VS }, // 10474 |
29632 | | { PseudoVWREDSUMU_VS_M4_E16, VWREDSUMU_VS }, // 10475 |
29633 | | { PseudoVWREDSUMU_VS_M4_E16_MASK, VWREDSUMU_VS }, // 10476 |
29634 | | { PseudoVWREDSUMU_VS_M4_E32, VWREDSUMU_VS }, // 10477 |
29635 | | { PseudoVWREDSUMU_VS_M4_E32_MASK, VWREDSUMU_VS }, // 10478 |
29636 | | { PseudoVWREDSUMU_VS_M4_E8, VWREDSUMU_VS }, // 10479 |
29637 | | { PseudoVWREDSUMU_VS_M4_E8_MASK, VWREDSUMU_VS }, // 10480 |
29638 | | { PseudoVWREDSUMU_VS_M8_E16, VWREDSUMU_VS }, // 10481 |
29639 | | { PseudoVWREDSUMU_VS_M8_E16_MASK, VWREDSUMU_VS }, // 10482 |
29640 | | { PseudoVWREDSUMU_VS_M8_E32, VWREDSUMU_VS }, // 10483 |
29641 | | { PseudoVWREDSUMU_VS_M8_E32_MASK, VWREDSUMU_VS }, // 10484 |
29642 | | { PseudoVWREDSUMU_VS_M8_E8, VWREDSUMU_VS }, // 10485 |
29643 | | { PseudoVWREDSUMU_VS_M8_E8_MASK, VWREDSUMU_VS }, // 10486 |
29644 | | { PseudoVWREDSUMU_VS_MF2_E16, VWREDSUMU_VS }, // 10487 |
29645 | | { PseudoVWREDSUMU_VS_MF2_E16_MASK, VWREDSUMU_VS }, // 10488 |
29646 | | { PseudoVWREDSUMU_VS_MF2_E32, VWREDSUMU_VS }, // 10489 |
29647 | | { PseudoVWREDSUMU_VS_MF2_E32_MASK, VWREDSUMU_VS }, // 10490 |
29648 | | { PseudoVWREDSUMU_VS_MF2_E8, VWREDSUMU_VS }, // 10491 |
29649 | | { PseudoVWREDSUMU_VS_MF2_E8_MASK, VWREDSUMU_VS }, // 10492 |
29650 | | { PseudoVWREDSUMU_VS_MF4_E16, VWREDSUMU_VS }, // 10493 |
29651 | | { PseudoVWREDSUMU_VS_MF4_E16_MASK, VWREDSUMU_VS }, // 10494 |
29652 | | { PseudoVWREDSUMU_VS_MF4_E8, VWREDSUMU_VS }, // 10495 |
29653 | | { PseudoVWREDSUMU_VS_MF4_E8_MASK, VWREDSUMU_VS }, // 10496 |
29654 | | { PseudoVWREDSUMU_VS_MF8_E8, VWREDSUMU_VS }, // 10497 |
29655 | | { PseudoVWREDSUMU_VS_MF8_E8_MASK, VWREDSUMU_VS }, // 10498 |
29656 | | { PseudoVWREDSUM_VS_M1_E16, VWREDSUM_VS }, // 10499 |
29657 | | { PseudoVWREDSUM_VS_M1_E16_MASK, VWREDSUM_VS }, // 10500 |
29658 | | { PseudoVWREDSUM_VS_M1_E32, VWREDSUM_VS }, // 10501 |
29659 | | { PseudoVWREDSUM_VS_M1_E32_MASK, VWREDSUM_VS }, // 10502 |
29660 | | { PseudoVWREDSUM_VS_M1_E8, VWREDSUM_VS }, // 10503 |
29661 | | { PseudoVWREDSUM_VS_M1_E8_MASK, VWREDSUM_VS }, // 10504 |
29662 | | { PseudoVWREDSUM_VS_M2_E16, VWREDSUM_VS }, // 10505 |
29663 | | { PseudoVWREDSUM_VS_M2_E16_MASK, VWREDSUM_VS }, // 10506 |
29664 | | { PseudoVWREDSUM_VS_M2_E32, VWREDSUM_VS }, // 10507 |
29665 | | { PseudoVWREDSUM_VS_M2_E32_MASK, VWREDSUM_VS }, // 10508 |
29666 | | { PseudoVWREDSUM_VS_M2_E8, VWREDSUM_VS }, // 10509 |
29667 | | { PseudoVWREDSUM_VS_M2_E8_MASK, VWREDSUM_VS }, // 10510 |
29668 | | { PseudoVWREDSUM_VS_M4_E16, VWREDSUM_VS }, // 10511 |
29669 | | { PseudoVWREDSUM_VS_M4_E16_MASK, VWREDSUM_VS }, // 10512 |
29670 | | { PseudoVWREDSUM_VS_M4_E32, VWREDSUM_VS }, // 10513 |
29671 | | { PseudoVWREDSUM_VS_M4_E32_MASK, VWREDSUM_VS }, // 10514 |
29672 | | { PseudoVWREDSUM_VS_M4_E8, VWREDSUM_VS }, // 10515 |
29673 | | { PseudoVWREDSUM_VS_M4_E8_MASK, VWREDSUM_VS }, // 10516 |
29674 | | { PseudoVWREDSUM_VS_M8_E16, VWREDSUM_VS }, // 10517 |
29675 | | { PseudoVWREDSUM_VS_M8_E16_MASK, VWREDSUM_VS }, // 10518 |
29676 | | { PseudoVWREDSUM_VS_M8_E32, VWREDSUM_VS }, // 10519 |
29677 | | { PseudoVWREDSUM_VS_M8_E32_MASK, VWREDSUM_VS }, // 10520 |
29678 | | { PseudoVWREDSUM_VS_M8_E8, VWREDSUM_VS }, // 10521 |
29679 | | { PseudoVWREDSUM_VS_M8_E8_MASK, VWREDSUM_VS }, // 10522 |
29680 | | { PseudoVWREDSUM_VS_MF2_E16, VWREDSUM_VS }, // 10523 |
29681 | | { PseudoVWREDSUM_VS_MF2_E16_MASK, VWREDSUM_VS }, // 10524 |
29682 | | { PseudoVWREDSUM_VS_MF2_E32, VWREDSUM_VS }, // 10525 |
29683 | | { PseudoVWREDSUM_VS_MF2_E32_MASK, VWREDSUM_VS }, // 10526 |
29684 | | { PseudoVWREDSUM_VS_MF2_E8, VWREDSUM_VS }, // 10527 |
29685 | | { PseudoVWREDSUM_VS_MF2_E8_MASK, VWREDSUM_VS }, // 10528 |
29686 | | { PseudoVWREDSUM_VS_MF4_E16, VWREDSUM_VS }, // 10529 |
29687 | | { PseudoVWREDSUM_VS_MF4_E16_MASK, VWREDSUM_VS }, // 10530 |
29688 | | { PseudoVWREDSUM_VS_MF4_E8, VWREDSUM_VS }, // 10531 |
29689 | | { PseudoVWREDSUM_VS_MF4_E8_MASK, VWREDSUM_VS }, // 10532 |
29690 | | { PseudoVWREDSUM_VS_MF8_E8, VWREDSUM_VS }, // 10533 |
29691 | | { PseudoVWREDSUM_VS_MF8_E8_MASK, VWREDSUM_VS }, // 10534 |
29692 | | { PseudoVWSLL_VI_M1, VWSLL_VI }, // 10535 |
29693 | | { PseudoVWSLL_VI_M1_MASK, VWSLL_VI }, // 10536 |
29694 | | { PseudoVWSLL_VI_M2, VWSLL_VI }, // 10537 |
29695 | | { PseudoVWSLL_VI_M2_MASK, VWSLL_VI }, // 10538 |
29696 | | { PseudoVWSLL_VI_M4, VWSLL_VI }, // 10539 |
29697 | | { PseudoVWSLL_VI_M4_MASK, VWSLL_VI }, // 10540 |
29698 | | { PseudoVWSLL_VI_MF2, VWSLL_VI }, // 10541 |
29699 | | { PseudoVWSLL_VI_MF2_MASK, VWSLL_VI }, // 10542 |
29700 | | { PseudoVWSLL_VI_MF4, VWSLL_VI }, // 10543 |
29701 | | { PseudoVWSLL_VI_MF4_MASK, VWSLL_VI }, // 10544 |
29702 | | { PseudoVWSLL_VI_MF8, VWSLL_VI }, // 10545 |
29703 | | { PseudoVWSLL_VI_MF8_MASK, VWSLL_VI }, // 10546 |
29704 | | { PseudoVWSLL_VV_M1, VWSLL_VV }, // 10547 |
29705 | | { PseudoVWSLL_VV_M1_MASK, VWSLL_VV }, // 10548 |
29706 | | { PseudoVWSLL_VV_M2, VWSLL_VV }, // 10549 |
29707 | | { PseudoVWSLL_VV_M2_MASK, VWSLL_VV }, // 10550 |
29708 | | { PseudoVWSLL_VV_M4, VWSLL_VV }, // 10551 |
29709 | | { PseudoVWSLL_VV_M4_MASK, VWSLL_VV }, // 10552 |
29710 | | { PseudoVWSLL_VV_MF2, VWSLL_VV }, // 10553 |
29711 | | { PseudoVWSLL_VV_MF2_MASK, VWSLL_VV }, // 10554 |
29712 | | { PseudoVWSLL_VV_MF4, VWSLL_VV }, // 10555 |
29713 | | { PseudoVWSLL_VV_MF4_MASK, VWSLL_VV }, // 10556 |
29714 | | { PseudoVWSLL_VV_MF8, VWSLL_VV }, // 10557 |
29715 | | { PseudoVWSLL_VV_MF8_MASK, VWSLL_VV }, // 10558 |
29716 | | { PseudoVWSLL_VX_M1, VWSLL_VX }, // 10559 |
29717 | | { PseudoVWSLL_VX_M1_MASK, VWSLL_VX }, // 10560 |
29718 | | { PseudoVWSLL_VX_M2, VWSLL_VX }, // 10561 |
29719 | | { PseudoVWSLL_VX_M2_MASK, VWSLL_VX }, // 10562 |
29720 | | { PseudoVWSLL_VX_M4, VWSLL_VX }, // 10563 |
29721 | | { PseudoVWSLL_VX_M4_MASK, VWSLL_VX }, // 10564 |
29722 | | { PseudoVWSLL_VX_MF2, VWSLL_VX }, // 10565 |
29723 | | { PseudoVWSLL_VX_MF2_MASK, VWSLL_VX }, // 10566 |
29724 | | { PseudoVWSLL_VX_MF4, VWSLL_VX }, // 10567 |
29725 | | { PseudoVWSLL_VX_MF4_MASK, VWSLL_VX }, // 10568 |
29726 | | { PseudoVWSLL_VX_MF8, VWSLL_VX }, // 10569 |
29727 | | { PseudoVWSLL_VX_MF8_MASK, VWSLL_VX }, // 10570 |
29728 | | { PseudoVWSUBU_VV_M1, VWSUBU_VV }, // 10571 |
29729 | | { PseudoVWSUBU_VV_M1_MASK, VWSUBU_VV }, // 10572 |
29730 | | { PseudoVWSUBU_VV_M2, VWSUBU_VV }, // 10573 |
29731 | | { PseudoVWSUBU_VV_M2_MASK, VWSUBU_VV }, // 10574 |
29732 | | { PseudoVWSUBU_VV_M4, VWSUBU_VV }, // 10575 |
29733 | | { PseudoVWSUBU_VV_M4_MASK, VWSUBU_VV }, // 10576 |
29734 | | { PseudoVWSUBU_VV_MF2, VWSUBU_VV }, // 10577 |
29735 | | { PseudoVWSUBU_VV_MF2_MASK, VWSUBU_VV }, // 10578 |
29736 | | { PseudoVWSUBU_VV_MF4, VWSUBU_VV }, // 10579 |
29737 | | { PseudoVWSUBU_VV_MF4_MASK, VWSUBU_VV }, // 10580 |
29738 | | { PseudoVWSUBU_VV_MF8, VWSUBU_VV }, // 10581 |
29739 | | { PseudoVWSUBU_VV_MF8_MASK, VWSUBU_VV }, // 10582 |
29740 | | { PseudoVWSUBU_VX_M1, VWSUBU_VX }, // 10583 |
29741 | | { PseudoVWSUBU_VX_M1_MASK, VWSUBU_VX }, // 10584 |
29742 | | { PseudoVWSUBU_VX_M2, VWSUBU_VX }, // 10585 |
29743 | | { PseudoVWSUBU_VX_M2_MASK, VWSUBU_VX }, // 10586 |
29744 | | { PseudoVWSUBU_VX_M4, VWSUBU_VX }, // 10587 |
29745 | | { PseudoVWSUBU_VX_M4_MASK, VWSUBU_VX }, // 10588 |
29746 | | { PseudoVWSUBU_VX_MF2, VWSUBU_VX }, // 10589 |
29747 | | { PseudoVWSUBU_VX_MF2_MASK, VWSUBU_VX }, // 10590 |
29748 | | { PseudoVWSUBU_VX_MF4, VWSUBU_VX }, // 10591 |
29749 | | { PseudoVWSUBU_VX_MF4_MASK, VWSUBU_VX }, // 10592 |
29750 | | { PseudoVWSUBU_VX_MF8, VWSUBU_VX }, // 10593 |
29751 | | { PseudoVWSUBU_VX_MF8_MASK, VWSUBU_VX }, // 10594 |
29752 | | { PseudoVWSUBU_WV_M1, VWSUBU_WV }, // 10595 |
29753 | | { PseudoVWSUBU_WV_M1_MASK, VWSUBU_WV }, // 10596 |
29754 | | { PseudoVWSUBU_WV_M1_MASK_TIED, VWSUBU_WV }, // 10597 |
29755 | | { PseudoVWSUBU_WV_M1_TIED, VWSUBU_WV }, // 10598 |
29756 | | { PseudoVWSUBU_WV_M2, VWSUBU_WV }, // 10599 |
29757 | | { PseudoVWSUBU_WV_M2_MASK, VWSUBU_WV }, // 10600 |
29758 | | { PseudoVWSUBU_WV_M2_MASK_TIED, VWSUBU_WV }, // 10601 |
29759 | | { PseudoVWSUBU_WV_M2_TIED, VWSUBU_WV }, // 10602 |
29760 | | { PseudoVWSUBU_WV_M4, VWSUBU_WV }, // 10603 |
29761 | | { PseudoVWSUBU_WV_M4_MASK, VWSUBU_WV }, // 10604 |
29762 | | { PseudoVWSUBU_WV_M4_MASK_TIED, VWSUBU_WV }, // 10605 |
29763 | | { PseudoVWSUBU_WV_M4_TIED, VWSUBU_WV }, // 10606 |
29764 | | { PseudoVWSUBU_WV_MF2, VWSUBU_WV }, // 10607 |
29765 | | { PseudoVWSUBU_WV_MF2_MASK, VWSUBU_WV }, // 10608 |
29766 | | { PseudoVWSUBU_WV_MF2_MASK_TIED, VWSUBU_WV }, // 10609 |
29767 | | { PseudoVWSUBU_WV_MF2_TIED, VWSUBU_WV }, // 10610 |
29768 | | { PseudoVWSUBU_WV_MF4, VWSUBU_WV }, // 10611 |
29769 | | { PseudoVWSUBU_WV_MF4_MASK, VWSUBU_WV }, // 10612 |
29770 | | { PseudoVWSUBU_WV_MF4_MASK_TIED, VWSUBU_WV }, // 10613 |
29771 | | { PseudoVWSUBU_WV_MF4_TIED, VWSUBU_WV }, // 10614 |
29772 | | { PseudoVWSUBU_WV_MF8, VWSUBU_WV }, // 10615 |
29773 | | { PseudoVWSUBU_WV_MF8_MASK, VWSUBU_WV }, // 10616 |
29774 | | { PseudoVWSUBU_WV_MF8_MASK_TIED, VWSUBU_WV }, // 10617 |
29775 | | { PseudoVWSUBU_WV_MF8_TIED, VWSUBU_WV }, // 10618 |
29776 | | { PseudoVWSUBU_WX_M1, VWSUBU_WX }, // 10619 |
29777 | | { PseudoVWSUBU_WX_M1_MASK, VWSUBU_WX }, // 10620 |
29778 | | { PseudoVWSUBU_WX_M2, VWSUBU_WX }, // 10621 |
29779 | | { PseudoVWSUBU_WX_M2_MASK, VWSUBU_WX }, // 10622 |
29780 | | { PseudoVWSUBU_WX_M4, VWSUBU_WX }, // 10623 |
29781 | | { PseudoVWSUBU_WX_M4_MASK, VWSUBU_WX }, // 10624 |
29782 | | { PseudoVWSUBU_WX_MF2, VWSUBU_WX }, // 10625 |
29783 | | { PseudoVWSUBU_WX_MF2_MASK, VWSUBU_WX }, // 10626 |
29784 | | { PseudoVWSUBU_WX_MF4, VWSUBU_WX }, // 10627 |
29785 | | { PseudoVWSUBU_WX_MF4_MASK, VWSUBU_WX }, // 10628 |
29786 | | { PseudoVWSUBU_WX_MF8, VWSUBU_WX }, // 10629 |
29787 | | { PseudoVWSUBU_WX_MF8_MASK, VWSUBU_WX }, // 10630 |
29788 | | { PseudoVWSUB_VV_M1, VWSUB_VV }, // 10631 |
29789 | | { PseudoVWSUB_VV_M1_MASK, VWSUB_VV }, // 10632 |
29790 | | { PseudoVWSUB_VV_M2, VWSUB_VV }, // 10633 |
29791 | | { PseudoVWSUB_VV_M2_MASK, VWSUB_VV }, // 10634 |
29792 | | { PseudoVWSUB_VV_M4, VWSUB_VV }, // 10635 |
29793 | | { PseudoVWSUB_VV_M4_MASK, VWSUB_VV }, // 10636 |
29794 | | { PseudoVWSUB_VV_MF2, VWSUB_VV }, // 10637 |
29795 | | { PseudoVWSUB_VV_MF2_MASK, VWSUB_VV }, // 10638 |
29796 | | { PseudoVWSUB_VV_MF4, VWSUB_VV }, // 10639 |
29797 | | { PseudoVWSUB_VV_MF4_MASK, VWSUB_VV }, // 10640 |
29798 | | { PseudoVWSUB_VV_MF8, VWSUB_VV }, // 10641 |
29799 | | { PseudoVWSUB_VV_MF8_MASK, VWSUB_VV }, // 10642 |
29800 | | { PseudoVWSUB_VX_M1, VWSUB_VX }, // 10643 |
29801 | | { PseudoVWSUB_VX_M1_MASK, VWSUB_VX }, // 10644 |
29802 | | { PseudoVWSUB_VX_M2, VWSUB_VX }, // 10645 |
29803 | | { PseudoVWSUB_VX_M2_MASK, VWSUB_VX }, // 10646 |
29804 | | { PseudoVWSUB_VX_M4, VWSUB_VX }, // 10647 |
29805 | | { PseudoVWSUB_VX_M4_MASK, VWSUB_VX }, // 10648 |
29806 | | { PseudoVWSUB_VX_MF2, VWSUB_VX }, // 10649 |
29807 | | { PseudoVWSUB_VX_MF2_MASK, VWSUB_VX }, // 10650 |
29808 | | { PseudoVWSUB_VX_MF4, VWSUB_VX }, // 10651 |
29809 | | { PseudoVWSUB_VX_MF4_MASK, VWSUB_VX }, // 10652 |
29810 | | { PseudoVWSUB_VX_MF8, VWSUB_VX }, // 10653 |
29811 | | { PseudoVWSUB_VX_MF8_MASK, VWSUB_VX }, // 10654 |
29812 | | { PseudoVWSUB_WV_M1, VWSUB_WV }, // 10655 |
29813 | | { PseudoVWSUB_WV_M1_MASK, VWSUB_WV }, // 10656 |
29814 | | { PseudoVWSUB_WV_M1_MASK_TIED, VWSUB_WV }, // 10657 |
29815 | | { PseudoVWSUB_WV_M1_TIED, VWSUB_WV }, // 10658 |
29816 | | { PseudoVWSUB_WV_M2, VWSUB_WV }, // 10659 |
29817 | | { PseudoVWSUB_WV_M2_MASK, VWSUB_WV }, // 10660 |
29818 | | { PseudoVWSUB_WV_M2_MASK_TIED, VWSUB_WV }, // 10661 |
29819 | | { PseudoVWSUB_WV_M2_TIED, VWSUB_WV }, // 10662 |
29820 | | { PseudoVWSUB_WV_M4, VWSUB_WV }, // 10663 |
29821 | | { PseudoVWSUB_WV_M4_MASK, VWSUB_WV }, // 10664 |
29822 | | { PseudoVWSUB_WV_M4_MASK_TIED, VWSUB_WV }, // 10665 |
29823 | | { PseudoVWSUB_WV_M4_TIED, VWSUB_WV }, // 10666 |
29824 | | { PseudoVWSUB_WV_MF2, VWSUB_WV }, // 10667 |
29825 | | { PseudoVWSUB_WV_MF2_MASK, VWSUB_WV }, // 10668 |
29826 | | { PseudoVWSUB_WV_MF2_MASK_TIED, VWSUB_WV }, // 10669 |
29827 | | { PseudoVWSUB_WV_MF2_TIED, VWSUB_WV }, // 10670 |
29828 | | { PseudoVWSUB_WV_MF4, VWSUB_WV }, // 10671 |
29829 | | { PseudoVWSUB_WV_MF4_MASK, VWSUB_WV }, // 10672 |
29830 | | { PseudoVWSUB_WV_MF4_MASK_TIED, VWSUB_WV }, // 10673 |
29831 | | { PseudoVWSUB_WV_MF4_TIED, VWSUB_WV }, // 10674 |
29832 | | { PseudoVWSUB_WV_MF8, VWSUB_WV }, // 10675 |
29833 | | { PseudoVWSUB_WV_MF8_MASK, VWSUB_WV }, // 10676 |
29834 | | { PseudoVWSUB_WV_MF8_MASK_TIED, VWSUB_WV }, // 10677 |
29835 | | { PseudoVWSUB_WV_MF8_TIED, VWSUB_WV }, // 10678 |
29836 | | { PseudoVWSUB_WX_M1, VWSUB_WX }, // 10679 |
29837 | | { PseudoVWSUB_WX_M1_MASK, VWSUB_WX }, // 10680 |
29838 | | { PseudoVWSUB_WX_M2, VWSUB_WX }, // 10681 |
29839 | | { PseudoVWSUB_WX_M2_MASK, VWSUB_WX }, // 10682 |
29840 | | { PseudoVWSUB_WX_M4, VWSUB_WX }, // 10683 |
29841 | | { PseudoVWSUB_WX_M4_MASK, VWSUB_WX }, // 10684 |
29842 | | { PseudoVWSUB_WX_MF2, VWSUB_WX }, // 10685 |
29843 | | { PseudoVWSUB_WX_MF2_MASK, VWSUB_WX }, // 10686 |
29844 | | { PseudoVWSUB_WX_MF4, VWSUB_WX }, // 10687 |
29845 | | { PseudoVWSUB_WX_MF4_MASK, VWSUB_WX }, // 10688 |
29846 | | { PseudoVWSUB_WX_MF8, VWSUB_WX }, // 10689 |
29847 | | { PseudoVWSUB_WX_MF8_MASK, VWSUB_WX }, // 10690 |
29848 | | { PseudoVXOR_VI_M1, VXOR_VI }, // 10691 |
29849 | | { PseudoVXOR_VI_M1_MASK, VXOR_VI }, // 10692 |
29850 | | { PseudoVXOR_VI_M2, VXOR_VI }, // 10693 |
29851 | | { PseudoVXOR_VI_M2_MASK, VXOR_VI }, // 10694 |
29852 | | { PseudoVXOR_VI_M4, VXOR_VI }, // 10695 |
29853 | | { PseudoVXOR_VI_M4_MASK, VXOR_VI }, // 10696 |
29854 | | { PseudoVXOR_VI_M8, VXOR_VI }, // 10697 |
29855 | | { PseudoVXOR_VI_M8_MASK, VXOR_VI }, // 10698 |
29856 | | { PseudoVXOR_VI_MF2, VXOR_VI }, // 10699 |
29857 | | { PseudoVXOR_VI_MF2_MASK, VXOR_VI }, // 10700 |
29858 | | { PseudoVXOR_VI_MF4, VXOR_VI }, // 10701 |
29859 | | { PseudoVXOR_VI_MF4_MASK, VXOR_VI }, // 10702 |
29860 | | { PseudoVXOR_VI_MF8, VXOR_VI }, // 10703 |
29861 | | { PseudoVXOR_VI_MF8_MASK, VXOR_VI }, // 10704 |
29862 | | { PseudoVXOR_VV_M1, VXOR_VV }, // 10705 |
29863 | | { PseudoVXOR_VV_M1_MASK, VXOR_VV }, // 10706 |
29864 | | { PseudoVXOR_VV_M2, VXOR_VV }, // 10707 |
29865 | | { PseudoVXOR_VV_M2_MASK, VXOR_VV }, // 10708 |
29866 | | { PseudoVXOR_VV_M4, VXOR_VV }, // 10709 |
29867 | | { PseudoVXOR_VV_M4_MASK, VXOR_VV }, // 10710 |
29868 | | { PseudoVXOR_VV_M8, VXOR_VV }, // 10711 |
29869 | | { PseudoVXOR_VV_M8_MASK, VXOR_VV }, // 10712 |
29870 | | { PseudoVXOR_VV_MF2, VXOR_VV }, // 10713 |
29871 | | { PseudoVXOR_VV_MF2_MASK, VXOR_VV }, // 10714 |
29872 | | { PseudoVXOR_VV_MF4, VXOR_VV }, // 10715 |
29873 | | { PseudoVXOR_VV_MF4_MASK, VXOR_VV }, // 10716 |
29874 | | { PseudoVXOR_VV_MF8, VXOR_VV }, // 10717 |
29875 | | { PseudoVXOR_VV_MF8_MASK, VXOR_VV }, // 10718 |
29876 | | { PseudoVXOR_VX_M1, VXOR_VX }, // 10719 |
29877 | | { PseudoVXOR_VX_M1_MASK, VXOR_VX }, // 10720 |
29878 | | { PseudoVXOR_VX_M2, VXOR_VX }, // 10721 |
29879 | | { PseudoVXOR_VX_M2_MASK, VXOR_VX }, // 10722 |
29880 | | { PseudoVXOR_VX_M4, VXOR_VX }, // 10723 |
29881 | | { PseudoVXOR_VX_M4_MASK, VXOR_VX }, // 10724 |
29882 | | { PseudoVXOR_VX_M8, VXOR_VX }, // 10725 |
29883 | | { PseudoVXOR_VX_M8_MASK, VXOR_VX }, // 10726 |
29884 | | { PseudoVXOR_VX_MF2, VXOR_VX }, // 10727 |
29885 | | { PseudoVXOR_VX_MF2_MASK, VXOR_VX }, // 10728 |
29886 | | { PseudoVXOR_VX_MF4, VXOR_VX }, // 10729 |
29887 | | { PseudoVXOR_VX_MF4_MASK, VXOR_VX }, // 10730 |
29888 | | { PseudoVXOR_VX_MF8, VXOR_VX }, // 10731 |
29889 | | { PseudoVXOR_VX_MF8_MASK, VXOR_VX }, // 10732 |
29890 | | { PseudoVZEXT_VF2_M1, VZEXT_VF2 }, // 10733 |
29891 | | { PseudoVZEXT_VF2_M1_MASK, VZEXT_VF2 }, // 10734 |
29892 | | { PseudoVZEXT_VF2_M2, VZEXT_VF2 }, // 10735 |
29893 | | { PseudoVZEXT_VF2_M2_MASK, VZEXT_VF2 }, // 10736 |
29894 | | { PseudoVZEXT_VF2_M4, VZEXT_VF2 }, // 10737 |
29895 | | { PseudoVZEXT_VF2_M4_MASK, VZEXT_VF2 }, // 10738 |
29896 | | { PseudoVZEXT_VF2_M8, VZEXT_VF2 }, // 10739 |
29897 | | { PseudoVZEXT_VF2_M8_MASK, VZEXT_VF2 }, // 10740 |
29898 | | { PseudoVZEXT_VF2_MF2, VZEXT_VF2 }, // 10741 |
29899 | | { PseudoVZEXT_VF2_MF2_MASK, VZEXT_VF2 }, // 10742 |
29900 | | { PseudoVZEXT_VF2_MF4, VZEXT_VF2 }, // 10743 |
29901 | | { PseudoVZEXT_VF2_MF4_MASK, VZEXT_VF2 }, // 10744 |
29902 | | { PseudoVZEXT_VF4_M1, VZEXT_VF4 }, // 10745 |
29903 | | { PseudoVZEXT_VF4_M1_MASK, VZEXT_VF4 }, // 10746 |
29904 | | { PseudoVZEXT_VF4_M2, VZEXT_VF4 }, // 10747 |
29905 | | { PseudoVZEXT_VF4_M2_MASK, VZEXT_VF4 }, // 10748 |
29906 | | { PseudoVZEXT_VF4_M4, VZEXT_VF4 }, // 10749 |
29907 | | { PseudoVZEXT_VF4_M4_MASK, VZEXT_VF4 }, // 10750 |
29908 | | { PseudoVZEXT_VF4_M8, VZEXT_VF4 }, // 10751 |
29909 | | { PseudoVZEXT_VF4_M8_MASK, VZEXT_VF4 }, // 10752 |
29910 | | { PseudoVZEXT_VF4_MF2, VZEXT_VF4 }, // 10753 |
29911 | | { PseudoVZEXT_VF4_MF2_MASK, VZEXT_VF4 }, // 10754 |
29912 | | { PseudoVZEXT_VF8_M1, VZEXT_VF8 }, // 10755 |
29913 | | { PseudoVZEXT_VF8_M1_MASK, VZEXT_VF8 }, // 10756 |
29914 | | { PseudoVZEXT_VF8_M2, VZEXT_VF8 }, // 10757 |
29915 | | { PseudoVZEXT_VF8_M2_MASK, VZEXT_VF8 }, // 10758 |
29916 | | { PseudoVZEXT_VF8_M4, VZEXT_VF8 }, // 10759 |
29917 | | { PseudoVZEXT_VF8_M4_MASK, VZEXT_VF8 }, // 10760 |
29918 | | { PseudoVZEXT_VF8_M8, VZEXT_VF8 }, // 10761 |
29919 | | { PseudoVZEXT_VF8_M8_MASK, VZEXT_VF8 }, // 10762 |
29920 | | }; |
29921 | | |
29922 | | const RISCV_PseudoInfo *RISCV_getPseudoInfo(unsigned Pseudo) { |
29923 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Pseudo); |
29924 | | if (i == -1) |
29925 | | return NULL; |
29926 | | else |
29927 | | return &RISCVVPseudosTable[Index[i].index]; |
29928 | | } |
29929 | | |
29930 | | #endif |
29931 | | |
29932 | | #ifdef GET_RISCVVSETable_IMPL |
29933 | | static const RISCV_VSEPseudo RISCVVSETable[] = { |
29934 | | { 0x0, 0x0, 0x0, 0x0, PseudoVSM_V_B8 }, // 0 |
29935 | | { 0x0, 0x0, 0x0, 0x1, PseudoVSM_V_B16 }, // 1 |
29936 | | { 0x0, 0x0, 0x0, 0x2, PseudoVSM_V_B32 }, // 2 |
29937 | | { 0x0, 0x0, 0x0, 0x3, PseudoVSM_V_B64 }, // 3 |
29938 | | { 0x0, 0x0, 0x0, 0x5, PseudoVSM_V_B1 }, // 4 |
29939 | | { 0x0, 0x0, 0x0, 0x6, PseudoVSM_V_B2 }, // 5 |
29940 | | { 0x0, 0x0, 0x0, 0x7, PseudoVSM_V_B4 }, // 6 |
29941 | | { 0x0, 0x0, 0x3, 0x0, PseudoVSE8_V_M1 }, // 7 |
29942 | | { 0x0, 0x0, 0x3, 0x1, PseudoVSE8_V_M2 }, // 8 |
29943 | | { 0x0, 0x0, 0x3, 0x2, PseudoVSE8_V_M4 }, // 9 |
29944 | | { 0x0, 0x0, 0x3, 0x3, PseudoVSE8_V_M8 }, // 10 |
29945 | | { 0x0, 0x0, 0x3, 0x5, PseudoVSE8_V_MF8 }, // 11 |
29946 | | { 0x0, 0x0, 0x3, 0x6, PseudoVSE8_V_MF4 }, // 12 |
29947 | | { 0x0, 0x0, 0x3, 0x7, PseudoVSE8_V_MF2 }, // 13 |
29948 | | { 0x0, 0x0, 0x4, 0x0, PseudoVSE16_V_M1 }, // 14 |
29949 | | { 0x0, 0x0, 0x4, 0x1, PseudoVSE16_V_M2 }, // 15 |
29950 | | { 0x0, 0x0, 0x4, 0x2, PseudoVSE16_V_M4 }, // 16 |
29951 | | { 0x0, 0x0, 0x4, 0x3, PseudoVSE16_V_M8 }, // 17 |
29952 | | { 0x0, 0x0, 0x4, 0x6, PseudoVSE16_V_MF4 }, // 18 |
29953 | | { 0x0, 0x0, 0x4, 0x7, PseudoVSE16_V_MF2 }, // 19 |
29954 | | { 0x0, 0x0, 0x5, 0x0, PseudoVSE32_V_M1 }, // 20 |
29955 | | { 0x0, 0x0, 0x5, 0x1, PseudoVSE32_V_M2 }, // 21 |
29956 | | { 0x0, 0x0, 0x5, 0x2, PseudoVSE32_V_M4 }, // 22 |
29957 | | { 0x0, 0x0, 0x5, 0x3, PseudoVSE32_V_M8 }, // 23 |
29958 | | { 0x0, 0x0, 0x5, 0x7, PseudoVSE32_V_MF2 }, // 24 |
29959 | | { 0x0, 0x0, 0x6, 0x0, PseudoVSE64_V_M1 }, // 25 |
29960 | | { 0x0, 0x0, 0x6, 0x1, PseudoVSE64_V_M2 }, // 26 |
29961 | | { 0x0, 0x0, 0x6, 0x2, PseudoVSE64_V_M4 }, // 27 |
29962 | | { 0x0, 0x0, 0x6, 0x3, PseudoVSE64_V_M8 }, // 28 |
29963 | | { 0x0, 0x1, 0x3, 0x0, PseudoVSSE8_V_M1 }, // 29 |
29964 | | { 0x0, 0x1, 0x3, 0x1, PseudoVSSE8_V_M2 }, // 30 |
29965 | | { 0x0, 0x1, 0x3, 0x2, PseudoVSSE8_V_M4 }, // 31 |
29966 | | { 0x0, 0x1, 0x3, 0x3, PseudoVSSE8_V_M8 }, // 32 |
29967 | | { 0x0, 0x1, 0x3, 0x5, PseudoVSSE8_V_MF8 }, // 33 |
29968 | | { 0x0, 0x1, 0x3, 0x6, PseudoVSSE8_V_MF4 }, // 34 |
29969 | | { 0x0, 0x1, 0x3, 0x7, PseudoVSSE8_V_MF2 }, // 35 |
29970 | | { 0x0, 0x1, 0x4, 0x0, PseudoVSSE16_V_M1 }, // 36 |
29971 | | { 0x0, 0x1, 0x4, 0x1, PseudoVSSE16_V_M2 }, // 37 |
29972 | | { 0x0, 0x1, 0x4, 0x2, PseudoVSSE16_V_M4 }, // 38 |
29973 | | { 0x0, 0x1, 0x4, 0x3, PseudoVSSE16_V_M8 }, // 39 |
29974 | | { 0x0, 0x1, 0x4, 0x6, PseudoVSSE16_V_MF4 }, // 40 |
29975 | | { 0x0, 0x1, 0x4, 0x7, PseudoVSSE16_V_MF2 }, // 41 |
29976 | | { 0x0, 0x1, 0x5, 0x0, PseudoVSSE32_V_M1 }, // 42 |
29977 | | { 0x0, 0x1, 0x5, 0x1, PseudoVSSE32_V_M2 }, // 43 |
29978 | | { 0x0, 0x1, 0x5, 0x2, PseudoVSSE32_V_M4 }, // 44 |
29979 | | { 0x0, 0x1, 0x5, 0x3, PseudoVSSE32_V_M8 }, // 45 |
29980 | | { 0x0, 0x1, 0x5, 0x7, PseudoVSSE32_V_MF2 }, // 46 |
29981 | | { 0x0, 0x1, 0x6, 0x0, PseudoVSSE64_V_M1 }, // 47 |
29982 | | { 0x0, 0x1, 0x6, 0x1, PseudoVSSE64_V_M2 }, // 48 |
29983 | | { 0x0, 0x1, 0x6, 0x2, PseudoVSSE64_V_M4 }, // 49 |
29984 | | { 0x0, 0x1, 0x6, 0x3, PseudoVSSE64_V_M8 }, // 50 |
29985 | | { 0x1, 0x0, 0x3, 0x0, PseudoVSE8_V_M1_MASK }, // 51 |
29986 | | { 0x1, 0x0, 0x3, 0x1, PseudoVSE8_V_M2_MASK }, // 52 |
29987 | | { 0x1, 0x0, 0x3, 0x2, PseudoVSE8_V_M4_MASK }, // 53 |
29988 | | { 0x1, 0x0, 0x3, 0x3, PseudoVSE8_V_M8_MASK }, // 54 |
29989 | | { 0x1, 0x0, 0x3, 0x5, PseudoVSE8_V_MF8_MASK }, // 55 |
29990 | | { 0x1, 0x0, 0x3, 0x6, PseudoVSE8_V_MF4_MASK }, // 56 |
29991 | | { 0x1, 0x0, 0x3, 0x7, PseudoVSE8_V_MF2_MASK }, // 57 |
29992 | | { 0x1, 0x0, 0x4, 0x0, PseudoVSE16_V_M1_MASK }, // 58 |
29993 | | { 0x1, 0x0, 0x4, 0x1, PseudoVSE16_V_M2_MASK }, // 59 |
29994 | | { 0x1, 0x0, 0x4, 0x2, PseudoVSE16_V_M4_MASK }, // 60 |
29995 | | { 0x1, 0x0, 0x4, 0x3, PseudoVSE16_V_M8_MASK }, // 61 |
29996 | | { 0x1, 0x0, 0x4, 0x6, PseudoVSE16_V_MF4_MASK }, // 62 |
29997 | | { 0x1, 0x0, 0x4, 0x7, PseudoVSE16_V_MF2_MASK }, // 63 |
29998 | | { 0x1, 0x0, 0x5, 0x0, PseudoVSE32_V_M1_MASK }, // 64 |
29999 | | { 0x1, 0x0, 0x5, 0x1, PseudoVSE32_V_M2_MASK }, // 65 |
30000 | | { 0x1, 0x0, 0x5, 0x2, PseudoVSE32_V_M4_MASK }, // 66 |
30001 | | { 0x1, 0x0, 0x5, 0x3, PseudoVSE32_V_M8_MASK }, // 67 |
30002 | | { 0x1, 0x0, 0x5, 0x7, PseudoVSE32_V_MF2_MASK }, // 68 |
30003 | | { 0x1, 0x0, 0x6, 0x0, PseudoVSE64_V_M1_MASK }, // 69 |
30004 | | { 0x1, 0x0, 0x6, 0x1, PseudoVSE64_V_M2_MASK }, // 70 |
30005 | | { 0x1, 0x0, 0x6, 0x2, PseudoVSE64_V_M4_MASK }, // 71 |
30006 | | { 0x1, 0x0, 0x6, 0x3, PseudoVSE64_V_M8_MASK }, // 72 |
30007 | | { 0x1, 0x1, 0x3, 0x0, PseudoVSSE8_V_M1_MASK }, // 73 |
30008 | | { 0x1, 0x1, 0x3, 0x1, PseudoVSSE8_V_M2_MASK }, // 74 |
30009 | | { 0x1, 0x1, 0x3, 0x2, PseudoVSSE8_V_M4_MASK }, // 75 |
30010 | | { 0x1, 0x1, 0x3, 0x3, PseudoVSSE8_V_M8_MASK }, // 76 |
30011 | | { 0x1, 0x1, 0x3, 0x5, PseudoVSSE8_V_MF8_MASK }, // 77 |
30012 | | { 0x1, 0x1, 0x3, 0x6, PseudoVSSE8_V_MF4_MASK }, // 78 |
30013 | | { 0x1, 0x1, 0x3, 0x7, PseudoVSSE8_V_MF2_MASK }, // 79 |
30014 | | { 0x1, 0x1, 0x4, 0x0, PseudoVSSE16_V_M1_MASK }, // 80 |
30015 | | { 0x1, 0x1, 0x4, 0x1, PseudoVSSE16_V_M2_MASK }, // 81 |
30016 | | { 0x1, 0x1, 0x4, 0x2, PseudoVSSE16_V_M4_MASK }, // 82 |
30017 | | { 0x1, 0x1, 0x4, 0x3, PseudoVSSE16_V_M8_MASK }, // 83 |
30018 | | { 0x1, 0x1, 0x4, 0x6, PseudoVSSE16_V_MF4_MASK }, // 84 |
30019 | | { 0x1, 0x1, 0x4, 0x7, PseudoVSSE16_V_MF2_MASK }, // 85 |
30020 | | { 0x1, 0x1, 0x5, 0x0, PseudoVSSE32_V_M1_MASK }, // 86 |
30021 | | { 0x1, 0x1, 0x5, 0x1, PseudoVSSE32_V_M2_MASK }, // 87 |
30022 | | { 0x1, 0x1, 0x5, 0x2, PseudoVSSE32_V_M4_MASK }, // 88 |
30023 | | { 0x1, 0x1, 0x5, 0x3, PseudoVSSE32_V_M8_MASK }, // 89 |
30024 | | { 0x1, 0x1, 0x5, 0x7, PseudoVSSE32_V_MF2_MASK }, // 90 |
30025 | | { 0x1, 0x1, 0x6, 0x0, PseudoVSSE64_V_M1_MASK }, // 91 |
30026 | | { 0x1, 0x1, 0x6, 0x1, PseudoVSSE64_V_M2_MASK }, // 92 |
30027 | | { 0x1, 0x1, 0x6, 0x2, PseudoVSSE64_V_M4_MASK }, // 93 |
30028 | | { 0x1, 0x1, 0x6, 0x3, PseudoVSSE64_V_M8_MASK }, // 94 |
30029 | | }; |
30030 | | |
30031 | | const RISCV_VSEPseudo *RISCV_getVSEPseudo(uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL) { |
30032 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), MaskedStridedLog2SEWLMUL); |
30033 | | if (i == -1) |
30034 | | return NULL; |
30035 | | else |
30036 | | return &RISCVVSETable[Index[i].index]; |
30037 | | } |
30038 | | |
30039 | | #endif |
30040 | | |
30041 | | #ifdef GET_RISCVVSSEGTable_IMPL |
30042 | | static const RISCV_VSSEGPseudo RISCVVSSEGTable[] = { |
30043 | | { 0x2, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG2E8_V_M1 }, // 0 |
30044 | | { 0x2, 0x0, 0x0, 0x3, 0x1, PseudoVSSEG2E8_V_M2 }, // 1 |
30045 | | { 0x2, 0x0, 0x0, 0x3, 0x2, PseudoVSSEG2E8_V_M4 }, // 2 |
30046 | | { 0x2, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG2E8_V_MF8 }, // 3 |
30047 | | { 0x2, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG2E8_V_MF4 }, // 4 |
30048 | | { 0x2, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG2E8_V_MF2 }, // 5 |
30049 | | { 0x2, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG2E16_V_M1 }, // 6 |
30050 | | { 0x2, 0x0, 0x0, 0x4, 0x1, PseudoVSSEG2E16_V_M2 }, // 7 |
30051 | | { 0x2, 0x0, 0x0, 0x4, 0x2, PseudoVSSEG2E16_V_M4 }, // 8 |
30052 | | { 0x2, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG2E16_V_MF4 }, // 9 |
30053 | | { 0x2, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG2E16_V_MF2 }, // 10 |
30054 | | { 0x2, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG2E32_V_M1 }, // 11 |
30055 | | { 0x2, 0x0, 0x0, 0x5, 0x1, PseudoVSSEG2E32_V_M2 }, // 12 |
30056 | | { 0x2, 0x0, 0x0, 0x5, 0x2, PseudoVSSEG2E32_V_M4 }, // 13 |
30057 | | { 0x2, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG2E32_V_MF2 }, // 14 |
30058 | | { 0x2, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG2E64_V_M1 }, // 15 |
30059 | | { 0x2, 0x0, 0x0, 0x6, 0x1, PseudoVSSEG2E64_V_M2 }, // 16 |
30060 | | { 0x2, 0x0, 0x0, 0x6, 0x2, PseudoVSSEG2E64_V_M4 }, // 17 |
30061 | | { 0x2, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG2E8_V_M1 }, // 18 |
30062 | | { 0x2, 0x0, 0x1, 0x3, 0x1, PseudoVSSSEG2E8_V_M2 }, // 19 |
30063 | | { 0x2, 0x0, 0x1, 0x3, 0x2, PseudoVSSSEG2E8_V_M4 }, // 20 |
30064 | | { 0x2, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG2E8_V_MF8 }, // 21 |
30065 | | { 0x2, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG2E8_V_MF4 }, // 22 |
30066 | | { 0x2, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG2E8_V_MF2 }, // 23 |
30067 | | { 0x2, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG2E16_V_M1 }, // 24 |
30068 | | { 0x2, 0x0, 0x1, 0x4, 0x1, PseudoVSSSEG2E16_V_M2 }, // 25 |
30069 | | { 0x2, 0x0, 0x1, 0x4, 0x2, PseudoVSSSEG2E16_V_M4 }, // 26 |
30070 | | { 0x2, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG2E16_V_MF4 }, // 27 |
30071 | | { 0x2, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG2E16_V_MF2 }, // 28 |
30072 | | { 0x2, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG2E32_V_M1 }, // 29 |
30073 | | { 0x2, 0x0, 0x1, 0x5, 0x1, PseudoVSSSEG2E32_V_M2 }, // 30 |
30074 | | { 0x2, 0x0, 0x1, 0x5, 0x2, PseudoVSSSEG2E32_V_M4 }, // 31 |
30075 | | { 0x2, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG2E32_V_MF2 }, // 32 |
30076 | | { 0x2, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG2E64_V_M1 }, // 33 |
30077 | | { 0x2, 0x0, 0x1, 0x6, 0x1, PseudoVSSSEG2E64_V_M2 }, // 34 |
30078 | | { 0x2, 0x0, 0x1, 0x6, 0x2, PseudoVSSSEG2E64_V_M4 }, // 35 |
30079 | | { 0x2, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG2E8_V_M1_MASK }, // 36 |
30080 | | { 0x2, 0x1, 0x0, 0x3, 0x1, PseudoVSSEG2E8_V_M2_MASK }, // 37 |
30081 | | { 0x2, 0x1, 0x0, 0x3, 0x2, PseudoVSSEG2E8_V_M4_MASK }, // 38 |
30082 | | { 0x2, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG2E8_V_MF8_MASK }, // 39 |
30083 | | { 0x2, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG2E8_V_MF4_MASK }, // 40 |
30084 | | { 0x2, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG2E8_V_MF2_MASK }, // 41 |
30085 | | { 0x2, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG2E16_V_M1_MASK }, // 42 |
30086 | | { 0x2, 0x1, 0x0, 0x4, 0x1, PseudoVSSEG2E16_V_M2_MASK }, // 43 |
30087 | | { 0x2, 0x1, 0x0, 0x4, 0x2, PseudoVSSEG2E16_V_M4_MASK }, // 44 |
30088 | | { 0x2, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG2E16_V_MF4_MASK }, // 45 |
30089 | | { 0x2, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG2E16_V_MF2_MASK }, // 46 |
30090 | | { 0x2, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG2E32_V_M1_MASK }, // 47 |
30091 | | { 0x2, 0x1, 0x0, 0x5, 0x1, PseudoVSSEG2E32_V_M2_MASK }, // 48 |
30092 | | { 0x2, 0x1, 0x0, 0x5, 0x2, PseudoVSSEG2E32_V_M4_MASK }, // 49 |
30093 | | { 0x2, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG2E32_V_MF2_MASK }, // 50 |
30094 | | { 0x2, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG2E64_V_M1_MASK }, // 51 |
30095 | | { 0x2, 0x1, 0x0, 0x6, 0x1, PseudoVSSEG2E64_V_M2_MASK }, // 52 |
30096 | | { 0x2, 0x1, 0x0, 0x6, 0x2, PseudoVSSEG2E64_V_M4_MASK }, // 53 |
30097 | | { 0x2, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG2E8_V_M1_MASK }, // 54 |
30098 | | { 0x2, 0x1, 0x1, 0x3, 0x1, PseudoVSSSEG2E8_V_M2_MASK }, // 55 |
30099 | | { 0x2, 0x1, 0x1, 0x3, 0x2, PseudoVSSSEG2E8_V_M4_MASK }, // 56 |
30100 | | { 0x2, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG2E8_V_MF8_MASK }, // 57 |
30101 | | { 0x2, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG2E8_V_MF4_MASK }, // 58 |
30102 | | { 0x2, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG2E8_V_MF2_MASK }, // 59 |
30103 | | { 0x2, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG2E16_V_M1_MASK }, // 60 |
30104 | | { 0x2, 0x1, 0x1, 0x4, 0x1, PseudoVSSSEG2E16_V_M2_MASK }, // 61 |
30105 | | { 0x2, 0x1, 0x1, 0x4, 0x2, PseudoVSSSEG2E16_V_M4_MASK }, // 62 |
30106 | | { 0x2, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG2E16_V_MF4_MASK }, // 63 |
30107 | | { 0x2, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG2E16_V_MF2_MASK }, // 64 |
30108 | | { 0x2, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG2E32_V_M1_MASK }, // 65 |
30109 | | { 0x2, 0x1, 0x1, 0x5, 0x1, PseudoVSSSEG2E32_V_M2_MASK }, // 66 |
30110 | | { 0x2, 0x1, 0x1, 0x5, 0x2, PseudoVSSSEG2E32_V_M4_MASK }, // 67 |
30111 | | { 0x2, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG2E32_V_MF2_MASK }, // 68 |
30112 | | { 0x2, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG2E64_V_M1_MASK }, // 69 |
30113 | | { 0x2, 0x1, 0x1, 0x6, 0x1, PseudoVSSSEG2E64_V_M2_MASK }, // 70 |
30114 | | { 0x2, 0x1, 0x1, 0x6, 0x2, PseudoVSSSEG2E64_V_M4_MASK }, // 71 |
30115 | | { 0x3, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG3E8_V_M1 }, // 72 |
30116 | | { 0x3, 0x0, 0x0, 0x3, 0x1, PseudoVSSEG3E8_V_M2 }, // 73 |
30117 | | { 0x3, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG3E8_V_MF8 }, // 74 |
30118 | | { 0x3, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG3E8_V_MF4 }, // 75 |
30119 | | { 0x3, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG3E8_V_MF2 }, // 76 |
30120 | | { 0x3, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG3E16_V_M1 }, // 77 |
30121 | | { 0x3, 0x0, 0x0, 0x4, 0x1, PseudoVSSEG3E16_V_M2 }, // 78 |
30122 | | { 0x3, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG3E16_V_MF4 }, // 79 |
30123 | | { 0x3, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG3E16_V_MF2 }, // 80 |
30124 | | { 0x3, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG3E32_V_M1 }, // 81 |
30125 | | { 0x3, 0x0, 0x0, 0x5, 0x1, PseudoVSSEG3E32_V_M2 }, // 82 |
30126 | | { 0x3, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG3E32_V_MF2 }, // 83 |
30127 | | { 0x3, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG3E64_V_M1 }, // 84 |
30128 | | { 0x3, 0x0, 0x0, 0x6, 0x1, PseudoVSSEG3E64_V_M2 }, // 85 |
30129 | | { 0x3, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG3E8_V_M1 }, // 86 |
30130 | | { 0x3, 0x0, 0x1, 0x3, 0x1, PseudoVSSSEG3E8_V_M2 }, // 87 |
30131 | | { 0x3, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG3E8_V_MF8 }, // 88 |
30132 | | { 0x3, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG3E8_V_MF4 }, // 89 |
30133 | | { 0x3, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG3E8_V_MF2 }, // 90 |
30134 | | { 0x3, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG3E16_V_M1 }, // 91 |
30135 | | { 0x3, 0x0, 0x1, 0x4, 0x1, PseudoVSSSEG3E16_V_M2 }, // 92 |
30136 | | { 0x3, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG3E16_V_MF4 }, // 93 |
30137 | | { 0x3, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG3E16_V_MF2 }, // 94 |
30138 | | { 0x3, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG3E32_V_M1 }, // 95 |
30139 | | { 0x3, 0x0, 0x1, 0x5, 0x1, PseudoVSSSEG3E32_V_M2 }, // 96 |
30140 | | { 0x3, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG3E32_V_MF2 }, // 97 |
30141 | | { 0x3, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG3E64_V_M1 }, // 98 |
30142 | | { 0x3, 0x0, 0x1, 0x6, 0x1, PseudoVSSSEG3E64_V_M2 }, // 99 |
30143 | | { 0x3, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG3E8_V_M1_MASK }, // 100 |
30144 | | { 0x3, 0x1, 0x0, 0x3, 0x1, PseudoVSSEG3E8_V_M2_MASK }, // 101 |
30145 | | { 0x3, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG3E8_V_MF8_MASK }, // 102 |
30146 | | { 0x3, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG3E8_V_MF4_MASK }, // 103 |
30147 | | { 0x3, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG3E8_V_MF2_MASK }, // 104 |
30148 | | { 0x3, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG3E16_V_M1_MASK }, // 105 |
30149 | | { 0x3, 0x1, 0x0, 0x4, 0x1, PseudoVSSEG3E16_V_M2_MASK }, // 106 |
30150 | | { 0x3, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG3E16_V_MF4_MASK }, // 107 |
30151 | | { 0x3, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG3E16_V_MF2_MASK }, // 108 |
30152 | | { 0x3, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG3E32_V_M1_MASK }, // 109 |
30153 | | { 0x3, 0x1, 0x0, 0x5, 0x1, PseudoVSSEG3E32_V_M2_MASK }, // 110 |
30154 | | { 0x3, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG3E32_V_MF2_MASK }, // 111 |
30155 | | { 0x3, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG3E64_V_M1_MASK }, // 112 |
30156 | | { 0x3, 0x1, 0x0, 0x6, 0x1, PseudoVSSEG3E64_V_M2_MASK }, // 113 |
30157 | | { 0x3, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG3E8_V_M1_MASK }, // 114 |
30158 | | { 0x3, 0x1, 0x1, 0x3, 0x1, PseudoVSSSEG3E8_V_M2_MASK }, // 115 |
30159 | | { 0x3, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG3E8_V_MF8_MASK }, // 116 |
30160 | | { 0x3, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG3E8_V_MF4_MASK }, // 117 |
30161 | | { 0x3, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG3E8_V_MF2_MASK }, // 118 |
30162 | | { 0x3, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG3E16_V_M1_MASK }, // 119 |
30163 | | { 0x3, 0x1, 0x1, 0x4, 0x1, PseudoVSSSEG3E16_V_M2_MASK }, // 120 |
30164 | | { 0x3, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG3E16_V_MF4_MASK }, // 121 |
30165 | | { 0x3, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG3E16_V_MF2_MASK }, // 122 |
30166 | | { 0x3, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG3E32_V_M1_MASK }, // 123 |
30167 | | { 0x3, 0x1, 0x1, 0x5, 0x1, PseudoVSSSEG3E32_V_M2_MASK }, // 124 |
30168 | | { 0x3, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG3E32_V_MF2_MASK }, // 125 |
30169 | | { 0x3, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG3E64_V_M1_MASK }, // 126 |
30170 | | { 0x3, 0x1, 0x1, 0x6, 0x1, PseudoVSSSEG3E64_V_M2_MASK }, // 127 |
30171 | | { 0x4, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG4E8_V_M1 }, // 128 |
30172 | | { 0x4, 0x0, 0x0, 0x3, 0x1, PseudoVSSEG4E8_V_M2 }, // 129 |
30173 | | { 0x4, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG4E8_V_MF8 }, // 130 |
30174 | | { 0x4, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG4E8_V_MF4 }, // 131 |
30175 | | { 0x4, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG4E8_V_MF2 }, // 132 |
30176 | | { 0x4, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG4E16_V_M1 }, // 133 |
30177 | | { 0x4, 0x0, 0x0, 0x4, 0x1, PseudoVSSEG4E16_V_M2 }, // 134 |
30178 | | { 0x4, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG4E16_V_MF4 }, // 135 |
30179 | | { 0x4, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG4E16_V_MF2 }, // 136 |
30180 | | { 0x4, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG4E32_V_M1 }, // 137 |
30181 | | { 0x4, 0x0, 0x0, 0x5, 0x1, PseudoVSSEG4E32_V_M2 }, // 138 |
30182 | | { 0x4, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG4E32_V_MF2 }, // 139 |
30183 | | { 0x4, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG4E64_V_M1 }, // 140 |
30184 | | { 0x4, 0x0, 0x0, 0x6, 0x1, PseudoVSSEG4E64_V_M2 }, // 141 |
30185 | | { 0x4, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG4E8_V_M1 }, // 142 |
30186 | | { 0x4, 0x0, 0x1, 0x3, 0x1, PseudoVSSSEG4E8_V_M2 }, // 143 |
30187 | | { 0x4, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG4E8_V_MF8 }, // 144 |
30188 | | { 0x4, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG4E8_V_MF4 }, // 145 |
30189 | | { 0x4, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG4E8_V_MF2 }, // 146 |
30190 | | { 0x4, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG4E16_V_M1 }, // 147 |
30191 | | { 0x4, 0x0, 0x1, 0x4, 0x1, PseudoVSSSEG4E16_V_M2 }, // 148 |
30192 | | { 0x4, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG4E16_V_MF4 }, // 149 |
30193 | | { 0x4, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG4E16_V_MF2 }, // 150 |
30194 | | { 0x4, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG4E32_V_M1 }, // 151 |
30195 | | { 0x4, 0x0, 0x1, 0x5, 0x1, PseudoVSSSEG4E32_V_M2 }, // 152 |
30196 | | { 0x4, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG4E32_V_MF2 }, // 153 |
30197 | | { 0x4, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG4E64_V_M1 }, // 154 |
30198 | | { 0x4, 0x0, 0x1, 0x6, 0x1, PseudoVSSSEG4E64_V_M2 }, // 155 |
30199 | | { 0x4, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG4E8_V_M1_MASK }, // 156 |
30200 | | { 0x4, 0x1, 0x0, 0x3, 0x1, PseudoVSSEG4E8_V_M2_MASK }, // 157 |
30201 | | { 0x4, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG4E8_V_MF8_MASK }, // 158 |
30202 | | { 0x4, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG4E8_V_MF4_MASK }, // 159 |
30203 | | { 0x4, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG4E8_V_MF2_MASK }, // 160 |
30204 | | { 0x4, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG4E16_V_M1_MASK }, // 161 |
30205 | | { 0x4, 0x1, 0x0, 0x4, 0x1, PseudoVSSEG4E16_V_M2_MASK }, // 162 |
30206 | | { 0x4, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG4E16_V_MF4_MASK }, // 163 |
30207 | | { 0x4, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG4E16_V_MF2_MASK }, // 164 |
30208 | | { 0x4, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG4E32_V_M1_MASK }, // 165 |
30209 | | { 0x4, 0x1, 0x0, 0x5, 0x1, PseudoVSSEG4E32_V_M2_MASK }, // 166 |
30210 | | { 0x4, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG4E32_V_MF2_MASK }, // 167 |
30211 | | { 0x4, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG4E64_V_M1_MASK }, // 168 |
30212 | | { 0x4, 0x1, 0x0, 0x6, 0x1, PseudoVSSEG4E64_V_M2_MASK }, // 169 |
30213 | | { 0x4, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG4E8_V_M1_MASK }, // 170 |
30214 | | { 0x4, 0x1, 0x1, 0x3, 0x1, PseudoVSSSEG4E8_V_M2_MASK }, // 171 |
30215 | | { 0x4, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG4E8_V_MF8_MASK }, // 172 |
30216 | | { 0x4, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG4E8_V_MF4_MASK }, // 173 |
30217 | | { 0x4, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG4E8_V_MF2_MASK }, // 174 |
30218 | | { 0x4, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG4E16_V_M1_MASK }, // 175 |
30219 | | { 0x4, 0x1, 0x1, 0x4, 0x1, PseudoVSSSEG4E16_V_M2_MASK }, // 176 |
30220 | | { 0x4, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG4E16_V_MF4_MASK }, // 177 |
30221 | | { 0x4, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG4E16_V_MF2_MASK }, // 178 |
30222 | | { 0x4, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG4E32_V_M1_MASK }, // 179 |
30223 | | { 0x4, 0x1, 0x1, 0x5, 0x1, PseudoVSSSEG4E32_V_M2_MASK }, // 180 |
30224 | | { 0x4, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG4E32_V_MF2_MASK }, // 181 |
30225 | | { 0x4, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG4E64_V_M1_MASK }, // 182 |
30226 | | { 0x4, 0x1, 0x1, 0x6, 0x1, PseudoVSSSEG4E64_V_M2_MASK }, // 183 |
30227 | | { 0x5, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG5E8_V_M1 }, // 184 |
30228 | | { 0x5, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG5E8_V_MF8 }, // 185 |
30229 | | { 0x5, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG5E8_V_MF4 }, // 186 |
30230 | | { 0x5, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG5E8_V_MF2 }, // 187 |
30231 | | { 0x5, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG5E16_V_M1 }, // 188 |
30232 | | { 0x5, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG5E16_V_MF4 }, // 189 |
30233 | | { 0x5, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG5E16_V_MF2 }, // 190 |
30234 | | { 0x5, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG5E32_V_M1 }, // 191 |
30235 | | { 0x5, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG5E32_V_MF2 }, // 192 |
30236 | | { 0x5, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG5E64_V_M1 }, // 193 |
30237 | | { 0x5, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG5E8_V_M1 }, // 194 |
30238 | | { 0x5, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG5E8_V_MF8 }, // 195 |
30239 | | { 0x5, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG5E8_V_MF4 }, // 196 |
30240 | | { 0x5, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG5E8_V_MF2 }, // 197 |
30241 | | { 0x5, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG5E16_V_M1 }, // 198 |
30242 | | { 0x5, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG5E16_V_MF4 }, // 199 |
30243 | | { 0x5, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG5E16_V_MF2 }, // 200 |
30244 | | { 0x5, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG5E32_V_M1 }, // 201 |
30245 | | { 0x5, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG5E32_V_MF2 }, // 202 |
30246 | | { 0x5, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG5E64_V_M1 }, // 203 |
30247 | | { 0x5, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG5E8_V_M1_MASK }, // 204 |
30248 | | { 0x5, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG5E8_V_MF8_MASK }, // 205 |
30249 | | { 0x5, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG5E8_V_MF4_MASK }, // 206 |
30250 | | { 0x5, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG5E8_V_MF2_MASK }, // 207 |
30251 | | { 0x5, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG5E16_V_M1_MASK }, // 208 |
30252 | | { 0x5, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG5E16_V_MF4_MASK }, // 209 |
30253 | | { 0x5, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG5E16_V_MF2_MASK }, // 210 |
30254 | | { 0x5, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG5E32_V_M1_MASK }, // 211 |
30255 | | { 0x5, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG5E32_V_MF2_MASK }, // 212 |
30256 | | { 0x5, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG5E64_V_M1_MASK }, // 213 |
30257 | | { 0x5, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG5E8_V_M1_MASK }, // 214 |
30258 | | { 0x5, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG5E8_V_MF8_MASK }, // 215 |
30259 | | { 0x5, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG5E8_V_MF4_MASK }, // 216 |
30260 | | { 0x5, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG5E8_V_MF2_MASK }, // 217 |
30261 | | { 0x5, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG5E16_V_M1_MASK }, // 218 |
30262 | | { 0x5, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG5E16_V_MF4_MASK }, // 219 |
30263 | | { 0x5, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG5E16_V_MF2_MASK }, // 220 |
30264 | | { 0x5, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG5E32_V_M1_MASK }, // 221 |
30265 | | { 0x5, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG5E32_V_MF2_MASK }, // 222 |
30266 | | { 0x5, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG5E64_V_M1_MASK }, // 223 |
30267 | | { 0x6, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG6E8_V_M1 }, // 224 |
30268 | | { 0x6, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG6E8_V_MF8 }, // 225 |
30269 | | { 0x6, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG6E8_V_MF4 }, // 226 |
30270 | | { 0x6, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG6E8_V_MF2 }, // 227 |
30271 | | { 0x6, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG6E16_V_M1 }, // 228 |
30272 | | { 0x6, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG6E16_V_MF4 }, // 229 |
30273 | | { 0x6, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG6E16_V_MF2 }, // 230 |
30274 | | { 0x6, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG6E32_V_M1 }, // 231 |
30275 | | { 0x6, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG6E32_V_MF2 }, // 232 |
30276 | | { 0x6, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG6E64_V_M1 }, // 233 |
30277 | | { 0x6, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG6E8_V_M1 }, // 234 |
30278 | | { 0x6, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG6E8_V_MF8 }, // 235 |
30279 | | { 0x6, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG6E8_V_MF4 }, // 236 |
30280 | | { 0x6, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG6E8_V_MF2 }, // 237 |
30281 | | { 0x6, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG6E16_V_M1 }, // 238 |
30282 | | { 0x6, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG6E16_V_MF4 }, // 239 |
30283 | | { 0x6, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG6E16_V_MF2 }, // 240 |
30284 | | { 0x6, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG6E32_V_M1 }, // 241 |
30285 | | { 0x6, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG6E32_V_MF2 }, // 242 |
30286 | | { 0x6, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG6E64_V_M1 }, // 243 |
30287 | | { 0x6, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG6E8_V_M1_MASK }, // 244 |
30288 | | { 0x6, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG6E8_V_MF8_MASK }, // 245 |
30289 | | { 0x6, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG6E8_V_MF4_MASK }, // 246 |
30290 | | { 0x6, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG6E8_V_MF2_MASK }, // 247 |
30291 | | { 0x6, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG6E16_V_M1_MASK }, // 248 |
30292 | | { 0x6, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG6E16_V_MF4_MASK }, // 249 |
30293 | | { 0x6, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG6E16_V_MF2_MASK }, // 250 |
30294 | | { 0x6, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG6E32_V_M1_MASK }, // 251 |
30295 | | { 0x6, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG6E32_V_MF2_MASK }, // 252 |
30296 | | { 0x6, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG6E64_V_M1_MASK }, // 253 |
30297 | | { 0x6, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG6E8_V_M1_MASK }, // 254 |
30298 | | { 0x6, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG6E8_V_MF8_MASK }, // 255 |
30299 | | { 0x6, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG6E8_V_MF4_MASK }, // 256 |
30300 | | { 0x6, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG6E8_V_MF2_MASK }, // 257 |
30301 | | { 0x6, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG6E16_V_M1_MASK }, // 258 |
30302 | | { 0x6, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG6E16_V_MF4_MASK }, // 259 |
30303 | | { 0x6, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG6E16_V_MF2_MASK }, // 260 |
30304 | | { 0x6, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG6E32_V_M1_MASK }, // 261 |
30305 | | { 0x6, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG6E32_V_MF2_MASK }, // 262 |
30306 | | { 0x6, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG6E64_V_M1_MASK }, // 263 |
30307 | | { 0x7, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG7E8_V_M1 }, // 264 |
30308 | | { 0x7, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG7E8_V_MF8 }, // 265 |
30309 | | { 0x7, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG7E8_V_MF4 }, // 266 |
30310 | | { 0x7, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG7E8_V_MF2 }, // 267 |
30311 | | { 0x7, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG7E16_V_M1 }, // 268 |
30312 | | { 0x7, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG7E16_V_MF4 }, // 269 |
30313 | | { 0x7, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG7E16_V_MF2 }, // 270 |
30314 | | { 0x7, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG7E32_V_M1 }, // 271 |
30315 | | { 0x7, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG7E32_V_MF2 }, // 272 |
30316 | | { 0x7, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG7E64_V_M1 }, // 273 |
30317 | | { 0x7, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG7E8_V_M1 }, // 274 |
30318 | | { 0x7, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG7E8_V_MF8 }, // 275 |
30319 | | { 0x7, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG7E8_V_MF4 }, // 276 |
30320 | | { 0x7, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG7E8_V_MF2 }, // 277 |
30321 | | { 0x7, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG7E16_V_M1 }, // 278 |
30322 | | { 0x7, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG7E16_V_MF4 }, // 279 |
30323 | | { 0x7, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG7E16_V_MF2 }, // 280 |
30324 | | { 0x7, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG7E32_V_M1 }, // 281 |
30325 | | { 0x7, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG7E32_V_MF2 }, // 282 |
30326 | | { 0x7, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG7E64_V_M1 }, // 283 |
30327 | | { 0x7, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG7E8_V_M1_MASK }, // 284 |
30328 | | { 0x7, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG7E8_V_MF8_MASK }, // 285 |
30329 | | { 0x7, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG7E8_V_MF4_MASK }, // 286 |
30330 | | { 0x7, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG7E8_V_MF2_MASK }, // 287 |
30331 | | { 0x7, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG7E16_V_M1_MASK }, // 288 |
30332 | | { 0x7, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG7E16_V_MF4_MASK }, // 289 |
30333 | | { 0x7, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG7E16_V_MF2_MASK }, // 290 |
30334 | | { 0x7, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG7E32_V_M1_MASK }, // 291 |
30335 | | { 0x7, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG7E32_V_MF2_MASK }, // 292 |
30336 | | { 0x7, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG7E64_V_M1_MASK }, // 293 |
30337 | | { 0x7, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG7E8_V_M1_MASK }, // 294 |
30338 | | { 0x7, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG7E8_V_MF8_MASK }, // 295 |
30339 | | { 0x7, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG7E8_V_MF4_MASK }, // 296 |
30340 | | { 0x7, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG7E8_V_MF2_MASK }, // 297 |
30341 | | { 0x7, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG7E16_V_M1_MASK }, // 298 |
30342 | | { 0x7, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG7E16_V_MF4_MASK }, // 299 |
30343 | | { 0x7, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG7E16_V_MF2_MASK }, // 300 |
30344 | | { 0x7, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG7E32_V_M1_MASK }, // 301 |
30345 | | { 0x7, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG7E32_V_MF2_MASK }, // 302 |
30346 | | { 0x7, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG7E64_V_M1_MASK }, // 303 |
30347 | | { 0x8, 0x0, 0x0, 0x3, 0x0, PseudoVSSEG8E8_V_M1 }, // 304 |
30348 | | { 0x8, 0x0, 0x0, 0x3, 0x5, PseudoVSSEG8E8_V_MF8 }, // 305 |
30349 | | { 0x8, 0x0, 0x0, 0x3, 0x6, PseudoVSSEG8E8_V_MF4 }, // 306 |
30350 | | { 0x8, 0x0, 0x0, 0x3, 0x7, PseudoVSSEG8E8_V_MF2 }, // 307 |
30351 | | { 0x8, 0x0, 0x0, 0x4, 0x0, PseudoVSSEG8E16_V_M1 }, // 308 |
30352 | | { 0x8, 0x0, 0x0, 0x4, 0x6, PseudoVSSEG8E16_V_MF4 }, // 309 |
30353 | | { 0x8, 0x0, 0x0, 0x4, 0x7, PseudoVSSEG8E16_V_MF2 }, // 310 |
30354 | | { 0x8, 0x0, 0x0, 0x5, 0x0, PseudoVSSEG8E32_V_M1 }, // 311 |
30355 | | { 0x8, 0x0, 0x0, 0x5, 0x7, PseudoVSSEG8E32_V_MF2 }, // 312 |
30356 | | { 0x8, 0x0, 0x0, 0x6, 0x0, PseudoVSSEG8E64_V_M1 }, // 313 |
30357 | | { 0x8, 0x0, 0x1, 0x3, 0x0, PseudoVSSSEG8E8_V_M1 }, // 314 |
30358 | | { 0x8, 0x0, 0x1, 0x3, 0x5, PseudoVSSSEG8E8_V_MF8 }, // 315 |
30359 | | { 0x8, 0x0, 0x1, 0x3, 0x6, PseudoVSSSEG8E8_V_MF4 }, // 316 |
30360 | | { 0x8, 0x0, 0x1, 0x3, 0x7, PseudoVSSSEG8E8_V_MF2 }, // 317 |
30361 | | { 0x8, 0x0, 0x1, 0x4, 0x0, PseudoVSSSEG8E16_V_M1 }, // 318 |
30362 | | { 0x8, 0x0, 0x1, 0x4, 0x6, PseudoVSSSEG8E16_V_MF4 }, // 319 |
30363 | | { 0x8, 0x0, 0x1, 0x4, 0x7, PseudoVSSSEG8E16_V_MF2 }, // 320 |
30364 | | { 0x8, 0x0, 0x1, 0x5, 0x0, PseudoVSSSEG8E32_V_M1 }, // 321 |
30365 | | { 0x8, 0x0, 0x1, 0x5, 0x7, PseudoVSSSEG8E32_V_MF2 }, // 322 |
30366 | | { 0x8, 0x0, 0x1, 0x6, 0x0, PseudoVSSSEG8E64_V_M1 }, // 323 |
30367 | | { 0x8, 0x1, 0x0, 0x3, 0x0, PseudoVSSEG8E8_V_M1_MASK }, // 324 |
30368 | | { 0x8, 0x1, 0x0, 0x3, 0x5, PseudoVSSEG8E8_V_MF8_MASK }, // 325 |
30369 | | { 0x8, 0x1, 0x0, 0x3, 0x6, PseudoVSSEG8E8_V_MF4_MASK }, // 326 |
30370 | | { 0x8, 0x1, 0x0, 0x3, 0x7, PseudoVSSEG8E8_V_MF2_MASK }, // 327 |
30371 | | { 0x8, 0x1, 0x0, 0x4, 0x0, PseudoVSSEG8E16_V_M1_MASK }, // 328 |
30372 | | { 0x8, 0x1, 0x0, 0x4, 0x6, PseudoVSSEG8E16_V_MF4_MASK }, // 329 |
30373 | | { 0x8, 0x1, 0x0, 0x4, 0x7, PseudoVSSEG8E16_V_MF2_MASK }, // 330 |
30374 | | { 0x8, 0x1, 0x0, 0x5, 0x0, PseudoVSSEG8E32_V_M1_MASK }, // 331 |
30375 | | { 0x8, 0x1, 0x0, 0x5, 0x7, PseudoVSSEG8E32_V_MF2_MASK }, // 332 |
30376 | | { 0x8, 0x1, 0x0, 0x6, 0x0, PseudoVSSEG8E64_V_M1_MASK }, // 333 |
30377 | | { 0x8, 0x1, 0x1, 0x3, 0x0, PseudoVSSSEG8E8_V_M1_MASK }, // 334 |
30378 | | { 0x8, 0x1, 0x1, 0x3, 0x5, PseudoVSSSEG8E8_V_MF8_MASK }, // 335 |
30379 | | { 0x8, 0x1, 0x1, 0x3, 0x6, PseudoVSSSEG8E8_V_MF4_MASK }, // 336 |
30380 | | { 0x8, 0x1, 0x1, 0x3, 0x7, PseudoVSSSEG8E8_V_MF2_MASK }, // 337 |
30381 | | { 0x8, 0x1, 0x1, 0x4, 0x0, PseudoVSSSEG8E16_V_M1_MASK }, // 338 |
30382 | | { 0x8, 0x1, 0x1, 0x4, 0x6, PseudoVSSSEG8E16_V_MF4_MASK }, // 339 |
30383 | | { 0x8, 0x1, 0x1, 0x4, 0x7, PseudoVSSSEG8E16_V_MF2_MASK }, // 340 |
30384 | | { 0x8, 0x1, 0x1, 0x5, 0x0, PseudoVSSSEG8E32_V_M1_MASK }, // 341 |
30385 | | { 0x8, 0x1, 0x1, 0x5, 0x7, PseudoVSSSEG8E32_V_MF2_MASK }, // 342 |
30386 | | { 0x8, 0x1, 0x1, 0x6, 0x0, PseudoVSSSEG8E64_V_M1_MASK }, // 343 |
30387 | | }; |
30388 | | |
30389 | | const RISCV_VSSEGPseudo *RISCV_getVSSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Strided, uint8_t Log2SEW, uint8_t LMUL) { |
30390 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), NFMaskedStridedLog2SEWLMUL); |
30391 | | if (i == -1) |
30392 | | return NULL; |
30393 | | else |
30394 | | return &RISCVVSSEGTable[Index[i].index]; |
30395 | | } |
30396 | | |
30397 | | #endif |
30398 | | |
30399 | | #ifdef GET_RISCVVSXSEGTable_IMPL |
30400 | | static const RISCV_VSXSEGPseudo RISCVVSXSEGTable[] = { |
30401 | | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG2EI8_V_M1_M1 }, // 0 |
30402 | | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG2EI8_V_MF8_M1 }, // 1 |
30403 | | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG2EI8_V_MF4_M1 }, // 2 |
30404 | | { 0x2, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG2EI8_V_MF2_M1 }, // 3 |
30405 | | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG2EI8_V_M1_M2 }, // 4 |
30406 | | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG2EI8_V_M2_M2 }, // 5 |
30407 | | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG2EI8_V_MF4_M2 }, // 6 |
30408 | | { 0x2, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG2EI8_V_MF2_M2 }, // 7 |
30409 | | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVSUXSEG2EI8_V_M1_M4 }, // 8 |
30410 | | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVSUXSEG2EI8_V_M2_M4 }, // 9 |
30411 | | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVSUXSEG2EI8_V_M4_M4 }, // 10 |
30412 | | { 0x2, 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVSUXSEG2EI8_V_MF2_M4 }, // 11 |
30413 | | { 0x2, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF8 }, // 12 |
30414 | | { 0x2, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF4 }, // 13 |
30415 | | { 0x2, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF4 }, // 14 |
30416 | | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF2 }, // 15 |
30417 | | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF2 }, // 16 |
30418 | | { 0x2, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG2EI8_V_MF2_MF2 }, // 17 |
30419 | | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG2EI16_V_M1_M1 }, // 18 |
30420 | | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG2EI16_V_M2_M1 }, // 19 |
30421 | | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG2EI16_V_MF4_M1 }, // 20 |
30422 | | { 0x2, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG2EI16_V_MF2_M1 }, // 21 |
30423 | | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG2EI16_V_M1_M2 }, // 22 |
30424 | | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG2EI16_V_M2_M2 }, // 23 |
30425 | | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG2EI16_V_M4_M2 }, // 24 |
30426 | | { 0x2, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG2EI16_V_MF2_M2 }, // 25 |
30427 | | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVSUXSEG2EI16_V_M1_M4 }, // 26 |
30428 | | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVSUXSEG2EI16_V_M2_M4 }, // 27 |
30429 | | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVSUXSEG2EI16_V_M4_M4 }, // 28 |
30430 | | { 0x2, 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVSUXSEG2EI16_V_M8_M4 }, // 29 |
30431 | | { 0x2, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF8 }, // 30 |
30432 | | { 0x2, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF4 }, // 31 |
30433 | | { 0x2, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF4 }, // 32 |
30434 | | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG2EI16_V_M1_MF2 }, // 33 |
30435 | | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF2 }, // 34 |
30436 | | { 0x2, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF2 }, // 35 |
30437 | | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG2EI32_V_M1_M1 }, // 36 |
30438 | | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG2EI32_V_M2_M1 }, // 37 |
30439 | | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG2EI32_V_M4_M1 }, // 38 |
30440 | | { 0x2, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG2EI32_V_MF2_M1 }, // 39 |
30441 | | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG2EI32_V_M1_M2 }, // 40 |
30442 | | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG2EI32_V_M2_M2 }, // 41 |
30443 | | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG2EI32_V_M4_M2 }, // 42 |
30444 | | { 0x2, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG2EI32_V_M8_M2 }, // 43 |
30445 | | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVSUXSEG2EI32_V_M2_M4 }, // 44 |
30446 | | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVSUXSEG2EI32_V_M4_M4 }, // 45 |
30447 | | { 0x2, 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVSUXSEG2EI32_V_M8_M4 }, // 46 |
30448 | | { 0x2, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF8 }, // 47 |
30449 | | { 0x2, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG2EI32_V_M1_MF4 }, // 48 |
30450 | | { 0x2, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF4 }, // 49 |
30451 | | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG2EI32_V_M1_MF2 }, // 50 |
30452 | | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG2EI32_V_M2_MF2 }, // 51 |
30453 | | { 0x2, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF2 }, // 52 |
30454 | | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG2EI64_V_M1_M1 }, // 53 |
30455 | | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG2EI64_V_M2_M1 }, // 54 |
30456 | | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG2EI64_V_M4_M1 }, // 55 |
30457 | | { 0x2, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG2EI64_V_M8_M1 }, // 56 |
30458 | | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG2EI64_V_M2_M2 }, // 57 |
30459 | | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG2EI64_V_M4_M2 }, // 58 |
30460 | | { 0x2, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG2EI64_V_M8_M2 }, // 59 |
30461 | | { 0x2, 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVSUXSEG2EI64_V_M4_M4 }, // 60 |
30462 | | { 0x2, 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVSUXSEG2EI64_V_M8_M4 }, // 61 |
30463 | | { 0x2, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG2EI64_V_M1_MF8 }, // 62 |
30464 | | { 0x2, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG2EI64_V_M1_MF4 }, // 63 |
30465 | | { 0x2, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG2EI64_V_M2_MF4 }, // 64 |
30466 | | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG2EI64_V_M1_MF2 }, // 65 |
30467 | | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG2EI64_V_M2_MF2 }, // 66 |
30468 | | { 0x2, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG2EI64_V_M4_MF2 }, // 67 |
30469 | | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG2EI8_V_M1_M1 }, // 68 |
30470 | | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG2EI8_V_MF8_M1 }, // 69 |
30471 | | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG2EI8_V_MF4_M1 }, // 70 |
30472 | | { 0x2, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG2EI8_V_MF2_M1 }, // 71 |
30473 | | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG2EI8_V_M1_M2 }, // 72 |
30474 | | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG2EI8_V_M2_M2 }, // 73 |
30475 | | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG2EI8_V_MF4_M2 }, // 74 |
30476 | | { 0x2, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG2EI8_V_MF2_M2 }, // 75 |
30477 | | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVSOXSEG2EI8_V_M1_M4 }, // 76 |
30478 | | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVSOXSEG2EI8_V_M2_M4 }, // 77 |
30479 | | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVSOXSEG2EI8_V_M4_M4 }, // 78 |
30480 | | { 0x2, 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVSOXSEG2EI8_V_MF2_M4 }, // 79 |
30481 | | { 0x2, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF8 }, // 80 |
30482 | | { 0x2, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF4 }, // 81 |
30483 | | { 0x2, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF4 }, // 82 |
30484 | | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF2 }, // 83 |
30485 | | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF2 }, // 84 |
30486 | | { 0x2, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG2EI8_V_MF2_MF2 }, // 85 |
30487 | | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG2EI16_V_M1_M1 }, // 86 |
30488 | | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG2EI16_V_M2_M1 }, // 87 |
30489 | | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG2EI16_V_MF4_M1 }, // 88 |
30490 | | { 0x2, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG2EI16_V_MF2_M1 }, // 89 |
30491 | | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG2EI16_V_M1_M2 }, // 90 |
30492 | | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG2EI16_V_M2_M2 }, // 91 |
30493 | | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG2EI16_V_M4_M2 }, // 92 |
30494 | | { 0x2, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG2EI16_V_MF2_M2 }, // 93 |
30495 | | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVSOXSEG2EI16_V_M1_M4 }, // 94 |
30496 | | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVSOXSEG2EI16_V_M2_M4 }, // 95 |
30497 | | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVSOXSEG2EI16_V_M4_M4 }, // 96 |
30498 | | { 0x2, 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVSOXSEG2EI16_V_M8_M4 }, // 97 |
30499 | | { 0x2, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF8 }, // 98 |
30500 | | { 0x2, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF4 }, // 99 |
30501 | | { 0x2, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF4 }, // 100 |
30502 | | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG2EI16_V_M1_MF2 }, // 101 |
30503 | | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF2 }, // 102 |
30504 | | { 0x2, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF2 }, // 103 |
30505 | | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG2EI32_V_M1_M1 }, // 104 |
30506 | | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG2EI32_V_M2_M1 }, // 105 |
30507 | | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG2EI32_V_M4_M1 }, // 106 |
30508 | | { 0x2, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG2EI32_V_MF2_M1 }, // 107 |
30509 | | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG2EI32_V_M1_M2 }, // 108 |
30510 | | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG2EI32_V_M2_M2 }, // 109 |
30511 | | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG2EI32_V_M4_M2 }, // 110 |
30512 | | { 0x2, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG2EI32_V_M8_M2 }, // 111 |
30513 | | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVSOXSEG2EI32_V_M2_M4 }, // 112 |
30514 | | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVSOXSEG2EI32_V_M4_M4 }, // 113 |
30515 | | { 0x2, 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVSOXSEG2EI32_V_M8_M4 }, // 114 |
30516 | | { 0x2, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF8 }, // 115 |
30517 | | { 0x2, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG2EI32_V_M1_MF4 }, // 116 |
30518 | | { 0x2, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF4 }, // 117 |
30519 | | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG2EI32_V_M1_MF2 }, // 118 |
30520 | | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG2EI32_V_M2_MF2 }, // 119 |
30521 | | { 0x2, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF2 }, // 120 |
30522 | | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG2EI64_V_M1_M1 }, // 121 |
30523 | | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG2EI64_V_M2_M1 }, // 122 |
30524 | | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG2EI64_V_M4_M1 }, // 123 |
30525 | | { 0x2, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG2EI64_V_M8_M1 }, // 124 |
30526 | | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG2EI64_V_M2_M2 }, // 125 |
30527 | | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG2EI64_V_M4_M2 }, // 126 |
30528 | | { 0x2, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG2EI64_V_M8_M2 }, // 127 |
30529 | | { 0x2, 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVSOXSEG2EI64_V_M4_M4 }, // 128 |
30530 | | { 0x2, 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVSOXSEG2EI64_V_M8_M4 }, // 129 |
30531 | | { 0x2, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG2EI64_V_M1_MF8 }, // 130 |
30532 | | { 0x2, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG2EI64_V_M1_MF4 }, // 131 |
30533 | | { 0x2, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG2EI64_V_M2_MF4 }, // 132 |
30534 | | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG2EI64_V_M1_MF2 }, // 133 |
30535 | | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG2EI64_V_M2_MF2 }, // 134 |
30536 | | { 0x2, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG2EI64_V_M4_MF2 }, // 135 |
30537 | | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG2EI8_V_M1_M1_MASK }, // 136 |
30538 | | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG2EI8_V_MF8_M1_MASK }, // 137 |
30539 | | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG2EI8_V_MF4_M1_MASK }, // 138 |
30540 | | { 0x2, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG2EI8_V_MF2_M1_MASK }, // 139 |
30541 | | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG2EI8_V_M1_M2_MASK }, // 140 |
30542 | | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG2EI8_V_M2_M2_MASK }, // 141 |
30543 | | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG2EI8_V_MF4_M2_MASK }, // 142 |
30544 | | { 0x2, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG2EI8_V_MF2_M2_MASK }, // 143 |
30545 | | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVSUXSEG2EI8_V_M1_M4_MASK }, // 144 |
30546 | | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVSUXSEG2EI8_V_M2_M4_MASK }, // 145 |
30547 | | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVSUXSEG2EI8_V_M4_M4_MASK }, // 146 |
30548 | | { 0x2, 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVSUXSEG2EI8_V_MF2_M4_MASK }, // 147 |
30549 | | { 0x2, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF8_MASK }, // 148 |
30550 | | { 0x2, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF4_MASK }, // 149 |
30551 | | { 0x2, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF4_MASK }, // 150 |
30552 | | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG2EI8_V_MF8_MF2_MASK }, // 151 |
30553 | | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG2EI8_V_MF4_MF2_MASK }, // 152 |
30554 | | { 0x2, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG2EI8_V_MF2_MF2_MASK }, // 153 |
30555 | | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG2EI16_V_M1_M1_MASK }, // 154 |
30556 | | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG2EI16_V_M2_M1_MASK }, // 155 |
30557 | | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG2EI16_V_MF4_M1_MASK }, // 156 |
30558 | | { 0x2, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG2EI16_V_MF2_M1_MASK }, // 157 |
30559 | | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG2EI16_V_M1_M2_MASK }, // 158 |
30560 | | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG2EI16_V_M2_M2_MASK }, // 159 |
30561 | | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG2EI16_V_M4_M2_MASK }, // 160 |
30562 | | { 0x2, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG2EI16_V_MF2_M2_MASK }, // 161 |
30563 | | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVSUXSEG2EI16_V_M1_M4_MASK }, // 162 |
30564 | | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVSUXSEG2EI16_V_M2_M4_MASK }, // 163 |
30565 | | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVSUXSEG2EI16_V_M4_M4_MASK }, // 164 |
30566 | | { 0x2, 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVSUXSEG2EI16_V_M8_M4_MASK }, // 165 |
30567 | | { 0x2, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF8_MASK }, // 166 |
30568 | | { 0x2, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF4_MASK }, // 167 |
30569 | | { 0x2, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF4_MASK }, // 168 |
30570 | | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG2EI16_V_M1_MF2_MASK }, // 169 |
30571 | | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG2EI16_V_MF4_MF2_MASK }, // 170 |
30572 | | { 0x2, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG2EI16_V_MF2_MF2_MASK }, // 171 |
30573 | | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG2EI32_V_M1_M1_MASK }, // 172 |
30574 | | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG2EI32_V_M2_M1_MASK }, // 173 |
30575 | | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG2EI32_V_M4_M1_MASK }, // 174 |
30576 | | { 0x2, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG2EI32_V_MF2_M1_MASK }, // 175 |
30577 | | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG2EI32_V_M1_M2_MASK }, // 176 |
30578 | | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG2EI32_V_M2_M2_MASK }, // 177 |
30579 | | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG2EI32_V_M4_M2_MASK }, // 178 |
30580 | | { 0x2, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG2EI32_V_M8_M2_MASK }, // 179 |
30581 | | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVSUXSEG2EI32_V_M2_M4_MASK }, // 180 |
30582 | | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVSUXSEG2EI32_V_M4_M4_MASK }, // 181 |
30583 | | { 0x2, 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVSUXSEG2EI32_V_M8_M4_MASK }, // 182 |
30584 | | { 0x2, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF8_MASK }, // 183 |
30585 | | { 0x2, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG2EI32_V_M1_MF4_MASK }, // 184 |
30586 | | { 0x2, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF4_MASK }, // 185 |
30587 | | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG2EI32_V_M1_MF2_MASK }, // 186 |
30588 | | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG2EI32_V_M2_MF2_MASK }, // 187 |
30589 | | { 0x2, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG2EI32_V_MF2_MF2_MASK }, // 188 |
30590 | | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG2EI64_V_M1_M1_MASK }, // 189 |
30591 | | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG2EI64_V_M2_M1_MASK }, // 190 |
30592 | | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG2EI64_V_M4_M1_MASK }, // 191 |
30593 | | { 0x2, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG2EI64_V_M8_M1_MASK }, // 192 |
30594 | | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG2EI64_V_M2_M2_MASK }, // 193 |
30595 | | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG2EI64_V_M4_M2_MASK }, // 194 |
30596 | | { 0x2, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG2EI64_V_M8_M2_MASK }, // 195 |
30597 | | { 0x2, 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVSUXSEG2EI64_V_M4_M4_MASK }, // 196 |
30598 | | { 0x2, 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVSUXSEG2EI64_V_M8_M4_MASK }, // 197 |
30599 | | { 0x2, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG2EI64_V_M1_MF8_MASK }, // 198 |
30600 | | { 0x2, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG2EI64_V_M1_MF4_MASK }, // 199 |
30601 | | { 0x2, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG2EI64_V_M2_MF4_MASK }, // 200 |
30602 | | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG2EI64_V_M1_MF2_MASK }, // 201 |
30603 | | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG2EI64_V_M2_MF2_MASK }, // 202 |
30604 | | { 0x2, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG2EI64_V_M4_MF2_MASK }, // 203 |
30605 | | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG2EI8_V_M1_M1_MASK }, // 204 |
30606 | | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG2EI8_V_MF8_M1_MASK }, // 205 |
30607 | | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG2EI8_V_MF4_M1_MASK }, // 206 |
30608 | | { 0x2, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG2EI8_V_MF2_M1_MASK }, // 207 |
30609 | | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG2EI8_V_M1_M2_MASK }, // 208 |
30610 | | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG2EI8_V_M2_M2_MASK }, // 209 |
30611 | | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG2EI8_V_MF4_M2_MASK }, // 210 |
30612 | | { 0x2, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG2EI8_V_MF2_M2_MASK }, // 211 |
30613 | | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVSOXSEG2EI8_V_M1_M4_MASK }, // 212 |
30614 | | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVSOXSEG2EI8_V_M2_M4_MASK }, // 213 |
30615 | | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVSOXSEG2EI8_V_M4_M4_MASK }, // 214 |
30616 | | { 0x2, 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVSOXSEG2EI8_V_MF2_M4_MASK }, // 215 |
30617 | | { 0x2, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF8_MASK }, // 216 |
30618 | | { 0x2, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF4_MASK }, // 217 |
30619 | | { 0x2, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF4_MASK }, // 218 |
30620 | | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG2EI8_V_MF8_MF2_MASK }, // 219 |
30621 | | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG2EI8_V_MF4_MF2_MASK }, // 220 |
30622 | | { 0x2, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG2EI8_V_MF2_MF2_MASK }, // 221 |
30623 | | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG2EI16_V_M1_M1_MASK }, // 222 |
30624 | | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG2EI16_V_M2_M1_MASK }, // 223 |
30625 | | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG2EI16_V_MF4_M1_MASK }, // 224 |
30626 | | { 0x2, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG2EI16_V_MF2_M1_MASK }, // 225 |
30627 | | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG2EI16_V_M1_M2_MASK }, // 226 |
30628 | | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG2EI16_V_M2_M2_MASK }, // 227 |
30629 | | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG2EI16_V_M4_M2_MASK }, // 228 |
30630 | | { 0x2, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG2EI16_V_MF2_M2_MASK }, // 229 |
30631 | | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVSOXSEG2EI16_V_M1_M4_MASK }, // 230 |
30632 | | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVSOXSEG2EI16_V_M2_M4_MASK }, // 231 |
30633 | | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVSOXSEG2EI16_V_M4_M4_MASK }, // 232 |
30634 | | { 0x2, 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVSOXSEG2EI16_V_M8_M4_MASK }, // 233 |
30635 | | { 0x2, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF8_MASK }, // 234 |
30636 | | { 0x2, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF4_MASK }, // 235 |
30637 | | { 0x2, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF4_MASK }, // 236 |
30638 | | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG2EI16_V_M1_MF2_MASK }, // 237 |
30639 | | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG2EI16_V_MF4_MF2_MASK }, // 238 |
30640 | | { 0x2, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG2EI16_V_MF2_MF2_MASK }, // 239 |
30641 | | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG2EI32_V_M1_M1_MASK }, // 240 |
30642 | | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG2EI32_V_M2_M1_MASK }, // 241 |
30643 | | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG2EI32_V_M4_M1_MASK }, // 242 |
30644 | | { 0x2, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG2EI32_V_MF2_M1_MASK }, // 243 |
30645 | | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG2EI32_V_M1_M2_MASK }, // 244 |
30646 | | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG2EI32_V_M2_M2_MASK }, // 245 |
30647 | | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG2EI32_V_M4_M2_MASK }, // 246 |
30648 | | { 0x2, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG2EI32_V_M8_M2_MASK }, // 247 |
30649 | | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVSOXSEG2EI32_V_M2_M4_MASK }, // 248 |
30650 | | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVSOXSEG2EI32_V_M4_M4_MASK }, // 249 |
30651 | | { 0x2, 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVSOXSEG2EI32_V_M8_M4_MASK }, // 250 |
30652 | | { 0x2, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF8_MASK }, // 251 |
30653 | | { 0x2, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG2EI32_V_M1_MF4_MASK }, // 252 |
30654 | | { 0x2, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF4_MASK }, // 253 |
30655 | | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG2EI32_V_M1_MF2_MASK }, // 254 |
30656 | | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG2EI32_V_M2_MF2_MASK }, // 255 |
30657 | | { 0x2, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG2EI32_V_MF2_MF2_MASK }, // 256 |
30658 | | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG2EI64_V_M1_M1_MASK }, // 257 |
30659 | | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG2EI64_V_M2_M1_MASK }, // 258 |
30660 | | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG2EI64_V_M4_M1_MASK }, // 259 |
30661 | | { 0x2, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG2EI64_V_M8_M1_MASK }, // 260 |
30662 | | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG2EI64_V_M2_M2_MASK }, // 261 |
30663 | | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG2EI64_V_M4_M2_MASK }, // 262 |
30664 | | { 0x2, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG2EI64_V_M8_M2_MASK }, // 263 |
30665 | | { 0x2, 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVSOXSEG2EI64_V_M4_M4_MASK }, // 264 |
30666 | | { 0x2, 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVSOXSEG2EI64_V_M8_M4_MASK }, // 265 |
30667 | | { 0x2, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG2EI64_V_M1_MF8_MASK }, // 266 |
30668 | | { 0x2, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG2EI64_V_M1_MF4_MASK }, // 267 |
30669 | | { 0x2, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG2EI64_V_M2_MF4_MASK }, // 268 |
30670 | | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG2EI64_V_M1_MF2_MASK }, // 269 |
30671 | | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG2EI64_V_M2_MF2_MASK }, // 270 |
30672 | | { 0x2, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG2EI64_V_M4_MF2_MASK }, // 271 |
30673 | | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG3EI8_V_M1_M1 }, // 272 |
30674 | | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG3EI8_V_MF8_M1 }, // 273 |
30675 | | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG3EI8_V_MF4_M1 }, // 274 |
30676 | | { 0x3, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG3EI8_V_MF2_M1 }, // 275 |
30677 | | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG3EI8_V_M1_M2 }, // 276 |
30678 | | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG3EI8_V_M2_M2 }, // 277 |
30679 | | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG3EI8_V_MF4_M2 }, // 278 |
30680 | | { 0x3, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG3EI8_V_MF2_M2 }, // 279 |
30681 | | { 0x3, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF8 }, // 280 |
30682 | | { 0x3, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF4 }, // 281 |
30683 | | { 0x3, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF4 }, // 282 |
30684 | | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF2 }, // 283 |
30685 | | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF2 }, // 284 |
30686 | | { 0x3, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG3EI8_V_MF2_MF2 }, // 285 |
30687 | | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG3EI16_V_M1_M1 }, // 286 |
30688 | | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG3EI16_V_M2_M1 }, // 287 |
30689 | | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG3EI16_V_MF4_M1 }, // 288 |
30690 | | { 0x3, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG3EI16_V_MF2_M1 }, // 289 |
30691 | | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG3EI16_V_M1_M2 }, // 290 |
30692 | | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG3EI16_V_M2_M2 }, // 291 |
30693 | | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG3EI16_V_M4_M2 }, // 292 |
30694 | | { 0x3, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG3EI16_V_MF2_M2 }, // 293 |
30695 | | { 0x3, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF8 }, // 294 |
30696 | | { 0x3, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF4 }, // 295 |
30697 | | { 0x3, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF4 }, // 296 |
30698 | | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG3EI16_V_M1_MF2 }, // 297 |
30699 | | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF2 }, // 298 |
30700 | | { 0x3, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF2 }, // 299 |
30701 | | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG3EI32_V_M1_M1 }, // 300 |
30702 | | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG3EI32_V_M2_M1 }, // 301 |
30703 | | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG3EI32_V_M4_M1 }, // 302 |
30704 | | { 0x3, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG3EI32_V_MF2_M1 }, // 303 |
30705 | | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG3EI32_V_M1_M2 }, // 304 |
30706 | | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG3EI32_V_M2_M2 }, // 305 |
30707 | | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG3EI32_V_M4_M2 }, // 306 |
30708 | | { 0x3, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG3EI32_V_M8_M2 }, // 307 |
30709 | | { 0x3, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF8 }, // 308 |
30710 | | { 0x3, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG3EI32_V_M1_MF4 }, // 309 |
30711 | | { 0x3, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF4 }, // 310 |
30712 | | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG3EI32_V_M1_MF2 }, // 311 |
30713 | | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG3EI32_V_M2_MF2 }, // 312 |
30714 | | { 0x3, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF2 }, // 313 |
30715 | | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG3EI64_V_M1_M1 }, // 314 |
30716 | | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG3EI64_V_M2_M1 }, // 315 |
30717 | | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG3EI64_V_M4_M1 }, // 316 |
30718 | | { 0x3, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG3EI64_V_M8_M1 }, // 317 |
30719 | | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG3EI64_V_M2_M2 }, // 318 |
30720 | | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG3EI64_V_M4_M2 }, // 319 |
30721 | | { 0x3, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG3EI64_V_M8_M2 }, // 320 |
30722 | | { 0x3, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG3EI64_V_M1_MF8 }, // 321 |
30723 | | { 0x3, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG3EI64_V_M1_MF4 }, // 322 |
30724 | | { 0x3, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG3EI64_V_M2_MF4 }, // 323 |
30725 | | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG3EI64_V_M1_MF2 }, // 324 |
30726 | | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG3EI64_V_M2_MF2 }, // 325 |
30727 | | { 0x3, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG3EI64_V_M4_MF2 }, // 326 |
30728 | | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG3EI8_V_M1_M1 }, // 327 |
30729 | | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG3EI8_V_MF8_M1 }, // 328 |
30730 | | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG3EI8_V_MF4_M1 }, // 329 |
30731 | | { 0x3, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG3EI8_V_MF2_M1 }, // 330 |
30732 | | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG3EI8_V_M1_M2 }, // 331 |
30733 | | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG3EI8_V_M2_M2 }, // 332 |
30734 | | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG3EI8_V_MF4_M2 }, // 333 |
30735 | | { 0x3, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG3EI8_V_MF2_M2 }, // 334 |
30736 | | { 0x3, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF8 }, // 335 |
30737 | | { 0x3, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF4 }, // 336 |
30738 | | { 0x3, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF4 }, // 337 |
30739 | | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF2 }, // 338 |
30740 | | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF2 }, // 339 |
30741 | | { 0x3, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG3EI8_V_MF2_MF2 }, // 340 |
30742 | | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG3EI16_V_M1_M1 }, // 341 |
30743 | | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG3EI16_V_M2_M1 }, // 342 |
30744 | | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG3EI16_V_MF4_M1 }, // 343 |
30745 | | { 0x3, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG3EI16_V_MF2_M1 }, // 344 |
30746 | | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG3EI16_V_M1_M2 }, // 345 |
30747 | | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG3EI16_V_M2_M2 }, // 346 |
30748 | | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG3EI16_V_M4_M2 }, // 347 |
30749 | | { 0x3, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG3EI16_V_MF2_M2 }, // 348 |
30750 | | { 0x3, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF8 }, // 349 |
30751 | | { 0x3, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF4 }, // 350 |
30752 | | { 0x3, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF4 }, // 351 |
30753 | | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG3EI16_V_M1_MF2 }, // 352 |
30754 | | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF2 }, // 353 |
30755 | | { 0x3, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF2 }, // 354 |
30756 | | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG3EI32_V_M1_M1 }, // 355 |
30757 | | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG3EI32_V_M2_M1 }, // 356 |
30758 | | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG3EI32_V_M4_M1 }, // 357 |
30759 | | { 0x3, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG3EI32_V_MF2_M1 }, // 358 |
30760 | | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG3EI32_V_M1_M2 }, // 359 |
30761 | | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG3EI32_V_M2_M2 }, // 360 |
30762 | | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG3EI32_V_M4_M2 }, // 361 |
30763 | | { 0x3, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG3EI32_V_M8_M2 }, // 362 |
30764 | | { 0x3, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF8 }, // 363 |
30765 | | { 0x3, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG3EI32_V_M1_MF4 }, // 364 |
30766 | | { 0x3, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF4 }, // 365 |
30767 | | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG3EI32_V_M1_MF2 }, // 366 |
30768 | | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG3EI32_V_M2_MF2 }, // 367 |
30769 | | { 0x3, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF2 }, // 368 |
30770 | | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG3EI64_V_M1_M1 }, // 369 |
30771 | | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG3EI64_V_M2_M1 }, // 370 |
30772 | | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG3EI64_V_M4_M1 }, // 371 |
30773 | | { 0x3, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG3EI64_V_M8_M1 }, // 372 |
30774 | | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG3EI64_V_M2_M2 }, // 373 |
30775 | | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG3EI64_V_M4_M2 }, // 374 |
30776 | | { 0x3, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG3EI64_V_M8_M2 }, // 375 |
30777 | | { 0x3, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG3EI64_V_M1_MF8 }, // 376 |
30778 | | { 0x3, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG3EI64_V_M1_MF4 }, // 377 |
30779 | | { 0x3, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG3EI64_V_M2_MF4 }, // 378 |
30780 | | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG3EI64_V_M1_MF2 }, // 379 |
30781 | | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG3EI64_V_M2_MF2 }, // 380 |
30782 | | { 0x3, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG3EI64_V_M4_MF2 }, // 381 |
30783 | | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG3EI8_V_M1_M1_MASK }, // 382 |
30784 | | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG3EI8_V_MF8_M1_MASK }, // 383 |
30785 | | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG3EI8_V_MF4_M1_MASK }, // 384 |
30786 | | { 0x3, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG3EI8_V_MF2_M1_MASK }, // 385 |
30787 | | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG3EI8_V_M1_M2_MASK }, // 386 |
30788 | | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG3EI8_V_M2_M2_MASK }, // 387 |
30789 | | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG3EI8_V_MF4_M2_MASK }, // 388 |
30790 | | { 0x3, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG3EI8_V_MF2_M2_MASK }, // 389 |
30791 | | { 0x3, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF8_MASK }, // 390 |
30792 | | { 0x3, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF4_MASK }, // 391 |
30793 | | { 0x3, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF4_MASK }, // 392 |
30794 | | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG3EI8_V_MF8_MF2_MASK }, // 393 |
30795 | | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG3EI8_V_MF4_MF2_MASK }, // 394 |
30796 | | { 0x3, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG3EI8_V_MF2_MF2_MASK }, // 395 |
30797 | | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG3EI16_V_M1_M1_MASK }, // 396 |
30798 | | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG3EI16_V_M2_M1_MASK }, // 397 |
30799 | | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG3EI16_V_MF4_M1_MASK }, // 398 |
30800 | | { 0x3, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG3EI16_V_MF2_M1_MASK }, // 399 |
30801 | | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG3EI16_V_M1_M2_MASK }, // 400 |
30802 | | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG3EI16_V_M2_M2_MASK }, // 401 |
30803 | | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG3EI16_V_M4_M2_MASK }, // 402 |
30804 | | { 0x3, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG3EI16_V_MF2_M2_MASK }, // 403 |
30805 | | { 0x3, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF8_MASK }, // 404 |
30806 | | { 0x3, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF4_MASK }, // 405 |
30807 | | { 0x3, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF4_MASK }, // 406 |
30808 | | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG3EI16_V_M1_MF2_MASK }, // 407 |
30809 | | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG3EI16_V_MF4_MF2_MASK }, // 408 |
30810 | | { 0x3, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG3EI16_V_MF2_MF2_MASK }, // 409 |
30811 | | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG3EI32_V_M1_M1_MASK }, // 410 |
30812 | | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG3EI32_V_M2_M1_MASK }, // 411 |
30813 | | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG3EI32_V_M4_M1_MASK }, // 412 |
30814 | | { 0x3, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG3EI32_V_MF2_M1_MASK }, // 413 |
30815 | | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG3EI32_V_M1_M2_MASK }, // 414 |
30816 | | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG3EI32_V_M2_M2_MASK }, // 415 |
30817 | | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG3EI32_V_M4_M2_MASK }, // 416 |
30818 | | { 0x3, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG3EI32_V_M8_M2_MASK }, // 417 |
30819 | | { 0x3, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF8_MASK }, // 418 |
30820 | | { 0x3, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG3EI32_V_M1_MF4_MASK }, // 419 |
30821 | | { 0x3, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF4_MASK }, // 420 |
30822 | | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG3EI32_V_M1_MF2_MASK }, // 421 |
30823 | | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG3EI32_V_M2_MF2_MASK }, // 422 |
30824 | | { 0x3, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG3EI32_V_MF2_MF2_MASK }, // 423 |
30825 | | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG3EI64_V_M1_M1_MASK }, // 424 |
30826 | | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG3EI64_V_M2_M1_MASK }, // 425 |
30827 | | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG3EI64_V_M4_M1_MASK }, // 426 |
30828 | | { 0x3, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG3EI64_V_M8_M1_MASK }, // 427 |
30829 | | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG3EI64_V_M2_M2_MASK }, // 428 |
30830 | | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG3EI64_V_M4_M2_MASK }, // 429 |
30831 | | { 0x3, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG3EI64_V_M8_M2_MASK }, // 430 |
30832 | | { 0x3, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG3EI64_V_M1_MF8_MASK }, // 431 |
30833 | | { 0x3, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG3EI64_V_M1_MF4_MASK }, // 432 |
30834 | | { 0x3, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG3EI64_V_M2_MF4_MASK }, // 433 |
30835 | | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG3EI64_V_M1_MF2_MASK }, // 434 |
30836 | | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG3EI64_V_M2_MF2_MASK }, // 435 |
30837 | | { 0x3, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG3EI64_V_M4_MF2_MASK }, // 436 |
30838 | | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG3EI8_V_M1_M1_MASK }, // 437 |
30839 | | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG3EI8_V_MF8_M1_MASK }, // 438 |
30840 | | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG3EI8_V_MF4_M1_MASK }, // 439 |
30841 | | { 0x3, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG3EI8_V_MF2_M1_MASK }, // 440 |
30842 | | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG3EI8_V_M1_M2_MASK }, // 441 |
30843 | | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG3EI8_V_M2_M2_MASK }, // 442 |
30844 | | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG3EI8_V_MF4_M2_MASK }, // 443 |
30845 | | { 0x3, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG3EI8_V_MF2_M2_MASK }, // 444 |
30846 | | { 0x3, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF8_MASK }, // 445 |
30847 | | { 0x3, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF4_MASK }, // 446 |
30848 | | { 0x3, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF4_MASK }, // 447 |
30849 | | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG3EI8_V_MF8_MF2_MASK }, // 448 |
30850 | | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG3EI8_V_MF4_MF2_MASK }, // 449 |
30851 | | { 0x3, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG3EI8_V_MF2_MF2_MASK }, // 450 |
30852 | | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG3EI16_V_M1_M1_MASK }, // 451 |
30853 | | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG3EI16_V_M2_M1_MASK }, // 452 |
30854 | | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG3EI16_V_MF4_M1_MASK }, // 453 |
30855 | | { 0x3, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG3EI16_V_MF2_M1_MASK }, // 454 |
30856 | | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG3EI16_V_M1_M2_MASK }, // 455 |
30857 | | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG3EI16_V_M2_M2_MASK }, // 456 |
30858 | | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG3EI16_V_M4_M2_MASK }, // 457 |
30859 | | { 0x3, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG3EI16_V_MF2_M2_MASK }, // 458 |
30860 | | { 0x3, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF8_MASK }, // 459 |
30861 | | { 0x3, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF4_MASK }, // 460 |
30862 | | { 0x3, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF4_MASK }, // 461 |
30863 | | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG3EI16_V_M1_MF2_MASK }, // 462 |
30864 | | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG3EI16_V_MF4_MF2_MASK }, // 463 |
30865 | | { 0x3, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG3EI16_V_MF2_MF2_MASK }, // 464 |
30866 | | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG3EI32_V_M1_M1_MASK }, // 465 |
30867 | | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG3EI32_V_M2_M1_MASK }, // 466 |
30868 | | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG3EI32_V_M4_M1_MASK }, // 467 |
30869 | | { 0x3, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG3EI32_V_MF2_M1_MASK }, // 468 |
30870 | | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG3EI32_V_M1_M2_MASK }, // 469 |
30871 | | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG3EI32_V_M2_M2_MASK }, // 470 |
30872 | | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG3EI32_V_M4_M2_MASK }, // 471 |
30873 | | { 0x3, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG3EI32_V_M8_M2_MASK }, // 472 |
30874 | | { 0x3, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF8_MASK }, // 473 |
30875 | | { 0x3, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG3EI32_V_M1_MF4_MASK }, // 474 |
30876 | | { 0x3, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF4_MASK }, // 475 |
30877 | | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG3EI32_V_M1_MF2_MASK }, // 476 |
30878 | | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG3EI32_V_M2_MF2_MASK }, // 477 |
30879 | | { 0x3, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG3EI32_V_MF2_MF2_MASK }, // 478 |
30880 | | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG3EI64_V_M1_M1_MASK }, // 479 |
30881 | | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG3EI64_V_M2_M1_MASK }, // 480 |
30882 | | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG3EI64_V_M4_M1_MASK }, // 481 |
30883 | | { 0x3, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG3EI64_V_M8_M1_MASK }, // 482 |
30884 | | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG3EI64_V_M2_M2_MASK }, // 483 |
30885 | | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG3EI64_V_M4_M2_MASK }, // 484 |
30886 | | { 0x3, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG3EI64_V_M8_M2_MASK }, // 485 |
30887 | | { 0x3, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG3EI64_V_M1_MF8_MASK }, // 486 |
30888 | | { 0x3, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG3EI64_V_M1_MF4_MASK }, // 487 |
30889 | | { 0x3, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG3EI64_V_M2_MF4_MASK }, // 488 |
30890 | | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG3EI64_V_M1_MF2_MASK }, // 489 |
30891 | | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG3EI64_V_M2_MF2_MASK }, // 490 |
30892 | | { 0x3, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG3EI64_V_M4_MF2_MASK }, // 491 |
30893 | | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG4EI8_V_M1_M1 }, // 492 |
30894 | | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG4EI8_V_MF8_M1 }, // 493 |
30895 | | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG4EI8_V_MF4_M1 }, // 494 |
30896 | | { 0x4, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG4EI8_V_MF2_M1 }, // 495 |
30897 | | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG4EI8_V_M1_M2 }, // 496 |
30898 | | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG4EI8_V_M2_M2 }, // 497 |
30899 | | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG4EI8_V_MF4_M2 }, // 498 |
30900 | | { 0x4, 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG4EI8_V_MF2_M2 }, // 499 |
30901 | | { 0x4, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF8 }, // 500 |
30902 | | { 0x4, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF4 }, // 501 |
30903 | | { 0x4, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF4 }, // 502 |
30904 | | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF2 }, // 503 |
30905 | | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF2 }, // 504 |
30906 | | { 0x4, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG4EI8_V_MF2_MF2 }, // 505 |
30907 | | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG4EI16_V_M1_M1 }, // 506 |
30908 | | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG4EI16_V_M2_M1 }, // 507 |
30909 | | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG4EI16_V_MF4_M1 }, // 508 |
30910 | | { 0x4, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG4EI16_V_MF2_M1 }, // 509 |
30911 | | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG4EI16_V_M1_M2 }, // 510 |
30912 | | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG4EI16_V_M2_M2 }, // 511 |
30913 | | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG4EI16_V_M4_M2 }, // 512 |
30914 | | { 0x4, 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG4EI16_V_MF2_M2 }, // 513 |
30915 | | { 0x4, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF8 }, // 514 |
30916 | | { 0x4, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF4 }, // 515 |
30917 | | { 0x4, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF4 }, // 516 |
30918 | | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG4EI16_V_M1_MF2 }, // 517 |
30919 | | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF2 }, // 518 |
30920 | | { 0x4, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF2 }, // 519 |
30921 | | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG4EI32_V_M1_M1 }, // 520 |
30922 | | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG4EI32_V_M2_M1 }, // 521 |
30923 | | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG4EI32_V_M4_M1 }, // 522 |
30924 | | { 0x4, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG4EI32_V_MF2_M1 }, // 523 |
30925 | | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG4EI32_V_M1_M2 }, // 524 |
30926 | | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG4EI32_V_M2_M2 }, // 525 |
30927 | | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG4EI32_V_M4_M2 }, // 526 |
30928 | | { 0x4, 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG4EI32_V_M8_M2 }, // 527 |
30929 | | { 0x4, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF8 }, // 528 |
30930 | | { 0x4, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG4EI32_V_M1_MF4 }, // 529 |
30931 | | { 0x4, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF4 }, // 530 |
30932 | | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG4EI32_V_M1_MF2 }, // 531 |
30933 | | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG4EI32_V_M2_MF2 }, // 532 |
30934 | | { 0x4, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF2 }, // 533 |
30935 | | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG4EI64_V_M1_M1 }, // 534 |
30936 | | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG4EI64_V_M2_M1 }, // 535 |
30937 | | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG4EI64_V_M4_M1 }, // 536 |
30938 | | { 0x4, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG4EI64_V_M8_M1 }, // 537 |
30939 | | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG4EI64_V_M2_M2 }, // 538 |
30940 | | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG4EI64_V_M4_M2 }, // 539 |
30941 | | { 0x4, 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG4EI64_V_M8_M2 }, // 540 |
30942 | | { 0x4, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG4EI64_V_M1_MF8 }, // 541 |
30943 | | { 0x4, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG4EI64_V_M1_MF4 }, // 542 |
30944 | | { 0x4, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG4EI64_V_M2_MF4 }, // 543 |
30945 | | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG4EI64_V_M1_MF2 }, // 544 |
30946 | | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG4EI64_V_M2_MF2 }, // 545 |
30947 | | { 0x4, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG4EI64_V_M4_MF2 }, // 546 |
30948 | | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG4EI8_V_M1_M1 }, // 547 |
30949 | | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG4EI8_V_MF8_M1 }, // 548 |
30950 | | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG4EI8_V_MF4_M1 }, // 549 |
30951 | | { 0x4, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG4EI8_V_MF2_M1 }, // 550 |
30952 | | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG4EI8_V_M1_M2 }, // 551 |
30953 | | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG4EI8_V_M2_M2 }, // 552 |
30954 | | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG4EI8_V_MF4_M2 }, // 553 |
30955 | | { 0x4, 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG4EI8_V_MF2_M2 }, // 554 |
30956 | | { 0x4, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF8 }, // 555 |
30957 | | { 0x4, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF4 }, // 556 |
30958 | | { 0x4, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF4 }, // 557 |
30959 | | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF2 }, // 558 |
30960 | | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF2 }, // 559 |
30961 | | { 0x4, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG4EI8_V_MF2_MF2 }, // 560 |
30962 | | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG4EI16_V_M1_M1 }, // 561 |
30963 | | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG4EI16_V_M2_M1 }, // 562 |
30964 | | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG4EI16_V_MF4_M1 }, // 563 |
30965 | | { 0x4, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG4EI16_V_MF2_M1 }, // 564 |
30966 | | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG4EI16_V_M1_M2 }, // 565 |
30967 | | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG4EI16_V_M2_M2 }, // 566 |
30968 | | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG4EI16_V_M4_M2 }, // 567 |
30969 | | { 0x4, 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG4EI16_V_MF2_M2 }, // 568 |
30970 | | { 0x4, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF8 }, // 569 |
30971 | | { 0x4, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF4 }, // 570 |
30972 | | { 0x4, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF4 }, // 571 |
30973 | | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG4EI16_V_M1_MF2 }, // 572 |
30974 | | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF2 }, // 573 |
30975 | | { 0x4, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF2 }, // 574 |
30976 | | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG4EI32_V_M1_M1 }, // 575 |
30977 | | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG4EI32_V_M2_M1 }, // 576 |
30978 | | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG4EI32_V_M4_M1 }, // 577 |
30979 | | { 0x4, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG4EI32_V_MF2_M1 }, // 578 |
30980 | | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG4EI32_V_M1_M2 }, // 579 |
30981 | | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG4EI32_V_M2_M2 }, // 580 |
30982 | | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG4EI32_V_M4_M2 }, // 581 |
30983 | | { 0x4, 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG4EI32_V_M8_M2 }, // 582 |
30984 | | { 0x4, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF8 }, // 583 |
30985 | | { 0x4, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG4EI32_V_M1_MF4 }, // 584 |
30986 | | { 0x4, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF4 }, // 585 |
30987 | | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG4EI32_V_M1_MF2 }, // 586 |
30988 | | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG4EI32_V_M2_MF2 }, // 587 |
30989 | | { 0x4, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF2 }, // 588 |
30990 | | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG4EI64_V_M1_M1 }, // 589 |
30991 | | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG4EI64_V_M2_M1 }, // 590 |
30992 | | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG4EI64_V_M4_M1 }, // 591 |
30993 | | { 0x4, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG4EI64_V_M8_M1 }, // 592 |
30994 | | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG4EI64_V_M2_M2 }, // 593 |
30995 | | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG4EI64_V_M4_M2 }, // 594 |
30996 | | { 0x4, 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG4EI64_V_M8_M2 }, // 595 |
30997 | | { 0x4, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG4EI64_V_M1_MF8 }, // 596 |
30998 | | { 0x4, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG4EI64_V_M1_MF4 }, // 597 |
30999 | | { 0x4, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG4EI64_V_M2_MF4 }, // 598 |
31000 | | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG4EI64_V_M1_MF2 }, // 599 |
31001 | | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG4EI64_V_M2_MF2 }, // 600 |
31002 | | { 0x4, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG4EI64_V_M4_MF2 }, // 601 |
31003 | | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG4EI8_V_M1_M1_MASK }, // 602 |
31004 | | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG4EI8_V_MF8_M1_MASK }, // 603 |
31005 | | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG4EI8_V_MF4_M1_MASK }, // 604 |
31006 | | { 0x4, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG4EI8_V_MF2_M1_MASK }, // 605 |
31007 | | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXSEG4EI8_V_M1_M2_MASK }, // 606 |
31008 | | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXSEG4EI8_V_M2_M2_MASK }, // 607 |
31009 | | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXSEG4EI8_V_MF4_M2_MASK }, // 608 |
31010 | | { 0x4, 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXSEG4EI8_V_MF2_M2_MASK }, // 609 |
31011 | | { 0x4, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF8_MASK }, // 610 |
31012 | | { 0x4, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF4_MASK }, // 611 |
31013 | | { 0x4, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF4_MASK }, // 612 |
31014 | | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG4EI8_V_MF8_MF2_MASK }, // 613 |
31015 | | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG4EI8_V_MF4_MF2_MASK }, // 614 |
31016 | | { 0x4, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG4EI8_V_MF2_MF2_MASK }, // 615 |
31017 | | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG4EI16_V_M1_M1_MASK }, // 616 |
31018 | | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG4EI16_V_M2_M1_MASK }, // 617 |
31019 | | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG4EI16_V_MF4_M1_MASK }, // 618 |
31020 | | { 0x4, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG4EI16_V_MF2_M1_MASK }, // 619 |
31021 | | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXSEG4EI16_V_M1_M2_MASK }, // 620 |
31022 | | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXSEG4EI16_V_M2_M2_MASK }, // 621 |
31023 | | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXSEG4EI16_V_M4_M2_MASK }, // 622 |
31024 | | { 0x4, 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXSEG4EI16_V_MF2_M2_MASK }, // 623 |
31025 | | { 0x4, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF8_MASK }, // 624 |
31026 | | { 0x4, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF4_MASK }, // 625 |
31027 | | { 0x4, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF4_MASK }, // 626 |
31028 | | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG4EI16_V_M1_MF2_MASK }, // 627 |
31029 | | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG4EI16_V_MF4_MF2_MASK }, // 628 |
31030 | | { 0x4, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG4EI16_V_MF2_MF2_MASK }, // 629 |
31031 | | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG4EI32_V_M1_M1_MASK }, // 630 |
31032 | | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG4EI32_V_M2_M1_MASK }, // 631 |
31033 | | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG4EI32_V_M4_M1_MASK }, // 632 |
31034 | | { 0x4, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG4EI32_V_MF2_M1_MASK }, // 633 |
31035 | | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXSEG4EI32_V_M1_M2_MASK }, // 634 |
31036 | | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXSEG4EI32_V_M2_M2_MASK }, // 635 |
31037 | | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXSEG4EI32_V_M4_M2_MASK }, // 636 |
31038 | | { 0x4, 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXSEG4EI32_V_M8_M2_MASK }, // 637 |
31039 | | { 0x4, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF8_MASK }, // 638 |
31040 | | { 0x4, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG4EI32_V_M1_MF4_MASK }, // 639 |
31041 | | { 0x4, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF4_MASK }, // 640 |
31042 | | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG4EI32_V_M1_MF2_MASK }, // 641 |
31043 | | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG4EI32_V_M2_MF2_MASK }, // 642 |
31044 | | { 0x4, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG4EI32_V_MF2_MF2_MASK }, // 643 |
31045 | | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG4EI64_V_M1_M1_MASK }, // 644 |
31046 | | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG4EI64_V_M2_M1_MASK }, // 645 |
31047 | | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG4EI64_V_M4_M1_MASK }, // 646 |
31048 | | { 0x4, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG4EI64_V_M8_M1_MASK }, // 647 |
31049 | | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXSEG4EI64_V_M2_M2_MASK }, // 648 |
31050 | | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXSEG4EI64_V_M4_M2_MASK }, // 649 |
31051 | | { 0x4, 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXSEG4EI64_V_M8_M2_MASK }, // 650 |
31052 | | { 0x4, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG4EI64_V_M1_MF8_MASK }, // 651 |
31053 | | { 0x4, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG4EI64_V_M1_MF4_MASK }, // 652 |
31054 | | { 0x4, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG4EI64_V_M2_MF4_MASK }, // 653 |
31055 | | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG4EI64_V_M1_MF2_MASK }, // 654 |
31056 | | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG4EI64_V_M2_MF2_MASK }, // 655 |
31057 | | { 0x4, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG4EI64_V_M4_MF2_MASK }, // 656 |
31058 | | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG4EI8_V_M1_M1_MASK }, // 657 |
31059 | | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG4EI8_V_MF8_M1_MASK }, // 658 |
31060 | | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG4EI8_V_MF4_M1_MASK }, // 659 |
31061 | | { 0x4, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG4EI8_V_MF2_M1_MASK }, // 660 |
31062 | | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXSEG4EI8_V_M1_M2_MASK }, // 661 |
31063 | | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXSEG4EI8_V_M2_M2_MASK }, // 662 |
31064 | | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXSEG4EI8_V_MF4_M2_MASK }, // 663 |
31065 | | { 0x4, 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXSEG4EI8_V_MF2_M2_MASK }, // 664 |
31066 | | { 0x4, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF8_MASK }, // 665 |
31067 | | { 0x4, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF4_MASK }, // 666 |
31068 | | { 0x4, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF4_MASK }, // 667 |
31069 | | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG4EI8_V_MF8_MF2_MASK }, // 668 |
31070 | | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG4EI8_V_MF4_MF2_MASK }, // 669 |
31071 | | { 0x4, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG4EI8_V_MF2_MF2_MASK }, // 670 |
31072 | | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG4EI16_V_M1_M1_MASK }, // 671 |
31073 | | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG4EI16_V_M2_M1_MASK }, // 672 |
31074 | | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG4EI16_V_MF4_M1_MASK }, // 673 |
31075 | | { 0x4, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG4EI16_V_MF2_M1_MASK }, // 674 |
31076 | | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXSEG4EI16_V_M1_M2_MASK }, // 675 |
31077 | | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXSEG4EI16_V_M2_M2_MASK }, // 676 |
31078 | | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXSEG4EI16_V_M4_M2_MASK }, // 677 |
31079 | | { 0x4, 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXSEG4EI16_V_MF2_M2_MASK }, // 678 |
31080 | | { 0x4, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF8_MASK }, // 679 |
31081 | | { 0x4, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF4_MASK }, // 680 |
31082 | | { 0x4, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF4_MASK }, // 681 |
31083 | | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG4EI16_V_M1_MF2_MASK }, // 682 |
31084 | | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG4EI16_V_MF4_MF2_MASK }, // 683 |
31085 | | { 0x4, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG4EI16_V_MF2_MF2_MASK }, // 684 |
31086 | | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG4EI32_V_M1_M1_MASK }, // 685 |
31087 | | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG4EI32_V_M2_M1_MASK }, // 686 |
31088 | | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG4EI32_V_M4_M1_MASK }, // 687 |
31089 | | { 0x4, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG4EI32_V_MF2_M1_MASK }, // 688 |
31090 | | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXSEG4EI32_V_M1_M2_MASK }, // 689 |
31091 | | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXSEG4EI32_V_M2_M2_MASK }, // 690 |
31092 | | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXSEG4EI32_V_M4_M2_MASK }, // 691 |
31093 | | { 0x4, 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXSEG4EI32_V_M8_M2_MASK }, // 692 |
31094 | | { 0x4, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF8_MASK }, // 693 |
31095 | | { 0x4, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG4EI32_V_M1_MF4_MASK }, // 694 |
31096 | | { 0x4, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF4_MASK }, // 695 |
31097 | | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG4EI32_V_M1_MF2_MASK }, // 696 |
31098 | | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG4EI32_V_M2_MF2_MASK }, // 697 |
31099 | | { 0x4, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG4EI32_V_MF2_MF2_MASK }, // 698 |
31100 | | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG4EI64_V_M1_M1_MASK }, // 699 |
31101 | | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG4EI64_V_M2_M1_MASK }, // 700 |
31102 | | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG4EI64_V_M4_M1_MASK }, // 701 |
31103 | | { 0x4, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG4EI64_V_M8_M1_MASK }, // 702 |
31104 | | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXSEG4EI64_V_M2_M2_MASK }, // 703 |
31105 | | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXSEG4EI64_V_M4_M2_MASK }, // 704 |
31106 | | { 0x4, 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXSEG4EI64_V_M8_M2_MASK }, // 705 |
31107 | | { 0x4, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG4EI64_V_M1_MF8_MASK }, // 706 |
31108 | | { 0x4, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG4EI64_V_M1_MF4_MASK }, // 707 |
31109 | | { 0x4, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG4EI64_V_M2_MF4_MASK }, // 708 |
31110 | | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG4EI64_V_M1_MF2_MASK }, // 709 |
31111 | | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG4EI64_V_M2_MF2_MASK }, // 710 |
31112 | | { 0x4, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG4EI64_V_M4_MF2_MASK }, // 711 |
31113 | | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG5EI8_V_M1_M1 }, // 712 |
31114 | | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG5EI8_V_MF8_M1 }, // 713 |
31115 | | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG5EI8_V_MF4_M1 }, // 714 |
31116 | | { 0x5, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG5EI8_V_MF2_M1 }, // 715 |
31117 | | { 0x5, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF8 }, // 716 |
31118 | | { 0x5, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF4 }, // 717 |
31119 | | { 0x5, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF4 }, // 718 |
31120 | | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF2 }, // 719 |
31121 | | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF2 }, // 720 |
31122 | | { 0x5, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG5EI8_V_MF2_MF2 }, // 721 |
31123 | | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG5EI16_V_M1_M1 }, // 722 |
31124 | | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG5EI16_V_M2_M1 }, // 723 |
31125 | | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG5EI16_V_MF4_M1 }, // 724 |
31126 | | { 0x5, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG5EI16_V_MF2_M1 }, // 725 |
31127 | | { 0x5, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF8 }, // 726 |
31128 | | { 0x5, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF4 }, // 727 |
31129 | | { 0x5, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF4 }, // 728 |
31130 | | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG5EI16_V_M1_MF2 }, // 729 |
31131 | | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF2 }, // 730 |
31132 | | { 0x5, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF2 }, // 731 |
31133 | | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG5EI32_V_M1_M1 }, // 732 |
31134 | | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG5EI32_V_M2_M1 }, // 733 |
31135 | | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG5EI32_V_M4_M1 }, // 734 |
31136 | | { 0x5, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG5EI32_V_MF2_M1 }, // 735 |
31137 | | { 0x5, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF8 }, // 736 |
31138 | | { 0x5, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG5EI32_V_M1_MF4 }, // 737 |
31139 | | { 0x5, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF4 }, // 738 |
31140 | | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG5EI32_V_M1_MF2 }, // 739 |
31141 | | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG5EI32_V_M2_MF2 }, // 740 |
31142 | | { 0x5, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF2 }, // 741 |
31143 | | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG5EI64_V_M1_M1 }, // 742 |
31144 | | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG5EI64_V_M2_M1 }, // 743 |
31145 | | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG5EI64_V_M4_M1 }, // 744 |
31146 | | { 0x5, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG5EI64_V_M8_M1 }, // 745 |
31147 | | { 0x5, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG5EI64_V_M1_MF8 }, // 746 |
31148 | | { 0x5, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG5EI64_V_M1_MF4 }, // 747 |
31149 | | { 0x5, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG5EI64_V_M2_MF4 }, // 748 |
31150 | | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG5EI64_V_M1_MF2 }, // 749 |
31151 | | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG5EI64_V_M2_MF2 }, // 750 |
31152 | | { 0x5, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG5EI64_V_M4_MF2 }, // 751 |
31153 | | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG5EI8_V_M1_M1 }, // 752 |
31154 | | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG5EI8_V_MF8_M1 }, // 753 |
31155 | | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG5EI8_V_MF4_M1 }, // 754 |
31156 | | { 0x5, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG5EI8_V_MF2_M1 }, // 755 |
31157 | | { 0x5, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF8 }, // 756 |
31158 | | { 0x5, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF4 }, // 757 |
31159 | | { 0x5, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF4 }, // 758 |
31160 | | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF2 }, // 759 |
31161 | | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF2 }, // 760 |
31162 | | { 0x5, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG5EI8_V_MF2_MF2 }, // 761 |
31163 | | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG5EI16_V_M1_M1 }, // 762 |
31164 | | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG5EI16_V_M2_M1 }, // 763 |
31165 | | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG5EI16_V_MF4_M1 }, // 764 |
31166 | | { 0x5, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG5EI16_V_MF2_M1 }, // 765 |
31167 | | { 0x5, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF8 }, // 766 |
31168 | | { 0x5, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF4 }, // 767 |
31169 | | { 0x5, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF4 }, // 768 |
31170 | | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG5EI16_V_M1_MF2 }, // 769 |
31171 | | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF2 }, // 770 |
31172 | | { 0x5, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF2 }, // 771 |
31173 | | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG5EI32_V_M1_M1 }, // 772 |
31174 | | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG5EI32_V_M2_M1 }, // 773 |
31175 | | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG5EI32_V_M4_M1 }, // 774 |
31176 | | { 0x5, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG5EI32_V_MF2_M1 }, // 775 |
31177 | | { 0x5, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF8 }, // 776 |
31178 | | { 0x5, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG5EI32_V_M1_MF4 }, // 777 |
31179 | | { 0x5, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF4 }, // 778 |
31180 | | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG5EI32_V_M1_MF2 }, // 779 |
31181 | | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG5EI32_V_M2_MF2 }, // 780 |
31182 | | { 0x5, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF2 }, // 781 |
31183 | | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG5EI64_V_M1_M1 }, // 782 |
31184 | | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG5EI64_V_M2_M1 }, // 783 |
31185 | | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG5EI64_V_M4_M1 }, // 784 |
31186 | | { 0x5, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG5EI64_V_M8_M1 }, // 785 |
31187 | | { 0x5, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG5EI64_V_M1_MF8 }, // 786 |
31188 | | { 0x5, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG5EI64_V_M1_MF4 }, // 787 |
31189 | | { 0x5, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG5EI64_V_M2_MF4 }, // 788 |
31190 | | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG5EI64_V_M1_MF2 }, // 789 |
31191 | | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG5EI64_V_M2_MF2 }, // 790 |
31192 | | { 0x5, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG5EI64_V_M4_MF2 }, // 791 |
31193 | | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG5EI8_V_M1_M1_MASK }, // 792 |
31194 | | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG5EI8_V_MF8_M1_MASK }, // 793 |
31195 | | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG5EI8_V_MF4_M1_MASK }, // 794 |
31196 | | { 0x5, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG5EI8_V_MF2_M1_MASK }, // 795 |
31197 | | { 0x5, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF8_MASK }, // 796 |
31198 | | { 0x5, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF4_MASK }, // 797 |
31199 | | { 0x5, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF4_MASK }, // 798 |
31200 | | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG5EI8_V_MF8_MF2_MASK }, // 799 |
31201 | | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG5EI8_V_MF4_MF2_MASK }, // 800 |
31202 | | { 0x5, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG5EI8_V_MF2_MF2_MASK }, // 801 |
31203 | | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG5EI16_V_M1_M1_MASK }, // 802 |
31204 | | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG5EI16_V_M2_M1_MASK }, // 803 |
31205 | | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG5EI16_V_MF4_M1_MASK }, // 804 |
31206 | | { 0x5, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG5EI16_V_MF2_M1_MASK }, // 805 |
31207 | | { 0x5, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF8_MASK }, // 806 |
31208 | | { 0x5, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF4_MASK }, // 807 |
31209 | | { 0x5, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF4_MASK }, // 808 |
31210 | | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG5EI16_V_M1_MF2_MASK }, // 809 |
31211 | | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG5EI16_V_MF4_MF2_MASK }, // 810 |
31212 | | { 0x5, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG5EI16_V_MF2_MF2_MASK }, // 811 |
31213 | | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG5EI32_V_M1_M1_MASK }, // 812 |
31214 | | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG5EI32_V_M2_M1_MASK }, // 813 |
31215 | | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG5EI32_V_M4_M1_MASK }, // 814 |
31216 | | { 0x5, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG5EI32_V_MF2_M1_MASK }, // 815 |
31217 | | { 0x5, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF8_MASK }, // 816 |
31218 | | { 0x5, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG5EI32_V_M1_MF4_MASK }, // 817 |
31219 | | { 0x5, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF4_MASK }, // 818 |
31220 | | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG5EI32_V_M1_MF2_MASK }, // 819 |
31221 | | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG5EI32_V_M2_MF2_MASK }, // 820 |
31222 | | { 0x5, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG5EI32_V_MF2_MF2_MASK }, // 821 |
31223 | | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG5EI64_V_M1_M1_MASK }, // 822 |
31224 | | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG5EI64_V_M2_M1_MASK }, // 823 |
31225 | | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG5EI64_V_M4_M1_MASK }, // 824 |
31226 | | { 0x5, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG5EI64_V_M8_M1_MASK }, // 825 |
31227 | | { 0x5, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG5EI64_V_M1_MF8_MASK }, // 826 |
31228 | | { 0x5, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG5EI64_V_M1_MF4_MASK }, // 827 |
31229 | | { 0x5, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG5EI64_V_M2_MF4_MASK }, // 828 |
31230 | | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG5EI64_V_M1_MF2_MASK }, // 829 |
31231 | | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG5EI64_V_M2_MF2_MASK }, // 830 |
31232 | | { 0x5, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG5EI64_V_M4_MF2_MASK }, // 831 |
31233 | | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG5EI8_V_M1_M1_MASK }, // 832 |
31234 | | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG5EI8_V_MF8_M1_MASK }, // 833 |
31235 | | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG5EI8_V_MF4_M1_MASK }, // 834 |
31236 | | { 0x5, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG5EI8_V_MF2_M1_MASK }, // 835 |
31237 | | { 0x5, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF8_MASK }, // 836 |
31238 | | { 0x5, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF4_MASK }, // 837 |
31239 | | { 0x5, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF4_MASK }, // 838 |
31240 | | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG5EI8_V_MF8_MF2_MASK }, // 839 |
31241 | | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG5EI8_V_MF4_MF2_MASK }, // 840 |
31242 | | { 0x5, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG5EI8_V_MF2_MF2_MASK }, // 841 |
31243 | | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG5EI16_V_M1_M1_MASK }, // 842 |
31244 | | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG5EI16_V_M2_M1_MASK }, // 843 |
31245 | | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG5EI16_V_MF4_M1_MASK }, // 844 |
31246 | | { 0x5, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG5EI16_V_MF2_M1_MASK }, // 845 |
31247 | | { 0x5, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF8_MASK }, // 846 |
31248 | | { 0x5, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF4_MASK }, // 847 |
31249 | | { 0x5, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF4_MASK }, // 848 |
31250 | | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG5EI16_V_M1_MF2_MASK }, // 849 |
31251 | | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG5EI16_V_MF4_MF2_MASK }, // 850 |
31252 | | { 0x5, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG5EI16_V_MF2_MF2_MASK }, // 851 |
31253 | | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG5EI32_V_M1_M1_MASK }, // 852 |
31254 | | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG5EI32_V_M2_M1_MASK }, // 853 |
31255 | | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG5EI32_V_M4_M1_MASK }, // 854 |
31256 | | { 0x5, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG5EI32_V_MF2_M1_MASK }, // 855 |
31257 | | { 0x5, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF8_MASK }, // 856 |
31258 | | { 0x5, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG5EI32_V_M1_MF4_MASK }, // 857 |
31259 | | { 0x5, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF4_MASK }, // 858 |
31260 | | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG5EI32_V_M1_MF2_MASK }, // 859 |
31261 | | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG5EI32_V_M2_MF2_MASK }, // 860 |
31262 | | { 0x5, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG5EI32_V_MF2_MF2_MASK }, // 861 |
31263 | | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG5EI64_V_M1_M1_MASK }, // 862 |
31264 | | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG5EI64_V_M2_M1_MASK }, // 863 |
31265 | | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG5EI64_V_M4_M1_MASK }, // 864 |
31266 | | { 0x5, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG5EI64_V_M8_M1_MASK }, // 865 |
31267 | | { 0x5, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG5EI64_V_M1_MF8_MASK }, // 866 |
31268 | | { 0x5, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG5EI64_V_M1_MF4_MASK }, // 867 |
31269 | | { 0x5, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG5EI64_V_M2_MF4_MASK }, // 868 |
31270 | | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG5EI64_V_M1_MF2_MASK }, // 869 |
31271 | | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG5EI64_V_M2_MF2_MASK }, // 870 |
31272 | | { 0x5, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG5EI64_V_M4_MF2_MASK }, // 871 |
31273 | | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG6EI8_V_M1_M1 }, // 872 |
31274 | | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG6EI8_V_MF8_M1 }, // 873 |
31275 | | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG6EI8_V_MF4_M1 }, // 874 |
31276 | | { 0x6, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG6EI8_V_MF2_M1 }, // 875 |
31277 | | { 0x6, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF8 }, // 876 |
31278 | | { 0x6, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF4 }, // 877 |
31279 | | { 0x6, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF4 }, // 878 |
31280 | | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF2 }, // 879 |
31281 | | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF2 }, // 880 |
31282 | | { 0x6, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG6EI8_V_MF2_MF2 }, // 881 |
31283 | | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG6EI16_V_M1_M1 }, // 882 |
31284 | | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG6EI16_V_M2_M1 }, // 883 |
31285 | | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG6EI16_V_MF4_M1 }, // 884 |
31286 | | { 0x6, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG6EI16_V_MF2_M1 }, // 885 |
31287 | | { 0x6, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF8 }, // 886 |
31288 | | { 0x6, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF4 }, // 887 |
31289 | | { 0x6, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF4 }, // 888 |
31290 | | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG6EI16_V_M1_MF2 }, // 889 |
31291 | | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF2 }, // 890 |
31292 | | { 0x6, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF2 }, // 891 |
31293 | | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG6EI32_V_M1_M1 }, // 892 |
31294 | | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG6EI32_V_M2_M1 }, // 893 |
31295 | | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG6EI32_V_M4_M1 }, // 894 |
31296 | | { 0x6, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG6EI32_V_MF2_M1 }, // 895 |
31297 | | { 0x6, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF8 }, // 896 |
31298 | | { 0x6, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG6EI32_V_M1_MF4 }, // 897 |
31299 | | { 0x6, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF4 }, // 898 |
31300 | | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG6EI32_V_M1_MF2 }, // 899 |
31301 | | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG6EI32_V_M2_MF2 }, // 900 |
31302 | | { 0x6, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF2 }, // 901 |
31303 | | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG6EI64_V_M1_M1 }, // 902 |
31304 | | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG6EI64_V_M2_M1 }, // 903 |
31305 | | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG6EI64_V_M4_M1 }, // 904 |
31306 | | { 0x6, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG6EI64_V_M8_M1 }, // 905 |
31307 | | { 0x6, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG6EI64_V_M1_MF8 }, // 906 |
31308 | | { 0x6, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG6EI64_V_M1_MF4 }, // 907 |
31309 | | { 0x6, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG6EI64_V_M2_MF4 }, // 908 |
31310 | | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG6EI64_V_M1_MF2 }, // 909 |
31311 | | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG6EI64_V_M2_MF2 }, // 910 |
31312 | | { 0x6, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG6EI64_V_M4_MF2 }, // 911 |
31313 | | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG6EI8_V_M1_M1 }, // 912 |
31314 | | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG6EI8_V_MF8_M1 }, // 913 |
31315 | | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG6EI8_V_MF4_M1 }, // 914 |
31316 | | { 0x6, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG6EI8_V_MF2_M1 }, // 915 |
31317 | | { 0x6, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF8 }, // 916 |
31318 | | { 0x6, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF4 }, // 917 |
31319 | | { 0x6, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF4 }, // 918 |
31320 | | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF2 }, // 919 |
31321 | | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF2 }, // 920 |
31322 | | { 0x6, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG6EI8_V_MF2_MF2 }, // 921 |
31323 | | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG6EI16_V_M1_M1 }, // 922 |
31324 | | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG6EI16_V_M2_M1 }, // 923 |
31325 | | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG6EI16_V_MF4_M1 }, // 924 |
31326 | | { 0x6, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG6EI16_V_MF2_M1 }, // 925 |
31327 | | { 0x6, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF8 }, // 926 |
31328 | | { 0x6, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF4 }, // 927 |
31329 | | { 0x6, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF4 }, // 928 |
31330 | | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG6EI16_V_M1_MF2 }, // 929 |
31331 | | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF2 }, // 930 |
31332 | | { 0x6, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF2 }, // 931 |
31333 | | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG6EI32_V_M1_M1 }, // 932 |
31334 | | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG6EI32_V_M2_M1 }, // 933 |
31335 | | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG6EI32_V_M4_M1 }, // 934 |
31336 | | { 0x6, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG6EI32_V_MF2_M1 }, // 935 |
31337 | | { 0x6, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF8 }, // 936 |
31338 | | { 0x6, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG6EI32_V_M1_MF4 }, // 937 |
31339 | | { 0x6, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF4 }, // 938 |
31340 | | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG6EI32_V_M1_MF2 }, // 939 |
31341 | | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG6EI32_V_M2_MF2 }, // 940 |
31342 | | { 0x6, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF2 }, // 941 |
31343 | | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG6EI64_V_M1_M1 }, // 942 |
31344 | | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG6EI64_V_M2_M1 }, // 943 |
31345 | | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG6EI64_V_M4_M1 }, // 944 |
31346 | | { 0x6, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG6EI64_V_M8_M1 }, // 945 |
31347 | | { 0x6, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG6EI64_V_M1_MF8 }, // 946 |
31348 | | { 0x6, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG6EI64_V_M1_MF4 }, // 947 |
31349 | | { 0x6, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG6EI64_V_M2_MF4 }, // 948 |
31350 | | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG6EI64_V_M1_MF2 }, // 949 |
31351 | | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG6EI64_V_M2_MF2 }, // 950 |
31352 | | { 0x6, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG6EI64_V_M4_MF2 }, // 951 |
31353 | | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG6EI8_V_M1_M1_MASK }, // 952 |
31354 | | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG6EI8_V_MF8_M1_MASK }, // 953 |
31355 | | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG6EI8_V_MF4_M1_MASK }, // 954 |
31356 | | { 0x6, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG6EI8_V_MF2_M1_MASK }, // 955 |
31357 | | { 0x6, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF8_MASK }, // 956 |
31358 | | { 0x6, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF4_MASK }, // 957 |
31359 | | { 0x6, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF4_MASK }, // 958 |
31360 | | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG6EI8_V_MF8_MF2_MASK }, // 959 |
31361 | | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG6EI8_V_MF4_MF2_MASK }, // 960 |
31362 | | { 0x6, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG6EI8_V_MF2_MF2_MASK }, // 961 |
31363 | | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG6EI16_V_M1_M1_MASK }, // 962 |
31364 | | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG6EI16_V_M2_M1_MASK }, // 963 |
31365 | | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG6EI16_V_MF4_M1_MASK }, // 964 |
31366 | | { 0x6, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG6EI16_V_MF2_M1_MASK }, // 965 |
31367 | | { 0x6, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF8_MASK }, // 966 |
31368 | | { 0x6, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF4_MASK }, // 967 |
31369 | | { 0x6, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF4_MASK }, // 968 |
31370 | | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG6EI16_V_M1_MF2_MASK }, // 969 |
31371 | | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG6EI16_V_MF4_MF2_MASK }, // 970 |
31372 | | { 0x6, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG6EI16_V_MF2_MF2_MASK }, // 971 |
31373 | | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG6EI32_V_M1_M1_MASK }, // 972 |
31374 | | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG6EI32_V_M2_M1_MASK }, // 973 |
31375 | | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG6EI32_V_M4_M1_MASK }, // 974 |
31376 | | { 0x6, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG6EI32_V_MF2_M1_MASK }, // 975 |
31377 | | { 0x6, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF8_MASK }, // 976 |
31378 | | { 0x6, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG6EI32_V_M1_MF4_MASK }, // 977 |
31379 | | { 0x6, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF4_MASK }, // 978 |
31380 | | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG6EI32_V_M1_MF2_MASK }, // 979 |
31381 | | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG6EI32_V_M2_MF2_MASK }, // 980 |
31382 | | { 0x6, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG6EI32_V_MF2_MF2_MASK }, // 981 |
31383 | | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG6EI64_V_M1_M1_MASK }, // 982 |
31384 | | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG6EI64_V_M2_M1_MASK }, // 983 |
31385 | | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG6EI64_V_M4_M1_MASK }, // 984 |
31386 | | { 0x6, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG6EI64_V_M8_M1_MASK }, // 985 |
31387 | | { 0x6, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG6EI64_V_M1_MF8_MASK }, // 986 |
31388 | | { 0x6, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG6EI64_V_M1_MF4_MASK }, // 987 |
31389 | | { 0x6, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG6EI64_V_M2_MF4_MASK }, // 988 |
31390 | | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG6EI64_V_M1_MF2_MASK }, // 989 |
31391 | | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG6EI64_V_M2_MF2_MASK }, // 990 |
31392 | | { 0x6, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG6EI64_V_M4_MF2_MASK }, // 991 |
31393 | | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG6EI8_V_M1_M1_MASK }, // 992 |
31394 | | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG6EI8_V_MF8_M1_MASK }, // 993 |
31395 | | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG6EI8_V_MF4_M1_MASK }, // 994 |
31396 | | { 0x6, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG6EI8_V_MF2_M1_MASK }, // 995 |
31397 | | { 0x6, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF8_MASK }, // 996 |
31398 | | { 0x6, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF4_MASK }, // 997 |
31399 | | { 0x6, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF4_MASK }, // 998 |
31400 | | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG6EI8_V_MF8_MF2_MASK }, // 999 |
31401 | | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG6EI8_V_MF4_MF2_MASK }, // 1000 |
31402 | | { 0x6, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG6EI8_V_MF2_MF2_MASK }, // 1001 |
31403 | | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG6EI16_V_M1_M1_MASK }, // 1002 |
31404 | | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG6EI16_V_M2_M1_MASK }, // 1003 |
31405 | | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG6EI16_V_MF4_M1_MASK }, // 1004 |
31406 | | { 0x6, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG6EI16_V_MF2_M1_MASK }, // 1005 |
31407 | | { 0x6, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF8_MASK }, // 1006 |
31408 | | { 0x6, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF4_MASK }, // 1007 |
31409 | | { 0x6, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF4_MASK }, // 1008 |
31410 | | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG6EI16_V_M1_MF2_MASK }, // 1009 |
31411 | | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG6EI16_V_MF4_MF2_MASK }, // 1010 |
31412 | | { 0x6, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG6EI16_V_MF2_MF2_MASK }, // 1011 |
31413 | | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG6EI32_V_M1_M1_MASK }, // 1012 |
31414 | | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG6EI32_V_M2_M1_MASK }, // 1013 |
31415 | | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG6EI32_V_M4_M1_MASK }, // 1014 |
31416 | | { 0x6, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG6EI32_V_MF2_M1_MASK }, // 1015 |
31417 | | { 0x6, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF8_MASK }, // 1016 |
31418 | | { 0x6, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG6EI32_V_M1_MF4_MASK }, // 1017 |
31419 | | { 0x6, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF4_MASK }, // 1018 |
31420 | | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG6EI32_V_M1_MF2_MASK }, // 1019 |
31421 | | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG6EI32_V_M2_MF2_MASK }, // 1020 |
31422 | | { 0x6, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG6EI32_V_MF2_MF2_MASK }, // 1021 |
31423 | | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG6EI64_V_M1_M1_MASK }, // 1022 |
31424 | | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG6EI64_V_M2_M1_MASK }, // 1023 |
31425 | | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG6EI64_V_M4_M1_MASK }, // 1024 |
31426 | | { 0x6, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG6EI64_V_M8_M1_MASK }, // 1025 |
31427 | | { 0x6, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG6EI64_V_M1_MF8_MASK }, // 1026 |
31428 | | { 0x6, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG6EI64_V_M1_MF4_MASK }, // 1027 |
31429 | | { 0x6, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG6EI64_V_M2_MF4_MASK }, // 1028 |
31430 | | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG6EI64_V_M1_MF2_MASK }, // 1029 |
31431 | | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG6EI64_V_M2_MF2_MASK }, // 1030 |
31432 | | { 0x6, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG6EI64_V_M4_MF2_MASK }, // 1031 |
31433 | | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG7EI8_V_M1_M1 }, // 1032 |
31434 | | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG7EI8_V_MF8_M1 }, // 1033 |
31435 | | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG7EI8_V_MF4_M1 }, // 1034 |
31436 | | { 0x7, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG7EI8_V_MF2_M1 }, // 1035 |
31437 | | { 0x7, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF8 }, // 1036 |
31438 | | { 0x7, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF4 }, // 1037 |
31439 | | { 0x7, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF4 }, // 1038 |
31440 | | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF2 }, // 1039 |
31441 | | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF2 }, // 1040 |
31442 | | { 0x7, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG7EI8_V_MF2_MF2 }, // 1041 |
31443 | | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG7EI16_V_M1_M1 }, // 1042 |
31444 | | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG7EI16_V_M2_M1 }, // 1043 |
31445 | | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG7EI16_V_MF4_M1 }, // 1044 |
31446 | | { 0x7, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG7EI16_V_MF2_M1 }, // 1045 |
31447 | | { 0x7, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF8 }, // 1046 |
31448 | | { 0x7, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF4 }, // 1047 |
31449 | | { 0x7, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF4 }, // 1048 |
31450 | | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG7EI16_V_M1_MF2 }, // 1049 |
31451 | | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF2 }, // 1050 |
31452 | | { 0x7, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF2 }, // 1051 |
31453 | | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG7EI32_V_M1_M1 }, // 1052 |
31454 | | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG7EI32_V_M2_M1 }, // 1053 |
31455 | | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG7EI32_V_M4_M1 }, // 1054 |
31456 | | { 0x7, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG7EI32_V_MF2_M1 }, // 1055 |
31457 | | { 0x7, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF8 }, // 1056 |
31458 | | { 0x7, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG7EI32_V_M1_MF4 }, // 1057 |
31459 | | { 0x7, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF4 }, // 1058 |
31460 | | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG7EI32_V_M1_MF2 }, // 1059 |
31461 | | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG7EI32_V_M2_MF2 }, // 1060 |
31462 | | { 0x7, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF2 }, // 1061 |
31463 | | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG7EI64_V_M1_M1 }, // 1062 |
31464 | | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG7EI64_V_M2_M1 }, // 1063 |
31465 | | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG7EI64_V_M4_M1 }, // 1064 |
31466 | | { 0x7, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG7EI64_V_M8_M1 }, // 1065 |
31467 | | { 0x7, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG7EI64_V_M1_MF8 }, // 1066 |
31468 | | { 0x7, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG7EI64_V_M1_MF4 }, // 1067 |
31469 | | { 0x7, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG7EI64_V_M2_MF4 }, // 1068 |
31470 | | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG7EI64_V_M1_MF2 }, // 1069 |
31471 | | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG7EI64_V_M2_MF2 }, // 1070 |
31472 | | { 0x7, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG7EI64_V_M4_MF2 }, // 1071 |
31473 | | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG7EI8_V_M1_M1 }, // 1072 |
31474 | | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG7EI8_V_MF8_M1 }, // 1073 |
31475 | | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG7EI8_V_MF4_M1 }, // 1074 |
31476 | | { 0x7, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG7EI8_V_MF2_M1 }, // 1075 |
31477 | | { 0x7, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF8 }, // 1076 |
31478 | | { 0x7, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF4 }, // 1077 |
31479 | | { 0x7, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF4 }, // 1078 |
31480 | | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF2 }, // 1079 |
31481 | | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF2 }, // 1080 |
31482 | | { 0x7, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG7EI8_V_MF2_MF2 }, // 1081 |
31483 | | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG7EI16_V_M1_M1 }, // 1082 |
31484 | | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG7EI16_V_M2_M1 }, // 1083 |
31485 | | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG7EI16_V_MF4_M1 }, // 1084 |
31486 | | { 0x7, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG7EI16_V_MF2_M1 }, // 1085 |
31487 | | { 0x7, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF8 }, // 1086 |
31488 | | { 0x7, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF4 }, // 1087 |
31489 | | { 0x7, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF4 }, // 1088 |
31490 | | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG7EI16_V_M1_MF2 }, // 1089 |
31491 | | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF2 }, // 1090 |
31492 | | { 0x7, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF2 }, // 1091 |
31493 | | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG7EI32_V_M1_M1 }, // 1092 |
31494 | | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG7EI32_V_M2_M1 }, // 1093 |
31495 | | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG7EI32_V_M4_M1 }, // 1094 |
31496 | | { 0x7, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG7EI32_V_MF2_M1 }, // 1095 |
31497 | | { 0x7, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF8 }, // 1096 |
31498 | | { 0x7, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG7EI32_V_M1_MF4 }, // 1097 |
31499 | | { 0x7, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF4 }, // 1098 |
31500 | | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG7EI32_V_M1_MF2 }, // 1099 |
31501 | | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG7EI32_V_M2_MF2 }, // 1100 |
31502 | | { 0x7, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF2 }, // 1101 |
31503 | | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG7EI64_V_M1_M1 }, // 1102 |
31504 | | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG7EI64_V_M2_M1 }, // 1103 |
31505 | | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG7EI64_V_M4_M1 }, // 1104 |
31506 | | { 0x7, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG7EI64_V_M8_M1 }, // 1105 |
31507 | | { 0x7, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG7EI64_V_M1_MF8 }, // 1106 |
31508 | | { 0x7, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG7EI64_V_M1_MF4 }, // 1107 |
31509 | | { 0x7, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG7EI64_V_M2_MF4 }, // 1108 |
31510 | | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG7EI64_V_M1_MF2 }, // 1109 |
31511 | | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG7EI64_V_M2_MF2 }, // 1110 |
31512 | | { 0x7, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG7EI64_V_M4_MF2 }, // 1111 |
31513 | | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG7EI8_V_M1_M1_MASK }, // 1112 |
31514 | | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG7EI8_V_MF8_M1_MASK }, // 1113 |
31515 | | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG7EI8_V_MF4_M1_MASK }, // 1114 |
31516 | | { 0x7, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG7EI8_V_MF2_M1_MASK }, // 1115 |
31517 | | { 0x7, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF8_MASK }, // 1116 |
31518 | | { 0x7, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF4_MASK }, // 1117 |
31519 | | { 0x7, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF4_MASK }, // 1118 |
31520 | | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG7EI8_V_MF8_MF2_MASK }, // 1119 |
31521 | | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG7EI8_V_MF4_MF2_MASK }, // 1120 |
31522 | | { 0x7, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG7EI8_V_MF2_MF2_MASK }, // 1121 |
31523 | | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG7EI16_V_M1_M1_MASK }, // 1122 |
31524 | | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG7EI16_V_M2_M1_MASK }, // 1123 |
31525 | | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG7EI16_V_MF4_M1_MASK }, // 1124 |
31526 | | { 0x7, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG7EI16_V_MF2_M1_MASK }, // 1125 |
31527 | | { 0x7, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF8_MASK }, // 1126 |
31528 | | { 0x7, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF4_MASK }, // 1127 |
31529 | | { 0x7, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF4_MASK }, // 1128 |
31530 | | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG7EI16_V_M1_MF2_MASK }, // 1129 |
31531 | | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG7EI16_V_MF4_MF2_MASK }, // 1130 |
31532 | | { 0x7, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG7EI16_V_MF2_MF2_MASK }, // 1131 |
31533 | | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG7EI32_V_M1_M1_MASK }, // 1132 |
31534 | | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG7EI32_V_M2_M1_MASK }, // 1133 |
31535 | | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG7EI32_V_M4_M1_MASK }, // 1134 |
31536 | | { 0x7, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG7EI32_V_MF2_M1_MASK }, // 1135 |
31537 | | { 0x7, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF8_MASK }, // 1136 |
31538 | | { 0x7, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG7EI32_V_M1_MF4_MASK }, // 1137 |
31539 | | { 0x7, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF4_MASK }, // 1138 |
31540 | | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG7EI32_V_M1_MF2_MASK }, // 1139 |
31541 | | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG7EI32_V_M2_MF2_MASK }, // 1140 |
31542 | | { 0x7, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG7EI32_V_MF2_MF2_MASK }, // 1141 |
31543 | | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG7EI64_V_M1_M1_MASK }, // 1142 |
31544 | | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG7EI64_V_M2_M1_MASK }, // 1143 |
31545 | | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG7EI64_V_M4_M1_MASK }, // 1144 |
31546 | | { 0x7, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG7EI64_V_M8_M1_MASK }, // 1145 |
31547 | | { 0x7, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG7EI64_V_M1_MF8_MASK }, // 1146 |
31548 | | { 0x7, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG7EI64_V_M1_MF4_MASK }, // 1147 |
31549 | | { 0x7, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG7EI64_V_M2_MF4_MASK }, // 1148 |
31550 | | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG7EI64_V_M1_MF2_MASK }, // 1149 |
31551 | | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG7EI64_V_M2_MF2_MASK }, // 1150 |
31552 | | { 0x7, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG7EI64_V_M4_MF2_MASK }, // 1151 |
31553 | | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG7EI8_V_M1_M1_MASK }, // 1152 |
31554 | | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG7EI8_V_MF8_M1_MASK }, // 1153 |
31555 | | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG7EI8_V_MF4_M1_MASK }, // 1154 |
31556 | | { 0x7, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG7EI8_V_MF2_M1_MASK }, // 1155 |
31557 | | { 0x7, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF8_MASK }, // 1156 |
31558 | | { 0x7, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF4_MASK }, // 1157 |
31559 | | { 0x7, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF4_MASK }, // 1158 |
31560 | | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG7EI8_V_MF8_MF2_MASK }, // 1159 |
31561 | | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG7EI8_V_MF4_MF2_MASK }, // 1160 |
31562 | | { 0x7, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG7EI8_V_MF2_MF2_MASK }, // 1161 |
31563 | | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG7EI16_V_M1_M1_MASK }, // 1162 |
31564 | | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG7EI16_V_M2_M1_MASK }, // 1163 |
31565 | | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG7EI16_V_MF4_M1_MASK }, // 1164 |
31566 | | { 0x7, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG7EI16_V_MF2_M1_MASK }, // 1165 |
31567 | | { 0x7, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF8_MASK }, // 1166 |
31568 | | { 0x7, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF4_MASK }, // 1167 |
31569 | | { 0x7, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF4_MASK }, // 1168 |
31570 | | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG7EI16_V_M1_MF2_MASK }, // 1169 |
31571 | | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG7EI16_V_MF4_MF2_MASK }, // 1170 |
31572 | | { 0x7, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG7EI16_V_MF2_MF2_MASK }, // 1171 |
31573 | | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG7EI32_V_M1_M1_MASK }, // 1172 |
31574 | | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG7EI32_V_M2_M1_MASK }, // 1173 |
31575 | | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG7EI32_V_M4_M1_MASK }, // 1174 |
31576 | | { 0x7, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG7EI32_V_MF2_M1_MASK }, // 1175 |
31577 | | { 0x7, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF8_MASK }, // 1176 |
31578 | | { 0x7, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG7EI32_V_M1_MF4_MASK }, // 1177 |
31579 | | { 0x7, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF4_MASK }, // 1178 |
31580 | | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG7EI32_V_M1_MF2_MASK }, // 1179 |
31581 | | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG7EI32_V_M2_MF2_MASK }, // 1180 |
31582 | | { 0x7, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG7EI32_V_MF2_MF2_MASK }, // 1181 |
31583 | | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG7EI64_V_M1_M1_MASK }, // 1182 |
31584 | | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG7EI64_V_M2_M1_MASK }, // 1183 |
31585 | | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG7EI64_V_M4_M1_MASK }, // 1184 |
31586 | | { 0x7, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG7EI64_V_M8_M1_MASK }, // 1185 |
31587 | | { 0x7, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG7EI64_V_M1_MF8_MASK }, // 1186 |
31588 | | { 0x7, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG7EI64_V_M1_MF4_MASK }, // 1187 |
31589 | | { 0x7, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG7EI64_V_M2_MF4_MASK }, // 1188 |
31590 | | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG7EI64_V_M1_MF2_MASK }, // 1189 |
31591 | | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG7EI64_V_M2_MF2_MASK }, // 1190 |
31592 | | { 0x7, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG7EI64_V_M4_MF2_MASK }, // 1191 |
31593 | | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG8EI8_V_M1_M1 }, // 1192 |
31594 | | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG8EI8_V_MF8_M1 }, // 1193 |
31595 | | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG8EI8_V_MF4_M1 }, // 1194 |
31596 | | { 0x8, 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG8EI8_V_MF2_M1 }, // 1195 |
31597 | | { 0x8, 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF8 }, // 1196 |
31598 | | { 0x8, 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF4 }, // 1197 |
31599 | | { 0x8, 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF4 }, // 1198 |
31600 | | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF2 }, // 1199 |
31601 | | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF2 }, // 1200 |
31602 | | { 0x8, 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG8EI8_V_MF2_MF2 }, // 1201 |
31603 | | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG8EI16_V_M1_M1 }, // 1202 |
31604 | | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG8EI16_V_M2_M1 }, // 1203 |
31605 | | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG8EI16_V_MF4_M1 }, // 1204 |
31606 | | { 0x8, 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG8EI16_V_MF2_M1 }, // 1205 |
31607 | | { 0x8, 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF8 }, // 1206 |
31608 | | { 0x8, 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF4 }, // 1207 |
31609 | | { 0x8, 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF4 }, // 1208 |
31610 | | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG8EI16_V_M1_MF2 }, // 1209 |
31611 | | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF2 }, // 1210 |
31612 | | { 0x8, 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF2 }, // 1211 |
31613 | | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG8EI32_V_M1_M1 }, // 1212 |
31614 | | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG8EI32_V_M2_M1 }, // 1213 |
31615 | | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG8EI32_V_M4_M1 }, // 1214 |
31616 | | { 0x8, 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG8EI32_V_MF2_M1 }, // 1215 |
31617 | | { 0x8, 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF8 }, // 1216 |
31618 | | { 0x8, 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG8EI32_V_M1_MF4 }, // 1217 |
31619 | | { 0x8, 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF4 }, // 1218 |
31620 | | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG8EI32_V_M1_MF2 }, // 1219 |
31621 | | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG8EI32_V_M2_MF2 }, // 1220 |
31622 | | { 0x8, 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF2 }, // 1221 |
31623 | | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG8EI64_V_M1_M1 }, // 1222 |
31624 | | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG8EI64_V_M2_M1 }, // 1223 |
31625 | | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG8EI64_V_M4_M1 }, // 1224 |
31626 | | { 0x8, 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG8EI64_V_M8_M1 }, // 1225 |
31627 | | { 0x8, 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG8EI64_V_M1_MF8 }, // 1226 |
31628 | | { 0x8, 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG8EI64_V_M1_MF4 }, // 1227 |
31629 | | { 0x8, 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG8EI64_V_M2_MF4 }, // 1228 |
31630 | | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG8EI64_V_M1_MF2 }, // 1229 |
31631 | | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG8EI64_V_M2_MF2 }, // 1230 |
31632 | | { 0x8, 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG8EI64_V_M4_MF2 }, // 1231 |
31633 | | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG8EI8_V_M1_M1 }, // 1232 |
31634 | | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG8EI8_V_MF8_M1 }, // 1233 |
31635 | | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG8EI8_V_MF4_M1 }, // 1234 |
31636 | | { 0x8, 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG8EI8_V_MF2_M1 }, // 1235 |
31637 | | { 0x8, 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF8 }, // 1236 |
31638 | | { 0x8, 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF4 }, // 1237 |
31639 | | { 0x8, 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF4 }, // 1238 |
31640 | | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF2 }, // 1239 |
31641 | | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF2 }, // 1240 |
31642 | | { 0x8, 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG8EI8_V_MF2_MF2 }, // 1241 |
31643 | | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG8EI16_V_M1_M1 }, // 1242 |
31644 | | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG8EI16_V_M2_M1 }, // 1243 |
31645 | | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG8EI16_V_MF4_M1 }, // 1244 |
31646 | | { 0x8, 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG8EI16_V_MF2_M1 }, // 1245 |
31647 | | { 0x8, 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF8 }, // 1246 |
31648 | | { 0x8, 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF4 }, // 1247 |
31649 | | { 0x8, 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF4 }, // 1248 |
31650 | | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG8EI16_V_M1_MF2 }, // 1249 |
31651 | | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF2 }, // 1250 |
31652 | | { 0x8, 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF2 }, // 1251 |
31653 | | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG8EI32_V_M1_M1 }, // 1252 |
31654 | | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG8EI32_V_M2_M1 }, // 1253 |
31655 | | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG8EI32_V_M4_M1 }, // 1254 |
31656 | | { 0x8, 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG8EI32_V_MF2_M1 }, // 1255 |
31657 | | { 0x8, 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF8 }, // 1256 |
31658 | | { 0x8, 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG8EI32_V_M1_MF4 }, // 1257 |
31659 | | { 0x8, 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF4 }, // 1258 |
31660 | | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG8EI32_V_M1_MF2 }, // 1259 |
31661 | | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG8EI32_V_M2_MF2 }, // 1260 |
31662 | | { 0x8, 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF2 }, // 1261 |
31663 | | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG8EI64_V_M1_M1 }, // 1262 |
31664 | | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG8EI64_V_M2_M1 }, // 1263 |
31665 | | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG8EI64_V_M4_M1 }, // 1264 |
31666 | | { 0x8, 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG8EI64_V_M8_M1 }, // 1265 |
31667 | | { 0x8, 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG8EI64_V_M1_MF8 }, // 1266 |
31668 | | { 0x8, 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG8EI64_V_M1_MF4 }, // 1267 |
31669 | | { 0x8, 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG8EI64_V_M2_MF4 }, // 1268 |
31670 | | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG8EI64_V_M1_MF2 }, // 1269 |
31671 | | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG8EI64_V_M2_MF2 }, // 1270 |
31672 | | { 0x8, 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG8EI64_V_M4_MF2 }, // 1271 |
31673 | | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXSEG8EI8_V_M1_M1_MASK }, // 1272 |
31674 | | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXSEG8EI8_V_MF8_M1_MASK }, // 1273 |
31675 | | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXSEG8EI8_V_MF4_M1_MASK }, // 1274 |
31676 | | { 0x8, 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXSEG8EI8_V_MF2_M1_MASK }, // 1275 |
31677 | | { 0x8, 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF8_MASK }, // 1276 |
31678 | | { 0x8, 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF4_MASK }, // 1277 |
31679 | | { 0x8, 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF4_MASK }, // 1278 |
31680 | | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXSEG8EI8_V_MF8_MF2_MASK }, // 1279 |
31681 | | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXSEG8EI8_V_MF4_MF2_MASK }, // 1280 |
31682 | | { 0x8, 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXSEG8EI8_V_MF2_MF2_MASK }, // 1281 |
31683 | | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXSEG8EI16_V_M1_M1_MASK }, // 1282 |
31684 | | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXSEG8EI16_V_M2_M1_MASK }, // 1283 |
31685 | | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXSEG8EI16_V_MF4_M1_MASK }, // 1284 |
31686 | | { 0x8, 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXSEG8EI16_V_MF2_M1_MASK }, // 1285 |
31687 | | { 0x8, 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF8_MASK }, // 1286 |
31688 | | { 0x8, 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF4_MASK }, // 1287 |
31689 | | { 0x8, 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF4_MASK }, // 1288 |
31690 | | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXSEG8EI16_V_M1_MF2_MASK }, // 1289 |
31691 | | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXSEG8EI16_V_MF4_MF2_MASK }, // 1290 |
31692 | | { 0x8, 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXSEG8EI16_V_MF2_MF2_MASK }, // 1291 |
31693 | | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXSEG8EI32_V_M1_M1_MASK }, // 1292 |
31694 | | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXSEG8EI32_V_M2_M1_MASK }, // 1293 |
31695 | | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXSEG8EI32_V_M4_M1_MASK }, // 1294 |
31696 | | { 0x8, 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXSEG8EI32_V_MF2_M1_MASK }, // 1295 |
31697 | | { 0x8, 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF8_MASK }, // 1296 |
31698 | | { 0x8, 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXSEG8EI32_V_M1_MF4_MASK }, // 1297 |
31699 | | { 0x8, 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF4_MASK }, // 1298 |
31700 | | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXSEG8EI32_V_M1_MF2_MASK }, // 1299 |
31701 | | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXSEG8EI32_V_M2_MF2_MASK }, // 1300 |
31702 | | { 0x8, 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXSEG8EI32_V_MF2_MF2_MASK }, // 1301 |
31703 | | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXSEG8EI64_V_M1_M1_MASK }, // 1302 |
31704 | | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXSEG8EI64_V_M2_M1_MASK }, // 1303 |
31705 | | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXSEG8EI64_V_M4_M1_MASK }, // 1304 |
31706 | | { 0x8, 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXSEG8EI64_V_M8_M1_MASK }, // 1305 |
31707 | | { 0x8, 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXSEG8EI64_V_M1_MF8_MASK }, // 1306 |
31708 | | { 0x8, 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXSEG8EI64_V_M1_MF4_MASK }, // 1307 |
31709 | | { 0x8, 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXSEG8EI64_V_M2_MF4_MASK }, // 1308 |
31710 | | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXSEG8EI64_V_M1_MF2_MASK }, // 1309 |
31711 | | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXSEG8EI64_V_M2_MF2_MASK }, // 1310 |
31712 | | { 0x8, 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXSEG8EI64_V_M4_MF2_MASK }, // 1311 |
31713 | | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXSEG8EI8_V_M1_M1_MASK }, // 1312 |
31714 | | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXSEG8EI8_V_MF8_M1_MASK }, // 1313 |
31715 | | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXSEG8EI8_V_MF4_M1_MASK }, // 1314 |
31716 | | { 0x8, 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXSEG8EI8_V_MF2_M1_MASK }, // 1315 |
31717 | | { 0x8, 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF8_MASK }, // 1316 |
31718 | | { 0x8, 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF4_MASK }, // 1317 |
31719 | | { 0x8, 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF4_MASK }, // 1318 |
31720 | | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXSEG8EI8_V_MF8_MF2_MASK }, // 1319 |
31721 | | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXSEG8EI8_V_MF4_MF2_MASK }, // 1320 |
31722 | | { 0x8, 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXSEG8EI8_V_MF2_MF2_MASK }, // 1321 |
31723 | | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXSEG8EI16_V_M1_M1_MASK }, // 1322 |
31724 | | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXSEG8EI16_V_M2_M1_MASK }, // 1323 |
31725 | | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXSEG8EI16_V_MF4_M1_MASK }, // 1324 |
31726 | | { 0x8, 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXSEG8EI16_V_MF2_M1_MASK }, // 1325 |
31727 | | { 0x8, 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF8_MASK }, // 1326 |
31728 | | { 0x8, 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF4_MASK }, // 1327 |
31729 | | { 0x8, 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF4_MASK }, // 1328 |
31730 | | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXSEG8EI16_V_M1_MF2_MASK }, // 1329 |
31731 | | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXSEG8EI16_V_MF4_MF2_MASK }, // 1330 |
31732 | | { 0x8, 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXSEG8EI16_V_MF2_MF2_MASK }, // 1331 |
31733 | | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXSEG8EI32_V_M1_M1_MASK }, // 1332 |
31734 | | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXSEG8EI32_V_M2_M1_MASK }, // 1333 |
31735 | | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXSEG8EI32_V_M4_M1_MASK }, // 1334 |
31736 | | { 0x8, 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXSEG8EI32_V_MF2_M1_MASK }, // 1335 |
31737 | | { 0x8, 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF8_MASK }, // 1336 |
31738 | | { 0x8, 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXSEG8EI32_V_M1_MF4_MASK }, // 1337 |
31739 | | { 0x8, 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF4_MASK }, // 1338 |
31740 | | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXSEG8EI32_V_M1_MF2_MASK }, // 1339 |
31741 | | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXSEG8EI32_V_M2_MF2_MASK }, // 1340 |
31742 | | { 0x8, 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXSEG8EI32_V_MF2_MF2_MASK }, // 1341 |
31743 | | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXSEG8EI64_V_M1_M1_MASK }, // 1342 |
31744 | | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXSEG8EI64_V_M2_M1_MASK }, // 1343 |
31745 | | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXSEG8EI64_V_M4_M1_MASK }, // 1344 |
31746 | | { 0x8, 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXSEG8EI64_V_M8_M1_MASK }, // 1345 |
31747 | | { 0x8, 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXSEG8EI64_V_M1_MF8_MASK }, // 1346 |
31748 | | { 0x8, 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXSEG8EI64_V_M1_MF4_MASK }, // 1347 |
31749 | | { 0x8, 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXSEG8EI64_V_M2_MF4_MASK }, // 1348 |
31750 | | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXSEG8EI64_V_M1_MF2_MASK }, // 1349 |
31751 | | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXSEG8EI64_V_M2_MF2_MASK }, // 1350 |
31752 | | { 0x8, 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXSEG8EI64_V_M4_MF2_MASK }, // 1351 |
31753 | | }; |
31754 | | |
31755 | | const RISCV_VSXSEGPseudo *RISCV_getVSXSEGPseudo(uint8_t NF, uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) { |
31756 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), NFMaskedOrderedLog2SEWLMULIndexLMUL); |
31757 | | if (i == -1) |
31758 | | return NULL; |
31759 | | else |
31760 | | return &RISCVVSXSEGTable[Index[i].index]; |
31761 | | } |
31762 | | |
31763 | | #endif |
31764 | | |
31765 | | #ifdef GET_RISCVVSXTable_IMPL |
31766 | | static const RISCV_VLX_VSXPseudo RISCVVSXTable[] = { |
31767 | | { 0x0, 0x0, 0x3, 0x0, 0x0, PseudoVSUXEI8_V_M1_M1 }, // 0 |
31768 | | { 0x0, 0x0, 0x3, 0x0, 0x5, PseudoVSUXEI8_V_MF8_M1 }, // 1 |
31769 | | { 0x0, 0x0, 0x3, 0x0, 0x6, PseudoVSUXEI8_V_MF4_M1 }, // 2 |
31770 | | { 0x0, 0x0, 0x3, 0x0, 0x7, PseudoVSUXEI8_V_MF2_M1 }, // 3 |
31771 | | { 0x0, 0x0, 0x3, 0x1, 0x0, PseudoVSUXEI8_V_M1_M2 }, // 4 |
31772 | | { 0x0, 0x0, 0x3, 0x1, 0x1, PseudoVSUXEI8_V_M2_M2 }, // 5 |
31773 | | { 0x0, 0x0, 0x3, 0x1, 0x6, PseudoVSUXEI8_V_MF4_M2 }, // 6 |
31774 | | { 0x0, 0x0, 0x3, 0x1, 0x7, PseudoVSUXEI8_V_MF2_M2 }, // 7 |
31775 | | { 0x0, 0x0, 0x3, 0x2, 0x0, PseudoVSUXEI8_V_M1_M4 }, // 8 |
31776 | | { 0x0, 0x0, 0x3, 0x2, 0x1, PseudoVSUXEI8_V_M2_M4 }, // 9 |
31777 | | { 0x0, 0x0, 0x3, 0x2, 0x2, PseudoVSUXEI8_V_M4_M4 }, // 10 |
31778 | | { 0x0, 0x0, 0x3, 0x2, 0x7, PseudoVSUXEI8_V_MF2_M4 }, // 11 |
31779 | | { 0x0, 0x0, 0x3, 0x3, 0x0, PseudoVSUXEI8_V_M1_M8 }, // 12 |
31780 | | { 0x0, 0x0, 0x3, 0x3, 0x1, PseudoVSUXEI8_V_M2_M8 }, // 13 |
31781 | | { 0x0, 0x0, 0x3, 0x3, 0x2, PseudoVSUXEI8_V_M4_M8 }, // 14 |
31782 | | { 0x0, 0x0, 0x3, 0x3, 0x3, PseudoVSUXEI8_V_M8_M8 }, // 15 |
31783 | | { 0x0, 0x0, 0x3, 0x5, 0x5, PseudoVSUXEI8_V_MF8_MF8 }, // 16 |
31784 | | { 0x0, 0x0, 0x3, 0x6, 0x5, PseudoVSUXEI8_V_MF8_MF4 }, // 17 |
31785 | | { 0x0, 0x0, 0x3, 0x6, 0x6, PseudoVSUXEI8_V_MF4_MF4 }, // 18 |
31786 | | { 0x0, 0x0, 0x3, 0x7, 0x5, PseudoVSUXEI8_V_MF8_MF2 }, // 19 |
31787 | | { 0x0, 0x0, 0x3, 0x7, 0x6, PseudoVSUXEI8_V_MF4_MF2 }, // 20 |
31788 | | { 0x0, 0x0, 0x3, 0x7, 0x7, PseudoVSUXEI8_V_MF2_MF2 }, // 21 |
31789 | | { 0x0, 0x0, 0x4, 0x0, 0x0, PseudoVSUXEI16_V_M1_M1 }, // 22 |
31790 | | { 0x0, 0x0, 0x4, 0x0, 0x1, PseudoVSUXEI16_V_M2_M1 }, // 23 |
31791 | | { 0x0, 0x0, 0x4, 0x0, 0x6, PseudoVSUXEI16_V_MF4_M1 }, // 24 |
31792 | | { 0x0, 0x0, 0x4, 0x0, 0x7, PseudoVSUXEI16_V_MF2_M1 }, // 25 |
31793 | | { 0x0, 0x0, 0x4, 0x1, 0x0, PseudoVSUXEI16_V_M1_M2 }, // 26 |
31794 | | { 0x0, 0x0, 0x4, 0x1, 0x1, PseudoVSUXEI16_V_M2_M2 }, // 27 |
31795 | | { 0x0, 0x0, 0x4, 0x1, 0x2, PseudoVSUXEI16_V_M4_M2 }, // 28 |
31796 | | { 0x0, 0x0, 0x4, 0x1, 0x7, PseudoVSUXEI16_V_MF2_M2 }, // 29 |
31797 | | { 0x0, 0x0, 0x4, 0x2, 0x0, PseudoVSUXEI16_V_M1_M4 }, // 30 |
31798 | | { 0x0, 0x0, 0x4, 0x2, 0x1, PseudoVSUXEI16_V_M2_M4 }, // 31 |
31799 | | { 0x0, 0x0, 0x4, 0x2, 0x2, PseudoVSUXEI16_V_M4_M4 }, // 32 |
31800 | | { 0x0, 0x0, 0x4, 0x2, 0x3, PseudoVSUXEI16_V_M8_M4 }, // 33 |
31801 | | { 0x0, 0x0, 0x4, 0x3, 0x1, PseudoVSUXEI16_V_M2_M8 }, // 34 |
31802 | | { 0x0, 0x0, 0x4, 0x3, 0x2, PseudoVSUXEI16_V_M4_M8 }, // 35 |
31803 | | { 0x0, 0x0, 0x4, 0x3, 0x3, PseudoVSUXEI16_V_M8_M8 }, // 36 |
31804 | | { 0x0, 0x0, 0x4, 0x5, 0x6, PseudoVSUXEI16_V_MF4_MF8 }, // 37 |
31805 | | { 0x0, 0x0, 0x4, 0x6, 0x6, PseudoVSUXEI16_V_MF4_MF4 }, // 38 |
31806 | | { 0x0, 0x0, 0x4, 0x6, 0x7, PseudoVSUXEI16_V_MF2_MF4 }, // 39 |
31807 | | { 0x0, 0x0, 0x4, 0x7, 0x0, PseudoVSUXEI16_V_M1_MF2 }, // 40 |
31808 | | { 0x0, 0x0, 0x4, 0x7, 0x6, PseudoVSUXEI16_V_MF4_MF2 }, // 41 |
31809 | | { 0x0, 0x0, 0x4, 0x7, 0x7, PseudoVSUXEI16_V_MF2_MF2 }, // 42 |
31810 | | { 0x0, 0x0, 0x5, 0x0, 0x0, PseudoVSUXEI32_V_M1_M1 }, // 43 |
31811 | | { 0x0, 0x0, 0x5, 0x0, 0x1, PseudoVSUXEI32_V_M2_M1 }, // 44 |
31812 | | { 0x0, 0x0, 0x5, 0x0, 0x2, PseudoVSUXEI32_V_M4_M1 }, // 45 |
31813 | | { 0x0, 0x0, 0x5, 0x0, 0x7, PseudoVSUXEI32_V_MF2_M1 }, // 46 |
31814 | | { 0x0, 0x0, 0x5, 0x1, 0x0, PseudoVSUXEI32_V_M1_M2 }, // 47 |
31815 | | { 0x0, 0x0, 0x5, 0x1, 0x1, PseudoVSUXEI32_V_M2_M2 }, // 48 |
31816 | | { 0x0, 0x0, 0x5, 0x1, 0x2, PseudoVSUXEI32_V_M4_M2 }, // 49 |
31817 | | { 0x0, 0x0, 0x5, 0x1, 0x3, PseudoVSUXEI32_V_M8_M2 }, // 50 |
31818 | | { 0x0, 0x0, 0x5, 0x2, 0x1, PseudoVSUXEI32_V_M2_M4 }, // 51 |
31819 | | { 0x0, 0x0, 0x5, 0x2, 0x2, PseudoVSUXEI32_V_M4_M4 }, // 52 |
31820 | | { 0x0, 0x0, 0x5, 0x2, 0x3, PseudoVSUXEI32_V_M8_M4 }, // 53 |
31821 | | { 0x0, 0x0, 0x5, 0x3, 0x2, PseudoVSUXEI32_V_M4_M8 }, // 54 |
31822 | | { 0x0, 0x0, 0x5, 0x3, 0x3, PseudoVSUXEI32_V_M8_M8 }, // 55 |
31823 | | { 0x0, 0x0, 0x5, 0x5, 0x7, PseudoVSUXEI32_V_MF2_MF8 }, // 56 |
31824 | | { 0x0, 0x0, 0x5, 0x6, 0x0, PseudoVSUXEI32_V_M1_MF4 }, // 57 |
31825 | | { 0x0, 0x0, 0x5, 0x6, 0x7, PseudoVSUXEI32_V_MF2_MF4 }, // 58 |
31826 | | { 0x0, 0x0, 0x5, 0x7, 0x0, PseudoVSUXEI32_V_M1_MF2 }, // 59 |
31827 | | { 0x0, 0x0, 0x5, 0x7, 0x1, PseudoVSUXEI32_V_M2_MF2 }, // 60 |
31828 | | { 0x0, 0x0, 0x5, 0x7, 0x7, PseudoVSUXEI32_V_MF2_MF2 }, // 61 |
31829 | | { 0x0, 0x0, 0x6, 0x0, 0x0, PseudoVSUXEI64_V_M1_M1 }, // 62 |
31830 | | { 0x0, 0x0, 0x6, 0x0, 0x1, PseudoVSUXEI64_V_M2_M1 }, // 63 |
31831 | | { 0x0, 0x0, 0x6, 0x0, 0x2, PseudoVSUXEI64_V_M4_M1 }, // 64 |
31832 | | { 0x0, 0x0, 0x6, 0x0, 0x3, PseudoVSUXEI64_V_M8_M1 }, // 65 |
31833 | | { 0x0, 0x0, 0x6, 0x1, 0x1, PseudoVSUXEI64_V_M2_M2 }, // 66 |
31834 | | { 0x0, 0x0, 0x6, 0x1, 0x2, PseudoVSUXEI64_V_M4_M2 }, // 67 |
31835 | | { 0x0, 0x0, 0x6, 0x1, 0x3, PseudoVSUXEI64_V_M8_M2 }, // 68 |
31836 | | { 0x0, 0x0, 0x6, 0x2, 0x2, PseudoVSUXEI64_V_M4_M4 }, // 69 |
31837 | | { 0x0, 0x0, 0x6, 0x2, 0x3, PseudoVSUXEI64_V_M8_M4 }, // 70 |
31838 | | { 0x0, 0x0, 0x6, 0x3, 0x3, PseudoVSUXEI64_V_M8_M8 }, // 71 |
31839 | | { 0x0, 0x0, 0x6, 0x5, 0x0, PseudoVSUXEI64_V_M1_MF8 }, // 72 |
31840 | | { 0x0, 0x0, 0x6, 0x6, 0x0, PseudoVSUXEI64_V_M1_MF4 }, // 73 |
31841 | | { 0x0, 0x0, 0x6, 0x6, 0x1, PseudoVSUXEI64_V_M2_MF4 }, // 74 |
31842 | | { 0x0, 0x0, 0x6, 0x7, 0x0, PseudoVSUXEI64_V_M1_MF2 }, // 75 |
31843 | | { 0x0, 0x0, 0x6, 0x7, 0x1, PseudoVSUXEI64_V_M2_MF2 }, // 76 |
31844 | | { 0x0, 0x0, 0x6, 0x7, 0x2, PseudoVSUXEI64_V_M4_MF2 }, // 77 |
31845 | | { 0x0, 0x1, 0x3, 0x0, 0x0, PseudoVSOXEI8_V_M1_M1 }, // 78 |
31846 | | { 0x0, 0x1, 0x3, 0x0, 0x5, PseudoVSOXEI8_V_MF8_M1 }, // 79 |
31847 | | { 0x0, 0x1, 0x3, 0x0, 0x6, PseudoVSOXEI8_V_MF4_M1 }, // 80 |
31848 | | { 0x0, 0x1, 0x3, 0x0, 0x7, PseudoVSOXEI8_V_MF2_M1 }, // 81 |
31849 | | { 0x0, 0x1, 0x3, 0x1, 0x0, PseudoVSOXEI8_V_M1_M2 }, // 82 |
31850 | | { 0x0, 0x1, 0x3, 0x1, 0x1, PseudoVSOXEI8_V_M2_M2 }, // 83 |
31851 | | { 0x0, 0x1, 0x3, 0x1, 0x6, PseudoVSOXEI8_V_MF4_M2 }, // 84 |
31852 | | { 0x0, 0x1, 0x3, 0x1, 0x7, PseudoVSOXEI8_V_MF2_M2 }, // 85 |
31853 | | { 0x0, 0x1, 0x3, 0x2, 0x0, PseudoVSOXEI8_V_M1_M4 }, // 86 |
31854 | | { 0x0, 0x1, 0x3, 0x2, 0x1, PseudoVSOXEI8_V_M2_M4 }, // 87 |
31855 | | { 0x0, 0x1, 0x3, 0x2, 0x2, PseudoVSOXEI8_V_M4_M4 }, // 88 |
31856 | | { 0x0, 0x1, 0x3, 0x2, 0x7, PseudoVSOXEI8_V_MF2_M4 }, // 89 |
31857 | | { 0x0, 0x1, 0x3, 0x3, 0x0, PseudoVSOXEI8_V_M1_M8 }, // 90 |
31858 | | { 0x0, 0x1, 0x3, 0x3, 0x1, PseudoVSOXEI8_V_M2_M8 }, // 91 |
31859 | | { 0x0, 0x1, 0x3, 0x3, 0x2, PseudoVSOXEI8_V_M4_M8 }, // 92 |
31860 | | { 0x0, 0x1, 0x3, 0x3, 0x3, PseudoVSOXEI8_V_M8_M8 }, // 93 |
31861 | | { 0x0, 0x1, 0x3, 0x5, 0x5, PseudoVSOXEI8_V_MF8_MF8 }, // 94 |
31862 | | { 0x0, 0x1, 0x3, 0x6, 0x5, PseudoVSOXEI8_V_MF8_MF4 }, // 95 |
31863 | | { 0x0, 0x1, 0x3, 0x6, 0x6, PseudoVSOXEI8_V_MF4_MF4 }, // 96 |
31864 | | { 0x0, 0x1, 0x3, 0x7, 0x5, PseudoVSOXEI8_V_MF8_MF2 }, // 97 |
31865 | | { 0x0, 0x1, 0x3, 0x7, 0x6, PseudoVSOXEI8_V_MF4_MF2 }, // 98 |
31866 | | { 0x0, 0x1, 0x3, 0x7, 0x7, PseudoVSOXEI8_V_MF2_MF2 }, // 99 |
31867 | | { 0x0, 0x1, 0x4, 0x0, 0x0, PseudoVSOXEI16_V_M1_M1 }, // 100 |
31868 | | { 0x0, 0x1, 0x4, 0x0, 0x1, PseudoVSOXEI16_V_M2_M1 }, // 101 |
31869 | | { 0x0, 0x1, 0x4, 0x0, 0x6, PseudoVSOXEI16_V_MF4_M1 }, // 102 |
31870 | | { 0x0, 0x1, 0x4, 0x0, 0x7, PseudoVSOXEI16_V_MF2_M1 }, // 103 |
31871 | | { 0x0, 0x1, 0x4, 0x1, 0x0, PseudoVSOXEI16_V_M1_M2 }, // 104 |
31872 | | { 0x0, 0x1, 0x4, 0x1, 0x1, PseudoVSOXEI16_V_M2_M2 }, // 105 |
31873 | | { 0x0, 0x1, 0x4, 0x1, 0x2, PseudoVSOXEI16_V_M4_M2 }, // 106 |
31874 | | { 0x0, 0x1, 0x4, 0x1, 0x7, PseudoVSOXEI16_V_MF2_M2 }, // 107 |
31875 | | { 0x0, 0x1, 0x4, 0x2, 0x0, PseudoVSOXEI16_V_M1_M4 }, // 108 |
31876 | | { 0x0, 0x1, 0x4, 0x2, 0x1, PseudoVSOXEI16_V_M2_M4 }, // 109 |
31877 | | { 0x0, 0x1, 0x4, 0x2, 0x2, PseudoVSOXEI16_V_M4_M4 }, // 110 |
31878 | | { 0x0, 0x1, 0x4, 0x2, 0x3, PseudoVSOXEI16_V_M8_M4 }, // 111 |
31879 | | { 0x0, 0x1, 0x4, 0x3, 0x1, PseudoVSOXEI16_V_M2_M8 }, // 112 |
31880 | | { 0x0, 0x1, 0x4, 0x3, 0x2, PseudoVSOXEI16_V_M4_M8 }, // 113 |
31881 | | { 0x0, 0x1, 0x4, 0x3, 0x3, PseudoVSOXEI16_V_M8_M8 }, // 114 |
31882 | | { 0x0, 0x1, 0x4, 0x5, 0x6, PseudoVSOXEI16_V_MF4_MF8 }, // 115 |
31883 | | { 0x0, 0x1, 0x4, 0x6, 0x6, PseudoVSOXEI16_V_MF4_MF4 }, // 116 |
31884 | | { 0x0, 0x1, 0x4, 0x6, 0x7, PseudoVSOXEI16_V_MF2_MF4 }, // 117 |
31885 | | { 0x0, 0x1, 0x4, 0x7, 0x0, PseudoVSOXEI16_V_M1_MF2 }, // 118 |
31886 | | { 0x0, 0x1, 0x4, 0x7, 0x6, PseudoVSOXEI16_V_MF4_MF2 }, // 119 |
31887 | | { 0x0, 0x1, 0x4, 0x7, 0x7, PseudoVSOXEI16_V_MF2_MF2 }, // 120 |
31888 | | { 0x0, 0x1, 0x5, 0x0, 0x0, PseudoVSOXEI32_V_M1_M1 }, // 121 |
31889 | | { 0x0, 0x1, 0x5, 0x0, 0x1, PseudoVSOXEI32_V_M2_M1 }, // 122 |
31890 | | { 0x0, 0x1, 0x5, 0x0, 0x2, PseudoVSOXEI32_V_M4_M1 }, // 123 |
31891 | | { 0x0, 0x1, 0x5, 0x0, 0x7, PseudoVSOXEI32_V_MF2_M1 }, // 124 |
31892 | | { 0x0, 0x1, 0x5, 0x1, 0x0, PseudoVSOXEI32_V_M1_M2 }, // 125 |
31893 | | { 0x0, 0x1, 0x5, 0x1, 0x1, PseudoVSOXEI32_V_M2_M2 }, // 126 |
31894 | | { 0x0, 0x1, 0x5, 0x1, 0x2, PseudoVSOXEI32_V_M4_M2 }, // 127 |
31895 | | { 0x0, 0x1, 0x5, 0x1, 0x3, PseudoVSOXEI32_V_M8_M2 }, // 128 |
31896 | | { 0x0, 0x1, 0x5, 0x2, 0x1, PseudoVSOXEI32_V_M2_M4 }, // 129 |
31897 | | { 0x0, 0x1, 0x5, 0x2, 0x2, PseudoVSOXEI32_V_M4_M4 }, // 130 |
31898 | | { 0x0, 0x1, 0x5, 0x2, 0x3, PseudoVSOXEI32_V_M8_M4 }, // 131 |
31899 | | { 0x0, 0x1, 0x5, 0x3, 0x2, PseudoVSOXEI32_V_M4_M8 }, // 132 |
31900 | | { 0x0, 0x1, 0x5, 0x3, 0x3, PseudoVSOXEI32_V_M8_M8 }, // 133 |
31901 | | { 0x0, 0x1, 0x5, 0x5, 0x7, PseudoVSOXEI32_V_MF2_MF8 }, // 134 |
31902 | | { 0x0, 0x1, 0x5, 0x6, 0x0, PseudoVSOXEI32_V_M1_MF4 }, // 135 |
31903 | | { 0x0, 0x1, 0x5, 0x6, 0x7, PseudoVSOXEI32_V_MF2_MF4 }, // 136 |
31904 | | { 0x0, 0x1, 0x5, 0x7, 0x0, PseudoVSOXEI32_V_M1_MF2 }, // 137 |
31905 | | { 0x0, 0x1, 0x5, 0x7, 0x1, PseudoVSOXEI32_V_M2_MF2 }, // 138 |
31906 | | { 0x0, 0x1, 0x5, 0x7, 0x7, PseudoVSOXEI32_V_MF2_MF2 }, // 139 |
31907 | | { 0x0, 0x1, 0x6, 0x0, 0x0, PseudoVSOXEI64_V_M1_M1 }, // 140 |
31908 | | { 0x0, 0x1, 0x6, 0x0, 0x1, PseudoVSOXEI64_V_M2_M1 }, // 141 |
31909 | | { 0x0, 0x1, 0x6, 0x0, 0x2, PseudoVSOXEI64_V_M4_M1 }, // 142 |
31910 | | { 0x0, 0x1, 0x6, 0x0, 0x3, PseudoVSOXEI64_V_M8_M1 }, // 143 |
31911 | | { 0x0, 0x1, 0x6, 0x1, 0x1, PseudoVSOXEI64_V_M2_M2 }, // 144 |
31912 | | { 0x0, 0x1, 0x6, 0x1, 0x2, PseudoVSOXEI64_V_M4_M2 }, // 145 |
31913 | | { 0x0, 0x1, 0x6, 0x1, 0x3, PseudoVSOXEI64_V_M8_M2 }, // 146 |
31914 | | { 0x0, 0x1, 0x6, 0x2, 0x2, PseudoVSOXEI64_V_M4_M4 }, // 147 |
31915 | | { 0x0, 0x1, 0x6, 0x2, 0x3, PseudoVSOXEI64_V_M8_M4 }, // 148 |
31916 | | { 0x0, 0x1, 0x6, 0x3, 0x3, PseudoVSOXEI64_V_M8_M8 }, // 149 |
31917 | | { 0x0, 0x1, 0x6, 0x5, 0x0, PseudoVSOXEI64_V_M1_MF8 }, // 150 |
31918 | | { 0x0, 0x1, 0x6, 0x6, 0x0, PseudoVSOXEI64_V_M1_MF4 }, // 151 |
31919 | | { 0x0, 0x1, 0x6, 0x6, 0x1, PseudoVSOXEI64_V_M2_MF4 }, // 152 |
31920 | | { 0x0, 0x1, 0x6, 0x7, 0x0, PseudoVSOXEI64_V_M1_MF2 }, // 153 |
31921 | | { 0x0, 0x1, 0x6, 0x7, 0x1, PseudoVSOXEI64_V_M2_MF2 }, // 154 |
31922 | | { 0x0, 0x1, 0x6, 0x7, 0x2, PseudoVSOXEI64_V_M4_MF2 }, // 155 |
31923 | | { 0x1, 0x0, 0x3, 0x0, 0x0, PseudoVSUXEI8_V_M1_M1_MASK }, // 156 |
31924 | | { 0x1, 0x0, 0x3, 0x0, 0x5, PseudoVSUXEI8_V_MF8_M1_MASK }, // 157 |
31925 | | { 0x1, 0x0, 0x3, 0x0, 0x6, PseudoVSUXEI8_V_MF4_M1_MASK }, // 158 |
31926 | | { 0x1, 0x0, 0x3, 0x0, 0x7, PseudoVSUXEI8_V_MF2_M1_MASK }, // 159 |
31927 | | { 0x1, 0x0, 0x3, 0x1, 0x0, PseudoVSUXEI8_V_M1_M2_MASK }, // 160 |
31928 | | { 0x1, 0x0, 0x3, 0x1, 0x1, PseudoVSUXEI8_V_M2_M2_MASK }, // 161 |
31929 | | { 0x1, 0x0, 0x3, 0x1, 0x6, PseudoVSUXEI8_V_MF4_M2_MASK }, // 162 |
31930 | | { 0x1, 0x0, 0x3, 0x1, 0x7, PseudoVSUXEI8_V_MF2_M2_MASK }, // 163 |
31931 | | { 0x1, 0x0, 0x3, 0x2, 0x0, PseudoVSUXEI8_V_M1_M4_MASK }, // 164 |
31932 | | { 0x1, 0x0, 0x3, 0x2, 0x1, PseudoVSUXEI8_V_M2_M4_MASK }, // 165 |
31933 | | { 0x1, 0x0, 0x3, 0x2, 0x2, PseudoVSUXEI8_V_M4_M4_MASK }, // 166 |
31934 | | { 0x1, 0x0, 0x3, 0x2, 0x7, PseudoVSUXEI8_V_MF2_M4_MASK }, // 167 |
31935 | | { 0x1, 0x0, 0x3, 0x3, 0x0, PseudoVSUXEI8_V_M1_M8_MASK }, // 168 |
31936 | | { 0x1, 0x0, 0x3, 0x3, 0x1, PseudoVSUXEI8_V_M2_M8_MASK }, // 169 |
31937 | | { 0x1, 0x0, 0x3, 0x3, 0x2, PseudoVSUXEI8_V_M4_M8_MASK }, // 170 |
31938 | | { 0x1, 0x0, 0x3, 0x3, 0x3, PseudoVSUXEI8_V_M8_M8_MASK }, // 171 |
31939 | | { 0x1, 0x0, 0x3, 0x5, 0x5, PseudoVSUXEI8_V_MF8_MF8_MASK }, // 172 |
31940 | | { 0x1, 0x0, 0x3, 0x6, 0x5, PseudoVSUXEI8_V_MF8_MF4_MASK }, // 173 |
31941 | | { 0x1, 0x0, 0x3, 0x6, 0x6, PseudoVSUXEI8_V_MF4_MF4_MASK }, // 174 |
31942 | | { 0x1, 0x0, 0x3, 0x7, 0x5, PseudoVSUXEI8_V_MF8_MF2_MASK }, // 175 |
31943 | | { 0x1, 0x0, 0x3, 0x7, 0x6, PseudoVSUXEI8_V_MF4_MF2_MASK }, // 176 |
31944 | | { 0x1, 0x0, 0x3, 0x7, 0x7, PseudoVSUXEI8_V_MF2_MF2_MASK }, // 177 |
31945 | | { 0x1, 0x0, 0x4, 0x0, 0x0, PseudoVSUXEI16_V_M1_M1_MASK }, // 178 |
31946 | | { 0x1, 0x0, 0x4, 0x0, 0x1, PseudoVSUXEI16_V_M2_M1_MASK }, // 179 |
31947 | | { 0x1, 0x0, 0x4, 0x0, 0x6, PseudoVSUXEI16_V_MF4_M1_MASK }, // 180 |
31948 | | { 0x1, 0x0, 0x4, 0x0, 0x7, PseudoVSUXEI16_V_MF2_M1_MASK }, // 181 |
31949 | | { 0x1, 0x0, 0x4, 0x1, 0x0, PseudoVSUXEI16_V_M1_M2_MASK }, // 182 |
31950 | | { 0x1, 0x0, 0x4, 0x1, 0x1, PseudoVSUXEI16_V_M2_M2_MASK }, // 183 |
31951 | | { 0x1, 0x0, 0x4, 0x1, 0x2, PseudoVSUXEI16_V_M4_M2_MASK }, // 184 |
31952 | | { 0x1, 0x0, 0x4, 0x1, 0x7, PseudoVSUXEI16_V_MF2_M2_MASK }, // 185 |
31953 | | { 0x1, 0x0, 0x4, 0x2, 0x0, PseudoVSUXEI16_V_M1_M4_MASK }, // 186 |
31954 | | { 0x1, 0x0, 0x4, 0x2, 0x1, PseudoVSUXEI16_V_M2_M4_MASK }, // 187 |
31955 | | { 0x1, 0x0, 0x4, 0x2, 0x2, PseudoVSUXEI16_V_M4_M4_MASK }, // 188 |
31956 | | { 0x1, 0x0, 0x4, 0x2, 0x3, PseudoVSUXEI16_V_M8_M4_MASK }, // 189 |
31957 | | { 0x1, 0x0, 0x4, 0x3, 0x1, PseudoVSUXEI16_V_M2_M8_MASK }, // 190 |
31958 | | { 0x1, 0x0, 0x4, 0x3, 0x2, PseudoVSUXEI16_V_M4_M8_MASK }, // 191 |
31959 | | { 0x1, 0x0, 0x4, 0x3, 0x3, PseudoVSUXEI16_V_M8_M8_MASK }, // 192 |
31960 | | { 0x1, 0x0, 0x4, 0x5, 0x6, PseudoVSUXEI16_V_MF4_MF8_MASK }, // 193 |
31961 | | { 0x1, 0x0, 0x4, 0x6, 0x6, PseudoVSUXEI16_V_MF4_MF4_MASK }, // 194 |
31962 | | { 0x1, 0x0, 0x4, 0x6, 0x7, PseudoVSUXEI16_V_MF2_MF4_MASK }, // 195 |
31963 | | { 0x1, 0x0, 0x4, 0x7, 0x0, PseudoVSUXEI16_V_M1_MF2_MASK }, // 196 |
31964 | | { 0x1, 0x0, 0x4, 0x7, 0x6, PseudoVSUXEI16_V_MF4_MF2_MASK }, // 197 |
31965 | | { 0x1, 0x0, 0x4, 0x7, 0x7, PseudoVSUXEI16_V_MF2_MF2_MASK }, // 198 |
31966 | | { 0x1, 0x0, 0x5, 0x0, 0x0, PseudoVSUXEI32_V_M1_M1_MASK }, // 199 |
31967 | | { 0x1, 0x0, 0x5, 0x0, 0x1, PseudoVSUXEI32_V_M2_M1_MASK }, // 200 |
31968 | | { 0x1, 0x0, 0x5, 0x0, 0x2, PseudoVSUXEI32_V_M4_M1_MASK }, // 201 |
31969 | | { 0x1, 0x0, 0x5, 0x0, 0x7, PseudoVSUXEI32_V_MF2_M1_MASK }, // 202 |
31970 | | { 0x1, 0x0, 0x5, 0x1, 0x0, PseudoVSUXEI32_V_M1_M2_MASK }, // 203 |
31971 | | { 0x1, 0x0, 0x5, 0x1, 0x1, PseudoVSUXEI32_V_M2_M2_MASK }, // 204 |
31972 | | { 0x1, 0x0, 0x5, 0x1, 0x2, PseudoVSUXEI32_V_M4_M2_MASK }, // 205 |
31973 | | { 0x1, 0x0, 0x5, 0x1, 0x3, PseudoVSUXEI32_V_M8_M2_MASK }, // 206 |
31974 | | { 0x1, 0x0, 0x5, 0x2, 0x1, PseudoVSUXEI32_V_M2_M4_MASK }, // 207 |
31975 | | { 0x1, 0x0, 0x5, 0x2, 0x2, PseudoVSUXEI32_V_M4_M4_MASK }, // 208 |
31976 | | { 0x1, 0x0, 0x5, 0x2, 0x3, PseudoVSUXEI32_V_M8_M4_MASK }, // 209 |
31977 | | { 0x1, 0x0, 0x5, 0x3, 0x2, PseudoVSUXEI32_V_M4_M8_MASK }, // 210 |
31978 | | { 0x1, 0x0, 0x5, 0x3, 0x3, PseudoVSUXEI32_V_M8_M8_MASK }, // 211 |
31979 | | { 0x1, 0x0, 0x5, 0x5, 0x7, PseudoVSUXEI32_V_MF2_MF8_MASK }, // 212 |
31980 | | { 0x1, 0x0, 0x5, 0x6, 0x0, PseudoVSUXEI32_V_M1_MF4_MASK }, // 213 |
31981 | | { 0x1, 0x0, 0x5, 0x6, 0x7, PseudoVSUXEI32_V_MF2_MF4_MASK }, // 214 |
31982 | | { 0x1, 0x0, 0x5, 0x7, 0x0, PseudoVSUXEI32_V_M1_MF2_MASK }, // 215 |
31983 | | { 0x1, 0x0, 0x5, 0x7, 0x1, PseudoVSUXEI32_V_M2_MF2_MASK }, // 216 |
31984 | | { 0x1, 0x0, 0x5, 0x7, 0x7, PseudoVSUXEI32_V_MF2_MF2_MASK }, // 217 |
31985 | | { 0x1, 0x0, 0x6, 0x0, 0x0, PseudoVSUXEI64_V_M1_M1_MASK }, // 218 |
31986 | | { 0x1, 0x0, 0x6, 0x0, 0x1, PseudoVSUXEI64_V_M2_M1_MASK }, // 219 |
31987 | | { 0x1, 0x0, 0x6, 0x0, 0x2, PseudoVSUXEI64_V_M4_M1_MASK }, // 220 |
31988 | | { 0x1, 0x0, 0x6, 0x0, 0x3, PseudoVSUXEI64_V_M8_M1_MASK }, // 221 |
31989 | | { 0x1, 0x0, 0x6, 0x1, 0x1, PseudoVSUXEI64_V_M2_M2_MASK }, // 222 |
31990 | | { 0x1, 0x0, 0x6, 0x1, 0x2, PseudoVSUXEI64_V_M4_M2_MASK }, // 223 |
31991 | | { 0x1, 0x0, 0x6, 0x1, 0x3, PseudoVSUXEI64_V_M8_M2_MASK }, // 224 |
31992 | | { 0x1, 0x0, 0x6, 0x2, 0x2, PseudoVSUXEI64_V_M4_M4_MASK }, // 225 |
31993 | | { 0x1, 0x0, 0x6, 0x2, 0x3, PseudoVSUXEI64_V_M8_M4_MASK }, // 226 |
31994 | | { 0x1, 0x0, 0x6, 0x3, 0x3, PseudoVSUXEI64_V_M8_M8_MASK }, // 227 |
31995 | | { 0x1, 0x0, 0x6, 0x5, 0x0, PseudoVSUXEI64_V_M1_MF8_MASK }, // 228 |
31996 | | { 0x1, 0x0, 0x6, 0x6, 0x0, PseudoVSUXEI64_V_M1_MF4_MASK }, // 229 |
31997 | | { 0x1, 0x0, 0x6, 0x6, 0x1, PseudoVSUXEI64_V_M2_MF4_MASK }, // 230 |
31998 | | { 0x1, 0x0, 0x6, 0x7, 0x0, PseudoVSUXEI64_V_M1_MF2_MASK }, // 231 |
31999 | | { 0x1, 0x0, 0x6, 0x7, 0x1, PseudoVSUXEI64_V_M2_MF2_MASK }, // 232 |
32000 | | { 0x1, 0x0, 0x6, 0x7, 0x2, PseudoVSUXEI64_V_M4_MF2_MASK }, // 233 |
32001 | | { 0x1, 0x1, 0x3, 0x0, 0x0, PseudoVSOXEI8_V_M1_M1_MASK }, // 234 |
32002 | | { 0x1, 0x1, 0x3, 0x0, 0x5, PseudoVSOXEI8_V_MF8_M1_MASK }, // 235 |
32003 | | { 0x1, 0x1, 0x3, 0x0, 0x6, PseudoVSOXEI8_V_MF4_M1_MASK }, // 236 |
32004 | | { 0x1, 0x1, 0x3, 0x0, 0x7, PseudoVSOXEI8_V_MF2_M1_MASK }, // 237 |
32005 | | { 0x1, 0x1, 0x3, 0x1, 0x0, PseudoVSOXEI8_V_M1_M2_MASK }, // 238 |
32006 | | { 0x1, 0x1, 0x3, 0x1, 0x1, PseudoVSOXEI8_V_M2_M2_MASK }, // 239 |
32007 | | { 0x1, 0x1, 0x3, 0x1, 0x6, PseudoVSOXEI8_V_MF4_M2_MASK }, // 240 |
32008 | | { 0x1, 0x1, 0x3, 0x1, 0x7, PseudoVSOXEI8_V_MF2_M2_MASK }, // 241 |
32009 | | { 0x1, 0x1, 0x3, 0x2, 0x0, PseudoVSOXEI8_V_M1_M4_MASK }, // 242 |
32010 | | { 0x1, 0x1, 0x3, 0x2, 0x1, PseudoVSOXEI8_V_M2_M4_MASK }, // 243 |
32011 | | { 0x1, 0x1, 0x3, 0x2, 0x2, PseudoVSOXEI8_V_M4_M4_MASK }, // 244 |
32012 | | { 0x1, 0x1, 0x3, 0x2, 0x7, PseudoVSOXEI8_V_MF2_M4_MASK }, // 245 |
32013 | | { 0x1, 0x1, 0x3, 0x3, 0x0, PseudoVSOXEI8_V_M1_M8_MASK }, // 246 |
32014 | | { 0x1, 0x1, 0x3, 0x3, 0x1, PseudoVSOXEI8_V_M2_M8_MASK }, // 247 |
32015 | | { 0x1, 0x1, 0x3, 0x3, 0x2, PseudoVSOXEI8_V_M4_M8_MASK }, // 248 |
32016 | | { 0x1, 0x1, 0x3, 0x3, 0x3, PseudoVSOXEI8_V_M8_M8_MASK }, // 249 |
32017 | | { 0x1, 0x1, 0x3, 0x5, 0x5, PseudoVSOXEI8_V_MF8_MF8_MASK }, // 250 |
32018 | | { 0x1, 0x1, 0x3, 0x6, 0x5, PseudoVSOXEI8_V_MF8_MF4_MASK }, // 251 |
32019 | | { 0x1, 0x1, 0x3, 0x6, 0x6, PseudoVSOXEI8_V_MF4_MF4_MASK }, // 252 |
32020 | | { 0x1, 0x1, 0x3, 0x7, 0x5, PseudoVSOXEI8_V_MF8_MF2_MASK }, // 253 |
32021 | | { 0x1, 0x1, 0x3, 0x7, 0x6, PseudoVSOXEI8_V_MF4_MF2_MASK }, // 254 |
32022 | | { 0x1, 0x1, 0x3, 0x7, 0x7, PseudoVSOXEI8_V_MF2_MF2_MASK }, // 255 |
32023 | | { 0x1, 0x1, 0x4, 0x0, 0x0, PseudoVSOXEI16_V_M1_M1_MASK }, // 256 |
32024 | | { 0x1, 0x1, 0x4, 0x0, 0x1, PseudoVSOXEI16_V_M2_M1_MASK }, // 257 |
32025 | | { 0x1, 0x1, 0x4, 0x0, 0x6, PseudoVSOXEI16_V_MF4_M1_MASK }, // 258 |
32026 | | { 0x1, 0x1, 0x4, 0x0, 0x7, PseudoVSOXEI16_V_MF2_M1_MASK }, // 259 |
32027 | | { 0x1, 0x1, 0x4, 0x1, 0x0, PseudoVSOXEI16_V_M1_M2_MASK }, // 260 |
32028 | | { 0x1, 0x1, 0x4, 0x1, 0x1, PseudoVSOXEI16_V_M2_M2_MASK }, // 261 |
32029 | | { 0x1, 0x1, 0x4, 0x1, 0x2, PseudoVSOXEI16_V_M4_M2_MASK }, // 262 |
32030 | | { 0x1, 0x1, 0x4, 0x1, 0x7, PseudoVSOXEI16_V_MF2_M2_MASK }, // 263 |
32031 | | { 0x1, 0x1, 0x4, 0x2, 0x0, PseudoVSOXEI16_V_M1_M4_MASK }, // 264 |
32032 | | { 0x1, 0x1, 0x4, 0x2, 0x1, PseudoVSOXEI16_V_M2_M4_MASK }, // 265 |
32033 | | { 0x1, 0x1, 0x4, 0x2, 0x2, PseudoVSOXEI16_V_M4_M4_MASK }, // 266 |
32034 | | { 0x1, 0x1, 0x4, 0x2, 0x3, PseudoVSOXEI16_V_M8_M4_MASK }, // 267 |
32035 | | { 0x1, 0x1, 0x4, 0x3, 0x1, PseudoVSOXEI16_V_M2_M8_MASK }, // 268 |
32036 | | { 0x1, 0x1, 0x4, 0x3, 0x2, PseudoVSOXEI16_V_M4_M8_MASK }, // 269 |
32037 | | { 0x1, 0x1, 0x4, 0x3, 0x3, PseudoVSOXEI16_V_M8_M8_MASK }, // 270 |
32038 | | { 0x1, 0x1, 0x4, 0x5, 0x6, PseudoVSOXEI16_V_MF4_MF8_MASK }, // 271 |
32039 | | { 0x1, 0x1, 0x4, 0x6, 0x6, PseudoVSOXEI16_V_MF4_MF4_MASK }, // 272 |
32040 | | { 0x1, 0x1, 0x4, 0x6, 0x7, PseudoVSOXEI16_V_MF2_MF4_MASK }, // 273 |
32041 | | { 0x1, 0x1, 0x4, 0x7, 0x0, PseudoVSOXEI16_V_M1_MF2_MASK }, // 274 |
32042 | | { 0x1, 0x1, 0x4, 0x7, 0x6, PseudoVSOXEI16_V_MF4_MF2_MASK }, // 275 |
32043 | | { 0x1, 0x1, 0x4, 0x7, 0x7, PseudoVSOXEI16_V_MF2_MF2_MASK }, // 276 |
32044 | | { 0x1, 0x1, 0x5, 0x0, 0x0, PseudoVSOXEI32_V_M1_M1_MASK }, // 277 |
32045 | | { 0x1, 0x1, 0x5, 0x0, 0x1, PseudoVSOXEI32_V_M2_M1_MASK }, // 278 |
32046 | | { 0x1, 0x1, 0x5, 0x0, 0x2, PseudoVSOXEI32_V_M4_M1_MASK }, // 279 |
32047 | | { 0x1, 0x1, 0x5, 0x0, 0x7, PseudoVSOXEI32_V_MF2_M1_MASK }, // 280 |
32048 | | { 0x1, 0x1, 0x5, 0x1, 0x0, PseudoVSOXEI32_V_M1_M2_MASK }, // 281 |
32049 | | { 0x1, 0x1, 0x5, 0x1, 0x1, PseudoVSOXEI32_V_M2_M2_MASK }, // 282 |
32050 | | { 0x1, 0x1, 0x5, 0x1, 0x2, PseudoVSOXEI32_V_M4_M2_MASK }, // 283 |
32051 | | { 0x1, 0x1, 0x5, 0x1, 0x3, PseudoVSOXEI32_V_M8_M2_MASK }, // 284 |
32052 | | { 0x1, 0x1, 0x5, 0x2, 0x1, PseudoVSOXEI32_V_M2_M4_MASK }, // 285 |
32053 | | { 0x1, 0x1, 0x5, 0x2, 0x2, PseudoVSOXEI32_V_M4_M4_MASK }, // 286 |
32054 | | { 0x1, 0x1, 0x5, 0x2, 0x3, PseudoVSOXEI32_V_M8_M4_MASK }, // 287 |
32055 | | { 0x1, 0x1, 0x5, 0x3, 0x2, PseudoVSOXEI32_V_M4_M8_MASK }, // 288 |
32056 | | { 0x1, 0x1, 0x5, 0x3, 0x3, PseudoVSOXEI32_V_M8_M8_MASK }, // 289 |
32057 | | { 0x1, 0x1, 0x5, 0x5, 0x7, PseudoVSOXEI32_V_MF2_MF8_MASK }, // 290 |
32058 | | { 0x1, 0x1, 0x5, 0x6, 0x0, PseudoVSOXEI32_V_M1_MF4_MASK }, // 291 |
32059 | | { 0x1, 0x1, 0x5, 0x6, 0x7, PseudoVSOXEI32_V_MF2_MF4_MASK }, // 292 |
32060 | | { 0x1, 0x1, 0x5, 0x7, 0x0, PseudoVSOXEI32_V_M1_MF2_MASK }, // 293 |
32061 | | { 0x1, 0x1, 0x5, 0x7, 0x1, PseudoVSOXEI32_V_M2_MF2_MASK }, // 294 |
32062 | | { 0x1, 0x1, 0x5, 0x7, 0x7, PseudoVSOXEI32_V_MF2_MF2_MASK }, // 295 |
32063 | | { 0x1, 0x1, 0x6, 0x0, 0x0, PseudoVSOXEI64_V_M1_M1_MASK }, // 296 |
32064 | | { 0x1, 0x1, 0x6, 0x0, 0x1, PseudoVSOXEI64_V_M2_M1_MASK }, // 297 |
32065 | | { 0x1, 0x1, 0x6, 0x0, 0x2, PseudoVSOXEI64_V_M4_M1_MASK }, // 298 |
32066 | | { 0x1, 0x1, 0x6, 0x0, 0x3, PseudoVSOXEI64_V_M8_M1_MASK }, // 299 |
32067 | | { 0x1, 0x1, 0x6, 0x1, 0x1, PseudoVSOXEI64_V_M2_M2_MASK }, // 300 |
32068 | | { 0x1, 0x1, 0x6, 0x1, 0x2, PseudoVSOXEI64_V_M4_M2_MASK }, // 301 |
32069 | | { 0x1, 0x1, 0x6, 0x1, 0x3, PseudoVSOXEI64_V_M8_M2_MASK }, // 302 |
32070 | | { 0x1, 0x1, 0x6, 0x2, 0x2, PseudoVSOXEI64_V_M4_M4_MASK }, // 303 |
32071 | | { 0x1, 0x1, 0x6, 0x2, 0x3, PseudoVSOXEI64_V_M8_M4_MASK }, // 304 |
32072 | | { 0x1, 0x1, 0x6, 0x3, 0x3, PseudoVSOXEI64_V_M8_M8_MASK }, // 305 |
32073 | | { 0x1, 0x1, 0x6, 0x5, 0x0, PseudoVSOXEI64_V_M1_MF8_MASK }, // 306 |
32074 | | { 0x1, 0x1, 0x6, 0x6, 0x0, PseudoVSOXEI64_V_M1_MF4_MASK }, // 307 |
32075 | | { 0x1, 0x1, 0x6, 0x6, 0x1, PseudoVSOXEI64_V_M2_MF4_MASK }, // 308 |
32076 | | { 0x1, 0x1, 0x6, 0x7, 0x0, PseudoVSOXEI64_V_M1_MF2_MASK }, // 309 |
32077 | | { 0x1, 0x1, 0x6, 0x7, 0x1, PseudoVSOXEI64_V_M2_MF2_MASK }, // 310 |
32078 | | { 0x1, 0x1, 0x6, 0x7, 0x2, PseudoVSOXEI64_V_M4_MF2_MASK }, // 311 |
32079 | | }; |
32080 | | |
32081 | | const RISCV_VLX_VSXPseudo *RISCV_getVSXPseudo(uint8_t Masked, uint8_t Ordered, uint8_t Log2SEW, uint8_t LMUL, uint8_t IndexLMUL) { |
32082 | | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), MaskedOrderedLog2SEWLMULIndexLMUL); |
32083 | | if (i == -1) |
32084 | | return NULL; |
32085 | | else |
32086 | | return &RISCVVSXTable[Index[i].index]; |
32087 | | } |
32088 | | |
32089 | | #endif |
32090 | | |
32091 | | #ifdef GET_SysRegsList_IMPL |
32092 | | static const RISCV_SysReg SysRegsList[] = { |
32093 | | { "fflags", { .raw_val = RISCV_SYSREG_FFLAGS }, "fflags", { .raw_val = RISCV_SYSREG_FFLAGS }, "", 0x1, {0} , false }, // 0 |
32094 | | { "frm", { .raw_val = RISCV_SYSREG_FRM }, "frm", { .raw_val = RISCV_SYSREG_FRM }, "", 0x2, {0} , false }, // 1 |
32095 | | { "fcsr", { .raw_val = RISCV_SYSREG_FCSR }, "fcsr", { .raw_val = RISCV_SYSREG_FCSR }, "", 0x3, {0} , false }, // 2 |
32096 | | { "vstart", { .raw_val = RISCV_SYSREG_VSTART }, "vstart", { .raw_val = RISCV_SYSREG_VSTART }, "", 0x8, {0} , false }, // 3 |
32097 | | { "vxsat", { .raw_val = RISCV_SYSREG_VXSAT }, "vxsat", { .raw_val = RISCV_SYSREG_VXSAT }, "", 0x9, {0} , false }, // 4 |
32098 | | { "vxrm", { .raw_val = RISCV_SYSREG_VXRM }, "vxrm", { .raw_val = RISCV_SYSREG_VXRM }, "", 0xA, {0} , false }, // 5 |
32099 | | { "vcsr", { .raw_val = RISCV_SYSREG_VCSR }, "vcsr", { .raw_val = RISCV_SYSREG_VCSR }, "", 0xF, {0} , false }, // 6 |
32100 | | { "seed", { .raw_val = RISCV_SYSREG_SEED }, "seed", { .raw_val = RISCV_SYSREG_SEED }, "", 0x15, {0} , false }, // 7 |
32101 | | { "jvt", { .raw_val = RISCV_SYSREG_JVT }, "jvt", { .raw_val = RISCV_SYSREG_JVT }, "", 0x17, {0} , false }, // 8 |
32102 | | { "sstatus", { .raw_val = RISCV_SYSREG_SSTATUS }, "sstatus", { .raw_val = RISCV_SYSREG_SSTATUS }, "", 0x100, {0} , false }, // 9 |
32103 | | { "sie", { .raw_val = RISCV_SYSREG_SIE }, "sie", { .raw_val = RISCV_SYSREG_SIE }, "", 0x104, {0} , false }, // 10 |
32104 | | { "stvec", { .raw_val = RISCV_SYSREG_STVEC }, "stvec", { .raw_val = RISCV_SYSREG_STVEC }, "", 0x105, {0} , false }, // 11 |
32105 | | { "scounteren", { .raw_val = RISCV_SYSREG_SCOUNTEREN }, "scounteren", { .raw_val = RISCV_SYSREG_SCOUNTEREN }, "", 0x106, {0} , false }, // 12 |
32106 | | { "senvcfg", { .raw_val = RISCV_SYSREG_SENVCFG }, "senvcfg", { .raw_val = RISCV_SYSREG_SENVCFG }, "", 0x10A, {0} , false }, // 13 |
32107 | | { "sstateen0", { .raw_val = RISCV_SYSREG_SSTATEEN0 }, "sstateen0", { .raw_val = RISCV_SYSREG_SSTATEEN0 }, "", 0x10C, {0} , false }, // 14 |
32108 | | { "sstateen1", { .raw_val = RISCV_SYSREG_SSTATEEN1 }, "sstateen1", { .raw_val = RISCV_SYSREG_SSTATEEN1 }, "", 0x10D, {0} , false }, // 15 |
32109 | | { "sstateen2", { .raw_val = RISCV_SYSREG_SSTATEEN2 }, "sstateen2", { .raw_val = RISCV_SYSREG_SSTATEEN2 }, "", 0x10E, {0} , false }, // 16 |
32110 | | { "sstateen3", { .raw_val = RISCV_SYSREG_SSTATEEN3 }, "sstateen3", { .raw_val = RISCV_SYSREG_SSTATEEN3 }, "", 0x10F, {0} , false }, // 17 |
32111 | | { "sieh", { .raw_val = RISCV_SYSREG_SIEH }, "sieh", { .raw_val = RISCV_SYSREG_SIEH }, "", 0x114, {0} , true }, // 18 |
32112 | | { "sscratch", { .raw_val = RISCV_SYSREG_SSCRATCH }, "sscratch", { .raw_val = RISCV_SYSREG_SSCRATCH }, "", 0x140, {0} , false }, // 19 |
32113 | | { "sepc", { .raw_val = RISCV_SYSREG_SEPC }, "sepc", { .raw_val = RISCV_SYSREG_SEPC }, "", 0x141, {0} , false }, // 20 |
32114 | | { "scause", { .raw_val = RISCV_SYSREG_SCAUSE }, "scause", { .raw_val = RISCV_SYSREG_SCAUSE }, "", 0x142, {0} , false }, // 21 |
32115 | | { "stval", { .raw_val = RISCV_SYSREG_STVAL }, "stval", { .raw_val = RISCV_SYSREG_STVAL }, "sbadaddr", 0x143, {0} , false }, // 22 |
32116 | | { "sip", { .raw_val = RISCV_SYSREG_SIP }, "sip", { .raw_val = RISCV_SYSREG_SIP }, "", 0x144, {0} , false }, // 23 |
32117 | | { "stimecmp", { .raw_val = RISCV_SYSREG_STIMECMP }, "stimecmp", { .raw_val = RISCV_SYSREG_STIMECMP }, "", 0x14D, {0} , false }, // 24 |
32118 | | { "siselect", { .raw_val = RISCV_SYSREG_SISELECT }, "siselect", { .raw_val = RISCV_SYSREG_SISELECT }, "", 0x150, {0} , false }, // 25 |
32119 | | { "sireg", { .raw_val = RISCV_SYSREG_SIREG }, "sireg", { .raw_val = RISCV_SYSREG_SIREG }, "", 0x151, {0} , false }, // 26 |
32120 | | { "siph", { .raw_val = RISCV_SYSREG_SIPH }, "siph", { .raw_val = RISCV_SYSREG_SIPH }, "", 0x154, {0} , true }, // 27 |
32121 | | { "stopei", { .raw_val = RISCV_SYSREG_STOPEI }, "stopei", { .raw_val = RISCV_SYSREG_STOPEI }, "", 0x15C, {0} , false }, // 28 |
32122 | | { "stimecmph", { .raw_val = RISCV_SYSREG_STIMECMPH }, "stimecmph", { .raw_val = RISCV_SYSREG_STIMECMPH }, "", 0x15D, {0} , true }, // 29 |
32123 | | { "satp", { .raw_val = RISCV_SYSREG_SATP }, "satp", { .raw_val = RISCV_SYSREG_SATP }, "sptbr", 0x180, {0} , false }, // 30 |
32124 | | { "vsstatus", { .raw_val = RISCV_SYSREG_VSSTATUS }, "vsstatus", { .raw_val = RISCV_SYSREG_VSSTATUS }, "", 0x200, {0} , false }, // 31 |
32125 | | { "vsie", { .raw_val = RISCV_SYSREG_VSIE }, "vsie", { .raw_val = RISCV_SYSREG_VSIE }, "", 0x204, {0} , false }, // 32 |
32126 | | { "vstvec", { .raw_val = RISCV_SYSREG_VSTVEC }, "vstvec", { .raw_val = RISCV_SYSREG_VSTVEC }, "", 0x205, {0} , false }, // 33 |
32127 | | { "vsieh", { .raw_val = RISCV_SYSREG_VSIEH }, "vsieh", { .raw_val = RISCV_SYSREG_VSIEH }, "", 0x214, {0} , true }, // 34 |
32128 | | { "vsscratch", { .raw_val = RISCV_SYSREG_VSSCRATCH }, "vsscratch", { .raw_val = RISCV_SYSREG_VSSCRATCH }, "", 0x240, {0} , false }, // 35 |
32129 | | { "vsepc", { .raw_val = RISCV_SYSREG_VSEPC }, "vsepc", { .raw_val = RISCV_SYSREG_VSEPC }, "", 0x241, {0} , false }, // 36 |
32130 | | { "vscause", { .raw_val = RISCV_SYSREG_VSCAUSE }, "vscause", { .raw_val = RISCV_SYSREG_VSCAUSE }, "", 0x242, {0} , false }, // 37 |
32131 | | { "vstval", { .raw_val = RISCV_SYSREG_VSTVAL }, "vstval", { .raw_val = RISCV_SYSREG_VSTVAL }, "", 0x243, {0} , false }, // 38 |
32132 | | { "vsip", { .raw_val = RISCV_SYSREG_VSIP }, "vsip", { .raw_val = RISCV_SYSREG_VSIP }, "", 0x244, {0} , false }, // 39 |
32133 | | { "vstimecmp", { .raw_val = RISCV_SYSREG_VSTIMECMP }, "vstimecmp", { .raw_val = RISCV_SYSREG_VSTIMECMP }, "", 0x24D, {0} , false }, // 40 |
32134 | | { "vsiselect", { .raw_val = RISCV_SYSREG_VSISELECT }, "vsiselect", { .raw_val = RISCV_SYSREG_VSISELECT }, "", 0x250, {0} , false }, // 41 |
32135 | | { "vsireg", { .raw_val = RISCV_SYSREG_VSIREG }, "vsireg", { .raw_val = RISCV_SYSREG_VSIREG }, "", 0x251, {0} , false }, // 42 |
32136 | | { "vsiph", { .raw_val = RISCV_SYSREG_VSIPH }, "vsiph", { .raw_val = RISCV_SYSREG_VSIPH }, "", 0x254, {0} , true }, // 43 |
32137 | | { "vstopei", { .raw_val = RISCV_SYSREG_VSTOPEI }, "vstopei", { .raw_val = RISCV_SYSREG_VSTOPEI }, "", 0x25C, {0} , false }, // 44 |
32138 | | { "vstimecmph", { .raw_val = RISCV_SYSREG_VSTIMECMPH }, "vstimecmph", { .raw_val = RISCV_SYSREG_VSTIMECMPH }, "", 0x25D, {0} , true }, // 45 |
32139 | | { "vsatp", { .raw_val = RISCV_SYSREG_VSATP }, "vsatp", { .raw_val = RISCV_SYSREG_VSATP }, "", 0x280, {0} , false }, // 46 |
32140 | | { "mstatus", { .raw_val = RISCV_SYSREG_MSTATUS }, "mstatus", { .raw_val = RISCV_SYSREG_MSTATUS }, "", 0x300, {0} , false }, // 47 |
32141 | | { "misa", { .raw_val = RISCV_SYSREG_MISA }, "misa", { .raw_val = RISCV_SYSREG_MISA }, "", 0x301, {0} , false }, // 48 |
32142 | | { "medeleg", { .raw_val = RISCV_SYSREG_MEDELEG }, "medeleg", { .raw_val = RISCV_SYSREG_MEDELEG }, "", 0x302, {0} , false }, // 49 |
32143 | | { "mideleg", { .raw_val = RISCV_SYSREG_MIDELEG }, "mideleg", { .raw_val = RISCV_SYSREG_MIDELEG }, "", 0x303, {0} , false }, // 50 |
32144 | | { "mie", { .raw_val = RISCV_SYSREG_MIE }, "mie", { .raw_val = RISCV_SYSREG_MIE }, "", 0x304, {0} , false }, // 51 |
32145 | | { "mtvec", { .raw_val = RISCV_SYSREG_MTVEC }, "mtvec", { .raw_val = RISCV_SYSREG_MTVEC }, "", 0x305, {0} , false }, // 52 |
32146 | | { "mcounteren", { .raw_val = RISCV_SYSREG_MCOUNTEREN }, "mcounteren", { .raw_val = RISCV_SYSREG_MCOUNTEREN }, "", 0x306, {0} , false }, // 53 |
32147 | | { "mvien", { .raw_val = RISCV_SYSREG_MVIEN }, "mvien", { .raw_val = RISCV_SYSREG_MVIEN }, "", 0x308, {0} , false }, // 54 |
32148 | | { "mvip", { .raw_val = RISCV_SYSREG_MVIP }, "mvip", { .raw_val = RISCV_SYSREG_MVIP }, "", 0x309, {0} , false }, // 55 |
32149 | | { "menvcfg", { .raw_val = RISCV_SYSREG_MENVCFG }, "menvcfg", { .raw_val = RISCV_SYSREG_MENVCFG }, "", 0x30A, {0} , false }, // 56 |
32150 | | { "mstateen0", { .raw_val = RISCV_SYSREG_MSTATEEN0 }, "mstateen0", { .raw_val = RISCV_SYSREG_MSTATEEN0 }, "", 0x30C, {0} , false }, // 57 |
32151 | | { "mstateen1", { .raw_val = RISCV_SYSREG_MSTATEEN1 }, "mstateen1", { .raw_val = RISCV_SYSREG_MSTATEEN1 }, "", 0x30D, {0} , false }, // 58 |
32152 | | { "mstateen2", { .raw_val = RISCV_SYSREG_MSTATEEN2 }, "mstateen2", { .raw_val = RISCV_SYSREG_MSTATEEN2 }, "", 0x30E, {0} , false }, // 59 |
32153 | | { "mstateen3", { .raw_val = RISCV_SYSREG_MSTATEEN3 }, "mstateen3", { .raw_val = RISCV_SYSREG_MSTATEEN3 }, "", 0x30F, {0} , false }, // 60 |
32154 | | { "mstatush", { .raw_val = RISCV_SYSREG_MSTATUSH }, "mstatush", { .raw_val = RISCV_SYSREG_MSTATUSH }, "", 0x310, {0} , true }, // 61 |
32155 | | { "midelegh", { .raw_val = RISCV_SYSREG_MIDELEGH }, "midelegh", { .raw_val = RISCV_SYSREG_MIDELEGH }, "", 0x313, {0} , true }, // 62 |
32156 | | { "mieh", { .raw_val = RISCV_SYSREG_MIEH }, "mieh", { .raw_val = RISCV_SYSREG_MIEH }, "", 0x314, {0} , true }, // 63 |
32157 | | { "mvienh", { .raw_val = RISCV_SYSREG_MVIENH }, "mvienh", { .raw_val = RISCV_SYSREG_MVIENH }, "", 0x318, {0} , true }, // 64 |
32158 | | { "mviph", { .raw_val = RISCV_SYSREG_MVIPH }, "mviph", { .raw_val = RISCV_SYSREG_MVIPH }, "", 0x319, {0} , true }, // 65 |
32159 | | { "menvcfgh", { .raw_val = RISCV_SYSREG_MENVCFGH }, "menvcfgh", { .raw_val = RISCV_SYSREG_MENVCFGH }, "", 0x31A, {0} , true }, // 66 |
32160 | | { "mstateen0h", { .raw_val = RISCV_SYSREG_MSTATEEN0H }, "mstateen0h", { .raw_val = RISCV_SYSREG_MSTATEEN0H }, "", 0x31C, {0} , true }, // 67 |
32161 | | { "mstateen1h", { .raw_val = RISCV_SYSREG_MSTATEEN1H }, "mstateen1h", { .raw_val = RISCV_SYSREG_MSTATEEN1H }, "", 0x31D, {0} , true }, // 68 |
32162 | | { "mstateen2h", { .raw_val = RISCV_SYSREG_MSTATEEN2H }, "mstateen2h", { .raw_val = RISCV_SYSREG_MSTATEEN2H }, "", 0x31E, {0} , true }, // 69 |
32163 | | { "mstateen3h", { .raw_val = RISCV_SYSREG_MSTATEEN3H }, "mstateen3h", { .raw_val = RISCV_SYSREG_MSTATEEN3H }, "", 0x31F, {0} , true }, // 70 |
32164 | | { "mcountinhibit", { .raw_val = RISCV_SYSREG_MCOUNTINHIBIT }, "mucounteren", { .raw_val = RISCV_SYSREG_MUCOUNTEREN }, "", 0x320, {0} , false }, // 71 |
32165 | | { "mhpmevent3", { .raw_val = RISCV_SYSREG_MHPMEVENT3 }, "mhpmevent3", { .raw_val = RISCV_SYSREG_MHPMEVENT3 }, "", 0x323, {0} , false }, // 72 |
32166 | | { "mhpmevent4", { .raw_val = RISCV_SYSREG_MHPMEVENT4 }, "mhpmevent4", { .raw_val = RISCV_SYSREG_MHPMEVENT4 }, "", 0x324, {0} , false }, // 73 |
32167 | | { "mhpmevent5", { .raw_val = RISCV_SYSREG_MHPMEVENT5 }, "mhpmevent5", { .raw_val = RISCV_SYSREG_MHPMEVENT5 }, "", 0x325, {0} , false }, // 74 |
32168 | | { "mhpmevent6", { .raw_val = RISCV_SYSREG_MHPMEVENT6 }, "mhpmevent6", { .raw_val = RISCV_SYSREG_MHPMEVENT6 }, "", 0x326, {0} , false }, // 75 |
32169 | | { "mhpmevent7", { .raw_val = RISCV_SYSREG_MHPMEVENT7 }, "mhpmevent7", { .raw_val = RISCV_SYSREG_MHPMEVENT7 }, "", 0x327, {0} , false }, // 76 |
32170 | | { "mhpmevent8", { .raw_val = RISCV_SYSREG_MHPMEVENT8 }, "mhpmevent8", { .raw_val = RISCV_SYSREG_MHPMEVENT8 }, "", 0x328, {0} , false }, // 77 |
32171 | | { "mhpmevent9", { .raw_val = RISCV_SYSREG_MHPMEVENT9 }, "mhpmevent9", { .raw_val = RISCV_SYSREG_MHPMEVENT9 }, "", 0x329, {0} , false }, // 78 |
32172 | | { "mhpmevent10", { .raw_val = RISCV_SYSREG_MHPMEVENT10 }, "mhpmevent10", { .raw_val = RISCV_SYSREG_MHPMEVENT10 }, "", 0x32A, {0} , false }, // 79 |
32173 | | { "mhpmevent11", { .raw_val = RISCV_SYSREG_MHPMEVENT11 }, "mhpmevent11", { .raw_val = RISCV_SYSREG_MHPMEVENT11 }, "", 0x32B, {0} , false }, // 80 |
32174 | | { "mhpmevent12", { .raw_val = RISCV_SYSREG_MHPMEVENT12 }, "mhpmevent12", { .raw_val = RISCV_SYSREG_MHPMEVENT12 }, "", 0x32C, {0} , false }, // 81 |
32175 | | { "mhpmevent13", { .raw_val = RISCV_SYSREG_MHPMEVENT13 }, "mhpmevent13", { .raw_val = RISCV_SYSREG_MHPMEVENT13 }, "", 0x32D, {0} , false }, // 82 |
32176 | | { "mhpmevent14", { .raw_val = RISCV_SYSREG_MHPMEVENT14 }, "mhpmevent14", { .raw_val = RISCV_SYSREG_MHPMEVENT14 }, "", 0x32E, {0} , false }, // 83 |
32177 | | { "mhpmevent15", { .raw_val = RISCV_SYSREG_MHPMEVENT15 }, "mhpmevent15", { .raw_val = RISCV_SYSREG_MHPMEVENT15 }, "", 0x32F, {0} , false }, // 84 |
32178 | | { "mhpmevent16", { .raw_val = RISCV_SYSREG_MHPMEVENT16 }, "mhpmevent16", { .raw_val = RISCV_SYSREG_MHPMEVENT16 }, "", 0x330, {0} , false }, // 85 |
32179 | | { "mhpmevent17", { .raw_val = RISCV_SYSREG_MHPMEVENT17 }, "mhpmevent17", { .raw_val = RISCV_SYSREG_MHPMEVENT17 }, "", 0x331, {0} , false }, // 86 |
32180 | | { "mhpmevent18", { .raw_val = RISCV_SYSREG_MHPMEVENT18 }, "mhpmevent18", { .raw_val = RISCV_SYSREG_MHPMEVENT18 }, "", 0x332, {0} , false }, // 87 |
32181 | | { "mhpmevent19", { .raw_val = RISCV_SYSREG_MHPMEVENT19 }, "mhpmevent19", { .raw_val = RISCV_SYSREG_MHPMEVENT19 }, "", 0x333, {0} , false }, // 88 |
32182 | | { "mhpmevent20", { .raw_val = RISCV_SYSREG_MHPMEVENT20 }, "mhpmevent20", { .raw_val = RISCV_SYSREG_MHPMEVENT20 }, "", 0x334, {0} , false }, // 89 |
32183 | | { "mhpmevent21", { .raw_val = RISCV_SYSREG_MHPMEVENT21 }, "mhpmevent21", { .raw_val = RISCV_SYSREG_MHPMEVENT21 }, "", 0x335, {0} , false }, // 90 |
32184 | | { "mhpmevent22", { .raw_val = RISCV_SYSREG_MHPMEVENT22 }, "mhpmevent22", { .raw_val = RISCV_SYSREG_MHPMEVENT22 }, "", 0x336, {0} , false }, // 91 |
32185 | | { "mhpmevent23", { .raw_val = RISCV_SYSREG_MHPMEVENT23 }, "mhpmevent23", { .raw_val = RISCV_SYSREG_MHPMEVENT23 }, "", 0x337, {0} , false }, // 92 |
32186 | | { "mhpmevent24", { .raw_val = RISCV_SYSREG_MHPMEVENT24 }, "mhpmevent24", { .raw_val = RISCV_SYSREG_MHPMEVENT24 }, "", 0x338, {0} , false }, // 93 |
32187 | | { "mhpmevent25", { .raw_val = RISCV_SYSREG_MHPMEVENT25 }, "mhpmevent25", { .raw_val = RISCV_SYSREG_MHPMEVENT25 }, "", 0x339, {0} , false }, // 94 |
32188 | | { "mhpmevent26", { .raw_val = RISCV_SYSREG_MHPMEVENT26 }, "mhpmevent26", { .raw_val = RISCV_SYSREG_MHPMEVENT26 }, "", 0x33A, {0} , false }, // 95 |
32189 | | { "mhpmevent27", { .raw_val = RISCV_SYSREG_MHPMEVENT27 }, "mhpmevent27", { .raw_val = RISCV_SYSREG_MHPMEVENT27 }, "", 0x33B, {0} , false }, // 96 |
32190 | | { "mhpmevent28", { .raw_val = RISCV_SYSREG_MHPMEVENT28 }, "mhpmevent28", { .raw_val = RISCV_SYSREG_MHPMEVENT28 }, "", 0x33C, {0} , false }, // 97 |
32191 | | { "mhpmevent29", { .raw_val = RISCV_SYSREG_MHPMEVENT29 }, "mhpmevent29", { .raw_val = RISCV_SYSREG_MHPMEVENT29 }, "", 0x33D, {0} , false }, // 98 |
32192 | | { "mhpmevent30", { .raw_val = RISCV_SYSREG_MHPMEVENT30 }, "mhpmevent30", { .raw_val = RISCV_SYSREG_MHPMEVENT30 }, "", 0x33E, {0} , false }, // 99 |
32193 | | { "mhpmevent31", { .raw_val = RISCV_SYSREG_MHPMEVENT31 }, "mhpmevent31", { .raw_val = RISCV_SYSREG_MHPMEVENT31 }, "", 0x33F, {0} , false }, // 100 |
32194 | | { "mscratch", { .raw_val = RISCV_SYSREG_MSCRATCH }, "mscratch", { .raw_val = RISCV_SYSREG_MSCRATCH }, "", 0x340, {0} , false }, // 101 |
32195 | | { "mepc", { .raw_val = RISCV_SYSREG_MEPC }, "mepc", { .raw_val = RISCV_SYSREG_MEPC }, "", 0x341, {0} , false }, // 102 |
32196 | | { "mcause", { .raw_val = RISCV_SYSREG_MCAUSE }, "mcause", { .raw_val = RISCV_SYSREG_MCAUSE }, "", 0x342, {0} , false }, // 103 |
32197 | | { "mtval", { .raw_val = RISCV_SYSREG_MTVAL }, "mtval", { .raw_val = RISCV_SYSREG_MTVAL }, "mbadaddr", 0x343, {0} , false }, // 104 |
32198 | | { "mip", { .raw_val = RISCV_SYSREG_MIP }, "mip", { .raw_val = RISCV_SYSREG_MIP }, "", 0x344, {0} , false }, // 105 |
32199 | | { "mtinst", { .raw_val = RISCV_SYSREG_MTINST }, "mtinst", { .raw_val = RISCV_SYSREG_MTINST }, "", 0x34A, {0} , false }, // 106 |
32200 | | { "mtval2", { .raw_val = RISCV_SYSREG_MTVAL2 }, "mtval2", { .raw_val = RISCV_SYSREG_MTVAL2 }, "", 0x34B, {0} , false }, // 107 |
32201 | | { "miselect", { .raw_val = RISCV_SYSREG_MISELECT }, "miselect", { .raw_val = RISCV_SYSREG_MISELECT }, "", 0x350, {0} , false }, // 108 |
32202 | | { "mireg", { .raw_val = RISCV_SYSREG_MIREG }, "mireg", { .raw_val = RISCV_SYSREG_MIREG }, "", 0x351, {0} , false }, // 109 |
32203 | | { "miph", { .raw_val = RISCV_SYSREG_MIPH }, "miph", { .raw_val = RISCV_SYSREG_MIPH }, "", 0x354, {0} , true }, // 110 |
32204 | | { "mtopei", { .raw_val = RISCV_SYSREG_MTOPEI }, "mtopei", { .raw_val = RISCV_SYSREG_MTOPEI }, "", 0x35C, {0} , false }, // 111 |
32205 | | { "pmpcfg0", { .raw_val = RISCV_SYSREG_PMPCFG0 }, "pmpcfg0", { .raw_val = RISCV_SYSREG_PMPCFG0 }, "", 0x3A0, {0} , false }, // 112 |
32206 | | { "pmpcfg1", { .raw_val = RISCV_SYSREG_PMPCFG1 }, "pmpcfg1", { .raw_val = RISCV_SYSREG_PMPCFG1 }, "", 0x3A1, {0} , true }, // 113 |
32207 | | { "pmpcfg2", { .raw_val = RISCV_SYSREG_PMPCFG2 }, "pmpcfg2", { .raw_val = RISCV_SYSREG_PMPCFG2 }, "", 0x3A2, {0} , false }, // 114 |
32208 | | { "pmpcfg3", { .raw_val = RISCV_SYSREG_PMPCFG3 }, "pmpcfg3", { .raw_val = RISCV_SYSREG_PMPCFG3 }, "", 0x3A3, {0} , true }, // 115 |
32209 | | { "pmpcfg4", { .raw_val = RISCV_SYSREG_PMPCFG4 }, "pmpcfg4", { .raw_val = RISCV_SYSREG_PMPCFG4 }, "", 0x3A4, {0} , false }, // 116 |
32210 | | { "pmpcfg5", { .raw_val = RISCV_SYSREG_PMPCFG5 }, "pmpcfg5", { .raw_val = RISCV_SYSREG_PMPCFG5 }, "", 0x3A5, {0} , true }, // 117 |
32211 | | { "pmpcfg6", { .raw_val = RISCV_SYSREG_PMPCFG6 }, "pmpcfg6", { .raw_val = RISCV_SYSREG_PMPCFG6 }, "", 0x3A6, {0} , false }, // 118 |
32212 | | { "pmpcfg7", { .raw_val = RISCV_SYSREG_PMPCFG7 }, "pmpcfg7", { .raw_val = RISCV_SYSREG_PMPCFG7 }, "", 0x3A7, {0} , true }, // 119 |
32213 | | { "pmpcfg8", { .raw_val = RISCV_SYSREG_PMPCFG8 }, "pmpcfg8", { .raw_val = RISCV_SYSREG_PMPCFG8 }, "", 0x3A8, {0} , false }, // 120 |
32214 | | { "pmpcfg9", { .raw_val = RISCV_SYSREG_PMPCFG9 }, "pmpcfg9", { .raw_val = RISCV_SYSREG_PMPCFG9 }, "", 0x3A9, {0} , true }, // 121 |
32215 | | { "pmpcfg10", { .raw_val = RISCV_SYSREG_PMPCFG10 }, "pmpcfg10", { .raw_val = RISCV_SYSREG_PMPCFG10 }, "", 0x3AA, {0} , false }, // 122 |
32216 | | { "pmpcfg11", { .raw_val = RISCV_SYSREG_PMPCFG11 }, "pmpcfg11", { .raw_val = RISCV_SYSREG_PMPCFG11 }, "", 0x3AB, {0} , true }, // 123 |
32217 | | { "pmpcfg12", { .raw_val = RISCV_SYSREG_PMPCFG12 }, "pmpcfg12", { .raw_val = RISCV_SYSREG_PMPCFG12 }, "", 0x3AC, {0} , false }, // 124 |
32218 | | { "pmpcfg13", { .raw_val = RISCV_SYSREG_PMPCFG13 }, "pmpcfg13", { .raw_val = RISCV_SYSREG_PMPCFG13 }, "", 0x3AD, {0} , true }, // 125 |
32219 | | { "pmpcfg14", { .raw_val = RISCV_SYSREG_PMPCFG14 }, "pmpcfg14", { .raw_val = RISCV_SYSREG_PMPCFG14 }, "", 0x3AE, {0} , false }, // 126 |
32220 | | { "pmpcfg15", { .raw_val = RISCV_SYSREG_PMPCFG15 }, "pmpcfg15", { .raw_val = RISCV_SYSREG_PMPCFG15 }, "", 0x3AF, {0} , true }, // 127 |
32221 | | { "pmpaddr0", { .raw_val = RISCV_SYSREG_PMPADDR0 }, "pmpaddr0", { .raw_val = RISCV_SYSREG_PMPADDR0 }, "", 0x3B0, {0} , false }, // 128 |
32222 | | { "pmpaddr1", { .raw_val = RISCV_SYSREG_PMPADDR1 }, "pmpaddr1", { .raw_val = RISCV_SYSREG_PMPADDR1 }, "", 0x3B1, {0} , false }, // 129 |
32223 | | { "pmpaddr2", { .raw_val = RISCV_SYSREG_PMPADDR2 }, "pmpaddr2", { .raw_val = RISCV_SYSREG_PMPADDR2 }, "", 0x3B2, {0} , false }, // 130 |
32224 | | { "pmpaddr3", { .raw_val = RISCV_SYSREG_PMPADDR3 }, "pmpaddr3", { .raw_val = RISCV_SYSREG_PMPADDR3 }, "", 0x3B3, {0} , false }, // 131 |
32225 | | { "pmpaddr4", { .raw_val = RISCV_SYSREG_PMPADDR4 }, "pmpaddr4", { .raw_val = RISCV_SYSREG_PMPADDR4 }, "", 0x3B4, {0} , false }, // 132 |
32226 | | { "pmpaddr5", { .raw_val = RISCV_SYSREG_PMPADDR5 }, "pmpaddr5", { .raw_val = RISCV_SYSREG_PMPADDR5 }, "", 0x3B5, {0} , false }, // 133 |
32227 | | { "pmpaddr6", { .raw_val = RISCV_SYSREG_PMPADDR6 }, "pmpaddr6", { .raw_val = RISCV_SYSREG_PMPADDR6 }, "", 0x3B6, {0} , false }, // 134 |
32228 | | { "pmpaddr7", { .raw_val = RISCV_SYSREG_PMPADDR7 }, "pmpaddr7", { .raw_val = RISCV_SYSREG_PMPADDR7 }, "", 0x3B7, {0} , false }, // 135 |
32229 | | { "pmpaddr8", { .raw_val = RISCV_SYSREG_PMPADDR8 }, "pmpaddr8", { .raw_val = RISCV_SYSREG_PMPADDR8 }, "", 0x3B8, {0} , false }, // 136 |
32230 | | { "pmpaddr9", { .raw_val = RISCV_SYSREG_PMPADDR9 }, "pmpaddr9", { .raw_val = RISCV_SYSREG_PMPADDR9 }, "", 0x3B9, {0} , false }, // 137 |
32231 | | { "pmpaddr10", { .raw_val = RISCV_SYSREG_PMPADDR10 }, "pmpaddr10", { .raw_val = RISCV_SYSREG_PMPADDR10 }, "", 0x3BA, {0} , false }, // 138 |
32232 | | { "pmpaddr11", { .raw_val = RISCV_SYSREG_PMPADDR11 }, "pmpaddr11", { .raw_val = RISCV_SYSREG_PMPADDR11 }, "", 0x3BB, {0} , false }, // 139 |
32233 | | { "pmpaddr12", { .raw_val = RISCV_SYSREG_PMPADDR12 }, "pmpaddr12", { .raw_val = RISCV_SYSREG_PMPADDR12 }, "", 0x3BC, {0} , false }, // 140 |
32234 | | { "pmpaddr13", { .raw_val = RISCV_SYSREG_PMPADDR13 }, "pmpaddr13", { .raw_val = RISCV_SYSREG_PMPADDR13 }, "", 0x3BD, {0} , false }, // 141 |
32235 | | { "pmpaddr14", { .raw_val = RISCV_SYSREG_PMPADDR14 }, "pmpaddr14", { .raw_val = RISCV_SYSREG_PMPADDR14 }, "", 0x3BE, {0} , false }, // 142 |
32236 | | { "pmpaddr15", { .raw_val = RISCV_SYSREG_PMPADDR15 }, "pmpaddr15", { .raw_val = RISCV_SYSREG_PMPADDR15 }, "", 0x3BF, {0} , false }, // 143 |
32237 | | { "pmpaddr16", { .raw_val = RISCV_SYSREG_PMPADDR16 }, "pmpaddr16", { .raw_val = RISCV_SYSREG_PMPADDR16 }, "", 0x3C0, {0} , false }, // 144 |
32238 | | { "pmpaddr17", { .raw_val = RISCV_SYSREG_PMPADDR17 }, "pmpaddr17", { .raw_val = RISCV_SYSREG_PMPADDR17 }, "", 0x3C1, {0} , false }, // 145 |
32239 | | { "pmpaddr18", { .raw_val = RISCV_SYSREG_PMPADDR18 }, "pmpaddr18", { .raw_val = RISCV_SYSREG_PMPADDR18 }, "", 0x3C2, {0} , false }, // 146 |
32240 | | { "pmpaddr19", { .raw_val = RISCV_SYSREG_PMPADDR19 }, "pmpaddr19", { .raw_val = RISCV_SYSREG_PMPADDR19 }, "", 0x3C3, {0} , false }, // 147 |
32241 | | { "pmpaddr20", { .raw_val = RISCV_SYSREG_PMPADDR20 }, "pmpaddr20", { .raw_val = RISCV_SYSREG_PMPADDR20 }, "", 0x3C4, {0} , false }, // 148 |
32242 | | { "pmpaddr21", { .raw_val = RISCV_SYSREG_PMPADDR21 }, "pmpaddr21", { .raw_val = RISCV_SYSREG_PMPADDR21 }, "", 0x3C5, {0} , false }, // 149 |
32243 | | { "pmpaddr22", { .raw_val = RISCV_SYSREG_PMPADDR22 }, "pmpaddr22", { .raw_val = RISCV_SYSREG_PMPADDR22 }, "", 0x3C6, {0} , false }, // 150 |
32244 | | { "pmpaddr23", { .raw_val = RISCV_SYSREG_PMPADDR23 }, "pmpaddr23", { .raw_val = RISCV_SYSREG_PMPADDR23 }, "", 0x3C7, {0} , false }, // 151 |
32245 | | { "pmpaddr24", { .raw_val = RISCV_SYSREG_PMPADDR24 }, "pmpaddr24", { .raw_val = RISCV_SYSREG_PMPADDR24 }, "", 0x3C8, {0} , false }, // 152 |
32246 | | { "pmpaddr25", { .raw_val = RISCV_SYSREG_PMPADDR25 }, "pmpaddr25", { .raw_val = RISCV_SYSREG_PMPADDR25 }, "", 0x3C9, {0} , false }, // 153 |
32247 | | { "pmpaddr26", { .raw_val = RISCV_SYSREG_PMPADDR26 }, "pmpaddr26", { .raw_val = RISCV_SYSREG_PMPADDR26 }, "", 0x3CA, {0} , false }, // 154 |
32248 | | { "pmpaddr27", { .raw_val = RISCV_SYSREG_PMPADDR27 }, "pmpaddr27", { .raw_val = RISCV_SYSREG_PMPADDR27 }, "", 0x3CB, {0} , false }, // 155 |
32249 | | { "pmpaddr28", { .raw_val = RISCV_SYSREG_PMPADDR28 }, "pmpaddr28", { .raw_val = RISCV_SYSREG_PMPADDR28 }, "", 0x3CC, {0} , false }, // 156 |
32250 | | { "pmpaddr29", { .raw_val = RISCV_SYSREG_PMPADDR29 }, "pmpaddr29", { .raw_val = RISCV_SYSREG_PMPADDR29 }, "", 0x3CD, {0} , false }, // 157 |
32251 | | { "pmpaddr30", { .raw_val = RISCV_SYSREG_PMPADDR30 }, "pmpaddr30", { .raw_val = RISCV_SYSREG_PMPADDR30 }, "", 0x3CE, {0} , false }, // 158 |
32252 | | { "pmpaddr31", { .raw_val = RISCV_SYSREG_PMPADDR31 }, "pmpaddr31", { .raw_val = RISCV_SYSREG_PMPADDR31 }, "", 0x3CF, {0} , false }, // 159 |
32253 | | { "pmpaddr32", { .raw_val = RISCV_SYSREG_PMPADDR32 }, "pmpaddr32", { .raw_val = RISCV_SYSREG_PMPADDR32 }, "", 0x3D0, {0} , false }, // 160 |
32254 | | { "pmpaddr33", { .raw_val = RISCV_SYSREG_PMPADDR33 }, "pmpaddr33", { .raw_val = RISCV_SYSREG_PMPADDR33 }, "", 0x3D1, {0} , false }, // 161 |
32255 | | { "pmpaddr34", { .raw_val = RISCV_SYSREG_PMPADDR34 }, "pmpaddr34", { .raw_val = RISCV_SYSREG_PMPADDR34 }, "", 0x3D2, {0} , false }, // 162 |
32256 | | { "pmpaddr35", { .raw_val = RISCV_SYSREG_PMPADDR35 }, "pmpaddr35", { .raw_val = RISCV_SYSREG_PMPADDR35 }, "", 0x3D3, {0} , false }, // 163 |
32257 | | { "pmpaddr36", { .raw_val = RISCV_SYSREG_PMPADDR36 }, "pmpaddr36", { .raw_val = RISCV_SYSREG_PMPADDR36 }, "", 0x3D4, {0} , false }, // 164 |
32258 | | { "pmpaddr37", { .raw_val = RISCV_SYSREG_PMPADDR37 }, "pmpaddr37", { .raw_val = RISCV_SYSREG_PMPADDR37 }, "", 0x3D5, {0} , false }, // 165 |
32259 | | { "pmpaddr38", { .raw_val = RISCV_SYSREG_PMPADDR38 }, "pmpaddr38", { .raw_val = RISCV_SYSREG_PMPADDR38 }, "", 0x3D6, {0} , false }, // 166 |
32260 | | { "pmpaddr39", { .raw_val = RISCV_SYSREG_PMPADDR39 }, "pmpaddr39", { .raw_val = RISCV_SYSREG_PMPADDR39 }, "", 0x3D7, {0} , false }, // 167 |
32261 | | { "pmpaddr40", { .raw_val = RISCV_SYSREG_PMPADDR40 }, "pmpaddr40", { .raw_val = RISCV_SYSREG_PMPADDR40 }, "", 0x3D8, {0} , false }, // 168 |
32262 | | { "pmpaddr41", { .raw_val = RISCV_SYSREG_PMPADDR41 }, "pmpaddr41", { .raw_val = RISCV_SYSREG_PMPADDR41 }, "", 0x3D9, {0} , false }, // 169 |
32263 | | { "pmpaddr42", { .raw_val = RISCV_SYSREG_PMPADDR42 }, "pmpaddr42", { .raw_val = RISCV_SYSREG_PMPADDR42 }, "", 0x3DA, {0} , false }, // 170 |
32264 | | { "pmpaddr43", { .raw_val = RISCV_SYSREG_PMPADDR43 }, "pmpaddr43", { .raw_val = RISCV_SYSREG_PMPADDR43 }, "", 0x3DB, {0} , false }, // 171 |
32265 | | { "pmpaddr44", { .raw_val = RISCV_SYSREG_PMPADDR44 }, "pmpaddr44", { .raw_val = RISCV_SYSREG_PMPADDR44 }, "", 0x3DC, {0} , false }, // 172 |
32266 | | { "pmpaddr45", { .raw_val = RISCV_SYSREG_PMPADDR45 }, "pmpaddr45", { .raw_val = RISCV_SYSREG_PMPADDR45 }, "", 0x3DD, {0} , false }, // 173 |
32267 | | { "pmpaddr46", { .raw_val = RISCV_SYSREG_PMPADDR46 }, "pmpaddr46", { .raw_val = RISCV_SYSREG_PMPADDR46 }, "", 0x3DE, {0} , false }, // 174 |
32268 | | { "pmpaddr47", { .raw_val = RISCV_SYSREG_PMPADDR47 }, "pmpaddr47", { .raw_val = RISCV_SYSREG_PMPADDR47 }, "", 0x3DF, {0} , false }, // 175 |
32269 | | { "pmpaddr48", { .raw_val = RISCV_SYSREG_PMPADDR48 }, "pmpaddr48", { .raw_val = RISCV_SYSREG_PMPADDR48 }, "", 0x3E0, {0} , false }, // 176 |
32270 | | { "pmpaddr49", { .raw_val = RISCV_SYSREG_PMPADDR49 }, "pmpaddr49", { .raw_val = RISCV_SYSREG_PMPADDR49 }, "", 0x3E1, {0} , false }, // 177 |
32271 | | { "pmpaddr50", { .raw_val = RISCV_SYSREG_PMPADDR50 }, "pmpaddr50", { .raw_val = RISCV_SYSREG_PMPADDR50 }, "", 0x3E2, {0} , false }, // 178 |
32272 | | { "pmpaddr51", { .raw_val = RISCV_SYSREG_PMPADDR51 }, "pmpaddr51", { .raw_val = RISCV_SYSREG_PMPADDR51 }, "", 0x3E3, {0} , false }, // 179 |
32273 | | { "pmpaddr52", { .raw_val = RISCV_SYSREG_PMPADDR52 }, "pmpaddr52", { .raw_val = RISCV_SYSREG_PMPADDR52 }, "", 0x3E4, {0} , false }, // 180 |
32274 | | { "pmpaddr53", { .raw_val = RISCV_SYSREG_PMPADDR53 }, "pmpaddr53", { .raw_val = RISCV_SYSREG_PMPADDR53 }, "", 0x3E5, {0} , false }, // 181 |
32275 | | { "pmpaddr54", { .raw_val = RISCV_SYSREG_PMPADDR54 }, "pmpaddr54", { .raw_val = RISCV_SYSREG_PMPADDR54 }, "", 0x3E6, {0} , false }, // 182 |
32276 | | { "pmpaddr55", { .raw_val = RISCV_SYSREG_PMPADDR55 }, "pmpaddr55", { .raw_val = RISCV_SYSREG_PMPADDR55 }, "", 0x3E7, {0} , false }, // 183 |
32277 | | { "pmpaddr56", { .raw_val = RISCV_SYSREG_PMPADDR56 }, "pmpaddr56", { .raw_val = RISCV_SYSREG_PMPADDR56 }, "", 0x3E8, {0} , false }, // 184 |
32278 | | { "pmpaddr57", { .raw_val = RISCV_SYSREG_PMPADDR57 }, "pmpaddr57", { .raw_val = RISCV_SYSREG_PMPADDR57 }, "", 0x3E9, {0} , false }, // 185 |
32279 | | { "pmpaddr58", { .raw_val = RISCV_SYSREG_PMPADDR58 }, "pmpaddr58", { .raw_val = RISCV_SYSREG_PMPADDR58 }, "", 0x3EA, {0} , false }, // 186 |
32280 | | { "pmpaddr59", { .raw_val = RISCV_SYSREG_PMPADDR59 }, "pmpaddr59", { .raw_val = RISCV_SYSREG_PMPADDR59 }, "", 0x3EB, {0} , false }, // 187 |
32281 | | { "pmpaddr60", { .raw_val = RISCV_SYSREG_PMPADDR60 }, "pmpaddr60", { .raw_val = RISCV_SYSREG_PMPADDR60 }, "", 0x3EC, {0} , false }, // 188 |
32282 | | { "pmpaddr61", { .raw_val = RISCV_SYSREG_PMPADDR61 }, "pmpaddr61", { .raw_val = RISCV_SYSREG_PMPADDR61 }, "", 0x3ED, {0} , false }, // 189 |
32283 | | { "pmpaddr62", { .raw_val = RISCV_SYSREG_PMPADDR62 }, "pmpaddr62", { .raw_val = RISCV_SYSREG_PMPADDR62 }, "", 0x3EE, {0} , false }, // 190 |
32284 | | { "pmpaddr63", { .raw_val = RISCV_SYSREG_PMPADDR63 }, "pmpaddr63", { .raw_val = RISCV_SYSREG_PMPADDR63 }, "", 0x3EF, {0} , false }, // 191 |
32285 | | { "scontext", { .raw_val = RISCV_SYSREG_SCONTEXT }, "scontext", { .raw_val = RISCV_SYSREG_SCONTEXT }, "", 0x5A8, {0} , false }, // 192 |
32286 | | { "hstatus", { .raw_val = RISCV_SYSREG_HSTATUS }, "hstatus", { .raw_val = RISCV_SYSREG_HSTATUS }, "", 0x600, {0} , false }, // 193 |
32287 | | { "hedeleg", { .raw_val = RISCV_SYSREG_HEDELEG }, "hedeleg", { .raw_val = RISCV_SYSREG_HEDELEG }, "", 0x602, {0} , false }, // 194 |
32288 | | { "hideleg", { .raw_val = RISCV_SYSREG_HIDELEG }, "hideleg", { .raw_val = RISCV_SYSREG_HIDELEG }, "", 0x603, {0} , false }, // 195 |
32289 | | { "hie", { .raw_val = RISCV_SYSREG_HIE }, "hie", { .raw_val = RISCV_SYSREG_HIE }, "", 0x604, {0} , false }, // 196 |
32290 | | { "htimedelta", { .raw_val = RISCV_SYSREG_HTIMEDELTA }, "htimedelta", { .raw_val = RISCV_SYSREG_HTIMEDELTA }, "", 0x605, {0} , false }, // 197 |
32291 | | { "hcounteren", { .raw_val = RISCV_SYSREG_HCOUNTEREN }, "hcounteren", { .raw_val = RISCV_SYSREG_HCOUNTEREN }, "", 0x606, {0} , false }, // 198 |
32292 | | { "hgeie", { .raw_val = RISCV_SYSREG_HGEIE }, "hgeie", { .raw_val = RISCV_SYSREG_HGEIE }, "", 0x607, {0} , false }, // 199 |
32293 | | { "hvien", { .raw_val = RISCV_SYSREG_HVIEN }, "hvien", { .raw_val = RISCV_SYSREG_HVIEN }, "", 0x608, {0} , false }, // 200 |
32294 | | { "hvictl", { .raw_val = RISCV_SYSREG_HVICTL }, "hvictl", { .raw_val = RISCV_SYSREG_HVICTL }, "", 0x609, {0} , false }, // 201 |
32295 | | { "henvcfg", { .raw_val = RISCV_SYSREG_HENVCFG }, "henvcfg", { .raw_val = RISCV_SYSREG_HENVCFG }, "", 0x60A, {0} , false }, // 202 |
32296 | | { "hstateen0", { .raw_val = RISCV_SYSREG_HSTATEEN0 }, "hstateen0", { .raw_val = RISCV_SYSREG_HSTATEEN0 }, "", 0x60C, {0} , false }, // 203 |
32297 | | { "hstateen1", { .raw_val = RISCV_SYSREG_HSTATEEN1 }, "hstateen1", { .raw_val = RISCV_SYSREG_HSTATEEN1 }, "", 0x60D, {0} , false }, // 204 |
32298 | | { "hstateen2", { .raw_val = RISCV_SYSREG_HSTATEEN2 }, "hstateen2", { .raw_val = RISCV_SYSREG_HSTATEEN2 }, "", 0x60E, {0} , false }, // 205 |
32299 | | { "hstateen3", { .raw_val = RISCV_SYSREG_HSTATEEN3 }, "hstateen3", { .raw_val = RISCV_SYSREG_HSTATEEN3 }, "", 0x60F, {0} , false }, // 206 |
32300 | | { "hidelegh", { .raw_val = RISCV_SYSREG_HIDELEGH }, "hidelegh", { .raw_val = RISCV_SYSREG_HIDELEGH }, "", 0x613, {0} , true }, // 207 |
32301 | | { "htimedeltah", { .raw_val = RISCV_SYSREG_HTIMEDELTAH }, "htimedeltah", { .raw_val = RISCV_SYSREG_HTIMEDELTAH }, "", 0x615, {0} , true }, // 208 |
32302 | | { "hvienh", { .raw_val = RISCV_SYSREG_HVIENH }, "hvienh", { .raw_val = RISCV_SYSREG_HVIENH }, "", 0x618, {0} , true }, // 209 |
32303 | | { "henvcfgh", { .raw_val = RISCV_SYSREG_HENVCFGH }, "henvcfgh", { .raw_val = RISCV_SYSREG_HENVCFGH }, "", 0x61A, {0} , true }, // 210 |
32304 | | { "hstateen0h", { .raw_val = RISCV_SYSREG_HSTATEEN0H }, "hstateen0h", { .raw_val = RISCV_SYSREG_HSTATEEN0H }, "", 0x61C, {0} , true }, // 211 |
32305 | | { "hstateen1h", { .raw_val = RISCV_SYSREG_HSTATEEN1H }, "hstateen1h", { .raw_val = RISCV_SYSREG_HSTATEEN1H }, "", 0x61D, {0} , true }, // 212 |
32306 | | { "hstateen2h", { .raw_val = RISCV_SYSREG_HSTATEEN2H }, "hstateen2h", { .raw_val = RISCV_SYSREG_HSTATEEN2H }, "", 0x61E, {0} , true }, // 213 |
32307 | | { "hstateen3h", { .raw_val = RISCV_SYSREG_HSTATEEN3H }, "hstateen3h", { .raw_val = RISCV_SYSREG_HSTATEEN3H }, "", 0x61F, {0} , true }, // 214 |
32308 | | { "htval", { .raw_val = RISCV_SYSREG_HTVAL }, "htval", { .raw_val = RISCV_SYSREG_HTVAL }, "", 0x643, {0} , false }, // 215 |
32309 | | { "hip", { .raw_val = RISCV_SYSREG_HIP }, "hip", { .raw_val = RISCV_SYSREG_HIP }, "", 0x644, {0} , false }, // 216 |
32310 | | { "hvip", { .raw_val = RISCV_SYSREG_HVIP }, "hvip", { .raw_val = RISCV_SYSREG_HVIP }, "", 0x645, {0} , false }, // 217 |
32311 | | { "hviprio1", { .raw_val = RISCV_SYSREG_HVIPRIO1 }, "hviprio1", { .raw_val = RISCV_SYSREG_HVIPRIO1 }, "", 0x646, {0} , false }, // 218 |
32312 | | { "hviprio2", { .raw_val = RISCV_SYSREG_HVIPRIO2 }, "hviprio2", { .raw_val = RISCV_SYSREG_HVIPRIO2 }, "", 0x647, {0} , false }, // 219 |
32313 | | { "htinst", { .raw_val = RISCV_SYSREG_HTINST }, "htinst", { .raw_val = RISCV_SYSREG_HTINST }, "", 0x64A, {0} , false }, // 220 |
32314 | | { "hviph", { .raw_val = RISCV_SYSREG_HVIPH }, "hviph", { .raw_val = RISCV_SYSREG_HVIPH }, "", 0x655, {0} , true }, // 221 |
32315 | | { "hviprio1h", { .raw_val = RISCV_SYSREG_HVIPRIO1H }, "hviprio1h", { .raw_val = RISCV_SYSREG_HVIPRIO1H }, "", 0x656, {0} , true }, // 222 |
32316 | | { "hviprio2h", { .raw_val = RISCV_SYSREG_HVIPRIO2H }, "hviprio2h", { .raw_val = RISCV_SYSREG_HVIPRIO2H }, "", 0x657, {0} , true }, // 223 |
32317 | | { "hgatp", { .raw_val = RISCV_SYSREG_HGATP }, "hgatp", { .raw_val = RISCV_SYSREG_HGATP }, "", 0x680, {0} , false }, // 224 |
32318 | | { "hcontext", { .raw_val = RISCV_SYSREG_HCONTEXT }, "hcontext", { .raw_val = RISCV_SYSREG_HCONTEXT }, "", 0x6A8, {0} , false }, // 225 |
32319 | | { "mhpmevent3h", { .raw_val = RISCV_SYSREG_MHPMEVENT3H }, "mhpmevent3h", { .raw_val = RISCV_SYSREG_MHPMEVENT3H }, "", 0x723, {0} , true }, // 226 |
32320 | | { "mhpmevent4h", { .raw_val = RISCV_SYSREG_MHPMEVENT4H }, "mhpmevent4h", { .raw_val = RISCV_SYSREG_MHPMEVENT4H }, "", 0x724, {0} , true }, // 227 |
32321 | | { "mhpmevent5h", { .raw_val = RISCV_SYSREG_MHPMEVENT5H }, "mhpmevent5h", { .raw_val = RISCV_SYSREG_MHPMEVENT5H }, "", 0x725, {0} , true }, // 228 |
32322 | | { "mhpmevent6h", { .raw_val = RISCV_SYSREG_MHPMEVENT6H }, "mhpmevent6h", { .raw_val = RISCV_SYSREG_MHPMEVENT6H }, "", 0x726, {0} , true }, // 229 |
32323 | | { "mhpmevent7h", { .raw_val = RISCV_SYSREG_MHPMEVENT7H }, "mhpmevent7h", { .raw_val = RISCV_SYSREG_MHPMEVENT7H }, "", 0x727, {0} , true }, // 230 |
32324 | | { "mhpmevent8h", { .raw_val = RISCV_SYSREG_MHPMEVENT8H }, "mhpmevent8h", { .raw_val = RISCV_SYSREG_MHPMEVENT8H }, "", 0x728, {0} , true }, // 231 |
32325 | | { "mhpmevent9h", { .raw_val = RISCV_SYSREG_MHPMEVENT9H }, "mhpmevent9h", { .raw_val = RISCV_SYSREG_MHPMEVENT9H }, "", 0x729, {0} , true }, // 232 |
32326 | | { "mhpmevent10h", { .raw_val = RISCV_SYSREG_MHPMEVENT10H }, "mhpmevent10h", { .raw_val = RISCV_SYSREG_MHPMEVENT10H }, "", 0x72A, {0} , true }, // 233 |
32327 | | { "mhpmevent11h", { .raw_val = RISCV_SYSREG_MHPMEVENT11H }, "mhpmevent11h", { .raw_val = RISCV_SYSREG_MHPMEVENT11H }, "", 0x72B, {0} , true }, // 234 |
32328 | | { "mhpmevent12h", { .raw_val = RISCV_SYSREG_MHPMEVENT12H }, "mhpmevent12h", { .raw_val = RISCV_SYSREG_MHPMEVENT12H }, "", 0x72C, {0} , true }, // 235 |
32329 | | { "mhpmevent13h", { .raw_val = RISCV_SYSREG_MHPMEVENT13H }, "mhpmevent13h", { .raw_val = RISCV_SYSREG_MHPMEVENT13H }, "", 0x72D, {0} , true }, // 236 |
32330 | | { "mhpmevent14h", { .raw_val = RISCV_SYSREG_MHPMEVENT14H }, "mhpmevent14h", { .raw_val = RISCV_SYSREG_MHPMEVENT14H }, "", 0x72E, {0} , true }, // 237 |
32331 | | { "mhpmevent15h", { .raw_val = RISCV_SYSREG_MHPMEVENT15H }, "mhpmevent15h", { .raw_val = RISCV_SYSREG_MHPMEVENT15H }, "", 0x72F, {0} , true }, // 238 |
32332 | | { "mhpmevent16h", { .raw_val = RISCV_SYSREG_MHPMEVENT16H }, "mhpmevent16h", { .raw_val = RISCV_SYSREG_MHPMEVENT16H }, "", 0x730, {0} , true }, // 239 |
32333 | | { "mhpmevent17h", { .raw_val = RISCV_SYSREG_MHPMEVENT17H }, "mhpmevent17h", { .raw_val = RISCV_SYSREG_MHPMEVENT17H }, "", 0x731, {0} , true }, // 240 |
32334 | | { "mhpmevent18h", { .raw_val = RISCV_SYSREG_MHPMEVENT18H }, "mhpmevent18h", { .raw_val = RISCV_SYSREG_MHPMEVENT18H }, "", 0x732, {0} , true }, // 241 |
32335 | | { "mhpmevent19h", { .raw_val = RISCV_SYSREG_MHPMEVENT19H }, "mhpmevent19h", { .raw_val = RISCV_SYSREG_MHPMEVENT19H }, "", 0x733, {0} , true }, // 242 |
32336 | | { "mhpmevent20h", { .raw_val = RISCV_SYSREG_MHPMEVENT20H }, "mhpmevent20h", { .raw_val = RISCV_SYSREG_MHPMEVENT20H }, "", 0x734, {0} , true }, // 243 |
32337 | | { "mhpmevent21h", { .raw_val = RISCV_SYSREG_MHPMEVENT21H }, "mhpmevent21h", { .raw_val = RISCV_SYSREG_MHPMEVENT21H }, "", 0x735, {0} , true }, // 244 |
32338 | | { "mhpmevent22h", { .raw_val = RISCV_SYSREG_MHPMEVENT22H }, "mhpmevent22h", { .raw_val = RISCV_SYSREG_MHPMEVENT22H }, "", 0x736, {0} , true }, // 245 |
32339 | | { "mhpmevent23h", { .raw_val = RISCV_SYSREG_MHPMEVENT23H }, "mhpmevent23h", { .raw_val = RISCV_SYSREG_MHPMEVENT23H }, "", 0x737, {0} , true }, // 246 |
32340 | | { "mhpmevent24h", { .raw_val = RISCV_SYSREG_MHPMEVENT24H }, "mhpmevent24h", { .raw_val = RISCV_SYSREG_MHPMEVENT24H }, "", 0x738, {0} , true }, // 247 |
32341 | | { "mhpmevent25h", { .raw_val = RISCV_SYSREG_MHPMEVENT25H }, "mhpmevent25h", { .raw_val = RISCV_SYSREG_MHPMEVENT25H }, "", 0x739, {0} , true }, // 248 |
32342 | | { "mhpmevent26h", { .raw_val = RISCV_SYSREG_MHPMEVENT26H }, "mhpmevent26h", { .raw_val = RISCV_SYSREG_MHPMEVENT26H }, "", 0x73A, {0} , true }, // 249 |
32343 | | { "mhpmevent27h", { .raw_val = RISCV_SYSREG_MHPMEVENT27H }, "mhpmevent27h", { .raw_val = RISCV_SYSREG_MHPMEVENT27H }, "", 0x73B, {0} , true }, // 250 |
32344 | | { "mhpmevent28h", { .raw_val = RISCV_SYSREG_MHPMEVENT28H }, "mhpmevent28h", { .raw_val = RISCV_SYSREG_MHPMEVENT28H }, "", 0x73C, {0} , true }, // 251 |
32345 | | { "mhpmevent29h", { .raw_val = RISCV_SYSREG_MHPMEVENT29H }, "mhpmevent29h", { .raw_val = RISCV_SYSREG_MHPMEVENT29H }, "", 0x73D, {0} , true }, // 252 |
32346 | | { "mhpmevent30h", { .raw_val = RISCV_SYSREG_MHPMEVENT30H }, "mhpmevent30h", { .raw_val = RISCV_SYSREG_MHPMEVENT30H }, "", 0x73E, {0} , true }, // 253 |
32347 | | { "mhpmevent31h", { .raw_val = RISCV_SYSREG_MHPMEVENT31H }, "mhpmevent31h", { .raw_val = RISCV_SYSREG_MHPMEVENT31H }, "", 0x73F, {0} , true }, // 254 |
32348 | | { "mseccfg", { .raw_val = RISCV_SYSREG_MSECCFG }, "mseccfg", { .raw_val = RISCV_SYSREG_MSECCFG }, "", 0x747, {0} , false }, // 255 |
32349 | | { "mseccfgh", { .raw_val = RISCV_SYSREG_MSECCFGH }, "mseccfgh", { .raw_val = RISCV_SYSREG_MSECCFGH }, "", 0x757, {0} , true }, // 256 |
32350 | | { "tselect", { .raw_val = RISCV_SYSREG_TSELECT }, "tselect", { .raw_val = RISCV_SYSREG_TSELECT }, "", 0x7A0, {0} , false }, // 257 |
32351 | | { "tdata1", { .raw_val = RISCV_SYSREG_TDATA1 }, "tdata1", { .raw_val = RISCV_SYSREG_TDATA1 }, "", 0x7A1, {0} , false }, // 258 |
32352 | | { "tdata2", { .raw_val = RISCV_SYSREG_TDATA2 }, "tdata2", { .raw_val = RISCV_SYSREG_TDATA2 }, "", 0x7A2, {0} , false }, // 259 |
32353 | | { "tdata3", { .raw_val = RISCV_SYSREG_TDATA3 }, "tdata3", { .raw_val = RISCV_SYSREG_TDATA3 }, "", 0x7A3, {0} , false }, // 260 |
32354 | | { "mcontext", { .raw_val = RISCV_SYSREG_MCONTEXT }, "mcontext", { .raw_val = RISCV_SYSREG_MCONTEXT }, "", 0x7A8, {0} , false }, // 261 |
32355 | | { "dcsr", { .raw_val = RISCV_SYSREG_DCSR }, "dcsr", { .raw_val = RISCV_SYSREG_DCSR }, "", 0x7B0, {0} , false }, // 262 |
32356 | | { "dpc", { .raw_val = RISCV_SYSREG_DPC }, "dpc", { .raw_val = RISCV_SYSREG_DPC }, "", 0x7B1, {0} , false }, // 263 |
32357 | | { "dscratch0", { .raw_val = RISCV_SYSREG_DSCRATCH0 }, "dscratch", { .raw_val = RISCV_SYSREG_DSCRATCH }, "", 0x7B2, {0} , false }, // 264 |
32358 | | { "dscratch1", { .raw_val = RISCV_SYSREG_DSCRATCH1 }, "dscratch1", { .raw_val = RISCV_SYSREG_DSCRATCH1 }, "", 0x7B3, {0} , false }, // 265 |
32359 | | { "mcycle", { .raw_val = RISCV_SYSREG_MCYCLE }, "mcycle", { .raw_val = RISCV_SYSREG_MCYCLE }, "", 0xB00, {0} , false }, // 266 |
32360 | | { "minstret", { .raw_val = RISCV_SYSREG_MINSTRET }, "minstret", { .raw_val = RISCV_SYSREG_MINSTRET }, "", 0xB02, {0} , false }, // 267 |
32361 | | { "mhpmcounter3", { .raw_val = RISCV_SYSREG_MHPMCOUNTER3 }, "mhpmcounter3", { .raw_val = RISCV_SYSREG_MHPMCOUNTER3 }, "", 0xB03, {0} , false }, // 268 |
32362 | | { "mhpmcounter4", { .raw_val = RISCV_SYSREG_MHPMCOUNTER4 }, "mhpmcounter4", { .raw_val = RISCV_SYSREG_MHPMCOUNTER4 }, "", 0xB04, {0} , false }, // 269 |
32363 | | { "mhpmcounter5", { .raw_val = RISCV_SYSREG_MHPMCOUNTER5 }, "mhpmcounter5", { .raw_val = RISCV_SYSREG_MHPMCOUNTER5 }, "", 0xB05, {0} , false }, // 270 |
32364 | | { "mhpmcounter6", { .raw_val = RISCV_SYSREG_MHPMCOUNTER6 }, "mhpmcounter6", { .raw_val = RISCV_SYSREG_MHPMCOUNTER6 }, "", 0xB06, {0} , false }, // 271 |
32365 | | { "mhpmcounter7", { .raw_val = RISCV_SYSREG_MHPMCOUNTER7 }, "mhpmcounter7", { .raw_val = RISCV_SYSREG_MHPMCOUNTER7 }, "", 0xB07, {0} , false }, // 272 |
32366 | | { "mhpmcounter8", { .raw_val = RISCV_SYSREG_MHPMCOUNTER8 }, "mhpmcounter8", { .raw_val = RISCV_SYSREG_MHPMCOUNTER8 }, "", 0xB08, {0} , false }, // 273 |
32367 | | { "mhpmcounter9", { .raw_val = RISCV_SYSREG_MHPMCOUNTER9 }, "mhpmcounter9", { .raw_val = RISCV_SYSREG_MHPMCOUNTER9 }, "", 0xB09, {0} , false }, // 274 |
32368 | | { "mhpmcounter10", { .raw_val = RISCV_SYSREG_MHPMCOUNTER10 }, "mhpmcounter10", { .raw_val = RISCV_SYSREG_MHPMCOUNTER10 }, "", 0xB0A, {0} , false }, // 275 |
32369 | | { "mhpmcounter11", { .raw_val = RISCV_SYSREG_MHPMCOUNTER11 }, "mhpmcounter11", { .raw_val = RISCV_SYSREG_MHPMCOUNTER11 }, "", 0xB0B, {0} , false }, // 276 |
32370 | | { "mhpmcounter12", { .raw_val = RISCV_SYSREG_MHPMCOUNTER12 }, "mhpmcounter12", { .raw_val = RISCV_SYSREG_MHPMCOUNTER12 }, "", 0xB0C, {0} , false }, // 277 |
32371 | | { "mhpmcounter13", { .raw_val = RISCV_SYSREG_MHPMCOUNTER13 }, "mhpmcounter13", { .raw_val = RISCV_SYSREG_MHPMCOUNTER13 }, "", 0xB0D, {0} , false }, // 278 |
32372 | | { "mhpmcounter14", { .raw_val = RISCV_SYSREG_MHPMCOUNTER14 }, "mhpmcounter14", { .raw_val = RISCV_SYSREG_MHPMCOUNTER14 }, "", 0xB0E, {0} , false }, // 279 |
32373 | | { "mhpmcounter15", { .raw_val = RISCV_SYSREG_MHPMCOUNTER15 }, "mhpmcounter15", { .raw_val = RISCV_SYSREG_MHPMCOUNTER15 }, "", 0xB0F, {0} , false }, // 280 |
32374 | | { "mhpmcounter16", { .raw_val = RISCV_SYSREG_MHPMCOUNTER16 }, "mhpmcounter16", { .raw_val = RISCV_SYSREG_MHPMCOUNTER16 }, "", 0xB10, {0} , false }, // 281 |
32375 | | { "mhpmcounter17", { .raw_val = RISCV_SYSREG_MHPMCOUNTER17 }, "mhpmcounter17", { .raw_val = RISCV_SYSREG_MHPMCOUNTER17 }, "", 0xB11, {0} , false }, // 282 |
32376 | | { "mhpmcounter18", { .raw_val = RISCV_SYSREG_MHPMCOUNTER18 }, "mhpmcounter18", { .raw_val = RISCV_SYSREG_MHPMCOUNTER18 }, "", 0xB12, {0} , false }, // 283 |
32377 | | { "mhpmcounter19", { .raw_val = RISCV_SYSREG_MHPMCOUNTER19 }, "mhpmcounter19", { .raw_val = RISCV_SYSREG_MHPMCOUNTER19 }, "", 0xB13, {0} , false }, // 284 |
32378 | | { "mhpmcounter20", { .raw_val = RISCV_SYSREG_MHPMCOUNTER20 }, "mhpmcounter20", { .raw_val = RISCV_SYSREG_MHPMCOUNTER20 }, "", 0xB14, {0} , false }, // 285 |
32379 | | { "mhpmcounter21", { .raw_val = RISCV_SYSREG_MHPMCOUNTER21 }, "mhpmcounter21", { .raw_val = RISCV_SYSREG_MHPMCOUNTER21 }, "", 0xB15, {0} , false }, // 286 |
32380 | | { "mhpmcounter22", { .raw_val = RISCV_SYSREG_MHPMCOUNTER22 }, "mhpmcounter22", { .raw_val = RISCV_SYSREG_MHPMCOUNTER22 }, "", 0xB16, {0} , false }, // 287 |
32381 | | { "mhpmcounter23", { .raw_val = RISCV_SYSREG_MHPMCOUNTER23 }, "mhpmcounter23", { .raw_val = RISCV_SYSREG_MHPMCOUNTER23 }, "", 0xB17, {0} , false }, // 288 |
32382 | | { "mhpmcounter24", { .raw_val = RISCV_SYSREG_MHPMCOUNTER24 }, "mhpmcounter24", { .raw_val = RISCV_SYSREG_MHPMCOUNTER24 }, "", 0xB18, {0} , false }, // 289 |
32383 | | { "mhpmcounter25", { .raw_val = RISCV_SYSREG_MHPMCOUNTER25 }, "mhpmcounter25", { .raw_val = RISCV_SYSREG_MHPMCOUNTER25 }, "", 0xB19, {0} , false }, // 290 |
32384 | | { "mhpmcounter26", { .raw_val = RISCV_SYSREG_MHPMCOUNTER26 }, "mhpmcounter26", { .raw_val = RISCV_SYSREG_MHPMCOUNTER26 }, "", 0xB1A, {0} , false }, // 291 |
32385 | | { "mhpmcounter27", { .raw_val = RISCV_SYSREG_MHPMCOUNTER27 }, "mhpmcounter27", { .raw_val = RISCV_SYSREG_MHPMCOUNTER27 }, "", 0xB1B, {0} , false }, // 292 |
32386 | | { "mhpmcounter28", { .raw_val = RISCV_SYSREG_MHPMCOUNTER28 }, "mhpmcounter28", { .raw_val = RISCV_SYSREG_MHPMCOUNTER28 }, "", 0xB1C, {0} , false }, // 293 |
32387 | | { "mhpmcounter29", { .raw_val = RISCV_SYSREG_MHPMCOUNTER29 }, "mhpmcounter29", { .raw_val = RISCV_SYSREG_MHPMCOUNTER29 }, "", 0xB1D, {0} , false }, // 294 |
32388 | | { "mhpmcounter30", { .raw_val = RISCV_SYSREG_MHPMCOUNTER30 }, "mhpmcounter30", { .raw_val = RISCV_SYSREG_MHPMCOUNTER30 }, "", 0xB1E, {0} , false }, // 295 |
32389 | | { "mhpmcounter31", { .raw_val = RISCV_SYSREG_MHPMCOUNTER31 }, "mhpmcounter31", { .raw_val = RISCV_SYSREG_MHPMCOUNTER31 }, "", 0xB1F, {0} , false }, // 296 |
32390 | | { "mcycleh", { .raw_val = RISCV_SYSREG_MCYCLEH }, "mcycleh", { .raw_val = RISCV_SYSREG_MCYCLEH }, "", 0xB80, {0} , true }, // 297 |
32391 | | { "minstreth", { .raw_val = RISCV_SYSREG_MINSTRETH }, "minstreth", { .raw_val = RISCV_SYSREG_MINSTRETH }, "", 0xB82, {0} , true }, // 298 |
32392 | | { "mhpmcounter3h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER3H }, "mhpmcounter3h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER3H }, "", 0xB83, {0} , true }, // 299 |
32393 | | { "mhpmcounter4h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER4H }, "mhpmcounter4h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER4H }, "", 0xB84, {0} , true }, // 300 |
32394 | | { "mhpmcounter5h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER5H }, "mhpmcounter5h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER5H }, "", 0xB85, {0} , true }, // 301 |
32395 | | { "mhpmcounter6h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER6H }, "mhpmcounter6h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER6H }, "", 0xB86, {0} , true }, // 302 |
32396 | | { "mhpmcounter7h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER7H }, "mhpmcounter7h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER7H }, "", 0xB87, {0} , true }, // 303 |
32397 | | { "mhpmcounter8h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER8H }, "mhpmcounter8h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER8H }, "", 0xB88, {0} , true }, // 304 |
32398 | | { "mhpmcounter9h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER9H }, "mhpmcounter9h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER9H }, "", 0xB89, {0} , true }, // 305 |
32399 | | { "mhpmcounter10h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER10H }, "mhpmcounter10h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER10H }, "", 0xB8A, {0} , true }, // 306 |
32400 | | { "mhpmcounter11h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER11H }, "mhpmcounter11h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER11H }, "", 0xB8B, {0} , true }, // 307 |
32401 | | { "mhpmcounter12h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER12H }, "mhpmcounter12h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER12H }, "", 0xB8C, {0} , true }, // 308 |
32402 | | { "mhpmcounter13h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER13H }, "mhpmcounter13h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER13H }, "", 0xB8D, {0} , true }, // 309 |
32403 | | { "mhpmcounter14h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER14H }, "mhpmcounter14h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER14H }, "", 0xB8E, {0} , true }, // 310 |
32404 | | { "mhpmcounter15h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER15H }, "mhpmcounter15h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER15H }, "", 0xB8F, {0} , true }, // 311 |
32405 | | { "mhpmcounter16h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER16H }, "mhpmcounter16h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER16H }, "", 0xB90, {0} , true }, // 312 |
32406 | | { "mhpmcounter17h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER17H }, "mhpmcounter17h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER17H }, "", 0xB91, {0} , true }, // 313 |
32407 | | { "mhpmcounter18h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER18H }, "mhpmcounter18h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER18H }, "", 0xB92, {0} , true }, // 314 |
32408 | | { "mhpmcounter19h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER19H }, "mhpmcounter19h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER19H }, "", 0xB93, {0} , true }, // 315 |
32409 | | { "mhpmcounter20h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER20H }, "mhpmcounter20h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER20H }, "", 0xB94, {0} , true }, // 316 |
32410 | | { "mhpmcounter21h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER21H }, "mhpmcounter21h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER21H }, "", 0xB95, {0} , true }, // 317 |
32411 | | { "mhpmcounter22h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER22H }, "mhpmcounter22h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER22H }, "", 0xB96, {0} , true }, // 318 |
32412 | | { "mhpmcounter23h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER23H }, "mhpmcounter23h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER23H }, "", 0xB97, {0} , true }, // 319 |
32413 | | { "mhpmcounter24h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER24H }, "mhpmcounter24h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER24H }, "", 0xB98, {0} , true }, // 320 |
32414 | | { "mhpmcounter25h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER25H }, "mhpmcounter25h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER25H }, "", 0xB99, {0} , true }, // 321 |
32415 | | { "mhpmcounter26h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER26H }, "mhpmcounter26h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER26H }, "", 0xB9A, {0} , true }, // 322 |
32416 | | { "mhpmcounter27h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER27H }, "mhpmcounter27h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER27H }, "", 0xB9B, {0} , true }, // 323 |
32417 | | { "mhpmcounter28h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER28H }, "mhpmcounter28h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER28H }, "", 0xB9C, {0} , true }, // 324 |
32418 | | { "mhpmcounter29h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER29H }, "mhpmcounter29h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER29H }, "", 0xB9D, {0} , true }, // 325 |
32419 | | { "mhpmcounter30h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER30H }, "mhpmcounter30h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER30H }, "", 0xB9E, {0} , true }, // 326 |
32420 | | { "mhpmcounter31h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER31H }, "mhpmcounter31h", { .raw_val = RISCV_SYSREG_MHPMCOUNTER31H }, "", 0xB9F, {0} , true }, // 327 |
32421 | | { "cycle", { .raw_val = RISCV_SYSREG_CYCLE }, "cycle", { .raw_val = RISCV_SYSREG_CYCLE }, "", 0xC00, {0} , false }, // 328 |
32422 | | { "time", { .raw_val = RISCV_SYSREG_TIME }, "time", { .raw_val = RISCV_SYSREG_TIME }, "", 0xC01, {0} , false }, // 329 |
32423 | | { "instret", { .raw_val = RISCV_SYSREG_INSTRET }, "instret", { .raw_val = RISCV_SYSREG_INSTRET }, "", 0xC02, {0} , false }, // 330 |
32424 | | { "hpmcounter3", { .raw_val = RISCV_SYSREG_HPMCOUNTER3 }, "hpmcounter3", { .raw_val = RISCV_SYSREG_HPMCOUNTER3 }, "", 0xC03, {0} , false }, // 331 |
32425 | | { "hpmcounter4", { .raw_val = RISCV_SYSREG_HPMCOUNTER4 }, "hpmcounter4", { .raw_val = RISCV_SYSREG_HPMCOUNTER4 }, "", 0xC04, {0} , false }, // 332 |
32426 | | { "hpmcounter5", { .raw_val = RISCV_SYSREG_HPMCOUNTER5 }, "hpmcounter5", { .raw_val = RISCV_SYSREG_HPMCOUNTER5 }, "", 0xC05, {0} , false }, // 333 |
32427 | | { "hpmcounter6", { .raw_val = RISCV_SYSREG_HPMCOUNTER6 }, "hpmcounter6", { .raw_val = RISCV_SYSREG_HPMCOUNTER6 }, "", 0xC06, {0} , false }, // 334 |
32428 | | { "hpmcounter7", { .raw_val = RISCV_SYSREG_HPMCOUNTER7 }, "hpmcounter7", { .raw_val = RISCV_SYSREG_HPMCOUNTER7 }, "", 0xC07, {0} , false }, // 335 |
32429 | | { "hpmcounter8", { .raw_val = RISCV_SYSREG_HPMCOUNTER8 }, "hpmcounter8", { .raw_val = RISCV_SYSREG_HPMCOUNTER8 }, "", 0xC08, {0} , false }, // 336 |
32430 | | { "hpmcounter9", { .raw_val = RISCV_SYSREG_HPMCOUNTER9 }, "hpmcounter9", { .raw_val = RISCV_SYSREG_HPMCOUNTER9 }, "", 0xC09, {0} , false }, // 337 |
32431 | | { "hpmcounter10", { .raw_val = RISCV_SYSREG_HPMCOUNTER10 }, "hpmcounter10", { .raw_val = RISCV_SYSREG_HPMCOUNTER10 }, "", 0xC0A, {0} , false }, // 338 |
32432 | | { "hpmcounter11", { .raw_val = RISCV_SYSREG_HPMCOUNTER11 }, "hpmcounter11", { .raw_val = RISCV_SYSREG_HPMCOUNTER11 }, "", 0xC0B, {0} , false }, // 339 |
32433 | | { "hpmcounter12", { .raw_val = RISCV_SYSREG_HPMCOUNTER12 }, "hpmcounter12", { .raw_val = RISCV_SYSREG_HPMCOUNTER12 }, "", 0xC0C, {0} , false }, // 340 |
32434 | | { "hpmcounter13", { .raw_val = RISCV_SYSREG_HPMCOUNTER13 }, "hpmcounter13", { .raw_val = RISCV_SYSREG_HPMCOUNTER13 }, "", 0xC0D, {0} , false }, // 341 |
32435 | | { "hpmcounter14", { .raw_val = RISCV_SYSREG_HPMCOUNTER14 }, "hpmcounter14", { .raw_val = RISCV_SYSREG_HPMCOUNTER14 }, "", 0xC0E, {0} , false }, // 342 |
32436 | | { "hpmcounter15", { .raw_val = RISCV_SYSREG_HPMCOUNTER15 }, "hpmcounter15", { .raw_val = RISCV_SYSREG_HPMCOUNTER15 }, "", 0xC0F, {0} , false }, // 343 |
32437 | | { "hpmcounter16", { .raw_val = RISCV_SYSREG_HPMCOUNTER16 }, "hpmcounter16", { .raw_val = RISCV_SYSREG_HPMCOUNTER16 }, "", 0xC10, {0} , false }, // 344 |
32438 | | { "hpmcounter17", { .raw_val = RISCV_SYSREG_HPMCOUNTER17 }, "hpmcounter17", { .raw_val = RISCV_SYSREG_HPMCOUNTER17 }, "", 0xC11, {0} , false }, // 345 |
32439 | | { "hpmcounter18", { .raw_val = RISCV_SYSREG_HPMCOUNTER18 }, "hpmcounter18", { .raw_val = RISCV_SYSREG_HPMCOUNTER18 }, "", 0xC12, {0} , false }, // 346 |
32440 | | { "hpmcounter19", { .raw_val = RISCV_SYSREG_HPMCOUNTER19 }, "hpmcounter19", { .raw_val = RISCV_SYSREG_HPMCOUNTER19 }, "", 0xC13, {0} , false }, // 347 |
32441 | | { "hpmcounter20", { .raw_val = RISCV_SYSREG_HPMCOUNTER20 }, "hpmcounter20", { .raw_val = RISCV_SYSREG_HPMCOUNTER20 }, "", 0xC14, {0} , false }, // 348 |
32442 | | { "hpmcounter21", { .raw_val = RISCV_SYSREG_HPMCOUNTER21 }, "hpmcounter21", { .raw_val = RISCV_SYSREG_HPMCOUNTER21 }, "", 0xC15, {0} , false }, // 349 |
32443 | | { "hpmcounter22", { .raw_val = RISCV_SYSREG_HPMCOUNTER22 }, "hpmcounter22", { .raw_val = RISCV_SYSREG_HPMCOUNTER22 }, "", 0xC16, {0} , false }, // 350 |
32444 | | { "hpmcounter23", { .raw_val = RISCV_SYSREG_HPMCOUNTER23 }, "hpmcounter23", { .raw_val = RISCV_SYSREG_HPMCOUNTER23 }, "", 0xC17, {0} , false }, // 351 |
32445 | | { "hpmcounter24", { .raw_val = RISCV_SYSREG_HPMCOUNTER24 }, "hpmcounter24", { .raw_val = RISCV_SYSREG_HPMCOUNTER24 }, "", 0xC18, {0} , false }, // 352 |
32446 | | { "hpmcounter25", { .raw_val = RISCV_SYSREG_HPMCOUNTER25 }, "hpmcounter25", { .raw_val = RISCV_SYSREG_HPMCOUNTER25 }, "", 0xC19, {0} , false }, // 353 |
32447 | | { "hpmcounter26", { .raw_val = RISCV_SYSREG_HPMCOUNTER26 }, "hpmcounter26", { .raw_val = RISCV_SYSREG_HPMCOUNTER26 }, "", 0xC1A, {0} , false }, // 354 |
32448 | | { "hpmcounter27", { .raw_val = RISCV_SYSREG_HPMCOUNTER27 }, "hpmcounter27", { .raw_val = RISCV_SYSREG_HPMCOUNTER27 }, "", 0xC1B, {0} , false }, // 355 |
32449 | | { "hpmcounter28", { .raw_val = RISCV_SYSREG_HPMCOUNTER28 }, "hpmcounter28", { .raw_val = RISCV_SYSREG_HPMCOUNTER28 }, "", 0xC1C, {0} , false }, // 356 |
32450 | | { "hpmcounter29", { .raw_val = RISCV_SYSREG_HPMCOUNTER29 }, "hpmcounter29", { .raw_val = RISCV_SYSREG_HPMCOUNTER29 }, "", 0xC1D, {0} , false }, // 357 |
32451 | | { "hpmcounter30", { .raw_val = RISCV_SYSREG_HPMCOUNTER30 }, "hpmcounter30", { .raw_val = RISCV_SYSREG_HPMCOUNTER30 }, "", 0xC1E, {0} , false }, // 358 |
32452 | | { "hpmcounter31", { .raw_val = RISCV_SYSREG_HPMCOUNTER31 }, "hpmcounter31", { .raw_val = RISCV_SYSREG_HPMCOUNTER31 }, "", 0xC1F, {0} , false }, // 359 |
32453 | | { "vl", { .raw_val = RISCV_SYSREG_VL }, "vl", { .raw_val = RISCV_SYSREG_VL }, "", 0xC20, {0} , false }, // 360 |
32454 | | { "vtype", { .raw_val = RISCV_SYSREG_VTYPE }, "vtype", { .raw_val = RISCV_SYSREG_VTYPE }, "", 0xC21, {0} , false }, // 361 |
32455 | | { "vlenb", { .raw_val = RISCV_SYSREG_VLENB }, "vlenb", { .raw_val = RISCV_SYSREG_VLENB }, "", 0xC22, {0} , false }, // 362 |
32456 | | { "cycleh", { .raw_val = RISCV_SYSREG_CYCLEH }, "cycleh", { .raw_val = RISCV_SYSREG_CYCLEH }, "", 0xC80, {0} , true }, // 363 |
32457 | | { "timeh", { .raw_val = RISCV_SYSREG_TIMEH }, "timeh", { .raw_val = RISCV_SYSREG_TIMEH }, "", 0xC81, {0} , true }, // 364 |
32458 | | { "instreth", { .raw_val = RISCV_SYSREG_INSTRETH }, "instreth", { .raw_val = RISCV_SYSREG_INSTRETH }, "", 0xC82, {0} , true }, // 365 |
32459 | | { "hpmcounter3h", { .raw_val = RISCV_SYSREG_HPMCOUNTER3H }, "hpmcounter3h", { .raw_val = RISCV_SYSREG_HPMCOUNTER3H }, "", 0xC83, {0} , true }, // 366 |
32460 | | { "hpmcounter4h", { .raw_val = RISCV_SYSREG_HPMCOUNTER4H }, "hpmcounter4h", { .raw_val = RISCV_SYSREG_HPMCOUNTER4H }, "", 0xC84, {0} , true }, // 367 |
32461 | | { "hpmcounter5h", { .raw_val = RISCV_SYSREG_HPMCOUNTER5H }, "hpmcounter5h", { .raw_val = RISCV_SYSREG_HPMCOUNTER5H }, "", 0xC85, {0} , true }, // 368 |
32462 | | { "hpmcounter6h", { .raw_val = RISCV_SYSREG_HPMCOUNTER6H }, "hpmcounter6h", { .raw_val = RISCV_SYSREG_HPMCOUNTER6H }, "", 0xC86, {0} , true }, // 369 |
32463 | | { "hpmcounter7h", { .raw_val = RISCV_SYSREG_HPMCOUNTER7H }, "hpmcounter7h", { .raw_val = RISCV_SYSREG_HPMCOUNTER7H }, "", 0xC87, {0} , true }, // 370 |
32464 | | { "hpmcounter8h", { .raw_val = RISCV_SYSREG_HPMCOUNTER8H }, "hpmcounter8h", { .raw_val = RISCV_SYSREG_HPMCOUNTER8H }, "", 0xC88, {0} , true }, // 371 |
32465 | | { "hpmcounter9h", { .raw_val = RISCV_SYSREG_HPMCOUNTER9H }, "hpmcounter9h", { .raw_val = RISCV_SYSREG_HPMCOUNTER9H }, "", 0xC89, {0} , true }, // 372 |
32466 | | { "hpmcounter10h", { .raw_val = RISCV_SYSREG_HPMCOUNTER10H }, "hpmcounter10h", { .raw_val = RISCV_SYSREG_HPMCOUNTER10H }, "", 0xC8A, {0} , true }, // 373 |
32467 | | { "hpmcounter11h", { .raw_val = RISCV_SYSREG_HPMCOUNTER11H }, "hpmcounter11h", { .raw_val = RISCV_SYSREG_HPMCOUNTER11H }, "", 0xC8B, {0} , true }, // 374 |
32468 | | { "hpmcounter12h", { .raw_val = RISCV_SYSREG_HPMCOUNTER12H }, "hpmcounter12h", { .raw_val = RISCV_SYSREG_HPMCOUNTER12H }, "", 0xC8C, {0} , true }, // 375 |
32469 | | { "hpmcounter13h", { .raw_val = RISCV_SYSREG_HPMCOUNTER13H }, "hpmcounter13h", { .raw_val = RISCV_SYSREG_HPMCOUNTER13H }, "", 0xC8D, {0} , true }, // 376 |
32470 | | { "hpmcounter14h", { .raw_val = RISCV_SYSREG_HPMCOUNTER14H }, "hpmcounter14h", { .raw_val = RISCV_SYSREG_HPMCOUNTER14H }, "", 0xC8E, {0} , true }, // 377 |
32471 | | { "hpmcounter15h", { .raw_val = RISCV_SYSREG_HPMCOUNTER15H }, "hpmcounter15h", { .raw_val = RISCV_SYSREG_HPMCOUNTER15H }, "", 0xC8F, {0} , true }, // 378 |
32472 | | { "hpmcounter16h", { .raw_val = RISCV_SYSREG_HPMCOUNTER16H }, "hpmcounter16h", { .raw_val = RISCV_SYSREG_HPMCOUNTER16H }, "", 0xC90, {0} , true }, // 379 |
32473 | | { "hpmcounter17h", { .raw_val = RISCV_SYSREG_HPMCOUNTER17H }, "hpmcounter17h", { .raw_val = RISCV_SYSREG_HPMCOUNTER17H }, "", 0xC91, {0} , true }, // 380 |
32474 | | { "hpmcounter18h", { .raw_val = RISCV_SYSREG_HPMCOUNTER18H }, "hpmcounter18h", { .raw_val = RISCV_SYSREG_HPMCOUNTER18H }, "", 0xC92, {0} , true }, // 381 |
32475 | | { "hpmcounter19h", { .raw_val = RISCV_SYSREG_HPMCOUNTER19H }, "hpmcounter19h", { .raw_val = RISCV_SYSREG_HPMCOUNTER19H }, "", 0xC93, {0} , true }, // 382 |
32476 | | { "hpmcounter20h", { .raw_val = RISCV_SYSREG_HPMCOUNTER20H }, "hpmcounter20h", { .raw_val = RISCV_SYSREG_HPMCOUNTER20H }, "", 0xC94, {0} , true }, // 383 |
32477 | | { "hpmcounter21h", { .raw_val = RISCV_SYSREG_HPMCOUNTER21H }, "hpmcounter21h", { .raw_val = RISCV_SYSREG_HPMCOUNTER21H }, "", 0xC95, {0} , true }, // 384 |
32478 | | { "hpmcounter22h", { .raw_val = RISCV_SYSREG_HPMCOUNTER22H }, "hpmcounter22h", { .raw_val = RISCV_SYSREG_HPMCOUNTER22H }, "", 0xC96, {0} , true }, // 385 |
32479 | | { "hpmcounter23h", { .raw_val = RISCV_SYSREG_HPMCOUNTER23H }, "hpmcounter23h", { .raw_val = RISCV_SYSREG_HPMCOUNTER23H }, "", 0xC97, {0} , true }, // 386 |
32480 | | { "hpmcounter24h", { .raw_val = RISCV_SYSREG_HPMCOUNTER24H }, "hpmcounter24h", { .raw_val = RISCV_SYSREG_HPMCOUNTER24H }, "", 0xC98, {0} , true }, // 387 |
32481 | | { "hpmcounter25h", { .raw_val = RISCV_SYSREG_HPMCOUNTER25H }, "hpmcounter25h", { .raw_val = RISCV_SYSREG_HPMCOUNTER25H }, "", 0xC99, {0} , true }, // 388 |
32482 | | { "hpmcounter26h", { .raw_val = RISCV_SYSREG_HPMCOUNTER26H }, "hpmcounter26h", { .raw_val = RISCV_SYSREG_HPMCOUNTER26H }, "", 0xC9A, {0} , true }, // 389 |
32483 | | { "hpmcounter27h", { .raw_val = RISCV_SYSREG_HPMCOUNTER27H }, "hpmcounter27h", { .raw_val = RISCV_SYSREG_HPMCOUNTER27H }, "", 0xC9B, {0} , true }, // 390 |
32484 | | { "hpmcounter28h", { .raw_val = RISCV_SYSREG_HPMCOUNTER28H }, "hpmcounter28h", { .raw_val = RISCV_SYSREG_HPMCOUNTER28H }, "", 0xC9C, {0} , true }, // 391 |
32485 | | { "hpmcounter29h", { .raw_val = RISCV_SYSREG_HPMCOUNTER29H }, "hpmcounter29h", { .raw_val = RISCV_SYSREG_HPMCOUNTER29H }, "", 0xC9D, {0} , true }, // 392 |
32486 | | { "hpmcounter30h", { .raw_val = RISCV_SYSREG_HPMCOUNTER30H }, "hpmcounter30h", { .raw_val = RISCV_SYSREG_HPMCOUNTER30H }, "", 0xC9E, {0} , true }, // 393 |
32487 | | { "hpmcounter31h", { .raw_val = RISCV_SYSREG_HPMCOUNTER31H }, "hpmcounter31h", { .raw_val = RISCV_SYSREG_HPMCOUNTER31H }, "", 0xC9F, {0} , true }, // 394 |
32488 | | { "scountovf", { .raw_val = RISCV_SYSREG_SCOUNTOVF }, "scountovf", { .raw_val = RISCV_SYSREG_SCOUNTOVF }, "", 0xDA0, {0} , false }, // 395 |
32489 | | { "stopi", { .raw_val = RISCV_SYSREG_STOPI }, "stopi", { .raw_val = RISCV_SYSREG_STOPI }, "", 0xDB0, {0} , false }, // 396 |
32490 | | { "hgeip", { .raw_val = RISCV_SYSREG_HGEIP }, "hgeip", { .raw_val = RISCV_SYSREG_HGEIP }, "", 0xE12, {0} , false }, // 397 |
32491 | | { "vstopi", { .raw_val = RISCV_SYSREG_VSTOPI }, "vstopi", { .raw_val = RISCV_SYSREG_VSTOPI }, "", 0xEB0, {0} , false }, // 398 |
32492 | | { "mvendorid", { .raw_val = RISCV_SYSREG_MVENDORID }, "mvendorid", { .raw_val = RISCV_SYSREG_MVENDORID }, "", 0xF11, {0} , false }, // 399 |
32493 | | { "marchid", { .raw_val = RISCV_SYSREG_MARCHID }, "marchid", { .raw_val = RISCV_SYSREG_MARCHID }, "", 0xF12, {0} , false }, // 400 |
32494 | | { "mimpid", { .raw_val = RISCV_SYSREG_MIMPID }, "mimpid", { .raw_val = RISCV_SYSREG_MIMPID }, "", 0xF13, {0} , false }, // 401 |
32495 | | { "mhartid", { .raw_val = RISCV_SYSREG_MHARTID }, "mhartid", { .raw_val = RISCV_SYSREG_MHARTID }, "", 0xF14, {0} , false }, // 402 |
32496 | | { "mconfigptr", { .raw_val = RISCV_SYSREG_MCONFIGPTR }, "mconfigptr", { .raw_val = RISCV_SYSREG_MCONFIGPTR }, "", 0xF15, {0} , false }, // 403 |
32497 | | { "mtopi", { .raw_val = RISCV_SYSREG_MTOPI }, "mtopi", { .raw_val = RISCV_SYSREG_MTOPI }, "", 0xFB0, {0} , false }, // 404 |
32498 | | }; |
32499 | | |
32500 | 2.53k | const RISCV_SysReg *RISCV_lookupSysRegByEncoding(uint16_t Encoding) { |
32501 | 2.53k | static const struct IndexType Index[] = { |
32502 | 2.53k | {1,0}, |
32503 | 2.53k | {2,1}, |
32504 | 2.53k | {3,2}, |
32505 | 2.53k | {8,3}, |
32506 | 2.53k | {9,4}, |
32507 | 2.53k | {10,5}, |
32508 | 2.53k | {15,6}, |
32509 | 2.53k | {21,7}, |
32510 | 2.53k | {23,8}, |
32511 | 2.53k | {256,9}, |
32512 | 2.53k | {260,10}, |
32513 | 2.53k | {261,11}, |
32514 | 2.53k | {262,12}, |
32515 | 2.53k | {266,13}, |
32516 | 2.53k | {268,14}, |
32517 | 2.53k | {269,15}, |
32518 | 2.53k | {270,16}, |
32519 | 2.53k | {271,17}, |
32520 | 2.53k | {276,18}, |
32521 | 2.53k | {320,19}, |
32522 | 2.53k | {321,20}, |
32523 | 2.53k | {322,21}, |
32524 | 2.53k | {323,22}, |
32525 | 2.53k | {324,23}, |
32526 | 2.53k | {333,24}, |
32527 | 2.53k | {336,25}, |
32528 | 2.53k | {337,26}, |
32529 | 2.53k | {340,27}, |
32530 | 2.53k | {348,28}, |
32531 | 2.53k | {349,29}, |
32532 | 2.53k | {384,30}, |
32533 | 2.53k | {512,31}, |
32534 | 2.53k | {516,32}, |
32535 | 2.53k | {517,33}, |
32536 | 2.53k | {532,34}, |
32537 | 2.53k | {576,35}, |
32538 | 2.53k | {577,36}, |
32539 | 2.53k | {578,37}, |
32540 | 2.53k | {579,38}, |
32541 | 2.53k | {580,39}, |
32542 | 2.53k | {589,40}, |
32543 | 2.53k | {592,41}, |
32544 | 2.53k | {593,42}, |
32545 | 2.53k | {596,43}, |
32546 | 2.53k | {604,44}, |
32547 | 2.53k | {605,45}, |
32548 | 2.53k | {640,46}, |
32549 | 2.53k | {768,47}, |
32550 | 2.53k | {769,48}, |
32551 | 2.53k | {770,49}, |
32552 | 2.53k | {771,50}, |
32553 | 2.53k | {772,51}, |
32554 | 2.53k | {773,52}, |
32555 | 2.53k | {774,53}, |
32556 | 2.53k | {776,54}, |
32557 | 2.53k | {777,55}, |
32558 | 2.53k | {778,56}, |
32559 | 2.53k | {780,57}, |
32560 | 2.53k | {781,58}, |
32561 | 2.53k | {782,59}, |
32562 | 2.53k | {783,60}, |
32563 | 2.53k | {784,61}, |
32564 | 2.53k | {787,62}, |
32565 | 2.53k | {788,63}, |
32566 | 2.53k | {792,64}, |
32567 | 2.53k | {793,65}, |
32568 | 2.53k | {794,66}, |
32569 | 2.53k | {796,67}, |
32570 | 2.53k | {797,68}, |
32571 | 2.53k | {798,69}, |
32572 | 2.53k | {799,70}, |
32573 | 2.53k | {800,71}, |
32574 | 2.53k | {803,72}, |
32575 | 2.53k | {804,73}, |
32576 | 2.53k | {805,74}, |
32577 | 2.53k | {806,75}, |
32578 | 2.53k | {807,76}, |
32579 | 2.53k | {808,77}, |
32580 | 2.53k | {809,78}, |
32581 | 2.53k | {810,79}, |
32582 | 2.53k | {811,80}, |
32583 | 2.53k | {812,81}, |
32584 | 2.53k | {813,82}, |
32585 | 2.53k | {814,83}, |
32586 | 2.53k | {815,84}, |
32587 | 2.53k | {816,85}, |
32588 | 2.53k | {817,86}, |
32589 | 2.53k | {818,87}, |
32590 | 2.53k | {819,88}, |
32591 | 2.53k | {820,89}, |
32592 | 2.53k | {821,90}, |
32593 | 2.53k | {822,91}, |
32594 | 2.53k | {823,92}, |
32595 | 2.53k | {824,93}, |
32596 | 2.53k | {825,94}, |
32597 | 2.53k | {826,95}, |
32598 | 2.53k | {827,96}, |
32599 | 2.53k | {828,97}, |
32600 | 2.53k | {829,98}, |
32601 | 2.53k | {830,99}, |
32602 | 2.53k | {831,100}, |
32603 | 2.53k | {832,101}, |
32604 | 2.53k | {833,102}, |
32605 | 2.53k | {834,103}, |
32606 | 2.53k | {835,104}, |
32607 | 2.53k | {836,105}, |
32608 | 2.53k | {842,106}, |
32609 | 2.53k | {843,107}, |
32610 | 2.53k | {848,108}, |
32611 | 2.53k | {849,109}, |
32612 | 2.53k | {852,110}, |
32613 | 2.53k | {860,111}, |
32614 | 2.53k | {928,112}, |
32615 | 2.53k | {929,113}, |
32616 | 2.53k | {930,114}, |
32617 | 2.53k | {931,115}, |
32618 | 2.53k | {932,116}, |
32619 | 2.53k | {933,117}, |
32620 | 2.53k | {934,118}, |
32621 | 2.53k | {935,119}, |
32622 | 2.53k | {936,120}, |
32623 | 2.53k | {937,121}, |
32624 | 2.53k | {938,122}, |
32625 | 2.53k | {939,123}, |
32626 | 2.53k | {940,124}, |
32627 | 2.53k | {941,125}, |
32628 | 2.53k | {942,126}, |
32629 | 2.53k | {943,127}, |
32630 | 2.53k | {944,128}, |
32631 | 2.53k | {945,129}, |
32632 | 2.53k | {946,130}, |
32633 | 2.53k | {947,131}, |
32634 | 2.53k | {948,132}, |
32635 | 2.53k | {949,133}, |
32636 | 2.53k | {950,134}, |
32637 | 2.53k | {951,135}, |
32638 | 2.53k | {952,136}, |
32639 | 2.53k | {953,137}, |
32640 | 2.53k | {954,138}, |
32641 | 2.53k | {955,139}, |
32642 | 2.53k | {956,140}, |
32643 | 2.53k | {957,141}, |
32644 | 2.53k | {958,142}, |
32645 | 2.53k | {959,143}, |
32646 | 2.53k | {960,144}, |
32647 | 2.53k | {961,145}, |
32648 | 2.53k | {962,146}, |
32649 | 2.53k | {963,147}, |
32650 | 2.53k | {964,148}, |
32651 | 2.53k | {965,149}, |
32652 | 2.53k | {966,150}, |
32653 | 2.53k | {967,151}, |
32654 | 2.53k | {968,152}, |
32655 | 2.53k | {969,153}, |
32656 | 2.53k | {970,154}, |
32657 | 2.53k | {971,155}, |
32658 | 2.53k | {972,156}, |
32659 | 2.53k | {973,157}, |
32660 | 2.53k | {974,158}, |
32661 | 2.53k | {975,159}, |
32662 | 2.53k | {976,160}, |
32663 | 2.53k | {977,161}, |
32664 | 2.53k | {978,162}, |
32665 | 2.53k | {979,163}, |
32666 | 2.53k | {980,164}, |
32667 | 2.53k | {981,165}, |
32668 | 2.53k | {982,166}, |
32669 | 2.53k | {983,167}, |
32670 | 2.53k | {984,168}, |
32671 | 2.53k | {985,169}, |
32672 | 2.53k | {986,170}, |
32673 | 2.53k | {987,171}, |
32674 | 2.53k | {988,172}, |
32675 | 2.53k | {989,173}, |
32676 | 2.53k | {990,174}, |
32677 | 2.53k | {991,175}, |
32678 | 2.53k | {992,176}, |
32679 | 2.53k | {993,177}, |
32680 | 2.53k | {994,178}, |
32681 | 2.53k | {995,179}, |
32682 | 2.53k | {996,180}, |
32683 | 2.53k | {997,181}, |
32684 | 2.53k | {998,182}, |
32685 | 2.53k | {999,183}, |
32686 | 2.53k | {1000,184}, |
32687 | 2.53k | {1001,185}, |
32688 | 2.53k | {1002,186}, |
32689 | 2.53k | {1003,187}, |
32690 | 2.53k | {1004,188}, |
32691 | 2.53k | {1005,189}, |
32692 | 2.53k | {1006,190}, |
32693 | 2.53k | {1007,191}, |
32694 | 2.53k | {1448,192}, |
32695 | 2.53k | {1536,193}, |
32696 | 2.53k | {1538,194}, |
32697 | 2.53k | {1539,195}, |
32698 | 2.53k | {1540,196}, |
32699 | 2.53k | {1541,197}, |
32700 | 2.53k | {1542,198}, |
32701 | 2.53k | {1543,199}, |
32702 | 2.53k | {1544,200}, |
32703 | 2.53k | {1545,201}, |
32704 | 2.53k | {1546,202}, |
32705 | 2.53k | {1548,203}, |
32706 | 2.53k | {1549,204}, |
32707 | 2.53k | {1550,205}, |
32708 | 2.53k | {1551,206}, |
32709 | 2.53k | {1555,207}, |
32710 | 2.53k | {1557,208}, |
32711 | 2.53k | {1560,209}, |
32712 | 2.53k | {1562,210}, |
32713 | 2.53k | {1564,211}, |
32714 | 2.53k | {1565,212}, |
32715 | 2.53k | {1566,213}, |
32716 | 2.53k | {1567,214}, |
32717 | 2.53k | {1603,215}, |
32718 | 2.53k | {1604,216}, |
32719 | 2.53k | {1605,217}, |
32720 | 2.53k | {1606,218}, |
32721 | 2.53k | {1607,219}, |
32722 | 2.53k | {1610,220}, |
32723 | 2.53k | {1621,221}, |
32724 | 2.53k | {1622,222}, |
32725 | 2.53k | {1623,223}, |
32726 | 2.53k | {1664,224}, |
32727 | 2.53k | {1704,225}, |
32728 | 2.53k | {1827,226}, |
32729 | 2.53k | {1828,227}, |
32730 | 2.53k | {1829,228}, |
32731 | 2.53k | {1830,229}, |
32732 | 2.53k | {1831,230}, |
32733 | 2.53k | {1832,231}, |
32734 | 2.53k | {1833,232}, |
32735 | 2.53k | {1834,233}, |
32736 | 2.53k | {1835,234}, |
32737 | 2.53k | {1836,235}, |
32738 | 2.53k | {1837,236}, |
32739 | 2.53k | {1838,237}, |
32740 | 2.53k | {1839,238}, |
32741 | 2.53k | {1840,239}, |
32742 | 2.53k | {1841,240}, |
32743 | 2.53k | {1842,241}, |
32744 | 2.53k | {1843,242}, |
32745 | 2.53k | {1844,243}, |
32746 | 2.53k | {1845,244}, |
32747 | 2.53k | {1846,245}, |
32748 | 2.53k | {1847,246}, |
32749 | 2.53k | {1848,247}, |
32750 | 2.53k | {1849,248}, |
32751 | 2.53k | {1850,249}, |
32752 | 2.53k | {1851,250}, |
32753 | 2.53k | {1852,251}, |
32754 | 2.53k | {1853,252}, |
32755 | 2.53k | {1854,253}, |
32756 | 2.53k | {1855,254}, |
32757 | 2.53k | {1863,255}, |
32758 | 2.53k | {1879,256}, |
32759 | 2.53k | {1952,257}, |
32760 | 2.53k | {1953,258}, |
32761 | 2.53k | {1954,259}, |
32762 | 2.53k | {1955,260}, |
32763 | 2.53k | {1960,261}, |
32764 | 2.53k | {1968,262}, |
32765 | 2.53k | {1969,263}, |
32766 | 2.53k | {1970,264}, |
32767 | 2.53k | {1971,265}, |
32768 | 2.53k | {2816,266}, |
32769 | 2.53k | {2818,267}, |
32770 | 2.53k | {2819,268}, |
32771 | 2.53k | {2820,269}, |
32772 | 2.53k | {2821,270}, |
32773 | 2.53k | {2822,271}, |
32774 | 2.53k | {2823,272}, |
32775 | 2.53k | {2824,273}, |
32776 | 2.53k | {2825,274}, |
32777 | 2.53k | {2826,275}, |
32778 | 2.53k | {2827,276}, |
32779 | 2.53k | {2828,277}, |
32780 | 2.53k | {2829,278}, |
32781 | 2.53k | {2830,279}, |
32782 | 2.53k | {2831,280}, |
32783 | 2.53k | {2832,281}, |
32784 | 2.53k | {2833,282}, |
32785 | 2.53k | {2834,283}, |
32786 | 2.53k | {2835,284}, |
32787 | 2.53k | {2836,285}, |
32788 | 2.53k | {2837,286}, |
32789 | 2.53k | {2838,287}, |
32790 | 2.53k | {2839,288}, |
32791 | 2.53k | {2840,289}, |
32792 | 2.53k | {2841,290}, |
32793 | 2.53k | {2842,291}, |
32794 | 2.53k | {2843,292}, |
32795 | 2.53k | {2844,293}, |
32796 | 2.53k | {2845,294}, |
32797 | 2.53k | {2846,295}, |
32798 | 2.53k | {2847,296}, |
32799 | 2.53k | {2944,297}, |
32800 | 2.53k | {2946,298}, |
32801 | 2.53k | {2947,299}, |
32802 | 2.53k | {2948,300}, |
32803 | 2.53k | {2949,301}, |
32804 | 2.53k | {2950,302}, |
32805 | 2.53k | {2951,303}, |
32806 | 2.53k | {2952,304}, |
32807 | 2.53k | {2953,305}, |
32808 | 2.53k | {2954,306}, |
32809 | 2.53k | {2955,307}, |
32810 | 2.53k | {2956,308}, |
32811 | 2.53k | {2957,309}, |
32812 | 2.53k | {2958,310}, |
32813 | 2.53k | {2959,311}, |
32814 | 2.53k | {2960,312}, |
32815 | 2.53k | {2961,313}, |
32816 | 2.53k | {2962,314}, |
32817 | 2.53k | {2963,315}, |
32818 | 2.53k | {2964,316}, |
32819 | 2.53k | {2965,317}, |
32820 | 2.53k | {2966,318}, |
32821 | 2.53k | {2967,319}, |
32822 | 2.53k | {2968,320}, |
32823 | 2.53k | {2969,321}, |
32824 | 2.53k | {2970,322}, |
32825 | 2.53k | {2971,323}, |
32826 | 2.53k | {2972,324}, |
32827 | 2.53k | {2973,325}, |
32828 | 2.53k | {2974,326}, |
32829 | 2.53k | {2975,327}, |
32830 | 2.53k | {3072,328}, |
32831 | 2.53k | {3073,329}, |
32832 | 2.53k | {3074,330}, |
32833 | 2.53k | {3075,331}, |
32834 | 2.53k | {3076,332}, |
32835 | 2.53k | {3077,333}, |
32836 | 2.53k | {3078,334}, |
32837 | 2.53k | {3079,335}, |
32838 | 2.53k | {3080,336}, |
32839 | 2.53k | {3081,337}, |
32840 | 2.53k | {3082,338}, |
32841 | 2.53k | {3083,339}, |
32842 | 2.53k | {3084,340}, |
32843 | 2.53k | {3085,341}, |
32844 | 2.53k | {3086,342}, |
32845 | 2.53k | {3087,343}, |
32846 | 2.53k | {3088,344}, |
32847 | 2.53k | {3089,345}, |
32848 | 2.53k | {3090,346}, |
32849 | 2.53k | {3091,347}, |
32850 | 2.53k | {3092,348}, |
32851 | 2.53k | {3093,349}, |
32852 | 2.53k | {3094,350}, |
32853 | 2.53k | {3095,351}, |
32854 | 2.53k | {3096,352}, |
32855 | 2.53k | {3097,353}, |
32856 | 2.53k | {3098,354}, |
32857 | 2.53k | {3099,355}, |
32858 | 2.53k | {3100,356}, |
32859 | 2.53k | {3101,357}, |
32860 | 2.53k | {3102,358}, |
32861 | 2.53k | {3103,359}, |
32862 | 2.53k | {3104,360}, |
32863 | 2.53k | {3105,361}, |
32864 | 2.53k | {3106,362}, |
32865 | 2.53k | {3200,363}, |
32866 | 2.53k | {3201,364}, |
32867 | 2.53k | {3202,365}, |
32868 | 2.53k | {3203,366}, |
32869 | 2.53k | {3204,367}, |
32870 | 2.53k | {3205,368}, |
32871 | 2.53k | {3206,369}, |
32872 | 2.53k | {3207,370}, |
32873 | 2.53k | {3208,371}, |
32874 | 2.53k | {3209,372}, |
32875 | 2.53k | {3210,373}, |
32876 | 2.53k | {3211,374}, |
32877 | 2.53k | {3212,375}, |
32878 | 2.53k | {3213,376}, |
32879 | 2.53k | {3214,377}, |
32880 | 2.53k | {3215,378}, |
32881 | 2.53k | {3216,379}, |
32882 | 2.53k | {3217,380}, |
32883 | 2.53k | {3218,381}, |
32884 | 2.53k | {3219,382}, |
32885 | 2.53k | {3220,383}, |
32886 | 2.53k | {3221,384}, |
32887 | 2.53k | {3222,385}, |
32888 | 2.53k | {3223,386}, |
32889 | 2.53k | {3224,387}, |
32890 | 2.53k | {3225,388}, |
32891 | 2.53k | {3226,389}, |
32892 | 2.53k | {3227,390}, |
32893 | 2.53k | {3228,391}, |
32894 | 2.53k | {3229,392}, |
32895 | 2.53k | {3230,393}, |
32896 | 2.53k | {3231,394}, |
32897 | 2.53k | {3488,395}, |
32898 | 2.53k | {3504,396}, |
32899 | 2.53k | {3602,397}, |
32900 | 2.53k | {3760,398}, |
32901 | 2.53k | {3857,399}, |
32902 | 2.53k | {3858,400}, |
32903 | 2.53k | {3859,401}, |
32904 | 2.53k | {3860,402}, |
32905 | 2.53k | {3861,403}, |
32906 | 2.53k | {4016,404}, |
32907 | 2.53k | }; |
32908 | 2.53k | unsigned i = binsearch_IndexTypeEncoding(Index, ARR_SIZE(Index), Encoding); |
32909 | 2.53k | if (i == -1) |
32910 | 1.07k | return NULL; |
32911 | 1.46k | else |
32912 | 1.46k | return &SysRegsList[Index[i].index]; |
32913 | 2.53k | } |
32914 | | |
32915 | 0 | const RISCV_SysReg *RISCV_lookupSysRegByAltName(const char * AltName) { |
32916 | 0 | static const struct IndexTypeStr Index[] = { |
32917 | 0 | { "CYCLE", 328 }, |
32918 | 0 | { "CYCLEH", 363 }, |
32919 | 0 | { "DCSR", 262 }, |
32920 | 0 | { "DPC", 263 }, |
32921 | 0 | { "DSCRATCH", 264 }, |
32922 | 0 | { "DSCRATCH1", 265 }, |
32923 | 0 | { "FCSR", 2 }, |
32924 | 0 | { "FFLAGS", 0 }, |
32925 | 0 | { "FRM", 1 }, |
32926 | 0 | { "HCONTEXT", 225 }, |
32927 | 0 | { "HCOUNTEREN", 198 }, |
32928 | 0 | { "HEDELEG", 194 }, |
32929 | 0 | { "HENVCFG", 202 }, |
32930 | 0 | { "HENVCFGH", 210 }, |
32931 | 0 | { "HGATP", 224 }, |
32932 | 0 | { "HGEIE", 199 }, |
32933 | 0 | { "HGEIP", 397 }, |
32934 | 0 | { "HIDELEG", 195 }, |
32935 | 0 | { "HIDELEGH", 207 }, |
32936 | 0 | { "HIE", 196 }, |
32937 | 0 | { "HIP", 216 }, |
32938 | 0 | { "HPMCOUNTER10", 338 }, |
32939 | 0 | { "HPMCOUNTER10H", 373 }, |
32940 | 0 | { "HPMCOUNTER11", 339 }, |
32941 | 0 | { "HPMCOUNTER11H", 374 }, |
32942 | 0 | { "HPMCOUNTER12", 340 }, |
32943 | 0 | { "HPMCOUNTER12H", 375 }, |
32944 | 0 | { "HPMCOUNTER13", 341 }, |
32945 | 0 | { "HPMCOUNTER13H", 376 }, |
32946 | 0 | { "HPMCOUNTER14", 342 }, |
32947 | 0 | { "HPMCOUNTER14H", 377 }, |
32948 | 0 | { "HPMCOUNTER15", 343 }, |
32949 | 0 | { "HPMCOUNTER15H", 378 }, |
32950 | 0 | { "HPMCOUNTER16", 344 }, |
32951 | 0 | { "HPMCOUNTER16H", 379 }, |
32952 | 0 | { "HPMCOUNTER17", 345 }, |
32953 | 0 | { "HPMCOUNTER17H", 380 }, |
32954 | 0 | { "HPMCOUNTER18", 346 }, |
32955 | 0 | { "HPMCOUNTER18H", 381 }, |
32956 | 0 | { "HPMCOUNTER19", 347 }, |
32957 | 0 | { "HPMCOUNTER19H", 382 }, |
32958 | 0 | { "HPMCOUNTER20", 348 }, |
32959 | 0 | { "HPMCOUNTER20H", 383 }, |
32960 | 0 | { "HPMCOUNTER21", 349 }, |
32961 | 0 | { "HPMCOUNTER21H", 384 }, |
32962 | 0 | { "HPMCOUNTER22", 350 }, |
32963 | 0 | { "HPMCOUNTER22H", 385 }, |
32964 | 0 | { "HPMCOUNTER23", 351 }, |
32965 | 0 | { "HPMCOUNTER23H", 386 }, |
32966 | 0 | { "HPMCOUNTER24", 352 }, |
32967 | 0 | { "HPMCOUNTER24H", 387 }, |
32968 | 0 | { "HPMCOUNTER25", 353 }, |
32969 | 0 | { "HPMCOUNTER25H", 388 }, |
32970 | 0 | { "HPMCOUNTER26", 354 }, |
32971 | 0 | { "HPMCOUNTER26H", 389 }, |
32972 | 0 | { "HPMCOUNTER27", 355 }, |
32973 | 0 | { "HPMCOUNTER27H", 390 }, |
32974 | 0 | { "HPMCOUNTER28", 356 }, |
32975 | 0 | { "HPMCOUNTER28H", 391 }, |
32976 | 0 | { "HPMCOUNTER29", 357 }, |
32977 | 0 | { "HPMCOUNTER29H", 392 }, |
32978 | 0 | { "HPMCOUNTER3", 331 }, |
32979 | 0 | { "HPMCOUNTER30", 358 }, |
32980 | 0 | { "HPMCOUNTER30H", 393 }, |
32981 | 0 | { "HPMCOUNTER31", 359 }, |
32982 | 0 | { "HPMCOUNTER31H", 394 }, |
32983 | 0 | { "HPMCOUNTER3H", 366 }, |
32984 | 0 | { "HPMCOUNTER4", 332 }, |
32985 | 0 | { "HPMCOUNTER4H", 367 }, |
32986 | 0 | { "HPMCOUNTER5", 333 }, |
32987 | 0 | { "HPMCOUNTER5H", 368 }, |
32988 | 0 | { "HPMCOUNTER6", 334 }, |
32989 | 0 | { "HPMCOUNTER6H", 369 }, |
32990 | 0 | { "HPMCOUNTER7", 335 }, |
32991 | 0 | { "HPMCOUNTER7H", 370 }, |
32992 | 0 | { "HPMCOUNTER8", 336 }, |
32993 | 0 | { "HPMCOUNTER8H", 371 }, |
32994 | 0 | { "HPMCOUNTER9", 337 }, |
32995 | 0 | { "HPMCOUNTER9H", 372 }, |
32996 | 0 | { "HSTATEEN0", 203 }, |
32997 | 0 | { "HSTATEEN0H", 211 }, |
32998 | 0 | { "HSTATEEN1", 204 }, |
32999 | 0 | { "HSTATEEN1H", 212 }, |
33000 | 0 | { "HSTATEEN2", 205 }, |
33001 | 0 | { "HSTATEEN2H", 213 }, |
33002 | 0 | { "HSTATEEN3", 206 }, |
33003 | 0 | { "HSTATEEN3H", 214 }, |
33004 | 0 | { "HSTATUS", 193 }, |
33005 | 0 | { "HTIMEDELTA", 197 }, |
33006 | 0 | { "HTIMEDELTAH", 208 }, |
33007 | 0 | { "HTINST", 220 }, |
33008 | 0 | { "HTVAL", 215 }, |
33009 | 0 | { "HVICTL", 201 }, |
33010 | 0 | { "HVIEN", 200 }, |
33011 | 0 | { "HVIENH", 209 }, |
33012 | 0 | { "HVIP", 217 }, |
33013 | 0 | { "HVIPH", 221 }, |
33014 | 0 | { "HVIPRIO1", 218 }, |
33015 | 0 | { "HVIPRIO1H", 222 }, |
33016 | 0 | { "HVIPRIO2", 219 }, |
33017 | 0 | { "HVIPRIO2H", 223 }, |
33018 | 0 | { "INSTRET", 330 }, |
33019 | 0 | { "INSTRETH", 365 }, |
33020 | 0 | { "JVT", 8 }, |
33021 | 0 | { "MARCHID", 400 }, |
33022 | 0 | { "MCAUSE", 103 }, |
33023 | 0 | { "MCONFIGPTR", 403 }, |
33024 | 0 | { "MCONTEXT", 261 }, |
33025 | 0 | { "MCOUNTEREN", 53 }, |
33026 | 0 | { "MCYCLE", 266 }, |
33027 | 0 | { "MCYCLEH", 297 }, |
33028 | 0 | { "MEDELEG", 49 }, |
33029 | 0 | { "MENVCFG", 56 }, |
33030 | 0 | { "MENVCFGH", 66 }, |
33031 | 0 | { "MEPC", 102 }, |
33032 | 0 | { "MHARTID", 402 }, |
33033 | 0 | { "MHPMCOUNTER10", 275 }, |
33034 | 0 | { "MHPMCOUNTER10H", 306 }, |
33035 | 0 | { "MHPMCOUNTER11", 276 }, |
33036 | 0 | { "MHPMCOUNTER11H", 307 }, |
33037 | 0 | { "MHPMCOUNTER12", 277 }, |
33038 | 0 | { "MHPMCOUNTER12H", 308 }, |
33039 | 0 | { "MHPMCOUNTER13", 278 }, |
33040 | 0 | { "MHPMCOUNTER13H", 309 }, |
33041 | 0 | { "MHPMCOUNTER14", 279 }, |
33042 | 0 | { "MHPMCOUNTER14H", 310 }, |
33043 | 0 | { "MHPMCOUNTER15", 280 }, |
33044 | 0 | { "MHPMCOUNTER15H", 311 }, |
33045 | 0 | { "MHPMCOUNTER16", 281 }, |
33046 | 0 | { "MHPMCOUNTER16H", 312 }, |
33047 | 0 | { "MHPMCOUNTER17", 282 }, |
33048 | 0 | { "MHPMCOUNTER17H", 313 }, |
33049 | 0 | { "MHPMCOUNTER18", 283 }, |
33050 | 0 | { "MHPMCOUNTER18H", 314 }, |
33051 | 0 | { "MHPMCOUNTER19", 284 }, |
33052 | 0 | { "MHPMCOUNTER19H", 315 }, |
33053 | 0 | { "MHPMCOUNTER20", 285 }, |
33054 | 0 | { "MHPMCOUNTER20H", 316 }, |
33055 | 0 | { "MHPMCOUNTER21", 286 }, |
33056 | 0 | { "MHPMCOUNTER21H", 317 }, |
33057 | 0 | { "MHPMCOUNTER22", 287 }, |
33058 | 0 | { "MHPMCOUNTER22H", 318 }, |
33059 | 0 | { "MHPMCOUNTER23", 288 }, |
33060 | 0 | { "MHPMCOUNTER23H", 319 }, |
33061 | 0 | { "MHPMCOUNTER24", 289 }, |
33062 | 0 | { "MHPMCOUNTER24H", 320 }, |
33063 | 0 | { "MHPMCOUNTER25", 290 }, |
33064 | 0 | { "MHPMCOUNTER25H", 321 }, |
33065 | 0 | { "MHPMCOUNTER26", 291 }, |
33066 | 0 | { "MHPMCOUNTER26H", 322 }, |
33067 | 0 | { "MHPMCOUNTER27", 292 }, |
33068 | 0 | { "MHPMCOUNTER27H", 323 }, |
33069 | 0 | { "MHPMCOUNTER28", 293 }, |
33070 | 0 | { "MHPMCOUNTER28H", 324 }, |
33071 | 0 | { "MHPMCOUNTER29", 294 }, |
33072 | 0 | { "MHPMCOUNTER29H", 325 }, |
33073 | 0 | { "MHPMCOUNTER3", 268 }, |
33074 | 0 | { "MHPMCOUNTER30", 295 }, |
33075 | 0 | { "MHPMCOUNTER30H", 326 }, |
33076 | 0 | { "MHPMCOUNTER31", 296 }, |
33077 | 0 | { "MHPMCOUNTER31H", 327 }, |
33078 | 0 | { "MHPMCOUNTER3H", 299 }, |
33079 | 0 | { "MHPMCOUNTER4", 269 }, |
33080 | 0 | { "MHPMCOUNTER4H", 300 }, |
33081 | 0 | { "MHPMCOUNTER5", 270 }, |
33082 | 0 | { "MHPMCOUNTER5H", 301 }, |
33083 | 0 | { "MHPMCOUNTER6", 271 }, |
33084 | 0 | { "MHPMCOUNTER6H", 302 }, |
33085 | 0 | { "MHPMCOUNTER7", 272 }, |
33086 | 0 | { "MHPMCOUNTER7H", 303 }, |
33087 | 0 | { "MHPMCOUNTER8", 273 }, |
33088 | 0 | { "MHPMCOUNTER8H", 304 }, |
33089 | 0 | { "MHPMCOUNTER9", 274 }, |
33090 | 0 | { "MHPMCOUNTER9H", 305 }, |
33091 | 0 | { "MHPMEVENT10", 79 }, |
33092 | 0 | { "MHPMEVENT10H", 233 }, |
33093 | 0 | { "MHPMEVENT11", 80 }, |
33094 | 0 | { "MHPMEVENT11H", 234 }, |
33095 | 0 | { "MHPMEVENT12", 81 }, |
33096 | 0 | { "MHPMEVENT12H", 235 }, |
33097 | 0 | { "MHPMEVENT13", 82 }, |
33098 | 0 | { "MHPMEVENT13H", 236 }, |
33099 | 0 | { "MHPMEVENT14", 83 }, |
33100 | 0 | { "MHPMEVENT14H", 237 }, |
33101 | 0 | { "MHPMEVENT15", 84 }, |
33102 | 0 | { "MHPMEVENT15H", 238 }, |
33103 | 0 | { "MHPMEVENT16", 85 }, |
33104 | 0 | { "MHPMEVENT16H", 239 }, |
33105 | 0 | { "MHPMEVENT17", 86 }, |
33106 | 0 | { "MHPMEVENT17H", 240 }, |
33107 | 0 | { "MHPMEVENT18", 87 }, |
33108 | 0 | { "MHPMEVENT18H", 241 }, |
33109 | 0 | { "MHPMEVENT19", 88 }, |
33110 | 0 | { "MHPMEVENT19H", 242 }, |
33111 | 0 | { "MHPMEVENT20", 89 }, |
33112 | 0 | { "MHPMEVENT20H", 243 }, |
33113 | 0 | { "MHPMEVENT21", 90 }, |
33114 | 0 | { "MHPMEVENT21H", 244 }, |
33115 | 0 | { "MHPMEVENT22", 91 }, |
33116 | 0 | { "MHPMEVENT22H", 245 }, |
33117 | 0 | { "MHPMEVENT23", 92 }, |
33118 | 0 | { "MHPMEVENT23H", 246 }, |
33119 | 0 | { "MHPMEVENT24", 93 }, |
33120 | 0 | { "MHPMEVENT24H", 247 }, |
33121 | 0 | { "MHPMEVENT25", 94 }, |
33122 | 0 | { "MHPMEVENT25H", 248 }, |
33123 | 0 | { "MHPMEVENT26", 95 }, |
33124 | 0 | { "MHPMEVENT26H", 249 }, |
33125 | 0 | { "MHPMEVENT27", 96 }, |
33126 | 0 | { "MHPMEVENT27H", 250 }, |
33127 | 0 | { "MHPMEVENT28", 97 }, |
33128 | 0 | { "MHPMEVENT28H", 251 }, |
33129 | 0 | { "MHPMEVENT29", 98 }, |
33130 | 0 | { "MHPMEVENT29H", 252 }, |
33131 | 0 | { "MHPMEVENT3", 72 }, |
33132 | 0 | { "MHPMEVENT30", 99 }, |
33133 | 0 | { "MHPMEVENT30H", 253 }, |
33134 | 0 | { "MHPMEVENT31", 100 }, |
33135 | 0 | { "MHPMEVENT31H", 254 }, |
33136 | 0 | { "MHPMEVENT3H", 226 }, |
33137 | 0 | { "MHPMEVENT4", 73 }, |
33138 | 0 | { "MHPMEVENT4H", 227 }, |
33139 | 0 | { "MHPMEVENT5", 74 }, |
33140 | 0 | { "MHPMEVENT5H", 228 }, |
33141 | 0 | { "MHPMEVENT6", 75 }, |
33142 | 0 | { "MHPMEVENT6H", 229 }, |
33143 | 0 | { "MHPMEVENT7", 76 }, |
33144 | 0 | { "MHPMEVENT7H", 230 }, |
33145 | 0 | { "MHPMEVENT8", 77 }, |
33146 | 0 | { "MHPMEVENT8H", 231 }, |
33147 | 0 | { "MHPMEVENT9", 78 }, |
33148 | 0 | { "MHPMEVENT9H", 232 }, |
33149 | 0 | { "MIDELEG", 50 }, |
33150 | 0 | { "MIDELEGH", 62 }, |
33151 | 0 | { "MIE", 51 }, |
33152 | 0 | { "MIEH", 63 }, |
33153 | 0 | { "MIMPID", 401 }, |
33154 | 0 | { "MINSTRET", 267 }, |
33155 | 0 | { "MINSTRETH", 298 }, |
33156 | 0 | { "MIP", 105 }, |
33157 | 0 | { "MIPH", 110 }, |
33158 | 0 | { "MIREG", 109 }, |
33159 | 0 | { "MISA", 48 }, |
33160 | 0 | { "MISELECT", 108 }, |
33161 | 0 | { "MSCRATCH", 101 }, |
33162 | 0 | { "MSECCFG", 255 }, |
33163 | 0 | { "MSECCFGH", 256 }, |
33164 | 0 | { "MSTATEEN0", 57 }, |
33165 | 0 | { "MSTATEEN0H", 67 }, |
33166 | 0 | { "MSTATEEN1", 58 }, |
33167 | 0 | { "MSTATEEN1H", 68 }, |
33168 | 0 | { "MSTATEEN2", 59 }, |
33169 | 0 | { "MSTATEEN2H", 69 }, |
33170 | 0 | { "MSTATEEN3", 60 }, |
33171 | 0 | { "MSTATEEN3H", 70 }, |
33172 | 0 | { "MSTATUS", 47 }, |
33173 | 0 | { "MSTATUSH", 61 }, |
33174 | 0 | { "MTINST", 106 }, |
33175 | 0 | { "MTOPEI", 111 }, |
33176 | 0 | { "MTOPI", 404 }, |
33177 | 0 | { "MTVAL", 104 }, |
33178 | 0 | { "MTVAL2", 107 }, |
33179 | 0 | { "MTVEC", 52 }, |
33180 | 0 | { "MUCOUNTEREN", 71 }, |
33181 | 0 | { "MVENDORID", 399 }, |
33182 | 0 | { "MVIEN", 54 }, |
33183 | 0 | { "MVIENH", 64 }, |
33184 | 0 | { "MVIP", 55 }, |
33185 | 0 | { "MVIPH", 65 }, |
33186 | 0 | { "PMPADDR0", 128 }, |
33187 | 0 | { "PMPADDR1", 129 }, |
33188 | 0 | { "PMPADDR10", 138 }, |
33189 | 0 | { "PMPADDR11", 139 }, |
33190 | 0 | { "PMPADDR12", 140 }, |
33191 | 0 | { "PMPADDR13", 141 }, |
33192 | 0 | { "PMPADDR14", 142 }, |
33193 | 0 | { "PMPADDR15", 143 }, |
33194 | 0 | { "PMPADDR16", 144 }, |
33195 | 0 | { "PMPADDR17", 145 }, |
33196 | 0 | { "PMPADDR18", 146 }, |
33197 | 0 | { "PMPADDR19", 147 }, |
33198 | 0 | { "PMPADDR2", 130 }, |
33199 | 0 | { "PMPADDR20", 148 }, |
33200 | 0 | { "PMPADDR21", 149 }, |
33201 | 0 | { "PMPADDR22", 150 }, |
33202 | 0 | { "PMPADDR23", 151 }, |
33203 | 0 | { "PMPADDR24", 152 }, |
33204 | 0 | { "PMPADDR25", 153 }, |
33205 | 0 | { "PMPADDR26", 154 }, |
33206 | 0 | { "PMPADDR27", 155 }, |
33207 | 0 | { "PMPADDR28", 156 }, |
33208 | 0 | { "PMPADDR29", 157 }, |
33209 | 0 | { "PMPADDR3", 131 }, |
33210 | 0 | { "PMPADDR30", 158 }, |
33211 | 0 | { "PMPADDR31", 159 }, |
33212 | 0 | { "PMPADDR32", 160 }, |
33213 | 0 | { "PMPADDR33", 161 }, |
33214 | 0 | { "PMPADDR34", 162 }, |
33215 | 0 | { "PMPADDR35", 163 }, |
33216 | 0 | { "PMPADDR36", 164 }, |
33217 | 0 | { "PMPADDR37", 165 }, |
33218 | 0 | { "PMPADDR38", 166 }, |
33219 | 0 | { "PMPADDR39", 167 }, |
33220 | 0 | { "PMPADDR4", 132 }, |
33221 | 0 | { "PMPADDR40", 168 }, |
33222 | 0 | { "PMPADDR41", 169 }, |
33223 | 0 | { "PMPADDR42", 170 }, |
33224 | 0 | { "PMPADDR43", 171 }, |
33225 | 0 | { "PMPADDR44", 172 }, |
33226 | 0 | { "PMPADDR45", 173 }, |
33227 | 0 | { "PMPADDR46", 174 }, |
33228 | 0 | { "PMPADDR47", 175 }, |
33229 | 0 | { "PMPADDR48", 176 }, |
33230 | 0 | { "PMPADDR49", 177 }, |
33231 | 0 | { "PMPADDR5", 133 }, |
33232 | 0 | { "PMPADDR50", 178 }, |
33233 | 0 | { "PMPADDR51", 179 }, |
33234 | 0 | { "PMPADDR52", 180 }, |
33235 | 0 | { "PMPADDR53", 181 }, |
33236 | 0 | { "PMPADDR54", 182 }, |
33237 | 0 | { "PMPADDR55", 183 }, |
33238 | 0 | { "PMPADDR56", 184 }, |
33239 | 0 | { "PMPADDR57", 185 }, |
33240 | 0 | { "PMPADDR58", 186 }, |
33241 | 0 | { "PMPADDR59", 187 }, |
33242 | 0 | { "PMPADDR6", 134 }, |
33243 | 0 | { "PMPADDR60", 188 }, |
33244 | 0 | { "PMPADDR61", 189 }, |
33245 | 0 | { "PMPADDR62", 190 }, |
33246 | 0 | { "PMPADDR63", 191 }, |
33247 | 0 | { "PMPADDR7", 135 }, |
33248 | 0 | { "PMPADDR8", 136 }, |
33249 | 0 | { "PMPADDR9", 137 }, |
33250 | 0 | { "PMPCFG0", 112 }, |
33251 | 0 | { "PMPCFG1", 113 }, |
33252 | 0 | { "PMPCFG10", 122 }, |
33253 | 0 | { "PMPCFG11", 123 }, |
33254 | 0 | { "PMPCFG12", 124 }, |
33255 | 0 | { "PMPCFG13", 125 }, |
33256 | 0 | { "PMPCFG14", 126 }, |
33257 | 0 | { "PMPCFG15", 127 }, |
33258 | 0 | { "PMPCFG2", 114 }, |
33259 | 0 | { "PMPCFG3", 115 }, |
33260 | 0 | { "PMPCFG4", 116 }, |
33261 | 0 | { "PMPCFG5", 117 }, |
33262 | 0 | { "PMPCFG6", 118 }, |
33263 | 0 | { "PMPCFG7", 119 }, |
33264 | 0 | { "PMPCFG8", 120 }, |
33265 | 0 | { "PMPCFG9", 121 }, |
33266 | 0 | { "SATP", 30 }, |
33267 | 0 | { "SCAUSE", 21 }, |
33268 | 0 | { "SCONTEXT", 192 }, |
33269 | 0 | { "SCOUNTEREN", 12 }, |
33270 | 0 | { "SCOUNTOVF", 395 }, |
33271 | 0 | { "SEED", 7 }, |
33272 | 0 | { "SENVCFG", 13 }, |
33273 | 0 | { "SEPC", 20 }, |
33274 | 0 | { "SIE", 10 }, |
33275 | 0 | { "SIEH", 18 }, |
33276 | 0 | { "SIP", 23 }, |
33277 | 0 | { "SIPH", 27 }, |
33278 | 0 | { "SIREG", 26 }, |
33279 | 0 | { "SISELECT", 25 }, |
33280 | 0 | { "SSCRATCH", 19 }, |
33281 | 0 | { "SSTATEEN0", 14 }, |
33282 | 0 | { "SSTATEEN1", 15 }, |
33283 | 0 | { "SSTATEEN2", 16 }, |
33284 | 0 | { "SSTATEEN3", 17 }, |
33285 | 0 | { "SSTATUS", 9 }, |
33286 | 0 | { "STIMECMP", 24 }, |
33287 | 0 | { "STIMECMPH", 29 }, |
33288 | 0 | { "STOPEI", 28 }, |
33289 | 0 | { "STOPI", 396 }, |
33290 | 0 | { "STVAL", 22 }, |
33291 | 0 | { "STVEC", 11 }, |
33292 | 0 | { "TDATA1", 258 }, |
33293 | 0 | { "TDATA2", 259 }, |
33294 | 0 | { "TDATA3", 260 }, |
33295 | 0 | { "TIME", 329 }, |
33296 | 0 | { "TIMEH", 364 }, |
33297 | 0 | { "TSELECT", 257 }, |
33298 | 0 | { "VCSR", 6 }, |
33299 | 0 | { "VL", 360 }, |
33300 | 0 | { "VLENB", 362 }, |
33301 | 0 | { "VSATP", 46 }, |
33302 | 0 | { "VSCAUSE", 37 }, |
33303 | 0 | { "VSEPC", 36 }, |
33304 | 0 | { "VSIE", 32 }, |
33305 | 0 | { "VSIEH", 34 }, |
33306 | 0 | { "VSIP", 39 }, |
33307 | 0 | { "VSIPH", 43 }, |
33308 | 0 | { "VSIREG", 42 }, |
33309 | 0 | { "VSISELECT", 41 }, |
33310 | 0 | { "VSSCRATCH", 35 }, |
33311 | 0 | { "VSSTATUS", 31 }, |
33312 | 0 | { "VSTART", 3 }, |
33313 | 0 | { "VSTIMECMP", 40 }, |
33314 | 0 | { "VSTIMECMPH", 45 }, |
33315 | 0 | { "VSTOPEI", 44 }, |
33316 | 0 | { "VSTOPI", 398 }, |
33317 | 0 | { "VSTVAL", 38 }, |
33318 | 0 | { "VSTVEC", 33 }, |
33319 | 0 | { "VTYPE", 361 }, |
33320 | 0 | { "VXRM", 5 }, |
33321 | 0 | { "VXSAT", 4 }, |
33322 | 0 | }; |
33323 | |
|
33324 | 0 | unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), AltName); |
33325 | 0 | if (i == -1) |
33326 | 0 | return NULL; |
33327 | 0 | else |
33328 | 0 | return &SysRegsList[Index[i].index]; |
33329 | 0 | } |
33330 | | |
33331 | 0 | const RISCV_SysReg *RISCV_lookupSysRegByDeprecatedName(const char * DeprecatedName) { |
33332 | 0 | static const struct IndexTypeStr Index[] = { |
33333 | 0 | { "", 0 }, |
33334 | 0 | { "", 1 }, |
33335 | 0 | { "", 2 }, |
33336 | 0 | { "", 3 }, |
33337 | 0 | { "", 4 }, |
33338 | 0 | { "", 5 }, |
33339 | 0 | { "", 6 }, |
33340 | 0 | { "", 7 }, |
33341 | 0 | { "", 8 }, |
33342 | 0 | { "", 9 }, |
33343 | 0 | { "", 10 }, |
33344 | 0 | { "", 11 }, |
33345 | 0 | { "", 12 }, |
33346 | 0 | { "", 13 }, |
33347 | 0 | { "", 14 }, |
33348 | 0 | { "", 15 }, |
33349 | 0 | { "", 16 }, |
33350 | 0 | { "", 17 }, |
33351 | 0 | { "", 18 }, |
33352 | 0 | { "", 19 }, |
33353 | 0 | { "", 20 }, |
33354 | 0 | { "", 21 }, |
33355 | 0 | { "", 23 }, |
33356 | 0 | { "", 24 }, |
33357 | 0 | { "", 25 }, |
33358 | 0 | { "", 26 }, |
33359 | 0 | { "", 27 }, |
33360 | 0 | { "", 28 }, |
33361 | 0 | { "", 29 }, |
33362 | 0 | { "", 31 }, |
33363 | 0 | { "", 32 }, |
33364 | 0 | { "", 33 }, |
33365 | 0 | { "", 34 }, |
33366 | 0 | { "", 35 }, |
33367 | 0 | { "", 36 }, |
33368 | 0 | { "", 37 }, |
33369 | 0 | { "", 38 }, |
33370 | 0 | { "", 39 }, |
33371 | 0 | { "", 40 }, |
33372 | 0 | { "", 41 }, |
33373 | 0 | { "", 42 }, |
33374 | 0 | { "", 43 }, |
33375 | 0 | { "", 44 }, |
33376 | 0 | { "", 45 }, |
33377 | 0 | { "", 46 }, |
33378 | 0 | { "", 47 }, |
33379 | 0 | { "", 48 }, |
33380 | 0 | { "", 49 }, |
33381 | 0 | { "", 50 }, |
33382 | 0 | { "", 51 }, |
33383 | 0 | { "", 52 }, |
33384 | 0 | { "", 53 }, |
33385 | 0 | { "", 54 }, |
33386 | 0 | { "", 55 }, |
33387 | 0 | { "", 56 }, |
33388 | 0 | { "", 57 }, |
33389 | 0 | { "", 58 }, |
33390 | 0 | { "", 59 }, |
33391 | 0 | { "", 60 }, |
33392 | 0 | { "", 61 }, |
33393 | 0 | { "", 62 }, |
33394 | 0 | { "", 63 }, |
33395 | 0 | { "", 64 }, |
33396 | 0 | { "", 65 }, |
33397 | 0 | { "", 66 }, |
33398 | 0 | { "", 67 }, |
33399 | 0 | { "", 68 }, |
33400 | 0 | { "", 69 }, |
33401 | 0 | { "", 70 }, |
33402 | 0 | { "", 71 }, |
33403 | 0 | { "", 72 }, |
33404 | 0 | { "", 73 }, |
33405 | 0 | { "", 74 }, |
33406 | 0 | { "", 75 }, |
33407 | 0 | { "", 76 }, |
33408 | 0 | { "", 77 }, |
33409 | 0 | { "", 78 }, |
33410 | 0 | { "", 79 }, |
33411 | 0 | { "", 80 }, |
33412 | 0 | { "", 81 }, |
33413 | 0 | { "", 82 }, |
33414 | 0 | { "", 83 }, |
33415 | 0 | { "", 84 }, |
33416 | 0 | { "", 85 }, |
33417 | 0 | { "", 86 }, |
33418 | 0 | { "", 87 }, |
33419 | 0 | { "", 88 }, |
33420 | 0 | { "", 89 }, |
33421 | 0 | { "", 90 }, |
33422 | 0 | { "", 91 }, |
33423 | 0 | { "", 92 }, |
33424 | 0 | { "", 93 }, |
33425 | 0 | { "", 94 }, |
33426 | 0 | { "", 95 }, |
33427 | 0 | { "", 96 }, |
33428 | 0 | { "", 97 }, |
33429 | 0 | { "", 98 }, |
33430 | 0 | { "", 99 }, |
33431 | 0 | { "", 100 }, |
33432 | 0 | { "", 101 }, |
33433 | 0 | { "", 102 }, |
33434 | 0 | { "", 103 }, |
33435 | 0 | { "", 105 }, |
33436 | 0 | { "", 106 }, |
33437 | 0 | { "", 107 }, |
33438 | 0 | { "", 108 }, |
33439 | 0 | { "", 109 }, |
33440 | 0 | { "", 110 }, |
33441 | 0 | { "", 111 }, |
33442 | 0 | { "", 112 }, |
33443 | 0 | { "", 113 }, |
33444 | 0 | { "", 114 }, |
33445 | 0 | { "", 115 }, |
33446 | 0 | { "", 116 }, |
33447 | 0 | { "", 117 }, |
33448 | 0 | { "", 118 }, |
33449 | 0 | { "", 119 }, |
33450 | 0 | { "", 120 }, |
33451 | 0 | { "", 121 }, |
33452 | 0 | { "", 122 }, |
33453 | 0 | { "", 123 }, |
33454 | 0 | { "", 124 }, |
33455 | 0 | { "", 125 }, |
33456 | 0 | { "", 126 }, |
33457 | 0 | { "", 127 }, |
33458 | 0 | { "", 128 }, |
33459 | 0 | { "", 129 }, |
33460 | 0 | { "", 130 }, |
33461 | 0 | { "", 131 }, |
33462 | 0 | { "", 132 }, |
33463 | 0 | { "", 133 }, |
33464 | 0 | { "", 134 }, |
33465 | 0 | { "", 135 }, |
33466 | 0 | { "", 136 }, |
33467 | 0 | { "", 137 }, |
33468 | 0 | { "", 138 }, |
33469 | 0 | { "", 139 }, |
33470 | 0 | { "", 140 }, |
33471 | 0 | { "", 141 }, |
33472 | 0 | { "", 142 }, |
33473 | 0 | { "", 143 }, |
33474 | 0 | { "", 144 }, |
33475 | 0 | { "", 145 }, |
33476 | 0 | { "", 146 }, |
33477 | 0 | { "", 147 }, |
33478 | 0 | { "", 148 }, |
33479 | 0 | { "", 149 }, |
33480 | 0 | { "", 150 }, |
33481 | 0 | { "", 151 }, |
33482 | 0 | { "", 152 }, |
33483 | 0 | { "", 153 }, |
33484 | 0 | { "", 154 }, |
33485 | 0 | { "", 155 }, |
33486 | 0 | { "", 156 }, |
33487 | 0 | { "", 157 }, |
33488 | 0 | { "", 158 }, |
33489 | 0 | { "", 159 }, |
33490 | 0 | { "", 160 }, |
33491 | 0 | { "", 161 }, |
33492 | 0 | { "", 162 }, |
33493 | 0 | { "", 163 }, |
33494 | 0 | { "", 164 }, |
33495 | 0 | { "", 165 }, |
33496 | 0 | { "", 166 }, |
33497 | 0 | { "", 167 }, |
33498 | 0 | { "", 168 }, |
33499 | 0 | { "", 169 }, |
33500 | 0 | { "", 170 }, |
33501 | 0 | { "", 171 }, |
33502 | 0 | { "", 172 }, |
33503 | 0 | { "", 173 }, |
33504 | 0 | { "", 174 }, |
33505 | 0 | { "", 175 }, |
33506 | 0 | { "", 176 }, |
33507 | 0 | { "", 177 }, |
33508 | 0 | { "", 178 }, |
33509 | 0 | { "", 179 }, |
33510 | 0 | { "", 180 }, |
33511 | 0 | { "", 181 }, |
33512 | 0 | { "", 182 }, |
33513 | 0 | { "", 183 }, |
33514 | 0 | { "", 184 }, |
33515 | 0 | { "", 185 }, |
33516 | 0 | { "", 186 }, |
33517 | 0 | { "", 187 }, |
33518 | 0 | { "", 188 }, |
33519 | 0 | { "", 189 }, |
33520 | 0 | { "", 190 }, |
33521 | 0 | { "", 191 }, |
33522 | 0 | { "", 192 }, |
33523 | 0 | { "", 193 }, |
33524 | 0 | { "", 194 }, |
33525 | 0 | { "", 195 }, |
33526 | 0 | { "", 196 }, |
33527 | 0 | { "", 197 }, |
33528 | 0 | { "", 198 }, |
33529 | 0 | { "", 199 }, |
33530 | 0 | { "", 200 }, |
33531 | 0 | { "", 201 }, |
33532 | 0 | { "", 202 }, |
33533 | 0 | { "", 203 }, |
33534 | 0 | { "", 204 }, |
33535 | 0 | { "", 205 }, |
33536 | 0 | { "", 206 }, |
33537 | 0 | { "", 207 }, |
33538 | 0 | { "", 208 }, |
33539 | 0 | { "", 209 }, |
33540 | 0 | { "", 210 }, |
33541 | 0 | { "", 211 }, |
33542 | 0 | { "", 212 }, |
33543 | 0 | { "", 213 }, |
33544 | 0 | { "", 214 }, |
33545 | 0 | { "", 215 }, |
33546 | 0 | { "", 216 }, |
33547 | 0 | { "", 217 }, |
33548 | 0 | { "", 218 }, |
33549 | 0 | { "", 219 }, |
33550 | 0 | { "", 220 }, |
33551 | 0 | { "", 221 }, |
33552 | 0 | { "", 222 }, |
33553 | 0 | { "", 223 }, |
33554 | 0 | { "", 224 }, |
33555 | 0 | { "", 225 }, |
33556 | 0 | { "", 226 }, |
33557 | 0 | { "", 227 }, |
33558 | 0 | { "", 228 }, |
33559 | 0 | { "", 229 }, |
33560 | 0 | { "", 230 }, |
33561 | 0 | { "", 231 }, |
33562 | 0 | { "", 232 }, |
33563 | 0 | { "", 233 }, |
33564 | 0 | { "", 234 }, |
33565 | 0 | { "", 235 }, |
33566 | 0 | { "", 236 }, |
33567 | 0 | { "", 237 }, |
33568 | 0 | { "", 238 }, |
33569 | 0 | { "", 239 }, |
33570 | 0 | { "", 240 }, |
33571 | 0 | { "", 241 }, |
33572 | 0 | { "", 242 }, |
33573 | 0 | { "", 243 }, |
33574 | 0 | { "", 244 }, |
33575 | 0 | { "", 245 }, |
33576 | 0 | { "", 246 }, |
33577 | 0 | { "", 247 }, |
33578 | 0 | { "", 248 }, |
33579 | 0 | { "", 249 }, |
33580 | 0 | { "", 250 }, |
33581 | 0 | { "", 251 }, |
33582 | 0 | { "", 252 }, |
33583 | 0 | { "", 253 }, |
33584 | 0 | { "", 254 }, |
33585 | 0 | { "", 255 }, |
33586 | 0 | { "", 256 }, |
33587 | 0 | { "", 257 }, |
33588 | 0 | { "", 258 }, |
33589 | 0 | { "", 259 }, |
33590 | 0 | { "", 260 }, |
33591 | 0 | { "", 261 }, |
33592 | 0 | { "", 262 }, |
33593 | 0 | { "", 263 }, |
33594 | 0 | { "", 264 }, |
33595 | 0 | { "", 265 }, |
33596 | 0 | { "", 266 }, |
33597 | 0 | { "", 267 }, |
33598 | 0 | { "", 268 }, |
33599 | 0 | { "", 269 }, |
33600 | 0 | { "", 270 }, |
33601 | 0 | { "", 271 }, |
33602 | 0 | { "", 272 }, |
33603 | 0 | { "", 273 }, |
33604 | 0 | { "", 274 }, |
33605 | 0 | { "", 275 }, |
33606 | 0 | { "", 276 }, |
33607 | 0 | { "", 277 }, |
33608 | 0 | { "", 278 }, |
33609 | 0 | { "", 279 }, |
33610 | 0 | { "", 280 }, |
33611 | 0 | { "", 281 }, |
33612 | 0 | { "", 282 }, |
33613 | 0 | { "", 283 }, |
33614 | 0 | { "", 284 }, |
33615 | 0 | { "", 285 }, |
33616 | 0 | { "", 286 }, |
33617 | 0 | { "", 287 }, |
33618 | 0 | { "", 288 }, |
33619 | 0 | { "", 289 }, |
33620 | 0 | { "", 290 }, |
33621 | 0 | { "", 291 }, |
33622 | 0 | { "", 292 }, |
33623 | 0 | { "", 293 }, |
33624 | 0 | { "", 294 }, |
33625 | 0 | { "", 295 }, |
33626 | 0 | { "", 296 }, |
33627 | 0 | { "", 297 }, |
33628 | 0 | { "", 298 }, |
33629 | 0 | { "", 299 }, |
33630 | 0 | { "", 300 }, |
33631 | 0 | { "", 301 }, |
33632 | 0 | { "", 302 }, |
33633 | 0 | { "", 303 }, |
33634 | 0 | { "", 304 }, |
33635 | 0 | { "", 305 }, |
33636 | 0 | { "", 306 }, |
33637 | 0 | { "", 307 }, |
33638 | 0 | { "", 308 }, |
33639 | 0 | { "", 309 }, |
33640 | 0 | { "", 310 }, |
33641 | 0 | { "", 311 }, |
33642 | 0 | { "", 312 }, |
33643 | 0 | { "", 313 }, |
33644 | 0 | { "", 314 }, |
33645 | 0 | { "", 315 }, |
33646 | 0 | { "", 316 }, |
33647 | 0 | { "", 317 }, |
33648 | 0 | { "", 318 }, |
33649 | 0 | { "", 319 }, |
33650 | 0 | { "", 320 }, |
33651 | 0 | { "", 321 }, |
33652 | 0 | { "", 322 }, |
33653 | 0 | { "", 323 }, |
33654 | 0 | { "", 324 }, |
33655 | 0 | { "", 325 }, |
33656 | 0 | { "", 326 }, |
33657 | 0 | { "", 327 }, |
33658 | 0 | { "", 328 }, |
33659 | 0 | { "", 329 }, |
33660 | 0 | { "", 330 }, |
33661 | 0 | { "", 331 }, |
33662 | 0 | { "", 332 }, |
33663 | 0 | { "", 333 }, |
33664 | 0 | { "", 334 }, |
33665 | 0 | { "", 335 }, |
33666 | 0 | { "", 336 }, |
33667 | 0 | { "", 337 }, |
33668 | 0 | { "", 338 }, |
33669 | 0 | { "", 339 }, |
33670 | 0 | { "", 340 }, |
33671 | 0 | { "", 341 }, |
33672 | 0 | { "", 342 }, |
33673 | 0 | { "", 343 }, |
33674 | 0 | { "", 344 }, |
33675 | 0 | { "", 345 }, |
33676 | 0 | { "", 346 }, |
33677 | 0 | { "", 347 }, |
33678 | 0 | { "", 348 }, |
33679 | 0 | { "", 349 }, |
33680 | 0 | { "", 350 }, |
33681 | 0 | { "", 351 }, |
33682 | 0 | { "", 352 }, |
33683 | 0 | { "", 353 }, |
33684 | 0 | { "", 354 }, |
33685 | 0 | { "", 355 }, |
33686 | 0 | { "", 356 }, |
33687 | 0 | { "", 357 }, |
33688 | 0 | { "", 358 }, |
33689 | 0 | { "", 359 }, |
33690 | 0 | { "", 360 }, |
33691 | 0 | { "", 361 }, |
33692 | 0 | { "", 362 }, |
33693 | 0 | { "", 363 }, |
33694 | 0 | { "", 364 }, |
33695 | 0 | { "", 365 }, |
33696 | 0 | { "", 366 }, |
33697 | 0 | { "", 367 }, |
33698 | 0 | { "", 368 }, |
33699 | 0 | { "", 369 }, |
33700 | 0 | { "", 370 }, |
33701 | 0 | { "", 371 }, |
33702 | 0 | { "", 372 }, |
33703 | 0 | { "", 373 }, |
33704 | 0 | { "", 374 }, |
33705 | 0 | { "", 375 }, |
33706 | 0 | { "", 376 }, |
33707 | 0 | { "", 377 }, |
33708 | 0 | { "", 378 }, |
33709 | 0 | { "", 379 }, |
33710 | 0 | { "", 380 }, |
33711 | 0 | { "", 381 }, |
33712 | 0 | { "", 382 }, |
33713 | 0 | { "", 383 }, |
33714 | 0 | { "", 384 }, |
33715 | 0 | { "", 385 }, |
33716 | 0 | { "", 386 }, |
33717 | 0 | { "", 387 }, |
33718 | 0 | { "", 388 }, |
33719 | 0 | { "", 389 }, |
33720 | 0 | { "", 390 }, |
33721 | 0 | { "", 391 }, |
33722 | 0 | { "", 392 }, |
33723 | 0 | { "", 393 }, |
33724 | 0 | { "", 394 }, |
33725 | 0 | { "", 395 }, |
33726 | 0 | { "", 396 }, |
33727 | 0 | { "", 397 }, |
33728 | 0 | { "", 398 }, |
33729 | 0 | { "", 399 }, |
33730 | 0 | { "", 400 }, |
33731 | 0 | { "", 401 }, |
33732 | 0 | { "", 402 }, |
33733 | 0 | { "", 403 }, |
33734 | 0 | { "", 404 }, |
33735 | 0 | { "MBADADDR", 104 }, |
33736 | 0 | { "SBADADDR", 22 }, |
33737 | 0 | { "SPTBR", 30 }, |
33738 | 0 | }; |
33739 | |
|
33740 | 0 | unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), DeprecatedName); |
33741 | 0 | if (i == -1) |
33742 | 0 | return NULL; |
33743 | 0 | else |
33744 | 0 | return &SysRegsList[Index[i].index]; |
33745 | 0 | } |
33746 | | |
33747 | 0 | const RISCV_SysReg *RISCV_lookupSysRegByName(const char * Name) { |
33748 | 0 | static const struct IndexTypeStr Index[] = { |
33749 | 0 | { "CYCLE", 328 }, |
33750 | 0 | { "CYCLEH", 363 }, |
33751 | 0 | { "DCSR", 262 }, |
33752 | 0 | { "DPC", 263 }, |
33753 | 0 | { "DSCRATCH0", 264 }, |
33754 | 0 | { "DSCRATCH1", 265 }, |
33755 | 0 | { "FCSR", 2 }, |
33756 | 0 | { "FFLAGS", 0 }, |
33757 | 0 | { "FRM", 1 }, |
33758 | 0 | { "HCONTEXT", 225 }, |
33759 | 0 | { "HCOUNTEREN", 198 }, |
33760 | 0 | { "HEDELEG", 194 }, |
33761 | 0 | { "HENVCFG", 202 }, |
33762 | 0 | { "HENVCFGH", 210 }, |
33763 | 0 | { "HGATP", 224 }, |
33764 | 0 | { "HGEIE", 199 }, |
33765 | 0 | { "HGEIP", 397 }, |
33766 | 0 | { "HIDELEG", 195 }, |
33767 | 0 | { "HIDELEGH", 207 }, |
33768 | 0 | { "HIE", 196 }, |
33769 | 0 | { "HIP", 216 }, |
33770 | 0 | { "HPMCOUNTER10", 338 }, |
33771 | 0 | { "HPMCOUNTER10H", 373 }, |
33772 | 0 | { "HPMCOUNTER11", 339 }, |
33773 | 0 | { "HPMCOUNTER11H", 374 }, |
33774 | 0 | { "HPMCOUNTER12", 340 }, |
33775 | 0 | { "HPMCOUNTER12H", 375 }, |
33776 | 0 | { "HPMCOUNTER13", 341 }, |
33777 | 0 | { "HPMCOUNTER13H", 376 }, |
33778 | 0 | { "HPMCOUNTER14", 342 }, |
33779 | 0 | { "HPMCOUNTER14H", 377 }, |
33780 | 0 | { "HPMCOUNTER15", 343 }, |
33781 | 0 | { "HPMCOUNTER15H", 378 }, |
33782 | 0 | { "HPMCOUNTER16", 344 }, |
33783 | 0 | { "HPMCOUNTER16H", 379 }, |
33784 | 0 | { "HPMCOUNTER17", 345 }, |
33785 | 0 | { "HPMCOUNTER17H", 380 }, |
33786 | 0 | { "HPMCOUNTER18", 346 }, |
33787 | 0 | { "HPMCOUNTER18H", 381 }, |
33788 | 0 | { "HPMCOUNTER19", 347 }, |
33789 | 0 | { "HPMCOUNTER19H", 382 }, |
33790 | 0 | { "HPMCOUNTER20", 348 }, |
33791 | 0 | { "HPMCOUNTER20H", 383 }, |
33792 | 0 | { "HPMCOUNTER21", 349 }, |
33793 | 0 | { "HPMCOUNTER21H", 384 }, |
33794 | 0 | { "HPMCOUNTER22", 350 }, |
33795 | 0 | { "HPMCOUNTER22H", 385 }, |
33796 | 0 | { "HPMCOUNTER23", 351 }, |
33797 | 0 | { "HPMCOUNTER23H", 386 }, |
33798 | 0 | { "HPMCOUNTER24", 352 }, |
33799 | 0 | { "HPMCOUNTER24H", 387 }, |
33800 | 0 | { "HPMCOUNTER25", 353 }, |
33801 | 0 | { "HPMCOUNTER25H", 388 }, |
33802 | 0 | { "HPMCOUNTER26", 354 }, |
33803 | 0 | { "HPMCOUNTER26H", 389 }, |
33804 | 0 | { "HPMCOUNTER27", 355 }, |
33805 | 0 | { "HPMCOUNTER27H", 390 }, |
33806 | 0 | { "HPMCOUNTER28", 356 }, |
33807 | 0 | { "HPMCOUNTER28H", 391 }, |
33808 | 0 | { "HPMCOUNTER29", 357 }, |
33809 | 0 | { "HPMCOUNTER29H", 392 }, |
33810 | 0 | { "HPMCOUNTER3", 331 }, |
33811 | 0 | { "HPMCOUNTER30", 358 }, |
33812 | 0 | { "HPMCOUNTER30H", 393 }, |
33813 | 0 | { "HPMCOUNTER31", 359 }, |
33814 | 0 | { "HPMCOUNTER31H", 394 }, |
33815 | 0 | { "HPMCOUNTER3H", 366 }, |
33816 | 0 | { "HPMCOUNTER4", 332 }, |
33817 | 0 | { "HPMCOUNTER4H", 367 }, |
33818 | 0 | { "HPMCOUNTER5", 333 }, |
33819 | 0 | { "HPMCOUNTER5H", 368 }, |
33820 | 0 | { "HPMCOUNTER6", 334 }, |
33821 | 0 | { "HPMCOUNTER6H", 369 }, |
33822 | 0 | { "HPMCOUNTER7", 335 }, |
33823 | 0 | { "HPMCOUNTER7H", 370 }, |
33824 | 0 | { "HPMCOUNTER8", 336 }, |
33825 | 0 | { "HPMCOUNTER8H", 371 }, |
33826 | 0 | { "HPMCOUNTER9", 337 }, |
33827 | 0 | { "HPMCOUNTER9H", 372 }, |
33828 | 0 | { "HSTATEEN0", 203 }, |
33829 | 0 | { "HSTATEEN0H", 211 }, |
33830 | 0 | { "HSTATEEN1", 204 }, |
33831 | 0 | { "HSTATEEN1H", 212 }, |
33832 | 0 | { "HSTATEEN2", 205 }, |
33833 | 0 | { "HSTATEEN2H", 213 }, |
33834 | 0 | { "HSTATEEN3", 206 }, |
33835 | 0 | { "HSTATEEN3H", 214 }, |
33836 | 0 | { "HSTATUS", 193 }, |
33837 | 0 | { "HTIMEDELTA", 197 }, |
33838 | 0 | { "HTIMEDELTAH", 208 }, |
33839 | 0 | { "HTINST", 220 }, |
33840 | 0 | { "HTVAL", 215 }, |
33841 | 0 | { "HVICTL", 201 }, |
33842 | 0 | { "HVIEN", 200 }, |
33843 | 0 | { "HVIENH", 209 }, |
33844 | 0 | { "HVIP", 217 }, |
33845 | 0 | { "HVIPH", 221 }, |
33846 | 0 | { "HVIPRIO1", 218 }, |
33847 | 0 | { "HVIPRIO1H", 222 }, |
33848 | 0 | { "HVIPRIO2", 219 }, |
33849 | 0 | { "HVIPRIO2H", 223 }, |
33850 | 0 | { "INSTRET", 330 }, |
33851 | 0 | { "INSTRETH", 365 }, |
33852 | 0 | { "JVT", 8 }, |
33853 | 0 | { "MARCHID", 400 }, |
33854 | 0 | { "MCAUSE", 103 }, |
33855 | 0 | { "MCONFIGPTR", 403 }, |
33856 | 0 | { "MCONTEXT", 261 }, |
33857 | 0 | { "MCOUNTEREN", 53 }, |
33858 | 0 | { "MCOUNTINHIBIT", 71 }, |
33859 | 0 | { "MCYCLE", 266 }, |
33860 | 0 | { "MCYCLEH", 297 }, |
33861 | 0 | { "MEDELEG", 49 }, |
33862 | 0 | { "MENVCFG", 56 }, |
33863 | 0 | { "MENVCFGH", 66 }, |
33864 | 0 | { "MEPC", 102 }, |
33865 | 0 | { "MHARTID", 402 }, |
33866 | 0 | { "MHPMCOUNTER10", 275 }, |
33867 | 0 | { "MHPMCOUNTER10H", 306 }, |
33868 | 0 | { "MHPMCOUNTER11", 276 }, |
33869 | 0 | { "MHPMCOUNTER11H", 307 }, |
33870 | 0 | { "MHPMCOUNTER12", 277 }, |
33871 | 0 | { "MHPMCOUNTER12H", 308 }, |
33872 | 0 | { "MHPMCOUNTER13", 278 }, |
33873 | 0 | { "MHPMCOUNTER13H", 309 }, |
33874 | 0 | { "MHPMCOUNTER14", 279 }, |
33875 | 0 | { "MHPMCOUNTER14H", 310 }, |
33876 | 0 | { "MHPMCOUNTER15", 280 }, |
33877 | 0 | { "MHPMCOUNTER15H", 311 }, |
33878 | 0 | { "MHPMCOUNTER16", 281 }, |
33879 | 0 | { "MHPMCOUNTER16H", 312 }, |
33880 | 0 | { "MHPMCOUNTER17", 282 }, |
33881 | 0 | { "MHPMCOUNTER17H", 313 }, |
33882 | 0 | { "MHPMCOUNTER18", 283 }, |
33883 | 0 | { "MHPMCOUNTER18H", 314 }, |
33884 | 0 | { "MHPMCOUNTER19", 284 }, |
33885 | 0 | { "MHPMCOUNTER19H", 315 }, |
33886 | 0 | { "MHPMCOUNTER20", 285 }, |
33887 | 0 | { "MHPMCOUNTER20H", 316 }, |
33888 | 0 | { "MHPMCOUNTER21", 286 }, |
33889 | 0 | { "MHPMCOUNTER21H", 317 }, |
33890 | 0 | { "MHPMCOUNTER22", 287 }, |
33891 | 0 | { "MHPMCOUNTER22H", 318 }, |
33892 | 0 | { "MHPMCOUNTER23", 288 }, |
33893 | 0 | { "MHPMCOUNTER23H", 319 }, |
33894 | 0 | { "MHPMCOUNTER24", 289 }, |
33895 | 0 | { "MHPMCOUNTER24H", 320 }, |
33896 | 0 | { "MHPMCOUNTER25", 290 }, |
33897 | 0 | { "MHPMCOUNTER25H", 321 }, |
33898 | 0 | { "MHPMCOUNTER26", 291 }, |
33899 | 0 | { "MHPMCOUNTER26H", 322 }, |
33900 | 0 | { "MHPMCOUNTER27", 292 }, |
33901 | 0 | { "MHPMCOUNTER27H", 323 }, |
33902 | 0 | { "MHPMCOUNTER28", 293 }, |
33903 | 0 | { "MHPMCOUNTER28H", 324 }, |
33904 | 0 | { "MHPMCOUNTER29", 294 }, |
33905 | 0 | { "MHPMCOUNTER29H", 325 }, |
33906 | 0 | { "MHPMCOUNTER3", 268 }, |
33907 | 0 | { "MHPMCOUNTER30", 295 }, |
33908 | 0 | { "MHPMCOUNTER30H", 326 }, |
33909 | 0 | { "MHPMCOUNTER31", 296 }, |
33910 | 0 | { "MHPMCOUNTER31H", 327 }, |
33911 | 0 | { "MHPMCOUNTER3H", 299 }, |
33912 | 0 | { "MHPMCOUNTER4", 269 }, |
33913 | 0 | { "MHPMCOUNTER4H", 300 }, |
33914 | 0 | { "MHPMCOUNTER5", 270 }, |
33915 | 0 | { "MHPMCOUNTER5H", 301 }, |
33916 | 0 | { "MHPMCOUNTER6", 271 }, |
33917 | 0 | { "MHPMCOUNTER6H", 302 }, |
33918 | 0 | { "MHPMCOUNTER7", 272 }, |
33919 | 0 | { "MHPMCOUNTER7H", 303 }, |
33920 | 0 | { "MHPMCOUNTER8", 273 }, |
33921 | 0 | { "MHPMCOUNTER8H", 304 }, |
33922 | 0 | { "MHPMCOUNTER9", 274 }, |
33923 | 0 | { "MHPMCOUNTER9H", 305 }, |
33924 | 0 | { "MHPMEVENT10", 79 }, |
33925 | 0 | { "MHPMEVENT10H", 233 }, |
33926 | 0 | { "MHPMEVENT11", 80 }, |
33927 | 0 | { "MHPMEVENT11H", 234 }, |
33928 | 0 | { "MHPMEVENT12", 81 }, |
33929 | 0 | { "MHPMEVENT12H", 235 }, |
33930 | 0 | { "MHPMEVENT13", 82 }, |
33931 | 0 | { "MHPMEVENT13H", 236 }, |
33932 | 0 | { "MHPMEVENT14", 83 }, |
33933 | 0 | { "MHPMEVENT14H", 237 }, |
33934 | 0 | { "MHPMEVENT15", 84 }, |
33935 | 0 | { "MHPMEVENT15H", 238 }, |
33936 | 0 | { "MHPMEVENT16", 85 }, |
33937 | 0 | { "MHPMEVENT16H", 239 }, |
33938 | 0 | { "MHPMEVENT17", 86 }, |
33939 | 0 | { "MHPMEVENT17H", 240 }, |
33940 | 0 | { "MHPMEVENT18", 87 }, |
33941 | 0 | { "MHPMEVENT18H", 241 }, |
33942 | 0 | { "MHPMEVENT19", 88 }, |
33943 | 0 | { "MHPMEVENT19H", 242 }, |
33944 | 0 | { "MHPMEVENT20", 89 }, |
33945 | 0 | { "MHPMEVENT20H", 243 }, |
33946 | 0 | { "MHPMEVENT21", 90 }, |
33947 | 0 | { "MHPMEVENT21H", 244 }, |
33948 | 0 | { "MHPMEVENT22", 91 }, |
33949 | 0 | { "MHPMEVENT22H", 245 }, |
33950 | 0 | { "MHPMEVENT23", 92 }, |
33951 | 0 | { "MHPMEVENT23H", 246 }, |
33952 | 0 | { "MHPMEVENT24", 93 }, |
33953 | 0 | { "MHPMEVENT24H", 247 }, |
33954 | 0 | { "MHPMEVENT25", 94 }, |
33955 | 0 | { "MHPMEVENT25H", 248 }, |
33956 | 0 | { "MHPMEVENT26", 95 }, |
33957 | 0 | { "MHPMEVENT26H", 249 }, |
33958 | 0 | { "MHPMEVENT27", 96 }, |
33959 | 0 | { "MHPMEVENT27H", 250 }, |
33960 | 0 | { "MHPMEVENT28", 97 }, |
33961 | 0 | { "MHPMEVENT28H", 251 }, |
33962 | 0 | { "MHPMEVENT29", 98 }, |
33963 | 0 | { "MHPMEVENT29H", 252 }, |
33964 | 0 | { "MHPMEVENT3", 72 }, |
33965 | 0 | { "MHPMEVENT30", 99 }, |
33966 | 0 | { "MHPMEVENT30H", 253 }, |
33967 | 0 | { "MHPMEVENT31", 100 }, |
33968 | 0 | { "MHPMEVENT31H", 254 }, |
33969 | 0 | { "MHPMEVENT3H", 226 }, |
33970 | 0 | { "MHPMEVENT4", 73 }, |
33971 | 0 | { "MHPMEVENT4H", 227 }, |
33972 | 0 | { "MHPMEVENT5", 74 }, |
33973 | 0 | { "MHPMEVENT5H", 228 }, |
33974 | 0 | { "MHPMEVENT6", 75 }, |
33975 | 0 | { "MHPMEVENT6H", 229 }, |
33976 | 0 | { "MHPMEVENT7", 76 }, |
33977 | 0 | { "MHPMEVENT7H", 230 }, |
33978 | 0 | { "MHPMEVENT8", 77 }, |
33979 | 0 | { "MHPMEVENT8H", 231 }, |
33980 | 0 | { "MHPMEVENT9", 78 }, |
33981 | 0 | { "MHPMEVENT9H", 232 }, |
33982 | 0 | { "MIDELEG", 50 }, |
33983 | 0 | { "MIDELEGH", 62 }, |
33984 | 0 | { "MIE", 51 }, |
33985 | 0 | { "MIEH", 63 }, |
33986 | 0 | { "MIMPID", 401 }, |
33987 | 0 | { "MINSTRET", 267 }, |
33988 | 0 | { "MINSTRETH", 298 }, |
33989 | 0 | { "MIP", 105 }, |
33990 | 0 | { "MIPH", 110 }, |
33991 | 0 | { "MIREG", 109 }, |
33992 | 0 | { "MISA", 48 }, |
33993 | 0 | { "MISELECT", 108 }, |
33994 | 0 | { "MSCRATCH", 101 }, |
33995 | 0 | { "MSECCFG", 255 }, |
33996 | 0 | { "MSECCFGH", 256 }, |
33997 | 0 | { "MSTATEEN0", 57 }, |
33998 | 0 | { "MSTATEEN0H", 67 }, |
33999 | 0 | { "MSTATEEN1", 58 }, |
34000 | 0 | { "MSTATEEN1H", 68 }, |
34001 | 0 | { "MSTATEEN2", 59 }, |
34002 | 0 | { "MSTATEEN2H", 69 }, |
34003 | 0 | { "MSTATEEN3", 60 }, |
34004 | 0 | { "MSTATEEN3H", 70 }, |
34005 | 0 | { "MSTATUS", 47 }, |
34006 | 0 | { "MSTATUSH", 61 }, |
34007 | 0 | { "MTINST", 106 }, |
34008 | 0 | { "MTOPEI", 111 }, |
34009 | 0 | { "MTOPI", 404 }, |
34010 | 0 | { "MTVAL", 104 }, |
34011 | 0 | { "MTVAL2", 107 }, |
34012 | 0 | { "MTVEC", 52 }, |
34013 | 0 | { "MVENDORID", 399 }, |
34014 | 0 | { "MVIEN", 54 }, |
34015 | 0 | { "MVIENH", 64 }, |
34016 | 0 | { "MVIP", 55 }, |
34017 | 0 | { "MVIPH", 65 }, |
34018 | 0 | { "PMPADDR0", 128 }, |
34019 | 0 | { "PMPADDR1", 129 }, |
34020 | 0 | { "PMPADDR10", 138 }, |
34021 | 0 | { "PMPADDR11", 139 }, |
34022 | 0 | { "PMPADDR12", 140 }, |
34023 | 0 | { "PMPADDR13", 141 }, |
34024 | 0 | { "PMPADDR14", 142 }, |
34025 | 0 | { "PMPADDR15", 143 }, |
34026 | 0 | { "PMPADDR16", 144 }, |
34027 | 0 | { "PMPADDR17", 145 }, |
34028 | 0 | { "PMPADDR18", 146 }, |
34029 | 0 | { "PMPADDR19", 147 }, |
34030 | 0 | { "PMPADDR2", 130 }, |
34031 | 0 | { "PMPADDR20", 148 }, |
34032 | 0 | { "PMPADDR21", 149 }, |
34033 | 0 | { "PMPADDR22", 150 }, |
34034 | 0 | { "PMPADDR23", 151 }, |
34035 | 0 | { "PMPADDR24", 152 }, |
34036 | 0 | { "PMPADDR25", 153 }, |
34037 | 0 | { "PMPADDR26", 154 }, |
34038 | 0 | { "PMPADDR27", 155 }, |
34039 | 0 | { "PMPADDR28", 156 }, |
34040 | 0 | { "PMPADDR29", 157 }, |
34041 | 0 | { "PMPADDR3", 131 }, |
34042 | 0 | { "PMPADDR30", 158 }, |
34043 | 0 | { "PMPADDR31", 159 }, |
34044 | 0 | { "PMPADDR32", 160 }, |
34045 | 0 | { "PMPADDR33", 161 }, |
34046 | 0 | { "PMPADDR34", 162 }, |
34047 | 0 | { "PMPADDR35", 163 }, |
34048 | 0 | { "PMPADDR36", 164 }, |
34049 | 0 | { "PMPADDR37", 165 }, |
34050 | 0 | { "PMPADDR38", 166 }, |
34051 | 0 | { "PMPADDR39", 167 }, |
34052 | 0 | { "PMPADDR4", 132 }, |
34053 | 0 | { "PMPADDR40", 168 }, |
34054 | 0 | { "PMPADDR41", 169 }, |
34055 | 0 | { "PMPADDR42", 170 }, |
34056 | 0 | { "PMPADDR43", 171 }, |
34057 | 0 | { "PMPADDR44", 172 }, |
34058 | 0 | { "PMPADDR45", 173 }, |
34059 | 0 | { "PMPADDR46", 174 }, |
34060 | 0 | { "PMPADDR47", 175 }, |
34061 | 0 | { "PMPADDR48", 176 }, |
34062 | 0 | { "PMPADDR49", 177 }, |
34063 | 0 | { "PMPADDR5", 133 }, |
34064 | 0 | { "PMPADDR50", 178 }, |
34065 | 0 | { "PMPADDR51", 179 }, |
34066 | 0 | { "PMPADDR52", 180 }, |
34067 | 0 | { "PMPADDR53", 181 }, |
34068 | 0 | { "PMPADDR54", 182 }, |
34069 | 0 | { "PMPADDR55", 183 }, |
34070 | 0 | { "PMPADDR56", 184 }, |
34071 | 0 | { "PMPADDR57", 185 }, |
34072 | 0 | { "PMPADDR58", 186 }, |
34073 | 0 | { "PMPADDR59", 187 }, |
34074 | 0 | { "PMPADDR6", 134 }, |
34075 | 0 | { "PMPADDR60", 188 }, |
34076 | 0 | { "PMPADDR61", 189 }, |
34077 | 0 | { "PMPADDR62", 190 }, |
34078 | 0 | { "PMPADDR63", 191 }, |
34079 | 0 | { "PMPADDR7", 135 }, |
34080 | 0 | { "PMPADDR8", 136 }, |
34081 | 0 | { "PMPADDR9", 137 }, |
34082 | 0 | { "PMPCFG0", 112 }, |
34083 | 0 | { "PMPCFG1", 113 }, |
34084 | 0 | { "PMPCFG10", 122 }, |
34085 | 0 | { "PMPCFG11", 123 }, |
34086 | 0 | { "PMPCFG12", 124 }, |
34087 | 0 | { "PMPCFG13", 125 }, |
34088 | 0 | { "PMPCFG14", 126 }, |
34089 | 0 | { "PMPCFG15", 127 }, |
34090 | 0 | { "PMPCFG2", 114 }, |
34091 | 0 | { "PMPCFG3", 115 }, |
34092 | 0 | { "PMPCFG4", 116 }, |
34093 | 0 | { "PMPCFG5", 117 }, |
34094 | 0 | { "PMPCFG6", 118 }, |
34095 | 0 | { "PMPCFG7", 119 }, |
34096 | 0 | { "PMPCFG8", 120 }, |
34097 | 0 | { "PMPCFG9", 121 }, |
34098 | 0 | { "SATP", 30 }, |
34099 | 0 | { "SCAUSE", 21 }, |
34100 | 0 | { "SCONTEXT", 192 }, |
34101 | 0 | { "SCOUNTEREN", 12 }, |
34102 | 0 | { "SCOUNTOVF", 395 }, |
34103 | 0 | { "SEED", 7 }, |
34104 | 0 | { "SENVCFG", 13 }, |
34105 | 0 | { "SEPC", 20 }, |
34106 | 0 | { "SIE", 10 }, |
34107 | 0 | { "SIEH", 18 }, |
34108 | 0 | { "SIP", 23 }, |
34109 | 0 | { "SIPH", 27 }, |
34110 | 0 | { "SIREG", 26 }, |
34111 | 0 | { "SISELECT", 25 }, |
34112 | 0 | { "SSCRATCH", 19 }, |
34113 | 0 | { "SSTATEEN0", 14 }, |
34114 | 0 | { "SSTATEEN1", 15 }, |
34115 | 0 | { "SSTATEEN2", 16 }, |
34116 | 0 | { "SSTATEEN3", 17 }, |
34117 | 0 | { "SSTATUS", 9 }, |
34118 | 0 | { "STIMECMP", 24 }, |
34119 | 0 | { "STIMECMPH", 29 }, |
34120 | 0 | { "STOPEI", 28 }, |
34121 | 0 | { "STOPI", 396 }, |
34122 | 0 | { "STVAL", 22 }, |
34123 | 0 | { "STVEC", 11 }, |
34124 | 0 | { "TDATA1", 258 }, |
34125 | 0 | { "TDATA2", 259 }, |
34126 | 0 | { "TDATA3", 260 }, |
34127 | 0 | { "TIME", 329 }, |
34128 | 0 | { "TIMEH", 364 }, |
34129 | 0 | { "TSELECT", 257 }, |
34130 | 0 | { "VCSR", 6 }, |
34131 | 0 | { "VL", 360 }, |
34132 | 0 | { "VLENB", 362 }, |
34133 | 0 | { "VSATP", 46 }, |
34134 | 0 | { "VSCAUSE", 37 }, |
34135 | 0 | { "VSEPC", 36 }, |
34136 | 0 | { "VSIE", 32 }, |
34137 | 0 | { "VSIEH", 34 }, |
34138 | 0 | { "VSIP", 39 }, |
34139 | 0 | { "VSIPH", 43 }, |
34140 | 0 | { "VSIREG", 42 }, |
34141 | 0 | { "VSISELECT", 41 }, |
34142 | 0 | { "VSSCRATCH", 35 }, |
34143 | 0 | { "VSSTATUS", 31 }, |
34144 | 0 | { "VSTART", 3 }, |
34145 | 0 | { "VSTIMECMP", 40 }, |
34146 | 0 | { "VSTIMECMPH", 45 }, |
34147 | 0 | { "VSTOPEI", 44 }, |
34148 | 0 | { "VSTOPI", 398 }, |
34149 | 0 | { "VSTVAL", 38 }, |
34150 | 0 | { "VSTVEC", 33 }, |
34151 | 0 | { "VTYPE", 361 }, |
34152 | 0 | { "VXRM", 5 }, |
34153 | 0 | { "VXSAT", 4 }, |
34154 | 0 | }; |
34155 | |
|
34156 | 0 | unsigned i = binsearch_IndexTypeStrEncoding(Index, ARR_SIZE(Index), Name); |
34157 | 0 | if (i == -1) |
34158 | 0 | return NULL; |
34159 | 0 | else |
34160 | 0 | return &SysRegsList[Index[i].index]; |
34161 | 0 | } |
34162 | | |
34163 | | #endif |
34164 | | |
34165 | | #undef GET_RISCVMaskedPseudosTable_DECL |
34166 | | #undef GET_RISCVMaskedPseudosTable_IMPL |
34167 | | #undef GET_RISCVOpcodesList_DECL |
34168 | | #undef GET_RISCVOpcodesList_IMPL |
34169 | | #undef GET_RISCVTuneInfoTable_DECL |
34170 | | #undef GET_RISCVTuneInfoTable_IMPL |
34171 | | #undef GET_RISCVVInversePseudosTable_DECL |
34172 | | #undef GET_RISCVVInversePseudosTable_IMPL |
34173 | | #undef GET_RISCVVLETable_DECL |
34174 | | #undef GET_RISCVVLETable_IMPL |
34175 | | #undef GET_RISCVVLSEGTable_DECL |
34176 | | #undef GET_RISCVVLSEGTable_IMPL |
34177 | | #undef GET_RISCVVLXSEGTable_DECL |
34178 | | #undef GET_RISCVVLXSEGTable_IMPL |
34179 | | #undef GET_RISCVVLXTable_DECL |
34180 | | #undef GET_RISCVVLXTable_IMPL |
34181 | | #undef GET_RISCVVPseudosTable_DECL |
34182 | | #undef GET_RISCVVPseudosTable_IMPL |
34183 | | #undef GET_RISCVVSETable_DECL |
34184 | | #undef GET_RISCVVSETable_IMPL |
34185 | | #undef GET_RISCVVSSEGTable_DECL |
34186 | | #undef GET_RISCVVSSEGTable_IMPL |
34187 | | #undef GET_RISCVVSXSEGTable_DECL |
34188 | | #undef GET_RISCVVSXSEGTable_IMPL |
34189 | | #undef GET_RISCVVSXTable_DECL |
34190 | | #undef GET_RISCVVSXTable_IMPL |
34191 | | #undef GET_SysRegsList_DECL |
34192 | | #undef GET_SysRegsList_IMPL |