Coverage Report

Created: 2026-03-03 06:15

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonenext/arch/AArch64/AArch64InstPrinter.h
Line
Count
Source
1
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
2
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
3
/*    Rot127 <unisono@quyllur.org> 2022-2023 */
4
/* Automatically translated source file from LLVM. */
5
6
/* LLVM-commit: <commit> */
7
/* LLVM-tag: <tag> */
8
9
/* Only small edits allowed. */
10
/* For multiple similar edits, please create a Patch for the translator. */
11
12
/* Capstone's C++ file translator: */
13
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
14
15
//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
16
//
17
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18
// See https://llvm.org/LICENSE.txt for license information.
19
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
20
//
21
//===----------------------------------------------------------------------===//
22
//
23
// This class prints an AArch64 MCInst to a .s file.
24
//
25
//===----------------------------------------------------------------------===//
26
27
#ifndef LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
28
#define LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H
29
30
#include <stdio.h>
31
#include <string.h>
32
#include <stdlib.h>
33
#include <capstone/platform.h>
34
35
#include "AArch64Mapping.h"
36
37
#include "../../MCInst.h"
38
#include "../../MCRegisterInfo.h"
39
#include "../../MCInstPrinter.h"
40
#include "../../SStream.h"
41
#include "../../utils.h"
42
43
11.3k
#define CONCAT(a, b) CONCAT_(a, b)
44
11.3k
#define CONCAT_(a, b) a##_##b
45
438k
#define CHAR(c) #c[0]
46
47
void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
48
void printRegName(SStream *OS, unsigned Reg);
49
void printRegNameAlt(SStream *OS, unsigned Reg, unsigned AltIdx);
50
// Autogenerated by tblgen.
51
const char *getRegName(unsigned Reg);
52
bool printSysAlias(MCInst *MI, SStream *O);
53
bool printSyspAlias(MCInst *MI, SStream *O);
54
bool printRangePrefetchAlias(MCInst *MI, SStream *O, const char *Annot);
55
// Operand printers
56
void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
57
void printImm(MCInst *MI, unsigned OpNo, SStream *O);
58
void printImmHex(MCInst *MI, unsigned OpNo, SStream *O);
59
#define DECLARE_printSImm(Size) \
60
  void CONCAT(printSImm, Size)(MCInst * MI, unsigned OpNo, SStream *O);
61
DECLARE_printSImm(16);
62
DECLARE_printSImm(8);
63
64
#define DECLARE_printImmSVE(T) void CONCAT(printImmSVE, T)(T Val, SStream * O);
65
DECLARE_printImmSVE(int16_t);
66
DECLARE_printImmSVE(int8_t);
67
DECLARE_printImmSVE(int64_t);
68
DECLARE_printImmSVE(int32_t);
69
DECLARE_printImmSVE(uint16_t);
70
DECLARE_printImmSVE(uint8_t);
71
DECLARE_printImmSVE(uint64_t);
72
DECLARE_printImmSVE(uint32_t);
73
74
void printPostIncOperand(MCInst *MI, unsigned OpNo, unsigned Imm, SStream *O);
75
#define DEFINE_printPostIncOperand(Amount) \
76
  static inline void CONCAT(printPostIncOperand, Amount)( \
77
    MCInst * MI, unsigned OpNo, SStream *O) \
78
6.48k
  { \
79
6.48k
    AArch64_add_cs_detail_1( \
80
6.48k
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
6.48k
      OpNo, Amount); \
82
6.48k
    printPostIncOperand(MI, OpNo, Amount, O); \
83
6.48k
  }
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_64
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_32
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_16
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_8
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_1
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_4
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_2
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_48
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_24
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_3
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_12
Unexecuted instantiation: AArch64Module.c:printPostIncOperand_6
AArch64InstPrinter.c:printPostIncOperand_64
Line
Count
Source
78
52
  { \
79
52
    AArch64_add_cs_detail_1( \
80
52
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
52
      OpNo, Amount); \
82
52
    printPostIncOperand(MI, OpNo, Amount, O); \
83
52
  }
AArch64InstPrinter.c:printPostIncOperand_32
Line
Count
Source
78
399
  { \
79
399
    AArch64_add_cs_detail_1( \
80
399
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
399
      OpNo, Amount); \
82
399
    printPostIncOperand(MI, OpNo, Amount, O); \
83
399
  }
AArch64InstPrinter.c:printPostIncOperand_16
Line
Count
Source
78
400
  { \
79
400
    AArch64_add_cs_detail_1( \
80
400
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
400
      OpNo, Amount); \
82
400
    printPostIncOperand(MI, OpNo, Amount, O); \
83
400
  }
AArch64InstPrinter.c:printPostIncOperand_8
Line
Count
Source
78
525
  { \
79
525
    AArch64_add_cs_detail_1( \
80
525
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
525
      OpNo, Amount); \
82
525
    printPostIncOperand(MI, OpNo, Amount, O); \
83
525
  }
AArch64InstPrinter.c:printPostIncOperand_1
Line
Count
Source
78
1.01k
  { \
79
1.01k
    AArch64_add_cs_detail_1( \
80
1.01k
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
1.01k
      OpNo, Amount); \
82
1.01k
    printPostIncOperand(MI, OpNo, Amount, O); \
83
1.01k
  }
AArch64InstPrinter.c:printPostIncOperand_4
Line
Count
Source
78
326
  { \
79
326
    AArch64_add_cs_detail_1( \
80
326
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
326
      OpNo, Amount); \
82
326
    printPostIncOperand(MI, OpNo, Amount, O); \
83
326
  }
AArch64InstPrinter.c:printPostIncOperand_2
Line
Count
Source
78
1.12k
  { \
79
1.12k
    AArch64_add_cs_detail_1( \
80
1.12k
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
1.12k
      OpNo, Amount); \
82
1.12k
    printPostIncOperand(MI, OpNo, Amount, O); \
83
1.12k
  }
AArch64InstPrinter.c:printPostIncOperand_48
Line
Count
Source
78
377
  { \
79
377
    AArch64_add_cs_detail_1( \
80
377
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
377
      OpNo, Amount); \
82
377
    printPostIncOperand(MI, OpNo, Amount, O); \
83
377
  }
AArch64InstPrinter.c:printPostIncOperand_24
Line
Count
Source
78
495
  { \
79
495
    AArch64_add_cs_detail_1( \
80
495
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
495
      OpNo, Amount); \
82
495
    printPostIncOperand(MI, OpNo, Amount, O); \
83
495
  }
AArch64InstPrinter.c:printPostIncOperand_3
Line
Count
Source
78
990
  { \
79
990
    AArch64_add_cs_detail_1( \
80
990
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
990
      OpNo, Amount); \
82
990
    printPostIncOperand(MI, OpNo, Amount, O); \
83
990
  }
AArch64InstPrinter.c:printPostIncOperand_12
Line
Count
Source
78
259
  { \
79
259
    AArch64_add_cs_detail_1( \
80
259
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
259
      OpNo, Amount); \
82
259
    printPostIncOperand(MI, OpNo, Amount, O); \
83
259
  }
AArch64InstPrinter.c:printPostIncOperand_6
Line
Count
Source
78
533
  { \
79
533
    AArch64_add_cs_detail_1( \
80
533
      MI, CONCAT(AArch64_OP_GROUP_PostIncOperand, Amount), \
81
533
      OpNo, Amount); \
82
533
    printPostIncOperand(MI, OpNo, Amount, O); \
83
533
  }
84
DEFINE_printPostIncOperand(64);
85
DEFINE_printPostIncOperand(32);
86
DEFINE_printPostIncOperand(16);
87
DEFINE_printPostIncOperand(8);
88
DEFINE_printPostIncOperand(1);
89
DEFINE_printPostIncOperand(4);
90
DEFINE_printPostIncOperand(2);
91
DEFINE_printPostIncOperand(48);
92
DEFINE_printPostIncOperand(24);
93
DEFINE_printPostIncOperand(3);
94
DEFINE_printPostIncOperand(12);
95
DEFINE_printPostIncOperand(6);
96
97
void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O);
98
void printSysCROperand(MCInst *MI, unsigned OpNo, SStream *O);
99
void printAddSubImm(MCInst *MI, unsigned OpNum, SStream *O);
100
#define DECLARE_printLogicalImm(T) \
101
  void CONCAT(printLogicalImm, T)(MCInst * MI, unsigned OpNum, \
102
          SStream *O);
103
DECLARE_printLogicalImm(int64_t);
104
DECLARE_printLogicalImm(int32_t);
105
DECLARE_printLogicalImm(int8_t);
106
DECLARE_printLogicalImm(int16_t);
107
108
void printShifter(MCInst *MI, unsigned OpNum, SStream *O);
109
void printShiftedRegister(MCInst *MI, unsigned OpNum, SStream *O);
110
void printExtendedRegister(MCInst *MI, unsigned OpNum, SStream *O);
111
void printArithExtend(MCInst *MI, unsigned OpNum, SStream *O);
112
113
void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
114
        unsigned Width);
115
void printMemExtend(MCInst *MI, unsigned OpNum, SStream *O, char SrcRegKind,
116
        unsigned Width);
117
#define DEFINE_printMemExtend(SrcRegKind, Width) \
118
  static inline void CONCAT(printMemExtend, CONCAT(SrcRegKind, Width))( \
119
    MCInst * MI, unsigned OpNum, SStream *O) \
120
1.12k
  { \
121
1.12k
    AArch64_add_cs_detail_2( \
122
1.12k
      MI, \
123
1.12k
      CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
124
1.12k
             Width), \
125
1.12k
      OpNum, CHAR(SrcRegKind), Width); \
126
1.12k
    printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
127
1.12k
  }
Unexecuted instantiation: AArch64Module.c:printMemExtend_w_8
Unexecuted instantiation: AArch64Module.c:printMemExtend_x_8
Unexecuted instantiation: AArch64Module.c:printMemExtend_w_64
Unexecuted instantiation: AArch64Module.c:printMemExtend_x_64
Unexecuted instantiation: AArch64Module.c:printMemExtend_w_16
Unexecuted instantiation: AArch64Module.c:printMemExtend_x_16
Unexecuted instantiation: AArch64Module.c:printMemExtend_w_128
Unexecuted instantiation: AArch64Module.c:printMemExtend_x_128
Unexecuted instantiation: AArch64Module.c:printMemExtend_w_32
Unexecuted instantiation: AArch64Module.c:printMemExtend_x_32
AArch64InstPrinter.c:printMemExtend_w_8
Line
Count
Source
120
100
  { \
121
100
    AArch64_add_cs_detail_2( \
122
100
      MI, \
123
100
      CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
124
100
             Width), \
125
100
      OpNum, CHAR(SrcRegKind), Width); \
126
100
    printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
127
100
  }
AArch64InstPrinter.c:printMemExtend_x_8
Line
Count
Source
120
316
  { \
121
316
    AArch64_add_cs_detail_2( \
122
316
      MI, \
123
316
      CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
124
316
             Width), \
125
316
      OpNum, CHAR(SrcRegKind), Width); \
126
316
    printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
127
316
  }
AArch64InstPrinter.c:printMemExtend_w_64
Line
Count
Source
120
131
  { \
121
131
    AArch64_add_cs_detail_2( \
122
131
      MI, \
123
131
      CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
124
131
             Width), \
125
131
      OpNum, CHAR(SrcRegKind), Width); \
126
131
    printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
127
131
  }
AArch64InstPrinter.c:printMemExtend_x_64
Line
Count
Source
120
214
  { \
121
214
    AArch64_add_cs_detail_2( \
122
214
      MI, \
123
214
      CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
124
214
             Width), \
125
214
      OpNum, CHAR(SrcRegKind), Width); \
126
214
    printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
127
214
  }
AArch64InstPrinter.c:printMemExtend_w_16
Line
Count
Source
120
34
  { \
121
34
    AArch64_add_cs_detail_2( \
122
34
      MI, \
123
34
      CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
124
34
             Width), \
125
34
      OpNum, CHAR(SrcRegKind), Width); \
126
34
    printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
127
34
  }
AArch64InstPrinter.c:printMemExtend_x_16
Line
Count
Source
120
172
  { \
121
172
    AArch64_add_cs_detail_2( \
122
172
      MI, \
123
172
      CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
124
172
             Width), \
125
172
      OpNum, CHAR(SrcRegKind), Width); \
126
172
    printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
127
172
  }
AArch64InstPrinter.c:printMemExtend_w_128
Line
Count
Source
120
12
  { \
121
12
    AArch64_add_cs_detail_2( \
122
12
      MI, \
123
12
      CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
124
12
             Width), \
125
12
      OpNum, CHAR(SrcRegKind), Width); \
126
12
    printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
127
12
  }
AArch64InstPrinter.c:printMemExtend_x_128
Line
Count
Source
120
81
  { \
121
81
    AArch64_add_cs_detail_2( \
122
81
      MI, \
123
81
      CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
124
81
             Width), \
125
81
      OpNum, CHAR(SrcRegKind), Width); \
126
81
    printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
127
81
  }
AArch64InstPrinter.c:printMemExtend_w_32
Line
Count
Source
120
21
  { \
121
21
    AArch64_add_cs_detail_2( \
122
21
      MI, \
123
21
      CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
124
21
             Width), \
125
21
      OpNum, CHAR(SrcRegKind), Width); \
126
21
    printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
127
21
  }
AArch64InstPrinter.c:printMemExtend_x_32
Line
Count
Source
120
39
  { \
121
39
    AArch64_add_cs_detail_2( \
122
39
      MI, \
123
39
      CONCAT(CONCAT(AArch64_OP_GROUP_MemExtend, SrcRegKind), \
124
39
             Width), \
125
39
      OpNum, CHAR(SrcRegKind), Width); \
126
39
    printMemExtend(MI, OpNum, O, CHAR(SrcRegKind), Width); \
127
39
  }
128
DEFINE_printMemExtend(w, 8);
129
DEFINE_printMemExtend(x, 8);
130
DEFINE_printMemExtend(w, 64);
131
DEFINE_printMemExtend(x, 64);
132
DEFINE_printMemExtend(w, 16);
133
DEFINE_printMemExtend(x, 16);
134
DEFINE_printMemExtend(w, 128);
135
DEFINE_printMemExtend(x, 128);
136
DEFINE_printMemExtend(w, 32);
137
DEFINE_printMemExtend(x, 32);
138
139
#define DECLARE_printRegWithShiftExtend(SignedExtend, ExtWidth, SrcRegKind, \
140
          Suffix) \
141
  void CONCAT(printRegWithShiftExtend, \
142
        CONCAT(SignedExtend, \
143
         CONCAT(ExtWidth, CONCAT(SrcRegKind, Suffix))))( \
144
    MCInst * MI, unsigned OpNum, SStream *O);
145
DECLARE_printRegWithShiftExtend(false, 8, x, d);
146
DECLARE_printRegWithShiftExtend(true, 8, w, d);
147
DECLARE_printRegWithShiftExtend(false, 8, w, d);
148
DECLARE_printRegWithShiftExtend(false, 8, x, 0);
149
DECLARE_printRegWithShiftExtend(true, 8, w, s);
150
DECLARE_printRegWithShiftExtend(false, 8, w, s);
151
DECLARE_printRegWithShiftExtend(false, 64, x, d);
152
DECLARE_printRegWithShiftExtend(true, 64, w, d);
153
DECLARE_printRegWithShiftExtend(false, 64, w, d);
154
DECLARE_printRegWithShiftExtend(false, 64, x, 0);
155
DECLARE_printRegWithShiftExtend(true, 64, w, s);
156
DECLARE_printRegWithShiftExtend(false, 64, w, s);
157
DECLARE_printRegWithShiftExtend(false, 16, x, d);
158
DECLARE_printRegWithShiftExtend(true, 16, w, d);
159
DECLARE_printRegWithShiftExtend(false, 16, w, d);
160
DECLARE_printRegWithShiftExtend(false, 16, x, 0);
161
DECLARE_printRegWithShiftExtend(true, 16, w, s);
162
DECLARE_printRegWithShiftExtend(false, 16, w, s);
163
DECLARE_printRegWithShiftExtend(false, 32, x, d);
164
DECLARE_printRegWithShiftExtend(true, 32, w, d);
165
DECLARE_printRegWithShiftExtend(false, 32, w, d);
166
DECLARE_printRegWithShiftExtend(false, 32, x, 0);
167
DECLARE_printRegWithShiftExtend(true, 32, w, s);
168
DECLARE_printRegWithShiftExtend(false, 32, w, s);
169
DECLARE_printRegWithShiftExtend(false, 8, x, s);
170
DECLARE_printRegWithShiftExtend(false, 16, x, s);
171
DECLARE_printRegWithShiftExtend(false, 32, x, s);
172
DECLARE_printRegWithShiftExtend(false, 64, x, s);
173
DECLARE_printRegWithShiftExtend(false, 128, x, 0);
174
175
void printCondCode(MCInst *MI, unsigned OpNum, SStream *O);
176
void printInverseCondCode(MCInst *MI, unsigned OpNum, SStream *O);
177
void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
178
           SStream *O);
179
void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
180
void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O);
181
#define DEFINE_printUImm12Offset(Scale) \
182
  static inline void CONCAT(printUImm12Offset, Scale)( \
183
    MCInst * MI, unsigned OpNum, SStream *O) \
184
3.78k
  { \
185
3.78k
    AArch64_add_cs_detail_1( \
186
3.78k
      MI, CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
187
3.78k
      OpNum, Scale); \
188
3.78k
    printUImm12Offset(MI, OpNum, Scale, O); \
189
3.78k
  }
Unexecuted instantiation: AArch64Module.c:printUImm12Offset_1
Unexecuted instantiation: AArch64Module.c:printUImm12Offset_8
Unexecuted instantiation: AArch64Module.c:printUImm12Offset_2
Unexecuted instantiation: AArch64Module.c:printUImm12Offset_16
Unexecuted instantiation: AArch64Module.c:printUImm12Offset_4
AArch64InstPrinter.c:printUImm12Offset_1
Line
Count
Source
184
1.60k
  { \
185
1.60k
    AArch64_add_cs_detail_1( \
186
1.60k
      MI, CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
187
1.60k
      OpNum, Scale); \
188
1.60k
    printUImm12Offset(MI, OpNum, Scale, O); \
189
1.60k
  }
AArch64InstPrinter.c:printUImm12Offset_8
Line
Count
Source
184
975
  { \
185
975
    AArch64_add_cs_detail_1( \
186
975
      MI, CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
187
975
      OpNum, Scale); \
188
975
    printUImm12Offset(MI, OpNum, Scale, O); \
189
975
  }
AArch64InstPrinter.c:printUImm12Offset_2
Line
Count
Source
184
330
  { \
185
330
    AArch64_add_cs_detail_1( \
186
330
      MI, CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
187
330
      OpNum, Scale); \
188
330
    printUImm12Offset(MI, OpNum, Scale, O); \
189
330
  }
AArch64InstPrinter.c:printUImm12Offset_16
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Source
184
142
  { \
185
142
    AArch64_add_cs_detail_1( \
186
142
      MI, CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
187
142
      OpNum, Scale); \
188
142
    printUImm12Offset(MI, OpNum, Scale, O); \
189
142
  }
AArch64InstPrinter.c:printUImm12Offset_4
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184
739
  { \
185
739
    AArch64_add_cs_detail_1( \
186
739
      MI, CONCAT(AArch64_OP_GROUP_UImm12Offset, Scale), \
187
739
      OpNum, Scale); \
188
739
    printUImm12Offset(MI, OpNum, Scale, O); \
189
739
  }
190
DEFINE_printUImm12Offset(1);
191
DEFINE_printUImm12Offset(8);
192
DEFINE_printUImm12Offset(2);
193
DEFINE_printUImm12Offset(16);
194
DEFINE_printUImm12Offset(4);
195
196
void printAMNoIndex(MCInst *MI, unsigned OpNum, SStream *O);
197
#define DECLARE_printImmScale(Scale) \
198
  void CONCAT(printImmScale, Scale)(MCInst * MI, unsigned OpNum, \
199
            SStream *O);
200
DECLARE_printImmScale(8);
201
DECLARE_printImmScale(2);
202
DECLARE_printImmScale(4);
203
DECLARE_printImmScale(16);
204
DECLARE_printImmScale(32);
205
DECLARE_printImmScale(3);
206
207
#define DECLARE_printImmRangeScale(Scale, Offset) \
208
  void CONCAT(printImmRangeScale, CONCAT(Scale, Offset))( \
209
    MCInst * MI, unsigned OpNum, SStream *O);
210
DECLARE_printImmRangeScale(2, 1);
211
DECLARE_printImmRangeScale(4, 3);
212
213
#define DECLARE_printPrefetchOp(IsSVEPrefetch) \
214
  void CONCAT(printPrefetchOp, \
215
        IsSVEPrefetch)(MCInst * MI, unsigned OpNum, SStream *O);
216
DECLARE_printPrefetchOp(true);
217
DECLARE_printPrefetchOp(false);
218
219
void printRPRFMOperand(MCInst *MI, unsigned OpNum, SStream *O);
220
void printPSBHintOp(MCInst *MI, unsigned OpNum, SStream *O);
221
void printBTIHintOp(MCInst *MI, unsigned OpNum, SStream *O);
222
void printVectorList(MCInst *MI, unsigned OpNum, SStream *O,
223
         const char *LayoutSuffix);
224
void printMatrixTileList(MCInst *MI, unsigned OpNum, SStream *O);
225
/// (i.e. attached to the instruction rather than the registers).
226
/// Print a list of vector registers where the type suffix is implicit
227
void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O);
228
#define DECLARE_printTypedVectorList(NumLanes, LaneKind) \
229
  void CONCAT(printTypedVectorList, CONCAT(NumLanes, LaneKind))( \
230
    MCInst * MI, unsigned OpNum, SStream *O);
231
DECLARE_printTypedVectorList(0, b);
232
DECLARE_printTypedVectorList(0, d);
233
DECLARE_printTypedVectorList(0, h);
234
DECLARE_printTypedVectorList(0, s);
235
DECLARE_printTypedVectorList(0, q);
236
DECLARE_printTypedVectorList(16, b);
237
DECLARE_printTypedVectorList(1, d);
238
DECLARE_printTypedVectorList(2, d);
239
DECLARE_printTypedVectorList(2, s);
240
DECLARE_printTypedVectorList(4, h);
241
DECLARE_printTypedVectorList(4, s);
242
DECLARE_printTypedVectorList(8, b);
243
DECLARE_printTypedVectorList(8, h);
244
DECLARE_printTypedVectorList(0, 0);
245
246
#define DECLARE_printVectorIndex(Scale) \
247
  void CONCAT(printVectorIndex, Scale)(MCInst * MI, unsigned OpNum, \
248
               SStream *O);
249
DECLARE_printVectorIndex(1);
250
DECLARE_printVectorIndex(8);
251
252
void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum,
253
           SStream *O);
254
void printAppleSysBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
255
void printBarrierOption(MCInst *MI, unsigned OpNum, SStream *O);
256
void printBarriernXSOption(MCInst *MI, unsigned OpNum, SStream *O);
257
void printMSRSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
258
void printMRSSystemRegister(MCInst *MI, unsigned OpNum, SStream *O);
259
void printSystemPStateField(MCInst *MI, unsigned OpNum, SStream *O);
260
void printSIMDType10Operand(MCInst *MI, unsigned OpNum, SStream *O);
261
#define DECLARE_printPredicateAsCounter(EltSize) \
262
  void CONCAT(printPredicateAsCounter, \
263
        EltSize)(MCInst * MI, unsigned OpNum, SStream *O);
264
DECLARE_printPredicateAsCounter(8);
265
DECLARE_printPredicateAsCounter(64);
266
DECLARE_printPredicateAsCounter(16);
267
DECLARE_printPredicateAsCounter(32);
268
DECLARE_printPredicateAsCounter(0);
269
270
#define DECLARE_printGPRSeqPairsClassOperand(size) \
271
  void CONCAT(printGPRSeqPairsClassOperand, \
272
        size)(MCInst * MI, unsigned OpNum, SStream *O);
273
DECLARE_printGPRSeqPairsClassOperand(32);
274
DECLARE_printGPRSeqPairsClassOperand(64);
275
276
#define DECLARE_printImm8OptLsl(T) \
277
  void CONCAT(printImm8OptLsl, T)(MCInst * MI, unsigned OpNum, \
278
          SStream *O);
279
DECLARE_printImm8OptLsl(int16_t);
280
DECLARE_printImm8OptLsl(int8_t);
281
DECLARE_printImm8OptLsl(int64_t);
282
DECLARE_printImm8OptLsl(int32_t);
283
DECLARE_printImm8OptLsl(uint16_t);
284
DECLARE_printImm8OptLsl(uint8_t);
285
DECLARE_printImm8OptLsl(uint64_t);
286
DECLARE_printImm8OptLsl(uint32_t);
287
288
#define DECLARE_printSVELogicalImm(T) \
289
  void CONCAT(printSVELogicalImm, T)(MCInst * MI, unsigned OpNum, \
290
             SStream *O);
291
DECLARE_printSVELogicalImm(int16_t);
292
DECLARE_printSVELogicalImm(int32_t);
293
DECLARE_printSVELogicalImm(int64_t);
294
295
void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O);
296
void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O);
297
#define DECLARE_printMatrixTileVector(IsVertical) \
298
  void CONCAT(printMatrixTileVector, \
299
        IsVertical)(MCInst * MI, unsigned OpNum, SStream *O);
300
DECLARE_printMatrixTileVector(0);
301
DECLARE_printMatrixTileVector(1);
302
303
void printMatrixTile(MCInst *MI, unsigned OpNum, SStream *O);
304
#define DECLARE_printMatrix(EltSize) \
305
  void CONCAT(printMatrix, EltSize)(MCInst * MI, unsigned OpNum, \
306
            SStream *O);
307
DECLARE_printMatrix(64);
308
DECLARE_printMatrix(32);
309
DECLARE_printMatrix(16);
310
DECLARE_printMatrix(0);
311
312
void printSVCROp(MCInst *MI, unsigned OpNum, SStream *O);
313
#define DECLARE_printSVERegOp(char) \
314
  void CONCAT(printSVERegOp, char)(MCInst * MI, unsigned OpNum, \
315
           SStream *O);
316
DECLARE_printSVERegOp(b);
317
DECLARE_printSVERegOp(d);
318
DECLARE_printSVERegOp(h);
319
DECLARE_printSVERegOp(s);
320
DECLARE_printSVERegOp(0);
321
DECLARE_printSVERegOp(q);
322
323
void printGPR64as32(MCInst *MI, unsigned OpNum, SStream *O);
324
void printGPR64x8(MCInst *MI, unsigned OpNum, SStream *O);
325
void printSyspXzrPair(MCInst *MI, unsigned OpNum, SStream *O);
326
#define DECLARE_printZPRasFPR(Width) \
327
  void CONCAT(printZPRasFPR, Width)(MCInst * MI, unsigned OpNum, \
328
            SStream *O);
329
DECLARE_printZPRasFPR(8);
330
DECLARE_printZPRasFPR(64);
331
DECLARE_printZPRasFPR(16);
332
DECLARE_printZPRasFPR(32);
333
DECLARE_printZPRasFPR(128);
334
335
#define DECLARE_printExactFPImm(ImmIs0, ImmIs1) \
336
  void CONCAT(printExactFPImm, CONCAT(ImmIs0, ImmIs1))( \
337
    MCInst * MI, unsigned OpNum, SStream *O);
338
DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_one);
339
DECLARE_printExactFPImm(AArch64ExactFPImm_zero, AArch64ExactFPImm_one);
340
DECLARE_printExactFPImm(AArch64ExactFPImm_half, AArch64ExactFPImm_two);
341
342
#define DECLARE_printMatrixIndex(Scale) \
343
  void CONCAT(printMatrixIndex, Scale)(MCInst * MI, unsigned OpNum, \
344
               SStream *O);
345
DECLARE_printMatrixIndex(8);
346
DECLARE_printMatrixIndex(0);
347
DECLARE_printMatrixIndex(1);
348
349
// end namespace llvm
350
351
#endif // LLVM_LIB_TARGET_AARCH64_MCTARGETDESC_AARCH64INSTPRINTER_H