Coverage Report

Created: 2026-03-03 06:15

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonenext/arch/Xtensa/XtensaDisassembler.c
Line
Count
Source
1
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
2
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
3
/*    Rot127 <unisono@quyllur.org> 2022-2023 */
4
/* Automatically translated source file from LLVM. */
5
6
/* LLVM-commit: <commit> */
7
/* LLVM-tag: <tag> */
8
9
/* Only small edits allowed. */
10
/* For multiple similar edits, please create a Patch for the translator. */
11
12
/* Capstone's C++ file translator: */
13
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
14
15
//===-- XtensaDisassembler.cpp - Disassembler for Xtensa ------------------===//
16
//
17
//                     The LLVM Compiler Infrastructure
18
//
19
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
20
// See https://llvm.org/LICENSE.txt for license information.
21
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
22
//
23
//===----------------------------------------------------------------------===//
24
//
25
// This file implements the XtensaDisassembler class.
26
//
27
//===----------------------------------------------------------------------===//
28
29
#include <stdio.h>
30
#include <string.h>
31
#include <stdlib.h>
32
#include <capstone/platform.h>
33
34
#include "../../MathExtras.h"
35
#include "../../MCDisassembler.h"
36
#include "../../MCFixedLenDisassembler.h"
37
#include "../../SStream.h"
38
#include "../../cs_priv.h"
39
#include "../../utils.h"
40
41
#include "priv.h"
42
43
#define GET_INSTRINFO_MC_DESC
44
#include "XtensaGenInstrInfo.inc"
45
46
#define CONCAT(a, b) CONCAT_(a, b)
47
#define CONCAT_(a, b) a##_##b
48
49
#define DEBUG_TYPE "Xtensa-disassembler"
50
51
static const unsigned ARDecoderTable[] = {
52
  Xtensa_A0,  Xtensa_SP,  Xtensa_A2,  Xtensa_A3, Xtensa_A4,  Xtensa_A5,
53
  Xtensa_A6,  Xtensa_A7,  Xtensa_A8,  Xtensa_A9, Xtensa_A10, Xtensa_A11,
54
  Xtensa_A12, Xtensa_A13, Xtensa_A14, Xtensa_A15
55
};
56
57
static const unsigned AE_DRDecoderTable[] = {
58
  Xtensa_AED0,  Xtensa_AED1,  Xtensa_AED2,  Xtensa_AED3,
59
  Xtensa_AED4,  Xtensa_AED5,  Xtensa_AED6,  Xtensa_AED7,
60
  Xtensa_AED8,  Xtensa_AED9,  Xtensa_AED10, Xtensa_AED11,
61
  Xtensa_AED12, Xtensa_AED13, Xtensa_AED14, Xtensa_AED15
62
};
63
64
static const unsigned AE_VALIGNDecoderTable[] = { Xtensa_U0, Xtensa_U1,
65
              Xtensa_U2, Xtensa_U3 };
66
67
static DecodeStatus DecodeAE_DRRegisterClass(MCInst *Inst, uint64_t RegNo,
68
               uint64_t Address,
69
               const void *Decoder)
70
53
{
71
53
  if (RegNo >= ARR_SIZE(AE_DRDecoderTable))
72
0
    return MCDisassembler_Fail;
73
74
53
  unsigned Reg = AE_DRDecoderTable[RegNo];
75
53
  MCOperand_CreateReg0(Inst, (Reg));
76
53
  return MCDisassembler_Success;
77
53
}
78
79
static DecodeStatus DecodeAE_VALIGNRegisterClass(MCInst *Inst, uint64_t RegNo,
80
             uint64_t Address,
81
             const void *Decoder)
82
48
{
83
48
  if (RegNo >= ARR_SIZE(AE_VALIGNDecoderTable))
84
0
    return MCDisassembler_Fail;
85
86
48
  unsigned Reg = AE_VALIGNDecoderTable[RegNo];
87
48
  MCOperand_CreateReg0(Inst, (Reg));
88
48
  return MCDisassembler_Success;
89
48
}
90
91
static DecodeStatus DecodeARRegisterClass(MCInst *Inst, uint64_t RegNo,
92
            uint64_t Address, const void *Decoder)
93
40.9k
{
94
40.9k
  if (RegNo >= ARR_SIZE(ARDecoderTable))
95
0
    return MCDisassembler_Fail;
96
97
40.9k
  unsigned Reg = ARDecoderTable[RegNo];
98
40.9k
  MCOperand_CreateReg0(Inst, (Reg));
99
40.9k
  return MCDisassembler_Success;
100
40.9k
}
101
102
static const unsigned QRDecoderTable[] = { Xtensa_Q0, Xtensa_Q1, Xtensa_Q2,
103
             Xtensa_Q3, Xtensa_Q4, Xtensa_Q5,
104
             Xtensa_Q6, Xtensa_Q7 };
105
106
static DecodeStatus DecodeQRRegisterClass(MCInst *Inst, uint64_t RegNo,
107
            uint64_t Address, const void *Decoder)
108
13.5k
{
109
13.5k
  if (RegNo >= ARR_SIZE(QRDecoderTable))
110
0
    return MCDisassembler_Fail;
111
112
13.5k
  unsigned Reg = QRDecoderTable[RegNo];
113
13.5k
  MCOperand_CreateReg0(Inst, (Reg));
114
13.5k
  return MCDisassembler_Success;
115
13.5k
}
116
117
static const unsigned FPRDecoderTable[] = {
118
  Xtensa_F0,  Xtensa_F1,  Xtensa_F2,  Xtensa_F3, Xtensa_F4,  Xtensa_F5,
119
  Xtensa_F6,  Xtensa_F7,  Xtensa_F8,  Xtensa_F9, Xtensa_F10, Xtensa_F11,
120
  Xtensa_F12, Xtensa_F13, Xtensa_F14, Xtensa_F15
121
};
122
123
static DecodeStatus DecodeFPRRegisterClass(MCInst *Inst, uint64_t RegNo,
124
             uint64_t Address,
125
             const void *Decoder)
126
3.63k
{
127
3.63k
  if (RegNo >= ARR_SIZE(FPRDecoderTable))
128
0
    return MCDisassembler_Fail;
129
130
3.63k
  unsigned Reg = FPRDecoderTable[RegNo];
131
3.63k
  MCOperand_CreateReg0(Inst, (Reg));
132
3.63k
  return MCDisassembler_Success;
133
3.63k
}
134
135
static const unsigned BRDecoderTable[] = {
136
  Xtensa_B0,  Xtensa_B1,  Xtensa_B2,  Xtensa_B3, Xtensa_B4,  Xtensa_B5,
137
  Xtensa_B6,  Xtensa_B7,  Xtensa_B8,  Xtensa_B9, Xtensa_B10, Xtensa_B11,
138
  Xtensa_B12, Xtensa_B13, Xtensa_B14, Xtensa_B15
139
};
140
141
static const unsigned BR2DecoderTable[] = { Xtensa_B0_B1,   Xtensa_B2_B3,
142
              Xtensa_B4_B5,   Xtensa_B6_B7,
143
              Xtensa_B8_B9,   Xtensa_B10_B11,
144
              Xtensa_B12_B13, Xtensa_B14_B15 };
145
146
static const unsigned BR4DecoderTable[] = { Xtensa_B0_B1_B2_B3,
147
              Xtensa_B4_B5_B6_B7,
148
              Xtensa_B8_B9_B10_B11,
149
              Xtensa_B12_B13_B14_B15 };
150
151
static DecodeStatus DecodeXtensaRegisterClass(MCInst *Inst, uint64_t RegNo,
152
                uint64_t Address,
153
                const void *Decoder,
154
                const unsigned *DecoderTable,
155
                size_t DecoderTableLen)
156
0
{
157
0
  if (RegNo >= DecoderTableLen)
158
0
    return MCDisassembler_Fail;
159
160
0
  unsigned Reg = DecoderTable[RegNo];
161
0
  MCOperand_CreateReg0(Inst, (Reg));
162
0
  return MCDisassembler_Success;
163
0
}
164
165
static DecodeStatus DecodeBR2RegisterClass(MCInst *Inst, uint64_t RegNo,
166
             uint64_t Address,
167
             const void *Decoder)
168
0
{
169
0
  return DecodeXtensaRegisterClass(Inst, RegNo, Address, Decoder,
170
0
           BR2DecoderTable,
171
0
           ARR_SIZE(BR2DecoderTable));
172
0
}
173
174
static DecodeStatus DecodeBR4RegisterClass(MCInst *Inst, uint64_t RegNo,
175
             uint64_t Address,
176
             const void *Decoder)
177
0
{
178
0
  return DecodeXtensaRegisterClass(Inst, RegNo, Address, Decoder,
179
0
           BR4DecoderTable,
180
0
           ARR_SIZE(BR4DecoderTable));
181
0
}
182
183
static DecodeStatus DecodeBRRegisterClass(MCInst *Inst, uint64_t RegNo,
184
            uint64_t Address, const void *Decoder)
185
1.17k
{
186
1.17k
  if (RegNo >= ARR_SIZE(BRDecoderTable))
187
0
    return MCDisassembler_Fail;
188
189
1.17k
  unsigned Reg = BRDecoderTable[RegNo];
190
1.17k
  MCOperand_CreateReg0(Inst, (Reg));
191
1.17k
  return MCDisassembler_Success;
192
1.17k
}
193
194
static const unsigned MRDecoderTable[] = { Xtensa_M0, Xtensa_M1, Xtensa_M2,
195
             Xtensa_M3 };
196
197
static DecodeStatus DecodeMRRegisterClass(MCInst *Inst, uint64_t RegNo,
198
            uint64_t Address, const void *Decoder)
199
252
{
200
252
  if (RegNo >= ARR_SIZE(MRDecoderTable))
201
0
    return MCDisassembler_Fail;
202
203
252
  unsigned Reg = MRDecoderTable[RegNo];
204
252
  MCOperand_CreateReg0(Inst, (Reg));
205
252
  return MCDisassembler_Success;
206
252
}
207
208
static const unsigned MR01DecoderTable[] = { Xtensa_M0, Xtensa_M1 };
209
210
static DecodeStatus DecodeMR01RegisterClass(MCInst *Inst, uint64_t RegNo,
211
              uint64_t Address,
212
              const void *Decoder)
213
245
{
214
245
  if (RegNo >= ARR_SIZE(MR01DecoderTable))
215
0
    return MCDisassembler_Fail;
216
217
245
  unsigned Reg = MR01DecoderTable[RegNo];
218
245
  MCOperand_CreateReg0(Inst, (Reg));
219
245
  return MCDisassembler_Success;
220
245
}
221
222
static const unsigned MR23DecoderTable[] = { Xtensa_M2, Xtensa_M3 };
223
224
static DecodeStatus DecodeMR23RegisterClass(MCInst *Inst, uint64_t RegNo,
225
              uint64_t Address,
226
              const void *Decoder)
227
31
{
228
31
  if (RegNo >= ARR_SIZE(MR23DecoderTable))
229
0
    return MCDisassembler_Fail;
230
231
31
  unsigned Reg = MR23DecoderTable[RegNo];
232
31
  MCOperand_CreateReg0(Inst, (Reg));
233
31
  return MCDisassembler_Success;
234
31
}
235
236
bool Xtensa_getFeatureBits(unsigned int mode, unsigned int feature)
237
17.0k
{
238
  // we support everything
239
17.0k
  return true;
240
17.0k
}
241
242
// Verify SR and UR
243
bool CheckRegister(MCInst *Inst, unsigned RegNo)
244
805
{
245
805
  unsigned NumIntLevels = 0;
246
805
  unsigned NumTimers = 0;
247
805
  unsigned NumMiscSR = 0;
248
805
  bool IsESP32 = false;
249
805
  bool IsESP32S2 = false;
250
805
  bool Res = true;
251
252
  // Assume that CPU is esp32 by default
253
805
  if ((Inst->csh->mode & CS_MODE_XTENSA_ESP32)) {
254
238
    NumIntLevels = 6;
255
238
    NumTimers = 3;
256
238
    NumMiscSR = 4;
257
238
    IsESP32 = true;
258
567
  } else if (Inst->csh->mode & CS_MODE_XTENSA_ESP32S2) {
259
560
    NumIntLevels = 6;
260
560
    NumTimers = 3;
261
560
    NumMiscSR = 4;
262
560
    IsESP32S2 = true;
263
560
  } else if (Inst->csh->mode & CS_MODE_XTENSA_ESP8266) {
264
7
    NumIntLevels = 2;
265
7
    NumTimers = 1;
266
7
  }
267
268
805
  switch (RegNo) {
269
126
  case Xtensa_LBEG:
270
130
  case Xtensa_LEND:
271
235
  case Xtensa_LCOUNT:
272
235
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
273
235
              Xtensa_FeatureLoop);
274
235
    break;
275
0
  case Xtensa_BREG:
276
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
277
0
              Xtensa_FeatureBoolean);
278
0
    break;
279
2
  case Xtensa_LITBASE:
280
2
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
281
2
              Xtensa_FeatureExtendedL32R);
282
2
    break;
283
0
  case Xtensa_SCOMPARE1:
284
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
285
0
              Xtensa_FeatureS32C1I);
286
0
    break;
287
76
  case Xtensa_ACCLO:
288
78
  case Xtensa_ACCHI:
289
78
  case Xtensa_M0:
290
78
  case Xtensa_M1:
291
78
  case Xtensa_M2:
292
78
  case Xtensa_M3:
293
78
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
294
78
              Xtensa_FeatureMAC16);
295
78
    break;
296
0
  case Xtensa_WINDOWBASE:
297
0
  case Xtensa_WINDOWSTART:
298
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
299
0
              Xtensa_FeatureWindowed);
300
0
    break;
301
0
  case Xtensa_IBREAKENABLE:
302
0
  case Xtensa_IBREAKA0:
303
0
  case Xtensa_IBREAKA1:
304
0
  case Xtensa_DBREAKA0:
305
0
  case Xtensa_DBREAKA1:
306
0
  case Xtensa_DBREAKC0:
307
0
  case Xtensa_DBREAKC1:
308
0
  case Xtensa_DEBUGCAUSE:
309
0
  case Xtensa_ICOUNT:
310
0
  case Xtensa_ICOUNTLEVEL:
311
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
312
0
              Xtensa_FeatureDebug);
313
0
    break;
314
0
  case Xtensa_ATOMCTL:
315
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
316
0
              Xtensa_FeatureATOMCTL);
317
0
    break;
318
2
  case Xtensa_MEMCTL:
319
2
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
320
2
              Xtensa_FeatureMEMCTL);
321
2
    break;
322
0
  case Xtensa_EPC1:
323
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
324
0
              Xtensa_FeatureException);
325
0
    break;
326
162
  case Xtensa_EPC2:
327
344
  case Xtensa_EPC3:
328
360
  case Xtensa_EPC4:
329
362
  case Xtensa_EPC5:
330
370
  case Xtensa_EPC6:
331
372
  case Xtensa_EPC7:
332
372
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
333
372
              Xtensa_FeatureHighPriInterrupts);
334
372
    Res = Res & (NumIntLevels >= (RegNo - Xtensa_EPC1));
335
372
    break;
336
0
  case Xtensa_EPS2:
337
56
  case Xtensa_EPS3:
338
57
  case Xtensa_EPS4:
339
59
  case Xtensa_EPS5:
340
59
  case Xtensa_EPS6:
341
66
  case Xtensa_EPS7:
342
66
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
343
66
              Xtensa_FeatureHighPriInterrupts);
344
66
    Res = Res & (NumIntLevels > (RegNo - Xtensa_EPS2));
345
66
    break;
346
0
  case Xtensa_EXCSAVE1:
347
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
348
0
              Xtensa_FeatureException);
349
0
    break;
350
5
  case Xtensa_EXCSAVE2:
351
5
  case Xtensa_EXCSAVE3:
352
8
  case Xtensa_EXCSAVE4:
353
9
  case Xtensa_EXCSAVE5:
354
9
  case Xtensa_EXCSAVE6:
355
15
  case Xtensa_EXCSAVE7:
356
15
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
357
15
              Xtensa_FeatureHighPriInterrupts);
358
15
    Res = Res & (NumIntLevels >= (RegNo - Xtensa_EXCSAVE1));
359
15
    break;
360
0
  case Xtensa_DEPC:
361
0
  case Xtensa_EXCCAUSE:
362
0
  case Xtensa_EXCVADDR:
363
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
364
0
              Xtensa_FeatureException);
365
0
    break;
366
0
  case Xtensa_CPENABLE:
367
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
368
0
              Xtensa_FeatureCoprocessor);
369
0
    break;
370
0
  case Xtensa_VECBASE:
371
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
372
0
              Xtensa_FeatureRelocatableVector);
373
0
    break;
374
1
  case Xtensa_CCOUNT:
375
1
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
376
1
              Xtensa_FeatureTimerInt);
377
1
    Res &= (NumTimers > 0);
378
1
    break;
379
4
  case Xtensa_CCOMPARE0:
380
12
  case Xtensa_CCOMPARE1:
381
12
  case Xtensa_CCOMPARE2:
382
12
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
383
12
              Xtensa_FeatureTimerInt);
384
12
    Res &= (NumTimers > (RegNo - Xtensa_CCOMPARE0));
385
12
    break;
386
0
  case Xtensa_PRID:
387
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
388
0
              Xtensa_FeaturePRID);
389
0
    break;
390
0
  case Xtensa_INTERRUPT:
391
0
  case Xtensa_INTCLEAR:
392
0
  case Xtensa_INTENABLE:
393
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
394
0
              Xtensa_FeatureInterrupt);
395
0
    break;
396
5
  case Xtensa_MISC0:
397
5
  case Xtensa_MISC1:
398
7
  case Xtensa_MISC2:
399
7
  case Xtensa_MISC3:
400
7
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
401
7
              Xtensa_FeatureMiscSR);
402
7
    Res &= (NumMiscSR > (RegNo - Xtensa_MISC0));
403
7
    break;
404
5
  case Xtensa_THREADPTR:
405
5
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
406
5
              Xtensa_FeatureTHREADPTR);
407
5
    break;
408
3
  case Xtensa_GPIO_OUT:
409
3
    Res = IsESP32S2;
410
3
    break;
411
7
  case Xtensa_EXPSTATE:
412
7
    Res = IsESP32;
413
7
    break;
414
0
  case Xtensa_FCR:
415
0
  case Xtensa_FSR:
416
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
417
0
              Xtensa_FeatureSingleFloat);
418
0
    break;
419
0
  case Xtensa_F64R_LO:
420
0
  case Xtensa_F64R_HI:
421
0
  case Xtensa_F64S:
422
0
    Res = Xtensa_getFeatureBits(Inst->csh->mode,
423
0
              Xtensa_FeatureDFPAccel);
424
0
    break;
425
805
  }
426
427
805
  return Res;
428
805
}
429
430
static const unsigned SRDecoderTable[] = {
431
  Xtensa_LBEG,      0,   Xtensa_LEND,       1,
432
  Xtensa_LCOUNT,      2,   Xtensa_SAR,        3,
433
  Xtensa_BREG,      4,   Xtensa_LITBASE,      5,
434
  Xtensa_SCOMPARE1,   12,  Xtensa_ACCLO,        16,
435
  Xtensa_ACCHI,     17,  Xtensa_M0,       32,
436
  Xtensa_M1,      33,  Xtensa_M2,       34,
437
  Xtensa_M3,      35,  Xtensa_WINDOWBASE,   72,
438
  Xtensa_WINDOWSTART, 73,  Xtensa_IBREAKENABLE, 96,
439
  Xtensa_MEMCTL,      97,  Xtensa_ATOMCTL,      99,
440
  Xtensa_DDR,     104, Xtensa_IBREAKA0,     128,
441
  Xtensa_IBREAKA1,    129, Xtensa_DBREAKA0,     144,
442
  Xtensa_DBREAKA1,    145, Xtensa_DBREAKC0,     160,
443
  Xtensa_DBREAKC1,    161, Xtensa_CONFIGID0,    176,
444
  Xtensa_EPC1,      177, Xtensa_EPC2,       178,
445
  Xtensa_EPC3,      179, Xtensa_EPC4,       180,
446
  Xtensa_EPC5,      181, Xtensa_EPC6,       182,
447
  Xtensa_EPC7,      183, Xtensa_DEPC,       192,
448
  Xtensa_EPS2,      194, Xtensa_EPS3,       195,
449
  Xtensa_EPS4,      196, Xtensa_EPS5,       197,
450
  Xtensa_EPS6,      198, Xtensa_EPS7,       199,
451
  Xtensa_CONFIGID1,   208, Xtensa_EXCSAVE1,     209,
452
  Xtensa_EXCSAVE2,    210, Xtensa_EXCSAVE3,     211,
453
  Xtensa_EXCSAVE4,    212, Xtensa_EXCSAVE5,     213,
454
  Xtensa_EXCSAVE6,    214, Xtensa_EXCSAVE7,     215,
455
  Xtensa_CPENABLE,    224, Xtensa_INTERRUPT,    226,
456
  Xtensa_INTCLEAR,    227, Xtensa_INTENABLE,    228,
457
  Xtensa_PS,      230, Xtensa_VECBASE,      231,
458
  Xtensa_EXCCAUSE,    232, Xtensa_DEBUGCAUSE,   233,
459
  Xtensa_CCOUNT,      234, Xtensa_PRID,       235,
460
  Xtensa_ICOUNT,      236, Xtensa_ICOUNTLEVEL,  237,
461
  Xtensa_EXCVADDR,    238, Xtensa_CCOMPARE0,    240,
462
  Xtensa_CCOMPARE1,   241, Xtensa_CCOMPARE2,    242,
463
  Xtensa_MISC0,     244, Xtensa_MISC1,        245,
464
  Xtensa_MISC2,     246, Xtensa_MISC3,        247
465
};
466
467
static DecodeStatus DecodeSRRegisterClass(MCInst *Inst, uint64_t RegNo,
468
            uint64_t Address, const void *Decoder)
469
792
{
470
  //  const llvm_MCSubtargetInfo STI =
471
  //    ((const MCDisassembler *)Decoder)->getSubtargetInfo();
472
473
792
  if (RegNo > 255)
474
0
    return MCDisassembler_Fail;
475
476
16.2k
  for (unsigned i = 0; i < ARR_SIZE(SRDecoderTable); i += 2) {
477
16.2k
    if (SRDecoderTable[i + 1] == RegNo) {
478
790
      unsigned Reg = SRDecoderTable[i];
479
480
790
      if (!CheckRegister(Inst, Reg))
481
1
        return MCDisassembler_Fail;
482
483
789
      MCOperand_CreateReg0(Inst, (Reg));
484
789
      return MCDisassembler_Success;
485
790
    }
486
16.2k
  }
487
488
2
  return MCDisassembler_Fail;
489
792
}
490
491
static const unsigned URDecoderTable[] = {
492
  Xtensa_GPIO_OUT, 0,   Xtensa_EXPSTATE, 230, Xtensa_THREADPTR, 231,
493
  Xtensa_FCR,  232, Xtensa_FSR,      233, Xtensa_F64R_LO,   234,
494
  Xtensa_F64R_HI,  235, Xtensa_F64S,     236
495
};
496
497
static DecodeStatus DecodeURRegisterClass(MCInst *Inst, uint64_t RegNo,
498
            uint64_t Address, const void *Decoder)
499
31
{
500
31
  if (RegNo > 255)
501
0
    return MCDisassembler_Fail;
502
503
176
  for (unsigned i = 0; i < ARR_SIZE(URDecoderTable); i += 2) {
504
160
    if (URDecoderTable[i + 1] == RegNo) {
505
15
      unsigned Reg = URDecoderTable[i];
506
507
15
      if (!CheckRegister(Inst, Reg))
508
1
        return MCDisassembler_Fail;
509
510
14
      MCOperand_CreateReg0(Inst, (Reg));
511
14
      return MCDisassembler_Success;
512
15
    }
513
160
  }
514
515
16
  return MCDisassembler_Fail;
516
31
}
517
518
static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
519
             uint64_t Address, uint64_t Offset,
520
             uint64_t InstSize, MCInst *MI,
521
             const void *Decoder)
522
4.54k
{
523
  //  return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
524
  //               Offset, /*OpSize=*/0, InstSize);
525
4.54k
  return false;
526
4.54k
}
527
528
static DecodeStatus decodeCallOperand(MCInst *Inst, uint64_t Imm,
529
              int64_t Address, const void *Decoder)
530
1.16k
{
531
1.16k
  CS_ASSERT_RET_VAL(isUIntN(18, Imm) && "Invalid immediate",
532
1.16k
        MCDisassembler_Fail);
533
1.16k
  MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 2), 20)));
534
1.16k
  return MCDisassembler_Success;
535
1.16k
}
536
537
static DecodeStatus decodeJumpOperand(MCInst *Inst, uint64_t Imm,
538
              int64_t Address, const void *Decoder)
539
438
{
540
438
  CS_ASSERT_RET_VAL(isUIntN(18, Imm) && "Invalid immediate",
541
438
        MCDisassembler_Fail);
542
438
  MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 18)));
543
438
  return MCDisassembler_Success;
544
438
}
545
546
static DecodeStatus decodeBranchOperand(MCInst *Inst, uint64_t Imm,
547
          int64_t Address, const void *Decoder)
548
4.53k
{
549
4.53k
  switch (MCInst_getOpcode(Inst)) {
550
55
  case Xtensa_BEQZ:
551
164
  case Xtensa_BGEZ:
552
243
  case Xtensa_BLTZ:
553
345
  case Xtensa_BNEZ:
554
345
    CS_ASSERT_RET_VAL(isUIntN(12, Imm) && "Invalid immediate",
555
345
          MCDisassembler_Fail);
556
345
    if (!tryAddingSymbolicOperand(
557
345
          SignExtend64((Imm), 12) + 4 + Address, true,
558
345
          Address, 0, 3, Inst, Decoder))
559
345
      MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 12)));
560
345
    break;
561
4.18k
  default:
562
4.18k
    CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
563
4.18k
          MCDisassembler_Fail);
564
4.18k
    if (!tryAddingSymbolicOperand(
565
4.18k
          SignExtend64((Imm), 8) + 4 + Address, true, Address,
566
4.18k
          0, 3, Inst, Decoder))
567
4.18k
      MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 8)));
568
4.53k
  }
569
4.53k
  return MCDisassembler_Success;
570
4.53k
}
571
572
static DecodeStatus decodeLoopOperand(MCInst *Inst, uint64_t Imm,
573
              int64_t Address, const void *Decoder)
574
11
{
575
11
  CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
576
11
        MCDisassembler_Fail);
577
11
  if (!tryAddingSymbolicOperand(Imm + 4 + Address, true, Address, 0, 3,
578
11
              Inst, Decoder))
579
11
    MCOperand_CreateImm0(Inst, (Imm));
580
11
  return MCDisassembler_Success;
581
11
}
582
583
static DecodeStatus decodeL32ROperand(MCInst *Inst, uint64_t Imm,
584
              int64_t Address, const void *Decoder)
585
2.37k
{
586
2.37k
  CS_ASSERT_RET_VAL(isUIntN(16, Imm) && "Invalid immediate",
587
2.37k
        MCDisassembler_Fail);
588
2.37k
  MCOperand_CreateImm0(Inst, OneExtend64(Imm << 2, 18));
589
2.37k
  return MCDisassembler_Success;
590
2.37k
}
591
592
static DecodeStatus decodeImm8Operand(MCInst *Inst, uint64_t Imm,
593
              int64_t Address, const void *Decoder)
594
130
{
595
130
  CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
596
130
        MCDisassembler_Fail);
597
130
  MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 8)));
598
130
  return MCDisassembler_Success;
599
130
}
600
601
static DecodeStatus decodeImm8_sh8Operand(MCInst *Inst, uint64_t Imm,
602
            int64_t Address, const void *Decoder)
603
69
{
604
69
  CS_ASSERT_RET_VAL(isUIntN(16, Imm) && ((Imm & 0xff) == 0) &&
605
69
          "Invalid immediate",
606
69
        MCDisassembler_Fail);
607
69
  MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 16)));
608
69
  return MCDisassembler_Success;
609
69
}
610
611
static DecodeStatus decodeImm12Operand(MCInst *Inst, uint64_t Imm,
612
               int64_t Address, const void *Decoder)
613
100
{
614
100
  CS_ASSERT_RET_VAL(isUIntN(12, Imm) && "Invalid immediate",
615
100
        MCDisassembler_Fail);
616
100
  MCOperand_CreateImm0(Inst, (SignExtend64((Imm), 12)));
617
100
  return MCDisassembler_Success;
618
100
}
619
620
static DecodeStatus decodeUimm4Operand(MCInst *Inst, uint64_t Imm,
621
               int64_t Address, const void *Decoder)
622
306
{
623
306
  CS_ASSERT_RET_VAL(isUIntN(4, Imm) && "Invalid immediate",
624
306
        MCDisassembler_Fail);
625
306
  MCOperand_CreateImm0(Inst, (Imm));
626
306
  return MCDisassembler_Success;
627
306
}
628
629
static DecodeStatus decodeUimm5Operand(MCInst *Inst, uint64_t Imm,
630
               int64_t Address, const void *Decoder)
631
571
{
632
571
  CS_ASSERT_RET_VAL(isUIntN(5, Imm) && "Invalid immediate",
633
571
        MCDisassembler_Fail);
634
571
  MCOperand_CreateImm0(Inst, (Imm));
635
571
  return MCDisassembler_Success;
636
571
}
637
638
static DecodeStatus decodeImm1_16Operand(MCInst *Inst, uint64_t Imm,
639
           int64_t Address, const void *Decoder)
640
297
{
641
297
  CS_ASSERT_RET_VAL(isUIntN(4, Imm) && "Invalid immediate",
642
297
        MCDisassembler_Fail);
643
297
  MCOperand_CreateImm0(Inst, (Imm + 1));
644
297
  return MCDisassembler_Success;
645
297
}
646
647
static DecodeStatus decodeImm1n_15Operand(MCInst *Inst, uint64_t Imm,
648
            int64_t Address, const void *Decoder)
649
1.37k
{
650
1.37k
  CS_ASSERT_RET_VAL(isUIntN(4, Imm) && "Invalid immediate",
651
1.37k
        MCDisassembler_Fail);
652
1.37k
  if (!Imm)
653
44
    MCOperand_CreateImm0(Inst, (-1));
654
1.33k
  else
655
1.33k
    MCOperand_CreateImm0(Inst, (Imm));
656
1.37k
  return MCDisassembler_Success;
657
1.37k
}
658
659
static DecodeStatus decodeImm32n_95Operand(MCInst *Inst, uint64_t Imm,
660
             int64_t Address, const void *Decoder)
661
343
{
662
343
  CS_ASSERT_RET_VAL(isUIntN(7, Imm) && "Invalid immediate",
663
343
        MCDisassembler_Fail);
664
343
  if ((Imm & 0x60) == 0x60)
665
223
    MCOperand_CreateImm0(Inst, ((~0x1f) | Imm));
666
120
  else
667
120
    MCOperand_CreateImm0(Inst, (Imm));
668
343
  return MCDisassembler_Success;
669
343
}
670
671
static DecodeStatus decodeImm8n_7Operand(MCInst *Inst, uint64_t Imm,
672
           int64_t Address, const void *Decoder)
673
240
{
674
240
  CS_ASSERT_RET_VAL(isUIntN(4, Imm) && "Invalid immediate",
675
240
        MCDisassembler_Fail);
676
240
  if (Imm > 7)
677
146
    MCOperand_CreateImm0(Inst, (Imm - 16));
678
94
  else
679
94
    MCOperand_CreateImm0(Inst, (Imm));
680
240
  return MCDisassembler_Success;
681
240
}
682
683
static DecodeStatus decodeImm64n_4nOperand(MCInst *Inst, uint64_t Imm,
684
             int64_t Address, const void *Decoder)
685
41
{
686
41
  CS_ASSERT_RET_VAL(isUIntN(6, Imm) && ((Imm & 0x3) == 0) &&
687
41
          "Invalid immediate",
688
41
        MCDisassembler_Fail);
689
41
  MCOperand_CreateImm0(Inst, ((~0x3f) | (Imm)));
690
41
  return MCDisassembler_Success;
691
41
}
692
693
static DecodeStatus decodeOffset8m32Operand(MCInst *Inst, uint64_t Imm,
694
              int64_t Address,
695
              const void *Decoder)
696
165
{
697
165
  CS_ASSERT_RET_VAL(isUIntN(10, Imm) && ((Imm & 0x3) == 0) &&
698
165
          "Invalid immediate",
699
165
        MCDisassembler_Fail);
700
165
  MCOperand_CreateImm0(Inst, (Imm));
701
165
  return MCDisassembler_Success;
702
165
}
703
704
static DecodeStatus decodeEntry_Imm12OpValue(MCInst *Inst, uint64_t Imm,
705
               int64_t Address,
706
               const void *Decoder)
707
443
{
708
443
  CS_ASSERT_RET_VAL(isUIntN(15, Imm) && ((Imm & 0x7) == 0) &&
709
443
          "Invalid immediate",
710
443
        MCDisassembler_Fail);
711
443
  MCOperand_CreateImm0(Inst, (Imm));
712
443
  return MCDisassembler_Success;
713
443
}
714
715
static DecodeStatus decodeShimm1_31Operand(MCInst *Inst, uint64_t Imm,
716
             int64_t Address, const void *Decoder)
717
276
{
718
276
  CS_ASSERT_RET_VAL(isUIntN(5, Imm) && "Invalid immediate",
719
276
        MCDisassembler_Fail);
720
276
  MCOperand_CreateImm0(Inst, (32 - Imm));
721
276
  return MCDisassembler_Success;
722
276
}
723
724
//static DecodeStatus decodeShimm0_31Operand(MCInst *Inst, uint64_t Imm,
725
//             int64_t Address, const void *Decoder)
726
//{
727
//  CS_ASSERT_RET_VAL(isUIntN(5, Imm) && "Invalid immediate", MCDisassembler_Fail);
728
//  MCOperand_CreateImm0(Inst, (32 - Imm));
729
//  return MCDisassembler_Success;
730
//}
731
732
static DecodeStatus decodeImm7_22Operand(MCInst *Inst, uint64_t Imm,
733
           int64_t Address, const void *Decoder)
734
7
{
735
7
  CS_ASSERT_RET_VAL(isUIntN(4, Imm) && "Invalid immediate",
736
7
        MCDisassembler_Fail);
737
7
  MCOperand_CreateImm0(Inst, (Imm + 7));
738
7
  return MCDisassembler_Success;
739
7
}
740
741
static DecodeStatus decodeSelect_2Operand(MCInst *Inst, uint64_t Imm,
742
            int64_t Address, const void *Decoder)
743
182
{
744
182
  CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
745
182
        MCDisassembler_Fail);
746
182
  MCOperand_CreateImm0(Inst, (Imm));
747
182
  return MCDisassembler_Success;
748
182
}
749
750
static DecodeStatus decodeSelect_4Operand(MCInst *Inst, uint64_t Imm,
751
            int64_t Address, const void *Decoder)
752
806
{
753
806
  CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
754
806
        MCDisassembler_Fail);
755
806
  MCOperand_CreateImm0(Inst, (Imm));
756
806
  return MCDisassembler_Success;
757
806
}
758
759
static DecodeStatus decodeSelect_8Operand(MCInst *Inst, uint64_t Imm,
760
            int64_t Address, const void *Decoder)
761
436
{
762
436
  CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
763
436
        MCDisassembler_Fail);
764
436
  MCOperand_CreateImm0(Inst, (Imm));
765
436
  return MCDisassembler_Success;
766
436
}
767
768
static DecodeStatus decodeSelect_16Operand(MCInst *Inst, uint64_t Imm,
769
             int64_t Address, const void *Decoder)
770
66
{
771
66
  CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
772
66
        MCDisassembler_Fail);
773
66
  MCOperand_CreateImm0(Inst, (Imm));
774
66
  return MCDisassembler_Success;
775
66
}
776
777
static DecodeStatus decodeSelect_256Operand(MCInst *Inst, uint64_t Imm,
778
              int64_t Address,
779
              const void *Decoder)
780
1
{
781
1
  CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
782
1
        MCDisassembler_Fail);
783
1
  MCOperand_CreateImm0(Inst, (Imm));
784
1
  return MCDisassembler_Success;
785
1
}
786
787
static DecodeStatus decodeOffset_16_16Operand(MCInst *Inst, uint64_t Imm,
788
                int64_t Address,
789
                const void *Decoder)
790
148
{
791
148
  CS_ASSERT_RET_VAL(isIntN(Imm, 8) && "Invalid immediate",
792
148
        MCDisassembler_Fail);
793
145
  if ((Imm & 0xf) != 0)
794
145
    MCOperand_CreateImm0(Inst, (Imm << 4));
795
0
  else
796
0
    MCOperand_CreateImm0(Inst, (Imm));
797
145
  return MCDisassembler_Success;
798
148
}
799
800
static DecodeStatus decodeOffset_256_8Operand(MCInst *Inst, uint64_t Imm,
801
                int64_t Address,
802
                const void *Decoder)
803
300
{
804
300
  CS_ASSERT_RET_VAL(isIntN(16, Imm) && "Invalid immediate",
805
300
        MCDisassembler_Fail);
806
300
  if ((Imm & 0x7) != 0)
807
291
    MCOperand_CreateImm0(Inst, (Imm << 3));
808
9
  else
809
9
    MCOperand_CreateImm0(Inst, (Imm));
810
300
  return MCDisassembler_Success;
811
300
}
812
813
static DecodeStatus decodeOffset_256_16Operand(MCInst *Inst, uint64_t Imm,
814
                 int64_t Address,
815
                 const void *Decoder)
816
432
{
817
432
  CS_ASSERT_RET_VAL(isIntN(16, Imm) && "Invalid immediate",
818
432
        MCDisassembler_Fail);
819
432
  if ((Imm & 0xf) != 0)
820
375
    MCOperand_CreateImm0(Inst, (Imm << 4));
821
57
  else
822
57
    MCOperand_CreateImm0(Inst, (Imm));
823
432
  return MCDisassembler_Success;
824
432
}
825
826
static DecodeStatus decodeOffset_256_4Operand(MCInst *Inst, uint64_t Imm,
827
                int64_t Address,
828
                const void *Decoder)
829
246
{
830
246
  CS_ASSERT_RET_VAL(isIntN(16, Imm) && "Invalid immediate",
831
246
        MCDisassembler_Fail);
832
246
  if ((Imm & 0x2) != 0)
833
186
    MCOperand_CreateImm0(Inst, (Imm << 2));
834
60
  else
835
60
    MCOperand_CreateImm0(Inst, (Imm));
836
246
  return MCDisassembler_Success;
837
246
}
838
839
static DecodeStatus decodeOffset_128_2Operand(MCInst *Inst, uint64_t Imm,
840
                int64_t Address,
841
                const void *Decoder)
842
602
{
843
602
  CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
844
602
        MCDisassembler_Fail);
845
602
  if ((Imm & 0x1) != 0)
846
353
    MCOperand_CreateImm0(Inst, (Imm << 1));
847
249
  else
848
249
    MCOperand_CreateImm0(Inst, (Imm));
849
602
  return MCDisassembler_Success;
850
602
}
851
852
static DecodeStatus decodeOffset_128_1Operand(MCInst *Inst, uint64_t Imm,
853
                int64_t Address,
854
                const void *Decoder)
855
394
{
856
394
  CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
857
394
        MCDisassembler_Fail);
858
394
  MCOperand_CreateImm0(Inst, (Imm));
859
394
  return MCDisassembler_Success;
860
394
}
861
862
static DecodeStatus decodeOffset_64_16Operand(MCInst *Inst, uint64_t Imm,
863
                int64_t Address,
864
                const void *Decoder)
865
1.02k
{
866
1.02k
  CS_ASSERT_RET_VAL(isIntN(16, Imm) && "Invalid immediate",
867
1.02k
        MCDisassembler_Fail);
868
1.02k
  if ((Imm & 0xf) != 0)
869
941
    MCOperand_CreateImm0(Inst, (Imm << 4));
870
80
  else
871
80
    MCOperand_CreateImm0(Inst, (Imm));
872
1.02k
  return MCDisassembler_Success;
873
1.02k
}
874
875
static int64_t TableB4const[16] = { -1, 1,  2,  3,  4,  5,  6,   7,
876
            8,  10, 12, 16, 32, 64, 128, 256 };
877
static DecodeStatus decodeB4constOperand(MCInst *Inst, uint64_t Imm,
878
           int64_t Address, const void *Decoder)
879
1.49k
{
880
1.49k
  CS_ASSERT_RET_VAL(isUIntN(4, Imm) && "Invalid immediate",
881
1.49k
        MCDisassembler_Fail);
882
883
1.49k
  MCOperand_CreateImm0(Inst, (TableB4const[Imm]));
884
1.49k
  return MCDisassembler_Success;
885
1.49k
}
886
887
static int64_t TableB4constu[16] = { 32768, 65536, 2,  3,  4,  5,  6, 7,
888
             8,     10,    12, 16, 32, 64, 128, 256 };
889
static DecodeStatus decodeB4constuOperand(MCInst *Inst, uint64_t Imm,
890
            int64_t Address, const void *Decoder)
891
2.04k
{
892
2.04k
  CS_ASSERT_RET_VAL(isUIntN(4, Imm) && "Invalid immediate",
893
2.04k
        MCDisassembler_Fail);
894
895
2.04k
  MCOperand_CreateImm0(Inst, (TableB4constu[Imm]));
896
2.04k
  return MCDisassembler_Success;
897
2.04k
}
898
899
static DecodeStatus decodeMem8Operand(MCInst *Inst, uint64_t Imm,
900
              int64_t Address, const void *Decoder)
901
499
{
902
499
  CS_ASSERT_RET_VAL(isUIntN(12, Imm) && "Invalid immediate",
903
499
        MCDisassembler_Fail);
904
499
  DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
905
499
  MCOperand_CreateImm0(Inst, ((Imm >> 4) & 0xff));
906
499
  return MCDisassembler_Success;
907
499
}
908
909
static DecodeStatus decodeMem16Operand(MCInst *Inst, uint64_t Imm,
910
               int64_t Address, const void *Decoder)
911
117
{
912
117
  CS_ASSERT_RET_VAL(isUIntN(12, Imm) && "Invalid immediate",
913
117
        MCDisassembler_Fail);
914
117
  DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
915
117
  MCOperand_CreateImm0(Inst, ((Imm >> 3) & 0x1fe));
916
117
  return MCDisassembler_Success;
917
117
}
918
919
static DecodeStatus decodeMem32Operand(MCInst *Inst, uint64_t Imm,
920
               int64_t Address, const void *Decoder)
921
294
{
922
294
  CS_ASSERT_RET_VAL(isUIntN(12, Imm) && "Invalid immediate",
923
294
        MCDisassembler_Fail);
924
294
  DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
925
294
  MCOperand_CreateImm0(Inst, ((Imm >> 2) & 0x3fc));
926
294
  return MCDisassembler_Success;
927
294
}
928
929
static DecodeStatus decodeMem32nOperand(MCInst *Inst, uint64_t Imm,
930
          int64_t Address, const void *Decoder)
931
1.47k
{
932
1.47k
  CS_ASSERT_RET_VAL(isUIntN(8, Imm) && "Invalid immediate",
933
1.47k
        MCDisassembler_Fail);
934
1.47k
  DecodeARRegisterClass(Inst, Imm & 0xf, Address, Decoder);
935
1.47k
  MCOperand_CreateImm0(Inst, ((Imm >> 2) & 0x3c));
936
1.47k
  return MCDisassembler_Success;
937
1.47k
}
938
939
/// Read two bytes from the ArrayRef and return 16 bit data sorted
940
/// according to the given endianness.
941
static DecodeStatus readInstruction16(MCInst *MI, const uint8_t *Bytes,
942
              size_t BytesLen, uint64_t Address,
943
              uint64_t *Size, uint64_t *Insn,
944
              bool IsLittleEndian)
945
26.9k
{
946
  // We want to read exactly 2 Bytes of data.
947
26.9k
  if (BytesLen < 2) {
948
177
    *Size = 0;
949
177
    return MCDisassembler_Fail;
950
177
  }
951
952
26.7k
  *Insn = readBytes16(MI, Bytes);
953
26.7k
  *Size = 2;
954
955
26.7k
  return MCDisassembler_Success;
956
26.9k
}
957
958
/// Read three bytes from the ArrayRef and return 24 bit data
959
static DecodeStatus readInstruction24(MCInst *MI, const uint8_t *Bytes,
960
              size_t BytesLen, uint64_t Address,
961
              uint64_t *Size, uint64_t *Insn,
962
              bool IsLittleEndian, bool CheckTIE)
963
27.6k
{
964
  // We want to read exactly 3 Bytes of data.
965
27.6k
  if (BytesLen < 3) {
966
98
    *Size = 0;
967
98
    return MCDisassembler_Fail;
968
98
  }
969
970
27.5k
  if (CheckTIE && (Bytes[0] & 0x8) != 0)
971
2.61k
    return MCDisassembler_Fail;
972
24.9k
  *Insn = readBytes24(MI, Bytes);
973
24.9k
  *Size = 3;
974
975
24.9k
  return MCDisassembler_Success;
976
27.5k
}
977
978
/// Read three bytes from the ArrayRef and return 32 bit data
979
static DecodeStatus readInstruction32(MCInst *MI, const uint8_t *Bytes,
980
              size_t BytesLen, uint64_t Address,
981
              uint64_t *Size, uint64_t *Insn,
982
              bool IsLittleEndian)
983
2.76k
{
984
  // We want to read exactly 4 Bytes of data.
985
2.76k
  if (BytesLen < 4) {
986
32
    *Size = 0;
987
32
    return MCDisassembler_Fail;
988
32
  }
989
990
2.73k
  if ((Bytes[0] & 0x8) == 0)
991
136
    return MCDisassembler_Fail;
992
2.59k
  *Insn = readBytes32(MI, Bytes);
993
2.59k
  *Size = 4;
994
995
2.59k
  return MCDisassembler_Success;
996
2.73k
}
997
998
/// Read InstSize bytes from the ArrayRef and return 24 bit data
999
static DecodeStatus readInstructionN(const uint8_t *Bytes, size_t BytesLen,
1000
             uint64_t Address, unsigned InstSize,
1001
             uint64_t *Size, uint64_t *Insn,
1002
             bool IsLittleEndian)
1003
165
{
1004
  // We want to read exactly 3 Bytes of data.
1005
165
  if (BytesLen < InstSize) {
1006
52
    *Size = 0;
1007
52
    return MCDisassembler_Fail;
1008
52
  }
1009
1010
113
  *Insn = 0;
1011
5.53k
  for (unsigned i = 0; i < InstSize; i++)
1012
5.42k
    *Insn |= (uint64_t)(Bytes[i]) << (8 * i);
1013
1014
113
  *Size = InstSize;
1015
113
  return MCDisassembler_Success;
1016
165
}
1017
1018
#include "XtensaGenDisassemblerTables.inc"
1019
1020
FieldFromInstruction(fieldFromInstruction_2, uint64_t);
1021
5.20k
DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2, uint64_t);
1022
26.7k
DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2,
1023
      uint64_t);
1024
1025
FieldFromInstruction(fieldFromInstruction_4, uint64_t);
1026
2.43k
DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint64_t);
1027
2.59k
DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4,
1028
      uint64_t);
1029
1030
FieldFromInstruction(fieldFromInstruction_6, uint64_t);
1031
73
DecodeToMCInst(decodeToMCInst_6, fieldFromInstruction_6, uint64_t);
1032
113
DecodeInstruction(decodeInstruction_6, fieldFromInstruction_6, decodeToMCInst_6,
1033
      uint64_t);
1034
1035
static bool hasDensity()
1036
26.9k
{
1037
26.9k
  return true;
1038
26.9k
}
1039
static bool hasESP32S3Ops()
1040
6.10k
{
1041
6.10k
  return true;
1042
6.10k
}
1043
static bool hasHIFI3()
1044
165
{
1045
165
  return true;
1046
165
}
1047
1048
static DecodeStatus getInstruction(MCInst *MI, uint64_t *Size,
1049
           const uint8_t *Bytes, size_t BytesLen,
1050
           uint64_t Address)
1051
26.9k
{
1052
26.9k
  uint64_t Insn;
1053
26.9k
  DecodeStatus Result;
1054
26.9k
  bool IsLittleEndian = MI->csh->mode & CS_MODE_LITTLE_ENDIAN;
1055
1056
  // Parse 16-bit instructions
1057
26.9k
  if (hasDensity()) {
1058
26.9k
    Result = readInstruction16(MI, Bytes, BytesLen, Address, Size,
1059
26.9k
             &Insn, IsLittleEndian);
1060
26.9k
    if (Result == MCDisassembler_Fail)
1061
177
      return MCDisassembler_Fail;
1062
1063
26.7k
    Result = decodeInstruction_2(DecoderTable16, MI, Insn, Address,
1064
26.7k
               NULL);
1065
26.7k
    if (Result != MCDisassembler_Fail) {
1066
5.20k
      *Size = 2;
1067
5.20k
      return Result;
1068
5.20k
    }
1069
26.7k
  }
1070
1071
  // Parse Core 24-bit instructions
1072
21.5k
  Result = readInstruction24(MI, Bytes, BytesLen, Address, Size, &Insn,
1073
21.5k
           IsLittleEndian, false);
1074
21.5k
  if (Result == MCDisassembler_Fail)
1075
98
    return MCDisassembler_Fail;
1076
1077
21.4k
  Result = decodeInstruction_3(DecoderTable24, MI, Insn, Address, NULL);
1078
21.4k
  if (Result != MCDisassembler_Fail) {
1079
15.3k
    *Size = 3;
1080
15.3k
    return Result;
1081
15.3k
  }
1082
1083
6.10k
  if (hasESP32S3Ops()) {
1084
    // Parse ESP32S3 24-bit instructions
1085
6.10k
    Result = readInstruction24(MI, Bytes, BytesLen, Address, Size,
1086
6.10k
             &Insn, IsLittleEndian, true);
1087
6.10k
    if (Result != MCDisassembler_Fail) {
1088
3.49k
      Result = decodeInstruction_3(DecoderTableESP32S324, MI,
1089
3.49k
                 Insn, Address, NULL);
1090
3.49k
      if (Result != MCDisassembler_Fail) {
1091
3.34k
        *Size = 3;
1092
3.34k
        return Result;
1093
3.34k
      }
1094
3.49k
    }
1095
1096
    // Parse ESP32S3 32-bit instructions
1097
2.76k
    Result = readInstruction32(MI, Bytes, BytesLen, Address, Size,
1098
2.76k
             &Insn, IsLittleEndian);
1099
2.76k
    if (Result == MCDisassembler_Fail)
1100
168
      return MCDisassembler_Fail;
1101
1102
2.59k
    Result = decodeInstruction_4(DecoderTableESP32S332, MI, Insn,
1103
2.59k
               Address, NULL);
1104
2.59k
    if (Result != MCDisassembler_Fail) {
1105
2.42k
      *Size = 4;
1106
2.42k
      return Result;
1107
2.42k
    }
1108
2.59k
  }
1109
1110
165
  if (hasHIFI3()) {
1111
165
    Result = decodeInstruction_3(DecoderTableHIFI324, MI, Insn,
1112
165
               Address, NULL);
1113
165
    if (Result != MCDisassembler_Fail)
1114
0
      return Result;
1115
1116
165
    Result = readInstructionN(Bytes, BytesLen, Address, 48, Size,
1117
165
            &Insn, IsLittleEndian);
1118
165
    if (Result == MCDisassembler_Fail)
1119
52
      return MCDisassembler_Fail;
1120
1121
113
    Result = decodeInstruction_6(DecoderTableHIFI348, MI, Insn,
1122
113
               Address, NULL);
1123
113
    if (Result != MCDisassembler_Fail)
1124
73
      return Result;
1125
113
  }
1126
40
  return Result;
1127
165
}
1128
1129
DecodeStatus Xtensa_LLVM_getInstruction(MCInst *MI, uint16_t *size16,
1130
          const uint8_t *Bytes,
1131
          unsigned BytesSize, uint64_t Address)
1132
26.9k
{
1133
26.9k
  uint64_t size64;
1134
26.9k
  DecodeStatus status =
1135
26.9k
    getInstruction(MI, &size64, Bytes, BytesSize, Address);
1136
26.9k
  CS_ASSERT_RET_VAL(size64 < 0xffff, MCDisassembler_Fail);
1137
26.9k
  *size16 = size64;
1138
26.9k
  return status;
1139
26.9k
}