Coverage Report

Created: 2026-04-29 06:06

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonev5/arch/PowerPC/PPCInstPrinter.c
Line
Count
Source
1
//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This class prints an PPC MCInst to a .s file.
11
//
12
//===----------------------------------------------------------------------===//
13
14
/* Capstone Disassembly Engine */
15
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
16
17
#ifdef CAPSTONE_HAS_POWERPC
18
19
#include <stdio.h>
20
#include <stdlib.h>
21
#include <string.h>
22
23
#include "PPCInstPrinter.h"
24
#include "PPCPredicates.h"
25
#include "../../MCInst.h"
26
#include "../../utils.h"
27
#include "../../SStream.h"
28
#include "../../MCRegisterInfo.h"
29
#include "../../MathExtras.h"
30
#include "PPCMapping.h"
31
32
#ifndef CAPSTONE_DIET
33
static const char *getRegisterName(unsigned RegNo);
34
#endif
35
36
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
37
static void printInstruction(MCInst *MI, SStream *O);
38
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
39
static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI);
40
static char *printAliasBcc(MCInst *MI, SStream *OS, void *info);
41
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
42
    unsigned PrintMethodIdx, SStream *OS);
43
44
#if 0
45
static void printRegName(SStream *OS, unsigned RegNo)
46
{
47
  char *RegName = getRegisterName(RegNo);
48
49
  if (RegName[0] == 'q' /* QPX */) {
50
    // The system toolchain on the BG/Q does not understand QPX register names
51
    // in .cfi_* directives, so print the name of the floating-point
52
    // subregister instead.
53
    RegName[0] = 'f';
54
  }
55
56
  SStream_concat0(OS, RegName);
57
}
58
#endif
59
60
static void set_mem_access(MCInst *MI, bool status)
61
28.3k
{
62
28.3k
  if (MI->csh->detail != CS_OPT_ON)
63
0
    return;
64
65
28.3k
  MI->csh->doing_mem = status;
66
67
28.3k
  if (status) {
68
14.1k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM;
69
14.1k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = PPC_REG_INVALID;
70
14.1k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = 0;
71
14.1k
  } else {
72
    // done, create the next operand slot
73
14.1k
    MI->flat_insn->detail->ppc.op_count++;
74
14.1k
  }
75
28.3k
}
76
77
void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
78
91.9k
{
79
91.9k
  if (((cs_struct *)ud)->detail != CS_OPT_ON)
80
0
    return;
81
82
  // check if this insn has branch hint
83
91.9k
  if (strrchr(insn->mnemonic, '+') != NULL && !strstr(insn_asm, ".+")) {
84
2.48k
    insn->detail->ppc.bh = PPC_BH_PLUS;
85
89.4k
  } else if (strrchr(insn->mnemonic, '-') != NULL) {
86
1.45k
    insn->detail->ppc.bh = PPC_BH_MINUS;
87
1.45k
  }
88
89
91.9k
  if (strrchr(insn->mnemonic, '.') != NULL) {
90
6.27k
    insn->detail->ppc.update_cr0 = true;
91
6.27k
  }
92
91.9k
}
93
94
#define GET_INSTRINFO_ENUM
95
#include "PPCGenInstrInfo.inc"
96
97
#define GET_REGINFO_ENUM
98
#include "PPCGenRegisterInfo.inc"
99
100
static void op_addBC(MCInst *MI, unsigned int bc)
101
3.10k
{
102
3.10k
  if (MI->csh->detail) {
103
3.10k
    MI->flat_insn->detail->ppc.bc = (ppc_bc)bc;
104
3.10k
  }
105
3.10k
}
106
107
954
#define CREQ (0)
108
533
#define CRGT (1)
109
1.88k
#define CRLT (2)
110
1.33k
#define CRUN (3)
111
112
static int getBICRCond(int bi)
113
4.70k
{
114
4.70k
  return (bi - PPC_CR0EQ) >> 3;
115
4.70k
}
116
117
static int getBICR(int bi)
118
4.70k
{
119
4.70k
  return ((bi - PPC_CR0EQ) & 7) + PPC_CR0;
120
4.70k
}
121
122
static void op_addReg(MCInst *MI, unsigned int reg)
123
1.19k
{
124
1.19k
  if (MI->csh->detail) {
125
1.19k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
126
1.19k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
127
1.19k
    MI->flat_insn->detail->ppc.op_count++;
128
1.19k
  }
129
1.19k
}
130
131
static void add_CRxx(MCInst *MI, ppc_reg reg)
132
1.49k
{
133
1.49k
  if (MI->csh->detail) {
134
1.49k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
135
1.49k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
136
1.49k
    MI->flat_insn->detail->ppc.op_count++;
137
1.49k
  }
138
1.49k
}
139
140
static char *printAliasBcc(MCInst *MI, SStream *OS, void *info)
141
91.2k
{
142
91.2k
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
143
91.2k
  SStream ss;
144
91.2k
  const char *opCode;
145
91.2k
  char *tmp, *AsmMnem, *AsmOps, *c;
146
91.2k
  int OpIdx, PrintMethodIdx;
147
91.2k
  int decCtr = false, needComma = false;
148
91.2k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
149
150
91.2k
  SStream_Init(&ss);
151
152
91.2k
  switch (MCInst_getOpcode(MI)) {
153
84.5k
    default: return NULL;
154
2.60k
    case PPC_gBC:
155
2.60k
         opCode = "b%s";
156
2.60k
         break;
157
1.98k
    case PPC_gBCA:
158
1.98k
         opCode = "b%sa";
159
1.98k
         break;
160
44
    case PPC_gBCCTR:
161
44
         opCode = "b%sctr";
162
44
         break;
163
86
    case PPC_gBCCTRL:
164
86
         opCode = "b%sctrl";
165
86
         break;
166
944
    case PPC_gBCL:
167
944
         opCode = "b%sl";
168
944
         break;
169
983
    case PPC_gBCLA:
170
983
         opCode = "b%sla";
171
983
         break;
172
65
    case PPC_gBCLR:
173
65
         opCode = "b%slr";
174
65
         break;
175
38
    case PPC_gBCLRL:
176
38
         opCode = "b%slrl";
177
38
         break;
178
91.2k
  }
179
180
6.74k
  if (MCInst_getNumOperands(MI) == 3 &&
181
6.74k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
182
6.74k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 0) &&
183
6.74k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 1)) {
184
1.16k
    SStream_concat(&ss, opCode, "dnzf");
185
1.16k
    decCtr = true;
186
1.16k
  }
187
188
6.74k
  if (MCInst_getNumOperands(MI) == 3 &&
189
6.74k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
190
6.74k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 2) &&
191
5.58k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 3)) {
192
1.18k
    SStream_concat(&ss, opCode, "dzf");
193
1.18k
    decCtr = true;
194
1.18k
  }
195
196
6.74k
  if (MCInst_getNumOperands(MI) == 3 &&
197
6.74k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
198
6.74k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 4) &&
199
4.40k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 7) &&
200
823
      MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
201
823
      GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
202
823
    int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
203
204
823
    switch(cr) {
205
89
      case CREQ:
206
89
        SStream_concat(&ss, opCode, "ne");
207
89
        break;
208
34
      case CRGT:
209
34
        SStream_concat(&ss, opCode, "le");
210
34
        break;
211
373
      case CRLT:
212
373
        SStream_concat(&ss, opCode, "ge");
213
373
        break;
214
327
      case CRUN:
215
327
        SStream_concat(&ss, opCode, "ns");
216
327
        break;
217
823
    }
218
219
823
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6)
220
327
      SStream_concat0(&ss, "-");
221
222
823
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7)
223
98
      SStream_concat0(&ss, "+");
224
225
823
    decCtr = false;
226
823
  }
227
228
6.74k
  if (MCInst_getNumOperands(MI) == 3 &&
229
6.74k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
230
6.74k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 8) &&
231
3.57k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 9)) {
232
350
    SStream_concat(&ss, opCode, "dnzt");
233
350
    decCtr = true;
234
350
  }
235
236
6.74k
  if (MCInst_getNumOperands(MI) == 3 &&
237
6.74k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
238
6.74k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 10) &&
239
3.22k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 11)) {
240
407
    SStream_concat(&ss, opCode, "dzt");
241
407
    decCtr = true;
242
407
  }
243
244
6.74k
  if (MCInst_getNumOperands(MI) == 3 &&
245
6.74k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
246
6.74k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 12) &&
247
2.82k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 15) &&
248
778
      MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
249
778
      GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
250
778
    int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
251
252
778
    switch(cr) {
253
69
      case CREQ:
254
69
        SStream_concat(&ss, opCode, "eq");
255
69
        break;
256
67
      case CRGT:
257
67
        SStream_concat(&ss, opCode, "gt");
258
67
        break;
259
441
      case CRLT:
260
441
        SStream_concat(&ss, opCode, "lt");
261
441
        break;
262
201
      case CRUN:
263
201
        SStream_concat(&ss, opCode, "so");
264
201
        break;
265
778
    }
266
267
778
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14)
268
328
      SStream_concat0(&ss, "-");
269
270
778
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15)
271
233
      SStream_concat0(&ss, "+");
272
273
778
    decCtr = false;
274
778
  }
275
276
6.74k
  if (MCInst_getNumOperands(MI) == 3 &&
277
6.74k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
278
6.74k
      ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 16)) {
279
736
    SStream_concat(&ss, opCode, "dnz");
280
281
736
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24)
282
236
      SStream_concat0(&ss, "-");
283
284
736
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 25)
285
167
      SStream_concat0(&ss, "+");
286
287
736
    needComma = false;
288
736
  }
289
290
6.74k
  if (MCInst_getNumOperands(MI) == 3 &&
291
6.74k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
292
6.74k
      ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 18)) {
293
1.30k
    SStream_concat(&ss, opCode, "dz");
294
295
1.30k
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 26)
296
355
      SStream_concat0(&ss, "-");
297
298
1.30k
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 27)
299
88
      SStream_concat0(&ss, "+");
300
301
1.30k
    needComma = false;
302
1.30k
  }
303
304
6.74k
  if (MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
305
6.74k
      GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
306
6.74k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
307
6.74k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) < 16)) {
308
4.70k
    int cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1)));
309
310
4.70k
    if (decCtr) {
311
3.10k
      int cd;
312
3.10k
      needComma = true;
313
3.10k
      SStream_concat0(&ss, " ");
314
315
3.10k
      if (cr > PPC_CR0) {
316
1.61k
        SStream_concat(&ss, "4*cr%d+", cr - PPC_CR0);
317
1.61k
      }
318
319
3.10k
      cd = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
320
3.10k
      switch(cd) {
321
796
        case CREQ:
322
796
          SStream_concat0(&ss, "eq");
323
796
          if (cr <= PPC_CR0)
324
207
            add_CRxx(MI, PPC_REG_CR0EQ);
325
796
          op_addBC(MI, PPC_BC_EQ);
326
796
          break;
327
432
        case CRGT:
328
432
          SStream_concat0(&ss, "gt");
329
432
          if (cr <= PPC_CR0)
330
298
            add_CRxx(MI, PPC_REG_CR0GT);
331
432
          op_addBC(MI, PPC_BC_GT);
332
432
          break;
333
1.07k
        case CRLT:
334
1.07k
          SStream_concat0(&ss, "lt");
335
1.07k
          if (cr <= PPC_CR0)
336
730
            add_CRxx(MI, PPC_REG_CR0LT);
337
1.07k
          op_addBC(MI, PPC_BC_LT);
338
1.07k
          break;
339
804
        case CRUN:
340
804
          SStream_concat0(&ss, "so");
341
804
          if (cr <= PPC_CR0)
342
255
            add_CRxx(MI, PPC_REG_CR0UN);
343
804
          op_addBC(MI, PPC_BC_SO);
344
804
          break;
345
3.10k
      }
346
347
3.10k
      if (cr > PPC_CR0) {
348
1.61k
        if (MI->csh->detail) {
349
1.61k
          MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
350
1.61k
          MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
351
1.61k
          MI->flat_insn->detail->ppc.op_count++;
352
1.61k
        }
353
1.61k
      }
354
3.10k
    } else {
355
1.60k
      if (cr > PPC_CR0) {
356
1.19k
        needComma = true;
357
1.19k
        SStream_concat(&ss, " cr%d", cr - PPC_CR0);
358
1.19k
        op_addReg(MI, PPC_REG_CR0 + cr - PPC_CR0);
359
1.19k
      }
360
1.60k
    }
361
4.70k
  }
362
363
6.74k
  if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
364
6.74k
      MCOperand_getImm(MCInst_getOperand(MI, 2)) != 0) {
365
6.48k
    if (needComma)
366
4.18k
      SStream_concat0(&ss, ",");
367
368
6.48k
    SStream_concat0(&ss, " $\xFF\x03\x01");
369
6.48k
  }
370
371
6.74k
  tmp = cs_strdup(ss.buffer);
372
6.74k
  AsmMnem = tmp;
373
39.7k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
374
39.6k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
375
6.60k
      *AsmOps = '\0';
376
6.60k
      AsmOps++;
377
6.60k
      break;
378
6.60k
    }
379
39.6k
  }
380
381
6.74k
  SStream_concat0(OS, AsmMnem);
382
6.74k
  if (*AsmOps) {
383
6.60k
    SStream_concat0(OS, "\t");
384
40.9k
    for (c = AsmOps; *c; c++) {
385
34.3k
      if (*c == '$') {
386
6.48k
        c += 1;
387
6.48k
        if (*c == (char)0xff) {
388
6.48k
          c += 1;
389
6.48k
          OpIdx = *c - 1;
390
6.48k
          c += 1;
391
6.48k
          PrintMethodIdx = *c - 1;
392
6.48k
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
393
6.48k
        } else
394
0
          printOperand(MI, *c - 1, OS);
395
27.8k
      } else {
396
27.8k
        SStream_concat1(OS, *c);
397
27.8k
      }
398
34.3k
    }
399
6.60k
  }
400
401
6.74k
  return tmp;
402
6.74k
}
403
404
static bool isBOCTRBranch(unsigned int op)
405
91.2k
{
406
91.2k
  return ((op >= PPC_BDNZ) && (op <= PPC_BDZp));
407
91.2k
}
408
409
void PPC_printInst(MCInst *MI, SStream *O, void *Info)
410
91.9k
{
411
91.9k
  char *mnem;
412
91.9k
  unsigned int opcode = MCInst_getOpcode(MI);
413
91.9k
  memset(O->buffer, 0, sizeof(O->buffer));
414
415
  // printf("opcode = %u\n", opcode);
416
417
  // Check for slwi/srwi mnemonics.
418
91.9k
  if (opcode == PPC_RLWINM) {
419
1.41k
    unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
420
1.41k
    unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
421
1.41k
    unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4));
422
1.41k
    bool useSubstituteMnemonic = false;
423
424
1.41k
    if (SH <= 31 && MB == 0 && ME == (31 - SH)) {
425
121
      SStream_concat0(O, "slwi\t");
426
121
      MCInst_setOpcodePub(MI, PPC_INS_SLWI);
427
121
      useSubstituteMnemonic = true;
428
121
    }
429
430
1.41k
    if (SH <= 31 && MB == (32 - SH) && ME == 31) {
431
58
      SStream_concat0(O, "srwi\t");
432
58
      MCInst_setOpcodePub(MI, PPC_INS_SRWI);
433
58
      useSubstituteMnemonic = true;
434
58
      SH = 32 - SH;
435
58
    }
436
437
1.41k
    if (useSubstituteMnemonic) {
438
179
      printOperand(MI, 0, O);
439
179
      SStream_concat0(O, ", ");
440
179
      printOperand(MI, 1, O);
441
442
179
      if (SH > HEX_THRESHOLD)
443
59
        SStream_concat(O, ", 0x%x", (unsigned int)SH);
444
120
      else
445
120
        SStream_concat(O, ", %u", (unsigned int)SH);
446
447
179
      if (MI->csh->detail) {
448
179
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
449
450
179
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
451
179
        ppc->operands[ppc->op_count].imm = SH;
452
179
        ++ppc->op_count;
453
179
      }
454
455
179
      return;
456
179
    }
457
1.41k
  }
458
459
91.7k
  if ((opcode == PPC_OR || opcode == PPC_OR8) &&
460
39
      MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2))) {
461
10
    SStream_concat0(O, "mr\t");
462
10
    MCInst_setOpcodePub(MI, PPC_INS_MR);
463
464
10
    printOperand(MI, 0, O);
465
10
    SStream_concat0(O, ", ");
466
10
    printOperand(MI, 1, O);
467
468
10
    return;
469
10
  }
470
471
91.7k
  if (opcode == PPC_RLDICR ||
472
91.5k
      opcode == PPC_RLDICR_32) {
473
176
    unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
474
176
    unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
475
476
    // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
477
176
    if (63 - SH == ME) {
478
32
      SStream_concat0(O, "sldi\t");
479
32
      MCInst_setOpcodePub(MI, PPC_INS_SLDI);
480
481
32
      printOperand(MI, 0, O);
482
32
      SStream_concat0(O, ", ");
483
32
      printOperand(MI, 1, O);
484
485
32
      if (SH > HEX_THRESHOLD)
486
10
        SStream_concat(O, ", 0x%x", (unsigned int)SH);
487
22
      else
488
22
        SStream_concat(O, ", %u", (unsigned int)SH);
489
490
32
      if (MI->csh->detail) {
491
32
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
492
493
32
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
494
32
        ppc->operands[ppc->op_count].imm = SH;
495
32
        ++ppc->op_count;
496
32
      }
497
498
499
32
      return;
500
32
    }
501
176
  }
502
503
  // dcbt[st] is printed manually here because:
504
  //  1. The assembly syntax is different between embedded and server targets
505
  //  2. We must print the short mnemonics for TH == 0 because the
506
  //     embedded/server syntax default will not be stable across assemblers
507
  //  The syntax for dcbt is:
508
  //    dcbt ra, rb, th [server]
509
  //    dcbt th, ra, rb [embedded]
510
  //  where th can be omitted when it is 0. dcbtst is the same.
511
91.7k
  if (opcode == PPC_DCBT || opcode == PPC_DCBTST) {
512
192
    unsigned char TH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0));
513
514
192
    SStream_concat0(O, "dcbt");
515
192
    MCInst_setOpcodePub(MI, PPC_INS_DCBT);
516
517
192
    if (opcode == PPC_DCBTST) {
518
93
      SStream_concat0(O, "st");
519
93
      MCInst_setOpcodePub(MI, PPC_INS_DCBTST);
520
93
    }
521
522
192
    if (TH == 16) {
523
62
      SStream_concat0(O, "t");
524
62
      MCInst_setOpcodePub(MI, PPC_INS_DCBTSTT);
525
62
    }
526
527
192
    SStream_concat0(O, "\t");
528
529
192
    if (MI->csh->mode & CS_MODE_BOOKE && TH != 0 && TH != 16) {
530
0
      if (TH > HEX_THRESHOLD)
531
0
        SStream_concat(O, "0x%x, ", (unsigned int)TH);
532
0
      else
533
0
        SStream_concat(O, "%u, ", (unsigned int)TH);
534
535
0
      if (MI->csh->detail) {
536
0
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
537
538
0
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
539
0
        ppc->operands[ppc->op_count].imm = TH;
540
0
        ++ppc->op_count;
541
0
      }
542
0
    }
543
544
192
    printOperand(MI, 1, O);
545
192
    SStream_concat0(O, ", ");
546
192
    printOperand(MI, 2, O);
547
548
192
    if (!(MI->csh->mode & CS_MODE_BOOKE) && TH != 0 && TH != 16) {
549
102
      if (TH > HEX_THRESHOLD)
550
40
        SStream_concat(O, ", 0x%x", (unsigned int)TH);
551
62
      else
552
62
        SStream_concat(O, ", %u", (unsigned int)TH);
553
554
102
      if (MI->csh->detail) {
555
102
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
556
557
102
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
558
102
        ppc->operands[ppc->op_count].imm = TH;
559
102
        ++ppc->op_count;
560
102
      }
561
102
    }
562
563
192
    return;
564
192
  }
565
566
91.5k
  if (opcode == PPC_DCBF) {
567
316
    unsigned char L = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0));
568
569
316
    if (!L || L == 1 || L == 3) {
570
264
      SStream_concat0(O, "dcbf");
571
264
      MCInst_setOpcodePub(MI, PPC_INS_DCBF);
572
573
264
      if (L == 1 || L == 3) {
574
145
        SStream_concat0(O, "l");
575
145
        MCInst_setOpcodePub(MI, PPC_INS_DCBFL);
576
145
      }
577
578
264
      if (L == 3) {
579
77
        SStream_concat0(O, "p");
580
77
        MCInst_setOpcodePub(MI, PPC_INS_DCBFLP);
581
77
      }
582
583
264
      SStream_concat0(O, "\t");
584
585
264
      printOperand(MI, 1, O);
586
264
      SStream_concat0(O, ", ");
587
264
      printOperand(MI, 2, O);
588
589
264
      return;
590
264
    }
591
316
  }
592
593
91.2k
  if (opcode == PPC_B || opcode == PPC_BA || opcode == PPC_BL ||
594
90.1k
      opcode == PPC_BLA) {
595
1.61k
    int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0));
596
1.61k
    bd = SignExtend64(bd, 24);
597
1.61k
    MCOperand_setImm(MCInst_getOperand(MI, 0), bd);
598
1.61k
  }
599
600
91.2k
  if (opcode == PPC_gBC || opcode == PPC_gBCA || opcode == PPC_gBCL ||
601
85.7k
      opcode == PPC_gBCLA) {
602
6.51k
    int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 2));
603
6.51k
    bd = SignExtend64(bd, 14);
604
6.51k
    MCOperand_setImm(MCInst_getOperand(MI, 2), bd);
605
6.51k
  }
606
607
91.2k
  if (isBOCTRBranch(MCInst_getOpcode(MI))) {
608
1.64k
    if (MCOperand_isImm(MCInst_getOperand(MI,0))) {
609
1.58k
      int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0));
610
1.58k
      bd = SignExtend64(bd, 14);
611
1.58k
      MCOperand_setImm(MCInst_getOperand(MI, 0), bd);
612
1.58k
    }
613
1.64k
  }
614
615
91.2k
  mnem = printAliasBcc(MI, O, Info);
616
91.2k
  if (!mnem)
617
84.5k
    mnem = printAliasInstr(MI, O, Info);
618
619
91.2k
  if (mnem != NULL) {
620
30.2k
    if (strlen(mnem) > 0) {
621
      // check to remove the last letter of ('.', '-', '+')
622
30.2k
      if (mnem[strlen(mnem) - 1] == '-' || mnem[strlen(mnem) - 1] == '+' || mnem[strlen(mnem) - 1] == '.')
623
2.65k
        mnem[strlen(mnem) - 1] = '\0';
624
625
30.2k
            MCInst_setOpcodePub(MI, PPC_map_insn(mnem));
626
627
30.2k
            if (MI->csh->detail) {
628
30.2k
        struct ppc_alias alias;
629
630
30.2k
        if (PPC_alias_insn(mnem, &alias)) {
631
1.60k
          MI->flat_insn->detail->ppc.bc = (ppc_bc)alias.cc;
632
1.60k
        }
633
30.2k
            }
634
30.2k
    }
635
636
30.2k
    cs_mem_free(mnem);
637
30.2k
  } else
638
60.9k
    printInstruction(MI, O);
639
640
91.2k
  const char *mnem_end = strchr(O->buffer, ' ');
641
91.2k
  unsigned mnem_len = 0;
642
91.2k
  if (mnem_end)
643
87.9k
    mnem_len = mnem_end - O->buffer;
644
91.2k
  if (!mnem_end || mnem_len >= sizeof(MI->flat_insn->mnemonic))
645
3.30k
    mnem_len = sizeof(MI->flat_insn->mnemonic) - 1;
646
647
91.2k
  memset(MI->flat_insn->mnemonic, 0, sizeof(MI->flat_insn->mnemonic));
648
91.2k
  memcpy(MI->flat_insn->mnemonic, O->buffer, mnem_len);
649
91.2k
}
650
651
// FIXME
652
enum ppc_bc_hint {
653
  PPC_BC_LT_MINUS = (0 << 5) | 14,
654
  PPC_BC_LE_MINUS = (1 << 5) |  6,
655
  PPC_BC_EQ_MINUS = (2 << 5) | 14,
656
  PPC_BC_GE_MINUS = (0 << 5) |  6,
657
  PPC_BC_GT_MINUS = (1 << 5) | 14,
658
  PPC_BC_NE_MINUS = (2 << 5) |  6,
659
  PPC_BC_UN_MINUS = (3 << 5) | 14,
660
  PPC_BC_NU_MINUS = (3 << 5) |  6,
661
  PPC_BC_LT_PLUS  = (0 << 5) | 15,
662
  PPC_BC_LE_PLUS  = (1 << 5) |  7,
663
  PPC_BC_EQ_PLUS  = (2 << 5) | 15,
664
  PPC_BC_GE_PLUS  = (0 << 5) |  7,
665
  PPC_BC_GT_PLUS  = (1 << 5) | 15,
666
  PPC_BC_NE_PLUS  = (2 << 5) |  7,
667
  PPC_BC_UN_PLUS  = (3 << 5) | 15,
668
  PPC_BC_NU_PLUS  = (3 << 5) |  7,
669
};
670
671
// FIXME
672
// normalize CC to remove _MINUS & _PLUS
673
static int cc_normalize(int cc)
674
0
{
675
0
  switch(cc) {
676
0
    default: return cc;
677
0
    case PPC_BC_LT_MINUS: return PPC_BC_LT;
678
0
    case PPC_BC_LE_MINUS: return PPC_BC_LE;
679
0
    case PPC_BC_EQ_MINUS: return PPC_BC_EQ;
680
0
    case PPC_BC_GE_MINUS: return PPC_BC_GE;
681
0
    case PPC_BC_GT_MINUS: return PPC_BC_GT;
682
0
    case PPC_BC_NE_MINUS: return PPC_BC_NE;
683
0
    case PPC_BC_UN_MINUS: return PPC_BC_UN;
684
0
    case PPC_BC_NU_MINUS: return PPC_BC_NU;
685
0
    case PPC_BC_LT_PLUS : return PPC_BC_LT;
686
0
    case PPC_BC_LE_PLUS : return PPC_BC_LE;
687
0
    case PPC_BC_EQ_PLUS : return PPC_BC_EQ;
688
0
    case PPC_BC_GE_PLUS : return PPC_BC_GE;
689
0
    case PPC_BC_GT_PLUS : return PPC_BC_GT;
690
0
    case PPC_BC_NE_PLUS : return PPC_BC_NE;
691
0
    case PPC_BC_UN_PLUS : return PPC_BC_UN;
692
0
    case PPC_BC_NU_PLUS : return PPC_BC_NU;
693
0
  }
694
0
}
695
696
static void printPredicateOperand(MCInst *MI, unsigned OpNo,
697
    SStream *O, const char *Modifier)
698
0
{
699
0
  unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
700
701
0
  MI->flat_insn->detail->ppc.bc = (ppc_bc)cc_normalize(Code);
702
703
0
  if (!strcmp(Modifier, "cc")) {
704
0
    switch ((ppc_predicate)Code) {
705
0
      default:  // unreachable
706
0
      case PPC_PRED_LT_MINUS:
707
0
      case PPC_PRED_LT_PLUS:
708
0
      case PPC_PRED_LT:
709
0
        SStream_concat0(O, "lt");
710
0
        return;
711
0
      case PPC_PRED_LE_MINUS:
712
0
      case PPC_PRED_LE_PLUS:
713
0
      case PPC_PRED_LE:
714
0
        SStream_concat0(O, "le");
715
0
        return;
716
0
      case PPC_PRED_EQ_MINUS:
717
0
      case PPC_PRED_EQ_PLUS:
718
0
      case PPC_PRED_EQ:
719
0
        SStream_concat0(O, "eq");
720
0
        return;
721
0
      case PPC_PRED_GE_MINUS:
722
0
      case PPC_PRED_GE_PLUS:
723
0
      case PPC_PRED_GE:
724
0
        SStream_concat0(O, "ge");
725
0
        return;
726
0
      case PPC_PRED_GT_MINUS:
727
0
      case PPC_PRED_GT_PLUS:
728
0
      case PPC_PRED_GT:
729
0
        SStream_concat0(O, "gt");
730
0
        return;
731
0
      case PPC_PRED_NE_MINUS:
732
0
      case PPC_PRED_NE_PLUS:
733
0
      case PPC_PRED_NE:
734
0
        SStream_concat0(O, "ne");
735
0
        return;
736
0
      case PPC_PRED_UN_MINUS:
737
0
      case PPC_PRED_UN_PLUS:
738
0
      case PPC_PRED_UN:
739
0
        SStream_concat0(O, "un");
740
0
        return;
741
0
      case PPC_PRED_NU_MINUS:
742
0
      case PPC_PRED_NU_PLUS:
743
0
      case PPC_PRED_NU:
744
0
        SStream_concat0(O, "nu");
745
0
        return;
746
0
      case PPC_PRED_BIT_SET:
747
0
      case PPC_PRED_BIT_UNSET:
748
        // llvm_unreachable("Invalid use of bit predicate code");
749
0
        SStream_concat0(O, "invalid-predicate");
750
0
        return;
751
0
    }
752
0
  }
753
754
0
  if (!strcmp(Modifier, "pm")) {
755
0
    switch ((ppc_predicate)Code) {
756
0
      case PPC_PRED_LT:
757
0
      case PPC_PRED_LE:
758
0
      case PPC_PRED_EQ:
759
0
      case PPC_PRED_GE:
760
0
      case PPC_PRED_GT:
761
0
      case PPC_PRED_NE:
762
0
      case PPC_PRED_UN:
763
0
      case PPC_PRED_NU:
764
0
        return;
765
0
      case PPC_PRED_LT_MINUS:
766
0
      case PPC_PRED_LE_MINUS:
767
0
      case PPC_PRED_EQ_MINUS:
768
0
      case PPC_PRED_GE_MINUS:
769
0
      case PPC_PRED_GT_MINUS:
770
0
      case PPC_PRED_NE_MINUS:
771
0
      case PPC_PRED_UN_MINUS:
772
0
      case PPC_PRED_NU_MINUS:
773
0
        SStream_concat0(O, "-");
774
0
        return;
775
0
      case PPC_PRED_LT_PLUS:
776
0
      case PPC_PRED_LE_PLUS:
777
0
      case PPC_PRED_EQ_PLUS:
778
0
      case PPC_PRED_GE_PLUS:
779
0
      case PPC_PRED_GT_PLUS:
780
0
      case PPC_PRED_NE_PLUS:
781
0
      case PPC_PRED_UN_PLUS:
782
0
      case PPC_PRED_NU_PLUS:
783
0
        SStream_concat0(O, "+");
784
0
        return;
785
0
      case PPC_PRED_BIT_SET:
786
0
      case PPC_PRED_BIT_UNSET:
787
        // llvm_unreachable("Invalid use of bit predicate code");
788
0
        SStream_concat0(O, "invalid-predicate");
789
0
        return;
790
0
      default:  // unreachable
791
0
        return;
792
0
    }
793
    // llvm_unreachable("Invalid predicate code");
794
0
  }
795
796
  //assert(StringRef(Modifier) == "reg" &&
797
  //    "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
798
0
  printOperand(MI, OpNo + 1, O);
799
0
}
800
801
static void printATBitsAsHint(MCInst *MI, unsigned OpNo, SStream *O)
802
0
{
803
0
  unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
804
805
0
  if (Code == 2) {
806
0
    SStream_concat0(O, "-");
807
0
  } else if (Code == 3) {
808
0
    SStream_concat0(O, "+");
809
0
  }
810
0
}
811
812
static void printU1ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
813
881
{
814
881
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
815
816
  // assert(Value <= 1 && "Invalid u1imm argument!");
817
818
881
  printUInt32(O, Value);
819
820
881
  if (MI->csh->detail) {
821
881
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
822
881
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
823
881
    MI->flat_insn->detail->ppc.op_count++;
824
881
  }
825
881
}
826
827
static void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
828
1.37k
{
829
1.37k
  unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
830
  //assert(Value <= 3 && "Invalid u2imm argument!");
831
832
1.37k
  printUInt32(O, Value);
833
834
1.37k
  if (MI->csh->detail) {
835
1.37k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
836
1.37k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
837
1.37k
    MI->flat_insn->detail->ppc.op_count++;
838
1.37k
  }
839
1.37k
}
840
841
static void printU3ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
842
47
{
843
47
  unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
844
  //assert(Value <= 8 && "Invalid u3imm argument!");
845
846
47
  printUInt32(O, Value);
847
848
47
  if (MI->csh->detail) {
849
47
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
850
47
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
851
47
    MI->flat_insn->detail->ppc.op_count++;
852
47
  }
853
47
}
854
855
static void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
856
689
{
857
689
  unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
858
  //assert(Value <= 15 && "Invalid u4imm argument!");
859
860
689
  printUInt32(O, Value);
861
862
689
  if (MI->csh->detail) {
863
689
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
864
689
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
865
689
    MI->flat_insn->detail->ppc.op_count++;
866
689
  }
867
689
}
868
869
static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
870
161
{
871
161
  int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
872
161
  Value = SignExtend32(Value, 5);
873
874
161
  printInt32(O, Value);
875
876
161
  if (MI->csh->detail) {
877
161
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
878
161
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
879
161
    MI->flat_insn->detail->ppc.op_count++;
880
161
  }
881
161
}
882
883
static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
884
14.6k
{
885
14.6k
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
886
887
  //assert(Value <= 31 && "Invalid u5imm argument!");
888
14.6k
  printUInt32(O, Value);
889
890
14.6k
  if (MI->csh->detail) {
891
14.6k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
892
14.6k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
893
14.6k
    MI->flat_insn->detail->ppc.op_count++;
894
14.6k
  }
895
14.6k
}
896
897
static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
898
2.89k
{
899
2.89k
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
900
901
  //assert(Value <= 63 && "Invalid u6imm argument!");
902
2.89k
  printUInt32(O, Value);
903
904
2.89k
  if (MI->csh->detail) {
905
2.89k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
906
2.89k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
907
2.89k
    MI->flat_insn->detail->ppc.op_count++;
908
2.89k
  }
909
2.89k
}
910
911
static void printU7ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
912
258
{
913
258
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
914
915
  //assert(Value <= 127 && "Invalid u7imm argument!");
916
258
  printUInt32(O, Value);
917
918
258
  if (MI->csh->detail) {
919
258
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
920
258
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
921
258
    MI->flat_insn->detail->ppc.op_count++;
922
258
  }
923
258
}
924
925
// Operands of BUILD_VECTOR are signed and we use this to print operands
926
// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
927
// print as unsigned.
928
static void printU8ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
929
85
{
930
85
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
931
932
85
  printUInt32(O, Value);
933
934
85
  if (MI->csh->detail) {
935
85
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
936
85
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
937
85
    MI->flat_insn->detail->ppc.op_count++;
938
85
  }
939
85
}
940
941
static void printU10ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
942
95
{
943
95
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
944
945
  //assert(Value <= 1023 && "Invalid u10imm argument!");
946
95
  printUInt32(O, Value);
947
948
95
  if (MI->csh->detail) {
949
95
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
950
95
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
951
95
    MI->flat_insn->detail->ppc.op_count++;
952
95
  }
953
95
}
954
955
static void printS12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
956
0
{
957
0
  if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
958
0
    int Imm = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
959
0
    Imm = SignExtend32(Imm, 12);
960
961
0
    printInt32(O, Imm);
962
963
0
    if (MI->csh->detail) {
964
0
      if (MI->csh->doing_mem) {
965
0
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm;
966
0
      } else {
967
0
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
968
0
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
969
0
                MI->flat_insn->detail->ppc.op_count++;
970
0
            }
971
0
    }
972
0
  } else
973
0
    printOperand(MI, OpNo, O);
974
0
}
975
976
static void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
977
819
{
978
819
  unsigned short Value = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
979
980
  // assert(Value <= 4095 && "Invalid u12imm argument!");
981
982
819
  printUInt32(O, Value);
983
984
819
  if (MI->csh->detail) {
985
819
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
986
819
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
987
819
    MI->flat_insn->detail->ppc.op_count++;
988
819
  }
989
819
}
990
991
static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
992
26.1k
{
993
26.1k
  if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
994
26.1k
    short Imm = (short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
995
26.1k
    printInt32(O, Imm);
996
997
26.1k
    if (MI->csh->detail) {
998
26.1k
      if (MI->csh->doing_mem) {
999
14.1k
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm;
1000
14.1k
      } else {
1001
11.9k
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1002
11.9k
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
1003
11.9k
                MI->flat_insn->detail->ppc.op_count++;
1004
11.9k
            }
1005
26.1k
    }
1006
26.1k
  } else
1007
0
    printOperand(MI, OpNo, O);
1008
26.1k
}
1009
1010
static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
1011
5.33k
{
1012
5.33k
  if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
1013
5.33k
    unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
1014
5.33k
    printUInt32(O, Imm);
1015
1016
5.33k
    if (MI->csh->detail) {
1017
5.33k
      MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1018
5.33k
      MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
1019
5.33k
      MI->flat_insn->detail->ppc.op_count++;
1020
5.33k
    }
1021
5.33k
  } else
1022
0
    printOperand(MI, OpNo, O);
1023
5.33k
}
1024
1025
static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
1026
7.14k
{
1027
7.14k
  if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
1028
0
    printOperand(MI, OpNo, O);
1029
1030
0
    return;
1031
0
  }
1032
1033
  // Branches can take an immediate operand.  This is used by the branch
1034
  // selection pass to print .+8, an eight byte displacement from the PC.
1035
  // O << ".+";
1036
7.14k
  printAbsBranchOperand(MI, OpNo, O);
1037
7.14k
}
1038
1039
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
1040
9.67k
{
1041
9.67k
  int64_t imm;
1042
1043
9.67k
  if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
1044
0
    printOperand(MI, OpNo, O);
1045
1046
0
    return;
1047
0
  }
1048
1049
9.67k
  imm = SignExtend32(MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4, 32);
1050
  //imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4;
1051
1052
9.67k
  if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) {
1053
4.18k
    imm += MI->address;
1054
4.18k
  }
1055
1056
9.67k
  printUInt64(O, imm);
1057
1058
9.67k
  if (MI->csh->detail) {
1059
9.67k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1060
9.67k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
1061
9.67k
    MI->flat_insn->detail->ppc.op_count++;
1062
9.67k
  }
1063
9.67k
}
1064
1065
static void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O)
1066
982
{
1067
982
  unsigned RegNo;
1068
982
  unsigned CCReg = MCOperand_getReg(MCInst_getOperand(MI, OpNo));
1069
1070
982
  switch (CCReg) {
1071
0
    default: // llvm_unreachable("Unknown CR register");
1072
128
    case PPC_CR0: RegNo = 0; break;
1073
78
    case PPC_CR1: RegNo = 1; break;
1074
129
    case PPC_CR2: RegNo = 2; break;
1075
71
    case PPC_CR3: RegNo = 3; break;
1076
39
    case PPC_CR4: RegNo = 4; break;
1077
221
    case PPC_CR5: RegNo = 5; break;
1078
100
    case PPC_CR6: RegNo = 6; break;
1079
216
    case PPC_CR7: RegNo = 7; break;
1080
982
  }
1081
1082
982
  printUInt32(O, 0x80 >> RegNo);
1083
982
}
1084
1085
static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
1086
28.4k
{
1087
28.4k
  set_mem_access(MI, true);
1088
1089
28.4k
  printS16ImmOperand(MI, OpNo, O);
1090
1091
28.4k
  SStream_concat0(O, "(");
1092
1093
28.4k
  if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0)
1094
0
    SStream_concat0(O, "0");
1095
28.4k
  else
1096
28.4k
    printOperand(MI, OpNo + 1, O);
1097
1098
28.4k
  SStream_concat0(O, ")");
1099
1100
28.4k
  set_mem_access(MI, false);
1101
28.4k
}
1102
1103
static void printPSMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
1104
0
{
1105
0
  set_mem_access(MI, true);
1106
1107
0
  printS12ImmOperand(MI, OpNo, O);
1108
1109
0
  SStream_concat0(O, "(");
1110
0
  printOperand(MI, OpNo + 1, O);
1111
0
  SStream_concat0(O, ")");
1112
1113
0
  set_mem_access(MI, false);
1114
0
}
1115
1116
static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O)
1117
5.48k
{
1118
  // When used as the base register, r0 reads constant zero rather than
1119
  // the value contained in the register.  For this reason, the darwin
1120
  // assembler requires that we print r0 as 0 (no r) when used as the base.
1121
5.48k
  if (MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == PPC_R0)
1122
0
    SStream_concat0(O, "0");
1123
5.48k
  else
1124
5.48k
    printOperand(MI, OpNo, O);
1125
5.48k
  SStream_concat0(O, ", ");
1126
1127
5.48k
  printOperand(MI, OpNo + 1, O);
1128
5.48k
}
1129
1130
static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
1131
0
{
1132
0
  set_mem_access(MI, true);
1133
  //printBranchOperand(MI, OpNo, O);
1134
1135
  // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
1136
  // come at the _end_ of the expression.
1137
1138
0
  SStream_concat0(O, "(");
1139
0
  printOperand(MI, OpNo + 1, O);
1140
0
  SStream_concat0(O, ")");
1141
1142
0
  set_mem_access(MI, false);
1143
0
}
1144
1145
/// stripRegisterPrefix - This method strips the character prefix from a
1146
/// register name so that only the number is left.  Used by for linux asm.
1147
static char *stripRegisterPrefix(const char *RegName)
1148
0
{
1149
0
  switch (RegName[0]) {
1150
0
    case 'r':
1151
0
    case 'f':
1152
0
    case 'q': // for QPX
1153
0
    case 'v':
1154
0
      if (RegName[1] == 's')
1155
0
        return cs_strdup(RegName + 2);
1156
1157
0
      return cs_strdup(RegName + 1);
1158
0
    case 'c':
1159
0
      if (RegName[1] == 'r') {
1160
        // skip the first 2 letters "cr"
1161
0
        char *name = cs_strdup(RegName + 2);
1162
1163
        // also strip the last 2 letters
1164
0
        if(strlen(name) > 2)
1165
0
          name[strlen(name) - 2] = '\0';
1166
1167
0
        return name;
1168
0
      }
1169
0
  }
1170
1171
0
  return cs_strdup(RegName);
1172
0
}
1173
1174
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
1175
158k
{
1176
158k
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
1177
158k
  if (MCOperand_isReg(Op)) {
1178
153k
    unsigned reg = MCOperand_getReg(Op);
1179
153k
#ifndef CAPSTONE_DIET
1180
153k
    const char *RegName = getRegisterName(reg);
1181
1182
    // printf("reg = %u (%s)\n", reg, RegName);
1183
1184
    // convert internal register ID to public register ID
1185
153k
    reg = PPC_name_reg(RegName);
1186
1187
    // The linux and AIX assembler does not take register prefixes.
1188
153k
    if (MI->csh->syntax == CS_OPT_SYNTAX_NOREGNAME) {
1189
0
      char *name = stripRegisterPrefix(RegName);
1190
0
      SStream_concat0(O, name);
1191
0
      cs_mem_free(name);
1192
0
    } else
1193
153k
      SStream_concat0(O, RegName);
1194
153k
#endif
1195
1196
153k
    if (MI->csh->detail) {
1197
153k
      if (MI->csh->doing_mem) {
1198
14.1k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = reg;
1199
139k
      } else {
1200
139k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
1201
139k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
1202
139k
        MI->flat_insn->detail->ppc.op_count++;
1203
139k
      }
1204
153k
    }
1205
1206
153k
    return;
1207
153k
  }
1208
1209
4.59k
  if (MCOperand_isImm(Op)) {
1210
4.59k
    int32_t imm = (int32_t)MCOperand_getImm(Op);
1211
4.59k
    printInt32(O, imm);
1212
1213
4.59k
    if (MI->csh->detail) {
1214
4.59k
      if (MI->csh->doing_mem) {
1215
0
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = (int32_t)imm;
1216
4.59k
      } else {
1217
4.59k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1218
4.59k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
1219
4.59k
        MI->flat_insn->detail->ppc.op_count++;
1220
4.59k
      }
1221
4.59k
    }
1222
4.59k
  }
1223
4.59k
}
1224
1225
static void op_addImm(MCInst *MI, int v)
1226
17
{
1227
17
  if (MI->csh->detail) {
1228
17
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1229
17
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = v;
1230
17
    MI->flat_insn->detail->ppc.op_count++;
1231
17
  }
1232
17
}
1233
1234
#define PRINT_ALIAS_INSTR
1235
#include "PPCGenRegisterName.inc"
1236
#include "PPCGenAsmWriter.inc"
1237
1238
#endif