Coverage Report

Created: 2026-06-06 06:15

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonenext/arch/RISCV/RISCVBaseInfo.c
Line
Count
Source
1
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
2
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
3
/*    Rot127 <unisono@quyllur.org> 2022-2023 */
4
/* Automatically translated source file from LLVM. */
5
6
/* LLVM-commit: <commit> */
7
/* LLVM-tag: <tag> */
8
9
/* Only small edits allowed. */
10
/* For multiple similar edits, please create a Patch for the translator. */
11
12
/* Capstone's C++ file translator: */
13
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
14
15
//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
16
//
17
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
18
// See https://llvm.org/LICENSE.txt for license information.
19
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
20
//
21
//===----------------------------------------------------------------------===//
22
//
23
// This file contains small standalone enum definitions for the RISC-V target
24
// useful for the compiler back-end and the MC libraries.
25
//
26
//===----------------------------------------------------------------------===//
27
28
#include <stdio.h>
29
#include <string.h>
30
#include <stdlib.h>
31
#include <capstone/platform.h>
32
33
#include "RISCVBaseInfo.h"
34
35
#define CONCAT(a, b) CONCAT_(a, b)
36
#define CONCAT_(a, b) a##_##b
37
38
typedef struct {
39
  unsigned value;
40
  bool isFractional;
41
} VLMULDecodeResult;
42
43
VLMULDecodeResult decodeVLMUL(RISCVII_VLMUL VLMUL)
44
480
{
45
480
  switch (VLMUL) {
46
0
  default:
47
0
    CS_ASSERT(0 && "Unexpected LMUL value!");
48
0
    break;
49
33
  case RISCVII_LMUL_1:
50
249
  case RISCVII_LMUL_2:
51
283
  case RISCVII_LMUL_4:
52
310
  case RISCVII_LMUL_8: {
53
310
    VLMULDecodeResult result = { .value = 1 << (unsigned)(VLMUL),
54
310
               .isFractional = false };
55
310
    return result;
56
283
  }
57
3
  case RISCVII_LMUL_F2:
58
54
  case RISCVII_LMUL_F4:
59
170
  case RISCVII_LMUL_F8: {
60
170
    VLMULDecodeResult result = { .value = 1 << (8 -
61
170
                  (unsigned)(VLMUL)),
62
170
               .isFractional = true };
63
170
    return result;
64
54
  }
65
480
  }
66
0
  VLMULDecodeResult result = { .value = 0, .isFractional = false };
67
0
  return result;
68
480
}
69
70
void printVType(unsigned VType, SStream *OS)
71
480
{
72
480
  unsigned Sew = RISCVVType_getSEW(VType);
73
480
  SStream_concat(OS, "%s", "e");
74
480
  printUInt64(OS, Sew);
75
76
480
  unsigned LMul;
77
480
  bool Fractional;
78
480
  VLMULDecodeResult result = decodeVLMUL(RISCVVType_getVLMUL(VType));
79
480
  LMul = result.value;
80
480
  Fractional = result.isFractional;
81
82
480
  if (Fractional)
83
170
    SStream_concat0(OS, ", mf");
84
310
  else
85
310
    SStream_concat0(OS, ", m");
86
480
  printUInt64(OS, LMul);
87
88
480
  if (RISCVVType_isTailAgnostic(VType))
89
331
    SStream_concat0(OS, ", ta");
90
149
  else
91
149
    SStream_concat0(OS, ", tu");
92
93
480
  if (RISCVVType_isMaskAgnostic(VType))
94
150
    SStream_concat0(OS, ", ma");
95
330
  else
96
330
    SStream_concat0(OS, ", mu");
97
480
}
98
99
typedef struct {
100
  uint8_t first;
101
  uint8_t second;
102
} LoadFP32ImmArrElement;
103
104
// Lookup table for fli.s for entries 2-31.
105
static const LoadFP32ImmArrElement LoadFP32ImmArr[] = {
106
  { 0x6f, 0x00 }, { 0x70, 0x00 }, { 0x77, 0x00 }, { 0x78, 0x00 },
107
  { 0x7b, 0x00 }, { 0x7c, 0x00 }, { 0x7d, 0x00 }, { 0x7d, 0x01 },
108
  { 0x7d, 0x02 }, { 0x7d, 0x03 }, { 0x7e, 0x00 }, { 0x7e, 0x01 },
109
  { 0x7e, 0x02 }, { 0x7e, 0x03 }, { 0x7f, 0x00 }, { 0x7f, 0x01 },
110
  { 0x7f, 0x02 }, { 0x7f, 0x03 }, { 0x80, 0x00 }, { 0x80, 0x01 },
111
  { 0x80, 0x02 }, { 0x81, 0x00 }, { 0x82, 0x00 }, { 0x83, 0x00 },
112
  { 0x86, 0x00 }, { 0x87, 0x00 }, { 0x8e, 0x00 }, { 0x8f, 0x00 },
113
  { 0xff, 0x00 }, { 0xff, 0x02 },
114
};
115
116
float getFPImm(unsigned Imm)
117
472
{
118
472
  CS_ASSERT(Imm != 1 && Imm != 30 && Imm != 31 &&
119
472
      "Unsupported immediate");
120
472
  CS_ASSERT((Imm == 0 || (Imm >= 2 && Imm < 30)) &&
121
472
      "Unsupported immediate");
122
  // Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
123
472
  uint32_t Sign = 0;
124
472
  if (Imm == 0) {
125
188
    Sign = 0x01;
126
188
    Imm = 16;
127
188
  }
128
129
472
  uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
130
472
  uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
131
132
472
  uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
133
472
  float result;
134
472
  memcpy(&result, &I, sizeof(float));
135
472
  return result;
136
472
}
137
138
void RISCVZC_printSpimm(int64_t Spimm, SStream *OS)
139
0
{
140
0
  printInt32(OS, Spimm);
141
0
}
142
143
// namespace llvm