/src/capstonenext/arch/RISCV/RISCVDisassemblerExtension.c
Line | Count | Source |
1 | | #include "RISCVDisassemblerExtension.h" |
2 | | |
3 | | #define GET_SUBTARGETINFO_ENUM |
4 | | #include "RISCVGenSubtargetInfo.inc" |
5 | | |
6 | | bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature) |
7 | 717k | { |
8 | 717k | if (feature == RISCV_FeatureNoRVCHints) { |
9 | 9.82k | return false; |
10 | 9.82k | } |
11 | | |
12 | 707k | switch (feature) { |
13 | 0 | case RISCV_Feature32Bit: |
14 | 0 | return mode & CS_MODE_RISCV32; |
15 | | |
16 | 80.8k | case RISCV_Feature64Bit: |
17 | 80.8k | return mode & CS_MODE_RISCV64; |
18 | | |
19 | 64 | case RISCV_FeatureStdExtF: |
20 | 157 | case RISCV_FeatureStdExtD: |
21 | 157 | return mode & CS_MODE_RISCV_FD; |
22 | | |
23 | 0 | case RISCV_FeatureStdExtV: |
24 | 0 | return mode & CS_MODE_RISCV_V; |
25 | | |
26 | 12.3k | case RISCV_FeatureStdExtZfinx: |
27 | 24.6k | case RISCV_FeatureStdExtZdinx: |
28 | 24.6k | case RISCV_FeatureStdExtZhinx: |
29 | 24.6k | case RISCV_FeatureStdExtZhinxmin: |
30 | 24.6k | return mode & CS_MODE_RISCV_ZFINX; |
31 | | |
32 | 80.4k | case RISCV_FeatureStdExtC: |
33 | 80.4k | return mode & CS_MODE_RISCV_C; |
34 | | |
35 | 22.2k | case RISCV_FeatureStdExtZcmp: |
36 | 44.5k | case RISCV_FeatureStdExtZcmt: |
37 | 44.5k | case RISCV_FeatureStdExtZce: |
38 | 44.5k | return mode & CS_MODE_RISCV_ZCMP_ZCMT_ZCE; |
39 | | |
40 | 22.4k | case RISCV_FeatureStdExtZicfiss: |
41 | 22.4k | return mode & CS_MODE_RISCV_ZICFISS; |
42 | | |
43 | 30.9k | case RISCV_FeatureRVE: |
44 | 30.9k | return mode & CS_MODE_RISCV_E; |
45 | | |
46 | 4 | case RISCV_FeatureStdExtA: |
47 | 4 | return mode & CS_MODE_RISCV_A; |
48 | | |
49 | 12.2k | case RISCV_FeatureVendorXCVelw: |
50 | 12.2k | return mode & CS_MODE_RISCV_COREV; |
51 | | |
52 | 12.3k | case RISCV_FeatureVendorXSfvcp: |
53 | 24.6k | case RISCV_FeatureVendorXSfvfnrclipxfqf: |
54 | 37.0k | case RISCV_FeatureVendorXSfvfwmaccqqq: |
55 | 49.3k | case RISCV_FeatureVendorXSfvqmaccdod: |
56 | 61.7k | case RISCV_FeatureVendorXSfvqmaccqoq: |
57 | 61.7k | return mode & CS_MODE_RISCV_SIFIVE; |
58 | | |
59 | 12.3k | case RISCV_FeatureVendorXTHeadBa: |
60 | 24.6k | case RISCV_FeatureVendorXTHeadBb: |
61 | 37.0k | case RISCV_FeatureVendorXTHeadBs: |
62 | 49.3k | case RISCV_FeatureVendorXTHeadCmo: |
63 | 61.7k | case RISCV_FeatureVendorXTHeadCondMov: |
64 | 74.0k | case RISCV_FeatureVendorXTHeadFMemIdx: |
65 | 86.3k | case RISCV_FeatureVendorXTHeadMac: |
66 | 98.7k | case RISCV_FeatureVendorXTHeadMemIdx: |
67 | 111k | case RISCV_FeatureVendorXTHeadMemPair: |
68 | 123k | case RISCV_FeatureVendorXTHeadSync: |
69 | 135k | case RISCV_FeatureVendorXTHeadVdot: |
70 | 135k | return mode & CS_MODE_RISCV_THEAD; |
71 | | |
72 | 12.3k | case RISCV_FeatureVendorXVentanaCondOps: |
73 | 12.3k | return mode & CS_MODE_RISCV_VENTANA; |
74 | | |
75 | 4 | case RISCV_FeatureStdExtZba: |
76 | 4 | return mode & CS_MODE_RISCV_ZBA; |
77 | 5 | case RISCV_FeatureStdExtZbb: |
78 | 5 | return mode & CS_MODE_RISCV_ZBB; |
79 | 1 | case RISCV_FeatureStdExtZbc: |
80 | 1 | return mode & CS_MODE_RISCV_ZBC; |
81 | 5 | case RISCV_FeatureStdExtZbkb: |
82 | 5 | return mode & CS_MODE_RISCV_ZBKB; |
83 | 0 | case RISCV_FeatureStdExtZbkc: |
84 | 0 | return mode & CS_MODE_RISCV_ZBKC; |
85 | 1 | case RISCV_FeatureStdExtZbkx: |
86 | 1 | return mode & CS_MODE_RISCV_ZBKX; |
87 | 1 | case RISCV_FeatureStdExtZbs: |
88 | 1 | return mode & CS_MODE_RISCV_ZBS; |
89 | 201k | default: |
90 | | // support everything by default |
91 | | return true; |
92 | 707k | } |
93 | 707k | } |