Coverage Report

Created: 2026-06-15 06:41

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/capstonev5/arch/PowerPC/PPCInstPrinter.c
Line
Count
Source
1
//===-- PPCInstPrinter.cpp - Convert PPC MCInst to assembly syntax --------===//
2
//
3
//                     The LLVM Compiler Infrastructure
4
//
5
// This file is distributed under the University of Illinois Open Source
6
// License. See LICENSE.TXT for details.
7
//
8
//===----------------------------------------------------------------------===//
9
//
10
// This class prints an PPC MCInst to a .s file.
11
//
12
//===----------------------------------------------------------------------===//
13
14
/* Capstone Disassembly Engine */
15
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
16
17
#ifdef CAPSTONE_HAS_POWERPC
18
19
#include <stdio.h>
20
#include <stdlib.h>
21
#include <string.h>
22
23
#include "PPCInstPrinter.h"
24
#include "PPCPredicates.h"
25
#include "../../MCInst.h"
26
#include "../../utils.h"
27
#include "../../SStream.h"
28
#include "../../MCRegisterInfo.h"
29
#include "../../MathExtras.h"
30
#include "PPCMapping.h"
31
32
#ifndef CAPSTONE_DIET
33
static const char *getRegisterName(unsigned RegNo);
34
#endif
35
36
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
37
static void printInstruction(MCInst *MI, SStream *O);
38
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
39
static char *printAliasInstr(MCInst *MI, SStream *OS, MCRegisterInfo *MRI);
40
static char *printAliasBcc(MCInst *MI, SStream *OS, void *info);
41
static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
42
    unsigned PrintMethodIdx, SStream *OS);
43
44
#if 0
45
static void printRegName(SStream *OS, unsigned RegNo)
46
{
47
  char *RegName = getRegisterName(RegNo);
48
49
  if (RegName[0] == 'q' /* QPX */) {
50
    // The system toolchain on the BG/Q does not understand QPX register names
51
    // in .cfi_* directives, so print the name of the floating-point
52
    // subregister instead.
53
    RegName[0] = 'f';
54
  }
55
56
  SStream_concat0(OS, RegName);
57
}
58
#endif
59
60
static void set_mem_access(MCInst *MI, bool status)
61
39.3k
{
62
39.3k
  if (MI->csh->detail != CS_OPT_ON)
63
0
    return;
64
65
39.3k
  MI->csh->doing_mem = status;
66
67
39.3k
  if (status) {
68
19.6k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_MEM;
69
19.6k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = PPC_REG_INVALID;
70
19.6k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = 0;
71
19.6k
  } else {
72
    // done, create the next operand slot
73
19.6k
    MI->flat_insn->detail->ppc.op_count++;
74
19.6k
  }
75
39.3k
}
76
77
void PPC_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
78
139k
{
79
139k
  if (((cs_struct *)ud)->detail != CS_OPT_ON)
80
0
    return;
81
82
  // check if this insn has branch hint
83
139k
  if (strrchr(insn->mnemonic, '+') != NULL && !strstr(insn_asm, ".+")) {
84
4.08k
    insn->detail->ppc.bh = PPC_BH_PLUS;
85
135k
  } else if (strrchr(insn->mnemonic, '-') != NULL) {
86
2.48k
    insn->detail->ppc.bh = PPC_BH_MINUS;
87
2.48k
  }
88
89
139k
  if (strrchr(insn->mnemonic, '.') != NULL) {
90
10.1k
    insn->detail->ppc.update_cr0 = true;
91
10.1k
  }
92
139k
}
93
94
#define GET_INSTRINFO_ENUM
95
#include "PPCGenInstrInfo.inc"
96
97
#define GET_REGINFO_ENUM
98
#include "PPCGenRegisterInfo.inc"
99
100
static void op_addBC(MCInst *MI, unsigned int bc)
101
3.72k
{
102
3.72k
  if (MI->csh->detail) {
103
3.72k
    MI->flat_insn->detail->ppc.bc = (ppc_bc)bc;
104
3.72k
  }
105
3.72k
}
106
107
1.34k
#define CREQ (0)
108
581
#define CRGT (1)
109
2.07k
#define CRLT (2)
110
1.84k
#define CRUN (3)
111
112
static int getBICRCond(int bi)
113
5.84k
{
114
5.84k
  return (bi - PPC_CR0EQ) >> 3;
115
5.84k
}
116
117
static int getBICR(int bi)
118
5.84k
{
119
5.84k
  return ((bi - PPC_CR0EQ) & 7) + PPC_CR0;
120
5.84k
}
121
122
static void op_addReg(MCInst *MI, unsigned int reg)
123
1.76k
{
124
1.76k
  if (MI->csh->detail) {
125
1.76k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
126
1.76k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
127
1.76k
    MI->flat_insn->detail->ppc.op_count++;
128
1.76k
  }
129
1.76k
}
130
131
static void add_CRxx(MCInst *MI, ppc_reg reg)
132
1.40k
{
133
1.40k
  if (MI->csh->detail) {
134
1.40k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
135
1.40k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
136
1.40k
    MI->flat_insn->detail->ppc.op_count++;
137
1.40k
  }
138
1.40k
}
139
140
static char *printAliasBcc(MCInst *MI, SStream *OS, void *info)
141
137k
{
142
137k
#define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
143
137k
  SStream ss;
144
137k
  const char *opCode;
145
137k
  char *tmp, *AsmMnem, *AsmOps, *c;
146
137k
  int OpIdx, PrintMethodIdx;
147
137k
  int decCtr = false, needComma = false;
148
137k
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
149
150
137k
  SStream_Init(&ss);
151
152
137k
  switch (MCInst_getOpcode(MI)) {
153
128k
    default: return NULL;
154
3.96k
    case PPC_gBC:
155
3.96k
         opCode = "b%s";
156
3.96k
         break;
157
1.94k
    case PPC_gBCA:
158
1.94k
         opCode = "b%sa";
159
1.94k
         break;
160
53
    case PPC_gBCCTR:
161
53
         opCode = "b%sctr";
162
53
         break;
163
147
    case PPC_gBCCTRL:
164
147
         opCode = "b%sctrl";
165
147
         break;
166
1.20k
    case PPC_gBCL:
167
1.20k
         opCode = "b%sl";
168
1.20k
         break;
169
1.25k
    case PPC_gBCLA:
170
1.25k
         opCode = "b%sla";
171
1.25k
         break;
172
73
    case PPC_gBCLR:
173
73
         opCode = "b%slr";
174
73
         break;
175
42
    case PPC_gBCLRL:
176
42
         opCode = "b%slrl";
177
42
         break;
178
137k
  }
179
180
8.69k
  if (MCInst_getNumOperands(MI) == 3 &&
181
8.69k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
182
8.69k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 0) &&
183
8.69k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 1)) {
184
1.22k
    SStream_concat(&ss, opCode, "dnzf");
185
1.22k
    decCtr = true;
186
1.22k
  }
187
188
8.69k
  if (MCInst_getNumOperands(MI) == 3 &&
189
8.69k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
190
8.69k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 2) &&
191
7.46k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 3)) {
192
1.49k
    SStream_concat(&ss, opCode, "dzf");
193
1.49k
    decCtr = true;
194
1.49k
  }
195
196
8.69k
  if (MCInst_getNumOperands(MI) == 3 &&
197
8.69k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
198
8.69k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 4) &&
199
5.97k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 7) &&
200
858
      MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
201
858
      GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
202
858
    int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
203
204
858
    switch(cr) {
205
87
      case CREQ:
206
87
        SStream_concat(&ss, opCode, "ne");
207
87
        break;
208
65
      case CRGT:
209
65
        SStream_concat(&ss, opCode, "le");
210
65
        break;
211
404
      case CRLT:
212
404
        SStream_concat(&ss, opCode, "ge");
213
404
        break;
214
302
      case CRUN:
215
302
        SStream_concat(&ss, opCode, "ns");
216
302
        break;
217
858
    }
218
219
858
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 6)
220
234
      SStream_concat0(&ss, "-");
221
222
858
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 7)
223
240
      SStream_concat0(&ss, "+");
224
225
858
    decCtr = false;
226
858
  }
227
228
8.69k
  if (MCInst_getNumOperands(MI) == 3 &&
229
8.69k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
230
8.69k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 8) &&
231
5.11k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 9)) {
232
587
    SStream_concat(&ss, opCode, "dnzt");
233
587
    decCtr = true;
234
587
  }
235
236
8.69k
  if (MCInst_getNumOperands(MI) == 3 &&
237
8.69k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
238
8.69k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 10) &&
239
4.52k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 11)) {
240
418
    SStream_concat(&ss, opCode, "dzt");
241
418
    decCtr = true;
242
418
  }
243
244
8.69k
  if (MCInst_getNumOperands(MI) == 3 &&
245
8.69k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
246
8.69k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) >= 12) &&
247
4.10k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) <= 15) &&
248
1.25k
      MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
249
1.25k
      GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1)) {
250
1.25k
    int cr = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
251
252
1.25k
    switch(cr) {
253
281
      case CREQ:
254
281
        SStream_concat(&ss, opCode, "eq");
255
281
        break;
256
78
      case CRGT:
257
78
        SStream_concat(&ss, opCode, "gt");
258
78
        break;
259
604
      case CRLT:
260
604
        SStream_concat(&ss, opCode, "lt");
261
604
        break;
262
292
      case CRUN:
263
292
        SStream_concat(&ss, opCode, "so");
264
292
        break;
265
1.25k
    }
266
267
1.25k
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 14)
268
622
      SStream_concat0(&ss, "-");
269
270
1.25k
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 15)
271
264
      SStream_concat0(&ss, "+");
272
273
1.25k
    decCtr = false;
274
1.25k
  }
275
276
8.69k
  if (MCInst_getNumOperands(MI) == 3 &&
277
8.69k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
278
8.69k
      ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 16)) {
279
1.10k
    SStream_concat(&ss, opCode, "dnz");
280
281
1.10k
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 24)
282
425
      SStream_concat0(&ss, "-");
283
284
1.10k
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 25)
285
144
      SStream_concat0(&ss, "+");
286
287
1.10k
    needComma = false;
288
1.10k
  }
289
290
8.69k
  if (MCInst_getNumOperands(MI) == 3 &&
291
8.69k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
292
8.69k
      ((MCOperand_getImm(MCInst_getOperand(MI, 0)) & 0x12)== 18)) {
293
1.74k
    SStream_concat(&ss, opCode, "dz");
294
295
1.74k
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 26)
296
805
      SStream_concat0(&ss, "-");
297
298
1.74k
    if (MCOperand_getImm(MCInst_getOperand(MI, 0)) == 27)
299
97
      SStream_concat0(&ss, "+");
300
301
1.74k
    needComma = false;
302
1.74k
  }
303
304
8.69k
  if (MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
305
8.69k
      GETREGCLASS_CONTAIN(PPC_CRBITRCRegClassID, 1) &&
306
8.69k
      MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
307
8.69k
      (MCOperand_getImm(MCInst_getOperand(MI, 0)) < 16)) {
308
5.84k
    int cr = getBICR(MCOperand_getReg(MCInst_getOperand(MI, 1)));
309
310
5.84k
    if (decCtr) {
311
3.72k
      int cd;
312
3.72k
      needComma = true;
313
3.72k
      SStream_concat0(&ss, " ");
314
315
3.72k
      if (cr > PPC_CR0) {
316
2.32k
        SStream_concat(&ss, "4*cr%d+", cr - PPC_CR0);
317
2.32k
      }
318
319
3.72k
      cd = getBICRCond(MCOperand_getReg(MCInst_getOperand(MI, 1)));
320
3.72k
      switch(cd) {
321
975
        case CREQ:
322
975
          SStream_concat0(&ss, "eq");
323
975
          if (cr <= PPC_CR0)
324
133
            add_CRxx(MI, PPC_REG_CR0EQ);
325
975
          op_addBC(MI, PPC_BC_EQ);
326
975
          break;
327
438
        case CRGT:
328
438
          SStream_concat0(&ss, "gt");
329
438
          if (cr <= PPC_CR0)
330
322
            add_CRxx(MI, PPC_REG_CR0GT);
331
438
          op_addBC(MI, PPC_BC_GT);
332
438
          break;
333
1.06k
        case CRLT:
334
1.06k
          SStream_concat0(&ss, "lt");
335
1.06k
          if (cr <= PPC_CR0)
336
646
            add_CRxx(MI, PPC_REG_CR0LT);
337
1.06k
          op_addBC(MI, PPC_BC_LT);
338
1.06k
          break;
339
1.24k
        case CRUN:
340
1.24k
          SStream_concat0(&ss, "so");
341
1.24k
          if (cr <= PPC_CR0)
342
300
            add_CRxx(MI, PPC_REG_CR0UN);
343
1.24k
          op_addBC(MI, PPC_BC_SO);
344
1.24k
          break;
345
3.72k
      }
346
347
3.72k
      if (cr > PPC_CR0) {
348
2.32k
        if (MI->csh->detail) {
349
2.32k
          MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
350
2.32k
          MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 1));
351
2.32k
          MI->flat_insn->detail->ppc.op_count++;
352
2.32k
        }
353
2.32k
      }
354
3.72k
    } else {
355
2.11k
      if (cr > PPC_CR0) {
356
1.76k
        needComma = true;
357
1.76k
        SStream_concat(&ss, " cr%d", cr - PPC_CR0);
358
1.76k
        op_addReg(MI, PPC_REG_CR0 + cr - PPC_CR0);
359
1.76k
      }
360
2.11k
    }
361
5.84k
  }
362
363
8.69k
  if (MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
364
8.69k
      MCOperand_getImm(MCInst_getOperand(MI, 2)) != 0) {
365
8.12k
    if (needComma)
366
5.11k
      SStream_concat0(&ss, ",");
367
368
8.12k
    SStream_concat0(&ss, " $\xFF\x03\x01");
369
8.12k
  }
370
371
8.69k
  tmp = cs_strdup(ss.buffer);
372
8.69k
  AsmMnem = tmp;
373
50.9k
  for(AsmOps = tmp; *AsmOps; AsmOps++) {
374
50.7k
    if (*AsmOps == ' ' || *AsmOps == '\t') {
375
8.50k
      *AsmOps = '\0';
376
8.50k
      AsmOps++;
377
8.50k
      break;
378
8.50k
    }
379
50.7k
  }
380
381
8.69k
  SStream_concat0(OS, AsmMnem);
382
8.69k
  if (*AsmOps) {
383
8.50k
    SStream_concat0(OS, "\t");
384
53.5k
    for (c = AsmOps; *c; c++) {
385
45.0k
      if (*c == '$') {
386
8.12k
        c += 1;
387
8.12k
        if (*c == (char)0xff) {
388
8.12k
          c += 1;
389
8.12k
          OpIdx = *c - 1;
390
8.12k
          c += 1;
391
8.12k
          PrintMethodIdx = *c - 1;
392
8.12k
          printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
393
8.12k
        } else
394
0
          printOperand(MI, *c - 1, OS);
395
36.9k
      } else {
396
36.9k
        SStream_concat1(OS, *c);
397
36.9k
      }
398
45.0k
    }
399
8.50k
  }
400
401
8.69k
  return tmp;
402
8.69k
}
403
404
static bool isBOCTRBranch(unsigned int op)
405
137k
{
406
137k
  return ((op >= PPC_BDNZ) && (op <= PPC_BDZp));
407
137k
}
408
409
void PPC_printInst(MCInst *MI, SStream *O, void *Info)
410
139k
{
411
139k
  char *mnem;
412
139k
  unsigned int opcode = MCInst_getOpcode(MI);
413
139k
  memset(O->buffer, 0, sizeof(O->buffer));
414
415
  // printf("opcode = %u\n", opcode);
416
417
  // Check for slwi/srwi mnemonics.
418
139k
  if (opcode == PPC_RLWINM) {
419
2.33k
    unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
420
2.33k
    unsigned char MB = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
421
2.33k
    unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 4));
422
2.33k
    bool useSubstituteMnemonic = false;
423
424
2.33k
    if (SH <= 31 && MB == 0 && ME == (31 - SH)) {
425
402
      SStream_concat0(O, "slwi\t");
426
402
      MCInst_setOpcodePub(MI, PPC_INS_SLWI);
427
402
      useSubstituteMnemonic = true;
428
402
    }
429
430
2.33k
    if (SH <= 31 && MB == (32 - SH) && ME == 31) {
431
191
      SStream_concat0(O, "srwi\t");
432
191
      MCInst_setOpcodePub(MI, PPC_INS_SRWI);
433
191
      useSubstituteMnemonic = true;
434
191
      SH = 32 - SH;
435
191
    }
436
437
2.33k
    if (useSubstituteMnemonic) {
438
593
      printOperand(MI, 0, O);
439
593
      SStream_concat0(O, ", ");
440
593
      printOperand(MI, 1, O);
441
442
593
      if (SH > HEX_THRESHOLD)
443
191
        SStream_concat(O, ", 0x%x", (unsigned int)SH);
444
402
      else
445
402
        SStream_concat(O, ", %u", (unsigned int)SH);
446
447
593
      if (MI->csh->detail) {
448
593
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
449
450
593
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
451
593
        ppc->operands[ppc->op_count].imm = SH;
452
593
        ++ppc->op_count;
453
593
      }
454
455
593
      return;
456
593
    }
457
2.33k
  }
458
459
138k
  if ((opcode == PPC_OR || opcode == PPC_OR8) &&
460
175
      MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2))) {
461
100
    SStream_concat0(O, "mr\t");
462
100
    MCInst_setOpcodePub(MI, PPC_INS_MR);
463
464
100
    printOperand(MI, 0, O);
465
100
    SStream_concat0(O, ", ");
466
100
    printOperand(MI, 1, O);
467
468
100
    return;
469
100
  }
470
471
138k
  if (opcode == PPC_RLDICR ||
472
137k
      opcode == PPC_RLDICR_32) {
473
571
    unsigned char SH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 2));
474
571
    unsigned char ME = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 3));
475
476
    // rldicr RA, RS, SH, 63-SH == sldi RA, RS, SH
477
571
    if (63 - SH == ME) {
478
138
      SStream_concat0(O, "sldi\t");
479
138
      MCInst_setOpcodePub(MI, PPC_INS_SLDI);
480
481
138
      printOperand(MI, 0, O);
482
138
      SStream_concat0(O, ", ");
483
138
      printOperand(MI, 1, O);
484
485
138
      if (SH > HEX_THRESHOLD)
486
70
        SStream_concat(O, ", 0x%x", (unsigned int)SH);
487
68
      else
488
68
        SStream_concat(O, ", %u", (unsigned int)SH);
489
490
138
      if (MI->csh->detail) {
491
138
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
492
493
138
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
494
138
        ppc->operands[ppc->op_count].imm = SH;
495
138
        ++ppc->op_count;
496
138
      }
497
498
499
138
      return;
500
138
    }
501
571
  }
502
503
  // dcbt[st] is printed manually here because:
504
  //  1. The assembly syntax is different between embedded and server targets
505
  //  2. We must print the short mnemonics for TH == 0 because the
506
  //     embedded/server syntax default will not be stable across assemblers
507
  //  The syntax for dcbt is:
508
  //    dcbt ra, rb, th [server]
509
  //    dcbt th, ra, rb [embedded]
510
  //  where th can be omitted when it is 0. dcbtst is the same.
511
138k
  if (opcode == PPC_DCBT || opcode == PPC_DCBTST) {
512
277
    unsigned char TH = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0));
513
514
277
    SStream_concat0(O, "dcbt");
515
277
    MCInst_setOpcodePub(MI, PPC_INS_DCBT);
516
517
277
    if (opcode == PPC_DCBTST) {
518
121
      SStream_concat0(O, "st");
519
121
      MCInst_setOpcodePub(MI, PPC_INS_DCBTST);
520
121
    }
521
522
277
    if (TH == 16) {
523
109
      SStream_concat0(O, "t");
524
109
      MCInst_setOpcodePub(MI, PPC_INS_DCBTSTT);
525
109
    }
526
527
277
    SStream_concat0(O, "\t");
528
529
277
    if (MI->csh->mode & CS_MODE_BOOKE && TH != 0 && TH != 16) {
530
0
      if (TH > HEX_THRESHOLD)
531
0
        SStream_concat(O, "0x%x, ", (unsigned int)TH);
532
0
      else
533
0
        SStream_concat(O, "%u, ", (unsigned int)TH);
534
535
0
      if (MI->csh->detail) {
536
0
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
537
538
0
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
539
0
        ppc->operands[ppc->op_count].imm = TH;
540
0
        ++ppc->op_count;
541
0
      }
542
0
    }
543
544
277
    printOperand(MI, 1, O);
545
277
    SStream_concat0(O, ", ");
546
277
    printOperand(MI, 2, O);
547
548
277
    if (!(MI->csh->mode & CS_MODE_BOOKE) && TH != 0 && TH != 16) {
549
128
      if (TH > HEX_THRESHOLD)
550
49
        SStream_concat(O, ", 0x%x", (unsigned int)TH);
551
79
      else
552
79
        SStream_concat(O, ", %u", (unsigned int)TH);
553
554
128
      if (MI->csh->detail) {
555
128
        cs_ppc *ppc = &MI->flat_insn->detail->ppc;
556
557
128
        ppc->operands[ppc->op_count].type = PPC_OP_IMM;
558
128
        ppc->operands[ppc->op_count].imm = TH;
559
128
        ++ppc->op_count;
560
128
      }
561
128
    }
562
563
277
    return;
564
277
  }
565
566
138k
  if (opcode == PPC_DCBF) {
567
539
    unsigned char L = (unsigned char)MCOperand_getImm(MCInst_getOperand(MI, 0));
568
569
539
    if (!L || L == 1 || L == 3) {
570
433
      SStream_concat0(O, "dcbf");
571
433
      MCInst_setOpcodePub(MI, PPC_INS_DCBF);
572
573
433
      if (L == 1 || L == 3) {
574
332
        SStream_concat0(O, "l");
575
332
        MCInst_setOpcodePub(MI, PPC_INS_DCBFL);
576
332
      }
577
578
433
      if (L == 3) {
579
259
        SStream_concat0(O, "p");
580
259
        MCInst_setOpcodePub(MI, PPC_INS_DCBFLP);
581
259
      }
582
583
433
      SStream_concat0(O, "\t");
584
585
433
      printOperand(MI, 1, O);
586
433
      SStream_concat0(O, ", ");
587
433
      printOperand(MI, 2, O);
588
589
433
      return;
590
433
    }
591
539
  }
592
593
137k
  if (opcode == PPC_B || opcode == PPC_BA || opcode == PPC_BL ||
594
135k
      opcode == PPC_BLA) {
595
2.76k
    int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0));
596
2.76k
    bd = SignExtend64(bd, 24);
597
2.76k
    MCOperand_setImm(MCInst_getOperand(MI, 0), bd);
598
2.76k
  }
599
600
137k
  if (opcode == PPC_gBC || opcode == PPC_gBCA || opcode == PPC_gBCL ||
601
130k
      opcode == PPC_gBCLA) {
602
8.37k
    int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 2));
603
8.37k
    bd = SignExtend64(bd, 14);
604
8.37k
    MCOperand_setImm(MCInst_getOperand(MI, 2), bd);
605
8.37k
  }
606
607
137k
  if (isBOCTRBranch(MCInst_getOpcode(MI))) {
608
2.46k
    if (MCOperand_isImm(MCInst_getOperand(MI,0))) {
609
2.37k
      int64_t bd = MCOperand_getImm(MCInst_getOperand(MI, 0));
610
2.37k
      bd = SignExtend64(bd, 14);
611
2.37k
      MCOperand_setImm(MCInst_getOperand(MI, 0), bd);
612
2.37k
    }
613
2.46k
  }
614
615
137k
  mnem = printAliasBcc(MI, O, Info);
616
137k
  if (!mnem)
617
128k
    mnem = printAliasInstr(MI, O, Info);
618
619
137k
  if (mnem != NULL) {
620
45.6k
    if (strlen(mnem) > 0) {
621
      // check to remove the last letter of ('.', '-', '+')
622
45.6k
      if (mnem[strlen(mnem) - 1] == '-' || mnem[strlen(mnem) - 1] == '+' || mnem[strlen(mnem) - 1] == '.')
623
4.13k
        mnem[strlen(mnem) - 1] = '\0';
624
625
45.6k
            MCInst_setOpcodePub(MI, PPC_map_insn(mnem));
626
627
45.6k
            if (MI->csh->detail) {
628
45.6k
        struct ppc_alias alias;
629
630
45.6k
        if (PPC_alias_insn(mnem, &alias)) {
631
2.11k
          MI->flat_insn->detail->ppc.bc = (ppc_bc)alias.cc;
632
2.11k
        }
633
45.6k
            }
634
45.6k
    }
635
636
45.6k
    cs_mem_free(mnem);
637
45.6k
  } else
638
91.9k
    printInstruction(MI, O);
639
640
137k
  const char *mnem_end = strchr(O->buffer, ' ');
641
137k
  unsigned mnem_len = 0;
642
137k
  if (mnem_end)
643
131k
    mnem_len = mnem_end - O->buffer;
644
137k
  if (!mnem_end || mnem_len >= sizeof(MI->flat_insn->mnemonic))
645
5.58k
    mnem_len = sizeof(MI->flat_insn->mnemonic) - 1;
646
647
137k
  memset(MI->flat_insn->mnemonic, 0, sizeof(MI->flat_insn->mnemonic));
648
137k
  memcpy(MI->flat_insn->mnemonic, O->buffer, mnem_len);
649
137k
}
650
651
// FIXME
652
enum ppc_bc_hint {
653
  PPC_BC_LT_MINUS = (0 << 5) | 14,
654
  PPC_BC_LE_MINUS = (1 << 5) |  6,
655
  PPC_BC_EQ_MINUS = (2 << 5) | 14,
656
  PPC_BC_GE_MINUS = (0 << 5) |  6,
657
  PPC_BC_GT_MINUS = (1 << 5) | 14,
658
  PPC_BC_NE_MINUS = (2 << 5) |  6,
659
  PPC_BC_UN_MINUS = (3 << 5) | 14,
660
  PPC_BC_NU_MINUS = (3 << 5) |  6,
661
  PPC_BC_LT_PLUS  = (0 << 5) | 15,
662
  PPC_BC_LE_PLUS  = (1 << 5) |  7,
663
  PPC_BC_EQ_PLUS  = (2 << 5) | 15,
664
  PPC_BC_GE_PLUS  = (0 << 5) |  7,
665
  PPC_BC_GT_PLUS  = (1 << 5) | 15,
666
  PPC_BC_NE_PLUS  = (2 << 5) |  7,
667
  PPC_BC_UN_PLUS  = (3 << 5) | 15,
668
  PPC_BC_NU_PLUS  = (3 << 5) |  7,
669
};
670
671
// FIXME
672
// normalize CC to remove _MINUS & _PLUS
673
static int cc_normalize(int cc)
674
0
{
675
0
  switch(cc) {
676
0
    default: return cc;
677
0
    case PPC_BC_LT_MINUS: return PPC_BC_LT;
678
0
    case PPC_BC_LE_MINUS: return PPC_BC_LE;
679
0
    case PPC_BC_EQ_MINUS: return PPC_BC_EQ;
680
0
    case PPC_BC_GE_MINUS: return PPC_BC_GE;
681
0
    case PPC_BC_GT_MINUS: return PPC_BC_GT;
682
0
    case PPC_BC_NE_MINUS: return PPC_BC_NE;
683
0
    case PPC_BC_UN_MINUS: return PPC_BC_UN;
684
0
    case PPC_BC_NU_MINUS: return PPC_BC_NU;
685
0
    case PPC_BC_LT_PLUS : return PPC_BC_LT;
686
0
    case PPC_BC_LE_PLUS : return PPC_BC_LE;
687
0
    case PPC_BC_EQ_PLUS : return PPC_BC_EQ;
688
0
    case PPC_BC_GE_PLUS : return PPC_BC_GE;
689
0
    case PPC_BC_GT_PLUS : return PPC_BC_GT;
690
0
    case PPC_BC_NE_PLUS : return PPC_BC_NE;
691
0
    case PPC_BC_UN_PLUS : return PPC_BC_UN;
692
0
    case PPC_BC_NU_PLUS : return PPC_BC_NU;
693
0
  }
694
0
}
695
696
static void printPredicateOperand(MCInst *MI, unsigned OpNo,
697
    SStream *O, const char *Modifier)
698
0
{
699
0
  unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
700
701
0
  MI->flat_insn->detail->ppc.bc = (ppc_bc)cc_normalize(Code);
702
703
0
  if (!strcmp(Modifier, "cc")) {
704
0
    switch ((ppc_predicate)Code) {
705
0
      default:  // unreachable
706
0
      case PPC_PRED_LT_MINUS:
707
0
      case PPC_PRED_LT_PLUS:
708
0
      case PPC_PRED_LT:
709
0
        SStream_concat0(O, "lt");
710
0
        return;
711
0
      case PPC_PRED_LE_MINUS:
712
0
      case PPC_PRED_LE_PLUS:
713
0
      case PPC_PRED_LE:
714
0
        SStream_concat0(O, "le");
715
0
        return;
716
0
      case PPC_PRED_EQ_MINUS:
717
0
      case PPC_PRED_EQ_PLUS:
718
0
      case PPC_PRED_EQ:
719
0
        SStream_concat0(O, "eq");
720
0
        return;
721
0
      case PPC_PRED_GE_MINUS:
722
0
      case PPC_PRED_GE_PLUS:
723
0
      case PPC_PRED_GE:
724
0
        SStream_concat0(O, "ge");
725
0
        return;
726
0
      case PPC_PRED_GT_MINUS:
727
0
      case PPC_PRED_GT_PLUS:
728
0
      case PPC_PRED_GT:
729
0
        SStream_concat0(O, "gt");
730
0
        return;
731
0
      case PPC_PRED_NE_MINUS:
732
0
      case PPC_PRED_NE_PLUS:
733
0
      case PPC_PRED_NE:
734
0
        SStream_concat0(O, "ne");
735
0
        return;
736
0
      case PPC_PRED_UN_MINUS:
737
0
      case PPC_PRED_UN_PLUS:
738
0
      case PPC_PRED_UN:
739
0
        SStream_concat0(O, "un");
740
0
        return;
741
0
      case PPC_PRED_NU_MINUS:
742
0
      case PPC_PRED_NU_PLUS:
743
0
      case PPC_PRED_NU:
744
0
        SStream_concat0(O, "nu");
745
0
        return;
746
0
      case PPC_PRED_BIT_SET:
747
0
      case PPC_PRED_BIT_UNSET:
748
        // llvm_unreachable("Invalid use of bit predicate code");
749
0
        SStream_concat0(O, "invalid-predicate");
750
0
        return;
751
0
    }
752
0
  }
753
754
0
  if (!strcmp(Modifier, "pm")) {
755
0
    switch ((ppc_predicate)Code) {
756
0
      case PPC_PRED_LT:
757
0
      case PPC_PRED_LE:
758
0
      case PPC_PRED_EQ:
759
0
      case PPC_PRED_GE:
760
0
      case PPC_PRED_GT:
761
0
      case PPC_PRED_NE:
762
0
      case PPC_PRED_UN:
763
0
      case PPC_PRED_NU:
764
0
        return;
765
0
      case PPC_PRED_LT_MINUS:
766
0
      case PPC_PRED_LE_MINUS:
767
0
      case PPC_PRED_EQ_MINUS:
768
0
      case PPC_PRED_GE_MINUS:
769
0
      case PPC_PRED_GT_MINUS:
770
0
      case PPC_PRED_NE_MINUS:
771
0
      case PPC_PRED_UN_MINUS:
772
0
      case PPC_PRED_NU_MINUS:
773
0
        SStream_concat0(O, "-");
774
0
        return;
775
0
      case PPC_PRED_LT_PLUS:
776
0
      case PPC_PRED_LE_PLUS:
777
0
      case PPC_PRED_EQ_PLUS:
778
0
      case PPC_PRED_GE_PLUS:
779
0
      case PPC_PRED_GT_PLUS:
780
0
      case PPC_PRED_NE_PLUS:
781
0
      case PPC_PRED_UN_PLUS:
782
0
      case PPC_PRED_NU_PLUS:
783
0
        SStream_concat0(O, "+");
784
0
        return;
785
0
      case PPC_PRED_BIT_SET:
786
0
      case PPC_PRED_BIT_UNSET:
787
        // llvm_unreachable("Invalid use of bit predicate code");
788
0
        SStream_concat0(O, "invalid-predicate");
789
0
        return;
790
0
      default:  // unreachable
791
0
        return;
792
0
    }
793
    // llvm_unreachable("Invalid predicate code");
794
0
  }
795
796
  //assert(StringRef(Modifier) == "reg" &&
797
  //    "Need to specify 'cc', 'pm' or 'reg' as predicate op modifier!");
798
0
  printOperand(MI, OpNo + 1, O);
799
0
}
800
801
static void printATBitsAsHint(MCInst *MI, unsigned OpNo, SStream *O)
802
0
{
803
0
  unsigned Code = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
804
805
0
  if (Code == 2) {
806
0
    SStream_concat0(O, "-");
807
0
  } else if (Code == 3) {
808
0
    SStream_concat0(O, "+");
809
0
  }
810
0
}
811
812
static void printU1ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
813
1.12k
{
814
1.12k
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
815
816
  // assert(Value <= 1 && "Invalid u1imm argument!");
817
818
1.12k
  printUInt32(O, Value);
819
820
1.12k
  if (MI->csh->detail) {
821
1.12k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
822
1.12k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
823
1.12k
    MI->flat_insn->detail->ppc.op_count++;
824
1.12k
  }
825
1.12k
}
826
827
static void printU2ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
828
1.99k
{
829
1.99k
  unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
830
  //assert(Value <= 3 && "Invalid u2imm argument!");
831
832
1.99k
  printUInt32(O, Value);
833
834
1.99k
  if (MI->csh->detail) {
835
1.99k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
836
1.99k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
837
1.99k
    MI->flat_insn->detail->ppc.op_count++;
838
1.99k
  }
839
1.99k
}
840
841
static void printU3ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
842
549
{
843
549
  unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
844
  //assert(Value <= 8 && "Invalid u3imm argument!");
845
846
549
  printUInt32(O, Value);
847
848
549
  if (MI->csh->detail) {
849
549
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
850
549
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
851
549
    MI->flat_insn->detail->ppc.op_count++;
852
549
  }
853
549
}
854
855
static void printU4ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
856
1.21k
{
857
1.21k
  unsigned int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
858
  //assert(Value <= 15 && "Invalid u4imm argument!");
859
860
1.21k
  printUInt32(O, Value);
861
862
1.21k
  if (MI->csh->detail) {
863
1.21k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
864
1.21k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
865
1.21k
    MI->flat_insn->detail->ppc.op_count++;
866
1.21k
  }
867
1.21k
}
868
869
static void printS5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
870
99
{
871
99
  int Value = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
872
99
  Value = SignExtend32(Value, 5);
873
874
99
  printInt32(O, Value);
875
876
99
  if (MI->csh->detail) {
877
99
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
878
99
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
879
99
    MI->flat_insn->detail->ppc.op_count++;
880
99
  }
881
99
}
882
883
static void printU5ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
884
20.2k
{
885
20.2k
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
886
887
  //assert(Value <= 31 && "Invalid u5imm argument!");
888
20.2k
  printUInt32(O, Value);
889
890
20.2k
  if (MI->csh->detail) {
891
20.2k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
892
20.2k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
893
20.2k
    MI->flat_insn->detail->ppc.op_count++;
894
20.2k
  }
895
20.2k
}
896
897
static void printU6ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
898
4.85k
{
899
4.85k
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
900
901
  //assert(Value <= 63 && "Invalid u6imm argument!");
902
4.85k
  printUInt32(O, Value);
903
904
4.85k
  if (MI->csh->detail) {
905
4.85k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
906
4.85k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
907
4.85k
    MI->flat_insn->detail->ppc.op_count++;
908
4.85k
  }
909
4.85k
}
910
911
static void printU7ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
912
186
{
913
186
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
914
915
  //assert(Value <= 127 && "Invalid u7imm argument!");
916
186
  printUInt32(O, Value);
917
918
186
  if (MI->csh->detail) {
919
186
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
920
186
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
921
186
    MI->flat_insn->detail->ppc.op_count++;
922
186
  }
923
186
}
924
925
// Operands of BUILD_VECTOR are signed and we use this to print operands
926
// of XXSPLTIB which are unsigned. So we simply truncate to 8 bits and
927
// print as unsigned.
928
static void printU8ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
929
107
{
930
107
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
931
932
107
  printUInt32(O, Value);
933
934
107
  if (MI->csh->detail) {
935
107
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
936
107
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
937
107
    MI->flat_insn->detail->ppc.op_count++;
938
107
  }
939
107
}
940
941
static void printU10ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
942
100
{
943
100
  unsigned int Value = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
944
945
  //assert(Value <= 1023 && "Invalid u10imm argument!");
946
100
  printUInt32(O, Value);
947
948
100
  if (MI->csh->detail) {
949
100
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
950
100
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
951
100
    MI->flat_insn->detail->ppc.op_count++;
952
100
  }
953
100
}
954
955
static void printS12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
956
0
{
957
0
  if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
958
0
    int Imm = (int)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
959
0
    Imm = SignExtend32(Imm, 12);
960
961
0
    printInt32(O, Imm);
962
963
0
    if (MI->csh->detail) {
964
0
      if (MI->csh->doing_mem) {
965
0
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm;
966
0
      } else {
967
0
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
968
0
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
969
0
                MI->flat_insn->detail->ppc.op_count++;
970
0
            }
971
0
    }
972
0
  } else
973
0
    printOperand(MI, OpNo, O);
974
0
}
975
976
static void printU12ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
977
1.05k
{
978
1.05k
  unsigned short Value = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
979
980
  // assert(Value <= 4095 && "Invalid u12imm argument!");
981
982
1.05k
  printUInt32(O, Value);
983
984
1.05k
  if (MI->csh->detail) {
985
1.05k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
986
1.05k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Value;
987
1.05k
    MI->flat_insn->detail->ppc.op_count++;
988
1.05k
  }
989
1.05k
}
990
991
static void printS16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
992
37.1k
{
993
37.1k
  if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
994
37.1k
    short Imm = (short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
995
37.1k
    printInt32(O, Imm);
996
997
37.1k
    if (MI->csh->detail) {
998
37.1k
      if (MI->csh->doing_mem) {
999
19.6k
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = Imm;
1000
19.6k
      } else {
1001
17.4k
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1002
17.4k
                MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
1003
17.4k
                MI->flat_insn->detail->ppc.op_count++;
1004
17.4k
            }
1005
37.1k
    }
1006
37.1k
  } else
1007
0
    printOperand(MI, OpNo, O);
1008
37.1k
}
1009
1010
static void printU16ImmOperand(MCInst *MI, unsigned OpNo, SStream *O)
1011
8.89k
{
1012
8.89k
  if (MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
1013
8.89k
    unsigned short Imm = (unsigned short)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
1014
8.89k
    printUInt32(O, Imm);
1015
1016
8.89k
    if (MI->csh->detail) {
1017
8.89k
      MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1018
8.89k
      MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = Imm;
1019
8.89k
      MI->flat_insn->detail->ppc.op_count++;
1020
8.89k
    }
1021
8.89k
  } else
1022
0
    printOperand(MI, OpNo, O);
1023
8.89k
}
1024
1025
static void printBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
1026
9.33k
{
1027
9.33k
  if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
1028
0
    printOperand(MI, OpNo, O);
1029
1030
0
    return;
1031
0
  }
1032
1033
  // Branches can take an immediate operand.  This is used by the branch
1034
  // selection pass to print .+8, an eight byte displacement from the PC.
1035
  // O << ".+";
1036
9.33k
  printAbsBranchOperand(MI, OpNo, O);
1037
9.33k
}
1038
1039
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O)
1040
13.2k
{
1041
13.2k
  int64_t imm;
1042
1043
13.2k
  if (!MCOperand_isImm(MCInst_getOperand(MI, OpNo))) {
1044
0
    printOperand(MI, OpNo, O);
1045
1046
0
    return;
1047
0
  }
1048
1049
13.2k
  imm = SignExtend32(MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4, 32);
1050
  //imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo)) * 4;
1051
1052
13.2k
  if (!PPC_abs_branch(MI->csh, MCInst_getOpcode(MI))) {
1053
6.12k
    imm += MI->address;
1054
6.12k
  }
1055
1056
13.2k
  printUInt64(O, imm);
1057
1058
13.2k
  if (MI->csh->detail) {
1059
13.2k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1060
13.2k
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
1061
13.2k
    MI->flat_insn->detail->ppc.op_count++;
1062
13.2k
  }
1063
13.2k
}
1064
1065
static void printcrbitm(MCInst *MI, unsigned OpNo, SStream *O)
1066
2.47k
{
1067
2.47k
  unsigned RegNo;
1068
2.47k
  unsigned CCReg = MCOperand_getReg(MCInst_getOperand(MI, OpNo));
1069
1070
2.47k
  switch (CCReg) {
1071
0
    default: // llvm_unreachable("Unknown CR register");
1072
342
    case PPC_CR0: RegNo = 0; break;
1073
212
    case PPC_CR1: RegNo = 1; break;
1074
126
    case PPC_CR2: RegNo = 2; break;
1075
147
    case PPC_CR3: RegNo = 3; break;
1076
123
    case PPC_CR4: RegNo = 4; break;
1077
135
    case PPC_CR5: RegNo = 5; break;
1078
217
    case PPC_CR6: RegNo = 6; break;
1079
1.17k
    case PPC_CR7: RegNo = 7; break;
1080
2.47k
  }
1081
1082
2.47k
  printUInt32(O, 0x80 >> RegNo);
1083
2.47k
}
1084
1085
static void printMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
1086
28.0k
{
1087
28.0k
  set_mem_access(MI, true);
1088
1089
28.0k
  printS16ImmOperand(MI, OpNo, O);
1090
1091
28.0k
  SStream_concat0(O, "(");
1092
1093
28.0k
  if (MCOperand_getReg(MCInst_getOperand(MI, OpNo + 1)) == PPC_R0)
1094
0
    SStream_concat0(O, "0");
1095
28.0k
  else
1096
28.0k
    printOperand(MI, OpNo + 1, O);
1097
1098
28.0k
  SStream_concat0(O, ")");
1099
1100
28.0k
  set_mem_access(MI, false);
1101
28.0k
}
1102
1103
static void printPSMemRegImm(MCInst *MI, unsigned OpNo, SStream *O)
1104
0
{
1105
0
  set_mem_access(MI, true);
1106
1107
0
  printS12ImmOperand(MI, OpNo, O);
1108
1109
0
  SStream_concat0(O, "(");
1110
0
  printOperand(MI, OpNo + 1, O);
1111
0
  SStream_concat0(O, ")");
1112
1113
0
  set_mem_access(MI, false);
1114
0
}
1115
1116
static void printMemRegReg(MCInst *MI, unsigned OpNo, SStream *O)
1117
6.13k
{
1118
  // When used as the base register, r0 reads constant zero rather than
1119
  // the value contained in the register.  For this reason, the darwin
1120
  // assembler requires that we print r0 as 0 (no r) when used as the base.
1121
6.13k
  if (MCOperand_getReg(MCInst_getOperand(MI, OpNo)) == PPC_R0)
1122
0
    SStream_concat0(O, "0");
1123
6.13k
  else
1124
6.13k
    printOperand(MI, OpNo, O);
1125
6.13k
  SStream_concat0(O, ", ");
1126
1127
6.13k
  printOperand(MI, OpNo + 1, O);
1128
6.13k
}
1129
1130
static void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O)
1131
0
{
1132
0
  set_mem_access(MI, true);
1133
  //printBranchOperand(MI, OpNo, O);
1134
1135
  // On PPC64, VariantKind is VK_None, but on PPC32, it's VK_PLT, and it must
1136
  // come at the _end_ of the expression.
1137
1138
0
  SStream_concat0(O, "(");
1139
0
  printOperand(MI, OpNo + 1, O);
1140
0
  SStream_concat0(O, ")");
1141
1142
0
  set_mem_access(MI, false);
1143
0
}
1144
1145
/// stripRegisterPrefix - This method strips the character prefix from a
1146
/// register name so that only the number is left.  Used by for linux asm.
1147
static char *stripRegisterPrefix(const char *RegName)
1148
0
{
1149
0
  switch (RegName[0]) {
1150
0
    case 'r':
1151
0
    case 'f':
1152
0
    case 'q': // for QPX
1153
0
    case 'v':
1154
0
      if (RegName[1] == 's')
1155
0
        return cs_strdup(RegName + 2);
1156
1157
0
      return cs_strdup(RegName + 1);
1158
0
    case 'c':
1159
0
      if (RegName[1] == 'r') {
1160
        // skip the first 2 letters "cr"
1161
0
        char *name = cs_strdup(RegName + 2);
1162
1163
        // also strip the last 2 letters
1164
0
        if(strlen(name) > 2)
1165
0
          name[strlen(name) - 2] = '\0';
1166
1167
0
        return name;
1168
0
      }
1169
0
  }
1170
1171
0
  return cs_strdup(RegName);
1172
0
}
1173
1174
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
1175
240k
{
1176
240k
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
1177
240k
  if (MCOperand_isReg(Op)) {
1178
231k
    unsigned reg = MCOperand_getReg(Op);
1179
231k
#ifndef CAPSTONE_DIET
1180
231k
    const char *RegName = getRegisterName(reg);
1181
1182
    // printf("reg = %u (%s)\n", reg, RegName);
1183
1184
    // convert internal register ID to public register ID
1185
231k
    reg = PPC_name_reg(RegName);
1186
1187
    // The linux and AIX assembler does not take register prefixes.
1188
231k
    if (MI->csh->syntax == CS_OPT_SYNTAX_NOREGNAME) {
1189
0
      char *name = stripRegisterPrefix(RegName);
1190
0
      SStream_concat0(O, name);
1191
0
      cs_mem_free(name);
1192
0
    } else
1193
231k
      SStream_concat0(O, RegName);
1194
231k
#endif
1195
1196
231k
    if (MI->csh->detail) {
1197
231k
      if (MI->csh->doing_mem) {
1198
19.6k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.base = reg;
1199
212k
      } else {
1200
212k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_REG;
1201
212k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].reg = reg;
1202
212k
        MI->flat_insn->detail->ppc.op_count++;
1203
212k
      }
1204
231k
    }
1205
1206
231k
    return;
1207
231k
  }
1208
1209
8.60k
  if (MCOperand_isImm(Op)) {
1210
8.60k
    int32_t imm = (int32_t)MCOperand_getImm(Op);
1211
8.60k
    printInt32(O, imm);
1212
1213
8.60k
    if (MI->csh->detail) {
1214
8.60k
      if (MI->csh->doing_mem) {
1215
0
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].mem.disp = (int32_t)imm;
1216
8.60k
      } else {
1217
8.60k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1218
8.60k
        MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = imm;
1219
8.60k
        MI->flat_insn->detail->ppc.op_count++;
1220
8.60k
      }
1221
8.60k
    }
1222
8.60k
  }
1223
8.60k
}
1224
1225
static void op_addImm(MCInst *MI, int v)
1226
272
{
1227
272
  if (MI->csh->detail) {
1228
272
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].type = PPC_OP_IMM;
1229
272
    MI->flat_insn->detail->ppc.operands[MI->flat_insn->detail->ppc.op_count].imm = v;
1230
272
    MI->flat_insn->detail->ppc.op_count++;
1231
272
  }
1232
272
}
1233
1234
#define PRINT_ALIAS_INSTR
1235
#include "PPCGenRegisterName.inc"
1236
#include "PPCGenAsmWriter.inc"
1237
1238
#endif