/src/capstonenext/arch/Mips/MipsMapping.c

Source
/* Capstone Disassembly Engine */
/* By Giovanni Dante Grazioli, deroad <wargio@libero.it>, 2024 */

#ifdef CAPSTONE_HAS_MIPS

#include <stdio.h>
#include <string.h>

#include <capstone/capstone.h>
#include <capstone/mips.h>

#include "../../Mapping.h"
#include "../../MCDisassembler.h"
#include "../../cs_priv.h"
#include "../../cs_simple_types.h"

#include "MipsMapping.h"
#include "MipsLinkage.h"
#include "MipsDisassembler.h"

#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "MipsGenRegisterInfo.inc"

#define GET_INSTRINFO_ENUM
#include "MipsGenInstrInfo.inc"

void Mips_init_mri(MCRegisterInfo *MRI)
{
  MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, sizeof(MipsRegDesc),
            0, 0, MipsMCRegisterClasses,
            ARR_SIZE(MipsMCRegisterClasses), 0, 0,
            MipsRegDiffLists, 0,
            MipsSubRegIdxLists,
            ARR_SIZE(MipsSubRegIdxLists), 0);
}

const char *Mips_reg_name(csh handle, unsigned int reg)
{
  int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
  return Mips_LLVM_getRegisterName(reg,
           syntax_opt & CS_OPT_SYNTAX_NOREGNAME);
}

void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
  // Not used by Mips. Information is set after disassembly.
}

static const char *const insn_name_maps[] = {
#include "MipsGenCSMappingInsnName.inc"
};

#ifndef CAPSTONE_DIET
static const name_map insn_alias_mnem_map[] = {
#include "MipsGenCSAliasMnemMap.inc"
  // The followings aliases are not generated by LLVM table gen.
  { MIPS_INS_ALIAS_B, "b" }, // beq
  { MIPS_INS_ALIAS_BEQZ, "beqz" }, // beq
  { MIPS_INS_ALIAS_BNEZ, "bnez" }, // bne
  { MIPS_INS_ALIAS_LI, "li" }, // addiu
  { MIPS_INS_ALIAS_END, NULL },
};
#endif
const char *Mips_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
  if (id < MIPS_INS_ALIAS_END && id > MIPS_INS_ALIAS_BEGIN) {
    if (id - MIPS_INS_ALIAS_BEGIN >= ARR_SIZE(insn_alias_mnem_map))
      return NULL;

    return insn_alias_mnem_map[id - MIPS_INS_ALIAS_BEGIN - 1].name;
  }
  if (id >= MIPS_INS_ENDING)
    return NULL;

  if (id < ARR_SIZE(insn_name_maps))
    return insn_name_maps[id];
  // not found
  return NULL;
#else
  return NULL;
#endif
}

#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
  { MIPS_GRP_INVALID, NULL },

  { MIPS_GRP_JUMP, "jump" },
  { MIPS_GRP_CALL, "call" },
  { MIPS_GRP_RET, "return" },
  { MIPS_GRP_INT, "int" },
  { MIPS_GRP_IRET, "iret" },
  { MIPS_GRP_PRIVILEGE, "privilege" },
  { MIPS_GRP_BRANCH_RELATIVE, "branch_relative" },

// architecture-specific groups
#include "MipsGenCSFeatureName.inc"
};
#endif

const char *Mips_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
  return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
  return NULL;
#endif
}

const insn_map mips_insns[] = {
#include "MipsGenCSMappingInsn.inc"
};

void Mips_reg_access(const cs_insn *insn, cs_regs regs_read,
         uint8_t *regs_read_count, cs_regs regs_write,
         uint8_t *regs_write_count)
{
  uint8_t i;
  uint8_t read_count, write_count;
  cs_mips *mips = &(insn->detail->mips);

  read_count = insn->detail->regs_read_count;
  write_count = insn->detail->regs_write_count;

  // implicit registers
  memcpy(regs_read, insn->detail->regs_read,
         read_count * sizeof(insn->detail->regs_read[0]));
  memcpy(regs_write, insn->detail->regs_write,
         write_count * sizeof(insn->detail->regs_write[0]));

  // explicit registers
  for (i = 0; i < mips->op_count; i++) {
    cs_mips_op *op = &(mips->operands[i]);
    switch ((int)op->type) {
    case MIPS_OP_REG:
      if ((op->access & CS_AC_READ) &&
          !arr_exist(regs_read, read_count, op->reg)) {
        regs_read[read_count] = (uint16_t)op->reg;
        read_count++;
      }
      if ((op->access & CS_AC_WRITE) &&
          !arr_exist(regs_write, write_count, op->reg)) {
        regs_write[write_count] = (uint16_t)op->reg;
        write_count++;
      }
      break;
    case MIPS_OP_MEM:
      // registers appeared in memory references always being read
      if ((op->mem.base != MIPS_REG_INVALID) &&
          !arr_exist(regs_read, read_count, op->mem.base)) {
        regs_read[read_count] = (uint16_t)op->mem.base;
        read_count++;
      }
      if ((insn->detail->writeback) &&
          (op->mem.base != MIPS_REG_INVALID) &&
          !arr_exist(regs_write, write_count, op->mem.base)) {
        regs_write[write_count] =
          (uint16_t)op->mem.base;
        write_count++;
      }
    default:
      break;
    }
  }

  *regs_read_count = read_count;
  *regs_write_count = write_count;
}

void Mips_set_instr_map_data(MCInst *MI)
{
  // Fixes for missing groups.
  if (MCInst_getOpcode(MI) == Mips_JR) {
    unsigned Reg = MCInst_getOpVal(MI, 0);
    switch (Reg) {
    case MIPS_REG_RA:
    case MIPS_REG_RA_64:
      add_group(MI, MIPS_GRP_RET);
      break;
    }
  }

  map_cs_id(MI, mips_insns, ARR_SIZE(mips_insns));
  map_implicit_reads(MI, mips_insns);
  map_implicit_writes(MI, mips_insns);
  map_groups(MI, mips_insns);
}

bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len,
       MCInst *instr, uint16_t *size, uint64_t address,
       void *info)
{
  uint64_t size64;
  Mips_init_cs_detail(instr);
  instr->MRI = (MCRegisterInfo *)info;
  map_set_fill_detail_ops(instr, true);

  DecodeStatus Result = Mips_LLVM_getInstruction(instr, &size64, code,
                   code_len, address, info);
  *size = size64;
  if (Result != MCDisassembler_Fail) {
    Mips_set_instr_map_data(instr);
  }
  if (Result == MCDisassembler_SoftFail) {
    MCInst_setSoftFail(instr);
  }
  return Result != MCDisassembler_Fail;
}

void Mips_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
{
  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
  MI->MRI = MRI;

  Mips_LLVM_printInst(MI, MI->address, O);
#ifndef CAPSTONE_DIET
  map_set_alias_id(MI, O, insn_alias_mnem_map,
       ARR_SIZE(insn_alias_mnem_map));
#endif
}

static void Mips_setup_op(cs_mips_op *op)
{
  memset(op, 0, sizeof(cs_mips_op));
  op->type = MIPS_OP_INVALID;
}

void Mips_init_cs_detail(MCInst *MI)
{
  if (detail_is_set(MI)) {
    unsigned int i;

    memset(get_detail(MI), 0,
           offsetof(cs_detail, mips) + sizeof(cs_mips));

    for (i = 0; i < ARR_SIZE(Mips_get_detail(MI)->operands); i++)
      Mips_setup_op(&Mips_get_detail(MI)->operands[i]);
  }
}

static const map_insn_ops insn_operands[] = {
#include "MipsGenCSMappingInsnOp.inc"
};

static void Mips_set_detail_op_mem_reg(MCInst *MI, unsigned OpNum, mips_reg Reg)
{
  Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
  Mips_get_detail_op(MI, 0)->mem.base = Reg;
  Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
}

static void Mips_set_detail_op_mem_disp(MCInst *MI, unsigned OpNum, int64_t Imm)
{
  Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
  Mips_get_detail_op(MI, 0)->mem.disp = Imm;
  Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
}

static void Mips_set_detail_op_imm(MCInst *MI, unsigned OpNum, int64_t Imm)
{
  if (!detail_is_set(MI))
    return;

  if (doing_mem(MI)) {
    Mips_set_detail_op_mem_disp(MI, OpNum, Imm);
    return;
  }

  Mips_get_detail_op(MI, 0)->type = MIPS_OP_IMM;
  Mips_get_detail_op(MI, 0)->imm = Imm;
  Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
  Mips_inc_op_count(MI);
}

static void Mips_set_detail_op_uimm(MCInst *MI, unsigned OpNum, uint64_t Imm)
{
  if (!detail_is_set(MI))
    return;

  if (doing_mem(MI)) {
    Mips_set_detail_op_mem_disp(MI, OpNum, Imm);
    return;
  }

  Mips_get_detail_op(MI, 0)->type = MIPS_OP_IMM;
  Mips_get_detail_op(MI, 0)->uimm = Imm;
  Mips_get_detail_op(MI, 0)->is_unsigned = true;
  Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
  Mips_inc_op_count(MI);
}

static void Mips_set_detail_op_reg(MCInst *MI, unsigned OpNum, mips_reg Reg,
           bool is_reglist)
{
  if (!detail_is_set(MI))
    return;

  if (doing_mem(MI)) {
    Mips_set_detail_op_mem_reg(MI, OpNum, Reg);
    return;
  }

  CS_ASSERT(is_reglist ||
      (map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
  Mips_get_detail_op(MI, 0)->type = MIPS_OP_REG;
  Mips_get_detail_op(MI, 0)->reg = Reg;
  Mips_get_detail_op(MI, 0)->is_reglist = is_reglist;
  Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
  Mips_inc_op_count(MI);
}

static void Mips_set_detail_op_operand(MCInst *MI, unsigned OpNum)
{
  cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
  int64_t value = MCInst_getOpVal(MI, OpNum);
  if (op_type == CS_OP_IMM) {
    Mips_set_detail_op_imm(MI, OpNum, value);
  } else if (op_type == CS_OP_REG) {
    Mips_set_detail_op_reg(MI, OpNum, value, false);
  } else {
    // Register list which ends with a memory operand
    // Gives very large MCInst operand numbers but don't
    // have the respective Capstone type in the mapping table.
    if (MCOperand_isImm(MCInst_getOperand(MI, OpNum))) {
      Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
      Mips_get_detail_op(MI, 0)->mem.disp = value;
    } else if (MCOperand_isReg(MCInst_getOperand(MI, OpNum))) {
      Mips_get_detail_op(MI, 0)->mem.base = value;
    } else {
      printf("Operand type %d not handled!\n", op_type);
    }
  }
}

static void Mips_set_detail_op_jump(MCInst *MI, unsigned OpNum)
{
  cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
  if (op_type == CS_OP_IMM) {
    uint64_t Base = MI->address & ~0x0fffffffull;
    uint64_t Target = Base | (uint64_t)MCInst_getOpVal(MI, OpNum);
    Mips_set_detail_op_uimm(MI, OpNum, Target);
  } else if (op_type == CS_OP_REG) {
    Mips_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum),
               false);
  } else
    printf("Operand type %d not handled!\n", op_type);
}

static void Mips_set_detail_op_branch(MCInst *MI, unsigned OpNum)
{
  cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
  if (op_type == CS_OP_IMM) {
    uint64_t Target = MI->address + MCInst_getOpVal(MI, OpNum);
    Mips_set_detail_op_uimm(MI, OpNum, Target);
  } else if (op_type == CS_OP_REG) {
    Mips_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum),
               false);
  } else
    printf("Operand type %d not handled!\n", op_type);
}

static void Mips_set_detail_op_unsigned(MCInst *MI, unsigned OpNum)
{
  Mips_set_detail_op_uimm(MI, OpNum, MCInst_getOpVal(MI, OpNum));
}

static void Mips_set_detail_op_unsigned_offset(MCInst *MI, unsigned OpNum,
                 unsigned Bits, uint64_t Offset)
{
  uint64_t Imm = MCInst_getOpVal(MI, OpNum);
  Imm -= Offset;
  Imm &= (((uint64_t)1) << Bits) - 1;
  Imm += Offset;
  Mips_set_detail_op_uimm(MI, OpNum, Imm);
}

static void Mips_set_detail_op_mem_nanomips(MCInst *MI, unsigned OpNum)
{
  CS_ASSERT(doing_mem(MI));

  MCOperand *Op = MCInst_getOperand(MI, OpNum);
  Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
  // Base is a register, but nanoMips uses the Imm value as register.
  Mips_get_detail_op(MI, 0)->mem.base = MCOperand_getImm(Op);
  Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
}

static void Mips_set_detail_op_reglist(MCInst *MI, unsigned OpNum,
               bool isNanoMips)
{
  if (isNanoMips) {
    for (unsigned i = OpNum; i < MCInst_getNumOperands(MI); i++) {
      Mips_set_detail_op_reg(MI, i, MCInst_getOpVal(MI, i),
                 true);
    }
    return;
  }
  // -2 because register List is always first operand of instruction
  // and it is always followed by memory operand (base + offset).
  for (unsigned i = OpNum, e = MCInst_getNumOperands(MI) - 2; i != e;
       ++i) {
    Mips_set_detail_op_reg(MI, i, MCInst_getOpVal(MI, i), true);
  }
}

static void Mips_set_detail_op_unsigned_address(MCInst *MI, unsigned OpNum)
{
  uint64_t Target = MI->address + (uint64_t)MCInst_getOpVal(MI, OpNum);
  Mips_set_detail_op_imm(MI, OpNum, Target);
}

void Mips_add_cs_detail_0(MCInst *MI, mips_op_group op_group, size_t OpNum)
{
  if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
    return;

  switch (op_group) {
  default:
    printf("Operand group %d not handled!\n", op_group);
    return;
  case Mips_OP_GROUP_MemOperand:
    // this is only used by nanoMips.
    return Mips_set_detail_op_mem_nanomips(MI, OpNum);
  case Mips_OP_GROUP_BranchOperand:
    return Mips_set_detail_op_branch(MI, OpNum);
  case Mips_OP_GROUP_JumpOperand:
    return Mips_set_detail_op_jump(MI, OpNum);
  case Mips_OP_GROUP_Operand:
    return Mips_set_detail_op_operand(MI, OpNum);
  case Mips_OP_GROUP_UImm_1_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 1, 0);
  case Mips_OP_GROUP_UImm_2_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 2, 0);
  case Mips_OP_GROUP_UImm_3_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 3, 0);
  case Mips_OP_GROUP_UImm_32_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 32, 0);
  case Mips_OP_GROUP_UImm_16_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 16, 0);
  case Mips_OP_GROUP_UImm_8_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 8, 0);
  case Mips_OP_GROUP_UImm_5_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 0);
  case Mips_OP_GROUP_UImm_6_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 0);
  case Mips_OP_GROUP_UImm_4_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 4, 0);
  case Mips_OP_GROUP_UImm_7_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 7, 0);
  case Mips_OP_GROUP_UImm_10_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 10, 0);
  case Mips_OP_GROUP_UImm_6_1:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 1);
  case Mips_OP_GROUP_UImm_5_1:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 1);
  case Mips_OP_GROUP_UImm_5_33:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 33);
  case Mips_OP_GROUP_UImm_5_32:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 32);
  case Mips_OP_GROUP_UImm_6_2:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 2);
  case Mips_OP_GROUP_UImm_2_1:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 2, 1);
  case Mips_OP_GROUP_UImm_0_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 0, 0);
  case Mips_OP_GROUP_UImm_26_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 26, 0);
  case Mips_OP_GROUP_UImm_12_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 12, 0);
  case Mips_OP_GROUP_UImm_20_0:
    return Mips_set_detail_op_unsigned_offset(MI, OpNum, 20, 0);
  case Mips_OP_GROUP_RegisterList:
    return Mips_set_detail_op_reglist(MI, OpNum, false);
  case Mips_OP_GROUP_NanoMipsRegisterList:
    return Mips_set_detail_op_reglist(MI, OpNum, true);
  case Mips_OP_GROUP_PCRel:
    /* fall-thru */
  case Mips_OP_GROUP_Hi20PCRel:
    return Mips_set_detail_op_unsigned_address(MI, OpNum);
  case Mips_OP_GROUP_Hi20:
    return Mips_set_detail_op_unsigned(MI, OpNum);
  }
}

void Mips_set_mem_access(MCInst *MI, bool status)
{
  if (!detail_is_set(MI))
    return;
  set_doing_mem(MI, status);
  if (status) {
    if (Mips_get_detail(MI)->op_count > 0 &&
        Mips_get_detail_op(MI, -1)->type == MIPS_OP_MEM &&
        Mips_get_detail_op(MI, -1)->mem.disp == 0) {
      // Previous memory operand not done yet. Select it.
      Mips_dec_op_count(MI);
      return;
    }

    // Init a new one.
    Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
    Mips_get_detail_op(MI, 0)->mem.base = MIPS_REG_INVALID;
    Mips_get_detail_op(MI, 0)->mem.disp = 0;

#ifndef CAPSTONE_DIET
    uint8_t access =
      map_get_op_access(MI, Mips_get_detail(MI)->op_count);
    Mips_get_detail_op(MI, 0)->access = access;
#endif
  } else {
    // done, select the next operand slot
    Mips_inc_op_count(MI);
  }
}

#endif

Coverage Report

Created: 2026-08-31 06:58

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* By Giovanni Dante Grazioli, deroad <wargio@libero.it>, 2024 */
3
4		#ifdef CAPSTONE_HAS_MIPS
5
6		#include <stdio.h>
7		#include <string.h>
8
9		#include <capstone/capstone.h>
10		#include <capstone/mips.h>
11
12		#include "../../Mapping.h"
13		#include "../../MCDisassembler.h"
14		#include "../../cs_priv.h"
15		#include "../../cs_simple_types.h"
16
17		#include "MipsMapping.h"
18		#include "MipsLinkage.h"
19		#include "MipsDisassembler.h"
20
21		#define GET_REGINFO_ENUM
22		#define GET_REGINFO_MC_DESC
23		#include "MipsGenRegisterInfo.inc"
24
25		#define GET_INSTRINFO_ENUM
26		#include "MipsGenInstrInfo.inc"
27
28		void Mips_init_mri(MCRegisterInfo *MRI)
29	3.69k	{
30	3.69k	MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, sizeof(MipsRegDesc),
31	3.69k	0, 0, MipsMCRegisterClasses,
32	3.69k	ARR_SIZE(MipsMCRegisterClasses), 0, 0,
33	3.69k	MipsRegDiffLists, 0,
34	3.69k	MipsSubRegIdxLists,
35	3.69k	ARR_SIZE(MipsSubRegIdxLists), 0);
36	3.69k	}
37
38		const char *Mips_reg_name(csh handle, unsigned int reg)
39	35.8k	{
40	35.8k	int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
41	35.8k	return Mips_LLVM_getRegisterName(reg,
42	35.8k	syntax_opt & CS_OPT_SYNTAX_NOREGNAME);
43	35.8k	}
44
45		void Mips_get_insn_id(cs_struct h, cs_insn insn, unsigned int id)
46	153k	{
47		// Not used by Mips. Information is set after disassembly.
48	153k	}
49
50		static const char *const insn_name_maps[] = {
51		#include "MipsGenCSMappingInsnName.inc"
52		};
53
54		#ifndef CAPSTONE_DIET
55		static const name_map insn_alias_mnem_map[] = {
56		#include "MipsGenCSAliasMnemMap.inc"
57		// The followings aliases are not generated by LLVM table gen.
58		{ MIPS_INS_ALIAS_B, "b" }, // beq
59		{ MIPS_INS_ALIAS_BEQZ, "beqz" }, // beq
60		{ MIPS_INS_ALIAS_BNEZ, "bnez" }, // bne
61		{ MIPS_INS_ALIAS_LI, "li" }, // addiu
62		{ MIPS_INS_ALIAS_END, NULL },
63		};
64		#endif
65		const char *Mips_insn_name(csh handle, unsigned int id)
66	153k	{
67	153k	#ifndef CAPSTONE_DIET
68	153k	if (id < MIPS_INS_ALIAS_END && id > MIPS_INS_ALIAS_BEGIN) {
69	0	if (id - MIPS_INS_ALIAS_BEGIN >= ARR_SIZE(insn_alias_mnem_map))
70	0	return NULL;
71
72	0	return insn_alias_mnem_map[id - MIPS_INS_ALIAS_BEGIN - 1].name;
73	0	}
74	153k	if (id >= MIPS_INS_ENDING)
75	0	return NULL;
76
77	153k	if (id < ARR_SIZE(insn_name_maps))
78	153k	return insn_name_maps[id];
79		// not found
80	0	return NULL;
81		#else
82		return NULL;
83		#endif
84	153k	}
85
86		#ifndef CAPSTONE_DIET
87		static const name_map group_name_maps[] = {
88		{ MIPS_GRP_INVALID, NULL },
89
90		{ MIPS_GRP_JUMP, "jump" },
91		{ MIPS_GRP_CALL, "call" },
92		{ MIPS_GRP_RET, "return" },
93		{ MIPS_GRP_INT, "int" },
94		{ MIPS_GRP_IRET, "iret" },
95		{ MIPS_GRP_PRIVILEGE, "privilege" },
96		{ MIPS_GRP_BRANCH_RELATIVE, "branch_relative" },
97
98		// architecture-specific groups
99		#include "MipsGenCSFeatureName.inc"
100		};
101		#endif
102
103		const char *Mips_group_name(csh handle, unsigned int id)
104	710k	{
105	710k	#ifndef CAPSTONE_DIET
106	710k	return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
107		#else
108		return NULL;
109		#endif
110	710k	}
111
112		const insn_map mips_insns[] = {
113		#include "MipsGenCSMappingInsn.inc"
114		};
115
116		void Mips_reg_access(const cs_insn *insn, cs_regs regs_read,
117		uint8_t *regs_read_count, cs_regs regs_write,
118		uint8_t *regs_write_count)
119	0	{
120	0	uint8_t i;
121	0	uint8_t read_count, write_count;
122	0	cs_mips *mips = &(insn->detail->mips);
123
124	0	read_count = insn->detail->regs_read_count;
125	0	write_count = insn->detail->regs_write_count;
126
127		// implicit registers
128	0	memcpy(regs_read, insn->detail->regs_read,
129	0	read_count * sizeof(insn->detail->regs_read[0]));
130	0	memcpy(regs_write, insn->detail->regs_write,
131	0	write_count * sizeof(insn->detail->regs_write[0]));
132
133		// explicit registers
134	0	for (i = 0; i < mips->op_count; i++) {
135	0	cs_mips_op *op = &(mips->operands[i]);
136	0	switch ((int)op->type) {
137	0	case MIPS_OP_REG:
138	0	if ((op->access & CS_AC_READ) &&
139	0	!arr_exist(regs_read, read_count, op->reg)) {
140	0	regs_read[read_count] = (uint16_t)op->reg;
141	0	read_count++;
142	0	}
143	0	if ((op->access & CS_AC_WRITE) &&
144	0	!arr_exist(regs_write, write_count, op->reg)) {
145	0	regs_write[write_count] = (uint16_t)op->reg;
146	0	write_count++;
147	0	}
148	0	break;
149	0	case MIPS_OP_MEM:
150		// registers appeared in memory references always being read
151	0	if ((op->mem.base != MIPS_REG_INVALID) &&
152	0	!arr_exist(regs_read, read_count, op->mem.base)) {
153	0	regs_read[read_count] = (uint16_t)op->mem.base;
154	0	read_count++;
155	0	}
156	0	if ((insn->detail->writeback) &&
157	0	(op->mem.base != MIPS_REG_INVALID) &&
158	0	!arr_exist(regs_write, write_count, op->mem.base)) {
159	0	regs_write[write_count] =
160	0	(uint16_t)op->mem.base;
161	0	write_count++;
162	0	}
163	0	default:
164	0	break;
165	0	}
166	0	}
167
168	0	*regs_read_count = read_count;
169	0	*regs_write_count = write_count;
170	0	}
171
172		void Mips_set_instr_map_data(MCInst *MI)
173	153k	{
174		// Fixes for missing groups.
175	153k	if (MCInst_getOpcode(MI) == Mips_JR) {
176	355	unsigned Reg = MCInst_getOpVal(MI, 0);
177	355	switch (Reg) {
178	235	case MIPS_REG_RA:
179	235	case MIPS_REG_RA_64:
180	235	add_group(MI, MIPS_GRP_RET);
181	235	break;
182	355	}
183	355	}
184
185	153k	map_cs_id(MI, mips_insns, ARR_SIZE(mips_insns));
186	153k	map_implicit_reads(MI, mips_insns);
187	153k	map_implicit_writes(MI, mips_insns);
188	153k	map_groups(MI, mips_insns);
189	153k	}
190
191		bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len,
192		MCInst instr, uint16_t size, uint64_t address,
193		void *info)
194	156k	{
195	156k	uint64_t size64;
196	156k	Mips_init_cs_detail(instr);
197	156k	instr->MRI = (MCRegisterInfo *)info;
198	156k	map_set_fill_detail_ops(instr, true);
199
200	156k	DecodeStatus Result = Mips_LLVM_getInstruction(instr, &size64, code,
201	156k	code_len, address, info);
202	156k	*size = size64;
203	156k	if (Result != MCDisassembler_Fail) {
204	153k	Mips_set_instr_map_data(instr);
205	153k	}
206	156k	if (Result == MCDisassembler_SoftFail) {
207	0	MCInst_setSoftFail(instr);
208	0	}
209	156k	return Result != MCDisassembler_Fail;
210	156k	}
211
212		void Mips_printer(MCInst MI, SStream O, void * /* MCRegisterInfo* */ info)
213	153k	{
214	153k	MCRegisterInfo MRI = (MCRegisterInfo )info;
215	153k	MI->MRI = MRI;
216
217	153k	Mips_LLVM_printInst(MI, MI->address, O);
218	153k	#ifndef CAPSTONE_DIET
219	153k	map_set_alias_id(MI, O, insn_alias_mnem_map,
220	153k	ARR_SIZE(insn_alias_mnem_map));
221	153k	#endif
222	153k	}
223
224		static void Mips_setup_op(cs_mips_op *op)
225	2.50M	{
226	2.50M	memset(op, 0, sizeof(cs_mips_op));
227	2.50M	op->type = MIPS_OP_INVALID;
228	2.50M	}
229
230		void Mips_init_cs_detail(MCInst *MI)
231	156k	{
232	156k	if (detail_is_set(MI)) {
233	156k	unsigned int i;
234
235	156k	memset(get_detail(MI), 0,
236	156k	offsetof(cs_detail, mips) + sizeof(cs_mips));
237
238	2.66M	for (i = 0; i < ARR_SIZE(Mips_get_detail(MI)->operands); i++)
239	2.50M	Mips_setup_op(&Mips_get_detail(MI)->operands[i]);
240	156k	}
241	156k	}
242
243		static const map_insn_ops insn_operands[] = {
244		#include "MipsGenCSMappingInsnOp.inc"
245		};
246
247		static void Mips_set_detail_op_mem_reg(MCInst *MI, unsigned OpNum, mips_reg Reg)
248	41.8k	{
249	41.8k	Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
250	41.8k	Mips_get_detail_op(MI, 0)->mem.base = Reg;
251	41.8k	Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
252	41.8k	}
253
254		static void Mips_set_detail_op_mem_disp(MCInst *MI, unsigned OpNum, int64_t Imm)
255	42.4k	{
256	42.4k	Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
257	42.4k	Mips_get_detail_op(MI, 0)->mem.disp = Imm;
258	42.4k	Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
259	42.4k	}
260
261		static void Mips_set_detail_op_imm(MCInst *MI, unsigned OpNum, int64_t Imm)
262	65.9k	{
263	65.9k	if (!detail_is_set(MI))
264	0	return;
265
266	65.9k	if (doing_mem(MI)) {
267	42.4k	Mips_set_detail_op_mem_disp(MI, OpNum, Imm);
268	42.4k	return;
269	42.4k	}
270
271	23.4k	Mips_get_detail_op(MI, 0)->type = MIPS_OP_IMM;
272	23.4k	Mips_get_detail_op(MI, 0)->imm = Imm;
273	23.4k	Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
274	23.4k	Mips_inc_op_count(MI);
275	23.4k	}
276
277		static void Mips_set_detail_op_uimm(MCInst *MI, unsigned OpNum, uint64_t Imm)
278	52.5k	{
279	52.5k	if (!detail_is_set(MI))
280	0	return;
281
282	52.5k	if (doing_mem(MI)) {
283	0	Mips_set_detail_op_mem_disp(MI, OpNum, Imm);
284	0	return;
285	0	}
286
287	52.5k	Mips_get_detail_op(MI, 0)->type = MIPS_OP_IMM;
288	52.5k	Mips_get_detail_op(MI, 0)->uimm = Imm;
289	52.5k	Mips_get_detail_op(MI, 0)->is_unsigned = true;
290	52.5k	Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
291	52.5k	Mips_inc_op_count(MI);
292	52.5k	}
293
294		static void Mips_set_detail_op_reg(MCInst *MI, unsigned OpNum, mips_reg Reg,
295		bool is_reglist)
296	281k	{
297	281k	if (!detail_is_set(MI))
298	0	return;
299
300	281k	if (doing_mem(MI)) {
301	41.8k	Mips_set_detail_op_mem_reg(MI, OpNum, Reg);
302	41.8k	return;
303	41.8k	}
304
305	239k	CS_ASSERT(is_reglist \|\|
306	239k	(map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
307	239k	Mips_get_detail_op(MI, 0)->type = MIPS_OP_REG;
308	239k	Mips_get_detail_op(MI, 0)->reg = Reg;
309	239k	Mips_get_detail_op(MI, 0)->is_reglist = is_reglist;
310	239k	Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
311	239k	Mips_inc_op_count(MI);
312	239k	}
313
314		static void Mips_set_detail_op_operand(MCInst *MI, unsigned OpNum)
315	343k	{
316	343k	cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
317	343k	int64_t value = MCInst_getOpVal(MI, OpNum);
318	343k	if (op_type == CS_OP_IMM) {
319	65.9k	Mips_set_detail_op_imm(MI, OpNum, value);
320	278k	} else if (op_type == CS_OP_REG) {
321	274k	Mips_set_detail_op_reg(MI, OpNum, value, false);
322	274k	} else {
323		// Register list which ends with a memory operand
324		// Gives very large MCInst operand numbers but don't
325		// have the respective Capstone type in the mapping table.
326	3.13k	if (MCOperand_isImm(MCInst_getOperand(MI, OpNum))) {
327	1.85k	Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
328	1.85k	Mips_get_detail_op(MI, 0)->mem.disp = value;
329	1.85k	} else if (MCOperand_isReg(MCInst_getOperand(MI, OpNum))) {
330	1.28k	Mips_get_detail_op(MI, 0)->mem.base = value;
331	1.28k	} else {
332	0	printf("Operand type %d not handled!\n", op_type);
333	0	}
334	3.13k	}
335	343k	}
336
337		static void Mips_set_detail_op_jump(MCInst *MI, unsigned OpNum)
338	5.16k	{
339	5.16k	cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
340	5.16k	if (op_type == CS_OP_IMM) {
341	5.16k	uint64_t Base = MI->address & ~0x0fffffffull;
342	5.16k	uint64_t Target = Base \| (uint64_t)MCInst_getOpVal(MI, OpNum);
343	5.16k	Mips_set_detail_op_uimm(MI, OpNum, Target);
344	5.16k	} else if (op_type == CS_OP_REG) {
345	0	Mips_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum),
346	0	false);
347	0	} else
348	0	printf("Operand type %d not handled!\n", op_type);
349	5.16k	}
350
351		static void Mips_set_detail_op_branch(MCInst *MI, unsigned OpNum)
352	26.1k	{
353	26.1k	cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
354	26.1k	if (op_type == CS_OP_IMM) {
355	25.7k	uint64_t Target = MI->address + MCInst_getOpVal(MI, OpNum);
356	25.7k	Mips_set_detail_op_uimm(MI, OpNum, Target);
357	25.7k	} else if (op_type == CS_OP_REG) {
358	424	Mips_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum),
359	424	false);
360	424	} else
361	0	printf("Operand type %d not handled!\n", op_type);
362	26.1k	}
363
364		static void Mips_set_detail_op_unsigned(MCInst *MI, unsigned OpNum)
365	0	{
366	0	Mips_set_detail_op_uimm(MI, OpNum, MCInst_getOpVal(MI, OpNum));
367	0	}
368
369		static void Mips_set_detail_op_unsigned_offset(MCInst *MI, unsigned OpNum,
370		unsigned Bits, uint64_t Offset)
371	21.6k	{
372	21.6k	uint64_t Imm = MCInst_getOpVal(MI, OpNum);
373	21.6k	Imm -= Offset;
374	21.6k	Imm &= (((uint64_t)1) << Bits) - 1;
375	21.6k	Imm += Offset;
376	21.6k	Mips_set_detail_op_uimm(MI, OpNum, Imm);
377	21.6k	}
378
379		static void Mips_set_detail_op_mem_nanomips(MCInst *MI, unsigned OpNum)
380	0	{
381	0	CS_ASSERT(doing_mem(MI));
382
383	0	MCOperand *Op = MCInst_getOperand(MI, OpNum);
384	0	Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
385		// Base is a register, but nanoMips uses the Imm value as register.
386	0	Mips_get_detail_op(MI, 0)->mem.base = MCOperand_getImm(Op);
387	0	Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
388	0	}
389
390		static void Mips_set_detail_op_reglist(MCInst *MI, unsigned OpNum,
391		bool isNanoMips)
392	1.95k	{
393	1.95k	if (isNanoMips) {
394	0	for (unsigned i = OpNum; i < MCInst_getNumOperands(MI); i++) {
395	0	Mips_set_detail_op_reg(MI, i, MCInst_getOpVal(MI, i),
396	0	true);
397	0	}
398	0	return;
399	0	}
400		// -2 because register List is always first operand of instruction
401		// and it is always followed by memory operand (base + offset).
402	8.36k	for (unsigned i = OpNum, e = MCInst_getNumOperands(MI) - 2; i != e;
403	6.41k	++i) {
404	6.41k	Mips_set_detail_op_reg(MI, i, MCInst_getOpVal(MI, i), true);
405	6.41k	}
406	1.95k	}
407
408		static void Mips_set_detail_op_unsigned_address(MCInst *MI, unsigned OpNum)
409	0	{
410	0	uint64_t Target = MI->address + (uint64_t)MCInst_getOpVal(MI, OpNum);
411	0	Mips_set_detail_op_imm(MI, OpNum, Target);
412	0	}
413
414		void Mips_add_cs_detail_0(MCInst *MI, mips_op_group op_group, size_t OpNum)
415	398k	{
416	398k	if (!detail_is_set(MI) \|\| !map_fill_detail_ops(MI))
417	0	return;
418
419	398k	switch (op_group) {
420	0	default:
421	0	printf("Operand group %d not handled!\n", op_group);
422	0	return;
423	0	case Mips_OP_GROUP_MemOperand:
424		// this is only used by nanoMips.
425	0	return Mips_set_detail_op_mem_nanomips(MI, OpNum);
426	26.1k	case Mips_OP_GROUP_BranchOperand:
427	26.1k	return Mips_set_detail_op_branch(MI, OpNum);
428	5.16k	case Mips_OP_GROUP_JumpOperand:
429	5.16k	return Mips_set_detail_op_jump(MI, OpNum);
430	343k	case Mips_OP_GROUP_Operand:
431	343k	return Mips_set_detail_op_operand(MI, OpNum);
432	719	case Mips_OP_GROUP_UImm_1_0:
433	719	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 1, 0);
434	1.82k	case Mips_OP_GROUP_UImm_2_0:
435	1.82k	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 2, 0);
436	2.14k	case Mips_OP_GROUP_UImm_3_0:
437	2.14k	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 3, 0);
438	0	case Mips_OP_GROUP_UImm_32_0:
439	0	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 32, 0);
440	5.27k	case Mips_OP_GROUP_UImm_16_0:
441	5.27k	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 16, 0);
442	1.12k	case Mips_OP_GROUP_UImm_8_0:
443	1.12k	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 8, 0);
444	4.83k	case Mips_OP_GROUP_UImm_5_0:
445	4.83k	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 0);
446	1.22k	case Mips_OP_GROUP_UImm_6_0:
447	1.22k	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 0);
448	1.20k	case Mips_OP_GROUP_UImm_4_0:
449	1.20k	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 4, 0);
450	301	case Mips_OP_GROUP_UImm_7_0:
451	301	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 7, 0);
452	1.39k	case Mips_OP_GROUP_UImm_10_0:
453	1.39k	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 10, 0);
454	0	case Mips_OP_GROUP_UImm_6_1:
455	0	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 1);
456	186	case Mips_OP_GROUP_UImm_5_1:
457	186	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 1);
458	0	case Mips_OP_GROUP_UImm_5_33:
459	0	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 33);
460	0	case Mips_OP_GROUP_UImm_5_32:
461	0	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 32);
462	0	case Mips_OP_GROUP_UImm_6_2:
463	0	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 2);
464	606	case Mips_OP_GROUP_UImm_2_1:
465	606	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 2, 1);
466	279	case Mips_OP_GROUP_UImm_0_0:
467	279	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 0, 0);
468	0	case Mips_OP_GROUP_UImm_26_0:
469	0	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 26, 0);
470	0	case Mips_OP_GROUP_UImm_12_0:
471	0	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 12, 0);
472	517	case Mips_OP_GROUP_UImm_20_0:
473	517	return Mips_set_detail_op_unsigned_offset(MI, OpNum, 20, 0);
474	1.95k	case Mips_OP_GROUP_RegisterList:
475	1.95k	return Mips_set_detail_op_reglist(MI, OpNum, false);
476	0	case Mips_OP_GROUP_NanoMipsRegisterList:
477	0	return Mips_set_detail_op_reglist(MI, OpNum, true);
478	0	case Mips_OP_GROUP_PCRel:
479		/* fall-thru */
480	0	case Mips_OP_GROUP_Hi20PCRel:
481	0	return Mips_set_detail_op_unsigned_address(MI, OpNum);
482	0	case Mips_OP_GROUP_Hi20:
483	0	return Mips_set_detail_op_unsigned(MI, OpNum);
484	398k	}
485	398k	}
486
487		void Mips_set_mem_access(MCInst *MI, bool status)
488	87.4k	{
489	87.4k	if (!detail_is_set(MI))
490	0	return;
491	87.4k	set_doing_mem(MI, status);
492	87.4k	if (status) {
493	43.7k	if (Mips_get_detail(MI)->op_count > 0 &&
494	43.1k	Mips_get_detail_op(MI, -1)->type == MIPS_OP_MEM &&
495	0	Mips_get_detail_op(MI, -1)->mem.disp == 0) {
496		// Previous memory operand not done yet. Select it.
497	0	Mips_dec_op_count(MI);
498	0	return;
499	0	}
500
501		// Init a new one.
502	43.7k	Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
503	43.7k	Mips_get_detail_op(MI, 0)->mem.base = MIPS_REG_INVALID;
504	43.7k	Mips_get_detail_op(MI, 0)->mem.disp = 0;
505
506	43.7k	#ifndef CAPSTONE_DIET
507	43.7k	uint8_t access =
508	43.7k	map_get_op_access(MI, Mips_get_detail(MI)->op_count);
509	43.7k	Mips_get_detail_op(MI, 0)->access = access;
510	43.7k	#endif
511	43.7k	} else {
512		// done, select the next operand slot
513	43.7k	Mips_inc_op_count(MI);
514	43.7k	}
515	87.4k	}
516
517		#endif