/src/capstonev5/arch/TMS320C64x/TMS320C64xInstPrinter.c

Source
/* Capstone Disassembly Engine */
/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */

#ifdef CAPSTONE_HAS_TMS320C64X

#ifdef _MSC_VER
// Disable security warnings for strcpy
#ifndef _CRT_SECURE_NO_WARNINGS
#define _CRT_SECURE_NO_WARNINGS
#endif

// Banned API Usage : strcpy is a Banned API as listed in dontuse.h for
// security purposes.
#pragma warning(disable:28719)
#endif

#include <ctype.h>
#include <string.h>

#include "TMS320C64xInstPrinter.h"
#include "../../MCInst.h"
#include "../../utils.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../MathExtras.h"
#include "TMS320C64xMapping.h"

#include "capstone/tms320c64x.h"

static const char *getRegisterName(unsigned RegNo);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);

void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
{
  SStream ss;
  char *p, *p2, tmp[8];
  unsigned int unit = 0;
  int i;
  cs_tms320c64x *tms320c64x;

  if (mci->csh->detail) {
    tms320c64x = &mci->flat_insn->detail->tms320c64x;

    for (i = 0; i < insn->detail->groups_count; i++) {
      switch(insn->detail->groups[i]) {
        case TMS320C64X_GRP_FUNIT_D:
          unit = TMS320C64X_FUNIT_D;
          break;
        case TMS320C64X_GRP_FUNIT_L:
          unit = TMS320C64X_FUNIT_L;
          break;
        case TMS320C64X_GRP_FUNIT_M:
          unit = TMS320C64X_FUNIT_M;
          break;
        case TMS320C64X_GRP_FUNIT_S:
          unit = TMS320C64X_FUNIT_S;
          break;
        case TMS320C64X_GRP_FUNIT_NO:
          unit = TMS320C64X_FUNIT_NO;
          break;
      }
      if (unit != 0)
        break;
    }
    tms320c64x->funit.unit = unit;

    SStream_Init(&ss);
    if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
      SStream_concat(&ss, "[%c%s]|", (tms320c64x->condition.zero == 1) ? '!' : '|', cs_reg_name(ud, tms320c64x->condition.reg));

    p = strchr(insn_asm, '\t');
    if (p != NULL)
      *p++ = '\0';

    SStream_concat0(&ss, insn_asm);
    if ((p != NULL) && (((p2 = strchr(p, '[')) != NULL) || ((p2 = strchr(p, '(')) != NULL))) {
      while ((p2 > p) && ((*p2 != 'a') && (*p2 != 'b')))
        p2--;
      if (p2 == p) {
        strcpy(insn_asm, "Invalid!");
        return;
      }
      if (*p2 == 'a')
        strcpy(tmp, "1T");
      else
        strcpy(tmp, "2T");
    } else {
      tmp[0] = '\0';
    }
    switch(tms320c64x->funit.unit) {
      case TMS320C64X_FUNIT_D:
        SStream_concat(&ss, ".D%s%u", tmp, tms320c64x->funit.side);
        break;
      case TMS320C64X_FUNIT_L:
        SStream_concat(&ss, ".L%s%u", tmp, tms320c64x->funit.side);
        break;
      case TMS320C64X_FUNIT_M:
        SStream_concat(&ss, ".M%s%u", tmp, tms320c64x->funit.side);
        break;
      case TMS320C64X_FUNIT_S:
        SStream_concat(&ss, ".S%s%u", tmp, tms320c64x->funit.side);
        break;
    }
    if (tms320c64x->funit.crosspath > 0)
      SStream_concat0(&ss, "X");

    if (p != NULL)
      SStream_concat(&ss, "\t%s", p);

    if (tms320c64x->parallel != 0)
      SStream_concat0(&ss, "\t||");

    /* insn_asm is a buffer from an SStream, so there should be enough space */
    strcpy(insn_asm, ss.buffer);
  }
}

#define PRINT_ALIAS_INSTR
#include "TMS320C64xGenAsmWriter.inc"

#define GET_INSTRINFO_ENUM
#include "TMS320C64xGenInstrInfo.inc"

static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg;

  if (MCOperand_isReg(Op)) {
    reg = MCOperand_getReg(Op);
    if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && (OpNo == 1)) {
      switch(reg) {
        case TMS320C64X_REG_EFR:
          SStream_concat0(O, "EFR");
          break;
        case TMS320C64X_REG_IFR:
          SStream_concat0(O, "IFR");
          break;
        default:
          SStream_concat0(O, getRegisterName(reg));
          break;
      }
    } else {
      SStream_concat0(O, getRegisterName(reg));
    }

    if (MI->csh->detail) {
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG;
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  } else if (MCOperand_isImm(Op)) {
    int64_t Imm = MCOperand_getImm(Op);

    if (Imm >= 0) {
      if (Imm > HEX_THRESHOLD)
        SStream_concat(O, "0x%"PRIx64, Imm);
      else
        SStream_concat(O, "%"PRIu64, Imm);
    } else {
      if (Imm < -HEX_THRESHOLD)
        SStream_concat(O, "-0x%"PRIx64, -Imm);
      else
        SStream_concat(O, "-%"PRIu64, -Imm);
    }

    if (MI->csh->detail) {
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM;
      MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm;
      MI->flat_insn->detail->tms320c64x.op_count++;
    }
  }
}

static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  unsigned scaled, base, offset, mode, unit;
  cs_tms320c64x *tms320c64x;
  char st, nd;

  scaled = (Val >> 19) & 1;
  base = (Val >> 12) & 0x7f;
  offset = (Val >> 5) & 0x7f;
  mode = (Val >> 1) & 0xf;
  unit = Val & 1;

  if (scaled) {
    st = '[';
    nd = ']';
  } else {
    st = '(';
    nd = ')';
  }

  switch(mode) {
    case 0:
      SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 1:
      SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 4:
      SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
    case 5:
      SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
    case 8:
      SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 9:
      SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 10:
      SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 11:
      SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, offset, nd);
      break;
    case 12:
      SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
    case 13:
      SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
    case 14:
      SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
    case 15:
      SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
      break;
  }

  if (MI->csh->detail) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = base;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
    tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
    switch(mode) {
      case 0:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
        break;
      case 1:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
        break;
      case 4:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
        break;
      case 5:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
        break;
      case 8:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
        break;
      case 9:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
        break;
      case 10:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
        break;
      case 11:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
        break;
      case 12:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
        break;
      case 13:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
        break;
      case 14:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
        break;
      case 15:
        tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
        tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
        tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
        break;
    }
    tms320c64x->op_count++;
  }
}

static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  int64_t Val = MCOperand_getImm(Op);
  uint16_t offset;
  unsigned basereg;
  cs_tms320c64x *tms320c64x;

  basereg = Val & 0x7f;
  offset = (Val >> 7) & 0x7fff;
  SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);

  if (MI->csh->detail) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
    tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
    tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
    tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
    tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
    tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
    tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
    tms320c64x->op_count++;
  }
}

static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
{
  MCOperand *Op = MCInst_getOperand(MI, OpNo);
  unsigned reg = MCOperand_getReg(Op);
  cs_tms320c64x *tms320c64x;

  SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg));

  if (MI->csh->detail) {
    tms320c64x = &MI->flat_insn->detail->tms320c64x;

    tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR;
    tms320c64x->operands[tms320c64x->op_count].reg = reg;
    tms320c64x->op_count++;
  }
}

static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
{
  unsigned opcode = MCInst_getOpcode(MI);
  MCOperand *op;

  switch(opcode) {
    /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
    case TMS320C64x_ADD_d2_rir:
    /* ADD.L -i, x, y -> SUB.L x, i, y */
    case TMS320C64x_ADD_l1_irr:
    case TMS320C64x_ADD_l1_ipp:
    /* ADD.S -i, x, y -> SUB.S x, i, y */
    case TMS320C64x_ADD_s1_irr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
        op = MCInst_getOperand(MI, 2);
        MCOperand_setImm(op, -MCOperand_getImm(op));

        SStream_concat0(O, "SUB\t");
        printOperand(MI, 1, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 2, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* ADD.D 0, x, y -> MV.D x, y */
    case TMS320C64x_ADD_d1_rir:
    /* OR.D x, 0, y -> MV.D x, y */
    case TMS320C64x_OR_d2_rir:
    /* ADD.L 0, x, y -> MV.L x, y */
    case TMS320C64x_ADD_l1_irr:
    case TMS320C64x_ADD_l1_ipp:
    /* OR.L 0, x, y -> MV.L x, y */
    case TMS320C64x_OR_l1_irr:
    /* ADD.S 0, x, y -> MV.S x, y */
    case TMS320C64x_ADD_s1_irr:
    /* OR.S 0, x, y -> MV.S x, y */
    case TMS320C64x_OR_s1_irr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
        MI->size--;

        SStream_concat0(O, "MV\t");
        printOperand(MI, 1, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* XOR.D -1, x, y -> NOT.D x, y */
    case TMS320C64x_XOR_d2_rir:
    /* XOR.L -1, x, y -> NOT.L x, y */
    case TMS320C64x_XOR_l1_irr:
    /* XOR.S -1, x, y -> NOT.S x, y */
    case TMS320C64x_XOR_s1_irr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
        MI->size--;

        SStream_concat0(O, "NOT\t");
        printOperand(MI, 1, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* MVK.D 0, x -> ZERO.D x */
    case TMS320C64x_MVK_d1_rr:
    /* MVK.L 0, x -> ZERO.L x */
    case TMS320C64x_MVK_l2_ir:
      if ((MCInst_getNumOperands(MI) == 2) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
        MI->size--;

        SStream_concat0(O, "ZERO\t");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* SUB.L x, x, y -> ZERO.L y */
    case TMS320C64x_SUB_l1_rrp_x1:
    /* SUB.S x, x, y -> ZERO.S y */
    case TMS320C64x_SUB_s1_rrr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
        MI->size -= 2;

        SStream_concat0(O, "ZERO\t");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* SUB.L 0, x, y -> NEG.L x, y */
    case TMS320C64x_SUB_l1_irr:
    case TMS320C64x_SUB_l1_ipp:
    /* SUB.S 0, x, y -> NEG.S x, y */
    case TMS320C64x_SUB_s1_irr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
        MI->size--;

        SStream_concat0(O, "NEG\t");
        printOperand(MI, 1, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* PACKLH2.L x, x, y -> SWAP2.L x, y */
    case TMS320C64x_PACKLH2_l1_rrr_x2:
    /* PACKLH2.S x, x, y -> SWAP2.S x, y */
    case TMS320C64x_PACKLH2_s1_rrr:
      if ((MCInst_getNumOperands(MI) == 3) &&
        MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
        MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
        MI->size--;

        SStream_concat0(O, "SWAP2\t");
        printOperand(MI, 1, O);
        SStream_concat0(O, ", ");
        printOperand(MI, 0, O);

        return true;
      }
      break;
  }
  switch(opcode) {
    /* NOP 16 -> IDLE */
    /* NOP 1 -> NOP */
    case TMS320C64x_NOP_n:
      if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {

        MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
        MI->size--;

        SStream_concat0(O, "IDLE");

        return true;
      }
      if ((MCInst_getNumOperands(MI) == 1) &&
        MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
        (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {

        MI->size--;

        SStream_concat0(O, "NOP");

        return true;
      }
      break;
  }

  return false;
}

void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
{
  if (!printAliasInstruction(MI, O, Info))
    printInstruction(MI, O, Info);
}

#endif

Coverage Report

Created: 2026-09-01 07:20

Line	Count	Source
1		/* Capstone Disassembly Engine */
2		/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3
4		#ifdef CAPSTONE_HAS_TMS320C64X
5
6		#ifdef _MSC_VER
7		// Disable security warnings for strcpy
8		#ifndef _CRT_SECURE_NO_WARNINGS
9		#define _CRT_SECURE_NO_WARNINGS
10		#endif
11
12		// Banned API Usage : strcpy is a Banned API as listed in dontuse.h for
13		// security purposes.
14		#pragma warning(disable:28719)
15		#endif
16
17		#include <ctype.h>
18		#include <string.h>
19
20		#include "TMS320C64xInstPrinter.h"
21		#include "../../MCInst.h"
22		#include "../../utils.h"
23		#include "../../SStream.h"
24		#include "../../MCRegisterInfo.h"
25		#include "../../MathExtras.h"
26		#include "TMS320C64xMapping.h"
27
28		#include "capstone/tms320c64x.h"
29
30		static const char *getRegisterName(unsigned RegNo);
31		static void printOperand(MCInst MI, unsigned OpNo, SStream O);
32		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O);
33		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O);
34		static void printRegPair(MCInst MI, unsigned OpNo, SStream O);
35
36		void TMS320C64x_post_printer(csh ud, cs_insn insn, char insn_asm, MCInst *mci)
37	28.8k	{
38	28.8k	SStream ss;
39	28.8k	char p, p2, tmp[8];
40	28.8k	unsigned int unit = 0;
41	28.8k	int i;
42	28.8k	cs_tms320c64x *tms320c64x;
43
44	28.8k	if (mci->csh->detail) {
45	28.8k	tms320c64x = &mci->flat_insn->detail->tms320c64x;
46
47	28.8k	for (i = 0; i < insn->detail->groups_count; i++) {
48	28.8k	switch(insn->detail->groups[i]) {
49	8.23k	case TMS320C64X_GRP_FUNIT_D:
50	8.23k	unit = TMS320C64X_FUNIT_D;
51	8.23k	break;
52	7.00k	case TMS320C64X_GRP_FUNIT_L:
53	7.00k	unit = TMS320C64X_FUNIT_L;
54	7.00k	break;
55	1.41k	case TMS320C64X_GRP_FUNIT_M:
56	1.41k	unit = TMS320C64X_FUNIT_M;
57	1.41k	break;
58	11.4k	case TMS320C64X_GRP_FUNIT_S:
59	11.4k	unit = TMS320C64X_FUNIT_S;
60	11.4k	break;
61	804	case TMS320C64X_GRP_FUNIT_NO:
62	804	unit = TMS320C64X_FUNIT_NO;
63	804	break;
64	28.8k	}
65	28.8k	if (unit != 0)
66	28.8k	break;
67	28.8k	}
68	28.8k	tms320c64x->funit.unit = unit;
69
70	28.8k	SStream_Init(&ss);
71	28.8k	if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
72	19.1k	SStream_concat(&ss, "[%c%s]\|", (tms320c64x->condition.zero == 1) ? '!' : '\|', cs_reg_name(ud, tms320c64x->condition.reg));
73
74	28.8k	p = strchr(insn_asm, '\t');
75	28.8k	if (p != NULL)
76	28.2k	*p++ = '\0';
77
78	28.8k	SStream_concat0(&ss, insn_asm);
79	28.8k	if ((p != NULL) && (((p2 = strchr(p, '[')) != NULL) \|\| ((p2 = strchr(p, '(')) != NULL))) {
80	24.5k	while ((p2 > p) && ((p2 != 'a') && (p2 != 'b')))
81	18.4k	p2--;
82	6.06k	if (p2 == p) {
83	0	strcpy(insn_asm, "Invalid!");
84	0	return;
85	0	}
86	6.06k	if (*p2 == 'a')
87	2.58k	strcpy(tmp, "1T");
88	3.48k	else
89	3.48k	strcpy(tmp, "2T");
90	22.8k	} else {
91	22.8k	tmp[0] = '\0';
92	22.8k	}
93	28.8k	switch(tms320c64x->funit.unit) {
94	8.23k	case TMS320C64X_FUNIT_D:
95	8.23k	SStream_concat(&ss, ".D%s%u", tmp, tms320c64x->funit.side);
96	8.23k	break;
97	7.00k	case TMS320C64X_FUNIT_L:
98	7.00k	SStream_concat(&ss, ".L%s%u", tmp, tms320c64x->funit.side);
99	7.00k	break;
100	1.41k	case TMS320C64X_FUNIT_M:
101	1.41k	SStream_concat(&ss, ".M%s%u", tmp, tms320c64x->funit.side);
102	1.41k	break;
103	11.4k	case TMS320C64X_FUNIT_S:
104	11.4k	SStream_concat(&ss, ".S%s%u", tmp, tms320c64x->funit.side);
105	11.4k	break;
106	28.8k	}
107	28.8k	if (tms320c64x->funit.crosspath > 0)
108	8.29k	SStream_concat0(&ss, "X");
109
110	28.8k	if (p != NULL)
111	28.2k	SStream_concat(&ss, "\t%s", p);
112
113	28.8k	if (tms320c64x->parallel != 0)
114	13.9k	SStream_concat0(&ss, "\t\|\|");
115
116		/* insn_asm is a buffer from an SStream, so there should be enough space */
117	28.8k	strcpy(insn_asm, ss.buffer);
118	28.8k	}
119	28.8k	}
120
121		#define PRINT_ALIAS_INSTR
122		#include "TMS320C64xGenAsmWriter.inc"
123
124		#define GET_INSTRINFO_ENUM
125		#include "TMS320C64xGenInstrInfo.inc"
126
127		static void printOperand(MCInst MI, unsigned OpNo, SStream O)
128	112k	{
129	112k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
130	112k	unsigned reg;
131
132	112k	if (MCOperand_isReg(Op)) {
133	83.5k	reg = MCOperand_getReg(Op);
134	83.5k	if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && (OpNo == 1)) {
135	1.37k	switch(reg) {
136	435	case TMS320C64X_REG_EFR:
137	435	SStream_concat0(O, "EFR");
138	435	break;
139	273	case TMS320C64X_REG_IFR:
140	273	SStream_concat0(O, "IFR");
141	273	break;
142	663	default:
143	663	SStream_concat0(O, getRegisterName(reg));
144	663	break;
145	1.37k	}
146	82.1k	} else {
147	82.1k	SStream_concat0(O, getRegisterName(reg));
148	82.1k	}
149
150	83.5k	if (MI->csh->detail) {
151	83.5k	MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG;
152	83.5k	MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg;
153	83.5k	MI->flat_insn->detail->tms320c64x.op_count++;
154	83.5k	}
155	83.5k	} else if (MCOperand_isImm(Op)) {
156	29.0k	int64_t Imm = MCOperand_getImm(Op);
157
158	29.0k	if (Imm >= 0) {
159	21.2k	if (Imm > HEX_THRESHOLD)
160	12.2k	SStream_concat(O, "0x%"PRIx64, Imm);
161	9.06k	else
162	9.06k	SStream_concat(O, "%"PRIu64, Imm);
163	21.2k	} else {
164	7.77k	if (Imm < -HEX_THRESHOLD)
165	5.56k	SStream_concat(O, "-0x%"PRIx64, -Imm);
166	2.21k	else
167	2.21k	SStream_concat(O, "-%"PRIu64, -Imm);
168	7.77k	}
169
170	29.0k	if (MI->csh->detail) {
171	29.0k	MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM;
172	29.0k	MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm;
173	29.0k	MI->flat_insn->detail->tms320c64x.op_count++;
174	29.0k	}
175	29.0k	}
176	112k	}
177
178		static void printMemOperand(MCInst MI, unsigned OpNo, SStream O)
179	7.01k	{
180	7.01k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
181	7.01k	int64_t Val = MCOperand_getImm(Op);
182	7.01k	unsigned scaled, base, offset, mode, unit;
183	7.01k	cs_tms320c64x *tms320c64x;
184	7.01k	char st, nd;
185
186	7.01k	scaled = (Val >> 19) & 1;
187	7.01k	base = (Val >> 12) & 0x7f;
188	7.01k	offset = (Val >> 5) & 0x7f;
189	7.01k	mode = (Val >> 1) & 0xf;
190	7.01k	unit = Val & 1;
191
192	7.01k	if (scaled) {
193	5.72k	st = '[';
194	5.72k	nd = ']';
195	5.72k	} else {
196	1.28k	st = '(';
197	1.28k	nd = ')';
198	1.28k	}
199
200	7.01k	switch(mode) {
201	627	case 0:
202	627	SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, offset, nd);
203	627	break;
204	444	case 1:
205	444	SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, offset, nd);
206	444	break;
207	540	case 4:
208	540	SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
209	540	break;
210	286	case 5:
211	286	SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
212	286	break;
213	644	case 8:
214	644	SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, offset, nd);
215	644	break;
216	537	case 9:
217	537	SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, offset, nd);
218	537	break;
219	501	case 10:
220	501	SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, offset, nd);
221	501	break;
222	509	case 11:
223	509	SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, offset, nd);
224	509	break;
225	1.04k	case 12:
226	1.04k	SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
227	1.04k	break;
228	651	case 13:
229	651	SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
230	651	break;
231	681	case 14:
232	681	SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
233	681	break;
234	553	case 15:
235	553	SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
236	553	break;
237	7.01k	}
238
239	7.01k	if (MI->csh->detail) {
240	7.01k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
241
242	7.01k	tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
243	7.01k	tms320c64x->operands[tms320c64x->op_count].mem.base = base;
244	7.01k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
245	7.01k	tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
246	7.01k	tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
247	7.01k	switch(mode) {
248	627	case 0:
249	627	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
250	627	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
251	627	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
252	627	break;
253	444	case 1:
254	444	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
255	444	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
256	444	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
257	444	break;
258	540	case 4:
259	540	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
260	540	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
261	540	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
262	540	break;
263	286	case 5:
264	286	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
265	286	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
266	286	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
267	286	break;
268	644	case 8:
269	644	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
270	644	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
271	644	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
272	644	break;
273	537	case 9:
274	537	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
275	537	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
276	537	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
277	537	break;
278	501	case 10:
279	501	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
280	501	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
281	501	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
282	501	break;
283	509	case 11:
284	509	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
285	509	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
286	509	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
287	509	break;
288	1.04k	case 12:
289	1.04k	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
290	1.04k	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
291	1.04k	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
292	1.04k	break;
293	651	case 13:
294	651	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
295	651	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
296	651	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
297	651	break;
298	681	case 14:
299	681	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
300	681	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
301	681	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
302	681	break;
303	553	case 15:
304	553	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
305	553	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
306	553	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
307	553	break;
308	7.01k	}
309	7.01k	tms320c64x->op_count++;
310	7.01k	}
311	7.01k	}
312
313		static void printMemOperand2(MCInst MI, unsigned OpNo, SStream O)
314	7.88k	{
315	7.88k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
316	7.88k	int64_t Val = MCOperand_getImm(Op);
317	7.88k	uint16_t offset;
318	7.88k	unsigned basereg;
319	7.88k	cs_tms320c64x *tms320c64x;
320
321	7.88k	basereg = Val & 0x7f;
322	7.88k	offset = (Val >> 7) & 0x7fff;
323	7.88k	SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
324
325	7.88k	if (MI->csh->detail) {
326	7.88k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
327
328	7.88k	tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
329	7.88k	tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
330	7.88k	tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
331	7.88k	tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
332	7.88k	tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
333	7.88k	tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
334	7.88k	tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
335	7.88k	tms320c64x->op_count++;
336	7.88k	}
337	7.88k	}
338
339		static void printRegPair(MCInst MI, unsigned OpNo, SStream O)
340	18.5k	{
341	18.5k	MCOperand *Op = MCInst_getOperand(MI, OpNo);
342	18.5k	unsigned reg = MCOperand_getReg(Op);
343	18.5k	cs_tms320c64x *tms320c64x;
344
345	18.5k	SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg));
346
347	18.5k	if (MI->csh->detail) {
348	18.5k	tms320c64x = &MI->flat_insn->detail->tms320c64x;
349
350	18.5k	tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR;
351	18.5k	tms320c64x->operands[tms320c64x->op_count].reg = reg;
352	18.5k	tms320c64x->op_count++;
353	18.5k	}
354	18.5k	}
355
356		static bool printAliasInstruction(MCInst MI, SStream O, MCRegisterInfo *MRI)
357	63.1k	{
358	63.1k	unsigned opcode = MCInst_getOpcode(MI);
359	63.1k	MCOperand *op;
360
361	63.1k	switch(opcode) {
362		/* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
363	470	case TMS320C64x_ADD_d2_rir:
364		/* ADD.L -i, x, y -> SUB.L x, i, y */
365	860	case TMS320C64x_ADD_l1_irr:
366	1.59k	case TMS320C64x_ADD_l1_ipp:
367		/* ADD.S -i, x, y -> SUB.S x, i, y */
368	2.34k	case TMS320C64x_ADD_s1_irr:
369	2.34k	if ((MCInst_getNumOperands(MI) == 3) &&
370	2.34k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
371	2.34k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
372	2.34k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
373	2.34k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
374
375	397	MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
376	397	op = MCInst_getOperand(MI, 2);
377	397	MCOperand_setImm(op, -MCOperand_getImm(op));
378
379	397	SStream_concat0(O, "SUB\t");
380	397	printOperand(MI, 1, O);
381	397	SStream_concat0(O, ", ");
382	397	printOperand(MI, 2, O);
383	397	SStream_concat0(O, ", ");
384	397	printOperand(MI, 0, O);
385
386	397	return true;
387	397	}
388	1.94k	break;
389	63.1k	}
390	62.7k	switch(opcode) {
391		/* ADD.D 0, x, y -> MV.D x, y */
392	1.01k	case TMS320C64x_ADD_d1_rir:
393		/* OR.D x, 0, y -> MV.D x, y */
394	1.17k	case TMS320C64x_OR_d2_rir:
395		/* ADD.L 0, x, y -> MV.L x, y */
396	1.47k	case TMS320C64x_ADD_l1_irr:
397	2.16k	case TMS320C64x_ADD_l1_ipp:
398		/* OR.L 0, x, y -> MV.L x, y */
399	2.39k	case TMS320C64x_OR_l1_irr:
400		/* ADD.S 0, x, y -> MV.S x, y */
401	3.12k	case TMS320C64x_ADD_s1_irr:
402		/* OR.S 0, x, y -> MV.S x, y */
403	3.23k	case TMS320C64x_OR_s1_irr:
404	3.23k	if ((MCInst_getNumOperands(MI) == 3) &&
405	3.23k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
406	3.23k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
407	3.23k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
408	3.23k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
409
410	794	MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
411	794	MI->size--;
412
413	794	SStream_concat0(O, "MV\t");
414	794	printOperand(MI, 1, O);
415	794	SStream_concat0(O, ", ");
416	794	printOperand(MI, 0, O);
417
418	794	return true;
419	794	}
420	2.44k	break;
421	62.7k	}
422	61.9k	switch(opcode) {
423		/* XOR.D -1, x, y -> NOT.D x, y */
424	890	case TMS320C64x_XOR_d2_rir:
425		/* XOR.L -1, x, y -> NOT.L x, y */
426	1.12k	case TMS320C64x_XOR_l1_irr:
427		/* XOR.S -1, x, y -> NOT.S x, y */
428	1.57k	case TMS320C64x_XOR_s1_irr:
429	1.57k	if ((MCInst_getNumOperands(MI) == 3) &&
430	1.57k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
431	1.57k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
432	1.57k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
433	1.57k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
434
435	306	MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
436	306	MI->size--;
437
438	306	SStream_concat0(O, "NOT\t");
439	306	printOperand(MI, 1, O);
440	306	SStream_concat0(O, ", ");
441	306	printOperand(MI, 0, O);
442
443	306	return true;
444	306	}
445	1.27k	break;
446	61.9k	}
447	61.6k	switch(opcode) {
448		/* MVK.D 0, x -> ZERO.D x */
449	742	case TMS320C64x_MVK_d1_rr:
450		/* MVK.L 0, x -> ZERO.L x */
451	1.50k	case TMS320C64x_MVK_l2_ir:
452	1.50k	if ((MCInst_getNumOperands(MI) == 2) &&
453	1.50k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
454	1.50k	MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
455	1.50k	(MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
456
457	442	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
458	442	MI->size--;
459
460	442	SStream_concat0(O, "ZERO\t");
461	442	printOperand(MI, 0, O);
462
463	442	return true;
464	442	}
465	1.05k	break;
466	61.6k	}
467	61.1k	switch(opcode) {
468		/* SUB.L x, x, y -> ZERO.L y */
469	322	case TMS320C64x_SUB_l1_rrp_x1:
470		/* SUB.S x, x, y -> ZERO.S y */
471	363	case TMS320C64x_SUB_s1_rrr:
472	363	if ((MCInst_getNumOperands(MI) == 3) &&
473	363	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
474	363	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
475	363	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
476	363	(MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
477
478	33	MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
479	33	MI->size -= 2;
480
481	33	SStream_concat0(O, "ZERO\t");
482	33	printOperand(MI, 0, O);
483
484	33	return true;
485	33	}
486	330	break;
487	61.1k	}
488	61.1k	switch(opcode) {
489		/* SUB.L 0, x, y -> NEG.L x, y */
490	519	case TMS320C64x_SUB_l1_irr:
491	785	case TMS320C64x_SUB_l1_ipp:
492		/* SUB.S 0, x, y -> NEG.S x, y */
493	1.13k	case TMS320C64x_SUB_s1_irr:
494	1.13k	if ((MCInst_getNumOperands(MI) == 3) &&
495	1.13k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
496	1.13k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
497	1.13k	MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
498	1.13k	(MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
499
500	362	MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
501	362	MI->size--;
502
503	362	SStream_concat0(O, "NEG\t");
504	362	printOperand(MI, 1, O);
505	362	SStream_concat0(O, ", ");
506	362	printOperand(MI, 0, O);
507
508	362	return true;
509	362	}
510	770	break;
511	61.1k	}
512	60.7k	switch(opcode) {
513		/* PACKLH2.L x, x, y -> SWAP2.L x, y */
514	844	case TMS320C64x_PACKLH2_l1_rrr_x2:
515		/* PACKLH2.S x, x, y -> SWAP2.S x, y */
516	1.63k	case TMS320C64x_PACKLH2_s1_rrr:
517	1.63k	if ((MCInst_getNumOperands(MI) == 3) &&
518	1.63k	MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
519	1.63k	MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
520	1.63k	MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
521	1.63k	(MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
522
523	130	MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
524	130	MI->size--;
525
526	130	SStream_concat0(O, "SWAP2\t");
527	130	printOperand(MI, 1, O);
528	130	SStream_concat0(O, ", ");
529	130	printOperand(MI, 0, O);
530
531	130	return true;
532	130	}
533	1.50k	break;
534	60.7k	}
535	60.6k	switch(opcode) {
536		/* NOP 16 -> IDLE */
537		/* NOP 1 -> NOP */
538	1.54k	case TMS320C64x_NOP_n:
539	1.54k	if ((MCInst_getNumOperands(MI) == 1) &&
540	1.54k	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
541	1.54k	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
542
543	316	MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
544	316	MI->size--;
545
546	316	SStream_concat0(O, "IDLE");
547
548	316	return true;
549	316	}
550	1.22k	if ((MCInst_getNumOperands(MI) == 1) &&
551	1.22k	MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
552	1.22k	(MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
553
554	977	MI->size--;
555
556	977	SStream_concat0(O, "NOP");
557
558	977	return true;
559	977	}
560	247	break;
561	60.6k	}
562
563	59.3k	return false;
564	60.6k	}
565
566		void TMS320C64x_printInst(MCInst MI, SStream O, void *Info)
567	63.1k	{
568	63.1k	if (!printAliasInstruction(MI, O, Info))
569	59.3k	printInstruction(MI, O, Info);
570	63.1k	}
571
572		#endif