/src/capstonenext/arch/Mips/MipsDisassembler.c
Line | Count | Source |
1 | | /* Capstone Disassembly Engine, http://www.capstone-engine.org */ |
2 | | /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */ |
3 | | /* Rot127 <unisono@quyllur.org> 2022-2023 */ |
4 | | /* Automatically translated source file from LLVM. */ |
5 | | |
6 | | /* LLVM-commit: <commit> */ |
7 | | /* LLVM-tag: <tag> */ |
8 | | |
9 | | /* Only small edits allowed. */ |
10 | | /* For multiple similar edits, please create a Patch for the translator. */ |
11 | | |
12 | | /* Capstone's C++ file translator: */ |
13 | | /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ |
14 | | |
15 | | //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===// |
16 | | // |
17 | | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
18 | | // See https://llvm.org/LICENSE.txt for license information. |
19 | | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
20 | | // |
21 | | //===----------------------------------------------------------------------===// |
22 | | // |
23 | | // This file is part of the Mips Disassembler. |
24 | | // |
25 | | //===----------------------------------------------------------------------===// |
26 | | |
27 | | #include <stdio.h> |
28 | | #include <string.h> |
29 | | #include <stdlib.h> |
30 | | #include <capstone/platform.h> |
31 | | |
32 | | #include "../../MCInst.h" |
33 | | #include "../../MathExtras.h" |
34 | | #include "../../MCInstPrinter.h" |
35 | | #include "../../MCDisassembler.h" |
36 | | #include "../../MCRegisterInfo.h" |
37 | | #include "../../MCFixedLenDisassembler.h" |
38 | | #include "../../cs_priv.h" |
39 | | #include "../../utils.h" |
40 | | #define GET_SUBTARGETINFO_ENUM |
41 | | #include "MipsGenSubtargetInfo.inc" |
42 | | |
43 | | #define GET_INSTRINFO_ENUM |
44 | | #include "MipsGenInstrInfo.inc" |
45 | | |
46 | | #define GET_REGINFO_ENUM |
47 | | #include "MipsGenRegisterInfo.inc" |
48 | | |
49 | 962 | #define CONCAT(a, b) CONCAT_(a, b) |
50 | 962 | #define CONCAT_(a, b) a##_##b |
51 | | |
52 | | #define DEBUG_TYPE "mips-disassembler" |
53 | | |
54 | | bool Mips_getFeatureBits(unsigned int mode, unsigned int feature) |
55 | 2.06M | { |
56 | 2.06M | switch (feature) { |
57 | 142k | case Mips_FeatureGP64Bit: |
58 | 142k | return mode & |
59 | 142k | (CS_MODE_MIPS3 | CS_MODE_MIPS4 | CS_MODE_MIPS5 | |
60 | 142k | CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | |
61 | 142k | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | CS_MODE_OCTEON | |
62 | 142k | CS_MODE_OCTEONP); |
63 | 152k | case Mips_FeatureFP64Bit: |
64 | 152k | return mode & |
65 | 152k | (CS_MODE_MIPS32R6 | CS_MODE_MIPS3 | CS_MODE_MIPS4 | |
66 | 152k | CS_MODE_MIPS5 | CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | |
67 | 152k | CS_MODE_MIPS32R5 | CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | |
68 | 152k | CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | |
69 | 152k | CS_MODE_OCTEON | CS_MODE_OCTEONP); |
70 | 0 | case Mips_FeatureNaN2008: |
71 | 0 | return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS64R6); |
72 | 0 | case Mips_FeatureAbs2008: |
73 | 0 | return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS64R6); |
74 | 0 | case Mips_FeatureMips1: |
75 | 0 | return mode & |
76 | 0 | (CS_MODE_MIPS1 | CS_MODE_MIPS2 | CS_MODE_MIPS32 | |
77 | 0 | CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | |
78 | 0 | CS_MODE_MIPS32R6 | CS_MODE_MIPS3 | CS_MODE_MIPS4 | |
79 | 0 | CS_MODE_MIPS5 | CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | |
80 | 0 | CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | |
81 | 0 | CS_MODE_OCTEON | CS_MODE_OCTEONP); |
82 | 143k | case Mips_FeatureMips2: |
83 | 143k | return mode & |
84 | 143k | (CS_MODE_MIPS2 | CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | |
85 | 143k | CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | |
86 | 143k | CS_MODE_MIPS3 | CS_MODE_MIPS4 | CS_MODE_MIPS5 | |
87 | 143k | CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | |
88 | 143k | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | CS_MODE_OCTEON | |
89 | 143k | CS_MODE_OCTEONP); |
90 | 600 | case Mips_FeatureMips3_32: |
91 | 600 | return mode & |
92 | 600 | (CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | |
93 | 600 | CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | CS_MODE_MIPS3 | |
94 | 600 | CS_MODE_MIPS4 | CS_MODE_MIPS5 | CS_MODE_MIPS64 | |
95 | 600 | CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | |
96 | 600 | CS_MODE_MIPS64R6 | CS_MODE_OCTEON | CS_MODE_OCTEONP); |
97 | 304 | case Mips_FeatureMips3_32r2: |
98 | 304 | return mode & |
99 | 304 | (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | |
100 | 304 | CS_MODE_MIPS32R6 | CS_MODE_MIPS3 | CS_MODE_MIPS4 | |
101 | 304 | CS_MODE_MIPS5 | CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | |
102 | 304 | CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | |
103 | 304 | CS_MODE_OCTEON | CS_MODE_OCTEONP); |
104 | 7.11k | case Mips_FeatureMips3: |
105 | 7.11k | return mode & |
106 | 7.11k | (CS_MODE_MIPS3 | CS_MODE_MIPS4 | CS_MODE_MIPS5 | |
107 | 7.11k | CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | |
108 | 7.11k | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | CS_MODE_OCTEON | |
109 | 7.11k | CS_MODE_OCTEONP); |
110 | 2.66k | case Mips_FeatureMips4_32: |
111 | 2.66k | return mode & |
112 | 2.66k | (CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | |
113 | 2.66k | CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | CS_MODE_MIPS4 | |
114 | 2.66k | CS_MODE_MIPS5 | CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | |
115 | 2.66k | CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | |
116 | 2.66k | CS_MODE_OCTEON | CS_MODE_OCTEONP); |
117 | 1.80k | case Mips_FeatureMips4_32r2: |
118 | 1.80k | return mode & |
119 | 1.80k | (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | |
120 | 1.80k | CS_MODE_MIPS32R6 | CS_MODE_MIPS4 | CS_MODE_MIPS5 | |
121 | 1.80k | CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | |
122 | 1.80k | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | CS_MODE_OCTEON | |
123 | 1.80k | CS_MODE_OCTEONP); |
124 | 0 | case Mips_FeatureMips4: |
125 | 0 | return mode & |
126 | 0 | (CS_MODE_MIPS4 | CS_MODE_MIPS5 | CS_MODE_MIPS64 | |
127 | 0 | CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | |
128 | 0 | CS_MODE_MIPS64R6 | CS_MODE_OCTEON | CS_MODE_OCTEONP); |
129 | 70 | case Mips_FeatureMips5_32r2: |
130 | 70 | return mode & |
131 | 70 | (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | |
132 | 70 | CS_MODE_MIPS32R6 | CS_MODE_MIPS5 | CS_MODE_MIPS64 | |
133 | 70 | CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | |
134 | 70 | CS_MODE_MIPS64R6 | CS_MODE_OCTEON | CS_MODE_OCTEONP); |
135 | 0 | case Mips_FeatureMips5: |
136 | 0 | return mode & |
137 | 0 | (CS_MODE_MIPS5 | CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | |
138 | 0 | CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | |
139 | 0 | CS_MODE_OCTEON | CS_MODE_OCTEONP); |
140 | 139k | case Mips_FeatureMips32: |
141 | 139k | return mode & |
142 | 139k | (CS_MODE_MIPS32 | CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | |
143 | 139k | CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | CS_MODE_MIPS64 | |
144 | 139k | CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | |
145 | 139k | CS_MODE_MIPS64R6 | CS_MODE_OCTEON | CS_MODE_OCTEONP); |
146 | 1.50k | case Mips_FeatureMips32r2: |
147 | 1.50k | return mode & |
148 | 1.50k | (CS_MODE_MIPS32R2 | CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | |
149 | 1.50k | CS_MODE_MIPS32R6 | CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | |
150 | 1.50k | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | CS_MODE_OCTEON | |
151 | 1.50k | CS_MODE_OCTEONP); |
152 | 0 | case Mips_FeatureMips32r3: |
153 | 0 | return mode & |
154 | 0 | (CS_MODE_MIPS32R3 | CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | |
155 | 0 | CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6); |
156 | 970 | case Mips_FeatureMips32r5: |
157 | 970 | return mode & (CS_MODE_MIPS32R5 | CS_MODE_MIPS32R6 | |
158 | 970 | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6); |
159 | 209k | case Mips_FeatureMips32r6: |
160 | 209k | return mode & (CS_MODE_MIPS32R6 | CS_MODE_MIPS64R6); |
161 | 821 | case Mips_FeatureMips64: |
162 | 821 | return mode & |
163 | 821 | (CS_MODE_MIPS64 | CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | |
164 | 821 | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6 | CS_MODE_OCTEON | |
165 | 821 | CS_MODE_OCTEONP); |
166 | 216 | case Mips_FeatureMips64r2: |
167 | 216 | return mode & |
168 | 216 | (CS_MODE_MIPS64R2 | CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | |
169 | 216 | CS_MODE_MIPS64R6 | CS_MODE_OCTEON | CS_MODE_OCTEONP); |
170 | 0 | case Mips_FeatureMips64r3: |
171 | 0 | return mode & |
172 | 0 | (CS_MODE_MIPS64R3 | CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6); |
173 | 1 | case Mips_FeatureMips64r5: |
174 | 1 | return mode & (CS_MODE_MIPS64R5 | CS_MODE_MIPS64R6); |
175 | 153k | case Mips_FeatureMips64r6: |
176 | 153k | return mode & CS_MODE_MIPS64R6; |
177 | 217k | case Mips_FeatureMips16: |
178 | 217k | return mode & CS_MODE_MIPS16; |
179 | 258k | case Mips_FeatureMicroMips: |
180 | 258k | return mode & CS_MODE_MICRO; |
181 | 164k | case Mips_FeatureNanoMips: |
182 | 164k | return mode & (CS_MODE_NANOMIPS | CS_MODE_NMS1 | CS_MODE_I7200); |
183 | 0 | case Mips_FeatureNMS1: |
184 | 0 | return mode & CS_MODE_NMS1; |
185 | 0 | case Mips_FeatureTLB: |
186 | 0 | return mode & CS_MODE_I7200; |
187 | 137k | case Mips_FeatureCnMips: |
188 | 137k | return mode & (CS_MODE_OCTEON | CS_MODE_OCTEONP); |
189 | 137k | case Mips_FeatureCnMipsP: |
190 | 137k | return mode & CS_MODE_OCTEONP; |
191 | 138k | case Mips_FeaturePTR64Bit: |
192 | 138k | return mode & CS_MODE_MIPS_PTR64; |
193 | 18.2k | case Mips_FeatureSoftFloat: |
194 | 18.2k | return mode & CS_MODE_MIPS_NOFLOAT; |
195 | 0 | case Mips_FeatureI7200: |
196 | 0 | return mode & CS_MODE_I7200; |
197 | | // optional features always enabled |
198 | 7.66k | case Mips_FeatureDSP: // Mips DSP ASE |
199 | 7.66k | return true; |
200 | 1.71k | case Mips_FeatureDSPR2: // Mips DSP-R2 ASE |
201 | 1.71k | return true; |
202 | 66 | case Mips_FeatureDSPR3: // Mips DSP-R3 ASE |
203 | 66 | return true; |
204 | 0 | case Mips_FeatureMips3D: // Mips 3D ASE |
205 | 0 | return true; |
206 | 19.0k | case Mips_FeatureMSA: // Mips MSA ASE |
207 | 19.0k | return true; |
208 | 1.06k | case Mips_FeatureEVA: { // Mips EVA ASE |
209 | 1.06k | if (mode & CS_MODE_NANOMIPS) { |
210 | 0 | return mode & CS_MODE_I7200; |
211 | 0 | } |
212 | 1.06k | return true; |
213 | 1.06k | } |
214 | 247 | case Mips_FeatureCRC: // Mips R6 CRC ASE |
215 | 247 | return true; |
216 | 501 | case Mips_FeatureVirt: // Mips Virtualization ASE |
217 | 501 | return true; |
218 | 154 | case Mips_FeatureGINV: // Mips Global Invalidate ASE |
219 | 154 | return true; |
220 | 1.00k | case Mips_FeatureMT: { // Mips MT ASE |
221 | 1.00k | if (mode & CS_MODE_NANOMIPS) { |
222 | 0 | return mode & CS_MODE_I7200; |
223 | 0 | } |
224 | 1.00k | return true; |
225 | 1.00k | } |
226 | 1.46k | default: |
227 | 1.46k | return false; |
228 | 2.06M | } |
229 | 2.06M | } |
230 | | |
231 | | static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, |
232 | | const uint8_t *Bytes, size_t BytesLen, |
233 | | uint64_t Address, SStream *CStream); |
234 | | |
235 | | // end anonymous namespace |
236 | | |
237 | | // Forward declare these because the autogenerated code will reference them. |
238 | | // Definitions are further down. |
239 | | static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, |
240 | | uint64_t Address, |
241 | | const void *Decoder); |
242 | | |
243 | | static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, |
244 | | uint64_t Address, |
245 | | const void *Decoder); |
246 | | |
247 | | static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, |
248 | | uint64_t Address, |
249 | | const void *Decoder); |
250 | | |
251 | | static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, |
252 | | uint64_t Address, |
253 | | const void *Decoder); |
254 | | |
255 | | static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, |
256 | | unsigned RegNo, |
257 | | uint64_t Address, |
258 | | const void *Decoder); |
259 | | |
260 | | static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, |
261 | | uint64_t Address, |
262 | | const void *Decoder); |
263 | | |
264 | | static DecodeStatus DecodeGPRNM3RegisterClass(MCInst *Inst, unsigned RegNo, |
265 | | uint64_t Address, |
266 | | const void *Decoder); |
267 | | |
268 | | static DecodeStatus DecodeGPRNM4RegisterClass(MCInst *Inst, unsigned RegNo, |
269 | | uint64_t Address, |
270 | | const void *Decoder); |
271 | | |
272 | | static DecodeStatus DecodeGPRNMRARegisterClass(MCInst *Inst, unsigned RegNo, |
273 | | uint64_t Address, |
274 | | const void *Decoder); |
275 | | |
276 | | static DecodeStatus DecodeGPRNM3ZRegisterClass(MCInst *Inst, unsigned RegNo, |
277 | | uint64_t Address, |
278 | | const void *Decoder); |
279 | | |
280 | | static DecodeStatus DecodeGPRNM4ZRegisterClass(MCInst *Inst, unsigned RegNo, |
281 | | uint64_t Address, |
282 | | const void *Decoder); |
283 | | |
284 | | static DecodeStatus DecodeGPRNM32NZRegisterClass(MCInst *Inst, unsigned RegNo, |
285 | | uint64_t Address, |
286 | | const void *Decoder); |
287 | | |
288 | | static DecodeStatus DecodeGPRNM32RegisterClass(MCInst *Inst, unsigned RegNo, |
289 | | uint64_t Address, |
290 | | const void *Decoder); |
291 | | |
292 | | static DecodeStatus DecodeGPRNM2R1RegisterClass(MCInst *Inst, unsigned RegNo, |
293 | | uint64_t Address, |
294 | | const void *Decoder); |
295 | | |
296 | | static DecodeStatus DecodeGPRNM1R1RegisterClass(MCInst *Inst, unsigned RegNo, |
297 | | uint64_t Address, |
298 | | const void *Decoder); |
299 | | |
300 | | static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, uint32_t Insn, |
301 | | uint64_t Address, |
302 | | const void *Decoder); |
303 | | |
304 | | static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, |
305 | | uint64_t Address, |
306 | | const void *Decoder); |
307 | | |
308 | | static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, |
309 | | uint64_t Address, |
310 | | const void *Decoder); |
311 | | |
312 | | static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, |
313 | | uint64_t Address, |
314 | | const void *Decoder); |
315 | | |
316 | | static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, |
317 | | uint64_t Address, |
318 | | const void *Decoder); |
319 | | |
320 | | static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, |
321 | | uint64_t Address, |
322 | | const void *Decoder); |
323 | | |
324 | | static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, |
325 | | uint64_t Address, |
326 | | const void *Decoder); |
327 | | |
328 | | static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, uint32_t Insn, |
329 | | uint64_t Address, |
330 | | const void *Decoder); |
331 | | |
332 | | static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, |
333 | | uint64_t Address, |
334 | | const void *Decoder); |
335 | | |
336 | | static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, |
337 | | uint64_t Address, |
338 | | const void *Decoder); |
339 | | |
340 | | static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, |
341 | | uint64_t Address, |
342 | | const void *Decoder); |
343 | | |
344 | | static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, |
345 | | uint64_t Address, |
346 | | const void *Decoder); |
347 | | |
348 | | static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, |
349 | | uint64_t Address, |
350 | | const void *Decoder); |
351 | | |
352 | | static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, |
353 | | uint64_t Address, |
354 | | const void *Decoder); |
355 | | |
356 | | static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, |
357 | | uint64_t Address, |
358 | | const void *Decoder); |
359 | | |
360 | | static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, |
361 | | uint64_t Address, |
362 | | const void *Decoder); |
363 | | |
364 | | static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, |
365 | | uint64_t Address, |
366 | | const void *Decoder); |
367 | | |
368 | | static DecodeStatus DecodeCOP0RegisterClass(MCInst *Inst, unsigned RegNo, |
369 | | uint64_t Address, |
370 | | const void *Decoder); |
371 | | |
372 | | static DecodeStatus DecodeCOP0SelRegisterClass(MCInst *Inst, unsigned RegNo, |
373 | | uint64_t Address, |
374 | | const void *Decoder); |
375 | | |
376 | | static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, |
377 | | uint64_t Address, |
378 | | const void *Decoder); |
379 | | |
380 | | static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, |
381 | | uint64_t Address, const void *Decoder); |
382 | | |
383 | | static DecodeStatus DecodeBranchTarget1SImm16(MCInst *Inst, unsigned Offset, |
384 | | uint64_t Address, |
385 | | const void *Decoder); |
386 | | |
387 | | static DecodeStatus DecodeJumpTarget(MCInst *Inst, uint32_t Insn, |
388 | | uint64_t Address, const void *Decoder); |
389 | | |
390 | | static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, |
391 | | uint64_t Address, const void *Decoder); |
392 | | |
393 | | static DecodeStatus DecodeBranchTarget21MM(MCInst *Inst, unsigned Offset, |
394 | | uint64_t Address, |
395 | | const void *Decoder); |
396 | | |
397 | | static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, |
398 | | uint64_t Address, const void *Decoder); |
399 | | |
400 | | // DecodeBranchTarget7MM - Decode microMIPS branch offset, which is |
401 | | // shifted left by 1 bit. |
402 | | static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, |
403 | | uint64_t Address, |
404 | | const void *Decoder); |
405 | | |
406 | | // DecodeBranchTarget10MM - Decode microMIPS branch offset, which is |
407 | | // shifted left by 1 bit. |
408 | | static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, |
409 | | uint64_t Address, |
410 | | const void *Decoder); |
411 | | |
412 | | // DecodeBranchTargetMM - Decode microMIPS branch offset, which is |
413 | | // shifted left by 1 bit. |
414 | | static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, |
415 | | uint64_t Address, const void *Decoder); |
416 | | |
417 | | // DecodeBranchTarget26MM - Decode microMIPS branch offset, which is |
418 | | // shifted left by 1 bit. |
419 | | static DecodeStatus DecodeBranchTarget26MM(MCInst *Inst, unsigned Offset, |
420 | | uint64_t Address, |
421 | | const void *Decoder); |
422 | | |
423 | | // DecodeBranchTargetMM - Decode nanoMIPS branch offset, which is |
424 | | // shifted left by 1 bit. |
425 | | #define DECLARE_DecodeBranchTargetNM(bits) \ |
426 | | static DecodeStatus CONCAT(DecodeBranchTargetNM, bits)( \ |
427 | | MCInst * Inst, unsigned Offset, uint64_t Address, \ |
428 | | const void *Decoder); |
429 | | DECLARE_DecodeBranchTargetNM(10); |
430 | | DECLARE_DecodeBranchTargetNM(7); |
431 | | DECLARE_DecodeBranchTargetNM(21); |
432 | | DECLARE_DecodeBranchTargetNM(25); |
433 | | DECLARE_DecodeBranchTargetNM(14); |
434 | | DECLARE_DecodeBranchTargetNM(11); |
435 | | DECLARE_DecodeBranchTargetNM(5); |
436 | | |
437 | | // DecodeJumpTargetMM - Decode microMIPS jump target, which is |
438 | | // shifted left by 1 bit. |
439 | | static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, uint32_t Insn, |
440 | | uint64_t Address, const void *Decoder); |
441 | | |
442 | | // DecodeJumpTargetXMM - Decode microMIPS jump and link exchange target, |
443 | | // which is shifted left by 2 bit. |
444 | | static DecodeStatus DecodeJumpTargetXMM(MCInst *Inst, uint32_t Insn, |
445 | | uint64_t Address, const void *Decoder); |
446 | | |
447 | | static DecodeStatus DecodeMem(MCInst *Inst, uint32_t Insn, uint64_t Address, |
448 | | const void *Decoder); |
449 | | |
450 | | #define DECLARE_DecodeMemNM(Offbits, isSigned, rt) \ |
451 | | static DecodeStatus CONCAT(DecodeMemNM, \ |
452 | | CONCAT(Offbits, CONCAT(isSigned, rt)))( \ |
453 | | MCInst * Inst, uint32_t Insn, uint64_t Address, \ |
454 | | const void *Decoder); |
455 | | DECLARE_DecodeMemNM(6, 0, Mips_GPRNM3RegClassID); |
456 | | DECLARE_DecodeMemNM(7, 0, Mips_GPRNMSPRegClassID); |
457 | | DECLARE_DecodeMemNM(9, 0, Mips_GPRNMGPRegClassID); |
458 | | DECLARE_DecodeMemNM(2, 0, Mips_GPRNM3RegClassID); |
459 | | DECLARE_DecodeMemNM(3, 0, Mips_GPRNM3RegClassID); |
460 | | DECLARE_DecodeMemNM(21, 0, Mips_GPRNMGPRegClassID); |
461 | | DECLARE_DecodeMemNM(18, 0, Mips_GPRNMGPRegClassID); |
462 | | DECLARE_DecodeMemNM(12, 0, Mips_GPRNM32RegClassID); |
463 | | DECLARE_DecodeMemNM(9, 1, Mips_GPRNM32RegClassID); |
464 | | |
465 | | static DecodeStatus DecodeMemZeroNM(MCInst *Inst, uint32_t Insn, |
466 | | uint64_t Address, const void *Decoder); |
467 | | |
468 | | #define DECLARE_DecodeMemNMRX(rt) \ |
469 | | static DecodeStatus CONCAT(DecodeMemNMRX, \ |
470 | | rt)(MCInst * Inst, uint32_t Insn, \ |
471 | | uint64_t Address, const void *Decoder); |
472 | | DECLARE_DecodeMemNMRX(Mips_GPRNM3RegClassID); |
473 | | DECLARE_DecodeMemNMRX(Mips_GPRNM32RegClassID); |
474 | | |
475 | | static DecodeStatus DecodeMemNM4x4(MCInst *Inst, uint32_t Insn, |
476 | | uint64_t Address, const void *Decoder); |
477 | | |
478 | | static DecodeStatus DecodeMemEVA(MCInst *Inst, uint32_t Insn, uint64_t Address, |
479 | | const void *Decoder); |
480 | | |
481 | | static DecodeStatus DecodeLoadByte15(MCInst *Inst, uint32_t Insn, |
482 | | uint64_t Address, const void *Decoder); |
483 | | |
484 | | static DecodeStatus DecodeCacheOp(MCInst *Inst, uint32_t Insn, uint64_t Address, |
485 | | const void *Decoder); |
486 | | |
487 | | static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst *Inst, uint32_t Insn, |
488 | | uint64_t Address, |
489 | | const void *Decoder); |
490 | | |
491 | | static DecodeStatus DecodeCacheOpMM(MCInst *Inst, uint32_t Insn, |
492 | | uint64_t Address, const void *Decoder); |
493 | | |
494 | | static DecodeStatus DecodePrefeOpMM(MCInst *Inst, uint32_t Insn, |
495 | | uint64_t Address, const void *Decoder); |
496 | | |
497 | | static DecodeStatus DecodeSyncI(MCInst *Inst, uint32_t Insn, uint64_t Address, |
498 | | const void *Decoder); |
499 | | |
500 | | static DecodeStatus DecodeSyncI_MM(MCInst *Inst, uint32_t Insn, |
501 | | uint64_t Address, const void *Decoder); |
502 | | |
503 | | static DecodeStatus DecodeSynciR6(MCInst *Inst, uint32_t Insn, uint64_t Address, |
504 | | const void *Decoder); |
505 | | |
506 | | static DecodeStatus DecodeMSA128Mem(MCInst *Inst, uint32_t Insn, |
507 | | uint64_t Address, const void *Decoder); |
508 | | |
509 | | static DecodeStatus DecodeMemMMImm4(MCInst *Inst, uint32_t Insn, |
510 | | uint64_t Address, const void *Decoder); |
511 | | |
512 | | static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, uint32_t Insn, |
513 | | uint64_t Address, |
514 | | const void *Decoder); |
515 | | |
516 | | static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, uint32_t Insn, |
517 | | uint64_t Address, |
518 | | const void *Decoder); |
519 | | |
520 | | static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, uint32_t Insn, |
521 | | uint64_t Address, |
522 | | const void *Decoder); |
523 | | |
524 | | static DecodeStatus DecodeMemMMImm9(MCInst *Inst, uint32_t Insn, |
525 | | uint64_t Address, const void *Decoder); |
526 | | |
527 | | static DecodeStatus DecodeMemMMImm12(MCInst *Inst, uint32_t Insn, |
528 | | uint64_t Address, const void *Decoder); |
529 | | |
530 | | static DecodeStatus DecodeMemMMImm16(MCInst *Inst, uint32_t Insn, |
531 | | uint64_t Address, const void *Decoder); |
532 | | |
533 | | static DecodeStatus DecodeFMem(MCInst *Inst, uint32_t Insn, uint64_t Address, |
534 | | const void *Decoder); |
535 | | |
536 | | static DecodeStatus DecodeFMemMMR2(MCInst *Inst, uint32_t Insn, |
537 | | uint64_t Address, const void *Decoder); |
538 | | |
539 | | static DecodeStatus DecodeFMem2(MCInst *Inst, uint32_t Insn, uint64_t Address, |
540 | | const void *Decoder); |
541 | | |
542 | | static DecodeStatus DecodeFMem3(MCInst *Inst, uint32_t Insn, uint64_t Address, |
543 | | const void *Decoder); |
544 | | |
545 | | static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, uint32_t Insn, |
546 | | uint64_t Address, const void *Decoder); |
547 | | |
548 | | static DecodeStatus DecodeFMemCop2MMR6(MCInst *Inst, uint32_t Insn, |
549 | | uint64_t Address, const void *Decoder); |
550 | | |
551 | | static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, uint32_t Insn, |
552 | | uint64_t Address, const void *Decoder); |
553 | | |
554 | | static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, |
555 | | uint64_t Address, const void *Decoder); |
556 | | |
557 | | static DecodeStatus DecodeLi16Imm(MCInst *Inst, unsigned Value, |
558 | | uint64_t Address, const void *Decoder); |
559 | | |
560 | | static DecodeStatus DecodePOOL16BEncodedField(MCInst *Inst, unsigned Value, |
561 | | uint64_t Address, |
562 | | const void *Decoder); |
563 | | |
564 | | #define DECLARE_DecodeUImmWithOffsetAndScale(Bits, Offset, Scale) \ |
565 | | static DecodeStatus CONCAT(DecodeUImmWithOffsetAndScale, \ |
566 | | CONCAT(Bits, CONCAT(Offset, Scale)))( \ |
567 | | MCInst * Inst, unsigned Value, uint64_t Address, \ |
568 | | const void *Decoder); |
569 | | DECLARE_DecodeUImmWithOffsetAndScale(5, 0, 4); |
570 | | DECLARE_DecodeUImmWithOffsetAndScale(6, 0, 4); |
571 | | DECLARE_DecodeUImmWithOffsetAndScale(2, 1, 1); |
572 | | DECLARE_DecodeUImmWithOffsetAndScale(5, 1, 1); |
573 | | DECLARE_DecodeUImmWithOffsetAndScale(8, 0, 1); |
574 | | DECLARE_DecodeUImmWithOffsetAndScale(18, 0, 1); |
575 | | DECLARE_DecodeUImmWithOffsetAndScale(21, 0, 1); |
576 | | |
577 | | #define DEFINE_DecodeUImmWithOffset(Bits, Offset) \ |
578 | | static DecodeStatus CONCAT(DecodeUImmWithOffset, \ |
579 | | CONCAT(Bits, Offset))(MCInst * Inst, \ |
580 | | unsigned Value, \ |
581 | | uint64_t Address, \ |
582 | | const void *Decoder) \ |
583 | 962 | { \ |
584 | 962 | return CONCAT(DecodeUImmWithOffsetAndScale, \ |
585 | 962 | CONCAT(Bits, CONCAT(Offset, 1)))( \ |
586 | 962 | Inst, Value, Address, Decoder); \ |
587 | 962 | } MipsDisassembler.c:DecodeUImmWithOffset_5_1 Line | Count | Source | 583 | 429 | { \ | 584 | 429 | return CONCAT(DecodeUImmWithOffsetAndScale, \ | 585 | 429 | CONCAT(Bits, CONCAT(Offset, 1)))( \ | 586 | 429 | Inst, Value, Address, Decoder); \ | 587 | 429 | } |
MipsDisassembler.c:DecodeUImmWithOffset_2_1 Line | Count | Source | 583 | 533 | { \ | 584 | 533 | return CONCAT(DecodeUImmWithOffsetAndScale, \ | 585 | 533 | CONCAT(Bits, CONCAT(Offset, 1)))( \ | 586 | 533 | Inst, Value, Address, Decoder); \ | 587 | 533 | } |
|
588 | | DEFINE_DecodeUImmWithOffset(5, 1); |
589 | | DEFINE_DecodeUImmWithOffset(2, 1); |
590 | | |
591 | | #define DECLARE_DecodeSImmWithOffsetAndScale(Bits, Offset, ScaleBy) \ |
592 | | static DecodeStatus CONCAT(DecodeSImmWithOffsetAndScale, \ |
593 | | CONCAT(Bits, CONCAT(Offset, ScaleBy)))( \ |
594 | | MCInst * Inst, unsigned Value, uint64_t Address, \ |
595 | | const void *Decoder); |
596 | | |
597 | | #define DECLARE_DecodeSImmWithOffsetAndScale_2(Bits, Offset) \ |
598 | | DECLARE_DecodeSImmWithOffsetAndScale(Bits, Offset, 1) |
599 | | #define DECLARE_DecodeSImmWithOffsetAndScale_3(Bits) \ |
600 | | DECLARE_DecodeSImmWithOffsetAndScale(Bits, 0, 1) |
601 | | |
602 | | DECLARE_DecodeSImmWithOffsetAndScale_3(16); |
603 | | DECLARE_DecodeSImmWithOffsetAndScale_3(10); |
604 | | DECLARE_DecodeSImmWithOffsetAndScale_3(4); |
605 | | DECLARE_DecodeSImmWithOffsetAndScale_3(6); |
606 | | DECLARE_DecodeSImmWithOffsetAndScale_3(32); |
607 | | |
608 | | static DecodeStatus DecodeInsSize(MCInst *Inst, uint32_t Insn, uint64_t Address, |
609 | | const void *Decoder); |
610 | | |
611 | | static DecodeStatus DecodeImmM1To126(MCInst *Inst, unsigned Value, |
612 | | uint64_t Address, const void *Decoder); |
613 | | |
614 | | static DecodeStatus DecodeUImm4Mask(MCInst *Inst, unsigned Value, |
615 | | uint64_t Address, const void *Decoder); |
616 | | |
617 | | static DecodeStatus DecodeUImm3Shift(MCInst *Inst, unsigned Value, |
618 | | uint64_t Address, const void *Decoder); |
619 | | |
620 | | static DecodeStatus DecodeNMRegListOperand(MCInst *Inst, uint32_t Insn, |
621 | | uint64_t Address, |
622 | | const void *Decoder); |
623 | | |
624 | | static DecodeStatus DecodeNMRegList16Operand(MCInst *Inst, uint32_t Insn, |
625 | | uint64_t Address, |
626 | | const void *Decoder); |
627 | | |
628 | | static DecodeStatus DecodeNegImm12(MCInst *Inst, uint32_t Insn, |
629 | | uint64_t Address, const void *Decoder); |
630 | | |
631 | | #define DECLARE_DecodeSImmWithReg(Bits, Offset, Scale, RegNum) \ |
632 | | static DecodeStatus CONCAT( \ |
633 | | DecodeSImmWithReg, \ |
634 | | CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ |
635 | | MCInst * Inst, unsigned Value, uint64_t Address, \ |
636 | | const void *Decoder); |
637 | | DECLARE_DecodeSImmWithReg(32, 0, 1, Mips_GP_NM); |
638 | | |
639 | | #define DECLARE_DecodeUImmWithReg(Bits, Offset, Scale, RegNum) \ |
640 | | static DecodeStatus CONCAT( \ |
641 | | DecodeUImmWithReg, \ |
642 | | CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ |
643 | | MCInst * Inst, unsigned Value, uint64_t Address, \ |
644 | | const void *Decoder); |
645 | | DECLARE_DecodeUImmWithReg(8, 0, 1, Mips_SP_NM); |
646 | | DECLARE_DecodeUImmWithReg(21, 0, 1, Mips_GP_NM); |
647 | | DECLARE_DecodeUImmWithReg(18, 0, 1, Mips_GP_NM); |
648 | | |
649 | | static DecodeStatus DecodeSImm32s12(MCInst *Inst, uint32_t Insn, |
650 | | uint64_t Address, const void *Decoder); |
651 | | |
652 | | #define DECLARE_DecodeAddressPCRelNM(Bits) \ |
653 | | static DecodeStatus CONCAT(DecodeAddressPCRelNM, Bits)( \ |
654 | | MCInst * Inst, uint32_t Insn, uint64_t Address, \ |
655 | | const void *Decoder); |
656 | | DECLARE_DecodeAddressPCRelNM(22); |
657 | | DECLARE_DecodeAddressPCRelNM(32); |
658 | | |
659 | | static DecodeStatus DecodeBranchConflictNM(MCInst *Inst, uint32_t Insn, |
660 | | uint64_t Address, |
661 | | const void *Decoder); |
662 | | |
663 | | static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, uint32_t Insn, |
664 | | uint64_t Address, const void *Decoder); |
665 | | |
666 | | static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, uint32_t Insn, |
667 | | uint64_t Address, const void *Decoder); |
668 | | |
669 | | static DecodeStatus DecodeSimm9SP(MCInst *Inst, uint32_t Insn, uint64_t Address, |
670 | | const void *Decoder); |
671 | | |
672 | | static DecodeStatus DecodeANDI16Imm(MCInst *Inst, uint32_t Insn, |
673 | | uint64_t Address, const void *Decoder); |
674 | | |
675 | | static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, uint32_t Insn, |
676 | | uint64_t Address, const void *Decoder); |
677 | | |
678 | | /// INSVE_[BHWD] have an implicit operand that the generated decoder doesn't |
679 | | /// handle. |
680 | | static DecodeStatus DecodeINSVE_DF(MCInst *MI, uint32_t insn, uint64_t Address, |
681 | | const void *Decoder); |
682 | | |
683 | | /* |
684 | | static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, uint32_t insn, |
685 | | uint64_t Address, const void *Decoder); |
686 | | */ |
687 | | |
688 | | static DecodeStatus DecodeDAHIDATI(MCInst *MI, uint32_t insn, uint64_t Address, |
689 | | const void *Decoder); |
690 | | |
691 | | static DecodeStatus DecodeAddiGroupBranch(MCInst *MI, uint32_t insn, |
692 | | uint64_t Address, |
693 | | const void *Decoder); |
694 | | |
695 | | static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst *MI, uint32_t insn, |
696 | | uint64_t Address, |
697 | | const void *Decoder); |
698 | | |
699 | | static DecodeStatus DecodeDaddiGroupBranch(MCInst *MI, uint32_t insn, |
700 | | uint64_t Address, |
701 | | const void *Decoder); |
702 | | |
703 | | static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst *MI, uint32_t insn, |
704 | | uint64_t Address, |
705 | | const void *Decoder); |
706 | | |
707 | | static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst *MI, uint32_t insn, |
708 | | uint64_t Address, |
709 | | const void *Decoder); |
710 | | |
711 | | static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst *MI, uint32_t insn, |
712 | | uint64_t Address, |
713 | | const void *Decoder); |
714 | | |
715 | | static DecodeStatus DecodeBlezlGroupBranch(MCInst *MI, uint32_t insn, |
716 | | uint64_t Address, |
717 | | const void *Decoder); |
718 | | |
719 | | static DecodeStatus DecodeBgtzlGroupBranch(MCInst *MI, uint32_t insn, |
720 | | uint64_t Address, |
721 | | const void *Decoder); |
722 | | |
723 | | static DecodeStatus DecodeBgtzGroupBranch(MCInst *MI, uint32_t insn, |
724 | | uint64_t Address, |
725 | | const void *Decoder); |
726 | | |
727 | | static DecodeStatus DecodeBlezGroupBranch(MCInst *MI, uint32_t insn, |
728 | | uint64_t Address, |
729 | | const void *Decoder); |
730 | | |
731 | | static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst *MI, uint32_t insn, |
732 | | uint64_t Address, |
733 | | const void *Decoder); |
734 | | |
735 | | static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst *MI, uint32_t insn, |
736 | | uint64_t Address, |
737 | | const void *Decoder); |
738 | | |
739 | | static DecodeStatus DecodeDINS(MCInst *MI, uint32_t Insn, uint64_t Address, |
740 | | const void *Decoder); |
741 | | |
742 | | static DecodeStatus DecodeDEXT(MCInst *MI, uint32_t Insn, uint64_t Address, |
743 | | const void *Decoder); |
744 | | |
745 | | static DecodeStatus DecodeCRC(MCInst *MI, uint32_t Insn, uint64_t Address, |
746 | | const void *Decoder); |
747 | | |
748 | | static DecodeStatus DecodeRegListOperand(MCInst *Inst, uint32_t Insn, |
749 | | uint64_t Address, const void *Decoder); |
750 | | |
751 | | static DecodeStatus DecodeRegListOperand16(MCInst *Inst, uint32_t Insn, |
752 | | uint64_t Address, |
753 | | const void *Decoder); |
754 | | |
755 | | static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned RegPair, |
756 | | uint64_t Address, const void *Decoder); |
757 | | |
758 | | static DecodeStatus DecodeMovePOperands(MCInst *Inst, uint32_t Insn, |
759 | | uint64_t Address, const void *Decoder); |
760 | | |
761 | | static DecodeStatus DecodeFIXMEInstruction(MCInst *Inst, uint32_t Insn, |
762 | | uint64_t Address, |
763 | | const void *Decoder); |
764 | | |
765 | | #include "MipsGenDisassemblerTables.inc" |
766 | | |
767 | | static unsigned getReg(const MCInst *Inst, unsigned RC, unsigned RegNo) |
768 | 458k | { |
769 | 458k | const MCRegisterClass *c = MCRegisterInfo_getRegClass(Inst->MRI, RC); |
770 | 458k | return MCRegisterClass_getRegister(c, RegNo); |
771 | 458k | } |
772 | | |
773 | | typedef DecodeStatus (*DecodeFN)(MCInst *Inst, uint32_t Insn, uint64_t Address, |
774 | | const void *Decoder); |
775 | | |
776 | | static DecodeStatus DecodeINSVE_DF(MCInst *MI, uint32_t insn, uint64_t Address, |
777 | | const void *Decoder) |
778 | 770 | { |
779 | | // The size of the n field depends on the element size |
780 | | // The register class also depends on this. |
781 | 770 | uint32_t tmp = fieldFromInstruction_4(insn, 17, 5); |
782 | 770 | unsigned NSize = 0; |
783 | 770 | DecodeFN RegDecoder = NULL; |
784 | 770 | if ((tmp & 0x18) == 0x00) { // INSVE_B |
785 | 196 | NSize = 4; |
786 | 196 | RegDecoder = DecodeMSA128BRegisterClass; |
787 | 574 | } else if ((tmp & 0x1c) == 0x10) { // INSVE_H |
788 | 271 | NSize = 3; |
789 | 271 | RegDecoder = DecodeMSA128HRegisterClass; |
790 | 303 | } else if ((tmp & 0x1e) == 0x18) { // INSVE_W |
791 | 255 | NSize = 2; |
792 | 255 | RegDecoder = DecodeMSA128WRegisterClass; |
793 | 255 | } else if ((tmp & 0x1f) == 0x1c) { // INSVE_D |
794 | 48 | NSize = 1; |
795 | 48 | RegDecoder = DecodeMSA128DRegisterClass; |
796 | 48 | } else { |
797 | 0 | CS_ASSERT_RET_VAL(0 && "Invalid encoding", MCDisassembler_Fail); |
798 | 0 | return MCDisassembler_Fail; |
799 | 0 | } |
800 | | |
801 | | // $wd |
802 | 770 | tmp = fieldFromInstruction_4(insn, 6, 5); |
803 | 770 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) |
804 | 0 | return MCDisassembler_Fail; |
805 | | // $wd_in |
806 | 770 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) |
807 | 0 | return MCDisassembler_Fail; |
808 | | // $n |
809 | 770 | tmp = fieldFromInstruction_4(insn, 16, NSize); |
810 | 770 | MCOperand_CreateImm0(MI, (tmp)); |
811 | | // $ws |
812 | 770 | tmp = fieldFromInstruction_4(insn, 11, 5); |
813 | 770 | if (RegDecoder(MI, tmp, Address, Decoder) == MCDisassembler_Fail) |
814 | 0 | return MCDisassembler_Fail; |
815 | | // $n2 |
816 | 770 | MCOperand_CreateImm0(MI, (0)); |
817 | | |
818 | 770 | return MCDisassembler_Success; |
819 | 770 | } |
820 | | |
821 | | /* |
822 | | static DecodeStatus DecodeDAHIDATIMMR6(MCInst *MI, uint32_t insn, |
823 | | uint64_t Address, const void *Decoder) |
824 | | { |
825 | | uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); |
826 | | uint32_t Imm = fieldFromInstruction_4(insn, 0, 16); |
827 | | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); |
828 | | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); |
829 | | MCOperand_CreateImm0(MI, (Imm)); |
830 | | |
831 | | return MCDisassembler_Success; |
832 | | } |
833 | | */ |
834 | | |
835 | | static DecodeStatus DecodeDAHIDATI(MCInst *MI, uint32_t insn, uint64_t Address, |
836 | | const void *Decoder) |
837 | 0 | { |
838 | 0 | uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); |
839 | 0 | uint32_t Imm = fieldFromInstruction_4(insn, 0, 16); |
840 | 0 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); |
841 | 0 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); |
842 | 0 | MCOperand_CreateImm0(MI, (Imm)); |
843 | |
|
844 | 0 | return MCDisassembler_Success; |
845 | 0 | } |
846 | | |
847 | | static DecodeStatus DecodeAddiGroupBranch(MCInst *MI, uint32_t insn, |
848 | | uint64_t Address, const void *Decoder) |
849 | 1.51k | { |
850 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
851 | | // (otherwise we would have matched the ADDI instruction from the earlier |
852 | | // ISA's instead). |
853 | | // |
854 | | // We have: |
855 | | // 0b001000 sssss ttttt iiiiiiiiiiiiiiii |
856 | | // BOVC if rs >= rt |
857 | | // BEQZALC if rs == 0 && rt != 0 |
858 | | // BEQC if rs < rt && rs != 0 |
859 | | |
860 | 1.51k | uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); |
861 | 1.51k | uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); |
862 | 1.51k | int64_t Imm = |
863 | 1.51k | SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; |
864 | 1.51k | bool HasRs = false; |
865 | | |
866 | 1.51k | if (Rs >= Rt) { |
867 | 651 | MCInst_setOpcode(MI, (Mips_BOVC)); |
868 | 651 | HasRs = true; |
869 | 863 | } else if (Rs != 0 && Rs < Rt) { |
870 | 440 | MCInst_setOpcode(MI, (Mips_BEQC)); |
871 | 440 | HasRs = true; |
872 | 440 | } else |
873 | 423 | MCInst_setOpcode(MI, (Mips_BEQZALC)); |
874 | | |
875 | 1.51k | if (HasRs) |
876 | 1.09k | MCOperand_CreateReg0(MI, |
877 | 1.09k | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
878 | | |
879 | 1.51k | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); |
880 | 1.51k | MCOperand_CreateImm0(MI, (Imm)); |
881 | | |
882 | 1.51k | return MCDisassembler_Success; |
883 | 1.51k | } |
884 | | |
885 | | static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst *MI, uint32_t insn, |
886 | | uint64_t Address, |
887 | | const void *Decoder) |
888 | 849 | { |
889 | 849 | uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); |
890 | 849 | uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); |
891 | 849 | int64_t Imm = 0; |
892 | | |
893 | 849 | if (Rs >= Rt) { |
894 | 263 | MCInst_setOpcode(MI, (Mips_BOVC_MMR6)); |
895 | 263 | MCOperand_CreateReg0(MI, |
896 | 263 | (getReg(MI, Mips_GPR32RegClassID, Rt))); |
897 | 263 | MCOperand_CreateReg0(MI, |
898 | 263 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
899 | 263 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
900 | 263 | 2 + |
901 | 263 | 4; |
902 | 586 | } else if (Rs != 0 && Rs < Rt) { |
903 | 391 | MCInst_setOpcode(MI, (Mips_BEQC_MMR6)); |
904 | 391 | MCOperand_CreateReg0(MI, |
905 | 391 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
906 | 391 | MCOperand_CreateReg0(MI, |
907 | 391 | (getReg(MI, Mips_GPR32RegClassID, Rt))); |
908 | 391 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
909 | 391 | 4 + |
910 | 391 | 4; |
911 | 391 | } else { |
912 | 195 | MCInst_setOpcode(MI, (Mips_BEQZALC_MMR6)); |
913 | 195 | MCOperand_CreateReg0(MI, |
914 | 195 | (getReg(MI, Mips_GPR32RegClassID, Rt))); |
915 | 195 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
916 | 195 | 2 + |
917 | 195 | 4; |
918 | 195 | } |
919 | | |
920 | 849 | MCOperand_CreateImm0(MI, (Imm)); |
921 | | |
922 | 849 | return MCDisassembler_Success; |
923 | 849 | } |
924 | | |
925 | | static DecodeStatus DecodeDaddiGroupBranch(MCInst *MI, uint32_t insn, |
926 | | uint64_t Address, |
927 | | const void *Decoder) |
928 | 589 | { |
929 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
930 | | // (otherwise we would have matched the ADDI instruction from the earlier |
931 | | // ISA's instead). |
932 | | // |
933 | | // We have: |
934 | | // 0b011000 sssss ttttt iiiiiiiiiiiiiiii |
935 | | // BNVC if rs >= rt |
936 | | // BNEZALC if rs == 0 && rt != 0 |
937 | | // BNEC if rs < rt && rs != 0 |
938 | | |
939 | 589 | uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); |
940 | 589 | uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); |
941 | 589 | int64_t Imm = |
942 | 589 | SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; |
943 | 589 | bool HasRs = false; |
944 | | |
945 | 589 | if (Rs >= Rt) { |
946 | 286 | MCInst_setOpcode(MI, (Mips_BNVC)); |
947 | 286 | HasRs = true; |
948 | 303 | } else if (Rs != 0 && Rs < Rt) { |
949 | 236 | MCInst_setOpcode(MI, (Mips_BNEC)); |
950 | 236 | HasRs = true; |
951 | 236 | } else |
952 | 67 | MCInst_setOpcode(MI, (Mips_BNEZALC)); |
953 | | |
954 | 589 | if (HasRs) |
955 | 522 | MCOperand_CreateReg0(MI, |
956 | 522 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
957 | | |
958 | 589 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); |
959 | 589 | MCOperand_CreateImm0(MI, (Imm)); |
960 | | |
961 | 589 | return MCDisassembler_Success; |
962 | 589 | } |
963 | | |
964 | | static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst *MI, uint32_t insn, |
965 | | uint64_t Address, |
966 | | const void *Decoder) |
967 | 1.06k | { |
968 | 1.06k | uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); |
969 | 1.06k | uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); |
970 | 1.06k | int64_t Imm = 0; |
971 | | |
972 | 1.06k | if (Rs >= Rt) { |
973 | 260 | MCInst_setOpcode(MI, (Mips_BNVC_MMR6)); |
974 | 260 | MCOperand_CreateReg0(MI, |
975 | 260 | (getReg(MI, Mips_GPR32RegClassID, Rt))); |
976 | 260 | MCOperand_CreateReg0(MI, |
977 | 260 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
978 | 260 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
979 | 260 | 2 + |
980 | 260 | 4; |
981 | 801 | } else if (Rs != 0 && Rs < Rt) { |
982 | 591 | MCInst_setOpcode(MI, (Mips_BNEC_MMR6)); |
983 | 591 | MCOperand_CreateReg0(MI, |
984 | 591 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
985 | 591 | MCOperand_CreateReg0(MI, |
986 | 591 | (getReg(MI, Mips_GPR32RegClassID, Rt))); |
987 | 591 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
988 | 591 | 4 + |
989 | 591 | 4; |
990 | 591 | } else { |
991 | 210 | MCInst_setOpcode(MI, (Mips_BNEZALC_MMR6)); |
992 | 210 | MCOperand_CreateReg0(MI, |
993 | 210 | (getReg(MI, Mips_GPR32RegClassID, Rt))); |
994 | 210 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
995 | 210 | 2 + |
996 | 210 | 4; |
997 | 210 | } |
998 | | |
999 | 1.06k | MCOperand_CreateImm0(MI, (Imm)); |
1000 | | |
1001 | 1.06k | return MCDisassembler_Success; |
1002 | 1.06k | } |
1003 | | |
1004 | | static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst *MI, uint32_t insn, |
1005 | | uint64_t Address, |
1006 | | const void *Decoder) |
1007 | 775 | { |
1008 | | // We have: |
1009 | | // 0b110101 ttttt sssss iiiiiiiiiiiiiiii |
1010 | | // Invalid if rt == 0 |
1011 | | // BGTZC_MMR6 if rs == 0 && rt != 0 |
1012 | | // BLTZC_MMR6 if rs == rt && rt != 0 |
1013 | | // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 |
1014 | | |
1015 | 775 | uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); |
1016 | 775 | uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); |
1017 | 775 | int64_t Imm = |
1018 | 775 | SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; |
1019 | 775 | bool HasRs = false; |
1020 | | |
1021 | 775 | if (Rt == 0) |
1022 | 1 | return MCDisassembler_Fail; |
1023 | 774 | else if (Rs == 0) |
1024 | 282 | MCInst_setOpcode(MI, (Mips_BGTZC_MMR6)); |
1025 | 492 | else if (Rs == Rt) |
1026 | 230 | MCInst_setOpcode(MI, (Mips_BLTZC_MMR6)); |
1027 | 262 | else { |
1028 | 262 | MCInst_setOpcode(MI, (Mips_BLTC_MMR6)); |
1029 | 262 | HasRs = true; |
1030 | 262 | } |
1031 | | |
1032 | 774 | if (HasRs) |
1033 | 262 | MCOperand_CreateReg0(MI, |
1034 | 262 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
1035 | | |
1036 | 774 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); |
1037 | | |
1038 | 774 | MCOperand_CreateImm0(MI, (Imm)); |
1039 | | |
1040 | 774 | return MCDisassembler_Success; |
1041 | 775 | } |
1042 | | |
1043 | | static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst *MI, uint32_t insn, |
1044 | | uint64_t Address, |
1045 | | const void *Decoder) |
1046 | 876 | { |
1047 | | // We have: |
1048 | | // 0b111101 ttttt sssss iiiiiiiiiiiiiiii |
1049 | | // Invalid if rt == 0 |
1050 | | // BLEZC_MMR6 if rs == 0 && rt != 0 |
1051 | | // BGEZC_MMR6 if rs == rt && rt != 0 |
1052 | | // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 |
1053 | | |
1054 | 876 | uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); |
1055 | 876 | uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); |
1056 | 876 | int64_t Imm = |
1057 | 876 | SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; |
1058 | 876 | bool HasRs = false; |
1059 | | |
1060 | 876 | if (Rt == 0) |
1061 | 1 | return MCDisassembler_Fail; |
1062 | 875 | else if (Rs == 0) |
1063 | 474 | MCInst_setOpcode(MI, (Mips_BLEZC_MMR6)); |
1064 | 401 | else if (Rs == Rt) |
1065 | 196 | MCInst_setOpcode(MI, (Mips_BGEZC_MMR6)); |
1066 | 205 | else { |
1067 | 205 | HasRs = true; |
1068 | 205 | MCInst_setOpcode(MI, (Mips_BGEC_MMR6)); |
1069 | 205 | } |
1070 | | |
1071 | 875 | if (HasRs) |
1072 | 205 | MCOperand_CreateReg0(MI, |
1073 | 205 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
1074 | | |
1075 | 875 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); |
1076 | | |
1077 | 875 | MCOperand_CreateImm0(MI, (Imm)); |
1078 | | |
1079 | 875 | return MCDisassembler_Success; |
1080 | 876 | } |
1081 | | |
1082 | | static DecodeStatus DecodeBlezlGroupBranch(MCInst *MI, uint32_t insn, |
1083 | | uint64_t Address, |
1084 | | const void *Decoder) |
1085 | 443 | { |
1086 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
1087 | | // (otherwise we would have matched the BLEZL instruction from the earlier |
1088 | | // ISA's instead). |
1089 | | // |
1090 | | // We have: |
1091 | | // 0b010110 sssss ttttt iiiiiiiiiiiiiiii |
1092 | | // Invalid if rs == 0 |
1093 | | // BLEZC if rs == 0 && rt != 0 |
1094 | | // BGEZC if rs == rt && rt != 0 |
1095 | | // BGEC if rs != rt && rs != 0 && rt != 0 |
1096 | | |
1097 | 443 | uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); |
1098 | 443 | uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); |
1099 | 443 | int64_t Imm = |
1100 | 443 | SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; |
1101 | 443 | bool HasRs = false; |
1102 | | |
1103 | 443 | if (Rt == 0) |
1104 | 10 | return MCDisassembler_Fail; |
1105 | 433 | else if (Rs == 0) |
1106 | 69 | MCInst_setOpcode(MI, (Mips_BLEZC)); |
1107 | 364 | else if (Rs == Rt) |
1108 | 105 | MCInst_setOpcode(MI, (Mips_BGEZC)); |
1109 | 259 | else { |
1110 | 259 | HasRs = true; |
1111 | 259 | MCInst_setOpcode(MI, (Mips_BGEC)); |
1112 | 259 | } |
1113 | | |
1114 | 433 | if (HasRs) |
1115 | 259 | MCOperand_CreateReg0(MI, |
1116 | 259 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
1117 | | |
1118 | 433 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); |
1119 | | |
1120 | 433 | MCOperand_CreateImm0(MI, (Imm)); |
1121 | | |
1122 | 433 | return MCDisassembler_Success; |
1123 | 443 | } |
1124 | | |
1125 | | static DecodeStatus DecodeBgtzlGroupBranch(MCInst *MI, uint32_t insn, |
1126 | | uint64_t Address, |
1127 | | const void *Decoder) |
1128 | 474 | { |
1129 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
1130 | | // (otherwise we would have matched the BGTZL instruction from the earlier |
1131 | | // ISA's instead). |
1132 | | // |
1133 | | // We have: |
1134 | | // 0b010111 sssss ttttt iiiiiiiiiiiiiiii |
1135 | | // Invalid if rs == 0 |
1136 | | // BGTZC if rs == 0 && rt != 0 |
1137 | | // BLTZC if rs == rt && rt != 0 |
1138 | | // BLTC if rs != rt && rs != 0 && rt != 0 |
1139 | | |
1140 | 474 | bool HasRs = false; |
1141 | | |
1142 | 474 | uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); |
1143 | 474 | uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); |
1144 | 474 | int64_t Imm = |
1145 | 474 | SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; |
1146 | | |
1147 | 474 | if (Rt == 0) |
1148 | 6 | return MCDisassembler_Fail; |
1149 | 468 | else if (Rs == 0) |
1150 | 68 | MCInst_setOpcode(MI, (Mips_BGTZC)); |
1151 | 400 | else if (Rs == Rt) |
1152 | 34 | MCInst_setOpcode(MI, (Mips_BLTZC)); |
1153 | 366 | else { |
1154 | 366 | MCInst_setOpcode(MI, (Mips_BLTC)); |
1155 | 366 | HasRs = true; |
1156 | 366 | } |
1157 | | |
1158 | 468 | if (HasRs) |
1159 | 366 | MCOperand_CreateReg0(MI, |
1160 | 366 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
1161 | | |
1162 | 468 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); |
1163 | | |
1164 | 468 | MCOperand_CreateImm0(MI, (Imm)); |
1165 | | |
1166 | 468 | return MCDisassembler_Success; |
1167 | 474 | } |
1168 | | |
1169 | | static DecodeStatus DecodeBgtzGroupBranch(MCInst *MI, uint32_t insn, |
1170 | | uint64_t Address, const void *Decoder) |
1171 | 805 | { |
1172 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
1173 | | // (otherwise we would have matched the BGTZ instruction from the earlier |
1174 | | // ISA's instead). |
1175 | | // |
1176 | | // We have: |
1177 | | // 0b000111 sssss ttttt iiiiiiiiiiiiiiii |
1178 | | // BGTZ if rt == 0 |
1179 | | // BGTZALC if rs == 0 && rt != 0 |
1180 | | // BLTZALC if rs != 0 && rs == rt |
1181 | | // BLTUC if rs != 0 && rs != rt |
1182 | | |
1183 | 805 | uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); |
1184 | 805 | uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); |
1185 | 805 | int64_t Imm = |
1186 | 805 | SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; |
1187 | 805 | bool HasRs = false; |
1188 | 805 | bool HasRt = false; |
1189 | | |
1190 | 805 | if (Rt == 0) { |
1191 | 206 | MCInst_setOpcode(MI, (Mips_BGTZ)); |
1192 | 206 | HasRs = true; |
1193 | 599 | } else if (Rs == 0) { |
1194 | 201 | MCInst_setOpcode(MI, (Mips_BGTZALC)); |
1195 | 201 | HasRt = true; |
1196 | 398 | } else if (Rs == Rt) { |
1197 | 103 | MCInst_setOpcode(MI, (Mips_BLTZALC)); |
1198 | 103 | HasRs = true; |
1199 | 295 | } else { |
1200 | 295 | MCInst_setOpcode(MI, (Mips_BLTUC)); |
1201 | 295 | HasRs = true; |
1202 | 295 | HasRt = true; |
1203 | 295 | } |
1204 | | |
1205 | 805 | if (HasRs) |
1206 | 604 | MCOperand_CreateReg0(MI, |
1207 | 604 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
1208 | | |
1209 | 805 | if (HasRt) |
1210 | 496 | MCOperand_CreateReg0(MI, |
1211 | 496 | (getReg(MI, Mips_GPR32RegClassID, Rt))); |
1212 | | |
1213 | 805 | MCOperand_CreateImm0(MI, (Imm)); |
1214 | | |
1215 | 805 | return MCDisassembler_Success; |
1216 | 805 | } |
1217 | | |
1218 | | static DecodeStatus DecodeBlezGroupBranch(MCInst *MI, uint32_t insn, |
1219 | | uint64_t Address, const void *Decoder) |
1220 | 1.26k | { |
1221 | | // If we are called then we can assume that MIPS32r6/MIPS64r6 is enabled |
1222 | | // (otherwise we would have matched the BLEZL instruction from the earlier |
1223 | | // ISA's instead). |
1224 | | // |
1225 | | // We have: |
1226 | | // 0b000110 sssss ttttt iiiiiiiiiiiiiiii |
1227 | | // Invalid if rs == 0 |
1228 | | // BLEZALC if rs == 0 && rt != 0 |
1229 | | // BGEZALC if rs == rt && rt != 0 |
1230 | | // BGEUC if rs != rt && rs != 0 && rt != 0 |
1231 | | |
1232 | 1.26k | uint32_t Rs = fieldFromInstruction_4(insn, 21, 5); |
1233 | 1.26k | uint32_t Rt = fieldFromInstruction_4(insn, 16, 5); |
1234 | 1.26k | int64_t Imm = |
1235 | 1.26k | SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * 4 + 4; |
1236 | 1.26k | bool HasRs = false; |
1237 | | |
1238 | 1.26k | if (Rt == 0) |
1239 | 256 | return MCDisassembler_Fail; |
1240 | 1.00k | else if (Rs == 0) |
1241 | 549 | MCInst_setOpcode(MI, (Mips_BLEZALC)); |
1242 | 459 | else if (Rs == Rt) |
1243 | 67 | MCInst_setOpcode(MI, (Mips_BGEZALC)); |
1244 | 392 | else { |
1245 | 392 | HasRs = true; |
1246 | 392 | MCInst_setOpcode(MI, (Mips_BGEUC)); |
1247 | 392 | } |
1248 | | |
1249 | 1.00k | if (HasRs) |
1250 | 392 | MCOperand_CreateReg0(MI, |
1251 | 392 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
1252 | 1.00k | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); |
1253 | | |
1254 | 1.00k | MCOperand_CreateImm0(MI, (Imm)); |
1255 | | |
1256 | 1.00k | return MCDisassembler_Success; |
1257 | 1.26k | } |
1258 | | |
1259 | | // Override the generated disassembler to produce DEXT all the time. This is |
1260 | | // for feature / behaviour parity with binutils. |
1261 | | static DecodeStatus DecodeDEXT(MCInst *MI, uint32_t Insn, uint64_t Address, |
1262 | | const void *Decoder) |
1263 | 0 | { |
1264 | 0 | unsigned Msbd = fieldFromInstruction_4(Insn, 11, 5); |
1265 | 0 | unsigned Lsb = fieldFromInstruction_4(Insn, 6, 5); |
1266 | 0 | unsigned Size = 0; |
1267 | 0 | unsigned Pos = 0; |
1268 | |
|
1269 | 0 | switch (MCInst_getOpcode(MI)) { |
1270 | 0 | case Mips_DEXT: |
1271 | 0 | Pos = Lsb; |
1272 | 0 | Size = Msbd + 1; |
1273 | 0 | break; |
1274 | 0 | case Mips_DEXTM: |
1275 | 0 | Pos = Lsb; |
1276 | 0 | Size = Msbd + 1 + 32; |
1277 | 0 | break; |
1278 | 0 | case Mips_DEXTU: |
1279 | 0 | Pos = Lsb + 32; |
1280 | 0 | Size = Msbd + 1; |
1281 | 0 | break; |
1282 | 0 | default: |
1283 | 0 | CS_ASSERT_RET_VAL(0 && "Unknown DEXT instruction!", |
1284 | 0 | MCDisassembler_Fail); |
1285 | 0 | return MCDisassembler_Fail; |
1286 | 0 | } |
1287 | | |
1288 | 0 | MCInst_setOpcode(MI, (Mips_DEXT)); |
1289 | |
|
1290 | 0 | uint32_t Rs = fieldFromInstruction_4(Insn, 21, 5); |
1291 | 0 | uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); |
1292 | |
|
1293 | 0 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rt))); |
1294 | 0 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); |
1295 | 0 | MCOperand_CreateImm0(MI, (Pos)); |
1296 | 0 | MCOperand_CreateImm0(MI, (Size)); |
1297 | |
|
1298 | 0 | return MCDisassembler_Success; |
1299 | 0 | } |
1300 | | |
1301 | | // Override the generated disassembler to produce DINS all the time. This is |
1302 | | // for feature / behaviour parity with binutils. |
1303 | | static DecodeStatus DecodeDINS(MCInst *MI, uint32_t Insn, uint64_t Address, |
1304 | | const void *Decoder) |
1305 | 0 | { |
1306 | 0 | unsigned Msbd = fieldFromInstruction_4(Insn, 11, 5); |
1307 | 0 | unsigned Lsb = fieldFromInstruction_4(Insn, 6, 5); |
1308 | 0 | unsigned Size = 0; |
1309 | 0 | unsigned Pos = 0; |
1310 | |
|
1311 | 0 | switch (MCInst_getOpcode(MI)) { |
1312 | 0 | case Mips_DINS: |
1313 | 0 | Pos = Lsb; |
1314 | 0 | Size = Msbd + 1 - Pos; |
1315 | 0 | break; |
1316 | 0 | case Mips_DINSM: |
1317 | 0 | Pos = Lsb; |
1318 | 0 | Size = Msbd + 33 - Pos; |
1319 | 0 | break; |
1320 | 0 | case Mips_DINSU: |
1321 | 0 | Pos = Lsb + 32; |
1322 | | // mbsd = pos + size - 33 |
1323 | | // mbsd - pos + 33 = size |
1324 | 0 | Size = Msbd + 33 - Pos; |
1325 | 0 | break; |
1326 | 0 | default: |
1327 | 0 | CS_ASSERT_RET_VAL(0 && "Unknown DINS instruction!", |
1328 | 0 | MCDisassembler_Fail); |
1329 | 0 | return MCDisassembler_Fail; |
1330 | 0 | } |
1331 | | |
1332 | 0 | uint32_t Rs = fieldFromInstruction_4(Insn, 21, 5); |
1333 | 0 | uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); |
1334 | |
|
1335 | 0 | MCInst_setOpcode(MI, (Mips_DINS)); |
1336 | 0 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rt))); |
1337 | 0 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR64RegClassID, Rs))); |
1338 | 0 | MCOperand_CreateImm0(MI, (Pos)); |
1339 | 0 | MCOperand_CreateImm0(MI, (Size)); |
1340 | |
|
1341 | 0 | return MCDisassembler_Success; |
1342 | 0 | } |
1343 | | |
1344 | | // Auto-generated decoder wouldn't add the third operand for CRC32*. |
1345 | | static DecodeStatus DecodeCRC(MCInst *MI, uint32_t Insn, uint64_t Address, |
1346 | | const void *Decoder) |
1347 | 247 | { |
1348 | 247 | uint32_t Rs = fieldFromInstruction_4(Insn, 21, 5); |
1349 | 247 | uint32_t Rt = fieldFromInstruction_4(Insn, 16, 5); |
1350 | 247 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); |
1351 | 247 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rs))); |
1352 | 247 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); |
1353 | 247 | return MCDisassembler_Success; |
1354 | 247 | } |
1355 | | |
1356 | | /// Read two bytes from the ArrayRef and return 16 bit halfword sorted |
1357 | | /// according to the given endianness. |
1358 | | static DecodeStatus readInstruction16(const uint8_t *Bytes, size_t BytesLen, |
1359 | | uint64_t Address, uint64_t *Size, |
1360 | | uint64_t *Insn, bool IsBigEndian) |
1361 | 63.6k | { |
1362 | | // We want to read exactly 2 Bytes of data. |
1363 | 63.6k | if (BytesLen < 2) { |
1364 | 323 | *Size = 0; |
1365 | 323 | return MCDisassembler_Fail; |
1366 | 323 | } |
1367 | | |
1368 | 63.2k | if (IsBigEndian) { |
1369 | 18.2k | *Insn = (Bytes[0] << 8) | Bytes[1]; |
1370 | 44.9k | } else { |
1371 | 44.9k | *Insn = (Bytes[1] << 8) | Bytes[0]; |
1372 | 44.9k | } |
1373 | | |
1374 | 63.2k | return MCDisassembler_Success; |
1375 | 63.6k | } |
1376 | | |
1377 | | /// Read four bytes from the ArrayRef and return 32 bit word sorted |
1378 | | /// according to the given endianness. |
1379 | | static DecodeStatus readInstruction32(const uint8_t *Bytes, size_t BytesLen, |
1380 | | uint64_t Address, uint64_t *Size, |
1381 | | uint64_t *Insn, bool IsBigEndian, |
1382 | | bool IsMicroMips) |
1383 | 112k | { |
1384 | | // We want to read exactly 4 Bytes of data. |
1385 | 112k | if (BytesLen < 4) { |
1386 | 1.10k | *Size = 0; |
1387 | 1.10k | return MCDisassembler_Fail; |
1388 | 1.10k | } |
1389 | | |
1390 | | // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) |
1391 | | // always precede the low 16 bits in the instruction stream (that is, they |
1392 | | // are placed at lower addresses in the instruction stream). |
1393 | | // |
1394 | | // microMIPS byte ordering: |
1395 | | // Big-endian: 0 | 1 | 2 | 3 |
1396 | | // Little-endian: 1 | 0 | 3 | 2 |
1397 | | |
1398 | 111k | if (IsBigEndian) { |
1399 | | // Encoded as a big-endian 32-bit word in the stream. |
1400 | 45.3k | *Insn = (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) | |
1401 | 45.3k | ((unsigned)Bytes[0] << 24); |
1402 | 65.8k | } else { |
1403 | 65.8k | if (IsMicroMips) { |
1404 | 28.8k | *Insn = (Bytes[2] << 0) | (Bytes[3] << 8) | |
1405 | 28.8k | (Bytes[0] << 16) | ((unsigned)Bytes[1] << 24); |
1406 | 37.0k | } else { |
1407 | 37.0k | *Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | |
1408 | 37.0k | (Bytes[2] << 16) | ((unsigned)Bytes[3] << 24); |
1409 | 37.0k | } |
1410 | 65.8k | } |
1411 | | |
1412 | 111k | return MCDisassembler_Success; |
1413 | 112k | } |
1414 | | |
1415 | | /// Read 6 bytes from the ArrayRef and return in a 64-bit bit word sorted |
1416 | | /// according to the given endianness and encoding byte-order. |
1417 | | static DecodeStatus readInstruction48(const uint8_t *Bytes, size_t BytesLen, |
1418 | | uint64_t Address, uint64_t *Size, |
1419 | | uint64_t *Insn, bool IsBigEndian, |
1420 | | bool IsNanoMips) |
1421 | 0 | { |
1422 | | // We want to read exactly 6 Bytes of little-endian data in nanoMIPS mode. |
1423 | 0 | if (BytesLen < 6 || IsBigEndian || !IsNanoMips) { |
1424 | 0 | *Size = 0; |
1425 | 0 | return MCDisassembler_Fail; |
1426 | 0 | } |
1427 | | |
1428 | | // High 16 bits of a 32-bit nanoMIPS instruction (where the opcode is) |
1429 | | // always precede the low 16 bits in the instruction stream (that is, they |
1430 | | // are placed at lower addresses in the instruction stream). |
1431 | | // |
1432 | | // nanoMIPS byte ordering: |
1433 | | // Little-endian: 1 | 0 | 3 | 2 | 5 | 4 |
1434 | | |
1435 | 0 | *Insn = (Bytes[0] << 0) | (Bytes[1] << 8); |
1436 | 0 | *Insn = ((*Insn << 32) | (Bytes[4] << 0) | (Bytes[5] << 8) | |
1437 | 0 | (Bytes[2] << 16) | ((unsigned)Bytes[3] << 24)); |
1438 | 0 | return MCDisassembler_Success; |
1439 | 0 | } |
1440 | | |
1441 | | static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, |
1442 | | const uint8_t *Bytes, size_t BytesLen, |
1443 | | uint64_t Address, SStream *CStream) |
1444 | 137k | { |
1445 | 137k | uint64_t Insn; |
1446 | 137k | DecodeStatus Result; |
1447 | 137k | *Size = 0; |
1448 | | |
1449 | 137k | cs_mode mode = Instr->csh->mode; |
1450 | 137k | bool IsBigEndian = mode & CS_MODE_BIG_ENDIAN; |
1451 | 137k | bool IsMicroMips = Mips_getFeatureBits(mode, Mips_FeatureMicroMips); |
1452 | 137k | bool IsNanoMips = Mips_getFeatureBits(mode, Mips_FeatureNanoMips); |
1453 | 137k | bool IsMips32r6 = Mips_getFeatureBits(mode, Mips_FeatureMips32r6); |
1454 | 137k | bool IsMips64r6 = Mips_getFeatureBits(mode, Mips_FeatureMips64r6); |
1455 | 137k | bool IsMips2 = Mips_getFeatureBits(mode, Mips_FeatureMips2); |
1456 | 137k | bool IsMips16 = Mips_getFeatureBits(mode, Mips_FeatureMips16); |
1457 | 137k | bool IsCnMips = Mips_getFeatureBits(mode, Mips_FeatureCnMips); |
1458 | 137k | bool IsCnMipsP = Mips_getFeatureBits(mode, Mips_FeatureCnMipsP); |
1459 | 137k | bool IsFP64 = Mips_getFeatureBits(mode, Mips_FeatureFP64Bit); |
1460 | 137k | bool IsGP64 = Mips_getFeatureBits(mode, Mips_FeatureGP64Bit); |
1461 | 137k | bool IsPTR64 = Mips_getFeatureBits(mode, Mips_FeaturePTR64Bit); |
1462 | | // Only present in MIPS-I and MIPS-II |
1463 | 137k | bool HasCOP3 = !Mips_getFeatureBits(mode, Mips_FeatureMips32) && |
1464 | 0 | !Mips_getFeatureBits(mode, Mips_FeatureMips3); |
1465 | | |
1466 | 137k | if (IsNanoMips) { |
1467 | 0 | uint64_t Insn2; |
1468 | 0 | Result = readInstruction48(Bytes, BytesLen, Address, Size, |
1469 | 0 | &Insn2, IsBigEndian, IsNanoMips); |
1470 | 0 | if (Result != MCDisassembler_Fail) { |
1471 | | // Calling the auto-generated decoder function. |
1472 | 0 | Result = decodeInstruction_8(DecoderTableNanoMips48, |
1473 | 0 | Instr, Insn2, Address, |
1474 | 0 | NULL); |
1475 | 0 | if (Result != MCDisassembler_Fail) { |
1476 | 0 | *Size = 6; |
1477 | 0 | return Result; |
1478 | 0 | } |
1479 | 0 | } |
1480 | | |
1481 | 0 | Result = readInstruction32(Bytes, BytesLen, Address, Size, |
1482 | 0 | &Insn, IsBigEndian, IsNanoMips); |
1483 | 0 | if (Result != MCDisassembler_Fail) { |
1484 | | // Calling the auto-generated decoder function. |
1485 | 0 | Result = decodeInstruction_4(DecoderTableNanoMips32, |
1486 | 0 | Instr, Insn, Address, |
1487 | 0 | NULL); |
1488 | 0 | if (Result != MCDisassembler_Fail) { |
1489 | 0 | *Size = 4; |
1490 | 0 | return Result; |
1491 | 0 | } |
1492 | 0 | } |
1493 | | |
1494 | 0 | Result = readInstruction16(Bytes, BytesLen, Address, Size, |
1495 | 0 | &Insn, IsBigEndian); |
1496 | 0 | if (Result != MCDisassembler_Fail) { |
1497 | | // Calling the auto-generated decoder function for NanoMips |
1498 | | // 16-bit instructions. |
1499 | 0 | Result = decodeInstruction_2(DecoderTableNanoMips16, |
1500 | 0 | Instr, Insn, Address, |
1501 | 0 | NULL); |
1502 | 0 | if (Result != MCDisassembler_Fail) { |
1503 | 0 | *Size = 2; |
1504 | 0 | return Result; |
1505 | 0 | } |
1506 | | |
1507 | 0 | Result = decodeInstruction_2( |
1508 | 0 | DecoderTableNanoMips_Conflict_Space16, Instr, |
1509 | 0 | Insn, Address, NULL); |
1510 | 0 | if (Result != MCDisassembler_Fail) { |
1511 | 0 | *Size = 2; |
1512 | 0 | return Result; |
1513 | 0 | } |
1514 | 0 | } |
1515 | | |
1516 | | // This is an invalid instruction. Claim that the Size is 2 bytes. Since |
1517 | | // nanoMIPS instructions have a minimum alignment of 2, the next 2 bytes |
1518 | | // could form a valid instruction. |
1519 | 0 | *Size = 2; |
1520 | 0 | return MCDisassembler_Fail; |
1521 | 0 | } |
1522 | | |
1523 | 137k | if (IsMicroMips) { |
1524 | 63.6k | Result = readInstruction16(Bytes, BytesLen, Address, Size, |
1525 | 63.6k | &Insn, IsBigEndian); |
1526 | 63.6k | if (Result == MCDisassembler_Fail) |
1527 | 323 | return MCDisassembler_Fail; |
1528 | | |
1529 | 63.2k | if (IsMips32r6) { |
1530 | | // Calling the auto-generated decoder function for microMIPS32R6 |
1531 | | // 16-bit instructions. |
1532 | 37.4k | Result = decodeInstruction_2(DecoderTableMicroMipsR616, |
1533 | 37.4k | Instr, Insn, Address, |
1534 | 37.4k | NULL); |
1535 | 37.4k | if (Result != MCDisassembler_Fail) { |
1536 | 8.63k | *Size = 2; |
1537 | 8.63k | return Result; |
1538 | 8.63k | } |
1539 | 37.4k | } |
1540 | | |
1541 | | // Calling the auto-generated decoder function for microMIPS 16-bit |
1542 | | // instructions. |
1543 | 54.6k | Result = decodeInstruction_2(DecoderTableMicroMips16, Instr, |
1544 | 54.6k | Insn, Address, NULL); |
1545 | 54.6k | if (Result != MCDisassembler_Fail) { |
1546 | 16.6k | *Size = 2; |
1547 | 16.6k | return Result; |
1548 | 16.6k | } |
1549 | | |
1550 | 37.9k | Result = readInstruction32(Bytes, BytesLen, Address, Size, |
1551 | 37.9k | &Insn, IsBigEndian, IsMicroMips); |
1552 | 37.9k | if (Result == MCDisassembler_Fail) |
1553 | 255 | return MCDisassembler_Fail; |
1554 | | |
1555 | 37.7k | if (IsMips32r6) { |
1556 | | // Calling the auto-generated decoder function. |
1557 | 24.8k | Result = decodeInstruction_4( |
1558 | 24.8k | DecoderTableMicroMipsR6_Ambiguous32, Instr, |
1559 | 24.8k | Insn, Address, NULL); |
1560 | 24.8k | if (Result != MCDisassembler_Fail) { |
1561 | 3.40k | *Size = 4; |
1562 | 3.40k | return Result; |
1563 | 3.40k | } |
1564 | | |
1565 | 21.4k | Result = decodeInstruction_4(DecoderTableMicroMipsR632, |
1566 | 21.4k | Instr, Insn, Address, |
1567 | 21.4k | NULL); |
1568 | 21.4k | if (Result != MCDisassembler_Fail) { |
1569 | 12.9k | *Size = 4; |
1570 | 12.9k | return Result; |
1571 | 12.9k | } |
1572 | 21.4k | } |
1573 | | |
1574 | | // Calling the auto-generated decoder function. |
1575 | 21.3k | Result = decodeInstruction_4(DecoderTableMicroMips32, Instr, |
1576 | 21.3k | Insn, Address, NULL); |
1577 | 21.3k | if (Result != MCDisassembler_Fail) { |
1578 | 19.0k | *Size = 4; |
1579 | 19.0k | return Result; |
1580 | 19.0k | } |
1581 | | |
1582 | 2.28k | Result = decodeInstruction_4(DecoderTableMicroMipsDSP32, Instr, |
1583 | 2.28k | Insn, Address, NULL); |
1584 | 2.28k | if (Result != MCDisassembler_Fail) { |
1585 | 0 | *Size = 4; |
1586 | 0 | return Result; |
1587 | 0 | } |
1588 | | |
1589 | 2.28k | if (IsFP64) { |
1590 | 2.18k | Result = |
1591 | 2.18k | decodeInstruction_4(DecoderTableMicroMipsFP6432, |
1592 | 2.18k | Instr, Insn, Address, NULL); |
1593 | 2.18k | if (Result != MCDisassembler_Fail) { |
1594 | 2.07k | *Size = 4; |
1595 | 2.07k | return Result; |
1596 | 2.07k | } |
1597 | 2.18k | } |
1598 | | |
1599 | | // This is an invalid instruction. Claim that the Size is 2 bytes. Since |
1600 | | // microMIPS instructions have a minimum alignment of 2, the next 2 bytes |
1601 | | // could form a valid instruction. The two bytes we rejected as an |
1602 | | // instruction could have actually beeen an inline constant pool that is |
1603 | | // unconditionally branched over. |
1604 | 208 | *Size = 2; |
1605 | 208 | return MCDisassembler_Fail; |
1606 | 2.28k | } |
1607 | | |
1608 | 74.2k | if (IsMips16) { |
1609 | 0 | Result = readInstruction32(Bytes, BytesLen, Address, Size, |
1610 | 0 | &Insn, IsBigEndian, IsMicroMips); |
1611 | 0 | if (Result != MCDisassembler_Fail) { |
1612 | 0 | Result = decodeInstruction_4(DecoderTable32, Instr, |
1613 | 0 | Insn, Address, NULL); |
1614 | 0 | if (Result != MCDisassembler_Fail) { |
1615 | 0 | *Size = 4; |
1616 | 0 | return Result; |
1617 | 0 | } |
1618 | 0 | } |
1619 | | |
1620 | 0 | Result = readInstruction16(Bytes, BytesLen, Address, Size, |
1621 | 0 | &Insn, IsBigEndian); |
1622 | 0 | if (Result == MCDisassembler_Fail) { |
1623 | 0 | return MCDisassembler_Fail; |
1624 | 0 | } |
1625 | | |
1626 | 0 | *Size = 2; |
1627 | 0 | return decodeInstruction_2(DecoderTable16, Instr, Insn, Address, |
1628 | 0 | NULL); |
1629 | 0 | } |
1630 | | |
1631 | | // Attempt to read the instruction so that we can attempt to decode it. If |
1632 | | // the buffer is not 4 bytes long, let the higher level logic figure out |
1633 | | // what to do with a size of zero and MCDisassembler::Fail. |
1634 | 74.2k | Result = readInstruction32(Bytes, BytesLen, Address, Size, &Insn, |
1635 | 74.2k | IsBigEndian, IsMicroMips); |
1636 | 74.2k | if (Result == MCDisassembler_Fail) |
1637 | 846 | return MCDisassembler_Fail; |
1638 | | |
1639 | | // The only instruction size for standard encoded MIPS. |
1640 | 73.3k | *Size = 4; |
1641 | | |
1642 | 73.3k | if (HasCOP3) { |
1643 | 0 | Result = decodeInstruction_4(DecoderTableCOP3_32, Instr, Insn, |
1644 | 0 | Address, NULL); |
1645 | 0 | if (Result != MCDisassembler_Fail) |
1646 | 0 | return Result; |
1647 | 0 | } |
1648 | | |
1649 | 73.3k | if (IsMips32r6 && IsGP64) { |
1650 | 0 | Result = decodeInstruction_4(DecoderTableMips32r6_64r6_GP6432, |
1651 | 0 | Instr, Insn, Address, NULL); |
1652 | 0 | if (Result != MCDisassembler_Fail) |
1653 | 0 | return Result; |
1654 | 0 | } |
1655 | | |
1656 | 73.3k | if (IsMips32r6 && IsPTR64) { |
1657 | 0 | Result = decodeInstruction_4(DecoderTableMips32r6_64r6_PTR6432, |
1658 | 0 | Instr, Insn, Address, NULL); |
1659 | 0 | if (Result != MCDisassembler_Fail) |
1660 | 0 | return Result; |
1661 | 0 | } |
1662 | | |
1663 | 73.3k | if (IsMips32r6 || IsMips64r6) { |
1664 | 31.7k | Result = decodeInstruction_4( |
1665 | 31.7k | DecoderTableMips32r6_64r6_BranchZero32, Instr, Insn, |
1666 | 31.7k | Address, NULL); |
1667 | 31.7k | if (Result != MCDisassembler_Fail) |
1668 | 0 | return Result; |
1669 | | |
1670 | 31.7k | Result = decodeInstruction_4(DecoderTableMips32r6_64r632, Instr, |
1671 | 31.7k | Insn, Address, NULL); |
1672 | 31.7k | if (Result != MCDisassembler_Fail) |
1673 | 9.74k | return Result; |
1674 | | |
1675 | 21.9k | Result = decodeInstruction_4( |
1676 | 21.9k | DecoderTableMips32r6_64r6_Ambiguous32, Instr, Insn, |
1677 | 21.9k | Address, NULL); |
1678 | 21.9k | if (Result != MCDisassembler_Fail) |
1679 | 0 | return Result; |
1680 | 21.9k | } |
1681 | | |
1682 | 63.6k | if (IsMips2 && IsPTR64) { |
1683 | 0 | Result = decodeInstruction_4(DecoderTableMips32_64_PTR6432, |
1684 | 0 | Instr, Insn, Address, NULL); |
1685 | 0 | if (Result != MCDisassembler_Fail) |
1686 | 0 | return Result; |
1687 | 0 | } |
1688 | | |
1689 | 63.6k | if (IsCnMips) { |
1690 | 0 | Result = decodeInstruction_4(DecoderTableCnMips32, Instr, Insn, |
1691 | 0 | Address, NULL); |
1692 | 0 | if (Result != MCDisassembler_Fail) |
1693 | 0 | return Result; |
1694 | 0 | } |
1695 | | |
1696 | 63.6k | if (IsCnMipsP) { |
1697 | 0 | Result = decodeInstruction_4(DecoderTableCnMipsP32, Instr, Insn, |
1698 | 0 | Address, NULL); |
1699 | 0 | if (Result != MCDisassembler_Fail) |
1700 | 0 | return Result; |
1701 | 0 | } |
1702 | | |
1703 | 63.6k | if (IsGP64) { |
1704 | 33.1k | Result = decodeInstruction_4(DecoderTableMips6432, Instr, Insn, |
1705 | 33.1k | Address, NULL); |
1706 | 33.1k | if (Result != MCDisassembler_Fail) |
1707 | 6.87k | return Result; |
1708 | 33.1k | } |
1709 | | |
1710 | 56.7k | if (IsFP64) { |
1711 | 48.2k | Result = decodeInstruction_4(DecoderTableMipsFP6432, Instr, |
1712 | 48.2k | Insn, Address, NULL); |
1713 | 48.2k | if (Result != MCDisassembler_Fail) |
1714 | 2.66k | return Result; |
1715 | 48.2k | } |
1716 | | |
1717 | 54.1k | Result = decodeInstruction_4(DecoderTableMipsDSP32, Instr, Insn, |
1718 | 54.1k | Address, NULL); |
1719 | 54.1k | if (Result != MCDisassembler_Fail) |
1720 | 1.12k | return Result; |
1721 | | |
1722 | | // Calling the auto-generated decoder function. |
1723 | 52.9k | Result = decodeInstruction_4(DecoderTableMips32, Instr, Insn, Address, |
1724 | 52.9k | NULL); |
1725 | 52.9k | if (Result != MCDisassembler_Fail) |
1726 | 52.5k | return Result; |
1727 | | |
1728 | 458 | return MCDisassembler_Fail; |
1729 | 52.9k | } |
1730 | | |
1731 | | static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo, |
1732 | | uint64_t Address, |
1733 | | const void *Decoder) |
1734 | 0 | { |
1735 | 0 | if (RegNo > 7) |
1736 | 0 | return MCDisassembler_Fail; |
1737 | | |
1738 | 0 | if (RegNo < 2) |
1739 | 0 | RegNo += 16; |
1740 | |
|
1741 | 0 | unsigned Reg = getReg(Inst, Mips_GPR32RegClassID, RegNo); |
1742 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
1743 | 0 | return MCDisassembler_Success; |
1744 | 0 | } |
1745 | | |
1746 | | static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo, |
1747 | | uint64_t Address, |
1748 | | const void *Decoder) |
1749 | 28.5k | { |
1750 | 28.5k | if (RegNo > 31) |
1751 | 0 | return MCDisassembler_Fail; |
1752 | | |
1753 | 28.5k | unsigned Reg = getReg(Inst, Mips_GPR64RegClassID, RegNo); |
1754 | 28.5k | MCOperand_CreateReg0(Inst, (Reg)); |
1755 | 28.5k | return MCDisassembler_Success; |
1756 | 28.5k | } |
1757 | | |
1758 | | static DecodeStatus DecodeGPRMM16RegisterClass(MCInst *Inst, unsigned RegNo, |
1759 | | uint64_t Address, |
1760 | | const void *Decoder) |
1761 | 35.1k | { |
1762 | 35.1k | if (RegNo > 7) |
1763 | 0 | return MCDisassembler_Fail; |
1764 | 35.1k | unsigned Reg = getReg(Inst, Mips_GPRMM16RegClassID, RegNo); |
1765 | 35.1k | MCOperand_CreateReg0(Inst, (Reg)); |
1766 | 35.1k | return MCDisassembler_Success; |
1767 | 35.1k | } |
1768 | | |
1769 | | static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst *Inst, unsigned RegNo, |
1770 | | uint64_t Address, |
1771 | | const void *Decoder) |
1772 | 3.32k | { |
1773 | 3.32k | if (RegNo > 7) |
1774 | 0 | return MCDisassembler_Fail; |
1775 | 3.32k | unsigned Reg = getReg(Inst, Mips_GPRMM16ZeroRegClassID, RegNo); |
1776 | 3.32k | MCOperand_CreateReg0(Inst, (Reg)); |
1777 | 3.32k | return MCDisassembler_Success; |
1778 | 3.32k | } |
1779 | | |
1780 | | static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst *Inst, |
1781 | | unsigned RegNo, |
1782 | | uint64_t Address, |
1783 | | const void *Decoder) |
1784 | 2.72k | { |
1785 | 2.72k | if (RegNo > 7) |
1786 | 0 | return MCDisassembler_Fail; |
1787 | 2.72k | unsigned Reg = getReg(Inst, Mips_GPRMM16MovePRegClassID, RegNo); |
1788 | 2.72k | MCOperand_CreateReg0(Inst, (Reg)); |
1789 | 2.72k | return MCDisassembler_Success; |
1790 | 2.72k | } |
1791 | | |
1792 | | static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo, |
1793 | | uint64_t Address, |
1794 | | const void *Decoder) |
1795 | 150k | { |
1796 | 150k | if (RegNo > 31) |
1797 | 0 | return MCDisassembler_Fail; |
1798 | 150k | unsigned Reg = getReg(Inst, Mips_GPR32RegClassID, RegNo); |
1799 | 150k | MCOperand_CreateReg0(Inst, (Reg)); |
1800 | 150k | return MCDisassembler_Success; |
1801 | 150k | } |
1802 | | |
1803 | | static DecodeStatus DecodeGPRNM3RegisterClass(MCInst *Inst, unsigned RegNo, |
1804 | | uint64_t Address, |
1805 | | const void *Decoder) |
1806 | 0 | { |
1807 | 0 | if (RegNo > 7) |
1808 | 0 | return MCDisassembler_Fail; |
1809 | 0 | RegNo |= ((RegNo & 0x4) ^ 0x4) << 2; |
1810 | 0 | unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); |
1811 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
1812 | 0 | return MCDisassembler_Success; |
1813 | 0 | } |
1814 | | |
1815 | | static DecodeStatus DecodeGPRNMRARegisterClass(MCInst *Inst, unsigned RegNo, |
1816 | | uint64_t Address, |
1817 | | const void *Decoder) |
1818 | 0 | { |
1819 | 0 | MCOperand_CreateReg0(Inst, (Mips_RA_NM)); |
1820 | 0 | return MCDisassembler_Success; |
1821 | 0 | } |
1822 | | |
1823 | | static DecodeStatus DecodeGPRNM3ZRegisterClass(MCInst *Inst, unsigned RegNo, |
1824 | | uint64_t Address, |
1825 | | const void *Decoder) |
1826 | 0 | { |
1827 | 0 | if (RegNo > 7) |
1828 | 0 | return MCDisassembler_Fail; |
1829 | 0 | if (RegNo != 0) |
1830 | 0 | RegNo |= ((RegNo & 0x4) ^ 0x4) << 2; |
1831 | 0 | unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); |
1832 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
1833 | 0 | return MCDisassembler_Success; |
1834 | 0 | } |
1835 | | |
1836 | | static DecodeStatus DecodeGPRNM4RegisterClass(MCInst *Inst, unsigned RegNo, |
1837 | | uint64_t Address, |
1838 | | const void *Decoder) |
1839 | 0 | { |
1840 | 0 | if (RegNo > 31) |
1841 | 0 | return MCDisassembler_Fail; |
1842 | 0 | RegNo &= ~0x8; |
1843 | 0 | RegNo += (RegNo < 4 ? 8 : 0); |
1844 | 0 | unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); |
1845 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
1846 | 0 | return MCDisassembler_Success; |
1847 | 0 | } |
1848 | | |
1849 | | static DecodeStatus DecodeGPRNM4ZRegisterClass(MCInst *Inst, unsigned RegNo, |
1850 | | uint64_t Address, |
1851 | | const void *Decoder) |
1852 | 0 | { |
1853 | 0 | if (RegNo > 31) |
1854 | 0 | return MCDisassembler_Fail; |
1855 | 0 | RegNo &= ~0x8; |
1856 | 0 | if (RegNo == 3) |
1857 | 0 | RegNo = 0; |
1858 | 0 | else |
1859 | 0 | RegNo += (RegNo < 3 ? 8 : 0); |
1860 | 0 | unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); |
1861 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
1862 | 0 | return MCDisassembler_Success; |
1863 | 0 | } |
1864 | | |
1865 | | static DecodeStatus DecodeGPRNM32NZRegisterClass(MCInst *Inst, unsigned RegNo, |
1866 | | uint64_t Address, |
1867 | | const void *Decoder) |
1868 | 0 | { |
1869 | 0 | if (RegNo == 0) |
1870 | 0 | return MCDisassembler_Fail; |
1871 | 0 | unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); |
1872 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
1873 | 0 | return MCDisassembler_Success; |
1874 | 0 | } |
1875 | | |
1876 | | static DecodeStatus DecodeGPRNM32RegisterClass(MCInst *Inst, unsigned RegNo, |
1877 | | uint64_t Address, |
1878 | | const void *Decoder) |
1879 | 0 | { |
1880 | 0 | if (RegNo > 31) |
1881 | 0 | return MCDisassembler_Fail; |
1882 | 0 | unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); |
1883 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
1884 | 0 | return MCDisassembler_Success; |
1885 | 0 | } |
1886 | | |
1887 | | static DecodeStatus DecodeGPRNM2R1RegisterClass(MCInst *Inst, unsigned RegNo, |
1888 | | uint64_t Address, |
1889 | | const void *Decoder) |
1890 | 0 | { |
1891 | 0 | if (RegNo > 31) |
1892 | 0 | return MCDisassembler_Fail; |
1893 | 0 | RegNo += 4; |
1894 | 0 | unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); |
1895 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
1896 | 0 | MCOperand_CreateReg0(Inst, (Reg + 1)); |
1897 | 0 | return MCDisassembler_Success; |
1898 | 0 | } |
1899 | | |
1900 | | static DecodeStatus DecodeGPRNM1R1RegisterClass(MCInst *Inst, unsigned RegNo, |
1901 | | uint64_t Address, |
1902 | | const void *Decoder) |
1903 | 0 | { |
1904 | 0 | if (RegNo != 0 && RegNo != 1) |
1905 | 0 | return MCDisassembler_Fail; |
1906 | 0 | RegNo += 4; |
1907 | 0 | unsigned Reg = getReg(Inst, Mips_GPRNM32RegClassID, RegNo); |
1908 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
1909 | 0 | return MCDisassembler_Success; |
1910 | 0 | } |
1911 | | |
1912 | | static DecodeStatus DecodePtrRegisterClass(MCInst *Inst, unsigned RegNo, |
1913 | | uint64_t Address, |
1914 | | const void *Decoder) |
1915 | 5.22k | { |
1916 | 5.22k | if (Mips_getFeatureBits(Inst->csh->mode, Mips_FeatureGP64Bit)) |
1917 | 2.59k | return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder); |
1918 | | |
1919 | 2.63k | return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); |
1920 | 5.22k | } |
1921 | | |
1922 | | static DecodeStatus DecodeDSPRRegisterClass(MCInst *Inst, unsigned RegNo, |
1923 | | uint64_t Address, |
1924 | | const void *Decoder) |
1925 | 9.61k | { |
1926 | 9.61k | return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder); |
1927 | 9.61k | } |
1928 | | |
1929 | | static DecodeStatus DecodeFGR64RegisterClass(MCInst *Inst, unsigned RegNo, |
1930 | | uint64_t Address, |
1931 | | const void *Decoder) |
1932 | 14.6k | { |
1933 | 14.6k | if (RegNo > 31) |
1934 | 0 | return MCDisassembler_Fail; |
1935 | | |
1936 | 14.6k | unsigned Reg = getReg(Inst, Mips_FGR64RegClassID, RegNo); |
1937 | 14.6k | MCOperand_CreateReg0(Inst, (Reg)); |
1938 | 14.6k | return MCDisassembler_Success; |
1939 | 14.6k | } |
1940 | | |
1941 | | static DecodeStatus DecodeFGR32RegisterClass(MCInst *Inst, unsigned RegNo, |
1942 | | uint64_t Address, |
1943 | | const void *Decoder) |
1944 | 17.5k | { |
1945 | 17.5k | if (RegNo > 31) |
1946 | 0 | return MCDisassembler_Fail; |
1947 | | |
1948 | 17.5k | unsigned Reg = getReg(Inst, Mips_FGR32RegClassID, RegNo); |
1949 | 17.5k | MCOperand_CreateReg0(Inst, (Reg)); |
1950 | 17.5k | return MCDisassembler_Success; |
1951 | 17.5k | } |
1952 | | |
1953 | | static DecodeStatus DecodeCCRRegisterClass(MCInst *Inst, unsigned RegNo, |
1954 | | uint64_t Address, |
1955 | | const void *Decoder) |
1956 | 1.11k | { |
1957 | 1.11k | if (RegNo > 31) |
1958 | 0 | return MCDisassembler_Fail; |
1959 | 1.11k | unsigned Reg = getReg(Inst, Mips_CCRRegClassID, RegNo); |
1960 | 1.11k | MCOperand_CreateReg0(Inst, (Reg)); |
1961 | 1.11k | return MCDisassembler_Success; |
1962 | 1.11k | } |
1963 | | |
1964 | | static DecodeStatus DecodeFCCRegisterClass(MCInst *Inst, unsigned RegNo, |
1965 | | uint64_t Address, |
1966 | | const void *Decoder) |
1967 | 5.33k | { |
1968 | 5.33k | if (RegNo > 7) |
1969 | 0 | return MCDisassembler_Fail; |
1970 | 5.33k | unsigned Reg = getReg(Inst, Mips_FCCRegClassID, RegNo); |
1971 | 5.33k | MCOperand_CreateReg0(Inst, (Reg)); |
1972 | 5.33k | return MCDisassembler_Success; |
1973 | 5.33k | } |
1974 | | |
1975 | | static DecodeStatus DecodeFGRCCRegisterClass(MCInst *Inst, unsigned RegNo, |
1976 | | uint64_t Address, |
1977 | | const void *Decoder) |
1978 | 1.58k | { |
1979 | 1.58k | if (RegNo > 31) |
1980 | 0 | return MCDisassembler_Fail; |
1981 | | |
1982 | 1.58k | unsigned Reg = getReg(Inst, Mips_FGRCCRegClassID, RegNo); |
1983 | 1.58k | MCOperand_CreateReg0(Inst, (Reg)); |
1984 | 1.58k | return MCDisassembler_Success; |
1985 | 1.58k | } |
1986 | | |
1987 | | static DecodeStatus DecodeMem(MCInst *Inst, uint32_t Insn, uint64_t Address, |
1988 | | const void *Decoder) |
1989 | 13.3k | { |
1990 | 13.3k | int Offset = SignExtend32((Insn & 0xffff), 16); |
1991 | 13.3k | unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); |
1992 | 13.3k | unsigned Base = fieldFromInstruction_4(Insn, 21, 5); |
1993 | | |
1994 | 13.3k | Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); |
1995 | 13.3k | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
1996 | | |
1997 | 13.3k | if (MCInst_getOpcode(Inst) == Mips_SC || |
1998 | 11.7k | MCInst_getOpcode(Inst) == Mips_SCD) |
1999 | 2.67k | MCOperand_CreateReg0(Inst, (Reg)); |
2000 | | |
2001 | 13.3k | MCOperand_CreateReg0(Inst, (Reg)); |
2002 | 13.3k | MCOperand_CreateReg0(Inst, (Base)); |
2003 | 13.3k | MCOperand_CreateImm0(Inst, (Offset)); |
2004 | | |
2005 | 13.3k | return MCDisassembler_Success; |
2006 | 13.3k | } |
2007 | | |
2008 | | #define DEFINE_DecodeMemNM(Offbits, isSigned, rt) \ |
2009 | | static DecodeStatus CONCAT(DecodeMemNM, \ |
2010 | | CONCAT(Offbits, CONCAT(isSigned, rt)))( \ |
2011 | | MCInst * Inst, uint32_t Insn, uint64_t Address, \ |
2012 | | const void *Decoder) \ |
2013 | 0 | { \ |
2014 | 0 | int Offset = (Insn & ((1 << Offbits) - 1)); \ |
2015 | 0 | if (isSigned) \ |
2016 | 0 | Offset = SignExtend32((Offset), Offbits); \ |
2017 | 0 | unsigned Base; \ |
2018 | 0 | \ |
2019 | 0 | switch (rt) { \ |
2020 | 0 | case Mips_GPRNMGPRegClassID: \ |
2021 | 0 | case Mips_GPRNMSPRegClassID: \ |
2022 | 0 | Base = 0; \ |
2023 | 0 | break; \ |
2024 | 0 | case Mips_GPRNM3RegClassID: \ |
2025 | 0 | Base = fieldFromInstruction_4(Insn, Offbits, 3); \ |
2026 | 0 | break; \ |
2027 | 0 | case Mips_GPRNM4RegClassID: \ |
2028 | 0 | case Mips_GPRNM4ZRegClassID: \ |
2029 | 0 | \ |
2030 | 0 | break; \ |
2031 | 0 | default: \ |
2032 | 0 | Base = fieldFromInstruction_4(Insn, Offbits, 5); \ |
2033 | 0 | } \ |
2034 | 0 | Base = getReg(Inst, rt, Base); \ |
2035 | 0 | \ |
2036 | 0 | MCOperand_CreateReg0(Inst, (Base)); \ |
2037 | 0 | MCOperand_CreateImm0(Inst, (Offset)); \ |
2038 | 0 | \ |
2039 | 0 | return MCDisassembler_Success; \ |
2040 | 0 | } Unexecuted instantiation: MipsDisassembler.c:DecodeMemNM_6_0_Mips_GPRNM3RegClassID Unexecuted instantiation: MipsDisassembler.c:DecodeMemNM_7_0_Mips_GPRNMSPRegClassID Unexecuted instantiation: MipsDisassembler.c:DecodeMemNM_9_0_Mips_GPRNMGPRegClassID Unexecuted instantiation: MipsDisassembler.c:DecodeMemNM_2_0_Mips_GPRNM3RegClassID Unexecuted instantiation: MipsDisassembler.c:DecodeMemNM_3_0_Mips_GPRNM3RegClassID Unexecuted instantiation: MipsDisassembler.c:DecodeMemNM_21_0_Mips_GPRNMGPRegClassID Unexecuted instantiation: MipsDisassembler.c:DecodeMemNM_18_0_Mips_GPRNMGPRegClassID Unexecuted instantiation: MipsDisassembler.c:DecodeMemNM_12_0_Mips_GPRNM32RegClassID Unexecuted instantiation: MipsDisassembler.c:DecodeMemNM_9_1_Mips_GPRNM32RegClassID |
2041 | | DEFINE_DecodeMemNM(6, 0, Mips_GPRNM3RegClassID); |
2042 | | DEFINE_DecodeMemNM(7, 0, Mips_GPRNMSPRegClassID); |
2043 | | DEFINE_DecodeMemNM(9, 0, Mips_GPRNMGPRegClassID); |
2044 | | DEFINE_DecodeMemNM(2, 0, Mips_GPRNM3RegClassID); |
2045 | | DEFINE_DecodeMemNM(3, 0, Mips_GPRNM3RegClassID); |
2046 | | DEFINE_DecodeMemNM(21, 0, Mips_GPRNMGPRegClassID); |
2047 | | DEFINE_DecodeMemNM(18, 0, Mips_GPRNMGPRegClassID); |
2048 | | DEFINE_DecodeMemNM(12, 0, Mips_GPRNM32RegClassID); |
2049 | | DEFINE_DecodeMemNM(9, 1, Mips_GPRNM32RegClassID); |
2050 | | |
2051 | | static DecodeStatus DecodeMemZeroNM(MCInst *Inst, uint32_t Insn, |
2052 | | uint64_t Address, const void *Decoder) |
2053 | 0 | { |
2054 | 0 | unsigned Base; |
2055 | 0 | Base = fieldFromInstruction_4(Insn, 0, 5); |
2056 | 0 | Base = getReg(Inst, Mips_GPRNM32RegClassID, Base); |
2057 | 0 | MCOperand_CreateReg0(Inst, (Base)); |
2058 | |
|
2059 | 0 | return MCDisassembler_Success; |
2060 | 0 | } |
2061 | | |
2062 | | #define DEFINE_DecodeMemNMRX(RegClass) \ |
2063 | | static DecodeStatus CONCAT(DecodeMemNMRX, RegClass)( \ |
2064 | | MCInst * Inst, uint32_t Insn, uint64_t Address, \ |
2065 | | const void *Decoder) \ |
2066 | 0 | { \ |
2067 | 0 | unsigned Offset; \ |
2068 | 0 | unsigned Base; \ |
2069 | 0 | Offset = fieldFromInstruction_4(Insn, 0, 5); \ |
2070 | 0 | Base = fieldFromInstruction_4(Insn, 5, 5); \ |
2071 | 0 | \ |
2072 | 0 | Base = getReg(Inst, RegClass, Base); \ |
2073 | 0 | Offset = getReg(Inst, RegClass, Offset); \ |
2074 | 0 | MCOperand_CreateReg0(Inst, (Base)); \ |
2075 | 0 | MCOperand_CreateReg0(Inst, (Offset)); \ |
2076 | 0 | \ |
2077 | 0 | return MCDisassembler_Success; \ |
2078 | 0 | } Unexecuted instantiation: MipsDisassembler.c:DecodeMemNMRX_Mips_GPRNM3RegClassID Unexecuted instantiation: MipsDisassembler.c:DecodeMemNMRX_Mips_GPRNM32RegClassID |
2079 | | DEFINE_DecodeMemNMRX(Mips_GPRNM3RegClassID); |
2080 | | DEFINE_DecodeMemNMRX(Mips_GPRNM32RegClassID); |
2081 | | |
2082 | | static DecodeStatus DecodeMemNM4x4(MCInst *Inst, uint32_t Insn, |
2083 | | uint64_t Address, const void *Decoder) |
2084 | 0 | { |
2085 | 0 | int Offset = fieldFromInstruction_4(Insn, 0, 4); |
2086 | 0 | unsigned Base; |
2087 | |
|
2088 | 0 | Base = getReg(Inst, Mips_GPRNM32RegClassID, |
2089 | 0 | fieldFromInstruction_4(Insn, 4, 5) & ~0x8); |
2090 | |
|
2091 | 0 | MCOperand_CreateReg0(Inst, (Base)); |
2092 | 0 | MCOperand_CreateImm0(Inst, (Offset)); |
2093 | |
|
2094 | 0 | return MCDisassembler_Success; |
2095 | 0 | } |
2096 | | |
2097 | | static DecodeStatus DecodeMemEVA(MCInst *Inst, uint32_t Insn, uint64_t Address, |
2098 | | const void *Decoder) |
2099 | 170 | { |
2100 | 170 | int Offset = SignExtend32((Insn >> 7), 9); |
2101 | 170 | unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); |
2102 | 170 | unsigned Base = fieldFromInstruction_4(Insn, 21, 5); |
2103 | | |
2104 | 170 | Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); |
2105 | 170 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2106 | | |
2107 | 170 | if (MCInst_getOpcode(Inst) == Mips_SCE) |
2108 | 68 | MCOperand_CreateReg0(Inst, (Reg)); |
2109 | | |
2110 | 170 | MCOperand_CreateReg0(Inst, (Reg)); |
2111 | 170 | MCOperand_CreateReg0(Inst, (Base)); |
2112 | 170 | MCOperand_CreateImm0(Inst, (Offset)); |
2113 | | |
2114 | 170 | return MCDisassembler_Success; |
2115 | 170 | } |
2116 | | |
2117 | | #include "MipsCP0RegisterMap.h" |
2118 | | |
2119 | | static DecodeStatus DecodeCOP0SelRegisterClass(MCInst *Inst, unsigned RegNo, |
2120 | | uint64_t Address, |
2121 | | const void *Decoder) |
2122 | 0 | { |
2123 | 0 | int Reg = COP0Map_getEncIndexMap(RegNo); |
2124 | |
|
2125 | 0 | if (Reg != -1) { |
2126 | 0 | Reg = getReg(Inst, Mips_COP0SelRegClassID, Reg); |
2127 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
2128 | 0 | } else { |
2129 | | // Not a named register encoding - print numeric register and select value |
2130 | 0 | switch (MCInst_getOpcode(Inst)) { |
2131 | 0 | case Mips_MFC0Sel_NM: |
2132 | 0 | MCInst_setOpcode(Inst, (Mips_MFC0_NM)); |
2133 | 0 | break; |
2134 | 0 | case Mips_MFHC0Sel_NM: |
2135 | 0 | MCInst_setOpcode(Inst, (Mips_MFHC0_NM)); |
2136 | 0 | break; |
2137 | 0 | case Mips_MTC0Sel_NM: |
2138 | 0 | MCInst_setOpcode(Inst, (Mips_MTC0_NM)); |
2139 | 0 | break; |
2140 | 0 | case Mips_MTHC0Sel_NM: |
2141 | 0 | MCInst_setOpcode(Inst, (Mips_MTHC0_NM)); |
2142 | 0 | break; |
2143 | 0 | default: |
2144 | 0 | CS_ASSERT_RET_VAL(0 && "Unknown instruction!", |
2145 | 0 | MCDisassembler_Fail); |
2146 | 0 | return MCDisassembler_Fail; |
2147 | 0 | } |
2148 | 0 | Reg = getReg(Inst, Mips_COP0RegClassID, RegNo >> 5); |
2149 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
2150 | 0 | MCOperand_CreateImm0(Inst, (RegNo & 0x1f)); |
2151 | 0 | } |
2152 | 0 | return MCDisassembler_Success; |
2153 | 0 | } |
2154 | | |
2155 | | static DecodeStatus DecodeLoadByte15(MCInst *Inst, uint32_t Insn, |
2156 | | uint64_t Address, const void *Decoder) |
2157 | 1.18k | { |
2158 | 1.18k | int Offset = SignExtend32((Insn & 0xffff), 16); |
2159 | 1.18k | unsigned Base = fieldFromInstruction_4(Insn, 16, 5); |
2160 | 1.18k | unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); |
2161 | | |
2162 | 1.18k | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2163 | 1.18k | Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); |
2164 | | |
2165 | 1.18k | MCOperand_CreateReg0(Inst, (Reg)); |
2166 | 1.18k | MCOperand_CreateReg0(Inst, (Base)); |
2167 | 1.18k | MCOperand_CreateImm0(Inst, (Offset)); |
2168 | | |
2169 | 1.18k | return MCDisassembler_Success; |
2170 | 1.18k | } |
2171 | | |
2172 | | static DecodeStatus DecodeCacheOp(MCInst *Inst, uint32_t Insn, uint64_t Address, |
2173 | | const void *Decoder) |
2174 | 1.06k | { |
2175 | 1.06k | int Offset = SignExtend32((Insn & 0xffff), 16); |
2176 | 1.06k | unsigned Hint = fieldFromInstruction_4(Insn, 16, 5); |
2177 | 1.06k | unsigned Base = fieldFromInstruction_4(Insn, 21, 5); |
2178 | | |
2179 | 1.06k | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2180 | | |
2181 | 1.06k | MCOperand_CreateReg0(Inst, (Base)); |
2182 | 1.06k | MCOperand_CreateImm0(Inst, (Offset)); |
2183 | 1.06k | MCOperand_CreateImm0(Inst, (Hint)); |
2184 | | |
2185 | 1.06k | return MCDisassembler_Success; |
2186 | 1.06k | } |
2187 | | |
2188 | | static DecodeStatus DecodeCacheOpMM(MCInst *Inst, uint32_t Insn, |
2189 | | uint64_t Address, const void *Decoder) |
2190 | 508 | { |
2191 | 508 | int Offset = SignExtend32((Insn & 0xfff), 12); |
2192 | 508 | unsigned Base = fieldFromInstruction_4(Insn, 16, 5); |
2193 | 508 | unsigned Hint = fieldFromInstruction_4(Insn, 21, 5); |
2194 | | |
2195 | 508 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2196 | | |
2197 | 508 | MCOperand_CreateReg0(Inst, (Base)); |
2198 | 508 | MCOperand_CreateImm0(Inst, (Offset)); |
2199 | 508 | MCOperand_CreateImm0(Inst, (Hint)); |
2200 | | |
2201 | 508 | return MCDisassembler_Success; |
2202 | 508 | } |
2203 | | |
2204 | | static DecodeStatus DecodePrefeOpMM(MCInst *Inst, uint32_t Insn, |
2205 | | uint64_t Address, const void *Decoder) |
2206 | 178 | { |
2207 | 178 | int Offset = SignExtend32((Insn & 0x1ff), 9); |
2208 | 178 | unsigned Base = fieldFromInstruction_4(Insn, 16, 5); |
2209 | 178 | unsigned Hint = fieldFromInstruction_4(Insn, 21, 5); |
2210 | | |
2211 | 178 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2212 | | |
2213 | 178 | MCOperand_CreateReg0(Inst, (Base)); |
2214 | 178 | MCOperand_CreateImm0(Inst, (Offset)); |
2215 | 178 | MCOperand_CreateImm0(Inst, (Hint)); |
2216 | | |
2217 | 178 | return MCDisassembler_Success; |
2218 | 178 | } |
2219 | | |
2220 | | static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst *Inst, uint32_t Insn, |
2221 | | uint64_t Address, |
2222 | | const void *Decoder) |
2223 | 369 | { |
2224 | 369 | int Offset = SignExtend32((Insn >> 7), 9); |
2225 | 369 | unsigned Hint = fieldFromInstruction_4(Insn, 16, 5); |
2226 | 369 | unsigned Base = fieldFromInstruction_4(Insn, 21, 5); |
2227 | | |
2228 | 369 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2229 | | |
2230 | 369 | MCOperand_CreateReg0(Inst, (Base)); |
2231 | 369 | MCOperand_CreateImm0(Inst, (Offset)); |
2232 | 369 | MCOperand_CreateImm0(Inst, (Hint)); |
2233 | | |
2234 | 369 | return MCDisassembler_Success; |
2235 | 369 | } |
2236 | | |
2237 | | static DecodeStatus DecodeSyncI(MCInst *Inst, uint32_t Insn, uint64_t Address, |
2238 | | const void *Decoder) |
2239 | 266 | { |
2240 | 266 | int Offset = SignExtend32((Insn & 0xffff), 16); |
2241 | 266 | unsigned Base = fieldFromInstruction_4(Insn, 21, 5); |
2242 | | |
2243 | 266 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2244 | | |
2245 | 266 | MCOperand_CreateReg0(Inst, (Base)); |
2246 | 266 | MCOperand_CreateImm0(Inst, (Offset)); |
2247 | | |
2248 | 266 | return MCDisassembler_Success; |
2249 | 266 | } |
2250 | | |
2251 | | static DecodeStatus DecodeSyncI_MM(MCInst *Inst, uint32_t Insn, |
2252 | | uint64_t Address, const void *Decoder) |
2253 | 66 | { |
2254 | 66 | int Offset = SignExtend32((Insn & 0xffff), 16); |
2255 | 66 | unsigned Base = fieldFromInstruction_4(Insn, 16, 5); |
2256 | | |
2257 | 66 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2258 | | |
2259 | 66 | MCOperand_CreateReg0(Inst, (Base)); |
2260 | 66 | MCOperand_CreateImm0(Inst, (Offset)); |
2261 | | |
2262 | 66 | return MCDisassembler_Success; |
2263 | 66 | } |
2264 | | |
2265 | | static DecodeStatus DecodeSynciR6(MCInst *Inst, uint32_t Insn, uint64_t Address, |
2266 | | const void *Decoder) |
2267 | 67 | { |
2268 | 67 | int Immediate = SignExtend32((Insn & 0xffff), 16); |
2269 | 67 | unsigned Base = fieldFromInstruction_4(Insn, 16, 5); |
2270 | | |
2271 | 67 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2272 | | |
2273 | 67 | MCOperand_CreateReg0(Inst, (Base)); |
2274 | 67 | MCOperand_CreateImm0(Inst, (Immediate)); |
2275 | | |
2276 | 67 | return MCDisassembler_Success; |
2277 | 67 | } |
2278 | | |
2279 | | static DecodeStatus DecodeMSA128Mem(MCInst *Inst, uint32_t Insn, |
2280 | | uint64_t Address, const void *Decoder) |
2281 | 4.55k | { |
2282 | 4.55k | int Offset = SignExtend32((fieldFromInstruction_4(Insn, 16, 10)), 10); |
2283 | 4.55k | unsigned Reg = fieldFromInstruction_4(Insn, 6, 5); |
2284 | 4.55k | unsigned Base = fieldFromInstruction_4(Insn, 11, 5); |
2285 | | |
2286 | 4.55k | Reg = getReg(Inst, Mips_MSA128BRegClassID, Reg); |
2287 | 4.55k | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2288 | | |
2289 | 4.55k | MCOperand_CreateReg0(Inst, (Reg)); |
2290 | 4.55k | MCOperand_CreateReg0(Inst, (Base)); |
2291 | | |
2292 | | // The immediate field of an LD/ST instruction is scaled which means it must |
2293 | | // be multiplied (when decoding) by the size (in bytes) of the instructions' |
2294 | | // data format. |
2295 | | // .b - 1 byte |
2296 | | // .h - 2 bytes |
2297 | | // .w - 4 bytes |
2298 | | // .d - 8 bytes |
2299 | 4.55k | switch (MCInst_getOpcode(Inst)) { |
2300 | 0 | default: |
2301 | |
|
2302 | 0 | return MCDisassembler_Fail; |
2303 | 0 | break; |
2304 | 931 | case Mips_LD_B: |
2305 | 1.51k | case Mips_ST_B: |
2306 | 1.51k | MCOperand_CreateImm0(Inst, (Offset)); |
2307 | 1.51k | break; |
2308 | 634 | case Mips_LD_H: |
2309 | 1.08k | case Mips_ST_H: |
2310 | 1.08k | MCOperand_CreateImm0(Inst, (Offset * 2)); |
2311 | 1.08k | break; |
2312 | 475 | case Mips_LD_W: |
2313 | 980 | case Mips_ST_W: |
2314 | 980 | MCOperand_CreateImm0(Inst, (Offset * 4)); |
2315 | 980 | break; |
2316 | 340 | case Mips_LD_D: |
2317 | 980 | case Mips_ST_D: |
2318 | 980 | MCOperand_CreateImm0(Inst, (Offset * 8)); |
2319 | 980 | break; |
2320 | 4.55k | } |
2321 | | |
2322 | 4.55k | return MCDisassembler_Success; |
2323 | 4.55k | } |
2324 | | |
2325 | | static DecodeStatus DecodeMemMMImm4(MCInst *Inst, uint32_t Insn, |
2326 | | uint64_t Address, const void *Decoder) |
2327 | 5.52k | { |
2328 | 5.52k | unsigned Offset = Insn & 0xf; |
2329 | 5.52k | unsigned Reg = fieldFromInstruction_4(Insn, 7, 3); |
2330 | 5.52k | unsigned Base = fieldFromInstruction_4(Insn, 4, 3); |
2331 | | |
2332 | 5.52k | switch (MCInst_getOpcode(Inst)) { |
2333 | 1.43k | case Mips_LBU16_MM: |
2334 | 1.86k | case Mips_LHU16_MM: |
2335 | 2.94k | case Mips_LW16_MM: |
2336 | 2.94k | if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder) == |
2337 | 2.94k | MCDisassembler_Fail) |
2338 | 0 | return MCDisassembler_Fail; |
2339 | 2.94k | break; |
2340 | 2.94k | case Mips_SB16_MM: |
2341 | 1.24k | case Mips_SB16_MMR6: |
2342 | 1.50k | case Mips_SH16_MM: |
2343 | 2.02k | case Mips_SH16_MMR6: |
2344 | 2.33k | case Mips_SW16_MM: |
2345 | 2.58k | case Mips_SW16_MMR6: |
2346 | 2.58k | if (DecodeGPRMM16ZeroRegisterClass( |
2347 | 2.58k | Inst, Reg, Address, Decoder) == MCDisassembler_Fail) |
2348 | 0 | return MCDisassembler_Fail; |
2349 | 2.58k | break; |
2350 | 5.52k | } |
2351 | | |
2352 | 5.52k | if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder) == |
2353 | 5.52k | MCDisassembler_Fail) |
2354 | 0 | return MCDisassembler_Fail; |
2355 | | |
2356 | 5.52k | switch (MCInst_getOpcode(Inst)) { |
2357 | 1.43k | case Mips_LBU16_MM: |
2358 | 1.43k | if (Offset == 0xf) |
2359 | 245 | MCOperand_CreateImm0(Inst, (-1)); |
2360 | 1.19k | else |
2361 | 1.19k | MCOperand_CreateImm0(Inst, (Offset)); |
2362 | 1.43k | break; |
2363 | 787 | case Mips_SB16_MM: |
2364 | 1.24k | case Mips_SB16_MMR6: |
2365 | 1.24k | MCOperand_CreateImm0(Inst, (Offset)); |
2366 | 1.24k | break; |
2367 | 428 | case Mips_LHU16_MM: |
2368 | 681 | case Mips_SH16_MM: |
2369 | 1.20k | case Mips_SH16_MMR6: |
2370 | 1.20k | MCOperand_CreateImm0(Inst, (Offset << 1)); |
2371 | 1.20k | break; |
2372 | 1.08k | case Mips_LW16_MM: |
2373 | 1.38k | case Mips_SW16_MM: |
2374 | 1.63k | case Mips_SW16_MMR6: |
2375 | 1.63k | MCOperand_CreateImm0(Inst, (Offset << 2)); |
2376 | 1.63k | break; |
2377 | 5.52k | } |
2378 | | |
2379 | 5.52k | return MCDisassembler_Success; |
2380 | 5.52k | } |
2381 | | |
2382 | | static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst *Inst, uint32_t Insn, |
2383 | | uint64_t Address, const void *Decoder) |
2384 | 2.90k | { |
2385 | 2.90k | unsigned Offset = Insn & 0x1F; |
2386 | 2.90k | unsigned Reg = fieldFromInstruction_4(Insn, 5, 5); |
2387 | | |
2388 | 2.90k | Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); |
2389 | | |
2390 | 2.90k | MCOperand_CreateReg0(Inst, (Reg)); |
2391 | 2.90k | MCOperand_CreateReg0(Inst, (Mips_SP)); |
2392 | 2.90k | MCOperand_CreateImm0(Inst, (Offset << 2)); |
2393 | | |
2394 | 2.90k | return MCDisassembler_Success; |
2395 | 2.90k | } |
2396 | | |
2397 | | static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst *Inst, uint32_t Insn, |
2398 | | uint64_t Address, const void *Decoder) |
2399 | 1.70k | { |
2400 | 1.70k | unsigned Offset = Insn & 0x7F; |
2401 | 1.70k | unsigned Reg = fieldFromInstruction_4(Insn, 7, 3); |
2402 | | |
2403 | 1.70k | Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); |
2404 | | |
2405 | 1.70k | MCOperand_CreateReg0(Inst, (Reg)); |
2406 | 1.70k | MCOperand_CreateReg0(Inst, (Mips_GP)); |
2407 | 1.70k | MCOperand_CreateImm0(Inst, (Offset << 2)); |
2408 | | |
2409 | 1.70k | return MCDisassembler_Success; |
2410 | 1.70k | } |
2411 | | |
2412 | | static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst *Inst, uint32_t Insn, |
2413 | | uint64_t Address, |
2414 | | const void *Decoder) |
2415 | 901 | { |
2416 | 901 | int Offset; |
2417 | 901 | switch (MCInst_getOpcode(Inst)) { |
2418 | 83 | case Mips_LWM16_MMR6: |
2419 | 420 | case Mips_SWM16_MMR6: |
2420 | 420 | Offset = fieldFromInstruction_4(Insn, 4, 4); |
2421 | 420 | break; |
2422 | 481 | default: |
2423 | 481 | Offset = fieldFromInstruction_4(Insn, 0, 4); |
2424 | 481 | break; |
2425 | 901 | } |
2426 | | |
2427 | 901 | if (DecodeRegListOperand16(Inst, Insn, Address, Decoder) == |
2428 | 901 | MCDisassembler_Fail) |
2429 | 0 | return MCDisassembler_Fail; |
2430 | | |
2431 | 901 | MCOperand_CreateReg0(Inst, (Mips_SP)); |
2432 | 901 | MCOperand_CreateImm0(Inst, (Offset << 2)); |
2433 | | |
2434 | 901 | return MCDisassembler_Success; |
2435 | 901 | } |
2436 | | |
2437 | | static DecodeStatus DecodeMemMMImm9(MCInst *Inst, uint32_t Insn, |
2438 | | uint64_t Address, const void *Decoder) |
2439 | 906 | { |
2440 | 906 | int Offset = SignExtend32((Insn & 0x1ff), 9); |
2441 | 906 | unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); |
2442 | 906 | unsigned Base = fieldFromInstruction_4(Insn, 16, 5); |
2443 | | |
2444 | 906 | Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); |
2445 | 906 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2446 | | |
2447 | 906 | if (MCInst_getOpcode(Inst) == Mips_SCE_MM || |
2448 | 559 | MCInst_getOpcode(Inst) == Mips_SC_MMR6) |
2449 | 542 | MCOperand_CreateReg0(Inst, (Reg)); |
2450 | | |
2451 | 906 | MCOperand_CreateReg0(Inst, (Reg)); |
2452 | 906 | MCOperand_CreateReg0(Inst, (Base)); |
2453 | 906 | MCOperand_CreateImm0(Inst, (Offset)); |
2454 | | |
2455 | 906 | return MCDisassembler_Success; |
2456 | 906 | } |
2457 | | |
2458 | | static DecodeStatus DecodeMemMMImm12(MCInst *Inst, uint32_t Insn, |
2459 | | uint64_t Address, const void *Decoder) |
2460 | 2.15k | { |
2461 | 2.15k | int Offset = SignExtend32((Insn & 0x0fff), 12); |
2462 | 2.15k | unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); |
2463 | 2.15k | unsigned Base = fieldFromInstruction_4(Insn, 16, 5); |
2464 | | |
2465 | 2.15k | Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); |
2466 | 2.15k | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2467 | | |
2468 | 2.15k | switch (MCInst_getOpcode(Inst)) { |
2469 | 449 | case Mips_SWM32_MM: |
2470 | 1.03k | case Mips_LWM32_MM: |
2471 | 1.03k | if (DecodeRegListOperand(Inst, Insn, Address, Decoder) == |
2472 | 1.03k | MCDisassembler_Fail) |
2473 | 3 | return MCDisassembler_Fail; |
2474 | 1.03k | MCOperand_CreateReg0(Inst, (Base)); |
2475 | 1.03k | MCOperand_CreateImm0(Inst, (Offset)); |
2476 | 1.03k | break; |
2477 | 115 | case Mips_SC_MM: |
2478 | 115 | MCOperand_CreateReg0(Inst, (Reg)); |
2479 | | // fall through |
2480 | 1.11k | default: |
2481 | 1.11k | MCOperand_CreateReg0(Inst, (Reg)); |
2482 | 1.11k | if (MCInst_getOpcode(Inst) == Mips_LWP_MM || |
2483 | 806 | MCInst_getOpcode(Inst) == Mips_SWP_MM) |
2484 | 579 | MCOperand_CreateReg0(Inst, (Reg + 1)); |
2485 | | |
2486 | 1.11k | MCOperand_CreateReg0(Inst, (Base)); |
2487 | 1.11k | MCOperand_CreateImm0(Inst, (Offset)); |
2488 | 2.15k | } |
2489 | | |
2490 | 2.14k | return MCDisassembler_Success; |
2491 | 2.15k | } |
2492 | | |
2493 | | static DecodeStatus DecodeMemMMImm16(MCInst *Inst, uint32_t Insn, |
2494 | | uint64_t Address, const void *Decoder) |
2495 | 4.64k | { |
2496 | 4.64k | int Offset = SignExtend32((Insn & 0xffff), 16); |
2497 | 4.64k | unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); |
2498 | 4.64k | unsigned Base = fieldFromInstruction_4(Insn, 16, 5); |
2499 | | |
2500 | 4.64k | Reg = getReg(Inst, Mips_GPR32RegClassID, Reg); |
2501 | 4.64k | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2502 | | |
2503 | 4.64k | MCOperand_CreateReg0(Inst, (Reg)); |
2504 | 4.64k | MCOperand_CreateReg0(Inst, (Base)); |
2505 | 4.64k | MCOperand_CreateImm0(Inst, (Offset)); |
2506 | | |
2507 | 4.64k | return MCDisassembler_Success; |
2508 | 4.64k | } |
2509 | | |
2510 | | static DecodeStatus DecodeFMem(MCInst *Inst, uint32_t Insn, uint64_t Address, |
2511 | | const void *Decoder) |
2512 | 2.40k | { |
2513 | 2.40k | int Offset = SignExtend32((Insn & 0xffff), 16); |
2514 | 2.40k | unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); |
2515 | 2.40k | unsigned Base = fieldFromInstruction_4(Insn, 21, 5); |
2516 | | |
2517 | 2.40k | Reg = getReg(Inst, Mips_FGR64RegClassID, Reg); |
2518 | 2.40k | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2519 | | |
2520 | 2.40k | MCOperand_CreateReg0(Inst, (Reg)); |
2521 | 2.40k | MCOperand_CreateReg0(Inst, (Base)); |
2522 | 2.40k | MCOperand_CreateImm0(Inst, (Offset)); |
2523 | | |
2524 | 2.40k | return MCDisassembler_Success; |
2525 | 2.40k | } |
2526 | | |
2527 | | static DecodeStatus DecodeFMemMMR2(MCInst *Inst, uint32_t Insn, |
2528 | | uint64_t Address, const void *Decoder) |
2529 | 1.76k | { |
2530 | | // This function is the same as DecodeFMem but with the Reg and Base fields |
2531 | | // swapped according to microMIPS spec. |
2532 | 1.76k | int Offset = SignExtend32((Insn & 0xffff), 16); |
2533 | 1.76k | unsigned Base = fieldFromInstruction_4(Insn, 16, 5); |
2534 | 1.76k | unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); |
2535 | | |
2536 | 1.76k | Reg = getReg(Inst, Mips_FGR64RegClassID, Reg); |
2537 | 1.76k | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2538 | | |
2539 | 1.76k | MCOperand_CreateReg0(Inst, (Reg)); |
2540 | 1.76k | MCOperand_CreateReg0(Inst, (Base)); |
2541 | 1.76k | MCOperand_CreateImm0(Inst, (Offset)); |
2542 | | |
2543 | 1.76k | return MCDisassembler_Success; |
2544 | 1.76k | } |
2545 | | |
2546 | | static DecodeStatus DecodeFMem2(MCInst *Inst, uint32_t Insn, uint64_t Address, |
2547 | | const void *Decoder) |
2548 | 872 | { |
2549 | 872 | int Offset = SignExtend32((Insn & 0xffff), 16); |
2550 | 872 | unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); |
2551 | 872 | unsigned Base = fieldFromInstruction_4(Insn, 21, 5); |
2552 | | |
2553 | 872 | Reg = getReg(Inst, Mips_COP2RegClassID, Reg); |
2554 | 872 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2555 | | |
2556 | 872 | MCOperand_CreateReg0(Inst, (Reg)); |
2557 | 872 | MCOperand_CreateReg0(Inst, (Base)); |
2558 | 872 | MCOperand_CreateImm0(Inst, (Offset)); |
2559 | | |
2560 | 872 | return MCDisassembler_Success; |
2561 | 872 | } |
2562 | | |
2563 | | static DecodeStatus DecodeFMem3(MCInst *Inst, uint32_t Insn, uint64_t Address, |
2564 | | const void *Decoder) |
2565 | 0 | { |
2566 | 0 | int Offset = SignExtend32((Insn & 0xffff), 16); |
2567 | 0 | unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); |
2568 | 0 | unsigned Base = fieldFromInstruction_4(Insn, 21, 5); |
2569 | |
|
2570 | 0 | Reg = getReg(Inst, Mips_COP3RegClassID, Reg); |
2571 | 0 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2572 | |
|
2573 | 0 | MCOperand_CreateReg0(Inst, (Reg)); |
2574 | 0 | MCOperand_CreateReg0(Inst, (Base)); |
2575 | 0 | MCOperand_CreateImm0(Inst, (Offset)); |
2576 | |
|
2577 | 0 | return MCDisassembler_Success; |
2578 | 0 | } |
2579 | | |
2580 | | static DecodeStatus DecodeFMemCop2R6(MCInst *Inst, uint32_t Insn, |
2581 | | uint64_t Address, const void *Decoder) |
2582 | 600 | { |
2583 | 600 | int Offset = SignExtend32((Insn & 0x07ff), 11); |
2584 | 600 | unsigned Reg = fieldFromInstruction_4(Insn, 16, 5); |
2585 | 600 | unsigned Base = fieldFromInstruction_4(Insn, 11, 5); |
2586 | | |
2587 | 600 | Reg = getReg(Inst, Mips_COP2RegClassID, Reg); |
2588 | 600 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2589 | | |
2590 | 600 | MCOperand_CreateReg0(Inst, (Reg)); |
2591 | 600 | MCOperand_CreateReg0(Inst, (Base)); |
2592 | 600 | MCOperand_CreateImm0(Inst, (Offset)); |
2593 | | |
2594 | 600 | return MCDisassembler_Success; |
2595 | 600 | } |
2596 | | |
2597 | | static DecodeStatus DecodeFMemCop2MMR6(MCInst *Inst, uint32_t Insn, |
2598 | | uint64_t Address, const void *Decoder) |
2599 | 656 | { |
2600 | 656 | int Offset = SignExtend32((Insn & 0x07ff), 11); |
2601 | 656 | unsigned Reg = fieldFromInstruction_4(Insn, 21, 5); |
2602 | 656 | unsigned Base = fieldFromInstruction_4(Insn, 16, 5); |
2603 | | |
2604 | 656 | Reg = getReg(Inst, Mips_COP2RegClassID, Reg); |
2605 | 656 | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2606 | | |
2607 | 656 | MCOperand_CreateReg0(Inst, (Reg)); |
2608 | 656 | MCOperand_CreateReg0(Inst, (Base)); |
2609 | 656 | MCOperand_CreateImm0(Inst, (Offset)); |
2610 | | |
2611 | 656 | return MCDisassembler_Success; |
2612 | 656 | } |
2613 | | |
2614 | | static DecodeStatus DecodeSpecial3LlSc(MCInst *Inst, uint32_t Insn, |
2615 | | uint64_t Address, const void *Decoder) |
2616 | 1.21k | { |
2617 | 1.21k | int64_t Offset = SignExtend64(((Insn >> 7) & 0x1ff), 9); |
2618 | 1.21k | unsigned Rt = fieldFromInstruction_4(Insn, 16, 5); |
2619 | 1.21k | unsigned Base = fieldFromInstruction_4(Insn, 21, 5); |
2620 | | |
2621 | 1.21k | Rt = getReg(Inst, Mips_GPR32RegClassID, Rt); |
2622 | 1.21k | Base = getReg(Inst, Mips_GPR32RegClassID, Base); |
2623 | | |
2624 | 1.21k | if (MCInst_getOpcode(Inst) == Mips_SC_R6 || |
2625 | 909 | MCInst_getOpcode(Inst) == Mips_SCD_R6) { |
2626 | 909 | MCOperand_CreateReg0(Inst, (Rt)); |
2627 | 909 | } |
2628 | | |
2629 | 1.21k | MCOperand_CreateReg0(Inst, (Rt)); |
2630 | 1.21k | MCOperand_CreateReg0(Inst, (Base)); |
2631 | 1.21k | MCOperand_CreateImm0(Inst, (Offset)); |
2632 | | |
2633 | 1.21k | return MCDisassembler_Success; |
2634 | 1.21k | } |
2635 | | |
2636 | | static DecodeStatus DecodeHWRegsRegisterClass(MCInst *Inst, unsigned RegNo, |
2637 | | uint64_t Address, |
2638 | | const void *Decoder) |
2639 | 598 | { |
2640 | | // Currently only hardware register 29 is supported. |
2641 | 598 | if (RegNo != 29) |
2642 | 20 | return MCDisassembler_Fail; |
2643 | 578 | MCOperand_CreateReg0(Inst, (Mips_HWR29)); |
2644 | 578 | return MCDisassembler_Success; |
2645 | 598 | } |
2646 | | |
2647 | | static DecodeStatus DecodeAFGR64RegisterClass(MCInst *Inst, unsigned RegNo, |
2648 | | uint64_t Address, |
2649 | | const void *Decoder) |
2650 | 9.97k | { |
2651 | 9.97k | if (RegNo > 30 || RegNo % 2) |
2652 | 62 | return MCDisassembler_Fail; |
2653 | | |
2654 | 9.90k | unsigned Reg = getReg(Inst, Mips_AFGR64RegClassID, RegNo / 2); |
2655 | 9.90k | MCOperand_CreateReg0(Inst, (Reg)); |
2656 | 9.90k | return MCDisassembler_Success; |
2657 | 9.97k | } |
2658 | | |
2659 | | static DecodeStatus DecodeACC64DSPRegisterClass(MCInst *Inst, unsigned RegNo, |
2660 | | uint64_t Address, |
2661 | | const void *Decoder) |
2662 | 4.69k | { |
2663 | 4.69k | if (RegNo >= 4) |
2664 | 0 | return MCDisassembler_Fail; |
2665 | | |
2666 | 4.69k | unsigned Reg = getReg(Inst, Mips_ACC64DSPRegClassID, RegNo); |
2667 | 4.69k | MCOperand_CreateReg0(Inst, (Reg)); |
2668 | 4.69k | return MCDisassembler_Success; |
2669 | 4.69k | } |
2670 | | |
2671 | | static DecodeStatus DecodeHI32DSPRegisterClass(MCInst *Inst, unsigned RegNo, |
2672 | | uint64_t Address, |
2673 | | const void *Decoder) |
2674 | 173 | { |
2675 | 173 | if (RegNo >= 4) |
2676 | 0 | return MCDisassembler_Fail; |
2677 | | |
2678 | 173 | unsigned Reg = getReg(Inst, Mips_HI32DSPRegClassID, RegNo); |
2679 | 173 | MCOperand_CreateReg0(Inst, (Reg)); |
2680 | 173 | return MCDisassembler_Success; |
2681 | 173 | } |
2682 | | |
2683 | | static DecodeStatus DecodeLO32DSPRegisterClass(MCInst *Inst, unsigned RegNo, |
2684 | | uint64_t Address, |
2685 | | const void *Decoder) |
2686 | 379 | { |
2687 | 379 | if (RegNo >= 4) |
2688 | 0 | return MCDisassembler_Fail; |
2689 | | |
2690 | 379 | unsigned Reg = getReg(Inst, Mips_LO32DSPRegClassID, RegNo); |
2691 | 379 | MCOperand_CreateReg0(Inst, (Reg)); |
2692 | 379 | return MCDisassembler_Success; |
2693 | 379 | } |
2694 | | |
2695 | | static DecodeStatus DecodeMSA128BRegisterClass(MCInst *Inst, unsigned RegNo, |
2696 | | uint64_t Address, |
2697 | | const void *Decoder) |
2698 | 20.4k | { |
2699 | 20.4k | if (RegNo > 31) |
2700 | 0 | return MCDisassembler_Fail; |
2701 | | |
2702 | 20.4k | unsigned Reg = getReg(Inst, Mips_MSA128BRegClassID, RegNo); |
2703 | 20.4k | MCOperand_CreateReg0(Inst, (Reg)); |
2704 | 20.4k | return MCDisassembler_Success; |
2705 | 20.4k | } |
2706 | | |
2707 | | static DecodeStatus DecodeMSA128HRegisterClass(MCInst *Inst, unsigned RegNo, |
2708 | | uint64_t Address, |
2709 | | const void *Decoder) |
2710 | 18.2k | { |
2711 | 18.2k | if (RegNo > 31) |
2712 | 0 | return MCDisassembler_Fail; |
2713 | | |
2714 | 18.2k | unsigned Reg = getReg(Inst, Mips_MSA128HRegClassID, RegNo); |
2715 | 18.2k | MCOperand_CreateReg0(Inst, (Reg)); |
2716 | 18.2k | return MCDisassembler_Success; |
2717 | 18.2k | } |
2718 | | |
2719 | | static DecodeStatus DecodeMSA128WRegisterClass(MCInst *Inst, unsigned RegNo, |
2720 | | uint64_t Address, |
2721 | | const void *Decoder) |
2722 | 20.3k | { |
2723 | 20.3k | if (RegNo > 31) |
2724 | 0 | return MCDisassembler_Fail; |
2725 | | |
2726 | 20.3k | unsigned Reg = getReg(Inst, Mips_MSA128WRegClassID, RegNo); |
2727 | 20.3k | MCOperand_CreateReg0(Inst, (Reg)); |
2728 | 20.3k | return MCDisassembler_Success; |
2729 | 20.3k | } |
2730 | | |
2731 | | static DecodeStatus DecodeMSA128DRegisterClass(MCInst *Inst, unsigned RegNo, |
2732 | | uint64_t Address, |
2733 | | const void *Decoder) |
2734 | 17.4k | { |
2735 | 17.4k | if (RegNo > 31) |
2736 | 0 | return MCDisassembler_Fail; |
2737 | | |
2738 | 17.4k | unsigned Reg = getReg(Inst, Mips_MSA128DRegClassID, RegNo); |
2739 | 17.4k | MCOperand_CreateReg0(Inst, (Reg)); |
2740 | 17.4k | return MCDisassembler_Success; |
2741 | 17.4k | } |
2742 | | |
2743 | | static DecodeStatus DecodeMSACtrlRegisterClass(MCInst *Inst, unsigned RegNo, |
2744 | | uint64_t Address, |
2745 | | const void *Decoder) |
2746 | 1.27k | { |
2747 | 1.27k | if (RegNo > 7) |
2748 | 5 | return MCDisassembler_Fail; |
2749 | | |
2750 | 1.27k | unsigned Reg = getReg(Inst, Mips_MSACtrlRegClassID, RegNo); |
2751 | 1.27k | MCOperand_CreateReg0(Inst, (Reg)); |
2752 | 1.27k | return MCDisassembler_Success; |
2753 | 1.27k | } |
2754 | | |
2755 | | static DecodeStatus DecodeCOP0RegisterClass(MCInst *Inst, unsigned RegNo, |
2756 | | uint64_t Address, |
2757 | | const void *Decoder) |
2758 | 513 | { |
2759 | 513 | if (RegNo > 31) |
2760 | 0 | return MCDisassembler_Fail; |
2761 | | |
2762 | 513 | unsigned Reg = getReg(Inst, Mips_COP0RegClassID, RegNo); |
2763 | 513 | MCOperand_CreateReg0(Inst, (Reg)); |
2764 | 513 | return MCDisassembler_Success; |
2765 | 513 | } |
2766 | | |
2767 | | static DecodeStatus DecodeCOP2RegisterClass(MCInst *Inst, unsigned RegNo, |
2768 | | uint64_t Address, |
2769 | | const void *Decoder) |
2770 | 1.34k | { |
2771 | 1.34k | if (RegNo > 31) |
2772 | 0 | return MCDisassembler_Fail; |
2773 | | |
2774 | 1.34k | unsigned Reg = getReg(Inst, Mips_COP2RegClassID, RegNo); |
2775 | 1.34k | MCOperand_CreateReg0(Inst, (Reg)); |
2776 | 1.34k | return MCDisassembler_Success; |
2777 | 1.34k | } |
2778 | | |
2779 | | static DecodeStatus DecodeBranchTarget(MCInst *Inst, unsigned Offset, |
2780 | | uint64_t Address, const void *Decoder) |
2781 | 20.5k | { |
2782 | 20.5k | int32_t BranchOffset = (SignExtend32((Offset), 16) * 4) + 4; |
2783 | 20.5k | MCOperand_CreateImm0(Inst, (BranchOffset)); |
2784 | 20.5k | return MCDisassembler_Success; |
2785 | 20.5k | } |
2786 | | |
2787 | | static DecodeStatus DecodeBranchTarget1SImm16(MCInst *Inst, unsigned Offset, |
2788 | | uint64_t Address, |
2789 | | const void *Decoder) |
2790 | 66 | { |
2791 | 66 | int32_t BranchOffset = (SignExtend32((Offset), 16) * 2); |
2792 | 66 | MCOperand_CreateImm0(Inst, (BranchOffset)); |
2793 | 66 | return MCDisassembler_Success; |
2794 | 66 | } |
2795 | | |
2796 | | static DecodeStatus DecodeJumpTarget(MCInst *Inst, uint32_t Insn, |
2797 | | uint64_t Address, const void *Decoder) |
2798 | 6.12k | { |
2799 | 6.12k | unsigned JumpOffset = fieldFromInstruction_4(Insn, 0, 26) << 2; |
2800 | 6.12k | MCOperand_CreateImm0(Inst, (JumpOffset)); |
2801 | 6.12k | return MCDisassembler_Success; |
2802 | 6.12k | } |
2803 | | |
2804 | | static DecodeStatus DecodeBranchTarget21(MCInst *Inst, unsigned Offset, |
2805 | | uint64_t Address, const void *Decoder) |
2806 | 969 | { |
2807 | 969 | int32_t BranchOffset = SignExtend32((Offset), 21) * 4 + 4; |
2808 | | |
2809 | 969 | MCOperand_CreateImm0(Inst, (BranchOffset)); |
2810 | 969 | return MCDisassembler_Success; |
2811 | 969 | } |
2812 | | |
2813 | | static DecodeStatus DecodeBranchTarget21MM(MCInst *Inst, unsigned Offset, |
2814 | | uint64_t Address, |
2815 | | const void *Decoder) |
2816 | 1.04k | { |
2817 | 1.04k | int32_t BranchOffset = SignExtend32((Offset), 21) * 4 + 4; |
2818 | | |
2819 | 1.04k | MCOperand_CreateImm0(Inst, (BranchOffset)); |
2820 | 1.04k | return MCDisassembler_Success; |
2821 | 1.04k | } |
2822 | | |
2823 | | static DecodeStatus DecodeBranchTarget26(MCInst *Inst, unsigned Offset, |
2824 | | uint64_t Address, const void *Decoder) |
2825 | 568 | { |
2826 | 568 | int32_t BranchOffset = SignExtend32((Offset), 26) * 4 + 4; |
2827 | | |
2828 | 568 | MCOperand_CreateImm0(Inst, (BranchOffset)); |
2829 | 568 | return MCDisassembler_Success; |
2830 | 568 | } |
2831 | | |
2832 | | static DecodeStatus DecodeBranchTarget7MM(MCInst *Inst, unsigned Offset, |
2833 | | uint64_t Address, const void *Decoder) |
2834 | 1.10k | { |
2835 | 1.10k | int32_t BranchOffset = SignExtend32((Offset << 1), 8); |
2836 | 1.10k | MCOperand_CreateImm0(Inst, (BranchOffset)); |
2837 | 1.10k | return MCDisassembler_Success; |
2838 | 1.10k | } |
2839 | | |
2840 | | static DecodeStatus DecodeBranchTarget10MM(MCInst *Inst, unsigned Offset, |
2841 | | uint64_t Address, |
2842 | | const void *Decoder) |
2843 | 636 | { |
2844 | 636 | int32_t BranchOffset = SignExtend32((Offset << 1), 11); |
2845 | 636 | MCOperand_CreateImm0(Inst, (BranchOffset)); |
2846 | 636 | return MCDisassembler_Success; |
2847 | 636 | } |
2848 | | |
2849 | | static DecodeStatus DecodeBranchTargetMM(MCInst *Inst, unsigned Offset, |
2850 | | uint64_t Address, const void *Decoder) |
2851 | 2.08k | { |
2852 | 2.08k | int32_t BranchOffset = SignExtend32((Offset), 16) * 2 + 4; |
2853 | 2.08k | MCOperand_CreateImm0(Inst, (BranchOffset)); |
2854 | 2.08k | return MCDisassembler_Success; |
2855 | 2.08k | } |
2856 | | |
2857 | | static DecodeStatus DecodeBranchTarget26MM(MCInst *Inst, unsigned Offset, |
2858 | | uint64_t Address, |
2859 | | const void *Decoder) |
2860 | 422 | { |
2861 | 422 | int32_t BranchOffset = SignExtend32((Offset << 1), 27); |
2862 | | |
2863 | 422 | MCOperand_CreateImm0(Inst, (BranchOffset)); |
2864 | 422 | return MCDisassembler_Success; |
2865 | 422 | } |
2866 | | |
2867 | | static DecodeStatus DecodeJumpTargetMM(MCInst *Inst, uint32_t Insn, |
2868 | | uint64_t Address, const void *Decoder) |
2869 | 1.01k | { |
2870 | 1.01k | unsigned JumpOffset = fieldFromInstruction_4(Insn, 0, 26) << 1; |
2871 | 1.01k | MCOperand_CreateImm0(Inst, (JumpOffset)); |
2872 | 1.01k | return MCDisassembler_Success; |
2873 | 1.01k | } |
2874 | | |
2875 | | #define DEFINE_DecodeBranchTargetNM(Bits) \ |
2876 | | static DecodeStatus CONCAT(DecodeBranchTargetNM, Bits)( \ |
2877 | | MCInst * Inst, unsigned Offset, uint64_t Address, \ |
2878 | | const void *Decoder) \ |
2879 | 0 | { \ |
2880 | 0 | uint32_t InsnSize = (Bits <= 10) ? 2 : 4; \ |
2881 | 0 | int32_t BranchOffset = \ |
2882 | 0 | SignExtend32((Offset), Bits + 1) + InsnSize; \ |
2883 | 0 | \ |
2884 | 0 | MCOperand_CreateImm0(Inst, (BranchOffset)); \ |
2885 | 0 | return MCDisassembler_Success; \ |
2886 | 0 | } Unexecuted instantiation: MipsDisassembler.c:DecodeBranchTargetNM_10 Unexecuted instantiation: MipsDisassembler.c:DecodeBranchTargetNM_7 Unexecuted instantiation: MipsDisassembler.c:DecodeBranchTargetNM_5 Unexecuted instantiation: MipsDisassembler.c:DecodeBranchTargetNM_21 Unexecuted instantiation: MipsDisassembler.c:DecodeBranchTargetNM_25 Unexecuted instantiation: MipsDisassembler.c:DecodeBranchTargetNM_14 Unexecuted instantiation: MipsDisassembler.c:DecodeBranchTargetNM_11 |
2887 | | DEFINE_DecodeBranchTargetNM(10); |
2888 | | DEFINE_DecodeBranchTargetNM(7); |
2889 | | DEFINE_DecodeBranchTargetNM(21); |
2890 | | DEFINE_DecodeBranchTargetNM(25); |
2891 | | DEFINE_DecodeBranchTargetNM(14); |
2892 | | DEFINE_DecodeBranchTargetNM(11); |
2893 | | DEFINE_DecodeBranchTargetNM(5); |
2894 | | |
2895 | | static DecodeStatus DecodeJumpTargetXMM(MCInst *Inst, uint32_t Insn, |
2896 | | uint64_t Address, const void *Decoder) |
2897 | 292 | { |
2898 | 292 | unsigned JumpOffset = fieldFromInstruction_4(Insn, 0, 26) << 2; |
2899 | 292 | MCOperand_CreateImm0(Inst, (JumpOffset)); |
2900 | 292 | return MCDisassembler_Success; |
2901 | 292 | } |
2902 | | |
2903 | | static DecodeStatus DecodeAddiur2Simm7(MCInst *Inst, unsigned Value, |
2904 | | uint64_t Address, const void *Decoder) |
2905 | 2.00k | { |
2906 | 2.00k | if (Value == 0) |
2907 | 466 | MCOperand_CreateImm0(Inst, (1)); |
2908 | 1.53k | else if (Value == 0x7) |
2909 | 506 | MCOperand_CreateImm0(Inst, (-1)); |
2910 | 1.03k | else |
2911 | 1.03k | MCOperand_CreateImm0(Inst, (Value << 2)); |
2912 | 2.00k | return MCDisassembler_Success; |
2913 | 2.00k | } |
2914 | | |
2915 | | static DecodeStatus DecodeLi16Imm(MCInst *Inst, unsigned Value, |
2916 | | uint64_t Address, const void *Decoder) |
2917 | 954 | { |
2918 | 954 | if (Value == 0x7F) |
2919 | 67 | MCOperand_CreateImm0(Inst, (-1)); |
2920 | 887 | else |
2921 | 887 | MCOperand_CreateImm0(Inst, (Value)); |
2922 | 954 | return MCDisassembler_Success; |
2923 | 954 | } |
2924 | | |
2925 | | static DecodeStatus DecodePOOL16BEncodedField(MCInst *Inst, unsigned Value, |
2926 | | uint64_t Address, |
2927 | | const void *Decoder) |
2928 | 687 | { |
2929 | 687 | MCOperand_CreateImm0(Inst, (Value == 0x0 ? 8 : Value)); |
2930 | 687 | return MCDisassembler_Success; |
2931 | 687 | } |
2932 | | |
2933 | | #define DEFINE_DecodeUImmWithOffsetAndScale(Bits, Offset, Scale) \ |
2934 | | static DecodeStatus CONCAT(DecodeUImmWithOffsetAndScale, \ |
2935 | | CONCAT(Bits, CONCAT(Offset, Scale)))( \ |
2936 | | MCInst * Inst, unsigned Value, uint64_t Address, \ |
2937 | | const void *Decoder) \ |
2938 | 1.95k | { \ |
2939 | 1.95k | Value &= ((1 << Bits) - 1); \ |
2940 | 1.95k | Value *= Scale; \ |
2941 | 1.95k | MCOperand_CreateImm0(Inst, (Value + Offset)); \ |
2942 | 1.95k | return MCDisassembler_Success; \ |
2943 | 1.95k | } MipsDisassembler.c:DecodeUImmWithOffsetAndScale_5_0_4 Line | Count | Source | 2938 | 563 | { \ | 2939 | 563 | Value &= ((1 << Bits) - 1); \ | 2940 | 563 | Value *= Scale; \ | 2941 | 563 | MCOperand_CreateImm0(Inst, (Value + Offset)); \ | 2942 | 563 | return MCDisassembler_Success; \ | 2943 | 563 | } |
MipsDisassembler.c:DecodeUImmWithOffsetAndScale_6_0_4 Line | Count | Source | 2938 | 427 | { \ | 2939 | 427 | Value &= ((1 << Bits) - 1); \ | 2940 | 427 | Value *= Scale; \ | 2941 | 427 | MCOperand_CreateImm0(Inst, (Value + Offset)); \ | 2942 | 427 | return MCDisassembler_Success; \ | 2943 | 427 | } |
MipsDisassembler.c:DecodeUImmWithOffsetAndScale_5_1_1 Line | Count | Source | 2938 | 429 | { \ | 2939 | 429 | Value &= ((1 << Bits) - 1); \ | 2940 | 429 | Value *= Scale; \ | 2941 | 429 | MCOperand_CreateImm0(Inst, (Value + Offset)); \ | 2942 | 429 | return MCDisassembler_Success; \ | 2943 | 429 | } |
MipsDisassembler.c:DecodeUImmWithOffsetAndScale_2_1_1 Line | Count | Source | 2938 | 533 | { \ | 2939 | 533 | Value &= ((1 << Bits) - 1); \ | 2940 | 533 | Value *= Scale; \ | 2941 | 533 | MCOperand_CreateImm0(Inst, (Value + Offset)); \ | 2942 | 533 | return MCDisassembler_Success; \ | 2943 | 533 | } |
Unexecuted instantiation: MipsDisassembler.c:DecodeUImmWithOffsetAndScale_8_0_1 Unexecuted instantiation: MipsDisassembler.c:DecodeUImmWithOffsetAndScale_21_0_1 Unexecuted instantiation: MipsDisassembler.c:DecodeUImmWithOffsetAndScale_18_0_1 |
2944 | | DEFINE_DecodeUImmWithOffsetAndScale(5, 0, 4); |
2945 | | DEFINE_DecodeUImmWithOffsetAndScale(6, 0, 4); |
2946 | | DEFINE_DecodeUImmWithOffsetAndScale(2, 1, 1); |
2947 | | DEFINE_DecodeUImmWithOffsetAndScale(5, 1, 1); |
2948 | | DEFINE_DecodeUImmWithOffsetAndScale(8, 0, 1); |
2949 | | DEFINE_DecodeUImmWithOffsetAndScale(18, 0, 1); |
2950 | | DEFINE_DecodeUImmWithOffsetAndScale(21, 0, 1); |
2951 | | |
2952 | | #define DEFINE_DecodeSImmWithOffsetAndScale(Bits, Offset, ScaleBy) \ |
2953 | | static DecodeStatus CONCAT(DecodeSImmWithOffsetAndScale, \ |
2954 | | CONCAT(Bits, CONCAT(Offset, ScaleBy)))( \ |
2955 | | MCInst * Inst, unsigned Value, uint64_t Address, \ |
2956 | | const void *Decoder) \ |
2957 | 10.6k | { \ |
2958 | 10.6k | int32_t Imm = SignExtend32((Value), Bits) * ScaleBy; \ |
2959 | 10.6k | MCOperand_CreateImm0(Inst, (Imm + Offset)); \ |
2960 | 10.6k | return MCDisassembler_Success; \ |
2961 | 10.6k | } MipsDisassembler.c:DecodeSImmWithOffsetAndScale_16_0_1 Line | Count | Source | 2957 | 9.75k | { \ | 2958 | 9.75k | int32_t Imm = SignExtend32((Value), Bits) * ScaleBy; \ | 2959 | 9.75k | MCOperand_CreateImm0(Inst, (Imm + Offset)); \ | 2960 | 9.75k | return MCDisassembler_Success; \ | 2961 | 9.75k | } |
MipsDisassembler.c:DecodeSImmWithOffsetAndScale_10_0_1 Line | Count | Source | 2957 | 68 | { \ | 2958 | 68 | int32_t Imm = SignExtend32((Value), Bits) * ScaleBy; \ | 2959 | 68 | MCOperand_CreateImm0(Inst, (Imm + Offset)); \ | 2960 | 68 | return MCDisassembler_Success; \ | 2961 | 68 | } |
MipsDisassembler.c:DecodeSImmWithOffsetAndScale_4_0_1 Line | Count | Source | 2957 | 344 | { \ | 2958 | 344 | int32_t Imm = SignExtend32((Value), Bits) * ScaleBy; \ | 2959 | 344 | MCOperand_CreateImm0(Inst, (Imm + Offset)); \ | 2960 | 344 | return MCDisassembler_Success; \ | 2961 | 344 | } |
MipsDisassembler.c:DecodeSImmWithOffsetAndScale_6_0_1 Line | Count | Source | 2957 | 530 | { \ | 2958 | 530 | int32_t Imm = SignExtend32((Value), Bits) * ScaleBy; \ | 2959 | 530 | MCOperand_CreateImm0(Inst, (Imm + Offset)); \ | 2960 | 530 | return MCDisassembler_Success; \ | 2961 | 530 | } |
Unexecuted instantiation: MipsDisassembler.c:DecodeSImmWithOffsetAndScale_32_0_1 |
2962 | | |
2963 | | #define DEFINE_DecodeSImmWithOffsetAndScale_2(Bits, Offset) \ |
2964 | | DEFINE_DecodeSImmWithOffsetAndScale(Bits, Offset, 1) |
2965 | | #define DEFINE_DecodeSImmWithOffsetAndScale_3(Bits) \ |
2966 | | DEFINE_DecodeSImmWithOffsetAndScale(Bits, 0, 1) |
2967 | | |
2968 | | DEFINE_DecodeSImmWithOffsetAndScale_3(16); |
2969 | | DEFINE_DecodeSImmWithOffsetAndScale_3(10); |
2970 | | DEFINE_DecodeSImmWithOffsetAndScale_3(4); |
2971 | | DEFINE_DecodeSImmWithOffsetAndScale_3(6); |
2972 | | DEFINE_DecodeSImmWithOffsetAndScale_3(32); |
2973 | | |
2974 | | static DecodeStatus DecodeInsSize(MCInst *Inst, uint32_t Insn, uint64_t Address, |
2975 | | const void *Decoder) |
2976 | 917 | { |
2977 | | // First we need to grab the pos(lsb) from MCInst. |
2978 | | // This function only handles the 32 bit variants of ins, as dins |
2979 | | // variants are handled differently. |
2980 | 917 | int Pos = MCOperand_getImm(MCInst_getOperand(Inst, (2))); |
2981 | 917 | int Size = (int)Insn - Pos + 1; |
2982 | 917 | MCOperand_CreateImm0(Inst, (SignExtend32((Size), 16))); |
2983 | 917 | return MCDisassembler_Success; |
2984 | 917 | } |
2985 | | |
2986 | | static DecodeStatus DecodeSimm19Lsl2(MCInst *Inst, uint32_t Insn, |
2987 | | uint64_t Address, const void *Decoder) |
2988 | 541 | { |
2989 | 541 | MCOperand_CreateImm0(Inst, (SignExtend32((Insn), 19) * 4)); |
2990 | 541 | return MCDisassembler_Success; |
2991 | 541 | } |
2992 | | |
2993 | | static DecodeStatus DecodeSimm18Lsl3(MCInst *Inst, uint32_t Insn, |
2994 | | uint64_t Address, const void *Decoder) |
2995 | 0 | { |
2996 | 0 | MCOperand_CreateImm0(Inst, (SignExtend32((Insn), 18) * 8)); |
2997 | 0 | return MCDisassembler_Success; |
2998 | 0 | } |
2999 | | |
3000 | | static DecodeStatus DecodeSimm9SP(MCInst *Inst, uint32_t Insn, uint64_t Address, |
3001 | | const void *Decoder) |
3002 | 2.04k | { |
3003 | 2.04k | int32_t DecodedValue; |
3004 | 2.04k | switch (Insn) { |
3005 | 380 | case 0: |
3006 | 380 | DecodedValue = 256; |
3007 | 380 | break; |
3008 | 406 | case 1: |
3009 | 406 | DecodedValue = 257; |
3010 | 406 | break; |
3011 | 270 | case 510: |
3012 | 270 | DecodedValue = -258; |
3013 | 270 | break; |
3014 | 392 | case 511: |
3015 | 392 | DecodedValue = -257; |
3016 | 392 | break; |
3017 | 600 | default: |
3018 | 600 | DecodedValue = SignExtend32((Insn), 9); |
3019 | 600 | break; |
3020 | 2.04k | } |
3021 | 2.04k | MCOperand_CreateImm0(Inst, (DecodedValue * 4)); |
3022 | 2.04k | return MCDisassembler_Success; |
3023 | 2.04k | } |
3024 | | |
3025 | | static DecodeStatus DecodeANDI16Imm(MCInst *Inst, uint32_t Insn, |
3026 | | uint64_t Address, const void *Decoder) |
3027 | 1.24k | { |
3028 | | // Insn must be >= 0, since it is unsigned that condition is always true. |
3029 | | |
3030 | 1.24k | int32_t DecodedValues[] = { 128, 1, 2, 3, 4, 7, 8, 15, |
3031 | 1.24k | 16, 31, 32, 63, 64, 255, 32768, 65535 }; |
3032 | 1.24k | MCOperand_CreateImm0(Inst, (DecodedValues[Insn])); |
3033 | 1.24k | return MCDisassembler_Success; |
3034 | 1.24k | } |
3035 | | |
3036 | | static DecodeStatus DecodeRegListOperand(MCInst *Inst, uint32_t Insn, |
3037 | | uint64_t Address, const void *Decoder) |
3038 | 211 | { |
3039 | 211 | unsigned Regs[] = { Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, |
3040 | 211 | Mips_S5, Mips_S6, Mips_S7, Mips_FP }; |
3041 | 211 | unsigned RegNum; |
3042 | | |
3043 | 211 | unsigned RegLst = fieldFromInstruction_4(Insn, 21, 5); |
3044 | | |
3045 | | // Empty register lists are not allowed. |
3046 | 211 | if (RegLst == 0) |
3047 | 1 | return MCDisassembler_Fail; |
3048 | | |
3049 | 210 | RegNum = RegLst & 0xf; |
3050 | | |
3051 | | // RegLst values 10-15, and 26-31 are reserved. |
3052 | 210 | if (RegNum > 9) |
3053 | 1 | return MCDisassembler_Fail; |
3054 | | |
3055 | 1.24k | for (unsigned i = 0; i < RegNum; i++) |
3056 | 1.03k | MCOperand_CreateReg0(Inst, (Regs[i])); |
3057 | | |
3058 | 209 | if (RegLst & 0x10) |
3059 | 131 | MCOperand_CreateReg0(Inst, (Mips_RA)); |
3060 | | |
3061 | 209 | return MCDisassembler_Success; |
3062 | 210 | } |
3063 | | |
3064 | | static DecodeStatus DecodeRegListOperand16(MCInst *Inst, uint32_t Insn, |
3065 | | uint64_t Address, |
3066 | | const void *Decoder) |
3067 | 901 | { |
3068 | 901 | unsigned Regs[] = { Mips_S0, Mips_S1, Mips_S2, Mips_S3 }; |
3069 | 901 | unsigned RegLst; |
3070 | 901 | switch (MCInst_getOpcode(Inst)) { |
3071 | 481 | default: |
3072 | 481 | RegLst = fieldFromInstruction_4(Insn, 4, 2); |
3073 | 481 | break; |
3074 | 83 | case Mips_LWM16_MMR6: |
3075 | 420 | case Mips_SWM16_MMR6: |
3076 | 420 | RegLst = fieldFromInstruction_4(Insn, 8, 2); |
3077 | 420 | break; |
3078 | 901 | } |
3079 | 901 | unsigned RegNum = RegLst & 0x3; |
3080 | | |
3081 | 2.92k | for (unsigned i = 0; i <= RegNum; i++) |
3082 | 2.02k | MCOperand_CreateReg0(Inst, (Regs[i])); |
3083 | | |
3084 | 901 | MCOperand_CreateReg0(Inst, (Mips_RA)); |
3085 | | |
3086 | 901 | return MCDisassembler_Success; |
3087 | 901 | } |
3088 | | |
3089 | | static DecodeStatus DecodeMovePOperands(MCInst *Inst, uint32_t Insn, |
3090 | | uint64_t Address, const void *Decoder) |
3091 | 1.10k | { |
3092 | 1.10k | unsigned RegPair = fieldFromInstruction_4(Insn, 7, 3); |
3093 | 1.10k | if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) == |
3094 | 1.10k | MCDisassembler_Fail) |
3095 | 0 | return MCDisassembler_Fail; |
3096 | | |
3097 | 1.10k | unsigned RegRs; |
3098 | 1.10k | if (Inst->csh->mode & CS_MODE_MIPS32R6) |
3099 | 751 | RegRs = fieldFromInstruction_4(Insn, 0, 2) | |
3100 | 751 | (fieldFromInstruction_4(Insn, 3, 1) << 2); |
3101 | 350 | else |
3102 | 350 | RegRs = fieldFromInstruction_4(Insn, 1, 3); |
3103 | 1.10k | if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) == |
3104 | 1.10k | MCDisassembler_Fail) |
3105 | 0 | return MCDisassembler_Fail; |
3106 | | |
3107 | 1.10k | unsigned RegRt = fieldFromInstruction_4(Insn, 4, 3); |
3108 | 1.10k | if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) == |
3109 | 1.10k | MCDisassembler_Fail) |
3110 | 0 | return MCDisassembler_Fail; |
3111 | | |
3112 | 1.10k | return MCDisassembler_Success; |
3113 | 1.10k | } |
3114 | | |
3115 | | static DecodeStatus DecodeMovePRegPair(MCInst *Inst, unsigned RegPair, |
3116 | | uint64_t Address, const void *Decoder) |
3117 | 1.36k | { |
3118 | 1.36k | switch (RegPair) { |
3119 | 0 | default: |
3120 | 0 | return MCDisassembler_Fail; |
3121 | 277 | case 0: |
3122 | 277 | MCOperand_CreateReg0(Inst, (Mips_A1)); |
3123 | 277 | MCOperand_CreateReg0(Inst, (Mips_A2)); |
3124 | 277 | break; |
3125 | 38 | case 1: |
3126 | 38 | MCOperand_CreateReg0(Inst, (Mips_A1)); |
3127 | 38 | MCOperand_CreateReg0(Inst, (Mips_A3)); |
3128 | 38 | break; |
3129 | 21 | case 2: |
3130 | 21 | MCOperand_CreateReg0(Inst, (Mips_A2)); |
3131 | 21 | MCOperand_CreateReg0(Inst, (Mips_A3)); |
3132 | 21 | break; |
3133 | 13 | case 3: |
3134 | 13 | MCOperand_CreateReg0(Inst, (Mips_A0)); |
3135 | 13 | MCOperand_CreateReg0(Inst, (Mips_S5)); |
3136 | 13 | break; |
3137 | 660 | case 4: |
3138 | 660 | MCOperand_CreateReg0(Inst, (Mips_A0)); |
3139 | 660 | MCOperand_CreateReg0(Inst, (Mips_S6)); |
3140 | 660 | break; |
3141 | 317 | case 5: |
3142 | 317 | MCOperand_CreateReg0(Inst, (Mips_A0)); |
3143 | 317 | MCOperand_CreateReg0(Inst, (Mips_A1)); |
3144 | 317 | break; |
3145 | 33 | case 6: |
3146 | 33 | MCOperand_CreateReg0(Inst, (Mips_A0)); |
3147 | 33 | MCOperand_CreateReg0(Inst, (Mips_A2)); |
3148 | 33 | break; |
3149 | 1 | case 7: |
3150 | 1 | MCOperand_CreateReg0(Inst, (Mips_A0)); |
3151 | 1 | MCOperand_CreateReg0(Inst, (Mips_A3)); |
3152 | 1 | break; |
3153 | 1.36k | } |
3154 | | |
3155 | 1.36k | return MCDisassembler_Success; |
3156 | 1.36k | } |
3157 | | |
3158 | | static DecodeStatus DecodeSimm23Lsl2(MCInst *Inst, uint32_t Insn, |
3159 | | uint64_t Address, const void *Decoder) |
3160 | 714 | { |
3161 | 714 | MCOperand_CreateImm0(Inst, (SignExtend32((Insn << 2), 25))); |
3162 | 714 | return MCDisassembler_Success; |
3163 | 714 | } |
3164 | | |
3165 | | static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst *MI, uint32_t insn, |
3166 | | uint64_t Address, |
3167 | | const void *Decoder) |
3168 | 744 | { |
3169 | | // We have: |
3170 | | // 0b000111 ttttt sssss iiiiiiiiiiiiiiii |
3171 | | // Invalid if rt == 0 |
3172 | | // BGTZALC_MMR6 if rs == 0 && rt != 0 |
3173 | | // BLTZALC_MMR6 if rs != 0 && rs == rt |
3174 | | // BLTUC_MMR6 if rs != 0 && rs != rt |
3175 | | |
3176 | 744 | uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); |
3177 | 744 | uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); |
3178 | 744 | uint32_t Imm = 0; |
3179 | 744 | bool HasRs = false; |
3180 | 744 | bool HasRt = false; |
3181 | | |
3182 | 744 | if (Rt == 0) |
3183 | 8 | return MCDisassembler_Fail; |
3184 | 736 | else if (Rs == 0) { |
3185 | 211 | MCInst_setOpcode(MI, (Mips_BGTZALC_MMR6)); |
3186 | 211 | HasRt = true; |
3187 | 211 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
3188 | 211 | 2 + |
3189 | 211 | 4; |
3190 | 525 | } else if (Rs == Rt) { |
3191 | 171 | MCInst_setOpcode(MI, (Mips_BLTZALC_MMR6)); |
3192 | 171 | HasRs = true; |
3193 | 171 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
3194 | 171 | 2 + |
3195 | 171 | 4; |
3196 | 354 | } else { |
3197 | 354 | MCInst_setOpcode(MI, (Mips_BLTUC_MMR6)); |
3198 | 354 | HasRs = true; |
3199 | 354 | HasRt = true; |
3200 | 354 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
3201 | 354 | 4 + |
3202 | 354 | 4; |
3203 | 354 | } |
3204 | | |
3205 | 736 | if (HasRs) |
3206 | 525 | MCOperand_CreateReg0(MI, |
3207 | 525 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
3208 | | |
3209 | 736 | if (HasRt) |
3210 | 565 | MCOperand_CreateReg0(MI, |
3211 | 565 | (getReg(MI, Mips_GPR32RegClassID, Rt))); |
3212 | | |
3213 | 736 | MCOperand_CreateImm0(MI, (Imm)); |
3214 | | |
3215 | 736 | return MCDisassembler_Success; |
3216 | 744 | } |
3217 | | |
3218 | | static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst *MI, uint32_t insn, |
3219 | | uint64_t Address, |
3220 | | const void *Decoder) |
3221 | 762 | { |
3222 | | // We have: |
3223 | | // 0b000110 ttttt sssss iiiiiiiiiiiiiiii |
3224 | | // Invalid if rt == 0 |
3225 | | // BLEZALC_MMR6 if rs == 0 && rt != 0 |
3226 | | // BGEZALC_MMR6 if rs == rt && rt != 0 |
3227 | | // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 |
3228 | | |
3229 | 762 | uint32_t Rt = fieldFromInstruction_4(insn, 21, 5); |
3230 | 762 | uint32_t Rs = fieldFromInstruction_4(insn, 16, 5); |
3231 | 762 | uint32_t Imm = 0; |
3232 | 762 | bool HasRs = false; |
3233 | | |
3234 | 762 | if (Rt == 0) |
3235 | 4 | return MCDisassembler_Fail; |
3236 | 758 | else if (Rs == 0) { |
3237 | 290 | MCInst_setOpcode(MI, (Mips_BLEZALC_MMR6)); |
3238 | 290 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
3239 | 290 | 2 + |
3240 | 290 | 4; |
3241 | 468 | } else if (Rs == Rt) { |
3242 | 69 | MCInst_setOpcode(MI, (Mips_BGEZALC_MMR6)); |
3243 | 69 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
3244 | 69 | 2 + |
3245 | 69 | 4; |
3246 | 399 | } else { |
3247 | 399 | HasRs = true; |
3248 | 399 | MCInst_setOpcode(MI, (Mips_BGEUC_MMR6)); |
3249 | 399 | Imm = SignExtend64(fieldFromInstruction_4(insn, 0, 16), 16) * |
3250 | 399 | 4 + |
3251 | 399 | 4; |
3252 | 399 | } |
3253 | | |
3254 | 758 | if (HasRs) |
3255 | 399 | MCOperand_CreateReg0(MI, |
3256 | 399 | (getReg(MI, Mips_GPR32RegClassID, Rs))); |
3257 | 758 | MCOperand_CreateReg0(MI, (getReg(MI, Mips_GPR32RegClassID, Rt))); |
3258 | | |
3259 | 758 | MCOperand_CreateImm0(MI, (Imm)); |
3260 | | |
3261 | 758 | return MCDisassembler_Success; |
3262 | 762 | } |
3263 | | |
3264 | | // This instruction does not have a working decoder, and needs to be |
3265 | | // fixed. This "fixme" function was introduced to keep the backend compiling, |
3266 | | // while making changes to tablegen code. |
3267 | | static DecodeStatus DecodeFIXMEInstruction(MCInst *Inst, uint32_t Insn, |
3268 | | uint64_t Address, |
3269 | | const void *Decoder) |
3270 | 0 | { |
3271 | 0 | return MCDisassembler_Fail; |
3272 | 0 | } |
3273 | | |
3274 | | static DecodeStatus DecodeImmM1To126(MCInst *Inst, unsigned Value, |
3275 | | uint64_t Address, const void *Decoder) |
3276 | 0 | { |
3277 | 0 | if (Value == 127) |
3278 | 0 | MCOperand_CreateImm0(Inst, (-1)); |
3279 | 0 | else |
3280 | 0 | MCOperand_CreateImm0(Inst, (Value)); |
3281 | 0 | return MCDisassembler_Success; |
3282 | 0 | } |
3283 | | |
3284 | | static DecodeStatus DecodeUImm4Mask(MCInst *Inst, unsigned Value, |
3285 | | uint64_t Address, const void *Decoder) |
3286 | 0 | { |
3287 | 0 | if (Value == 12) |
3288 | 0 | MCOperand_CreateImm0(Inst, (0xff)); |
3289 | 0 | else if (Value == 13) |
3290 | 0 | MCOperand_CreateImm0(Inst, (0xffff)); |
3291 | 0 | else |
3292 | 0 | MCOperand_CreateImm0(Inst, (Value)); |
3293 | 0 | return MCDisassembler_Success; |
3294 | 0 | } |
3295 | | |
3296 | | static DecodeStatus DecodeUImm3Shift(MCInst *Inst, unsigned Value, |
3297 | | uint64_t Address, const void *Decoder) |
3298 | 0 | { |
3299 | 0 | if (Value == 0) |
3300 | 0 | MCOperand_CreateImm0(Inst, (8)); |
3301 | 0 | else |
3302 | 0 | MCOperand_CreateImm0(Inst, (Value)); |
3303 | 0 | return MCDisassembler_Success; |
3304 | 0 | } |
3305 | | |
3306 | | static DecodeStatus DecodeNMRegListOperand(MCInst *Inst, uint32_t Insn, |
3307 | | uint64_t Address, |
3308 | | const void *Decoder) |
3309 | 0 | { |
3310 | 0 | unsigned RegStart = fieldFromInstruction_4(Insn, 5, 5); |
3311 | 0 | unsigned RegCount = fieldFromInstruction_4(Insn, 1, 4); |
3312 | 0 | unsigned GP_bit = fieldFromInstruction_4(Insn, 0, 1); |
3313 | 0 | unsigned i; |
3314 | 0 | unsigned RegNo; |
3315 | |
|
3316 | 0 | MCOperand_CreateReg0(Inst, |
3317 | 0 | (getReg(Inst, Mips_GPRNM32RegClassID, RegStart))); |
3318 | 0 | for (i = RegStart + 1; i < RegStart + RegCount; i++) { |
3319 | 0 | if (i == RegStart + RegCount - 1 && GP_bit) |
3320 | 0 | RegNo = 28; |
3321 | 0 | else if (i > 31) |
3322 | 0 | RegNo = 16 + (i % 32); // $ra+1 wraps to $s0 |
3323 | 0 | else |
3324 | 0 | RegNo = i; |
3325 | 0 | MCOperand_CreateReg0( |
3326 | 0 | Inst, (getReg(Inst, Mips_GPRNM32RegClassID, RegNo))); |
3327 | 0 | } |
3328 | 0 | return MCDisassembler_Success; |
3329 | 0 | } |
3330 | | |
3331 | | static DecodeStatus DecodeNMRegList16Operand(MCInst *Inst, uint32_t Insn, |
3332 | | uint64_t Address, |
3333 | | const void *Decoder) |
3334 | 0 | { |
3335 | 0 | unsigned RegStart = 30 + fieldFromInstruction_4(Insn, 4, 1); |
3336 | 0 | unsigned RegCount = fieldFromInstruction_4(Insn, 0, 4); |
3337 | | // Re-encode the parameters for 32-bit instruction operand |
3338 | | // and call it's decoder |
3339 | 0 | return DecodeNMRegListOperand(Inst, (RegStart << 5) | (RegCount << 1), |
3340 | 0 | Address, Decoder); |
3341 | 0 | } |
3342 | | |
3343 | | static DecodeStatus DecodeNegImm12(MCInst *Inst, uint32_t Insn, |
3344 | | uint64_t Address, const void *Decoder) |
3345 | 0 | { |
3346 | 0 | int Imm = fieldFromInstruction_4(Insn, 0, 12); |
3347 | |
|
3348 | 0 | MCOperand_CreateImm0(Inst, (-Imm)); |
3349 | 0 | return MCDisassembler_Success; |
3350 | 0 | } |
3351 | | |
3352 | | #define DEFINE_DecodeSImmWithReg(Bits, Offset, Scale, RegNum) \ |
3353 | | static DecodeStatus CONCAT( \ |
3354 | | DecodeSImmWithReg, \ |
3355 | | CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ |
3356 | | MCInst * Inst, unsigned Value, uint64_t Address, \ |
3357 | | const void *Decoder) \ |
3358 | 0 | { \ |
3359 | 0 | MCOperand_CreateReg0(Inst, (RegNum)); \ |
3360 | 0 | return CONCAT(DecodeSImmWithOffsetAndScale, \ |
3361 | 0 | CONCAT(Bits, CONCAT(Offset, Scale)))( \ |
3362 | 0 | Inst, Value, Address, Decoder); \ |
3363 | 0 | } |
3364 | | DEFINE_DecodeSImmWithReg(32, 0, 1, Mips_GP_NM); |
3365 | | |
3366 | | #define DEFINE_DecodeUImmWithReg(Bits, Offset, Scale, RegNum) \ |
3367 | | static DecodeStatus CONCAT( \ |
3368 | | DecodeUImmWithReg, \ |
3369 | | CONCAT(Bits, CONCAT(Offset, CONCAT(Scale, RegNum))))( \ |
3370 | | MCInst * Inst, unsigned Value, uint64_t Address, \ |
3371 | | const void *Decoder) \ |
3372 | 0 | { \ |
3373 | 0 | MCOperand_CreateReg0(Inst, (RegNum)); \ |
3374 | 0 | return CONCAT(DecodeUImmWithOffsetAndScale, \ |
3375 | 0 | CONCAT(Bits, CONCAT(Offset, Scale)))( \ |
3376 | 0 | Inst, Value, Address, Decoder); \ |
3377 | 0 | } Unexecuted instantiation: MipsDisassembler.c:DecodeUImmWithReg_8_0_1_Mips_SP_NM Unexecuted instantiation: MipsDisassembler.c:DecodeUImmWithReg_21_0_1_Mips_GP_NM Unexecuted instantiation: MipsDisassembler.c:DecodeUImmWithReg_18_0_1_Mips_GP_NM |
3378 | | DEFINE_DecodeUImmWithReg(8, 0, 1, Mips_SP_NM); |
3379 | | DEFINE_DecodeUImmWithReg(21, 0, 1, Mips_GP_NM); |
3380 | | DEFINE_DecodeUImmWithReg(18, 0, 1, Mips_GP_NM); |
3381 | | |
3382 | | static DecodeStatus DecodeSImm32s12(MCInst *Inst, uint32_t Insn, |
3383 | | uint64_t Address, const void *Decoder) |
3384 | 0 | { |
3385 | 0 | uint64_t Imm = ((uint64_t)Insn) << 12; |
3386 | 0 | MCOperand_CreateImm0(Inst, (Imm)); |
3387 | 0 | return MCDisassembler_Success; |
3388 | 0 | } |
3389 | | |
3390 | | #define DEFINE_DecodeAddressPCRelNM(Bits) \ |
3391 | | static DecodeStatus CONCAT(DecodeAddressPCRelNM, Bits)( \ |
3392 | | MCInst * Inst, unsigned Offset, uint64_t Address, \ |
3393 | | const void *Decoder) \ |
3394 | 0 | { \ |
3395 | 0 | uint32_t InsnSize = Bits == 32 ? 6 : 4; \ |
3396 | 0 | int32_t BranchOffset = \ |
3397 | 0 | SignExtend32((Offset), Bits) + InsnSize; \ |
3398 | 0 | \ |
3399 | 0 | MCOperand_CreateImm0(Inst, (BranchOffset)); \ |
3400 | 0 | return MCDisassembler_Success; \ |
3401 | 0 | } Unexecuted instantiation: MipsDisassembler.c:DecodeAddressPCRelNM_22 Unexecuted instantiation: MipsDisassembler.c:DecodeAddressPCRelNM_32 |
3402 | | DEFINE_DecodeAddressPCRelNM(22); |
3403 | | DEFINE_DecodeAddressPCRelNM(32); |
3404 | | |
3405 | | static DecodeStatus DecodeBranchConflictNM(MCInst *Inst, uint32_t Insn, |
3406 | | uint64_t Address, |
3407 | | const void *Decoder) |
3408 | 0 | { |
3409 | 0 | unsigned Rt = fieldFromInstruction_4(Insn, 7, 3); |
3410 | 0 | unsigned Rs = fieldFromInstruction_4(Insn, 4, 3); |
3411 | 0 | unsigned Offset = fieldFromInstruction_4(Insn, 0, 4) << 1; |
3412 | 0 | if (Rs < Rt) |
3413 | 0 | MCInst_setOpcode(Inst, (Mips_BEQC16_NM)); |
3414 | 0 | else |
3415 | 0 | MCInst_setOpcode(Inst, (Mips_BNEC16_NM)); |
3416 | 0 | if (DecodeGPRNM3RegisterClass(Inst, Rt, Address, Decoder) == |
3417 | 0 | MCDisassembler_Success && |
3418 | 0 | DecodeGPRNM3RegisterClass(Inst, Rs, Address, Decoder) == |
3419 | 0 | MCDisassembler_Success) |
3420 | 0 | return CONCAT(DecodeBranchTargetNM, 5)(Inst, Offset, Address, |
3421 | 0 | Decoder); |
3422 | 0 | else |
3423 | 0 | return MCDisassembler_Fail; |
3424 | 0 | } |
3425 | | |
3426 | | DecodeStatus Mips_LLVM_getInstruction(MCInst *Instr, uint64_t *Size, |
3427 | | const uint8_t *Bytes, size_t BytesLen, |
3428 | | uint64_t Address, SStream *CStream) |
3429 | 137k | { |
3430 | 137k | return getInstruction(Instr, Size, Bytes, BytesLen, Address, CStream); |
3431 | 137k | } |