Coverage Report

Created: 2026-02-14 06:57

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/rust/registry/src/index.crates.io-1949cf8c6b5b557f/iced-x86-1.21.0/src/register.rs
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// SPDX-License-Identifier: MIT
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// Copyright (C) 2018-present iced project and contributors
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use crate::iced_constants::IcedConstants;
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use crate::iced_error::IcedError;
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use core::iter::{ExactSizeIterator, FusedIterator, Iterator};
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use core::ops::{Add, AddAssign, Sub, SubAssign};
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use core::{fmt, mem};
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#[cfg(feature = "instr_info")]
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pub use crate::register::info::*;
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#[cfg(feature = "instr_info")]
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mod info {
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  use crate::iced_constants::IcedConstants;
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  use crate::Register;
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  #[rustfmt::skip]
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  #[allow(deprecated)]
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  pub(super) static REGISTER_INFOS: &[RegisterInfo; IcedConstants::REGISTER_ENUM_COUNT] = &[
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    // GENERATOR-BEGIN: RegisterInfoTable
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    // ⚠️This was generated by GENERATOR!🦹‍♂️
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    RegisterInfo { register: Register::None, base: Register::None, full_register32: Register::None, full_register: Register::None, size: 0 },
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    RegisterInfo { register: Register::AL, base: Register::AL, full_register32: Register::EAX, full_register: Register::RAX, size: 1 },
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    RegisterInfo { register: Register::CL, base: Register::AL, full_register32: Register::ECX, full_register: Register::RCX, size: 1 },
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    RegisterInfo { register: Register::DL, base: Register::AL, full_register32: Register::EDX, full_register: Register::RDX, size: 1 },
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    RegisterInfo { register: Register::BL, base: Register::AL, full_register32: Register::EBX, full_register: Register::RBX, size: 1 },
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    RegisterInfo { register: Register::AH, base: Register::AL, full_register32: Register::EAX, full_register: Register::RAX, size: 1 },
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    RegisterInfo { register: Register::CH, base: Register::AL, full_register32: Register::ECX, full_register: Register::RCX, size: 1 },
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    RegisterInfo { register: Register::DH, base: Register::AL, full_register32: Register::EDX, full_register: Register::RDX, size: 1 },
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    RegisterInfo { register: Register::BH, base: Register::AL, full_register32: Register::EBX, full_register: Register::RBX, size: 1 },
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    RegisterInfo { register: Register::SPL, base: Register::AL, full_register32: Register::ESP, full_register: Register::RSP, size: 1 },
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    RegisterInfo { register: Register::BPL, base: Register::AL, full_register32: Register::EBP, full_register: Register::RBP, size: 1 },
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    RegisterInfo { register: Register::SIL, base: Register::AL, full_register32: Register::ESI, full_register: Register::RSI, size: 1 },
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    RegisterInfo { register: Register::DIL, base: Register::AL, full_register32: Register::EDI, full_register: Register::RDI, size: 1 },
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    RegisterInfo { register: Register::R8L, base: Register::AL, full_register32: Register::R8D, full_register: Register::R8, size: 1 },
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    RegisterInfo { register: Register::R9L, base: Register::AL, full_register32: Register::R9D, full_register: Register::R9, size: 1 },
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    RegisterInfo { register: Register::R10L, base: Register::AL, full_register32: Register::R10D, full_register: Register::R10, size: 1 },
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    RegisterInfo { register: Register::R11L, base: Register::AL, full_register32: Register::R11D, full_register: Register::R11, size: 1 },
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    RegisterInfo { register: Register::R12L, base: Register::AL, full_register32: Register::R12D, full_register: Register::R12, size: 1 },
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    RegisterInfo { register: Register::R13L, base: Register::AL, full_register32: Register::R13D, full_register: Register::R13, size: 1 },
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    RegisterInfo { register: Register::R14L, base: Register::AL, full_register32: Register::R14D, full_register: Register::R14, size: 1 },
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    RegisterInfo { register: Register::R15L, base: Register::AL, full_register32: Register::R15D, full_register: Register::R15, size: 1 },
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    RegisterInfo { register: Register::AX, base: Register::AX, full_register32: Register::EAX, full_register: Register::RAX, size: 2 },
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    RegisterInfo { register: Register::CX, base: Register::AX, full_register32: Register::ECX, full_register: Register::RCX, size: 2 },
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    RegisterInfo { register: Register::DX, base: Register::AX, full_register32: Register::EDX, full_register: Register::RDX, size: 2 },
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    RegisterInfo { register: Register::BX, base: Register::AX, full_register32: Register::EBX, full_register: Register::RBX, size: 2 },
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    RegisterInfo { register: Register::SP, base: Register::AX, full_register32: Register::ESP, full_register: Register::RSP, size: 2 },
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    RegisterInfo { register: Register::BP, base: Register::AX, full_register32: Register::EBP, full_register: Register::RBP, size: 2 },
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    RegisterInfo { register: Register::SI, base: Register::AX, full_register32: Register::ESI, full_register: Register::RSI, size: 2 },
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    RegisterInfo { register: Register::DI, base: Register::AX, full_register32: Register::EDI, full_register: Register::RDI, size: 2 },
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    RegisterInfo { register: Register::R8W, base: Register::AX, full_register32: Register::R8D, full_register: Register::R8, size: 2 },
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    RegisterInfo { register: Register::R9W, base: Register::AX, full_register32: Register::R9D, full_register: Register::R9, size: 2 },
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    RegisterInfo { register: Register::R10W, base: Register::AX, full_register32: Register::R10D, full_register: Register::R10, size: 2 },
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    RegisterInfo { register: Register::R11W, base: Register::AX, full_register32: Register::R11D, full_register: Register::R11, size: 2 },
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    RegisterInfo { register: Register::R12W, base: Register::AX, full_register32: Register::R12D, full_register: Register::R12, size: 2 },
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    RegisterInfo { register: Register::R13W, base: Register::AX, full_register32: Register::R13D, full_register: Register::R13, size: 2 },
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    RegisterInfo { register: Register::R14W, base: Register::AX, full_register32: Register::R14D, full_register: Register::R14, size: 2 },
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    RegisterInfo { register: Register::R15W, base: Register::AX, full_register32: Register::R15D, full_register: Register::R15, size: 2 },
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    RegisterInfo { register: Register::EAX, base: Register::EAX, full_register32: Register::EAX, full_register: Register::RAX, size: 4 },
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    RegisterInfo { register: Register::ECX, base: Register::EAX, full_register32: Register::ECX, full_register: Register::RCX, size: 4 },
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    RegisterInfo { register: Register::EDX, base: Register::EAX, full_register32: Register::EDX, full_register: Register::RDX, size: 4 },
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    RegisterInfo { register: Register::EBX, base: Register::EAX, full_register32: Register::EBX, full_register: Register::RBX, size: 4 },
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    RegisterInfo { register: Register::ESP, base: Register::EAX, full_register32: Register::ESP, full_register: Register::RSP, size: 4 },
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    RegisterInfo { register: Register::EBP, base: Register::EAX, full_register32: Register::EBP, full_register: Register::RBP, size: 4 },
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    RegisterInfo { register: Register::ESI, base: Register::EAX, full_register32: Register::ESI, full_register: Register::RSI, size: 4 },
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    RegisterInfo { register: Register::EDI, base: Register::EAX, full_register32: Register::EDI, full_register: Register::RDI, size: 4 },
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    RegisterInfo { register: Register::R8D, base: Register::EAX, full_register32: Register::R8D, full_register: Register::R8, size: 4 },
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    RegisterInfo { register: Register::R9D, base: Register::EAX, full_register32: Register::R9D, full_register: Register::R9, size: 4 },
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    RegisterInfo { register: Register::R10D, base: Register::EAX, full_register32: Register::R10D, full_register: Register::R10, size: 4 },
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    RegisterInfo { register: Register::R11D, base: Register::EAX, full_register32: Register::R11D, full_register: Register::R11, size: 4 },
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    RegisterInfo { register: Register::R12D, base: Register::EAX, full_register32: Register::R12D, full_register: Register::R12, size: 4 },
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    RegisterInfo { register: Register::R13D, base: Register::EAX, full_register32: Register::R13D, full_register: Register::R13, size: 4 },
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    RegisterInfo { register: Register::R14D, base: Register::EAX, full_register32: Register::R14D, full_register: Register::R14, size: 4 },
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    RegisterInfo { register: Register::R15D, base: Register::EAX, full_register32: Register::R15D, full_register: Register::R15, size: 4 },
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    RegisterInfo { register: Register::RAX, base: Register::RAX, full_register32: Register::EAX, full_register: Register::RAX, size: 8 },
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    RegisterInfo { register: Register::RCX, base: Register::RAX, full_register32: Register::ECX, full_register: Register::RCX, size: 8 },
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    RegisterInfo { register: Register::RDX, base: Register::RAX, full_register32: Register::EDX, full_register: Register::RDX, size: 8 },
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    RegisterInfo { register: Register::RBX, base: Register::RAX, full_register32: Register::EBX, full_register: Register::RBX, size: 8 },
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    RegisterInfo { register: Register::RSP, base: Register::RAX, full_register32: Register::ESP, full_register: Register::RSP, size: 8 },
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    RegisterInfo { register: Register::RBP, base: Register::RAX, full_register32: Register::EBP, full_register: Register::RBP, size: 8 },
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    RegisterInfo { register: Register::RSI, base: Register::RAX, full_register32: Register::ESI, full_register: Register::RSI, size: 8 },
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    RegisterInfo { register: Register::RDI, base: Register::RAX, full_register32: Register::EDI, full_register: Register::RDI, size: 8 },
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    RegisterInfo { register: Register::R8, base: Register::RAX, full_register32: Register::R8D, full_register: Register::R8, size: 8 },
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    RegisterInfo { register: Register::R9, base: Register::RAX, full_register32: Register::R9D, full_register: Register::R9, size: 8 },
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    RegisterInfo { register: Register::R10, base: Register::RAX, full_register32: Register::R10D, full_register: Register::R10, size: 8 },
87
    RegisterInfo { register: Register::R11, base: Register::RAX, full_register32: Register::R11D, full_register: Register::R11, size: 8 },
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    RegisterInfo { register: Register::R12, base: Register::RAX, full_register32: Register::R12D, full_register: Register::R12, size: 8 },
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    RegisterInfo { register: Register::R13, base: Register::RAX, full_register32: Register::R13D, full_register: Register::R13, size: 8 },
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    RegisterInfo { register: Register::R14, base: Register::RAX, full_register32: Register::R14D, full_register: Register::R14, size: 8 },
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    RegisterInfo { register: Register::R15, base: Register::RAX, full_register32: Register::R15D, full_register: Register::R15, size: 8 },
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    RegisterInfo { register: Register::EIP, base: Register::EIP, full_register32: Register::RIP, full_register: Register::RIP, size: 4 },
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    RegisterInfo { register: Register::RIP, base: Register::EIP, full_register32: Register::RIP, full_register: Register::RIP, size: 8 },
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    RegisterInfo { register: Register::ES, base: Register::ES, full_register32: Register::ES, full_register: Register::ES, size: 2 },
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    RegisterInfo { register: Register::CS, base: Register::ES, full_register32: Register::CS, full_register: Register::CS, size: 2 },
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    RegisterInfo { register: Register::SS, base: Register::ES, full_register32: Register::SS, full_register: Register::SS, size: 2 },
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    RegisterInfo { register: Register::DS, base: Register::ES, full_register32: Register::DS, full_register: Register::DS, size: 2 },
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    RegisterInfo { register: Register::FS, base: Register::ES, full_register32: Register::FS, full_register: Register::FS, size: 2 },
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    RegisterInfo { register: Register::GS, base: Register::ES, full_register32: Register::GS, full_register: Register::GS, size: 2 },
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    RegisterInfo { register: Register::XMM0, base: Register::XMM0, full_register32: Register::ZMM0, full_register: Register::ZMM0, size: 16 },
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    RegisterInfo { register: Register::XMM1, base: Register::XMM0, full_register32: Register::ZMM1, full_register: Register::ZMM1, size: 16 },
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    RegisterInfo { register: Register::XMM2, base: Register::XMM0, full_register32: Register::ZMM2, full_register: Register::ZMM2, size: 16 },
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    RegisterInfo { register: Register::XMM3, base: Register::XMM0, full_register32: Register::ZMM3, full_register: Register::ZMM3, size: 16 },
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    RegisterInfo { register: Register::XMM4, base: Register::XMM0, full_register32: Register::ZMM4, full_register: Register::ZMM4, size: 16 },
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    RegisterInfo { register: Register::XMM5, base: Register::XMM0, full_register32: Register::ZMM5, full_register: Register::ZMM5, size: 16 },
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    RegisterInfo { register: Register::XMM6, base: Register::XMM0, full_register32: Register::ZMM6, full_register: Register::ZMM6, size: 16 },
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    RegisterInfo { register: Register::XMM7, base: Register::XMM0, full_register32: Register::ZMM7, full_register: Register::ZMM7, size: 16 },
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    RegisterInfo { register: Register::XMM8, base: Register::XMM0, full_register32: Register::ZMM8, full_register: Register::ZMM8, size: 16 },
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    RegisterInfo { register: Register::XMM9, base: Register::XMM0, full_register32: Register::ZMM9, full_register: Register::ZMM9, size: 16 },
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    RegisterInfo { register: Register::XMM10, base: Register::XMM0, full_register32: Register::ZMM10, full_register: Register::ZMM10, size: 16 },
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    RegisterInfo { register: Register::XMM11, base: Register::XMM0, full_register32: Register::ZMM11, full_register: Register::ZMM11, size: 16 },
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    RegisterInfo { register: Register::XMM12, base: Register::XMM0, full_register32: Register::ZMM12, full_register: Register::ZMM12, size: 16 },
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    RegisterInfo { register: Register::XMM13, base: Register::XMM0, full_register32: Register::ZMM13, full_register: Register::ZMM13, size: 16 },
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    RegisterInfo { register: Register::XMM14, base: Register::XMM0, full_register32: Register::ZMM14, full_register: Register::ZMM14, size: 16 },
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    RegisterInfo { register: Register::XMM15, base: Register::XMM0, full_register32: Register::ZMM15, full_register: Register::ZMM15, size: 16 },
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    RegisterInfo { register: Register::XMM16, base: Register::XMM0, full_register32: Register::ZMM16, full_register: Register::ZMM16, size: 16 },
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    RegisterInfo { register: Register::XMM17, base: Register::XMM0, full_register32: Register::ZMM17, full_register: Register::ZMM17, size: 16 },
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    RegisterInfo { register: Register::XMM18, base: Register::XMM0, full_register32: Register::ZMM18, full_register: Register::ZMM18, size: 16 },
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    RegisterInfo { register: Register::XMM19, base: Register::XMM0, full_register32: Register::ZMM19, full_register: Register::ZMM19, size: 16 },
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    RegisterInfo { register: Register::XMM20, base: Register::XMM0, full_register32: Register::ZMM20, full_register: Register::ZMM20, size: 16 },
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    RegisterInfo { register: Register::XMM21, base: Register::XMM0, full_register32: Register::ZMM21, full_register: Register::ZMM21, size: 16 },
122
    RegisterInfo { register: Register::XMM22, base: Register::XMM0, full_register32: Register::ZMM22, full_register: Register::ZMM22, size: 16 },
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    RegisterInfo { register: Register::XMM23, base: Register::XMM0, full_register32: Register::ZMM23, full_register: Register::ZMM23, size: 16 },
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    RegisterInfo { register: Register::XMM24, base: Register::XMM0, full_register32: Register::ZMM24, full_register: Register::ZMM24, size: 16 },
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    RegisterInfo { register: Register::XMM25, base: Register::XMM0, full_register32: Register::ZMM25, full_register: Register::ZMM25, size: 16 },
126
    RegisterInfo { register: Register::XMM26, base: Register::XMM0, full_register32: Register::ZMM26, full_register: Register::ZMM26, size: 16 },
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    RegisterInfo { register: Register::XMM27, base: Register::XMM0, full_register32: Register::ZMM27, full_register: Register::ZMM27, size: 16 },
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    RegisterInfo { register: Register::XMM28, base: Register::XMM0, full_register32: Register::ZMM28, full_register: Register::ZMM28, size: 16 },
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    RegisterInfo { register: Register::XMM29, base: Register::XMM0, full_register32: Register::ZMM29, full_register: Register::ZMM29, size: 16 },
130
    RegisterInfo { register: Register::XMM30, base: Register::XMM0, full_register32: Register::ZMM30, full_register: Register::ZMM30, size: 16 },
131
    RegisterInfo { register: Register::XMM31, base: Register::XMM0, full_register32: Register::ZMM31, full_register: Register::ZMM31, size: 16 },
132
    RegisterInfo { register: Register::YMM0, base: Register::YMM0, full_register32: Register::ZMM0, full_register: Register::ZMM0, size: 32 },
133
    RegisterInfo { register: Register::YMM1, base: Register::YMM0, full_register32: Register::ZMM1, full_register: Register::ZMM1, size: 32 },
134
    RegisterInfo { register: Register::YMM2, base: Register::YMM0, full_register32: Register::ZMM2, full_register: Register::ZMM2, size: 32 },
135
    RegisterInfo { register: Register::YMM3, base: Register::YMM0, full_register32: Register::ZMM3, full_register: Register::ZMM3, size: 32 },
136
    RegisterInfo { register: Register::YMM4, base: Register::YMM0, full_register32: Register::ZMM4, full_register: Register::ZMM4, size: 32 },
137
    RegisterInfo { register: Register::YMM5, base: Register::YMM0, full_register32: Register::ZMM5, full_register: Register::ZMM5, size: 32 },
138
    RegisterInfo { register: Register::YMM6, base: Register::YMM0, full_register32: Register::ZMM6, full_register: Register::ZMM6, size: 32 },
139
    RegisterInfo { register: Register::YMM7, base: Register::YMM0, full_register32: Register::ZMM7, full_register: Register::ZMM7, size: 32 },
140
    RegisterInfo { register: Register::YMM8, base: Register::YMM0, full_register32: Register::ZMM8, full_register: Register::ZMM8, size: 32 },
141
    RegisterInfo { register: Register::YMM9, base: Register::YMM0, full_register32: Register::ZMM9, full_register: Register::ZMM9, size: 32 },
142
    RegisterInfo { register: Register::YMM10, base: Register::YMM0, full_register32: Register::ZMM10, full_register: Register::ZMM10, size: 32 },
143
    RegisterInfo { register: Register::YMM11, base: Register::YMM0, full_register32: Register::ZMM11, full_register: Register::ZMM11, size: 32 },
144
    RegisterInfo { register: Register::YMM12, base: Register::YMM0, full_register32: Register::ZMM12, full_register: Register::ZMM12, size: 32 },
145
    RegisterInfo { register: Register::YMM13, base: Register::YMM0, full_register32: Register::ZMM13, full_register: Register::ZMM13, size: 32 },
146
    RegisterInfo { register: Register::YMM14, base: Register::YMM0, full_register32: Register::ZMM14, full_register: Register::ZMM14, size: 32 },
147
    RegisterInfo { register: Register::YMM15, base: Register::YMM0, full_register32: Register::ZMM15, full_register: Register::ZMM15, size: 32 },
148
    RegisterInfo { register: Register::YMM16, base: Register::YMM0, full_register32: Register::ZMM16, full_register: Register::ZMM16, size: 32 },
149
    RegisterInfo { register: Register::YMM17, base: Register::YMM0, full_register32: Register::ZMM17, full_register: Register::ZMM17, size: 32 },
150
    RegisterInfo { register: Register::YMM18, base: Register::YMM0, full_register32: Register::ZMM18, full_register: Register::ZMM18, size: 32 },
151
    RegisterInfo { register: Register::YMM19, base: Register::YMM0, full_register32: Register::ZMM19, full_register: Register::ZMM19, size: 32 },
152
    RegisterInfo { register: Register::YMM20, base: Register::YMM0, full_register32: Register::ZMM20, full_register: Register::ZMM20, size: 32 },
153
    RegisterInfo { register: Register::YMM21, base: Register::YMM0, full_register32: Register::ZMM21, full_register: Register::ZMM21, size: 32 },
154
    RegisterInfo { register: Register::YMM22, base: Register::YMM0, full_register32: Register::ZMM22, full_register: Register::ZMM22, size: 32 },
155
    RegisterInfo { register: Register::YMM23, base: Register::YMM0, full_register32: Register::ZMM23, full_register: Register::ZMM23, size: 32 },
156
    RegisterInfo { register: Register::YMM24, base: Register::YMM0, full_register32: Register::ZMM24, full_register: Register::ZMM24, size: 32 },
157
    RegisterInfo { register: Register::YMM25, base: Register::YMM0, full_register32: Register::ZMM25, full_register: Register::ZMM25, size: 32 },
158
    RegisterInfo { register: Register::YMM26, base: Register::YMM0, full_register32: Register::ZMM26, full_register: Register::ZMM26, size: 32 },
159
    RegisterInfo { register: Register::YMM27, base: Register::YMM0, full_register32: Register::ZMM27, full_register: Register::ZMM27, size: 32 },
160
    RegisterInfo { register: Register::YMM28, base: Register::YMM0, full_register32: Register::ZMM28, full_register: Register::ZMM28, size: 32 },
161
    RegisterInfo { register: Register::YMM29, base: Register::YMM0, full_register32: Register::ZMM29, full_register: Register::ZMM29, size: 32 },
162
    RegisterInfo { register: Register::YMM30, base: Register::YMM0, full_register32: Register::ZMM30, full_register: Register::ZMM30, size: 32 },
163
    RegisterInfo { register: Register::YMM31, base: Register::YMM0, full_register32: Register::ZMM31, full_register: Register::ZMM31, size: 32 },
164
    RegisterInfo { register: Register::ZMM0, base: Register::ZMM0, full_register32: Register::ZMM0, full_register: Register::ZMM0, size: 64 },
165
    RegisterInfo { register: Register::ZMM1, base: Register::ZMM0, full_register32: Register::ZMM1, full_register: Register::ZMM1, size: 64 },
166
    RegisterInfo { register: Register::ZMM2, base: Register::ZMM0, full_register32: Register::ZMM2, full_register: Register::ZMM2, size: 64 },
167
    RegisterInfo { register: Register::ZMM3, base: Register::ZMM0, full_register32: Register::ZMM3, full_register: Register::ZMM3, size: 64 },
168
    RegisterInfo { register: Register::ZMM4, base: Register::ZMM0, full_register32: Register::ZMM4, full_register: Register::ZMM4, size: 64 },
169
    RegisterInfo { register: Register::ZMM5, base: Register::ZMM0, full_register32: Register::ZMM5, full_register: Register::ZMM5, size: 64 },
170
    RegisterInfo { register: Register::ZMM6, base: Register::ZMM0, full_register32: Register::ZMM6, full_register: Register::ZMM6, size: 64 },
171
    RegisterInfo { register: Register::ZMM7, base: Register::ZMM0, full_register32: Register::ZMM7, full_register: Register::ZMM7, size: 64 },
172
    RegisterInfo { register: Register::ZMM8, base: Register::ZMM0, full_register32: Register::ZMM8, full_register: Register::ZMM8, size: 64 },
173
    RegisterInfo { register: Register::ZMM9, base: Register::ZMM0, full_register32: Register::ZMM9, full_register: Register::ZMM9, size: 64 },
174
    RegisterInfo { register: Register::ZMM10, base: Register::ZMM0, full_register32: Register::ZMM10, full_register: Register::ZMM10, size: 64 },
175
    RegisterInfo { register: Register::ZMM11, base: Register::ZMM0, full_register32: Register::ZMM11, full_register: Register::ZMM11, size: 64 },
176
    RegisterInfo { register: Register::ZMM12, base: Register::ZMM0, full_register32: Register::ZMM12, full_register: Register::ZMM12, size: 64 },
177
    RegisterInfo { register: Register::ZMM13, base: Register::ZMM0, full_register32: Register::ZMM13, full_register: Register::ZMM13, size: 64 },
178
    RegisterInfo { register: Register::ZMM14, base: Register::ZMM0, full_register32: Register::ZMM14, full_register: Register::ZMM14, size: 64 },
179
    RegisterInfo { register: Register::ZMM15, base: Register::ZMM0, full_register32: Register::ZMM15, full_register: Register::ZMM15, size: 64 },
180
    RegisterInfo { register: Register::ZMM16, base: Register::ZMM0, full_register32: Register::ZMM16, full_register: Register::ZMM16, size: 64 },
181
    RegisterInfo { register: Register::ZMM17, base: Register::ZMM0, full_register32: Register::ZMM17, full_register: Register::ZMM17, size: 64 },
182
    RegisterInfo { register: Register::ZMM18, base: Register::ZMM0, full_register32: Register::ZMM18, full_register: Register::ZMM18, size: 64 },
183
    RegisterInfo { register: Register::ZMM19, base: Register::ZMM0, full_register32: Register::ZMM19, full_register: Register::ZMM19, size: 64 },
184
    RegisterInfo { register: Register::ZMM20, base: Register::ZMM0, full_register32: Register::ZMM20, full_register: Register::ZMM20, size: 64 },
185
    RegisterInfo { register: Register::ZMM21, base: Register::ZMM0, full_register32: Register::ZMM21, full_register: Register::ZMM21, size: 64 },
186
    RegisterInfo { register: Register::ZMM22, base: Register::ZMM0, full_register32: Register::ZMM22, full_register: Register::ZMM22, size: 64 },
187
    RegisterInfo { register: Register::ZMM23, base: Register::ZMM0, full_register32: Register::ZMM23, full_register: Register::ZMM23, size: 64 },
188
    RegisterInfo { register: Register::ZMM24, base: Register::ZMM0, full_register32: Register::ZMM24, full_register: Register::ZMM24, size: 64 },
189
    RegisterInfo { register: Register::ZMM25, base: Register::ZMM0, full_register32: Register::ZMM25, full_register: Register::ZMM25, size: 64 },
190
    RegisterInfo { register: Register::ZMM26, base: Register::ZMM0, full_register32: Register::ZMM26, full_register: Register::ZMM26, size: 64 },
191
    RegisterInfo { register: Register::ZMM27, base: Register::ZMM0, full_register32: Register::ZMM27, full_register: Register::ZMM27, size: 64 },
192
    RegisterInfo { register: Register::ZMM28, base: Register::ZMM0, full_register32: Register::ZMM28, full_register: Register::ZMM28, size: 64 },
193
    RegisterInfo { register: Register::ZMM29, base: Register::ZMM0, full_register32: Register::ZMM29, full_register: Register::ZMM29, size: 64 },
194
    RegisterInfo { register: Register::ZMM30, base: Register::ZMM0, full_register32: Register::ZMM30, full_register: Register::ZMM30, size: 64 },
195
    RegisterInfo { register: Register::ZMM31, base: Register::ZMM0, full_register32: Register::ZMM31, full_register: Register::ZMM31, size: 64 },
196
    RegisterInfo { register: Register::K0, base: Register::K0, full_register32: Register::K0, full_register: Register::K0, size: 8 },
197
    RegisterInfo { register: Register::K1, base: Register::K0, full_register32: Register::K1, full_register: Register::K1, size: 8 },
198
    RegisterInfo { register: Register::K2, base: Register::K0, full_register32: Register::K2, full_register: Register::K2, size: 8 },
199
    RegisterInfo { register: Register::K3, base: Register::K0, full_register32: Register::K3, full_register: Register::K3, size: 8 },
200
    RegisterInfo { register: Register::K4, base: Register::K0, full_register32: Register::K4, full_register: Register::K4, size: 8 },
201
    RegisterInfo { register: Register::K5, base: Register::K0, full_register32: Register::K5, full_register: Register::K5, size: 8 },
202
    RegisterInfo { register: Register::K6, base: Register::K0, full_register32: Register::K6, full_register: Register::K6, size: 8 },
203
    RegisterInfo { register: Register::K7, base: Register::K0, full_register32: Register::K7, full_register: Register::K7, size: 8 },
204
    RegisterInfo { register: Register::BND0, base: Register::BND0, full_register32: Register::BND0, full_register: Register::BND0, size: 16 },
205
    RegisterInfo { register: Register::BND1, base: Register::BND0, full_register32: Register::BND1, full_register: Register::BND1, size: 16 },
206
    RegisterInfo { register: Register::BND2, base: Register::BND0, full_register32: Register::BND2, full_register: Register::BND2, size: 16 },
207
    RegisterInfo { register: Register::BND3, base: Register::BND0, full_register32: Register::BND3, full_register: Register::BND3, size: 16 },
208
    RegisterInfo { register: Register::CR0, base: Register::CR0, full_register32: Register::CR0, full_register: Register::CR0, size: 8 },
209
    RegisterInfo { register: Register::CR1, base: Register::CR0, full_register32: Register::CR1, full_register: Register::CR1, size: 8 },
210
    RegisterInfo { register: Register::CR2, base: Register::CR0, full_register32: Register::CR2, full_register: Register::CR2, size: 8 },
211
    RegisterInfo { register: Register::CR3, base: Register::CR0, full_register32: Register::CR3, full_register: Register::CR3, size: 8 },
212
    RegisterInfo { register: Register::CR4, base: Register::CR0, full_register32: Register::CR4, full_register: Register::CR4, size: 8 },
213
    RegisterInfo { register: Register::CR5, base: Register::CR0, full_register32: Register::CR5, full_register: Register::CR5, size: 8 },
214
    RegisterInfo { register: Register::CR6, base: Register::CR0, full_register32: Register::CR6, full_register: Register::CR6, size: 8 },
215
    RegisterInfo { register: Register::CR7, base: Register::CR0, full_register32: Register::CR7, full_register: Register::CR7, size: 8 },
216
    RegisterInfo { register: Register::CR8, base: Register::CR0, full_register32: Register::CR8, full_register: Register::CR8, size: 8 },
217
    RegisterInfo { register: Register::CR9, base: Register::CR0, full_register32: Register::CR9, full_register: Register::CR9, size: 8 },
218
    RegisterInfo { register: Register::CR10, base: Register::CR0, full_register32: Register::CR10, full_register: Register::CR10, size: 8 },
219
    RegisterInfo { register: Register::CR11, base: Register::CR0, full_register32: Register::CR11, full_register: Register::CR11, size: 8 },
220
    RegisterInfo { register: Register::CR12, base: Register::CR0, full_register32: Register::CR12, full_register: Register::CR12, size: 8 },
221
    RegisterInfo { register: Register::CR13, base: Register::CR0, full_register32: Register::CR13, full_register: Register::CR13, size: 8 },
222
    RegisterInfo { register: Register::CR14, base: Register::CR0, full_register32: Register::CR14, full_register: Register::CR14, size: 8 },
223
    RegisterInfo { register: Register::CR15, base: Register::CR0, full_register32: Register::CR15, full_register: Register::CR15, size: 8 },
224
    RegisterInfo { register: Register::DR0, base: Register::DR0, full_register32: Register::DR0, full_register: Register::DR0, size: 8 },
225
    RegisterInfo { register: Register::DR1, base: Register::DR0, full_register32: Register::DR1, full_register: Register::DR1, size: 8 },
226
    RegisterInfo { register: Register::DR2, base: Register::DR0, full_register32: Register::DR2, full_register: Register::DR2, size: 8 },
227
    RegisterInfo { register: Register::DR3, base: Register::DR0, full_register32: Register::DR3, full_register: Register::DR3, size: 8 },
228
    RegisterInfo { register: Register::DR4, base: Register::DR0, full_register32: Register::DR4, full_register: Register::DR4, size: 8 },
229
    RegisterInfo { register: Register::DR5, base: Register::DR0, full_register32: Register::DR5, full_register: Register::DR5, size: 8 },
230
    RegisterInfo { register: Register::DR6, base: Register::DR0, full_register32: Register::DR6, full_register: Register::DR6, size: 8 },
231
    RegisterInfo { register: Register::DR7, base: Register::DR0, full_register32: Register::DR7, full_register: Register::DR7, size: 8 },
232
    RegisterInfo { register: Register::DR8, base: Register::DR0, full_register32: Register::DR8, full_register: Register::DR8, size: 8 },
233
    RegisterInfo { register: Register::DR9, base: Register::DR0, full_register32: Register::DR9, full_register: Register::DR9, size: 8 },
234
    RegisterInfo { register: Register::DR10, base: Register::DR0, full_register32: Register::DR10, full_register: Register::DR10, size: 8 },
235
    RegisterInfo { register: Register::DR11, base: Register::DR0, full_register32: Register::DR11, full_register: Register::DR11, size: 8 },
236
    RegisterInfo { register: Register::DR12, base: Register::DR0, full_register32: Register::DR12, full_register: Register::DR12, size: 8 },
237
    RegisterInfo { register: Register::DR13, base: Register::DR0, full_register32: Register::DR13, full_register: Register::DR13, size: 8 },
238
    RegisterInfo { register: Register::DR14, base: Register::DR0, full_register32: Register::DR14, full_register: Register::DR14, size: 8 },
239
    RegisterInfo { register: Register::DR15, base: Register::DR0, full_register32: Register::DR15, full_register: Register::DR15, size: 8 },
240
    RegisterInfo { register: Register::ST0, base: Register::ST0, full_register32: Register::ST0, full_register: Register::ST0, size: 10 },
241
    RegisterInfo { register: Register::ST1, base: Register::ST0, full_register32: Register::ST1, full_register: Register::ST1, size: 10 },
242
    RegisterInfo { register: Register::ST2, base: Register::ST0, full_register32: Register::ST2, full_register: Register::ST2, size: 10 },
243
    RegisterInfo { register: Register::ST3, base: Register::ST0, full_register32: Register::ST3, full_register: Register::ST3, size: 10 },
244
    RegisterInfo { register: Register::ST4, base: Register::ST0, full_register32: Register::ST4, full_register: Register::ST4, size: 10 },
245
    RegisterInfo { register: Register::ST5, base: Register::ST0, full_register32: Register::ST5, full_register: Register::ST5, size: 10 },
246
    RegisterInfo { register: Register::ST6, base: Register::ST0, full_register32: Register::ST6, full_register: Register::ST6, size: 10 },
247
    RegisterInfo { register: Register::ST7, base: Register::ST0, full_register32: Register::ST7, full_register: Register::ST7, size: 10 },
248
    RegisterInfo { register: Register::MM0, base: Register::MM0, full_register32: Register::MM0, full_register: Register::MM0, size: 8 },
249
    RegisterInfo { register: Register::MM1, base: Register::MM0, full_register32: Register::MM1, full_register: Register::MM1, size: 8 },
250
    RegisterInfo { register: Register::MM2, base: Register::MM0, full_register32: Register::MM2, full_register: Register::MM2, size: 8 },
251
    RegisterInfo { register: Register::MM3, base: Register::MM0, full_register32: Register::MM3, full_register: Register::MM3, size: 8 },
252
    RegisterInfo { register: Register::MM4, base: Register::MM0, full_register32: Register::MM4, full_register: Register::MM4, size: 8 },
253
    RegisterInfo { register: Register::MM5, base: Register::MM0, full_register32: Register::MM5, full_register: Register::MM5, size: 8 },
254
    RegisterInfo { register: Register::MM6, base: Register::MM0, full_register32: Register::MM6, full_register: Register::MM6, size: 8 },
255
    RegisterInfo { register: Register::MM7, base: Register::MM0, full_register32: Register::MM7, full_register: Register::MM7, size: 8 },
256
    RegisterInfo { register: Register::TR0, base: Register::TR0, full_register32: Register::TR0, full_register: Register::TR0, size: 4 },
257
    RegisterInfo { register: Register::TR1, base: Register::TR0, full_register32: Register::TR1, full_register: Register::TR1, size: 4 },
258
    RegisterInfo { register: Register::TR2, base: Register::TR0, full_register32: Register::TR2, full_register: Register::TR2, size: 4 },
259
    RegisterInfo { register: Register::TR3, base: Register::TR0, full_register32: Register::TR3, full_register: Register::TR3, size: 4 },
260
    RegisterInfo { register: Register::TR4, base: Register::TR0, full_register32: Register::TR4, full_register: Register::TR4, size: 4 },
261
    RegisterInfo { register: Register::TR5, base: Register::TR0, full_register32: Register::TR5, full_register: Register::TR5, size: 4 },
262
    RegisterInfo { register: Register::TR6, base: Register::TR0, full_register32: Register::TR6, full_register: Register::TR6, size: 4 },
263
    RegisterInfo { register: Register::TR7, base: Register::TR0, full_register32: Register::TR7, full_register: Register::TR7, size: 4 },
264
    RegisterInfo { register: Register::TMM0, base: Register::TMM0, full_register32: Register::TMM0, full_register: Register::TMM0, size: 1024 },
265
    RegisterInfo { register: Register::TMM1, base: Register::TMM0, full_register32: Register::TMM1, full_register: Register::TMM1, size: 1024 },
266
    RegisterInfo { register: Register::TMM2, base: Register::TMM0, full_register32: Register::TMM2, full_register: Register::TMM2, size: 1024 },
267
    RegisterInfo { register: Register::TMM3, base: Register::TMM0, full_register32: Register::TMM3, full_register: Register::TMM3, size: 1024 },
268
    RegisterInfo { register: Register::TMM4, base: Register::TMM0, full_register32: Register::TMM4, full_register: Register::TMM4, size: 1024 },
269
    RegisterInfo { register: Register::TMM5, base: Register::TMM0, full_register32: Register::TMM5, full_register: Register::TMM5, size: 1024 },
270
    RegisterInfo { register: Register::TMM6, base: Register::TMM0, full_register32: Register::TMM6, full_register: Register::TMM6, size: 1024 },
271
    RegisterInfo { register: Register::TMM7, base: Register::TMM0, full_register32: Register::TMM7, full_register: Register::TMM7, size: 1024 },
272
    RegisterInfo { register: Register::DontUse0, base: Register::DontUse0, full_register32: Register::DontUse0, full_register: Register::DontUse0, size: 0 },
273
    RegisterInfo { register: Register::DontUseFA, base: Register::DontUseFA, full_register32: Register::DontUseFA, full_register: Register::DontUseFA, size: 0 },
274
    RegisterInfo { register: Register::DontUseFB, base: Register::DontUseFA, full_register32: Register::DontUseFB, full_register: Register::DontUseFB, size: 0 },
275
    RegisterInfo { register: Register::DontUseFC, base: Register::DontUseFA, full_register32: Register::DontUseFC, full_register: Register::DontUseFC, size: 0 },
276
    RegisterInfo { register: Register::DontUseFD, base: Register::DontUseFA, full_register32: Register::DontUseFD, full_register: Register::DontUseFD, size: 0 },
277
    RegisterInfo { register: Register::DontUseFE, base: Register::DontUseFA, full_register32: Register::DontUseFE, full_register: Register::DontUseFE, size: 0 },
278
    RegisterInfo { register: Register::DontUseFF, base: Register::DontUseFA, full_register32: Register::DontUseFF, full_register: Register::DontUseFF, size: 0 },
279
    // GENERATOR-END: RegisterInfoTable
280
  ];
281
282
  /// [`Register`] information
283
  ///
284
  /// [`Register`]: enum.Register.html
285
  #[derive(Debug, Copy, Clone, Eq, PartialEq, Hash)]
286
  pub struct RegisterInfo {
287
    register: Register,
288
    base: Register,
289
    full_register: Register,
290
    full_register32: Register,
291
    size: u16,
292
  }
293
294
  impl RegisterInfo {
295
    /// Gets the register
296
    ///
297
    /// # Examples
298
    ///
299
    /// ```
300
    /// use iced_x86::*;
301
    /// let info = Register::EAX.info();
302
    /// assert_eq!(info.register(), Register::EAX);
303
    /// ```
304
    #[must_use]
305
    #[inline]
306
0
    pub const fn register(&self) -> Register {
307
0
      self.register
308
0
    }
309
310
    /// Gets the base register, eg. `AL`, `AX`, `EAX`, `RAX`, `MM0`, `XMM0`, `YMM0`, `ZMM0`, `ES`
311
    ///
312
    /// # Examples
313
    ///
314
    /// ```
315
    /// use iced_x86::*;
316
    /// let info = Register::GS.info();
317
    /// assert_eq!(info.base(), Register::ES);
318
    /// let info = Register::RDX.info();
319
    /// assert_eq!(info.base(), Register::RAX);
320
    /// let info = Register::XMM13.info();
321
    /// assert_eq!(info.base(), Register::XMM0);
322
    /// let info = Register::YMM13.info();
323
    /// assert_eq!(info.base(), Register::YMM0);
324
    /// let info = Register::ZMM13.info();
325
    /// assert_eq!(info.base(), Register::ZMM0);
326
    /// ```
327
    #[must_use]
328
    #[inline]
329
0
    pub const fn base(&self) -> Register {
330
0
      self.base
331
0
    }
332
333
    /// The register number (index) relative to [`base()`], eg. 0-15, or 0-31, or if 8-bit GPR, 0-19
334
    ///
335
    /// [`base()`]: #method.base
336
    ///
337
    /// # Examples
338
    ///
339
    /// ```
340
    /// use iced_x86::*;
341
    /// let info = Register::GS.info();
342
    /// assert_eq!(info.number(), 5);
343
    /// let info = Register::RDX.info();
344
    /// assert_eq!(info.number(), 2);
345
    /// let info = Register::XMM13.info();
346
    /// assert_eq!(info.number(), 13);
347
    /// let info = Register::YMM13.info();
348
    /// assert_eq!(info.number(), 13);
349
    /// let info = Register::ZMM13.info();
350
    /// assert_eq!(info.number(), 13);
351
    /// ```
352
    #[must_use]
353
    #[inline]
354
0
    pub const fn number(&self) -> usize {
355
0
      self.register as usize - self.base as usize
356
0
    }
357
358
    /// The full register that this one is a part of, eg. `CL`/`CH`/`CX`/`ECX`/`RCX` -> `RCX`, `XMM11`/`YMM11`/`ZMM11` -> `ZMM11`
359
    ///
360
    /// # Examples
361
    ///
362
    /// ```
363
    /// use iced_x86::*;
364
    /// let info = Register::GS.info();
365
    /// assert_eq!(info.full_register(), Register::GS);
366
    /// let info = Register::BH.info();
367
    /// assert_eq!(info.full_register(), Register::RBX);
368
    /// let info = Register::DX.info();
369
    /// assert_eq!(info.full_register(), Register::RDX);
370
    /// let info = Register::ESP.info();
371
    /// assert_eq!(info.full_register(), Register::RSP);
372
    /// let info = Register::RCX.info();
373
    /// assert_eq!(info.full_register(), Register::RCX);
374
    /// let info = Register::XMM3.info();
375
    /// assert_eq!(info.full_register(), Register::ZMM3);
376
    /// let info = Register::YMM3.info();
377
    /// assert_eq!(info.full_register(), Register::ZMM3);
378
    /// let info = Register::ZMM3.info();
379
    /// assert_eq!(info.full_register(), Register::ZMM3);
380
    /// ```
381
    #[must_use]
382
    #[inline]
383
0
    pub const fn full_register(&self) -> Register {
384
0
      self.full_register
385
0
    }
386
387
    /// Gets the full register that this one is a part of, except if it's a GPR in which case the 32-bit register is returned,
388
    /// eg. `CL`/`CH`/`CX`/`ECX`/`RCX` -> `ECX`, `XMM11`/`YMM11`/`ZMM11` -> `ZMM11`
389
    ///
390
    /// # Examples
391
    ///
392
    /// ```
393
    /// use iced_x86::*;
394
    /// let info = Register::GS.info();
395
    /// assert_eq!(info.full_register32(), Register::GS);
396
    /// let info = Register::BH.info();
397
    /// assert_eq!(info.full_register32(), Register::EBX);
398
    /// let info = Register::DX.info();
399
    /// assert_eq!(info.full_register32(), Register::EDX);
400
    /// let info = Register::ESP.info();
401
    /// assert_eq!(info.full_register32(), Register::ESP);
402
    /// let info = Register::RCX.info();
403
    /// assert_eq!(info.full_register32(), Register::ECX);
404
    /// let info = Register::XMM3.info();
405
    /// assert_eq!(info.full_register32(), Register::ZMM3);
406
    /// let info = Register::YMM3.info();
407
    /// assert_eq!(info.full_register32(), Register::ZMM3);
408
    /// let info = Register::ZMM3.info();
409
    /// assert_eq!(info.full_register32(), Register::ZMM3);
410
    /// ```
411
    #[must_use]
412
    #[inline]
413
0
    pub const fn full_register32(&self) -> Register {
414
0
      self.full_register32
415
0
    }
416
417
    /// Size of the register in bytes
418
    ///
419
    /// # Examples
420
    ///
421
    /// ```
422
    /// use iced_x86::*;
423
    /// let info = Register::GS.info();
424
    /// assert_eq!(info.size(), 2);
425
    /// let info = Register::BH.info();
426
    /// assert_eq!(info.size(), 1);
427
    /// let info = Register::DX.info();
428
    /// assert_eq!(info.size(), 2);
429
    /// let info = Register::ESP.info();
430
    /// assert_eq!(info.size(), 4);
431
    /// let info = Register::RCX.info();
432
    /// assert_eq!(info.size(), 8);
433
    /// let info = Register::XMM3.info();
434
    /// assert_eq!(info.size(), 16);
435
    /// let info = Register::YMM3.info();
436
    /// assert_eq!(info.size(), 32);
437
    /// let info = Register::ZMM3.info();
438
    /// assert_eq!(info.size(), 64);
439
    /// ```
440
    #[must_use]
441
    #[inline]
442
0
    pub const fn size(&self) -> usize {
443
0
      self.size as usize
444
0
    }
445
  }
446
}
447
448
#[cfg(feature = "instr_info")]
449
impl Register {
450
  /// Gets register info
451
  ///
452
  /// # Examples
453
  ///
454
  /// ```
455
  /// use iced_x86::*;
456
  /// let info = Register::EAX.info();
457
  /// assert_eq!(info.size(), 4);
458
  /// ```
459
  #[must_use]
460
  #[inline]
461
0
  pub fn info(self) -> &'static RegisterInfo {
462
0
    &REGISTER_INFOS[self as usize]
463
0
  }
464
465
  /// Gets the base register, eg. `AL`, `AX`, `EAX`, `RAX`, `MM0`, `XMM0`, `YMM0`, `ZMM0`, `ES`
466
  ///
467
  /// # Examples
468
  ///
469
  /// ```
470
  /// use iced_x86::*;
471
  /// assert_eq!(Register::GS.base(), Register::ES);
472
  /// assert_eq!(Register::SIL.base(), Register::AL);
473
  /// assert_eq!(Register::SP.base(), Register::AX);
474
  /// assert_eq!(Register::R13D.base(), Register::EAX);
475
  /// assert_eq!(Register::RBP.base(), Register::RAX);
476
  /// assert_eq!(Register::MM6.base(), Register::MM0);
477
  /// assert_eq!(Register::XMM28.base(), Register::XMM0);
478
  /// assert_eq!(Register::YMM12.base(), Register::YMM0);
479
  /// assert_eq!(Register::ZMM31.base(), Register::ZMM0);
480
  /// assert_eq!(Register::K3.base(), Register::K0);
481
  /// assert_eq!(Register::BND1.base(), Register::BND0);
482
  /// assert_eq!(Register::ST7.base(), Register::ST0);
483
  /// assert_eq!(Register::CR8.base(), Register::CR0);
484
  /// assert_eq!(Register::DR6.base(), Register::DR0);
485
  /// assert_eq!(Register::TR3.base(), Register::TR0);
486
  /// assert_eq!(Register::RIP.base(), Register::EIP);
487
  /// ```
488
  #[must_use]
489
  #[inline]
490
0
  pub fn base(self) -> Self {
491
0
    self.info().base()
492
0
  }
493
494
  /// The register number (index) relative to [`base()`], eg. 0-15, or 0-31, or if 8-bit GPR, 0-19
495
  ///
496
  /// [`base()`]: #method.base
497
  ///
498
  /// # Examples
499
  ///
500
  /// ```
501
  /// use iced_x86::*;
502
  /// assert_eq!(Register::GS.number(), 5);
503
  /// assert_eq!(Register::SIL.number(), 10);
504
  /// assert_eq!(Register::SP.number(), 4);
505
  /// assert_eq!(Register::R13D.number(), 13);
506
  /// assert_eq!(Register::RBP.number(), 5);
507
  /// assert_eq!(Register::MM6.number(), 6);
508
  /// assert_eq!(Register::XMM28.number(), 28);
509
  /// assert_eq!(Register::YMM12.number(), 12);
510
  /// assert_eq!(Register::ZMM31.number(), 31);
511
  /// assert_eq!(Register::K3.number(), 3);
512
  /// assert_eq!(Register::BND1.number(), 1);
513
  /// assert_eq!(Register::ST7.number(), 7);
514
  /// assert_eq!(Register::CR8.number(), 8);
515
  /// assert_eq!(Register::DR6.number(), 6);
516
  /// assert_eq!(Register::TR3.number(), 3);
517
  /// assert_eq!(Register::RIP.number(), 1);
518
  /// ```
519
  #[must_use]
520
  #[inline]
521
0
  pub fn number(self) -> usize {
522
0
    self.info().number()
523
0
  }
524
525
  /// Gets the full register that this one is a part of, eg. `CL`/`CH`/`CX`/`ECX`/`RCX` -> `RCX`, `XMM11`/`YMM11`/`ZMM11` -> `ZMM11`
526
  ///
527
  /// # Examples
528
  ///
529
  /// ```
530
  /// use iced_x86::*;
531
  /// assert_eq!(Register::GS.full_register(), Register::GS);
532
  /// assert_eq!(Register::SIL.full_register(), Register::RSI);
533
  /// assert_eq!(Register::SP.full_register(), Register::RSP);
534
  /// assert_eq!(Register::R13D.full_register(), Register::R13);
535
  /// assert_eq!(Register::RBP.full_register(), Register::RBP);
536
  /// assert_eq!(Register::MM6.full_register(), Register::MM6);
537
  /// assert_eq!(Register::XMM10.full_register(), Register::ZMM10);
538
  /// assert_eq!(Register::YMM10.full_register(), Register::ZMM10);
539
  /// assert_eq!(Register::ZMM10.full_register(), Register::ZMM10);
540
  /// assert_eq!(Register::K3.full_register(), Register::K3);
541
  /// assert_eq!(Register::BND1.full_register(), Register::BND1);
542
  /// assert_eq!(Register::ST7.full_register(), Register::ST7);
543
  /// assert_eq!(Register::CR8.full_register(), Register::CR8);
544
  /// assert_eq!(Register::DR6.full_register(), Register::DR6);
545
  /// assert_eq!(Register::TR3.full_register(), Register::TR3);
546
  /// assert_eq!(Register::RIP.full_register(), Register::RIP);
547
  /// ```
548
  #[must_use]
549
  #[inline]
550
0
  pub fn full_register(self) -> Self {
551
0
    self.info().full_register()
552
0
  }
553
554
  /// Gets the full register that this one is a part of, except if it's a GPR in which case the 32-bit register is returned,
555
  /// eg. `CL`/`CH`/`CX`/`ECX`/`RCX` -> `ECX`, `XMM11`/`YMM11`/`ZMM11` -> `ZMM11`
556
  ///
557
  /// # Examples
558
  ///
559
  /// ```
560
  /// use iced_x86::*;
561
  /// assert_eq!(Register::GS.full_register32(), Register::GS);
562
  /// assert_eq!(Register::SIL.full_register32(), Register::ESI);
563
  /// assert_eq!(Register::SP.full_register32(), Register::ESP);
564
  /// assert_eq!(Register::R13D.full_register32(), Register::R13D);
565
  /// assert_eq!(Register::RBP.full_register32(), Register::EBP);
566
  /// assert_eq!(Register::MM6.full_register32(), Register::MM6);
567
  /// assert_eq!(Register::XMM10.full_register32(), Register::ZMM10);
568
  /// assert_eq!(Register::YMM10.full_register32(), Register::ZMM10);
569
  /// assert_eq!(Register::ZMM10.full_register32(), Register::ZMM10);
570
  /// assert_eq!(Register::K3.full_register32(), Register::K3);
571
  /// assert_eq!(Register::BND1.full_register32(), Register::BND1);
572
  /// assert_eq!(Register::ST7.full_register32(), Register::ST7);
573
  /// assert_eq!(Register::CR8.full_register32(), Register::CR8);
574
  /// assert_eq!(Register::DR6.full_register32(), Register::DR6);
575
  /// assert_eq!(Register::TR3.full_register32(), Register::TR3);
576
  /// assert_eq!(Register::RIP.full_register32(), Register::RIP);
577
  /// ```
578
  #[must_use]
579
  #[inline]
580
0
  pub fn full_register32(self) -> Self {
581
0
    self.info().full_register32()
582
0
  }
583
584
  /// Gets the size of the register in bytes
585
  ///
586
  /// # Examples
587
  ///
588
  /// ```
589
  /// use iced_x86::*;
590
  /// assert_eq!(Register::GS.size(), 2);
591
  /// assert_eq!(Register::SIL.size(), 1);
592
  /// assert_eq!(Register::SP.size(), 2);
593
  /// assert_eq!(Register::R13D.size(), 4);
594
  /// assert_eq!(Register::RBP.size(), 8);
595
  /// assert_eq!(Register::MM6.size(), 8);
596
  /// assert_eq!(Register::XMM10.size(), 16);
597
  /// assert_eq!(Register::YMM10.size(), 32);
598
  /// assert_eq!(Register::ZMM10.size(), 64);
599
  /// assert_eq!(Register::K3.size(), 8);
600
  /// assert_eq!(Register::BND1.size(), 16);
601
  /// assert_eq!(Register::ST7.size(), 10);
602
  /// assert_eq!(Register::CR8.size(), 8);
603
  /// assert_eq!(Register::DR6.size(), 8);
604
  /// assert_eq!(Register::TR3.size(), 4);
605
  /// assert_eq!(Register::RIP.size(), 8);
606
  /// ```
607
  #[must_use]
608
  #[inline]
609
0
  pub fn size(self) -> usize {
610
0
    self.info().size()
611
0
  }
612
}
613
614
#[cfg(any(feature = "instr_info", feature = "encoder"))]
615
impl Register {
616
  /// Checks if it's a segment register (`ES`, `CS`, `SS`, `DS`, `FS`, `GS`)
617
  ///
618
  /// # Examples
619
  ///
620
  /// ```
621
  /// use iced_x86::*;
622
  /// assert!(Register::GS.is_segment_register());
623
  /// assert!(!Register::RCX.is_segment_register());
624
  /// ```
625
  #[must_use]
626
  #[inline]
627
6.80M
  pub fn is_segment_register(self) -> bool {
628
6.80M
    Register::ES <= self && self <= Register::GS
629
6.80M
  }
<iced_x86::register::Register>::is_segment_register
Line
Count
Source
627
6.80M
  pub fn is_segment_register(self) -> bool {
628
6.80M
    Register::ES <= self && self <= Register::GS
629
6.80M
  }
Unexecuted instantiation: <iced_x86::register::Register>::is_segment_register
630
631
  /// Checks if it's a general purpose register (`AL`-`R15L`, `AX`-`R15W`, `EAX`-`R15D`, `RAX`-`R15`)
632
  ///
633
  /// # Examples
634
  ///
635
  /// ```
636
  /// use iced_x86::*;
637
  /// assert!(!Register::GS.is_gpr());
638
  /// assert!(Register::CH.is_gpr());
639
  /// assert!(Register::DX.is_gpr());
640
  /// assert!(Register::R13D.is_gpr());
641
  /// assert!(Register::RSP.is_gpr());
642
  /// assert!(!Register::XMM0.is_gpr());
643
  /// ```
644
  #[must_use]
645
  #[inline]
646
0
  pub fn is_gpr(self) -> bool {
647
0
    Register::AL <= self && self <= Register::R15
648
0
  }
649
650
  /// Checks if it's an 8-bit general purpose register (`AL`-`R15L`)
651
  ///
652
  /// # Examples
653
  ///
654
  /// ```
655
  /// use iced_x86::*;
656
  /// assert!(!Register::GS.is_gpr8());
657
  /// assert!(Register::CH.is_gpr8());
658
  /// assert!(!Register::DX.is_gpr8());
659
  /// assert!(!Register::R13D.is_gpr8());
660
  /// assert!(!Register::RSP.is_gpr8());
661
  /// assert!(!Register::XMM0.is_gpr8());
662
  /// ```
663
  #[must_use]
664
  #[inline]
665
253
  pub fn is_gpr8(self) -> bool {
666
253
    Register::AL <= self && self <= Register::R15L
667
253
  }
<iced_x86::register::Register>::is_gpr8
Line
Count
Source
665
253
  pub fn is_gpr8(self) -> bool {
666
253
    Register::AL <= self && self <= Register::R15L
667
253
  }
Unexecuted instantiation: <iced_x86::register::Register>::is_gpr8
668
669
  /// Checks if it's a 16-bit general purpose register (`AX`-`R15W`)
670
  ///
671
  /// # Examples
672
  ///
673
  /// ```
674
  /// use iced_x86::*;
675
  /// assert!(!Register::GS.is_gpr16());
676
  /// assert!(!Register::CH.is_gpr16());
677
  /// assert!(Register::DX.is_gpr16());
678
  /// assert!(!Register::R13D.is_gpr16());
679
  /// assert!(!Register::RSP.is_gpr16());
680
  /// assert!(!Register::XMM0.is_gpr16());
681
  /// ```
682
  #[must_use]
683
  #[inline]
684
301
  pub fn is_gpr16(self) -> bool {
685
301
    Register::AX <= self && self <= Register::R15W
686
301
  }
<iced_x86::register::Register>::is_gpr16
Line
Count
Source
684
301
  pub fn is_gpr16(self) -> bool {
685
301
    Register::AX <= self && self <= Register::R15W
686
301
  }
Unexecuted instantiation: <iced_x86::register::Register>::is_gpr16
687
688
  /// Checks if it's a 32-bit general purpose register (`EAX`-`R15D`)
689
  ///
690
  /// # Examples
691
  ///
692
  /// ```
693
  /// use iced_x86::*;
694
  /// assert!(!Register::GS.is_gpr32());
695
  /// assert!(!Register::CH.is_gpr32());
696
  /// assert!(!Register::DX.is_gpr32());
697
  /// assert!(Register::R13D.is_gpr32());
698
  /// assert!(!Register::RSP.is_gpr32());
699
  /// assert!(!Register::XMM0.is_gpr32());
700
  /// ```
701
  #[must_use]
702
  #[inline]
703
999
  pub fn is_gpr32(self) -> bool {
704
999
    Register::EAX <= self && self <= Register::R15D
705
999
  }
<iced_x86::register::Register>::is_gpr32
Line
Count
Source
703
999
  pub fn is_gpr32(self) -> bool {
704
999
    Register::EAX <= self && self <= Register::R15D
705
999
  }
Unexecuted instantiation: <iced_x86::register::Register>::is_gpr32
706
707
  /// Checks if it's a 64-bit general purpose register (`RAX`-`R15`)
708
  ///
709
  /// # Examples
710
  ///
711
  /// ```
712
  /// use iced_x86::*;
713
  /// assert!(!Register::GS.is_gpr64());
714
  /// assert!(!Register::CH.is_gpr64());
715
  /// assert!(!Register::DX.is_gpr64());
716
  /// assert!(!Register::R13D.is_gpr64());
717
  /// assert!(Register::RSP.is_gpr64());
718
  /// assert!(!Register::XMM0.is_gpr64());
719
  /// ```
720
  #[must_use]
721
  #[inline]
722
6.81M
  pub fn is_gpr64(self) -> bool {
723
6.81M
    Register::RAX <= self && self <= Register::R15
724
6.81M
  }
<iced_x86::register::Register>::is_gpr64
Line
Count
Source
722
6.81M
  pub fn is_gpr64(self) -> bool {
723
6.81M
    Register::RAX <= self && self <= Register::R15
724
6.81M
  }
Unexecuted instantiation: <iced_x86::register::Register>::is_gpr64
725
726
  /// Checks if it's a 128-bit vector register (`XMM0`-`XMM31`)
727
  ///
728
  /// # Examples
729
  ///
730
  /// ```
731
  /// use iced_x86::*;
732
  /// assert!(!Register::R13D.is_xmm());
733
  /// assert!(!Register::RSP.is_xmm());
734
  /// assert!(Register::XMM0.is_xmm());
735
  /// assert!(!Register::YMM0.is_xmm());
736
  /// assert!(!Register::ZMM0.is_xmm());
737
  /// ```
738
  #[must_use]
739
  #[inline]
740
0
  pub fn is_xmm(self) -> bool {
741
0
    Register::XMM0 <= self && self <= IcedConstants::XMM_LAST
742
0
  }
743
744
  /// Checks if it's a 256-bit vector register (`YMM0`-`YMM31`)
745
  ///
746
  /// # Examples
747
  ///
748
  /// ```
749
  /// use iced_x86::*;
750
  /// assert!(!Register::R13D.is_ymm());
751
  /// assert!(!Register::RSP.is_ymm());
752
  /// assert!(!Register::XMM0.is_ymm());
753
  /// assert!(Register::YMM0.is_ymm());
754
  /// assert!(!Register::ZMM0.is_ymm());
755
  /// ```
756
  #[must_use]
757
  #[inline]
758
0
  pub fn is_ymm(self) -> bool {
759
0
    Register::YMM0 <= self && self <= IcedConstants::YMM_LAST
760
0
  }
761
762
  /// Checks if it's a 512-bit vector register (`ZMM0`-`ZMM31`)
763
  ///
764
  /// # Examples
765
  ///
766
  /// ```
767
  /// use iced_x86::*;
768
  /// assert!(!Register::R13D.is_zmm());
769
  /// assert!(!Register::RSP.is_zmm());
770
  /// assert!(!Register::XMM0.is_zmm());
771
  /// assert!(!Register::YMM0.is_zmm());
772
  /// assert!(Register::ZMM0.is_zmm());
773
  /// ```
774
  #[must_use]
775
  #[inline]
776
0
  pub fn is_zmm(self) -> bool {
777
0
    Register::ZMM0 <= self && self <= IcedConstants::ZMM_LAST
778
0
  }
779
780
  /// Checks if it's an `XMM`, `YMM` or `ZMM` register
781
  ///
782
  /// # Examples
783
  ///
784
  /// ```
785
  /// use iced_x86::*;
786
  /// assert!(!Register::R13D.is_vector_register());
787
  /// assert!(!Register::RSP.is_vector_register());
788
  /// assert!(Register::XMM0.is_vector_register());
789
  /// assert!(Register::YMM0.is_vector_register());
790
  /// assert!(Register::ZMM0.is_vector_register());
791
  /// ```
792
  #[must_use]
793
  #[inline]
794
0
  pub fn is_vector_register(self) -> bool {
795
0
    Register::XMM0 <= self && self <= IcedConstants::VMM_LAST
796
0
  }
797
798
  /// Checks if it's `EIP`/`RIP`
799
  ///
800
  /// # Examples
801
  ///
802
  /// ```
803
  /// use iced_x86::*;
804
  /// assert!(Register::EIP.is_ip());
805
  /// assert!(Register::RIP.is_ip());
806
  /// ```
807
  #[must_use]
808
  #[inline]
809
0
  pub fn is_ip(self) -> bool {
810
0
    self == Register::EIP || self == Register::RIP
811
0
  }
812
813
  /// Checks if it's an opmask register (`K0`-`K7`)
814
  ///
815
  /// # Examples
816
  ///
817
  /// ```
818
  /// use iced_x86::*;
819
  /// assert!(!Register::R13D.is_k());
820
  /// assert!(Register::K3.is_k());
821
  /// ```
822
  #[must_use]
823
  #[inline]
824
0
  pub fn is_k(self) -> bool {
825
0
    Register::K0 <= self && self <= Register::K7
826
0
  }
827
828
  /// Checks if it's a control register (`CR0`-`CR15`)
829
  ///
830
  /// # Examples
831
  ///
832
  /// ```
833
  /// use iced_x86::*;
834
  /// assert!(!Register::R13D.is_cr());
835
  /// assert!(Register::CR3.is_cr());
836
  /// ```
837
  #[must_use]
838
  #[inline]
839
6.80M
  pub fn is_cr(self) -> bool {
840
6.80M
    Register::CR0 <= self && self <= Register::CR15
841
6.80M
  }
<iced_x86::register::Register>::is_cr
Line
Count
Source
839
6.80M
  pub fn is_cr(self) -> bool {
840
6.80M
    Register::CR0 <= self && self <= Register::CR15
841
6.80M
  }
Unexecuted instantiation: <iced_x86::register::Register>::is_cr
842
843
  /// Checks if it's a debug register (`DR0`-`DR15`)
844
  ///
845
  /// # Examples
846
  ///
847
  /// ```
848
  /// use iced_x86::*;
849
  /// assert!(!Register::R13D.is_dr());
850
  /// assert!(Register::DR3.is_dr());
851
  /// ```
852
  #[must_use]
853
  #[inline]
854
0
  pub fn is_dr(self) -> bool {
855
0
    Register::DR0 <= self && self <= Register::DR15
856
0
  }
857
858
  /// Checks if it's a test register (`TR0`-`TR7`)
859
  ///
860
  /// # Examples
861
  ///
862
  /// ```
863
  /// use iced_x86::*;
864
  /// assert!(!Register::R13D.is_tr());
865
  /// assert!(Register::TR3.is_tr());
866
  /// ```
867
  #[must_use]
868
  #[inline]
869
0
  pub fn is_tr(self) -> bool {
870
0
    Register::TR0 <= self && self <= Register::TR7
871
0
  }
872
873
  /// Checks if it's an FPU stack register (`ST0`-`ST7`)
874
  ///
875
  /// # Examples
876
  ///
877
  /// ```
878
  /// use iced_x86::*;
879
  /// assert!(!Register::R13D.is_st());
880
  /// assert!(Register::ST3.is_st());
881
  /// ```
882
  #[must_use]
883
  #[inline]
884
0
  pub fn is_st(self) -> bool {
885
0
    Register::ST0 <= self && self <= Register::ST7
886
0
  }
887
888
  /// Checks if it's a bound register (`BND0`-`BND3`)
889
  ///
890
  /// # Examples
891
  ///
892
  /// ```
893
  /// use iced_x86::*;
894
  /// assert!(!Register::R13D.is_bnd());
895
  /// assert!(Register::BND3.is_bnd());
896
  /// ```
897
  #[must_use]
898
  #[inline]
899
0
  pub fn is_bnd(self) -> bool {
900
0
    Register::BND0 <= self && self <= Register::BND3
901
0
  }
902
903
  /// Checks if it's an MMX register (`MM0`-`MM7`)
904
  ///
905
  /// # Examples
906
  ///
907
  /// ```
908
  /// use iced_x86::*;
909
  /// assert!(!Register::R13D.is_mm());
910
  /// assert!(Register::MM3.is_mm());
911
  /// ```
912
  #[must_use]
913
  #[inline]
914
0
  pub fn is_mm(self) -> bool {
915
0
    Register::MM0 <= self && self <= Register::MM7
916
0
  }
917
918
  /// Checks if it's a tile register (`TMM0`-`TMM7`)
919
  ///
920
  /// # Examples
921
  ///
922
  /// ```
923
  /// use iced_x86::*;
924
  /// assert!(!Register::R13D.is_tmm());
925
  /// assert!(Register::TMM3.is_tmm());
926
  /// ```
927
  #[must_use]
928
  #[inline]
929
0
  pub fn is_tmm(self) -> bool {
930
0
    Register::TMM0 <= self && self <= IcedConstants::TMM_LAST
931
0
  }
932
}
933
934
// GENERATOR-BEGIN: Register
935
// ⚠️This was generated by GENERATOR!🦹‍♂️
936
/// A register
937
#[derive(Copy, Clone, Eq, PartialEq, Ord, PartialOrd, Hash)]
938
#[cfg_attr(not(feature = "exhaustive_enums"), non_exhaustive)]
939
#[allow(missing_docs)]
940
pub enum Register {
941
  None = 0,
942
  AL = 1,
943
  CL = 2,
944
  DL = 3,
945
  BL = 4,
946
  AH = 5,
947
  CH = 6,
948
  DH = 7,
949
  BH = 8,
950
  SPL = 9,
951
  BPL = 10,
952
  SIL = 11,
953
  DIL = 12,
954
  R8L = 13,
955
  R9L = 14,
956
  R10L = 15,
957
  R11L = 16,
958
  R12L = 17,
959
  R13L = 18,
960
  R14L = 19,
961
  R15L = 20,
962
  AX = 21,
963
  CX = 22,
964
  DX = 23,
965
  BX = 24,
966
  SP = 25,
967
  BP = 26,
968
  SI = 27,
969
  DI = 28,
970
  R8W = 29,
971
  R9W = 30,
972
  R10W = 31,
973
  R11W = 32,
974
  R12W = 33,
975
  R13W = 34,
976
  R14W = 35,
977
  R15W = 36,
978
  EAX = 37,
979
  ECX = 38,
980
  EDX = 39,
981
  EBX = 40,
982
  ESP = 41,
983
  EBP = 42,
984
  ESI = 43,
985
  EDI = 44,
986
  R8D = 45,
987
  R9D = 46,
988
  R10D = 47,
989
  R11D = 48,
990
  R12D = 49,
991
  R13D = 50,
992
  R14D = 51,
993
  R15D = 52,
994
  RAX = 53,
995
  RCX = 54,
996
  RDX = 55,
997
  RBX = 56,
998
  RSP = 57,
999
  RBP = 58,
1000
  RSI = 59,
1001
  RDI = 60,
1002
  R8 = 61,
1003
  R9 = 62,
1004
  R10 = 63,
1005
  R11 = 64,
1006
  R12 = 65,
1007
  R13 = 66,
1008
  R14 = 67,
1009
  R15 = 68,
1010
  EIP = 69,
1011
  RIP = 70,
1012
  ES = 71,
1013
  CS = 72,
1014
  SS = 73,
1015
  DS = 74,
1016
  FS = 75,
1017
  GS = 76,
1018
  XMM0 = 77,
1019
  XMM1 = 78,
1020
  XMM2 = 79,
1021
  XMM3 = 80,
1022
  XMM4 = 81,
1023
  XMM5 = 82,
1024
  XMM6 = 83,
1025
  XMM7 = 84,
1026
  XMM8 = 85,
1027
  XMM9 = 86,
1028
  XMM10 = 87,
1029
  XMM11 = 88,
1030
  XMM12 = 89,
1031
  XMM13 = 90,
1032
  XMM14 = 91,
1033
  XMM15 = 92,
1034
  XMM16 = 93,
1035
  XMM17 = 94,
1036
  XMM18 = 95,
1037
  XMM19 = 96,
1038
  XMM20 = 97,
1039
  XMM21 = 98,
1040
  XMM22 = 99,
1041
  XMM23 = 100,
1042
  XMM24 = 101,
1043
  XMM25 = 102,
1044
  XMM26 = 103,
1045
  XMM27 = 104,
1046
  XMM28 = 105,
1047
  XMM29 = 106,
1048
  XMM30 = 107,
1049
  XMM31 = 108,
1050
  YMM0 = 109,
1051
  YMM1 = 110,
1052
  YMM2 = 111,
1053
  YMM3 = 112,
1054
  YMM4 = 113,
1055
  YMM5 = 114,
1056
  YMM6 = 115,
1057
  YMM7 = 116,
1058
  YMM8 = 117,
1059
  YMM9 = 118,
1060
  YMM10 = 119,
1061
  YMM11 = 120,
1062
  YMM12 = 121,
1063
  YMM13 = 122,
1064
  YMM14 = 123,
1065
  YMM15 = 124,
1066
  YMM16 = 125,
1067
  YMM17 = 126,
1068
  YMM18 = 127,
1069
  YMM19 = 128,
1070
  YMM20 = 129,
1071
  YMM21 = 130,
1072
  YMM22 = 131,
1073
  YMM23 = 132,
1074
  YMM24 = 133,
1075
  YMM25 = 134,
1076
  YMM26 = 135,
1077
  YMM27 = 136,
1078
  YMM28 = 137,
1079
  YMM29 = 138,
1080
  YMM30 = 139,
1081
  YMM31 = 140,
1082
  ZMM0 = 141,
1083
  ZMM1 = 142,
1084
  ZMM2 = 143,
1085
  ZMM3 = 144,
1086
  ZMM4 = 145,
1087
  ZMM5 = 146,
1088
  ZMM6 = 147,
1089
  ZMM7 = 148,
1090
  ZMM8 = 149,
1091
  ZMM9 = 150,
1092
  ZMM10 = 151,
1093
  ZMM11 = 152,
1094
  ZMM12 = 153,
1095
  ZMM13 = 154,
1096
  ZMM14 = 155,
1097
  ZMM15 = 156,
1098
  ZMM16 = 157,
1099
  ZMM17 = 158,
1100
  ZMM18 = 159,
1101
  ZMM19 = 160,
1102
  ZMM20 = 161,
1103
  ZMM21 = 162,
1104
  ZMM22 = 163,
1105
  ZMM23 = 164,
1106
  ZMM24 = 165,
1107
  ZMM25 = 166,
1108
  ZMM26 = 167,
1109
  ZMM27 = 168,
1110
  ZMM28 = 169,
1111
  ZMM29 = 170,
1112
  ZMM30 = 171,
1113
  ZMM31 = 172,
1114
  K0 = 173,
1115
  K1 = 174,
1116
  K2 = 175,
1117
  K3 = 176,
1118
  K4 = 177,
1119
  K5 = 178,
1120
  K6 = 179,
1121
  K7 = 180,
1122
  BND0 = 181,
1123
  BND1 = 182,
1124
  BND2 = 183,
1125
  BND3 = 184,
1126
  CR0 = 185,
1127
  CR1 = 186,
1128
  CR2 = 187,
1129
  CR3 = 188,
1130
  CR4 = 189,
1131
  CR5 = 190,
1132
  CR6 = 191,
1133
  CR7 = 192,
1134
  CR8 = 193,
1135
  CR9 = 194,
1136
  CR10 = 195,
1137
  CR11 = 196,
1138
  CR12 = 197,
1139
  CR13 = 198,
1140
  CR14 = 199,
1141
  CR15 = 200,
1142
  DR0 = 201,
1143
  DR1 = 202,
1144
  DR2 = 203,
1145
  DR3 = 204,
1146
  DR4 = 205,
1147
  DR5 = 206,
1148
  DR6 = 207,
1149
  DR7 = 208,
1150
  DR8 = 209,
1151
  DR9 = 210,
1152
  DR10 = 211,
1153
  DR11 = 212,
1154
  DR12 = 213,
1155
  DR13 = 214,
1156
  DR14 = 215,
1157
  DR15 = 216,
1158
  ST0 = 217,
1159
  ST1 = 218,
1160
  ST2 = 219,
1161
  ST3 = 220,
1162
  ST4 = 221,
1163
  ST5 = 222,
1164
  ST6 = 223,
1165
  ST7 = 224,
1166
  MM0 = 225,
1167
  MM1 = 226,
1168
  MM2 = 227,
1169
  MM3 = 228,
1170
  MM4 = 229,
1171
  MM5 = 230,
1172
  MM6 = 231,
1173
  MM7 = 232,
1174
  TR0 = 233,
1175
  TR1 = 234,
1176
  TR2 = 235,
1177
  TR3 = 236,
1178
  TR4 = 237,
1179
  TR5 = 238,
1180
  TR6 = 239,
1181
  TR7 = 240,
1182
  TMM0 = 241,
1183
  TMM1 = 242,
1184
  TMM2 = 243,
1185
  TMM3 = 244,
1186
  TMM4 = 245,
1187
  TMM5 = 246,
1188
  TMM6 = 247,
1189
  TMM7 = 248,
1190
  /// Don't use it!
1191
  #[deprecated(since = "1.12.0", note = "Not part of the public API")]
1192
  DontUse0 = 249,
1193
  /// Don't use it!
1194
  #[deprecated(since = "1.12.0", note = "Not part of the public API")]
1195
  DontUseFA = 250,
1196
  /// Don't use it!
1197
  #[deprecated(since = "1.12.0", note = "Not part of the public API")]
1198
  DontUseFB = 251,
1199
  /// Don't use it!
1200
  #[deprecated(since = "1.12.0", note = "Not part of the public API")]
1201
  DontUseFC = 252,
1202
  /// Don't use it!
1203
  #[deprecated(since = "1.12.0", note = "Not part of the public API")]
1204
  DontUseFD = 253,
1205
  /// Don't use it!
1206
  #[deprecated(since = "1.12.0", note = "Not part of the public API")]
1207
  DontUseFE = 254,
1208
  /// Don't use it!
1209
  #[deprecated(since = "1.12.0", note = "Not part of the public API")]
1210
  DontUseFF = 255,
1211
}
1212
#[rustfmt::skip]
1213
static GEN_DEBUG_REGISTER: [&str; 256] = [
1214
  "None",
1215
  "AL",
1216
  "CL",
1217
  "DL",
1218
  "BL",
1219
  "AH",
1220
  "CH",
1221
  "DH",
1222
  "BH",
1223
  "SPL",
1224
  "BPL",
1225
  "SIL",
1226
  "DIL",
1227
  "R8L",
1228
  "R9L",
1229
  "R10L",
1230
  "R11L",
1231
  "R12L",
1232
  "R13L",
1233
  "R14L",
1234
  "R15L",
1235
  "AX",
1236
  "CX",
1237
  "DX",
1238
  "BX",
1239
  "SP",
1240
  "BP",
1241
  "SI",
1242
  "DI",
1243
  "R8W",
1244
  "R9W",
1245
  "R10W",
1246
  "R11W",
1247
  "R12W",
1248
  "R13W",
1249
  "R14W",
1250
  "R15W",
1251
  "EAX",
1252
  "ECX",
1253
  "EDX",
1254
  "EBX",
1255
  "ESP",
1256
  "EBP",
1257
  "ESI",
1258
  "EDI",
1259
  "R8D",
1260
  "R9D",
1261
  "R10D",
1262
  "R11D",
1263
  "R12D",
1264
  "R13D",
1265
  "R14D",
1266
  "R15D",
1267
  "RAX",
1268
  "RCX",
1269
  "RDX",
1270
  "RBX",
1271
  "RSP",
1272
  "RBP",
1273
  "RSI",
1274
  "RDI",
1275
  "R8",
1276
  "R9",
1277
  "R10",
1278
  "R11",
1279
  "R12",
1280
  "R13",
1281
  "R14",
1282
  "R15",
1283
  "EIP",
1284
  "RIP",
1285
  "ES",
1286
  "CS",
1287
  "SS",
1288
  "DS",
1289
  "FS",
1290
  "GS",
1291
  "XMM0",
1292
  "XMM1",
1293
  "XMM2",
1294
  "XMM3",
1295
  "XMM4",
1296
  "XMM5",
1297
  "XMM6",
1298
  "XMM7",
1299
  "XMM8",
1300
  "XMM9",
1301
  "XMM10",
1302
  "XMM11",
1303
  "XMM12",
1304
  "XMM13",
1305
  "XMM14",
1306
  "XMM15",
1307
  "XMM16",
1308
  "XMM17",
1309
  "XMM18",
1310
  "XMM19",
1311
  "XMM20",
1312
  "XMM21",
1313
  "XMM22",
1314
  "XMM23",
1315
  "XMM24",
1316
  "XMM25",
1317
  "XMM26",
1318
  "XMM27",
1319
  "XMM28",
1320
  "XMM29",
1321
  "XMM30",
1322
  "XMM31",
1323
  "YMM0",
1324
  "YMM1",
1325
  "YMM2",
1326
  "YMM3",
1327
  "YMM4",
1328
  "YMM5",
1329
  "YMM6",
1330
  "YMM7",
1331
  "YMM8",
1332
  "YMM9",
1333
  "YMM10",
1334
  "YMM11",
1335
  "YMM12",
1336
  "YMM13",
1337
  "YMM14",
1338
  "YMM15",
1339
  "YMM16",
1340
  "YMM17",
1341
  "YMM18",
1342
  "YMM19",
1343
  "YMM20",
1344
  "YMM21",
1345
  "YMM22",
1346
  "YMM23",
1347
  "YMM24",
1348
  "YMM25",
1349
  "YMM26",
1350
  "YMM27",
1351
  "YMM28",
1352
  "YMM29",
1353
  "YMM30",
1354
  "YMM31",
1355
  "ZMM0",
1356
  "ZMM1",
1357
  "ZMM2",
1358
  "ZMM3",
1359
  "ZMM4",
1360
  "ZMM5",
1361
  "ZMM6",
1362
  "ZMM7",
1363
  "ZMM8",
1364
  "ZMM9",
1365
  "ZMM10",
1366
  "ZMM11",
1367
  "ZMM12",
1368
  "ZMM13",
1369
  "ZMM14",
1370
  "ZMM15",
1371
  "ZMM16",
1372
  "ZMM17",
1373
  "ZMM18",
1374
  "ZMM19",
1375
  "ZMM20",
1376
  "ZMM21",
1377
  "ZMM22",
1378
  "ZMM23",
1379
  "ZMM24",
1380
  "ZMM25",
1381
  "ZMM26",
1382
  "ZMM27",
1383
  "ZMM28",
1384
  "ZMM29",
1385
  "ZMM30",
1386
  "ZMM31",
1387
  "K0",
1388
  "K1",
1389
  "K2",
1390
  "K3",
1391
  "K4",
1392
  "K5",
1393
  "K6",
1394
  "K7",
1395
  "BND0",
1396
  "BND1",
1397
  "BND2",
1398
  "BND3",
1399
  "CR0",
1400
  "CR1",
1401
  "CR2",
1402
  "CR3",
1403
  "CR4",
1404
  "CR5",
1405
  "CR6",
1406
  "CR7",
1407
  "CR8",
1408
  "CR9",
1409
  "CR10",
1410
  "CR11",
1411
  "CR12",
1412
  "CR13",
1413
  "CR14",
1414
  "CR15",
1415
  "DR0",
1416
  "DR1",
1417
  "DR2",
1418
  "DR3",
1419
  "DR4",
1420
  "DR5",
1421
  "DR6",
1422
  "DR7",
1423
  "DR8",
1424
  "DR9",
1425
  "DR10",
1426
  "DR11",
1427
  "DR12",
1428
  "DR13",
1429
  "DR14",
1430
  "DR15",
1431
  "ST0",
1432
  "ST1",
1433
  "ST2",
1434
  "ST3",
1435
  "ST4",
1436
  "ST5",
1437
  "ST6",
1438
  "ST7",
1439
  "MM0",
1440
  "MM1",
1441
  "MM2",
1442
  "MM3",
1443
  "MM4",
1444
  "MM5",
1445
  "MM6",
1446
  "MM7",
1447
  "TR0",
1448
  "TR1",
1449
  "TR2",
1450
  "TR3",
1451
  "TR4",
1452
  "TR5",
1453
  "TR6",
1454
  "TR7",
1455
  "TMM0",
1456
  "TMM1",
1457
  "TMM2",
1458
  "TMM3",
1459
  "TMM4",
1460
  "TMM5",
1461
  "TMM6",
1462
  "TMM7",
1463
  "DontUse0",
1464
  "DontUseFA",
1465
  "DontUseFB",
1466
  "DontUseFC",
1467
  "DontUseFD",
1468
  "DontUseFE",
1469
  "DontUseFF",
1470
];
1471
impl fmt::Debug for Register {
1472
  #[inline]
1473
18
  fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result {
1474
18
    write!(f, "{}", GEN_DEBUG_REGISTER[*self as usize])
1475
18
  }
1476
}
1477
impl Default for Register {
1478
  #[must_use]
1479
  #[inline]
1480
25.8k
  fn default() -> Self {
1481
25.8k
    Register::None
1482
25.8k
  }
<iced_x86::register::Register as core::default::Default>::default
Line
Count
Source
1480
4.09k
  fn default() -> Self {
1481
4.09k
    Register::None
1482
4.09k
  }
<iced_x86::register::Register as core::default::Default>::default
Line
Count
Source
1480
21.7k
  fn default() -> Self {
1481
21.7k
    Register::None
1482
21.7k
  }
1483
}
1484
#[allow(non_camel_case_types)]
1485
#[allow(dead_code)]
1486
pub(crate) type RegisterUnderlyingType = u8;
1487
#[rustfmt::skip]
1488
impl Register {
1489
  /// Iterates over all `Register` enum values
1490
  #[inline]
1491
0
  pub fn values() -> impl Iterator<Item = Register> + DoubleEndedIterator + ExactSizeIterator + FusedIterator {
1492
    // SAFETY: all values 0-max are valid enum values
1493
0
    (0..IcedConstants::REGISTER_ENUM_COUNT).map(|x| unsafe { mem::transmute::<u8, Register>(x as u8) })
1494
0
  }
1495
}
1496
#[test]
1497
#[rustfmt::skip]
1498
fn test_register_values() {
1499
  let mut iter = Register::values();
1500
  assert_eq!(iter.size_hint(), (IcedConstants::REGISTER_ENUM_COUNT, Some(IcedConstants::REGISTER_ENUM_COUNT)));
1501
  assert_eq!(iter.len(), IcedConstants::REGISTER_ENUM_COUNT);
1502
  assert!(iter.next().is_some());
1503
  assert_eq!(iter.size_hint(), (IcedConstants::REGISTER_ENUM_COUNT - 1, Some(IcedConstants::REGISTER_ENUM_COUNT - 1)));
1504
  assert_eq!(iter.len(), IcedConstants::REGISTER_ENUM_COUNT - 1);
1505
1506
  let values: Vec<Register> = Register::values().collect();
1507
  assert_eq!(values.len(), IcedConstants::REGISTER_ENUM_COUNT);
1508
  for (i, value) in values.into_iter().enumerate() {
1509
    assert_eq!(i, value as usize);
1510
  }
1511
1512
  let values1: Vec<Register> = Register::values().collect();
1513
  let mut values2: Vec<Register> = Register::values().rev().collect();
1514
  values2.reverse();
1515
  assert_eq!(values1, values2);
1516
}
1517
#[rustfmt::skip]
1518
impl TryFrom<usize> for Register {
1519
  type Error = IcedError;
1520
  #[inline]
1521
0
  fn try_from(value: usize) -> Result<Self, Self::Error> {
1522
0
    if value < IcedConstants::REGISTER_ENUM_COUNT {
1523
      // SAFETY: all values 0-max are valid enum values
1524
0
      Ok(unsafe { mem::transmute(value as u8) })
1525
    } else {
1526
0
      Err(IcedError::new("Invalid Register value"))
1527
    }
1528
0
  }
1529
}
1530
#[test]
1531
#[rustfmt::skip]
1532
fn test_register_try_from_usize() {
1533
  for value in Register::values() {
1534
    let converted = <Register as TryFrom<usize>>::try_from(value as usize).unwrap();
1535
    assert_eq!(converted, value);
1536
  }
1537
  assert!(<Register as TryFrom<usize>>::try_from(IcedConstants::REGISTER_ENUM_COUNT).is_err());
1538
  assert!(<Register as TryFrom<usize>>::try_from(core::usize::MAX).is_err());
1539
}
1540
#[cfg(feature = "serde")]
1541
#[rustfmt::skip]
1542
#[allow(clippy::zero_sized_map_values)]
1543
const _: () = {
1544
  use core::marker::PhantomData;
1545
  use serde::de;
1546
  use serde::{Deserialize, Deserializer, Serialize, Serializer};
1547
  type EnumType = Register;
1548
  impl Serialize for EnumType {
1549
    #[inline]
1550
    fn serialize<S>(&self, serializer: S) -> Result<S::Ok, S::Error>
1551
    where
1552
      S: Serializer,
1553
    {
1554
      serializer.serialize_u8(*self as u8)
1555
    }
1556
  }
1557
  impl<'de> Deserialize<'de> for EnumType {
1558
    #[inline]
1559
    fn deserialize<D>(deserializer: D) -> Result<Self, D::Error>
1560
    where
1561
      D: Deserializer<'de>,
1562
    {
1563
      struct Visitor<'de> {
1564
        marker: PhantomData<EnumType>,
1565
        lifetime: PhantomData<&'de ()>,
1566
      }
1567
      impl<'de> de::Visitor<'de> for Visitor<'de> {
1568
        type Value = EnumType;
1569
        #[inline]
1570
        fn expecting(&self, formatter: &mut fmt::Formatter<'_>) -> fmt::Result {
1571
          formatter.write_str("enum Register")
1572
        }
1573
        #[inline]
1574
        fn visit_u64<E>(self, v: u64) -> Result<Self::Value, E>
1575
        where
1576
          E: de::Error,
1577
        {
1578
          if let Ok(v) = <usize as TryFrom<_>>::try_from(v) {
1579
            if let Ok(value) = <EnumType as TryFrom<_>>::try_from(v) {
1580
              return Ok(value);
1581
            }
1582
          }
1583
          Err(de::Error::invalid_value(de::Unexpected::Unsigned(v), &"a valid Register variant value"))
1584
        }
1585
      }
1586
      deserializer.deserialize_u8(Visitor { marker: PhantomData::<EnumType>, lifetime: PhantomData })
1587
    }
1588
  }
1589
};
1590
// GENERATOR-END: Register
1591
1592
impl Register {
1593
  #[allow(clippy::unwrap_used)]
1594
0
  pub(crate) fn from_u8(value: u8) -> Register {
1595
    const _: () = assert!(IcedConstants::REGISTER_ENUM_COUNT >= 0x100);
1596
    // This can't panic since all `u8` values are Register variants
1597
0
    Register::try_from(value as usize).unwrap()
1598
0
  }
1599
}
1600
1601
impl Register {
1602
  #[must_use]
1603
4
  fn add(self, rhs: u32) -> Self {
1604
4
    let result = (self as u32).wrapping_add(rhs);
1605
4
    iced_assert!(result < IcedConstants::REGISTER_ENUM_COUNT as u32);
1606
    // SAFETY: verified by the assert above. All values 0-max are valid enum values
1607
4
    unsafe { mem::transmute(result as RegisterUnderlyingType) }
1608
4
  }
1609
  #[must_use]
1610
0
  fn sub(self, rhs: u32) -> Self {
1611
0
    let result = (self as u32).wrapping_sub(rhs);
1612
0
    iced_assert!(result < IcedConstants::REGISTER_ENUM_COUNT as u32);
1613
    // SAFETY: verified by the assert above. All values 0-max are valid enum values
1614
0
    unsafe { mem::transmute(result as RegisterUnderlyingType) }
1615
0
  }
1616
}
1617
// i32 + Register
1618
impl Add<Register> for i32 {
1619
  type Output = Register;
1620
1621
  #[must_use]
1622
  #[inline]
1623
0
  fn add(self, rhs: Register) -> Self::Output {
1624
0
    rhs.add(self as u32)
1625
0
  }
1626
}
1627
// u32 + Register
1628
impl Add<Register> for u32 {
1629
  type Output = Register;
1630
1631
  #[must_use]
1632
  #[inline]
1633
4
  fn add(self, rhs: Register) -> Self::Output {
1634
4
    rhs.add(self)
1635
4
  }
1636
}
1637
// Register + i32
1638
impl Add<i32> for Register {
1639
  type Output = Self;
1640
1641
  #[must_use]
1642
  #[inline]
1643
0
  fn add(self, rhs: i32) -> Self::Output {
1644
0
    self.add(rhs as u32)
1645
0
  }
1646
}
1647
// Register + u32
1648
impl Add<u32> for Register {
1649
  type Output = Self;
1650
1651
  #[must_use]
1652
  #[inline]
1653
0
  fn add(self, rhs: u32) -> Self::Output {
1654
0
    self.add(rhs)
1655
0
  }
1656
}
1657
// Register += i32
1658
impl AddAssign<i32> for Register {
1659
  #[inline]
1660
0
  fn add_assign(&mut self, rhs: i32) {
1661
0
    *self = self.add(rhs as u32)
1662
0
  }
1663
}
1664
// Register += u32
1665
impl AddAssign<u32> for Register {
1666
  #[inline]
1667
0
  fn add_assign(&mut self, rhs: u32) {
1668
0
    *self = self.add(rhs)
1669
0
  }
1670
}
1671
// Register - i32
1672
impl Sub<i32> for Register {
1673
  type Output = Self;
1674
1675
  #[must_use]
1676
  #[inline]
1677
0
  fn sub(self, rhs: i32) -> Self::Output {
1678
0
    self.sub(rhs as u32)
1679
0
  }
1680
}
1681
// Register - u32
1682
impl Sub<u32> for Register {
1683
  type Output = Self;
1684
1685
  #[must_use]
1686
  #[inline]
1687
0
  fn sub(self, rhs: u32) -> Self::Output {
1688
0
    self.sub(rhs)
1689
0
  }
1690
}
1691
// Register -= i32
1692
impl SubAssign<i32> for Register {
1693
  #[inline]
1694
0
  fn sub_assign(&mut self, rhs: i32) {
1695
0
    *self = self.sub(rhs as u32)
1696
0
  }
1697
}
1698
// Register -= u32
1699
impl SubAssign<u32> for Register {
1700
  #[inline]
1701
0
  fn sub_assign(&mut self, rhs: u32) {
1702
0
    *self = self.sub(rhs)
1703
0
  }
1704
}