/src/boringssl/crypto/cpu_intel.c
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1 | | /* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com) |
2 | | * All rights reserved. |
3 | | * |
4 | | * This package is an SSL implementation written |
5 | | * by Eric Young (eay@cryptsoft.com). |
6 | | * The implementation was written so as to conform with Netscapes SSL. |
7 | | * |
8 | | * This library is free for commercial and non-commercial use as long as |
9 | | * the following conditions are aheared to. The following conditions |
10 | | * apply to all code found in this distribution, be it the RC4, RSA, |
11 | | * lhash, DES, etc., code; not just the SSL code. The SSL documentation |
12 | | * included with this distribution is covered by the same copyright terms |
13 | | * except that the holder is Tim Hudson (tjh@cryptsoft.com). |
14 | | * |
15 | | * Copyright remains Eric Young's, and as such any Copyright notices in |
16 | | * the code are not to be removed. |
17 | | * If this package is used in a product, Eric Young should be given attribution |
18 | | * as the author of the parts of the library used. |
19 | | * This can be in the form of a textual message at program startup or |
20 | | * in documentation (online or textual) provided with the package. |
21 | | * |
22 | | * Redistribution and use in source and binary forms, with or without |
23 | | * modification, are permitted provided that the following conditions |
24 | | * are met: |
25 | | * 1. Redistributions of source code must retain the copyright |
26 | | * notice, this list of conditions and the following disclaimer. |
27 | | * 2. Redistributions in binary form must reproduce the above copyright |
28 | | * notice, this list of conditions and the following disclaimer in the |
29 | | * documentation and/or other materials provided with the distribution. |
30 | | * 3. All advertising materials mentioning features or use of this software |
31 | | * must display the following acknowledgement: |
32 | | * "This product includes cryptographic software written by |
33 | | * Eric Young (eay@cryptsoft.com)" |
34 | | * The word 'cryptographic' can be left out if the rouines from the library |
35 | | * being used are not cryptographic related :-). |
36 | | * 4. If you include any Windows specific code (or a derivative thereof) from |
37 | | * the apps directory (application code) you must include an acknowledgement: |
38 | | * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)" |
39 | | * |
40 | | * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND |
41 | | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
42 | | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
43 | | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
44 | | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
45 | | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
46 | | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
47 | | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
48 | | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
49 | | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
50 | | * SUCH DAMAGE. |
51 | | * |
52 | | * The licence and distribution terms for any publically available version or |
53 | | * derivative of this code cannot be changed. i.e. this code cannot simply be |
54 | | * copied and put under another distribution licence |
55 | | * [including the GNU Public Licence.] */ |
56 | | |
57 | | #include <openssl/base.h> |
58 | | |
59 | | #if !defined(OPENSSL_NO_ASM) && (defined(OPENSSL_X86) || defined(OPENSSL_X86_64)) |
60 | | |
61 | | #include <inttypes.h> |
62 | | #include <stdio.h> |
63 | | #include <stdlib.h> |
64 | | #include <string.h> |
65 | | |
66 | | #if defined(_MSC_VER) |
67 | | OPENSSL_MSVC_PRAGMA(warning(push, 3)) |
68 | | #include <immintrin.h> |
69 | | #include <intrin.h> |
70 | | OPENSSL_MSVC_PRAGMA(warning(pop)) |
71 | | #endif |
72 | | |
73 | | #include "internal.h" |
74 | | |
75 | | |
76 | | // OPENSSL_cpuid runs the cpuid instruction. |leaf| is passed in as EAX and ECX |
77 | | // is set to zero. It writes EAX, EBX, ECX, and EDX to |*out_eax| through |
78 | | // |*out_edx|. |
79 | | static void OPENSSL_cpuid(uint32_t *out_eax, uint32_t *out_ebx, |
80 | 3 | uint32_t *out_ecx, uint32_t *out_edx, uint32_t leaf) { |
81 | | #if defined(_MSC_VER) |
82 | | int tmp[4]; |
83 | | __cpuid(tmp, (int)leaf); |
84 | | *out_eax = (uint32_t)tmp[0]; |
85 | | *out_ebx = (uint32_t)tmp[1]; |
86 | | *out_ecx = (uint32_t)tmp[2]; |
87 | | *out_edx = (uint32_t)tmp[3]; |
88 | | #elif defined(__pic__) && defined(OPENSSL_32_BIT) |
89 | | // Inline assembly may not clobber the PIC register. For 32-bit, this is EBX. |
90 | | // See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=47602. |
91 | | __asm__ volatile ( |
92 | | "xor %%ecx, %%ecx\n" |
93 | | "mov %%ebx, %%edi\n" |
94 | | "cpuid\n" |
95 | | "xchg %%edi, %%ebx\n" |
96 | | : "=a"(*out_eax), "=D"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx) |
97 | | : "a"(leaf) |
98 | | ); |
99 | | #else |
100 | 3 | __asm__ volatile ( |
101 | 3 | "xor %%ecx, %%ecx\n" |
102 | 3 | "cpuid\n" |
103 | 3 | : "=a"(*out_eax), "=b"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx) |
104 | 3 | : "a"(leaf) |
105 | 3 | ); |
106 | 3 | #endif |
107 | 3 | } |
108 | | |
109 | | // OPENSSL_xgetbv returns the value of an Intel Extended Control Register (XCR). |
110 | | // Currently only XCR0 is defined by Intel so |xcr| should always be zero. |
111 | 1 | static uint64_t OPENSSL_xgetbv(uint32_t xcr) { |
112 | | #if defined(_MSC_VER) |
113 | | return (uint64_t)_xgetbv(xcr); |
114 | | #else |
115 | 1 | uint32_t eax, edx; |
116 | 1 | __asm__ volatile ("xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr)); |
117 | 1 | return (((uint64_t)edx) << 32) | eax; |
118 | 1 | #endif |
119 | 1 | } |
120 | | |
121 | | // handle_cpu_env applies the value from |in| to the CPUID values in |out[0]| |
122 | | // and |out[1]|. See the comment in |OPENSSL_cpuid_setup| about this. |
123 | 0 | static void handle_cpu_env(uint32_t *out, const char *in) { |
124 | 0 | const int invert = in[0] == '~'; |
125 | 0 | const int or = in[0] == '|'; |
126 | 0 | const int skip_first_byte = invert || or; |
127 | 0 | const int hex = in[skip_first_byte] == '0' && in[skip_first_byte+1] == 'x'; |
128 | |
|
129 | 0 | int sscanf_result; |
130 | 0 | uint64_t v; |
131 | 0 | if (hex) { |
132 | 0 | sscanf_result = sscanf(in + invert + 2, "%" PRIx64, &v); |
133 | 0 | } else { |
134 | 0 | sscanf_result = sscanf(in + invert, "%" PRIu64, &v); |
135 | 0 | } |
136 | |
|
137 | 0 | if (!sscanf_result) { |
138 | 0 | return; |
139 | 0 | } |
140 | | |
141 | 0 | if (invert) { |
142 | 0 | out[0] &= ~v; |
143 | 0 | out[1] &= ~(v >> 32); |
144 | 0 | } else if (or) { |
145 | 0 | out[0] |= v; |
146 | 0 | out[1] |= (v >> 32); |
147 | 0 | } else { |
148 | 0 | out[0] = v; |
149 | 0 | out[1] = v >> 32; |
150 | 0 | } |
151 | 0 | } |
152 | | |
153 | 1 | void OPENSSL_cpuid_setup(void) { |
154 | | // Determine the vendor and maximum input value. |
155 | 1 | uint32_t eax, ebx, ecx, edx; |
156 | 1 | OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0); |
157 | | |
158 | 1 | uint32_t num_ids = eax; |
159 | | |
160 | 1 | int is_intel = ebx == 0x756e6547 /* Genu */ && |
161 | 1 | edx == 0x49656e69 /* ineI */ && |
162 | 1 | ecx == 0x6c65746e /* ntel */; |
163 | 1 | int is_amd = ebx == 0x68747541 /* Auth */ && |
164 | 1 | edx == 0x69746e65 /* enti */ && |
165 | 1 | ecx == 0x444d4163 /* cAMD */; |
166 | | |
167 | 1 | uint32_t extended_features[2] = {0}; |
168 | 1 | if (num_ids >= 7) { |
169 | 1 | OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 7); |
170 | 1 | extended_features[0] = ebx; |
171 | 1 | extended_features[1] = ecx; |
172 | 1 | } |
173 | | |
174 | 1 | OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 1); |
175 | | |
176 | 1 | const uint32_t base_family = (eax >> 8) & 15; |
177 | 1 | const uint32_t base_model = (eax >> 4) & 15; |
178 | | |
179 | 1 | uint32_t family = base_family; |
180 | 1 | uint32_t model = base_model; |
181 | 1 | if (base_family == 15) { |
182 | 1 | const uint32_t ext_family = (eax >> 20) & 255; |
183 | 1 | family += ext_family; |
184 | 1 | } |
185 | 1 | if (base_family == 6 || base_family == 15) { |
186 | 1 | const uint32_t ext_model = (eax >> 16) & 15; |
187 | 1 | model |= ext_model << 4; |
188 | 1 | } |
189 | | |
190 | 1 | if (is_amd) { |
191 | 1 | if (family < 0x17 || (family == 0x17 && 0x70 <= model && model <= 0x7f)) { |
192 | | // Disable RDRAND on AMD families before 0x17 (Zen) due to reported |
193 | | // failures after suspend. |
194 | | // https://bugzilla.redhat.com/show_bug.cgi?id=1150286 |
195 | | // Also disable for family 0x17, models 0x70–0x7f, due to possible RDRAND |
196 | | // failures there too. |
197 | 0 | ecx &= ~(1u << 30); |
198 | 0 | } |
199 | 1 | } |
200 | | |
201 | | // Force the hyper-threading bit so that the more conservative path is always |
202 | | // chosen. |
203 | 1 | edx |= 1u << 28; |
204 | | |
205 | | // Reserved bit #20 was historically repurposed to control the in-memory |
206 | | // representation of RC4 state. Always set it to zero. |
207 | 1 | edx &= ~(1u << 20); |
208 | | |
209 | | // Reserved bit #30 is repurposed to signal an Intel CPU. |
210 | 1 | if (is_intel) { |
211 | 0 | edx |= (1u << 30); |
212 | 1 | } else { |
213 | 1 | edx &= ~(1u << 30); |
214 | 1 | } |
215 | | |
216 | | // The SDBG bit is repurposed to denote AMD XOP support. Don't ever use AMD |
217 | | // XOP code paths. |
218 | 1 | ecx &= ~(1u << 11); |
219 | | |
220 | 1 | uint64_t xcr0 = 0; |
221 | 1 | if (ecx & (1u << 27)) { |
222 | | // XCR0 may only be queried if the OSXSAVE bit is set. |
223 | 1 | xcr0 = OPENSSL_xgetbv(0); |
224 | 1 | } |
225 | | // See Intel manual, volume 1, section 14.3. |
226 | 1 | if ((xcr0 & 6) != 6) { |
227 | | // YMM registers cannot be used. |
228 | 0 | ecx &= ~(1u << 28); // AVX |
229 | 0 | ecx &= ~(1u << 12); // FMA |
230 | 0 | ecx &= ~(1u << 11); // AMD XOP |
231 | 0 | extended_features[0] &= ~(1u << 5); // AVX2 |
232 | 0 | extended_features[1] &= ~(1u << 9); // VAES |
233 | 0 | extended_features[1] &= ~(1u << 10); // VPCLMULQDQ |
234 | 0 | } |
235 | | // See Intel manual, volume 1, sections 15.2 ("Detection of AVX-512 Foundation |
236 | | // Instructions") through 15.4 ("Detection of Intel AVX-512 Instruction Groups |
237 | | // Operating at 256 and 128-bit Vector Lengths"). |
238 | 1 | if ((xcr0 & 0xe6) != 0xe6) { |
239 | | // Without XCR0.111xx11x, no AVX512 feature can be used. This includes ZMM |
240 | | // registers, masking, SIMD registers 16-31 (even if accessed as YMM or |
241 | | // XMM), and EVEX-coded instructions (even on YMM or XMM). Even if only |
242 | | // XCR0.ZMM_Hi256 is missing, it isn't valid to use AVX512 features on |
243 | | // shorter vectors, since AVX512 ties everything to the availability of |
244 | | // 512-bit vectors. See the above-mentioned sections of the Intel manual, |
245 | | // which say that *all* these XCR0 bits must be checked even when just using |
246 | | // 128-bit or 256-bit vectors, and also volume 2a section 2.7.11 ("#UD |
247 | | // Equations for EVEX") which says that all EVEX-coded instructions raise an |
248 | | // undefined-instruction exception if any of these XCR0 bits is zero. |
249 | | // |
250 | | // AVX10 fixes this by reorganizing the features that used to be part of |
251 | | // "AVX512" and allowing them to be used independently of 512-bit support. |
252 | | // TODO: add AVX10 detection. |
253 | 1 | extended_features[0] &= ~(1u << 16); // AVX512F |
254 | 1 | extended_features[0] &= ~(1u << 17); // AVX512DQ |
255 | 1 | extended_features[0] &= ~(1u << 21); // AVX512IFMA |
256 | 1 | extended_features[0] &= ~(1u << 26); // AVX512PF |
257 | 1 | extended_features[0] &= ~(1u << 27); // AVX512ER |
258 | 1 | extended_features[0] &= ~(1u << 28); // AVX512CD |
259 | 1 | extended_features[0] &= ~(1u << 30); // AVX512BW |
260 | 1 | extended_features[0] &= ~(1u << 31); // AVX512VL |
261 | 1 | extended_features[1] &= ~(1u << 1); // AVX512VBMI |
262 | 1 | extended_features[1] &= ~(1u << 6); // AVX512VBMI2 |
263 | 1 | extended_features[1] &= ~(1u << 11); // AVX512VNNI |
264 | 1 | extended_features[1] &= ~(1u << 12); // AVX512BITALG |
265 | 1 | extended_features[1] &= ~(1u << 14); // AVX512VPOPCNTDQ |
266 | 1 | } |
267 | | |
268 | | // Repurpose the bit for the removed MPX feature to indicate when using zmm |
269 | | // registers should be avoided even when they are supported. (When set, AVX512 |
270 | | // features can still be used, but only using ymm or xmm registers.) Skylake |
271 | | // suffered from severe downclocking when zmm registers were used, which |
272 | | // affected unrelated code running on the system, making zmm registers not too |
273 | | // useful outside of benchmarks. The situation improved significantly by Ice |
274 | | // Lake, but a small amount of downclocking remained. (See |
275 | | // https://lore.kernel.org/linux-crypto/e8ce1146-3952-6977-1d0e-a22758e58914@intel.com/) |
276 | | // We take a conservative approach of not allowing zmm registers until after |
277 | | // Ice Lake and Tiger Lake, i.e. until Sapphire Rapids on the server side. |
278 | | // |
279 | | // AMD CPUs, which support AVX512 starting with Zen 4, have not been reported |
280 | | // to have any downclocking problem when zmm registers are used. |
281 | 1 | if (is_intel && family == 6 && |
282 | 1 | (model == 85 || // Skylake, Cascade Lake, Cooper Lake (server) |
283 | 0 | model == 106 || // Ice Lake (server) |
284 | 0 | model == 108 || // Ice Lake (micro server) |
285 | 0 | model == 125 || // Ice Lake (client) |
286 | 0 | model == 126 || // Ice Lake (mobile) |
287 | 0 | model == 140 || // Tiger Lake (mobile) |
288 | 0 | model == 141)) { // Tiger Lake (client) |
289 | 0 | extended_features[0] |= 1u << 14; |
290 | 1 | } else { |
291 | 1 | extended_features[0] &= ~(1u << 14); |
292 | 1 | } |
293 | | |
294 | 1 | OPENSSL_ia32cap_P[0] = edx; |
295 | 1 | OPENSSL_ia32cap_P[1] = ecx; |
296 | 1 | OPENSSL_ia32cap_P[2] = extended_features[0]; |
297 | 1 | OPENSSL_ia32cap_P[3] = extended_features[1]; |
298 | | |
299 | 1 | const char *env1, *env2; |
300 | 1 | env1 = getenv("OPENSSL_ia32cap"); |
301 | 1 | if (env1 == NULL) { |
302 | 1 | return; |
303 | 1 | } |
304 | | |
305 | | // OPENSSL_ia32cap can contain zero, one or two values, separated with a ':'. |
306 | | // Each value is a 64-bit, unsigned value which may start with "0x" to |
307 | | // indicate a hex value. Prior to the 64-bit value, a '~' or '|' may be given. |
308 | | // |
309 | | // If the '~' prefix is present: |
310 | | // the value is inverted and ANDed with the probed CPUID result |
311 | | // If the '|' prefix is present: |
312 | | // the value is ORed with the probed CPUID result |
313 | | // Otherwise: |
314 | | // the value is taken as the result of the CPUID |
315 | | // |
316 | | // The first value determines OPENSSL_ia32cap_P[0] and [1]. The second [2] |
317 | | // and [3]. |
318 | | |
319 | 0 | handle_cpu_env(&OPENSSL_ia32cap_P[0], env1); |
320 | 0 | env2 = strchr(env1, ':'); |
321 | 0 | if (env2 != NULL) { |
322 | 0 | handle_cpu_env(&OPENSSL_ia32cap_P[2], env2 + 1); |
323 | 0 | } |
324 | 0 | } |
325 | | |
326 | | #endif // !OPENSSL_NO_ASM && (OPENSSL_X86 || OPENSSL_X86_64) |