Coverage Report

Created: 2026-06-16 07:20

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/vvdec/source/Lib/CommonLib/x86/InitX86.cpp
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Source
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/* -----------------------------------------------------------------------------
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The copyright in this software is being made available under the Clear BSD
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License, included below. No patent rights, trademark rights and/or 
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other Intellectual Property Rights other than the copyrights concerning 
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the Software are granted under this license.
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The Clear BSD License
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Copyright (c) 2018-2026, Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. & The VVdeC Authors.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted (subject to the limitations in the disclaimer below) provided that
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the following conditions are met:
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     * Redistributions of source code must retain the above copyright notice,
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     this list of conditions and the following disclaimer.
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     * Redistributions in binary form must reproduce the above copyright
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     notice, this list of conditions and the following disclaimer in the
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     documentation and/or other materials provided with the distribution.
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     * Neither the name of the copyright holder nor the names of its
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     contributors may be used to endorse or promote products derived from this
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     software without specific prior written permission.
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NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY
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THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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------------------------------------------------------------------------------------------- */
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/*
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 * \ingroup CommonLib
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 * \file    InitX86.cpp
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 * \brief   Initialize encoder SIMD functions.
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 */
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#include "CommonDefX86.h"
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#include "CommonLib/CommonDef.h"
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#include "CommonLib/InterPrediction.h"
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#include "CommonLib/InterpolationFilter.h"
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#include "CommonLib/TrQuant.h"
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#include "CommonLib/RdCost.h"
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#include "CommonLib/Buffer.h"
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#include "CommonLib/TrQuant_EMT.h"
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#include "CommonLib/IntraPrediction.h"
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#include "CommonLib/LoopFilter.h"
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#include "CommonLib/Picture.h"
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#include "CommonLib/AdaptiveLoopFilter.h"
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#include "CommonLib/SampleAdaptiveOffset.h"
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namespace vvdec
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{
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#ifdef TARGET_SIMD_X86
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#  if defined( REAL_TARGET_X86 ) \
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    || ( defined( SIMD_EVERYWHERE_EXTENSION_LEVEL_ID ) && SIMD_EVERYWHERE_EXTENSION_LEVEL_ID >= X86_SIMD_AVX2 )
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#    define ENABLE_AVX2_IMPLEMENTATIONS 1
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#  else
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#    define ENABLE_AVX2_IMPLEMENTATIONS 0
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#  endif
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#if ENABLE_SIMD_OPT_MCIF
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void InterpolationFilter::initInterpolationFilterX86( /*int iBitDepthY, int iBitDepthC*/ )
80
22.8k
{
81
22.8k
  auto vext = read_x86_extension_flags();
82
22.8k
  switch (vext){
83
0
  case AVX512:
84
22.8k
  case AVX2:
85
22.8k
#if ENABLE_AVX2_IMPLEMENTATIONS
86
22.8k
    _initInterpolationFilterX86<AVX2>(/*iBitDepthY, iBitDepthC*/);
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22.8k
    break;
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0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
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0
  case AVX:
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0
  case SSE42:
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0
  case SSE41:
92
0
    _initInterpolationFilterX86<SSE41>(/*iBitDepthY, iBitDepthC*/);
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0
    break;
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0
  default:
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0
    break;
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22.8k
  }
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22.8k
}
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#endif
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#if ENABLE_SIMD_OPT_BUFFER
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void PelBufferOps::initPelBufOpsX86()
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5.61k
{
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5.61k
  auto vext = read_x86_extension_flags();
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5.61k
  switch (vext){
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0
    case AVX512:
106
5.61k
    case AVX2:
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5.61k
#if ENABLE_AVX2_IMPLEMENTATIONS
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5.61k
      _initPelBufOpsX86<AVX2>();
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5.61k
      break;
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0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
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0
    case AVX:
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0
    case SSE42:
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0
    case SSE41:
114
0
      _initPelBufOpsX86<SSE41>();
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0
      break;
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0
    default:
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0
      break;
118
5.61k
  }
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5.61k
}
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#endif
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#if ENABLE_SIMD_OPT_DIST
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void RdCost::initRdCostX86()
124
5.61k
{
125
5.61k
  auto vext = read_x86_extension_flags();
126
5.61k
  switch (vext){
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0
    case AVX512:
128
5.61k
    case AVX2:
129
5.61k
#if ENABLE_AVX2_IMPLEMENTATIONS
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5.61k
#if !(defined(_MSC_VER) && _MSC_VER >= 1938 && _MSC_VER < 1939) // workaround for buggy msvc versions
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5.61k
      _initRdCostX86<AVX2>();
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5.61k
      break;
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0
#endif
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0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
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0
    case AVX:
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0
    case SSE42:
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0
    case SSE41:
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0
      _initRdCostX86<SSE41>();
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0
      break;
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0
    default:
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0
      break;
142
5.61k
  }
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5.61k
}
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#endif
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#if ENABLE_SIMD_OPT_ALF
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void AdaptiveLoopFilter::initAdaptiveLoopFilterX86()
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5.61k
{
149
5.61k
  auto vext = read_x86_extension_flags();
150
5.61k
  switch ( vext )
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5.61k
  {
152
0
  case AVX512:
153
5.61k
  case AVX2:
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5.61k
#if ENABLE_AVX2_IMPLEMENTATIONS
155
5.61k
    _initAdaptiveLoopFilterX86<AVX2>();
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5.61k
    break;
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0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
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0
  case AVX:
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0
  case SSE42:
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0
  case SSE41:
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0
    _initAdaptiveLoopFilterX86<SSE41>();
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0
    break;
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0
  default:
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0
    break;
165
5.61k
  }
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5.61k
}
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#endif
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#if ENABLE_SIMD_DBLF
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void LoopFilter::initLoopFilterX86()
171
5.61k
{
172
5.61k
  auto vext = read_x86_extension_flags();
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5.61k
  switch ( vext )
174
5.61k
  {
175
0
  case AVX512:
176
5.61k
  case AVX2:
177
5.61k
#if ENABLE_AVX2_IMPLEMENTATIONS
178
5.61k
    _initLoopFilterX86<AVX2>();
179
5.61k
    break;
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0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
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0
  case AVX:
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0
  case SSE42:
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0
  case SSE41:
184
0
    _initLoopFilterX86<SSE41>();
185
0
    break;
186
0
  default:
187
0
    break;
188
5.61k
  }
189
5.61k
}
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#endif
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192
#if ENABLE_SIMD_TCOEFF_OPS
193
void TCoeffOps::initTCoeffOpsX86()
194
5.61k
{
195
5.61k
  auto vext = read_x86_extension_flags();
196
197
5.61k
  switch( vext )
198
5.61k
  {
199
0
  case AVX512:
200
5.61k
  case AVX2:
201
5.61k
#if ENABLE_AVX2_IMPLEMENTATIONS
202
5.61k
    _initTCoeffOpsX86<AVX2>();
203
5.61k
    break;
204
0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
205
0
  case AVX:
206
0
  case SSE42:
207
0
  case SSE41:
208
0
    _initTCoeffOpsX86<SSE41>();
209
0
    break;
210
0
  default:
211
0
  break;
212
5.61k
  }
213
5.61k
}
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215
void TrQuant::initTrQuantX86()
216
59.8k
{
217
59.8k
  auto vext = read_x86_extension_flags();
218
219
59.8k
  switch( vext )
220
59.8k
  {
221
0
  case AVX512:
222
59.8k
  case AVX2:
223
59.8k
#if ENABLE_AVX2_IMPLEMENTATIONS
224
59.8k
    _initTrQuantX86<AVX2>();
225
59.8k
    break;
226
0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
227
0
  case AVX:
228
0
  case SSE42:
229
0
  case SSE41:
230
0
    _initTrQuantX86<SSE41>();
231
0
    break;
232
0
  default:
233
0
  break;
234
59.8k
  }
235
59.8k
}
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#endif
237
238
#if ENABLE_SIMD_OPT_INTRAPRED
239
void IntraPrediction::initIntraPredictionX86()
240
22.8k
{
241
22.8k
  auto vext = read_x86_extension_flags();
242
22.8k
  switch (vext){
243
0
    case AVX512:
244
22.8k
    case AVX2:
245
22.8k
#if ENABLE_AVX2_IMPLEMENTATIONS
246
22.8k
      _initIntraPredictionX86<AVX2>();
247
22.8k
      break;
248
0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
249
0
    case AVX:
250
0
    case SSE42:
251
0
    case SSE41:
252
0
      _initIntraPredictionX86<SSE41>();
253
0
      break;
254
0
    default:
255
0
      break;
256
22.8k
  }
257
258
22.8k
}
259
260
#endif
261
#if ENABLE_SIMD_OPT_SAO
262
void SampleAdaptiveOffset::initSampleAdaptiveOffsetX86()
263
5.61k
{
264
5.61k
  auto vext = read_x86_extension_flags();
265
5.61k
  switch (vext){
266
0
    case AVX512:
267
5.61k
    case AVX2:
268
5.61k
#if ENABLE_AVX2_IMPLEMENTATIONS
269
5.61k
      _initSampleAdaptiveOffsetX86<AVX2>();
270
5.61k
      break;
271
0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
272
0
    case AVX:
273
0
    case SSE42:
274
0
    case SSE41:
275
0
      _initSampleAdaptiveOffsetX86<SSE41>();
276
0
      break;
277
0
    default:
278
0
      break;
279
5.61k
  }
280
281
5.61k
}
282
283
#endif
284
285
#if ENABLE_SIMD_OPT_INTER
286
void InterPrediction::initInterPredictionX86()
287
22.8k
{
288
22.8k
  auto vext = read_x86_extension_flags();
289
22.8k
  switch (vext){
290
0
    case AVX512:
291
22.8k
    case AVX2:
292
22.8k
#if ENABLE_AVX2_IMPLEMENTATIONS
293
22.8k
      _initInterPredictionX86<AVX2>();
294
22.8k
      break;
295
0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
296
0
    case AVX:
297
0
    case SSE42:
298
0
    case SSE41:
299
0
      _initInterPredictionX86<SSE41>();
300
0
      break;
301
0
    default:
302
0
      break;
303
22.8k
  }
304
305
22.8k
}
306
#endif
307
308
#if ENABLE_SIMD_OPT_PICTURE
309
void Picture::initPictureX86()
310
714
{
311
714
  auto vext = read_x86_extension_flags();
312
714
  switch (vext){
313
0
    case AVX512:
314
714
    case AVX2:
315
714
#if ENABLE_AVX2_IMPLEMENTATIONS
316
714
      _initPictureX86<AVX2>();
317
714
      break;
318
0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
319
0
    case AVX:
320
0
    case SSE42:
321
0
    case SSE41:
322
0
      _initPictureX86<SSE41>();
323
0
      break;
324
0
    default:
325
0
      break;
326
714
  }
327
328
714
}
329
#endif
330
331
#if ENABLE_SIMD_OPT_QUANT
332
void Quant::initQuantX86()
333
59.8k
{
334
59.8k
  auto vext = read_x86_extension_flags();
335
59.8k
  switch (vext){
336
0
    case AVX512:
337
59.8k
    case AVX2:
338
59.8k
#if ENABLE_AVX2_IMPLEMENTATIONS
339
59.8k
      _initQuantX86<AVX2>();
340
59.8k
      break;
341
0
#endif  // ENABLE_AVX2_IMPLEMENTATIONS
342
0
    case AVX:
343
0
    case SSE42:
344
0
    case SSE41:
345
0
      _initQuantX86<SSE41>();
346
0
      break;
347
0
    default:
348
0
      break;
349
59.8k
  }
350
351
59.8k
}
352
353
#endif
354
355
#endif  // TARGET_SIMD_X86
356
357
}   // namespace vvdec