Coverage Report

Created: 2025-12-20 06:48

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/rust/registry/src/index.crates.io-1949cf8c6b5b557f/pxfm-0.1.27/src/asinf.rs
Line
Count
Source
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/*
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 * // Copyright (c) Radzivon Bartoshyk 6/2025. All rights reserved.
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 * //
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 * // Redistribution and use in source and binary forms, with or without modification,
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 * // are permitted provided that the following conditions are met:
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 * //
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 * // 1.  Redistributions of source code must retain the above copyright notice, this
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 * // list of conditions and the following disclaimer.
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 * //
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 * // 2.  Redistributions in binary form must reproduce the above copyright notice,
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 * // this list of conditions and the following disclaimer in the documentation
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 * // and/or other materials provided with the distribution.
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 * //
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 * // 3.  Neither the name of the copyright holder nor the names of its
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 * // contributors may be used to endorse or promote products derived from
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 * // this software without specific prior written permission.
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 * //
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 * // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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 * // AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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 * // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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 * // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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 * // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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 * // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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 * // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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 * // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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 * // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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 * // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
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use crate::acosf::poly12;
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use crate::common::{dd_fmlaf, f_fmla};
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#[cold]
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0
fn as_special(x: f32) -> f32 {
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0
    let t = x.to_bits();
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0
    let ax = t.wrapping_shl(1);
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0
    if ax > (0xffu32 << 24) {
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0
        return x + x;
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0
    } // nan
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    f32::NAN
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0
}
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#[inline(always)]
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/// fma - fma
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/// dd_fma - mandatory fma fallback
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0
fn asinf_gen_impl<Q: Fn(f64, f64, f64) -> f64, F: Fn(f32, f32, f32) -> f32>(
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0
    x: f32,
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0
    fma: Q,
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0
    dd_fma: F,
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0
) -> f32 {
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    const PI2: f64 = f64::from_bits(0x3ff921fb54442d18);
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0
    let xs = x as f64;
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    let mut r;
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0
    let t = x.to_bits();
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0
    let ax = t.wrapping_shl(1);
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0
    if ax > 0x7f << 24 {
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0
        return as_special(x);
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0
    }
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0
    if ax < 0x7ec29000u32 {
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        // |x| < 1.49029
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0
        if ax < 115 << 24 {
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            // |x| < 0.000244141
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0
            return dd_fma(x, f64::from_bits(0x3e60000000000000) as f32, x);
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0
        }
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        const B: [u64; 16] = [
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            0x3ff0000000000005,
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            0x3fc55557aeca105d,
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            0x3fb3314ec3db7d12,
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            0x3fa775738a5a6f92,
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            0x3f75d5f7ce1c8538,
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            0x3fd605c6d58740f0,
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            0xc005728b732d73c6,
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            0x402f152170f151eb,
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            0xc04f962ea3ca992e,
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            0x40671971e17375a0,
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            0xc07860512b4ba230,
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            0x40826a3b8d4bdb14,
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            0xc0836f2ea5698b51,
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            0x407b3d722aebfa2e,
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            0xc066cf89703b1289,
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            0x4041518af6a65e2d,
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        ];
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0
        let z = xs;
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0
        let z2 = z * z;
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0
        let w0 = fma(z2, f64::from_bits(B[1]), f64::from_bits(B[0]));
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0
        let w1 = fma(z2, f64::from_bits(B[3]), f64::from_bits(B[2]));
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0
        let w2 = fma(z2, f64::from_bits(B[5]), f64::from_bits(B[4]));
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0
        let w3 = fma(z2, f64::from_bits(B[7]), f64::from_bits(B[6]));
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0
        let w4 = fma(z2, f64::from_bits(B[9]), f64::from_bits(B[8]));
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0
        let w5 = fma(z2, f64::from_bits(B[11]), f64::from_bits(B[10]));
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0
        let w6 = fma(z2, f64::from_bits(B[13]), f64::from_bits(B[12]));
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0
        let w7 = fma(z2, f64::from_bits(B[15]), f64::from_bits(B[14]));
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0
        let z4 = z2 * z2;
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0
        let z8 = z4 * z4;
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0
        let z16 = z8 * z8;
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        r = z
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0
            * ((fma(z4, w1, w0) + z8 * fma(z4, w3, w2))
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0
                + z16 * (fma(z4, w5, w4) + z8 * fma(z4, w7, w6)));
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0
        let ub = r;
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0
        let lb = r - z * f64::from_bits(0x3e0efa8eb0000000);
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        // Ziv's accuracy test
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0
        if ub == lb {
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            return ub as f32;
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0
        }
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0
    }
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0
    if ax < (0x7eu32 << 24) {
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        const C: [u64; 12] = [
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            0x3fc555555555529c,
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            0x3fb333333337e0dd,
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            0x3fa6db6db3b4465e,
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            0x3f9f1c72e13ac306,
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            0x3f96e89cebe06bc4,
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            0x3f91c6dcf5289094,
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            0x3f8c6dbbcc7c6315,
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            0x3f88f8dc2615e996,
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            0x3f7a5833b7bf15e8,
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            0x3f943f44ace1665c,
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            0xbf90fb17df881c73,
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            0x3fa07520c026b2d6,
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        ];
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0
        let z = xs;
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0
        let z2 = z * z;
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0
        let c0 = poly12(z2, C, &fma);
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0
        r = z + (z * z2) * c0;
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    } else {
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0
        if ax == 0x7e55688au32 {
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0
            return f32::copysign(f64::from_bits(0x3fe75b8a20000000) as f32, x)
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0
                + f32::copysign(f64::from_bits(0x3e50000000000000) as f32, x);
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0
        }
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0
        if ax == 0x7e107434u32 {
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0
            return f32::copysign(f64::from_bits(0x3fe1f4b640000000) as f32, x)
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0
                + f32::copysign(f64::from_bits(0x3e50000000000000) as f32, x);
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0
        }
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0
        let bx = xs.abs();
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0
        let z = 1.0 - bx;
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0
        let s = z.sqrt();
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        const C: [u64; 12] = [
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            0x3ff6a09e667f3bcb,
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            0x3fbe2b7dddff2db9,
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            0x3f9b27247ab42dbc,
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            0x3f802995cc4e0744,
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            0x3f65ffb0276ec8ea,
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            0x3f5033885a928dec,
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            0x3f3911f2be23f8c7,
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            0x3f24c3c55d2437fd,
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            0x3f0af477e1d7b461,
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            0x3f0abd6bdff67dcb,
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            0xbef1717e86d0fa28,
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            0x3ef6ff526de46023,
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        ];
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0
        r = PI2 - s * poly12(z, C, &fma);
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0
        r = f64::copysign(r, xs);
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    }
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0
    r as f32
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0
}
Unexecuted instantiation: pxfm::asinf::asinf_gen_impl::<<f64>::mul_add, <f32>::mul_add>
Unexecuted instantiation: pxfm::asinf::asinf_gen_impl::<pxfm::common::f_fmla, pxfm::common::dd_fmlaf>
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#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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#[target_feature(enable = "avx", enable = "fma")]
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0
unsafe fn asinf_fma_impl(x: f32) -> f32 {
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0
    asinf_gen_impl(x, f64::mul_add, f32::mul_add)
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0
}
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/// Computes asin
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///
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/// Max found ULP 0.49999928
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#[inline]
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0
pub fn f_asinf(x: f32) -> f32 {
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    #[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
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    {
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        asinf_gen_impl(x, f_fmla, dd_fmlaf)
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    }
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    #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
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    {
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        use std::sync::OnceLock;
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        static EXECUTOR: OnceLock<unsafe fn(f32) -> f32> = OnceLock::new();
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0
        let q = EXECUTOR.get_or_init(|| {
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0
            if std::arch::is_x86_feature_detected!("avx")
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0
                && std::arch::is_x86_feature_detected!("fma")
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            {
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0
                asinf_fma_impl
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            } else {
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0
                fn def_asinf(x: f32) -> f32 {
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0
                    asinf_gen_impl(x, f_fmla, dd_fmlaf)
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0
                }
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                def_asinf
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            }
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0
        });
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        unsafe { q(x) }
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    }
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0
}
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#[cfg(test)]
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mod tests {
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    use super::*;
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    #[test]
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    fn test_asinf() {
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        assert_eq!(f_asinf(-0.5), -std::f32::consts::FRAC_PI_6);
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        assert_eq!(f_asinf(0.5), std::f32::consts::FRAC_PI_6);
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        assert!(f_asinf(7.).is_nan());
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    }
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}