/src/keystone/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h
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1 | | //===-- MipsMCCodeEmitter.h - Convert Mips Code to Machine Code -----------===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file defines the MipsMCCodeEmitter class. |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | // |
14 | | |
15 | | #ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H |
16 | | #define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSMCCODEEMITTER_H |
17 | | |
18 | | #include "llvm/MC/MCCodeEmitter.h" |
19 | | #include "llvm/Support/DataTypes.h" |
20 | | |
21 | | using namespace llvm_ks; |
22 | | |
23 | | namespace llvm_ks { |
24 | | class MCContext; |
25 | | class MCExpr; |
26 | | class MCInst; |
27 | | class MCInstrInfo; |
28 | | class MCFixup; |
29 | | class MCOperand; |
30 | | class MCSubtargetInfo; |
31 | | class raw_ostream; |
32 | | |
33 | | class MipsMCCodeEmitter : public MCCodeEmitter { |
34 | | MipsMCCodeEmitter(const MipsMCCodeEmitter &) = delete; |
35 | | void operator=(const MipsMCCodeEmitter &) = delete; |
36 | | const MCInstrInfo &MCII; |
37 | | MCContext &Ctx; |
38 | | bool IsLittleEndian; |
39 | | |
40 | | bool isMicroMips(const MCSubtargetInfo &STI) const; |
41 | | bool isMips32r6(const MCSubtargetInfo &STI) const; |
42 | | |
43 | | public: |
44 | | MipsMCCodeEmitter(const MCInstrInfo &mcii, MCContext &Ctx_, bool IsLittle) |
45 | 5.15k | : MCII(mcii), Ctx(Ctx_), IsLittleEndian(IsLittle) {} |
46 | | |
47 | 0 | ~MipsMCCodeEmitter() override {} |
48 | | |
49 | | void EmitByte(unsigned char C, raw_ostream &OS) const; |
50 | | |
51 | | void EmitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI, |
52 | | raw_ostream &OS) const; |
53 | | |
54 | | void encodeInstruction(MCInst &MI, raw_ostream &OS, |
55 | | SmallVectorImpl<MCFixup> &Fixups, |
56 | | const MCSubtargetInfo &STI, |
57 | | unsigned int &KsError) const override; |
58 | | |
59 | | // getBinaryCodeForInstr - TableGen'erated function for getting the |
60 | | // binary encoding for an instruction. |
61 | | uint64_t getBinaryCodeForInstr(const MCInst &MI, |
62 | | SmallVectorImpl<MCFixup> &Fixups, |
63 | | const MCSubtargetInfo &STI) const; |
64 | | |
65 | | // getJumpTargetOpValue - Return binary encoding of the jump |
66 | | // target operand. If the machine operand requires relocation, |
67 | | // record the relocation and return zero. |
68 | | unsigned getJumpTargetOpValue(const MCInst &MI, unsigned OpNo, |
69 | | SmallVectorImpl<MCFixup> &Fixups, |
70 | | const MCSubtargetInfo &STI) const; |
71 | | |
72 | | // getBranchJumpOpValueMM - Return binary encoding of the microMIPS jump |
73 | | // target operand. If the machine operand requires relocation, |
74 | | // record the relocation and return zero. |
75 | | unsigned getJumpTargetOpValueMM(const MCInst &MI, unsigned OpNo, |
76 | | SmallVectorImpl<MCFixup> &Fixups, |
77 | | const MCSubtargetInfo &STI) const; |
78 | | |
79 | | // getUImm5Lsl2Encoding - Return binary encoding of the microMIPS jump |
80 | | // target operand. |
81 | | unsigned getUImm5Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
82 | | SmallVectorImpl<MCFixup> &Fixups, |
83 | | const MCSubtargetInfo &STI) const; |
84 | | |
85 | | unsigned getSImm3Lsa2Value(const MCInst &MI, unsigned OpNo, |
86 | | SmallVectorImpl<MCFixup> &Fixups, |
87 | | const MCSubtargetInfo &STI) const; |
88 | | |
89 | | unsigned getUImm6Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
90 | | SmallVectorImpl<MCFixup> &Fixups, |
91 | | const MCSubtargetInfo &STI) const; |
92 | | |
93 | | // getSImm9AddiuspValue - Return binary encoding of the microMIPS addiusp |
94 | | // instruction immediate operand. |
95 | | unsigned getSImm9AddiuspValue(const MCInst &MI, unsigned OpNo, |
96 | | SmallVectorImpl<MCFixup> &Fixups, |
97 | | const MCSubtargetInfo &STI) const; |
98 | | |
99 | | // getBranchTargetOpValue - Return binary encoding of the branch |
100 | | // target operand. If the machine operand requires relocation, |
101 | | // record the relocation and return zero. |
102 | | unsigned getBranchTargetOpValue(const MCInst &MI, unsigned OpNo, |
103 | | SmallVectorImpl<MCFixup> &Fixups, |
104 | | const MCSubtargetInfo &STI) const; |
105 | | |
106 | | // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch |
107 | | // target operand. If the machine operand requires relocation, |
108 | | // record the relocation and return zero. |
109 | | unsigned getBranchTarget7OpValueMM(const MCInst &MI, unsigned OpNo, |
110 | | SmallVectorImpl<MCFixup> &Fixups, |
111 | | const MCSubtargetInfo &STI) const; |
112 | | |
113 | | // getBranchTargetOpValueMMPC10 - Return binary encoding of the microMIPS |
114 | | // 10-bit branch target operand. If the machine operand requires relocation, |
115 | | // record the relocation and return zero. |
116 | | unsigned getBranchTargetOpValueMMPC10(const MCInst &MI, unsigned OpNo, |
117 | | SmallVectorImpl<MCFixup> &Fixups, |
118 | | const MCSubtargetInfo &STI) const; |
119 | | |
120 | | // getBranchTargetOpValue - Return binary encoding of the microMIPS branch |
121 | | // target operand. If the machine operand requires relocation, |
122 | | // record the relocation and return zero. |
123 | | unsigned getBranchTargetOpValueMM(const MCInst &MI, unsigned OpNo, |
124 | | SmallVectorImpl<MCFixup> &Fixups, |
125 | | const MCSubtargetInfo &STI) const; |
126 | | |
127 | | // getBranchTarget21OpValue - Return binary encoding of the branch |
128 | | // offset operand. If the machine operand requires relocation, |
129 | | // record the relocation and return zero. |
130 | | unsigned getBranchTarget21OpValue(const MCInst &MI, unsigned OpNo, |
131 | | SmallVectorImpl<MCFixup> &Fixups, |
132 | | const MCSubtargetInfo &STI) const; |
133 | | |
134 | | // getBranchTarget26OpValue - Return binary encoding of the branch |
135 | | // offset operand. If the machine operand requires relocation, |
136 | | // record the relocation and return zero. |
137 | | unsigned getBranchTarget26OpValue(const MCInst &MI, unsigned OpNo, |
138 | | SmallVectorImpl<MCFixup> &Fixups, |
139 | | const MCSubtargetInfo &STI) const; |
140 | | |
141 | | // getBranchTarget26OpValueMM - Return binary encoding of the branch |
142 | | // offset operand. If the machine operand requires relocation, |
143 | | // record the relocation and return zero. |
144 | | unsigned getBranchTarget26OpValueMM(const MCInst &MI, unsigned OpNo, |
145 | | SmallVectorImpl<MCFixup> &Fixups, |
146 | | const MCSubtargetInfo &STI) const; |
147 | | |
148 | | // getJumpOffset16OpValue - Return binary encoding of the jump |
149 | | // offset operand. If the machine operand requires relocation, |
150 | | // record the relocation and return zero. |
151 | | unsigned getJumpOffset16OpValue(const MCInst &MI, unsigned OpNo, |
152 | | SmallVectorImpl<MCFixup> &Fixups, |
153 | | const MCSubtargetInfo &STI) const; |
154 | | |
155 | | // getMachineOpValue - Return binary encoding of operand. If the machin |
156 | | // operand requires relocation, record the relocation and return zero. |
157 | | unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, |
158 | | SmallVectorImpl<MCFixup> &Fixups, |
159 | | const MCSubtargetInfo &STI) const; |
160 | | |
161 | | unsigned getMSAMemEncoding(const MCInst &MI, unsigned OpNo, |
162 | | SmallVectorImpl<MCFixup> &Fixups, |
163 | | const MCSubtargetInfo &STI) const; |
164 | | |
165 | | unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, |
166 | | SmallVectorImpl<MCFixup> &Fixups, |
167 | | const MCSubtargetInfo &STI) const; |
168 | | unsigned getMemEncodingMMImm4(const MCInst &MI, unsigned OpNo, |
169 | | SmallVectorImpl<MCFixup> &Fixups, |
170 | | const MCSubtargetInfo &STI) const; |
171 | | unsigned getMemEncodingMMImm4Lsl1(const MCInst &MI, unsigned OpNo, |
172 | | SmallVectorImpl<MCFixup> &Fixups, |
173 | | const MCSubtargetInfo &STI) const; |
174 | | unsigned getMemEncodingMMImm4Lsl2(const MCInst &MI, unsigned OpNo, |
175 | | SmallVectorImpl<MCFixup> &Fixups, |
176 | | const MCSubtargetInfo &STI) const; |
177 | | unsigned getMemEncodingMMSPImm5Lsl2(const MCInst &MI, unsigned OpNo, |
178 | | SmallVectorImpl<MCFixup> &Fixups, |
179 | | const MCSubtargetInfo &STI) const; |
180 | | unsigned getMemEncodingMMGPImm7Lsl2(const MCInst &MI, unsigned OpNo, |
181 | | SmallVectorImpl<MCFixup> &Fixups, |
182 | | const MCSubtargetInfo &STI) const; |
183 | | unsigned getMemEncodingMMImm9(const MCInst &MI, unsigned OpNo, |
184 | | SmallVectorImpl<MCFixup> &Fixups, |
185 | | const MCSubtargetInfo &STI) const; |
186 | | unsigned getMemEncodingMMImm12(const MCInst &MI, unsigned OpNo, |
187 | | SmallVectorImpl<MCFixup> &Fixups, |
188 | | const MCSubtargetInfo &STI) const; |
189 | | unsigned getMemEncodingMMImm16(const MCInst &MI, unsigned OpNo, |
190 | | SmallVectorImpl<MCFixup> &Fixups, |
191 | | const MCSubtargetInfo &STI) const; |
192 | | unsigned getMemEncodingMMImm4sp(const MCInst &MI, unsigned OpNo, |
193 | | SmallVectorImpl<MCFixup> &Fixups, |
194 | | const MCSubtargetInfo &STI) const; |
195 | | unsigned getSizeInsEncoding(const MCInst &MI, unsigned OpNo, |
196 | | SmallVectorImpl<MCFixup> &Fixups, |
197 | | const MCSubtargetInfo &STI) const; |
198 | | |
199 | | /// Subtract Offset then encode as a N-bit unsigned integer. |
200 | | template <unsigned Bits, int Offset> |
201 | | unsigned getUImmWithOffsetEncoding(const MCInst &MI, unsigned OpNo, |
202 | | SmallVectorImpl<MCFixup> &Fixups, |
203 | | const MCSubtargetInfo &STI) const; |
204 | | |
205 | | unsigned getSimm19Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
206 | | SmallVectorImpl<MCFixup> &Fixups, |
207 | | const MCSubtargetInfo &STI) const; |
208 | | |
209 | | unsigned getSimm18Lsl3Encoding(const MCInst &MI, unsigned OpNo, |
210 | | SmallVectorImpl<MCFixup> &Fixups, |
211 | | const MCSubtargetInfo &STI) const; |
212 | | |
213 | | unsigned getUImm3Mod8Encoding(const MCInst &MI, unsigned OpNo, |
214 | | SmallVectorImpl<MCFixup> &Fixups, |
215 | | const MCSubtargetInfo &STI) const; |
216 | | unsigned getUImm4AndValue(const MCInst &MI, unsigned OpNo, |
217 | | SmallVectorImpl<MCFixup> &Fixups, |
218 | | const MCSubtargetInfo &STI) const; |
219 | | |
220 | | unsigned getRegisterPairOpValue(const MCInst &MI, unsigned OpNo, |
221 | | SmallVectorImpl<MCFixup> &Fixups, |
222 | | const MCSubtargetInfo &STI) const; |
223 | | |
224 | | unsigned getMovePRegPairOpValue(const MCInst &MI, unsigned OpNo, |
225 | | SmallVectorImpl<MCFixup> &Fixups, |
226 | | const MCSubtargetInfo &STI) const; |
227 | | |
228 | | unsigned getSimm23Lsl2Encoding(const MCInst &MI, unsigned OpNo, |
229 | | SmallVectorImpl<MCFixup> &Fixups, |
230 | | const MCSubtargetInfo &STI) const; |
231 | | |
232 | | unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, |
233 | | const MCSubtargetInfo &STI) const; |
234 | | |
235 | | unsigned getRegisterListOpValue(const MCInst &MI, unsigned OpNo, |
236 | | SmallVectorImpl<MCFixup> &Fixups, |
237 | | const MCSubtargetInfo &STI) const; |
238 | | |
239 | | unsigned getRegisterListOpValue16(const MCInst &MI, unsigned OpNo, |
240 | | SmallVectorImpl<MCFixup> &Fixups, |
241 | | const MCSubtargetInfo &STI) const; |
242 | | }; // class MipsMCCodeEmitter |
243 | | } // namespace llvm_ks. |
244 | | |
245 | | #endif |