/src/keystone/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

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//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone enum definitions for the RISCV target
// useful for the compiler back-end and the MC libraries.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H

#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/MC/SubtargetFeature.h"

namespace llvm_ks {

// RISCVII - This namespace holds all of the target specific flags that
// instruction info tracks. All definitions must match RISCVInstrFormats.td.
namespace RISCVII {
enum {
  InstFormatPseudo = 0,
  InstFormatR = 1,
  InstFormatR4 = 2,
  InstFormatI = 3,
  InstFormatS = 4,
  InstFormatB = 5,
  InstFormatU = 6,
  InstFormatJ = 7,
  InstFormatCR = 8,
  InstFormatCI = 9,
  InstFormatCSS = 10,
  InstFormatCIW = 11,
  InstFormatCL = 12,
  InstFormatCS = 13,
  InstFormatCA = 14,
  InstFormatCB = 15,
  InstFormatCJ = 16,
  InstFormatOther = 17,

  InstFormatMask = 31
};

enum {
  MO_None,
  MO_CALL,
  MO_PLT,
  MO_LO,
  MO_HI,
  MO_PCREL_LO,
  MO_PCREL_HI,
  MO_GOT_HI,
  MO_TPREL_LO,
  MO_TPREL_HI,
  MO_TPREL_ADD,
  MO_TLS_GOT_HI,
  MO_TLS_GD_HI,
};
} // namespace RISCVII

// Describes the predecessor/successor bits used in the FENCE instruction.
namespace RISCVFenceField {
enum FenceField {
  I = 8,
  O = 4,
  R = 2,
  W = 1
};
}

// Describes the supported floating point rounding mode encodings.
namespace RISCVFPRndMode {
enum RoundingMode {
  RNE = 0,
  RTZ = 1,
  RDN = 2,
  RUP = 3,
  RMM = 4,
  DYN = 7,
  Invalid
};

inline static StringRef roundingModeToString(RoundingMode RndMode) {
  switch (RndMode) {
  default:
    llvm_unreachable("Unknown floating point rounding mode");
  case RISCVFPRndMode::RNE:
    return "rne";
  case RISCVFPRndMode::RTZ:
    return "rtz";
  case RISCVFPRndMode::RDN:
    return "rdn";
  case RISCVFPRndMode::RUP:
    return "rup";
  case RISCVFPRndMode::RMM:
    return "rmm";
  case RISCVFPRndMode::DYN:
    return "dyn";
  }
}

inline static RoundingMode stringToRoundingMode(StringRef Str) {
  return StringSwitch<RoundingMode>(Str)
      .Case("rne", RISCVFPRndMode::RNE)
      .Case("rtz", RISCVFPRndMode::RTZ)
      .Case("rdn", RISCVFPRndMode::RDN)
      .Case("rup", RISCVFPRndMode::RUP)
      .Case("rmm", RISCVFPRndMode::RMM)
      .Case("dyn", RISCVFPRndMode::DYN)
      .Default(RISCVFPRndMode::Invalid);
}

inline static bool isValidRoundingMode(unsigned Mode) {
  switch (Mode) {
  default:
    return false;
  case RISCVFPRndMode::RNE:
  case RISCVFPRndMode::RTZ:
  case RISCVFPRndMode::RDN:
  case RISCVFPRndMode::RUP:
  case RISCVFPRndMode::RMM:
  case RISCVFPRndMode::DYN:
    return true;
  }
}
} // namespace RISCVFPRndMode

namespace RISCVSysReg {
struct SysReg {
  const char *Name;
  unsigned Encoding;
  // FIXME: add these additional fields when needed.
  // Privilege Access: Read, Write, Read-Only.
  // unsigned ReadWrite;
  // Privilege Mode: User, System or Machine.
  // unsigned Mode;
  // Check field name.
  // unsigned Extra;
  // Register number without the privilege bits.
  // unsigned Number;
  FeatureBitset FeaturesRequired;
  bool isRV32Only;

  bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
    // Not in 32-bit mode.
    if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
      return false;
    // No required feature associated with the system register.
    if (FeaturesRequired.none())
      return true;
    return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
  }
};

#define GET_SysRegsList_DECL
#include "RISCVGenSystemOperands.inc"
} // end namespace RISCVSysReg

namespace RISCVABI {

enum ABI {
  ABI_ILP32,
  ABI_ILP32F,
  ABI_ILP32D,
  ABI_ILP32E,
  ABI_LP64,
  ABI_LP64F,
  ABI_LP64D,
  ABI_Unknown
};

// Returns the target ABI, or else a StringError if the requested ABIName is
// not supported for the given TT and FeatureBits combination.
ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
                     StringRef ABIName);

} // namespace RISCVABI

namespace RISCVFeatures {

// Validates if the given combination of features are valid for the target
// triple. Exits with report_fatal_error if not.
void validate(const Triple &TT, const FeatureBitset &FeatureBits);

} // namespace RISCVFeatures

} // namespace llvm_ks

#endif

Line	Count	Source (jump to first uncovered line)
1		//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----- C++ --===//
2		//
3		// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4		// See https://llvm.org/LICENSE.txt for license information.
5		// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6		//
7		//===----------------------------------------------------------------------===//
8		//
9		// This file contains small standalone enum definitions for the RISCV target
10		// useful for the compiler back-end and the MC libraries.
11		//
12		//===----------------------------------------------------------------------===//
13		#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
14		#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
15
16		#include "MCTargetDesc/RISCVMCTargetDesc.h"
17		#include "llvm/ADT/StringRef.h"
18		#include "llvm/ADT/StringSwitch.h"
19		#include "llvm/MC/SubtargetFeature.h"
20
21		namespace llvm_ks {
22
23		// RISCVII - This namespace holds all of the target specific flags that
24		// instruction info tracks. All definitions must match RISCVInstrFormats.td.
25		namespace RISCVII {
26		enum {
27		InstFormatPseudo = 0,
28		InstFormatR = 1,
29		InstFormatR4 = 2,
30		InstFormatI = 3,
31		InstFormatS = 4,
32		InstFormatB = 5,
33		InstFormatU = 6,
34		InstFormatJ = 7,
35		InstFormatCR = 8,
36		InstFormatCI = 9,
37		InstFormatCSS = 10,
38		InstFormatCIW = 11,
39		InstFormatCL = 12,
40		InstFormatCS = 13,
41		InstFormatCA = 14,
42		InstFormatCB = 15,
43		InstFormatCJ = 16,
44		InstFormatOther = 17,
45
46		InstFormatMask = 31
47		};
48
49		enum {
50		MO_None,
51		MO_CALL,
52		MO_PLT,
53		MO_LO,
54		MO_HI,
55		MO_PCREL_LO,
56		MO_PCREL_HI,
57		MO_GOT_HI,
58		MO_TPREL_LO,
59		MO_TPREL_HI,
60		MO_TPREL_ADD,
61		MO_TLS_GOT_HI,
62		MO_TLS_GD_HI,
63		};
64		} // namespace RISCVII
65
66		// Describes the predecessor/successor bits used in the FENCE instruction.
67		namespace RISCVFenceField {
68		enum FenceField {
69		I = 8,
70		O = 4,
71		R = 2,
72		W = 1
73		};
74		}
75
76		// Describes the supported floating point rounding mode encodings.
77		namespace RISCVFPRndMode {
78		enum RoundingMode {
79		RNE = 0,
80		RTZ = 1,
81		RDN = 2,
82		RUP = 3,
83		RMM = 4,
84		DYN = 7,
85		Invalid
86		};
87
88	0	inline static StringRef roundingModeToString(RoundingMode RndMode) {
89	0	switch (RndMode) {
90	0	default:
91	0	llvm_unreachable("Unknown floating point rounding mode");
92	0	case RISCVFPRndMode::RNE:
93	0	return "rne";
94	0	case RISCVFPRndMode::RTZ:
95	0	return "rtz";
96	0	case RISCVFPRndMode::RDN:
97	0	return "rdn";
98	0	case RISCVFPRndMode::RUP:
99	0	return "rup";
100	0	case RISCVFPRndMode::RMM:
101	0	return "rmm";
102	0	case RISCVFPRndMode::DYN:
103	0	return "dyn";
104	0	}
105	0	} Unexecuted instantiation: RISCVAsmParser.cpp:llvm_ks::RISCVFPRndMode::roundingModeToString(llvm_ks::RISCVFPRndMode::RoundingMode) Unexecuted instantiation: RISCVMCExpr.cpp:llvm_ks::RISCVFPRndMode::roundingModeToString(llvm_ks::RISCVFPRndMode::RoundingMode) Unexecuted instantiation: RISCVBaseInfo.cpp:llvm_ks::RISCVFPRndMode::roundingModeToString(llvm_ks::RISCVFPRndMode::RoundingMode) Unexecuted instantiation: RISCVAsmBackend.cpp:llvm_ks::RISCVFPRndMode::roundingModeToString(llvm_ks::RISCVFPRndMode::RoundingMode) Unexecuted instantiation: RISCVELFStreamer.cpp:llvm_ks::RISCVFPRndMode::roundingModeToString(llvm_ks::RISCVFPRndMode::RoundingMode) Unexecuted instantiation: RISCVMCCodeEmitter.cpp:llvm_ks::RISCVFPRndMode::roundingModeToString(llvm_ks::RISCVFPRndMode::RoundingMode)
106
107	0	inline static RoundingMode stringToRoundingMode(StringRef Str) {
108	0	return StringSwitch<RoundingMode>(Str)
109	0	.Case("rne", RISCVFPRndMode::RNE)
110	0	.Case("rtz", RISCVFPRndMode::RTZ)
111	0	.Case("rdn", RISCVFPRndMode::RDN)
112	0	.Case("rup", RISCVFPRndMode::RUP)
113	0	.Case("rmm", RISCVFPRndMode::RMM)
114	0	.Case("dyn", RISCVFPRndMode::DYN)
115	0	.Default(RISCVFPRndMode::Invalid);
116	0	} Unexecuted instantiation: RISCVAsmParser.cpp:llvm_ks::RISCVFPRndMode::stringToRoundingMode(llvm_ks::StringRef) Unexecuted instantiation: RISCVMCExpr.cpp:llvm_ks::RISCVFPRndMode::stringToRoundingMode(llvm_ks::StringRef) Unexecuted instantiation: RISCVBaseInfo.cpp:llvm_ks::RISCVFPRndMode::stringToRoundingMode(llvm_ks::StringRef) Unexecuted instantiation: RISCVAsmBackend.cpp:llvm_ks::RISCVFPRndMode::stringToRoundingMode(llvm_ks::StringRef) Unexecuted instantiation: RISCVELFStreamer.cpp:llvm_ks::RISCVFPRndMode::stringToRoundingMode(llvm_ks::StringRef) Unexecuted instantiation: RISCVMCCodeEmitter.cpp:llvm_ks::RISCVFPRndMode::stringToRoundingMode(llvm_ks::StringRef)
117
118	0	inline static bool isValidRoundingMode(unsigned Mode) {
119	0	switch (Mode) {
120	0	default:
121	0	return false;
122	0	case RISCVFPRndMode::RNE:
123	0	case RISCVFPRndMode::RTZ:
124	0	case RISCVFPRndMode::RDN:
125	0	case RISCVFPRndMode::RUP:
126	0	case RISCVFPRndMode::RMM:
127	0	case RISCVFPRndMode::DYN:
128	0	return true;
129	0	}
130	0	} Unexecuted instantiation: RISCVAsmParser.cpp:llvm_ks::RISCVFPRndMode::isValidRoundingMode(unsigned int) Unexecuted instantiation: RISCVMCExpr.cpp:llvm_ks::RISCVFPRndMode::isValidRoundingMode(unsigned int) Unexecuted instantiation: RISCVBaseInfo.cpp:llvm_ks::RISCVFPRndMode::isValidRoundingMode(unsigned int) Unexecuted instantiation: RISCVAsmBackend.cpp:llvm_ks::RISCVFPRndMode::isValidRoundingMode(unsigned int) Unexecuted instantiation: RISCVELFStreamer.cpp:llvm_ks::RISCVFPRndMode::isValidRoundingMode(unsigned int) Unexecuted instantiation: RISCVMCCodeEmitter.cpp:llvm_ks::RISCVFPRndMode::isValidRoundingMode(unsigned int)
131		} // namespace RISCVFPRndMode
132
133		namespace RISCVSysReg {
134		struct SysReg {
135		const char *Name;
136		unsigned Encoding;
137		// FIXME: add these additional fields when needed.
138		// Privilege Access: Read, Write, Read-Only.
139		// unsigned ReadWrite;
140		// Privilege Mode: User, System or Machine.
141		// unsigned Mode;
142		// Check field name.
143		// unsigned Extra;
144		// Register number without the privilege bits.
145		// unsigned Number;
146		FeatureBitset FeaturesRequired;
147		bool isRV32Only;
148
149	1	bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const {
150		// Not in 32-bit mode.
151	1	if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit])
152	0	return false;
153		// No required feature associated with the system register.
154	1	if (FeaturesRequired.none())
155	1	return true;
156	0	return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
157	1	}
158		};
159
160		#define GET_SysRegsList_DECL
161		#include "RISCVGenSystemOperands.inc"
162		} // end namespace RISCVSysReg
163
164		namespace RISCVABI {
165
166		enum ABI {
167		ABI_ILP32,
168		ABI_ILP32F,
169		ABI_ILP32D,
170		ABI_ILP32E,
171		ABI_LP64,
172		ABI_LP64F,
173		ABI_LP64D,
174		ABI_Unknown
175		};
176
177		// Returns the target ABI, or else a StringError if the requested ABIName is
178		// not supported for the given TT and FeatureBits combination.
179		ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
180		StringRef ABIName);
181
182		} // namespace RISCVABI
183
184		namespace RISCVFeatures {
185
186		// Validates if the given combination of features are valid for the target
187		// triple. Exits with report_fatal_error if not.
188		void validate(const Triple &TT, const FeatureBitset &FeatureBits);
189
190		} // namespace RISCVFeatures
191
192		} // namespace llvm_ks
193
194		#endif

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Created: 2025-07-14 06:17