Coverage Report

Created: 2025-07-15 06:22

/src/keystone/llvm/lib/Target/Sparc/SparcGenInstrInfo.inc
Line
Count
Source
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_INSTRINFO_ENUM
11
#undef GET_INSTRINFO_ENUM
12
namespace llvm_ks {
13
14
namespace SP {
15
  enum {
16
    PHI = 0,
17
    INLINEASM = 1,
18
    CFI_INSTRUCTION = 2,
19
    EH_LABEL  = 3,
20
    GC_LABEL  = 4,
21
    KILL  = 5,
22
    EXTRACT_SUBREG  = 6,
23
    INSERT_SUBREG = 7,
24
    IMPLICIT_DEF  = 8,
25
    SUBREG_TO_REG = 9,
26
    COPY_TO_REGCLASS  = 10,
27
    DBG_VALUE = 11,
28
    REG_SEQUENCE  = 12,
29
    COPY  = 13,
30
    BUNDLE  = 14,
31
    LIFETIME_START  = 15,
32
    LIFETIME_END  = 16,
33
    STACKMAP  = 17,
34
    PATCHPOINT  = 18,
35
    LOAD_STACK_GUARD  = 19,
36
    STATEPOINT  = 20,
37
    LOCAL_ESCAPE  = 21,
38
    FAULTING_LOAD_OP  = 22,
39
    G_ADD = 23,
40
    ADDCCri = 24,
41
    ADDCCrr = 25,
42
    ADDCri  = 26,
43
    ADDCrr  = 27,
44
    ADDEri  = 28,
45
    ADDErr  = 29,
46
    ADDXC = 30,
47
    ADDXCCC = 31,
48
    ADDXri  = 32,
49
    ADDXrr  = 33,
50
    ADDri = 34,
51
    ADDrr = 35,
52
    ADJCALLSTACKDOWN  = 36,
53
    ADJCALLSTACKUP  = 37,
54
    ALIGNADDR = 38,
55
    ALIGNADDRL  = 39,
56
    ANDCCri = 40,
57
    ANDCCrr = 41,
58
    ANDNCCri  = 42,
59
    ANDNCCrr  = 43,
60
    ANDNri  = 44,
61
    ANDNrr  = 45,
62
    ANDXNrr = 46,
63
    ANDXri  = 47,
64
    ANDXrr  = 48,
65
    ANDri = 49,
66
    ANDrr = 50,
67
    ARRAY16 = 51,
68
    ARRAY32 = 52,
69
    ARRAY8  = 53,
70
    ATOMIC_LOAD_ADD_32  = 54,
71
    ATOMIC_LOAD_ADD_64  = 55,
72
    ATOMIC_LOAD_AND_32  = 56,
73
    ATOMIC_LOAD_AND_64  = 57,
74
    ATOMIC_LOAD_MAX_32  = 58,
75
    ATOMIC_LOAD_MAX_64  = 59,
76
    ATOMIC_LOAD_MIN_32  = 60,
77
    ATOMIC_LOAD_MIN_64  = 61,
78
    ATOMIC_LOAD_NAND_32 = 62,
79
    ATOMIC_LOAD_NAND_64 = 63,
80
    ATOMIC_LOAD_OR_32 = 64,
81
    ATOMIC_LOAD_OR_64 = 65,
82
    ATOMIC_LOAD_SUB_32  = 66,
83
    ATOMIC_LOAD_SUB_64  = 67,
84
    ATOMIC_LOAD_UMAX_32 = 68,
85
    ATOMIC_LOAD_UMAX_64 = 69,
86
    ATOMIC_LOAD_UMIN_32 = 70,
87
    ATOMIC_LOAD_UMIN_64 = 71,
88
    ATOMIC_LOAD_XOR_32  = 72,
89
    ATOMIC_LOAD_XOR_64  = 73,
90
    ATOMIC_SWAP_64  = 74,
91
    BA  = 75,
92
    BCOND = 76,
93
    BCONDA  = 77,
94
    BINDri  = 78,
95
    BINDrr  = 79,
96
    BMASK = 80,
97
    BPFCC = 81,
98
    BPFCCA  = 82,
99
    BPFCCANT  = 83,
100
    BPFCCNT = 84,
101
    BPGEZapn  = 85,
102
    BPGEZapt  = 86,
103
    BPGEZnapn = 87,
104
    BPGEZnapt = 88,
105
    BPGZapn = 89,
106
    BPGZapt = 90,
107
    BPGZnapn  = 91,
108
    BPGZnapt  = 92,
109
    BPICC = 93,
110
    BPICCA  = 94,
111
    BPICCANT  = 95,
112
    BPICCNT = 96,
113
    BPLEZapn  = 97,
114
    BPLEZapt  = 98,
115
    BPLEZnapn = 99,
116
    BPLEZnapt = 100,
117
    BPLZapn = 101,
118
    BPLZapt = 102,
119
    BPLZnapn  = 103,
120
    BPLZnapt  = 104,
121
    BPNZapn = 105,
122
    BPNZapt = 106,
123
    BPNZnapn  = 107,
124
    BPNZnapt  = 108,
125
    BPXCC = 109,
126
    BPXCCA  = 110,
127
    BPXCCANT  = 111,
128
    BPXCCNT = 112,
129
    BPZapn  = 113,
130
    BPZapt  = 114,
131
    BPZnapn = 115,
132
    BPZnapt = 116,
133
    BSHUFFLE  = 117,
134
    CALL  = 118,
135
    CALLri  = 119,
136
    CALLrr  = 120,
137
    CASXrr  = 121,
138
    CASrr = 122,
139
    CMASK16 = 123,
140
    CMASK32 = 124,
141
    CMASK8  = 125,
142
    CMPri = 126,
143
    CMPrr = 127,
144
    EDGE16  = 128,
145
    EDGE16L = 129,
146
    EDGE16LN  = 130,
147
    EDGE16N = 131,
148
    EDGE32  = 132,
149
    EDGE32L = 133,
150
    EDGE32LN  = 134,
151
    EDGE32N = 135,
152
    EDGE8 = 136,
153
    EDGE8L  = 137,
154
    EDGE8LN = 138,
155
    EDGE8N  = 139,
156
    FABSD = 140,
157
    FABSQ = 141,
158
    FABSS = 142,
159
    FADDD = 143,
160
    FADDQ = 144,
161
    FADDS = 145,
162
    FALIGNADATA = 146,
163
    FAND  = 147,
164
    FANDNOT1  = 148,
165
    FANDNOT1S = 149,
166
    FANDNOT2  = 150,
167
    FANDNOT2S = 151,
168
    FANDS = 152,
169
    FBCOND  = 153,
170
    FBCONDA = 154,
171
    FCHKSM16  = 155,
172
    FCMPD = 156,
173
    FCMPEQ16  = 157,
174
    FCMPEQ32  = 158,
175
    FCMPGT16  = 159,
176
    FCMPGT32  = 160,
177
    FCMPLE16  = 161,
178
    FCMPLE32  = 162,
179
    FCMPNE16  = 163,
180
    FCMPNE32  = 164,
181
    FCMPQ = 165,
182
    FCMPS = 166,
183
    FDIVD = 167,
184
    FDIVQ = 168,
185
    FDIVS = 169,
186
    FDMULQ  = 170,
187
    FDTOI = 171,
188
    FDTOQ = 172,
189
    FDTOS = 173,
190
    FDTOX = 174,
191
    FEXPAND = 175,
192
    FHADDD  = 176,
193
    FHADDS  = 177,
194
    FHSUBD  = 178,
195
    FHSUBS  = 179,
196
    FITOD = 180,
197
    FITOQ = 181,
198
    FITOS = 182,
199
    FLCMPD  = 183,
200
    FLCMPS  = 184,
201
    FLUSH = 185,
202
    FLUSHW  = 186,
203
    FLUSHri = 187,
204
    FLUSHrr = 188,
205
    FMEAN16 = 189,
206
    FMOVD = 190,
207
    FMOVD_FCC = 191,
208
    FMOVD_ICC = 192,
209
    FMOVD_XCC = 193,
210
    FMOVQ = 194,
211
    FMOVQ_FCC = 195,
212
    FMOVQ_ICC = 196,
213
    FMOVQ_XCC = 197,
214
    FMOVRGEZD = 198,
215
    FMOVRGEZQ = 199,
216
    FMOVRGEZS = 200,
217
    FMOVRGZD  = 201,
218
    FMOVRGZQ  = 202,
219
    FMOVRGZS  = 203,
220
    FMOVRLEZD = 204,
221
    FMOVRLEZQ = 205,
222
    FMOVRLEZS = 206,
223
    FMOVRLZD  = 207,
224
    FMOVRLZQ  = 208,
225
    FMOVRLZS  = 209,
226
    FMOVRNZD  = 210,
227
    FMOVRNZQ  = 211,
228
    FMOVRNZS  = 212,
229
    FMOVRZD = 213,
230
    FMOVRZQ = 214,
231
    FMOVRZS = 215,
232
    FMOVS = 216,
233
    FMOVS_FCC = 217,
234
    FMOVS_ICC = 218,
235
    FMOVS_XCC = 219,
236
    FMUL8SUX16  = 220,
237
    FMUL8ULX16  = 221,
238
    FMUL8X16  = 222,
239
    FMUL8X16AL  = 223,
240
    FMUL8X16AU  = 224,
241
    FMULD = 225,
242
    FMULD8SUX16 = 226,
243
    FMULD8ULX16 = 227,
244
    FMULQ = 228,
245
    FMULS = 229,
246
    FNADDD  = 230,
247
    FNADDS  = 231,
248
    FNAND = 232,
249
    FNANDS  = 233,
250
    FNEGD = 234,
251
    FNEGQ = 235,
252
    FNEGS = 236,
253
    FNHADDD = 237,
254
    FNHADDS = 238,
255
    FNMULD  = 239,
256
    FNMULS  = 240,
257
    FNOR  = 241,
258
    FNORS = 242,
259
    FNOT1 = 243,
260
    FNOT1S  = 244,
261
    FNOT2 = 245,
262
    FNOT2S  = 246,
263
    FNSMULD = 247,
264
    FONE  = 248,
265
    FONES = 249,
266
    FOR = 250,
267
    FORNOT1 = 251,
268
    FORNOT1S  = 252,
269
    FORNOT2 = 253,
270
    FORNOT2S  = 254,
271
    FORS  = 255,
272
    FPACK16 = 256,
273
    FPACK32 = 257,
274
    FPACKFIX  = 258,
275
    FPADD16 = 259,
276
    FPADD16S  = 260,
277
    FPADD32 = 261,
278
    FPADD32S  = 262,
279
    FPADD64 = 263,
280
    FPMERGE = 264,
281
    FPSUB16 = 265,
282
    FPSUB16S  = 266,
283
    FPSUB32 = 267,
284
    FPSUB32S  = 268,
285
    FQTOD = 269,
286
    FQTOI = 270,
287
    FQTOS = 271,
288
    FQTOX = 272,
289
    FSLAS16 = 273,
290
    FSLAS32 = 274,
291
    FSLL16  = 275,
292
    FSLL32  = 276,
293
    FSMULD  = 277,
294
    FSQRTD  = 278,
295
    FSQRTQ  = 279,
296
    FSQRTS  = 280,
297
    FSRA16  = 281,
298
    FSRA32  = 282,
299
    FSRC1 = 283,
300
    FSRC1S  = 284,
301
    FSRC2 = 285,
302
    FSRC2S  = 286,
303
    FSRL16  = 287,
304
    FSRL32  = 288,
305
    FSTOD = 289,
306
    FSTOI = 290,
307
    FSTOQ = 291,
308
    FSTOX = 292,
309
    FSUBD = 293,
310
    FSUBQ = 294,
311
    FSUBS = 295,
312
    FXNOR = 296,
313
    FXNORS  = 297,
314
    FXOR  = 298,
315
    FXORS = 299,
316
    FXTOD = 300,
317
    FXTOQ = 301,
318
    FXTOS = 302,
319
    FZERO = 303,
320
    FZEROS  = 304,
321
    GETPCX  = 305,
322
    JMPLri  = 306,
323
    JMPLrr  = 307,
324
    LDArr = 308,
325
    LDDArr  = 309,
326
    LDDFArr = 310,
327
    LDDFri  = 311,
328
    LDDFrr  = 312,
329
    LDDri = 313,
330
    LDDrr = 314,
331
    LDFArr  = 315,
332
    LDFSRri = 316,
333
    LDFSRrr = 317,
334
    LDFri = 318,
335
    LDFrr = 319,
336
    LDQFArr = 320,
337
    LDQFri  = 321,
338
    LDQFrr  = 322,
339
    LDSBArr = 323,
340
    LDSBri  = 324,
341
    LDSBrr  = 325,
342
    LDSHArr = 326,
343
    LDSHri  = 327,
344
    LDSHrr  = 328,
345
    LDSTUBArr = 329,
346
    LDSTUBri  = 330,
347
    LDSTUBrr  = 331,
348
    LDSWri  = 332,
349
    LDSWrr  = 333,
350
    LDUBArr = 334,
351
    LDUBri  = 335,
352
    LDUBrr  = 336,
353
    LDUHArr = 337,
354
    LDUHri  = 338,
355
    LDUHrr  = 339,
356
    LDXFSRri  = 340,
357
    LDXFSRrr  = 341,
358
    LDXri = 342,
359
    LDXrr = 343,
360
    LDri  = 344,
361
    LDrr  = 345,
362
    LEAX_ADDri  = 346,
363
    LEA_ADDri = 347,
364
    LZCNT = 348,
365
    MEMBARi = 349,
366
    MOVDTOX = 350,
367
    MOVFCCri  = 351,
368
    MOVFCCrr  = 352,
369
    MOVICCri  = 353,
370
    MOVICCrr  = 354,
371
    MOVRGEZri = 355,
372
    MOVRGEZrr = 356,
373
    MOVRGZri  = 357,
374
    MOVRGZrr  = 358,
375
    MOVRLEZri = 359,
376
    MOVRLEZrr = 360,
377
    MOVRLZri  = 361,
378
    MOVRLZrr  = 362,
379
    MOVRNZri  = 363,
380
    MOVRNZrr  = 364,
381
    MOVRRZri  = 365,
382
    MOVRRZrr  = 366,
383
    MOVSTOSW  = 367,
384
    MOVSTOUW  = 368,
385
    MOVWTOS = 369,
386
    MOVXCCri  = 370,
387
    MOVXCCrr  = 371,
388
    MOVXTOD = 372,
389
    MULSCCri  = 373,
390
    MULSCCrr  = 374,
391
    MULXri  = 375,
392
    MULXrr  = 376,
393
    NOP = 377,
394
    ORCCri  = 378,
395
    ORCCrr  = 379,
396
    ORNCCri = 380,
397
    ORNCCrr = 381,
398
    ORNri = 382,
399
    ORNrr = 383,
400
    ORXNrr  = 384,
401
    ORXri = 385,
402
    ORXrr = 386,
403
    ORri  = 387,
404
    ORrr  = 388,
405
    PDIST = 389,
406
    PDISTN  = 390,
407
    POPCrr  = 391,
408
    RDASR = 392,
409
    RDPR  = 393,
410
    RDPSR = 394,
411
    RDTBR = 395,
412
    RDWIM = 396,
413
    RESTOREri = 397,
414
    RESTORErr = 398,
415
    RET = 399,
416
    RETL  = 400,
417
    RETTri  = 401,
418
    RETTrr  = 402,
419
    SAVEri  = 403,
420
    SAVErr  = 404,
421
    SDIVCCri  = 405,
422
    SDIVCCrr  = 406,
423
    SDIVXri = 407,
424
    SDIVXrr = 408,
425
    SDIVri  = 409,
426
    SDIVrr  = 410,
427
    SELECT_CC_DFP_FCC = 411,
428
    SELECT_CC_DFP_ICC = 412,
429
    SELECT_CC_FP_FCC  = 413,
430
    SELECT_CC_FP_ICC  = 414,
431
    SELECT_CC_Int_FCC = 415,
432
    SELECT_CC_Int_ICC = 416,
433
    SELECT_CC_QFP_FCC = 417,
434
    SELECT_CC_QFP_ICC = 418,
435
    SET = 419,
436
    SETHIXi = 420,
437
    SETHIi  = 421,
438
    SHUTDOWN  = 422,
439
    SIAM  = 423,
440
    SLLXri  = 424,
441
    SLLXrr  = 425,
442
    SLLri = 426,
443
    SLLrr = 427,
444
    SMULCCri  = 428,
445
    SMULCCrr  = 429,
446
    SMULri  = 430,
447
    SMULrr  = 431,
448
    SRAXri  = 432,
449
    SRAXrr  = 433,
450
    SRAri = 434,
451
    SRArr = 435,
452
    SRLXri  = 436,
453
    SRLXrr  = 437,
454
    SRLri = 438,
455
    SRLrr = 439,
456
    STArr = 440,
457
    STBAR = 441,
458
    STBArr  = 442,
459
    STBri = 443,
460
    STBrr = 444,
461
    STDArr  = 445,
462
    STDFArr = 446,
463
    STDFri  = 447,
464
    STDFrr  = 448,
465
    STDri = 449,
466
    STDrr = 450,
467
    STFArr  = 451,
468
    STFSRri = 452,
469
    STFSRrr = 453,
470
    STFri = 454,
471
    STFrr = 455,
472
    STHArr  = 456,
473
    STHri = 457,
474
    STHrr = 458,
475
    STQFArr = 459,
476
    STQFri  = 460,
477
    STQFrr  = 461,
478
    STXFSRri  = 462,
479
    STXFSRrr  = 463,
480
    STXri = 464,
481
    STXrr = 465,
482
    STri  = 466,
483
    STrr  = 467,
484
    SUBCCri = 468,
485
    SUBCCrr = 469,
486
    SUBCri  = 470,
487
    SUBCrr  = 471,
488
    SUBEri  = 472,
489
    SUBErr  = 473,
490
    SUBXri  = 474,
491
    SUBXrr  = 475,
492
    SUBri = 476,
493
    SUBrr = 477,
494
    SWAPArr = 478,
495
    SWAPri  = 479,
496
    SWAPrr  = 480,
497
    TA3 = 481,
498
    TA5 = 482,
499
    TADDCCTVri  = 483,
500
    TADDCCTVrr  = 484,
501
    TADDCCri  = 485,
502
    TADDCCrr  = 486,
503
    TICCri  = 487,
504
    TICCrr  = 488,
505
    TLS_ADDXrr  = 489,
506
    TLS_ADDrr = 490,
507
    TLS_CALL  = 491,
508
    TLS_LDXrr = 492,
509
    TLS_LDrr  = 493,
510
    TSUBCCTVri  = 494,
511
    TSUBCCTVrr  = 495,
512
    TSUBCCri  = 496,
513
    TSUBCCrr  = 497,
514
    TXCCri  = 498,
515
    TXCCrr  = 499,
516
    UDIVCCri  = 500,
517
    UDIVCCrr  = 501,
518
    UDIVXri = 502,
519
    UDIVXrr = 503,
520
    UDIVri  = 504,
521
    UDIVrr  = 505,
522
    UMULCCri  = 506,
523
    UMULCCrr  = 507,
524
    UMULXHI = 508,
525
    UMULri  = 509,
526
    UMULrr  = 510,
527
    UNIMP = 511,
528
    V9FCMPD = 512,
529
    V9FCMPED  = 513,
530
    V9FCMPEQ  = 514,
531
    V9FCMPES  = 515,
532
    V9FCMPQ = 516,
533
    V9FCMPS = 517,
534
    V9FMOVD_FCC = 518,
535
    V9FMOVQ_FCC = 519,
536
    V9FMOVS_FCC = 520,
537
    V9MOVFCCri  = 521,
538
    V9MOVFCCrr  = 522,
539
    WRASRri = 523,
540
    WRASRrr = 524,
541
    WRPRri  = 525,
542
    WRPRrr  = 526,
543
    WRPSRri = 527,
544
    WRPSRrr = 528,
545
    WRTBRri = 529,
546
    WRTBRrr = 530,
547
    WRWIMri = 531,
548
    WRWIMrr = 532,
549
    XMULX = 533,
550
    XMULXHI = 534,
551
    XNORCCri  = 535,
552
    XNORCCrr  = 536,
553
    XNORXrr = 537,
554
    XNORri  = 538,
555
    XNORrr  = 539,
556
    XORCCri = 540,
557
    XORCCrr = 541,
558
    XORXri  = 542,
559
    XORXrr  = 543,
560
    XORri = 544,
561
    XORrr = 545,
562
    INSTRUCTION_LIST_END = 546
563
  };
564
565
namespace Sched {
566
  enum {
567
    NoInstrModel  = 0,
568
    SCHED_LIST_END = 1
569
  };
570
} // end Sched namespace
571
} // end SP namespace
572
} // end llvm namespace 
573
#endif // GET_INSTRINFO_ENUM
574
575
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
576
|*                                                                            *|
577
|* Target Instruction Descriptors                                             *|
578
|*                                                                            *|
579
|* Automatically generated file, do not edit!                                 *|
580
|*                                                                            *|
581
\*===----------------------------------------------------------------------===*/
582
583
584
#ifdef GET_INSTRINFO_MC_DESC
585
#undef GET_INSTRINFO_MC_DESC
586
namespace llvm_ks {
587
588
static const MCPhysReg ImplicitList1[] = { SP::ICC, 0 };
589
static const MCPhysReg ImplicitList2[] = { SP::O6, 0 };
590
static const MCPhysReg ImplicitList3[] = { SP::FCC0, 0 };
591
static const MCPhysReg ImplicitList4[] = { SP::O7, 0 };
592
static const MCPhysReg ImplicitList5[] = { SP::FSR, 0 };
593
static const MCPhysReg ImplicitList6[] = { SP::Y, SP::ICC, 0 };
594
static const MCPhysReg ImplicitList7[] = { SP::PSR, 0 };
595
static const MCPhysReg ImplicitList8[] = { SP::TBR, 0 };
596
static const MCPhysReg ImplicitList9[] = { SP::WIM, 0 };
597
static const MCPhysReg ImplicitList10[] = { SP::Y, 0 };
598
599
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
600
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
601
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
602
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
603
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
604
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
605
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
606
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
607
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
608
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
609
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
610
static const MCOperandInfo OperandInfo13[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
611
static const MCOperandInfo OperandInfo14[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
612
static const MCOperandInfo OperandInfo15[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
613
static const MCOperandInfo OperandInfo16[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
614
static const MCOperandInfo OperandInfo17[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
615
static const MCOperandInfo OperandInfo18[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
616
static const MCOperandInfo OperandInfo19[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
617
static const MCOperandInfo OperandInfo20[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
618
static const MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
619
static const MCOperandInfo OperandInfo22[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
620
static const MCOperandInfo OperandInfo23[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
621
static const MCOperandInfo OperandInfo24[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
622
static const MCOperandInfo OperandInfo25[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
623
static const MCOperandInfo OperandInfo26[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
624
static const MCOperandInfo OperandInfo27[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
625
static const MCOperandInfo OperandInfo28[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
626
static const MCOperandInfo OperandInfo29[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
627
static const MCOperandInfo OperandInfo30[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
628
static const MCOperandInfo OperandInfo31[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
629
static const MCOperandInfo OperandInfo32[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
630
static const MCOperandInfo OperandInfo33[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
631
static const MCOperandInfo OperandInfo34[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
632
static const MCOperandInfo OperandInfo35[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
633
static const MCOperandInfo OperandInfo36[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
634
static const MCOperandInfo OperandInfo37[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
635
static const MCOperandInfo OperandInfo38[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
636
static const MCOperandInfo OperandInfo39[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
637
static const MCOperandInfo OperandInfo40[] = { { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
638
static const MCOperandInfo OperandInfo41[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
639
static const MCOperandInfo OperandInfo42[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
640
static const MCOperandInfo OperandInfo43[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
641
static const MCOperandInfo OperandInfo44[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
642
static const MCOperandInfo OperandInfo45[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
643
static const MCOperandInfo OperandInfo46[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
644
static const MCOperandInfo OperandInfo47[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
645
static const MCOperandInfo OperandInfo48[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
646
static const MCOperandInfo OperandInfo49[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
647
static const MCOperandInfo OperandInfo50[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
648
static const MCOperandInfo OperandInfo51[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
649
static const MCOperandInfo OperandInfo52[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
650
static const MCOperandInfo OperandInfo53[] = { { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
651
static const MCOperandInfo OperandInfo54[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
652
static const MCOperandInfo OperandInfo55[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
653
static const MCOperandInfo OperandInfo56[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
654
static const MCOperandInfo OperandInfo57[] = { { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
655
static const MCOperandInfo OperandInfo58[] = { { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
656
static const MCOperandInfo OperandInfo59[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
657
static const MCOperandInfo OperandInfo60[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
658
static const MCOperandInfo OperandInfo61[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
659
static const MCOperandInfo OperandInfo62[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
660
static const MCOperandInfo OperandInfo63[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
661
static const MCOperandInfo OperandInfo64[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
662
static const MCOperandInfo OperandInfo65[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
663
static const MCOperandInfo OperandInfo66[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
664
static const MCOperandInfo OperandInfo67[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
665
static const MCOperandInfo OperandInfo68[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
666
static const MCOperandInfo OperandInfo69[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
667
static const MCOperandInfo OperandInfo70[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
668
static const MCOperandInfo OperandInfo71[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
669
static const MCOperandInfo OperandInfo72[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
670
static const MCOperandInfo OperandInfo73[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
671
static const MCOperandInfo OperandInfo74[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
672
static const MCOperandInfo OperandInfo75[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
673
static const MCOperandInfo OperandInfo76[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
674
static const MCOperandInfo OperandInfo77[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
675
static const MCOperandInfo OperandInfo78[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
676
static const MCOperandInfo OperandInfo79[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
677
static const MCOperandInfo OperandInfo80[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
678
static const MCOperandInfo OperandInfo81[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
679
static const MCOperandInfo OperandInfo82[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
680
static const MCOperandInfo OperandInfo83[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
681
static const MCOperandInfo OperandInfo84[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
682
static const MCOperandInfo OperandInfo85[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
683
static const MCOperandInfo OperandInfo86[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
684
static const MCOperandInfo OperandInfo87[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
685
static const MCOperandInfo OperandInfo88[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
686
static const MCOperandInfo OperandInfo89[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
687
static const MCOperandInfo OperandInfo90[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntPairRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
688
static const MCOperandInfo OperandInfo91[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
689
static const MCOperandInfo OperandInfo92[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
690
static const MCOperandInfo OperandInfo93[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
691
static const MCOperandInfo OperandInfo94[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
692
static const MCOperandInfo OperandInfo95[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
693
static const MCOperandInfo OperandInfo96[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
694
static const MCOperandInfo OperandInfo97[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
695
static const MCOperandInfo OperandInfo98[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
696
static const MCOperandInfo OperandInfo99[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
697
static const MCOperandInfo OperandInfo100[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
698
static const MCOperandInfo OperandInfo101[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
699
static const MCOperandInfo OperandInfo102[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
700
static const MCOperandInfo OperandInfo103[] = { { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::I64RegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
701
static const MCOperandInfo OperandInfo104[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
702
static const MCOperandInfo OperandInfo105[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
703
static const MCOperandInfo OperandInfo106[] = { { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
704
static const MCOperandInfo OperandInfo107[] = { { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
705
static const MCOperandInfo OperandInfo108[] = { { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::DFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
706
static const MCOperandInfo OperandInfo109[] = { { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::QFPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
707
static const MCOperandInfo OperandInfo110[] = { { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FPRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
708
static const MCOperandInfo OperandInfo111[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
709
static const MCOperandInfo OperandInfo112[] = { { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::FCCRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
710
static const MCOperandInfo OperandInfo113[] = { { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
711
static const MCOperandInfo OperandInfo114[] = { { SP::ASRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
712
static const MCOperandInfo OperandInfo115[] = { { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
713
static const MCOperandInfo OperandInfo116[] = { { SP::PRRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SP::IntRegsRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
714
715
extern const MCInstrDesc SparcInsts[] = {
716
  { 0,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #0 = PHI
717
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
718
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
719
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #3 = EH_LABEL
720
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #4 = GC_LABEL
721
  { 5,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #5 = KILL
722
  { 6,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #6 = EXTRACT_SUBREG
723
  { 7,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = INSERT_SUBREG
724
  { 8,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = IMPLICIT_DEF
725
  { 9,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #9 = SUBREG_TO_REG
726
  { 10, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #10 = COPY_TO_REGCLASS
727
  { 11, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #11 = DBG_VALUE
728
  { 12, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #12 = REG_SEQUENCE
729
  { 13, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #13 = COPY
730
  { 14, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #14 = BUNDLE
731
  { 15, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #15 = LIFETIME_START
732
  { 16, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #16 = LIFETIME_END
733
  { 17, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #17 = STACKMAP
734
  { 18, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #18 = PATCHPOINT
735
  { 19, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #19 = LOAD_STACK_GUARD
736
  { 20, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #20 = STATEPOINT
737
  { 21, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #21 = LOCAL_ESCAPE
738
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #22 = FAULTING_LOAD_OP
739
  { 23, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #23 = G_ADD
740
  { 24, 3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #24 = ADDCCri
741
  { 25, 3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #25 = ADDCCrr
742
  { 26, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #26 = ADDCri
743
  { 27, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #27 = ADDCrr
744
  { 28, 3,  1,  4,  0,  0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #28 = ADDEri
745
  { 29, 3,  1,  4,  0,  0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #29 = ADDErr
746
  { 30, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #30 = ADDXC
747
  { 31, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #31 = ADDXCCC
748
  { 32, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #32 = ADDXri
749
  { 33, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #33 = ADDXrr
750
  { 34, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #34 = ADDri
751
  { 35, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #35 = ADDrr
752
  { 36, 1,  0,  4,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2, -1 ,nullptr },  // Inst #36 = ADJCALLSTACKDOWN
753
  { 37, 2,  0,  4,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8, -1 ,nullptr },  // Inst #37 = ADJCALLSTACKUP
754
  { 38, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #38 = ALIGNADDR
755
  { 39, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #39 = ALIGNADDRL
756
  { 40, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #40 = ANDCCri
757
  { 41, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #41 = ANDCCrr
758
  { 42, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #42 = ANDNCCri
759
  { 43, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #43 = ANDNCCrr
760
  { 44, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #44 = ANDNri
761
  { 45, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #45 = ANDNrr
762
  { 46, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #46 = ANDXNrr
763
  { 47, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #47 = ANDXri
764
  { 48, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #48 = ANDXrr
765
  { 49, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #49 = ANDri
766
  { 50, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #50 = ANDrr
767
  { 51, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #51 = ARRAY16
768
  { 52, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #52 = ARRAY32
769
  { 53, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #53 = ARRAY8
770
  { 54, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #54 = ATOMIC_LOAD_ADD_32
771
  { 55, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #55 = ATOMIC_LOAD_ADD_64
772
  { 56, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #56 = ATOMIC_LOAD_AND_32
773
  { 57, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #57 = ATOMIC_LOAD_AND_64
774
  { 58, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #58 = ATOMIC_LOAD_MAX_32
775
  { 59, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #59 = ATOMIC_LOAD_MAX_64
776
  { 60, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #60 = ATOMIC_LOAD_MIN_32
777
  { 61, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #61 = ATOMIC_LOAD_MIN_64
778
  { 62, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #62 = ATOMIC_LOAD_NAND_32
779
  { 63, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #63 = ATOMIC_LOAD_NAND_64
780
  { 64, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #64 = ATOMIC_LOAD_OR_32
781
  { 65, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #65 = ATOMIC_LOAD_OR_64
782
  { 66, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #66 = ATOMIC_LOAD_SUB_32
783
  { 67, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #67 = ATOMIC_LOAD_SUB_64
784
  { 68, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #68 = ATOMIC_LOAD_UMAX_32
785
  { 69, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #69 = ATOMIC_LOAD_UMAX_64
786
  { 70, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #70 = ATOMIC_LOAD_UMIN_32
787
  { 71, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #71 = ATOMIC_LOAD_UMIN_64
788
  { 72, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #72 = ATOMIC_LOAD_XOR_32
789
  { 73, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #73 = ATOMIC_LOAD_XOR_64
790
  { 74, 3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #74 = ATOMIC_SWAP_64
791
  { 75, 1,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #75 = BA
792
  { 76, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #76 = BCOND
793
  { 77, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #77 = BCONDA
794
  { 78, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #78 = BINDri
795
  { 79, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #79 = BINDrr
796
  { 80, 3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #80 = BMASK
797
  { 81, 3,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #81 = BPFCC
798
  { 82, 3,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #82 = BPFCCA
799
  { 83, 3,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #83 = BPFCCANT
800
  { 84, 3,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #84 = BPFCCNT
801
  { 85, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #85 = BPGEZapn
802
  { 86, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #86 = BPGEZapt
803
  { 87, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #87 = BPGEZnapn
804
  { 88, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #88 = BPGEZnapt
805
  { 89, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #89 = BPGZapn
806
  { 90, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #90 = BPGZapt
807
  { 91, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #91 = BPGZnapn
808
  { 92, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #92 = BPGZnapt
809
  { 93, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #93 = BPICC
810
  { 94, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #94 = BPICCA
811
  { 95, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #95 = BPICCANT
812
  { 96, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #96 = BPICCNT
813
  { 97, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #97 = BPLEZapn
814
  { 98, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #98 = BPLEZapt
815
  { 99, 2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #99 = BPLEZnapn
816
  { 100,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #100 = BPLEZnapt
817
  { 101,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #101 = BPLZapn
818
  { 102,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #102 = BPLZapt
819
  { 103,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #103 = BPLZnapn
820
  { 104,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #104 = BPLZnapt
821
  { 105,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #105 = BPNZapn
822
  { 106,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #106 = BPNZapt
823
  { 107,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #107 = BPNZnapn
824
  { 108,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #108 = BPNZnapt
825
  { 109,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #109 = BPXCC
826
  { 110,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #110 = BPXCCA
827
  { 111,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #111 = BPXCCANT
828
  { 112,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #112 = BPXCCNT
829
  { 113,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #113 = BPZapn
830
  { 114,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #114 = BPZapt
831
  { 115,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #115 = BPZnapn
832
  { 116,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #116 = BPZnapt
833
  { 117,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #117 = BSHUFFLE
834
  { 118,  1,  0,  4,  0,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, ImplicitList2, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #118 = CALL
835
  { 119,  2,  0,  4,  0,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, ImplicitList2, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #119 = CALLri
836
  { 120,  2,  0,  4,  0,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, ImplicitList2, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #120 = CALLrr
837
  { 121,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #121 = CASXrr
838
  { 122,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #122 = CASrr
839
  { 123,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #123 = CMASK16
840
  { 124,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #124 = CMASK32
841
  { 125,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #125 = CMASK8
842
  { 126,  2,  0,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #126 = CMPri
843
  { 127,  2,  0,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #127 = CMPrr
844
  { 128,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #128 = EDGE16
845
  { 129,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #129 = EDGE16L
846
  { 130,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #130 = EDGE16LN
847
  { 131,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #131 = EDGE16N
848
  { 132,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #132 = EDGE32
849
  { 133,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #133 = EDGE32L
850
  { 134,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #134 = EDGE32LN
851
  { 135,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #135 = EDGE32N
852
  { 136,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #136 = EDGE8
853
  { 137,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #137 = EDGE8L
854
  { 138,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #138 = EDGE8LN
855
  { 139,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #139 = EDGE8N
856
  { 140,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #140 = FABSD
857
  { 141,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #141 = FABSQ
858
  { 142,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #142 = FABSS
859
  { 143,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #143 = FADDD
860
  { 144,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #144 = FADDQ
861
  { 145,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #145 = FADDS
862
  { 146,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #146 = FALIGNADATA
863
  { 147,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #147 = FAND
864
  { 148,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #148 = FANDNOT1
865
  { 149,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #149 = FANDNOT1S
866
  { 150,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #150 = FANDNOT2
867
  { 151,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #151 = FANDNOT2S
868
  { 152,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #152 = FANDS
869
  { 153,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList3, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #153 = FBCOND
870
  { 154,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList3, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #154 = FBCONDA
871
  { 155,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #155 = FCHKSM16
872
  { 156,  2,  0,  4,  0,  0, 0x0ULL, nullptr, ImplicitList3, OperandInfo29, -1 ,nullptr },  // Inst #156 = FCMPD
873
  { 157,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #157 = FCMPEQ16
874
  { 158,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #158 = FCMPEQ32
875
  { 159,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #159 = FCMPGT16
876
  { 160,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #160 = FCMPGT32
877
  { 161,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #161 = FCMPLE16
878
  { 162,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #162 = FCMPLE32
879
  { 163,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #163 = FCMPNE16
880
  { 164,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #164 = FCMPNE32
881
  { 165,  2,  0,  4,  0,  0, 0x0ULL, nullptr, ImplicitList3, OperandInfo30, -1 ,nullptr },  // Inst #165 = FCMPQ
882
  { 166,  2,  0,  4,  0,  0, 0x0ULL, nullptr, ImplicitList3, OperandInfo31, -1 ,nullptr },  // Inst #166 = FCMPS
883
  { 167,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #167 = FDIVD
884
  { 168,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #168 = FDIVQ
885
  { 169,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #169 = FDIVS
886
  { 170,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #170 = FDMULQ
887
  { 171,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #171 = FDTOI
888
  { 172,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #172 = FDTOQ
889
  { 173,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #173 = FDTOS
890
  { 174,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #174 = FDTOX
891
  { 175,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #175 = FEXPAND
892
  { 176,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #176 = FHADDD
893
  { 177,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #177 = FHADDS
894
  { 178,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #178 = FHSUBD
895
  { 179,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #179 = FHSUBS
896
  { 180,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #180 = FITOD
897
  { 181,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #181 = FITOQ
898
  { 182,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #182 = FITOS
899
  { 183,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #183 = FLCMPD
900
  { 184,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #184 = FLCMPS
901
  { 185,  0,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #185 = FLUSH
902
  { 186,  0,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #186 = FLUSHW
903
  { 187,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #187 = FLUSHri
904
  { 188,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #188 = FLUSHrr
905
  { 189,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #189 = FMEAN16
906
  { 190,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #190 = FMOVD
907
  { 191,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList3, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #191 = FMOVD_FCC
908
  { 192,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #192 = FMOVD_ICC
909
  { 193,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList1, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #193 = FMOVD_XCC
910
  { 194,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #194 = FMOVQ
911
  { 195,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList3, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #195 = FMOVQ_FCC
912
  { 196,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #196 = FMOVQ_ICC
913
  { 197,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #197 = FMOVQ_XCC
914
  { 198,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #198 = FMOVRGEZD
915
  { 199,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #199 = FMOVRGEZQ
916
  { 200,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #200 = FMOVRGEZS
917
  { 201,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #201 = FMOVRGZD
918
  { 202,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #202 = FMOVRGZQ
919
  { 203,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #203 = FMOVRGZS
920
  { 204,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #204 = FMOVRLEZD
921
  { 205,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #205 = FMOVRLEZQ
922
  { 206,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #206 = FMOVRLEZS
923
  { 207,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #207 = FMOVRLZD
924
  { 208,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #208 = FMOVRLZQ
925
  { 209,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #209 = FMOVRLZS
926
  { 210,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #210 = FMOVRNZD
927
  { 211,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #211 = FMOVRNZQ
928
  { 212,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #212 = FMOVRNZS
929
  { 213,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #213 = FMOVRZD
930
  { 214,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #214 = FMOVRZQ
931
  { 215,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #215 = FMOVRZS
932
  { 216,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #216 = FMOVS
933
  { 217,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList3, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #217 = FMOVS_FCC
934
  { 218,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #218 = FMOVS_ICC
935
  { 219,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #219 = FMOVS_XCC
936
  { 220,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #220 = FMUL8SUX16
937
  { 221,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #221 = FMUL8ULX16
938
  { 222,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #222 = FMUL8X16
939
  { 223,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #223 = FMUL8X16AL
940
  { 224,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #224 = FMUL8X16AU
941
  { 225,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #225 = FMULD
942
  { 226,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #226 = FMULD8SUX16
943
  { 227,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #227 = FMULD8ULX16
944
  { 228,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #228 = FMULQ
945
  { 229,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #229 = FMULS
946
  { 230,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #230 = FNADDD
947
  { 231,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #231 = FNADDS
948
  { 232,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #232 = FNAND
949
  { 233,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #233 = FNANDS
950
  { 234,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #234 = FNEGD
951
  { 235,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #235 = FNEGQ
952
  { 236,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #236 = FNEGS
953
  { 237,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #237 = FNHADDD
954
  { 238,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #238 = FNHADDS
955
  { 239,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #239 = FNMULD
956
  { 240,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #240 = FNMULS
957
  { 241,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #241 = FNOR
958
  { 242,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #242 = FNORS
959
  { 243,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #243 = FNOT1
960
  { 244,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #244 = FNOT1S
961
  { 245,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #245 = FNOT2
962
  { 246,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #246 = FNOT2S
963
  { 247,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #247 = FNSMULD
964
  { 248,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #248 = FONE
965
  { 249,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #249 = FONES
966
  { 250,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #250 = FOR
967
  { 251,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #251 = FORNOT1
968
  { 252,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #252 = FORNOT1S
969
  { 253,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #253 = FORNOT2
970
  { 254,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #254 = FORNOT2S
971
  { 255,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #255 = FORS
972
  { 256,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #256 = FPACK16
973
  { 257,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #257 = FPACK32
974
  { 258,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #258 = FPACKFIX
975
  { 259,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #259 = FPADD16
976
  { 260,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #260 = FPADD16S
977
  { 261,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #261 = FPADD32
978
  { 262,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #262 = FPADD32S
979
  { 263,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #263 = FPADD64
980
  { 264,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #264 = FPMERGE
981
  { 265,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #265 = FPSUB16
982
  { 266,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #266 = FPSUB16S
983
  { 267,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #267 = FPSUB32
984
  { 268,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #268 = FPSUB32S
985
  { 269,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #269 = FQTOD
986
  { 270,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #270 = FQTOI
987
  { 271,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #271 = FQTOS
988
  { 272,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #272 = FQTOX
989
  { 273,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #273 = FSLAS16
990
  { 274,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #274 = FSLAS32
991
  { 275,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #275 = FSLL16
992
  { 276,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #276 = FSLL32
993
  { 277,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #277 = FSMULD
994
  { 278,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #278 = FSQRTD
995
  { 279,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #279 = FSQRTQ
996
  { 280,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #280 = FSQRTS
997
  { 281,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #281 = FSRA16
998
  { 282,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #282 = FSRA32
999
  { 283,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #283 = FSRC1
1000
  { 284,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #284 = FSRC1S
1001
  { 285,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #285 = FSRC2
1002
  { 286,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #286 = FSRC2S
1003
  { 287,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #287 = FSRL16
1004
  { 288,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #288 = FSRL32
1005
  { 289,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #289 = FSTOD
1006
  { 290,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #290 = FSTOI
1007
  { 291,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #291 = FSTOQ
1008
  { 292,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #292 = FSTOX
1009
  { 293,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #293 = FSUBD
1010
  { 294,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #294 = FSUBQ
1011
  { 295,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #295 = FSUBS
1012
  { 296,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #296 = FXNOR
1013
  { 297,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #297 = FXNORS
1014
  { 298,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #298 = FXOR
1015
  { 299,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo33, -1 ,nullptr },  // Inst #299 = FXORS
1016
  { 300,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #300 = FXTOD
1017
  { 301,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #301 = FXTOQ
1018
  { 302,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #302 = FXTOS
1019
  { 303,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #303 = FZERO
1020
  { 304,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #304 = FZEROS
1021
  { 305,  1,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList4, OperandInfo5, -1 ,nullptr },  // Inst #305 = GETPCX
1022
  { 306,  3,  1,  4,  0,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #306 = JMPLri
1023
  { 307,  3,  1,  4,  0,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #307 = JMPLrr
1024
  { 308,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #308 = LDArr
1025
  { 309,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #309 = LDDArr
1026
  { 310,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #310 = LDDFArr
1027
  { 311,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #311 = LDDFri
1028
  { 312,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #312 = LDDFrr
1029
  { 313,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #313 = LDDri
1030
  { 314,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #314 = LDDrr
1031
  { 315,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #315 = LDFArr
1032
  { 316,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo19, -1 ,nullptr },  // Inst #316 = LDFSRri
1033
  { 317,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo20, -1 ,nullptr },  // Inst #317 = LDFSRrr
1034
  { 318,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #318 = LDFri
1035
  { 319,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #319 = LDFrr
1036
  { 320,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #320 = LDQFArr
1037
  { 321,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #321 = LDQFri
1038
  { 322,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #322 = LDQFrr
1039
  { 323,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #323 = LDSBArr
1040
  { 324,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #324 = LDSBri
1041
  { 325,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #325 = LDSBrr
1042
  { 326,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #326 = LDSHArr
1043
  { 327,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #327 = LDSHri
1044
  { 328,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #328 = LDSHrr
1045
  { 329,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #329 = LDSTUBArr
1046
  { 330,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #330 = LDSTUBri
1047
  { 331,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #331 = LDSTUBrr
1048
  { 332,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #332 = LDSWri
1049
  { 333,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #333 = LDSWrr
1050
  { 334,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #334 = LDUBArr
1051
  { 335,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #335 = LDUBri
1052
  { 336,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #336 = LDUBrr
1053
  { 337,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #337 = LDUHArr
1054
  { 338,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #338 = LDUHri
1055
  { 339,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #339 = LDUHrr
1056
  { 340,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo19, -1 ,nullptr },  // Inst #340 = LDXFSRri
1057
  { 341,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo20, -1 ,nullptr },  // Inst #341 = LDXFSRrr
1058
  { 342,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #342 = LDXri
1059
  { 343,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #343 = LDXrr
1060
  { 344,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #344 = LDri
1061
  { 345,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #345 = LDrr
1062
  { 346,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #346 = LEAX_ADDri
1063
  { 347,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #347 = LEA_ADDri
1064
  { 348,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #348 = LZCNT
1065
  { 349,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #349 = MEMBARi
1066
  { 350,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #350 = MOVDTOX
1067
  { 351,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList3, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #351 = MOVFCCri
1068
  { 352,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList3, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #352 = MOVFCCrr
1069
  { 353,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList1, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #353 = MOVICCri
1070
  { 354,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList1, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #354 = MOVICCrr
1071
  { 355,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #355 = MOVRGEZri
1072
  { 356,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #356 = MOVRGEZrr
1073
  { 357,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #357 = MOVRGZri
1074
  { 358,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #358 = MOVRGZrr
1075
  { 359,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #359 = MOVRLEZri
1076
  { 360,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #360 = MOVRLEZrr
1077
  { 361,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #361 = MOVRLZri
1078
  { 362,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #362 = MOVRLZrr
1079
  { 363,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #363 = MOVRNZri
1080
  { 364,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #364 = MOVRNZrr
1081
  { 365,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #365 = MOVRRZri
1082
  { 366,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #366 = MOVRRZrr
1083
  { 367,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #367 = MOVSTOSW
1084
  { 368,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #368 = MOVSTOUW
1085
  { 369,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #369 = MOVWTOS
1086
  { 370,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList1, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #370 = MOVXCCri
1087
  { 371,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList1, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #371 = MOVXCCrr
1088
  { 372,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #372 = MOVXTOD
1089
  { 373,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList6, OperandInfo13, -1 ,nullptr },  // Inst #373 = MULSCCri
1090
  { 374,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList6, ImplicitList6, OperandInfo14, -1 ,nullptr },  // Inst #374 = MULSCCrr
1091
  { 375,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #375 = MULXri
1092
  { 376,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #376 = MULXrr
1093
  { 377,  0,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #377 = NOP
1094
  { 378,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #378 = ORCCri
1095
  { 379,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #379 = ORCCrr
1096
  { 380,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #380 = ORNCCri
1097
  { 381,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #381 = ORNCCrr
1098
  { 382,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #382 = ORNri
1099
  { 383,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #383 = ORNrr
1100
  { 384,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #384 = ORXNrr
1101
  { 385,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #385 = ORXri
1102
  { 386,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #386 = ORXrr
1103
  { 387,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #387 = ORri
1104
  { 388,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #388 = ORrr
1105
  { 389,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #389 = PDIST
1106
  { 390,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #390 = PDISTN
1107
  { 391,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #391 = POPCrr
1108
  { 392,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #392 = RDASR
1109
  { 393,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #393 = RDPR
1110
  { 394,  1,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList7, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #394 = RDPSR
1111
  { 395,  1,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList8, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #395 = RDTBR
1112
  { 396,  1,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList9, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #396 = RDWIM
1113
  { 397,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #397 = RESTOREri
1114
  { 398,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #398 = RESTORErr
1115
  { 399,  1,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #399 = RET
1116
  { 400,  1,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #400 = RETL
1117
  { 401,  2,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #401 = RETTri
1118
  { 402,  2,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #402 = RETTrr
1119
  { 403,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #403 = SAVEri
1120
  { 404,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #404 = SAVErr
1121
  { 405,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList6, OperandInfo13, -1 ,nullptr },  // Inst #405 = SDIVCCri
1122
  { 406,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList6, OperandInfo14, -1 ,nullptr },  // Inst #406 = SDIVCCrr
1123
  { 407,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #407 = SDIVXri
1124
  { 408,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #408 = SDIVXrr
1125
  { 409,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList10, OperandInfo13, -1 ,nullptr },  // Inst #409 = SDIVri
1126
  { 410,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList10, OperandInfo14, -1 ,nullptr },  // Inst #410 = SDIVrr
1127
  { 411,  4,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #411 = SELECT_CC_DFP_FCC
1128
  { 412,  4,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #412 = SELECT_CC_DFP_ICC
1129
  { 413,  4,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #413 = SELECT_CC_FP_FCC
1130
  { 414,  4,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #414 = SELECT_CC_FP_ICC
1131
  { 415,  4,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #415 = SELECT_CC_Int_FCC
1132
  { 416,  4,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #416 = SELECT_CC_Int_ICC
1133
  { 417,  4,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList3, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #417 = SELECT_CC_QFP_FCC
1134
  { 418,  4,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #418 = SELECT_CC_QFP_ICC
1135
  { 419,  2,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #419 = SET
1136
  { 420,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #420 = SETHIXi
1137
  { 421,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #421 = SETHIi
1138
  { 422,  0,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #422 = SHUTDOWN
1139
  { 423,  0,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #423 = SIAM
1140
  { 424,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #424 = SLLXri
1141
  { 425,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #425 = SLLXrr
1142
  { 426,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #426 = SLLri
1143
  { 427,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #427 = SLLrr
1144
  { 428,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo13, -1 ,nullptr },  // Inst #428 = SMULCCri
1145
  { 429,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo14, -1 ,nullptr },  // Inst #429 = SMULCCrr
1146
  { 430,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList10, OperandInfo13, -1 ,nullptr },  // Inst #430 = SMULri
1147
  { 431,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList10, OperandInfo14, -1 ,nullptr },  // Inst #431 = SMULrr
1148
  { 432,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #432 = SRAXri
1149
  { 433,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #433 = SRAXrr
1150
  { 434,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #434 = SRAri
1151
  { 435,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #435 = SRArr
1152
  { 436,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #436 = SRLXri
1153
  { 437,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #437 = SRLXrr
1154
  { 438,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #438 = SRLri
1155
  { 439,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #439 = SRLrr
1156
  { 440,  4,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #440 = STArr
1157
  { 441,  0,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #441 = STBAR
1158
  { 442,  4,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #442 = STBArr
1159
  { 443,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #443 = STBri
1160
  { 444,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #444 = STBrr
1161
  { 445,  4,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #445 = STDArr
1162
  { 446,  4,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #446 = STDFArr
1163
  { 447,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #447 = STDFri
1164
  { 448,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #448 = STDFrr
1165
  { 449,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #449 = STDri
1166
  { 450,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #450 = STDrr
1167
  { 451,  4,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #451 = STFArr
1168
  { 452,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo19, -1 ,nullptr },  // Inst #452 = STFSRri
1169
  { 453,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo20, -1 ,nullptr },  // Inst #453 = STFSRrr
1170
  { 454,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #454 = STFri
1171
  { 455,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #455 = STFrr
1172
  { 456,  4,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #456 = STHArr
1173
  { 457,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #457 = STHri
1174
  { 458,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #458 = STHrr
1175
  { 459,  4,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #459 = STQFArr
1176
  { 460,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #460 = STQFri
1177
  { 461,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #461 = STQFrr
1178
  { 462,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo19, -1 ,nullptr },  // Inst #462 = STXFSRri
1179
  { 463,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList5, OperandInfo20, -1 ,nullptr },  // Inst #463 = STXFSRrr
1180
  { 464,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #464 = STXri
1181
  { 465,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #465 = STXrr
1182
  { 466,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #466 = STri
1183
  { 467,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #467 = STrr
1184
  { 468,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #468 = SUBCCri
1185
  { 469,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #469 = SUBCCrr
1186
  { 470,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #470 = SUBCri
1187
  { 471,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #471 = SUBCrr
1188
  { 472,  3,  1,  4,  0,  0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #472 = SUBEri
1189
  { 473,  3,  1,  4,  0,  0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #473 = SUBErr
1190
  { 474,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #474 = SUBXri
1191
  { 475,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #475 = SUBXrr
1192
  { 476,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #476 = SUBri
1193
  { 477,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #477 = SUBrr
1194
  { 478,  5,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #478 = SWAPArr
1195
  { 479,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #479 = SWAPri
1196
  { 480,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #480 = SWAPrr
1197
  { 481,  0,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #481 = TA3
1198
  { 482,  0,  0,  4,  0,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #482 = TA5
1199
  { 483,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #483 = TADDCCTVri
1200
  { 484,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #484 = TADDCCTVrr
1201
  { 485,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #485 = TADDCCri
1202
  { 486,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #486 = TADDCCrr
1203
  { 487,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #487 = TICCri
1204
  { 488,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #488 = TICCrr
1205
  { 489,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #489 = TLS_ADDXrr
1206
  { 490,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #490 = TLS_ADDrr
1207
  { 491,  2,  0,  4,  0,  0|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, ImplicitList2, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #491 = TLS_CALL
1208
  { 492,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #492 = TLS_LDXrr
1209
  { 493,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #493 = TLS_LDrr
1210
  { 494,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #494 = TSUBCCTVri
1211
  { 495,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #495 = TSUBCCTVrr
1212
  { 496,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #496 = TSUBCCri
1213
  { 497,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #497 = TSUBCCrr
1214
  { 498,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #498 = TXCCri
1215
  { 499,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #499 = TXCCrr
1216
  { 500,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList6, OperandInfo13, -1 ,nullptr },  // Inst #500 = UDIVCCri
1217
  { 501,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList6, OperandInfo14, -1 ,nullptr },  // Inst #501 = UDIVCCrr
1218
  { 502,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #502 = UDIVXri
1219
  { 503,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #503 = UDIVXrr
1220
  { 504,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList10, OperandInfo13, -1 ,nullptr },  // Inst #504 = UDIVri
1221
  { 505,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList10, ImplicitList10, OperandInfo14, -1 ,nullptr },  // Inst #505 = UDIVrr
1222
  { 506,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo13, -1 ,nullptr },  // Inst #506 = UMULCCri
1223
  { 507,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo14, -1 ,nullptr },  // Inst #507 = UMULCCrr
1224
  { 508,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #508 = UMULXHI
1225
  { 509,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList10, OperandInfo13, -1 ,nullptr },  // Inst #509 = UMULri
1226
  { 510,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList10, OperandInfo14, -1 ,nullptr },  // Inst #510 = UMULrr
1227
  { 511,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #511 = UNIMP
1228
  { 512,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #512 = V9FCMPD
1229
  { 513,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #513 = V9FCMPED
1230
  { 514,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #514 = V9FCMPEQ
1231
  { 515,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #515 = V9FCMPES
1232
  { 516,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #516 = V9FCMPQ
1233
  { 517,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #517 = V9FCMPS
1234
  { 518,  5,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #518 = V9FMOVD_FCC
1235
  { 519,  5,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #519 = V9FMOVQ_FCC
1236
  { 520,  5,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #520 = V9FMOVS_FCC
1237
  { 521,  5,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #521 = V9MOVFCCri
1238
  { 522,  5,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #522 = V9MOVFCCrr
1239
  { 523,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #523 = WRASRri
1240
  { 524,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #524 = WRASRrr
1241
  { 525,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #525 = WRPRri
1242
  { 526,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #526 = WRPRrr
1243
  { 527,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo27, -1 ,nullptr },  // Inst #527 = WRPSRri
1244
  { 528,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo28, -1 ,nullptr },  // Inst #528 = WRPSRrr
1245
  { 529,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList8, OperandInfo27, -1 ,nullptr },  // Inst #529 = WRTBRri
1246
  { 530,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList8, OperandInfo28, -1 ,nullptr },  // Inst #530 = WRTBRrr
1247
  { 531,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList9, OperandInfo27, -1 ,nullptr },  // Inst #531 = WRWIMri
1248
  { 532,  2,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList9, OperandInfo28, -1 ,nullptr },  // Inst #532 = WRWIMrr
1249
  { 533,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #533 = XMULX
1250
  { 534,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #534 = XMULXHI
1251
  { 535,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #535 = XNORCCri
1252
  { 536,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #536 = XNORCCrr
1253
  { 537,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #537 = XNORXrr
1254
  { 538,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #538 = XNORri
1255
  { 539,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #539 = XNORrr
1256
  { 540,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #540 = XORCCri
1257
  { 541,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #541 = XORCCrr
1258
  { 542,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #542 = XORXri
1259
  { 543,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #543 = XORXrr
1260
  { 544,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #544 = XORri
1261
  { 545,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #545 = XORrr
1262
};
1263
1264
11.8k
static inline void InitSparcMCInstrInfo(MCInstrInfo *II) {
1265
11.8k
  II->InitMCInstrInfo(SparcInsts, NULL, NULL, 546);
1266
11.8k
}
1267
1268
} // end llvm namespace 
1269
#endif // GET_INSTRINFO_MC_DESC
1270
1271
1272
#ifdef GET_INSTRINFO_HEADER
1273
#undef GET_INSTRINFO_HEADER
1274
namespace llvm_ks {
1275
struct SparcGenInstrInfo : public TargetInstrInfo {
1276
  explicit SparcGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1);
1277
  ~SparcGenInstrInfo() override {}
1278
};
1279
} // end llvm namespace 
1280
#endif // GET_INSTRINFO_HEADER
1281
1282
1283
#ifdef GET_INSTRINFO_OPERAND_ENUM
1284
#undef GET_INSTRINFO_OPERAND_ENUM
1285
namespace llvm_ks {
1286
namespace SP {
1287
namespace OpName { 
1288
enum {
1289
OPERAND_LAST
1290
};
1291
} // end namespace OpName
1292
} // end namespace SP
1293
} // end namespace llvm_ks
1294
#endif //GET_INSTRINFO_OPERAND_ENUM
1295
#ifdef GET_INSTRINFO_NAMED_OPS
1296
#undef GET_INSTRINFO_NAMED_OPS
1297
namespace llvm_ks {
1298
namespace SP {
1299
LLVM_READONLY
1300
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
1301
  return -1;
1302
}
1303
} // end namespace SP
1304
} // end namespace llvm_ks
1305
#endif //GET_INSTRINFO_NAMED_OPS
1306
1307
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
1308
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
1309
namespace llvm_ks {
1310
namespace SP {
1311
namespace OpTypes { 
1312
enum OperandType {
1313
  CCOp = 0,
1314
  MEMri = 1,
1315
  MEMrr = 2,
1316
  TLSSym = 3,
1317
  bprtarget = 4,
1318
  bprtarget16 = 5,
1319
  brtarget = 6,
1320
  calltarget = 7,
1321
  f32imm = 8,
1322
  f64imm = 9,
1323
  getPCX = 10,
1324
  i16imm = 11,
1325
  i1imm = 12,
1326
  i32imm = 13,
1327
  i64imm = 14,
1328
  i8imm = 15,
1329
  simm13Op = 16,
1330
  OPERAND_TYPE_LIST_END
1331
};
1332
} // end namespace OpTypes
1333
} // end namespace SP
1334
} // end namespace llvm_ks
1335
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM