Coverage Report

Created: 2025-07-15 06:22

/src/keystone/llvm/lib/Target/SystemZ/SystemZGenInstrInfo.inc
Line
Count
Source
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_INSTRINFO_ENUM
11
#undef GET_INSTRINFO_ENUM
12
namespace llvm_ks {
13
14
namespace SystemZ {
15
  enum {
16
    PHI = 0,
17
    INLINEASM = 1,
18
    CFI_INSTRUCTION = 2,
19
    EH_LABEL  = 3,
20
    GC_LABEL  = 4,
21
    KILL  = 5,
22
    EXTRACT_SUBREG  = 6,
23
    INSERT_SUBREG = 7,
24
    IMPLICIT_DEF  = 8,
25
    SUBREG_TO_REG = 9,
26
    COPY_TO_REGCLASS  = 10,
27
    DBG_VALUE = 11,
28
    REG_SEQUENCE  = 12,
29
    COPY  = 13,
30
    BUNDLE  = 14,
31
    LIFETIME_START  = 15,
32
    LIFETIME_END  = 16,
33
    STACKMAP  = 17,
34
    PATCHPOINT  = 18,
35
    LOAD_STACK_GUARD  = 19,
36
    STATEPOINT  = 20,
37
    LOCAL_ESCAPE  = 21,
38
    FAULTING_LOAD_OP  = 22,
39
    G_ADD = 23,
40
    A = 24,
41
    ADB = 25,
42
    ADBR  = 26,
43
    ADJCALLSTACKDOWN  = 27,
44
    ADJCALLSTACKUP  = 28,
45
    ADJDYNALLOC = 29,
46
    AEB = 30,
47
    AEBR  = 31,
48
    AEXT128_64  = 32,
49
    AFI = 33,
50
    AFIMux  = 34,
51
    AG  = 35,
52
    AGF = 36,
53
    AGFI  = 37,
54
    AGFR  = 38,
55
    AGHI  = 39,
56
    AGHIK = 40,
57
    AGR = 41,
58
    AGRK  = 42,
59
    AGSI  = 43,
60
    AH  = 44,
61
    AHI = 45,
62
    AHIK  = 46,
63
    AHIMux  = 47,
64
    AHIMuxK = 48,
65
    AHY = 49,
66
    AIH = 50,
67
    AL  = 51,
68
    ALC = 52,
69
    ALCG  = 53,
70
    ALCGR = 54,
71
    ALCR  = 55,
72
    ALFI  = 56,
73
    ALG = 57,
74
    ALGF  = 58,
75
    ALGFI = 59,
76
    ALGFR = 60,
77
    ALGHSIK = 61,
78
    ALGR  = 62,
79
    ALGRK = 63,
80
    ALHSIK  = 64,
81
    ALR = 65,
82
    ALRK  = 66,
83
    ALY = 67,
84
    AR  = 68,
85
    ARK = 69,
86
    ASI = 70,
87
    ATOMIC_CMP_SWAPW  = 71,
88
    ATOMIC_LOADW_AFI  = 72,
89
    ATOMIC_LOADW_AR = 73,
90
    ATOMIC_LOADW_MAX  = 74,
91
    ATOMIC_LOADW_MIN  = 75,
92
    ATOMIC_LOADW_NILH = 76,
93
    ATOMIC_LOADW_NILHi  = 77,
94
    ATOMIC_LOADW_NR = 78,
95
    ATOMIC_LOADW_NRi  = 79,
96
    ATOMIC_LOADW_OILH = 80,
97
    ATOMIC_LOADW_OR = 81,
98
    ATOMIC_LOADW_SR = 82,
99
    ATOMIC_LOADW_UMAX = 83,
100
    ATOMIC_LOADW_UMIN = 84,
101
    ATOMIC_LOADW_XILF = 85,
102
    ATOMIC_LOADW_XR = 86,
103
    ATOMIC_LOAD_AFI = 87,
104
    ATOMIC_LOAD_AGFI  = 88,
105
    ATOMIC_LOAD_AGHI  = 89,
106
    ATOMIC_LOAD_AGR = 90,
107
    ATOMIC_LOAD_AHI = 91,
108
    ATOMIC_LOAD_AR  = 92,
109
    ATOMIC_LOAD_MAX_32  = 93,
110
    ATOMIC_LOAD_MAX_64  = 94,
111
    ATOMIC_LOAD_MIN_32  = 95,
112
    ATOMIC_LOAD_MIN_64  = 96,
113
    ATOMIC_LOAD_NGR = 97,
114
    ATOMIC_LOAD_NGRi  = 98,
115
    ATOMIC_LOAD_NIHF64  = 99,
116
    ATOMIC_LOAD_NIHF64i = 100,
117
    ATOMIC_LOAD_NIHH64  = 101,
118
    ATOMIC_LOAD_NIHH64i = 102,
119
    ATOMIC_LOAD_NIHL64  = 103,
120
    ATOMIC_LOAD_NIHL64i = 104,
121
    ATOMIC_LOAD_NILF  = 105,
122
    ATOMIC_LOAD_NILF64  = 106,
123
    ATOMIC_LOAD_NILF64i = 107,
124
    ATOMIC_LOAD_NILFi = 108,
125
    ATOMIC_LOAD_NILH  = 109,
126
    ATOMIC_LOAD_NILH64  = 110,
127
    ATOMIC_LOAD_NILH64i = 111,
128
    ATOMIC_LOAD_NILHi = 112,
129
    ATOMIC_LOAD_NILL  = 113,
130
    ATOMIC_LOAD_NILL64  = 114,
131
    ATOMIC_LOAD_NILL64i = 115,
132
    ATOMIC_LOAD_NILLi = 116,
133
    ATOMIC_LOAD_NR  = 117,
134
    ATOMIC_LOAD_NRi = 118,
135
    ATOMIC_LOAD_OGR = 119,
136
    ATOMIC_LOAD_OIHF64  = 120,
137
    ATOMIC_LOAD_OIHH64  = 121,
138
    ATOMIC_LOAD_OIHL64  = 122,
139
    ATOMIC_LOAD_OILF  = 123,
140
    ATOMIC_LOAD_OILF64  = 124,
141
    ATOMIC_LOAD_OILH  = 125,
142
    ATOMIC_LOAD_OILH64  = 126,
143
    ATOMIC_LOAD_OILL  = 127,
144
    ATOMIC_LOAD_OILL64  = 128,
145
    ATOMIC_LOAD_OR  = 129,
146
    ATOMIC_LOAD_SGR = 130,
147
    ATOMIC_LOAD_SR  = 131,
148
    ATOMIC_LOAD_UMAX_32 = 132,
149
    ATOMIC_LOAD_UMAX_64 = 133,
150
    ATOMIC_LOAD_UMIN_32 = 134,
151
    ATOMIC_LOAD_UMIN_64 = 135,
152
    ATOMIC_LOAD_XGR = 136,
153
    ATOMIC_LOAD_XIHF64  = 137,
154
    ATOMIC_LOAD_XILF  = 138,
155
    ATOMIC_LOAD_XILF64  = 139,
156
    ATOMIC_LOAD_XR  = 140,
157
    ATOMIC_SWAPW  = 141,
158
    ATOMIC_SWAP_32  = 142,
159
    ATOMIC_SWAP_64  = 143,
160
    AXBR  = 144,
161
    AY  = 145,
162
    AsmBCR  = 146,
163
    AsmBRC  = 147,
164
    AsmBRCL = 148,
165
    AsmCGIJ = 149,
166
    AsmCGRJ = 150,
167
    AsmCIJ  = 151,
168
    AsmCLGIJ  = 152,
169
    AsmCLGRJ  = 153,
170
    AsmCLIJ = 154,
171
    AsmCLRJ = 155,
172
    AsmCRJ  = 156,
173
    AsmEBR  = 157,
174
    AsmEJ = 158,
175
    AsmEJG  = 159,
176
    AsmELOC = 160,
177
    AsmELOCG  = 161,
178
    AsmELOCGR = 162,
179
    AsmELOCR  = 163,
180
    AsmESTOC  = 164,
181
    AsmESTOCG = 165,
182
    AsmHBR  = 166,
183
    AsmHEBR = 167,
184
    AsmHEJ  = 168,
185
    AsmHEJG = 169,
186
    AsmHELOC  = 170,
187
    AsmHELOCG = 171,
188
    AsmHELOCGR  = 172,
189
    AsmHELOCR = 173,
190
    AsmHESTOC = 174,
191
    AsmHESTOCG  = 175,
192
    AsmHJ = 176,
193
    AsmHJG  = 177,
194
    AsmHLOC = 178,
195
    AsmHLOCG  = 179,
196
    AsmHLOCGR = 180,
197
    AsmHLOCR  = 181,
198
    AsmHSTOC  = 182,
199
    AsmHSTOCG = 183,
200
    AsmJEAltCGI = 184,
201
    AsmJEAltCGR = 185,
202
    AsmJEAltCI  = 186,
203
    AsmJEAltCLGI  = 187,
204
    AsmJEAltCLGR  = 188,
205
    AsmJEAltCLI = 189,
206
    AsmJEAltCLR = 190,
207
    AsmJEAltCR  = 191,
208
    AsmJECGI  = 192,
209
    AsmJECGR  = 193,
210
    AsmJECI = 194,
211
    AsmJECLGI = 195,
212
    AsmJECLGR = 196,
213
    AsmJECLI  = 197,
214
    AsmJECLR  = 198,
215
    AsmJECR = 199,
216
    AsmJHAltCGI = 200,
217
    AsmJHAltCGR = 201,
218
    AsmJHAltCI  = 202,
219
    AsmJHAltCLGI  = 203,
220
    AsmJHAltCLGR  = 204,
221
    AsmJHAltCLI = 205,
222
    AsmJHAltCLR = 206,
223
    AsmJHAltCR  = 207,
224
    AsmJHCGI  = 208,
225
    AsmJHCGR  = 209,
226
    AsmJHCI = 210,
227
    AsmJHCLGI = 211,
228
    AsmJHCLGR = 212,
229
    AsmJHCLI  = 213,
230
    AsmJHCLR  = 214,
231
    AsmJHCR = 215,
232
    AsmJHEAltCGI  = 216,
233
    AsmJHEAltCGR  = 217,
234
    AsmJHEAltCI = 218,
235
    AsmJHEAltCLGI = 219,
236
    AsmJHEAltCLGR = 220,
237
    AsmJHEAltCLI  = 221,
238
    AsmJHEAltCLR  = 222,
239
    AsmJHEAltCR = 223,
240
    AsmJHECGI = 224,
241
    AsmJHECGR = 225,
242
    AsmJHECI  = 226,
243
    AsmJHECLGI  = 227,
244
    AsmJHECLGR  = 228,
245
    AsmJHECLI = 229,
246
    AsmJHECLR = 230,
247
    AsmJHECR  = 231,
248
    AsmJLAltCGI = 232,
249
    AsmJLAltCGR = 233,
250
    AsmJLAltCI  = 234,
251
    AsmJLAltCLGI  = 235,
252
    AsmJLAltCLGR  = 236,
253
    AsmJLAltCLI = 237,
254
    AsmJLAltCLR = 238,
255
    AsmJLAltCR  = 239,
256
    AsmJLCGI  = 240,
257
    AsmJLCGR  = 241,
258
    AsmJLCI = 242,
259
    AsmJLCLGI = 243,
260
    AsmJLCLGR = 244,
261
    AsmJLCLI  = 245,
262
    AsmJLCLR  = 246,
263
    AsmJLCR = 247,
264
    AsmJLEAltCGI  = 248,
265
    AsmJLEAltCGR  = 249,
266
    AsmJLEAltCI = 250,
267
    AsmJLEAltCLGI = 251,
268
    AsmJLEAltCLGR = 252,
269
    AsmJLEAltCLI  = 253,
270
    AsmJLEAltCLR  = 254,
271
    AsmJLEAltCR = 255,
272
    AsmJLECGI = 256,
273
    AsmJLECGR = 257,
274
    AsmJLECI  = 258,
275
    AsmJLECLGI  = 259,
276
    AsmJLECLGR  = 260,
277
    AsmJLECLI = 261,
278
    AsmJLECLR = 262,
279
    AsmJLECR  = 263,
280
    AsmJLHAltCGI  = 264,
281
    AsmJLHAltCGR  = 265,
282
    AsmJLHAltCI = 266,
283
    AsmJLHAltCLGI = 267,
284
    AsmJLHAltCLGR = 268,
285
    AsmJLHAltCLI  = 269,
286
    AsmJLHAltCLR  = 270,
287
    AsmJLHAltCR = 271,
288
    AsmJLHCGI = 272,
289
    AsmJLHCGR = 273,
290
    AsmJLHCI  = 274,
291
    AsmJLHCLGI  = 275,
292
    AsmJLHCLGR  = 276,
293
    AsmJLHCLI = 277,
294
    AsmJLHCLR = 278,
295
    AsmJLHCR  = 279,
296
    AsmLBR  = 280,
297
    AsmLEBR = 281,
298
    AsmLEJ  = 282,
299
    AsmLEJG = 283,
300
    AsmLELOC  = 284,
301
    AsmLELOCG = 285,
302
    AsmLELOCGR  = 286,
303
    AsmLELOCR = 287,
304
    AsmLESTOC = 288,
305
    AsmLESTOCG  = 289,
306
    AsmLHBR = 290,
307
    AsmLHJ  = 291,
308
    AsmLHJG = 292,
309
    AsmLHLOC  = 293,
310
    AsmLHLOCG = 294,
311
    AsmLHLOCGR  = 295,
312
    AsmLHLOCR = 296,
313
    AsmLHSTOC = 297,
314
    AsmLHSTOCG  = 298,
315
    AsmLJ = 299,
316
    AsmLJG  = 300,
317
    AsmLLOC = 301,
318
    AsmLLOCG  = 302,
319
    AsmLLOCGR = 303,
320
    AsmLLOCR  = 304,
321
    AsmLOC  = 305,
322
    AsmLOCG = 306,
323
    AsmLOCGR  = 307,
324
    AsmLOCR = 308,
325
    AsmLSTOC  = 309,
326
    AsmLSTOCG = 310,
327
    AsmNEBR = 311,
328
    AsmNEJ  = 312,
329
    AsmNEJG = 313,
330
    AsmNELOC  = 314,
331
    AsmNELOCG = 315,
332
    AsmNELOCGR  = 316,
333
    AsmNELOCR = 317,
334
    AsmNESTOC = 318,
335
    AsmNESTOCG  = 319,
336
    AsmNHBR = 320,
337
    AsmNHEBR  = 321,
338
    AsmNHEJ = 322,
339
    AsmNHEJG  = 323,
340
    AsmNHELOC = 324,
341
    AsmNHELOCG  = 325,
342
    AsmNHELOCGR = 326,
343
    AsmNHELOCR  = 327,
344
    AsmNHESTOC  = 328,
345
    AsmNHESTOCG = 329,
346
    AsmNHJ  = 330,
347
    AsmNHJG = 331,
348
    AsmNHLOC  = 332,
349
    AsmNHLOCG = 333,
350
    AsmNHLOCGR  = 334,
351
    AsmNHLOCR = 335,
352
    AsmNHSTOC = 336,
353
    AsmNHSTOCG  = 337,
354
    AsmNLBR = 338,
355
    AsmNLEBR  = 339,
356
    AsmNLEJ = 340,
357
    AsmNLEJG  = 341,
358
    AsmNLELOC = 342,
359
    AsmNLELOCG  = 343,
360
    AsmNLELOCGR = 344,
361
    AsmNLELOCR  = 345,
362
    AsmNLESTOC  = 346,
363
    AsmNLESTOCG = 347,
364
    AsmNLHBR  = 348,
365
    AsmNLHJ = 349,
366
    AsmNLHJG  = 350,
367
    AsmNLHLOC = 351,
368
    AsmNLHLOCG  = 352,
369
    AsmNLHLOCGR = 353,
370
    AsmNLHLOCR  = 354,
371
    AsmNLHSTOC  = 355,
372
    AsmNLHSTOCG = 356,
373
    AsmNLJ  = 357,
374
    AsmNLJG = 358,
375
    AsmNLLOC  = 359,
376
    AsmNLLOCG = 360,
377
    AsmNLLOCGR  = 361,
378
    AsmNLLOCR = 362,
379
    AsmNLSTOC = 363,
380
    AsmNLSTOCG  = 364,
381
    AsmNOBR = 365,
382
    AsmNOJ  = 366,
383
    AsmNOJG = 367,
384
    AsmNOLOC  = 368,
385
    AsmNOLOCG = 369,
386
    AsmNOLOCGR  = 370,
387
    AsmNOLOCR = 371,
388
    AsmNOSTOC = 372,
389
    AsmNOSTOCG  = 373,
390
    AsmOBR  = 374,
391
    AsmOJ = 375,
392
    AsmOJG  = 376,
393
    AsmOLOC = 377,
394
    AsmOLOCG  = 378,
395
    AsmOLOCGR = 379,
396
    AsmOLOCR  = 380,
397
    AsmOSTOC  = 381,
398
    AsmOSTOCG = 382,
399
    AsmSTOC = 383,
400
    AsmSTOCG  = 384,
401
    BASR  = 385,
402
    BR  = 386,
403
    BRAS  = 387,
404
    BRASL = 388,
405
    BRC = 389,
406
    BRCL  = 390,
407
    BRCT  = 391,
408
    BRCTG = 392,
409
    C = 393,
410
    CDB = 394,
411
    CDBR  = 395,
412
    CDFBR = 396,
413
    CDGBR = 397,
414
    CDLFBR  = 398,
415
    CDLGBR  = 399,
416
    CEB = 400,
417
    CEBR  = 401,
418
    CEFBR = 402,
419
    CEGBR = 403,
420
    CELFBR  = 404,
421
    CELGBR  = 405,
422
    CFDBR = 406,
423
    CFEBR = 407,
424
    CFI = 408,
425
    CFIMux  = 409,
426
    CFXBR = 410,
427
    CG  = 411,
428
    CGDBR = 412,
429
    CGEBR = 413,
430
    CGF = 414,
431
    CGFI  = 415,
432
    CGFR  = 416,
433
    CGFRL = 417,
434
    CGH = 418,
435
    CGHI  = 419,
436
    CGHRL = 420,
437
    CGHSI = 421,
438
    CGIJ  = 422,
439
    CGR = 423,
440
    CGRJ  = 424,
441
    CGRL  = 425,
442
    CGXBR = 426,
443
    CH  = 427,
444
    CHF = 428,
445
    CHHSI = 429,
446
    CHI = 430,
447
    CHRL  = 431,
448
    CHSI  = 432,
449
    CHY = 433,
450
    CIH = 434,
451
    CIJ = 435,
452
    CL  = 436,
453
    CLC = 437,
454
    CLCLoop = 438,
455
    CLCSequence = 439,
456
    CLFDBR  = 440,
457
    CLFEBR  = 441,
458
    CLFHSI  = 442,
459
    CLFI  = 443,
460
    CLFIMux = 444,
461
    CLFXBR  = 445,
462
    CLG = 446,
463
    CLGDBR  = 447,
464
    CLGEBR  = 448,
465
    CLGF  = 449,
466
    CLGFI = 450,
467
    CLGFR = 451,
468
    CLGFRL  = 452,
469
    CLGHRL  = 453,
470
    CLGHSI  = 454,
471
    CLGIJ = 455,
472
    CLGR  = 456,
473
    CLGRJ = 457,
474
    CLGRL = 458,
475
    CLGXBR  = 459,
476
    CLHF  = 460,
477
    CLHHSI  = 461,
478
    CLHRL = 462,
479
    CLI = 463,
480
    CLIH  = 464,
481
    CLIJ  = 465,
482
    CLIY  = 466,
483
    CLMux = 467,
484
    CLR = 468,
485
    CLRJ  = 469,
486
    CLRL  = 470,
487
    CLST  = 471,
488
    CLSTLoop  = 472,
489
    CLY = 473,
490
    CMux  = 474,
491
    CPSDRdd = 475,
492
    CPSDRds = 476,
493
    CPSDRsd = 477,
494
    CPSDRss = 478,
495
    CR  = 479,
496
    CRJ = 480,
497
    CRL = 481,
498
    CS  = 482,
499
    CSG = 483,
500
    CSY = 484,
501
    CXBR  = 485,
502
    CXFBR = 486,
503
    CXGBR = 487,
504
    CXLFBR  = 488,
505
    CXLGBR  = 489,
506
    CY  = 490,
507
    CallBASR  = 491,
508
    CallBR  = 492,
509
    CallBRASL = 493,
510
    CallJG  = 494,
511
    CondStore16 = 495,
512
    CondStore16Inv  = 496,
513
    CondStore16Mux  = 497,
514
    CondStore16MuxInv = 498,
515
    CondStore32 = 499,
516
    CondStore32Inv  = 500,
517
    CondStore64 = 501,
518
    CondStore64Inv  = 502,
519
    CondStore8  = 503,
520
    CondStore8Inv = 504,
521
    CondStore8Mux = 505,
522
    CondStore8MuxInv  = 506,
523
    CondStoreF32  = 507,
524
    CondStoreF32Inv = 508,
525
    CondStoreF64  = 509,
526
    CondStoreF64Inv = 510,
527
    DDB = 511,
528
    DDBR  = 512,
529
    DEB = 513,
530
    DEBR  = 514,
531
    DL  = 515,
532
    DLG = 516,
533
    DLGR  = 517,
534
    DLR = 518,
535
    DSG = 519,
536
    DSGF  = 520,
537
    DSGFR = 521,
538
    DSGR  = 522,
539
    DXBR  = 523,
540
    EAR = 524,
541
    ETND  = 525,
542
    FIDBR = 526,
543
    FIDBRA  = 527,
544
    FIEBR = 528,
545
    FIEBRA  = 529,
546
    FIXBR = 530,
547
    FIXBRA  = 531,
548
    FLOGR = 532,
549
    GOT = 533,
550
    IC  = 534,
551
    IC32  = 535,
552
    IC32Y = 536,
553
    ICY = 537,
554
    IIFMux  = 538,
555
    IIHF  = 539,
556
    IIHF64  = 540,
557
    IIHH  = 541,
558
    IIHH64  = 542,
559
    IIHL  = 543,
560
    IIHL64  = 544,
561
    IIHMux  = 545,
562
    IILF  = 546,
563
    IILF64  = 547,
564
    IILH  = 548,
565
    IILH64  = 549,
566
    IILL  = 550,
567
    IILL64  = 551,
568
    IILMux  = 552,
569
    IPM = 553,
570
    J = 554,
571
    JG  = 555,
572
    L = 556,
573
    L128  = 557,
574
    LA  = 558,
575
    LAA = 559,
576
    LAAG  = 560,
577
    LAAL  = 561,
578
    LAALG = 562,
579
    LAN = 563,
580
    LANG  = 564,
581
    LAO = 565,
582
    LAOG  = 566,
583
    LARL  = 567,
584
    LAX = 568,
585
    LAXG  = 569,
586
    LAY = 570,
587
    LB  = 571,
588
    LBH = 572,
589
    LBMux = 573,
590
    LBR = 574,
591
    LCBB  = 575,
592
    LCDBR = 576,
593
    LCDFR = 577,
594
    LCDFR_32  = 578,
595
    LCEBR = 579,
596
    LCGFR = 580,
597
    LCGR  = 581,
598
    LCR = 582,
599
    LCXBR = 583,
600
    LD  = 584,
601
    LDE32 = 585,
602
    LDEB  = 586,
603
    LDEBR = 587,
604
    LDGR  = 588,
605
    LDR = 589,
606
    LDXBR = 590,
607
    LDXBRA  = 591,
608
    LDY = 592,
609
    LE  = 593,
610
    LEDBR = 594,
611
    LEDBRA  = 595,
612
    LEFR  = 596,
613
    LER = 597,
614
    LEXBR = 598,
615
    LEXBRA  = 599,
616
    LEY = 600,
617
    LFER  = 601,
618
    LFH = 602,
619
    LG  = 603,
620
    LGB = 604,
621
    LGBR  = 605,
622
    LGDR  = 606,
623
    LGF = 607,
624
    LGFI  = 608,
625
    LGFR  = 609,
626
    LGFRL = 610,
627
    LGH = 611,
628
    LGHI  = 612,
629
    LGHR  = 613,
630
    LGHRL = 614,
631
    LGR = 615,
632
    LGRL  = 616,
633
    LH  = 617,
634
    LHH = 618,
635
    LHI = 619,
636
    LHIMux  = 620,
637
    LHMux = 621,
638
    LHR = 622,
639
    LHRL  = 623,
640
    LHY = 624,
641
    LLC = 625,
642
    LLCH  = 626,
643
    LLCMux  = 627,
644
    LLCR  = 628,
645
    LLCRMux = 629,
646
    LLGC  = 630,
647
    LLGCR = 631,
648
    LLGF  = 632,
649
    LLGFR = 633,
650
    LLGFRL  = 634,
651
    LLGH  = 635,
652
    LLGHR = 636,
653
    LLGHRL  = 637,
654
    LLH = 638,
655
    LLHH  = 639,
656
    LLHMux  = 640,
657
    LLHR  = 641,
658
    LLHRL = 642,
659
    LLHRMux = 643,
660
    LLIHF = 644,
661
    LLIHH = 645,
662
    LLIHL = 646,
663
    LLILF = 647,
664
    LLILH = 648,
665
    LLILL = 649,
666
    LMG = 650,
667
    LMux  = 651,
668
    LNDBR = 652,
669
    LNDFR = 653,
670
    LNDFR_32  = 654,
671
    LNEBR = 655,
672
    LNGFR = 656,
673
    LNGR  = 657,
674
    LNR = 658,
675
    LNXBR = 659,
676
    LOC = 660,
677
    LOCG  = 661,
678
    LOCGR = 662,
679
    LOCR  = 663,
680
    LPDBR = 664,
681
    LPDFR = 665,
682
    LPDFR_32  = 666,
683
    LPEBR = 667,
684
    LPGFR = 668,
685
    LPGR  = 669,
686
    LPR = 670,
687
    LPXBR = 671,
688
    LR  = 672,
689
    LRL = 673,
690
    LRMux = 674,
691
    LRV = 675,
692
    LRVG  = 676,
693
    LRVGR = 677,
694
    LRVR  = 678,
695
    LT  = 679,
696
    LTDBR = 680,
697
    LTDBRCompare  = 681,
698
    LTDBRCompare_VecPseudo  = 682,
699
    LTEBR = 683,
700
    LTEBRCompare  = 684,
701
    LTEBRCompare_VecPseudo  = 685,
702
    LTG = 686,
703
    LTGF  = 687,
704
    LTGFR = 688,
705
    LTGR  = 689,
706
    LTR = 690,
707
    LTXBR = 691,
708
    LTXBRCompare  = 692,
709
    LTXBRCompare_VecPseudo  = 693,
710
    LX  = 694,
711
    LXDB  = 695,
712
    LXDBR = 696,
713
    LXEB  = 697,
714
    LXEBR = 698,
715
    LXR = 699,
716
    LY  = 700,
717
    LZDR  = 701,
718
    LZER  = 702,
719
    LZXR  = 703,
720
    MADB  = 704,
721
    MADBR = 705,
722
    MAEB  = 706,
723
    MAEBR = 707,
724
    MDB = 708,
725
    MDBR  = 709,
726
    MDEB  = 710,
727
    MDEBR = 711,
728
    MEEB  = 712,
729
    MEEBR = 713,
730
    MGHI  = 714,
731
    MH  = 715,
732
    MHI = 716,
733
    MHY = 717,
734
    MLG = 718,
735
    MLGR  = 719,
736
    MS  = 720,
737
    MSDB  = 721,
738
    MSDBR = 722,
739
    MSEB  = 723,
740
    MSEBR = 724,
741
    MSFI  = 725,
742
    MSG = 726,
743
    MSGF  = 727,
744
    MSGFI = 728,
745
    MSGFR = 729,
746
    MSGR  = 730,
747
    MSR = 731,
748
    MSY = 732,
749
    MVC = 733,
750
    MVCLoop = 734,
751
    MVCSequence = 735,
752
    MVGHI = 736,
753
    MVHHI = 737,
754
    MVHI  = 738,
755
    MVI = 739,
756
    MVIY  = 740,
757
    MVST  = 741,
758
    MVSTLoop  = 742,
759
    MXBR  = 743,
760
    MXDB  = 744,
761
    MXDBR = 745,
762
    N = 746,
763
    NC  = 747,
764
    NCLoop  = 748,
765
    NCSequence  = 749,
766
    NG  = 750,
767
    NGR = 751,
768
    NGRK  = 752,
769
    NI  = 753,
770
    NIFMux  = 754,
771
    NIHF  = 755,
772
    NIHF64  = 756,
773
    NIHH  = 757,
774
    NIHH64  = 758,
775
    NIHL  = 759,
776
    NIHL64  = 760,
777
    NIHMux  = 761,
778
    NILF  = 762,
779
    NILF64  = 763,
780
    NILH  = 764,
781
    NILH64  = 765,
782
    NILL  = 766,
783
    NILL64  = 767,
784
    NILMux  = 768,
785
    NIY = 769,
786
    NR  = 770,
787
    NRK = 771,
788
    NTSTG = 772,
789
    NY  = 773,
790
    O = 774,
791
    OC  = 775,
792
    OCLoop  = 776,
793
    OCSequence  = 777,
794
    OG  = 778,
795
    OGR = 779,
796
    OGRK  = 780,
797
    OI  = 781,
798
    OIFMux  = 782,
799
    OIHF  = 783,
800
    OIHF64  = 784,
801
    OIHH  = 785,
802
    OIHH64  = 786,
803
    OIHL  = 787,
804
    OIHL64  = 788,
805
    OIHMux  = 789,
806
    OILF  = 790,
807
    OILF64  = 791,
808
    OILH  = 792,
809
    OILH64  = 793,
810
    OILL  = 794,
811
    OILL64  = 795,
812
    OILMux  = 796,
813
    OIY = 797,
814
    OR  = 798,
815
    ORK = 799,
816
    OY  = 800,
817
    PFD = 801,
818
    PFDRL = 802,
819
    POPCNT  = 803,
820
    PPA = 804,
821
    RISBG = 805,
822
    RISBG32 = 806,
823
    RISBGN  = 807,
824
    RISBHG  = 808,
825
    RISBHH  = 809,
826
    RISBHL  = 810,
827
    RISBLG  = 811,
828
    RISBLH  = 812,
829
    RISBLL  = 813,
830
    RISBMux = 814,
831
    RLL = 815,
832
    RLLG  = 816,
833
    RNSBG = 817,
834
    ROSBG = 818,
835
    RXSBG = 819,
836
    Return  = 820,
837
    S = 821,
838
    SDB = 822,
839
    SDBR  = 823,
840
    SEB = 824,
841
    SEBR  = 825,
842
    SG  = 826,
843
    SGF = 827,
844
    SGFR  = 828,
845
    SGR = 829,
846
    SGRK  = 830,
847
    SH  = 831,
848
    SHY = 832,
849
    SL  = 833,
850
    SLB = 834,
851
    SLBG  = 835,
852
    SLBGR = 836,
853
    SLBR  = 837,
854
    SLFI  = 838,
855
    SLG = 839,
856
    SLGF  = 840,
857
    SLGFI = 841,
858
    SLGFR = 842,
859
    SLGR  = 843,
860
    SLGRK = 844,
861
    SLL = 845,
862
    SLLG  = 846,
863
    SLLK  = 847,
864
    SLR = 848,
865
    SLRK  = 849,
866
    SLY = 850,
867
    SQDB  = 851,
868
    SQDBR = 852,
869
    SQEB  = 853,
870
    SQEBR = 854,
871
    SQXBR = 855,
872
    SR  = 856,
873
    SRA = 857,
874
    SRAG  = 858,
875
    SRAK  = 859,
876
    SRK = 860,
877
    SRL = 861,
878
    SRLG  = 862,
879
    SRLK  = 863,
880
    SRST  = 864,
881
    SRSTLoop  = 865,
882
    ST  = 866,
883
    ST128 = 867,
884
    STC = 868,
885
    STCH  = 869,
886
    STCK  = 870,
887
    STCKE = 871,
888
    STCKF = 872,
889
    STCMux  = 873,
890
    STCY  = 874,
891
    STD = 875,
892
    STDY  = 876,
893
    STE = 877,
894
    STEY  = 878,
895
    STFH  = 879,
896
    STFLE = 880,
897
    STG = 881,
898
    STGRL = 882,
899
    STH = 883,
900
    STHH  = 884,
901
    STHMux  = 885,
902
    STHRL = 886,
903
    STHY  = 887,
904
    STMG  = 888,
905
    STMux = 889,
906
    STOC  = 890,
907
    STOCG = 891,
908
    STRL  = 892,
909
    STRV  = 893,
910
    STRVG = 894,
911
    STX = 895,
912
    STY = 896,
913
    SXBR  = 897,
914
    SY  = 898,
915
    Select32  = 899,
916
    Select32Mux = 900,
917
    Select64  = 901,
918
    SelectF128  = 902,
919
    SelectF32 = 903,
920
    SelectF64 = 904,
921
    Serialize = 905,
922
    TABORT  = 906,
923
    TBEGIN  = 907,
924
    TBEGINC = 908,
925
    TBEGIN_nofloat  = 909,
926
    TEND  = 910,
927
    TLS_GDCALL  = 911,
928
    TLS_LDCALL  = 912,
929
    TM  = 913,
930
    TMHH  = 914,
931
    TMHH64  = 915,
932
    TMHL  = 916,
933
    TMHL64  = 917,
934
    TMHMux  = 918,
935
    TMLH  = 919,
936
    TMLH64  = 920,
937
    TMLL  = 921,
938
    TMLL64  = 922,
939
    TMLMux  = 923,
940
    TMY = 924,
941
    VAB = 925,
942
    VACCB = 926,
943
    VACCCQ  = 927,
944
    VACCF = 928,
945
    VACCG = 929,
946
    VACCH = 930,
947
    VACCQ = 931,
948
    VACQ  = 932,
949
    VAF = 933,
950
    VAG = 934,
951
    VAH = 935,
952
    VAQ = 936,
953
    VAVGB = 937,
954
    VAVGF = 938,
955
    VAVGG = 939,
956
    VAVGH = 940,
957
    VAVGLB  = 941,
958
    VAVGLF  = 942,
959
    VAVGLG  = 943,
960
    VAVGLH  = 944,
961
    VCDGB = 945,
962
    VCDLGB  = 946,
963
    VCEQB = 947,
964
    VCEQBS  = 948,
965
    VCEQF = 949,
966
    VCEQFS  = 950,
967
    VCEQG = 951,
968
    VCEQGS  = 952,
969
    VCEQH = 953,
970
    VCEQHS  = 954,
971
    VCGDB = 955,
972
    VCHB  = 956,
973
    VCHBS = 957,
974
    VCHF  = 958,
975
    VCHFS = 959,
976
    VCHG  = 960,
977
    VCHGS = 961,
978
    VCHH  = 962,
979
    VCHHS = 963,
980
    VCHLB = 964,
981
    VCHLBS  = 965,
982
    VCHLF = 966,
983
    VCHLFS  = 967,
984
    VCHLG = 968,
985
    VCHLGS  = 969,
986
    VCHLH = 970,
987
    VCHLHS  = 971,
988
    VCKSM = 972,
989
    VCLGDB  = 973,
990
    VCLZB = 974,
991
    VCLZF = 975,
992
    VCLZG = 976,
993
    VCLZH = 977,
994
    VCTZB = 978,
995
    VCTZF = 979,
996
    VCTZG = 980,
997
    VCTZH = 981,
998
    VECB  = 982,
999
    VECF  = 983,
1000
    VECG  = 984,
1001
    VECH  = 985,
1002
    VECLB = 986,
1003
    VECLF = 987,
1004
    VECLG = 988,
1005
    VECLH = 989,
1006
    VERIMB  = 990,
1007
    VERIMF  = 991,
1008
    VERIMG  = 992,
1009
    VERIMH  = 993,
1010
    VERLLB  = 994,
1011
    VERLLF  = 995,
1012
    VERLLG  = 996,
1013
    VERLLH  = 997,
1014
    VERLLVB = 998,
1015
    VERLLVF = 999,
1016
    VERLLVG = 1000,
1017
    VERLLVH = 1001,
1018
    VESLB = 1002,
1019
    VESLF = 1003,
1020
    VESLG = 1004,
1021
    VESLH = 1005,
1022
    VESLVB  = 1006,
1023
    VESLVF  = 1007,
1024
    VESLVG  = 1008,
1025
    VESLVH  = 1009,
1026
    VESRAB  = 1010,
1027
    VESRAF  = 1011,
1028
    VESRAG  = 1012,
1029
    VESRAH  = 1013,
1030
    VESRAVB = 1014,
1031
    VESRAVF = 1015,
1032
    VESRAVG = 1016,
1033
    VESRAVH = 1017,
1034
    VESRLB  = 1018,
1035
    VESRLF  = 1019,
1036
    VESRLG  = 1020,
1037
    VESRLH  = 1021,
1038
    VESRLVB = 1022,
1039
    VESRLVF = 1023,
1040
    VESRLVG = 1024,
1041
    VESRLVH = 1025,
1042
    VFADB = 1026,
1043
    VFAEB = 1027,
1044
    VFAEBS  = 1028,
1045
    VFAEF = 1029,
1046
    VFAEFS  = 1030,
1047
    VFAEH = 1031,
1048
    VFAEHS  = 1032,
1049
    VFAEZB  = 1033,
1050
    VFAEZBS = 1034,
1051
    VFAEZF  = 1035,
1052
    VFAEZFS = 1036,
1053
    VFAEZH  = 1037,
1054
    VFAEZHS = 1038,
1055
    VFCEDB  = 1039,
1056
    VFCEDBS = 1040,
1057
    VFCHDB  = 1041,
1058
    VFCHDBS = 1042,
1059
    VFCHEDB = 1043,
1060
    VFCHEDBS  = 1044,
1061
    VFDDB = 1045,
1062
    VFEEB = 1046,
1063
    VFEEBS  = 1047,
1064
    VFEEF = 1048,
1065
    VFEEFS  = 1049,
1066
    VFEEH = 1050,
1067
    VFEEHS  = 1051,
1068
    VFEEZB  = 1052,
1069
    VFEEZBS = 1053,
1070
    VFEEZF  = 1054,
1071
    VFEEZFS = 1055,
1072
    VFEEZH  = 1056,
1073
    VFEEZHS = 1057,
1074
    VFENEB  = 1058,
1075
    VFENEBS = 1059,
1076
    VFENEF  = 1060,
1077
    VFENEFS = 1061,
1078
    VFENEH  = 1062,
1079
    VFENEHS = 1063,
1080
    VFENEZB = 1064,
1081
    VFENEZBS  = 1065,
1082
    VFENEZF = 1066,
1083
    VFENEZFS  = 1067,
1084
    VFENEZH = 1068,
1085
    VFENEZHS  = 1069,
1086
    VFIDB = 1070,
1087
    VFLCDB  = 1071,
1088
    VFLNDB  = 1072,
1089
    VFLPDB  = 1073,
1090
    VFMADB  = 1074,
1091
    VFMDB = 1075,
1092
    VFMSDB  = 1076,
1093
    VFSDB = 1077,
1094
    VFSQDB  = 1078,
1095
    VFTCIDB = 1079,
1096
    VGBM  = 1080,
1097
    VGEF  = 1081,
1098
    VGEG  = 1082,
1099
    VGFMAB  = 1083,
1100
    VGFMAF  = 1084,
1101
    VGFMAG  = 1085,
1102
    VGFMAH  = 1086,
1103
    VGFMB = 1087,
1104
    VGFMF = 1088,
1105
    VGFMG = 1089,
1106
    VGFMH = 1090,
1107
    VGMB  = 1091,
1108
    VGMF  = 1092,
1109
    VGMG  = 1093,
1110
    VGMH  = 1094,
1111
    VISTRB  = 1095,
1112
    VISTRBS = 1096,
1113
    VISTRF  = 1097,
1114
    VISTRFS = 1098,
1115
    VISTRH  = 1099,
1116
    VISTRHS = 1100,
1117
    VL  = 1101,
1118
    VL32  = 1102,
1119
    VL64  = 1103,
1120
    VLBB  = 1104,
1121
    VLCB  = 1105,
1122
    VLCF  = 1106,
1123
    VLCG  = 1107,
1124
    VLCH  = 1108,
1125
    VLDEB = 1109,
1126
    VLEB  = 1110,
1127
    VLEDB = 1111,
1128
    VLEF  = 1112,
1129
    VLEG  = 1113,
1130
    VLEH  = 1114,
1131
    VLEIB = 1115,
1132
    VLEIF = 1116,
1133
    VLEIG = 1117,
1134
    VLEIH = 1118,
1135
    VLGVB = 1119,
1136
    VLGVF = 1120,
1137
    VLGVG = 1121,
1138
    VLGVH = 1122,
1139
    VLL = 1123,
1140
    VLLEZB  = 1124,
1141
    VLLEZF  = 1125,
1142
    VLLEZG  = 1126,
1143
    VLLEZH  = 1127,
1144
    VLM = 1128,
1145
    VLPB  = 1129,
1146
    VLPF  = 1130,
1147
    VLPG  = 1131,
1148
    VLPH  = 1132,
1149
    VLR = 1133,
1150
    VLR32 = 1134,
1151
    VLR64 = 1135,
1152
    VLREPB  = 1136,
1153
    VLREPF  = 1137,
1154
    VLREPG  = 1138,
1155
    VLREPH  = 1139,
1156
    VLVGB = 1140,
1157
    VLVGF = 1141,
1158
    VLVGG = 1142,
1159
    VLVGH = 1143,
1160
    VLVGP = 1144,
1161
    VLVGP32 = 1145,
1162
    VMAEB = 1146,
1163
    VMAEF = 1147,
1164
    VMAEH = 1148,
1165
    VMAHB = 1149,
1166
    VMAHF = 1150,
1167
    VMAHH = 1151,
1168
    VMALB = 1152,
1169
    VMALEB  = 1153,
1170
    VMALEF  = 1154,
1171
    VMALEH  = 1155,
1172
    VMALF = 1156,
1173
    VMALHB  = 1157,
1174
    VMALHF  = 1158,
1175
    VMALHH  = 1159,
1176
    VMALHW  = 1160,
1177
    VMALOB  = 1161,
1178
    VMALOF  = 1162,
1179
    VMALOH  = 1163,
1180
    VMAOB = 1164,
1181
    VMAOF = 1165,
1182
    VMAOH = 1166,
1183
    VMEB  = 1167,
1184
    VMEF  = 1168,
1185
    VMEH  = 1169,
1186
    VMHB  = 1170,
1187
    VMHF  = 1171,
1188
    VMHH  = 1172,
1189
    VMLB  = 1173,
1190
    VMLEB = 1174,
1191
    VMLEF = 1175,
1192
    VMLEH = 1176,
1193
    VMLF  = 1177,
1194
    VMLHB = 1178,
1195
    VMLHF = 1179,
1196
    VMLHH = 1180,
1197
    VMLHW = 1181,
1198
    VMLOB = 1182,
1199
    VMLOF = 1183,
1200
    VMLOH = 1184,
1201
    VMNB  = 1185,
1202
    VMNF  = 1186,
1203
    VMNG  = 1187,
1204
    VMNH  = 1188,
1205
    VMNLB = 1189,
1206
    VMNLF = 1190,
1207
    VMNLG = 1191,
1208
    VMNLH = 1192,
1209
    VMOB  = 1193,
1210
    VMOF  = 1194,
1211
    VMOH  = 1195,
1212
    VMRHB = 1196,
1213
    VMRHF = 1197,
1214
    VMRHG = 1198,
1215
    VMRHH = 1199,
1216
    VMRLB = 1200,
1217
    VMRLF = 1201,
1218
    VMRLG = 1202,
1219
    VMRLH = 1203,
1220
    VMXB  = 1204,
1221
    VMXF  = 1205,
1222
    VMXG  = 1206,
1223
    VMXH  = 1207,
1224
    VMXLB = 1208,
1225
    VMXLF = 1209,
1226
    VMXLG = 1210,
1227
    VMXLH = 1211,
1228
    VN  = 1212,
1229
    VNC = 1213,
1230
    VNO = 1214,
1231
    VO  = 1215,
1232
    VONE  = 1216,
1233
    VPDI  = 1217,
1234
    VPERM = 1218,
1235
    VPKF  = 1219,
1236
    VPKG  = 1220,
1237
    VPKH  = 1221,
1238
    VPKLSF  = 1222,
1239
    VPKLSFS = 1223,
1240
    VPKLSG  = 1224,
1241
    VPKLSGS = 1225,
1242
    VPKLSH  = 1226,
1243
    VPKLSHS = 1227,
1244
    VPKSF = 1228,
1245
    VPKSFS  = 1229,
1246
    VPKSG = 1230,
1247
    VPKSGS  = 1231,
1248
    VPKSH = 1232,
1249
    VPKSHS  = 1233,
1250
    VPOPCT  = 1234,
1251
    VREPB = 1235,
1252
    VREPF = 1236,
1253
    VREPG = 1237,
1254
    VREPH = 1238,
1255
    VREPIB  = 1239,
1256
    VREPIF  = 1240,
1257
    VREPIG  = 1241,
1258
    VREPIH  = 1242,
1259
    VSB = 1243,
1260
    VSBCBIQ = 1244,
1261
    VSBIQ = 1245,
1262
    VSCBIB  = 1246,
1263
    VSCBIF  = 1247,
1264
    VSCBIG  = 1248,
1265
    VSCBIH  = 1249,
1266
    VSCBIQ  = 1250,
1267
    VSCEF = 1251,
1268
    VSCEG = 1252,
1269
    VSEGB = 1253,
1270
    VSEGF = 1254,
1271
    VSEGH = 1255,
1272
    VSEL  = 1256,
1273
    VSF = 1257,
1274
    VSG = 1258,
1275
    VSH = 1259,
1276
    VSL = 1260,
1277
    VSLB  = 1261,
1278
    VSLDB = 1262,
1279
    VSQ = 1263,
1280
    VSRA  = 1264,
1281
    VSRAB = 1265,
1282
    VSRL  = 1266,
1283
    VSRLB = 1267,
1284
    VST = 1268,
1285
    VST32 = 1269,
1286
    VST64 = 1270,
1287
    VSTEB = 1271,
1288
    VSTEF = 1272,
1289
    VSTEG = 1273,
1290
    VSTEH = 1274,
1291
    VSTL  = 1275,
1292
    VSTM  = 1276,
1293
    VSTRCB  = 1277,
1294
    VSTRCBS = 1278,
1295
    VSTRCF  = 1279,
1296
    VSTRCFS = 1280,
1297
    VSTRCH  = 1281,
1298
    VSTRCHS = 1282,
1299
    VSTRCZB = 1283,
1300
    VSTRCZBS  = 1284,
1301
    VSTRCZF = 1285,
1302
    VSTRCZFS  = 1286,
1303
    VSTRCZH = 1287,
1304
    VSTRCZHS  = 1288,
1305
    VSUMB = 1289,
1306
    VSUMGF  = 1290,
1307
    VSUMGH  = 1291,
1308
    VSUMH = 1292,
1309
    VSUMQF  = 1293,
1310
    VSUMQG  = 1294,
1311
    VTM = 1295,
1312
    VUPHB = 1296,
1313
    VUPHF = 1297,
1314
    VUPHH = 1298,
1315
    VUPLB = 1299,
1316
    VUPLF = 1300,
1317
    VUPLHB  = 1301,
1318
    VUPLHF  = 1302,
1319
    VUPLHH  = 1303,
1320
    VUPLHW  = 1304,
1321
    VUPLLB  = 1305,
1322
    VUPLLF  = 1306,
1323
    VUPLLH  = 1307,
1324
    VX  = 1308,
1325
    VZERO = 1309,
1326
    WCDGB = 1310,
1327
    WCDLGB  = 1311,
1328
    WCGDB = 1312,
1329
    WCLGDB  = 1313,
1330
    WFADB = 1314,
1331
    WFCDB = 1315,
1332
    WFCEDB  = 1316,
1333
    WFCEDBS = 1317,
1334
    WFCHDB  = 1318,
1335
    WFCHDBS = 1319,
1336
    WFCHEDB = 1320,
1337
    WFCHEDBS  = 1321,
1338
    WFDDB = 1322,
1339
    WFIDB = 1323,
1340
    WFKDB = 1324,
1341
    WFLCDB  = 1325,
1342
    WFLNDB  = 1326,
1343
    WFLPDB  = 1327,
1344
    WFMADB  = 1328,
1345
    WFMDB = 1329,
1346
    WFMSDB  = 1330,
1347
    WFSDB = 1331,
1348
    WFSQDB  = 1332,
1349
    WFTCIDB = 1333,
1350
    WLDEB = 1334,
1351
    WLEDB = 1335,
1352
    X = 1336,
1353
    XC  = 1337,
1354
    XCLoop  = 1338,
1355
    XCSequence  = 1339,
1356
    XG  = 1340,
1357
    XGR = 1341,
1358
    XGRK  = 1342,
1359
    XI  = 1343,
1360
    XIFMux  = 1344,
1361
    XIHF  = 1345,
1362
    XIHF64  = 1346,
1363
    XILF  = 1347,
1364
    XILF64  = 1348,
1365
    XIY = 1349,
1366
    XR  = 1350,
1367
    XRK = 1351,
1368
    XY  = 1352,
1369
    ZEXT128_32  = 1353,
1370
    ZEXT128_64  = 1354,
1371
    INSTRUCTION_LIST_END = 1355
1372
  };
1373
1374
namespace Sched {
1375
  enum {
1376
    NoInstrModel  = 0,
1377
    SCHED_LIST_END = 1
1378
  };
1379
} // end Sched namespace
1380
} // end SystemZ namespace
1381
} // end llvm namespace 
1382
#endif // GET_INSTRINFO_ENUM
1383
1384
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1385
|*                                                                            *|
1386
|* Target Instruction Descriptors                                             *|
1387
|*                                                                            *|
1388
|* Automatically generated file, do not edit!                                 *|
1389
|*                                                                            *|
1390
\*===----------------------------------------------------------------------===*/
1391
1392
1393
#ifdef GET_INSTRINFO_MC_DESC
1394
#undef GET_INSTRINFO_MC_DESC
1395
namespace llvm_ks {
1396
1397
static const MCPhysReg ImplicitList1[] = { SystemZ::CC, 0 };
1398
static const MCPhysReg ImplicitList2[] = { SystemZ::R0L, 0 };
1399
static const MCPhysReg ImplicitList3[] = { SystemZ::R14D, SystemZ::CC, 0 };
1400
static const MCPhysReg ImplicitList4[] = { SystemZ::R1D, 0 };
1401
1402
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1403
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1404
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1405
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1406
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1407
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1408
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1409
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1410
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1411
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1412
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1413
static const MCOperandInfo OperandInfo13[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1414
static const MCOperandInfo OperandInfo14[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1415
static const MCOperandInfo OperandInfo15[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1416
static const MCOperandInfo OperandInfo16[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1417
static const MCOperandInfo OperandInfo17[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1418
static const MCOperandInfo OperandInfo18[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1419
static const MCOperandInfo OperandInfo19[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1420
static const MCOperandInfo OperandInfo20[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1421
static const MCOperandInfo OperandInfo21[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1422
static const MCOperandInfo OperandInfo22[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1423
static const MCOperandInfo OperandInfo23[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1424
static const MCOperandInfo OperandInfo24[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1425
static const MCOperandInfo OperandInfo25[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1426
static const MCOperandInfo OperandInfo26[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1427
static const MCOperandInfo OperandInfo27[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1428
static const MCOperandInfo OperandInfo28[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1429
static const MCOperandInfo OperandInfo29[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1430
static const MCOperandInfo OperandInfo30[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1431
static const MCOperandInfo OperandInfo31[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1432
static const MCOperandInfo OperandInfo32[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1433
static const MCOperandInfo OperandInfo33[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1434
static const MCOperandInfo OperandInfo34[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1435
static const MCOperandInfo OperandInfo35[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1436
static const MCOperandInfo OperandInfo36[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1437
static const MCOperandInfo OperandInfo37[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1438
static const MCOperandInfo OperandInfo38[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1439
static const MCOperandInfo OperandInfo39[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1440
static const MCOperandInfo OperandInfo40[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1441
static const MCOperandInfo OperandInfo41[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1442
static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1443
static const MCOperandInfo OperandInfo43[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1444
static const MCOperandInfo OperandInfo44[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1445
static const MCOperandInfo OperandInfo45[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1446
static const MCOperandInfo OperandInfo46[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1447
static const MCOperandInfo OperandInfo47[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1448
static const MCOperandInfo OperandInfo48[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1449
static const MCOperandInfo OperandInfo49[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1450
static const MCOperandInfo OperandInfo50[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1451
static const MCOperandInfo OperandInfo51[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1452
static const MCOperandInfo OperandInfo52[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1453
static const MCOperandInfo OperandInfo53[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1454
static const MCOperandInfo OperandInfo54[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1455
static const MCOperandInfo OperandInfo55[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1456
static const MCOperandInfo OperandInfo56[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1457
static const MCOperandInfo OperandInfo57[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1458
static const MCOperandInfo OperandInfo58[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1459
static const MCOperandInfo OperandInfo59[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1460
static const MCOperandInfo OperandInfo60[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1461
static const MCOperandInfo OperandInfo61[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1462
static const MCOperandInfo OperandInfo62[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1463
static const MCOperandInfo OperandInfo63[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1464
static const MCOperandInfo OperandInfo64[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1465
static const MCOperandInfo OperandInfo65[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1466
static const MCOperandInfo OperandInfo66[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1467
static const MCOperandInfo OperandInfo67[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1468
static const MCOperandInfo OperandInfo68[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1469
static const MCOperandInfo OperandInfo69[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1470
static const MCOperandInfo OperandInfo70[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1471
static const MCOperandInfo OperandInfo71[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1472
static const MCOperandInfo OperandInfo72[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1473
static const MCOperandInfo OperandInfo73[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1474
static const MCOperandInfo OperandInfo74[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1475
static const MCOperandInfo OperandInfo75[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1476
static const MCOperandInfo OperandInfo76[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1477
static const MCOperandInfo OperandInfo77[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1478
static const MCOperandInfo OperandInfo78[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1479
static const MCOperandInfo OperandInfo79[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1480
static const MCOperandInfo OperandInfo80[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1481
static const MCOperandInfo OperandInfo81[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1482
static const MCOperandInfo OperandInfo82[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1483
static const MCOperandInfo OperandInfo83[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1484
static const MCOperandInfo OperandInfo84[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1485
static const MCOperandInfo OperandInfo85[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1486
static const MCOperandInfo OperandInfo86[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1487
static const MCOperandInfo OperandInfo87[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1488
static const MCOperandInfo OperandInfo88[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1489
static const MCOperandInfo OperandInfo89[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1490
static const MCOperandInfo OperandInfo90[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1491
static const MCOperandInfo OperandInfo91[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1492
static const MCOperandInfo OperandInfo92[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1493
static const MCOperandInfo OperandInfo93[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1494
static const MCOperandInfo OperandInfo94[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1495
static const MCOperandInfo OperandInfo95[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1496
static const MCOperandInfo OperandInfo96[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
1497
static const MCOperandInfo OperandInfo97[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1498
static const MCOperandInfo OperandInfo98[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1499
static const MCOperandInfo OperandInfo99[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1500
static const MCOperandInfo OperandInfo100[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1501
static const MCOperandInfo OperandInfo101[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1502
static const MCOperandInfo OperandInfo102[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1503
static const MCOperandInfo OperandInfo103[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1504
static const MCOperandInfo OperandInfo104[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1505
static const MCOperandInfo OperandInfo105[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1506
static const MCOperandInfo OperandInfo106[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1507
static const MCOperandInfo OperandInfo107[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1508
static const MCOperandInfo OperandInfo108[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1509
static const MCOperandInfo OperandInfo109[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1510
static const MCOperandInfo OperandInfo110[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1511
static const MCOperandInfo OperandInfo111[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1512
static const MCOperandInfo OperandInfo112[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1513
static const MCOperandInfo OperandInfo113[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1514
static const MCOperandInfo OperandInfo114[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1515
static const MCOperandInfo OperandInfo115[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1516
static const MCOperandInfo OperandInfo116[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1517
static const MCOperandInfo OperandInfo117[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1518
static const MCOperandInfo OperandInfo118[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1519
static const MCOperandInfo OperandInfo119[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1520
static const MCOperandInfo OperandInfo120[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1521
static const MCOperandInfo OperandInfo121[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1522
static const MCOperandInfo OperandInfo122[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1523
static const MCOperandInfo OperandInfo123[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1524
static const MCOperandInfo OperandInfo124[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1525
static const MCOperandInfo OperandInfo125[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1526
static const MCOperandInfo OperandInfo126[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1527
static const MCOperandInfo OperandInfo127[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1528
static const MCOperandInfo OperandInfo128[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1529
static const MCOperandInfo OperandInfo129[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1530
static const MCOperandInfo OperandInfo130[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1531
static const MCOperandInfo OperandInfo131[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1532
static const MCOperandInfo OperandInfo132[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1533
static const MCOperandInfo OperandInfo133[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1534
static const MCOperandInfo OperandInfo134[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1535
static const MCOperandInfo OperandInfo135[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1536
static const MCOperandInfo OperandInfo136[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1537
static const MCOperandInfo OperandInfo137[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1538
static const MCOperandInfo OperandInfo138[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1539
static const MCOperandInfo OperandInfo139[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1540
static const MCOperandInfo OperandInfo140[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1541
static const MCOperandInfo OperandInfo141[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1542
static const MCOperandInfo OperandInfo142[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1543
static const MCOperandInfo OperandInfo143[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1544
static const MCOperandInfo OperandInfo144[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1545
static const MCOperandInfo OperandInfo145[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1546
static const MCOperandInfo OperandInfo146[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1547
static const MCOperandInfo OperandInfo147[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1548
static const MCOperandInfo OperandInfo148[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1549
static const MCOperandInfo OperandInfo149[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1550
static const MCOperandInfo OperandInfo150[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1551
static const MCOperandInfo OperandInfo151[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1552
static const MCOperandInfo OperandInfo152[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1553
static const MCOperandInfo OperandInfo153[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1554
static const MCOperandInfo OperandInfo154[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1555
static const MCOperandInfo OperandInfo155[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1556
static const MCOperandInfo OperandInfo156[] = { { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1557
static const MCOperandInfo OperandInfo157[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1558
static const MCOperandInfo OperandInfo158[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRH32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1559
static const MCOperandInfo OperandInfo159[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1560
static const MCOperandInfo OperandInfo160[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1561
static const MCOperandInfo OperandInfo161[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1562
static const MCOperandInfo OperandInfo162[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1563
static const MCOperandInfo OperandInfo163[] = { { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1564
static const MCOperandInfo OperandInfo164[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1565
static const MCOperandInfo OperandInfo165[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1566
static const MCOperandInfo OperandInfo166[] = { { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1567
static const MCOperandInfo OperandInfo167[] = { { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GRX32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1568
static const MCOperandInfo OperandInfo168[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1569
static const MCOperandInfo OperandInfo169[] = { { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1570
static const MCOperandInfo OperandInfo170[] = { { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1571
static const MCOperandInfo OperandInfo171[] = { { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::FP64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1572
static const MCOperandInfo OperandInfo172[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1573
static const MCOperandInfo OperandInfo173[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1574
static const MCOperandInfo OperandInfo174[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1575
static const MCOperandInfo OperandInfo175[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1576
static const MCOperandInfo OperandInfo176[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1577
static const MCOperandInfo OperandInfo177[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1578
static const MCOperandInfo OperandInfo178[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1579
static const MCOperandInfo OperandInfo179[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1580
static const MCOperandInfo OperandInfo180[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1581
static const MCOperandInfo OperandInfo181[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1582
static const MCOperandInfo OperandInfo182[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1583
static const MCOperandInfo OperandInfo183[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1584
static const MCOperandInfo OperandInfo184[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1585
static const MCOperandInfo OperandInfo185[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1586
static const MCOperandInfo OperandInfo186[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1587
static const MCOperandInfo OperandInfo187[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1588
static const MCOperandInfo OperandInfo188[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1589
static const MCOperandInfo OperandInfo189[] = { { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1590
static const MCOperandInfo OperandInfo190[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1591
static const MCOperandInfo OperandInfo191[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1592
static const MCOperandInfo OperandInfo192[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1593
static const MCOperandInfo OperandInfo193[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1594
static const MCOperandInfo OperandInfo194[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1595
static const MCOperandInfo OperandInfo195[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR32BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1596
static const MCOperandInfo OperandInfo196[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1597
static const MCOperandInfo OperandInfo197[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1598
static const MCOperandInfo OperandInfo198[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1599
static const MCOperandInfo OperandInfo199[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::ADDR64BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1600
static const MCOperandInfo OperandInfo200[] = { { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1601
static const MCOperandInfo OperandInfo201[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1602
static const MCOperandInfo OperandInfo202[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1603
static const MCOperandInfo OperandInfo203[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1604
static const MCOperandInfo OperandInfo204[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1605
static const MCOperandInfo OperandInfo205[] = { { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1606
static const MCOperandInfo OperandInfo206[] = { { SystemZ::VR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::VR64BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1607
static const MCOperandInfo OperandInfo207[] = { { SystemZ::GR128BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { SystemZ::GR32BitRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1608
1609
extern const MCInstrDesc SystemZInsts[] = {
1610
  { 0,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #0 = PHI
1611
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
1612
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
1613
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #3 = EH_LABEL
1614
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #4 = GC_LABEL
1615
  { 5,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #5 = KILL
1616
  { 6,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #6 = EXTRACT_SUBREG
1617
  { 7,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = INSERT_SUBREG
1618
  { 8,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = IMPLICIT_DEF
1619
  { 9,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #9 = SUBREG_TO_REG
1620
  { 10, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #10 = COPY_TO_REGCLASS
1621
  { 11, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #11 = DBG_VALUE
1622
  { 12, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #12 = REG_SEQUENCE
1623
  { 13, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #13 = COPY
1624
  { 14, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #14 = BUNDLE
1625
  { 15, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #15 = LIFETIME_START
1626
  { 16, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #16 = LIFETIME_END
1627
  { 17, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #17 = STACKMAP
1628
  { 18, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #18 = PATCHPOINT
1629
  { 19, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #19 = LOAD_STACK_GUARD
1630
  { 20, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #20 = STATEPOINT
1631
  { 21, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #21 = LOCAL_ESCAPE
1632
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #22 = FAULTING_LOAD_OP
1633
  { 23, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #23 = G_ADD
1634
  { 24, 5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x23c88ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #24 = A
1635
  { 25, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x3fd08ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #25 = ADB
1636
  { 26, 3,  1,  4,  0,  0|(1ULL<<MCID::Commutable), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #26 = ADBR
1637
  { 27, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #27 = ADJCALLSTACKDOWN
1638
  { 28, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #28 = ADJCALLSTACKUP
1639
  { 29, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #29 = ADJDYNALLOC
1640
  { 30, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x3fc88ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #30 = AEB
1641
  { 31, 3,  1,  4,  0,  0|(1ULL<<MCID::Commutable), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #31 = AEBR
1642
  { 32, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #32 = AEXT128_64
1643
  { 33, 3,  1,  6,  0,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #33 = AFI
1644
  { 34, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #34 = AFIMux
1645
  { 35, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x23d0cULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #35 = AG
1646
  { 36, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x23c8cULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #36 = AGF
1647
  { 37, 3,  1,  6,  0,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #37 = AGFI
1648
  { 38, 3,  1,  4,  0,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo24, -1 ,nullptr },  // Inst #38 = AGFR
1649
  { 39, 3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #39 = AGHI
1650
  { 40, 3,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr },  // Inst #40 = AGHIK
1651
  { 41, 3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo26, -1 ,nullptr },  // Inst #41 = AGR
1652
  { 42, 3,  1,  4,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #42 = AGRK
1653
  { 43, 3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c04ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #43 = AGSI
1654
  { 44, 5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x23c48ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #44 = AH
1655
  { 45, 3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #45 = AHI
1656
  { 46, 3,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #46 = AHIK
1657
  { 47, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #47 = AHIMux
1658
  { 48, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo30, -1 ,nullptr },  // Inst #48 = AHIMuxK
1659
  { 49, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x23c4cULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #49 = AHY
1660
  { 50, 3,  1,  6,  0,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #50 = AIH
1661
  { 51, 5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #51 = AL
1662
  { 52, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, ImplicitList1, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #52 = ALC
1663
  { 53, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x10cULL, ImplicitList1, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #53 = ALCG
1664
  { 54, 3,  1,  4,  0,  0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo26, -1 ,nullptr },  // Inst #54 = ALCGR
1665
  { 55, 3,  1,  4,  0,  0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #55 = ALCR
1666
  { 56, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #56 = ALFI
1667
  { 57, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x10cULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #57 = ALG
1668
  { 58, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #58 = ALGF
1669
  { 59, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #59 = ALGFI
1670
  { 60, 3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo24, -1 ,nullptr },  // Inst #60 = ALGFR
1671
  { 61, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr },  // Inst #61 = ALGHSIK
1672
  { 62, 3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo26, -1 ,nullptr },  // Inst #62 = ALGR
1673
  { 63, 3,  1,  4,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #63 = ALGRK
1674
  { 64, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo29, -1 ,nullptr },  // Inst #64 = ALHSIK
1675
  { 65, 3,  1,  2,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #65 = ALR
1676
  { 66, 3,  1,  4,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #66 = ALRK
1677
  { 67, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #67 = ALY
1678
  { 68, 3,  1,  2,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #68 = AR
1679
  { 69, 3,  1,  4,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #69 = ARK
1680
  { 70, 3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x23c04ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #70 = ASI
1681
  { 71, 8,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #71 = ATOMIC_CMP_SWAPW
1682
  { 72, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #72 = ATOMIC_LOADW_AFI
1683
  { 73, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #73 = ATOMIC_LOADW_AR
1684
  { 74, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #74 = ATOMIC_LOADW_MAX
1685
  { 75, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #75 = ATOMIC_LOADW_MIN
1686
  { 76, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #76 = ATOMIC_LOADW_NILH
1687
  { 77, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #77 = ATOMIC_LOADW_NILHi
1688
  { 78, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #78 = ATOMIC_LOADW_NR
1689
  { 79, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #79 = ATOMIC_LOADW_NRi
1690
  { 80, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #80 = ATOMIC_LOADW_OILH
1691
  { 81, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #81 = ATOMIC_LOADW_OR
1692
  { 82, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #82 = ATOMIC_LOADW_SR
1693
  { 83, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #83 = ATOMIC_LOADW_UMAX
1694
  { 84, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #84 = ATOMIC_LOADW_UMIN
1695
  { 85, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo35, -1 ,nullptr },  // Inst #85 = ATOMIC_LOADW_XILF
1696
  { 86, 7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #86 = ATOMIC_LOADW_XR
1697
  { 87, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #87 = ATOMIC_LOAD_AFI
1698
  { 88, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #88 = ATOMIC_LOAD_AGFI
1699
  { 89, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #89 = ATOMIC_LOAD_AGHI
1700
  { 90, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #90 = ATOMIC_LOAD_AGR
1701
  { 91, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #91 = ATOMIC_LOAD_AHI
1702
  { 92, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #92 = ATOMIC_LOAD_AR
1703
  { 93, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #93 = ATOMIC_LOAD_MAX_32
1704
  { 94, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #94 = ATOMIC_LOAD_MAX_64
1705
  { 95, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #95 = ATOMIC_LOAD_MIN_32
1706
  { 96, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #96 = ATOMIC_LOAD_MIN_64
1707
  { 97, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #97 = ATOMIC_LOAD_NGR
1708
  { 98, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #98 = ATOMIC_LOAD_NGRi
1709
  { 99, 4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #99 = ATOMIC_LOAD_NIHF64
1710
  { 100,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #100 = ATOMIC_LOAD_NIHF64i
1711
  { 101,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #101 = ATOMIC_LOAD_NIHH64
1712
  { 102,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #102 = ATOMIC_LOAD_NIHH64i
1713
  { 103,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #103 = ATOMIC_LOAD_NIHL64
1714
  { 104,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #104 = ATOMIC_LOAD_NIHL64i
1715
  { 105,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #105 = ATOMIC_LOAD_NILF
1716
  { 106,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #106 = ATOMIC_LOAD_NILF64
1717
  { 107,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #107 = ATOMIC_LOAD_NILF64i
1718
  { 108,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #108 = ATOMIC_LOAD_NILFi
1719
  { 109,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #109 = ATOMIC_LOAD_NILH
1720
  { 110,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #110 = ATOMIC_LOAD_NILH64
1721
  { 111,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #111 = ATOMIC_LOAD_NILH64i
1722
  { 112,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #112 = ATOMIC_LOAD_NILHi
1723
  { 113,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #113 = ATOMIC_LOAD_NILL
1724
  { 114,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #114 = ATOMIC_LOAD_NILL64
1725
  { 115,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #115 = ATOMIC_LOAD_NILL64i
1726
  { 116,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #116 = ATOMIC_LOAD_NILLi
1727
  { 117,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #117 = ATOMIC_LOAD_NR
1728
  { 118,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #118 = ATOMIC_LOAD_NRi
1729
  { 119,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #119 = ATOMIC_LOAD_OGR
1730
  { 120,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #120 = ATOMIC_LOAD_OIHF64
1731
  { 121,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #121 = ATOMIC_LOAD_OIHH64
1732
  { 122,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #122 = ATOMIC_LOAD_OIHL64
1733
  { 123,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #123 = ATOMIC_LOAD_OILF
1734
  { 124,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #124 = ATOMIC_LOAD_OILF64
1735
  { 125,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #125 = ATOMIC_LOAD_OILH
1736
  { 126,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #126 = ATOMIC_LOAD_OILH64
1737
  { 127,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #127 = ATOMIC_LOAD_OILL
1738
  { 128,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #128 = ATOMIC_LOAD_OILL64
1739
  { 129,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #129 = ATOMIC_LOAD_OR
1740
  { 130,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #130 = ATOMIC_LOAD_SGR
1741
  { 131,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #131 = ATOMIC_LOAD_SR
1742
  { 132,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #132 = ATOMIC_LOAD_UMAX_32
1743
  { 133,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #133 = ATOMIC_LOAD_UMAX_64
1744
  { 134,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #134 = ATOMIC_LOAD_UMIN_32
1745
  { 135,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #135 = ATOMIC_LOAD_UMIN_64
1746
  { 136,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #136 = ATOMIC_LOAD_XGR
1747
  { 137,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #137 = ATOMIC_LOAD_XIHF64
1748
  { 138,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr },  // Inst #138 = ATOMIC_LOAD_XILF
1749
  { 139,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr },  // Inst #139 = ATOMIC_LOAD_XILF64
1750
  { 140,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #140 = ATOMIC_LOAD_XR
1751
  { 141,  7,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr },  // Inst #141 = ATOMIC_SWAPW
1752
  { 142,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr },  // Inst #142 = ATOMIC_SWAP_32
1753
  { 143,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x4ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr },  // Inst #143 = ATOMIC_SWAP_64
1754
  { 144,  3,  1,  4,  0,  0|(1ULL<<MCID::Commutable), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #144 = AXBR
1755
  { 145,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x23c8cULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #145 = AY
1756
  { 146,  2,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #146 = AsmBCR
1757
  { 147,  2,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #147 = AsmBRC
1758
  { 148,  2,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #148 = AsmBRCL
1759
  { 149,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #149 = AsmCGIJ
1760
  { 150,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #150 = AsmCGRJ
1761
  { 151,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #151 = AsmCIJ
1762
  { 152,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #152 = AsmCLGIJ
1763
  { 153,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #153 = AsmCLGRJ
1764
  { 154,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #154 = AsmCLIJ
1765
  { 155,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #155 = AsmCLRJ
1766
  { 156,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #156 = AsmCRJ
1767
  { 157,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #157 = AsmEBR
1768
  { 158,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #158 = AsmEJ
1769
  { 159,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #159 = AsmEJG
1770
  { 160,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #160 = AsmELOC
1771
  { 161,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #161 = AsmELOCG
1772
  { 162,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #162 = AsmELOCGR
1773
  { 163,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #163 = AsmELOCR
1774
  { 164,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #164 = AsmESTOC
1775
  { 165,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #165 = AsmESTOCG
1776
  { 166,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #166 = AsmHBR
1777
  { 167,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #167 = AsmHEBR
1778
  { 168,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #168 = AsmHEJ
1779
  { 169,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #169 = AsmHEJG
1780
  { 170,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #170 = AsmHELOC
1781
  { 171,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #171 = AsmHELOCG
1782
  { 172,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #172 = AsmHELOCGR
1783
  { 173,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #173 = AsmHELOCR
1784
  { 174,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #174 = AsmHESTOC
1785
  { 175,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #175 = AsmHESTOCG
1786
  { 176,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #176 = AsmHJ
1787
  { 177,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #177 = AsmHJG
1788
  { 178,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #178 = AsmHLOC
1789
  { 179,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #179 = AsmHLOCG
1790
  { 180,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #180 = AsmHLOCGR
1791
  { 181,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #181 = AsmHLOCR
1792
  { 182,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #182 = AsmHSTOC
1793
  { 183,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #183 = AsmHSTOCG
1794
  { 184,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #184 = AsmJEAltCGI
1795
  { 185,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #185 = AsmJEAltCGR
1796
  { 186,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #186 = AsmJEAltCI
1797
  { 187,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #187 = AsmJEAltCLGI
1798
  { 188,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #188 = AsmJEAltCLGR
1799
  { 189,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #189 = AsmJEAltCLI
1800
  { 190,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #190 = AsmJEAltCLR
1801
  { 191,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #191 = AsmJEAltCR
1802
  { 192,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #192 = AsmJECGI
1803
  { 193,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #193 = AsmJECGR
1804
  { 194,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #194 = AsmJECI
1805
  { 195,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #195 = AsmJECLGI
1806
  { 196,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #196 = AsmJECLGR
1807
  { 197,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #197 = AsmJECLI
1808
  { 198,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #198 = AsmJECLR
1809
  { 199,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #199 = AsmJECR
1810
  { 200,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #200 = AsmJHAltCGI
1811
  { 201,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #201 = AsmJHAltCGR
1812
  { 202,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #202 = AsmJHAltCI
1813
  { 203,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #203 = AsmJHAltCLGI
1814
  { 204,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #204 = AsmJHAltCLGR
1815
  { 205,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #205 = AsmJHAltCLI
1816
  { 206,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #206 = AsmJHAltCLR
1817
  { 207,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #207 = AsmJHAltCR
1818
  { 208,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #208 = AsmJHCGI
1819
  { 209,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #209 = AsmJHCGR
1820
  { 210,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #210 = AsmJHCI
1821
  { 211,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #211 = AsmJHCLGI
1822
  { 212,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #212 = AsmJHCLGR
1823
  { 213,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #213 = AsmJHCLI
1824
  { 214,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #214 = AsmJHCLR
1825
  { 215,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #215 = AsmJHCR
1826
  { 216,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #216 = AsmJHEAltCGI
1827
  { 217,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #217 = AsmJHEAltCGR
1828
  { 218,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #218 = AsmJHEAltCI
1829
  { 219,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #219 = AsmJHEAltCLGI
1830
  { 220,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #220 = AsmJHEAltCLGR
1831
  { 221,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #221 = AsmJHEAltCLI
1832
  { 222,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #222 = AsmJHEAltCLR
1833
  { 223,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #223 = AsmJHEAltCR
1834
  { 224,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #224 = AsmJHECGI
1835
  { 225,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #225 = AsmJHECGR
1836
  { 226,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #226 = AsmJHECI
1837
  { 227,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #227 = AsmJHECLGI
1838
  { 228,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #228 = AsmJHECLGR
1839
  { 229,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #229 = AsmJHECLI
1840
  { 230,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #230 = AsmJHECLR
1841
  { 231,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #231 = AsmJHECR
1842
  { 232,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #232 = AsmJLAltCGI
1843
  { 233,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #233 = AsmJLAltCGR
1844
  { 234,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #234 = AsmJLAltCI
1845
  { 235,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #235 = AsmJLAltCLGI
1846
  { 236,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #236 = AsmJLAltCLGR
1847
  { 237,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #237 = AsmJLAltCLI
1848
  { 238,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #238 = AsmJLAltCLR
1849
  { 239,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #239 = AsmJLAltCR
1850
  { 240,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #240 = AsmJLCGI
1851
  { 241,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #241 = AsmJLCGR
1852
  { 242,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #242 = AsmJLCI
1853
  { 243,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #243 = AsmJLCLGI
1854
  { 244,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #244 = AsmJLCLGR
1855
  { 245,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #245 = AsmJLCLI
1856
  { 246,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #246 = AsmJLCLR
1857
  { 247,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #247 = AsmJLCR
1858
  { 248,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #248 = AsmJLEAltCGI
1859
  { 249,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #249 = AsmJLEAltCGR
1860
  { 250,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #250 = AsmJLEAltCI
1861
  { 251,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #251 = AsmJLEAltCLGI
1862
  { 252,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #252 = AsmJLEAltCLGR
1863
  { 253,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #253 = AsmJLEAltCLI
1864
  { 254,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #254 = AsmJLEAltCLR
1865
  { 255,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #255 = AsmJLEAltCR
1866
  { 256,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #256 = AsmJLECGI
1867
  { 257,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #257 = AsmJLECGR
1868
  { 258,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #258 = AsmJLECI
1869
  { 259,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #259 = AsmJLECLGI
1870
  { 260,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #260 = AsmJLECLGR
1871
  { 261,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #261 = AsmJLECLI
1872
  { 262,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #262 = AsmJLECLR
1873
  { 263,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #263 = AsmJLECR
1874
  { 264,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #264 = AsmJLHAltCGI
1875
  { 265,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #265 = AsmJLHAltCGR
1876
  { 266,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #266 = AsmJLHAltCI
1877
  { 267,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #267 = AsmJLHAltCLGI
1878
  { 268,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #268 = AsmJLHAltCLGR
1879
  { 269,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #269 = AsmJLHAltCLI
1880
  { 270,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #270 = AsmJLHAltCLR
1881
  { 271,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #271 = AsmJLHAltCR
1882
  { 272,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #272 = AsmJLHCGI
1883
  { 273,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #273 = AsmJLHCGR
1884
  { 274,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #274 = AsmJLHCI
1885
  { 275,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #275 = AsmJLHCLGI
1886
  { 276,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #276 = AsmJLHCLGR
1887
  { 277,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #277 = AsmJLHCLI
1888
  { 278,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #278 = AsmJLHCLR
1889
  { 279,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #279 = AsmJLHCR
1890
  { 280,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #280 = AsmLBR
1891
  { 281,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #281 = AsmLEBR
1892
  { 282,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #282 = AsmLEJ
1893
  { 283,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #283 = AsmLEJG
1894
  { 284,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #284 = AsmLELOC
1895
  { 285,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #285 = AsmLELOCG
1896
  { 286,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #286 = AsmLELOCGR
1897
  { 287,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #287 = AsmLELOCR
1898
  { 288,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #288 = AsmLESTOC
1899
  { 289,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #289 = AsmLESTOCG
1900
  { 290,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #290 = AsmLHBR
1901
  { 291,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #291 = AsmLHJ
1902
  { 292,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #292 = AsmLHJG
1903
  { 293,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #293 = AsmLHLOC
1904
  { 294,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #294 = AsmLHLOCG
1905
  { 295,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #295 = AsmLHLOCGR
1906
  { 296,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #296 = AsmLHLOCR
1907
  { 297,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #297 = AsmLHSTOC
1908
  { 298,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #298 = AsmLHSTOCG
1909
  { 299,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #299 = AsmLJ
1910
  { 300,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #300 = AsmLJG
1911
  { 301,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #301 = AsmLLOC
1912
  { 302,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #302 = AsmLLOCG
1913
  { 303,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #303 = AsmLLOCGR
1914
  { 304,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #304 = AsmLLOCR
1915
  { 305,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, ImplicitList1, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #305 = AsmLOC
1916
  { 306,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, ImplicitList1, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #306 = AsmLOCG
1917
  { 307,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #307 = AsmLOCGR
1918
  { 308,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList1, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #308 = AsmLOCR
1919
  { 309,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #309 = AsmLSTOC
1920
  { 310,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #310 = AsmLSTOCG
1921
  { 311,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #311 = AsmNEBR
1922
  { 312,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #312 = AsmNEJ
1923
  { 313,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #313 = AsmNEJG
1924
  { 314,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #314 = AsmNELOC
1925
  { 315,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #315 = AsmNELOCG
1926
  { 316,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #316 = AsmNELOCGR
1927
  { 317,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #317 = AsmNELOCR
1928
  { 318,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #318 = AsmNESTOC
1929
  { 319,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #319 = AsmNESTOCG
1930
  { 320,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #320 = AsmNHBR
1931
  { 321,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #321 = AsmNHEBR
1932
  { 322,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #322 = AsmNHEJ
1933
  { 323,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #323 = AsmNHEJG
1934
  { 324,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #324 = AsmNHELOC
1935
  { 325,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #325 = AsmNHELOCG
1936
  { 326,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #326 = AsmNHELOCGR
1937
  { 327,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #327 = AsmNHELOCR
1938
  { 328,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #328 = AsmNHESTOC
1939
  { 329,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #329 = AsmNHESTOCG
1940
  { 330,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #330 = AsmNHJ
1941
  { 331,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #331 = AsmNHJG
1942
  { 332,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #332 = AsmNHLOC
1943
  { 333,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #333 = AsmNHLOCG
1944
  { 334,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #334 = AsmNHLOCGR
1945
  { 335,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #335 = AsmNHLOCR
1946
  { 336,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #336 = AsmNHSTOC
1947
  { 337,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #337 = AsmNHSTOCG
1948
  { 338,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #338 = AsmNLBR
1949
  { 339,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #339 = AsmNLEBR
1950
  { 340,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #340 = AsmNLEJ
1951
  { 341,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #341 = AsmNLEJG
1952
  { 342,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #342 = AsmNLELOC
1953
  { 343,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #343 = AsmNLELOCG
1954
  { 344,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #344 = AsmNLELOCGR
1955
  { 345,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #345 = AsmNLELOCR
1956
  { 346,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #346 = AsmNLESTOC
1957
  { 347,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #347 = AsmNLESTOCG
1958
  { 348,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #348 = AsmNLHBR
1959
  { 349,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #349 = AsmNLHJ
1960
  { 350,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #350 = AsmNLHJG
1961
  { 351,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #351 = AsmNLHLOC
1962
  { 352,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #352 = AsmNLHLOCG
1963
  { 353,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #353 = AsmNLHLOCGR
1964
  { 354,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #354 = AsmNLHLOCR
1965
  { 355,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #355 = AsmNLHSTOC
1966
  { 356,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #356 = AsmNLHSTOCG
1967
  { 357,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #357 = AsmNLJ
1968
  { 358,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #358 = AsmNLJG
1969
  { 359,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #359 = AsmNLLOC
1970
  { 360,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #360 = AsmNLLOCG
1971
  { 361,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #361 = AsmNLLOCGR
1972
  { 362,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #362 = AsmNLLOCR
1973
  { 363,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #363 = AsmNLSTOC
1974
  { 364,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #364 = AsmNLSTOCG
1975
  { 365,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #365 = AsmNOBR
1976
  { 366,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #366 = AsmNOJ
1977
  { 367,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #367 = AsmNOJG
1978
  { 368,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #368 = AsmNOLOC
1979
  { 369,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #369 = AsmNOLOCG
1980
  { 370,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #370 = AsmNOLOCGR
1981
  { 371,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #371 = AsmNOLOCR
1982
  { 372,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #372 = AsmNOSTOC
1983
  { 373,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #373 = AsmNOSTOCG
1984
  { 374,  1,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #374 = AsmOBR
1985
  { 375,  1,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #375 = AsmOJ
1986
  { 376,  1,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #376 = AsmOJG
1987
  { 377,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #377 = AsmOLOC
1988
  { 378,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #378 = AsmOLOCG
1989
  { 379,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #379 = AsmOLOCGR
1990
  { 380,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #380 = AsmOLOCR
1991
  { 381,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #381 = AsmOSTOC
1992
  { 382,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #382 = AsmOSTOCG
1993
  { 383,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x84ULL, ImplicitList1, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #383 = AsmSTOC
1994
  { 384,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x104ULL, ImplicitList1, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #384 = AsmSTOCG
1995
  { 385,  2,  0,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #385 = BASR
1996
  { 386,  1,  0,  2,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr },  // Inst #386 = BR
1997
  { 387,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #387 = BRAS
1998
  { 388,  3,  0,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #388 = BRASL
1999
  { 389,  3,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #389 = BRC
2000
  { 390,  3,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x40000ULL, ImplicitList1, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #390 = BRCL
2001
  { 391,  3,  1,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #391 = BRCT
2002
  { 392,  3,  1,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #392 = BRCTG
2003
  { 393,  4,  0,  4,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3888ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #393 = C
2004
  { 394,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3d08ULL, nullptr, ImplicitList1, OperandInfo60, -1 ,nullptr },  // Inst #394 = CDB
2005
  { 395,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x3c00ULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr },  // Inst #395 = CDBR
2006
  { 396,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #396 = CDFBR
2007
  { 397,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #397 = CDGBR
2008
  { 398,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #398 = CDLFBR
2009
  { 399,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #399 = CDLGBR
2010
  { 400,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3c88ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr },  // Inst #400 = CEB
2011
  { 401,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x3c00ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #401 = CEBR
2012
  { 402,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #402 = CEFBR
2013
  { 403,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #403 = CEGBR
2014
  { 404,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #404 = CELFBR
2015
  { 405,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #405 = CELGBR
2016
  { 406,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #406 = CFDBR
2017
  { 407,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo73, -1 ,nullptr },  // Inst #407 = CFEBR
2018
  { 408,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo74, -1 ,nullptr },  // Inst #408 = CFI
2019
  { 409,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x3800ULL, nullptr, ImplicitList1, OperandInfo75, -1 ,nullptr },  // Inst #409 = CFIMux
2020
  { 410,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo76, -1 ,nullptr },  // Inst #410 = CFXBR
2021
  { 411,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x390cULL, nullptr, ImplicitList1, OperandInfo16, -1 ,nullptr },  // Inst #411 = CG
2022
  { 412,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo77, -1 ,nullptr },  // Inst #412 = CGDBR
2023
  { 413,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo78, -1 ,nullptr },  // Inst #413 = CGEBR
2024
  { 414,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x388cULL, nullptr, ImplicitList1, OperandInfo16, -1 ,nullptr },  // Inst #414 = CGF
2025
  { 415,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #415 = CGFI
2026
  { 416,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr },  // Inst #416 = CGFR
2027
  { 417,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #417 = CGFRL
2028
  { 418,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x384cULL, nullptr, ImplicitList1, OperandInfo16, -1 ,nullptr },  // Inst #418 = CGH
2029
  { 419,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #419 = CGHI
2030
  { 420,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #420 = CGHRL
2031
  { 421,  3,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #421 = CGHSI
2032
  { 422,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #422 = CGIJ
2033
  { 423,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr },  // Inst #423 = CGR
2034
  { 424,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #424 = CGRJ
2035
  { 425,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #425 = CGRL
2036
  { 426,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo82, -1 ,nullptr },  // Inst #426 = CGXBR
2037
  { 427,  4,  0,  4,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3848ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #427 = CH
2038
  { 428,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x388cULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr },  // Inst #428 = CHF
2039
  { 429,  3,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #429 = CHHSI
2040
  { 430,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo74, -1 ,nullptr },  // Inst #430 = CHI
2041
  { 431,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo74, -1 ,nullptr },  // Inst #431 = CHRL
2042
  { 432,  3,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #432 = CHSI
2043
  { 433,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x384cULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #433 = CHY
2044
  { 434,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo84, -1 ,nullptr },  // Inst #434 = CIH
2045
  { 435,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #435 = CIJ
2046
  { 436,  4,  0,  4,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103888ULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #436 = CL
2047
  { 437,  5,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo85, -1 ,nullptr },  // Inst #437 = CLC
2048
  { 438,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #438 = CLCLoop
2049
  { 439,  5,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #439 = CLCSequence
2050
  { 440,  4,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo88, -1 ,nullptr },  // Inst #440 = CLFDBR
2051
  { 441,  4,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo89, -1 ,nullptr },  // Inst #441 = CLFEBR
2052
  { 442,  3,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #442 = CLFHSI
2053
  { 443,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare), 0x103800ULL, nullptr, ImplicitList1, OperandInfo74, -1 ,nullptr },  // Inst #443 = CLFI
2054
  { 444,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x103800ULL, nullptr, ImplicitList1, OperandInfo75, -1 ,nullptr },  // Inst #444 = CLFIMux
2055
  { 445,  4,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo90, -1 ,nullptr },  // Inst #445 = CLFXBR
2056
  { 446,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x10390cULL, nullptr, ImplicitList1, OperandInfo16, -1 ,nullptr },  // Inst #446 = CLG
2057
  { 447,  4,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo91, -1 ,nullptr },  // Inst #447 = CLGDBR
2058
  { 448,  4,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo92, -1 ,nullptr },  // Inst #448 = CLGEBR
2059
  { 449,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x10388cULL, nullptr, ImplicitList1, OperandInfo16, -1 ,nullptr },  // Inst #449 = CLGF
2060
  { 450,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare), 0x103800ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #450 = CLGFI
2061
  { 451,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x103800ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr },  // Inst #451 = CLGFR
2062
  { 452,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #452 = CLGFRL
2063
  { 453,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #453 = CLGHRL
2064
  { 454,  3,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #454 = CLGHSI
2065
  { 455,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr },  // Inst #455 = CLGIJ
2066
  { 456,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x103800ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr },  // Inst #456 = CLGR
2067
  { 457,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo44, -1 ,nullptr },  // Inst #457 = CLGRJ
2068
  { 458,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #458 = CLGRL
2069
  { 459,  4,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo93, -1 ,nullptr },  // Inst #459 = CLGXBR
2070
  { 460,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x10388cULL, nullptr, ImplicitList1, OperandInfo83, -1 ,nullptr },  // Inst #460 = CLHF
2071
  { 461,  3,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #461 = CLHHSI
2072
  { 462,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL, nullptr, ImplicitList1, OperandInfo74, -1 ,nullptr },  // Inst #462 = CLHRL
2073
  { 463,  3,  0,  4,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #463 = CLI
2074
  { 464,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare), 0x103800ULL, nullptr, ImplicitList1, OperandInfo84, -1 ,nullptr },  // Inst #464 = CLIH
2075
  { 465,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo45, -1 ,nullptr },  // Inst #465 = CLIJ
2076
  { 466,  3,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103804ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #466 = CLIY
2077
  { 467,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x10388cULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr },  // Inst #467 = CLMux
2078
  { 468,  2,  0,  2,  0,  0|(1ULL<<MCID::Compare), 0x103800ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr },  // Inst #468 = CLR
2079
  { 469,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #469 = CLRJ
2080
  { 470,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x103800ULL, nullptr, ImplicitList1, OperandInfo74, -1 ,nullptr },  // Inst #470 = CLRL
2081
  { 471,  4,  2,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo96, -1 ,nullptr },  // Inst #471 = CLST
2082
  { 472,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo97, -1 ,nullptr },  // Inst #472 = CLSTLoop
2083
  { 473,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x10388cULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #473 = CLY
2084
  { 474,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x388cULL, nullptr, ImplicitList1, OperandInfo94, -1 ,nullptr },  // Inst #474 = CMux
2085
  { 475,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #475 = CPSDRdd
2086
  { 476,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #476 = CPSDRds
2087
  { 477,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #477 = CPSDRsd
2088
  { 478,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #478 = CPSDRss
2089
  { 479,  2,  0,  2,  0,  0|(1ULL<<MCID::Compare), 0x3800ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr },  // Inst #479 = CR
2090
  { 480,  4,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo46, -1 ,nullptr },  // Inst #480 = CRJ
2091
  { 481,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x3800ULL, nullptr, ImplicitList1, OperandInfo74, -1 ,nullptr },  // Inst #481 = CRL
2092
  { 482,  5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo102, -1 ,nullptr },  // Inst #482 = CS
2093
  { 483,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo103, -1 ,nullptr },  // Inst #483 = CSG
2094
  { 484,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo102, -1 ,nullptr },  // Inst #484 = CSY
2095
  { 485,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x3c00ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr },  // Inst #485 = CXBR
2096
  { 486,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #486 = CXFBR
2097
  { 487,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #487 = CXGBR
2098
  { 488,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #488 = CXLFBR
2099
  { 489,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #489 = CXLGBR
2100
  { 490,  4,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x388cULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #490 = CY
2101
  { 491,  1,  0,  2,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo47, -1 ,nullptr },  // Inst #491 = CallBASR
2102
  { 492,  0,  0,  2,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList4, nullptr, nullptr, -1 ,nullptr },  // Inst #492 = CallBR
2103
  { 493,  1,  0,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo5, -1 ,nullptr },  // Inst #493 = CallBRASL
2104
  { 494,  1,  0,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #494 = CallJG
2105
  { 495,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo109, -1 ,nullptr },  // Inst #495 = CondStore16
2106
  { 496,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo109, -1 ,nullptr },  // Inst #496 = CondStore16Inv
2107
  { 497,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo110, -1 ,nullptr },  // Inst #497 = CondStore16Mux
2108
  { 498,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo110, -1 ,nullptr },  // Inst #498 = CondStore16MuxInv
2109
  { 499,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo109, -1 ,nullptr },  // Inst #499 = CondStore32
2110
  { 500,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo109, -1 ,nullptr },  // Inst #500 = CondStore32Inv
2111
  { 501,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo111, -1 ,nullptr },  // Inst #501 = CondStore64
2112
  { 502,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo111, -1 ,nullptr },  // Inst #502 = CondStore64Inv
2113
  { 503,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo109, -1 ,nullptr },  // Inst #503 = CondStore8
2114
  { 504,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo109, -1 ,nullptr },  // Inst #504 = CondStore8Inv
2115
  { 505,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo110, -1 ,nullptr },  // Inst #505 = CondStore8Mux
2116
  { 506,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo110, -1 ,nullptr },  // Inst #506 = CondStore8MuxInv
2117
  { 507,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo112, -1 ,nullptr },  // Inst #507 = CondStoreF32
2118
  { 508,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo112, -1 ,nullptr },  // Inst #508 = CondStoreF32Inv
2119
  { 509,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo113, -1 ,nullptr },  // Inst #509 = CondStoreF64
2120
  { 510,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo113, -1 ,nullptr },  // Inst #510 = CondStoreF64Inv
2121
  { 511,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #511 = DDB
2122
  { 512,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #512 = DDBR
2123
  { 513,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #513 = DEB
2124
  { 514,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #514 = DEBR
2125
  { 515,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #515 = DL
2126
  { 516,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x10cULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #516 = DLG
2127
  { 517,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #517 = DLGR
2128
  { 518,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #518 = DLR
2129
  { 519,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x10cULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #519 = DSG
2130
  { 520,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #520 = DSGF
2131
  { 521,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #521 = DSGFR
2132
  { 522,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #522 = DSGR
2133
  { 523,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #523 = DXBR
2134
  { 524,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #524 = EAR
2135
  { 525,  1,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #525 = ETND
2136
  { 526,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #526 = FIDBR
2137
  { 527,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #527 = FIDBRA
2138
  { 528,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #528 = FIEBR
2139
  { 529,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #529 = FIEBRA
2140
  { 530,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #530 = FIXBR
2141
  { 531,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #531 = FIXBRA
2142
  { 532,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo19, -1 ,nullptr },  // Inst #532 = FLOGR
2143
  { 533,  1,  1,  6,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #533 = GOT
2144
  { 534,  5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x28ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #534 = IC
2145
  { 535,  5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x28ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #535 = IC32
2146
  { 536,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #536 = IC32Y
2147
  { 537,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #537 = ICY
2148
  { 538,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #538 = IIFMux
2149
  { 539,  2,  1,  6,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #539 = IIHF
2150
  { 540,  3,  1,  6,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #540 = IIHF64
2151
  { 541,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #541 = IIHH
2152
  { 542,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #542 = IIHH64
2153
  { 543,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #543 = IIHL
2154
  { 544,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #544 = IIHL64
2155
  { 545,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #545 = IIHMux
2156
  { 546,  2,  1,  6,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #546 = IILF
2157
  { 547,  3,  1,  6,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #547 = IILF64
2158
  { 548,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #548 = IILH
2159
  { 549,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #549 = IILH64
2160
  { 550,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #550 = IILL
2161
  { 551,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #551 = IILL64
2162
  { 552,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #552 = IILMux
2163
  { 553,  1,  1,  4,  0,  0, 0x0ULL, ImplicitList1, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #553 = IPM
2164
  { 554,  1,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #554 = J
2165
  { 555,  1,  0,  6,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #555 = JG
2166
  { 556,  4,  1,  4,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x89ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #556 = L
2167
  { 557,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x1dULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #557 = L128
2168
  { 558,  4,  1,  4,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #558 = LA
2169
  { 559,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #559 = LAA
2170
  { 560,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr },  // Inst #560 = LAAG
2171
  { 561,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #561 = LAAL
2172
  { 562,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr },  // Inst #562 = LAALG
2173
  { 563,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #563 = LAN
2174
  { 564,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr },  // Inst #564 = LANG
2175
  { 565,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #565 = LAO
2176
  { 566,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr },  // Inst #566 = LAOG
2177
  { 567,  2,  1,  6,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #567 = LARL
2178
  { 568,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #568 = LAX
2179
  { 569,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr },  // Inst #569 = LAXG
2180
  { 570,  4,  1,  6,  0,  0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0xcULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #570 = LAY
2181
  { 571,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #571 = LB
2182
  { 572,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #572 = LBH
2183
  { 573,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #573 = LBMux
2184
  { 574,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #574 = LBR
2185
  { 575,  5,  1,  6,  0,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr },  // Inst #575 = LCBB
2186
  { 576,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr },  // Inst #576 = LCDBR
2187
  { 577,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #577 = LCDFR
2188
  { 578,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #578 = LCDFR_32
2189
  { 579,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #579 = LCEBR
2190
  { 580,  2,  1,  4,  0,  0, 0x3b800ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr },  // Inst #580 = LCGFR
2191
  { 581,  2,  1,  4,  0,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr },  // Inst #581 = LCGR
2192
  { 582,  2,  1,  2,  0,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr },  // Inst #582 = LCR
2193
  { 583,  2,  1,  4,  0,  0, 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr },  // Inst #583 = LCXBR
2194
  { 584,  4,  1,  4,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x109ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #584 = LD
2195
  { 585,  4,  1,  6,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x89ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #585 = LDE32
2196
  { 586,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #586 = LDEB
2197
  { 587,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #587 = LDEBR
2198
  { 588,  2,  1,  4,  0,  0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #588 = LDGR
2199
  { 589,  2,  1,  2,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #589 = LDR
2200
  { 590,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #590 = LDXBR
2201
  { 591,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #591 = LDXBRA
2202
  { 592,  4,  1,  6,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x10dULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #592 = LDY
2203
  { 593,  4,  1,  4,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x89ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #593 = LE
2204
  { 594,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #594 = LEDBR
2205
  { 595,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #595 = LEDBRA
2206
  { 596,  2,  1,  6,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #596 = LEFR
2207
  { 597,  2,  1,  2,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #597 = LER
2208
  { 598,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #598 = LEXBR
2209
  { 599,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #599 = LEXBRA
2210
  { 600,  4,  1,  6,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #600 = LEY
2211
  { 601,  2,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo133, -1 ,nullptr },  // Inst #601 = LFER
2212
  { 602,  4,  1,  6,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #602 = LFH
2213
  { 603,  4,  1,  6,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x10dULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #603 = LG
2214
  { 604,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #604 = LGB
2215
  { 605,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #605 = LGBR
2216
  { 606,  2,  1,  4,  0,  0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #606 = LGDR
2217
  { 607,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #607 = LGF
2218
  { 608,  2,  1,  6,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #608 = LGFI
2219
  { 609,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #609 = LGFR
2220
  { 610,  2,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #610 = LGFRL
2221
  { 611,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #611 = LGH
2222
  { 612,  2,  1,  4,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #612 = LGHI
2223
  { 613,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #613 = LGHR
2224
  { 614,  2,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #614 = LGHRL
2225
  { 615,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #615 = LGR
2226
  { 616,  2,  1,  6,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #616 = LGRL
2227
  { 617,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x48ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #617 = LH
2228
  { 618,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #618 = LHH
2229
  { 619,  2,  1,  4,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #619 = LHI
2230
  { 620,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #620 = LHIMux
2231
  { 621,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #621 = LHMux
2232
  { 622,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #622 = LHR
2233
  { 623,  2,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #623 = LHRL
2234
  { 624,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #624 = LHY
2235
  { 625,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #625 = LLC
2236
  { 626,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #626 = LLCH
2237
  { 627,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #627 = LLCMux
2238
  { 628,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #628 = LLCR
2239
  { 629,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #629 = LLCRMux
2240
  { 630,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2cULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #630 = LLGC
2241
  { 631,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #631 = LLGCR
2242
  { 632,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #632 = LLGF
2243
  { 633,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #633 = LLGFR
2244
  { 634,  2,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #634 = LLGFRL
2245
  { 635,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #635 = LLGH
2246
  { 636,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #636 = LLGHR
2247
  { 637,  2,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #637 = LLGHRL
2248
  { 638,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #638 = LLH
2249
  { 639,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #639 = LLHH
2250
  { 640,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #640 = LLHMux
2251
  { 641,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #641 = LLHR
2252
  { 642,  2,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #642 = LLHRL
2253
  { 643,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #643 = LLHRMux
2254
  { 644,  2,  1,  6,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #644 = LLIHF
2255
  { 645,  2,  1,  4,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #645 = LLIHH
2256
  { 646,  2,  1,  4,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #646 = LLIHL
2257
  { 647,  2,  1,  6,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #647 = LLILF
2258
  { 648,  2,  1,  4,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #648 = LLILH
2259
  { 649,  2,  1,  4,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #649 = LLILL
2260
  { 650,  4,  2,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #650 = LMG
2261
  { 651,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #651 = LMux
2262
  { 652,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr },  // Inst #652 = LNDBR
2263
  { 653,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #653 = LNDFR
2264
  { 654,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #654 = LNDFR_32
2265
  { 655,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #655 = LNEBR
2266
  { 656,  2,  1,  4,  0,  0, 0x3b800ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr },  // Inst #656 = LNGFR
2267
  { 657,  2,  1,  4,  0,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr },  // Inst #657 = LNGR
2268
  { 658,  2,  1,  2,  0,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr },  // Inst #658 = LNR
2269
  { 659,  2,  1,  4,  0,  0, 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr },  // Inst #659 = LNXBR
2270
  { 660,  6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x80084ULL, ImplicitList1, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #660 = LOC
2271
  { 661,  6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x80104ULL, ImplicitList1, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #661 = LOCG
2272
  { 662,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x80000ULL, ImplicitList1, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #662 = LOCGR
2273
  { 663,  4,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x80000ULL, ImplicitList1, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #663 = LOCR
2274
  { 664,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr },  // Inst #664 = LPDBR
2275
  { 665,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #665 = LPDFR
2276
  { 666,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #666 = LPDFR_32
2277
  { 667,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #667 = LPEBR
2278
  { 668,  2,  1,  4,  0,  0, 0x3b800ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr },  // Inst #668 = LPGFR
2279
  { 669,  2,  1,  4,  0,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr },  // Inst #669 = LPGR
2280
  { 670,  2,  1,  2,  0,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr },  // Inst #670 = LPR
2281
  { 671,  2,  1,  4,  0,  0, 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr },  // Inst #671 = LPXBR
2282
  { 672,  2,  1,  2,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #672 = LR
2283
  { 673,  2,  1,  6,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #673 = LRL
2284
  { 674,  2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #674 = LRMux
2285
  { 675,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #675 = LRV
2286
  { 676,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x10cULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #676 = LRVG
2287
  { 677,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #677 = LRVGR
2288
  { 678,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #678 = LRVR
2289
  { 679,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x3b88cULL, nullptr, ImplicitList1, OperandInfo59, -1 ,nullptr },  // Inst #679 = LT
2290
  { 680,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr },  // Inst #680 = LTDBR
2291
  { 681,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr },  // Inst #681 = LTDBRCompare
2292
  { 682,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo61, -1 ,nullptr },  // Inst #682 = LTDBRCompare_VecPseudo
2293
  { 683,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #683 = LTEBR
2294
  { 684,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #684 = LTEBRCompare
2295
  { 685,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo67, -1 ,nullptr },  // Inst #685 = LTEBRCompare_VecPseudo
2296
  { 686,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x3b90cULL, nullptr, ImplicitList1, OperandInfo16, -1 ,nullptr },  // Inst #686 = LTG
2297
  { 687,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x3b88cULL, nullptr, ImplicitList1, OperandInfo16, -1 ,nullptr },  // Inst #687 = LTGF
2298
  { 688,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3b800ULL, nullptr, ImplicitList1, OperandInfo80, -1 ,nullptr },  // Inst #688 = LTGFR
2299
  { 689,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3b800ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr },  // Inst #689 = LTGR
2300
  { 690,  2,  1,  2,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3b800ULL, nullptr, ImplicitList1, OperandInfo95, -1 ,nullptr },  // Inst #690 = LTR
2301
  { 691,  2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr },  // Inst #691 = LTXBR
2302
  { 692,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr },  // Inst #692 = LTXBRCompare
2303
  { 693,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo104, -1 ,nullptr },  // Inst #693 = LTXBRCompare_VecPseudo
2304
  { 694,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x1dULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #694 = LX
2305
  { 695,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #695 = LXDB
2306
  { 696,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #696 = LXDBR
2307
  { 697,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #697 = LXEB
2308
  { 698,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #698 = LXEBR
2309
  { 699,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #699 = LXR
2310
  { 700,  4,  1,  6,  0,  0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #700 = LY
2311
  { 701,  1,  1,  4,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #701 = LZDR
2312
  { 702,  1,  1,  4,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #702 = LZER
2313
  { 703,  1,  1,  4,  0,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #703 = LZXR
2314
  { 704,  6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #704 = MADB
2315
  { 705,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #705 = MADBR
2316
  { 706,  6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #706 = MAEB
2317
  { 707,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #707 = MAEBR
2318
  { 708,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #708 = MDB
2319
  { 709,  3,  1,  4,  0,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #709 = MDBR
2320
  { 710,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x88ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #710 = MDEB
2321
  { 711,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #711 = MDEBR
2322
  { 712,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #712 = MEEB
2323
  { 713,  3,  1,  4,  0,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #713 = MEEBR
2324
  { 714,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #714 = MGHI
2325
  { 715,  5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x48ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #715 = MH
2326
  { 716,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #716 = MHI
2327
  { 717,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x4cULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #717 = MHY
2328
  { 718,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x10cULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #718 = MLG
2329
  { 719,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #719 = MLGR
2330
  { 720,  5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #720 = MS
2331
  { 721,  6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #721 = MSDB
2332
  { 722,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #722 = MSDBR
2333
  { 723,  6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #723 = MSEB
2334
  { 724,  4,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #724 = MSEBR
2335
  { 725,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo20, -1 ,nullptr },  // Inst #725 = MSFI
2336
  { 726,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x10cULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #726 = MSG
2337
  { 727,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #727 = MSGF
2338
  { 728,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #728 = MSGFI
2339
  { 729,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #729 = MSGFR
2340
  { 730,  3,  1,  4,  0,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo26, -1 ,nullptr },  // Inst #730 = MSGR
2341
  { 731,  3,  1,  4,  0,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #731 = MSR
2342
  { 732,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #732 = MSY
2343
  { 733,  5,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #733 = MVC
2344
  { 734,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #734 = MVCLoop
2345
  { 735,  5,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #735 = MVCSequence
2346
  { 736,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #736 = MVGHI
2347
  { 737,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #737 = MVHHI
2348
  { 738,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #738 = MVHI
2349
  { 739,  3,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #739 = MVI
2350
  { 740,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, nullptr, OperandInfo28, -1 ,nullptr },  // Inst #740 = MVIY
2351
  { 741,  4,  2,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo96, -1 ,nullptr },  // Inst #741 = MVST
2352
  { 742,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo97, -1 ,nullptr },  // Inst #742 = MVSTLoop
2353
  { 743,  3,  1,  4,  0,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #743 = MXBR
2354
  { 744,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x108ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #744 = MXDB
2355
  { 745,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #745 = MXDBR
2356
  { 746,  5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x23088ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #746 = N
2357
  { 747,  5,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo85, -1 ,nullptr },  // Inst #747 = NC
2358
  { 748,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #748 = NCLoop
2359
  { 749,  5,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #749 = NCSequence
2360
  { 750,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2310cULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #750 = NG
2361
  { 751,  3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23000ULL, nullptr, ImplicitList1, OperandInfo26, -1 ,nullptr },  // Inst #751 = NGR
2362
  { 752,  3,  1,  4,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x23000ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #752 = NGRK
2363
  { 753,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #753 = NI
2364
  { 754,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x23000ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #754 = NIFMux
2365
  { 755,  3,  1,  6,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23000ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #755 = NIHF
2366
  { 756,  3,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #756 = NIHF64
2367
  { 757,  3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #757 = NIHH
2368
  { 758,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #758 = NIHH64
2369
  { 759,  3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #759 = NIHL
2370
  { 760,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #760 = NIHL64
2371
  { 761,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #761 = NIHMux
2372
  { 762,  3,  1,  6,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23000ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #762 = NILF
2373
  { 763,  3,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #763 = NILF64
2374
  { 764,  3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #764 = NILH
2375
  { 765,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #765 = NILH64
2376
  { 766,  3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #766 = NILL
2377
  { 767,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #767 = NILL64
2378
  { 768,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #768 = NILMux
2379
  { 769,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #769 = NIY
2380
  { 770,  3,  1,  2,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23000ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #770 = NR
2381
  { 771,  3,  1,  4,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x23000ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #771 = NRK
2382
  { 772,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x10cULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #772 = NTSTG
2383
  { 773,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2308cULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #773 = NY
2384
  { 774,  5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x23088ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #774 = O
2385
  { 775,  5,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo85, -1 ,nullptr },  // Inst #775 = OC
2386
  { 776,  6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #776 = OCLoop
2387
  { 777,  5,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #777 = OCSequence
2388
  { 778,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2310cULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #778 = OG
2389
  { 779,  3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23000ULL, nullptr, ImplicitList1, OperandInfo26, -1 ,nullptr },  // Inst #779 = OGR
2390
  { 780,  3,  1,  4,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x23000ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #780 = OGRK
2391
  { 781,  3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #781 = OI
2392
  { 782,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x23000ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #782 = OIFMux
2393
  { 783,  3,  1,  6,  0,  0, 0x23000ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #783 = OIHF
2394
  { 784,  3,  1,  6,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #784 = OIHF64
2395
  { 785,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #785 = OIHH
2396
  { 786,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #786 = OIHH64
2397
  { 787,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #787 = OIHL
2398
  { 788,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #788 = OIHL64
2399
  { 789,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #789 = OIHMux
2400
  { 790,  3,  1,  6,  0,  0, 0x23000ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #790 = OILF
2401
  { 791,  3,  1,  6,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #791 = OILF64
2402
  { 792,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #792 = OILH
2403
  { 793,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #793 = OILH64
2404
  { 794,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #794 = OILL
2405
  { 795,  3,  1,  4,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #795 = OILL64
2406
  { 796,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #796 = OILMux
2407
  { 797,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #797 = OIY
2408
  { 798,  3,  1,  2,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23000ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #798 = OR
2409
  { 799,  3,  1,  4,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x23000ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #799 = ORK
2410
  { 800,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2308cULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #800 = OY
2411
  { 801,  4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0xcULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #801 = PFD
2412
  { 802,  2,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #802 = PFDRL
2413
  { 803,  2,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo81, -1 ,nullptr },  // Inst #803 = POPCNT
2414
  { 804,  3,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo25, -1 ,nullptr },  // Inst #804 = PPA
2415
  { 805,  6,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3b800ULL, nullptr, ImplicitList1, OperandInfo152, -1 ,nullptr },  // Inst #805 = RISBG
2416
  { 806,  6,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo153, -1 ,nullptr },  // Inst #806 = RISBG32
2417
  { 807,  6,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #807 = RISBGN
2418
  { 808,  6,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr },  // Inst #808 = RISBHG
2419
  { 809,  6,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #809 = RISBHH
2420
  { 810,  6,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #810 = RISBHL
2421
  { 811,  6,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #811 = RISBLG
2422
  { 812,  6,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #812 = RISBLH
2423
  { 813,  6,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #813 = RISBLL
2424
  { 814,  6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #814 = RISBMux
2425
  { 815,  4,  1,  6,  0,  0, 0x4ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #815 = RLL
2426
  { 816,  4,  1,  6,  0,  0, 0x4ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #816 = RLLG
2427
  { 817,  6,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo152, -1 ,nullptr },  // Inst #817 = RNSBG
2428
  { 818,  6,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo152, -1 ,nullptr },  // Inst #818 = ROSBG
2429
  { 819,  6,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo152, -1 ,nullptr },  // Inst #819 = RXSBG
2430
  { 820,  0,  0,  2,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #820 = Return
2431
  { 821,  5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x23c88ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #821 = S
2432
  { 822,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x3fd08ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #822 = SDB
2433
  { 823,  3,  1,  4,  0,  0, 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #823 = SDBR
2434
  { 824,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x3fc88ULL, nullptr, ImplicitList1, OperandInfo17, -1 ,nullptr },  // Inst #824 = SEB
2435
  { 825,  3,  1,  4,  0,  0, 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo18, -1 ,nullptr },  // Inst #825 = SEBR
2436
  { 826,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x23d0cULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #826 = SG
2437
  { 827,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x23c8cULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #827 = SGF
2438
  { 828,  3,  1,  4,  0,  0, 0x23c00ULL, nullptr, ImplicitList1, OperandInfo24, -1 ,nullptr },  // Inst #828 = SGFR
2439
  { 829,  3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo26, -1 ,nullptr },  // Inst #829 = SGR
2440
  { 830,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #830 = SGRK
2441
  { 831,  5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x23c48ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #831 = SH
2442
  { 832,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x23c4cULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #832 = SHY
2443
  { 833,  5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #833 = SL
2444
  { 834,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, ImplicitList1, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #834 = SLB
2445
  { 835,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x10cULL, ImplicitList1, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #835 = SLBG
2446
  { 836,  3,  1,  4,  0,  0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo26, -1 ,nullptr },  // Inst #836 = SLBGR
2447
  { 837,  3,  1,  4,  0,  0, 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #837 = SLBR
2448
  { 838,  3,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #838 = SLFI
2449
  { 839,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x10cULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #839 = SLG
2450
  { 840,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #840 = SLGF
2451
  { 841,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #841 = SLGFI
2452
  { 842,  3,  1,  4,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo24, -1 ,nullptr },  // Inst #842 = SLGFR
2453
  { 843,  3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo26, -1 ,nullptr },  // Inst #843 = SLGR
2454
  { 844,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #844 = SLGRK
2455
  { 845,  4,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #845 = SLL
2456
  { 846,  4,  1,  6,  0,  0, 0x4ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #846 = SLLG
2457
  { 847,  4,  1,  6,  0,  0, 0x4ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #847 = SLLK
2458
  { 848,  3,  1,  2,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #848 = SLR
2459
  { 849,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #849 = SLRK
2460
  { 850,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x8cULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #850 = SLY
2461
  { 851,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x108ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #851 = SQDB
2462
  { 852,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #852 = SQDBR
2463
  { 853,  4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x88ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #853 = SQEB
2464
  { 854,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #854 = SQEBR
2465
  { 855,  2,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo104, -1 ,nullptr },  // Inst #855 = SQXBR
2466
  { 856,  3,  1,  2,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #856 = SR
2467
  { 857,  4,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3b800ULL, nullptr, ImplicitList1, OperandInfo162, -1 ,nullptr },  // Inst #857 = SRA
2468
  { 858,  4,  1,  6,  0,  0, 0x3b804ULL, nullptr, ImplicitList1, OperandInfo161, -1 ,nullptr },  // Inst #858 = SRAG
2469
  { 859,  4,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x3b804ULL, nullptr, ImplicitList1, OperandInfo160, -1 ,nullptr },  // Inst #859 = SRAK
2470
  { 860,  3,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x23c00ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #860 = SRK
2471
  { 861,  4,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #861 = SRL
2472
  { 862,  4,  1,  6,  0,  0, 0x4ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #862 = SRLG
2473
  { 863,  4,  1,  6,  0,  0, 0x4ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #863 = SRLK
2474
  { 864,  4,  2,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList1, OperandInfo96, -1 ,nullptr },  // Inst #864 = SRST
2475
  { 865,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo97, -1 ,nullptr },  // Inst #865 = SRSTLoop
2476
  { 866,  4,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x8aULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #866 = ST
2477
  { 867,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1eULL, nullptr, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #867 = ST128
2478
  { 868,  4,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x28ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #868 = STC
2479
  { 869,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x2cULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #869 = STCH
2480
  { 870,  2,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo163, -1 ,nullptr },  // Inst #870 = STCK
2481
  { 871,  2,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo163, -1 ,nullptr },  // Inst #871 = STCKE
2482
  { 872,  2,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo163, -1 ,nullptr },  // Inst #872 = STCKF
2483
  { 873,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2cULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #873 = STCMux
2484
  { 874,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x2cULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #874 = STCY
2485
  { 875,  4,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x10aULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #875 = STD
2486
  { 876,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x10eULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #876 = STDY
2487
  { 877,  4,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x8aULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #877 = STE
2488
  { 878,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x8eULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #878 = STEY
2489
  { 879,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x8eULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #879 = STFH
2490
  { 880,  2,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo163, -1 ,nullptr },  // Inst #880 = STFLE
2491
  { 881,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x10eULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #881 = STG
2492
  { 882,  2,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #882 = STGRL
2493
  { 883,  4,  0,  4,  0,  0|(1ULL<<MCID::MayStore), 0x48ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #883 = STH
2494
  { 884,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x4cULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #884 = STHH
2495
  { 885,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x2cULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #885 = STHMux
2496
  { 886,  2,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #886 = STHRL
2497
  { 887,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x4cULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #887 = STHY
2498
  { 888,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x4ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #888 = STMG
2499
  { 889,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x8eULL, nullptr, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #889 = STMux
2500
  { 890,  5,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80084ULL, ImplicitList1, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #890 = STOC
2501
  { 891,  5,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80104ULL, ImplicitList1, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #891 = STOCG
2502
  { 892,  2,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #892 = STRL
2503
  { 893,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x8cULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #893 = STRV
2504
  { 894,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x10cULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #894 = STRVG
2505
  { 895,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x1eULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #895 = STX
2506
  { 896,  4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x8eULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #896 = STY
2507
  { 897,  3,  1,  4,  0,  0, 0x3fc00ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr },  // Inst #897 = SXBR
2508
  { 898,  5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x23c8cULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #898 = SY
2509
  { 899,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo166, -1 ,nullptr },  // Inst #899 = Select32
2510
  { 900,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo167, -1 ,nullptr },  // Inst #900 = Select32Mux
2511
  { 901,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo168, -1 ,nullptr },  // Inst #901 = Select64
2512
  { 902,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo169, -1 ,nullptr },  // Inst #902 = SelectF128
2513
  { 903,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo170, -1 ,nullptr },  // Inst #903 = SelectF32
2514
  { 904,  5,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList1, ImplicitList1, OperandInfo171, -1 ,nullptr },  // Inst #904 = SelectF64
2515
  { 905,  0,  0,  2,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #905 = Serialize
2516
  { 906,  2,  0,  4,  0,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #906 = TABORT
2517
  { 907,  3,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #907 = TBEGIN
2518
  { 908,  3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #908 = TBEGINC
2519
  { 909,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #909 = TBEGIN_nofloat
2520
  { 910,  0,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, nullptr, -1 ,nullptr },  // Inst #910 = TEND
2521
  { 911,  1,  0,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo5, -1 ,nullptr },  // Inst #911 = TLS_GDCALL
2522
  { 912,  1,  0,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, ImplicitList3, OperandInfo5, -1 ,nullptr },  // Inst #912 = TLS_LDCALL
2523
  { 913,  3,  0,  4,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #913 = TM
2524
  { 914,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo84, -1 ,nullptr },  // Inst #914 = TMHH
2525
  { 915,  2,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #915 = TMHH64
2526
  { 916,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo84, -1 ,nullptr },  // Inst #916 = TMHL
2527
  { 917,  2,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #917 = TMHL64
2528
  { 918,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo75, -1 ,nullptr },  // Inst #918 = TMHMux
2529
  { 919,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo74, -1 ,nullptr },  // Inst #919 = TMLH
2530
  { 920,  2,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #920 = TMLH64
2531
  { 921,  2,  0,  4,  0,  0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo74, -1 ,nullptr },  // Inst #921 = TMLL
2532
  { 922,  2,  0,  4,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo79, -1 ,nullptr },  // Inst #922 = TMLL64
2533
  { 923,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo75, -1 ,nullptr },  // Inst #923 = TMLMux
2534
  { 924,  3,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::MayLoad), 0x4ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #924 = TMY
2535
  { 925,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #925 = VAB
2536
  { 926,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #926 = VACCB
2537
  { 927,  4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #927 = VACCCQ
2538
  { 928,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #928 = VACCF
2539
  { 929,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #929 = VACCG
2540
  { 930,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #930 = VACCH
2541
  { 931,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #931 = VACCQ
2542
  { 932,  4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #932 = VACQ
2543
  { 933,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #933 = VAF
2544
  { 934,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #934 = VAG
2545
  { 935,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #935 = VAH
2546
  { 936,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #936 = VAQ
2547
  { 937,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #937 = VAVGB
2548
  { 938,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #938 = VAVGF
2549
  { 939,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #939 = VAVGG
2550
  { 940,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #940 = VAVGH
2551
  { 941,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #941 = VAVGLB
2552
  { 942,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #942 = VAVGLF
2553
  { 943,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #943 = VAVGLG
2554
  { 944,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #944 = VAVGLH
2555
  { 945,  4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #945 = VCDGB
2556
  { 946,  4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #946 = VCDLGB
2557
  { 947,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #947 = VCEQB
2558
  { 948,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #948 = VCEQBS
2559
  { 949,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #949 = VCEQF
2560
  { 950,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #950 = VCEQFS
2561
  { 951,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #951 = VCEQG
2562
  { 952,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #952 = VCEQGS
2563
  { 953,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #953 = VCEQH
2564
  { 954,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #954 = VCEQHS
2565
  { 955,  4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #955 = VCGDB
2566
  { 956,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #956 = VCHB
2567
  { 957,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #957 = VCHBS
2568
  { 958,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #958 = VCHF
2569
  { 959,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #959 = VCHFS
2570
  { 960,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #960 = VCHG
2571
  { 961,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #961 = VCHGS
2572
  { 962,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #962 = VCHH
2573
  { 963,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #963 = VCHHS
2574
  { 964,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #964 = VCHLB
2575
  { 965,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #965 = VCHLBS
2576
  { 966,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #966 = VCHLF
2577
  { 967,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #967 = VCHLFS
2578
  { 968,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #968 = VCHLG
2579
  { 969,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #969 = VCHLGS
2580
  { 970,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #970 = VCHLH
2581
  { 971,  3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #971 = VCHLHS
2582
  { 972,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #972 = VCKSM
2583
  { 973,  4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #973 = VCLGDB
2584
  { 974,  2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #974 = VCLZB
2585
  { 975,  2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #975 = VCLZF
2586
  { 976,  2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #976 = VCLZG
2587
  { 977,  2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #977 = VCLZH
2588
  { 978,  2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #978 = VCTZB
2589
  { 979,  2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #979 = VCTZF
2590
  { 980,  2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #980 = VCTZG
2591
  { 981,  2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #981 = VCTZH
2592
  { 982,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #982 = VECB
2593
  { 983,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #983 = VECF
2594
  { 984,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #984 = VECG
2595
  { 985,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #985 = VECH
2596
  { 986,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #986 = VECLB
2597
  { 987,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #987 = VECLF
2598
  { 988,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #988 = VECLG
2599
  { 989,  2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #989 = VECLH
2600
  { 990,  5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #990 = VERIMB
2601
  { 991,  5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #991 = VERIMF
2602
  { 992,  5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #992 = VERIMG
2603
  { 993,  5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #993 = VERIMH
2604
  { 994,  4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #994 = VERLLB
2605
  { 995,  4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #995 = VERLLF
2606
  { 996,  4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #996 = VERLLG
2607
  { 997,  4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #997 = VERLLH
2608
  { 998,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #998 = VERLLVB
2609
  { 999,  3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #999 = VERLLVF
2610
  { 1000, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1000 = VERLLVG
2611
  { 1001, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1001 = VERLLVH
2612
  { 1002, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1002 = VESLB
2613
  { 1003, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1003 = VESLF
2614
  { 1004, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1004 = VESLG
2615
  { 1005, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1005 = VESLH
2616
  { 1006, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1006 = VESLVB
2617
  { 1007, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1007 = VESLVF
2618
  { 1008, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1008 = VESLVG
2619
  { 1009, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1009 = VESLVH
2620
  { 1010, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1010 = VESRAB
2621
  { 1011, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1011 = VESRAF
2622
  { 1012, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1012 = VESRAG
2623
  { 1013, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1013 = VESRAH
2624
  { 1014, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1014 = VESRAVB
2625
  { 1015, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1015 = VESRAVF
2626
  { 1016, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1016 = VESRAVG
2627
  { 1017, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1017 = VESRAVH
2628
  { 1018, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1018 = VESRLB
2629
  { 1019, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1019 = VESRLF
2630
  { 1020, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1020 = VESRLG
2631
  { 1021, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1021 = VESRLH
2632
  { 1022, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1022 = VESRLVB
2633
  { 1023, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1023 = VESRLVF
2634
  { 1024, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1024 = VESRLVG
2635
  { 1025, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1025 = VESRLVH
2636
  { 1026, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1026 = VFADB
2637
  { 1027, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1027 = VFAEB
2638
  { 1028, 4,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo178, -1 ,nullptr },  // Inst #1028 = VFAEBS
2639
  { 1029, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1029 = VFAEF
2640
  { 1030, 4,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo178, -1 ,nullptr },  // Inst #1030 = VFAEFS
2641
  { 1031, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1031 = VFAEH
2642
  { 1032, 4,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo178, -1 ,nullptr },  // Inst #1032 = VFAEHS
2643
  { 1033, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1033 = VFAEZB
2644
  { 1034, 4,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo178, -1 ,nullptr },  // Inst #1034 = VFAEZBS
2645
  { 1035, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1035 = VFAEZF
2646
  { 1036, 4,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo178, -1 ,nullptr },  // Inst #1036 = VFAEZFS
2647
  { 1037, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1037 = VFAEZH
2648
  { 1038, 4,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo178, -1 ,nullptr },  // Inst #1038 = VFAEZHS
2649
  { 1039, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1039 = VFCEDB
2650
  { 1040, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1040 = VFCEDBS
2651
  { 1041, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1041 = VFCHDB
2652
  { 1042, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1042 = VFCHDBS
2653
  { 1043, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1043 = VFCHEDB
2654
  { 1044, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1044 = VFCHEDBS
2655
  { 1045, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1045 = VFDDB
2656
  { 1046, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1046 = VFEEB
2657
  { 1047, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1047 = VFEEBS
2658
  { 1048, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1048 = VFEEF
2659
  { 1049, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1049 = VFEEFS
2660
  { 1050, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1050 = VFEEH
2661
  { 1051, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1051 = VFEEHS
2662
  { 1052, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1052 = VFEEZB
2663
  { 1053, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1053 = VFEEZBS
2664
  { 1054, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1054 = VFEEZF
2665
  { 1055, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1055 = VFEEZFS
2666
  { 1056, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1056 = VFEEZH
2667
  { 1057, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1057 = VFEEZHS
2668
  { 1058, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1058 = VFENEB
2669
  { 1059, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1059 = VFENEBS
2670
  { 1060, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1060 = VFENEF
2671
  { 1061, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1061 = VFENEFS
2672
  { 1062, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1062 = VFENEH
2673
  { 1063, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1063 = VFENEHS
2674
  { 1064, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1064 = VFENEZB
2675
  { 1065, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1065 = VFENEZBS
2676
  { 1066, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1066 = VFENEZF
2677
  { 1067, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1067 = VFENEZFS
2678
  { 1068, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1068 = VFENEZH
2679
  { 1069, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1069 = VFENEZHS
2680
  { 1070, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1070 = VFIDB
2681
  { 1071, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1071 = VFLCDB
2682
  { 1072, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1072 = VFLNDB
2683
  { 1073, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1073 = VFLPDB
2684
  { 1074, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1074 = VFMADB
2685
  { 1075, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1075 = VFMDB
2686
  { 1076, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1076 = VFMSDB
2687
  { 1077, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1077 = VFSDB
2688
  { 1078, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1078 = VFSQDB
2689
  { 1079, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo179, -1 ,nullptr },  // Inst #1079 = VFTCIDB
2690
  { 1080, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1080 = VGBM
2691
  { 1081, 6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1081 = VGEF
2692
  { 1082, 6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1082 = VGEG
2693
  { 1083, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1083 = VGFMAB
2694
  { 1084, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1084 = VGFMAF
2695
  { 1085, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1085 = VGFMAG
2696
  { 1086, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1086 = VGFMAH
2697
  { 1087, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1087 = VGFMB
2698
  { 1088, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1088 = VGFMF
2699
  { 1089, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1089 = VGFMG
2700
  { 1090, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1090 = VGFMH
2701
  { 1091, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1091 = VGMB
2702
  { 1092, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1092 = VGMF
2703
  { 1093, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1093 = VGMG
2704
  { 1094, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1094 = VGMH
2705
  { 1095, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1095 = VISTRB
2706
  { 1096, 2,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #1096 = VISTRBS
2707
  { 1097, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1097 = VISTRF
2708
  { 1098, 2,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #1098 = VISTRFS
2709
  { 1099, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1099 = VISTRH
2710
  { 1100, 2,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #1100 = VISTRHS
2711
  { 1101, 4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x200ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1101 = VL
2712
  { 1102, 4,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1102 = VL32
2713
  { 1103, 4,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr },  // Inst #1103 = VL64
2714
  { 1104, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1104 = VLBB
2715
  { 1105, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1105 = VLCB
2716
  { 1106, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1106 = VLCF
2717
  { 1107, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1107 = VLCG
2718
  { 1108, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1108 = VLCH
2719
  { 1109, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1109 = VLDEB
2720
  { 1110, 6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x20ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1110 = VLEB
2721
  { 1111, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1111 = VLEDB
2722
  { 1112, 6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1112 = VLEF
2723
  { 1113, 6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x100ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1113 = VLEG
2724
  { 1114, 6,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1114 = VLEH
2725
  { 1115, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr },  // Inst #1115 = VLEIB
2726
  { 1116, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr },  // Inst #1116 = VLEIF
2727
  { 1117, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr },  // Inst #1117 = VLEIG
2728
  { 1118, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr },  // Inst #1118 = VLEIH
2729
  { 1119, 4,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1119 = VLGVB
2730
  { 1120, 4,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1120 = VLGVF
2731
  { 1121, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1121 = VLGVG
2732
  { 1122, 4,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1122 = VLGVH
2733
  { 1123, 4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr },  // Inst #1123 = VLL
2734
  { 1124, 4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x20ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1124 = VLLEZB
2735
  { 1125, 4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1125 = VLLEZF
2736
  { 1126, 4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x100ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1126 = VLLEZG
2737
  { 1127, 4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1127 = VLLEZH
2738
  { 1128, 4,  2,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1128 = VLM
2739
  { 1129, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1129 = VLPB
2740
  { 1130, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1130 = VLPF
2741
  { 1131, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1131 = VLPG
2742
  { 1132, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1132 = VLPH
2743
  { 1133, 2,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1133 = VLR
2744
  { 1134, 2,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1134 = VLR32
2745
  { 1135, 2,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1135 = VLR64
2746
  { 1136, 4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x20ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1136 = VLREPB
2747
  { 1137, 4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x80ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1137 = VLREPF
2748
  { 1138, 4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x100ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1138 = VLREPG
2749
  { 1139, 4,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x40ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1139 = VLREPH
2750
  { 1140, 5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1140 = VLVGB
2751
  { 1141, 5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1141 = VLVGF
2752
  { 1142, 5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1142 = VLVGG
2753
  { 1143, 5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1143 = VLVGH
2754
  { 1144, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1144 = VLVGP
2755
  { 1145, 3,  1,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr },  // Inst #1145 = VLVGP32
2756
  { 1146, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1146 = VMAEB
2757
  { 1147, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1147 = VMAEF
2758
  { 1148, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1148 = VMAEH
2759
  { 1149, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1149 = VMAHB
2760
  { 1150, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1150 = VMAHF
2761
  { 1151, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1151 = VMAHH
2762
  { 1152, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1152 = VMALB
2763
  { 1153, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1153 = VMALEB
2764
  { 1154, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1154 = VMALEF
2765
  { 1155, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1155 = VMALEH
2766
  { 1156, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1156 = VMALF
2767
  { 1157, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1157 = VMALHB
2768
  { 1158, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1158 = VMALHF
2769
  { 1159, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1159 = VMALHH
2770
  { 1160, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1160 = VMALHW
2771
  { 1161, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1161 = VMALOB
2772
  { 1162, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1162 = VMALOF
2773
  { 1163, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1163 = VMALOH
2774
  { 1164, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1164 = VMAOB
2775
  { 1165, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1165 = VMAOF
2776
  { 1166, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1166 = VMAOH
2777
  { 1167, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1167 = VMEB
2778
  { 1168, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1168 = VMEF
2779
  { 1169, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1169 = VMEH
2780
  { 1170, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1170 = VMHB
2781
  { 1171, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1171 = VMHF
2782
  { 1172, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1172 = VMHH
2783
  { 1173, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1173 = VMLB
2784
  { 1174, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1174 = VMLEB
2785
  { 1175, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1175 = VMLEF
2786
  { 1176, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1176 = VMLEH
2787
  { 1177, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1177 = VMLF
2788
  { 1178, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1178 = VMLHB
2789
  { 1179, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1179 = VMLHF
2790
  { 1180, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1180 = VMLHH
2791
  { 1181, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1181 = VMLHW
2792
  { 1182, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1182 = VMLOB
2793
  { 1183, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1183 = VMLOF
2794
  { 1184, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1184 = VMLOH
2795
  { 1185, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1185 = VMNB
2796
  { 1186, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1186 = VMNF
2797
  { 1187, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1187 = VMNG
2798
  { 1188, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1188 = VMNH
2799
  { 1189, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1189 = VMNLB
2800
  { 1190, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1190 = VMNLF
2801
  { 1191, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1191 = VMNLG
2802
  { 1192, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1192 = VMNLH
2803
  { 1193, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1193 = VMOB
2804
  { 1194, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1194 = VMOF
2805
  { 1195, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1195 = VMOH
2806
  { 1196, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1196 = VMRHB
2807
  { 1197, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1197 = VMRHF
2808
  { 1198, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1198 = VMRHG
2809
  { 1199, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1199 = VMRHH
2810
  { 1200, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1200 = VMRLB
2811
  { 1201, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1201 = VMRLF
2812
  { 1202, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1202 = VMRLG
2813
  { 1203, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1203 = VMRLH
2814
  { 1204, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1204 = VMXB
2815
  { 1205, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1205 = VMXF
2816
  { 1206, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1206 = VMXG
2817
  { 1207, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1207 = VMXH
2818
  { 1208, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1208 = VMXLB
2819
  { 1209, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1209 = VMXLF
2820
  { 1210, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1210 = VMXLG
2821
  { 1211, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1211 = VMXLH
2822
  { 1212, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1212 = VN
2823
  { 1213, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1213 = VNC
2824
  { 1214, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1214 = VNO
2825
  { 1215, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1215 = VO
2826
  { 1216, 1,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #1216 = VONE
2827
  { 1217, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1217 = VPDI
2828
  { 1218, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1218 = VPERM
2829
  { 1219, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1219 = VPKF
2830
  { 1220, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1220 = VPKG
2831
  { 1221, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1221 = VPKH
2832
  { 1222, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1222 = VPKLSF
2833
  { 1223, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1223 = VPKLSFS
2834
  { 1224, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1224 = VPKLSG
2835
  { 1225, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1225 = VPKLSGS
2836
  { 1226, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1226 = VPKLSH
2837
  { 1227, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1227 = VPKLSHS
2838
  { 1228, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1228 = VPKSF
2839
  { 1229, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1229 = VPKSFS
2840
  { 1230, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1230 = VPKSG
2841
  { 1231, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1231 = VPKSGS
2842
  { 1232, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1232 = VPKSH
2843
  { 1233, 3,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo172, -1 ,nullptr },  // Inst #1233 = VPKSHS
2844
  { 1234, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1234 = VPOPCT
2845
  { 1235, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1235 = VREPB
2846
  { 1236, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1236 = VREPF
2847
  { 1237, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1237 = VREPG
2848
  { 1238, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1238 = VREPH
2849
  { 1239, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1239 = VREPIB
2850
  { 1240, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1240 = VREPIF
2851
  { 1241, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1241 = VREPIG
2852
  { 1242, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1242 = VREPIH
2853
  { 1243, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1243 = VSB
2854
  { 1244, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1244 = VSBCBIQ
2855
  { 1245, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1245 = VSBIQ
2856
  { 1246, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1246 = VSCBIB
2857
  { 1247, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1247 = VSCBIF
2858
  { 1248, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1248 = VSCBIG
2859
  { 1249, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1249 = VSCBIH
2860
  { 1250, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1250 = VSCBIQ
2861
  { 1251, 5,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1251 = VSCEF
2862
  { 1252, 5,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1252 = VSCEG
2863
  { 1253, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1253 = VSEGB
2864
  { 1254, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1254 = VSEGF
2865
  { 1255, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1255 = VSEGH
2866
  { 1256, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1256 = VSEL
2867
  { 1257, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1257 = VSF
2868
  { 1258, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1258 = VSG
2869
  { 1259, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1259 = VSH
2870
  { 1260, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1260 = VSL
2871
  { 1261, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1261 = VSLB
2872
  { 1262, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1262 = VSLDB
2873
  { 1263, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1263 = VSQ
2874
  { 1264, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1264 = VSRA
2875
  { 1265, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1265 = VSRAB
2876
  { 1266, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1266 = VSRL
2877
  { 1267, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1267 = VSRLB
2878
  { 1268, 4,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x200ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1268 = VST
2879
  { 1269, 4,  0,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1269 = VST32
2880
  { 1270, 4,  0,  6,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo185, -1 ,nullptr },  // Inst #1270 = VST64
2881
  { 1271, 5,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x20ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1271 = VSTEB
2882
  { 1272, 5,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x80ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1272 = VSTEF
2883
  { 1273, 5,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x100ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1273 = VSTEG
2884
  { 1274, 5,  0,  6,  0,  0|(1ULL<<MCID::MayStore), 0x40ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1274 = VSTEH
2885
  { 1275, 4,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr },  // Inst #1275 = VSTL
2886
  { 1276, 4,  0,  6,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1276 = VSTM
2887
  { 1277, 5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1277 = VSTRCB
2888
  { 1278, 5,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo200, -1 ,nullptr },  // Inst #1278 = VSTRCBS
2889
  { 1279, 5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1279 = VSTRCF
2890
  { 1280, 5,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo200, -1 ,nullptr },  // Inst #1280 = VSTRCFS
2891
  { 1281, 5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1281 = VSTRCH
2892
  { 1282, 5,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo200, -1 ,nullptr },  // Inst #1282 = VSTRCHS
2893
  { 1283, 5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1283 = VSTRCZB
2894
  { 1284, 5,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo200, -1 ,nullptr },  // Inst #1284 = VSTRCZBS
2895
  { 1285, 5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1285 = VSTRCZF
2896
  { 1286, 5,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo200, -1 ,nullptr },  // Inst #1286 = VSTRCZFS
2897
  { 1287, 5,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1287 = VSTRCZH
2898
  { 1288, 5,  1,  6,  0,  0, 0x0ULL, nullptr, ImplicitList1, OperandInfo200, -1 ,nullptr },  // Inst #1288 = VSTRCZHS
2899
  { 1289, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1289 = VSUMB
2900
  { 1290, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1290 = VSUMGF
2901
  { 1291, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1291 = VSUMGH
2902
  { 1292, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1292 = VSUMH
2903
  { 1293, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1293 = VSUMQF
2904
  { 1294, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1294 = VSUMQG
2905
  { 1295, 2,  0,  6,  0,  0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo175, -1 ,nullptr },  // Inst #1295 = VTM
2906
  { 1296, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1296 = VUPHB
2907
  { 1297, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1297 = VUPHF
2908
  { 1298, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1298 = VUPHH
2909
  { 1299, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1299 = VUPLB
2910
  { 1300, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1300 = VUPLF
2911
  { 1301, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1301 = VUPLHB
2912
  { 1302, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1302 = VUPLHF
2913
  { 1303, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1303 = VUPLHH
2914
  { 1304, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1304 = VUPLHW
2915
  { 1305, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1305 = VUPLLB
2916
  { 1306, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1306 = VUPLLF
2917
  { 1307, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1307 = VUPLLH
2918
  { 1308, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1308 = VX
2919
  { 1309, 1,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #1309 = VZERO
2920
  { 1310, 4,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1310 = WCDGB
2921
  { 1311, 4,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1311 = WCDLGB
2922
  { 1312, 4,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1312 = WCGDB
2923
  { 1313, 4,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1313 = WCLGDB
2924
  { 1314, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1314 = WFADB
2925
  { 1315, 2,  0,  6,  0,  0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr },  // Inst #1315 = WFCDB
2926
  { 1316, 3,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1316 = WFCEDB
2927
  { 1317, 3,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo202, -1 ,nullptr },  // Inst #1317 = WFCEDBS
2928
  { 1318, 3,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1318 = WFCHDB
2929
  { 1319, 3,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo202, -1 ,nullptr },  // Inst #1319 = WFCHDBS
2930
  { 1320, 3,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1320 = WFCHEDB
2931
  { 1321, 3,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo202, -1 ,nullptr },  // Inst #1321 = WFCHEDBS
2932
  { 1322, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1322 = WFDDB
2933
  { 1323, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1323 = WFIDB
2934
  { 1324, 2,  0,  6,  0,  0|(1ULL<<MCID::Compare)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo193, -1 ,nullptr },  // Inst #1324 = WFKDB
2935
  { 1325, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1325 = WFLCDB
2936
  { 1326, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1326 = WFLNDB
2937
  { 1327, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1327 = WFLPDB
2938
  { 1328, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr },  // Inst #1328 = WFMADB
2939
  { 1329, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1329 = WFMDB
2940
  { 1330, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr },  // Inst #1330 = WFMSDB
2941
  { 1331, 3,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1331 = WFSDB
2942
  { 1332, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1332 = WFSQDB
2943
  { 1333, 3,  1,  6,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo204, -1 ,nullptr },  // Inst #1333 = WFTCIDB
2944
  { 1334, 2,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1334 = WLDEB
2945
  { 1335, 4,  1,  6,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1335 = WLEDB
2946
  { 1336, 5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x23088ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #1336 = X
2947
  { 1337, 5,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo85, -1 ,nullptr },  // Inst #1337 = XC
2948
  { 1338, 6,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo86, -1 ,nullptr },  // Inst #1338 = XCLoop
2949
  { 1339, 5,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo87, -1 ,nullptr },  // Inst #1339 = XCSequence
2950
  { 1340, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2310cULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #1340 = XG
2951
  { 1341, 3,  1,  4,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23000ULL, nullptr, ImplicitList1, OperandInfo26, -1 ,nullptr },  // Inst #1341 = XGR
2952
  { 1342, 3,  1,  4,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x23000ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #1342 = XGRK
2953
  { 1343, 3,  0,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #1343 = XI
2954
  { 1344, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x23000ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #1344 = XIFMux
2955
  { 1345, 3,  1,  6,  0,  0, 0x23000ULL, nullptr, ImplicitList1, OperandInfo31, -1 ,nullptr },  // Inst #1345 = XIHF
2956
  { 1346, 3,  1,  6,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #1346 = XIHF64
2957
  { 1347, 3,  1,  6,  0,  0, 0x23000ULL, nullptr, ImplicitList1, OperandInfo20, -1 ,nullptr },  // Inst #1347 = XILF
2958
  { 1348, 3,  1,  6,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, ImplicitList1, OperandInfo23, -1 ,nullptr },  // Inst #1348 = XILF64
2959
  { 1349, 3,  0,  6,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x4ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #1349 = XIY
2960
  { 1350, 3,  1,  2,  0,  0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x23000ULL, nullptr, ImplicitList1, OperandInfo32, -1 ,nullptr },  // Inst #1350 = XR
2961
  { 1351, 3,  1,  4,  0,  0|(1ULL<<MCID::Commutable)|(1ULL<<MCID::UnmodeledSideEffects), 0x23000ULL, nullptr, ImplicitList1, OperandInfo33, -1 ,nullptr },  // Inst #1351 = XRK
2962
  { 1352, 5,  1,  6,  0,  0|(1ULL<<MCID::MayLoad), 0x2308cULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #1352 = XY
2963
  { 1353, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1353 = ZEXT128_32
2964
  { 1354, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo19, -1 ,nullptr },  // Inst #1354 = ZEXT128_64
2965
};
2966
2967
46
static inline void InitSystemZMCInstrInfo(MCInstrInfo *II) {
2968
46
  II->InitMCInstrInfo(SystemZInsts, NULL, NULL, 1355);
2969
46
}
2970
2971
} // end llvm namespace 
2972
#endif // GET_INSTRINFO_MC_DESC
2973
2974
2975
#ifdef GET_INSTRINFO_HEADER
2976
#undef GET_INSTRINFO_HEADER
2977
namespace llvm_ks {
2978
struct SystemZGenInstrInfo : public TargetInstrInfo {
2979
  explicit SystemZGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1);
2980
  ~SystemZGenInstrInfo() override {}
2981
};
2982
} // end llvm namespace 
2983
#endif // GET_INSTRINFO_HEADER
2984
2985
2986
#ifdef GET_INSTRINFO_OPERAND_ENUM
2987
#undef GET_INSTRINFO_OPERAND_ENUM
2988
namespace llvm_ks {
2989
namespace SystemZ {
2990
namespace OpName { 
2991
enum {
2992
OPERAND_LAST
2993
};
2994
} // end namespace OpName
2995
} // end namespace SystemZ
2996
} // end namespace llvm_ks
2997
#endif //GET_INSTRINFO_OPERAND_ENUM
2998
#ifdef GET_INSTRINFO_NAMED_OPS
2999
#undef GET_INSTRINFO_NAMED_OPS
3000
namespace llvm_ks {
3001
namespace SystemZ {
3002
LLVM_READONLY
3003
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
3004
  return -1;
3005
}
3006
} // end namespace SystemZ
3007
} // end namespace llvm_ks
3008
#endif //GET_INSTRINFO_NAMED_OPS
3009
3010
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
3011
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
3012
namespace llvm_ks {
3013
namespace SystemZ {
3014
namespace OpTypes { 
3015
enum OperandType {
3016
  access_reg = 0,
3017
  bdaddr12only = 1,
3018
  bdaddr12pair = 2,
3019
  bdaddr20only = 3,
3020
  bdaddr20pair = 4,
3021
  bdladdr12onlylen8 = 5,
3022
  bdvaddr12only = 6,
3023
  bdxaddr12only = 7,
3024
  bdxaddr12pair = 8,
3025
  bdxaddr20only = 9,
3026
  bdxaddr20only128 = 10,
3027
  bdxaddr20pair = 11,
3028
  brtarget16 = 12,
3029
  brtarget16tls = 13,
3030
  brtarget32 = 14,
3031
  brtarget32tls = 15,
3032
  cond4 = 16,
3033
  disp12imm32 = 17,
3034
  disp12imm64 = 18,
3035
  disp20imm32 = 19,
3036
  disp20imm64 = 20,
3037
  dynalloc12only = 21,
3038
  f32imm = 22,
3039
  f64imm = 23,
3040
  i16imm = 24,
3041
  i1imm = 25,
3042
  i32imm = 26,
3043
  i64imm = 27,
3044
  i8imm = 28,
3045
  imm32lh16 = 29,
3046
  imm32lh16c = 30,
3047
  imm32ll16 = 31,
3048
  imm32ll16c = 32,
3049
  imm32sx16 = 33,
3050
  imm32sx16trunc = 34,
3051
  imm32sx8 = 35,
3052
  imm32zx1 = 36,
3053
  imm32zx12 = 37,
3054
  imm32zx16 = 38,
3055
  imm32zx2 = 39,
3056
  imm32zx3 = 40,
3057
  imm32zx4 = 41,
3058
  imm32zx4even = 42,
3059
  imm32zx6 = 43,
3060
  imm32zx8 = 44,
3061
  imm32zx8trunc = 45,
3062
  imm64 = 46,
3063
  imm64hf32 = 47,
3064
  imm64hf32c = 48,
3065
  imm64hh16 = 49,
3066
  imm64hh16c = 50,
3067
  imm64hl16 = 51,
3068
  imm64hl16c = 52,
3069
  imm64lf32 = 53,
3070
  imm64lf32c = 54,
3071
  imm64lh16 = 55,
3072
  imm64lh16c = 56,
3073
  imm64ll16 = 57,
3074
  imm64ll16c = 58,
3075
  imm64sx16 = 59,
3076
  imm64sx32 = 60,
3077
  imm64sx8 = 61,
3078
  imm64zx16 = 62,
3079
  imm64zx32 = 63,
3080
  imm64zx32n = 64,
3081
  imm64zx8 = 65,
3082
  laaddr12pair = 66,
3083
  laaddr20pair = 67,
3084
  mviaddr12pair = 68,
3085
  mviaddr20pair = 69,
3086
  pcrel32 = 70,
3087
  shift12only = 71,
3088
  shift20only = 72,
3089
  simm32 = 73,
3090
  tlssym = 74,
3091
  uimm32 = 75,
3092
  OPERAND_TYPE_LIST_END
3093
};
3094
} // end namespace OpTypes
3095
} // end namespace SystemZ
3096
} // end namespace llvm_ks
3097
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
3098
#ifdef GET_INSTRMAP_INFO
3099
#undef GET_INSTRMAP_INFO
3100
namespace llvm_ks {
3101
3102
namespace SystemZ {
3103
3104
enum DispSize {
3105
  DispSize_12,
3106
  DispSize_20
3107
};
3108
3109
enum NumOpsValue {
3110
  NumOpsValue_3
3111
};
3112
3113
enum OpType {
3114
  OpType_mem
3115
};
3116
3117
// getDisp12Opcode
3118
LLVM_READONLY
3119
int getDisp12Opcode(uint16_t Opcode) {
3120
static const uint16_t getDisp12OpcodeTable[][2] = {
3121
  { SystemZ::AHY, SystemZ::AH },
3122
  { SystemZ::ALY, SystemZ::AL },
3123
  { SystemZ::AY, SystemZ::A },
3124
  { SystemZ::CHY, SystemZ::CH },
3125
  { SystemZ::CLIY, SystemZ::CLI },
3126
  { SystemZ::CLY, SystemZ::CL },
3127
  { SystemZ::CSY, SystemZ::CS },
3128
  { SystemZ::CY, SystemZ::C },
3129
  { SystemZ::IC32Y, SystemZ::IC32 },
3130
  { SystemZ::ICY, SystemZ::IC },
3131
  { SystemZ::LAY, SystemZ::LA },
3132
  { SystemZ::LDY, SystemZ::LD },
3133
  { SystemZ::LEY, SystemZ::LE },
3134
  { SystemZ::LHY, SystemZ::LH },
3135
  { SystemZ::LY, SystemZ::L },
3136
  { SystemZ::MHY, SystemZ::MH },
3137
  { SystemZ::MSY, SystemZ::MS },
3138
  { SystemZ::MVIY, SystemZ::MVI },
3139
  { SystemZ::NIY, SystemZ::NI },
3140
  { SystemZ::NY, SystemZ::N },
3141
  { SystemZ::OIY, SystemZ::OI },
3142
  { SystemZ::OY, SystemZ::O },
3143
  { SystemZ::SHY, SystemZ::SH },
3144
  { SystemZ::SLY, SystemZ::SL },
3145
  { SystemZ::STCY, SystemZ::STC },
3146
  { SystemZ::STDY, SystemZ::STD },
3147
  { SystemZ::STEY, SystemZ::STE },
3148
  { SystemZ::STHY, SystemZ::STH },
3149
  { SystemZ::STY, SystemZ::ST },
3150
  { SystemZ::SY, SystemZ::S },
3151
  { SystemZ::TMY, SystemZ::TM },
3152
  { SystemZ::XIY, SystemZ::XI },
3153
  { SystemZ::XY, SystemZ::X },
3154
}; // End of getDisp12OpcodeTable
3155
3156
  unsigned mid;
3157
  unsigned start = 0;
3158
  unsigned end = 33;
3159
  while (start < end) {
3160
    mid = start + (end - start)/2;
3161
    if (Opcode == getDisp12OpcodeTable[mid][0]) {
3162
      break;
3163
    }
3164
    if (Opcode < getDisp12OpcodeTable[mid][0])
3165
      end = mid;
3166
    else
3167
      start = mid + 1;
3168
  }
3169
  if (start == end)
3170
    return -1; // Instruction doesn't exist in this table.
3171
3172
  return getDisp12OpcodeTable[mid][1];
3173
}
3174
3175
// getDisp20Opcode
3176
LLVM_READONLY
3177
int getDisp20Opcode(uint16_t Opcode) {
3178
static const uint16_t getDisp20OpcodeTable[][2] = {
3179
  { SystemZ::A, SystemZ::AY },
3180
  { SystemZ::AH, SystemZ::AHY },
3181
  { SystemZ::AL, SystemZ::ALY },
3182
  { SystemZ::C, SystemZ::CY },
3183
  { SystemZ::CH, SystemZ::CHY },
3184
  { SystemZ::CL, SystemZ::CLY },
3185
  { SystemZ::CLI, SystemZ::CLIY },
3186
  { SystemZ::CS, SystemZ::CSY },
3187
  { SystemZ::IC, SystemZ::ICY },
3188
  { SystemZ::IC32, SystemZ::IC32Y },
3189
  { SystemZ::L, SystemZ::LY },
3190
  { SystemZ::LA, SystemZ::LAY },
3191
  { SystemZ::LD, SystemZ::LDY },
3192
  { SystemZ::LE, SystemZ::LEY },
3193
  { SystemZ::LH, SystemZ::LHY },
3194
  { SystemZ::MH, SystemZ::MHY },
3195
  { SystemZ::MS, SystemZ::MSY },
3196
  { SystemZ::MVI, SystemZ::MVIY },
3197
  { SystemZ::N, SystemZ::NY },
3198
  { SystemZ::NI, SystemZ::NIY },
3199
  { SystemZ::O, SystemZ::OY },
3200
  { SystemZ::OI, SystemZ::OIY },
3201
  { SystemZ::S, SystemZ::SY },
3202
  { SystemZ::SH, SystemZ::SHY },
3203
  { SystemZ::SL, SystemZ::SLY },
3204
  { SystemZ::ST, SystemZ::STY },
3205
  { SystemZ::STC, SystemZ::STCY },
3206
  { SystemZ::STD, SystemZ::STDY },
3207
  { SystemZ::STE, SystemZ::STEY },
3208
  { SystemZ::STH, SystemZ::STHY },
3209
  { SystemZ::TM, SystemZ::TMY },
3210
  { SystemZ::X, SystemZ::XY },
3211
  { SystemZ::XI, SystemZ::XIY },
3212
}; // End of getDisp20OpcodeTable
3213
3214
  unsigned mid;
3215
  unsigned start = 0;
3216
  unsigned end = 33;
3217
  while (start < end) {
3218
    mid = start + (end - start)/2;
3219
    if (Opcode == getDisp20OpcodeTable[mid][0]) {
3220
      break;
3221
    }
3222
    if (Opcode < getDisp20OpcodeTable[mid][0])
3223
      end = mid;
3224
    else
3225
      start = mid + 1;
3226
  }
3227
  if (start == end)
3228
    return -1; // Instruction doesn't exist in this table.
3229
3230
  return getDisp20OpcodeTable[mid][1];
3231
}
3232
3233
// getMemOpcode
3234
LLVM_READONLY
3235
int getMemOpcode(uint16_t Opcode) {
3236
static const uint16_t getMemOpcodeTable[][2] = {
3237
  { SystemZ::ADBR, SystemZ::ADB },
3238
  { SystemZ::AEBR, SystemZ::AEB },
3239
  { SystemZ::AGFR, SystemZ::AGF },
3240
  { SystemZ::AGR, SystemZ::AG },
3241
  { SystemZ::ALCGR, SystemZ::ALCG },
3242
  { SystemZ::ALCR, SystemZ::ALC },
3243
  { SystemZ::ALGFR, SystemZ::ALGF },
3244
  { SystemZ::ALGR, SystemZ::ALG },
3245
  { SystemZ::ALR, SystemZ::AL },
3246
  { SystemZ::AR, SystemZ::A },
3247
  { SystemZ::CDBR, SystemZ::CDB },
3248
  { SystemZ::CEBR, SystemZ::CEB },
3249
  { SystemZ::CGFR, SystemZ::CGF },
3250
  { SystemZ::CGR, SystemZ::CG },
3251
  { SystemZ::CLGFR, SystemZ::CLGF },
3252
  { SystemZ::CLGR, SystemZ::CLG },
3253
  { SystemZ::CLR, SystemZ::CL },
3254
  { SystemZ::CR, SystemZ::C },
3255
  { SystemZ::DDBR, SystemZ::DDB },
3256
  { SystemZ::DEBR, SystemZ::DEB },
3257
  { SystemZ::DLGR, SystemZ::DLG },
3258
  { SystemZ::DLR, SystemZ::DL },
3259
  { SystemZ::DSGFR, SystemZ::DSGF },
3260
  { SystemZ::DSGR, SystemZ::DSG },
3261
  { SystemZ::LBR, SystemZ::LB },
3262
  { SystemZ::LDEBR, SystemZ::LDEB },
3263
  { SystemZ::LDR, SystemZ::LD },
3264
  { SystemZ::LER, SystemZ::LE },
3265
  { SystemZ::LGBR, SystemZ::LGB },
3266
  { SystemZ::LGFR, SystemZ::LGF },
3267
  { SystemZ::LGHR, SystemZ::LGH },
3268
  { SystemZ::LGR, SystemZ::LG },
3269
  { SystemZ::LHR, SystemZ::LH },
3270
  { SystemZ::LLCR, SystemZ::LLC },
3271
  { SystemZ::LLCRMux, SystemZ::LLCMux },
3272
  { SystemZ::LLGCR, SystemZ::LLGC },
3273
  { SystemZ::LLGFR, SystemZ::LLGF },
3274
  { SystemZ::LLGHR, SystemZ::LLGH },
3275
  { SystemZ::LLHR, SystemZ::LLH },
3276
  { SystemZ::LLHRMux, SystemZ::LLHMux },
3277
  { SystemZ::LR, SystemZ::L },
3278
  { SystemZ::LRMux, SystemZ::LMux },
3279
  { SystemZ::LRVGR, SystemZ::LRVG },
3280
  { SystemZ::LRVR, SystemZ::LRV },
3281
  { SystemZ::LTGFR, SystemZ::LTGF },
3282
  { SystemZ::LTGR, SystemZ::LTG },
3283
  { SystemZ::LTR, SystemZ::LT },
3284
  { SystemZ::LXDBR, SystemZ::LXDB },
3285
  { SystemZ::LXEBR, SystemZ::LXEB },
3286
  { SystemZ::MADBR, SystemZ::MADB },
3287
  { SystemZ::MAEBR, SystemZ::MAEB },
3288
  { SystemZ::MDBR, SystemZ::MDB },
3289
  { SystemZ::MDEBR, SystemZ::MDEB },
3290
  { SystemZ::MEEBR, SystemZ::MEEB },
3291
  { SystemZ::MLGR, SystemZ::MLG },
3292
  { SystemZ::MSDBR, SystemZ::MSDB },
3293
  { SystemZ::MSEBR, SystemZ::MSEB },
3294
  { SystemZ::MSGFR, SystemZ::MSGF },
3295
  { SystemZ::MSGR, SystemZ::MSG },
3296
  { SystemZ::MSR, SystemZ::MS },
3297
  { SystemZ::MXDBR, SystemZ::MXDB },
3298
  { SystemZ::NGR, SystemZ::NG },
3299
  { SystemZ::NR, SystemZ::N },
3300
  { SystemZ::OGR, SystemZ::OG },
3301
  { SystemZ::OR, SystemZ::O },
3302
  { SystemZ::SDBR, SystemZ::SDB },
3303
  { SystemZ::SEBR, SystemZ::SEB },
3304
  { SystemZ::SGFR, SystemZ::SGF },
3305
  { SystemZ::SGR, SystemZ::SG },
3306
  { SystemZ::SLBGR, SystemZ::SLBG },
3307
  { SystemZ::SLBR, SystemZ::SLB },
3308
  { SystemZ::SLGFR, SystemZ::SLGF },
3309
  { SystemZ::SLGR, SystemZ::SLG },
3310
  { SystemZ::SLR, SystemZ::SL },
3311
  { SystemZ::SQDBR, SystemZ::SQDB },
3312
  { SystemZ::SQEBR, SystemZ::SQEB },
3313
  { SystemZ::SR, SystemZ::S },
3314
  { SystemZ::XGR, SystemZ::XG },
3315
  { SystemZ::XR, SystemZ::X },
3316
}; // End of getMemOpcodeTable
3317
3318
  unsigned mid;
3319
  unsigned start = 0;
3320
  unsigned end = 79;
3321
  while (start < end) {
3322
    mid = start + (end - start)/2;
3323
    if (Opcode == getMemOpcodeTable[mid][0]) {
3324
      break;
3325
    }
3326
    if (Opcode < getMemOpcodeTable[mid][0])
3327
      end = mid;
3328
    else
3329
      start = mid + 1;
3330
  }
3331
  if (start == end)
3332
    return -1; // Instruction doesn't exist in this table.
3333
3334
  return getMemOpcodeTable[mid][1];
3335
}
3336
3337
// getThreeOperandOpcode
3338
LLVM_READONLY
3339
int getThreeOperandOpcode(uint16_t Opcode) {
3340
static const uint16_t getThreeOperandOpcodeTable[][2] = {
3341
  { SystemZ::AGHI, SystemZ::AGHIK },
3342
  { SystemZ::AGR, SystemZ::AGRK },
3343
  { SystemZ::AHI, SystemZ::AHIK },
3344
  { SystemZ::AHIMux, SystemZ::AHIMuxK },
3345
  { SystemZ::ALGR, SystemZ::ALGRK },
3346
  { SystemZ::ALR, SystemZ::ALRK },
3347
  { SystemZ::AR, SystemZ::ARK },
3348
  { SystemZ::NGR, SystemZ::NGRK },
3349
  { SystemZ::NR, SystemZ::NRK },
3350
  { SystemZ::OGR, SystemZ::OGRK },
3351
  { SystemZ::OR, SystemZ::ORK },
3352
  { SystemZ::SGR, SystemZ::SGRK },
3353
  { SystemZ::SLGR, SystemZ::SLGRK },
3354
  { SystemZ::SLL, SystemZ::SLLK },
3355
  { SystemZ::SLR, SystemZ::SLRK },
3356
  { SystemZ::SR, SystemZ::SRK },
3357
  { SystemZ::SRA, SystemZ::SRAK },
3358
  { SystemZ::SRL, SystemZ::SRLK },
3359
  { SystemZ::XGR, SystemZ::XGRK },
3360
  { SystemZ::XR, SystemZ::XRK },
3361
}; // End of getThreeOperandOpcodeTable
3362
3363
  unsigned mid;
3364
  unsigned start = 0;
3365
  unsigned end = 20;
3366
  while (start < end) {
3367
    mid = start + (end - start)/2;
3368
    if (Opcode == getThreeOperandOpcodeTable[mid][0]) {
3369
      break;
3370
    }
3371
    if (Opcode < getThreeOperandOpcodeTable[mid][0])
3372
      end = mid;
3373
    else
3374
      start = mid + 1;
3375
  }
3376
  if (start == end)
3377
    return -1; // Instruction doesn't exist in this table.
3378
3379
  return getThreeOperandOpcodeTable[mid][1];
3380
}
3381
3382
} // End SystemZ namespace
3383
} // End llvm namespace
3384
#endif // GET_INSTRMAP_INFO
3385