/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\

|*                                                                            *|

|* Assembly Matcher Source Fragment                                           *|

|*                                                                            *|

|* Automatically generated file, do not edit!                                 *|

|*                                                                            *|

\*===----------------------------------------------------------------------===*/

#ifdef GET_ASSEMBLER_HEADER

#undef GET_ASSEMBLER_HEADER

  // This should be included into the middle of the declaration of

  // your subclasses implementation of MCTargetAsmParser.

  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;

  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,

                       const OperandVector &Operands);

  void convertToMapAndConstraints(unsigned Kind,

                           const OperandVector &Operands) override;

  bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);

  unsigned MatchInstructionImpl(const OperandVector &Operands,

                                MCInst &Inst,

                                uint64_t &ErrorInfo, bool matchingInlineAsm,

                                unsigned VariantID = 0);

  enum OperandMatchResultTy {

    MatchOperand_Success,    // operand matched successfully

    MatchOperand_NoMatch,    // operand did not match

    MatchOperand_ParseFail   // operand matched but had errors

  };

  OperandMatchResultTy MatchOperandParserImpl(

    OperandVector &Operands,

    StringRef Mnemonic);

  OperandMatchResultTy tryCustomParseOperand(

    OperandVector &Operands,

    unsigned MCK);

#endif // GET_ASSEMBLER_HEADER_INFO

#ifdef GET_OPERAND_DIAGNOSTIC_TYPES

#undef GET_OPERAND_DIAGNOSTIC_TYPES

  Match_Immz,

  Match_SImm6,

  Match_UImm10_0,

  Match_UImm16,

  Match_UImm16_Relaxed,

  Match_UImm1_0,

  Match_UImm2_0,

  Match_UImm2_1,

  Match_UImm3_0,

  Match_UImm4_0,

  Match_UImm5_0,

  Match_UImm5_0_Report_UImm6,

  Match_UImm5_1,

  Match_UImm5_32,

  Match_UImm5_33,

  Match_UImm5_Lsl2,

  Match_UImm6_0,

  Match_UImm7_0,

  Match_UImm8_0,

  END_OPERAND_DIAGNOSTIC_TYPES

#endif // GET_OPERAND_DIAGNOSTIC_TYPES

#ifdef GET_REGISTER_MATCHER

#undef GET_REGISTER_MATCHER

// Flags for subtarget features that participate in instruction matching.

enum SubtargetFeatureFlag : uint64_t {

  Feature_HasMips2 = (1ULL << 8),

  Feature_HasMips3_32 = (1ULL << 14),

  Feature_HasMips3_32r2 = (1ULL << 15),

  Feature_HasMips3 = (1ULL << 9),

  Feature_HasMips4_32 = (1ULL << 16),

  Feature_NotMips4_32 = (1ULL << 34),

  Feature_HasMips4_32r2 = (1ULL << 17),

  Feature_HasMips5_32r2 = (1ULL << 18),

  Feature_HasMips32 = (1ULL << 10),

  Feature_HasMips32r2 = (1ULL << 11),

  Feature_HasMips32r5 = (1ULL << 12),

  Feature_HasMips32r6 = (1ULL << 13),

  Feature_NotMips32r6 = (1ULL << 33),

  Feature_IsGP64bit = (1ULL << 27),

  Feature_IsGP32bit = (1ULL << 26),

  Feature_HasMips64 = (1ULL << 19),

  Feature_NotMips64 = (1ULL << 35),

  Feature_HasMips64r2 = (1ULL << 20),

  Feature_HasMips64r6 = (1ULL << 21),

  Feature_NotMips64r6 = (1ULL << 36),

  Feature_HasMicroMips32r6 = (1ULL << 6),

  Feature_HasMicroMips64r6 = (1ULL << 7),

  Feature_InMips16Mode = (1ULL << 24),

  Feature_HasCnMips = (1ULL << 0),

  Feature_HasStdEnc = (1ULL << 22),

  Feature_InMicroMips = (1ULL << 23),

  Feature_NotInMicroMips = (1ULL << 32),

  Feature_HasEVA = (1ULL << 4),

  Feature_HasMSA = (1ULL << 5),

  Feature_IsFP64bit = (1ULL << 25),

  Feature_NotFP64bit = (1ULL << 31),

  Feature_IsSingleFloat = (1ULL << 30),

  Feature_IsNotSingleFloat = (1ULL << 28),

  Feature_IsNotSoftFloat = (1ULL << 29),

  Feature_HasDSP = (1ULL << 1),

  Feature_HasDSPR2 = (1ULL << 2),

  Feature_HasDSPR3 = (1ULL << 3),

  Feature_None = 0

};

#endif // GET_REGISTER_MATCHER

#ifdef GET_SUBTARGET_FEATURE_NAME

#undef GET_SUBTARGET_FEATURE_NAME

// User-level names for subtarget features that participate in

// instruction matching.

static const char *getSubtargetFeatureName(uint64_t Val) {

  switch(Val) {

  case Feature_HasMips2: return "";

  case Feature_HasMips3_32: return "";

  case Feature_HasMips3_32r2: return "";

  case Feature_HasMips3: return "";

  case Feature_HasMips4_32: return "";

  case Feature_NotMips4_32: return "";

  case Feature_HasMips4_32r2: return "";

  case Feature_HasMips5_32r2: return "";

  case Feature_HasMips32: return "";

  case Feature_HasMips32r2: return "";

  case Feature_HasMips32r5: return "";

  case Feature_HasMips32r6: return "";

  case Feature_NotMips32r6: return "";

  case Feature_IsGP64bit: return "";

  case Feature_IsGP32bit: return "";

  case Feature_HasMips64: return "";

  case Feature_NotMips64: return "";

  case Feature_HasMips64r2: return "";

  case Feature_HasMips64r6: return "";

  case Feature_NotMips64r6: return "";

  case Feature_HasMicroMips32r6: return "";

  case Feature_HasMicroMips64r6: return "";

  case Feature_InMips16Mode: return "";

  case Feature_HasCnMips: return "";

  case Feature_HasStdEnc: return "";

  case Feature_InMicroMips: return "";

  case Feature_NotInMicroMips: return "";

  case Feature_HasEVA: return "";

  case Feature_HasMSA: return "";

  case Feature_IsFP64bit: return "";

  case Feature_NotFP64bit: return "";

  case Feature_IsSingleFloat: return "";

  case Feature_IsNotSingleFloat: return "";

  case Feature_IsNotSoftFloat: return "";

  case Feature_HasDSP: return "";

  case Feature_HasDSPR2: return "";

  case Feature_HasDSPR3: return "";

  default: return "(unknown)";

  }

}

#endif // GET_SUBTARGET_FEATURE_NAME

#ifdef GET_MATCHER_IMPLEMENTATION

#undef GET_MATCHER_IMPLEMENTATION

namespace {

enum OperatorConversionKind {

  CVT_Done,

  CVT_Reg,

  CVT_Tied,

  CVT_95_addGPR32AsmRegOperands,

  CVT_95_addAFGR64AsmRegOperands,

  CVT_95_addFGR64AsmRegOperands,

  CVT_95_addFGR32AsmRegOperands,

  CVT_95_addImmOperands,

  CVT_95_addMSA128AsmRegOperands,

  CVT_95_Reg,

  CVT_95_addGPRMM16AsmRegOperands,

  CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_,

  CVT_95_addUImmOperands_LT_16_GT_,

  CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_,

  CVT_regZERO,

  CVT_95_addGPR64AsmRegOperands,

  CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_,

  CVT_regFCC0,

  CVT_95_addFCCAsmRegOperands,

  CVT_95_addCOP2AsmRegOperands,

  CVT_imm_95_0,

  CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_,

  CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_,

  CVT_95_addMemOperands,

  CVT_95_addCCRAsmRegOperands,

  CVT_95_addMSACtrlAsmRegOperands,

  CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_,

  CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_,

  CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_,

  CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_,

  CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_,

  CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_,

  CVT_95_addCOP0AsmRegOperands,

  CVT_regZERO_64,

  CVT_95_addACC64DSPAsmRegOperands,

  CVT_95_addConstantUImmOperands_LT_1_GT_,

  CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_,

  CVT_regRA,

  CVT_95_addMicroMipsMemOperands,

  CVT_95_addCOP3AsmRegOperands,

  CVT_95_addRegListOperands,

  CVT_95_addRegPairOperands,

  CVT_95_addMovePRegPairOperands,

  CVT_95_addGPRMM16AsmRegMovePOperands,

  CVT_95_addHI32DSPAsmRegOperands,

  CVT_95_addLO32DSPAsmRegOperands,

  CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_,

  CVT_95_addHWRegsAsmRegOperands,

  CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_,

  CVT_95_addGPRMM16AsmRegZeroOperands,

  CVT_imm_95_2,

  CVT_imm_95_6,

  CVT_imm_95_4,

  CVT_imm_95_5,

  CVT_imm_95_31,

  CVT_NUM_CONVERTERS

};

enum InstructionConversionKind {

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1,

  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1,

  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1,

  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2,

  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2,

  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1,

  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,

  Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1,

  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2,

  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2,

  Convert__Imm1_1,

  Convert__Reg1_0__Imm1_1,

  Convert__Reg1_0__Imm1_2,

  Convert__Reg1_0__Reg1_1__Imm1_2,

  Convert__Reg1_0__Tie0__Imm1_1,

  Convert__GPR32AsmReg1_0__JumpTarget1_1,

  Convert__GPRMM16AsmReg1_0__Imm1_1,

  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2,

  Convert__GPR32AsmReg1_0__Tie0__Imm1_1,

  Convert__Imm1_0,

  Convert__Reg1_0__Reg1_1__Reg1_2,

  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2,

  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3,

  Convert__GPR32AsmReg1_0__Imm1_1,

  Convert__Reg1_0__Tie0__Reg1_1,

  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0,

  Convert__JumpTarget1_0,

  Convert__regZERO__regZERO__JumpTarget1_0,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2,

  Convert__regZERO__JumpTarget1_0,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0,

  Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2,

  Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2,

  Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2,

  Convert__FGR64AsmReg1_0__JumpTarget1_1,

  Convert__regFCC0__JumpTarget1_0,

  Convert__FCCAsmReg1_0__JumpTarget1_1,

  Convert__COP2AsmReg1_0__JumpTarget1_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2,

  Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2,

  Convert__Reg1_0__JumpTarget1_1,

  Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1,

  Convert__GPRMM16AsmReg1_0__JumpTarget1_1,

  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2,

  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2,

  Convert__MSA128AsmReg1_0__JumpTarget1_1,

  Convert__imm_95_0__imm_95_0,

  Convert_NoOperands,

  Convert__ConstantUImm10_01_0__imm_95_0,

  Convert__ConstantUImm10_01_0__ConstantUImm10_01_1,

  Convert__ConstantUImm4_01_0,

  Convert__MemOffsetSimm92_1__ConstantUImm5_01_0,

  Convert__Mem2_1__ConstantUImm5_01_0,

  Convert__FGR64AsmReg1_0__FGR32AsmReg1_1,

  Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1,

  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1,

  Convert__GPR32AsmReg1_0__CCRAsmReg1_1,

  Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3,

  Convert__Reg1_0__Reg1_1,

  Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2,

  Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__Imm1_3,

  Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__Imm1_3,

  Convert__CCRAsmReg1_1__GPR32AsmReg1_0,

  Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1,

  Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2,

  Convert__GPR64AsmReg1_0__Tie0__Imm1_1,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1,

  Convert__GPR64AsmReg1_1__GPR64AsmReg1_2,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3,

  Convert__regZERO,

  Convert__GPR32AsmReg1_0,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__Imm1_3__Tie0,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__Imm1_3__Tie0,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__Imm1_3__Tie0,

  Convert__Reg1_1__Reg1_2,

  Convert__GPR32AsmReg1_1__GPR32AsmReg1_2,

  Convert__GPR64AsmReg1_0__Imm1_1,

  Convert__GPR64AsmReg1_0__Mem2_1,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3,

  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0,

  Convert__GPR64AsmReg1_0__COP0AsmReg1_1__UImm161_2,

  Convert__GPR64AsmReg1_0__FGR64AsmReg1_1,

  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0,

  Convert__GPR64AsmReg1_0__UImm161_1,

  Convert__GPR64AsmReg1_0__COP2AsmReg1_1__UImm161_2,

  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0,

  Convert__COP0AsmReg1_1__GPR64AsmReg1_0__UImm161_2,

  Convert__FGR64AsmReg1_1__GPR64AsmReg1_0,

  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0,

  Convert__COP2AsmReg1_1__GPR64AsmReg1_0__UImm161_2,

  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0,

  Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1,

  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3,

  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2,

  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2,

  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1,

  Convert__MSA128AsmReg1_0__GPR32AsmReg1_1,

  Convert__MSA128AsmReg1_0__GPR64AsmReg1_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Imm1_3__Tie0,

  Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__Imm1_2,

  Convert__MSA128AsmReg1_0__Tie0__GPR64AsmReg1_4__Imm1_2,

  Convert__GPR32AsmReg1_0__Tie0__GPR32AsmReg1_1,

  Convert__MSA128AsmReg1_0__Tie0__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6,

  Convert__MSA128AsmReg1_0__Tie0__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6,

  Convert__MSA128AsmReg1_0__Tie0__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6,

  Convert__MSA128AsmReg1_0__Tie0__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6,

  Convert__regRA__GPR32AsmReg1_0,

  Convert__Reg1_0,

  Convert__regZERO__GPR32AsmReg1_0,

  Convert__regZERO_64__GPR64AsmReg1_0,

  Convert__UImm5Lsl21_0,

  Convert__GPR32AsmReg1_0__Mem2_1,

  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1,

  Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,

  Convert__MSA128AsmReg1_0__Mem2_1,

  Convert__AFGR64AsmReg1_0__Mem2_1,

  Convert__FGR64AsmReg1_0__Mem2_1,

  Convert__COP2AsmReg1_0__MemOffsetSimm112_1,

  Convert__COP2AsmReg1_0__Mem2_1,

  Convert__COP3AsmReg1_0__Mem2_1,

  Convert__MSA128AsmReg1_0__Imm1_1,

  Convert__GPR64AsmReg1_0__Mem2_1__Tie0,

  Convert__GPR64AsmReg1_0__JumpTarget1_1,

  Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,

  Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,

  Convert__GPR64AsmReg1_0__MemOffsetSimm92_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3,

  Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3,

  Convert__GPR32AsmReg1_0__UImm161_1,

  Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1,

  Convert__Reg1_0__Imm1_1__imm_95_0,

  Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1,

  Convert__GPRMM16AsmReg1_0__Reg1_1__Imm1_2,

  Convert__Reg1_0__Reg1_3__Imm1_1,

  Convert__FGR32AsmReg1_0__Mem2_1,

  Convert__GPR32AsmReg1_0__Mem2_1__Tie0,

  Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0,

  Convert__RegList1_0__Mem2_1,

  Convert__RegList161_0__MemOffsetUimm42_1,

  Convert__RegPair2_0__Mem2_1,

  Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1,

  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3,

  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3,

  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3,

  Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2,

  Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2,

  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0,

  Convert__GPR32AsmReg1_0__COP0AsmReg1_1__UImm161_2,

  Convert__GPR32AsmReg1_0__FGR32AsmReg1_1,

  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0,

  Convert__GPR32AsmReg1_0__COP2AsmReg1_1__UImm161_2,

  Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1,

  Convert__GPR32AsmReg1_0__FGR64AsmReg1_1,

  Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO,

  Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64,

  Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0,

  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0,

  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0,

  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0,

  Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0,

  Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0,

  Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0,

  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0,

  Convert__COP0AsmReg1_1__GPR32AsmReg1_0__UImm161_2,

  Convert__FGR32AsmReg1_1__GPR32AsmReg1_0,

  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0,

  Convert__COP2AsmReg1_1__GPR32AsmReg1_0__UImm161_2,

  Convert__AFGR64AsmReg1_1__Tie0__GPR32AsmReg1_0,

  Convert__FGR64AsmReg1_1__Tie0__GPR32AsmReg1_0,

  Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0,

  Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0,

  Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0,

  Convert__GPR64AsmReg1_0,

  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2,

  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1,

  Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0,

  Convert__regZERO__regZERO__imm_95_0,

  Convert__regZERO__regZERO,

  Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0,

  Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0,

  Convert__GPR32AsmReg1_0__ConstantUImm7_01_1,

  Convert__GPR32AsmReg1_0__ConstantUImm10_01_1,

  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1,

  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0,

  Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2,

  Convert__GPR32AsmReg1_0__ConstantUImm8_01_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2,

  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2,

  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2,

  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2,

  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2,

  Convert__Reg1_0__Reg1_1__Imm1_2__Reg1_3,

  Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1,

  Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1,

  Convert__GPR32AsmReg1_0__Tie0__Mem2_1,

  Convert__GPR64AsmReg1_0__Tie0__MemOffsetSimm92_1,

  Convert__GPR64AsmReg1_0__Tie0__Mem2_1,

  Convert__imm_95_0,

  Convert__Reg1_0__Tie0,

  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2,

  Convert__ACC64DSPAsmReg1_0__ConstantSImm61_1__Tie0,

  Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2,

  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3,

  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_3,

  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm1_01_3,

  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_3,

  Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm2_01_3,

  Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2,

  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3,

  Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_3,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2,

  Convert__GPR32AsmReg1_0__MemOffsetSimm9GPR2_1,

  Convert__MemOffsetSimm162_0,

  Convert__imm_95_2,

  Convert__imm_95_6,

  Convert__imm_95_4,

  Convert__imm_95_5,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0,

  Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2,

  Convert__ConstantUImm10_01_0,

  Convert__GPR32AsmReg1_0__imm_95_31,

  CVT_NUM_SIGNATURES

};

} // end anonymous namespace

static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },

  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1

  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },

  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1

  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },

  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__Imm1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__Imm1_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2

  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done },

  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_2__AFGR64AsmReg1_1

  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },

  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2

  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },

  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },

  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },

  // Convert__Imm1_1

  { CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__Reg1_0__Imm1_1

  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__Reg1_0__Imm1_2

  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__Reg1_0__Reg1_1__Imm1_2

  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__Reg1_0__Tie0__Imm1_1

  { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__JumpTarget1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPRMM16AsmReg1_0__Imm1_1

  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2

  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__Tie0__Imm1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__Imm1_0

  { CVT_95_addImmOperands, 1, CVT_Done },

  // Convert__Reg1_0__Reg1_1__Reg1_2

  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },

  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2

  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_2

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },

  // Convert__GPR32AsmReg1_0__Imm1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__Reg1_0__Tie0__Reg1_1

  { CVT_95_Reg, 1, CVT_Tied, 0, CVT_95_Reg, 2, CVT_Done },

  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0

  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, 0, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, 0, CVT_Done },

  // Convert__JumpTarget1_0

  { CVT_95_addImmOperands, 1, CVT_Done },

  // Convert__regZERO__regZERO__JumpTarget1_0

  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },

  // Convert__regZERO__JumpTarget1_0

  { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, 0, CVT_Done },

  // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__FGR64AsmReg1_0__JumpTarget1_1

  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__regFCC0__JumpTarget1_0

  { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done },

  // Convert__FCCAsmReg1_0__JumpTarget1_1

  { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__COP2AsmReg1_0__JumpTarget1_1

  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__Reg1_0__JumpTarget1_1

  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPRMM16AsmReg1_0__JumpTarget1_1

  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__MSA128AsmReg1_2

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__Imm1_2

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__JumpTarget1_1

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__imm_95_0__imm_95_0

  { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done },

  // Convert_NoOperands

  { CVT_Done },

  // Convert__ConstantUImm10_01_0__imm_95_0

  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done },

  // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1

  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },

  // Convert__ConstantUImm4_01_0

  { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done },

  // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0

  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },

  // Convert__Mem2_1__ConstantUImm5_01_0

  { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },

  // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1

  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },

  // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },

  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__CCRAsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done },

  // Convert__Reg1_0__Reg1_1

  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },

  // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__Imm1_3

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },

  // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__Imm1_3

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },

  // Convert__CCRAsmReg1_1__GPR32AsmReg1_0

  { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },

  // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1

  { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },

  // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1

  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__Tie0__Imm1_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2

  { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },

  // Convert__regZERO

  { CVT_regZERO, 0, CVT_Done },

  // Convert__GPR32AsmReg1_0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__Imm1_3__Tie0

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, 0, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__Imm1_3__Tie0

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, 0, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__Imm1_3__Tie0

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, 0, CVT_Done },

  // Convert__Reg1_1__Reg1_2

  { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },

  // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2

  { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__Imm1_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__Mem2_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },

  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },

  // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__UImm161_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },

  // Convert__GPR64AsmReg1_0__UImm161_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__UImm161_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },

  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0

  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },

  // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__UImm161_2

  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },

  // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0

  { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },

  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0

  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },

  // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__UImm161_2

  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },

  // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },

  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0

  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done },

  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done },

  // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },

  // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Imm1_3__Tie0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, 0, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__GPR32AsmReg1_4__Imm1_2

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__GPR64AsmReg1_4__Imm1_2

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__Tie0__GPR32AsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done },

  // Convert__regRA__GPR32AsmReg1_0

  { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },

  // Convert__Reg1_0

  { CVT_95_Reg, 1, CVT_Done },

  // Convert__regZERO__GPR32AsmReg1_0

  { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },

  // Convert__regZERO_64__GPR64AsmReg1_0

  { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },

  // Convert__UImm5Lsl21_0

  { CVT_95_addImmOperands, 1, CVT_Done },

  // Convert__GPR32AsmReg1_0__Mem2_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1

  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },

  // Convert__MSA128AsmReg1_0__Mem2_1

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__AFGR64AsmReg1_0__Mem2_1

  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__FGR64AsmReg1_0__Mem2_1

  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__COP2AsmReg1_0__MemOffsetSimm112_1

  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__COP2AsmReg1_0__Mem2_1

  { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__COP3AsmReg1_0__Mem2_1

  { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__MSA128AsmReg1_0__Imm1_1

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__Mem2_1__Tie0

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_Done },

  // Convert__GPR64AsmReg1_0__JumpTarget1_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1

  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },

  // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1

  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__MemOffsetSimm92_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },

  // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3

  { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done },

  // Convert__GPR32AsmReg1_0__UImm161_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done },

  // Convert__Reg1_0__Imm1_1__imm_95_0

  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },

  // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__GPRMM16AsmReg1_0__Reg1_1__Imm1_2

  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__Reg1_0__Reg1_3__Imm1_1

  { CVT_95_Reg, 1, CVT_95_Reg, 4, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__FGR32AsmReg1_0__Mem2_1

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__Mem2_1__Tie0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_Done },

  // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, 0, CVT_Done },

  // Convert__RegList1_0__Mem2_1

  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__RegList161_0__MemOffsetUimm42_1

  { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__RegPair2_0__Mem2_1

  { CVT_95_addRegPairOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },

  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3

  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done },

  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3

  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done },

  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done },

  // Convert__FGR64AsmReg1_0__Tie0__FGR64AsmReg1_1__FGR64AsmReg1_2

  { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done },

  // Convert__FGR32AsmReg1_0__Tie0__FGR32AsmReg1_1__FGR32AsmReg1_2

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },

  // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__UImm161_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },

  // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__UImm161_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done },

  // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done },

  // Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2

  { CVT_95_addMovePRegPairOperands, 1, CVT_95_addGPRMM16AsmRegMovePOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },

  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0

  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },

  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0

  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },

  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, 0, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },

  // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0

  { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },

  // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0

  { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },

  // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0

  { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, 0, CVT_Done },

  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0

  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },

  // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__UImm161_2

  { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },

  // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0

  { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },

  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0

  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done },

  // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__UImm161_2

  { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done },

  // Convert__AFGR64AsmReg1_1__Tie0__GPR32AsmReg1_0

  { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },

  // Convert__FGR64AsmReg1_1__Tie0__GPR32AsmReg1_0

  { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },

  // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0

  { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },

  // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0

  { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_Done },

  // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0

  { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },

  // Convert__GPR64AsmReg1_0

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done },

  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2

  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },

  // Convert__regZERO__regZERO__imm_95_0

  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done },

  // Convert__regZERO__regZERO

  { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done },

  // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1

  { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done },

  // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0

  { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done },

  // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },

  // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },

  // Convert__Reg1_0__Reg1_1__Imm1_2__Reg1_3

  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_95_Reg, 4, CVT_Done },

  // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1

  { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__Tie0__MemOffsetSimm92_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__Tie0__Mem2_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__Tie0__MemOffsetSimm92_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__GPR64AsmReg1_0__Tie0__Mem2_1

  { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__imm_95_0

  { CVT_imm_95_0, 0, CVT_Done },

  // Convert__Reg1_0__Tie0

  { CVT_95_Reg, 1, CVT_Tied, 0, CVT_Done },

  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done },

  // Convert__ACC64DSPAsmReg1_0__ConstantSImm61_1__Tie0

  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_Done },

  // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0

  { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, 0, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__GPR32AsmReg1_3

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm4_01_3

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm1_01_3

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm3_01_3

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done },

  // Convert__MSA128AsmReg1_0__Tie0__MSA128AsmReg1_1__ConstantUImm2_01_3

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, 0, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done },

  // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2

  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done },

  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done },

  // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__Imm1_3

  { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done },

  // Convert__GPR32AsmReg1_0__MemOffsetSimm9GPR2_1

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done },

  // Convert__MemOffsetSimm162_0

  { CVT_95_addMemOperands, 1, CVT_Done },

  // Convert__imm_95_2

  { CVT_imm_95_2, 0, CVT_Done },

  // Convert__imm_95_6

  { CVT_imm_95_6, 0, CVT_Done },

  // Convert__imm_95_4

  { CVT_imm_95_4, 0, CVT_Done },

  // Convert__imm_95_5

  { CVT_imm_95_5, 0, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done },

  // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done },

  // Convert__ConstantUImm10_01_0

  { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done },

  // Convert__GPR32AsmReg1_0__imm_95_31

  { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done },

};

void MipsAsmParser::

convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,

                const OperandVector &Operands) {

  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");

  const uint8_t *Converter = ConversionTable[Kind];

  Inst.setOpcode(Opcode);

  for (const uint8_t *p = Converter; *p; p+= 2) {

    switch (*p) {

    default: llvm_unreachable("invalid conversion entry!");

    case CVT_Reg:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);

      break;

    case CVT_Tied:

      Inst.addOperand(Inst.getOperand(*(p + 1)));

      break;

    case CVT_95_addGPR32AsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addGPR32AsmRegOperands(Inst, 1);

      break;

    case CVT_95_addAFGR64AsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addAFGR64AsmRegOperands(Inst, 1);

      break;

    case CVT_95_addFGR64AsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addFGR64AsmRegOperands(Inst, 1);

      break;

    case CVT_95_addFGR32AsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addFGR32AsmRegOperands(Inst, 1);

      break;

    case CVT_95_addImmOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addImmOperands(Inst, 1);

      break;

    case CVT_95_addMSA128AsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addMSA128AsmRegOperands(Inst, 1);

      break;

    case CVT_95_Reg:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);

      break;

    case CVT_95_addGPRMM16AsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addGPRMM16AsmRegOperands(Inst, 1);

      break;

    case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<2, 0>(Inst, 1);

      break;

    case CVT_95_addUImmOperands_LT_16_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addUImmOperands<16>(Inst, 1);

      break;

    case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<5, 0>(Inst, 1);

      break;

    case CVT_regZERO:

      Inst.addOperand(MCOperand::createReg(Mips::ZERO));

      break;

    case CVT_95_addGPR64AsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addGPR64AsmRegOperands(Inst, 1);

      break;

    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<5, 32, -32>(Inst, 1);

      break;

    case CVT_regFCC0:

      Inst.addOperand(MCOperand::createReg(Mips::FCC0));

      break;

    case CVT_95_addFCCAsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addFCCAsmRegOperands(Inst, 1);

      break;

    case CVT_95_addCOP2AsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addCOP2AsmRegOperands(Inst, 1);

      break;

    case CVT_imm_95_0:

      Inst.addOperand(MCOperand::createImm(0));

      break;

    case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<10, 0>(Inst, 1);

      break;

    case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<4, 0>(Inst, 1);

      break;

    case CVT_95_addMemOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addMemOperands(Inst, 2);

      break;

    case CVT_95_addCCRAsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addCCRAsmRegOperands(Inst, 1);

      break;

    case CVT_95_addMSACtrlAsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addMSACtrlAsmRegOperands(Inst, 1);

      break;

    case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<3, 0>(Inst, 1);

      break;

    case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<5, 1>(Inst, 1);

      break;

    case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<5, 33>(Inst, 1);

      break;

    case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<5, 32>(Inst, 1);

      break;

    case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<6, 0>(Inst, 1);

      break;

    case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addConstantUImmOperands<2, 1>(Inst, 1);

      break;

    case CVT_95_addCOP0AsmRegOperands:

      static_cast<MipsOperand&>(*Operands[*(p + 1)]).addCOP0AsmRegOperands(Inst, 1);

      break;