/src/keystone/llvm/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc
Line | Count | Source |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t RISCVMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 2.11k | const MCSubtargetInfo &STI) const { |
12 | 2.11k | static const uint64_t InstBits[] = { |
13 | 2.11k | UINT64_C(0), |
14 | 2.11k | UINT64_C(0), |
15 | 2.11k | UINT64_C(0), |
16 | 2.11k | UINT64_C(0), |
17 | 2.11k | UINT64_C(0), |
18 | 2.11k | UINT64_C(0), |
19 | 2.11k | UINT64_C(0), |
20 | 2.11k | UINT64_C(0), |
21 | 2.11k | UINT64_C(0), |
22 | 2.11k | UINT64_C(0), |
23 | 2.11k | UINT64_C(0), |
24 | 2.11k | UINT64_C(0), |
25 | 2.11k | UINT64_C(0), |
26 | 2.11k | UINT64_C(0), |
27 | 2.11k | UINT64_C(0), |
28 | 2.11k | UINT64_C(0), |
29 | 2.11k | UINT64_C(0), |
30 | 2.11k | UINT64_C(0), |
31 | 2.11k | UINT64_C(0), |
32 | 2.11k | UINT64_C(0), |
33 | 2.11k | UINT64_C(0), |
34 | 2.11k | UINT64_C(0), |
35 | 2.11k | UINT64_C(0), |
36 | 2.11k | UINT64_C(0), |
37 | 2.11k | UINT64_C(0), |
38 | 2.11k | UINT64_C(0), |
39 | 2.11k | UINT64_C(0), |
40 | 2.11k | UINT64_C(0), |
41 | 2.11k | UINT64_C(0), |
42 | 2.11k | UINT64_C(0), |
43 | 2.11k | UINT64_C(0), |
44 | 2.11k | UINT64_C(0), |
45 | 2.11k | UINT64_C(0), |
46 | 2.11k | UINT64_C(0), |
47 | 2.11k | UINT64_C(0), |
48 | 2.11k | UINT64_C(0), |
49 | 2.11k | UINT64_C(0), |
50 | 2.11k | UINT64_C(0), |
51 | 2.11k | UINT64_C(0), |
52 | 2.11k | UINT64_C(0), |
53 | 2.11k | UINT64_C(0), |
54 | 2.11k | UINT64_C(0), |
55 | 2.11k | UINT64_C(0), |
56 | 2.11k | UINT64_C(0), |
57 | 2.11k | UINT64_C(0), |
58 | 2.11k | UINT64_C(0), |
59 | 2.11k | UINT64_C(0), |
60 | 2.11k | UINT64_C(0), |
61 | 2.11k | UINT64_C(0), |
62 | 2.11k | UINT64_C(0), |
63 | 2.11k | UINT64_C(0), |
64 | 2.11k | UINT64_C(0), |
65 | 2.11k | UINT64_C(0), |
66 | 2.11k | UINT64_C(0), |
67 | 2.11k | UINT64_C(0), |
68 | 2.11k | UINT64_C(0), |
69 | 2.11k | UINT64_C(0), |
70 | 2.11k | UINT64_C(0), |
71 | 2.11k | UINT64_C(0), |
72 | 2.11k | UINT64_C(0), |
73 | 2.11k | UINT64_C(0), |
74 | 2.11k | UINT64_C(0), |
75 | 2.11k | UINT64_C(0), |
76 | 2.11k | UINT64_C(0), |
77 | 2.11k | UINT64_C(0), |
78 | 2.11k | UINT64_C(0), |
79 | 2.11k | UINT64_C(0), |
80 | 2.11k | UINT64_C(0), |
81 | 2.11k | UINT64_C(0), |
82 | 2.11k | UINT64_C(0), |
83 | 2.11k | UINT64_C(0), |
84 | 2.11k | UINT64_C(0), |
85 | 2.11k | UINT64_C(0), |
86 | 2.11k | UINT64_C(0), |
87 | 2.11k | UINT64_C(0), |
88 | 2.11k | UINT64_C(0), |
89 | 2.11k | UINT64_C(0), |
90 | 2.11k | UINT64_C(0), |
91 | 2.11k | UINT64_C(0), |
92 | 2.11k | UINT64_C(0), |
93 | 2.11k | UINT64_C(0), |
94 | 2.11k | UINT64_C(0), |
95 | 2.11k | UINT64_C(0), |
96 | 2.11k | UINT64_C(0), |
97 | 2.11k | UINT64_C(0), |
98 | 2.11k | UINT64_C(0), |
99 | 2.11k | UINT64_C(0), |
100 | 2.11k | UINT64_C(0), |
101 | 2.11k | UINT64_C(0), |
102 | 2.11k | UINT64_C(0), |
103 | 2.11k | UINT64_C(0), |
104 | 2.11k | UINT64_C(0), |
105 | 2.11k | UINT64_C(0), |
106 | 2.11k | UINT64_C(0), |
107 | 2.11k | UINT64_C(0), |
108 | 2.11k | UINT64_C(0), |
109 | 2.11k | UINT64_C(0), |
110 | 2.11k | UINT64_C(0), |
111 | 2.11k | UINT64_C(0), |
112 | 2.11k | UINT64_C(0), |
113 | 2.11k | UINT64_C(0), |
114 | 2.11k | UINT64_C(0), |
115 | 2.11k | UINT64_C(0), |
116 | 2.11k | UINT64_C(0), |
117 | 2.11k | UINT64_C(0), |
118 | 2.11k | UINT64_C(0), |
119 | 2.11k | UINT64_C(0), |
120 | 2.11k | UINT64_C(0), |
121 | 2.11k | UINT64_C(0), |
122 | 2.11k | UINT64_C(0), |
123 | 2.11k | UINT64_C(0), |
124 | 2.11k | UINT64_C(0), |
125 | 2.11k | UINT64_C(0), |
126 | 2.11k | UINT64_C(0), |
127 | 2.11k | UINT64_C(0), |
128 | 2.11k | UINT64_C(0), |
129 | 2.11k | UINT64_C(0), |
130 | 2.11k | UINT64_C(0), |
131 | 2.11k | UINT64_C(0), |
132 | 2.11k | UINT64_C(0), |
133 | 2.11k | UINT64_C(0), |
134 | 2.11k | UINT64_C(0), |
135 | 2.11k | UINT64_C(0), |
136 | 2.11k | UINT64_C(0), |
137 | 2.11k | UINT64_C(0), |
138 | 2.11k | UINT64_C(0), |
139 | 2.11k | UINT64_C(0), |
140 | 2.11k | UINT64_C(0), |
141 | 2.11k | UINT64_C(0), |
142 | 2.11k | UINT64_C(0), |
143 | 2.11k | UINT64_C(0), |
144 | 2.11k | UINT64_C(0), |
145 | 2.11k | UINT64_C(0), |
146 | 2.11k | UINT64_C(0), |
147 | 2.11k | UINT64_C(0), |
148 | 2.11k | UINT64_C(0), |
149 | 2.11k | UINT64_C(0), |
150 | 2.11k | UINT64_C(0), |
151 | 2.11k | UINT64_C(0), |
152 | 2.11k | UINT64_C(0), |
153 | 2.11k | UINT64_C(0), |
154 | 2.11k | UINT64_C(0), |
155 | 2.11k | UINT64_C(0), |
156 | 2.11k | UINT64_C(0), |
157 | 2.11k | UINT64_C(0), |
158 | 2.11k | UINT64_C(0), |
159 | 2.11k | UINT64_C(0), |
160 | 2.11k | UINT64_C(0), |
161 | 2.11k | UINT64_C(0), |
162 | 2.11k | UINT64_C(0), |
163 | 2.11k | UINT64_C(0), |
164 | 2.11k | UINT64_C(0), |
165 | 2.11k | UINT64_C(0), |
166 | 2.11k | UINT64_C(0), |
167 | 2.11k | UINT64_C(0), |
168 | 2.11k | UINT64_C(0), |
169 | 2.11k | UINT64_C(0), |
170 | 2.11k | UINT64_C(0), |
171 | 2.11k | UINT64_C(0), |
172 | 2.11k | UINT64_C(0), |
173 | 2.11k | UINT64_C(0), |
174 | 2.11k | UINT64_C(0), |
175 | 2.11k | UINT64_C(0), |
176 | 2.11k | UINT64_C(0), |
177 | 2.11k | UINT64_C(0), |
178 | 2.11k | UINT64_C(0), |
179 | 2.11k | UINT64_C(0), |
180 | 2.11k | UINT64_C(0), |
181 | 2.11k | UINT64_C(0), |
182 | 2.11k | UINT64_C(0), |
183 | 2.11k | UINT64_C(0), |
184 | 2.11k | UINT64_C(0), |
185 | 2.11k | UINT64_C(0), |
186 | 2.11k | UINT64_C(0), |
187 | 2.11k | UINT64_C(0), |
188 | 2.11k | UINT64_C(0), |
189 | 2.11k | UINT64_C(0), |
190 | 2.11k | UINT64_C(0), |
191 | 2.11k | UINT64_C(0), |
192 | 2.11k | UINT64_C(0), |
193 | 2.11k | UINT64_C(0), |
194 | 2.11k | UINT64_C(0), |
195 | 2.11k | UINT64_C(0), |
196 | 2.11k | UINT64_C(0), |
197 | 2.11k | UINT64_C(0), |
198 | 2.11k | UINT64_C(0), |
199 | 2.11k | UINT64_C(0), |
200 | 2.11k | UINT64_C(0), |
201 | 2.11k | UINT64_C(0), |
202 | 2.11k | UINT64_C(0), |
203 | 2.11k | UINT64_C(0), |
204 | 2.11k | UINT64_C(0), |
205 | 2.11k | UINT64_C(0), |
206 | 2.11k | UINT64_C(0), |
207 | 2.11k | UINT64_C(0), |
208 | 2.11k | UINT64_C(0), |
209 | 2.11k | UINT64_C(0), |
210 | 2.11k | UINT64_C(0), |
211 | 2.11k | UINT64_C(0), |
212 | 2.11k | UINT64_C(0), |
213 | 2.11k | UINT64_C(0), |
214 | 2.11k | UINT64_C(0), |
215 | 2.11k | UINT64_C(0), |
216 | 2.11k | UINT64_C(0), |
217 | 2.11k | UINT64_C(0), |
218 | 2.11k | UINT64_C(0), |
219 | 2.11k | UINT64_C(0), |
220 | 2.11k | UINT64_C(0), |
221 | 2.11k | UINT64_C(0), |
222 | 2.11k | UINT64_C(0), |
223 | 2.11k | UINT64_C(0), |
224 | 2.11k | UINT64_C(0), |
225 | 2.11k | UINT64_C(0), |
226 | 2.11k | UINT64_C(0), |
227 | 2.11k | UINT64_C(51), // ADD |
228 | 2.11k | UINT64_C(19), // ADDI |
229 | 2.11k | UINT64_C(27), // ADDIW |
230 | 2.11k | UINT64_C(59), // ADDW |
231 | 2.11k | UINT64_C(12335), // AMOADD_D |
232 | 2.11k | UINT64_C(67121199), // AMOADD_D_AQ |
233 | 2.11k | UINT64_C(100675631), // AMOADD_D_AQ_RL |
234 | 2.11k | UINT64_C(33566767), // AMOADD_D_RL |
235 | 2.11k | UINT64_C(8239), // AMOADD_W |
236 | 2.11k | UINT64_C(67117103), // AMOADD_W_AQ |
237 | 2.11k | UINT64_C(100671535), // AMOADD_W_AQ_RL |
238 | 2.11k | UINT64_C(33562671), // AMOADD_W_RL |
239 | 2.11k | UINT64_C(1610625071), // AMOAND_D |
240 | 2.11k | UINT64_C(1677733935), // AMOAND_D_AQ |
241 | 2.11k | UINT64_C(1711288367), // AMOAND_D_AQ_RL |
242 | 2.11k | UINT64_C(1644179503), // AMOAND_D_RL |
243 | 2.11k | UINT64_C(1610620975), // AMOAND_W |
244 | 2.11k | UINT64_C(1677729839), // AMOAND_W_AQ |
245 | 2.11k | UINT64_C(1711284271), // AMOAND_W_AQ_RL |
246 | 2.11k | UINT64_C(1644175407), // AMOAND_W_RL |
247 | 2.11k | UINT64_C(3758108719), // AMOMAXU_D |
248 | 2.11k | UINT64_C(3825217583), // AMOMAXU_D_AQ |
249 | 2.11k | UINT64_C(3858772015), // AMOMAXU_D_AQ_RL |
250 | 2.11k | UINT64_C(3791663151), // AMOMAXU_D_RL |
251 | 2.11k | UINT64_C(3758104623), // AMOMAXU_W |
252 | 2.11k | UINT64_C(3825213487), // AMOMAXU_W_AQ |
253 | 2.11k | UINT64_C(3858767919), // AMOMAXU_W_AQ_RL |
254 | 2.11k | UINT64_C(3791659055), // AMOMAXU_W_RL |
255 | 2.11k | UINT64_C(2684366895), // AMOMAX_D |
256 | 2.11k | UINT64_C(2751475759), // AMOMAX_D_AQ |
257 | 2.11k | UINT64_C(2785030191), // AMOMAX_D_AQ_RL |
258 | 2.11k | UINT64_C(2717921327), // AMOMAX_D_RL |
259 | 2.11k | UINT64_C(2684362799), // AMOMAX_W |
260 | 2.11k | UINT64_C(2751471663), // AMOMAX_W_AQ |
261 | 2.11k | UINT64_C(2785026095), // AMOMAX_W_AQ_RL |
262 | 2.11k | UINT64_C(2717917231), // AMOMAX_W_RL |
263 | 2.11k | UINT64_C(3221237807), // AMOMINU_D |
264 | 2.11k | UINT64_C(3288346671), // AMOMINU_D_AQ |
265 | 2.11k | UINT64_C(3321901103), // AMOMINU_D_AQ_RL |
266 | 2.11k | UINT64_C(3254792239), // AMOMINU_D_RL |
267 | 2.11k | UINT64_C(3221233711), // AMOMINU_W |
268 | 2.11k | UINT64_C(3288342575), // AMOMINU_W_AQ |
269 | 2.11k | UINT64_C(3321897007), // AMOMINU_W_AQ_RL |
270 | 2.11k | UINT64_C(3254788143), // AMOMINU_W_RL |
271 | 2.11k | UINT64_C(2147495983), // AMOMIN_D |
272 | 2.11k | UINT64_C(2214604847), // AMOMIN_D_AQ |
273 | 2.11k | UINT64_C(2248159279), // AMOMIN_D_AQ_RL |
274 | 2.11k | UINT64_C(2181050415), // AMOMIN_D_RL |
275 | 2.11k | UINT64_C(2147491887), // AMOMIN_W |
276 | 2.11k | UINT64_C(2214600751), // AMOMIN_W_AQ |
277 | 2.11k | UINT64_C(2248155183), // AMOMIN_W_AQ_RL |
278 | 2.11k | UINT64_C(2181046319), // AMOMIN_W_RL |
279 | 2.11k | UINT64_C(1073754159), // AMOOR_D |
280 | 2.11k | UINT64_C(1140863023), // AMOOR_D_AQ |
281 | 2.11k | UINT64_C(1174417455), // AMOOR_D_AQ_RL |
282 | 2.11k | UINT64_C(1107308591), // AMOOR_D_RL |
283 | 2.11k | UINT64_C(1073750063), // AMOOR_W |
284 | 2.11k | UINT64_C(1140858927), // AMOOR_W_AQ |
285 | 2.11k | UINT64_C(1174413359), // AMOOR_W_AQ_RL |
286 | 2.11k | UINT64_C(1107304495), // AMOOR_W_RL |
287 | 2.11k | UINT64_C(134230063), // AMOSWAP_D |
288 | 2.11k | UINT64_C(201338927), // AMOSWAP_D_AQ |
289 | 2.11k | UINT64_C(234893359), // AMOSWAP_D_AQ_RL |
290 | 2.11k | UINT64_C(167784495), // AMOSWAP_D_RL |
291 | 2.11k | UINT64_C(134225967), // AMOSWAP_W |
292 | 2.11k | UINT64_C(201334831), // AMOSWAP_W_AQ |
293 | 2.11k | UINT64_C(234889263), // AMOSWAP_W_AQ_RL |
294 | 2.11k | UINT64_C(167780399), // AMOSWAP_W_RL |
295 | 2.11k | UINT64_C(536883247), // AMOXOR_D |
296 | 2.11k | UINT64_C(603992111), // AMOXOR_D_AQ |
297 | 2.11k | UINT64_C(637546543), // AMOXOR_D_AQ_RL |
298 | 2.11k | UINT64_C(570437679), // AMOXOR_D_RL |
299 | 2.11k | UINT64_C(536879151), // AMOXOR_W |
300 | 2.11k | UINT64_C(603988015), // AMOXOR_W_AQ |
301 | 2.11k | UINT64_C(637542447), // AMOXOR_W_AQ_RL |
302 | 2.11k | UINT64_C(570433583), // AMOXOR_W_RL |
303 | 2.11k | UINT64_C(28723), // AND |
304 | 2.11k | UINT64_C(28691), // ANDI |
305 | 2.11k | UINT64_C(23), // AUIPC |
306 | 2.11k | UINT64_C(99), // BEQ |
307 | 2.11k | UINT64_C(20579), // BGE |
308 | 2.11k | UINT64_C(28771), // BGEU |
309 | 2.11k | UINT64_C(16483), // BLT |
310 | 2.11k | UINT64_C(24675), // BLTU |
311 | 2.11k | UINT64_C(4195), // BNE |
312 | 2.11k | UINT64_C(12403), // CSRRC |
313 | 2.11k | UINT64_C(28787), // CSRRCI |
314 | 2.11k | UINT64_C(8307), // CSRRS |
315 | 2.11k | UINT64_C(24691), // CSRRSI |
316 | 2.11k | UINT64_C(4211), // CSRRW |
317 | 2.11k | UINT64_C(20595), // CSRRWI |
318 | 2.11k | UINT64_C(36866), // C_ADD |
319 | 2.11k | UINT64_C(1), // C_ADDI |
320 | 2.11k | UINT64_C(24833), // C_ADDI16SP |
321 | 2.11k | UINT64_C(0), // C_ADDI4SPN |
322 | 2.11k | UINT64_C(8193), // C_ADDIW |
323 | 2.11k | UINT64_C(39969), // C_ADDW |
324 | 2.11k | UINT64_C(35937), // C_AND |
325 | 2.11k | UINT64_C(34817), // C_ANDI |
326 | 2.11k | UINT64_C(49153), // C_BEQZ |
327 | 2.11k | UINT64_C(57345), // C_BNEZ |
328 | 2.11k | UINT64_C(36866), // C_EBREAK |
329 | 2.11k | UINT64_C(8192), // C_FLD |
330 | 2.11k | UINT64_C(8194), // C_FLDSP |
331 | 2.11k | UINT64_C(24576), // C_FLW |
332 | 2.11k | UINT64_C(24578), // C_FLWSP |
333 | 2.11k | UINT64_C(40960), // C_FSD |
334 | 2.11k | UINT64_C(40962), // C_FSDSP |
335 | 2.11k | UINT64_C(57344), // C_FSW |
336 | 2.11k | UINT64_C(57346), // C_FSWSP |
337 | 2.11k | UINT64_C(40961), // C_J |
338 | 2.11k | UINT64_C(8193), // C_JAL |
339 | 2.11k | UINT64_C(36866), // C_JALR |
340 | 2.11k | UINT64_C(32770), // C_JR |
341 | 2.11k | UINT64_C(24576), // C_LD |
342 | 2.11k | UINT64_C(24578), // C_LDSP |
343 | 2.11k | UINT64_C(16385), // C_LI |
344 | 2.11k | UINT64_C(24577), // C_LUI |
345 | 2.11k | UINT64_C(16384), // C_LW |
346 | 2.11k | UINT64_C(16386), // C_LWSP |
347 | 2.11k | UINT64_C(32770), // C_MV |
348 | 2.11k | UINT64_C(1), // C_NOP |
349 | 2.11k | UINT64_C(35905), // C_OR |
350 | 2.11k | UINT64_C(57344), // C_SD |
351 | 2.11k | UINT64_C(57346), // C_SDSP |
352 | 2.11k | UINT64_C(2), // C_SLLI |
353 | 2.11k | UINT64_C(33793), // C_SRAI |
354 | 2.11k | UINT64_C(32769), // C_SRLI |
355 | 2.11k | UINT64_C(35841), // C_SUB |
356 | 2.11k | UINT64_C(39937), // C_SUBW |
357 | 2.11k | UINT64_C(49152), // C_SW |
358 | 2.11k | UINT64_C(49154), // C_SWSP |
359 | 2.11k | UINT64_C(0), // C_UNIMP |
360 | 2.11k | UINT64_C(35873), // C_XOR |
361 | 2.11k | UINT64_C(33570867), // DIV |
362 | 2.11k | UINT64_C(33574963), // DIVU |
363 | 2.11k | UINT64_C(33574971), // DIVUW |
364 | 2.11k | UINT64_C(33570875), // DIVW |
365 | 2.11k | UINT64_C(1048691), // EBREAK |
366 | 2.11k | UINT64_C(115), // ECALL |
367 | 2.11k | UINT64_C(33554515), // FADD_D |
368 | 2.11k | UINT64_C(83), // FADD_S |
369 | 2.11k | UINT64_C(3791654995), // FCLASS_D |
370 | 2.11k | UINT64_C(3758100563), // FCLASS_S |
371 | 2.11k | UINT64_C(3525312595), // FCVT_D_L |
372 | 2.11k | UINT64_C(3526361171), // FCVT_D_LU |
373 | 2.11k | UINT64_C(1107296339), // FCVT_D_S |
374 | 2.11k | UINT64_C(3523215443), // FCVT_D_W |
375 | 2.11k | UINT64_C(3524264019), // FCVT_D_WU |
376 | 2.11k | UINT64_C(3257925715), // FCVT_LU_D |
377 | 2.11k | UINT64_C(3224371283), // FCVT_LU_S |
378 | 2.11k | UINT64_C(3256877139), // FCVT_L_D |
379 | 2.11k | UINT64_C(3223322707), // FCVT_L_S |
380 | 2.11k | UINT64_C(1074790483), // FCVT_S_D |
381 | 2.11k | UINT64_C(3491758163), // FCVT_S_L |
382 | 2.11k | UINT64_C(3492806739), // FCVT_S_LU |
383 | 2.11k | UINT64_C(3489661011), // FCVT_S_W |
384 | 2.11k | UINT64_C(3490709587), // FCVT_S_WU |
385 | 2.11k | UINT64_C(3255828563), // FCVT_WU_D |
386 | 2.11k | UINT64_C(3222274131), // FCVT_WU_S |
387 | 2.11k | UINT64_C(3254779987), // FCVT_W_D |
388 | 2.11k | UINT64_C(3221225555), // FCVT_W_S |
389 | 2.11k | UINT64_C(436207699), // FDIV_D |
390 | 2.11k | UINT64_C(402653267), // FDIV_S |
391 | 2.11k | UINT64_C(15), // FENCE |
392 | 2.11k | UINT64_C(4111), // FENCE_I |
393 | 2.11k | UINT64_C(2200961039), // FENCE_TSO |
394 | 2.11k | UINT64_C(2717917267), // FEQ_D |
395 | 2.11k | UINT64_C(2684362835), // FEQ_S |
396 | 2.11k | UINT64_C(12295), // FLD |
397 | 2.11k | UINT64_C(2717909075), // FLE_D |
398 | 2.11k | UINT64_C(2684354643), // FLE_S |
399 | 2.11k | UINT64_C(2717913171), // FLT_D |
400 | 2.11k | UINT64_C(2684358739), // FLT_S |
401 | 2.11k | UINT64_C(8199), // FLW |
402 | 2.11k | UINT64_C(33554499), // FMADD_D |
403 | 2.11k | UINT64_C(67), // FMADD_S |
404 | 2.11k | UINT64_C(704647251), // FMAX_D |
405 | 2.11k | UINT64_C(671092819), // FMAX_S |
406 | 2.11k | UINT64_C(704643155), // FMIN_D |
407 | 2.11k | UINT64_C(671088723), // FMIN_S |
408 | 2.11k | UINT64_C(33554503), // FMSUB_D |
409 | 2.11k | UINT64_C(71), // FMSUB_S |
410 | 2.11k | UINT64_C(301989971), // FMUL_D |
411 | 2.11k | UINT64_C(268435539), // FMUL_S |
412 | 2.11k | UINT64_C(4060086355), // FMV_D_X |
413 | 2.11k | UINT64_C(4026531923), // FMV_W_X |
414 | 2.11k | UINT64_C(3791650899), // FMV_X_D |
415 | 2.11k | UINT64_C(3758096467), // FMV_X_W |
416 | 2.11k | UINT64_C(33554511), // FNMADD_D |
417 | 2.11k | UINT64_C(79), // FNMADD_S |
418 | 2.11k | UINT64_C(33554507), // FNMSUB_D |
419 | 2.11k | UINT64_C(75), // FNMSUB_S |
420 | 2.11k | UINT64_C(12327), // FSD |
421 | 2.11k | UINT64_C(570429523), // FSGNJN_D |
422 | 2.11k | UINT64_C(536875091), // FSGNJN_S |
423 | 2.11k | UINT64_C(570433619), // FSGNJX_D |
424 | 2.11k | UINT64_C(536879187), // FSGNJX_S |
425 | 2.11k | UINT64_C(570425427), // FSGNJ_D |
426 | 2.11k | UINT64_C(536870995), // FSGNJ_S |
427 | 2.11k | UINT64_C(1509949523), // FSQRT_D |
428 | 2.11k | UINT64_C(1476395091), // FSQRT_S |
429 | 2.11k | UINT64_C(167772243), // FSUB_D |
430 | 2.11k | UINT64_C(134217811), // FSUB_S |
431 | 2.11k | UINT64_C(8231), // FSW |
432 | 2.11k | UINT64_C(111), // JAL |
433 | 2.11k | UINT64_C(103), // JALR |
434 | 2.11k | UINT64_C(3), // LB |
435 | 2.11k | UINT64_C(16387), // LBU |
436 | 2.11k | UINT64_C(12291), // LD |
437 | 2.11k | UINT64_C(4099), // LH |
438 | 2.11k | UINT64_C(20483), // LHU |
439 | 2.11k | UINT64_C(268447791), // LR_D |
440 | 2.11k | UINT64_C(335556655), // LR_D_AQ |
441 | 2.11k | UINT64_C(369111087), // LR_D_AQ_RL |
442 | 2.11k | UINT64_C(302002223), // LR_D_RL |
443 | 2.11k | UINT64_C(268443695), // LR_W |
444 | 2.11k | UINT64_C(335552559), // LR_W_AQ |
445 | 2.11k | UINT64_C(369106991), // LR_W_AQ_RL |
446 | 2.11k | UINT64_C(301998127), // LR_W_RL |
447 | 2.11k | UINT64_C(55), // LUI |
448 | 2.11k | UINT64_C(8195), // LW |
449 | 2.11k | UINT64_C(24579), // LWU |
450 | 2.11k | UINT64_C(807403635), // MRET |
451 | 2.11k | UINT64_C(33554483), // MUL |
452 | 2.11k | UINT64_C(33558579), // MULH |
453 | 2.11k | UINT64_C(33562675), // MULHSU |
454 | 2.11k | UINT64_C(33566771), // MULHU |
455 | 2.11k | UINT64_C(33554491), // MULW |
456 | 2.11k | UINT64_C(24627), // OR |
457 | 2.11k | UINT64_C(24595), // ORI |
458 | 2.11k | UINT64_C(33579059), // REM |
459 | 2.11k | UINT64_C(33583155), // REMU |
460 | 2.11k | UINT64_C(33583163), // REMUW |
461 | 2.11k | UINT64_C(33579067), // REMW |
462 | 2.11k | UINT64_C(35), // SB |
463 | 2.11k | UINT64_C(402665519), // SC_D |
464 | 2.11k | UINT64_C(469774383), // SC_D_AQ |
465 | 2.11k | UINT64_C(503328815), // SC_D_AQ_RL |
466 | 2.11k | UINT64_C(436219951), // SC_D_RL |
467 | 2.11k | UINT64_C(402661423), // SC_W |
468 | 2.11k | UINT64_C(469770287), // SC_W_AQ |
469 | 2.11k | UINT64_C(503324719), // SC_W_AQ_RL |
470 | 2.11k | UINT64_C(436215855), // SC_W_RL |
471 | 2.11k | UINT64_C(12323), // SD |
472 | 2.11k | UINT64_C(301990003), // SFENCE_VMA |
473 | 2.11k | UINT64_C(4131), // SH |
474 | 2.11k | UINT64_C(4147), // SLL |
475 | 2.11k | UINT64_C(4115), // SLLI |
476 | 2.11k | UINT64_C(4123), // SLLIW |
477 | 2.11k | UINT64_C(4155), // SLLW |
478 | 2.11k | UINT64_C(8243), // SLT |
479 | 2.11k | UINT64_C(8211), // SLTI |
480 | 2.11k | UINT64_C(12307), // SLTIU |
481 | 2.11k | UINT64_C(12339), // SLTU |
482 | 2.11k | UINT64_C(1073762355), // SRA |
483 | 2.11k | UINT64_C(1073762323), // SRAI |
484 | 2.11k | UINT64_C(1073762331), // SRAIW |
485 | 2.11k | UINT64_C(1073762363), // SRAW |
486 | 2.11k | UINT64_C(270532723), // SRET |
487 | 2.11k | UINT64_C(20531), // SRL |
488 | 2.11k | UINT64_C(20499), // SRLI |
489 | 2.11k | UINT64_C(20507), // SRLIW |
490 | 2.11k | UINT64_C(20539), // SRLW |
491 | 2.11k | UINT64_C(1073741875), // SUB |
492 | 2.11k | UINT64_C(1073741883), // SUBW |
493 | 2.11k | UINT64_C(8227), // SW |
494 | 2.11k | UINT64_C(3221229683), // UNIMP |
495 | 2.11k | UINT64_C(2097267), // URET |
496 | 2.11k | UINT64_C(273678451), // WFI |
497 | 2.11k | UINT64_C(16435), // XOR |
498 | 2.11k | UINT64_C(16403), // XORI |
499 | 2.11k | UINT64_C(0) |
500 | 2.11k | }; |
501 | 2.11k | const unsigned opcode = MI.getOpcode(); |
502 | 2.11k | uint64_t Value = InstBits[opcode]; |
503 | 2.11k | uint64_t op = 0; |
504 | 2.11k | (void)op; // suppress warning |
505 | 2.11k | switch (opcode) { |
506 | 4 | case RISCV::C_EBREAK: |
507 | 289 | case RISCV::C_NOP: |
508 | 290 | case RISCV::C_UNIMP: |
509 | 290 | case RISCV::EBREAK: |
510 | 309 | case RISCV::ECALL: |
511 | 309 | case RISCV::FENCE_I: |
512 | 309 | case RISCV::FENCE_TSO: |
513 | 332 | case RISCV::MRET: |
514 | 341 | case RISCV::SRET: |
515 | 341 | case RISCV::UNIMP: |
516 | 347 | case RISCV::URET: |
517 | 583 | case RISCV::WFI: { |
518 | 583 | break; |
519 | 347 | } |
520 | 0 | case RISCV::C_LI: |
521 | 0 | case RISCV::C_LUI: { |
522 | | // op: imm |
523 | 0 | op = getImmOpValue(MI, 1, Fixups, STI); |
524 | 0 | Value |= (op & UINT64_C(32)) << 7; |
525 | 0 | Value |= (op & UINT64_C(31)) << 2; |
526 | | // op: rd |
527 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
528 | 0 | Value |= (op & UINT64_C(31)) << 7; |
529 | 0 | break; |
530 | 0 | } |
531 | 0 | case RISCV::C_FLDSP: |
532 | 0 | case RISCV::C_LDSP: { |
533 | | // op: imm |
534 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
535 | 0 | Value |= (op & UINT64_C(32)) << 7; |
536 | 0 | Value |= (op & UINT64_C(24)) << 2; |
537 | 0 | Value |= (op & UINT64_C(448)) >> 4; |
538 | | // op: rd |
539 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
540 | 0 | Value |= (op & UINT64_C(31)) << 7; |
541 | 0 | break; |
542 | 0 | } |
543 | 0 | case RISCV::C_FLWSP: |
544 | 0 | case RISCV::C_LWSP: { |
545 | | // op: imm |
546 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
547 | 0 | Value |= (op & UINT64_C(32)) << 7; |
548 | 0 | Value |= (op & UINT64_C(28)) << 2; |
549 | 0 | Value |= (op & UINT64_C(192)) >> 4; |
550 | | // op: rd |
551 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
552 | 0 | Value |= (op & UINT64_C(31)) << 7; |
553 | 0 | break; |
554 | 0 | } |
555 | 48 | case RISCV::C_ADDI: |
556 | 50 | case RISCV::C_ADDIW: { |
557 | | // op: imm |
558 | 50 | op = getImmOpValue(MI, 2, Fixups, STI); |
559 | 50 | Value |= (op & UINT64_C(32)) << 7; |
560 | 50 | Value |= (op & UINT64_C(31)) << 2; |
561 | | // op: rd |
562 | 50 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
563 | 50 | Value |= (op & UINT64_C(31)) << 7; |
564 | 50 | break; |
565 | 48 | } |
566 | 0 | case RISCV::C_ANDI: { |
567 | | // op: imm |
568 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
569 | 0 | Value |= (op & UINT64_C(32)) << 7; |
570 | 0 | Value |= (op & UINT64_C(31)) << 2; |
571 | | // op: rs1 |
572 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
573 | 0 | Value |= (op & UINT64_C(7)) << 7; |
574 | 0 | break; |
575 | 48 | } |
576 | 5 | case RISCV::C_ADDI4SPN: { |
577 | | // op: imm |
578 | 5 | op = getImmOpValue(MI, 2, Fixups, STI); |
579 | 5 | Value |= (op & UINT64_C(48)) << 7; |
580 | 5 | Value |= (op & UINT64_C(960)) << 1; |
581 | 5 | Value |= (op & UINT64_C(4)) << 4; |
582 | 5 | Value |= (op & UINT64_C(8)) << 2; |
583 | | // op: rd |
584 | 5 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
585 | 5 | Value |= (op & UINT64_C(7)) << 2; |
586 | 5 | break; |
587 | 48 | } |
588 | 7 | case RISCV::C_ADDI16SP: { |
589 | | // op: imm |
590 | 7 | op = getImmOpValue(MI, 2, Fixups, STI); |
591 | 7 | Value |= (op & UINT64_C(512)) << 3; |
592 | 7 | Value |= (op & UINT64_C(16)) << 2; |
593 | 7 | Value |= (op & UINT64_C(64)) >> 1; |
594 | 7 | Value |= (op & UINT64_C(384)) >> 4; |
595 | 7 | Value |= (op & UINT64_C(32)) >> 3; |
596 | 7 | break; |
597 | 48 | } |
598 | 0 | case RISCV::C_FSDSP: |
599 | 0 | case RISCV::C_SDSP: { |
600 | | // op: imm |
601 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
602 | 0 | Value |= (op & UINT64_C(56)) << 7; |
603 | 0 | Value |= (op & UINT64_C(448)) << 1; |
604 | | // op: rs2 |
605 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
606 | 0 | Value |= (op & UINT64_C(31)) << 2; |
607 | 0 | break; |
608 | 0 | } |
609 | 0 | case RISCV::C_FSWSP: |
610 | 0 | case RISCV::C_SWSP: { |
611 | | // op: imm |
612 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
613 | 0 | Value |= (op & UINT64_C(60)) << 7; |
614 | 0 | Value |= (op & UINT64_C(192)) << 1; |
615 | | // op: rs2 |
616 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
617 | 0 | Value |= (op & UINT64_C(31)) << 2; |
618 | 0 | break; |
619 | 0 | } |
620 | 0 | case RISCV::C_BEQZ: |
621 | 0 | case RISCV::C_BNEZ: { |
622 | | // op: imm |
623 | 0 | op = getImmOpValueAsr1(MI, 1, Fixups, STI); |
624 | 0 | Value |= (op & UINT64_C(128)) << 5; |
625 | 0 | Value |= (op & UINT64_C(12)) << 8; |
626 | 0 | Value |= op & UINT64_C(96); |
627 | 0 | Value |= (op & UINT64_C(3)) << 3; |
628 | 0 | Value |= (op & UINT64_C(16)) >> 2; |
629 | | // op: rs1 |
630 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
631 | 0 | Value |= (op & UINT64_C(7)) << 7; |
632 | 0 | break; |
633 | 0 | } |
634 | 0 | case RISCV::C_SLLI: { |
635 | | // op: imm |
636 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
637 | 0 | Value |= (op & UINT64_C(32)) << 7; |
638 | 0 | Value |= (op & UINT64_C(31)) << 2; |
639 | | // op: rd |
640 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
641 | 0 | Value |= (op & UINT64_C(31)) << 7; |
642 | 0 | break; |
643 | 0 | } |
644 | 0 | case RISCV::C_SRAI: |
645 | 0 | case RISCV::C_SRLI: { |
646 | | // op: imm |
647 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
648 | 0 | Value |= (op & UINT64_C(32)) << 7; |
649 | 0 | Value |= (op & UINT64_C(31)) << 2; |
650 | | // op: rs1 |
651 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
652 | 0 | Value |= (op & UINT64_C(7)) << 7; |
653 | 0 | break; |
654 | 0 | } |
655 | 0 | case RISCV::FSD: |
656 | 0 | case RISCV::FSW: |
657 | 1 | case RISCV::SB: |
658 | 11 | case RISCV::SD: |
659 | 12 | case RISCV::SH: |
660 | 14 | case RISCV::SW: { |
661 | | // op: imm12 |
662 | 14 | op = getImmOpValue(MI, 2, Fixups, STI); |
663 | 14 | Value |= (op & UINT64_C(4064)) << 20; |
664 | 14 | Value |= (op & UINT64_C(31)) << 7; |
665 | | // op: rs2 |
666 | 14 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
667 | 14 | Value |= (op & UINT64_C(31)) << 20; |
668 | | // op: rs1 |
669 | 14 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
670 | 14 | Value |= (op & UINT64_C(31)) << 15; |
671 | 14 | break; |
672 | 12 | } |
673 | 78 | case RISCV::ADDI: |
674 | 80 | case RISCV::ADDIW: |
675 | 84 | case RISCV::ANDI: |
676 | 84 | case RISCV::FLD: |
677 | 84 | case RISCV::FLW: |
678 | 113 | case RISCV::JALR: |
679 | 113 | case RISCV::LB: |
680 | 113 | case RISCV::LBU: |
681 | 113 | case RISCV::LD: |
682 | 113 | case RISCV::LH: |
683 | 113 | case RISCV::LHU: |
684 | 113 | case RISCV::LW: |
685 | 113 | case RISCV::LWU: |
686 | 113 | case RISCV::ORI: |
687 | 113 | case RISCV::SLTI: |
688 | 113 | case RISCV::SLTIU: |
689 | 113 | case RISCV::XORI: { |
690 | | // op: imm12 |
691 | 113 | op = getImmOpValue(MI, 2, Fixups, STI); |
692 | 113 | Value |= (op & UINT64_C(4095)) << 20; |
693 | | // op: rs1 |
694 | 113 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
695 | 113 | Value |= (op & UINT64_C(31)) << 15; |
696 | | // op: rd |
697 | 113 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
698 | 113 | Value |= (op & UINT64_C(31)) << 7; |
699 | 113 | break; |
700 | 113 | } |
701 | 0 | case RISCV::BEQ: |
702 | 0 | case RISCV::BGE: |
703 | 0 | case RISCV::BGEU: |
704 | 0 | case RISCV::BLT: |
705 | 0 | case RISCV::BLTU: |
706 | 0 | case RISCV::BNE: { |
707 | | // op: imm12 |
708 | 0 | op = getImmOpValueAsr1(MI, 2, Fixups, STI); |
709 | 0 | Value |= (op & UINT64_C(2048)) << 20; |
710 | 0 | Value |= (op & UINT64_C(1008)) << 21; |
711 | 0 | Value |= (op & UINT64_C(15)) << 8; |
712 | 0 | Value |= (op & UINT64_C(1024)) >> 3; |
713 | | // op: rs2 |
714 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
715 | 0 | Value |= (op & UINT64_C(31)) << 20; |
716 | | // op: rs1 |
717 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
718 | 0 | Value |= (op & UINT64_C(31)) << 15; |
719 | 0 | break; |
720 | 0 | } |
721 | 0 | case RISCV::CSRRC: |
722 | 2 | case RISCV::CSRRCI: |
723 | 2 | case RISCV::CSRRS: |
724 | 8 | case RISCV::CSRRSI: |
725 | 8 | case RISCV::CSRRW: |
726 | 9 | case RISCV::CSRRWI: { |
727 | | // op: imm12 |
728 | 9 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
729 | 9 | Value |= (op & UINT64_C(4095)) << 20; |
730 | | // op: rs1 |
731 | 9 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
732 | 9 | Value |= (op & UINT64_C(31)) << 15; |
733 | | // op: rd |
734 | 9 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
735 | 9 | Value |= (op & UINT64_C(31)) << 7; |
736 | 9 | break; |
737 | 8 | } |
738 | 43 | case RISCV::AUIPC: |
739 | 43 | case RISCV::LUI: { |
740 | | // op: imm20 |
741 | 43 | op = getImmOpValue(MI, 1, Fixups, STI); |
742 | 43 | Value |= (op & UINT64_C(1048575)) << 12; |
743 | | // op: rd |
744 | 43 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
745 | 43 | Value |= (op & UINT64_C(31)) << 7; |
746 | 43 | break; |
747 | 43 | } |
748 | 58 | case RISCV::JAL: { |
749 | | // op: imm20 |
750 | 58 | op = getImmOpValueAsr1(MI, 1, Fixups, STI); |
751 | 58 | Value |= (op & UINT64_C(524288)) << 12; |
752 | 58 | Value |= (op & UINT64_C(1023)) << 21; |
753 | 58 | Value |= (op & UINT64_C(1024)) << 10; |
754 | 58 | Value |= (op & UINT64_C(522240)) << 1; |
755 | | // op: rd |
756 | 58 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
757 | 58 | Value |= (op & UINT64_C(31)) << 7; |
758 | 58 | break; |
759 | 43 | } |
760 | 786 | case RISCV::C_J: |
761 | 804 | case RISCV::C_JAL: { |
762 | | // op: offset |
763 | 804 | op = getImmOpValueAsr1(MI, 0, Fixups, STI); |
764 | 804 | Value |= (op & UINT64_C(1024)) << 2; |
765 | 804 | Value |= (op & UINT64_C(8)) << 8; |
766 | 804 | Value |= (op & UINT64_C(384)) << 2; |
767 | 804 | Value |= (op & UINT64_C(512)) >> 1; |
768 | 804 | Value |= (op & UINT64_C(32)) << 2; |
769 | 804 | Value |= op & UINT64_C(64); |
770 | 804 | Value |= (op & UINT64_C(7)) << 3; |
771 | 804 | Value |= (op & UINT64_C(16)) >> 2; |
772 | 804 | break; |
773 | 786 | } |
774 | 1 | case RISCV::FENCE: { |
775 | | // op: pred |
776 | 1 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
777 | 1 | Value |= (op & UINT64_C(15)) << 24; |
778 | | // op: succ |
779 | 1 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
780 | 1 | Value |= (op & UINT64_C(15)) << 20; |
781 | 1 | break; |
782 | 786 | } |
783 | 0 | case RISCV::C_FLD: |
784 | 0 | case RISCV::C_LD: { |
785 | | // op: rd |
786 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
787 | 0 | Value |= (op & UINT64_C(7)) << 2; |
788 | | // op: rs1 |
789 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
790 | 0 | Value |= (op & UINT64_C(7)) << 7; |
791 | | // op: imm |
792 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
793 | 0 | Value |= (op & UINT64_C(56)) << 7; |
794 | 0 | Value |= (op & UINT64_C(192)) >> 1; |
795 | 0 | break; |
796 | 0 | } |
797 | 0 | case RISCV::C_FLW: |
798 | 0 | case RISCV::C_LW: { |
799 | | // op: rd |
800 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
801 | 0 | Value |= (op & UINT64_C(7)) << 2; |
802 | | // op: rs1 |
803 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
804 | 0 | Value |= (op & UINT64_C(7)) << 7; |
805 | | // op: imm |
806 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
807 | 0 | Value |= (op & UINT64_C(56)) << 7; |
808 | 0 | Value |= (op & UINT64_C(4)) << 4; |
809 | 0 | Value |= (op & UINT64_C(64)) >> 1; |
810 | 0 | break; |
811 | 0 | } |
812 | 0 | case RISCV::C_JALR: |
813 | 395 | case RISCV::C_JR: { |
814 | | // op: rs1 |
815 | 395 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
816 | 395 | Value |= (op & UINT64_C(31)) << 7; |
817 | 395 | break; |
818 | 0 | } |
819 | 7 | case RISCV::C_MV: { |
820 | | // op: rs1 |
821 | 7 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
822 | 7 | Value |= (op & UINT64_C(31)) << 7; |
823 | | // op: rs2 |
824 | 7 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
825 | 7 | Value |= (op & UINT64_C(31)) << 2; |
826 | 7 | break; |
827 | 0 | } |
828 | 0 | case RISCV::FCVT_D_L: |
829 | 0 | case RISCV::FCVT_D_LU: |
830 | 0 | case RISCV::FCVT_LU_D: |
831 | 0 | case RISCV::FCVT_LU_S: |
832 | 0 | case RISCV::FCVT_L_D: |
833 | 0 | case RISCV::FCVT_L_S: |
834 | 0 | case RISCV::FCVT_S_D: |
835 | 0 | case RISCV::FCVT_S_L: |
836 | 0 | case RISCV::FCVT_S_LU: |
837 | 0 | case RISCV::FCVT_S_W: |
838 | 0 | case RISCV::FCVT_S_WU: |
839 | 0 | case RISCV::FCVT_WU_D: |
840 | 0 | case RISCV::FCVT_WU_S: |
841 | 0 | case RISCV::FCVT_W_D: |
842 | 0 | case RISCV::FCVT_W_S: |
843 | 0 | case RISCV::FSQRT_D: |
844 | 0 | case RISCV::FSQRT_S: { |
845 | | // op: rs1 |
846 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
847 | 0 | Value |= (op & UINT64_C(31)) << 15; |
848 | | // op: funct3 |
849 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
850 | 0 | Value |= (op & UINT64_C(7)) << 12; |
851 | | // op: rd |
852 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
853 | 0 | Value |= (op & UINT64_C(31)) << 7; |
854 | 0 | break; |
855 | 0 | } |
856 | 0 | case RISCV::FCLASS_D: |
857 | 0 | case RISCV::FCLASS_S: |
858 | 0 | case RISCV::FCVT_D_S: |
859 | 0 | case RISCV::FCVT_D_W: |
860 | 0 | case RISCV::FCVT_D_WU: |
861 | 0 | case RISCV::FMV_D_X: |
862 | 0 | case RISCV::FMV_W_X: |
863 | 0 | case RISCV::FMV_X_D: |
864 | 0 | case RISCV::FMV_X_W: |
865 | 0 | case RISCV::LR_D: |
866 | 0 | case RISCV::LR_D_AQ: |
867 | 0 | case RISCV::LR_D_AQ_RL: |
868 | 0 | case RISCV::LR_D_RL: |
869 | 0 | case RISCV::LR_W: |
870 | 0 | case RISCV::LR_W_AQ: |
871 | 0 | case RISCV::LR_W_AQ_RL: |
872 | 0 | case RISCV::LR_W_RL: { |
873 | | // op: rs1 |
874 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
875 | 0 | Value |= (op & UINT64_C(31)) << 15; |
876 | | // op: rd |
877 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
878 | 0 | Value |= (op & UINT64_C(31)) << 7; |
879 | 0 | break; |
880 | 0 | } |
881 | 7 | case RISCV::C_ADD: { |
882 | | // op: rs1 |
883 | 7 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
884 | 7 | Value |= (op & UINT64_C(31)) << 7; |
885 | | // op: rs2 |
886 | 7 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
887 | 7 | Value |= (op & UINT64_C(31)) << 2; |
888 | 7 | break; |
889 | 0 | } |
890 | 0 | case RISCV::C_FSD: |
891 | 0 | case RISCV::C_SD: { |
892 | | // op: rs2 |
893 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
894 | 0 | Value |= (op & UINT64_C(7)) << 2; |
895 | | // op: rs1 |
896 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
897 | 0 | Value |= (op & UINT64_C(7)) << 7; |
898 | | // op: imm |
899 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
900 | 0 | Value |= (op & UINT64_C(56)) << 7; |
901 | 0 | Value |= (op & UINT64_C(192)) >> 1; |
902 | 0 | break; |
903 | 0 | } |
904 | 0 | case RISCV::C_FSW: |
905 | 0 | case RISCV::C_SW: { |
906 | | // op: rs2 |
907 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
908 | 0 | Value |= (op & UINT64_C(7)) << 2; |
909 | | // op: rs1 |
910 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
911 | 0 | Value |= (op & UINT64_C(7)) << 7; |
912 | | // op: imm |
913 | 0 | op = getImmOpValue(MI, 2, Fixups, STI); |
914 | 0 | Value |= (op & UINT64_C(56)) << 7; |
915 | 0 | Value |= (op & UINT64_C(4)) << 4; |
916 | 0 | Value |= (op & UINT64_C(64)) >> 1; |
917 | 0 | break; |
918 | 0 | } |
919 | 0 | case RISCV::SFENCE_VMA: { |
920 | | // op: rs2 |
921 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
922 | 0 | Value |= (op & UINT64_C(31)) << 20; |
923 | | // op: rs1 |
924 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
925 | 0 | Value |= (op & UINT64_C(31)) << 15; |
926 | 0 | break; |
927 | 0 | } |
928 | 0 | case RISCV::FADD_D: |
929 | 0 | case RISCV::FADD_S: |
930 | 0 | case RISCV::FDIV_D: |
931 | 0 | case RISCV::FDIV_S: |
932 | 0 | case RISCV::FMUL_D: |
933 | 0 | case RISCV::FMUL_S: |
934 | 0 | case RISCV::FSUB_D: |
935 | 0 | case RISCV::FSUB_S: { |
936 | | // op: rs2 |
937 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
938 | 0 | Value |= (op & UINT64_C(31)) << 20; |
939 | | // op: rs1 |
940 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
941 | 0 | Value |= (op & UINT64_C(31)) << 15; |
942 | | // op: funct3 |
943 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
944 | 0 | Value |= (op & UINT64_C(7)) << 12; |
945 | | // op: rd |
946 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
947 | 0 | Value |= (op & UINT64_C(31)) << 7; |
948 | 0 | break; |
949 | 0 | } |
950 | 4 | case RISCV::ADD: |
951 | 13 | case RISCV::ADDW: |
952 | 13 | case RISCV::AMOADD_D: |
953 | 13 | case RISCV::AMOADD_D_AQ: |
954 | 13 | case RISCV::AMOADD_D_AQ_RL: |
955 | 13 | case RISCV::AMOADD_D_RL: |
956 | 13 | case RISCV::AMOADD_W: |
957 | 13 | case RISCV::AMOADD_W_AQ: |
958 | 13 | case RISCV::AMOADD_W_AQ_RL: |
959 | 13 | case RISCV::AMOADD_W_RL: |
960 | 13 | case RISCV::AMOAND_D: |
961 | 13 | case RISCV::AMOAND_D_AQ: |
962 | 13 | case RISCV::AMOAND_D_AQ_RL: |
963 | 13 | case RISCV::AMOAND_D_RL: |
964 | 13 | case RISCV::AMOAND_W: |
965 | 13 | case RISCV::AMOAND_W_AQ: |
966 | 13 | case RISCV::AMOAND_W_AQ_RL: |
967 | 13 | case RISCV::AMOAND_W_RL: |
968 | 13 | case RISCV::AMOMAXU_D: |
969 | 13 | case RISCV::AMOMAXU_D_AQ: |
970 | 13 | case RISCV::AMOMAXU_D_AQ_RL: |
971 | 13 | case RISCV::AMOMAXU_D_RL: |
972 | 13 | case RISCV::AMOMAXU_W: |
973 | 13 | case RISCV::AMOMAXU_W_AQ: |
974 | 13 | case RISCV::AMOMAXU_W_AQ_RL: |
975 | 13 | case RISCV::AMOMAXU_W_RL: |
976 | 13 | case RISCV::AMOMAX_D: |
977 | 13 | case RISCV::AMOMAX_D_AQ: |
978 | 13 | case RISCV::AMOMAX_D_AQ_RL: |
979 | 13 | case RISCV::AMOMAX_D_RL: |
980 | 13 | case RISCV::AMOMAX_W: |
981 | 13 | case RISCV::AMOMAX_W_AQ: |
982 | 13 | case RISCV::AMOMAX_W_AQ_RL: |
983 | 13 | case RISCV::AMOMAX_W_RL: |
984 | 13 | case RISCV::AMOMINU_D: |
985 | 13 | case RISCV::AMOMINU_D_AQ: |
986 | 13 | case RISCV::AMOMINU_D_AQ_RL: |
987 | 13 | case RISCV::AMOMINU_D_RL: |
988 | 13 | case RISCV::AMOMINU_W: |
989 | 13 | case RISCV::AMOMINU_W_AQ: |
990 | 13 | case RISCV::AMOMINU_W_AQ_RL: |
991 | 13 | case RISCV::AMOMINU_W_RL: |
992 | 13 | case RISCV::AMOMIN_D: |
993 | 13 | case RISCV::AMOMIN_D_AQ: |
994 | 13 | case RISCV::AMOMIN_D_AQ_RL: |
995 | 13 | case RISCV::AMOMIN_D_RL: |
996 | 13 | case RISCV::AMOMIN_W: |
997 | 13 | case RISCV::AMOMIN_W_AQ: |
998 | 13 | case RISCV::AMOMIN_W_AQ_RL: |
999 | 13 | case RISCV::AMOMIN_W_RL: |
1000 | 13 | case RISCV::AMOOR_D: |
1001 | 13 | case RISCV::AMOOR_D_AQ: |
1002 | 13 | case RISCV::AMOOR_D_AQ_RL: |
1003 | 13 | case RISCV::AMOOR_D_RL: |
1004 | 13 | case RISCV::AMOOR_W: |
1005 | 13 | case RISCV::AMOOR_W_AQ: |
1006 | 13 | case RISCV::AMOOR_W_AQ_RL: |
1007 | 13 | case RISCV::AMOOR_W_RL: |
1008 | 13 | case RISCV::AMOSWAP_D: |
1009 | 13 | case RISCV::AMOSWAP_D_AQ: |
1010 | 13 | case RISCV::AMOSWAP_D_AQ_RL: |
1011 | 13 | case RISCV::AMOSWAP_D_RL: |
1012 | 13 | case RISCV::AMOSWAP_W: |
1013 | 13 | case RISCV::AMOSWAP_W_AQ: |
1014 | 13 | case RISCV::AMOSWAP_W_AQ_RL: |
1015 | 13 | case RISCV::AMOSWAP_W_RL: |
1016 | 13 | case RISCV::AMOXOR_D: |
1017 | 13 | case RISCV::AMOXOR_D_AQ: |
1018 | 13 | case RISCV::AMOXOR_D_AQ_RL: |
1019 | 13 | case RISCV::AMOXOR_D_RL: |
1020 | 13 | case RISCV::AMOXOR_W: |
1021 | 13 | case RISCV::AMOXOR_W_AQ: |
1022 | 13 | case RISCV::AMOXOR_W_AQ_RL: |
1023 | 13 | case RISCV::AMOXOR_W_RL: |
1024 | 14 | case RISCV::AND: |
1025 | 14 | case RISCV::DIV: |
1026 | 14 | case RISCV::DIVU: |
1027 | 14 | case RISCV::DIVUW: |
1028 | 14 | case RISCV::DIVW: |
1029 | 14 | case RISCV::FEQ_D: |
1030 | 14 | case RISCV::FEQ_S: |
1031 | 14 | case RISCV::FLE_D: |
1032 | 14 | case RISCV::FLE_S: |
1033 | 14 | case RISCV::FLT_D: |
1034 | 14 | case RISCV::FLT_S: |
1035 | 14 | case RISCV::FMAX_D: |
1036 | 14 | case RISCV::FMAX_S: |
1037 | 14 | case RISCV::FMIN_D: |
1038 | 14 | case RISCV::FMIN_S: |
1039 | 14 | case RISCV::FSGNJN_D: |
1040 | 14 | case RISCV::FSGNJN_S: |
1041 | 14 | case RISCV::FSGNJX_D: |
1042 | 14 | case RISCV::FSGNJX_S: |
1043 | 14 | case RISCV::FSGNJ_D: |
1044 | 14 | case RISCV::FSGNJ_S: |
1045 | 14 | case RISCV::MUL: |
1046 | 14 | case RISCV::MULH: |
1047 | 14 | case RISCV::MULHSU: |
1048 | 14 | case RISCV::MULHU: |
1049 | 14 | case RISCV::MULW: |
1050 | 14 | case RISCV::OR: |
1051 | 14 | case RISCV::REM: |
1052 | 14 | case RISCV::REMU: |
1053 | 14 | case RISCV::REMUW: |
1054 | 14 | case RISCV::REMW: |
1055 | 14 | case RISCV::SC_D: |
1056 | 14 | case RISCV::SC_D_AQ: |
1057 | 14 | case RISCV::SC_D_AQ_RL: |
1058 | 14 | case RISCV::SC_D_RL: |
1059 | 14 | case RISCV::SC_W: |
1060 | 14 | case RISCV::SC_W_AQ: |
1061 | 14 | case RISCV::SC_W_AQ_RL: |
1062 | 14 | case RISCV::SC_W_RL: |
1063 | 14 | case RISCV::SLL: |
1064 | 14 | case RISCV::SLLW: |
1065 | 14 | case RISCV::SLT: |
1066 | 14 | case RISCV::SLTU: |
1067 | 14 | case RISCV::SRA: |
1068 | 14 | case RISCV::SRAW: |
1069 | 14 | case RISCV::SRL: |
1070 | 14 | case RISCV::SRLW: |
1071 | 14 | case RISCV::SUB: |
1072 | 14 | case RISCV::SUBW: |
1073 | 14 | case RISCV::XOR: { |
1074 | | // op: rs2 |
1075 | 14 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1076 | 14 | Value |= (op & UINT64_C(31)) << 20; |
1077 | | // op: rs1 |
1078 | 14 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1079 | 14 | Value |= (op & UINT64_C(31)) << 15; |
1080 | | // op: rd |
1081 | 14 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1082 | 14 | Value |= (op & UINT64_C(31)) << 7; |
1083 | 14 | break; |
1084 | 14 | } |
1085 | 6 | case RISCV::C_ADDW: |
1086 | 6 | case RISCV::C_AND: |
1087 | 6 | case RISCV::C_OR: |
1088 | 6 | case RISCV::C_SUB: |
1089 | 6 | case RISCV::C_SUBW: |
1090 | 6 | case RISCV::C_XOR: { |
1091 | | // op: rs2 |
1092 | 6 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1093 | 6 | Value |= (op & UINT64_C(7)) << 2; |
1094 | | // op: rd |
1095 | 6 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1096 | 6 | Value |= (op & UINT64_C(7)) << 7; |
1097 | 6 | break; |
1098 | 6 | } |
1099 | 0 | case RISCV::FMADD_D: |
1100 | 0 | case RISCV::FMADD_S: |
1101 | 0 | case RISCV::FMSUB_D: |
1102 | 0 | case RISCV::FMSUB_S: |
1103 | 0 | case RISCV::FNMADD_D: |
1104 | 0 | case RISCV::FNMADD_S: |
1105 | 0 | case RISCV::FNMSUB_D: |
1106 | 0 | case RISCV::FNMSUB_S: { |
1107 | | // op: rs3 |
1108 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1109 | 0 | Value |= (op & UINT64_C(31)) << 27; |
1110 | | // op: rs2 |
1111 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1112 | 0 | Value |= (op & UINT64_C(31)) << 20; |
1113 | | // op: rs1 |
1114 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1115 | 0 | Value |= (op & UINT64_C(31)) << 15; |
1116 | | // op: funct3 |
1117 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
1118 | 0 | Value |= (op & UINT64_C(7)) << 12; |
1119 | | // op: rd |
1120 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1121 | 0 | Value |= (op & UINT64_C(31)) << 7; |
1122 | 0 | break; |
1123 | 0 | } |
1124 | 0 | case RISCV::SLLIW: |
1125 | 0 | case RISCV::SRAIW: |
1126 | 0 | case RISCV::SRLIW: { |
1127 | | // op: shamt |
1128 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1129 | 0 | Value |= (op & UINT64_C(31)) << 20; |
1130 | | // op: rs1 |
1131 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1132 | 0 | Value |= (op & UINT64_C(31)) << 15; |
1133 | | // op: rd |
1134 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1135 | 0 | Value |= (op & UINT64_C(31)) << 7; |
1136 | 0 | break; |
1137 | 0 | } |
1138 | 0 | case RISCV::SLLI: |
1139 | 0 | case RISCV::SRAI: |
1140 | 0 | case RISCV::SRLI: { |
1141 | | // op: shamt |
1142 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1143 | 0 | Value |= (op & UINT64_C(63)) << 20; |
1144 | | // op: rs1 |
1145 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1146 | 0 | Value |= (op & UINT64_C(31)) << 15; |
1147 | | // op: rd |
1148 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1149 | 0 | Value |= (op & UINT64_C(31)) << 7; |
1150 | 0 | break; |
1151 | 0 | } |
1152 | 0 | default: |
1153 | 0 | std::string msg; |
1154 | 0 | raw_string_ostream Msg(msg); |
1155 | 0 | Msg << "Not supported instr: " << MI; |
1156 | 0 | report_fatal_error(Msg.str()); |
1157 | 2.11k | } |
1158 | 2.11k | return Value; |
1159 | 2.11k | } |