/src/keystone/llvm/lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp

Source
//===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

#include "llvm/MC/MCAsmBackend.h"
#include "MCTargetDesc/SparcFixupKinds.h"
#include "MCTargetDesc/SparcMCTargetDesc.h"
#include "llvm/MC/MCELFObjectWriter.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCFixupKindInfo.h"
#include "llvm/MC/MCObjectWriter.h"
#include "llvm/MC/MCValue.h"
#include "llvm/Support/TargetRegistry.h"

using namespace llvm_ks;

static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
  switch (Kind) {
  default:
    llvm_unreachable("Unknown fixup kind!");
  case FK_Data_1:
  case FK_Data_2:
  case FK_Data_4:
  case FK_Data_8:
    return Value;

  case Sparc::fixup_sparc_wplt30:
  case Sparc::fixup_sparc_call30:
    return (Value >> 2) & 0x3fffffff;

  case Sparc::fixup_sparc_br22:
    return (Value >> 2) & 0x3fffff;

  case Sparc::fixup_sparc_br19:
    return (Value >> 2) & 0x7ffff;

  case Sparc::fixup_sparc_br16_2:
    return (Value >> 2) & 0xc000;

  case Sparc::fixup_sparc_br16_14:
    return (Value >> 2) & 0x3fff;

  case Sparc::fixup_sparc_pc22:
  case Sparc::fixup_sparc_got22:
  case Sparc::fixup_sparc_tls_gd_hi22:
  case Sparc::fixup_sparc_tls_ldm_hi22:
  case Sparc::fixup_sparc_tls_ie_hi22:
  case Sparc::fixup_sparc_hi22:
    return (Value >> 10) & 0x3fffff;

  case Sparc::fixup_sparc_pc10:
  case Sparc::fixup_sparc_got10:
  case Sparc::fixup_sparc_tls_gd_lo10:
  case Sparc::fixup_sparc_tls_ldm_lo10:
  case Sparc::fixup_sparc_tls_ie_lo10:
  case Sparc::fixup_sparc_lo10:
    return Value & 0x3ff;

  case Sparc::fixup_sparc_tls_ldo_hix22:
  case Sparc::fixup_sparc_tls_le_hix22:
    return (~Value >> 10) & 0x3fffff;

  case Sparc::fixup_sparc_tls_ldo_lox10:
  case Sparc::fixup_sparc_tls_le_lox10:
    return (~(~Value & 0x3ff)) & 0x1fff;

  case Sparc::fixup_sparc_h44:
    return (Value >> 22) & 0x3fffff;

  case Sparc::fixup_sparc_m44:
    return (Value >> 12) & 0x3ff;

  case Sparc::fixup_sparc_l44:
    return Value & 0xfff;

  case Sparc::fixup_sparc_hh:
    return (Value >> 42) & 0x3fffff;

  case Sparc::fixup_sparc_hm:
    return (Value >> 32) & 0x3ff;

  case Sparc::fixup_sparc_tls_gd_add:
  case Sparc::fixup_sparc_tls_gd_call:
  case Sparc::fixup_sparc_tls_ldm_add:
  case Sparc::fixup_sparc_tls_ldm_call:
  case Sparc::fixup_sparc_tls_ldo_add:
  case Sparc::fixup_sparc_tls_ie_ld:
  case Sparc::fixup_sparc_tls_ie_ldx:
  case Sparc::fixup_sparc_tls_ie_add:
    return 0;
  }
}

namespace {
  class SparcAsmBackend : public MCAsmBackend {
  protected:
    const Target &TheTarget;
    bool IsLittleEndian;
    bool Is64Bit;

  public:
    SparcAsmBackend(const Target &T)
        : MCAsmBackend(), TheTarget(T),
          IsLittleEndian(StringRef(TheTarget.getName()) == "sparcel"),
          Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {}

    unsigned getNumFixupKinds() const override {
      return Sparc::NumTargetFixupKinds;
    }

    const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
      const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
        // name                    offset bits  flags
        { "fixup_sparc_call30",     2,     30,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_br22",      10,     22,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_br19",      13,     19,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_br16_2",    10,      2,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_br16_14",   18,     14,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_hi22",      10,     22,  0 },
        { "fixup_sparc_lo10",      22,     10,  0 },
        { "fixup_sparc_h44",       10,     22,  0 },
        { "fixup_sparc_m44",       22,     10,  0 },
        { "fixup_sparc_l44",       20,     12,  0 },
        { "fixup_sparc_hh",        10,     22,  0 },
        { "fixup_sparc_hm",        22,     10,  0 },
        { "fixup_sparc_pc22",      10,     22,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_pc10",      22,     10,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_got22",     10,     22,  0 },
        { "fixup_sparc_got10",     22,     10,  0 },
        { "fixup_sparc_wplt30",     2,     30,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_tls_gd_hi22",   10, 22,  0 },
        { "fixup_sparc_tls_gd_lo10",   22, 10,  0 },
        { "fixup_sparc_tls_gd_add",     0,  0,  0 },
        { "fixup_sparc_tls_gd_call",    0,  0,  0 },
        { "fixup_sparc_tls_ldm_hi22",  10, 22,  0 },
        { "fixup_sparc_tls_ldm_lo10",  22, 10,  0 },
        { "fixup_sparc_tls_ldm_add",    0,  0,  0 },
        { "fixup_sparc_tls_ldm_call",   0,  0,  0 },
        { "fixup_sparc_tls_ldo_hix22", 10, 22,  0 },
        { "fixup_sparc_tls_ldo_lox10", 22, 10,  0 },
        { "fixup_sparc_tls_ldo_add",    0,  0,  0 },
        { "fixup_sparc_tls_ie_hi22",   10, 22,  0 },
        { "fixup_sparc_tls_ie_lo10",   22, 10,  0 },
        { "fixup_sparc_tls_ie_ld",      0,  0,  0 },
        { "fixup_sparc_tls_ie_ldx",     0,  0,  0 },
        { "fixup_sparc_tls_ie_add",     0,  0,  0 },
        { "fixup_sparc_tls_le_hix22",   0,  0,  0 },
        { "fixup_sparc_tls_le_lox10",   0,  0,  0 }
      };

      const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
        // name                    offset bits  flags
        { "fixup_sparc_call30",     0,     30,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_br22",       0,     22,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_br19",       0,     19,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_br16_2",    20,      2,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_br16_14",    0,     14,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_hi22",       0,     22,  0 },
        { "fixup_sparc_lo10",       0,     10,  0 },
        { "fixup_sparc_h44",        0,     22,  0 },
        { "fixup_sparc_m44",        0,     10,  0 },
        { "fixup_sparc_l44",        0,     12,  0 },
        { "fixup_sparc_hh",         0,     22,  0 },
        { "fixup_sparc_hm",         0,     10,  0 },
        { "fixup_sparc_pc22",       0,     22,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_pc10",       0,     10,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_got22",      0,     22,  0 },
        { "fixup_sparc_got10",      0,     10,  0 },
        { "fixup_sparc_wplt30",      0,     30,  MCFixupKindInfo::FKF_IsPCRel },
        { "fixup_sparc_tls_gd_hi22",    0, 22,  0 },
        { "fixup_sparc_tls_gd_lo10",    0, 10,  0 },
        { "fixup_sparc_tls_gd_add",     0,  0,  0 },
        { "fixup_sparc_tls_gd_call",    0,  0,  0 },
        { "fixup_sparc_tls_ldm_hi22",   0, 22,  0 },
        { "fixup_sparc_tls_ldm_lo10",   0, 10,  0 },
        { "fixup_sparc_tls_ldm_add",    0,  0,  0 },
        { "fixup_sparc_tls_ldm_call",   0,  0,  0 },
        { "fixup_sparc_tls_ldo_hix22",  0, 22,  0 },
        { "fixup_sparc_tls_ldo_lox10",  0, 10,  0 },
        { "fixup_sparc_tls_ldo_add",    0,  0,  0 },
        { "fixup_sparc_tls_ie_hi22",    0, 22,  0 },
        { "fixup_sparc_tls_ie_lo10",    0, 10,  0 },
        { "fixup_sparc_tls_ie_ld",      0,  0,  0 },
        { "fixup_sparc_tls_ie_ldx",     0,  0,  0 },
        { "fixup_sparc_tls_ie_add",     0,  0,  0 },
        { "fixup_sparc_tls_le_hix22",   0,  0,  0 },
        { "fixup_sparc_tls_le_lox10",   0,  0,  0 }
      };

      if (Kind < FirstTargetFixupKind)
        return MCAsmBackend::getFixupKindInfo(Kind);

      assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
             "Invalid kind!");
      if (IsLittleEndian)
        return InfosLE[Kind - FirstTargetFixupKind];

      return InfosBE[Kind - FirstTargetFixupKind];
    }

    void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
                           const MCFixup &Fixup, const MCFragment *DF,
                           const MCValue &Target, uint64_t &Value,
                           bool &IsResolved) override {
      switch ((Sparc::Fixups)Fixup.getKind()) {
      default: break;
      case Sparc::fixup_sparc_wplt30:
        if (Target.getSymA()->getSymbol().isTemporary())
          return;
      case Sparc::fixup_sparc_tls_gd_hi22:
      case Sparc::fixup_sparc_tls_gd_lo10:
      case Sparc::fixup_sparc_tls_gd_add:
      case Sparc::fixup_sparc_tls_gd_call:
      case Sparc::fixup_sparc_tls_ldm_hi22:
      case Sparc::fixup_sparc_tls_ldm_lo10:
      case Sparc::fixup_sparc_tls_ldm_add:
      case Sparc::fixup_sparc_tls_ldm_call:
      case Sparc::fixup_sparc_tls_ldo_hix22:
      case Sparc::fixup_sparc_tls_ldo_lox10:
      case Sparc::fixup_sparc_tls_ldo_add:
      case Sparc::fixup_sparc_tls_ie_hi22:
      case Sparc::fixup_sparc_tls_ie_lo10:
      case Sparc::fixup_sparc_tls_ie_ld:
      case Sparc::fixup_sparc_tls_ie_ldx:
      case Sparc::fixup_sparc_tls_ie_add:
      case Sparc::fixup_sparc_tls_le_hix22:
      case Sparc::fixup_sparc_tls_le_lox10:  IsResolved = false; break;
      }
    }

    bool mayNeedRelaxation(const MCInst &Inst) const override {
      // FIXME.
      return false;
    }

    /// fixupNeedsRelaxation - Target specific predicate for whether a given
    /// fixup requires the associated instruction to be relaxed.
    bool fixupNeedsRelaxation(const MCFixup &Fixup,
                              uint64_t Value,
                              const MCRelaxableFragment *DF,
                              const MCAsmLayout &Layout, unsigned &KsError) const override {
      // FIXME.
      llvm_unreachable("fixupNeedsRelaxation() unimplemented");
      return false;
    }
    void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
      // FIXME.
      llvm_unreachable("relaxInstruction() unimplemented");
    }

    bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
      // Cannot emit NOP with size not multiple of 32 bits.
      if (Count % 4 != 0)
        return false;

      uint64_t NumNops = Count / 4;
      for (uint64_t i = 0; i != NumNops; ++i)
        OW->write32(0x01000000);

      return true;
    }
  };

  class ELFSparcAsmBackend : public SparcAsmBackend {
    Triple::OSType OSType;
  public:
    ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
      SparcAsmBackend(T), OSType(OSType) { }

    void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
                    uint64_t Value, bool IsPCRel, unsigned int &KsError) const override {

      Value = adjustFixupValue(Fixup.getKind(), Value);
      if (!Value) return;           // Doesn't change encoding.

      unsigned Offset = Fixup.getOffset();

      // For each byte of the fragment that the fixup touches, mask in the bits
      // from the fixup value. The Value has been "split up" into the
      // appropriate bitfields above.
      for (unsigned i = 0; i != 4; ++i) {
        unsigned Idx = IsLittleEndian ? i : 3 - i;
        Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff);
      }
    }

    MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
      uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
      return createSparcELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI);
    }
  };

} // end anonymous namespace

MCAsmBackend *llvm_ks::createSparcAsmBackend(const Target &T,
                                          const MCRegisterInfo &MRI,
                                          const Triple &TT, StringRef CPU) {
  return new ELFSparcAsmBackend(T, TT.getOS());
}

Coverage Report

Created: 2025-11-16 07:15

Line	Count	Source
1		//===-- SparcAsmBackend.cpp - Sparc Assembler Backend ---------------------===//
2		//
3		// The LLVM Compiler Infrastructure
4		//
5		// This file is distributed under the University of Illinois Open Source
6		// License. See LICENSE.TXT for details.
7		//
8		//===----------------------------------------------------------------------===//
9
10		#include "llvm/MC/MCAsmBackend.h"
11		#include "MCTargetDesc/SparcFixupKinds.h"
12		#include "MCTargetDesc/SparcMCTargetDesc.h"
13		#include "llvm/MC/MCELFObjectWriter.h"
14		#include "llvm/MC/MCExpr.h"
15		#include "llvm/MC/MCFixupKindInfo.h"
16		#include "llvm/MC/MCObjectWriter.h"
17		#include "llvm/MC/MCValue.h"
18		#include "llvm/Support/TargetRegistry.h"
19
20		using namespace llvm_ks;
21
22	8.99k	static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
23	8.99k	switch (Kind) {
24	0	default:
25	0	llvm_unreachable("Unknown fixup kind!");
26	38	case FK_Data_1:
27	67	case FK_Data_2:
28	7.89k	case FK_Data_4:
29	7.93k	case FK_Data_8:
30	7.93k	return Value;
31
32	0	case Sparc::fixup_sparc_wplt30:
33	1	case Sparc::fixup_sparc_call30:
34	1	return (Value >> 2) & 0x3fffffff;
35
36	1.05k	case Sparc::fixup_sparc_br22:
37	1.05k	return (Value >> 2) & 0x3fffff;
38
39	0	case Sparc::fixup_sparc_br19:
40	0	return (Value >> 2) & 0x7ffff;
41
42	0	case Sparc::fixup_sparc_br16_2:
43	0	return (Value >> 2) & 0xc000;
44
45	0	case Sparc::fixup_sparc_br16_14:
46	0	return (Value >> 2) & 0x3fff;
47
48	0	case Sparc::fixup_sparc_pc22:
49	0	case Sparc::fixup_sparc_got22:
50	0	case Sparc::fixup_sparc_tls_gd_hi22:
51	0	case Sparc::fixup_sparc_tls_ldm_hi22:
52	0	case Sparc::fixup_sparc_tls_ie_hi22:
53	0	case Sparc::fixup_sparc_hi22:
54	0	return (Value >> 10) & 0x3fffff;
55
56	0	case Sparc::fixup_sparc_pc10:
57	0	case Sparc::fixup_sparc_got10:
58	0	case Sparc::fixup_sparc_tls_gd_lo10:
59	0	case Sparc::fixup_sparc_tls_ldm_lo10:
60	0	case Sparc::fixup_sparc_tls_ie_lo10:
61	0	case Sparc::fixup_sparc_lo10:
62	0	return Value & 0x3ff;
63
64	0	case Sparc::fixup_sparc_tls_ldo_hix22:
65	0	case Sparc::fixup_sparc_tls_le_hix22:
66	0	return (~Value >> 10) & 0x3fffff;
67
68	0	case Sparc::fixup_sparc_tls_ldo_lox10:
69	0	case Sparc::fixup_sparc_tls_le_lox10:
70	0	return (~(~Value & 0x3ff)) & 0x1fff;
71
72	0	case Sparc::fixup_sparc_h44:
73	0	return (Value >> 22) & 0x3fffff;
74
75	0	case Sparc::fixup_sparc_m44:
76	0	return (Value >> 12) & 0x3ff;
77
78	0	case Sparc::fixup_sparc_l44:
79	0	return Value & 0xfff;
80
81	0	case Sparc::fixup_sparc_hh:
82	0	return (Value >> 42) & 0x3fffff;
83
84	1	case Sparc::fixup_sparc_hm:
85	1	return (Value >> 32) & 0x3ff;
86
87	0	case Sparc::fixup_sparc_tls_gd_add:
88	0	case Sparc::fixup_sparc_tls_gd_call:
89	0	case Sparc::fixup_sparc_tls_ldm_add:
90	0	case Sparc::fixup_sparc_tls_ldm_call:
91	0	case Sparc::fixup_sparc_tls_ldo_add:
92	0	case Sparc::fixup_sparc_tls_ie_ld:
93	0	case Sparc::fixup_sparc_tls_ie_ldx:
94	0	case Sparc::fixup_sparc_tls_ie_add:
95	0	return 0;
96	8.99k	}
97	8.99k	}
98
99		namespace {
100		class SparcAsmBackend : public MCAsmBackend {
101		protected:
102		const Target &TheTarget;
103		bool IsLittleEndian;
104		bool Is64Bit;
105
106		public:
107		SparcAsmBackend(const Target &T)
108	10.5k	: MCAsmBackend(), TheTarget(T),
109	10.5k	IsLittleEndian(StringRef(TheTarget.getName()) == "sparcel"),
110	10.5k	Is64Bit(StringRef(TheTarget.getName()) == "sparcv9") {}
111
112	3.43k	unsigned getNumFixupKinds() const override {
113	3.43k	return Sparc::NumTargetFixupKinds;
114	3.43k	}
115
116	27.5k	const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
117	27.5k	const static MCFixupKindInfo InfosBE[Sparc::NumTargetFixupKinds] = {
118		// name offset bits flags
119	27.5k	{ "fixup_sparc_call30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
120	27.5k	{ "fixup_sparc_br22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
121	27.5k	{ "fixup_sparc_br19", 13, 19, MCFixupKindInfo::FKF_IsPCRel },
122	27.5k	{ "fixup_sparc_br16_2", 10, 2, MCFixupKindInfo::FKF_IsPCRel },
123	27.5k	{ "fixup_sparc_br16_14", 18, 14, MCFixupKindInfo::FKF_IsPCRel },
124	27.5k	{ "fixup_sparc_hi22", 10, 22, 0 },
125	27.5k	{ "fixup_sparc_lo10", 22, 10, 0 },
126	27.5k	{ "fixup_sparc_h44", 10, 22, 0 },
127	27.5k	{ "fixup_sparc_m44", 22, 10, 0 },
128	27.5k	{ "fixup_sparc_l44", 20, 12, 0 },
129	27.5k	{ "fixup_sparc_hh", 10, 22, 0 },
130	27.5k	{ "fixup_sparc_hm", 22, 10, 0 },
131	27.5k	{ "fixup_sparc_pc22", 10, 22, MCFixupKindInfo::FKF_IsPCRel },
132	27.5k	{ "fixup_sparc_pc10", 22, 10, MCFixupKindInfo::FKF_IsPCRel },
133	27.5k	{ "fixup_sparc_got22", 10, 22, 0 },
134	27.5k	{ "fixup_sparc_got10", 22, 10, 0 },
135	27.5k	{ "fixup_sparc_wplt30", 2, 30, MCFixupKindInfo::FKF_IsPCRel },
136	27.5k	{ "fixup_sparc_tls_gd_hi22", 10, 22, 0 },
137	27.5k	{ "fixup_sparc_tls_gd_lo10", 22, 10, 0 },
138	27.5k	{ "fixup_sparc_tls_gd_add", 0, 0, 0 },
139	27.5k	{ "fixup_sparc_tls_gd_call", 0, 0, 0 },
140	27.5k	{ "fixup_sparc_tls_ldm_hi22", 10, 22, 0 },
141	27.5k	{ "fixup_sparc_tls_ldm_lo10", 22, 10, 0 },
142	27.5k	{ "fixup_sparc_tls_ldm_add", 0, 0, 0 },
143	27.5k	{ "fixup_sparc_tls_ldm_call", 0, 0, 0 },
144	27.5k	{ "fixup_sparc_tls_ldo_hix22", 10, 22, 0 },
145	27.5k	{ "fixup_sparc_tls_ldo_lox10", 22, 10, 0 },
146	27.5k	{ "fixup_sparc_tls_ldo_add", 0, 0, 0 },
147	27.5k	{ "fixup_sparc_tls_ie_hi22", 10, 22, 0 },
148	27.5k	{ "fixup_sparc_tls_ie_lo10", 22, 10, 0 },
149	27.5k	{ "fixup_sparc_tls_ie_ld", 0, 0, 0 },
150	27.5k	{ "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
151	27.5k	{ "fixup_sparc_tls_ie_add", 0, 0, 0 },
152	27.5k	{ "fixup_sparc_tls_le_hix22", 0, 0, 0 },
153	27.5k	{ "fixup_sparc_tls_le_lox10", 0, 0, 0 }
154	27.5k	};
155
156	27.5k	const static MCFixupKindInfo InfosLE[Sparc::NumTargetFixupKinds] = {
157		// name offset bits flags
158	27.5k	{ "fixup_sparc_call30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
159	27.5k	{ "fixup_sparc_br22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
160	27.5k	{ "fixup_sparc_br19", 0, 19, MCFixupKindInfo::FKF_IsPCRel },
161	27.5k	{ "fixup_sparc_br16_2", 20, 2, MCFixupKindInfo::FKF_IsPCRel },
162	27.5k	{ "fixup_sparc_br16_14", 0, 14, MCFixupKindInfo::FKF_IsPCRel },
163	27.5k	{ "fixup_sparc_hi22", 0, 22, 0 },
164	27.5k	{ "fixup_sparc_lo10", 0, 10, 0 },
165	27.5k	{ "fixup_sparc_h44", 0, 22, 0 },
166	27.5k	{ "fixup_sparc_m44", 0, 10, 0 },
167	27.5k	{ "fixup_sparc_l44", 0, 12, 0 },
168	27.5k	{ "fixup_sparc_hh", 0, 22, 0 },
169	27.5k	{ "fixup_sparc_hm", 0, 10, 0 },
170	27.5k	{ "fixup_sparc_pc22", 0, 22, MCFixupKindInfo::FKF_IsPCRel },
171	27.5k	{ "fixup_sparc_pc10", 0, 10, MCFixupKindInfo::FKF_IsPCRel },
172	27.5k	{ "fixup_sparc_got22", 0, 22, 0 },
173	27.5k	{ "fixup_sparc_got10", 0, 10, 0 },
174	27.5k	{ "fixup_sparc_wplt30", 0, 30, MCFixupKindInfo::FKF_IsPCRel },
175	27.5k	{ "fixup_sparc_tls_gd_hi22", 0, 22, 0 },
176	27.5k	{ "fixup_sparc_tls_gd_lo10", 0, 10, 0 },
177	27.5k	{ "fixup_sparc_tls_gd_add", 0, 0, 0 },
178	27.5k	{ "fixup_sparc_tls_gd_call", 0, 0, 0 },
179	27.5k	{ "fixup_sparc_tls_ldm_hi22", 0, 22, 0 },
180	27.5k	{ "fixup_sparc_tls_ldm_lo10", 0, 10, 0 },
181	27.5k	{ "fixup_sparc_tls_ldm_add", 0, 0, 0 },
182	27.5k	{ "fixup_sparc_tls_ldm_call", 0, 0, 0 },
183	27.5k	{ "fixup_sparc_tls_ldo_hix22", 0, 22, 0 },
184	27.5k	{ "fixup_sparc_tls_ldo_lox10", 0, 10, 0 },
185	27.5k	{ "fixup_sparc_tls_ldo_add", 0, 0, 0 },
186	27.5k	{ "fixup_sparc_tls_ie_hi22", 0, 22, 0 },
187	27.5k	{ "fixup_sparc_tls_ie_lo10", 0, 10, 0 },
188	27.5k	{ "fixup_sparc_tls_ie_ld", 0, 0, 0 },
189	27.5k	{ "fixup_sparc_tls_ie_ldx", 0, 0, 0 },
190	27.5k	{ "fixup_sparc_tls_ie_add", 0, 0, 0 },
191	27.5k	{ "fixup_sparc_tls_le_hix22", 0, 0, 0 },
192	27.5k	{ "fixup_sparc_tls_le_lox10", 0, 0, 0 }
193	27.5k	};
194
195	27.5k	if (Kind < FirstTargetFixupKind)
196	24.1k	return MCAsmBackend::getFixupKindInfo(Kind);
197
198	27.5k	assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
199	3.43k	"Invalid kind!");
200	3.43k	if (IsLittleEndian)
201	3.43k	return InfosLE[Kind - FirstTargetFixupKind];
202
203	3	return InfosBE[Kind - FirstTargetFixupKind];
204	3.43k	}
205
206		void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
207		const MCFixup &Fixup, const MCFragment *DF,
208		const MCValue &Target, uint64_t &Value,
209	8.99k	bool &IsResolved) override {
210	8.99k	switch ((Sparc::Fixups)Fixup.getKind()) {
211	8.99k	default: break;
212	8.99k	case Sparc::fixup_sparc_wplt30:
213	0	if (Target.getSymA()->getSymbol().isTemporary())
214	0	return;
215	0	case Sparc::fixup_sparc_tls_gd_hi22:
216	0	case Sparc::fixup_sparc_tls_gd_lo10:
217	0	case Sparc::fixup_sparc_tls_gd_add:
218	0	case Sparc::fixup_sparc_tls_gd_call:
219	0	case Sparc::fixup_sparc_tls_ldm_hi22:
220	0	case Sparc::fixup_sparc_tls_ldm_lo10:
221	0	case Sparc::fixup_sparc_tls_ldm_add:
222	0	case Sparc::fixup_sparc_tls_ldm_call:
223	0	case Sparc::fixup_sparc_tls_ldo_hix22:
224	0	case Sparc::fixup_sparc_tls_ldo_lox10:
225	0	case Sparc::fixup_sparc_tls_ldo_add:
226	0	case Sparc::fixup_sparc_tls_ie_hi22:
227	0	case Sparc::fixup_sparc_tls_ie_lo10:
228	0	case Sparc::fixup_sparc_tls_ie_ld:
229	0	case Sparc::fixup_sparc_tls_ie_ldx:
230	0	case Sparc::fixup_sparc_tls_ie_add:
231	0	case Sparc::fixup_sparc_tls_le_hix22:
232	0	case Sparc::fixup_sparc_tls_le_lox10: IsResolved = false; break;
233	8.99k	}
234	8.99k	}
235
236	2.73k	bool mayNeedRelaxation(const MCInst &Inst) const override {
237		// FIXME.
238	2.73k	return false;
239	2.73k	}
240
241		/// fixupNeedsRelaxation - Target specific predicate for whether a given
242		/// fixup requires the associated instruction to be relaxed.
243		bool fixupNeedsRelaxation(const MCFixup &Fixup,
244		uint64_t Value,
245		const MCRelaxableFragment *DF,
246	0	const MCAsmLayout &Layout, unsigned &KsError) const override {
247		// FIXME.
248	0	llvm_unreachable("fixupNeedsRelaxation() unimplemented");
249	0	return false;
250	0	}
251	0	void relaxInstruction(const MCInst &Inst, MCInst &Res) const override {
252		// FIXME.
253	0	llvm_unreachable("relaxInstruction() unimplemented");
254	0	}
255
256	1.29k	bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override {
257		// Cannot emit NOP with size not multiple of 32 bits.
258	1.29k	if (Count % 4 != 0)
259	0	return false;
260
261	1.29k	uint64_t NumNops = Count / 4;
262	1.33k	for (uint64_t i = 0; i != NumNops; ++i)
263	46	OW->write32(0x01000000);
264
265	1.29k	return true;
266	1.29k	}
267		};
268
269		class ELFSparcAsmBackend : public SparcAsmBackend {
270		Triple::OSType OSType;
271		public:
272		ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
273	10.5k	SparcAsmBackend(T), OSType(OSType) { }
274
275		void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
276	8.99k	uint64_t Value, bool IsPCRel, unsigned int &KsError) const override {
277
278	8.99k	Value = adjustFixupValue(Fixup.getKind(), Value);
279	8.99k	if (!Value) return; // Doesn't change encoding.
280
281	7.27k	unsigned Offset = Fixup.getOffset();
282
283		// For each byte of the fragment that the fixup touches, mask in the bits
284		// from the fixup value. The Value has been "split up" into the
285		// appropriate bitfields above.
286	36.3k	for (unsigned i = 0; i != 4; ++i) {
287	29.0k	unsigned Idx = IsLittleEndian ? i : 3 - i;
288	29.0k	Data[Offset + Idx] \|= uint8_t((Value >> (i * 8)) & 0xff);
289	29.0k	}
290	7.27k	}
291
292	10.5k	MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
293	10.5k	uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
294	10.5k	return createSparcELFObjectWriter(OS, Is64Bit, IsLittleEndian, OSABI);
295	10.5k	}
296		};
297
298		} // end anonymous namespace
299
300		MCAsmBackend *llvm_ks::createSparcAsmBackend(const Target &T,
301		const MCRegisterInfo &MRI,
302	10.5k	const Triple &TT, StringRef CPU) {
303	10.5k	return new ELFSparcAsmBackend(T, TT.getOS());
304	10.5k	}