Coverage Report

Created: 2025-11-16 07:15

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/keystone/llvm/lib/Target/Sparc/SparcGenAsmMatcher.inc
Line
Count
Source
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Assembly Matcher Source Fragment                                           *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_ASSEMBLER_HEADER
11
#undef GET_ASSEMBLER_HEADER
12
  // This should be included into the middle of the declaration of
13
  // your subclasses implementation of MCTargetAsmParser.
14
  uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const;
15
  void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
16
                       const OperandVector &Operands);
17
  void convertToMapAndConstraints(unsigned Kind,
18
                           const OperandVector &Operands) override;
19
  unsigned MatchInstructionImpl(const OperandVector &Operands,
20
                                MCInst &Inst,
21
                                uint64_t &ErrorInfo, bool matchingInlineAsm,
22
                                unsigned VariantID = 0);
23
24
  enum OperandMatchResultTy {
25
    MatchOperand_Success,    // operand matched successfully
26
    MatchOperand_NoMatch,    // operand did not match
27
    MatchOperand_ParseFail   // operand matched but had errors
28
  };
29
  OperandMatchResultTy MatchOperandParserImpl(
30
    OperandVector &Operands,
31
    StringRef Mnemonic);
32
  OperandMatchResultTy tryCustomParseOperand(
33
    OperandVector &Operands,
34
    unsigned MCK);
35
36
#endif // GET_ASSEMBLER_HEADER_INFO
37
38
39
#ifdef GET_OPERAND_DIAGNOSTIC_TYPES
40
#undef GET_OPERAND_DIAGNOSTIC_TYPES
41
42
#endif // GET_OPERAND_DIAGNOSTIC_TYPES
43
44
45
#ifdef GET_REGISTER_MATCHER
46
#undef GET_REGISTER_MATCHER
47
48
// Flags for subtarget features that participate in instruction matching.
49
enum SubtargetFeatureFlag : uint8_t {
50
  Feature_HasV9 = (1ULL << 0),
51
  Feature_HasVIS = (1ULL << 1),
52
  Feature_HasVIS2 = (1ULL << 2),
53
  Feature_HasVIS3 = (1ULL << 3),
54
  Feature_None = 0
55
};
56
57
#endif // GET_REGISTER_MATCHER
58
59
60
#ifdef GET_SUBTARGET_FEATURE_NAME
61
#undef GET_SUBTARGET_FEATURE_NAME
62
63
// User-level names for subtarget features that participate in
64
// instruction matching.
65
static const char *getSubtargetFeatureName(uint64_t Val) {
66
  switch(Val) {
67
  case Feature_HasV9: return "";
68
  case Feature_HasVIS: return "";
69
  case Feature_HasVIS2: return "";
70
  case Feature_HasVIS3: return "";
71
  default: return "(unknown)";
72
  }
73
}
74
75
#endif // GET_SUBTARGET_FEATURE_NAME
76
77
78
#ifdef GET_MATCHER_IMPLEMENTATION
79
#undef GET_MATCHER_IMPLEMENTATION
80
81
78.7k
static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features, unsigned VariantID) {
82
78.7k
  switch (VariantID) {
83
78.7k
    case 0:
84
78.7k
      switch (Mnemonic.size()) {
85
76.6k
      default: break;
86
76.6k
      case 4:  // 3 strings to match.
87
1.53k
        switch (Mnemonic[0]) {
88
462
        default: break;
89
733
        case 'a':  // 1 string to match.
90
733
          if (memcmp(Mnemonic.data()+1, "ddc", 3))
91
730
            break;
92
3
          if ((Features & Feature_HasV9) == Feature_HasV9)   // "addc"
93
0
            Mnemonic = "addx";
94
3
          return;
95
80
        case 'l':  // 1 string to match.
96
80
          if (memcmp(Mnemonic.data()+1, "duw", 3))
97
77
            break;
98
3
          if ((Features & Feature_HasV9) == Feature_HasV9)   // "lduw"
99
0
            Mnemonic = "ld";
100
3
          return;
101
255
        case 's':  // 1 string to match.
102
255
          if (memcmp(Mnemonic.data()+1, "ubc", 3))
103
252
            break;
104
3
          if ((Features & Feature_HasV9) == Feature_HasV9)   // "subc"
105
0
            Mnemonic = "subx";
106
3
          return;
107
1.53k
        }
108
1.52k
        break;
109
1.52k
      case 5:  // 1 string to match.
110
250
        if (memcmp(Mnemonic.data()+0, "lduwa", 5))
111
247
          break;
112
3
        if ((Features & Feature_HasV9) == Feature_HasV9)   // "lduwa"
113
0
          Mnemonic = "lda";
114
3
        return;
115
360
      case 6:  // 3 strings to match.
116
360
        switch (Mnemonic[0]) {
117
294
        default: break;
118
294
        case 'a':  // 1 string to match.
119
34
          if (memcmp(Mnemonic.data()+1, "ddccc", 5))
120
31
            break;
121
3
          if ((Features & Feature_HasV9) == Feature_HasV9)   // "addccc"
122
0
            Mnemonic = "addxcc";
123
3
          return;
124
10
        case 'r':  // 1 string to match.
125
10
          if (memcmp(Mnemonic.data()+1, "eturn", 5))
126
7
            break;
127
3
          if ((Features & Feature_HasV9) == Feature_HasV9)   // "return"
128
0
            Mnemonic = "rett";
129
3
          return;
130
22
        case 's':  // 1 string to match.
131
22
          if (memcmp(Mnemonic.data()+1, "ubccc", 5))
132
19
            break;
133
3
          if ((Features & Feature_HasV9) == Feature_HasV9)   // "subccc"
134
0
            Mnemonic = "subxcc";
135
3
          return;
136
360
        }
137
351
        break;
138
78.7k
      }
139
78.7k
    break;
140
78.7k
  }
141
78.7k
  switch (Mnemonic.size()) {
142
76.6k
  default: break;
143
76.6k
  case 4:  // 3 strings to match.
144
1.52k
    switch (Mnemonic[0]) {
145
462
    default: break;
146
730
    case 'a':  // 1 string to match.
147
730
      if (memcmp(Mnemonic.data()+1, "ddc", 3))
148
730
        break;
149
0
      if ((Features & Feature_HasV9) == Feature_HasV9)  // "addc"
150
0
        Mnemonic = "addx";
151
0
      return;
152
77
    case 'l':  // 1 string to match.
153
77
      if (memcmp(Mnemonic.data()+1, "duw", 3))
154
77
        break;
155
0
      if ((Features & Feature_HasV9) == Feature_HasV9)  // "lduw"
156
0
        Mnemonic = "ld";
157
0
      return;
158
252
    case 's':  // 1 string to match.
159
252
      if (memcmp(Mnemonic.data()+1, "ubc", 3))
160
252
        break;
161
0
      if ((Features & Feature_HasV9) == Feature_HasV9)  // "subc"
162
0
        Mnemonic = "subx";
163
0
      return;
164
1.52k
    }
165
1.52k
    break;
166
1.52k
  case 5:  // 1 string to match.
167
247
    if (memcmp(Mnemonic.data()+0, "lduwa", 5))
168
247
      break;
169
0
    if ((Features & Feature_HasV9) == Feature_HasV9)  // "lduwa"
170
0
      Mnemonic = "lda";
171
0
    return;
172
351
  case 6:  // 3 strings to match.
173
351
    switch (Mnemonic[0]) {
174
294
    default: break;
175
294
    case 'a':  // 1 string to match.
176
31
      if (memcmp(Mnemonic.data()+1, "ddccc", 5))
177
31
        break;
178
0
      if ((Features & Feature_HasV9) == Feature_HasV9)  // "addccc"
179
0
        Mnemonic = "addxcc";
180
0
      return;
181
7
    case 'r':  // 1 string to match.
182
7
      if (memcmp(Mnemonic.data()+1, "eturn", 5))
183
7
        break;
184
0
      if ((Features & Feature_HasV9) == Feature_HasV9)  // "return"
185
0
        Mnemonic = "rett";
186
0
      return;
187
19
    case 's':  // 1 string to match.
188
19
      if (memcmp(Mnemonic.data()+1, "ubccc", 5))
189
19
        break;
190
0
      if ((Features & Feature_HasV9) == Feature_HasV9)  // "subccc"
191
0
        Mnemonic = "subxcc";
192
0
      return;
193
351
    }
194
351
    break;
195
78.7k
  }
196
78.7k
}
197
198
namespace {
199
enum OperatorConversionKind {
200
  CVT_Done,
201
  CVT_Reg,
202
  CVT_Tied,
203
  CVT_95_Reg,
204
  CVT_95_addImmOperands,
205
  CVT_imm_95_8,
206
  CVT_imm_95_13,
207
  CVT_imm_95_5,
208
  CVT_imm_95_1,
209
  CVT_imm_95_10,
210
  CVT_imm_95_11,
211
  CVT_imm_95_12,
212
  CVT_imm_95_3,
213
  CVT_imm_95_2,
214
  CVT_imm_95_4,
215
  CVT_imm_95_0,
216
  CVT_imm_95_9,
217
  CVT_imm_95_6,
218
  CVT_imm_95_14,
219
  CVT_regG0,
220
  CVT_imm_95_15,
221
  CVT_imm_95_7,
222
  CVT_regO7,
223
  CVT_95_addMEMriOperands,
224
  CVT_95_addMEMrrOperands,
225
  CVT_regFCC0,
226
  CVT_NUM_CONVERTERS
227
};
228
229
enum InstructionConversionKind {
230
  Convert__Reg1_2__Reg1_0__Reg1_1,
231
  Convert__Reg1_2__Reg1_0__Imm1_1,
232
  Convert__Imm1_0__imm_95_8,
233
  Convert__Imm1_1__imm_95_8,
234
  Convert__Imm1_1__Imm1_0,
235
  Convert__Imm1_2__imm_95_8,
236
  Convert__Imm1_2__Imm1_0,
237
  Convert__Imm1_3__imm_95_8,
238
  Convert__Imm1_3__Imm1_0,
239
  Convert__Imm1_4__Imm1_0,
240
  Convert__Imm1_0,
241
  Convert__Imm1_0__imm_95_13,
242
  Convert__Imm1_1__imm_95_13,
243
  Convert__Imm1_2__imm_95_13,
244
  Convert__Imm1_3__imm_95_13,
245
  Convert__Reg1_1__Reg1_1__Reg1_0,
246
  Convert__Reg1_1__Reg1_1__Imm1_0,
247
  Convert__Imm1_0__imm_95_5,
248
  Convert__Imm1_1__imm_95_5,
249
  Convert__Imm1_2__imm_95_5,
250
  Convert__Imm1_3__imm_95_5,
251
  Convert__Imm1_0__imm_95_1,
252
  Convert__Imm1_1__imm_95_1,
253
  Convert__Imm1_2__imm_95_1,
254
  Convert__Imm1_3__imm_95_1,
255
  Convert__Imm1_0__imm_95_10,
256
  Convert__Imm1_1__imm_95_10,
257
  Convert__Imm1_2__imm_95_10,
258
  Convert__Imm1_3__imm_95_10,
259
  Convert__Imm1_0__imm_95_11,
260
  Convert__Imm1_1__imm_95_11,
261
  Convert__Imm1_2__imm_95_11,
262
  Convert__Imm1_3__imm_95_11,
263
  Convert__Imm1_0__imm_95_12,
264
  Convert__Imm1_1__imm_95_12,
265
  Convert__Imm1_2__imm_95_12,
266
  Convert__Imm1_3__imm_95_12,
267
  Convert__Imm1_0__imm_95_3,
268
  Convert__Imm1_1__imm_95_3,
269
  Convert__Imm1_2__imm_95_3,
270
  Convert__Imm1_3__imm_95_3,
271
  Convert__Imm1_0__imm_95_2,
272
  Convert__Imm1_1__imm_95_2,
273
  Convert__Imm1_2__imm_95_2,
274
  Convert__Imm1_3__imm_95_2,
275
  Convert__Imm1_0__imm_95_4,
276
  Convert__Imm1_1__imm_95_4,
277
  Convert__Imm1_2__imm_95_4,
278
  Convert__Imm1_3__imm_95_4,
279
  Convert__Imm1_0__imm_95_0,
280
  Convert__Imm1_1__imm_95_0,
281
  Convert__Imm1_2__imm_95_0,
282
  Convert__Imm1_3__imm_95_0,
283
  Convert__Imm1_0__imm_95_9,
284
  Convert__Imm1_1__imm_95_9,
285
  Convert__Imm1_2__imm_95_9,
286
  Convert__Imm1_3__imm_95_9,
287
  Convert__Imm1_0__imm_95_6,
288
  Convert__Imm1_1__imm_95_6,
289
  Convert__Imm1_2__imm_95_6,
290
  Convert__Imm1_3__imm_95_6,
291
  Convert__Imm1_0__imm_95_14,
292
  Convert__Imm1_1__imm_95_14,
293
  Convert__Imm1_2__imm_95_14,
294
  Convert__Imm1_3__imm_95_14,
295
  Convert__Reg1_0__Imm1_1,
296
  Convert__Reg1_1__Imm1_2,
297
  Convert__Reg1_2__Imm1_3,
298
  Convert__regG0__Reg1_1__Reg1_0,
299
  Convert__regG0__Reg1_1__Imm1_0,
300
  Convert__Imm1_0__imm_95_15,
301
  Convert__Imm1_1__imm_95_15,
302
  Convert__Imm1_2__imm_95_15,
303
  Convert__Imm1_3__imm_95_15,
304
  Convert__Imm1_0__imm_95_7,
305
  Convert__Imm1_1__imm_95_7,
306
  Convert__Imm1_2__imm_95_7,
307
  Convert__Imm1_3__imm_95_7,
308
  Convert__regO7__MEMri2_0,
309
  Convert__regO7__MEMrr2_0,
310
  Convert__Reg1_4__Reg1_1__Reg1_3__Tie0,
311
  Convert__Reg1_0__regG0__regG0,
312
  Convert__MEMri2_1__regG0,
313
  Convert__MEMrr2_1__regG0,
314
  Convert__Reg1_0,
315
  Convert__Reg1_0__Reg1_1,
316
  Convert__Reg1_0__Reg1_0__imm_95_1,
317
  Convert__Reg1_1__Reg1_0,
318
  Convert__Imm1_1__imm_95_0__Reg1_0,
319
  Convert__Imm1_2__imm_95_0__Reg1_1,
320
  Convert__Imm1_2__Imm1_0__Reg1_1,
321
  Convert__Imm1_3__imm_95_0__Reg1_2,
322
  Convert__Imm1_3__Imm1_0__Reg1_2,
323
  Convert__Imm1_4__Imm1_0__Reg1_3,
324
  Convert__Imm1_1__imm_95_9__Reg1_0,
325
  Convert__Imm1_2__imm_95_9__Reg1_1,
326
  Convert__Imm1_3__imm_95_9__Reg1_2,
327
  Convert__Imm1_1__imm_95_6__Reg1_0,
328
  Convert__Imm1_2__imm_95_6__Reg1_1,
329
  Convert__Imm1_3__imm_95_6__Reg1_2,
330
  Convert__Imm1_1__imm_95_11__Reg1_0,
331
  Convert__Imm1_2__imm_95_11__Reg1_1,
332
  Convert__Imm1_3__imm_95_11__Reg1_2,
333
  Convert__Imm1_1__imm_95_4__Reg1_0,
334
  Convert__Imm1_2__imm_95_4__Reg1_1,
335
  Convert__Imm1_3__imm_95_4__Reg1_2,
336
  Convert__Imm1_1__imm_95_13__Reg1_0,
337
  Convert__Imm1_2__imm_95_13__Reg1_1,
338
  Convert__Imm1_3__imm_95_13__Reg1_2,
339
  Convert__Imm1_1__imm_95_2__Reg1_0,
340
  Convert__Imm1_2__imm_95_2__Reg1_1,
341
  Convert__Imm1_3__imm_95_2__Reg1_2,
342
  Convert__Imm1_1__imm_95_8__Reg1_0,
343
  Convert__Imm1_2__imm_95_8__Reg1_1,
344
  Convert__Imm1_3__imm_95_8__Reg1_2,
345
  Convert__Imm1_1__imm_95_1__Reg1_0,
346
  Convert__Imm1_2__imm_95_1__Reg1_1,
347
  Convert__Imm1_3__imm_95_1__Reg1_2,
348
  Convert__Imm1_1__imm_95_15__Reg1_0,
349
  Convert__Imm1_2__imm_95_15__Reg1_1,
350
  Convert__Imm1_3__imm_95_15__Reg1_2,
351
  Convert__Imm1_1__imm_95_7__Reg1_0,
352
  Convert__Imm1_2__imm_95_7__Reg1_1,
353
  Convert__Imm1_3__imm_95_7__Reg1_2,
354
  Convert__Imm1_1__imm_95_10__Reg1_0,
355
  Convert__Imm1_2__imm_95_10__Reg1_1,
356
  Convert__Imm1_3__imm_95_10__Reg1_2,
357
  Convert__Imm1_1__imm_95_5__Reg1_0,
358
  Convert__Imm1_2__imm_95_5__Reg1_1,
359
  Convert__Imm1_3__imm_95_5__Reg1_2,
360
  Convert__Imm1_1__imm_95_12__Reg1_0,
361
  Convert__Imm1_2__imm_95_12__Reg1_1,
362
  Convert__Imm1_3__imm_95_12__Reg1_2,
363
  Convert__Imm1_1__imm_95_3__Reg1_0,
364
  Convert__Imm1_2__imm_95_3__Reg1_1,
365
  Convert__Imm1_3__imm_95_3__Reg1_2,
366
  Convert__Imm1_1__imm_95_14__Reg1_0,
367
  Convert__Imm1_2__imm_95_14__Reg1_1,
368
  Convert__Imm1_3__imm_95_14__Reg1_2,
369
  Convert__regFCC0__Reg1_0__Reg1_1,
370
  Convert__Reg1_0__Reg1_1__Reg1_2,
371
  Convert_NoOperands,
372
  Convert__MEMri2_0,
373
  Convert__MEMrr2_0,
374
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_8,
375
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_0,
376
  Convert__Reg1_3__Reg1_2__Tie0__Imm1_0,
377
  Convert__Reg1_3__Reg1_1__Reg1_2__Tie0__Imm1_0,
378
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_13,
379
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_5,
380
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_1,
381
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_9,
382
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_10,
383
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_6,
384
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_11,
385
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_11,
386
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_12,
387
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_3,
388
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_4,
389
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_2,
390
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_13,
391
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_4,
392
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_2,
393
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_0,
394
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_8,
395
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_9,
396
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_1,
397
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_6,
398
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_15,
399
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_14,
400
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_7,
401
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_10,
402
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_5,
403
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_12,
404
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_3,
405
  Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_14,
406
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_15,
407
  Convert__Reg1_2__Reg1_1__Tie0__imm_95_7,
408
  Convert__Reg1_0__Tie0,
409
  Convert__regG0__MEMri2_0,
410
  Convert__regG0__MEMrr2_0,
411
  Convert__Reg1_1__MEMri2_0,
412
  Convert__Reg1_1__MEMrr2_0,
413
  Convert__MEMri2_1,
414
  Convert__Reg1_3__MEMri2_1,
415
  Convert__MEMrr2_1,
416
  Convert__Reg1_3__MEMrr2_1,
417
  Convert__Reg1_4__MEMrr2_1__Imm1_3,
418
  Convert__Reg1_1,
419
  Convert__regG0__Reg1_0,
420
  Convert__Reg1_1__regG0__Reg1_0,
421
  Convert__regG0__Imm1_0,
422
  Convert__Reg1_1__regG0__Imm1_0,
423
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_8,
424
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_0,
425
  Convert__Reg1_3__Imm1_2__Tie0__Imm1_0,
426
  Convert__Reg1_3__Reg1_1__Imm1_2__Tie0__Imm1_0,
427
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_13,
428
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_5,
429
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_1,
430
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_9,
431
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_10,
432
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_6,
433
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_11,
434
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_11,
435
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_12,
436
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_3,
437
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_4,
438
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_2,
439
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_13,
440
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_4,
441
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_2,
442
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_0,
443
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_8,
444
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_9,
445
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_1,
446
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_6,
447
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_15,
448
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_14,
449
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_7,
450
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_10,
451
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_5,
452
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_12,
453
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_3,
454
  Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_14,
455
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_15,
456
  Convert__Reg1_2__Imm1_1__Tie0__imm_95_7,
457
  Convert__Reg1_0__regG0__Reg1_0,
458
  Convert__Reg1_0__Reg1_0__regG0,
459
  Convert__Reg1_1__Reg1_0__regG0,
460
  Convert__regG0__regG0__regG0,
461
  Convert__imm_95_8,
462
  Convert__Reg1_1__Imm1_0,
463
  Convert__MEMri2_2,
464
  Convert__MEMrr2_2,
465
  Convert__MEMri2_2__Reg1_0,
466
  Convert__MEMrr2_2__Reg1_0,
467
  Convert__MEMrr2_2__Reg1_0__Imm1_4,
468
  Convert__Reg1_3__MEMri2_1__Tie0,
469
  Convert__Reg1_3__MEMrr2_1__Tie0,
470
  Convert__Reg1_4__MEMrr2_1__Imm1_3__Tie0,
471
  Convert__regG0__Reg1_0__imm_95_8,
472
  Convert__regG0__Imm1_0__imm_95_8,
473
  Convert__regG0__Reg1_1__imm_95_8,
474
  Convert__regG0__Imm1_1__imm_95_8,
475
  Convert__Reg1_0__Reg1_2__imm_95_8,
476
  Convert__Reg1_0__Imm1_2__imm_95_8,
477
  Convert__Reg1_1__Reg1_3__imm_95_8,
478
  Convert__Reg1_1__Imm1_3__imm_95_8,
479
  Convert__Reg1_2__Reg1_4__Imm1_0,
480
  Convert__Reg1_2__Imm1_4__Imm1_0,
481
  Convert__regG0__Reg1_0__imm_95_13,
482
  Convert__regG0__Imm1_0__imm_95_13,
483
  Convert__regG0__Reg1_1__imm_95_13,
484
  Convert__regG0__Imm1_1__imm_95_13,
485
  Convert__Reg1_0__Reg1_2__imm_95_13,
486
  Convert__Reg1_0__Imm1_2__imm_95_13,
487
  Convert__Reg1_1__Reg1_3__imm_95_13,
488
  Convert__Reg1_1__Imm1_3__imm_95_13,
489
  Convert__regG0__Reg1_0__imm_95_5,
490
  Convert__regG0__Imm1_0__imm_95_5,
491
  Convert__regG0__Reg1_1__imm_95_5,
492
  Convert__regG0__Imm1_1__imm_95_5,
493
  Convert__Reg1_0__Reg1_2__imm_95_5,
494
  Convert__Reg1_0__Imm1_2__imm_95_5,
495
  Convert__Reg1_1__Reg1_3__imm_95_5,
496
  Convert__Reg1_1__Imm1_3__imm_95_5,
497
  Convert__regG0__Reg1_0__imm_95_1,
498
  Convert__regG0__Imm1_0__imm_95_1,
499
  Convert__regG0__Reg1_1__imm_95_1,
500
  Convert__regG0__Imm1_1__imm_95_1,
501
  Convert__Reg1_0__Reg1_2__imm_95_1,
502
  Convert__Reg1_0__Imm1_2__imm_95_1,
503
  Convert__Reg1_1__Reg1_3__imm_95_1,
504
  Convert__Reg1_1__Imm1_3__imm_95_1,
505
  Convert__regG0__Reg1_0__imm_95_10,
506
  Convert__regG0__Imm1_0__imm_95_10,
507
  Convert__regG0__Reg1_1__imm_95_10,
508
  Convert__regG0__Imm1_1__imm_95_10,
509
  Convert__Reg1_0__Reg1_2__imm_95_10,
510
  Convert__Reg1_0__Imm1_2__imm_95_10,
511
  Convert__Reg1_1__Reg1_3__imm_95_10,
512
  Convert__Reg1_1__Imm1_3__imm_95_10,
513
  Convert__regG0__Reg1_0__imm_95_11,
514
  Convert__regG0__Imm1_0__imm_95_11,
515
  Convert__regG0__Reg1_1__imm_95_11,
516
  Convert__regG0__Imm1_1__imm_95_11,
517
  Convert__Reg1_0__Reg1_2__imm_95_11,
518
  Convert__Reg1_0__Imm1_2__imm_95_11,
519
  Convert__Reg1_1__Reg1_3__imm_95_11,
520
  Convert__Reg1_1__Imm1_3__imm_95_11,
521
  Convert__regG0__Reg1_0__imm_95_12,
522
  Convert__regG0__Imm1_0__imm_95_12,
523
  Convert__regG0__Reg1_1__imm_95_12,
524
  Convert__regG0__Imm1_1__imm_95_12,
525
  Convert__Reg1_0__Reg1_2__imm_95_12,
526
  Convert__Reg1_0__Imm1_2__imm_95_12,
527
  Convert__Reg1_1__Reg1_3__imm_95_12,
528
  Convert__Reg1_1__Imm1_3__imm_95_12,
529
  Convert__regG0__Reg1_0__imm_95_3,
530
  Convert__regG0__Imm1_0__imm_95_3,
531
  Convert__regG0__Reg1_1__imm_95_3,
532
  Convert__regG0__Imm1_1__imm_95_3,
533
  Convert__Reg1_0__Reg1_2__imm_95_3,
534
  Convert__Reg1_0__Imm1_2__imm_95_3,
535
  Convert__Reg1_1__Reg1_3__imm_95_3,
536
  Convert__Reg1_1__Imm1_3__imm_95_3,
537
  Convert__regG0__Reg1_0__imm_95_2,
538
  Convert__regG0__Imm1_0__imm_95_2,
539
  Convert__regG0__Reg1_1__imm_95_2,
540
  Convert__regG0__Imm1_1__imm_95_2,
541
  Convert__Reg1_0__Reg1_2__imm_95_2,
542
  Convert__Reg1_0__Imm1_2__imm_95_2,
543
  Convert__Reg1_1__Reg1_3__imm_95_2,
544
  Convert__Reg1_1__Imm1_3__imm_95_2,
545
  Convert__regG0__Reg1_0__imm_95_4,
546
  Convert__regG0__Imm1_0__imm_95_4,
547
  Convert__regG0__Reg1_1__imm_95_4,
548
  Convert__regG0__Imm1_1__imm_95_4,
549
  Convert__Reg1_0__Reg1_2__imm_95_4,
550
  Convert__Reg1_0__Imm1_2__imm_95_4,
551
  Convert__Reg1_1__Reg1_3__imm_95_4,
552
  Convert__Reg1_1__Imm1_3__imm_95_4,
553
  Convert__regG0__Reg1_0__imm_95_0,
554
  Convert__regG0__Imm1_0__imm_95_0,
555
  Convert__regG0__Reg1_1__imm_95_0,
556
  Convert__regG0__Imm1_1__imm_95_0,
557
  Convert__Reg1_0__Reg1_2__imm_95_0,
558
  Convert__Reg1_0__Imm1_2__imm_95_0,
559
  Convert__Reg1_1__Reg1_3__imm_95_0,
560
  Convert__Reg1_1__Imm1_3__imm_95_0,
561
  Convert__regG0__Reg1_0__imm_95_9,
562
  Convert__regG0__Imm1_0__imm_95_9,
563
  Convert__regG0__Reg1_1__imm_95_9,
564
  Convert__regG0__Imm1_1__imm_95_9,
565
  Convert__Reg1_0__Reg1_2__imm_95_9,
566
  Convert__Reg1_0__Imm1_2__imm_95_9,
567
  Convert__Reg1_1__Reg1_3__imm_95_9,
568
  Convert__Reg1_1__Imm1_3__imm_95_9,
569
  Convert__regG0__Reg1_0__imm_95_6,
570
  Convert__regG0__Imm1_0__imm_95_6,
571
  Convert__regG0__Reg1_1__imm_95_6,
572
  Convert__regG0__Imm1_1__imm_95_6,
573
  Convert__Reg1_0__Reg1_2__imm_95_6,
574
  Convert__Reg1_0__Imm1_2__imm_95_6,
575
  Convert__Reg1_1__Reg1_3__imm_95_6,
576
  Convert__Reg1_1__Imm1_3__imm_95_6,
577
  Convert__regG0__Reg1_0__imm_95_14,
578
  Convert__regG0__Imm1_0__imm_95_14,
579
  Convert__regG0__Reg1_1__imm_95_14,
580
  Convert__regG0__Imm1_1__imm_95_14,
581
  Convert__Reg1_0__Reg1_2__imm_95_14,
582
  Convert__Reg1_0__Imm1_2__imm_95_14,
583
  Convert__Reg1_1__Reg1_3__imm_95_14,
584
  Convert__Reg1_1__Imm1_3__imm_95_14,
585
  Convert__regG0__Reg1_0__regG0,
586
  Convert__regG0__Reg1_0__imm_95_15,
587
  Convert__regG0__Imm1_0__imm_95_15,
588
  Convert__regG0__Reg1_1__imm_95_15,
589
  Convert__regG0__Imm1_1__imm_95_15,
590
  Convert__Reg1_0__Reg1_2__imm_95_15,
591
  Convert__Reg1_0__Imm1_2__imm_95_15,
592
  Convert__Reg1_1__Reg1_3__imm_95_15,
593
  Convert__Reg1_1__Imm1_3__imm_95_15,
594
  Convert__regG0__Reg1_0__imm_95_7,
595
  Convert__regG0__Imm1_0__imm_95_7,
596
  Convert__regG0__Reg1_1__imm_95_7,
597
  Convert__regG0__Imm1_1__imm_95_7,
598
  Convert__Reg1_0__Reg1_2__imm_95_7,
599
  Convert__Reg1_0__Imm1_2__imm_95_7,
600
  Convert__Reg1_1__Reg1_3__imm_95_7,
601
  Convert__Reg1_1__Imm1_3__imm_95_7,
602
  CVT_NUM_SIGNATURES
603
};
604
605
} // end anonymous namespace
606
607
static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = {
608
  // Convert__Reg1_2__Reg1_0__Reg1_1
609
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
610
  // Convert__Reg1_2__Reg1_0__Imm1_1
611
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
612
  // Convert__Imm1_0__imm_95_8
613
  { CVT_95_addImmOperands, 1, CVT_imm_95_8, 0, CVT_Done },
614
  // Convert__Imm1_1__imm_95_8
615
  { CVT_95_addImmOperands, 2, CVT_imm_95_8, 0, CVT_Done },
616
  // Convert__Imm1_1__Imm1_0
617
  { CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 1, CVT_Done },
618
  // Convert__Imm1_2__imm_95_8
619
  { CVT_95_addImmOperands, 3, CVT_imm_95_8, 0, CVT_Done },
620
  // Convert__Imm1_2__Imm1_0
621
  { CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 1, CVT_Done },
622
  // Convert__Imm1_3__imm_95_8
623
  { CVT_95_addImmOperands, 4, CVT_imm_95_8, 0, CVT_Done },
624
  // Convert__Imm1_3__Imm1_0
625
  { CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_Done },
626
  // Convert__Imm1_4__Imm1_0
627
  { CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
628
  // Convert__Imm1_0
629
  { CVT_95_addImmOperands, 1, CVT_Done },
630
  // Convert__Imm1_0__imm_95_13
631
  { CVT_95_addImmOperands, 1, CVT_imm_95_13, 0, CVT_Done },
632
  // Convert__Imm1_1__imm_95_13
633
  { CVT_95_addImmOperands, 2, CVT_imm_95_13, 0, CVT_Done },
634
  // Convert__Imm1_2__imm_95_13
635
  { CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_Done },
636
  // Convert__Imm1_3__imm_95_13
637
  { CVT_95_addImmOperands, 4, CVT_imm_95_13, 0, CVT_Done },
638
  // Convert__Reg1_1__Reg1_1__Reg1_0
639
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
640
  // Convert__Reg1_1__Reg1_1__Imm1_0
641
  { CVT_95_Reg, 2, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
642
  // Convert__Imm1_0__imm_95_5
643
  { CVT_95_addImmOperands, 1, CVT_imm_95_5, 0, CVT_Done },
644
  // Convert__Imm1_1__imm_95_5
645
  { CVT_95_addImmOperands, 2, CVT_imm_95_5, 0, CVT_Done },
646
  // Convert__Imm1_2__imm_95_5
647
  { CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_Done },
648
  // Convert__Imm1_3__imm_95_5
649
  { CVT_95_addImmOperands, 4, CVT_imm_95_5, 0, CVT_Done },
650
  // Convert__Imm1_0__imm_95_1
651
  { CVT_95_addImmOperands, 1, CVT_imm_95_1, 0, CVT_Done },
652
  // Convert__Imm1_1__imm_95_1
653
  { CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_Done },
654
  // Convert__Imm1_2__imm_95_1
655
  { CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_Done },
656
  // Convert__Imm1_3__imm_95_1
657
  { CVT_95_addImmOperands, 4, CVT_imm_95_1, 0, CVT_Done },
658
  // Convert__Imm1_0__imm_95_10
659
  { CVT_95_addImmOperands, 1, CVT_imm_95_10, 0, CVT_Done },
660
  // Convert__Imm1_1__imm_95_10
661
  { CVT_95_addImmOperands, 2, CVT_imm_95_10, 0, CVT_Done },
662
  // Convert__Imm1_2__imm_95_10
663
  { CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_Done },
664
  // Convert__Imm1_3__imm_95_10
665
  { CVT_95_addImmOperands, 4, CVT_imm_95_10, 0, CVT_Done },
666
  // Convert__Imm1_0__imm_95_11
667
  { CVT_95_addImmOperands, 1, CVT_imm_95_11, 0, CVT_Done },
668
  // Convert__Imm1_1__imm_95_11
669
  { CVT_95_addImmOperands, 2, CVT_imm_95_11, 0, CVT_Done },
670
  // Convert__Imm1_2__imm_95_11
671
  { CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_Done },
672
  // Convert__Imm1_3__imm_95_11
673
  { CVT_95_addImmOperands, 4, CVT_imm_95_11, 0, CVT_Done },
674
  // Convert__Imm1_0__imm_95_12
675
  { CVT_95_addImmOperands, 1, CVT_imm_95_12, 0, CVT_Done },
676
  // Convert__Imm1_1__imm_95_12
677
  { CVT_95_addImmOperands, 2, CVT_imm_95_12, 0, CVT_Done },
678
  // Convert__Imm1_2__imm_95_12
679
  { CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_Done },
680
  // Convert__Imm1_3__imm_95_12
681
  { CVT_95_addImmOperands, 4, CVT_imm_95_12, 0, CVT_Done },
682
  // Convert__Imm1_0__imm_95_3
683
  { CVT_95_addImmOperands, 1, CVT_imm_95_3, 0, CVT_Done },
684
  // Convert__Imm1_1__imm_95_3
685
  { CVT_95_addImmOperands, 2, CVT_imm_95_3, 0, CVT_Done },
686
  // Convert__Imm1_2__imm_95_3
687
  { CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_Done },
688
  // Convert__Imm1_3__imm_95_3
689
  { CVT_95_addImmOperands, 4, CVT_imm_95_3, 0, CVT_Done },
690
  // Convert__Imm1_0__imm_95_2
691
  { CVT_95_addImmOperands, 1, CVT_imm_95_2, 0, CVT_Done },
692
  // Convert__Imm1_1__imm_95_2
693
  { CVT_95_addImmOperands, 2, CVT_imm_95_2, 0, CVT_Done },
694
  // Convert__Imm1_2__imm_95_2
695
  { CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_Done },
696
  // Convert__Imm1_3__imm_95_2
697
  { CVT_95_addImmOperands, 4, CVT_imm_95_2, 0, CVT_Done },
698
  // Convert__Imm1_0__imm_95_4
699
  { CVT_95_addImmOperands, 1, CVT_imm_95_4, 0, CVT_Done },
700
  // Convert__Imm1_1__imm_95_4
701
  { CVT_95_addImmOperands, 2, CVT_imm_95_4, 0, CVT_Done },
702
  // Convert__Imm1_2__imm_95_4
703
  { CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_Done },
704
  // Convert__Imm1_3__imm_95_4
705
  { CVT_95_addImmOperands, 4, CVT_imm_95_4, 0, CVT_Done },
706
  // Convert__Imm1_0__imm_95_0
707
  { CVT_95_addImmOperands, 1, CVT_imm_95_0, 0, CVT_Done },
708
  // Convert__Imm1_1__imm_95_0
709
  { CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
710
  // Convert__Imm1_2__imm_95_0
711
  { CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
712
  // Convert__Imm1_3__imm_95_0
713
  { CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_Done },
714
  // Convert__Imm1_0__imm_95_9
715
  { CVT_95_addImmOperands, 1, CVT_imm_95_9, 0, CVT_Done },
716
  // Convert__Imm1_1__imm_95_9
717
  { CVT_95_addImmOperands, 2, CVT_imm_95_9, 0, CVT_Done },
718
  // Convert__Imm1_2__imm_95_9
719
  { CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_Done },
720
  // Convert__Imm1_3__imm_95_9
721
  { CVT_95_addImmOperands, 4, CVT_imm_95_9, 0, CVT_Done },
722
  // Convert__Imm1_0__imm_95_6
723
  { CVT_95_addImmOperands, 1, CVT_imm_95_6, 0, CVT_Done },
724
  // Convert__Imm1_1__imm_95_6
725
  { CVT_95_addImmOperands, 2, CVT_imm_95_6, 0, CVT_Done },
726
  // Convert__Imm1_2__imm_95_6
727
  { CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_Done },
728
  // Convert__Imm1_3__imm_95_6
729
  { CVT_95_addImmOperands, 4, CVT_imm_95_6, 0, CVT_Done },
730
  // Convert__Imm1_0__imm_95_14
731
  { CVT_95_addImmOperands, 1, CVT_imm_95_14, 0, CVT_Done },
732
  // Convert__Imm1_1__imm_95_14
733
  { CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_Done },
734
  // Convert__Imm1_2__imm_95_14
735
  { CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_Done },
736
  // Convert__Imm1_3__imm_95_14
737
  { CVT_95_addImmOperands, 4, CVT_imm_95_14, 0, CVT_Done },
738
  // Convert__Reg1_0__Imm1_1
739
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done },
740
  // Convert__Reg1_1__Imm1_2
741
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Done },
742
  // Convert__Reg1_2__Imm1_3
743
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 4, CVT_Done },
744
  // Convert__regG0__Reg1_1__Reg1_0
745
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
746
  // Convert__regG0__Reg1_1__Imm1_0
747
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
748
  // Convert__Imm1_0__imm_95_15
749
  { CVT_95_addImmOperands, 1, CVT_imm_95_15, 0, CVT_Done },
750
  // Convert__Imm1_1__imm_95_15
751
  { CVT_95_addImmOperands, 2, CVT_imm_95_15, 0, CVT_Done },
752
  // Convert__Imm1_2__imm_95_15
753
  { CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_Done },
754
  // Convert__Imm1_3__imm_95_15
755
  { CVT_95_addImmOperands, 4, CVT_imm_95_15, 0, CVT_Done },
756
  // Convert__Imm1_0__imm_95_7
757
  { CVT_95_addImmOperands, 1, CVT_imm_95_7, 0, CVT_Done },
758
  // Convert__Imm1_1__imm_95_7
759
  { CVT_95_addImmOperands, 2, CVT_imm_95_7, 0, CVT_Done },
760
  // Convert__Imm1_2__imm_95_7
761
  { CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_Done },
762
  // Convert__Imm1_3__imm_95_7
763
  { CVT_95_addImmOperands, 4, CVT_imm_95_7, 0, CVT_Done },
764
  // Convert__regO7__MEMri2_0
765
  { CVT_regO7, 0, CVT_95_addMEMriOperands, 1, CVT_Done },
766
  // Convert__regO7__MEMrr2_0
767
  { CVT_regO7, 0, CVT_95_addMEMrrOperands, 1, CVT_Done },
768
  // Convert__Reg1_4__Reg1_1__Reg1_3__Tie0
769
  { CVT_95_Reg, 5, CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_Tied, 0, CVT_Done },
770
  // Convert__Reg1_0__regG0__regG0
771
  { CVT_95_Reg, 1, CVT_regG0, 0, CVT_regG0, 0, CVT_Done },
772
  // Convert__MEMri2_1__regG0
773
  { CVT_95_addMEMriOperands, 2, CVT_regG0, 0, CVT_Done },
774
  // Convert__MEMrr2_1__regG0
775
  { CVT_95_addMEMrrOperands, 2, CVT_regG0, 0, CVT_Done },
776
  // Convert__Reg1_0
777
  { CVT_95_Reg, 1, CVT_Done },
778
  // Convert__Reg1_0__Reg1_1
779
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
780
  // Convert__Reg1_0__Reg1_0__imm_95_1
781
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
782
  // Convert__Reg1_1__Reg1_0
783
  { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_Done },
784
  // Convert__Imm1_1__imm_95_0__Reg1_0
785
  { CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_95_Reg, 1, CVT_Done },
786
  // Convert__Imm1_2__imm_95_0__Reg1_1
787
  { CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_95_Reg, 2, CVT_Done },
788
  // Convert__Imm1_2__Imm1_0__Reg1_1
789
  { CVT_95_addImmOperands, 3, CVT_95_addImmOperands, 1, CVT_95_Reg, 2, CVT_Done },
790
  // Convert__Imm1_3__imm_95_0__Reg1_2
791
  { CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_95_Reg, 3, CVT_Done },
792
  // Convert__Imm1_3__Imm1_0__Reg1_2
793
  { CVT_95_addImmOperands, 4, CVT_95_addImmOperands, 1, CVT_95_Reg, 3, CVT_Done },
794
  // Convert__Imm1_4__Imm1_0__Reg1_3
795
  { CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 1, CVT_95_Reg, 4, CVT_Done },
796
  // Convert__Imm1_1__imm_95_9__Reg1_0
797
  { CVT_95_addImmOperands, 2, CVT_imm_95_9, 0, CVT_95_Reg, 1, CVT_Done },
798
  // Convert__Imm1_2__imm_95_9__Reg1_1
799
  { CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_95_Reg, 2, CVT_Done },
800
  // Convert__Imm1_3__imm_95_9__Reg1_2
801
  { CVT_95_addImmOperands, 4, CVT_imm_95_9, 0, CVT_95_Reg, 3, CVT_Done },
802
  // Convert__Imm1_1__imm_95_6__Reg1_0
803
  { CVT_95_addImmOperands, 2, CVT_imm_95_6, 0, CVT_95_Reg, 1, CVT_Done },
804
  // Convert__Imm1_2__imm_95_6__Reg1_1
805
  { CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_95_Reg, 2, CVT_Done },
806
  // Convert__Imm1_3__imm_95_6__Reg1_2
807
  { CVT_95_addImmOperands, 4, CVT_imm_95_6, 0, CVT_95_Reg, 3, CVT_Done },
808
  // Convert__Imm1_1__imm_95_11__Reg1_0
809
  { CVT_95_addImmOperands, 2, CVT_imm_95_11, 0, CVT_95_Reg, 1, CVT_Done },
810
  // Convert__Imm1_2__imm_95_11__Reg1_1
811
  { CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_95_Reg, 2, CVT_Done },
812
  // Convert__Imm1_3__imm_95_11__Reg1_2
813
  { CVT_95_addImmOperands, 4, CVT_imm_95_11, 0, CVT_95_Reg, 3, CVT_Done },
814
  // Convert__Imm1_1__imm_95_4__Reg1_0
815
  { CVT_95_addImmOperands, 2, CVT_imm_95_4, 0, CVT_95_Reg, 1, CVT_Done },
816
  // Convert__Imm1_2__imm_95_4__Reg1_1
817
  { CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_95_Reg, 2, CVT_Done },
818
  // Convert__Imm1_3__imm_95_4__Reg1_2
819
  { CVT_95_addImmOperands, 4, CVT_imm_95_4, 0, CVT_95_Reg, 3, CVT_Done },
820
  // Convert__Imm1_1__imm_95_13__Reg1_0
821
  { CVT_95_addImmOperands, 2, CVT_imm_95_13, 0, CVT_95_Reg, 1, CVT_Done },
822
  // Convert__Imm1_2__imm_95_13__Reg1_1
823
  { CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_95_Reg, 2, CVT_Done },
824
  // Convert__Imm1_3__imm_95_13__Reg1_2
825
  { CVT_95_addImmOperands, 4, CVT_imm_95_13, 0, CVT_95_Reg, 3, CVT_Done },
826
  // Convert__Imm1_1__imm_95_2__Reg1_0
827
  { CVT_95_addImmOperands, 2, CVT_imm_95_2, 0, CVT_95_Reg, 1, CVT_Done },
828
  // Convert__Imm1_2__imm_95_2__Reg1_1
829
  { CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_95_Reg, 2, CVT_Done },
830
  // Convert__Imm1_3__imm_95_2__Reg1_2
831
  { CVT_95_addImmOperands, 4, CVT_imm_95_2, 0, CVT_95_Reg, 3, CVT_Done },
832
  // Convert__Imm1_1__imm_95_8__Reg1_0
833
  { CVT_95_addImmOperands, 2, CVT_imm_95_8, 0, CVT_95_Reg, 1, CVT_Done },
834
  // Convert__Imm1_2__imm_95_8__Reg1_1
835
  { CVT_95_addImmOperands, 3, CVT_imm_95_8, 0, CVT_95_Reg, 2, CVT_Done },
836
  // Convert__Imm1_3__imm_95_8__Reg1_2
837
  { CVT_95_addImmOperands, 4, CVT_imm_95_8, 0, CVT_95_Reg, 3, CVT_Done },
838
  // Convert__Imm1_1__imm_95_1__Reg1_0
839
  { CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_95_Reg, 1, CVT_Done },
840
  // Convert__Imm1_2__imm_95_1__Reg1_1
841
  { CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_95_Reg, 2, CVT_Done },
842
  // Convert__Imm1_3__imm_95_1__Reg1_2
843
  { CVT_95_addImmOperands, 4, CVT_imm_95_1, 0, CVT_95_Reg, 3, CVT_Done },
844
  // Convert__Imm1_1__imm_95_15__Reg1_0
845
  { CVT_95_addImmOperands, 2, CVT_imm_95_15, 0, CVT_95_Reg, 1, CVT_Done },
846
  // Convert__Imm1_2__imm_95_15__Reg1_1
847
  { CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_95_Reg, 2, CVT_Done },
848
  // Convert__Imm1_3__imm_95_15__Reg1_2
849
  { CVT_95_addImmOperands, 4, CVT_imm_95_15, 0, CVT_95_Reg, 3, CVT_Done },
850
  // Convert__Imm1_1__imm_95_7__Reg1_0
851
  { CVT_95_addImmOperands, 2, CVT_imm_95_7, 0, CVT_95_Reg, 1, CVT_Done },
852
  // Convert__Imm1_2__imm_95_7__Reg1_1
853
  { CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_95_Reg, 2, CVT_Done },
854
  // Convert__Imm1_3__imm_95_7__Reg1_2
855
  { CVT_95_addImmOperands, 4, CVT_imm_95_7, 0, CVT_95_Reg, 3, CVT_Done },
856
  // Convert__Imm1_1__imm_95_10__Reg1_0
857
  { CVT_95_addImmOperands, 2, CVT_imm_95_10, 0, CVT_95_Reg, 1, CVT_Done },
858
  // Convert__Imm1_2__imm_95_10__Reg1_1
859
  { CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_95_Reg, 2, CVT_Done },
860
  // Convert__Imm1_3__imm_95_10__Reg1_2
861
  { CVT_95_addImmOperands, 4, CVT_imm_95_10, 0, CVT_95_Reg, 3, CVT_Done },
862
  // Convert__Imm1_1__imm_95_5__Reg1_0
863
  { CVT_95_addImmOperands, 2, CVT_imm_95_5, 0, CVT_95_Reg, 1, CVT_Done },
864
  // Convert__Imm1_2__imm_95_5__Reg1_1
865
  { CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_95_Reg, 2, CVT_Done },
866
  // Convert__Imm1_3__imm_95_5__Reg1_2
867
  { CVT_95_addImmOperands, 4, CVT_imm_95_5, 0, CVT_95_Reg, 3, CVT_Done },
868
  // Convert__Imm1_1__imm_95_12__Reg1_0
869
  { CVT_95_addImmOperands, 2, CVT_imm_95_12, 0, CVT_95_Reg, 1, CVT_Done },
870
  // Convert__Imm1_2__imm_95_12__Reg1_1
871
  { CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_95_Reg, 2, CVT_Done },
872
  // Convert__Imm1_3__imm_95_12__Reg1_2
873
  { CVT_95_addImmOperands, 4, CVT_imm_95_12, 0, CVT_95_Reg, 3, CVT_Done },
874
  // Convert__Imm1_1__imm_95_3__Reg1_0
875
  { CVT_95_addImmOperands, 2, CVT_imm_95_3, 0, CVT_95_Reg, 1, CVT_Done },
876
  // Convert__Imm1_2__imm_95_3__Reg1_1
877
  { CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_95_Reg, 2, CVT_Done },
878
  // Convert__Imm1_3__imm_95_3__Reg1_2
879
  { CVT_95_addImmOperands, 4, CVT_imm_95_3, 0, CVT_95_Reg, 3, CVT_Done },
880
  // Convert__Imm1_1__imm_95_14__Reg1_0
881
  { CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_95_Reg, 1, CVT_Done },
882
  // Convert__Imm1_2__imm_95_14__Reg1_1
883
  { CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_95_Reg, 2, CVT_Done },
884
  // Convert__Imm1_3__imm_95_14__Reg1_2
885
  { CVT_95_addImmOperands, 4, CVT_imm_95_14, 0, CVT_95_Reg, 3, CVT_Done },
886
  // Convert__regFCC0__Reg1_0__Reg1_1
887
  { CVT_regFCC0, 0, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done },
888
  // Convert__Reg1_0__Reg1_1__Reg1_2
889
  { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done },
890
  // Convert_NoOperands
891
  { CVT_Done },
892
  // Convert__MEMri2_0
893
  { CVT_95_addMEMriOperands, 1, CVT_Done },
894
  // Convert__MEMrr2_0
895
  { CVT_95_addMEMrrOperands, 1, CVT_Done },
896
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_8
897
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_8, 0, CVT_Done },
898
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_0
899
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_0, 0, CVT_Done },
900
  // Convert__Reg1_3__Reg1_2__Tie0__Imm1_0
901
  { CVT_95_Reg, 4, CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
902
  // Convert__Reg1_3__Reg1_1__Reg1_2__Tie0__Imm1_0
903
  { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
904
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_13
905
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_13, 0, CVT_Done },
906
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_5
907
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_5, 0, CVT_Done },
908
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_1
909
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_1, 0, CVT_Done },
910
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_9
911
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_9, 0, CVT_Done },
912
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_10
913
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_10, 0, CVT_Done },
914
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_6
915
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_6, 0, CVT_Done },
916
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_11
917
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_11, 0, CVT_Done },
918
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_11
919
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_11, 0, CVT_Done },
920
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_12
921
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_12, 0, CVT_Done },
922
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_3
923
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_3, 0, CVT_Done },
924
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_4
925
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_4, 0, CVT_Done },
926
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_2
927
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_2, 0, CVT_Done },
928
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_13
929
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_13, 0, CVT_Done },
930
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_4
931
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_4, 0, CVT_Done },
932
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_2
933
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_2, 0, CVT_Done },
934
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_0
935
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_0, 0, CVT_Done },
936
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_8
937
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_8, 0, CVT_Done },
938
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_9
939
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_9, 0, CVT_Done },
940
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_1
941
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_1, 0, CVT_Done },
942
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_6
943
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_6, 0, CVT_Done },
944
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_15
945
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_15, 0, CVT_Done },
946
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_14
947
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_14, 0, CVT_Done },
948
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_7
949
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_7, 0, CVT_Done },
950
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_10
951
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_10, 0, CVT_Done },
952
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_5
953
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_5, 0, CVT_Done },
954
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_12
955
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_12, 0, CVT_Done },
956
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_3
957
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_3, 0, CVT_Done },
958
  // Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_14
959
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_14, 0, CVT_Done },
960
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_15
961
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_15, 0, CVT_Done },
962
  // Convert__Reg1_2__Reg1_1__Tie0__imm_95_7
963
  { CVT_95_Reg, 3, CVT_95_Reg, 2, CVT_Tied, 0, CVT_imm_95_7, 0, CVT_Done },
964
  // Convert__Reg1_0__Tie0
965
  { CVT_95_Reg, 1, CVT_Tied, 0, CVT_Done },
966
  // Convert__regG0__MEMri2_0
967
  { CVT_regG0, 0, CVT_95_addMEMriOperands, 1, CVT_Done },
968
  // Convert__regG0__MEMrr2_0
969
  { CVT_regG0, 0, CVT_95_addMEMrrOperands, 1, CVT_Done },
970
  // Convert__Reg1_1__MEMri2_0
971
  { CVT_95_Reg, 2, CVT_95_addMEMriOperands, 1, CVT_Done },
972
  // Convert__Reg1_1__MEMrr2_0
973
  { CVT_95_Reg, 2, CVT_95_addMEMrrOperands, 1, CVT_Done },
974
  // Convert__MEMri2_1
975
  { CVT_95_addMEMriOperands, 2, CVT_Done },
976
  // Convert__Reg1_3__MEMri2_1
977
  { CVT_95_Reg, 4, CVT_95_addMEMriOperands, 2, CVT_Done },
978
  // Convert__MEMrr2_1
979
  { CVT_95_addMEMrrOperands, 2, CVT_Done },
980
  // Convert__Reg1_3__MEMrr2_1
981
  { CVT_95_Reg, 4, CVT_95_addMEMrrOperands, 2, CVT_Done },
982
  // Convert__Reg1_4__MEMrr2_1__Imm1_3
983
  { CVT_95_Reg, 5, CVT_95_addMEMrrOperands, 2, CVT_95_addImmOperands, 4, CVT_Done },
984
  // Convert__Reg1_1
985
  { CVT_95_Reg, 2, CVT_Done },
986
  // Convert__regG0__Reg1_0
987
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_Done },
988
  // Convert__Reg1_1__regG0__Reg1_0
989
  { CVT_95_Reg, 2, CVT_regG0, 0, CVT_95_Reg, 1, CVT_Done },
990
  // Convert__regG0__Imm1_0
991
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_Done },
992
  // Convert__Reg1_1__regG0__Imm1_0
993
  { CVT_95_Reg, 2, CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_Done },
994
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_8
995
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_8, 0, CVT_Done },
996
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_0
997
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_0, 0, CVT_Done },
998
  // Convert__Reg1_3__Imm1_2__Tie0__Imm1_0
999
  { CVT_95_Reg, 4, CVT_95_addImmOperands, 3, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
1000
  // Convert__Reg1_3__Reg1_1__Imm1_2__Tie0__Imm1_0
1001
  { CVT_95_Reg, 4, CVT_95_Reg, 2, CVT_95_addImmOperands, 3, CVT_Tied, 0, CVT_95_addImmOperands, 1, CVT_Done },
1002
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_13
1003
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_13, 0, CVT_Done },
1004
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_5
1005
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_5, 0, CVT_Done },
1006
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_1
1007
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_1, 0, CVT_Done },
1008
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_9
1009
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_9, 0, CVT_Done },
1010
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_10
1011
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_10, 0, CVT_Done },
1012
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_6
1013
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_6, 0, CVT_Done },
1014
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_11
1015
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_11, 0, CVT_Done },
1016
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_11
1017
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_11, 0, CVT_Done },
1018
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_12
1019
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_12, 0, CVT_Done },
1020
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_3
1021
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_3, 0, CVT_Done },
1022
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_4
1023
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_4, 0, CVT_Done },
1024
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_2
1025
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_2, 0, CVT_Done },
1026
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_13
1027
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_13, 0, CVT_Done },
1028
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_4
1029
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_4, 0, CVT_Done },
1030
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_2
1031
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_2, 0, CVT_Done },
1032
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_0
1033
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_0, 0, CVT_Done },
1034
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_8
1035
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_8, 0, CVT_Done },
1036
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_9
1037
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_9, 0, CVT_Done },
1038
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_1
1039
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_1, 0, CVT_Done },
1040
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_6
1041
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_6, 0, CVT_Done },
1042
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_15
1043
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_15, 0, CVT_Done },
1044
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_14
1045
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_14, 0, CVT_Done },
1046
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_7
1047
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_7, 0, CVT_Done },
1048
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_10
1049
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_10, 0, CVT_Done },
1050
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_5
1051
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_5, 0, CVT_Done },
1052
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_12
1053
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_12, 0, CVT_Done },
1054
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_3
1055
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_3, 0, CVT_Done },
1056
  // Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_14
1057
  { CVT_95_Reg, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_14, 0, CVT_Done },
1058
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_15
1059
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_15, 0, CVT_Done },
1060
  // Convert__Reg1_2__Imm1_1__Tie0__imm_95_7
1061
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 2, CVT_Tied, 0, CVT_imm_95_7, 0, CVT_Done },
1062
  // Convert__Reg1_0__regG0__Reg1_0
1063
  { CVT_95_Reg, 1, CVT_regG0, 0, CVT_95_Reg, 1, CVT_Done },
1064
  // Convert__Reg1_0__Reg1_0__regG0
1065
  { CVT_95_Reg, 1, CVT_95_Reg, 1, CVT_regG0, 0, CVT_Done },
1066
  // Convert__Reg1_1__Reg1_0__regG0
1067
  { CVT_95_Reg, 2, CVT_95_Reg, 1, CVT_regG0, 0, CVT_Done },
1068
  // Convert__regG0__regG0__regG0
1069
  { CVT_regG0, 0, CVT_regG0, 0, CVT_regG0, 0, CVT_Done },
1070
  // Convert__imm_95_8
1071
  { CVT_imm_95_8, 0, CVT_Done },
1072
  // Convert__Reg1_1__Imm1_0
1073
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 1, CVT_Done },
1074
  // Convert__MEMri2_2
1075
  { CVT_95_addMEMriOperands, 3, CVT_Done },
1076
  // Convert__MEMrr2_2
1077
  { CVT_95_addMEMrrOperands, 3, CVT_Done },
1078
  // Convert__MEMri2_2__Reg1_0
1079
  { CVT_95_addMEMriOperands, 3, CVT_95_Reg, 1, CVT_Done },
1080
  // Convert__MEMrr2_2__Reg1_0
1081
  { CVT_95_addMEMrrOperands, 3, CVT_95_Reg, 1, CVT_Done },
1082
  // Convert__MEMrr2_2__Reg1_0__Imm1_4
1083
  { CVT_95_addMEMrrOperands, 3, CVT_95_Reg, 1, CVT_95_addImmOperands, 5, CVT_Done },
1084
  // Convert__Reg1_3__MEMri2_1__Tie0
1085
  { CVT_95_Reg, 4, CVT_95_addMEMriOperands, 2, CVT_Tied, 0, CVT_Done },
1086
  // Convert__Reg1_3__MEMrr2_1__Tie0
1087
  { CVT_95_Reg, 4, CVT_95_addMEMrrOperands, 2, CVT_Tied, 0, CVT_Done },
1088
  // Convert__Reg1_4__MEMrr2_1__Imm1_3__Tie0
1089
  { CVT_95_Reg, 5, CVT_95_addMEMrrOperands, 2, CVT_95_addImmOperands, 4, CVT_Tied, 0, CVT_Done },
1090
  // Convert__regG0__Reg1_0__imm_95_8
1091
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_8, 0, CVT_Done },
1092
  // Convert__regG0__Imm1_0__imm_95_8
1093
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_8, 0, CVT_Done },
1094
  // Convert__regG0__Reg1_1__imm_95_8
1095
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_8, 0, CVT_Done },
1096
  // Convert__regG0__Imm1_1__imm_95_8
1097
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_8, 0, CVT_Done },
1098
  // Convert__Reg1_0__Reg1_2__imm_95_8
1099
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_8, 0, CVT_Done },
1100
  // Convert__Reg1_0__Imm1_2__imm_95_8
1101
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_8, 0, CVT_Done },
1102
  // Convert__Reg1_1__Reg1_3__imm_95_8
1103
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_8, 0, CVT_Done },
1104
  // Convert__Reg1_1__Imm1_3__imm_95_8
1105
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_8, 0, CVT_Done },
1106
  // Convert__Reg1_2__Reg1_4__Imm1_0
1107
  { CVT_95_Reg, 3, CVT_95_Reg, 5, CVT_95_addImmOperands, 1, CVT_Done },
1108
  // Convert__Reg1_2__Imm1_4__Imm1_0
1109
  { CVT_95_Reg, 3, CVT_95_addImmOperands, 5, CVT_95_addImmOperands, 1, CVT_Done },
1110
  // Convert__regG0__Reg1_0__imm_95_13
1111
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_13, 0, CVT_Done },
1112
  // Convert__regG0__Imm1_0__imm_95_13
1113
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_13, 0, CVT_Done },
1114
  // Convert__regG0__Reg1_1__imm_95_13
1115
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_13, 0, CVT_Done },
1116
  // Convert__regG0__Imm1_1__imm_95_13
1117
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_13, 0, CVT_Done },
1118
  // Convert__Reg1_0__Reg1_2__imm_95_13
1119
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_13, 0, CVT_Done },
1120
  // Convert__Reg1_0__Imm1_2__imm_95_13
1121
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_13, 0, CVT_Done },
1122
  // Convert__Reg1_1__Reg1_3__imm_95_13
1123
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_13, 0, CVT_Done },
1124
  // Convert__Reg1_1__Imm1_3__imm_95_13
1125
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_13, 0, CVT_Done },
1126
  // Convert__regG0__Reg1_0__imm_95_5
1127
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_5, 0, CVT_Done },
1128
  // Convert__regG0__Imm1_0__imm_95_5
1129
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_5, 0, CVT_Done },
1130
  // Convert__regG0__Reg1_1__imm_95_5
1131
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_5, 0, CVT_Done },
1132
  // Convert__regG0__Imm1_1__imm_95_5
1133
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_5, 0, CVT_Done },
1134
  // Convert__Reg1_0__Reg1_2__imm_95_5
1135
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_5, 0, CVT_Done },
1136
  // Convert__Reg1_0__Imm1_2__imm_95_5
1137
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_5, 0, CVT_Done },
1138
  // Convert__Reg1_1__Reg1_3__imm_95_5
1139
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_5, 0, CVT_Done },
1140
  // Convert__Reg1_1__Imm1_3__imm_95_5
1141
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_5, 0, CVT_Done },
1142
  // Convert__regG0__Reg1_0__imm_95_1
1143
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_1, 0, CVT_Done },
1144
  // Convert__regG0__Imm1_0__imm_95_1
1145
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_1, 0, CVT_Done },
1146
  // Convert__regG0__Reg1_1__imm_95_1
1147
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_1, 0, CVT_Done },
1148
  // Convert__regG0__Imm1_1__imm_95_1
1149
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_1, 0, CVT_Done },
1150
  // Convert__Reg1_0__Reg1_2__imm_95_1
1151
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_1, 0, CVT_Done },
1152
  // Convert__Reg1_0__Imm1_2__imm_95_1
1153
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_1, 0, CVT_Done },
1154
  // Convert__Reg1_1__Reg1_3__imm_95_1
1155
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_1, 0, CVT_Done },
1156
  // Convert__Reg1_1__Imm1_3__imm_95_1
1157
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_1, 0, CVT_Done },
1158
  // Convert__regG0__Reg1_0__imm_95_10
1159
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_10, 0, CVT_Done },
1160
  // Convert__regG0__Imm1_0__imm_95_10
1161
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_10, 0, CVT_Done },
1162
  // Convert__regG0__Reg1_1__imm_95_10
1163
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_10, 0, CVT_Done },
1164
  // Convert__regG0__Imm1_1__imm_95_10
1165
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_10, 0, CVT_Done },
1166
  // Convert__Reg1_0__Reg1_2__imm_95_10
1167
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_10, 0, CVT_Done },
1168
  // Convert__Reg1_0__Imm1_2__imm_95_10
1169
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_10, 0, CVT_Done },
1170
  // Convert__Reg1_1__Reg1_3__imm_95_10
1171
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_10, 0, CVT_Done },
1172
  // Convert__Reg1_1__Imm1_3__imm_95_10
1173
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_10, 0, CVT_Done },
1174
  // Convert__regG0__Reg1_0__imm_95_11
1175
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_11, 0, CVT_Done },
1176
  // Convert__regG0__Imm1_0__imm_95_11
1177
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_11, 0, CVT_Done },
1178
  // Convert__regG0__Reg1_1__imm_95_11
1179
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_11, 0, CVT_Done },
1180
  // Convert__regG0__Imm1_1__imm_95_11
1181
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_11, 0, CVT_Done },
1182
  // Convert__Reg1_0__Reg1_2__imm_95_11
1183
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_11, 0, CVT_Done },
1184
  // Convert__Reg1_0__Imm1_2__imm_95_11
1185
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_11, 0, CVT_Done },
1186
  // Convert__Reg1_1__Reg1_3__imm_95_11
1187
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_11, 0, CVT_Done },
1188
  // Convert__Reg1_1__Imm1_3__imm_95_11
1189
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_11, 0, CVT_Done },
1190
  // Convert__regG0__Reg1_0__imm_95_12
1191
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_12, 0, CVT_Done },
1192
  // Convert__regG0__Imm1_0__imm_95_12
1193
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_12, 0, CVT_Done },
1194
  // Convert__regG0__Reg1_1__imm_95_12
1195
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_12, 0, CVT_Done },
1196
  // Convert__regG0__Imm1_1__imm_95_12
1197
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_12, 0, CVT_Done },
1198
  // Convert__Reg1_0__Reg1_2__imm_95_12
1199
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_12, 0, CVT_Done },
1200
  // Convert__Reg1_0__Imm1_2__imm_95_12
1201
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_12, 0, CVT_Done },
1202
  // Convert__Reg1_1__Reg1_3__imm_95_12
1203
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_12, 0, CVT_Done },
1204
  // Convert__Reg1_1__Imm1_3__imm_95_12
1205
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_12, 0, CVT_Done },
1206
  // Convert__regG0__Reg1_0__imm_95_3
1207
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_3, 0, CVT_Done },
1208
  // Convert__regG0__Imm1_0__imm_95_3
1209
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_3, 0, CVT_Done },
1210
  // Convert__regG0__Reg1_1__imm_95_3
1211
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_3, 0, CVT_Done },
1212
  // Convert__regG0__Imm1_1__imm_95_3
1213
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_3, 0, CVT_Done },
1214
  // Convert__Reg1_0__Reg1_2__imm_95_3
1215
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_3, 0, CVT_Done },
1216
  // Convert__Reg1_0__Imm1_2__imm_95_3
1217
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_3, 0, CVT_Done },
1218
  // Convert__Reg1_1__Reg1_3__imm_95_3
1219
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_3, 0, CVT_Done },
1220
  // Convert__Reg1_1__Imm1_3__imm_95_3
1221
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_3, 0, CVT_Done },
1222
  // Convert__regG0__Reg1_0__imm_95_2
1223
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_2, 0, CVT_Done },
1224
  // Convert__regG0__Imm1_0__imm_95_2
1225
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_2, 0, CVT_Done },
1226
  // Convert__regG0__Reg1_1__imm_95_2
1227
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_2, 0, CVT_Done },
1228
  // Convert__regG0__Imm1_1__imm_95_2
1229
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_2, 0, CVT_Done },
1230
  // Convert__Reg1_0__Reg1_2__imm_95_2
1231
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_2, 0, CVT_Done },
1232
  // Convert__Reg1_0__Imm1_2__imm_95_2
1233
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_2, 0, CVT_Done },
1234
  // Convert__Reg1_1__Reg1_3__imm_95_2
1235
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_2, 0, CVT_Done },
1236
  // Convert__Reg1_1__Imm1_3__imm_95_2
1237
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_2, 0, CVT_Done },
1238
  // Convert__regG0__Reg1_0__imm_95_4
1239
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_4, 0, CVT_Done },
1240
  // Convert__regG0__Imm1_0__imm_95_4
1241
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_4, 0, CVT_Done },
1242
  // Convert__regG0__Reg1_1__imm_95_4
1243
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_4, 0, CVT_Done },
1244
  // Convert__regG0__Imm1_1__imm_95_4
1245
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_4, 0, CVT_Done },
1246
  // Convert__Reg1_0__Reg1_2__imm_95_4
1247
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_4, 0, CVT_Done },
1248
  // Convert__Reg1_0__Imm1_2__imm_95_4
1249
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_4, 0, CVT_Done },
1250
  // Convert__Reg1_1__Reg1_3__imm_95_4
1251
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_4, 0, CVT_Done },
1252
  // Convert__Reg1_1__Imm1_3__imm_95_4
1253
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_4, 0, CVT_Done },
1254
  // Convert__regG0__Reg1_0__imm_95_0
1255
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_0, 0, CVT_Done },
1256
  // Convert__regG0__Imm1_0__imm_95_0
1257
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_0, 0, CVT_Done },
1258
  // Convert__regG0__Reg1_1__imm_95_0
1259
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_0, 0, CVT_Done },
1260
  // Convert__regG0__Imm1_1__imm_95_0
1261
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done },
1262
  // Convert__Reg1_0__Reg1_2__imm_95_0
1263
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_0, 0, CVT_Done },
1264
  // Convert__Reg1_0__Imm1_2__imm_95_0
1265
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_0, 0, CVT_Done },
1266
  // Convert__Reg1_1__Reg1_3__imm_95_0
1267
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_0, 0, CVT_Done },
1268
  // Convert__Reg1_1__Imm1_3__imm_95_0
1269
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_0, 0, CVT_Done },
1270
  // Convert__regG0__Reg1_0__imm_95_9
1271
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_9, 0, CVT_Done },
1272
  // Convert__regG0__Imm1_0__imm_95_9
1273
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_9, 0, CVT_Done },
1274
  // Convert__regG0__Reg1_1__imm_95_9
1275
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_9, 0, CVT_Done },
1276
  // Convert__regG0__Imm1_1__imm_95_9
1277
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_9, 0, CVT_Done },
1278
  // Convert__Reg1_0__Reg1_2__imm_95_9
1279
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_9, 0, CVT_Done },
1280
  // Convert__Reg1_0__Imm1_2__imm_95_9
1281
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_9, 0, CVT_Done },
1282
  // Convert__Reg1_1__Reg1_3__imm_95_9
1283
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_9, 0, CVT_Done },
1284
  // Convert__Reg1_1__Imm1_3__imm_95_9
1285
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_9, 0, CVT_Done },
1286
  // Convert__regG0__Reg1_0__imm_95_6
1287
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_6, 0, CVT_Done },
1288
  // Convert__regG0__Imm1_0__imm_95_6
1289
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_6, 0, CVT_Done },
1290
  // Convert__regG0__Reg1_1__imm_95_6
1291
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_6, 0, CVT_Done },
1292
  // Convert__regG0__Imm1_1__imm_95_6
1293
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_6, 0, CVT_Done },
1294
  // Convert__Reg1_0__Reg1_2__imm_95_6
1295
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_6, 0, CVT_Done },
1296
  // Convert__Reg1_0__Imm1_2__imm_95_6
1297
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_6, 0, CVT_Done },
1298
  // Convert__Reg1_1__Reg1_3__imm_95_6
1299
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_6, 0, CVT_Done },
1300
  // Convert__Reg1_1__Imm1_3__imm_95_6
1301
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_6, 0, CVT_Done },
1302
  // Convert__regG0__Reg1_0__imm_95_14
1303
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_14, 0, CVT_Done },
1304
  // Convert__regG0__Imm1_0__imm_95_14
1305
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_14, 0, CVT_Done },
1306
  // Convert__regG0__Reg1_1__imm_95_14
1307
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_14, 0, CVT_Done },
1308
  // Convert__regG0__Imm1_1__imm_95_14
1309
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_14, 0, CVT_Done },
1310
  // Convert__Reg1_0__Reg1_2__imm_95_14
1311
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_14, 0, CVT_Done },
1312
  // Convert__Reg1_0__Imm1_2__imm_95_14
1313
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_14, 0, CVT_Done },
1314
  // Convert__Reg1_1__Reg1_3__imm_95_14
1315
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_14, 0, CVT_Done },
1316
  // Convert__Reg1_1__Imm1_3__imm_95_14
1317
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_14, 0, CVT_Done },
1318
  // Convert__regG0__Reg1_0__regG0
1319
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_regG0, 0, CVT_Done },
1320
  // Convert__regG0__Reg1_0__imm_95_15
1321
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_15, 0, CVT_Done },
1322
  // Convert__regG0__Imm1_0__imm_95_15
1323
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_15, 0, CVT_Done },
1324
  // Convert__regG0__Reg1_1__imm_95_15
1325
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_15, 0, CVT_Done },
1326
  // Convert__regG0__Imm1_1__imm_95_15
1327
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_15, 0, CVT_Done },
1328
  // Convert__Reg1_0__Reg1_2__imm_95_15
1329
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_15, 0, CVT_Done },
1330
  // Convert__Reg1_0__Imm1_2__imm_95_15
1331
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_15, 0, CVT_Done },
1332
  // Convert__Reg1_1__Reg1_3__imm_95_15
1333
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_15, 0, CVT_Done },
1334
  // Convert__Reg1_1__Imm1_3__imm_95_15
1335
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_15, 0, CVT_Done },
1336
  // Convert__regG0__Reg1_0__imm_95_7
1337
  { CVT_regG0, 0, CVT_95_Reg, 1, CVT_imm_95_7, 0, CVT_Done },
1338
  // Convert__regG0__Imm1_0__imm_95_7
1339
  { CVT_regG0, 0, CVT_95_addImmOperands, 1, CVT_imm_95_7, 0, CVT_Done },
1340
  // Convert__regG0__Reg1_1__imm_95_7
1341
  { CVT_regG0, 0, CVT_95_Reg, 2, CVT_imm_95_7, 0, CVT_Done },
1342
  // Convert__regG0__Imm1_1__imm_95_7
1343
  { CVT_regG0, 0, CVT_95_addImmOperands, 2, CVT_imm_95_7, 0, CVT_Done },
1344
  // Convert__Reg1_0__Reg1_2__imm_95_7
1345
  { CVT_95_Reg, 1, CVT_95_Reg, 3, CVT_imm_95_7, 0, CVT_Done },
1346
  // Convert__Reg1_0__Imm1_2__imm_95_7
1347
  { CVT_95_Reg, 1, CVT_95_addImmOperands, 3, CVT_imm_95_7, 0, CVT_Done },
1348
  // Convert__Reg1_1__Reg1_3__imm_95_7
1349
  { CVT_95_Reg, 2, CVT_95_Reg, 4, CVT_imm_95_7, 0, CVT_Done },
1350
  // Convert__Reg1_1__Imm1_3__imm_95_7
1351
  { CVT_95_Reg, 2, CVT_95_addImmOperands, 4, CVT_imm_95_7, 0, CVT_Done },
1352
};
1353
1354
void SparcAsmParser::
1355
convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode,
1356
2.73k
                const OperandVector &Operands) {
1357
2.73k
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1358
2.73k
  const uint8_t *Converter = ConversionTable[Kind];
1359
2.73k
  Inst.setOpcode(Opcode);
1360
8.13k
  for (const uint8_t *p = Converter; *p; p+= 2) {
1361
5.39k
    switch (*p) {
1362
0
    default: llvm_unreachable("invalid conversion entry!");
1363
0
    case CVT_Reg:
1364
0
      static_cast<SparcOperand&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);
1365
0
      break;
1366
0
    case CVT_Tied:
1367
0
      Inst.addOperand(Inst.getOperand(*(p + 1)));
1368
0
      break;
1369
6
    case CVT_95_Reg:
1370
6
      static_cast<SparcOperand&>(*Operands[*(p + 1)]).addRegOperands(Inst, 1);
1371
6
      break;
1372
2.06k
    case CVT_95_addImmOperands:
1373
2.06k
      static_cast<SparcOperand&>(*Operands[*(p + 1)]).addImmOperands(Inst, 1);
1374
2.06k
      break;
1375
999
    case CVT_imm_95_8:
1376
999
      Inst.addOperand(MCOperand::createImm(8));
1377
999
      break;
1378
20
    case CVT_imm_95_13:
1379
20
      Inst.addOperand(MCOperand::createImm(13));
1380
20
      break;
1381
205
    case CVT_imm_95_5:
1382
205
      Inst.addOperand(MCOperand::createImm(5));
1383
205
      break;
1384
68
    case CVT_imm_95_1:
1385
68
      Inst.addOperand(MCOperand::createImm(1));
1386
68
      break;
1387
37
    case CVT_imm_95_10:
1388
37
      Inst.addOperand(MCOperand::createImm(10));
1389
37
      break;
1390
1
    case CVT_imm_95_11:
1391
1
      Inst.addOperand(MCOperand::createImm(11));
1392
1
      break;
1393
0
    case CVT_imm_95_12:
1394
0
      Inst.addOperand(MCOperand::createImm(12));
1395
0
      break;
1396
465
    case CVT_imm_95_3:
1397
465
      Inst.addOperand(MCOperand::createImm(3));
1398
465
      break;
1399
38
    case CVT_imm_95_2:
1400
38
      Inst.addOperand(MCOperand::createImm(2));
1401
38
      break;
1402
1
    case CVT_imm_95_4:
1403
1
      Inst.addOperand(MCOperand::createImm(4));
1404
1
      break;
1405
3
    case CVT_imm_95_0:
1406
3
      Inst.addOperand(MCOperand::createImm(0));
1407
3
      break;
1408
16
    case CVT_imm_95_9:
1409
16
      Inst.addOperand(MCOperand::createImm(9));
1410
16
      break;
1411
9
    case CVT_imm_95_6:
1412
9
      Inst.addOperand(MCOperand::createImm(6));
1413
9
      break;
1414
2
    case CVT_imm_95_14:
1415
2
      Inst.addOperand(MCOperand::createImm(14));
1416
2
      break;
1417
796
    case CVT_regG0:
1418
796
      Inst.addOperand(MCOperand::createReg(SP::G0));
1419
796
      break;
1420
139
    case CVT_imm_95_15:
1421
139
      Inst.addOperand(MCOperand::createImm(15));
1422
139
      break;
1423
26
    case CVT_imm_95_7:
1424
26
      Inst.addOperand(MCOperand::createImm(7));
1425
26
      break;
1426
20
    case CVT_regO7:
1427
20
      Inst.addOperand(MCOperand::createReg(SP::O7));
1428
20
      break;
1429
25
    case CVT_95_addMEMriOperands:
1430
25
      static_cast<SparcOperand&>(*Operands[*(p + 1)]).addMEMriOperands(Inst, 2);
1431
25
      break;
1432
461
    case CVT_95_addMEMrrOperands:
1433
461
      static_cast<SparcOperand&>(*Operands[*(p + 1)]).addMEMrrOperands(Inst, 2);
1434
461
      break;
1435
0
    case CVT_regFCC0:
1436
0
      Inst.addOperand(MCOperand::createReg(SP::FCC0));
1437
0
      break;
1438
5.39k
    }
1439
5.39k
  }
1440
2.73k
}
1441
1442
void SparcAsmParser::
1443
convertToMapAndConstraints(unsigned Kind,
1444
0
                           const OperandVector &Operands) {
1445
0
  assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!");
1446
0
  unsigned NumMCOperands = 0;
1447
0
  const uint8_t *Converter = ConversionTable[Kind];
1448
0
  for (const uint8_t *p = Converter; *p; p+= 2) {
1449
0
    switch (*p) {
1450
0
    default: llvm_unreachable("invalid conversion entry!");
1451
0
    case CVT_Reg:
1452
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1453
0
      Operands[*(p + 1)]->setConstraint("r");
1454
0
      ++NumMCOperands;
1455
0
      break;
1456
0
    case CVT_Tied:
1457
0
      ++NumMCOperands;
1458
0
      break;
1459
0
    case CVT_95_Reg:
1460
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1461
0
      Operands[*(p + 1)]->setConstraint("r");
1462
0
      NumMCOperands += 1;
1463
0
      break;
1464
0
    case CVT_95_addImmOperands:
1465
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1466
0
      Operands[*(p + 1)]->setConstraint("m");
1467
0
      NumMCOperands += 1;
1468
0
      break;
1469
0
    case CVT_imm_95_8:
1470
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1471
0
      Operands[*(p + 1)]->setConstraint("");
1472
0
      ++NumMCOperands;
1473
0
      break;
1474
0
    case CVT_imm_95_13:
1475
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1476
0
      Operands[*(p + 1)]->setConstraint("");
1477
0
      ++NumMCOperands;
1478
0
      break;
1479
0
    case CVT_imm_95_5:
1480
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1481
0
      Operands[*(p + 1)]->setConstraint("");
1482
0
      ++NumMCOperands;
1483
0
      break;
1484
0
    case CVT_imm_95_1:
1485
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1486
0
      Operands[*(p + 1)]->setConstraint("");
1487
0
      ++NumMCOperands;
1488
0
      break;
1489
0
    case CVT_imm_95_10:
1490
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1491
0
      Operands[*(p + 1)]->setConstraint("");
1492
0
      ++NumMCOperands;
1493
0
      break;
1494
0
    case CVT_imm_95_11:
1495
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1496
0
      Operands[*(p + 1)]->setConstraint("");
1497
0
      ++NumMCOperands;
1498
0
      break;
1499
0
    case CVT_imm_95_12:
1500
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1501
0
      Operands[*(p + 1)]->setConstraint("");
1502
0
      ++NumMCOperands;
1503
0
      break;
1504
0
    case CVT_imm_95_3:
1505
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1506
0
      Operands[*(p + 1)]->setConstraint("");
1507
0
      ++NumMCOperands;
1508
0
      break;
1509
0
    case CVT_imm_95_2:
1510
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1511
0
      Operands[*(p + 1)]->setConstraint("");
1512
0
      ++NumMCOperands;
1513
0
      break;
1514
0
    case CVT_imm_95_4:
1515
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1516
0
      Operands[*(p + 1)]->setConstraint("");
1517
0
      ++NumMCOperands;
1518
0
      break;
1519
0
    case CVT_imm_95_0:
1520
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1521
0
      Operands[*(p + 1)]->setConstraint("");
1522
0
      ++NumMCOperands;
1523
0
      break;
1524
0
    case CVT_imm_95_9:
1525
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1526
0
      Operands[*(p + 1)]->setConstraint("");
1527
0
      ++NumMCOperands;
1528
0
      break;
1529
0
    case CVT_imm_95_6:
1530
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1531
0
      Operands[*(p + 1)]->setConstraint("");
1532
0
      ++NumMCOperands;
1533
0
      break;
1534
0
    case CVT_imm_95_14:
1535
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1536
0
      Operands[*(p + 1)]->setConstraint("");
1537
0
      ++NumMCOperands;
1538
0
      break;
1539
0
    case CVT_regG0:
1540
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1541
0
      Operands[*(p + 1)]->setConstraint("m");
1542
0
      ++NumMCOperands;
1543
0
      break;
1544
0
    case CVT_imm_95_15:
1545
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1546
0
      Operands[*(p + 1)]->setConstraint("");
1547
0
      ++NumMCOperands;
1548
0
      break;
1549
0
    case CVT_imm_95_7:
1550
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1551
0
      Operands[*(p + 1)]->setConstraint("");
1552
0
      ++NumMCOperands;
1553
0
      break;
1554
0
    case CVT_regO7:
1555
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1556
0
      Operands[*(p + 1)]->setConstraint("m");
1557
0
      ++NumMCOperands;
1558
0
      break;
1559
0
    case CVT_95_addMEMriOperands:
1560
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1561
0
      Operands[*(p + 1)]->setConstraint("m");
1562
0
      NumMCOperands += 2;
1563
0
      break;
1564
0
    case CVT_95_addMEMrrOperands:
1565
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1566
0
      Operands[*(p + 1)]->setConstraint("m");
1567
0
      NumMCOperands += 2;
1568
0
      break;
1569
0
    case CVT_regFCC0:
1570
0
      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);
1571
0
      Operands[*(p + 1)]->setConstraint("m");
1572
0
      ++NumMCOperands;
1573
0
      break;
1574
0
    }
1575
0
  }
1576
0
}
1577
1578
namespace {
1579
1580
/// MatchClassKind - The kinds of classes which participate in
1581
/// instruction matching.
1582
enum MatchClassKind {
1583
  InvalidMatchClass = 0,
1584
  MCK__PCT_fcc0, // '%fcc0'
1585
  MCK__PCT_fsr, // '%fsr'
1586
  MCK__PCT_g0, // '%g0'
1587
  MCK__PCT_icc, // '%icc'
1588
  MCK__PCT_psr, // '%psr'
1589
  MCK__PCT_tbr, // '%tbr'
1590
  MCK__PCT_wim, // '%wim'
1591
  MCK__PCT_xcc, // '%xcc'
1592
  MCK__43_, // '+'
1593
  MCK_3, // '3'
1594
  MCK_5, // '5'
1595
  MCK__91_, // '['
1596
  MCK__93_, // ']'
1597
  MCK_a, // 'a'
1598
  MCK_pn, // 'pn'
1599
  MCK_pt, // 'pt'
1600
  MCK_FCCRegs, // register class 'FCCRegs'
1601
  MCK_Reg7, // derived register class
1602
  MCK_PRRegs, // register class 'PRRegs'
1603
  MCK_Reg5, // derived register class
1604
  MCK_IntPair, // register class 'IntPair'
1605
  MCK_QFPRegs, // register class 'QFPRegs'
1606
  MCK_ASRRegs, // register class 'ASRRegs'
1607
  MCK_DFPRegs, // register class 'DFPRegs'
1608
  MCK_FPRegs, // register class 'FPRegs'
1609
  MCK_IntRegs, // register class 'IntRegs,I64Regs'
1610
  MCK_Imm, // user defined class 'ImmAsmOperand'
1611
  MCK_MEMri, // user defined class 'SparcMEMriAsmOperand'
1612
  MCK_MEMrr, // user defined class 'SparcMEMrrAsmOperand'
1613
  NumMatchClassKinds
1614
};
1615
1616
}
1617
1618
383
static MatchClassKind matchTokenString(StringRef Name) {
1619
383
  switch (Name.size()) {
1620
0
  default: break;
1621
181
  case 1:  // 6 strings to match.
1622
181
    switch (Name[0]) {
1623
0
    default: break;
1624
0
    case '+':  // 1 string to match.
1625
0
      return MCK__43_;  // "+"
1626
0
    case '3':  // 1 string to match.
1627
0
      return MCK_3;  // "3"
1628
0
    case '5':  // 1 string to match.
1629
0
      return MCK_5;  // "5"
1630
49
    case '[':  // 1 string to match.
1631
49
      return MCK__91_;  // "["
1632
6
    case ']':  // 1 string to match.
1633
6
      return MCK__93_;  // "]"
1634
126
    case 'a':  // 1 string to match.
1635
126
      return MCK_a;  // "a"
1636
181
    }
1637
0
    break;
1638
24
  case 2:  // 2 strings to match.
1639
24
    if (Name[0] != 'p')
1640
0
      break;
1641
24
    switch (Name[1]) {
1642
0
    default: break;
1643
24
    case 'n':  // 1 string to match.
1644
24
      return MCK_pn;  // "pn"
1645
0
    case 't':  // 1 string to match.
1646
0
      return MCK_pt;  // "pt"
1647
24
    }
1648
0
    break;
1649
0
  case 3:  // 1 string to match.
1650
0
    if (memcmp(Name.data()+0, "%g0", 3))
1651
0
      break;
1652
0
    return MCK__PCT_g0;  // "%g0"
1653
178
  case 4:  // 6 strings to match.
1654
178
    if (Name[0] != '%')
1655
0
      break;
1656
178
    switch (Name[1]) {
1657
0
    default: break;
1658
38
    case 'f':  // 1 string to match.
1659
38
      if (memcmp(Name.data()+2, "sr", 2))
1660
0
        break;
1661
38
      return MCK__PCT_fsr;   // "%fsr"
1662
44
    case 'i':  // 1 string to match.
1663
44
      if (memcmp(Name.data()+2, "cc", 2))
1664
0
        break;
1665
44
      return MCK__PCT_icc;   // "%icc"
1666
38
    case 'p':  // 1 string to match.
1667
38
      if (memcmp(Name.data()+2, "sr", 2))
1668
0
        break;
1669
38
      return MCK__PCT_psr;   // "%psr"
1670
14
    case 't':  // 1 string to match.
1671
14
      if (memcmp(Name.data()+2, "br", 2))
1672
0
        break;
1673
14
      return MCK__PCT_tbr;   // "%tbr"
1674
0
    case 'w':  // 1 string to match.
1675
0
      if (memcmp(Name.data()+2, "im", 2))
1676
0
        break;
1677
0
      return MCK__PCT_wim;  // "%wim"
1678
44
    case 'x':  // 1 string to match.
1679
44
      if (memcmp(Name.data()+2, "cc", 2))
1680
0
        break;
1681
44
      return MCK__PCT_xcc;  // "%xcc"
1682
178
    }
1683
0
    break;
1684
0
  case 5:  // 1 string to match.
1685
0
    if (memcmp(Name.data()+0, "%fcc0", 5))
1686
0
      break;
1687
0
    return MCK__PCT_fcc0;  // "%fcc0"
1688
383
  }
1689
0
  return InvalidMatchClass;
1690
383
}
1691
1692
/// isSubclass - Compute whether \p A is a subclass of \p B.
1693
1.29k
static bool isSubclass(MatchClassKind A, MatchClassKind B) {
1694
1.29k
  if (A == B)
1695
67
    return true;
1696
1697
1.23k
  switch (A) {
1698
1.22k
  default:
1699
1.22k
    return false;
1700
1701
4
  case MCK_Reg7:
1702
4
    return B == MCK_QFPRegs;
1703
1704
3
  case MCK_Reg5:
1705
3
    return B == MCK_DFPRegs;
1706
1.23k
  }
1707
1.23k
}
1708
1709
5.68k
static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) {
1710
5.68k
  SparcOperand &Operand = (SparcOperand&)GOp;
1711
5.68k
  if (Kind == InvalidMatchClass)
1712
16
    return MCTargetAsmParser::Match_InvalidOperand;
1713
1714
5.67k
  if (Operand.isToken())
1715
383
    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?
1716
41
             MCTargetAsmParser::Match_Success :
1717
383
             MCTargetAsmParser::Match_InvalidOperand;
1718
1719
  // 'Imm' class
1720
5.28k
  if (Kind == MCK_Imm) {
1721
2.46k
    if (Operand.isImm())
1722
2.10k
      return MCTargetAsmParser::Match_Success;
1723
2.46k
  }
1724
1725
  // 'MEMri' class
1726
3.18k
  if (Kind == MCK_MEMri) {
1727
953
    if (Operand.isMEMri())
1728
25
      return MCTargetAsmParser::Match_Success;
1729
953
  }
1730
1731
  // 'MEMrr' class
1732
3.15k
  if (Kind == MCK_MEMrr) {
1733
928
    if (Operand.isMEMrr())
1734
467
      return MCTargetAsmParser::Match_Success;
1735
928
  }
1736
1737
2.69k
  if (Operand.isReg()) {
1738
914
    MatchClassKind OpKind;
1739
914
    switch (Operand.getReg()) {
1740
0
    default: OpKind = InvalidMatchClass; break;
1741
0
    case Sparc::FCC0: OpKind = MCK_FCCRegs; break;
1742
0
    case Sparc::FCC1: OpKind = MCK_FCCRegs; break;
1743
0
    case Sparc::FCC2: OpKind = MCK_FCCRegs; break;
1744
0
    case Sparc::FCC3: OpKind = MCK_FCCRegs; break;
1745
39
    case Sparc::Y: OpKind = MCK_ASRRegs; break;
1746
0
    case Sparc::ASR1: OpKind = MCK_ASRRegs; break;
1747
0
    case Sparc::ASR2: OpKind = MCK_ASRRegs; break;
1748
0
    case Sparc::ASR3: OpKind = MCK_ASRRegs; break;
1749
0
    case Sparc::ASR4: OpKind = MCK_ASRRegs; break;
1750
0
    case Sparc::ASR5: OpKind = MCK_ASRRegs; break;
1751
0
    case Sparc::ASR6: OpKind = MCK_ASRRegs; break;
1752
0
    case Sparc::ASR7: OpKind = MCK_ASRRegs; break;
1753
0
    case Sparc::ASR8: OpKind = MCK_ASRRegs; break;
1754
0
    case Sparc::ASR9: OpKind = MCK_ASRRegs; break;
1755
0
    case Sparc::ASR10: OpKind = MCK_ASRRegs; break;
1756
0
    case Sparc::ASR11: OpKind = MCK_ASRRegs; break;
1757
0
    case Sparc::ASR12: OpKind = MCK_ASRRegs; break;
1758
0
    case Sparc::ASR13: OpKind = MCK_ASRRegs; break;
1759
0
    case Sparc::ASR14: OpKind = MCK_ASRRegs; break;
1760
0
    case Sparc::ASR15: OpKind = MCK_ASRRegs; break;
1761
0
    case Sparc::ASR16: OpKind = MCK_ASRRegs; break;
1762
0
    case Sparc::ASR17: OpKind = MCK_ASRRegs; break;
1763
0
    case Sparc::ASR18: OpKind = MCK_ASRRegs; break;
1764
0
    case Sparc::ASR19: OpKind = MCK_ASRRegs; break;
1765
0
    case Sparc::ASR20: OpKind = MCK_ASRRegs; break;
1766
0
    case Sparc::ASR21: OpKind = MCK_ASRRegs; break;
1767
0
    case Sparc::ASR22: OpKind = MCK_ASRRegs; break;
1768
0
    case Sparc::ASR23: OpKind = MCK_ASRRegs; break;
1769
0
    case Sparc::ASR24: OpKind = MCK_ASRRegs; break;
1770
0
    case Sparc::ASR25: OpKind = MCK_ASRRegs; break;
1771
0
    case Sparc::ASR26: OpKind = MCK_ASRRegs; break;
1772
0
    case Sparc::ASR27: OpKind = MCK_ASRRegs; break;
1773
0
    case Sparc::ASR28: OpKind = MCK_ASRRegs; break;
1774
0
    case Sparc::ASR29: OpKind = MCK_ASRRegs; break;
1775
0
    case Sparc::ASR30: OpKind = MCK_ASRRegs; break;
1776
0
    case Sparc::ASR31: OpKind = MCK_ASRRegs; break;
1777
0
    case Sparc::TPC: OpKind = MCK_PRRegs; break;
1778
0
    case Sparc::TNPC: OpKind = MCK_PRRegs; break;
1779
0
    case Sparc::TSTATE: OpKind = MCK_PRRegs; break;
1780
16
    case Sparc::TT: OpKind = MCK_PRRegs; break;
1781
0
    case Sparc::TICK: OpKind = MCK_PRRegs; break;
1782
0
    case Sparc::TBA: OpKind = MCK_PRRegs; break;
1783
0
    case Sparc::PSTATE: OpKind = MCK_PRRegs; break;
1784
24
    case Sparc::TL: OpKind = MCK_PRRegs; break;
1785
0
    case Sparc::PIL: OpKind = MCK_PRRegs; break;
1786
0
    case Sparc::CWP: OpKind = MCK_PRRegs; break;
1787
0
    case Sparc::CANSAVE: OpKind = MCK_PRRegs; break;
1788
0
    case Sparc::CANRESTORE: OpKind = MCK_PRRegs; break;
1789
0
    case Sparc::CLEANWIN: OpKind = MCK_PRRegs; break;
1790
0
    case Sparc::OTHERWIN: OpKind = MCK_PRRegs; break;
1791
0
    case Sparc::WSTATE: OpKind = MCK_PRRegs; break;
1792
28
    case Sparc::G0: OpKind = MCK_IntRegs; break;
1793
24
    case Sparc::G1: OpKind = MCK_IntRegs; break;
1794
1
    case Sparc::G2: OpKind = MCK_IntRegs; break;
1795
1
    case Sparc::G3: OpKind = MCK_IntRegs; break;
1796
0
    case Sparc::G4: OpKind = MCK_IntRegs; break;
1797
0
    case Sparc::G5: OpKind = MCK_IntRegs; break;
1798
25
    case Sparc::G6: OpKind = MCK_IntRegs; break;
1799
26
    case Sparc::G7: OpKind = MCK_IntRegs; break;
1800
1
    case Sparc::O0: OpKind = MCK_IntRegs; break;
1801
0
    case Sparc::O1: OpKind = MCK_IntRegs; break;
1802
3
    case Sparc::O2: OpKind = MCK_IntRegs; break;
1803
0
    case Sparc::O3: OpKind = MCK_IntRegs; break;
1804
2
    case Sparc::O4: OpKind = MCK_IntRegs; break;
1805
24
    case Sparc::O5: OpKind = MCK_IntRegs; break;
1806
1
    case Sparc::O6: OpKind = MCK_IntRegs; break;
1807
0
    case Sparc::O7: OpKind = MCK_IntRegs; break;
1808
24
    case Sparc::L0: OpKind = MCK_IntRegs; break;
1809
24
    case Sparc::L1: OpKind = MCK_IntRegs; break;
1810
24
    case Sparc::L2: OpKind = MCK_IntRegs; break;
1811
1
    case Sparc::L3: OpKind = MCK_IntRegs; break;
1812
0
    case Sparc::L4: OpKind = MCK_IntRegs; break;
1813
0
    case Sparc::L5: OpKind = MCK_IntRegs; break;
1814
2
    case Sparc::L6: OpKind = MCK_IntRegs; break;
1815
1
    case Sparc::L7: OpKind = MCK_IntRegs; break;
1816
41
    case Sparc::I0: OpKind = MCK_IntRegs; break;
1817
24
    case Sparc::I1: OpKind = MCK_IntRegs; break;
1818
0
    case Sparc::I2: OpKind = MCK_IntRegs; break;
1819
4
    case Sparc::I3: OpKind = MCK_IntRegs; break;
1820
1
    case Sparc::I4: OpKind = MCK_IntRegs; break;
1821
5
    case Sparc::I5: OpKind = MCK_IntRegs; break;
1822
31
    case Sparc::I6: OpKind = MCK_IntRegs; break;
1823
28
    case Sparc::I7: OpKind = MCK_IntRegs; break;
1824
25
    case Sparc::F0: OpKind = MCK_FPRegs; break;
1825
24
    case Sparc::F1: OpKind = MCK_FPRegs; break;
1826
0
    case Sparc::F2: OpKind = MCK_FPRegs; break;
1827
22
    case Sparc::F3: OpKind = MCK_FPRegs; break;
1828
2
    case Sparc::F4: OpKind = MCK_FPRegs; break;
1829
0
    case Sparc::F5: OpKind = MCK_FPRegs; break;
1830
5
    case Sparc::F6: OpKind = MCK_FPRegs; break;
1831
24
    case Sparc::F7: OpKind = MCK_FPRegs; break;
1832
37
    case Sparc::F8: OpKind = MCK_FPRegs; break;
1833
24
    case Sparc::F9: OpKind = MCK_FPRegs; break;
1834
0
    case Sparc::F10: OpKind = MCK_FPRegs; break;
1835
0
    case Sparc::F11: OpKind = MCK_FPRegs; break;
1836
0
    case Sparc::F12: OpKind = MCK_FPRegs; break;
1837
24
    case Sparc::F13: OpKind = MCK_FPRegs; break;
1838
0
    case Sparc::F14: OpKind = MCK_FPRegs; break;
1839
0
    case Sparc::F15: OpKind = MCK_FPRegs; break;
1840
0
    case Sparc::F16: OpKind = MCK_FPRegs; break;
1841
0
    case Sparc::F17: OpKind = MCK_FPRegs; break;
1842
0
    case Sparc::F18: OpKind = MCK_FPRegs; break;
1843
24
    case Sparc::F19: OpKind = MCK_FPRegs; break;
1844
0
    case Sparc::F20: OpKind = MCK_FPRegs; break;
1845
0
    case Sparc::F21: OpKind = MCK_FPRegs; break;
1846
27
    case Sparc::F22: OpKind = MCK_FPRegs; break;
1847
24
    case Sparc::F23: OpKind = MCK_FPRegs; break;
1848
5
    case Sparc::F24: OpKind = MCK_FPRegs; break;
1849
0
    case Sparc::F25: OpKind = MCK_FPRegs; break;
1850
0
    case Sparc::F26: OpKind = MCK_FPRegs; break;
1851
0
    case Sparc::F27: OpKind = MCK_FPRegs; break;
1852
22
    case Sparc::F28: OpKind = MCK_FPRegs; break;
1853
0
    case Sparc::F29: OpKind = MCK_FPRegs; break;
1854
0
    case Sparc::F30: OpKind = MCK_FPRegs; break;
1855
24
    case Sparc::F31: OpKind = MCK_FPRegs; break;
1856
0
    case Sparc::D0: OpKind = MCK_Reg5; break;
1857
0
    case Sparc::D1: OpKind = MCK_Reg5; break;
1858
0
    case Sparc::D2: OpKind = MCK_Reg5; break;
1859
1
    case Sparc::D3: OpKind = MCK_Reg5; break;
1860
0
    case Sparc::D4: OpKind = MCK_Reg5; break;
1861
0
    case Sparc::D5: OpKind = MCK_Reg5; break;
1862
0
    case Sparc::D6: OpKind = MCK_Reg5; break;
1863
0
    case Sparc::D7: OpKind = MCK_Reg5; break;
1864
0
    case Sparc::D8: OpKind = MCK_Reg5; break;
1865
1
    case Sparc::D9: OpKind = MCK_Reg5; break;
1866
0
    case Sparc::D10: OpKind = MCK_Reg5; break;
1867
0
    case Sparc::D11: OpKind = MCK_Reg5; break;
1868
0
    case Sparc::D12: OpKind = MCK_Reg5; break;
1869
0
    case Sparc::D13: OpKind = MCK_Reg5; break;
1870
1
    case Sparc::D14: OpKind = MCK_Reg5; break;
1871
0
    case Sparc::D15: OpKind = MCK_Reg5; break;
1872
24
    case Sparc::D16: OpKind = MCK_DFPRegs; break;
1873
24
    case Sparc::D17: OpKind = MCK_DFPRegs; break;
1874
0
    case Sparc::D18: OpKind = MCK_DFPRegs; break;
1875
24
    case Sparc::D19: OpKind = MCK_DFPRegs; break;
1876
0
    case Sparc::D20: OpKind = MCK_DFPRegs; break;
1877
2
    case Sparc::D21: OpKind = MCK_DFPRegs; break;
1878
16
    case Sparc::D22: OpKind = MCK_DFPRegs; break;
1879
0
    case Sparc::D23: OpKind = MCK_DFPRegs; break;
1880
25
    case Sparc::D24: OpKind = MCK_DFPRegs; break;
1881
0
    case Sparc::D25: OpKind = MCK_DFPRegs; break;
1882
0
    case Sparc::D26: OpKind = MCK_DFPRegs; break;
1883
0
    case Sparc::D27: OpKind = MCK_DFPRegs; break;
1884
0
    case Sparc::D28: OpKind = MCK_DFPRegs; break;
1885
24
    case Sparc::D29: OpKind = MCK_DFPRegs; break;
1886
0
    case Sparc::D30: OpKind = MCK_DFPRegs; break;
1887
2
    case Sparc::D31: OpKind = MCK_DFPRegs; break;
1888
1
    case Sparc::Q0: OpKind = MCK_Reg7; break;
1889
0
    case Sparc::Q1: OpKind = MCK_Reg7; break;
1890
1
    case Sparc::Q2: OpKind = MCK_Reg7; break;
1891
0
    case Sparc::Q3: OpKind = MCK_Reg7; break;
1892
0
    case Sparc::Q4: OpKind = MCK_Reg7; break;
1893
0
    case Sparc::Q5: OpKind = MCK_Reg7; break;
1894
1
    case Sparc::Q6: OpKind = MCK_Reg7; break;
1895
1
    case Sparc::Q7: OpKind = MCK_Reg7; break;
1896
0
    case Sparc::Q8: OpKind = MCK_QFPRegs; break;
1897
0
    case Sparc::Q9: OpKind = MCK_QFPRegs; break;
1898
0
    case Sparc::Q10: OpKind = MCK_QFPRegs; break;
1899
0
    case Sparc::Q11: OpKind = MCK_QFPRegs; break;
1900
1
    case Sparc::Q12: OpKind = MCK_QFPRegs; break;
1901
0
    case Sparc::Q13: OpKind = MCK_QFPRegs; break;
1902
0
    case Sparc::Q14: OpKind = MCK_QFPRegs; break;
1903
0
    case Sparc::Q15: OpKind = MCK_QFPRegs; break;
1904
0
    case Sparc::G0_G1: OpKind = MCK_IntPair; break;
1905
3
    case Sparc::G2_G3: OpKind = MCK_IntPair; break;
1906
0
    case Sparc::G4_G5: OpKind = MCK_IntPair; break;
1907
3
    case Sparc::G6_G7: OpKind = MCK_IntPair; break;
1908
3
    case Sparc::O0_O1: OpKind = MCK_IntPair; break;
1909
3
    case Sparc::O2_O3: OpKind = MCK_IntPair; break;
1910
0
    case Sparc::O4_O5: OpKind = MCK_IntPair; break;
1911
3
    case Sparc::O6_O7: OpKind = MCK_IntPair; break;
1912
0
    case Sparc::L0_L1: OpKind = MCK_IntPair; break;
1913
0
    case Sparc::L2_L3: OpKind = MCK_IntPair; break;
1914
0
    case Sparc::L4_L5: OpKind = MCK_IntPair; break;
1915
3
    case Sparc::L6_L7: OpKind = MCK_IntPair; break;
1916
3
    case Sparc::I0_I1: OpKind = MCK_IntPair; break;
1917
0
    case Sparc::I2_I3: OpKind = MCK_IntPair; break;
1918
3
    case Sparc::I4_I5: OpKind = MCK_IntPair; break;
1919
3
    case Sparc::I6_I7: OpKind = MCK_IntPair; break;
1920
914
    }
1921
914
    return isSubclass(OpKind, Kind) ? MCTargetAsmParser::Match_Success :
1922
914
                                      MCTargetAsmParser::Match_InvalidOperand;
1923
914
  }
1924
1925
1.77k
  return MCTargetAsmParser::Match_InvalidOperand;
1926
2.69k
}
1927
1928
uint64_t SparcAsmParser::
1929
10.5k
ComputeAvailableFeatures(const FeatureBitset& FB) const {
1930
10.5k
  uint64_t Features = 0;
1931
10.5k
  if ((FB[Sparc::FeatureV9]))
1932
0
    Features |= Feature_HasV9;
1933
10.5k
  if ((FB[Sparc::FeatureVIS]))
1934
0
    Features |= Feature_HasVIS;
1935
10.5k
  if ((FB[Sparc::FeatureVIS2]))
1936
0
    Features |= Feature_HasVIS2;
1937
10.5k
  if ((FB[Sparc::FeatureVIS3]))
1938
0
    Features |= Feature_HasVIS3;
1939
10.5k
  return Features;
1940
10.5k
}
1941
1942
static const char *const MnemonicTable =
1943
    "\003add\005addcc\004addx\005addxc\006addxcc\007addxccc\talignaddr\nalig"
1944
    "naddrl\003and\005andcc\004andn\006andncc\007array16\007array32\006array"
1945
    "8\001b\002ba\003bcc\004bclr\003bcs\002be\003beq\002bg\003bge\004bgeu\003"
1946
    "bgu\002bl\003ble\004bleu\003blu\005bmask\002bn\003bne\004bneg\003bnz\004"
1947
    "bpos\005brgez\004brgz\005brlez\004brlz\004brnz\003brz\004bset\010bshuff"
1948
    "le\004btog\004btst\003bvc\003bvs\002bz\004call\003cas\004casx\003clr\004"
1949
    "clrb\004clrh\007cmask16\007cmask32\006cmask8\003cmp\003dec\005deccc\006"
1950
    "edge16\007edge16l\010edge16ln\007edge16n\006edge32\007edge32l\010edge32"
1951
    "ln\007edge32n\005edge8\006edge8l\007edge8ln\006edge8n\005fabsd\005fabsq"
1952
    "\005fabss\005faddd\005faddq\005fadds\nfaligndata\004fand\010fandnot1\tf"
1953
    "andnot1s\010fandnot2\tfandnot2s\005fands\002fb\003fba\003fbe\003fbg\004"
1954
    "fbge\003fbl\004fble\004fblg\003fbn\004fbne\004fbnz\003fbo\003fbu\004fbu"
1955
    "e\004fbug\005fbuge\004fbul\005fbule\003fbz\010fchksm16\005fcmpd\006fcmp"
1956
    "ed\006fcmpeq\010fcmpeq16\010fcmpeq32\006fcmpes\010fcmpgt16\010fcmpgt32\010"
1957
    "fcmple16\010fcmple32\010fcmpne16\010fcmpne32\005fcmpq\005fcmps\005fdivd"
1958
    "\005fdivq\005fdivs\006fdmulq\005fdtoi\005fdtoq\005fdtos\005fdtox\007fex"
1959
    "pand\006fhaddd\006fhadds\006fhsubd\006fhsubs\005fitod\005fitoq\005fitos"
1960
    "\006flcmpd\006flcmps\005flush\006flushw\007fmean16\005fmovd\006fmovda\007"
1961
    "fmovdcc\007fmovdcs\006fmovde\007fmovdeq\006fmovdg\007fmovdge\010fmovdge"
1962
    "u\007fmovdgu\006fmovdl\007fmovdle\010fmovdleu\007fmovdlg\007fmovdlu\006"
1963
    "fmovdn\007fmovdne\010fmovdneg\007fmovdnz\006fmovdo\010fmovdpos\006fmovd"
1964
    "u\007fmovdue\007fmovdug\010fmovduge\007fmovdul\010fmovdule\007fmovdvc\007"
1965
    "fmovdvs\006fmovdz\005fmovq\006fmovqa\007fmovqcc\007fmovqcs\006fmovqe\007"
1966
    "fmovqeq\006fmovqg\007fmovqge\010fmovqgeu\007fmovqgu\006fmovql\007fmovql"
1967
    "e\010fmovqleu\007fmovqlg\007fmovqlu\006fmovqn\007fmovqne\010fmovqneg\007"
1968
    "fmovqnz\006fmovqo\010fmovqpos\006fmovqu\007fmovque\007fmovqug\010fmovqu"
1969
    "ge\007fmovqul\010fmovqule\007fmovqvc\007fmovqvs\006fmovqz\tfmovrdgez\010"
1970
    "fmovrdgz\tfmovrdlez\010fmovrdlz\010fmovrdnz\007fmovrdz\tfmovrqgez\010fm"
1971
    "ovrqgz\tfmovrqlez\010fmovrqlz\010fmovrqnz\007fmovrqz\tfmovrsgez\010fmov"
1972
    "rsgz\tfmovrslez\010fmovrslz\010fmovrsnz\007fmovrsz\005fmovs\006fmovsa\007"
1973
    "fmovscc\007fmovscs\006fmovse\007fmovseq\006fmovsg\007fmovsge\010fmovsge"
1974
    "u\007fmovsgu\006fmovsl\007fmovsle\010fmovsleu\007fmovslg\007fmovslu\006"
1975
    "fmovsn\007fmovsne\010fmovsneg\007fmovsnz\006fmovso\010fmovspos\006fmovs"
1976
    "u\007fmovsue\007fmovsug\010fmovsuge\007fmovsul\010fmovsule\007fmovsvc\007"
1977
    "fmovsvs\006fmovsz\nfmul8sux16\nfmul8ulx16\010fmul8x16\nfmul8x16al\nfmul"
1978
    "8x16au\005fmuld\013fmuld8sux16\013fmuld8ulx16\005fmulq\005fmuls\006fnad"
1979
    "dd\006fnadds\005fnand\006fnands\005fnegd\005fnegq\005fnegs\007fnhaddd\007"
1980
    "fnhadds\004fnor\005fnors\005fnot1\006fnot1s\005fnot2\006fnot2s\004fone\005"
1981
    "fones\003for\007fornot1\010fornot1s\007fornot2\010fornot2s\004fors\007f"
1982
    "pack16\007fpack32\010fpackfix\007fpadd16\010fpadd16s\007fpadd32\010fpad"
1983
    "d32s\007fpadd64\007fpmerge\007fpsub16\010fpsub16S\007fpsub32\010fpsub32"
1984
    "S\005fqtod\005fqtoi\005fqtos\005fqtox\007fslas16\007fslas32\006fsll16\006"
1985
    "fsll32\006fsmuld\006fsqrtd\006fsqrtq\006fsqrts\006fsra16\006fsra32\005f"
1986
    "src1\006fsrc1s\005fsrc2\006fsrc2s\006fsrl16\006fsrl32\005fstod\005fstoi"
1987
    "\005fstoq\005fstox\005fsubd\005fsubq\005fsubs\005fxnor\006fxnors\004fxo"
1988
    "r\005fxors\005fxtod\005fxtoq\005fxtos\005fzero\006fzeros\003inc\005incc"
1989
    "c\003jmp\004jmpl\002ld\003lda\003ldd\004ldda\003ldq\004ldqa\004ldsb\005"
1990
    "ldsba\004ldsh\005ldsha\006ldstub\007ldstuba\004ldsw\004ldub\005lduba\004"
1991
    "lduh\005lduha\003ldx\005lzcnt\006membar\003mov\004mova\005movcc\005movc"
1992
    "s\007movdtox\004move\005moveq\004movg\005movge\006movgeu\005movgu\004mo"
1993
    "vl\005movle\006movleu\005movlg\005movlu\004movn\005movne\006movneg\005m"
1994
    "ovnz\004movo\006movpos\007movrgez\006movrgz\007movrlez\006movrlz\006mov"
1995
    "rnz\005movrz\010movstosw\010movstouw\004movu\005movue\005movug\006movug"
1996
    "e\005movul\006movule\005movvc\005movvs\004movz\006mulscc\004mulx\003neg"
1997
    "\003nop\003not\002or\004orcc\003orn\005orncc\005pdist\006pdistn\004popc"
1998
    "\002rd\004rdpr\007restore\003ret\004retl\004rett\004save\004sdiv\006sdi"
1999
    "vcc\005sdivx\003set\005sethi\010shutdown\004siam\005signx\003sll\004sll"
2000
    "x\004smul\006smulcc\003sra\004srax\003srl\004srlx\002st\003sta\003stb\004"
2001
    "stba\005stbar\003std\004stda\003sth\004stha\003stq\004stqa\003stx\003su"
2002
    "b\005subcc\004subx\006subxcc\004swap\005swapa\001t\002ta\006taddcc\010t"
2003
    "addcctv\003tcc\003tcs\002te\003teq\002tg\003tge\004tgeu\003tgu\002tl\003"
2004
    "tle\004tleu\003tlu\002tn\003tne\004tneg\003tnz\004tpos\003tst\006tsubcc"
2005
    "\010tsubcctv\003tvc\003tvs\002tz\004udiv\006udivcc\005udivx\004umul\006"
2006
    "umulcc\007umulxhi\005unimp\002wr\004wrpr\005xmulx\007xmulxhi\004xnor\006"
2007
    "xnorcc\003xor\005xorcc";
2008
2009
namespace {
2010
  struct MatchEntry {
2011
    uint16_t Mnemonic;
2012
    uint16_t Opcode;
2013
    uint16_t ConvertFn;
2014
    uint8_t RequiredFeatures;
2015
    uint8_t Classes[5];
2016
90.8k
    StringRef getMnemonic() const {
2017
90.8k
      return StringRef(MnemonicTable + Mnemonic + 1,
2018
90.8k
                       MnemonicTable[Mnemonic]);
2019
90.8k
    }
2020
  };
2021
2022
  // Predicate for searching for an opcode.
2023
  struct LessOpcode {
2024
48.9k
    bool operator()(const MatchEntry &LHS, StringRef RHS) {
2025
48.9k
      return LHS.getMnemonic() < RHS;
2026
48.9k
    }
2027
35.5k
    bool operator()(StringRef LHS, const MatchEntry &RHS) {
2028
35.5k
      return LHS < RHS.getMnemonic();
2029
35.5k
    }
2030
0
    bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {
2031
0
      return LHS.getMnemonic() < RHS.getMnemonic();
2032
0
    }
2033
  };
2034
} // end anonymous namespace.
2035
2036
static const MatchEntry MatchTable0[] = {
2037
  { 0 /* add */, Sparc::ADDrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2038
  { 0 /* add */, Sparc::ADDri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
2039
  { 4 /* addcc */, Sparc::ADDCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2040
  { 4 /* addcc */, Sparc::ADDCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
2041
  { 10 /* addx */, Sparc::ADDCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2042
  { 10 /* addx */, Sparc::ADDCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
2043
  { 15 /* addxc */, Sparc::ADDXC, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2044
  { 21 /* addxcc */, Sparc::ADDErr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2045
  { 21 /* addxcc */, Sparc::ADDEri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
2046
  { 28 /* addxccc */, Sparc::ADDXCCC, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2047
  { 36 /* alignaddr */, Sparc::ALIGNADDR, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2048
  { 46 /* alignaddrl */, Sparc::ALIGNADDRL, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2049
  { 57 /* and */, Sparc::ANDrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2050
  { 57 /* and */, Sparc::ANDri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
2051
  { 61 /* andcc */, Sparc::ANDCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2052
  { 61 /* andcc */, Sparc::ANDCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
2053
  { 67 /* andn */, Sparc::ANDNrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2054
  { 67 /* andn */, Sparc::ANDNri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
2055
  { 72 /* andncc */, Sparc::ANDNCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2056
  { 72 /* andncc */, Sparc::ANDNCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
2057
  { 79 /* array16 */, Sparc::ARRAY16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2058
  { 87 /* array32 */, Sparc::ARRAY32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2059
  { 95 /* array8 */, Sparc::ARRAY8, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2060
  { 102 /* b */, Sparc::BCOND, Convert__Imm1_0__imm_95_8, 0, { MCK_Imm }, },
2061
  { 102 /* b */, Sparc::BPICC, Convert__Imm1_1__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2062
  { 102 /* b */, Sparc::BPXCC, Convert__Imm1_1__imm_95_8, 0, { MCK__PCT_xcc, MCK_Imm }, },
2063
  { 102 /* b */, Sparc::BCONDA, Convert__Imm1_1__imm_95_8, 0, { MCK_a, MCK_Imm }, },
2064
  { 102 /* b */, Sparc::BCOND, Convert__Imm1_1__Imm1_0, 0, { MCK_Imm, MCK_Imm }, },
2065
  { 102 /* b */, Sparc::BPICCA, Convert__Imm1_2__imm_95_8, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2066
  { 102 /* b */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_8, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2067
  { 102 /* b */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_8, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2068
  { 102 /* b */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_8, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2069
  { 102 /* b */, Sparc::BPICC, Convert__Imm1_2__imm_95_8, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2070
  { 102 /* b */, Sparc::BPXCC, Convert__Imm1_2__imm_95_8, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2071
  { 102 /* b */, Sparc::BPICC, Convert__Imm1_2__Imm1_0, Feature_HasV9, { MCK_Imm, MCK__PCT_icc, MCK_Imm }, },
2072
  { 102 /* b */, Sparc::BPXCC, Convert__Imm1_2__Imm1_0, 0, { MCK_Imm, MCK__PCT_xcc, MCK_Imm }, },
2073
  { 102 /* b */, Sparc::BCONDA, Convert__Imm1_2__Imm1_0, 0, { MCK_Imm, MCK_a, MCK_Imm }, },
2074
  { 102 /* b */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_8, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2075
  { 102 /* b */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_8, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2076
  { 102 /* b */, Sparc::BPICCA, Convert__Imm1_3__imm_95_8, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2077
  { 102 /* b */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_8, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2078
  { 102 /* b */, Sparc::BPICCA, Convert__Imm1_3__Imm1_0, Feature_HasV9, { MCK_Imm, MCK_a, MCK__PCT_icc, MCK_Imm }, },
2079
  { 102 /* b */, Sparc::BPXCCA, Convert__Imm1_3__Imm1_0, 0, { MCK_Imm, MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2080
  { 102 /* b */, Sparc::BPICCNT, Convert__Imm1_3__Imm1_0, Feature_HasV9, { MCK_Imm, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2081
  { 102 /* b */, Sparc::BPXCCNT, Convert__Imm1_3__Imm1_0, 0, { MCK_Imm, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2082
  { 102 /* b */, Sparc::BPICCANT, Convert__Imm1_4__Imm1_0, Feature_HasV9, { MCK_Imm, MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2083
  { 102 /* b */, Sparc::BPXCCANT, Convert__Imm1_4__Imm1_0, 0, { MCK_Imm, MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2084
  { 104 /* ba */, Sparc::BA, Convert__Imm1_0, 0, { MCK_Imm }, },
2085
  { 104 /* ba */, Sparc::BCOND, Convert__Imm1_0__imm_95_8, 0, { MCK_Imm }, },
2086
  { 104 /* ba */, Sparc::BPICC, Convert__Imm1_1__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2087
  { 104 /* ba */, Sparc::BPXCC, Convert__Imm1_1__imm_95_8, 0, { MCK__PCT_xcc, MCK_Imm }, },
2088
  { 104 /* ba */, Sparc::BCONDA, Convert__Imm1_1__imm_95_8, 0, { MCK_a, MCK_Imm }, },
2089
  { 104 /* ba */, Sparc::BPICCA, Convert__Imm1_2__imm_95_8, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2090
  { 104 /* ba */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_8, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2091
  { 104 /* ba */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_8, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2092
  { 104 /* ba */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_8, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2093
  { 104 /* ba */, Sparc::BPICC, Convert__Imm1_2__imm_95_8, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2094
  { 104 /* ba */, Sparc::BPXCC, Convert__Imm1_2__imm_95_8, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2095
  { 104 /* ba */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_8, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2096
  { 104 /* ba */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_8, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2097
  { 104 /* ba */, Sparc::BPICCA, Convert__Imm1_3__imm_95_8, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2098
  { 104 /* ba */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_8, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2099
  { 107 /* bcc */, Sparc::BCOND, Convert__Imm1_0__imm_95_13, 0, { MCK_Imm }, },
2100
  { 107 /* bcc */, Sparc::BPICC, Convert__Imm1_1__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2101
  { 107 /* bcc */, Sparc::BPXCC, Convert__Imm1_1__imm_95_13, 0, { MCK__PCT_xcc, MCK_Imm }, },
2102
  { 107 /* bcc */, Sparc::BCONDA, Convert__Imm1_1__imm_95_13, 0, { MCK_a, MCK_Imm }, },
2103
  { 107 /* bcc */, Sparc::BPICCA, Convert__Imm1_2__imm_95_13, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2104
  { 107 /* bcc */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_13, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2105
  { 107 /* bcc */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_13, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2106
  { 107 /* bcc */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_13, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2107
  { 107 /* bcc */, Sparc::BPICC, Convert__Imm1_2__imm_95_13, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2108
  { 107 /* bcc */, Sparc::BPXCC, Convert__Imm1_2__imm_95_13, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2109
  { 107 /* bcc */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_13, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2110
  { 107 /* bcc */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_13, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2111
  { 107 /* bcc */, Sparc::BPICCA, Convert__Imm1_3__imm_95_13, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2112
  { 107 /* bcc */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_13, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2113
  { 111 /* bclr */, Sparc::ANDNrr, Convert__Reg1_1__Reg1_1__Reg1_0, 0, { MCK_IntRegs, MCK_IntRegs }, },
2114
  { 111 /* bclr */, Sparc::ANDNri, Convert__Reg1_1__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_IntRegs }, },
2115
  { 116 /* bcs */, Sparc::BCOND, Convert__Imm1_0__imm_95_5, 0, { MCK_Imm }, },
2116
  { 116 /* bcs */, Sparc::BPICC, Convert__Imm1_1__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2117
  { 116 /* bcs */, Sparc::BPXCC, Convert__Imm1_1__imm_95_5, 0, { MCK__PCT_xcc, MCK_Imm }, },
2118
  { 116 /* bcs */, Sparc::BCONDA, Convert__Imm1_1__imm_95_5, 0, { MCK_a, MCK_Imm }, },
2119
  { 116 /* bcs */, Sparc::BPICCA, Convert__Imm1_2__imm_95_5, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2120
  { 116 /* bcs */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_5, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2121
  { 116 /* bcs */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_5, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2122
  { 116 /* bcs */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_5, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2123
  { 116 /* bcs */, Sparc::BPICC, Convert__Imm1_2__imm_95_5, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2124
  { 116 /* bcs */, Sparc::BPXCC, Convert__Imm1_2__imm_95_5, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2125
  { 116 /* bcs */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_5, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2126
  { 116 /* bcs */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_5, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2127
  { 116 /* bcs */, Sparc::BPICCA, Convert__Imm1_3__imm_95_5, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2128
  { 116 /* bcs */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_5, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2129
  { 120 /* be */, Sparc::BCOND, Convert__Imm1_0__imm_95_1, 0, { MCK_Imm }, },
2130
  { 120 /* be */, Sparc::BPICC, Convert__Imm1_1__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2131
  { 120 /* be */, Sparc::BPXCC, Convert__Imm1_1__imm_95_1, 0, { MCK__PCT_xcc, MCK_Imm }, },
2132
  { 120 /* be */, Sparc::BCONDA, Convert__Imm1_1__imm_95_1, 0, { MCK_a, MCK_Imm }, },
2133
  { 120 /* be */, Sparc::BPICCA, Convert__Imm1_2__imm_95_1, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2134
  { 120 /* be */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_1, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2135
  { 120 /* be */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_1, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2136
  { 120 /* be */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_1, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2137
  { 120 /* be */, Sparc::BPICC, Convert__Imm1_2__imm_95_1, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2138
  { 120 /* be */, Sparc::BPXCC, Convert__Imm1_2__imm_95_1, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2139
  { 120 /* be */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_1, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2140
  { 120 /* be */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_1, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2141
  { 120 /* be */, Sparc::BPICCA, Convert__Imm1_3__imm_95_1, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2142
  { 120 /* be */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_1, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2143
  { 123 /* beq */, Sparc::BCOND, Convert__Imm1_0__imm_95_1, 0, { MCK_Imm }, },
2144
  { 123 /* beq */, Sparc::BPICC, Convert__Imm1_1__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2145
  { 123 /* beq */, Sparc::BPXCC, Convert__Imm1_1__imm_95_1, 0, { MCK__PCT_xcc, MCK_Imm }, },
2146
  { 123 /* beq */, Sparc::BCONDA, Convert__Imm1_1__imm_95_1, 0, { MCK_a, MCK_Imm }, },
2147
  { 123 /* beq */, Sparc::BPICCA, Convert__Imm1_2__imm_95_1, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2148
  { 123 /* beq */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_1, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2149
  { 123 /* beq */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_1, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2150
  { 123 /* beq */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_1, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2151
  { 123 /* beq */, Sparc::BPICC, Convert__Imm1_2__imm_95_1, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2152
  { 123 /* beq */, Sparc::BPXCC, Convert__Imm1_2__imm_95_1, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2153
  { 123 /* beq */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_1, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2154
  { 123 /* beq */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_1, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2155
  { 123 /* beq */, Sparc::BPICCA, Convert__Imm1_3__imm_95_1, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2156
  { 123 /* beq */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_1, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2157
  { 127 /* bg */, Sparc::BCOND, Convert__Imm1_0__imm_95_10, 0, { MCK_Imm }, },
2158
  { 127 /* bg */, Sparc::BPICC, Convert__Imm1_1__imm_95_10, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2159
  { 127 /* bg */, Sparc::BPXCC, Convert__Imm1_1__imm_95_10, 0, { MCK__PCT_xcc, MCK_Imm }, },
2160
  { 127 /* bg */, Sparc::BCONDA, Convert__Imm1_1__imm_95_10, 0, { MCK_a, MCK_Imm }, },
2161
  { 127 /* bg */, Sparc::BPICCA, Convert__Imm1_2__imm_95_10, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2162
  { 127 /* bg */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_10, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2163
  { 127 /* bg */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_10, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2164
  { 127 /* bg */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_10, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2165
  { 127 /* bg */, Sparc::BPICC, Convert__Imm1_2__imm_95_10, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2166
  { 127 /* bg */, Sparc::BPXCC, Convert__Imm1_2__imm_95_10, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2167
  { 127 /* bg */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_10, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2168
  { 127 /* bg */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_10, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2169
  { 127 /* bg */, Sparc::BPICCA, Convert__Imm1_3__imm_95_10, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2170
  { 127 /* bg */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_10, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2171
  { 130 /* bge */, Sparc::BCOND, Convert__Imm1_0__imm_95_11, 0, { MCK_Imm }, },
2172
  { 130 /* bge */, Sparc::BPICC, Convert__Imm1_1__imm_95_11, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2173
  { 130 /* bge */, Sparc::BPXCC, Convert__Imm1_1__imm_95_11, 0, { MCK__PCT_xcc, MCK_Imm }, },
2174
  { 130 /* bge */, Sparc::BCONDA, Convert__Imm1_1__imm_95_11, 0, { MCK_a, MCK_Imm }, },
2175
  { 130 /* bge */, Sparc::BPICCA, Convert__Imm1_2__imm_95_11, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2176
  { 130 /* bge */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_11, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2177
  { 130 /* bge */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_11, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2178
  { 130 /* bge */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_11, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2179
  { 130 /* bge */, Sparc::BPICC, Convert__Imm1_2__imm_95_11, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2180
  { 130 /* bge */, Sparc::BPXCC, Convert__Imm1_2__imm_95_11, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2181
  { 130 /* bge */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_11, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2182
  { 130 /* bge */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_11, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2183
  { 130 /* bge */, Sparc::BPICCA, Convert__Imm1_3__imm_95_11, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2184
  { 130 /* bge */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_11, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2185
  { 134 /* bgeu */, Sparc::BCOND, Convert__Imm1_0__imm_95_13, 0, { MCK_Imm }, },
2186
  { 134 /* bgeu */, Sparc::BPICC, Convert__Imm1_1__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2187
  { 134 /* bgeu */, Sparc::BPXCC, Convert__Imm1_1__imm_95_13, 0, { MCK__PCT_xcc, MCK_Imm }, },
2188
  { 134 /* bgeu */, Sparc::BCONDA, Convert__Imm1_1__imm_95_13, 0, { MCK_a, MCK_Imm }, },
2189
  { 134 /* bgeu */, Sparc::BPICCA, Convert__Imm1_2__imm_95_13, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2190
  { 134 /* bgeu */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_13, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2191
  { 134 /* bgeu */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_13, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2192
  { 134 /* bgeu */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_13, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2193
  { 134 /* bgeu */, Sparc::BPICC, Convert__Imm1_2__imm_95_13, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2194
  { 134 /* bgeu */, Sparc::BPXCC, Convert__Imm1_2__imm_95_13, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2195
  { 134 /* bgeu */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_13, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2196
  { 134 /* bgeu */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_13, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2197
  { 134 /* bgeu */, Sparc::BPICCA, Convert__Imm1_3__imm_95_13, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2198
  { 134 /* bgeu */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_13, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2199
  { 139 /* bgu */, Sparc::BCOND, Convert__Imm1_0__imm_95_12, 0, { MCK_Imm }, },
2200
  { 139 /* bgu */, Sparc::BPICC, Convert__Imm1_1__imm_95_12, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2201
  { 139 /* bgu */, Sparc::BPXCC, Convert__Imm1_1__imm_95_12, 0, { MCK__PCT_xcc, MCK_Imm }, },
2202
  { 139 /* bgu */, Sparc::BCONDA, Convert__Imm1_1__imm_95_12, 0, { MCK_a, MCK_Imm }, },
2203
  { 139 /* bgu */, Sparc::BPICCA, Convert__Imm1_2__imm_95_12, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2204
  { 139 /* bgu */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_12, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2205
  { 139 /* bgu */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_12, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2206
  { 139 /* bgu */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_12, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2207
  { 139 /* bgu */, Sparc::BPICC, Convert__Imm1_2__imm_95_12, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2208
  { 139 /* bgu */, Sparc::BPXCC, Convert__Imm1_2__imm_95_12, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2209
  { 139 /* bgu */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_12, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2210
  { 139 /* bgu */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_12, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2211
  { 139 /* bgu */, Sparc::BPICCA, Convert__Imm1_3__imm_95_12, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2212
  { 139 /* bgu */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_12, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2213
  { 143 /* bl */, Sparc::BCOND, Convert__Imm1_0__imm_95_3, 0, { MCK_Imm }, },
2214
  { 143 /* bl */, Sparc::BPICC, Convert__Imm1_1__imm_95_3, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2215
  { 143 /* bl */, Sparc::BPXCC, Convert__Imm1_1__imm_95_3, 0, { MCK__PCT_xcc, MCK_Imm }, },
2216
  { 143 /* bl */, Sparc::BCONDA, Convert__Imm1_1__imm_95_3, 0, { MCK_a, MCK_Imm }, },
2217
  { 143 /* bl */, Sparc::BPICCA, Convert__Imm1_2__imm_95_3, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2218
  { 143 /* bl */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_3, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2219
  { 143 /* bl */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_3, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2220
  { 143 /* bl */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_3, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2221
  { 143 /* bl */, Sparc::BPICC, Convert__Imm1_2__imm_95_3, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2222
  { 143 /* bl */, Sparc::BPXCC, Convert__Imm1_2__imm_95_3, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2223
  { 143 /* bl */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_3, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2224
  { 143 /* bl */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_3, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2225
  { 143 /* bl */, Sparc::BPICCA, Convert__Imm1_3__imm_95_3, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2226
  { 143 /* bl */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_3, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2227
  { 146 /* ble */, Sparc::BCOND, Convert__Imm1_0__imm_95_2, 0, { MCK_Imm }, },
2228
  { 146 /* ble */, Sparc::BPICC, Convert__Imm1_1__imm_95_2, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2229
  { 146 /* ble */, Sparc::BPXCC, Convert__Imm1_1__imm_95_2, 0, { MCK__PCT_xcc, MCK_Imm }, },
2230
  { 146 /* ble */, Sparc::BCONDA, Convert__Imm1_1__imm_95_2, 0, { MCK_a, MCK_Imm }, },
2231
  { 146 /* ble */, Sparc::BPICCA, Convert__Imm1_2__imm_95_2, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2232
  { 146 /* ble */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_2, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2233
  { 146 /* ble */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_2, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2234
  { 146 /* ble */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_2, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2235
  { 146 /* ble */, Sparc::BPICC, Convert__Imm1_2__imm_95_2, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2236
  { 146 /* ble */, Sparc::BPXCC, Convert__Imm1_2__imm_95_2, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2237
  { 146 /* ble */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_2, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2238
  { 146 /* ble */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_2, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2239
  { 146 /* ble */, Sparc::BPICCA, Convert__Imm1_3__imm_95_2, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2240
  { 146 /* ble */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_2, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2241
  { 150 /* bleu */, Sparc::BCOND, Convert__Imm1_0__imm_95_4, 0, { MCK_Imm }, },
2242
  { 150 /* bleu */, Sparc::BPICC, Convert__Imm1_1__imm_95_4, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2243
  { 150 /* bleu */, Sparc::BPXCC, Convert__Imm1_1__imm_95_4, 0, { MCK__PCT_xcc, MCK_Imm }, },
2244
  { 150 /* bleu */, Sparc::BCONDA, Convert__Imm1_1__imm_95_4, 0, { MCK_a, MCK_Imm }, },
2245
  { 150 /* bleu */, Sparc::BPICCA, Convert__Imm1_2__imm_95_4, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2246
  { 150 /* bleu */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_4, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2247
  { 150 /* bleu */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_4, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2248
  { 150 /* bleu */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_4, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2249
  { 150 /* bleu */, Sparc::BPICC, Convert__Imm1_2__imm_95_4, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2250
  { 150 /* bleu */, Sparc::BPXCC, Convert__Imm1_2__imm_95_4, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2251
  { 150 /* bleu */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_4, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2252
  { 150 /* bleu */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_4, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2253
  { 150 /* bleu */, Sparc::BPICCA, Convert__Imm1_3__imm_95_4, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2254
  { 150 /* bleu */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_4, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2255
  { 155 /* blu */, Sparc::BCOND, Convert__Imm1_0__imm_95_5, 0, { MCK_Imm }, },
2256
  { 155 /* blu */, Sparc::BPICC, Convert__Imm1_1__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2257
  { 155 /* blu */, Sparc::BPXCC, Convert__Imm1_1__imm_95_5, 0, { MCK__PCT_xcc, MCK_Imm }, },
2258
  { 155 /* blu */, Sparc::BCONDA, Convert__Imm1_1__imm_95_5, 0, { MCK_a, MCK_Imm }, },
2259
  { 155 /* blu */, Sparc::BPICCA, Convert__Imm1_2__imm_95_5, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2260
  { 155 /* blu */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_5, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2261
  { 155 /* blu */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_5, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2262
  { 155 /* blu */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_5, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2263
  { 155 /* blu */, Sparc::BPICC, Convert__Imm1_2__imm_95_5, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2264
  { 155 /* blu */, Sparc::BPXCC, Convert__Imm1_2__imm_95_5, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2265
  { 155 /* blu */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_5, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2266
  { 155 /* blu */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_5, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2267
  { 155 /* blu */, Sparc::BPICCA, Convert__Imm1_3__imm_95_5, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2268
  { 155 /* blu */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_5, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2269
  { 159 /* bmask */, Sparc::BMASK, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2270
  { 165 /* bn */, Sparc::BCOND, Convert__Imm1_0__imm_95_0, 0, { MCK_Imm }, },
2271
  { 165 /* bn */, Sparc::BPICC, Convert__Imm1_1__imm_95_0, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2272
  { 165 /* bn */, Sparc::BPXCC, Convert__Imm1_1__imm_95_0, 0, { MCK__PCT_xcc, MCK_Imm }, },
2273
  { 165 /* bn */, Sparc::BCONDA, Convert__Imm1_1__imm_95_0, 0, { MCK_a, MCK_Imm }, },
2274
  { 165 /* bn */, Sparc::BPICCA, Convert__Imm1_2__imm_95_0, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2275
  { 165 /* bn */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_0, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2276
  { 165 /* bn */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_0, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2277
  { 165 /* bn */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_0, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2278
  { 165 /* bn */, Sparc::BPICC, Convert__Imm1_2__imm_95_0, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2279
  { 165 /* bn */, Sparc::BPXCC, Convert__Imm1_2__imm_95_0, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2280
  { 165 /* bn */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_0, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2281
  { 165 /* bn */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_0, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2282
  { 165 /* bn */, Sparc::BPICCA, Convert__Imm1_3__imm_95_0, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2283
  { 165 /* bn */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_0, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2284
  { 168 /* bne */, Sparc::BCOND, Convert__Imm1_0__imm_95_9, 0, { MCK_Imm }, },
2285
  { 168 /* bne */, Sparc::BPICC, Convert__Imm1_1__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2286
  { 168 /* bne */, Sparc::BPXCC, Convert__Imm1_1__imm_95_9, 0, { MCK__PCT_xcc, MCK_Imm }, },
2287
  { 168 /* bne */, Sparc::BCONDA, Convert__Imm1_1__imm_95_9, 0, { MCK_a, MCK_Imm }, },
2288
  { 168 /* bne */, Sparc::BPICCA, Convert__Imm1_2__imm_95_9, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2289
  { 168 /* bne */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_9, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2290
  { 168 /* bne */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_9, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2291
  { 168 /* bne */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_9, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2292
  { 168 /* bne */, Sparc::BPICC, Convert__Imm1_2__imm_95_9, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2293
  { 168 /* bne */, Sparc::BPXCC, Convert__Imm1_2__imm_95_9, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2294
  { 168 /* bne */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_9, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2295
  { 168 /* bne */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_9, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2296
  { 168 /* bne */, Sparc::BPICCA, Convert__Imm1_3__imm_95_9, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2297
  { 168 /* bne */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_9, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2298
  { 172 /* bneg */, Sparc::BCOND, Convert__Imm1_0__imm_95_6, 0, { MCK_Imm }, },
2299
  { 172 /* bneg */, Sparc::BPICC, Convert__Imm1_1__imm_95_6, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2300
  { 172 /* bneg */, Sparc::BPXCC, Convert__Imm1_1__imm_95_6, 0, { MCK__PCT_xcc, MCK_Imm }, },
2301
  { 172 /* bneg */, Sparc::BCONDA, Convert__Imm1_1__imm_95_6, 0, { MCK_a, MCK_Imm }, },
2302
  { 172 /* bneg */, Sparc::BPICCA, Convert__Imm1_2__imm_95_6, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2303
  { 172 /* bneg */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_6, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2304
  { 172 /* bneg */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_6, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2305
  { 172 /* bneg */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_6, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2306
  { 172 /* bneg */, Sparc::BPICC, Convert__Imm1_2__imm_95_6, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2307
  { 172 /* bneg */, Sparc::BPXCC, Convert__Imm1_2__imm_95_6, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2308
  { 172 /* bneg */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_6, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2309
  { 172 /* bneg */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_6, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2310
  { 172 /* bneg */, Sparc::BPICCA, Convert__Imm1_3__imm_95_6, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2311
  { 172 /* bneg */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_6, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2312
  { 177 /* bnz */, Sparc::BCOND, Convert__Imm1_0__imm_95_9, 0, { MCK_Imm }, },
2313
  { 177 /* bnz */, Sparc::BPICC, Convert__Imm1_1__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2314
  { 177 /* bnz */, Sparc::BPXCC, Convert__Imm1_1__imm_95_9, 0, { MCK__PCT_xcc, MCK_Imm }, },
2315
  { 177 /* bnz */, Sparc::BCONDA, Convert__Imm1_1__imm_95_9, 0, { MCK_a, MCK_Imm }, },
2316
  { 177 /* bnz */, Sparc::BPICCA, Convert__Imm1_2__imm_95_9, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2317
  { 177 /* bnz */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_9, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2318
  { 177 /* bnz */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_9, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2319
  { 177 /* bnz */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_9, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2320
  { 177 /* bnz */, Sparc::BPICC, Convert__Imm1_2__imm_95_9, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2321
  { 177 /* bnz */, Sparc::BPXCC, Convert__Imm1_2__imm_95_9, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2322
  { 177 /* bnz */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_9, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2323
  { 177 /* bnz */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_9, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2324
  { 177 /* bnz */, Sparc::BPICCA, Convert__Imm1_3__imm_95_9, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2325
  { 177 /* bnz */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_9, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2326
  { 181 /* bpos */, Sparc::BCOND, Convert__Imm1_0__imm_95_14, 0, { MCK_Imm }, },
2327
  { 181 /* bpos */, Sparc::BPICC, Convert__Imm1_1__imm_95_14, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2328
  { 181 /* bpos */, Sparc::BPXCC, Convert__Imm1_1__imm_95_14, 0, { MCK__PCT_xcc, MCK_Imm }, },
2329
  { 181 /* bpos */, Sparc::BCONDA, Convert__Imm1_1__imm_95_14, 0, { MCK_a, MCK_Imm }, },
2330
  { 181 /* bpos */, Sparc::BPICCA, Convert__Imm1_2__imm_95_14, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2331
  { 181 /* bpos */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_14, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2332
  { 181 /* bpos */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_14, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2333
  { 181 /* bpos */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_14, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2334
  { 181 /* bpos */, Sparc::BPICC, Convert__Imm1_2__imm_95_14, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2335
  { 181 /* bpos */, Sparc::BPXCC, Convert__Imm1_2__imm_95_14, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2336
  { 181 /* bpos */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_14, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2337
  { 181 /* bpos */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_14, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2338
  { 181 /* bpos */, Sparc::BPICCA, Convert__Imm1_3__imm_95_14, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2339
  { 181 /* bpos */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_14, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2340
  { 186 /* brgez */, Sparc::BPGEZnapt, Convert__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm }, },
2341
  { 186 /* brgez */, Sparc::BPGEZapt, Convert__Reg1_1__Imm1_2, 0, { MCK_a, MCK_IntRegs, MCK_Imm }, },
2342
  { 186 /* brgez */, Sparc::BPGEZnapn, Convert__Reg1_1__Imm1_2, 0, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
2343
  { 186 /* brgez */, Sparc::BPGEZnapt, Convert__Reg1_1__Imm1_2, 0, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
2344
  { 186 /* brgez */, Sparc::BPGEZapn, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
2345
  { 186 /* brgez */, Sparc::BPGEZapt, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
2346
  { 192 /* brgz */, Sparc::BPGZnapt, Convert__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm }, },
2347
  { 192 /* brgz */, Sparc::BPGZapt, Convert__Reg1_1__Imm1_2, 0, { MCK_a, MCK_IntRegs, MCK_Imm }, },
2348
  { 192 /* brgz */, Sparc::BPGZnapn, Convert__Reg1_1__Imm1_2, 0, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
2349
  { 192 /* brgz */, Sparc::BPGZnapt, Convert__Reg1_1__Imm1_2, 0, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
2350
  { 192 /* brgz */, Sparc::BPGZapn, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
2351
  { 192 /* brgz */, Sparc::BPGZapt, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
2352
  { 197 /* brlez */, Sparc::BPLEZnapt, Convert__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm }, },
2353
  { 197 /* brlez */, Sparc::BPLEZapt, Convert__Reg1_1__Imm1_2, 0, { MCK_a, MCK_IntRegs, MCK_Imm }, },
2354
  { 197 /* brlez */, Sparc::BPLEZnapn, Convert__Reg1_1__Imm1_2, 0, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
2355
  { 197 /* brlez */, Sparc::BPLEZnapt, Convert__Reg1_1__Imm1_2, 0, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
2356
  { 197 /* brlez */, Sparc::BPLEZapn, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
2357
  { 197 /* brlez */, Sparc::BPLEZapt, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
2358
  { 203 /* brlz */, Sparc::BPLZnapt, Convert__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm }, },
2359
  { 203 /* brlz */, Sparc::BPLZapt, Convert__Reg1_1__Imm1_2, 0, { MCK_a, MCK_IntRegs, MCK_Imm }, },
2360
  { 203 /* brlz */, Sparc::BPLZnapn, Convert__Reg1_1__Imm1_2, 0, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
2361
  { 203 /* brlz */, Sparc::BPLZnapt, Convert__Reg1_1__Imm1_2, 0, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
2362
  { 203 /* brlz */, Sparc::BPLZapn, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
2363
  { 203 /* brlz */, Sparc::BPLZapt, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
2364
  { 208 /* brnz */, Sparc::BPNZnapt, Convert__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm }, },
2365
  { 208 /* brnz */, Sparc::BPNZapt, Convert__Reg1_1__Imm1_2, 0, { MCK_a, MCK_IntRegs, MCK_Imm }, },
2366
  { 208 /* brnz */, Sparc::BPNZnapn, Convert__Reg1_1__Imm1_2, 0, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
2367
  { 208 /* brnz */, Sparc::BPNZnapt, Convert__Reg1_1__Imm1_2, 0, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
2368
  { 208 /* brnz */, Sparc::BPNZapn, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
2369
  { 208 /* brnz */, Sparc::BPNZapt, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
2370
  { 213 /* brz */, Sparc::BPZnapt, Convert__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm }, },
2371
  { 213 /* brz */, Sparc::BPZapt, Convert__Reg1_1__Imm1_2, 0, { MCK_a, MCK_IntRegs, MCK_Imm }, },
2372
  { 213 /* brz */, Sparc::BPZnapn, Convert__Reg1_1__Imm1_2, 0, { MCK_pn, MCK_IntRegs, MCK_Imm }, },
2373
  { 213 /* brz */, Sparc::BPZnapt, Convert__Reg1_1__Imm1_2, 0, { MCK_pt, MCK_IntRegs, MCK_Imm }, },
2374
  { 213 /* brz */, Sparc::BPZapn, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pn, MCK_IntRegs, MCK_Imm }, },
2375
  { 213 /* brz */, Sparc::BPZapt, Convert__Reg1_2__Imm1_3, 0, { MCK_a, MCK_pt, MCK_IntRegs, MCK_Imm }, },
2376
  { 217 /* bset */, Sparc::ORrr, Convert__Reg1_1__Reg1_1__Reg1_0, 0, { MCK_IntRegs, MCK_IntRegs }, },
2377
  { 217 /* bset */, Sparc::ORri, Convert__Reg1_1__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_IntRegs }, },
2378
  { 222 /* bshuffle */, Sparc::BSHUFFLE, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS2, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2379
  { 231 /* btog */, Sparc::XORrr, Convert__Reg1_1__Reg1_1__Reg1_0, 0, { MCK_IntRegs, MCK_IntRegs }, },
2380
  { 231 /* btog */, Sparc::XORri, Convert__Reg1_1__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_IntRegs }, },
2381
  { 236 /* btst */, Sparc::ANDCCrr, Convert__regG0__Reg1_1__Reg1_0, 0, { MCK_IntRegs, MCK_IntRegs }, },
2382
  { 236 /* btst */, Sparc::ANDCCri, Convert__regG0__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_IntRegs }, },
2383
  { 241 /* bvc */, Sparc::BCOND, Convert__Imm1_0__imm_95_15, 0, { MCK_Imm }, },
2384
  { 241 /* bvc */, Sparc::BPICC, Convert__Imm1_1__imm_95_15, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2385
  { 241 /* bvc */, Sparc::BPXCC, Convert__Imm1_1__imm_95_15, 0, { MCK__PCT_xcc, MCK_Imm }, },
2386
  { 241 /* bvc */, Sparc::BCONDA, Convert__Imm1_1__imm_95_15, 0, { MCK_a, MCK_Imm }, },
2387
  { 241 /* bvc */, Sparc::BPICCA, Convert__Imm1_2__imm_95_15, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2388
  { 241 /* bvc */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_15, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2389
  { 241 /* bvc */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_15, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2390
  { 241 /* bvc */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_15, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2391
  { 241 /* bvc */, Sparc::BPICC, Convert__Imm1_2__imm_95_15, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2392
  { 241 /* bvc */, Sparc::BPXCC, Convert__Imm1_2__imm_95_15, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2393
  { 241 /* bvc */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_15, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2394
  { 241 /* bvc */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_15, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2395
  { 241 /* bvc */, Sparc::BPICCA, Convert__Imm1_3__imm_95_15, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2396
  { 241 /* bvc */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_15, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2397
  { 245 /* bvs */, Sparc::BCOND, Convert__Imm1_0__imm_95_7, 0, { MCK_Imm }, },
2398
  { 245 /* bvs */, Sparc::BPICC, Convert__Imm1_1__imm_95_7, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2399
  { 245 /* bvs */, Sparc::BPXCC, Convert__Imm1_1__imm_95_7, 0, { MCK__PCT_xcc, MCK_Imm }, },
2400
  { 245 /* bvs */, Sparc::BCONDA, Convert__Imm1_1__imm_95_7, 0, { MCK_a, MCK_Imm }, },
2401
  { 245 /* bvs */, Sparc::BPICCA, Convert__Imm1_2__imm_95_7, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2402
  { 245 /* bvs */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_7, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2403
  { 245 /* bvs */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_7, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2404
  { 245 /* bvs */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_7, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2405
  { 245 /* bvs */, Sparc::BPICC, Convert__Imm1_2__imm_95_7, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2406
  { 245 /* bvs */, Sparc::BPXCC, Convert__Imm1_2__imm_95_7, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2407
  { 245 /* bvs */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_7, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2408
  { 245 /* bvs */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_7, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2409
  { 245 /* bvs */, Sparc::BPICCA, Convert__Imm1_3__imm_95_7, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2410
  { 245 /* bvs */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_7, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2411
  { 249 /* bz */, Sparc::BCOND, Convert__Imm1_0__imm_95_1, 0, { MCK_Imm }, },
2412
  { 249 /* bz */, Sparc::BPICC, Convert__Imm1_1__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
2413
  { 249 /* bz */, Sparc::BPXCC, Convert__Imm1_1__imm_95_1, 0, { MCK__PCT_xcc, MCK_Imm }, },
2414
  { 249 /* bz */, Sparc::BCONDA, Convert__Imm1_1__imm_95_1, 0, { MCK_a, MCK_Imm }, },
2415
  { 249 /* bz */, Sparc::BPICCA, Convert__Imm1_2__imm_95_1, Feature_HasV9, { MCK_a, MCK__PCT_icc, MCK_Imm }, },
2416
  { 249 /* bz */, Sparc::BPXCCA, Convert__Imm1_2__imm_95_1, 0, { MCK_a, MCK__PCT_xcc, MCK_Imm }, },
2417
  { 249 /* bz */, Sparc::BPICCNT, Convert__Imm1_2__imm_95_1, Feature_HasV9, { MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2418
  { 249 /* bz */, Sparc::BPXCCNT, Convert__Imm1_2__imm_95_1, 0, { MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2419
  { 249 /* bz */, Sparc::BPICC, Convert__Imm1_2__imm_95_1, Feature_HasV9, { MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2420
  { 249 /* bz */, Sparc::BPXCC, Convert__Imm1_2__imm_95_1, 0, { MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2421
  { 249 /* bz */, Sparc::BPICCANT, Convert__Imm1_3__imm_95_1, Feature_HasV9, { MCK_a, MCK_pn, MCK__PCT_icc, MCK_Imm }, },
2422
  { 249 /* bz */, Sparc::BPXCCANT, Convert__Imm1_3__imm_95_1, 0, { MCK_a, MCK_pn, MCK__PCT_xcc, MCK_Imm }, },
2423
  { 249 /* bz */, Sparc::BPICCA, Convert__Imm1_3__imm_95_1, Feature_HasV9, { MCK_a, MCK_pt, MCK__PCT_icc, MCK_Imm }, },
2424
  { 249 /* bz */, Sparc::BPXCCA, Convert__Imm1_3__imm_95_1, 0, { MCK_a, MCK_pt, MCK__PCT_xcc, MCK_Imm }, },
2425
  { 252 /* call */, Sparc::CALL, Convert__Imm1_0, 0, { MCK_Imm }, },
2426
  { 252 /* call */, Sparc::JMPLri, Convert__regO7__MEMri2_0, 0, { MCK_MEMri }, },
2427
  { 252 /* call */, Sparc::JMPLrr, Convert__regO7__MEMrr2_0, 0, { MCK_MEMrr }, },
2428
  { 257 /* cas */, Sparc::CASrr, Convert__Reg1_4__Reg1_1__Reg1_3__Tie0, Feature_HasV9, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_IntRegs, MCK_IntRegs }, },
2429
  { 261 /* casx */, Sparc::CASXrr, Convert__Reg1_4__Reg1_1__Reg1_3__Tie0, 0, { MCK__91_, MCK_IntRegs, MCK__93_, MCK_IntRegs, MCK_IntRegs }, },
2430
  { 266 /* clr */, Sparc::ORrr, Convert__Reg1_0__regG0__regG0, 0, { MCK_IntRegs }, },
2431
  { 266 /* clr */, Sparc::STri, Convert__MEMri2_1__regG0, 0, { MCK__91_, MCK_MEMri, MCK__93_ }, },
2432
  { 266 /* clr */, Sparc::STrr, Convert__MEMrr2_1__regG0, 0, { MCK__91_, MCK_MEMrr, MCK__93_ }, },
2433
  { 270 /* clrb */, Sparc::STBri, Convert__MEMri2_1__regG0, 0, { MCK__91_, MCK_MEMri, MCK__93_ }, },
2434
  { 270 /* clrb */, Sparc::STBrr, Convert__MEMrr2_1__regG0, 0, { MCK__91_, MCK_MEMrr, MCK__93_ }, },
2435
  { 275 /* clrh */, Sparc::STHri, Convert__MEMri2_1__regG0, 0, { MCK__91_, MCK_MEMri, MCK__93_ }, },
2436
  { 275 /* clrh */, Sparc::STHrr, Convert__MEMrr2_1__regG0, 0, { MCK__91_, MCK_MEMrr, MCK__93_ }, },
2437
  { 280 /* cmask16 */, Sparc::CMASK16, Convert__Reg1_0, Feature_HasVIS3, { MCK_IntRegs }, },
2438
  { 288 /* cmask32 */, Sparc::CMASK32, Convert__Reg1_0, Feature_HasVIS3, { MCK_IntRegs }, },
2439
  { 296 /* cmask8 */, Sparc::CMASK8, Convert__Reg1_0, Feature_HasVIS3, { MCK_IntRegs }, },
2440
  { 303 /* cmp */, Sparc::CMPrr, Convert__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs }, },
2441
  { 303 /* cmp */, Sparc::CMPri, Convert__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm }, },
2442
  { 307 /* dec */, Sparc::SUBri, Convert__Reg1_0__Reg1_0__imm_95_1, 0, { MCK_IntRegs }, },
2443
  { 307 /* dec */, Sparc::SUBri, Convert__Reg1_1__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_IntRegs }, },
2444
  { 311 /* deccc */, Sparc::SUBCCri, Convert__Reg1_0__Reg1_0__imm_95_1, 0, { MCK_IntRegs }, },
2445
  { 311 /* deccc */, Sparc::SUBCCri, Convert__Reg1_1__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_IntRegs }, },
2446
  { 317 /* edge16 */, Sparc::EDGE16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2447
  { 324 /* edge16l */, Sparc::EDGE16L, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2448
  { 332 /* edge16ln */, Sparc::EDGE16LN, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2449
  { 341 /* edge16n */, Sparc::EDGE16N, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2450
  { 349 /* edge32 */, Sparc::EDGE32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2451
  { 356 /* edge32l */, Sparc::EDGE32L, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2452
  { 364 /* edge32ln */, Sparc::EDGE32LN, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2453
  { 373 /* edge32n */, Sparc::EDGE32N, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2454
  { 381 /* edge8 */, Sparc::EDGE8, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2455
  { 387 /* edge8l */, Sparc::EDGE8L, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2456
  { 394 /* edge8ln */, Sparc::EDGE8LN, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2457
  { 402 /* edge8n */, Sparc::EDGE8N, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS2, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
2458
  { 409 /* fabsd */, Sparc::FABSD, Convert__Reg1_1__Reg1_0, Feature_HasV9, { MCK_DFPRegs, MCK_DFPRegs }, },
2459
  { 415 /* fabsq */, Sparc::FABSQ, Convert__Reg1_1__Reg1_0, Feature_HasV9, { MCK_QFPRegs, MCK_QFPRegs }, },
2460
  { 421 /* fabss */, Sparc::FABSS, Convert__Reg1_1__Reg1_0, 0, { MCK_FPRegs, MCK_FPRegs }, },
2461
  { 427 /* faddd */, Sparc::FADDD, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2462
  { 433 /* faddq */, Sparc::FADDQ, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2463
  { 439 /* fadds */, Sparc::FADDS, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2464
  { 445 /* faligndata */, Sparc::FALIGNADATA, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2465
  { 456 /* fand */, Sparc::FAND, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2466
  { 461 /* fandnot1 */, Sparc::FANDNOT1, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2467
  { 470 /* fandnot1s */, Sparc::FANDNOT1S, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2468
  { 480 /* fandnot2 */, Sparc::FANDNOT2, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2469
  { 489 /* fandnot2s */, Sparc::FANDNOT2S, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2470
  { 499 /* fands */, Sparc::FANDS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2471
  { 505 /* fb */, Sparc::FBCOND, Convert__Imm1_0__imm_95_0, 0, { MCK_Imm }, },
2472
  { 505 /* fb */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_0, 0, { MCK_a, MCK_Imm }, },
2473
  { 505 /* fb */, Sparc::BPFCC, Convert__Imm1_1__imm_95_0__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2474
  { 505 /* fb */, Sparc::FBCOND, Convert__Imm1_1__Imm1_0, 0, { MCK_Imm, MCK_Imm }, },
2475
  { 505 /* fb */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_0__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2476
  { 505 /* fb */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_0__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2477
  { 505 /* fb */, Sparc::BPFCC, Convert__Imm1_2__imm_95_0__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2478
  { 505 /* fb */, Sparc::FBCONDA, Convert__Imm1_2__Imm1_0, 0, { MCK_Imm, MCK_a, MCK_Imm }, },
2479
  { 505 /* fb */, Sparc::BPFCC, Convert__Imm1_2__Imm1_0__Reg1_1, Feature_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_Imm }, },
2480
  { 505 /* fb */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_0__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2481
  { 505 /* fb */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_0__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2482
  { 505 /* fb */, Sparc::BPFCCA, Convert__Imm1_3__Imm1_0__Reg1_2, Feature_HasV9, { MCK_Imm, MCK_a, MCK_FCCRegs, MCK_Imm }, },
2483
  { 505 /* fb */, Sparc::BPFCCNT, Convert__Imm1_3__Imm1_0__Reg1_2, Feature_HasV9, { MCK_Imm, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2484
  { 505 /* fb */, Sparc::BPFCCANT, Convert__Imm1_4__Imm1_0__Reg1_3, Feature_HasV9, { MCK_Imm, MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2485
  { 508 /* fba */, Sparc::FBCOND, Convert__Imm1_0__imm_95_0, 0, { MCK_Imm }, },
2486
  { 508 /* fba */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_0, 0, { MCK_a, MCK_Imm }, },
2487
  { 508 /* fba */, Sparc::BPFCC, Convert__Imm1_1__imm_95_0__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2488
  { 508 /* fba */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_0__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2489
  { 508 /* fba */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_0__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2490
  { 508 /* fba */, Sparc::BPFCC, Convert__Imm1_2__imm_95_0__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2491
  { 508 /* fba */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_0__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2492
  { 508 /* fba */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_0__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2493
  { 512 /* fbe */, Sparc::FBCOND, Convert__Imm1_0__imm_95_9, 0, { MCK_Imm }, },
2494
  { 512 /* fbe */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_9, 0, { MCK_a, MCK_Imm }, },
2495
  { 512 /* fbe */, Sparc::BPFCC, Convert__Imm1_1__imm_95_9__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2496
  { 512 /* fbe */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_9__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2497
  { 512 /* fbe */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_9__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2498
  { 512 /* fbe */, Sparc::BPFCC, Convert__Imm1_2__imm_95_9__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2499
  { 512 /* fbe */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_9__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2500
  { 512 /* fbe */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_9__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2501
  { 516 /* fbg */, Sparc::FBCOND, Convert__Imm1_0__imm_95_6, 0, { MCK_Imm }, },
2502
  { 516 /* fbg */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_6, 0, { MCK_a, MCK_Imm }, },
2503
  { 516 /* fbg */, Sparc::BPFCC, Convert__Imm1_1__imm_95_6__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2504
  { 516 /* fbg */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_6__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2505
  { 516 /* fbg */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_6__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2506
  { 516 /* fbg */, Sparc::BPFCC, Convert__Imm1_2__imm_95_6__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2507
  { 516 /* fbg */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_6__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2508
  { 516 /* fbg */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_6__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2509
  { 520 /* fbge */, Sparc::FBCOND, Convert__Imm1_0__imm_95_11, 0, { MCK_Imm }, },
2510
  { 520 /* fbge */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_11, 0, { MCK_a, MCK_Imm }, },
2511
  { 520 /* fbge */, Sparc::BPFCC, Convert__Imm1_1__imm_95_11__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2512
  { 520 /* fbge */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_11__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2513
  { 520 /* fbge */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_11__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2514
  { 520 /* fbge */, Sparc::BPFCC, Convert__Imm1_2__imm_95_11__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2515
  { 520 /* fbge */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_11__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2516
  { 520 /* fbge */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_11__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2517
  { 525 /* fbl */, Sparc::FBCOND, Convert__Imm1_0__imm_95_4, 0, { MCK_Imm }, },
2518
  { 525 /* fbl */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_4, 0, { MCK_a, MCK_Imm }, },
2519
  { 525 /* fbl */, Sparc::BPFCC, Convert__Imm1_1__imm_95_4__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2520
  { 525 /* fbl */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_4__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2521
  { 525 /* fbl */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_4__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2522
  { 525 /* fbl */, Sparc::BPFCC, Convert__Imm1_2__imm_95_4__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2523
  { 525 /* fbl */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_4__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2524
  { 525 /* fbl */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_4__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2525
  { 529 /* fble */, Sparc::FBCOND, Convert__Imm1_0__imm_95_13, 0, { MCK_Imm }, },
2526
  { 529 /* fble */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_13, 0, { MCK_a, MCK_Imm }, },
2527
  { 529 /* fble */, Sparc::BPFCC, Convert__Imm1_1__imm_95_13__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2528
  { 529 /* fble */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_13__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2529
  { 529 /* fble */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_13__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2530
  { 529 /* fble */, Sparc::BPFCC, Convert__Imm1_2__imm_95_13__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2531
  { 529 /* fble */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_13__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2532
  { 529 /* fble */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_13__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2533
  { 534 /* fblg */, Sparc::FBCOND, Convert__Imm1_0__imm_95_2, 0, { MCK_Imm }, },
2534
  { 534 /* fblg */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_2, 0, { MCK_a, MCK_Imm }, },
2535
  { 534 /* fblg */, Sparc::BPFCC, Convert__Imm1_1__imm_95_2__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2536
  { 534 /* fblg */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_2__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2537
  { 534 /* fblg */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_2__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2538
  { 534 /* fblg */, Sparc::BPFCC, Convert__Imm1_2__imm_95_2__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2539
  { 534 /* fblg */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_2__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2540
  { 534 /* fblg */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_2__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2541
  { 539 /* fbn */, Sparc::FBCOND, Convert__Imm1_0__imm_95_8, 0, { MCK_Imm }, },
2542
  { 539 /* fbn */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_8, 0, { MCK_a, MCK_Imm }, },
2543
  { 539 /* fbn */, Sparc::BPFCC, Convert__Imm1_1__imm_95_8__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2544
  { 539 /* fbn */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_8__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2545
  { 539 /* fbn */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_8__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2546
  { 539 /* fbn */, Sparc::BPFCC, Convert__Imm1_2__imm_95_8__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2547
  { 539 /* fbn */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_8__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2548
  { 539 /* fbn */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_8__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2549
  { 543 /* fbne */, Sparc::FBCOND, Convert__Imm1_0__imm_95_1, 0, { MCK_Imm }, },
2550
  { 543 /* fbne */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_1, 0, { MCK_a, MCK_Imm }, },
2551
  { 543 /* fbne */, Sparc::BPFCC, Convert__Imm1_1__imm_95_1__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2552
  { 543 /* fbne */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_1__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2553
  { 543 /* fbne */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_1__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2554
  { 543 /* fbne */, Sparc::BPFCC, Convert__Imm1_2__imm_95_1__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2555
  { 543 /* fbne */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_1__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2556
  { 543 /* fbne */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_1__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2557
  { 548 /* fbnz */, Sparc::FBCOND, Convert__Imm1_0__imm_95_1, 0, { MCK_Imm }, },
2558
  { 548 /* fbnz */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_1, 0, { MCK_a, MCK_Imm }, },
2559
  { 548 /* fbnz */, Sparc::BPFCC, Convert__Imm1_1__imm_95_1__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2560
  { 548 /* fbnz */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_1__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2561
  { 548 /* fbnz */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_1__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2562
  { 548 /* fbnz */, Sparc::BPFCC, Convert__Imm1_2__imm_95_1__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2563
  { 548 /* fbnz */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_1__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2564
  { 548 /* fbnz */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_1__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2565
  { 553 /* fbo */, Sparc::FBCOND, Convert__Imm1_0__imm_95_15, 0, { MCK_Imm }, },
2566
  { 553 /* fbo */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_15, 0, { MCK_a, MCK_Imm }, },
2567
  { 553 /* fbo */, Sparc::BPFCC, Convert__Imm1_1__imm_95_15__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2568
  { 553 /* fbo */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_15__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2569
  { 553 /* fbo */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_15__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2570
  { 553 /* fbo */, Sparc::BPFCC, Convert__Imm1_2__imm_95_15__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2571
  { 553 /* fbo */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_15__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2572
  { 553 /* fbo */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_15__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2573
  { 557 /* fbu */, Sparc::FBCOND, Convert__Imm1_0__imm_95_7, 0, { MCK_Imm }, },
2574
  { 557 /* fbu */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_7, 0, { MCK_a, MCK_Imm }, },
2575
  { 557 /* fbu */, Sparc::BPFCC, Convert__Imm1_1__imm_95_7__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2576
  { 557 /* fbu */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_7__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2577
  { 557 /* fbu */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_7__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2578
  { 557 /* fbu */, Sparc::BPFCC, Convert__Imm1_2__imm_95_7__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2579
  { 557 /* fbu */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_7__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2580
  { 557 /* fbu */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_7__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2581
  { 561 /* fbue */, Sparc::FBCOND, Convert__Imm1_0__imm_95_10, 0, { MCK_Imm }, },
2582
  { 561 /* fbue */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_10, 0, { MCK_a, MCK_Imm }, },
2583
  { 561 /* fbue */, Sparc::BPFCC, Convert__Imm1_1__imm_95_10__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2584
  { 561 /* fbue */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_10__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2585
  { 561 /* fbue */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_10__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2586
  { 561 /* fbue */, Sparc::BPFCC, Convert__Imm1_2__imm_95_10__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2587
  { 561 /* fbue */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_10__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2588
  { 561 /* fbue */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_10__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2589
  { 566 /* fbug */, Sparc::FBCOND, Convert__Imm1_0__imm_95_5, 0, { MCK_Imm }, },
2590
  { 566 /* fbug */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_5, 0, { MCK_a, MCK_Imm }, },
2591
  { 566 /* fbug */, Sparc::BPFCC, Convert__Imm1_1__imm_95_5__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2592
  { 566 /* fbug */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_5__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2593
  { 566 /* fbug */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_5__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2594
  { 566 /* fbug */, Sparc::BPFCC, Convert__Imm1_2__imm_95_5__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2595
  { 566 /* fbug */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_5__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2596
  { 566 /* fbug */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_5__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2597
  { 571 /* fbuge */, Sparc::FBCOND, Convert__Imm1_0__imm_95_12, 0, { MCK_Imm }, },
2598
  { 571 /* fbuge */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_12, 0, { MCK_a, MCK_Imm }, },
2599
  { 571 /* fbuge */, Sparc::BPFCC, Convert__Imm1_1__imm_95_12__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2600
  { 571 /* fbuge */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_12__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2601
  { 571 /* fbuge */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_12__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2602
  { 571 /* fbuge */, Sparc::BPFCC, Convert__Imm1_2__imm_95_12__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2603
  { 571 /* fbuge */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_12__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2604
  { 571 /* fbuge */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_12__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2605
  { 577 /* fbul */, Sparc::FBCOND, Convert__Imm1_0__imm_95_3, 0, { MCK_Imm }, },
2606
  { 577 /* fbul */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_3, 0, { MCK_a, MCK_Imm }, },
2607
  { 577 /* fbul */, Sparc::BPFCC, Convert__Imm1_1__imm_95_3__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2608
  { 577 /* fbul */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_3__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2609
  { 577 /* fbul */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_3__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2610
  { 577 /* fbul */, Sparc::BPFCC, Convert__Imm1_2__imm_95_3__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2611
  { 577 /* fbul */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_3__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2612
  { 577 /* fbul */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_3__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2613
  { 582 /* fbule */, Sparc::FBCOND, Convert__Imm1_0__imm_95_14, 0, { MCK_Imm }, },
2614
  { 582 /* fbule */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_14, 0, { MCK_a, MCK_Imm }, },
2615
  { 582 /* fbule */, Sparc::BPFCC, Convert__Imm1_1__imm_95_14__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2616
  { 582 /* fbule */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_14__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2617
  { 582 /* fbule */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_14__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2618
  { 582 /* fbule */, Sparc::BPFCC, Convert__Imm1_2__imm_95_14__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2619
  { 582 /* fbule */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_14__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2620
  { 582 /* fbule */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_14__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2621
  { 588 /* fbz */, Sparc::FBCOND, Convert__Imm1_0__imm_95_9, 0, { MCK_Imm }, },
2622
  { 588 /* fbz */, Sparc::FBCONDA, Convert__Imm1_1__imm_95_9, 0, { MCK_a, MCK_Imm }, },
2623
  { 588 /* fbz */, Sparc::BPFCC, Convert__Imm1_1__imm_95_9__Reg1_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm }, },
2624
  { 588 /* fbz */, Sparc::BPFCCA, Convert__Imm1_2__imm_95_9__Reg1_1, Feature_HasV9, { MCK_a, MCK_FCCRegs, MCK_Imm }, },
2625
  { 588 /* fbz */, Sparc::BPFCCNT, Convert__Imm1_2__imm_95_9__Reg1_1, Feature_HasV9, { MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2626
  { 588 /* fbz */, Sparc::BPFCC, Convert__Imm1_2__imm_95_9__Reg1_1, Feature_HasV9, { MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2627
  { 588 /* fbz */, Sparc::BPFCCANT, Convert__Imm1_3__imm_95_9__Reg1_2, Feature_HasV9, { MCK_a, MCK_pn, MCK_FCCRegs, MCK_Imm }, },
2628
  { 588 /* fbz */, Sparc::BPFCCA, Convert__Imm1_3__imm_95_9__Reg1_2, Feature_HasV9, { MCK_a, MCK_pt, MCK_FCCRegs, MCK_Imm }, },
2629
  { 592 /* fchksm16 */, Sparc::FCHKSM16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2630
  { 601 /* fcmpd */, Sparc::V9FCMPD, Convert__regFCC0__Reg1_0__Reg1_1, 0, { MCK_DFPRegs, MCK_DFPRegs }, },
2631
  { 601 /* fcmpd */, Sparc::V9FCMPD, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2632
  { 607 /* fcmped */, Sparc::V9FCMPED, Convert__regFCC0__Reg1_0__Reg1_1, 0, { MCK_DFPRegs, MCK_DFPRegs }, },
2633
  { 607 /* fcmped */, Sparc::V9FCMPED, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2634
  { 614 /* fcmpeq */, Sparc::V9FCMPEQ, Convert__regFCC0__Reg1_0__Reg1_1, 0, { MCK_QFPRegs, MCK_QFPRegs }, },
2635
  { 614 /* fcmpeq */, Sparc::V9FCMPEQ, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2636
  { 621 /* fcmpeq16 */, Sparc::FCMPEQ16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
2637
  { 630 /* fcmpeq32 */, Sparc::FCMPEQ32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
2638
  { 639 /* fcmpes */, Sparc::V9FCMPES, Convert__regFCC0__Reg1_0__Reg1_1, 0, { MCK_FPRegs, MCK_FPRegs }, },
2639
  { 639 /* fcmpes */, Sparc::V9FCMPES, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2640
  { 646 /* fcmpgt16 */, Sparc::FCMPGT16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
2641
  { 655 /* fcmpgt32 */, Sparc::FCMPGT32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
2642
  { 664 /* fcmple16 */, Sparc::FCMPLE16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
2643
  { 673 /* fcmple32 */, Sparc::FCMPLE32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
2644
  { 682 /* fcmpne16 */, Sparc::FCMPNE16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
2645
  { 691 /* fcmpne32 */, Sparc::FCMPNE32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_IntRegs }, },
2646
  { 700 /* fcmpq */, Sparc::V9FCMPQ, Convert__regFCC0__Reg1_0__Reg1_1, 0, { MCK_QFPRegs, MCK_QFPRegs }, },
2647
  { 700 /* fcmpq */, Sparc::V9FCMPQ, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2648
  { 706 /* fcmps */, Sparc::V9FCMPS, Convert__regFCC0__Reg1_0__Reg1_1, 0, { MCK_FPRegs, MCK_FPRegs }, },
2649
  { 706 /* fcmps */, Sparc::V9FCMPS, Convert__Reg1_0__Reg1_1__Reg1_2, 0, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2650
  { 712 /* fdivd */, Sparc::FDIVD, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2651
  { 718 /* fdivq */, Sparc::FDIVQ, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2652
  { 724 /* fdivs */, Sparc::FDIVS, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2653
  { 730 /* fdmulq */, Sparc::FDMULQ, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_DFPRegs, MCK_DFPRegs, MCK_QFPRegs }, },
2654
  { 737 /* fdtoi */, Sparc::FDTOI, Convert__Reg1_1__Reg1_0, 0, { MCK_DFPRegs, MCK_FPRegs }, },
2655
  { 743 /* fdtoq */, Sparc::FDTOQ, Convert__Reg1_1__Reg1_0, 0, { MCK_DFPRegs, MCK_QFPRegs }, },
2656
  { 749 /* fdtos */, Sparc::FDTOS, Convert__Reg1_1__Reg1_0, 0, { MCK_DFPRegs, MCK_FPRegs }, },
2657
  { 755 /* fdtox */, Sparc::FDTOX, Convert__Reg1_1__Reg1_0, 0, { MCK_DFPRegs, MCK_DFPRegs }, },
2658
  { 761 /* fexpand */, Sparc::FEXPAND, Convert__Reg1_1__Reg1_0, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
2659
  { 769 /* fhaddd */, Sparc::FHADDD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2660
  { 776 /* fhadds */, Sparc::FHADDS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2661
  { 783 /* fhsubd */, Sparc::FHSUBD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2662
  { 790 /* fhsubs */, Sparc::FHSUBS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2663
  { 797 /* fitod */, Sparc::FITOD, Convert__Reg1_1__Reg1_0, 0, { MCK_FPRegs, MCK_DFPRegs }, },
2664
  { 803 /* fitoq */, Sparc::FITOQ, Convert__Reg1_1__Reg1_0, 0, { MCK_FPRegs, MCK_QFPRegs }, },
2665
  { 809 /* fitos */, Sparc::FITOS, Convert__Reg1_1__Reg1_0, 0, { MCK_FPRegs, MCK_FPRegs }, },
2666
  { 815 /* flcmpd */, Sparc::FLCMPD, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasVIS3, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2667
  { 822 /* flcmps */, Sparc::FLCMPS, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_HasVIS3, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2668
  { 829 /* flush */, Sparc::FLUSH, Convert_NoOperands, 0, {  }, },
2669
  { 829 /* flush */, Sparc::FLUSH, Convert_NoOperands, 0, { MCK__PCT_g0 }, },
2670
  { 829 /* flush */, Sparc::FLUSHri, Convert__MEMri2_0, 0, { MCK_MEMri }, },
2671
  { 829 /* flush */, Sparc::FLUSHrr, Convert__MEMrr2_0, 0, { MCK_MEMrr }, },
2672
  { 835 /* flushw */, Sparc::FLUSHW, Convert_NoOperands, Feature_HasV9, {  }, },
2673
  { 842 /* fmean16 */, Sparc::FMEAN16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2674
  { 850 /* fmovd */, Sparc::FMOVD, Convert__Reg1_1__Reg1_0, Feature_HasV9, { MCK_DFPRegs, MCK_DFPRegs }, },
2675
  { 850 /* fmovd */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2676
  { 850 /* fmovd */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2677
  { 850 /* fmovd */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2678
  { 850 /* fmovd */, Sparc::FMOVD_FCC, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK__PCT_fcc0, MCK_DFPRegs, MCK_DFPRegs }, },
2679
  { 850 /* fmovd */, Sparc::FMOVD_ICC, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2680
  { 850 /* fmovd */, Sparc::FMOVD_XCC, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, 0, { MCK_Imm, MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2681
  { 850 /* fmovd */, Sparc::V9FMOVD_FCC, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2682
  { 856 /* fmovda */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2683
  { 856 /* fmovda */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2684
  { 856 /* fmovda */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2685
  { 863 /* fmovdcc */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2686
  { 863 /* fmovdcc */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2687
  { 871 /* fmovdcs */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2688
  { 871 /* fmovdcs */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2689
  { 879 /* fmovde */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2690
  { 879 /* fmovde */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2691
  { 879 /* fmovde */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2692
  { 886 /* fmovdeq */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2693
  { 886 /* fmovdeq */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2694
  { 894 /* fmovdg */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_10, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2695
  { 894 /* fmovdg */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_10, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2696
  { 894 /* fmovdg */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_6, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2697
  { 901 /* fmovdge */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_11, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2698
  { 901 /* fmovdge */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_11, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2699
  { 901 /* fmovdge */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_11, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2700
  { 909 /* fmovdgeu */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2701
  { 909 /* fmovdgeu */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2702
  { 918 /* fmovdgu */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_12, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2703
  { 918 /* fmovdgu */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_12, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2704
  { 926 /* fmovdl */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_3, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2705
  { 926 /* fmovdl */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_3, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2706
  { 926 /* fmovdl */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_4, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2707
  { 933 /* fmovdle */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_2, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2708
  { 933 /* fmovdle */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_2, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2709
  { 933 /* fmovdle */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2710
  { 941 /* fmovdleu */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_4, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2711
  { 941 /* fmovdleu */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_4, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2712
  { 950 /* fmovdlg */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_2, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2713
  { 958 /* fmovdlu */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2714
  { 958 /* fmovdlu */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2715
  { 966 /* fmovdn */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2716
  { 966 /* fmovdn */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_0, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2717
  { 966 /* fmovdn */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2718
  { 973 /* fmovdne */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2719
  { 973 /* fmovdne */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2720
  { 973 /* fmovdne */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2721
  { 981 /* fmovdneg */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_6, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2722
  { 981 /* fmovdneg */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_6, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2723
  { 990 /* fmovdnz */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2724
  { 990 /* fmovdnz */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2725
  { 990 /* fmovdnz */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2726
  { 998 /* fmovdo */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_15, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2727
  { 1005 /* fmovdpos */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_14, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2728
  { 1005 /* fmovdpos */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_14, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2729
  { 1014 /* fmovdu */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_7, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2730
  { 1021 /* fmovdue */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_10, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2731
  { 1029 /* fmovdug */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2732
  { 1037 /* fmovduge */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_12, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2733
  { 1046 /* fmovdul */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_3, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2734
  { 1054 /* fmovdule */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_14, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2735
  { 1063 /* fmovdvc */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_15, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2736
  { 1063 /* fmovdvc */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_15, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2737
  { 1071 /* fmovdvs */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_7, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2738
  { 1071 /* fmovdvs */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_7, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2739
  { 1079 /* fmovdz */, Sparc::FMOVD_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_DFPRegs, MCK_DFPRegs }, },
2740
  { 1079 /* fmovdz */, Sparc::FMOVD_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_DFPRegs, MCK_DFPRegs }, },
2741
  { 1079 /* fmovdz */, Sparc::V9FMOVD_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK_FCCRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2742
  { 1086 /* fmovq */, Sparc::FMOVQ, Convert__Reg1_1__Reg1_0, Feature_HasV9, { MCK_QFPRegs, MCK_QFPRegs }, },
2743
  { 1086 /* fmovq */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2744
  { 1086 /* fmovq */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2745
  { 1086 /* fmovq */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2746
  { 1086 /* fmovq */, Sparc::FMOVQ_FCC, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK__PCT_fcc0, MCK_QFPRegs, MCK_QFPRegs }, },
2747
  { 1086 /* fmovq */, Sparc::FMOVQ_ICC, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2748
  { 1086 /* fmovq */, Sparc::FMOVQ_XCC, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, 0, { MCK_Imm, MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2749
  { 1086 /* fmovq */, Sparc::V9FMOVQ_FCC, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2750
  { 1092 /* fmovqa */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2751
  { 1092 /* fmovqa */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2752
  { 1092 /* fmovqa */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2753
  { 1099 /* fmovqcc */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2754
  { 1099 /* fmovqcc */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2755
  { 1107 /* fmovqcs */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2756
  { 1107 /* fmovqcs */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2757
  { 1115 /* fmovqe */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2758
  { 1115 /* fmovqe */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2759
  { 1115 /* fmovqe */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2760
  { 1122 /* fmovqeq */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2761
  { 1122 /* fmovqeq */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2762
  { 1130 /* fmovqg */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_10, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2763
  { 1130 /* fmovqg */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_10, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2764
  { 1130 /* fmovqg */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_6, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2765
  { 1137 /* fmovqge */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_11, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2766
  { 1137 /* fmovqge */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_11, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2767
  { 1137 /* fmovqge */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_11, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2768
  { 1145 /* fmovqgeu */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2769
  { 1145 /* fmovqgeu */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2770
  { 1154 /* fmovqgu */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_12, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2771
  { 1154 /* fmovqgu */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_12, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2772
  { 1162 /* fmovql */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_3, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2773
  { 1162 /* fmovql */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_3, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2774
  { 1162 /* fmovql */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_4, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2775
  { 1169 /* fmovqle */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_2, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2776
  { 1169 /* fmovqle */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_2, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2777
  { 1169 /* fmovqle */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2778
  { 1177 /* fmovqleu */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_4, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2779
  { 1177 /* fmovqleu */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_4, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2780
  { 1186 /* fmovqlg */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_2, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2781
  { 1194 /* fmovqlu */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2782
  { 1194 /* fmovqlu */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2783
  { 1202 /* fmovqn */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2784
  { 1202 /* fmovqn */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_0, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2785
  { 1202 /* fmovqn */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2786
  { 1209 /* fmovqne */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2787
  { 1209 /* fmovqne */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2788
  { 1209 /* fmovqne */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2789
  { 1217 /* fmovqneg */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_6, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2790
  { 1217 /* fmovqneg */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_6, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2791
  { 1226 /* fmovqnz */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2792
  { 1226 /* fmovqnz */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2793
  { 1226 /* fmovqnz */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2794
  { 1234 /* fmovqo */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_15, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2795
  { 1241 /* fmovqpos */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_14, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2796
  { 1241 /* fmovqpos */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_14, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2797
  { 1250 /* fmovqu */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_7, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2798
  { 1257 /* fmovque */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_10, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2799
  { 1265 /* fmovqug */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2800
  { 1273 /* fmovquge */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_12, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2801
  { 1282 /* fmovqul */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_3, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2802
  { 1290 /* fmovqule */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_14, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2803
  { 1299 /* fmovqvc */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_15, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2804
  { 1299 /* fmovqvc */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_15, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2805
  { 1307 /* fmovqvs */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_7, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2806
  { 1307 /* fmovqvs */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_7, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2807
  { 1315 /* fmovqz */, Sparc::FMOVQ_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_QFPRegs, MCK_QFPRegs }, },
2808
  { 1315 /* fmovqz */, Sparc::FMOVQ_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_QFPRegs, MCK_QFPRegs }, },
2809
  { 1315 /* fmovqz */, Sparc::V9FMOVQ_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK_FCCRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2810
  { 1322 /* fmovrdgez */, Sparc::FMOVRGEZD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2811
  { 1332 /* fmovrdgz */, Sparc::FMOVRGZD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2812
  { 1341 /* fmovrdlez */, Sparc::FMOVRLEZD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2813
  { 1351 /* fmovrdlz */, Sparc::FMOVRLZD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2814
  { 1360 /* fmovrdnz */, Sparc::FMOVRNZD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2815
  { 1369 /* fmovrdz */, Sparc::FMOVRZD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2816
  { 1377 /* fmovrqgez */, Sparc::FMOVRGEZQ, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2817
  { 1387 /* fmovrqgz */, Sparc::FMOVRGZQ, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2818
  { 1396 /* fmovrqlez */, Sparc::FMOVRLEZQ, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2819
  { 1406 /* fmovrqlz */, Sparc::FMOVRLZQ, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2820
  { 1415 /* fmovrqnz */, Sparc::FMOVRNZQ, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2821
  { 1424 /* fmovrqz */, Sparc::FMOVRZQ, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2822
  { 1432 /* fmovrsgez */, Sparc::FMOVRGEZS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2823
  { 1442 /* fmovrsgz */, Sparc::FMOVRGZS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2824
  { 1451 /* fmovrslez */, Sparc::FMOVRLEZS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2825
  { 1461 /* fmovrslz */, Sparc::FMOVRLZS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2826
  { 1470 /* fmovrsnz */, Sparc::FMOVRNZS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2827
  { 1479 /* fmovrsz */, Sparc::FMOVRZS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_FPRegs, MCK_FPRegs }, },
2828
  { 1487 /* fmovs */, Sparc::FMOVS, Convert__Reg1_1__Reg1_0, 0, { MCK_FPRegs, MCK_FPRegs }, },
2829
  { 1487 /* fmovs */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2830
  { 1487 /* fmovs */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2831
  { 1487 /* fmovs */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2832
  { 1487 /* fmovs */, Sparc::FMOVS_FCC, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK__PCT_fcc0, MCK_FPRegs, MCK_FPRegs }, },
2833
  { 1487 /* fmovs */, Sparc::FMOVS_ICC, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2834
  { 1487 /* fmovs */, Sparc::FMOVS_XCC, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, 0, { MCK_Imm, MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2835
  { 1487 /* fmovs */, Sparc::V9FMOVS_FCC, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2836
  { 1493 /* fmovsa */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2837
  { 1493 /* fmovsa */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2838
  { 1493 /* fmovsa */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2839
  { 1500 /* fmovscc */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2840
  { 1500 /* fmovscc */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2841
  { 1508 /* fmovscs */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2842
  { 1508 /* fmovscs */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2843
  { 1516 /* fmovse */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2844
  { 1516 /* fmovse */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2845
  { 1516 /* fmovse */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2846
  { 1523 /* fmovseq */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2847
  { 1523 /* fmovseq */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2848
  { 1531 /* fmovsg */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_10, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2849
  { 1531 /* fmovsg */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_10, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2850
  { 1531 /* fmovsg */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_6, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2851
  { 1538 /* fmovsge */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_11, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2852
  { 1538 /* fmovsge */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_11, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2853
  { 1538 /* fmovsge */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_11, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2854
  { 1546 /* fmovsgeu */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2855
  { 1546 /* fmovsgeu */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2856
  { 1555 /* fmovsgu */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_12, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2857
  { 1555 /* fmovsgu */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_12, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2858
  { 1563 /* fmovsl */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_3, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2859
  { 1563 /* fmovsl */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_3, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2860
  { 1563 /* fmovsl */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_4, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2861
  { 1570 /* fmovsle */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_2, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2862
  { 1570 /* fmovsle */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_2, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2863
  { 1570 /* fmovsle */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2864
  { 1578 /* fmovsleu */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_4, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2865
  { 1578 /* fmovsleu */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_4, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2866
  { 1587 /* fmovslg */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_2, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2867
  { 1595 /* fmovslu */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2868
  { 1595 /* fmovslu */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2869
  { 1603 /* fmovsn */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2870
  { 1603 /* fmovsn */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_0, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2871
  { 1603 /* fmovsn */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2872
  { 1610 /* fmovsne */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2873
  { 1610 /* fmovsne */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2874
  { 1610 /* fmovsne */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2875
  { 1618 /* fmovsneg */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_6, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2876
  { 1618 /* fmovsneg */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_6, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2877
  { 1627 /* fmovsnz */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2878
  { 1627 /* fmovsnz */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2879
  { 1627 /* fmovsnz */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2880
  { 1635 /* fmovso */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_15, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2881
  { 1642 /* fmovspos */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_14, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2882
  { 1642 /* fmovspos */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_14, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2883
  { 1651 /* fmovsu */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_7, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2884
  { 1658 /* fmovsue */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_10, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2885
  { 1666 /* fmovsug */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2886
  { 1674 /* fmovsuge */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_12, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2887
  { 1683 /* fmovsul */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_3, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2888
  { 1691 /* fmovsule */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_14, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2889
  { 1700 /* fmovsvc */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_15, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2890
  { 1700 /* fmovsvc */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_15, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2891
  { 1708 /* fmovsvs */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_7, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2892
  { 1708 /* fmovsvs */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_7, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2893
  { 1716 /* fmovsz */, Sparc::FMOVS_ICC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_FPRegs, MCK_FPRegs }, },
2894
  { 1716 /* fmovsz */, Sparc::FMOVS_XCC, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_FPRegs, MCK_FPRegs }, },
2895
  { 1716 /* fmovsz */, Sparc::V9FMOVS_FCC, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK_FCCRegs, MCK_FPRegs, MCK_FPRegs }, },
2896
  { 1723 /* fmul8sux16 */, Sparc::FMUL8SUX16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2897
  { 1734 /* fmul8ulx16 */, Sparc::FMUL8ULX16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2898
  { 1745 /* fmul8x16 */, Sparc::FMUL8X16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2899
  { 1754 /* fmul8x16al */, Sparc::FMUL8X16AL, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2900
  { 1765 /* fmul8x16au */, Sparc::FMUL8X16AU, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2901
  { 1776 /* fmuld */, Sparc::FMULD, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2902
  { 1782 /* fmuld8sux16 */, Sparc::FMULD8SUX16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2903
  { 1794 /* fmuld8ulx16 */, Sparc::FMULD8ULX16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2904
  { 1806 /* fmulq */, Sparc::FMULQ, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2905
  { 1812 /* fmuls */, Sparc::FMULS, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2906
  { 1818 /* fnaddd */, Sparc::FNADDD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2907
  { 1825 /* fnadds */, Sparc::FNADDS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2908
  { 1832 /* fnand */, Sparc::FNAND, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2909
  { 1838 /* fnands */, Sparc::FNANDS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2910
  { 1845 /* fnegd */, Sparc::FNEGD, Convert__Reg1_1__Reg1_0, Feature_HasV9, { MCK_DFPRegs, MCK_DFPRegs }, },
2911
  { 1851 /* fnegq */, Sparc::FNEGQ, Convert__Reg1_1__Reg1_0, Feature_HasV9, { MCK_QFPRegs, MCK_QFPRegs }, },
2912
  { 1857 /* fnegs */, Sparc::FNEGS, Convert__Reg1_1__Reg1_0, 0, { MCK_FPRegs, MCK_FPRegs }, },
2913
  { 1863 /* fnhaddd */, Sparc::FNHADDD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2914
  { 1863 /* fnhaddd */, Sparc::FNMULD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2915
  { 1871 /* fnhadds */, Sparc::FNHADDS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2916
  { 1871 /* fnhadds */, Sparc::FNMULS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2917
  { 1871 /* fnhadds */, Sparc::FNSMULD, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2918
  { 1879 /* fnor */, Sparc::FNOR, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2919
  { 1884 /* fnors */, Sparc::FNORS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2920
  { 1890 /* fnot1 */, Sparc::FNOT1, Convert__Reg1_1__Reg1_0, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
2921
  { 1896 /* fnot1s */, Sparc::FNOT1S, Convert__Reg1_1__Reg1_0, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
2922
  { 1903 /* fnot2 */, Sparc::FNOT2, Convert__Reg1_1__Reg1_0, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
2923
  { 1909 /* fnot2s */, Sparc::FNOT2S, Convert__Reg1_1__Reg1_0, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
2924
  { 1916 /* fone */, Sparc::FONE, Convert__Reg1_0__Tie0, Feature_HasVIS, { MCK_DFPRegs }, },
2925
  { 1921 /* fones */, Sparc::FONES, Convert__Reg1_0__Tie0, Feature_HasVIS, { MCK_FPRegs }, },
2926
  { 1927 /* for */, Sparc::FOR, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2927
  { 1931 /* fornot1 */, Sparc::FORNOT1, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2928
  { 1939 /* fornot1s */, Sparc::FORNOT1S, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2929
  { 1948 /* fornot2 */, Sparc::FORNOT2, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2930
  { 1956 /* fornot2s */, Sparc::FORNOT2S, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2931
  { 1965 /* fors */, Sparc::FORS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2932
  { 1970 /* fpack16 */, Sparc::FPACK16, Convert__Reg1_1__Reg1_0, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
2933
  { 1978 /* fpack32 */, Sparc::FPACK32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2934
  { 1986 /* fpackfix */, Sparc::FPACKFIX, Convert__Reg1_1__Reg1_0, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
2935
  { 1995 /* fpadd16 */, Sparc::FPADD16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2936
  { 2003 /* fpadd16s */, Sparc::FPADD16S, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2937
  { 2012 /* fpadd32 */, Sparc::FPADD32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2938
  { 2020 /* fpadd32s */, Sparc::FPADD32S, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2939
  { 2029 /* fpadd64 */, Sparc::FPADD64, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2940
  { 2037 /* fpmerge */, Sparc::FPMERGE, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2941
  { 2045 /* fpsub16 */, Sparc::FPSUB16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2942
  { 2053 /* fpsub16S */, Sparc::FPSUB16S, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2943
  { 2062 /* fpsub32 */, Sparc::FPSUB32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2944
  { 2070 /* fpsub32S */, Sparc::FPSUB32S, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2945
  { 2079 /* fqtod */, Sparc::FQTOD, Convert__Reg1_1__Reg1_0, 0, { MCK_QFPRegs, MCK_DFPRegs }, },
2946
  { 2085 /* fqtoi */, Sparc::FQTOI, Convert__Reg1_1__Reg1_0, 0, { MCK_QFPRegs, MCK_FPRegs }, },
2947
  { 2091 /* fqtos */, Sparc::FQTOS, Convert__Reg1_1__Reg1_0, 0, { MCK_QFPRegs, MCK_FPRegs }, },
2948
  { 2097 /* fqtox */, Sparc::FQTOX, Convert__Reg1_1__Reg1_0, 0, { MCK_QFPRegs, MCK_DFPRegs }, },
2949
  { 2103 /* fslas16 */, Sparc::FSLAS16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2950
  { 2111 /* fslas32 */, Sparc::FSLAS32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2951
  { 2119 /* fsll16 */, Sparc::FSLL16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2952
  { 2126 /* fsll32 */, Sparc::FSLL32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2953
  { 2133 /* fsmuld */, Sparc::FSMULD, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_FPRegs, MCK_FPRegs, MCK_DFPRegs }, },
2954
  { 2140 /* fsqrtd */, Sparc::FSQRTD, Convert__Reg1_1__Reg1_0, 0, { MCK_DFPRegs, MCK_DFPRegs }, },
2955
  { 2147 /* fsqrtq */, Sparc::FSQRTQ, Convert__Reg1_1__Reg1_0, 0, { MCK_QFPRegs, MCK_QFPRegs }, },
2956
  { 2154 /* fsqrts */, Sparc::FSQRTS, Convert__Reg1_1__Reg1_0, 0, { MCK_FPRegs, MCK_FPRegs }, },
2957
  { 2161 /* fsra16 */, Sparc::FSRA16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2958
  { 2168 /* fsra32 */, Sparc::FSRA32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2959
  { 2175 /* fsrc1 */, Sparc::FSRC1, Convert__Reg1_1__Reg1_0, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
2960
  { 2181 /* fsrc1s */, Sparc::FSRC1S, Convert__Reg1_1__Reg1_0, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
2961
  { 2188 /* fsrc2 */, Sparc::FSRC2, Convert__Reg1_1__Reg1_0, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs }, },
2962
  { 2194 /* fsrc2s */, Sparc::FSRC2S, Convert__Reg1_1__Reg1_0, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs }, },
2963
  { 2201 /* fsrl16 */, Sparc::FSRL16, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2964
  { 2208 /* fsrl32 */, Sparc::FSRL32, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2965
  { 2215 /* fstod */, Sparc::FSTOD, Convert__Reg1_1__Reg1_0, 0, { MCK_FPRegs, MCK_DFPRegs }, },
2966
  { 2221 /* fstoi */, Sparc::FSTOI, Convert__Reg1_1__Reg1_0, 0, { MCK_FPRegs, MCK_FPRegs }, },
2967
  { 2227 /* fstoq */, Sparc::FSTOQ, Convert__Reg1_1__Reg1_0, 0, { MCK_FPRegs, MCK_QFPRegs }, },
2968
  { 2233 /* fstox */, Sparc::FSTOX, Convert__Reg1_1__Reg1_0, 0, { MCK_FPRegs, MCK_DFPRegs }, },
2969
  { 2239 /* fsubd */, Sparc::FSUBD, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2970
  { 2245 /* fsubq */, Sparc::FSUBQ, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_QFPRegs, MCK_QFPRegs, MCK_QFPRegs }, },
2971
  { 2251 /* fsubs */, Sparc::FSUBS, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2972
  { 2257 /* fxnor */, Sparc::FXNOR, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2973
  { 2263 /* fxnors */, Sparc::FXNORS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2974
  { 2270 /* fxor */, Sparc::FXOR, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
2975
  { 2275 /* fxors */, Sparc::FXORS, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_FPRegs, MCK_FPRegs, MCK_FPRegs }, },
2976
  { 2281 /* fxtod */, Sparc::FXTOD, Convert__Reg1_1__Reg1_0, 0, { MCK_DFPRegs, MCK_DFPRegs }, },
2977
  { 2287 /* fxtoq */, Sparc::FXTOQ, Convert__Reg1_1__Reg1_0, 0, { MCK_DFPRegs, MCK_QFPRegs }, },
2978
  { 2293 /* fxtos */, Sparc::FXTOS, Convert__Reg1_1__Reg1_0, 0, { MCK_DFPRegs, MCK_FPRegs }, },
2979
  { 2299 /* fzero */, Sparc::FZERO, Convert__Reg1_0__Tie0, Feature_HasVIS, { MCK_DFPRegs }, },
2980
  { 2305 /* fzeros */, Sparc::FZEROS, Convert__Reg1_0__Tie0, Feature_HasVIS, { MCK_FPRegs }, },
2981
  { 2312 /* inc */, Sparc::ADDri, Convert__Reg1_0__Reg1_0__imm_95_1, 0, { MCK_IntRegs }, },
2982
  { 2312 /* inc */, Sparc::ADDri, Convert__Reg1_1__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_IntRegs }, },
2983
  { 2316 /* inccc */, Sparc::ADDCCri, Convert__Reg1_0__Reg1_0__imm_95_1, 0, { MCK_IntRegs }, },
2984
  { 2316 /* inccc */, Sparc::ADDCCri, Convert__Reg1_1__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_IntRegs }, },
2985
  { 2322 /* jmp */, Sparc::JMPLri, Convert__regG0__MEMri2_0, 0, { MCK_MEMri }, },
2986
  { 2322 /* jmp */, Sparc::JMPLrr, Convert__regG0__MEMrr2_0, 0, { MCK_MEMrr }, },
2987
  { 2326 /* jmpl */, Sparc::JMPLri, Convert__Reg1_1__MEMri2_0, 0, { MCK_MEMri, MCK_IntRegs }, },
2988
  { 2326 /* jmpl */, Sparc::JMPLrr, Convert__Reg1_1__MEMrr2_0, 0, { MCK_MEMrr, MCK_IntRegs }, },
2989
  { 2331 /* ld */, Sparc::LDFSRri, Convert__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_fsr }, },
2990
  { 2331 /* ld */, Sparc::LDFri, Convert__Reg1_3__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_FPRegs }, },
2991
  { 2331 /* ld */, Sparc::LDri, Convert__Reg1_3__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
2992
  { 2331 /* ld */, Sparc::LDFSRrr, Convert__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK__PCT_fsr }, },
2993
  { 2331 /* ld */, Sparc::LDFrr, Convert__Reg1_3__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_FPRegs }, },
2994
  { 2331 /* ld */, Sparc::LDrr, Convert__Reg1_3__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
2995
  { 2334 /* lda */, Sparc::LDFArr, Convert__Reg1_4__MEMrr2_1__Imm1_3, Feature_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm, MCK_FPRegs }, },
2996
  { 2334 /* lda */, Sparc::LDArr, Convert__Reg1_4__MEMrr2_1__Imm1_3, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm, MCK_IntRegs }, },
2997
  { 2338 /* ldd */, Sparc::LDDri, Convert__Reg1_3__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntPair }, },
2998
  { 2338 /* ldd */, Sparc::LDDFri, Convert__Reg1_3__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_DFPRegs }, },
2999
  { 2338 /* ldd */, Sparc::LDDrr, Convert__Reg1_3__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntPair }, },
3000
  { 2338 /* ldd */, Sparc::LDDFrr, Convert__Reg1_3__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_DFPRegs }, },
3001
  { 2342 /* ldda */, Sparc::LDDArr, Convert__Reg1_4__MEMrr2_1__Imm1_3, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm, MCK_IntPair }, },
3002
  { 2342 /* ldda */, Sparc::LDDFArr, Convert__Reg1_4__MEMrr2_1__Imm1_3, Feature_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm, MCK_DFPRegs }, },
3003
  { 2347 /* ldq */, Sparc::LDQFri, Convert__Reg1_3__MEMri2_1, Feature_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK_QFPRegs }, },
3004
  { 2347 /* ldq */, Sparc::LDQFrr, Convert__Reg1_3__MEMrr2_1, Feature_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_QFPRegs }, },
3005
  { 2351 /* ldqa */, Sparc::LDQFArr, Convert__Reg1_4__MEMrr2_1__Imm1_3, Feature_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm, MCK_QFPRegs }, },
3006
  { 2356 /* ldsb */, Sparc::LDSBri, Convert__Reg1_3__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
3007
  { 2356 /* ldsb */, Sparc::LDSBrr, Convert__Reg1_3__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
3008
  { 2361 /* ldsba */, Sparc::LDSBArr, Convert__Reg1_4__MEMrr2_1__Imm1_3, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm, MCK_IntRegs }, },
3009
  { 2367 /* ldsh */, Sparc::LDSHri, Convert__Reg1_3__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
3010
  { 2367 /* ldsh */, Sparc::LDSHrr, Convert__Reg1_3__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
3011
  { 2372 /* ldsha */, Sparc::LDSHArr, Convert__Reg1_4__MEMrr2_1__Imm1_3, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm, MCK_IntRegs }, },
3012
  { 2378 /* ldstub */, Sparc::LDSTUBri, Convert__Reg1_3__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
3013
  { 2378 /* ldstub */, Sparc::LDSTUBrr, Convert__Reg1_3__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
3014
  { 2385 /* ldstuba */, Sparc::LDSTUBArr, Convert__Reg1_4__MEMrr2_1__Imm1_3, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm, MCK_IntRegs }, },
3015
  { 2393 /* ldsw */, Sparc::LDSWri, Convert__Reg1_3__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
3016
  { 2393 /* ldsw */, Sparc::LDSWrr, Convert__Reg1_3__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
3017
  { 2398 /* ldub */, Sparc::LDUBri, Convert__Reg1_3__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
3018
  { 2398 /* ldub */, Sparc::LDUBrr, Convert__Reg1_3__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
3019
  { 2403 /* lduba */, Sparc::LDUBArr, Convert__Reg1_4__MEMrr2_1__Imm1_3, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm, MCK_IntRegs }, },
3020
  { 2409 /* lduh */, Sparc::LDUHri, Convert__Reg1_3__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
3021
  { 2409 /* lduh */, Sparc::LDUHrr, Convert__Reg1_3__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
3022
  { 2414 /* lduha */, Sparc::LDUHArr, Convert__Reg1_4__MEMrr2_1__Imm1_3, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm, MCK_IntRegs }, },
3023
  { 2420 /* ldx */, Sparc::LDXFSRri, Convert__MEMri2_1, Feature_HasV9, { MCK__91_, MCK_MEMri, MCK__93_, MCK__PCT_fsr }, },
3024
  { 2420 /* ldx */, Sparc::LDXri, Convert__Reg1_3__MEMri2_1, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
3025
  { 2420 /* ldx */, Sparc::LDXFSRrr, Convert__MEMrr2_1, Feature_HasV9, { MCK__91_, MCK_MEMrr, MCK__93_, MCK__PCT_fsr }, },
3026
  { 2420 /* ldx */, Sparc::LDXrr, Convert__Reg1_3__MEMrr2_1, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
3027
  { 2424 /* lzcnt */, Sparc::LZCNT, Convert__Reg1_1__Reg1_0, Feature_HasVIS3, { MCK_IntRegs, MCK_IntRegs }, },
3028
  { 2430 /* membar */, Sparc::MEMBARi, Convert__Imm1_0, Feature_HasV9, { MCK_Imm }, },
3029
  { 2437 /* mov */, Sparc::RDPSR, Convert__Reg1_1, 0, { MCK__PCT_psr, MCK_IntRegs }, },
3030
  { 2437 /* mov */, Sparc::RDTBR, Convert__Reg1_1, 0, { MCK__PCT_tbr, MCK_IntRegs }, },
3031
  { 2437 /* mov */, Sparc::RDWIM, Convert__Reg1_1, 0, { MCK__PCT_wim, MCK_IntRegs }, },
3032
  { 2437 /* mov */, Sparc::RDASR, Convert__Reg1_1__Reg1_0, 0, { MCK_ASRRegs, MCK_IntRegs }, },
3033
  { 2437 /* mov */, Sparc::WRPSRrr, Convert__regG0__Reg1_0, 0, { MCK_IntRegs, MCK__PCT_psr }, },
3034
  { 2437 /* mov */, Sparc::WRTBRrr, Convert__regG0__Reg1_0, 0, { MCK_IntRegs, MCK__PCT_tbr }, },
3035
  { 2437 /* mov */, Sparc::WRWIMrr, Convert__regG0__Reg1_0, 0, { MCK_IntRegs, MCK__PCT_wim }, },
3036
  { 2437 /* mov */, Sparc::WRASRrr, Convert__Reg1_1__regG0__Reg1_0, 0, { MCK_IntRegs, MCK_ASRRegs }, },
3037
  { 2437 /* mov */, Sparc::ORrr, Convert__Reg1_1__regG0__Reg1_0, 0, { MCK_IntRegs, MCK_IntRegs }, },
3038
  { 2437 /* mov */, Sparc::WRPSRri, Convert__regG0__Imm1_0, 0, { MCK_Imm, MCK__PCT_psr }, },
3039
  { 2437 /* mov */, Sparc::WRTBRri, Convert__regG0__Imm1_0, 0, { MCK_Imm, MCK__PCT_tbr }, },
3040
  { 2437 /* mov */, Sparc::WRWIMri, Convert__regG0__Imm1_0, 0, { MCK_Imm, MCK__PCT_wim }, },
3041
  { 2437 /* mov */, Sparc::WRASRri, Convert__Reg1_1__regG0__Imm1_0, 0, { MCK_Imm, MCK_ASRRegs }, },
3042
  { 2437 /* mov */, Sparc::ORri, Convert__Reg1_1__regG0__Imm1_0, 0, { MCK_Imm, MCK_IntRegs }, },
3043
  { 2437 /* mov */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3044
  { 2437 /* mov */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3045
  { 2437 /* mov */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3046
  { 2437 /* mov */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_8, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3047
  { 2437 /* mov */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3048
  { 2437 /* mov */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3049
  { 2437 /* mov */, Sparc::MOVFCCrr, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK__PCT_fcc0, MCK_IntRegs, MCK_IntRegs }, },
3050
  { 2437 /* mov */, Sparc::MOVFCCri, Convert__Reg1_3__Imm1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK__PCT_fcc0, MCK_Imm, MCK_IntRegs }, },
3051
  { 2437 /* mov */, Sparc::MOVICCrr, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3052
  { 2437 /* mov */, Sparc::MOVICCri, Convert__Reg1_3__Imm1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3053
  { 2437 /* mov */, Sparc::MOVXCCrr, Convert__Reg1_3__Reg1_2__Tie0__Imm1_0, 0, { MCK_Imm, MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3054
  { 2437 /* mov */, Sparc::MOVXCCri, Convert__Reg1_3__Imm1_2__Tie0__Imm1_0, 0, { MCK_Imm, MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3055
  { 2437 /* mov */, Sparc::V9MOVFCCrr, Convert__Reg1_3__Reg1_1__Reg1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3056
  { 2437 /* mov */, Sparc::V9MOVFCCri, Convert__Reg1_3__Reg1_1__Imm1_2__Tie0__Imm1_0, Feature_HasV9, { MCK_Imm, MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3057
  { 2441 /* mova */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3058
  { 2441 /* mova */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3059
  { 2441 /* mova */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_8, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3060
  { 2441 /* mova */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_8, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3061
  { 2441 /* mova */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3062
  { 2441 /* mova */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_0, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3063
  { 2446 /* movcc */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3064
  { 2446 /* movcc */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3065
  { 2446 /* movcc */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3066
  { 2446 /* movcc */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_13, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3067
  { 2452 /* movcs */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3068
  { 2452 /* movcs */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3069
  { 2452 /* movcs */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3070
  { 2452 /* movcs */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_5, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3071
  { 2458 /* movdtox */, Sparc::MOVDTOX, Convert__Reg1_1__Reg1_0, Feature_HasVIS3, { MCK_DFPRegs, MCK_IntRegs }, },
3072
  { 2458 /* movdtox */, Sparc::MOVWTOS, Convert__Reg1_1__Reg1_0, Feature_HasVIS3, { MCK_IntRegs, MCK_DFPRegs }, },
3073
  { 2458 /* movdtox */, Sparc::MOVXTOD, Convert__Reg1_1__Reg1_0, Feature_HasVIS3, { MCK_IntRegs, MCK_DFPRegs }, },
3074
  { 2466 /* move */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3075
  { 2466 /* move */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3076
  { 2466 /* move */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3077
  { 2466 /* move */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3078
  { 2466 /* move */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3079
  { 2466 /* move */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_9, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3080
  { 2471 /* moveq */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3081
  { 2471 /* moveq */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3082
  { 2471 /* moveq */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3083
  { 2471 /* moveq */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3084
  { 2477 /* movg */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_10, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3085
  { 2477 /* movg */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_10, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3086
  { 2477 /* movg */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_10, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3087
  { 2477 /* movg */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_10, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3088
  { 2477 /* movg */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_6, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3089
  { 2477 /* movg */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_6, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3090
  { 2482 /* movge */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_11, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3091
  { 2482 /* movge */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_11, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3092
  { 2482 /* movge */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_11, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3093
  { 2482 /* movge */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_11, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3094
  { 2482 /* movge */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_11, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3095
  { 2482 /* movge */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_11, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3096
  { 2488 /* movgeu */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3097
  { 2488 /* movgeu */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3098
  { 2488 /* movgeu */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_13, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3099
  { 2488 /* movgeu */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_13, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3100
  { 2495 /* movgu */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_12, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3101
  { 2495 /* movgu */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_12, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3102
  { 2495 /* movgu */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_12, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3103
  { 2495 /* movgu */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_12, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3104
  { 2501 /* movl */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_3, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3105
  { 2501 /* movl */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_3, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3106
  { 2501 /* movl */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_3, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3107
  { 2501 /* movl */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_3, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3108
  { 2501 /* movl */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_4, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3109
  { 2501 /* movl */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_4, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3110
  { 2506 /* movle */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_2, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3111
  { 2506 /* movle */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_2, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3112
  { 2506 /* movle */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_2, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3113
  { 2506 /* movle */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_2, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3114
  { 2506 /* movle */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_13, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3115
  { 2506 /* movle */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_13, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3116
  { 2512 /* movleu */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_4, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3117
  { 2512 /* movleu */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_4, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3118
  { 2512 /* movleu */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_4, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3119
  { 2512 /* movleu */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_4, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3120
  { 2519 /* movlg */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_2, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3121
  { 2519 /* movlg */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_2, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3122
  { 2525 /* movlu */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3123
  { 2525 /* movlu */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3124
  { 2525 /* movlu */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_5, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3125
  { 2525 /* movlu */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_5, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3126
  { 2531 /* movn */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_0, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3127
  { 2531 /* movn */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_0, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3128
  { 2531 /* movn */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_0, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3129
  { 2531 /* movn */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_0, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3130
  { 2531 /* movn */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_8, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3131
  { 2531 /* movn */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_8, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3132
  { 2536 /* movne */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3133
  { 2536 /* movne */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3134
  { 2536 /* movne */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3135
  { 2536 /* movne */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_9, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3136
  { 2536 /* movne */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3137
  { 2536 /* movne */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_1, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3138
  { 2542 /* movneg */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_6, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3139
  { 2542 /* movneg */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_6, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3140
  { 2542 /* movneg */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_6, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3141
  { 2542 /* movneg */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_6, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3142
  { 2549 /* movnz */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3143
  { 2549 /* movnz */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3144
  { 2549 /* movnz */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_9, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3145
  { 2549 /* movnz */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_9, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3146
  { 2549 /* movnz */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3147
  { 2549 /* movnz */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_1, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3148
  { 2555 /* movo */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_15, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3149
  { 2555 /* movo */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_15, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3150
  { 2560 /* movpos */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_14, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3151
  { 2560 /* movpos */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_14, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3152
  { 2560 /* movpos */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_14, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3153
  { 2560 /* movpos */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_14, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3154
  { 2567 /* movrgez */, Sparc::MOVRGEZrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3155
  { 2567 /* movrgez */, Sparc::MOVRGEZri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3156
  { 2575 /* movrgz */, Sparc::MOVRGZrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3157
  { 2575 /* movrgz */, Sparc::MOVRGZri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3158
  { 2582 /* movrlez */, Sparc::MOVRLEZrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3159
  { 2582 /* movrlez */, Sparc::MOVRLEZri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3160
  { 2590 /* movrlz */, Sparc::MOVRLZrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3161
  { 2590 /* movrlz */, Sparc::MOVRLZri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3162
  { 2597 /* movrnz */, Sparc::MOVRNZrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3163
  { 2597 /* movrnz */, Sparc::MOVRNZri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3164
  { 2604 /* movrz */, Sparc::MOVRRZrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3165
  { 2604 /* movrz */, Sparc::MOVRRZri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3166
  { 2610 /* movstosw */, Sparc::MOVSTOSW, Convert__Reg1_1__Reg1_0, Feature_HasVIS3, { MCK_DFPRegs, MCK_IntRegs }, },
3167
  { 2619 /* movstouw */, Sparc::MOVSTOUW, Convert__Reg1_1__Reg1_0, Feature_HasVIS3, { MCK_DFPRegs, MCK_IntRegs }, },
3168
  { 2628 /* movu */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_7, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3169
  { 2628 /* movu */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_7, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3170
  { 2633 /* movue */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_10, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3171
  { 2633 /* movue */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_10, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3172
  { 2639 /* movug */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_5, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3173
  { 2639 /* movug */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_5, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3174
  { 2645 /* movuge */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_12, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3175
  { 2645 /* movuge */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_12, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3176
  { 2652 /* movul */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_3, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3177
  { 2652 /* movul */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_3, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3178
  { 2658 /* movule */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_14, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3179
  { 2658 /* movule */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_14, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3180
  { 2665 /* movvc */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_15, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3181
  { 2665 /* movvc */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_15, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3182
  { 2665 /* movvc */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_15, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3183
  { 2665 /* movvc */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_15, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3184
  { 2671 /* movvs */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_7, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3185
  { 2671 /* movvs */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_7, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3186
  { 2671 /* movvs */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_7, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3187
  { 2671 /* movvs */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_7, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3188
  { 2677 /* movz */, Sparc::MOVICCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK_IntRegs }, },
3189
  { 2677 /* movz */, Sparc::MOVICCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_Imm, MCK_IntRegs }, },
3190
  { 2677 /* movz */, Sparc::MOVXCCrr, Convert__Reg1_2__Reg1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_IntRegs, MCK_IntRegs }, },
3191
  { 2677 /* movz */, Sparc::MOVXCCri, Convert__Reg1_2__Imm1_1__Tie0__imm_95_1, 0, { MCK__PCT_xcc, MCK_Imm, MCK_IntRegs }, },
3192
  { 2677 /* movz */, Sparc::V9MOVFCCrr, Convert__Reg1_2__Reg1_0__Reg1_1__Tie0__imm_95_9, Feature_HasV9, { MCK_FCCRegs, MCK_IntRegs, MCK_IntRegs }, },
3193
  { 2677 /* movz */, Sparc::V9MOVFCCri, Convert__Reg1_2__Reg1_0__Imm1_1__Tie0__imm_95_9, Feature_HasV9, { MCK_FCCRegs, MCK_Imm, MCK_IntRegs }, },
3194
  { 2682 /* mulscc */, Sparc::MULSCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3195
  { 2682 /* mulscc */, Sparc::MULSCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3196
  { 2689 /* mulx */, Sparc::MULXrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3197
  { 2689 /* mulx */, Sparc::MULXri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3198
  { 2694 /* neg */, Sparc::SUBrr, Convert__Reg1_0__regG0__Reg1_0, 0, { MCK_IntRegs }, },
3199
  { 2694 /* neg */, Sparc::SUBrr, Convert__Reg1_1__regG0__Reg1_0, 0, { MCK_IntRegs, MCK_IntRegs }, },
3200
  { 2698 /* nop */, Sparc::NOP, Convert_NoOperands, 0, {  }, },
3201
  { 2702 /* not */, Sparc::XNORrr, Convert__Reg1_0__Reg1_0__regG0, 0, { MCK_IntRegs }, },
3202
  { 2702 /* not */, Sparc::XNORrr, Convert__Reg1_1__Reg1_0__regG0, 0, { MCK_IntRegs, MCK_IntRegs }, },
3203
  { 2706 /* or */, Sparc::ORrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3204
  { 2706 /* or */, Sparc::ORri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3205
  { 2709 /* orcc */, Sparc::ORCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3206
  { 2709 /* orcc */, Sparc::ORCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3207
  { 2714 /* orn */, Sparc::ORNrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3208
  { 2714 /* orn */, Sparc::ORNri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3209
  { 2718 /* orncc */, Sparc::ORNCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3210
  { 2718 /* orncc */, Sparc::ORNCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3211
  { 2724 /* pdist */, Sparc::PDIST, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3212
  { 2730 /* pdistn */, Sparc::PDISTN, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_DFPRegs, MCK_DFPRegs, MCK_DFPRegs }, },
3213
  { 2737 /* popc */, Sparc::POPCrr, Convert__Reg1_1__Reg1_0, Feature_HasV9, { MCK_IntRegs, MCK_IntRegs }, },
3214
  { 2742 /* rd */, Sparc::RDPSR, Convert__Reg1_1, 0, { MCK__PCT_psr, MCK_IntRegs }, },
3215
  { 2742 /* rd */, Sparc::RDTBR, Convert__Reg1_1, 0, { MCK__PCT_tbr, MCK_IntRegs }, },
3216
  { 2742 /* rd */, Sparc::RDWIM, Convert__Reg1_1, 0, { MCK__PCT_wim, MCK_IntRegs }, },
3217
  { 2742 /* rd */, Sparc::RDASR, Convert__Reg1_1__Reg1_0, 0, { MCK_ASRRegs, MCK_IntRegs }, },
3218
  { 2745 /* rdpr */, Sparc::RDPR, Convert__Reg1_1__Reg1_0, Feature_HasV9, { MCK_PRRegs, MCK_IntRegs }, },
3219
  { 2750 /* restore */, Sparc::RESTORErr, Convert__regG0__regG0__regG0, 0, {  }, },
3220
  { 2750 /* restore */, Sparc::RESTORErr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3221
  { 2750 /* restore */, Sparc::RESTOREri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3222
  { 2758 /* ret */, Sparc::RET, Convert__imm_95_8, 0, {  }, },
3223
  { 2762 /* retl */, Sparc::RETL, Convert__imm_95_8, 0, {  }, },
3224
  { 2767 /* rett */, Sparc::RETTri, Convert__MEMri2_0, 0, { MCK_MEMri }, },
3225
  { 2767 /* rett */, Sparc::RETTrr, Convert__MEMrr2_0, 0, { MCK_MEMrr }, },
3226
  { 2772 /* save */, Sparc::SAVErr, Convert__regG0__regG0__regG0, 0, {  }, },
3227
  { 2772 /* save */, Sparc::SAVErr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3228
  { 2772 /* save */, Sparc::SAVEri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3229
  { 2777 /* sdiv */, Sparc::SDIVrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3230
  { 2777 /* sdiv */, Sparc::SDIVri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3231
  { 2782 /* sdivcc */, Sparc::SDIVCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3232
  { 2782 /* sdivcc */, Sparc::SDIVCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3233
  { 2789 /* sdivx */, Sparc::SDIVXrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3234
  { 2789 /* sdivx */, Sparc::SDIVXri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3235
  { 2795 /* set */, Sparc::SET, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_IntRegs }, },
3236
  { 2799 /* sethi */, Sparc::SETHIi, Convert__Reg1_1__Imm1_0, 0, { MCK_Imm, MCK_IntRegs }, },
3237
  { 2805 /* shutdown */, Sparc::SHUTDOWN, Convert_NoOperands, Feature_HasVIS, {  }, },
3238
  { 2814 /* siam */, Sparc::SIAM, Convert_NoOperands, Feature_HasVIS2, {  }, },
3239
  { 2819 /* signx */, Sparc::SRArr, Convert__Reg1_0__Reg1_0__regG0, Feature_HasV9, { MCK_IntRegs }, },
3240
  { 2819 /* signx */, Sparc::SRArr, Convert__Reg1_1__Reg1_0__regG0, Feature_HasV9, { MCK_IntRegs, MCK_IntRegs }, },
3241
  { 2825 /* sll */, Sparc::SLLrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3242
  { 2825 /* sll */, Sparc::SLLri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3243
  { 2829 /* sllx */, Sparc::SLLXrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3244
  { 2829 /* sllx */, Sparc::SLLXri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3245
  { 2834 /* smul */, Sparc::SMULrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3246
  { 2834 /* smul */, Sparc::SMULri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3247
  { 2839 /* smulcc */, Sparc::SMULCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3248
  { 2839 /* smulcc */, Sparc::SMULCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3249
  { 2846 /* sra */, Sparc::SRArr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3250
  { 2846 /* sra */, Sparc::SRAri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3251
  { 2850 /* srax */, Sparc::SRAXrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3252
  { 2850 /* srax */, Sparc::SRAXri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3253
  { 2855 /* srl */, Sparc::SRLrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3254
  { 2855 /* srl */, Sparc::SRLri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3255
  { 2859 /* srlx */, Sparc::SRLXrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3256
  { 2859 /* srlx */, Sparc::SRLXri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3257
  { 2864 /* st */, Sparc::STFSRri, Convert__MEMri2_2, 0, { MCK__PCT_fsr, MCK__91_, MCK_MEMri, MCK__93_ }, },
3258
  { 2864 /* st */, Sparc::STFSRrr, Convert__MEMrr2_2, 0, { MCK__PCT_fsr, MCK__91_, MCK_MEMrr, MCK__93_ }, },
3259
  { 2864 /* st */, Sparc::STFri, Convert__MEMri2_2__Reg1_0, 0, { MCK_FPRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
3260
  { 2864 /* st */, Sparc::STFrr, Convert__MEMrr2_2__Reg1_0, 0, { MCK_FPRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
3261
  { 2864 /* st */, Sparc::STri, Convert__MEMri2_2__Reg1_0, 0, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
3262
  { 2864 /* st */, Sparc::STrr, Convert__MEMrr2_2__Reg1_0, 0, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
3263
  { 2867 /* sta */, Sparc::STFArr, Convert__MEMrr2_2__Reg1_0__Imm1_4, Feature_HasV9, { MCK_FPRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm }, },
3264
  { 2867 /* sta */, Sparc::STArr, Convert__MEMrr2_2__Reg1_0__Imm1_4, 0, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm }, },
3265
  { 2871 /* stb */, Sparc::STBri, Convert__MEMri2_2__Reg1_0, 0, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
3266
  { 2871 /* stb */, Sparc::STBrr, Convert__MEMrr2_2__Reg1_0, 0, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
3267
  { 2875 /* stba */, Sparc::STBArr, Convert__MEMrr2_2__Reg1_0__Imm1_4, 0, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm }, },
3268
  { 2880 /* stbar */, Sparc::STBAR, Convert_NoOperands, 0, {  }, },
3269
  { 2886 /* std */, Sparc::STDri, Convert__MEMri2_2__Reg1_0, 0, { MCK_IntPair, MCK__91_, MCK_MEMri, MCK__93_ }, },
3270
  { 2886 /* std */, Sparc::STDrr, Convert__MEMrr2_2__Reg1_0, 0, { MCK_IntPair, MCK__91_, MCK_MEMrr, MCK__93_ }, },
3271
  { 2886 /* std */, Sparc::STDFri, Convert__MEMri2_2__Reg1_0, 0, { MCK_DFPRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
3272
  { 2886 /* std */, Sparc::STDFrr, Convert__MEMrr2_2__Reg1_0, 0, { MCK_DFPRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
3273
  { 2890 /* stda */, Sparc::STDArr, Convert__MEMrr2_2__Reg1_0__Imm1_4, 0, { MCK_IntPair, MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm }, },
3274
  { 2890 /* stda */, Sparc::STDFArr, Convert__MEMrr2_2__Reg1_0__Imm1_4, Feature_HasV9, { MCK_DFPRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm }, },
3275
  { 2895 /* sth */, Sparc::STHri, Convert__MEMri2_2__Reg1_0, 0, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
3276
  { 2895 /* sth */, Sparc::STHrr, Convert__MEMrr2_2__Reg1_0, 0, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
3277
  { 2899 /* stha */, Sparc::STHArr, Convert__MEMrr2_2__Reg1_0__Imm1_4, 0, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm }, },
3278
  { 2904 /* stq */, Sparc::STQFri, Convert__MEMri2_2__Reg1_0, Feature_HasV9, { MCK_QFPRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
3279
  { 2904 /* stq */, Sparc::STQFrr, Convert__MEMrr2_2__Reg1_0, Feature_HasV9, { MCK_QFPRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
3280
  { 2908 /* stqa */, Sparc::STQFArr, Convert__MEMrr2_2__Reg1_0__Imm1_4, Feature_HasV9, { MCK_QFPRegs, MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm }, },
3281
  { 2913 /* stx */, Sparc::STXFSRri, Convert__MEMri2_2, Feature_HasV9, { MCK__PCT_fsr, MCK__91_, MCK_MEMri, MCK__93_ }, },
3282
  { 2913 /* stx */, Sparc::STXFSRrr, Convert__MEMrr2_2, Feature_HasV9, { MCK__PCT_fsr, MCK__91_, MCK_MEMrr, MCK__93_ }, },
3283
  { 2913 /* stx */, Sparc::STXri, Convert__MEMri2_2__Reg1_0, 0, { MCK_IntRegs, MCK__91_, MCK_MEMri, MCK__93_ }, },
3284
  { 2913 /* stx */, Sparc::STXrr, Convert__MEMrr2_2__Reg1_0, 0, { MCK_IntRegs, MCK__91_, MCK_MEMrr, MCK__93_ }, },
3285
  { 2917 /* sub */, Sparc::SUBrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3286
  { 2917 /* sub */, Sparc::SUBri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3287
  { 2921 /* subcc */, Sparc::SUBCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3288
  { 2921 /* subcc */, Sparc::SUBCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3289
  { 2927 /* subx */, Sparc::SUBCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3290
  { 2927 /* subx */, Sparc::SUBCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3291
  { 2932 /* subxcc */, Sparc::SUBErr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3292
  { 2932 /* subxcc */, Sparc::SUBEri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3293
  { 2939 /* swap */, Sparc::SWAPri, Convert__Reg1_3__MEMri2_1__Tie0, 0, { MCK__91_, MCK_MEMri, MCK__93_, MCK_IntRegs }, },
3294
  { 2939 /* swap */, Sparc::SWAPrr, Convert__Reg1_3__MEMrr2_1__Tie0, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_IntRegs }, },
3295
  { 2944 /* swapa */, Sparc::SWAPArr, Convert__Reg1_4__MEMrr2_1__Imm1_3__Tie0, 0, { MCK__91_, MCK_MEMrr, MCK__93_, MCK_Imm, MCK_IntRegs }, },
3296
  { 2950 /* t */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_8, 0, { MCK_IntRegs }, },
3297
  { 2950 /* t */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_8, 0, { MCK_Imm }, },
3298
  { 2950 /* t */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3299
  { 2950 /* t */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3300
  { 2950 /* t */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_8, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3301
  { 2950 /* t */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_8, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3302
  { 2950 /* t */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_8, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3303
  { 2950 /* t */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_8, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3304
  { 2950 /* t */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3305
  { 2950 /* t */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3306
  { 2950 /* t */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_8, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3307
  { 2950 /* t */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_8, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3308
  { 2950 /* t */, Sparc::TICCrr, Convert__Reg1_2__Reg1_4__Imm1_0, 0, { MCK_Imm, MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3309
  { 2950 /* t */, Sparc::TICCri, Convert__Reg1_2__Imm1_4__Imm1_0, 0, { MCK_Imm, MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3310
  { 2950 /* t */, Sparc::TXCCrr, Convert__Reg1_2__Reg1_4__Imm1_0, 0, { MCK_Imm, MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3311
  { 2950 /* t */, Sparc::TXCCri, Convert__Reg1_2__Imm1_4__Imm1_0, 0, { MCK_Imm, MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3312
  { 2952 /* ta */, Sparc::TA3, Convert_NoOperands, 0, { MCK_3 }, },
3313
  { 2952 /* ta */, Sparc::TA5, Convert_NoOperands, 0, { MCK_5 }, },
3314
  { 2952 /* ta */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_8, 0, { MCK_IntRegs }, },
3315
  { 2952 /* ta */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_8, 0, { MCK_Imm }, },
3316
  { 2952 /* ta */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3317
  { 2952 /* ta */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3318
  { 2952 /* ta */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_8, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3319
  { 2952 /* ta */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_8, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3320
  { 2952 /* ta */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_8, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3321
  { 2952 /* ta */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_8, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3322
  { 2952 /* ta */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3323
  { 2952 /* ta */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_8, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3324
  { 2952 /* ta */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_8, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3325
  { 2952 /* ta */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_8, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3326
  { 2955 /* taddcc */, Sparc::TADDCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3327
  { 2955 /* taddcc */, Sparc::TADDCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3328
  { 2962 /* taddcctv */, Sparc::TADDCCTVrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3329
  { 2962 /* taddcctv */, Sparc::TADDCCTVri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3330
  { 2971 /* tcc */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_13, 0, { MCK_IntRegs }, },
3331
  { 2971 /* tcc */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_13, 0, { MCK_Imm }, },
3332
  { 2971 /* tcc */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3333
  { 2971 /* tcc */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3334
  { 2971 /* tcc */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_13, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3335
  { 2971 /* tcc */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_13, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3336
  { 2971 /* tcc */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_13, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3337
  { 2971 /* tcc */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_13, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3338
  { 2971 /* tcc */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3339
  { 2971 /* tcc */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3340
  { 2971 /* tcc */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_13, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3341
  { 2971 /* tcc */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_13, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3342
  { 2975 /* tcs */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_5, 0, { MCK_IntRegs }, },
3343
  { 2975 /* tcs */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_5, 0, { MCK_Imm }, },
3344
  { 2975 /* tcs */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3345
  { 2975 /* tcs */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3346
  { 2975 /* tcs */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_5, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3347
  { 2975 /* tcs */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_5, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3348
  { 2975 /* tcs */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_5, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3349
  { 2975 /* tcs */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_5, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3350
  { 2975 /* tcs */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3351
  { 2975 /* tcs */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3352
  { 2975 /* tcs */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_5, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3353
  { 2975 /* tcs */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_5, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3354
  { 2979 /* te */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_1, 0, { MCK_IntRegs }, },
3355
  { 2979 /* te */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_1, 0, { MCK_Imm }, },
3356
  { 2979 /* te */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3357
  { 2979 /* te */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3358
  { 2979 /* te */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3359
  { 2979 /* te */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3360
  { 2979 /* te */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_1, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3361
  { 2979 /* te */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_1, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3362
  { 2979 /* te */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3363
  { 2979 /* te */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3364
  { 2979 /* te */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3365
  { 2979 /* te */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3366
  { 2982 /* teq */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_1, 0, { MCK_IntRegs }, },
3367
  { 2982 /* teq */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_1, 0, { MCK_Imm }, },
3368
  { 2982 /* teq */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3369
  { 2982 /* teq */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3370
  { 2982 /* teq */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3371
  { 2982 /* teq */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3372
  { 2982 /* teq */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_1, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3373
  { 2982 /* teq */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_1, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3374
  { 2982 /* teq */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3375
  { 2982 /* teq */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3376
  { 2982 /* teq */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3377
  { 2982 /* teq */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3378
  { 2986 /* tg */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_10, 0, { MCK_IntRegs }, },
3379
  { 2986 /* tg */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_10, 0, { MCK_Imm }, },
3380
  { 2986 /* tg */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_10, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3381
  { 2986 /* tg */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_10, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3382
  { 2986 /* tg */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_10, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3383
  { 2986 /* tg */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_10, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3384
  { 2986 /* tg */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_10, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3385
  { 2986 /* tg */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_10, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3386
  { 2986 /* tg */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_10, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3387
  { 2986 /* tg */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_10, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3388
  { 2986 /* tg */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_10, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3389
  { 2986 /* tg */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_10, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3390
  { 2989 /* tge */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_11, 0, { MCK_IntRegs }, },
3391
  { 2989 /* tge */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_11, 0, { MCK_Imm }, },
3392
  { 2989 /* tge */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_11, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3393
  { 2989 /* tge */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_11, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3394
  { 2989 /* tge */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_11, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3395
  { 2989 /* tge */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_11, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3396
  { 2989 /* tge */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_11, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3397
  { 2989 /* tge */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_11, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3398
  { 2989 /* tge */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_11, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3399
  { 2989 /* tge */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_11, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3400
  { 2989 /* tge */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_11, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3401
  { 2989 /* tge */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_11, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3402
  { 2993 /* tgeu */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_13, 0, { MCK_IntRegs }, },
3403
  { 2993 /* tgeu */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_13, 0, { MCK_Imm }, },
3404
  { 2993 /* tgeu */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3405
  { 2993 /* tgeu */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3406
  { 2993 /* tgeu */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_13, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3407
  { 2993 /* tgeu */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_13, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3408
  { 2993 /* tgeu */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_13, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3409
  { 2993 /* tgeu */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_13, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3410
  { 2993 /* tgeu */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3411
  { 2993 /* tgeu */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_13, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3412
  { 2993 /* tgeu */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_13, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3413
  { 2993 /* tgeu */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_13, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3414
  { 2998 /* tgu */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_12, 0, { MCK_IntRegs }, },
3415
  { 2998 /* tgu */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_12, 0, { MCK_Imm }, },
3416
  { 2998 /* tgu */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_12, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3417
  { 2998 /* tgu */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_12, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3418
  { 2998 /* tgu */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_12, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3419
  { 2998 /* tgu */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_12, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3420
  { 2998 /* tgu */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_12, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3421
  { 2998 /* tgu */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_12, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3422
  { 2998 /* tgu */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_12, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3423
  { 2998 /* tgu */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_12, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3424
  { 2998 /* tgu */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_12, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3425
  { 2998 /* tgu */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_12, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3426
  { 3002 /* tl */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_3, 0, { MCK_IntRegs }, },
3427
  { 3002 /* tl */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_3, 0, { MCK_Imm }, },
3428
  { 3002 /* tl */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_3, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3429
  { 3002 /* tl */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_3, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3430
  { 3002 /* tl */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_3, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3431
  { 3002 /* tl */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_3, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3432
  { 3002 /* tl */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_3, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3433
  { 3002 /* tl */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_3, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3434
  { 3002 /* tl */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_3, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3435
  { 3002 /* tl */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_3, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3436
  { 3002 /* tl */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_3, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3437
  { 3002 /* tl */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_3, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3438
  { 3005 /* tle */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_2, 0, { MCK_IntRegs }, },
3439
  { 3005 /* tle */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_2, 0, { MCK_Imm }, },
3440
  { 3005 /* tle */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_2, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3441
  { 3005 /* tle */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_2, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3442
  { 3005 /* tle */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_2, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3443
  { 3005 /* tle */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_2, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3444
  { 3005 /* tle */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_2, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3445
  { 3005 /* tle */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_2, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3446
  { 3005 /* tle */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_2, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3447
  { 3005 /* tle */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_2, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3448
  { 3005 /* tle */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_2, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3449
  { 3005 /* tle */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_2, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3450
  { 3009 /* tleu */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_4, 0, { MCK_IntRegs }, },
3451
  { 3009 /* tleu */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_4, 0, { MCK_Imm }, },
3452
  { 3009 /* tleu */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_4, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3453
  { 3009 /* tleu */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_4, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3454
  { 3009 /* tleu */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_4, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3455
  { 3009 /* tleu */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_4, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3456
  { 3009 /* tleu */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_4, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3457
  { 3009 /* tleu */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_4, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3458
  { 3009 /* tleu */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_4, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3459
  { 3009 /* tleu */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_4, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3460
  { 3009 /* tleu */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_4, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3461
  { 3009 /* tleu */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_4, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3462
  { 3014 /* tlu */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_5, 0, { MCK_IntRegs }, },
3463
  { 3014 /* tlu */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_5, 0, { MCK_Imm }, },
3464
  { 3014 /* tlu */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3465
  { 3014 /* tlu */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3466
  { 3014 /* tlu */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_5, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3467
  { 3014 /* tlu */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_5, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3468
  { 3014 /* tlu */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_5, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3469
  { 3014 /* tlu */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_5, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3470
  { 3014 /* tlu */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3471
  { 3014 /* tlu */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_5, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3472
  { 3014 /* tlu */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_5, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3473
  { 3014 /* tlu */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_5, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3474
  { 3018 /* tn */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_0, 0, { MCK_IntRegs }, },
3475
  { 3018 /* tn */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_0, 0, { MCK_Imm }, },
3476
  { 3018 /* tn */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_0, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3477
  { 3018 /* tn */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_0, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3478
  { 3018 /* tn */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_0, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3479
  { 3018 /* tn */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_0, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3480
  { 3018 /* tn */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_0, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3481
  { 3018 /* tn */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_0, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3482
  { 3018 /* tn */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_0, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3483
  { 3018 /* tn */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_0, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3484
  { 3018 /* tn */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_0, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3485
  { 3018 /* tn */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_0, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3486
  { 3021 /* tne */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_9, 0, { MCK_IntRegs }, },
3487
  { 3021 /* tne */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_9, 0, { MCK_Imm }, },
3488
  { 3021 /* tne */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3489
  { 3021 /* tne */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3490
  { 3021 /* tne */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_9, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3491
  { 3021 /* tne */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_9, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3492
  { 3021 /* tne */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_9, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3493
  { 3021 /* tne */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_9, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3494
  { 3021 /* tne */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3495
  { 3021 /* tne */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3496
  { 3021 /* tne */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_9, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3497
  { 3021 /* tne */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_9, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3498
  { 3025 /* tneg */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_6, 0, { MCK_IntRegs }, },
3499
  { 3025 /* tneg */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_6, 0, { MCK_Imm }, },
3500
  { 3025 /* tneg */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_6, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3501
  { 3025 /* tneg */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_6, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3502
  { 3025 /* tneg */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_6, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3503
  { 3025 /* tneg */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_6, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3504
  { 3025 /* tneg */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_6, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3505
  { 3025 /* tneg */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_6, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3506
  { 3025 /* tneg */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_6, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3507
  { 3025 /* tneg */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_6, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3508
  { 3025 /* tneg */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_6, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3509
  { 3025 /* tneg */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_6, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3510
  { 3030 /* tnz */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_9, 0, { MCK_IntRegs }, },
3511
  { 3030 /* tnz */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_9, 0, { MCK_Imm }, },
3512
  { 3030 /* tnz */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3513
  { 3030 /* tnz */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3514
  { 3030 /* tnz */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_9, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3515
  { 3030 /* tnz */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_9, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3516
  { 3030 /* tnz */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_9, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3517
  { 3030 /* tnz */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_9, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3518
  { 3030 /* tnz */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3519
  { 3030 /* tnz */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_9, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3520
  { 3030 /* tnz */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_9, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3521
  { 3030 /* tnz */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_9, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3522
  { 3034 /* tpos */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_14, 0, { MCK_IntRegs }, },
3523
  { 3034 /* tpos */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_14, 0, { MCK_Imm }, },
3524
  { 3034 /* tpos */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_14, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3525
  { 3034 /* tpos */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_14, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3526
  { 3034 /* tpos */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_14, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3527
  { 3034 /* tpos */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_14, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3528
  { 3034 /* tpos */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_14, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3529
  { 3034 /* tpos */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_14, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3530
  { 3034 /* tpos */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_14, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3531
  { 3034 /* tpos */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_14, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3532
  { 3034 /* tpos */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_14, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3533
  { 3034 /* tpos */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_14, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3534
  { 3039 /* tst */, Sparc::ORCCrr, Convert__regG0__Reg1_0__regG0, 0, { MCK_IntRegs }, },
3535
  { 3043 /* tsubcc */, Sparc::TSUBCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3536
  { 3043 /* tsubcc */, Sparc::TSUBCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3537
  { 3050 /* tsubcctv */, Sparc::TSUBCCTVrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3538
  { 3050 /* tsubcctv */, Sparc::TSUBCCTVri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3539
  { 3059 /* tvc */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_15, 0, { MCK_IntRegs }, },
3540
  { 3059 /* tvc */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_15, 0, { MCK_Imm }, },
3541
  { 3059 /* tvc */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_15, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3542
  { 3059 /* tvc */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_15, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3543
  { 3059 /* tvc */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_15, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3544
  { 3059 /* tvc */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_15, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3545
  { 3059 /* tvc */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_15, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3546
  { 3059 /* tvc */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_15, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3547
  { 3059 /* tvc */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_15, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3548
  { 3059 /* tvc */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_15, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3549
  { 3059 /* tvc */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_15, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3550
  { 3059 /* tvc */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_15, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3551
  { 3063 /* tvs */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_7, 0, { MCK_IntRegs }, },
3552
  { 3063 /* tvs */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_7, 0, { MCK_Imm }, },
3553
  { 3063 /* tvs */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_7, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3554
  { 3063 /* tvs */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_7, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3555
  { 3063 /* tvs */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_7, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3556
  { 3063 /* tvs */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_7, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3557
  { 3063 /* tvs */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_7, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3558
  { 3063 /* tvs */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_7, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3559
  { 3063 /* tvs */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_7, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3560
  { 3063 /* tvs */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_7, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3561
  { 3063 /* tvs */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_7, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3562
  { 3063 /* tvs */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_7, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3563
  { 3067 /* tz */, Sparc::TICCrr, Convert__regG0__Reg1_0__imm_95_1, 0, { MCK_IntRegs }, },
3564
  { 3067 /* tz */, Sparc::TICCri, Convert__regG0__Imm1_0__imm_95_1, 0, { MCK_Imm }, },
3565
  { 3067 /* tz */, Sparc::TICCrr, Convert__regG0__Reg1_1__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs }, },
3566
  { 3067 /* tz */, Sparc::TICCri, Convert__regG0__Imm1_1__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_Imm }, },
3567
  { 3067 /* tz */, Sparc::TXCCrr, Convert__regG0__Reg1_1__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs }, },
3568
  { 3067 /* tz */, Sparc::TXCCri, Convert__regG0__Imm1_1__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_Imm }, },
3569
  { 3067 /* tz */, Sparc::TICCrr, Convert__Reg1_0__Reg1_2__imm_95_1, 0, { MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3570
  { 3067 /* tz */, Sparc::TICCri, Convert__Reg1_0__Imm1_2__imm_95_1, 0, { MCK_IntRegs, MCK__43_, MCK_Imm }, },
3571
  { 3067 /* tz */, Sparc::TICCrr, Convert__Reg1_1__Reg1_3__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3572
  { 3067 /* tz */, Sparc::TICCri, Convert__Reg1_1__Imm1_3__imm_95_1, Feature_HasV9, { MCK__PCT_icc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3573
  { 3067 /* tz */, Sparc::TXCCrr, Convert__Reg1_1__Reg1_3__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_IntRegs }, },
3574
  { 3067 /* tz */, Sparc::TXCCri, Convert__Reg1_1__Imm1_3__imm_95_1, Feature_HasV9, { MCK__PCT_xcc, MCK_IntRegs, MCK__43_, MCK_Imm }, },
3575
  { 3070 /* udiv */, Sparc::UDIVrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3576
  { 3070 /* udiv */, Sparc::UDIVri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3577
  { 3075 /* udivcc */, Sparc::UDIVCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3578
  { 3075 /* udivcc */, Sparc::UDIVCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3579
  { 3082 /* udivx */, Sparc::UDIVXrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3580
  { 3082 /* udivx */, Sparc::UDIVXri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3581
  { 3088 /* umul */, Sparc::UMULrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3582
  { 3088 /* umul */, Sparc::UMULri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3583
  { 3093 /* umulcc */, Sparc::UMULCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3584
  { 3093 /* umulcc */, Sparc::UMULCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3585
  { 3100 /* umulxhi */, Sparc::UMULXHI, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3586
  { 3108 /* unimp */, Sparc::UNIMP, Convert__Imm1_0, 0, { MCK_Imm }, },
3587
  { 3114 /* wr */, Sparc::WRPSRrr, Convert__regG0__Reg1_0, 0, { MCK_IntRegs, MCK__PCT_psr }, },
3588
  { 3114 /* wr */, Sparc::WRTBRrr, Convert__regG0__Reg1_0, 0, { MCK_IntRegs, MCK__PCT_tbr }, },
3589
  { 3114 /* wr */, Sparc::WRWIMrr, Convert__regG0__Reg1_0, 0, { MCK_IntRegs, MCK__PCT_wim }, },
3590
  { 3114 /* wr */, Sparc::WRASRrr, Convert__Reg1_1__regG0__Reg1_0, 0, { MCK_IntRegs, MCK_ASRRegs }, },
3591
  { 3114 /* wr */, Sparc::WRPSRri, Convert__regG0__Imm1_0, 0, { MCK_Imm, MCK__PCT_psr }, },
3592
  { 3114 /* wr */, Sparc::WRTBRri, Convert__regG0__Imm1_0, 0, { MCK_Imm, MCK__PCT_tbr }, },
3593
  { 3114 /* wr */, Sparc::WRWIMri, Convert__regG0__Imm1_0, 0, { MCK_Imm, MCK__PCT_wim }, },
3594
  { 3114 /* wr */, Sparc::WRASRri, Convert__Reg1_1__regG0__Imm1_0, 0, { MCK_Imm, MCK_ASRRegs }, },
3595
  { 3114 /* wr */, Sparc::WRPSRrr, Convert__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK__PCT_psr }, },
3596
  { 3114 /* wr */, Sparc::WRTBRrr, Convert__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK__PCT_tbr }, },
3597
  { 3114 /* wr */, Sparc::WRWIMrr, Convert__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK__PCT_wim }, },
3598
  { 3114 /* wr */, Sparc::WRASRrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_ASRRegs }, },
3599
  { 3114 /* wr */, Sparc::WRPSRri, Convert__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK__PCT_psr }, },
3600
  { 3114 /* wr */, Sparc::WRTBRri, Convert__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK__PCT_tbr }, },
3601
  { 3114 /* wr */, Sparc::WRWIMri, Convert__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK__PCT_wim }, },
3602
  { 3114 /* wr */, Sparc::WRASRri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_ASRRegs }, },
3603
  { 3117 /* wrpr */, Sparc::WRPRrr, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasV9, { MCK_IntRegs, MCK_IntRegs, MCK_PRRegs }, },
3604
  { 3117 /* wrpr */, Sparc::WRPRri, Convert__Reg1_2__Reg1_0__Imm1_1, Feature_HasV9, { MCK_IntRegs, MCK_Imm, MCK_PRRegs }, },
3605
  { 3122 /* xmulx */, Sparc::XMULX, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3606
  { 3128 /* xmulxhi */, Sparc::XMULXHI, Convert__Reg1_2__Reg1_0__Reg1_1, Feature_HasVIS3, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3607
  { 3136 /* xnor */, Sparc::XNORrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3608
  { 3136 /* xnor */, Sparc::XNORri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3609
  { 3141 /* xnorcc */, Sparc::XNORCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3610
  { 3141 /* xnorcc */, Sparc::XNORCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3611
  { 3148 /* xor */, Sparc::XORrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3612
  { 3148 /* xor */, Sparc::XORri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3613
  { 3152 /* xorcc */, Sparc::XORCCrr, Convert__Reg1_2__Reg1_0__Reg1_1, 0, { MCK_IntRegs, MCK_IntRegs, MCK_IntRegs }, },
3614
  { 3152 /* xorcc */, Sparc::XORCCri, Convert__Reg1_2__Reg1_0__Imm1_1, 0, { MCK_IntRegs, MCK_Imm, MCK_IntRegs }, },
3615
};
3616
3617
unsigned SparcAsmParser::
3618
MatchInstructionImpl(const OperandVector &Operands,
3619
                     MCInst &Inst, uint64_t &ErrorInfo,
3620
4.68k
                     bool matchingInlineAsm, unsigned VariantID) {
3621
  // Eliminate obvious mismatches.
3622
4.68k
  if (Operands.size() > 6) {
3623
35
    ErrorInfo = 6;
3624
35
    return Match_InvalidOperand;
3625
35
  }
3626
3627
  // Get the current feature set.
3628
4.64k
  uint64_t AvailableFeatures = getAvailableFeatures();
3629
3630
  // Get the instruction mnemonic, which is the first token.
3631
4.64k
  StringRef Mnemonic = ((SparcOperand&)*Operands[0]).getToken();
3632
3633
  // Process all MnemonicAliases to remap the mnemonic.
3634
4.64k
  applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);
3635
3636
  // Some state to try to produce better error messages.
3637
4.64k
  bool HadMatchOtherThanFeatures = false;
3638
4.64k
  bool HadMatchOtherThanPredicate = false;
3639
4.64k
  unsigned RetCode = Match_InvalidOperand;
3640
4.64k
  uint64_t MissingFeatures = ~0ULL;
3641
  // Set ErrorInfo to the operand that mismatches if it is
3642
  // wrong for all instances of the instruction.
3643
4.64k
  ErrorInfo = ~0ULL;
3644
  // Find the appropriate table for this asm variant.
3645
4.64k
  const MatchEntry *Start, *End;
3646
4.64k
  switch (VariantID) {
3647
0
  default: llvm_unreachable("invalid variant!");
3648
4.64k
  case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break;
3649
4.64k
  }
3650
  // Search the table.
3651
4.64k
  auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode());
3652
3653
  // Return a more specific error code if no mnemonics match.
3654
4.64k
  if (MnemonicRange.first == MnemonicRange.second)
3655
1.26k
    return Match_MnemonicFail;
3656
3657
3.38k
  for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second;
3658
7.02k
       it != ie; ++it) {
3659
    // equal_range guarantees that instruction mnemonic matches.
3660
6.37k
    assert(Mnemonic == it->getMnemonic());
3661
6.37k
    bool OperandsValid = true;
3662
9.06k
    for (unsigned i = 0; i != 5; ++i) {
3663
9.06k
      auto Formal = static_cast<MatchClassKind>(it->Classes[i]);
3664
9.06k
      if (i+1 >= Operands.size()) {
3665
3.37k
        OperandsValid = (Formal == InvalidMatchClass);
3666
3.37k
        if (!OperandsValid) ErrorInfo = i+1;
3667
3.37k
        break;
3668
3.37k
      }
3669
5.68k
      MCParsedAsmOperand &Actual = *Operands[i+1];
3670
5.68k
      unsigned Diag = validateOperandClass(Actual, Formal);
3671
5.68k
      if (Diag == Match_Success)
3672
2.67k
        continue;
3673
      // If the generic handler indicates an invalid operand
3674
      // failure, check for a special case.
3675
3.01k
      if (Diag == Match_InvalidOperand) {
3676
3.01k
        Diag = validateTargetOperandClass(Actual, Formal);
3677
3.01k
        if (Diag == Match_Success)
3678
17
          continue;
3679
3.01k
      }
3680
      // If this operand is broken for all of the instances of this
3681
      // mnemonic, keep track of it so we can report loc info.
3682
      // If we already had a match that only failed due to a
3683
      // target predicate, that diagnostic is preferred.
3684
2.99k
      if (!HadMatchOtherThanPredicate &&
3685
2.99k
          (it == MnemonicRange.first || ErrorInfo <= i+1)) {
3686
2.81k
        ErrorInfo = i+1;
3687
        // InvalidOperand is the default. Prefer specificity.
3688
2.81k
        if (Diag != Match_InvalidOperand)
3689
0
          RetCode = Diag;
3690
2.81k
      }
3691
      // Otherwise, just reject this instance of the mnemonic.
3692
2.99k
      OperandsValid = false;
3693
2.99k
      break;
3694
3.01k
    }
3695
3696
6.37k
    if (!OperandsValid) continue;
3697
2.73k
    if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) {
3698
1
      HadMatchOtherThanFeatures = true;
3699
1
      uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures;
3700
1
      if (countPopulation(NewMissingFeatures) <=
3701
1
          countPopulation(MissingFeatures))
3702
1
        MissingFeatures = NewMissingFeatures;
3703
1
      continue;
3704
1
    }
3705
3706
2.73k
    Inst.clear();
3707
3708
2.73k
    if (matchingInlineAsm) {
3709
0
      Inst.setOpcode(it->Opcode);
3710
0
      convertToMapAndConstraints(it->ConvertFn, Operands);
3711
0
      return Match_Success;
3712
0
    }
3713
3714
    // We have selected a definite instruction, convert the parsed
3715
    // operands into the appropriate MCInst.
3716
2.73k
    convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);
3717
3718
    // We have a potential match. Check the target predicate to
3719
    // handle any context sensitive constraints.
3720
2.73k
    unsigned MatchResult;
3721
2.73k
    if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) {
3722
0
      Inst.clear();
3723
0
      RetCode = MatchResult;
3724
0
      HadMatchOtherThanPredicate = true;
3725
0
      continue;
3726
0
    }
3727
3728
2.73k
    return Match_Success;
3729
2.73k
  }
3730
3731
  // Okay, we had no match.  Try to return a useful error code.
3732
650
  if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)
3733
649
    return RetCode;
3734
3735
  // Missing feature matches return which features were missing
3736
1
  ErrorInfo = MissingFeatures;
3737
1
  return Match_MissingFeature;
3738
650
}
3739
3740
namespace {
3741
  struct OperandMatchEntry {
3742
    uint8_t RequiredFeatures;
3743
    uint16_t Mnemonic;
3744
    uint8_t Class;
3745
    uint8_t OperandMask;
3746
3747
1.02M
    StringRef getMnemonic() const {
3748
1.02M
      return StringRef(MnemonicTable + Mnemonic + 1,
3749
1.02M
                       MnemonicTable[Mnemonic]);
3750
1.02M
    }
3751
  };
3752
3753
  // Predicate for searching for an opcode.
3754
  struct LessOpcodeOperand {
3755
539k
    bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {
3756
539k
      return LHS.getMnemonic()  < RHS;
3757
539k
    }
3758
477k
    bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {
3759
477k
      return LHS < RHS.getMnemonic();
3760
477k
    }
3761
0
    bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) {
3762
0
      return LHS.getMnemonic() < RHS.getMnemonic();
3763
0
    }
3764
  };
3765
} // end anonymous namespace.
3766
3767
static const OperandMatchEntry OperandMatchTable[84] = {
3768
  /* Operand List Mask, Mnemonic, Operand Class, Features */
3769
  { 0, 252 /* call */, MCK_MEMri, 1 /* 0 */ },
3770
  { 0, 252 /* call */, MCK_MEMrr, 1 /* 0 */ },
3771
  { 0, 266 /* clr */, MCK_MEMri, 2 /* 1 */ },
3772
  { 0, 266 /* clr */, MCK_MEMrr, 2 /* 1 */ },
3773
  { 0, 270 /* clrb */, MCK_MEMri, 2 /* 1 */ },
3774
  { 0, 270 /* clrb */, MCK_MEMrr, 2 /* 1 */ },
3775
  { 0, 275 /* clrh */, MCK_MEMri, 2 /* 1 */ },
3776
  { 0, 275 /* clrh */, MCK_MEMrr, 2 /* 1 */ },
3777
  { 0, 829 /* flush */, MCK_MEMri, 1 /* 0 */ },
3778
  { 0, 829 /* flush */, MCK_MEMrr, 1 /* 0 */ },
3779
  { 0, 2322 /* jmp */, MCK_MEMri, 1 /* 0 */ },
3780
  { 0, 2322 /* jmp */, MCK_MEMrr, 1 /* 0 */ },
3781
  { 0, 2326 /* jmpl */, MCK_MEMri, 1 /* 0 */ },
3782
  { 0, 2326 /* jmpl */, MCK_MEMrr, 1 /* 0 */ },
3783
  { 0, 2331 /* ld */, MCK_MEMri, 2 /* 1 */ },
3784
  { 0, 2331 /* ld */, MCK_MEMri, 2 /* 1 */ },
3785
  { 0, 2331 /* ld */, MCK_MEMri, 2 /* 1 */ },
3786
  { 0, 2331 /* ld */, MCK_MEMrr, 2 /* 1 */ },
3787
  { 0, 2331 /* ld */, MCK_MEMrr, 2 /* 1 */ },
3788
  { 0, 2331 /* ld */, MCK_MEMrr, 2 /* 1 */ },
3789
  { Feature_HasV9, 2334 /* lda */, MCK_MEMrr, 2 /* 1 */ },
3790
  { 0, 2334 /* lda */, MCK_MEMrr, 2 /* 1 */ },
3791
  { 0, 2338 /* ldd */, MCK_MEMri, 2 /* 1 */ },
3792
  { 0, 2338 /* ldd */, MCK_MEMri, 2 /* 1 */ },
3793
  { 0, 2338 /* ldd */, MCK_MEMrr, 2 /* 1 */ },
3794
  { 0, 2338 /* ldd */, MCK_MEMrr, 2 /* 1 */ },
3795
  { 0, 2342 /* ldda */, MCK_MEMrr, 2 /* 1 */ },
3796
  { Feature_HasV9, 2342 /* ldda */, MCK_MEMrr, 2 /* 1 */ },
3797
  { Feature_HasV9, 2347 /* ldq */, MCK_MEMri, 2 /* 1 */ },
3798
  { Feature_HasV9, 2347 /* ldq */, MCK_MEMrr, 2 /* 1 */ },
3799
  { Feature_HasV9, 2351 /* ldqa */, MCK_MEMrr, 2 /* 1 */ },
3800
  { 0, 2356 /* ldsb */, MCK_MEMri, 2 /* 1 */ },
3801
  { 0, 2356 /* ldsb */, MCK_MEMrr, 2 /* 1 */ },
3802
  { 0, 2361 /* ldsba */, MCK_MEMrr, 2 /* 1 */ },
3803
  { 0, 2367 /* ldsh */, MCK_MEMri, 2 /* 1 */ },
3804
  { 0, 2367 /* ldsh */, MCK_MEMrr, 2 /* 1 */ },
3805
  { 0, 2372 /* ldsha */, MCK_MEMrr, 2 /* 1 */ },
3806
  { 0, 2378 /* ldstub */, MCK_MEMri, 2 /* 1 */ },
3807
  { 0, 2378 /* ldstub */, MCK_MEMrr, 2 /* 1 */ },
3808
  { 0, 2385 /* ldstuba */, MCK_MEMrr, 2 /* 1 */ },
3809
  { 0, 2393 /* ldsw */, MCK_MEMri, 2 /* 1 */ },
3810
  { 0, 2393 /* ldsw */, MCK_MEMrr, 2 /* 1 */ },
3811
  { 0, 2398 /* ldub */, MCK_MEMri, 2 /* 1 */ },
3812
  { 0, 2398 /* ldub */, MCK_MEMrr, 2 /* 1 */ },
3813
  { 0, 2403 /* lduba */, MCK_MEMrr, 2 /* 1 */ },
3814
  { 0, 2409 /* lduh */, MCK_MEMri, 2 /* 1 */ },
3815
  { 0, 2409 /* lduh */, MCK_MEMrr, 2 /* 1 */ },
3816
  { 0, 2414 /* lduha */, MCK_MEMrr, 2 /* 1 */ },
3817
  { Feature_HasV9, 2420 /* ldx */, MCK_MEMri, 2 /* 1 */ },
3818
  { 0, 2420 /* ldx */, MCK_MEMri, 2 /* 1 */ },
3819
  { Feature_HasV9, 2420 /* ldx */, MCK_MEMrr, 2 /* 1 */ },
3820
  { 0, 2420 /* ldx */, MCK_MEMrr, 2 /* 1 */ },
3821
  { 0, 2767 /* rett */, MCK_MEMri, 1 /* 0 */ },
3822
  { 0, 2767 /* rett */, MCK_MEMrr, 1 /* 0 */ },
3823
  { 0, 2864 /* st */, MCK_MEMri, 4 /* 2 */ },
3824
  { 0, 2864 /* st */, MCK_MEMrr, 4 /* 2 */ },
3825
  { 0, 2864 /* st */, MCK_MEMri, 4 /* 2 */ },
3826
  { 0, 2864 /* st */, MCK_MEMrr, 4 /* 2 */ },
3827
  { 0, 2864 /* st */, MCK_MEMri, 4 /* 2 */ },
3828
  { 0, 2864 /* st */, MCK_MEMrr, 4 /* 2 */ },
3829
  { Feature_HasV9, 2867 /* sta */, MCK_MEMrr, 4 /* 2 */ },
3830
  { 0, 2867 /* sta */, MCK_MEMrr, 4 /* 2 */ },
3831
  { 0, 2871 /* stb */, MCK_MEMri, 4 /* 2 */ },
3832
  { 0, 2871 /* stb */, MCK_MEMrr, 4 /* 2 */ },
3833
  { 0, 2875 /* stba */, MCK_MEMrr, 4 /* 2 */ },
3834
  { 0, 2886 /* std */, MCK_MEMri, 4 /* 2 */ },
3835
  { 0, 2886 /* std */, MCK_MEMrr, 4 /* 2 */ },
3836
  { 0, 2886 /* std */, MCK_MEMri, 4 /* 2 */ },
3837
  { 0, 2886 /* std */, MCK_MEMrr, 4 /* 2 */ },
3838
  { 0, 2890 /* stda */, MCK_MEMrr, 4 /* 2 */ },
3839
  { Feature_HasV9, 2890 /* stda */, MCK_MEMrr, 4 /* 2 */ },
3840
  { 0, 2895 /* sth */, MCK_MEMri, 4 /* 2 */ },
3841
  { 0, 2895 /* sth */, MCK_MEMrr, 4 /* 2 */ },
3842
  { 0, 2899 /* stha */, MCK_MEMrr, 4 /* 2 */ },
3843
  { Feature_HasV9, 2904 /* stq */, MCK_MEMri, 4 /* 2 */ },
3844
  { Feature_HasV9, 2904 /* stq */, MCK_MEMrr, 4 /* 2 */ },
3845
  { Feature_HasV9, 2908 /* stqa */, MCK_MEMrr, 4 /* 2 */ },
3846
  { Feature_HasV9, 2913 /* stx */, MCK_MEMri, 4 /* 2 */ },
3847
  { Feature_HasV9, 2913 /* stx */, MCK_MEMrr, 4 /* 2 */ },
3848
  { 0, 2913 /* stx */, MCK_MEMri, 4 /* 2 */ },
3849
  { 0, 2913 /* stx */, MCK_MEMrr, 4 /* 2 */ },
3850
  { 0, 2939 /* swap */, MCK_MEMri, 2 /* 1 */ },
3851
  { 0, 2939 /* swap */, MCK_MEMrr, 2 /* 1 */ },
3852
  { 0, 2944 /* swapa */, MCK_MEMrr, 2 /* 1 */ },
3853
};
3854
3855
SparcAsmParser::OperandMatchResultTy SparcAsmParser::
3856
tryCustomParseOperand(OperandVector &Operands,
3857
6.14k
                      unsigned MCK) {
3858
3859
6.14k
  switch(MCK) {
3860
3.09k
  case MCK_MEMri:
3861
3.09k
    return parseMEMOperand(Operands);
3862
3.05k
  case MCK_MEMrr:
3863
3.05k
    return parseMEMOperand(Operands);
3864
0
  default:
3865
0
    return MatchOperand_NoMatch;
3866
6.14k
  }
3867
0
  return MatchOperand_NoMatch;
3868
6.14k
}
3869
3870
SparcAsmParser::OperandMatchResultTy SparcAsmParser::
3871
MatchOperandParserImpl(OperandVector &Operands,
3872
80.1k
                       StringRef Mnemonic) {
3873
  // Get the current feature set.
3874
80.1k
  uint64_t AvailableFeatures = getAvailableFeatures();
3875
3876
  // Get the next operand index.
3877
80.1k
  unsigned NextOpNum = Operands.size() - 1;
3878
  // Search the table.
3879
80.1k
  auto MnemonicRange =
3880
80.1k
    std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable),
3881
80.1k
                     Mnemonic, LessOpcodeOperand());
3882
3883
80.1k
  if (MnemonicRange.first == MnemonicRange.second)
3884
76.8k
    return MatchOperand_NoMatch;
3885
3886
3.33k
  for (const OperandMatchEntry *it = MnemonicRange.first,
3887
10.1k
       *ie = MnemonicRange.second; it != ie; ++it) {
3888
    // equal_range guarantees that instruction mnemonic matches.
3889
7.34k
    assert(Mnemonic == it->getMnemonic());
3890
3891
    // check if the available features match
3892
7.34k
    if ((AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) {
3893
81
      continue;
3894
81
    }
3895
3896
    // check if the operand in question has a custom parser.
3897
7.25k
    if (!(it->OperandMask & (1 << NextOpNum)))
3898
1.11k
      continue;
3899
3900
    // call custom parse method to handle the operand
3901
6.14k
    OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class);
3902
6.14k
    if (Result != MatchOperand_NoMatch)
3903
537
      return Result;
3904
6.14k
  }
3905
3906
  // Okay, we had no match.
3907
2.80k
  return MatchOperand_NoMatch;
3908
3.33k
}
3909
3910
#endif // GET_MATCHER_IMPLEMENTATION
3911