/src/keystone/llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp

Source
//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file provides X86 specific target descriptions.
//
//===----------------------------------------------------------------------===//

#include "X86MCTargetDesc.h"
#include "X86MCAsmInfo.h"
#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MachineLocation.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/Host.h"
#include "llvm/Support/TargetRegistry.h"

#if _MSC_VER
#include <intrin.h>
#endif

using namespace llvm_ks;

#define GET_REGINFO_MC_DESC
#include "X86GenRegisterInfo.inc"

#define GET_INSTRINFO_MC_DESC
#include "X86GenInstrInfo.inc"

#define GET_SUBTARGETINFO_MC_DESC
#include "X86GenSubtargetInfo.inc"

std::string X86_MC::ParseX86Triple(const Triple &TT) {
  std::string FS;
  if (TT.getArch() == Triple::x86_64)
    FS = "+64bit-mode,-32bit-mode,-16bit-mode";
  else if (TT.getEnvironment() != Triple::CODE16)
    FS = "-64bit-mode,+32bit-mode,-16bit-mode";
  else
    FS = "-64bit-mode,-32bit-mode,+16bit-mode";

  return FS;
}

unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
  if (TT.getArch() == Triple::x86_64)
    return DWARFFlavour::X86_64;

  if (TT.isOSDarwin())
    return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
  if (TT.isOSCygMing())
    // Unsupported by now, just quick fallback
    return DWARFFlavour::X86_32_Generic;
  return DWARFFlavour::X86_32_Generic;
}

void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
  // FIXME: TableGen these.
  for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
    unsigned SEH = MRI->getEncodingValue(Reg);
    MRI->mapLLVMRegToSEHReg(Reg, SEH);
  }
}

MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
                                                  StringRef CPU, StringRef FS) {
  std::string ArchFS = X86_MC::ParseX86Triple(TT);
  if (!FS.empty()) {
    if (!ArchFS.empty())
      ArchFS = (Twine(ArchFS) + "," + FS).str();
    else
      ArchFS = FS;
  }

  std::string CPUName = CPU;
  if (CPUName.empty())
    CPUName = "generic";

  return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
}

static MCInstrInfo *createX86MCInstrInfo() {
  MCInstrInfo *X = new MCInstrInfo();
  InitX86MCInstrInfo(X);
  return X;
}

static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
  unsigned RA = (TT.getArch() == Triple::x86_64)
                    ? X86::RIP  // Should have dwarf #16.
                    : X86::EIP; // Should have dwarf #8.

  MCRegisterInfo *X = new MCRegisterInfo();
  InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
                        X86_MC::getDwarfRegFlavour(TT, true), RA);
  X86_MC::InitLLVM2SEHRegisterMapping(X);
  return X;
}

static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
                                     const Triple &TheTriple) {
  bool is64Bit = TheTriple.getArch() == Triple::x86_64;

  MCAsmInfo *MAI;
  if (TheTriple.isOSBinFormatMachO()) {
    if (is64Bit)
      MAI = new X86_64MCAsmInfoDarwin(TheTriple);
    else
      MAI = new X86MCAsmInfoDarwin(TheTriple);
  } else if (TheTriple.isOSBinFormatELF()) {
    // Force the use of an ELF container.
    MAI = new X86ELFMCAsmInfo(TheTriple);
  } else if (TheTriple.isWindowsMSVCEnvironment() ||
             TheTriple.isWindowsCoreCLREnvironment()) {
    MAI = new X86MCAsmInfoMicrosoft(TheTriple);
  } else if (TheTriple.isOSCygMing() ||
             TheTriple.isWindowsItaniumEnvironment()) {
    MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
  } else {
    // The default is ELF.
    MAI = new X86ELFMCAsmInfo(TheTriple);
  }

  // Initialize initial frame state.
  // Calculate amount of bytes used for return address storing
  int stackGrowth = is64Bit ? -8 : -4;

  // Initial state of the frame pointer is esp+stackGrowth.
  unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
  MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
      nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
  MAI->addInitialFrameState(Inst);

  // Add return address to move list
  unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
  MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
      nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
  MAI->addInitialFrameState(Inst2);

  return MAI;
}

static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
                                                   MCContext &Ctx) {
  // Default to the stock relocation info.
  return NULL;
}

// Force static initialization.
extern "C" void LLVMInitializeX86TargetMC() {
  for (Target *T : {&TheX86_32Target, &TheX86_64Target}) {
    // Register the MC asm info.
    RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);

    // Register the MC instruction info.
    TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);

    // Register the MC register info.
    TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);

    // Register the MC subtarget info.
    TargetRegistry::RegisterMCSubtargetInfo(*T,
                                            X86_MC::createX86MCSubtargetInfo);

    // Register the code emitter.
    TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);

    // Register the MC relocation info.
    TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
  }

  // Register the asm backend.
  TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
                                       createX86_32AsmBackend);
  TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
                                       createX86_64AsmBackend);
}

unsigned llvm_ks::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
                                            bool High) {
  switch (Size) {
  default: return 0;
  case 8:
    if (High) {
      switch (Reg) {
      default: return getX86SubSuperRegisterOrZero(Reg, 64);
      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
        return X86::SI;
      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
        return X86::DI;
      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
        return X86::BP;
      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
        return X86::SP;
      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
        return X86::AH;
      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
        return X86::DH;
      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
        return X86::CH;
      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
        return X86::BH;
      }
    } else {
      switch (Reg) {
      default: return 0;
      case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
        return X86::AL;
      case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
        return X86::DL;
      case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
        return X86::CL;
      case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
        return X86::BL;
      case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
        return X86::SIL;
      case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
        return X86::DIL;
      case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
        return X86::BPL;
      case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
        return X86::SPL;
      case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
        return X86::R8B;
      case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
        return X86::R9B;
      case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
        return X86::R10B;
      case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
        return X86::R11B;
      case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
        return X86::R12B;
      case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
        return X86::R13B;
      case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
        return X86::R14B;
      case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
        return X86::R15B;
      }
    }
  case 16:
    switch (Reg) {
    default: return 0;
    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
      return X86::AX;
    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
      return X86::DX;
    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
      return X86::CX;
    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
      return X86::BX;
    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
      return X86::SI;
    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
      return X86::DI;
    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
      return X86::BP;
    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
      return X86::SP;
    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
      return X86::R8W;
    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
      return X86::R9W;
    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
      return X86::R10W;
    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
      return X86::R11W;
    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
      return X86::R12W;
    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
      return X86::R13W;
    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
      return X86::R14W;
    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
      return X86::R15W;
    }
  case 32:
    switch (Reg) {
    default: return 0;
    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
      return X86::EAX;
    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
      return X86::EDX;
    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
      return X86::ECX;
    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
      return X86::EBX;
    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
      return X86::ESI;
    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
      return X86::EDI;
    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
      return X86::EBP;
    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
      return X86::ESP;
    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
      return X86::R8D;
    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
      return X86::R9D;
    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
      return X86::R10D;
    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
      return X86::R11D;
    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
      return X86::R12D;
    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
      return X86::R13D;
    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
      return X86::R14D;
    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
      return X86::R15D;
    }
  case 64:
    switch (Reg) {
    default: return 0;
    case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
      return X86::RAX;
    case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
      return X86::RDX;
    case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
      return X86::RCX;
    case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
      return X86::RBX;
    case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
      return X86::RSI;
    case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
      return X86::RDI;
    case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
      return X86::RBP;
    case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
      return X86::RSP;
    case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
      return X86::R8;
    case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
      return X86::R9;
    case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
      return X86::R10;
    case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
      return X86::R11;
    case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
      return X86::R12;
    case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
      return X86::R13;
    case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
      return X86::R14;
    case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
      return X86::R15;
    }
  }
}

unsigned llvm_ks::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
  unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
  assert(Res != 0 && "Unexpected register or VT");
  return Res;
}



Coverage Report

Created: 2025-11-16 07:15

Line	Count	Source
1		//===-- X86MCTargetDesc.cpp - X86 Target Descriptions ---------------------===//
2		//
3		// The LLVM Compiler Infrastructure
4		//
5		// This file is distributed under the University of Illinois Open Source
6		// License. See LICENSE.TXT for details.
7		//
8		//===----------------------------------------------------------------------===//
9		//
10		// This file provides X86 specific target descriptions.
11		//
12		//===----------------------------------------------------------------------===//
13
14		#include "X86MCTargetDesc.h"
15		#include "X86MCAsmInfo.h"
16		#include "llvm/ADT/Triple.h"
17		#include "llvm/MC/MCInstrInfo.h"
18		#include "llvm/MC/MCRegisterInfo.h"
19		#include "llvm/MC/MCStreamer.h"
20		#include "llvm/MC/MCSubtargetInfo.h"
21		#include "llvm/MC/MachineLocation.h"
22		#include "llvm/Support/ErrorHandling.h"
23		#include "llvm/Support/Host.h"
24		#include "llvm/Support/TargetRegistry.h"
25
26		#if _MSC_VER
27		#include <intrin.h>
28		#endif
29
30		using namespace llvm_ks;
31
32		#define GET_REGINFO_MC_DESC
33		#include "X86GenRegisterInfo.inc"
34
35		#define GET_INSTRINFO_MC_DESC
36		#include "X86GenInstrInfo.inc"
37
38		#define GET_SUBTARGETINFO_MC_DESC
39		#include "X86GenSubtargetInfo.inc"
40
41	13.3k	std::string X86_MC::ParseX86Triple(const Triple &TT) {
42	13.3k	std::string FS;
43	13.3k	if (TT.getArch() == Triple::x86_64)
44	383	FS = "+64bit-mode,-32bit-mode,-16bit-mode";
45	12.9k	else if (TT.getEnvironment() != Triple::CODE16)
46	1.81k	FS = "-64bit-mode,+32bit-mode,-16bit-mode";
47	11.1k	else
48	11.1k	FS = "-64bit-mode,-32bit-mode,+16bit-mode";
49
50	13.3k	return FS;
51	13.3k	}
52
53	26.6k	unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
54	26.6k	if (TT.getArch() == Triple::x86_64)
55	766	return DWARFFlavour::X86_64;
56
57	25.9k	if (TT.isOSDarwin())
58	0	return isEH ? DWARFFlavour::X86_32_DarwinEH : DWARFFlavour::X86_32_Generic;
59	25.9k	if (TT.isOSCygMing())
60		// Unsupported by now, just quick fallback
61	0	return DWARFFlavour::X86_32_Generic;
62	25.9k	return DWARFFlavour::X86_32_Generic;
63	25.9k	}
64
65	13.3k	void X86_MC::InitLLVM2SEHRegisterMapping(MCRegisterInfo *MRI) {
66		// FIXME: TableGen these.
67	3.28M	for (unsigned Reg = X86::NoRegister+1; Reg < X86::NUM_TARGET_REGS; ++Reg) {
68	3.27M	unsigned SEH = MRI->getEncodingValue(Reg);
69	3.27M	MRI->mapLLVMRegToSEHReg(Reg, SEH);
70	3.27M	}
71	13.3k	}
72
73		MCSubtargetInfo *X86_MC::createX86MCSubtargetInfo(const Triple &TT,
74	13.3k	StringRef CPU, StringRef FS) {
75	13.3k	std::string ArchFS = X86_MC::ParseX86Triple(TT);
76	13.3k	if (!FS.empty()) {
77	0	if (!ArchFS.empty())
78	0	ArchFS = (Twine(ArchFS) + "," + FS).str();
79	0	else
80	0	ArchFS = FS;
81	0	}
82
83	13.3k	std::string CPUName = CPU;
84	13.3k	if (CPUName.empty())
85	0	CPUName = "generic";
86
87	13.3k	return createX86MCSubtargetInfoImpl(TT, CPUName, ArchFS);
88	13.3k	}
89
90	13.3k	static MCInstrInfo *createX86MCInstrInfo() {
91	13.3k	MCInstrInfo *X = new MCInstrInfo();
92	13.3k	InitX86MCInstrInfo(X);
93	13.3k	return X;
94	13.3k	}
95
96	13.3k	static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
97	13.3k	unsigned RA = (TT.getArch() == Triple::x86_64)
98	13.3k	? X86::RIP // Should have dwarf #16.
99	13.3k	: X86::EIP; // Should have dwarf #8.
100
101	13.3k	MCRegisterInfo *X = new MCRegisterInfo();
102	13.3k	InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
103	13.3k	X86_MC::getDwarfRegFlavour(TT, true), RA);
104	13.3k	X86_MC::InitLLVM2SEHRegisterMapping(X);
105	13.3k	return X;
106	13.3k	}
107
108		static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
109	13.3k	const Triple &TheTriple) {
110	13.3k	bool is64Bit = TheTriple.getArch() == Triple::x86_64;
111
112	13.3k	MCAsmInfo *MAI;
113	13.3k	if (TheTriple.isOSBinFormatMachO()) {
114	0	if (is64Bit)
115	0	MAI = new X86_64MCAsmInfoDarwin(TheTriple);
116	0	else
117	0	MAI = new X86MCAsmInfoDarwin(TheTriple);
118	13.3k	} else if (TheTriple.isOSBinFormatELF()) {
119		// Force the use of an ELF container.
120	13.3k	MAI = new X86ELFMCAsmInfo(TheTriple);
121	13.3k	} else if (TheTriple.isWindowsMSVCEnvironment() \|\|
122	0	TheTriple.isWindowsCoreCLREnvironment()) {
123	0	MAI = new X86MCAsmInfoMicrosoft(TheTriple);
124	0	} else if (TheTriple.isOSCygMing() \|\|
125	0	TheTriple.isWindowsItaniumEnvironment()) {
126	0	MAI = new X86MCAsmInfoGNUCOFF(TheTriple);
127	0	} else {
128		// The default is ELF.
129	0	MAI = new X86ELFMCAsmInfo(TheTriple);
130	0	}
131
132		// Initialize initial frame state.
133		// Calculate amount of bytes used for return address storing
134	13.3k	int stackGrowth = is64Bit ? -8 : -4;
135
136		// Initial state of the frame pointer is esp+stackGrowth.
137	13.3k	unsigned StackPtr = is64Bit ? X86::RSP : X86::ESP;
138	13.3k	MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(
139	13.3k	nullptr, MRI.getDwarfRegNum(StackPtr, true), -stackGrowth);
140	13.3k	MAI->addInitialFrameState(Inst);
141
142		// Add return address to move list
143	13.3k	unsigned InstPtr = is64Bit ? X86::RIP : X86::EIP;
144	13.3k	MCCFIInstruction Inst2 = MCCFIInstruction::createOffset(
145	13.3k	nullptr, MRI.getDwarfRegNum(InstPtr, true), stackGrowth);
146	13.3k	MAI->addInitialFrameState(Inst2);
147
148	13.3k	return MAI;
149	13.3k	}
150
151		static MCRelocationInfo *createX86MCRelocationInfo(const Triple &TheTriple,
152	0	MCContext &Ctx) {
153		// Default to the stock relocation info.
154	0	return NULL;
155	0	}
156
157		// Force static initialization.
158	25	extern "C" void LLVMInitializeX86TargetMC() {
159	50	for (Target *T : {&TheX86_32Target, &TheX86_64Target}) {
160		// Register the MC asm info.
161	50	RegisterMCAsmInfoFn X(*T, createX86MCAsmInfo);
162
163		// Register the MC instruction info.
164	50	TargetRegistry::RegisterMCInstrInfo(*T, createX86MCInstrInfo);
165
166		// Register the MC register info.
167	50	TargetRegistry::RegisterMCRegInfo(*T, createX86MCRegisterInfo);
168
169		// Register the MC subtarget info.
170	50	TargetRegistry::RegisterMCSubtargetInfo(*T,
171	50	X86_MC::createX86MCSubtargetInfo);
172
173		// Register the code emitter.
174	50	TargetRegistry::RegisterMCCodeEmitter(*T, createX86MCCodeEmitter);
175
176		// Register the MC relocation info.
177	50	TargetRegistry::RegisterMCRelocationInfo(*T, createX86MCRelocationInfo);
178	50	}
179
180		// Register the asm backend.
181	25	TargetRegistry::RegisterMCAsmBackend(TheX86_32Target,
182	25	createX86_32AsmBackend);
183	25	TargetRegistry::RegisterMCAsmBackend(TheX86_64Target,
184	25	createX86_64AsmBackend);
185	25	}
186
187		unsigned llvm_ks::getX86SubSuperRegisterOrZero(unsigned Reg, unsigned Size,
188	0	bool High) {
189	0	switch (Size) {
190	0	default: return 0;
191	0	case 8:
192	0	if (High) {
193	0	switch (Reg) {
194	0	default: return getX86SubSuperRegisterOrZero(Reg, 64);
195	0	case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
196	0	return X86::SI;
197	0	case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
198	0	return X86::DI;
199	0	case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
200	0	return X86::BP;
201	0	case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
202	0	return X86::SP;
203	0	case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
204	0	return X86::AH;
205	0	case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
206	0	return X86::DH;
207	0	case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
208	0	return X86::CH;
209	0	case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
210	0	return X86::BH;
211	0	}
212	0	} else {
213	0	switch (Reg) {
214	0	default: return 0;
215	0	case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
216	0	return X86::AL;
217	0	case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
218	0	return X86::DL;
219	0	case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
220	0	return X86::CL;
221	0	case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
222	0	return X86::BL;
223	0	case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
224	0	return X86::SIL;
225	0	case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
226	0	return X86::DIL;
227	0	case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
228	0	return X86::BPL;
229	0	case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
230	0	return X86::SPL;
231	0	case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
232	0	return X86::R8B;
233	0	case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
234	0	return X86::R9B;
235	0	case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
236	0	return X86::R10B;
237	0	case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
238	0	return X86::R11B;
239	0	case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
240	0	return X86::R12B;
241	0	case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
242	0	return X86::R13B;
243	0	case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
244	0	return X86::R14B;
245	0	case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
246	0	return X86::R15B;
247	0	}
248	0	}
249	0	case 16:
250	0	switch (Reg) {
251	0	default: return 0;
252	0	case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
253	0	return X86::AX;
254	0	case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
255	0	return X86::DX;
256	0	case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
257	0	return X86::CX;
258	0	case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
259	0	return X86::BX;
260	0	case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
261	0	return X86::SI;
262	0	case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
263	0	return X86::DI;
264	0	case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
265	0	return X86::BP;
266	0	case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
267	0	return X86::SP;
268	0	case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
269	0	return X86::R8W;
270	0	case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
271	0	return X86::R9W;
272	0	case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
273	0	return X86::R10W;
274	0	case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
275	0	return X86::R11W;
276	0	case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
277	0	return X86::R12W;
278	0	case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
279	0	return X86::R13W;
280	0	case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
281	0	return X86::R14W;
282	0	case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
283	0	return X86::R15W;
284	0	}
285	0	case 32:
286	0	switch (Reg) {
287	0	default: return 0;
288	0	case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
289	0	return X86::EAX;
290	0	case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
291	0	return X86::EDX;
292	0	case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
293	0	return X86::ECX;
294	0	case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
295	0	return X86::EBX;
296	0	case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
297	0	return X86::ESI;
298	0	case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
299	0	return X86::EDI;
300	0	case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
301	0	return X86::EBP;
302	0	case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
303	0	return X86::ESP;
304	0	case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
305	0	return X86::R8D;
306	0	case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
307	0	return X86::R9D;
308	0	case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
309	0	return X86::R10D;
310	0	case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
311	0	return X86::R11D;
312	0	case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
313	0	return X86::R12D;
314	0	case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
315	0	return X86::R13D;
316	0	case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
317	0	return X86::R14D;
318	0	case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
319	0	return X86::R15D;
320	0	}
321	0	case 64:
322	0	switch (Reg) {
323	0	default: return 0;
324	0	case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX:
325	0	return X86::RAX;
326	0	case X86::DH: case X86::DL: case X86::DX: case X86::EDX: case X86::RDX:
327	0	return X86::RDX;
328	0	case X86::CH: case X86::CL: case X86::CX: case X86::ECX: case X86::RCX:
329	0	return X86::RCX;
330	0	case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
331	0	return X86::RBX;
332	0	case X86::SIL: case X86::SI: case X86::ESI: case X86::RSI:
333	0	return X86::RSI;
334	0	case X86::DIL: case X86::DI: case X86::EDI: case X86::RDI:
335	0	return X86::RDI;
336	0	case X86::BPL: case X86::BP: case X86::EBP: case X86::RBP:
337	0	return X86::RBP;
338	0	case X86::SPL: case X86::SP: case X86::ESP: case X86::RSP:
339	0	return X86::RSP;
340	0	case X86::R8B: case X86::R8W: case X86::R8D: case X86::R8:
341	0	return X86::R8;
342	0	case X86::R9B: case X86::R9W: case X86::R9D: case X86::R9:
343	0	return X86::R9;
344	0	case X86::R10B: case X86::R10W: case X86::R10D: case X86::R10:
345	0	return X86::R10;
346	0	case X86::R11B: case X86::R11W: case X86::R11D: case X86::R11:
347	0	return X86::R11;
348	0	case X86::R12B: case X86::R12W: case X86::R12D: case X86::R12:
349	0	return X86::R12;
350	0	case X86::R13B: case X86::R13W: case X86::R13D: case X86::R13:
351	0	return X86::R13;
352	0	case X86::R14B: case X86::R14W: case X86::R14D: case X86::R14:
353	0	return X86::R14;
354	0	case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15:
355	0	return X86::R15;
356	0	}
357	0	}
358	0	}
359
360	0	unsigned llvm_ks::getX86SubSuperRegister(unsigned Reg, unsigned Size, bool High) {
361	0	unsigned Res = getX86SubSuperRegisterOrZero(Reg, Size, High);
362	0	assert(Res != 0 && "Unexpected register or VT");
363	0	return Res;
364	0	}
365
366