Coverage Report

Created: 2025-12-27 06:12

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/keystone/llvm/lib/Target/PowerPC/PPCGenInstrInfo.inc
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Source
1
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2
|*                                                                            *|
3
|* Target Instruction Enum Values                                             *|
4
|*                                                                            *|
5
|* Automatically generated file, do not edit!                                 *|
6
|*                                                                            *|
7
\*===----------------------------------------------------------------------===*/
8
9
10
#ifdef GET_INSTRINFO_ENUM
11
#undef GET_INSTRINFO_ENUM
12
namespace llvm_ks {
13
14
namespace PPC {
15
  enum {
16
    PHI = 0,
17
    INLINEASM = 1,
18
    CFI_INSTRUCTION = 2,
19
    EH_LABEL  = 3,
20
    GC_LABEL  = 4,
21
    KILL  = 5,
22
    EXTRACT_SUBREG  = 6,
23
    INSERT_SUBREG = 7,
24
    IMPLICIT_DEF  = 8,
25
    SUBREG_TO_REG = 9,
26
    COPY_TO_REGCLASS  = 10,
27
    DBG_VALUE = 11,
28
    REG_SEQUENCE  = 12,
29
    COPY  = 13,
30
    BUNDLE  = 14,
31
    LIFETIME_START  = 15,
32
    LIFETIME_END  = 16,
33
    STACKMAP  = 17,
34
    PATCHPOINT  = 18,
35
    LOAD_STACK_GUARD  = 19,
36
    STATEPOINT  = 20,
37
    LOCAL_ESCAPE  = 21,
38
    FAULTING_LOAD_OP  = 22,
39
    G_ADD = 23,
40
    ADD4  = 24,
41
    ADD4TLS = 25,
42
    ADD4o = 26,
43
    ADD8  = 27,
44
    ADD8TLS = 28,
45
    ADD8TLS_  = 29,
46
    ADD8o = 30,
47
    ADDC  = 31,
48
    ADDC8 = 32,
49
    ADDC8o  = 33,
50
    ADDCo = 34,
51
    ADDE  = 35,
52
    ADDE8 = 36,
53
    ADDE8o  = 37,
54
    ADDEo = 38,
55
    ADDI  = 39,
56
    ADDI8 = 40,
57
    ADDIC = 41,
58
    ADDIC8  = 42,
59
    ADDICo  = 43,
60
    ADDIS = 44,
61
    ADDIS8  = 45,
62
    ADDISdtprelHA = 46,
63
    ADDISdtprelHA32 = 47,
64
    ADDISgotTprelHA = 48,
65
    ADDIStlsgdHA  = 49,
66
    ADDIStlsldHA  = 50,
67
    ADDIStocHA  = 51,
68
    ADDIdtprelL = 52,
69
    ADDIdtprelL32 = 53,
70
    ADDItlsgdL  = 54,
71
    ADDItlsgdL32  = 55,
72
    ADDItlsgdLADDR  = 56,
73
    ADDItlsgdLADDR32  = 57,
74
    ADDItlsldL  = 58,
75
    ADDItlsldL32  = 59,
76
    ADDItlsldLADDR  = 60,
77
    ADDItlsldLADDR32  = 61,
78
    ADDItocL  = 62,
79
    ADDME = 63,
80
    ADDME8  = 64,
81
    ADDME8o = 65,
82
    ADDMEo  = 66,
83
    ADDZE = 67,
84
    ADDZE8  = 68,
85
    ADDZE8o = 69,
86
    ADDZEo  = 70,
87
    ADJCALLSTACKDOWN  = 71,
88
    ADJCALLSTACKUP  = 72,
89
    AND = 73,
90
    AND8  = 74,
91
    AND8o = 75,
92
    ANDC  = 76,
93
    ANDC8 = 77,
94
    ANDC8o  = 78,
95
    ANDCo = 79,
96
    ANDISo  = 80,
97
    ANDISo8 = 81,
98
    ANDIo = 82,
99
    ANDIo8  = 83,
100
    ANDIo_1_EQ_BIT  = 84,
101
    ANDIo_1_EQ_BIT8 = 85,
102
    ANDIo_1_GT_BIT  = 86,
103
    ANDIo_1_GT_BIT8 = 87,
104
    ANDo  = 88,
105
    ATOMIC_CMP_SWAP_I16 = 89,
106
    ATOMIC_CMP_SWAP_I32 = 90,
107
    ATOMIC_CMP_SWAP_I64 = 91,
108
    ATOMIC_CMP_SWAP_I8  = 92,
109
    ATOMIC_LOAD_ADD_I16 = 93,
110
    ATOMIC_LOAD_ADD_I32 = 94,
111
    ATOMIC_LOAD_ADD_I64 = 95,
112
    ATOMIC_LOAD_ADD_I8  = 96,
113
    ATOMIC_LOAD_AND_I16 = 97,
114
    ATOMIC_LOAD_AND_I32 = 98,
115
    ATOMIC_LOAD_AND_I64 = 99,
116
    ATOMIC_LOAD_AND_I8  = 100,
117
    ATOMIC_LOAD_NAND_I16  = 101,
118
    ATOMIC_LOAD_NAND_I32  = 102,
119
    ATOMIC_LOAD_NAND_I64  = 103,
120
    ATOMIC_LOAD_NAND_I8 = 104,
121
    ATOMIC_LOAD_OR_I16  = 105,
122
    ATOMIC_LOAD_OR_I32  = 106,
123
    ATOMIC_LOAD_OR_I64  = 107,
124
    ATOMIC_LOAD_OR_I8 = 108,
125
    ATOMIC_LOAD_SUB_I16 = 109,
126
    ATOMIC_LOAD_SUB_I32 = 110,
127
    ATOMIC_LOAD_SUB_I64 = 111,
128
    ATOMIC_LOAD_SUB_I8  = 112,
129
    ATOMIC_LOAD_XOR_I16 = 113,
130
    ATOMIC_LOAD_XOR_I32 = 114,
131
    ATOMIC_LOAD_XOR_I64 = 115,
132
    ATOMIC_LOAD_XOR_I8  = 116,
133
    ATOMIC_SWAP_I16 = 117,
134
    ATOMIC_SWAP_I32 = 118,
135
    ATOMIC_SWAP_I64 = 119,
136
    ATOMIC_SWAP_I8  = 120,
137
    ATTN  = 121,
138
    B = 122,
139
    BA  = 123,
140
    BC  = 124,
141
    BCC = 125,
142
    BCCA  = 126,
143
    BCCCTR  = 127,
144
    BCCCTR8 = 128,
145
    BCCCTRL = 129,
146
    BCCCTRL8  = 130,
147
    BCCL  = 131,
148
    BCCLA = 132,
149
    BCCLR = 133,
150
    BCCLRL  = 134,
151
    BCCTR = 135,
152
    BCCTR8  = 136,
153
    BCCTR8n = 137,
154
    BCCTRL  = 138,
155
    BCCTRL8 = 139,
156
    BCCTRL8n  = 140,
157
    BCCTRLn = 141,
158
    BCCTRn  = 142,
159
    BCL = 143,
160
    BCLR  = 144,
161
    BCLRL = 145,
162
    BCLRLn  = 146,
163
    BCLRn = 147,
164
    BCLalways = 148,
165
    BCLn  = 149,
166
    BCTR  = 150,
167
    BCTR8 = 151,
168
    BCTRL = 152,
169
    BCTRL8  = 153,
170
    BCTRL8_LDinto_toc = 154,
171
    BCn = 155,
172
    BDNZ  = 156,
173
    BDNZ8 = 157,
174
    BDNZA = 158,
175
    BDNZAm  = 159,
176
    BDNZAp  = 160,
177
    BDNZL = 161,
178
    BDNZLA  = 162,
179
    BDNZLAm = 163,
180
    BDNZLAp = 164,
181
    BDNZLR  = 165,
182
    BDNZLR8 = 166,
183
    BDNZLRL = 167,
184
    BDNZLRLm  = 168,
185
    BDNZLRLp  = 169,
186
    BDNZLRm = 170,
187
    BDNZLRp = 171,
188
    BDNZLm  = 172,
189
    BDNZLp  = 173,
190
    BDNZm = 174,
191
    BDNZp = 175,
192
    BDZ = 176,
193
    BDZ8  = 177,
194
    BDZA  = 178,
195
    BDZAm = 179,
196
    BDZAp = 180,
197
    BDZL  = 181,
198
    BDZLA = 182,
199
    BDZLAm  = 183,
200
    BDZLAp  = 184,
201
    BDZLR = 185,
202
    BDZLR8  = 186,
203
    BDZLRL  = 187,
204
    BDZLRLm = 188,
205
    BDZLRLp = 189,
206
    BDZLRm  = 190,
207
    BDZLRp  = 191,
208
    BDZLm = 192,
209
    BDZLp = 193,
210
    BDZm  = 194,
211
    BDZp  = 195,
212
    BL  = 196,
213
    BL8 = 197,
214
    BL8_NOP = 198,
215
    BL8_NOP_TLS = 199,
216
    BL8_TLS = 200,
217
    BL8_TLS_  = 201,
218
    BLA = 202,
219
    BLA8  = 203,
220
    BLA8_NOP  = 204,
221
    BLR = 205,
222
    BLR8  = 206,
223
    BLRL  = 207,
224
    BL_TLS  = 208,
225
    BPERMD  = 209,
226
    BRINC = 210,
227
    CLRBHRB = 211,
228
    CLRLSLDI  = 212,
229
    CLRLSLDIo = 213,
230
    CLRLSLWI  = 214,
231
    CLRLSLWIo = 215,
232
    CLRRDI  = 216,
233
    CLRRDIo = 217,
234
    CLRRWI  = 218,
235
    CLRRWIo = 219,
236
    CMPB  = 220,
237
    CMPB8 = 221,
238
    CMPD  = 222,
239
    CMPDI = 223,
240
    CMPLD = 224,
241
    CMPLDI  = 225,
242
    CMPLW = 226,
243
    CMPLWI  = 227,
244
    CMPW  = 228,
245
    CMPWI = 229,
246
    CNTLZD  = 230,
247
    CNTLZDo = 231,
248
    CNTLZW  = 232,
249
    CNTLZW8 = 233,
250
    CNTLZW8o  = 234,
251
    CNTLZWo = 235,
252
    CR6SET  = 236,
253
    CR6UNSET  = 237,
254
    CRAND = 238,
255
    CRANDC  = 239,
256
    CREQV = 240,
257
    CRNAND  = 241,
258
    CRNOR = 242,
259
    CROR  = 243,
260
    CRORC = 244,
261
    CRSET = 245,
262
    CRUNSET = 246,
263
    CRXOR = 247,
264
    DCBA  = 248,
265
    DCBF  = 249,
266
    DCBI  = 250,
267
    DCBST = 251,
268
    DCBT  = 252,
269
    DCBTCT  = 253,
270
    DCBTDS  = 254,
271
    DCBTST  = 255,
272
    DCBTSTCT  = 256,
273
    DCBTSTDS  = 257,
274
    DCBTSTT = 258,
275
    DCBTSTx = 259,
276
    DCBTT = 260,
277
    DCBTx = 261,
278
    DCBZ  = 262,
279
    DCBZL = 263,
280
    DCCCI = 264,
281
    DIVD  = 265,
282
    DIVDE = 266,
283
    DIVDEU  = 267,
284
    DIVDEUo = 268,
285
    DIVDEo  = 269,
286
    DIVDU = 270,
287
    DIVDUo  = 271,
288
    DIVDo = 272,
289
    DIVW  = 273,
290
    DIVWE = 274,
291
    DIVWEU  = 275,
292
    DIVWEUo = 276,
293
    DIVWEo  = 277,
294
    DIVWU = 278,
295
    DIVWUo  = 279,
296
    DIVWo = 280,
297
    DSS = 281,
298
    DSSALL  = 282,
299
    DST = 283,
300
    DST64 = 284,
301
    DSTST = 285,
302
    DSTST64 = 286,
303
    DSTSTT  = 287,
304
    DSTSTT64  = 288,
305
    DSTT  = 289,
306
    DSTT64  = 290,
307
    DYNALLOC  = 291,
308
    DYNALLOC8 = 292,
309
    DYNAREAOFFSET = 293,
310
    DYNAREAOFFSET8  = 294,
311
    EH_SjLj_LongJmp32 = 295,
312
    EH_SjLj_LongJmp64 = 296,
313
    EH_SjLj_SetJmp32  = 297,
314
    EH_SjLj_SetJmp64  = 298,
315
    EH_SjLj_Setup = 299,
316
    EQV = 300,
317
    EQV8  = 301,
318
    EQV8o = 302,
319
    EQVo  = 303,
320
    EVABS = 304,
321
    EVADDIW = 305,
322
    EVADDSMIAAW = 306,
323
    EVADDSSIAAW = 307,
324
    EVADDUMIAAW = 308,
325
    EVADDUSIAAW = 309,
326
    EVADDW  = 310,
327
    EVAND = 311,
328
    EVANDC  = 312,
329
    EVCMPEQ = 313,
330
    EVCMPGTS  = 314,
331
    EVCMPGTU  = 315,
332
    EVCMPLTS  = 316,
333
    EVCMPLTU  = 317,
334
    EVCNTLSW  = 318,
335
    EVCNTLZW  = 319,
336
    EVDIVWS = 320,
337
    EVDIVWU = 321,
338
    EVEQV = 322,
339
    EVEXTSB = 323,
340
    EVEXTSH = 324,
341
    EVLDD = 325,
342
    EVLDDX  = 326,
343
    EVLDH = 327,
344
    EVLDHX  = 328,
345
    EVLDW = 329,
346
    EVLDWX  = 330,
347
    EVLHHESPLAT = 331,
348
    EVLHHESPLATX  = 332,
349
    EVLHHOSSPLAT  = 333,
350
    EVLHHOSSPLATX = 334,
351
    EVLHHOUSPLAT  = 335,
352
    EVLHHOUSPLATX = 336,
353
    EVLWHE  = 337,
354
    EVLWHEX = 338,
355
    EVLWHOS = 339,
356
    EVLWHOSX  = 340,
357
    EVLWHOU = 341,
358
    EVLWHOUX  = 342,
359
    EVLWHSPLAT  = 343,
360
    EVLWHSPLATX = 344,
361
    EVLWWSPLAT  = 345,
362
    EVLWWSPLATX = 346,
363
    EVMERGEHI = 347,
364
    EVMERGEHILO = 348,
365
    EVMERGELO = 349,
366
    EVMERGELOHI = 350,
367
    EVMHEGSMFAA = 351,
368
    EVMHEGSMFAN = 352,
369
    EVMHEGSMIAA = 353,
370
    EVMHEGSMIAN = 354,
371
    EVMHEGUMIAA = 355,
372
    EVMHEGUMIAN = 356,
373
    EVMHESMF  = 357,
374
    EVMHESMFA = 358,
375
    EVMHESMFAAW = 359,
376
    EVMHESMFANW = 360,
377
    EVMHESMI  = 361,
378
    EVMHESMIA = 362,
379
    EVMHESMIAAW = 363,
380
    EVMHESMIANW = 364,
381
    EVMHESSF  = 365,
382
    EVMHESSFA = 366,
383
    EVMHESSFAAW = 367,
384
    EVMHESSFANW = 368,
385
    EVMHESSIAAW = 369,
386
    EVMHESSIANW = 370,
387
    EVMHEUMI  = 371,
388
    EVMHEUMIA = 372,
389
    EVMHEUMIAAW = 373,
390
    EVMHEUMIANW = 374,
391
    EVMHEUSIAAW = 375,
392
    EVMHEUSIANW = 376,
393
    EVMHOGSMFAA = 377,
394
    EVMHOGSMFAN = 378,
395
    EVMHOGSMIAA = 379,
396
    EVMHOGSMIAN = 380,
397
    EVMHOGUMIAA = 381,
398
    EVMHOGUMIAN = 382,
399
    EVMHOSMF  = 383,
400
    EVMHOSMFA = 384,
401
    EVMHOSMFAAW = 385,
402
    EVMHOSMFANW = 386,
403
    EVMHOSMI  = 387,
404
    EVMHOSMIA = 388,
405
    EVMHOSMIAAW = 389,
406
    EVMHOSMIANW = 390,
407
    EVMHOSSF  = 391,
408
    EVMHOSSFA = 392,
409
    EVMHOSSFAAW = 393,
410
    EVMHOSSFANW = 394,
411
    EVMHOSSIAAW = 395,
412
    EVMHOSSIANW = 396,
413
    EVMHOUMI  = 397,
414
    EVMHOUMIA = 398,
415
    EVMHOUMIAAW = 399,
416
    EVMHOUMIANW = 400,
417
    EVMHOUSIAAW = 401,
418
    EVMHOUSIANW = 402,
419
    EVMRA = 403,
420
    EVMWHSMF  = 404,
421
    EVMWHSMFA = 405,
422
    EVMWHSMI  = 406,
423
    EVMWHSMIA = 407,
424
    EVMWHSSF  = 408,
425
    EVMWHSSFA = 409,
426
    EVMWHUMI  = 410,
427
    EVMWHUMIA = 411,
428
    EVMWLSMIAAW = 412,
429
    EVMWLSMIANW = 413,
430
    EVMWLSSIAAW = 414,
431
    EVMWLSSIANW = 415,
432
    EVMWLUMI  = 416,
433
    EVMWLUMIA = 417,
434
    EVMWLUMIAAW = 418,
435
    EVMWLUMIANW = 419,
436
    EVMWLUSIAAW = 420,
437
    EVMWLUSIANW = 421,
438
    EVMWSMF = 422,
439
    EVMWSMFA  = 423,
440
    EVMWSMFAA = 424,
441
    EVMWSMFAN = 425,
442
    EVMWSMI = 426,
443
    EVMWSMIA  = 427,
444
    EVMWSMIAA = 428,
445
    EVMWSMIAN = 429,
446
    EVMWSSF = 430,
447
    EVMWSSFA  = 431,
448
    EVMWSSFAA = 432,
449
    EVMWSSFAN = 433,
450
    EVMWUMI = 434,
451
    EVMWUMIA  = 435,
452
    EVMWUMIAA = 436,
453
    EVMWUMIAN = 437,
454
    EVNAND  = 438,
455
    EVNEG = 439,
456
    EVNOR = 440,
457
    EVOR  = 441,
458
    EVORC = 442,
459
    EVRLW = 443,
460
    EVRLWI  = 444,
461
    EVRNDW  = 445,
462
    EVSLW = 446,
463
    EVSLWI  = 447,
464
    EVSPLATFI = 448,
465
    EVSPLATI  = 449,
466
    EVSRWIS = 450,
467
    EVSRWIU = 451,
468
    EVSRWS  = 452,
469
    EVSRWU  = 453,
470
    EVSTDD  = 454,
471
    EVSTDDX = 455,
472
    EVSTDH  = 456,
473
    EVSTDHX = 457,
474
    EVSTDW  = 458,
475
    EVSTDWX = 459,
476
    EVSTWHE = 460,
477
    EVSTWHEX  = 461,
478
    EVSTWHO = 462,
479
    EVSTWHOX  = 463,
480
    EVSTWWE = 464,
481
    EVSTWWEX  = 465,
482
    EVSTWWO = 466,
483
    EVSTWWOX  = 467,
484
    EVSUBFSMIAAW  = 468,
485
    EVSUBFSSIAAW  = 469,
486
    EVSUBFUMIAAW  = 470,
487
    EVSUBFUSIAAW  = 471,
488
    EVSUBFW = 472,
489
    EVSUBIFW  = 473,
490
    EVXOR = 474,
491
    EXTLDI  = 475,
492
    EXTLDIo = 476,
493
    EXTLWI  = 477,
494
    EXTLWIo = 478,
495
    EXTRDI  = 479,
496
    EXTRDIo = 480,
497
    EXTRWI  = 481,
498
    EXTRWIo = 482,
499
    EXTSB = 483,
500
    EXTSB8  = 484,
501
    EXTSB8_32_64  = 485,
502
    EXTSB8o = 486,
503
    EXTSBo  = 487,
504
    EXTSH = 488,
505
    EXTSH8  = 489,
506
    EXTSH8_32_64  = 490,
507
    EXTSH8o = 491,
508
    EXTSHo  = 492,
509
    EXTSW = 493,
510
    EXTSW_32_64 = 494,
511
    EXTSW_32_64o  = 495,
512
    EXTSWo  = 496,
513
    EnforceIEIO = 497,
514
    FABSD = 498,
515
    FABSDo  = 499,
516
    FABSS = 500,
517
    FABSSo  = 501,
518
    FADD  = 502,
519
    FADDS = 503,
520
    FADDSo  = 504,
521
    FADDo = 505,
522
    FADDrtz = 506,
523
    FCFID = 507,
524
    FCFIDS  = 508,
525
    FCFIDSo = 509,
526
    FCFIDU  = 510,
527
    FCFIDUS = 511,
528
    FCFIDUSo  = 512,
529
    FCFIDUo = 513,
530
    FCFIDo  = 514,
531
    FCMPUD  = 515,
532
    FCMPUS  = 516,
533
    FCPSGND = 517,
534
    FCPSGNDo  = 518,
535
    FCPSGNS = 519,
536
    FCPSGNSo  = 520,
537
    FCTID = 521,
538
    FCTIDUZ = 522,
539
    FCTIDUZo  = 523,
540
    FCTIDZ  = 524,
541
    FCTIDZo = 525,
542
    FCTIDo  = 526,
543
    FCTIW = 527,
544
    FCTIWUZ = 528,
545
    FCTIWUZo  = 529,
546
    FCTIWZ  = 530,
547
    FCTIWZo = 531,
548
    FCTIWo  = 532,
549
    FDIV  = 533,
550
    FDIVS = 534,
551
    FDIVSo  = 535,
552
    FDIVo = 536,
553
    FMADD = 537,
554
    FMADDS  = 538,
555
    FMADDSo = 539,
556
    FMADDo  = 540,
557
    FMR = 541,
558
    FMRo  = 542,
559
    FMSUB = 543,
560
    FMSUBS  = 544,
561
    FMSUBSo = 545,
562
    FMSUBo  = 546,
563
    FMUL  = 547,
564
    FMULS = 548,
565
    FMULSo  = 549,
566
    FMULo = 550,
567
    FNABSD  = 551,
568
    FNABSDo = 552,
569
    FNABSS  = 553,
570
    FNABSSo = 554,
571
    FNEGD = 555,
572
    FNEGDo  = 556,
573
    FNEGS = 557,
574
    FNEGSo  = 558,
575
    FNMADD  = 559,
576
    FNMADDS = 560,
577
    FNMADDSo  = 561,
578
    FNMADDo = 562,
579
    FNMSUB  = 563,
580
    FNMSUBS = 564,
581
    FNMSUBSo  = 565,
582
    FNMSUBo = 566,
583
    FRE = 567,
584
    FRES  = 568,
585
    FRESo = 569,
586
    FREo  = 570,
587
    FRIMD = 571,
588
    FRIMDo  = 572,
589
    FRIMS = 573,
590
    FRIMSo  = 574,
591
    FRIND = 575,
592
    FRINDo  = 576,
593
    FRINS = 577,
594
    FRINSo  = 578,
595
    FRIPD = 579,
596
    FRIPDo  = 580,
597
    FRIPS = 581,
598
    FRIPSo  = 582,
599
    FRIZD = 583,
600
    FRIZDo  = 584,
601
    FRIZS = 585,
602
    FRIZSo  = 586,
603
    FRSP  = 587,
604
    FRSPo = 588,
605
    FRSQRTE = 589,
606
    FRSQRTES  = 590,
607
    FRSQRTESo = 591,
608
    FRSQRTEo  = 592,
609
    FSELD = 593,
610
    FSELDo  = 594,
611
    FSELS = 595,
612
    FSELSo  = 596,
613
    FSQRT = 597,
614
    FSQRTS  = 598,
615
    FSQRTSo = 599,
616
    FSQRTo  = 600,
617
    FSUB  = 601,
618
    FSUBS = 602,
619
    FSUBSo  = 603,
620
    FSUBo = 604,
621
    GETtlsADDR  = 605,
622
    GETtlsADDR32  = 606,
623
    GETtlsldADDR  = 607,
624
    GETtlsldADDR32  = 608,
625
    ICBI  = 609,
626
    ICBT  = 610,
627
    ICCCI = 611,
628
    INSLWI  = 612,
629
    INSLWIo = 613,
630
    INSRDI  = 614,
631
    INSRDIo = 615,
632
    INSRWI  = 616,
633
    INSRWIo = 617,
634
    ISEL  = 618,
635
    ISEL8 = 619,
636
    ISYNC = 620,
637
    LA  = 621,
638
    LAx = 622,
639
    LBARX = 623,
640
    LBARXL  = 624,
641
    LBZ = 625,
642
    LBZ8  = 626,
643
    LBZCIX  = 627,
644
    LBZU  = 628,
645
    LBZU8 = 629,
646
    LBZUX = 630,
647
    LBZUX8  = 631,
648
    LBZX  = 632,
649
    LBZX8 = 633,
650
    LD  = 634,
651
    LDARX = 635,
652
    LDARXL  = 636,
653
    LDBRX = 637,
654
    LDCIX = 638,
655
    LDU = 639,
656
    LDUX  = 640,
657
    LDX = 641,
658
    LDgotTprelL = 642,
659
    LDgotTprelL32 = 643,
660
    LDtoc = 644,
661
    LDtocBA = 645,
662
    LDtocCPT  = 646,
663
    LDtocJTI  = 647,
664
    LDtocL  = 648,
665
    LFD = 649,
666
    LFDU  = 650,
667
    LFDUX = 651,
668
    LFDX  = 652,
669
    LFIWAX  = 653,
670
    LFIWZX  = 654,
671
    LFS = 655,
672
    LFSU  = 656,
673
    LFSUX = 657,
674
    LFSX  = 658,
675
    LHA = 659,
676
    LHA8  = 660,
677
    LHARX = 661,
678
    LHARXL  = 662,
679
    LHAU  = 663,
680
    LHAU8 = 664,
681
    LHAUX = 665,
682
    LHAUX8  = 666,
683
    LHAX  = 667,
684
    LHAX8 = 668,
685
    LHBRX = 669,
686
    LHBRX8  = 670,
687
    LHZ = 671,
688
    LHZ8  = 672,
689
    LHZCIX  = 673,
690
    LHZU  = 674,
691
    LHZU8 = 675,
692
    LHZUX = 676,
693
    LHZUX8  = 677,
694
    LHZX  = 678,
695
    LHZX8 = 679,
696
    LI  = 680,
697
    LI8 = 681,
698
    LIS = 682,
699
    LIS8  = 683,
700
    LMW = 684,
701
    LSWI  = 685,
702
    LVEBX = 686,
703
    LVEHX = 687,
704
    LVEWX = 688,
705
    LVSL  = 689,
706
    LVSR  = 690,
707
    LVX = 691,
708
    LVXL  = 692,
709
    LWA = 693,
710
    LWARX = 694,
711
    LWARXL  = 695,
712
    LWAUX = 696,
713
    LWAX  = 697,
714
    LWAX_32 = 698,
715
    LWA_32  = 699,
716
    LWBRX = 700,
717
    LWBRX8  = 701,
718
    LWZ = 702,
719
    LWZ8  = 703,
720
    LWZCIX  = 704,
721
    LWZU  = 705,
722
    LWZU8 = 706,
723
    LWZUX = 707,
724
    LWZUX8  = 708,
725
    LWZX  = 709,
726
    LWZX8 = 710,
727
    LWZtoc  = 711,
728
    LXSDX = 712,
729
    LXSIWAX = 713,
730
    LXSIWZX = 714,
731
    LXSSPX  = 715,
732
    LXVD2X  = 716,
733
    LXVDSX  = 717,
734
    LXVW4X  = 718,
735
    MBAR  = 719,
736
    MCRF  = 720,
737
    MCRFS = 721,
738
    MFBHRBE = 722,
739
    MFCR  = 723,
740
    MFCR8 = 724,
741
    MFCTR = 725,
742
    MFCTR8  = 726,
743
    MFDCR = 727,
744
    MFFS  = 728,
745
    MFFSo = 729,
746
    MFLR  = 730,
747
    MFLR8 = 731,
748
    MFMSR = 732,
749
    MFOCRF  = 733,
750
    MFOCRF8 = 734,
751
    MFSPR = 735,
752
    MFSPR8  = 736,
753
    MFSR  = 737,
754
    MFSRIN  = 738,
755
    MFTB  = 739,
756
    MFTB8 = 740,
757
    MFVRSAVE  = 741,
758
    MFVRSAVEv = 742,
759
    MFVSCR  = 743,
760
    MFVSRD  = 744,
761
    MFVSRWZ = 745,
762
    MSYNC = 746,
763
    MTCRF = 747,
764
    MTCRF8  = 748,
765
    MTCTR = 749,
766
    MTCTR8  = 750,
767
    MTCTR8loop  = 751,
768
    MTCTRloop = 752,
769
    MTDCR = 753,
770
    MTFSB0  = 754,
771
    MTFSB1  = 755,
772
    MTFSF = 756,
773
    MTFSFI  = 757,
774
    MTFSFIo = 758,
775
    MTFSFb  = 759,
776
    MTFSFo  = 760,
777
    MTLR  = 761,
778
    MTLR8 = 762,
779
    MTMSR = 763,
780
    MTMSRD  = 764,
781
    MTOCRF  = 765,
782
    MTOCRF8 = 766,
783
    MTSPR = 767,
784
    MTSPR8  = 768,
785
    MTSR  = 769,
786
    MTSRIN  = 770,
787
    MTVRSAVE  = 771,
788
    MTVRSAVEv = 772,
789
    MTVSCR  = 773,
790
    MTVSRD  = 774,
791
    MTVSRWA = 775,
792
    MTVSRWZ = 776,
793
    MULHD = 777,
794
    MULHDU  = 778,
795
    MULHDUo = 779,
796
    MULHDo  = 780,
797
    MULHW = 781,
798
    MULHWU  = 782,
799
    MULHWUo = 783,
800
    MULHWo  = 784,
801
    MULLD = 785,
802
    MULLDo  = 786,
803
    MULLI = 787,
804
    MULLI8  = 788,
805
    MULLW = 789,
806
    MULLWo  = 790,
807
    MoveGOTtoLR = 791,
808
    MovePCtoLR  = 792,
809
    MovePCtoLR8 = 793,
810
    NAND  = 794,
811
    NAND8 = 795,
812
    NAND8o  = 796,
813
    NANDo = 797,
814
    NEG = 798,
815
    NEG8  = 799,
816
    NEG8o = 800,
817
    NEGo  = 801,
818
    NOP = 802,
819
    NOP_GT_PWR6 = 803,
820
    NOP_GT_PWR7 = 804,
821
    NOR = 805,
822
    NOR8  = 806,
823
    NOR8o = 807,
824
    NORo  = 808,
825
    OR  = 809,
826
    OR8 = 810,
827
    OR8o  = 811,
828
    ORC = 812,
829
    ORC8  = 813,
830
    ORC8o = 814,
831
    ORCo  = 815,
832
    ORI = 816,
833
    ORI8  = 817,
834
    ORIS  = 818,
835
    ORIS8 = 819,
836
    ORo = 820,
837
    POPCNTD = 821,
838
    POPCNTW = 822,
839
    PPC32GOT  = 823,
840
    PPC32PICGOT = 824,
841
    QVALIGNI  = 825,
842
    QVALIGNIb = 826,
843
    QVALIGNIs = 827,
844
    QVESPLATI = 828,
845
    QVESPLATIb  = 829,
846
    QVESPLATIs  = 830,
847
    QVFABS  = 831,
848
    QVFABSs = 832,
849
    QVFADD  = 833,
850
    QVFADDS = 834,
851
    QVFADDSs  = 835,
852
    QVFCFID = 836,
853
    QVFCFIDS  = 837,
854
    QVFCFIDU  = 838,
855
    QVFCFIDUS = 839,
856
    QVFCFIDb  = 840,
857
    QVFCMPEQ  = 841,
858
    QVFCMPEQb = 842,
859
    QVFCMPEQbs  = 843,
860
    QVFCMPGT  = 844,
861
    QVFCMPGTb = 845,
862
    QVFCMPGTbs  = 846,
863
    QVFCMPLT  = 847,
864
    QVFCMPLTb = 848,
865
    QVFCMPLTbs  = 849,
866
    QVFCPSGN  = 850,
867
    QVFCPSGNs = 851,
868
    QVFCTID = 852,
869
    QVFCTIDU  = 853,
870
    QVFCTIDUZ = 854,
871
    QVFCTIDZ  = 855,
872
    QVFCTIDb  = 856,
873
    QVFCTIW = 857,
874
    QVFCTIWU  = 858,
875
    QVFCTIWUZ = 859,
876
    QVFCTIWZ  = 860,
877
    QVFLOGICAL  = 861,
878
    QVFLOGICALb = 862,
879
    QVFLOGICALs = 863,
880
    QVFMADD = 864,
881
    QVFMADDS  = 865,
882
    QVFMADDSs = 866,
883
    QVFMR = 867,
884
    QVFMRb  = 868,
885
    QVFMRs  = 869,
886
    QVFMSUB = 870,
887
    QVFMSUBS  = 871,
888
    QVFMSUBSs = 872,
889
    QVFMUL  = 873,
890
    QVFMULS = 874,
891
    QVFMULSs  = 875,
892
    QVFNABS = 876,
893
    QVFNABSs  = 877,
894
    QVFNEG  = 878,
895
    QVFNEGs = 879,
896
    QVFNMADD  = 880,
897
    QVFNMADDS = 881,
898
    QVFNMADDSs  = 882,
899
    QVFNMSUB  = 883,
900
    QVFNMSUBS = 884,
901
    QVFNMSUBSs  = 885,
902
    QVFPERM = 886,
903
    QVFPERMs  = 887,
904
    QVFRE = 888,
905
    QVFRES  = 889,
906
    QVFRESs = 890,
907
    QVFRIM  = 891,
908
    QVFRIMs = 892,
909
    QVFRIN  = 893,
910
    QVFRINs = 894,
911
    QVFRIP  = 895,
912
    QVFRIPs = 896,
913
    QVFRIZ  = 897,
914
    QVFRIZs = 898,
915
    QVFRSP  = 899,
916
    QVFRSPs = 900,
917
    QVFRSQRTE = 901,
918
    QVFRSQRTES  = 902,
919
    QVFRSQRTESs = 903,
920
    QVFSEL  = 904,
921
    QVFSELb = 905,
922
    QVFSELbb  = 906,
923
    QVFSELbs  = 907,
924
    QVFSUB  = 908,
925
    QVFSUBS = 909,
926
    QVFSUBSs  = 910,
927
    QVFTSTNAN = 911,
928
    QVFTSTNANb  = 912,
929
    QVFTSTNANbs = 913,
930
    QVFXMADD  = 914,
931
    QVFXMADDS = 915,
932
    QVFXMUL = 916,
933
    QVFXMULS  = 917,
934
    QVFXXCPNMADD  = 918,
935
    QVFXXCPNMADDS = 919,
936
    QVFXXMADD = 920,
937
    QVFXXMADDS  = 921,
938
    QVFXXNPMADD = 922,
939
    QVFXXNPMADDS  = 923,
940
    QVGPCI  = 924,
941
    QVLFCDUX  = 925,
942
    QVLFCDUXA = 926,
943
    QVLFCDX = 927,
944
    QVLFCDXA  = 928,
945
    QVLFCSUX  = 929,
946
    QVLFCSUXA = 930,
947
    QVLFCSX = 931,
948
    QVLFCSXA  = 932,
949
    QVLFCSXs  = 933,
950
    QVLFDUX = 934,
951
    QVLFDUXA  = 935,
952
    QVLFDX  = 936,
953
    QVLFDXA = 937,
954
    QVLFDXb = 938,
955
    QVLFIWAX  = 939,
956
    QVLFIWAXA = 940,
957
    QVLFIWZX  = 941,
958
    QVLFIWZXA = 942,
959
    QVLFSUX = 943,
960
    QVLFSUXA  = 944,
961
    QVLFSX  = 945,
962
    QVLFSXA = 946,
963
    QVLFSXb = 947,
964
    QVLFSXs = 948,
965
    QVLPCLDX  = 949,
966
    QVLPCLSX  = 950,
967
    QVLPCLSXint = 951,
968
    QVLPCRDX  = 952,
969
    QVLPCRSX  = 953,
970
    QVSTFCDUX = 954,
971
    QVSTFCDUXA  = 955,
972
    QVSTFCDUXI  = 956,
973
    QVSTFCDUXIA = 957,
974
    QVSTFCDX  = 958,
975
    QVSTFCDXA = 959,
976
    QVSTFCDXI = 960,
977
    QVSTFCDXIA  = 961,
978
    QVSTFCSUX = 962,
979
    QVSTFCSUXA  = 963,
980
    QVSTFCSUXI  = 964,
981
    QVSTFCSUXIA = 965,
982
    QVSTFCSX  = 966,
983
    QVSTFCSXA = 967,
984
    QVSTFCSXI = 968,
985
    QVSTFCSXIA  = 969,
986
    QVSTFCSXs = 970,
987
    QVSTFDUX  = 971,
988
    QVSTFDUXA = 972,
989
    QVSTFDUXI = 973,
990
    QVSTFDUXIA  = 974,
991
    QVSTFDX = 975,
992
    QVSTFDXA  = 976,
993
    QVSTFDXI  = 977,
994
    QVSTFDXIA = 978,
995
    QVSTFDXb  = 979,
996
    QVSTFIWX  = 980,
997
    QVSTFIWXA = 981,
998
    QVSTFSUX  = 982,
999
    QVSTFSUXA = 983,
1000
    QVSTFSUXI = 984,
1001
    QVSTFSUXIA  = 985,
1002
    QVSTFSUXs = 986,
1003
    QVSTFSX = 987,
1004
    QVSTFSXA  = 988,
1005
    QVSTFSXI  = 989,
1006
    QVSTFSXIA = 990,
1007
    QVSTFSXs  = 991,
1008
    RESTORE_CR  = 992,
1009
    RESTORE_CRBIT = 993,
1010
    RESTORE_VRSAVE  = 994,
1011
    RFCI  = 995,
1012
    RFDI  = 996,
1013
    RFEBB = 997,
1014
    RFI = 998,
1015
    RFID  = 999,
1016
    RFMCI = 1000,
1017
    RLDCL = 1001,
1018
    RLDCLo  = 1002,
1019
    RLDCR = 1003,
1020
    RLDCRo  = 1004,
1021
    RLDIC = 1005,
1022
    RLDICL  = 1006,
1023
    RLDICL_32_64  = 1007,
1024
    RLDICLo = 1008,
1025
    RLDICR  = 1009,
1026
    RLDICRo = 1010,
1027
    RLDICo  = 1011,
1028
    RLDIMI  = 1012,
1029
    RLDIMIo = 1013,
1030
    RLWIMI  = 1014,
1031
    RLWIMI8 = 1015,
1032
    RLWIMI8o  = 1016,
1033
    RLWIMIbm  = 1017,
1034
    RLWIMIo = 1018,
1035
    RLWIMIobm = 1019,
1036
    RLWINM  = 1020,
1037
    RLWINM8 = 1021,
1038
    RLWINM8o  = 1022,
1039
    RLWINMbm  = 1023,
1040
    RLWINMo = 1024,
1041
    RLWINMobm = 1025,
1042
    RLWNM = 1026,
1043
    RLWNM8  = 1027,
1044
    RLWNM8o = 1028,
1045
    RLWNMbm = 1029,
1046
    RLWNMo  = 1030,
1047
    RLWNMobm  = 1031,
1048
    ROTRDI  = 1032,
1049
    ROTRDIo = 1033,
1050
    ROTRWI  = 1034,
1051
    ROTRWIo = 1035,
1052
    ReadTB  = 1036,
1053
    SC  = 1037,
1054
    SELECT_CC_F4  = 1038,
1055
    SELECT_CC_F8  = 1039,
1056
    SELECT_CC_I4  = 1040,
1057
    SELECT_CC_I8  = 1041,
1058
    SELECT_CC_QBRC  = 1042,
1059
    SELECT_CC_QFRC  = 1043,
1060
    SELECT_CC_QSRC  = 1044,
1061
    SELECT_CC_VRRC  = 1045,
1062
    SELECT_CC_VSFRC = 1046,
1063
    SELECT_CC_VSRC  = 1047,
1064
    SELECT_CC_VSSRC = 1048,
1065
    SELECT_F4 = 1049,
1066
    SELECT_F8 = 1050,
1067
    SELECT_I4 = 1051,
1068
    SELECT_I8 = 1052,
1069
    SELECT_QBRC = 1053,
1070
    SELECT_QFRC = 1054,
1071
    SELECT_QSRC = 1055,
1072
    SELECT_VRRC = 1056,
1073
    SELECT_VSFRC  = 1057,
1074
    SELECT_VSRC = 1058,
1075
    SELECT_VSSRC  = 1059,
1076
    SLBIA = 1060,
1077
    SLBIE = 1061,
1078
    SLBMFEE = 1062,
1079
    SLBMTE  = 1063,
1080
    SLD = 1064,
1081
    SLDI  = 1065,
1082
    SLDIo = 1066,
1083
    SLDo  = 1067,
1084
    SLW = 1068,
1085
    SLW8  = 1069,
1086
    SLW8o = 1070,
1087
    SLWI  = 1071,
1088
    SLWIo = 1072,
1089
    SLWo  = 1073,
1090
    SPILL_CR  = 1074,
1091
    SPILL_CRBIT = 1075,
1092
    SPILL_VRSAVE  = 1076,
1093
    SRAD  = 1077,
1094
    SRADI = 1078,
1095
    SRADIo  = 1079,
1096
    SRADo = 1080,
1097
    SRAW  = 1081,
1098
    SRAWI = 1082,
1099
    SRAWIo  = 1083,
1100
    SRAWo = 1084,
1101
    SRD = 1085,
1102
    SRDI  = 1086,
1103
    SRDIo = 1087,
1104
    SRDo  = 1088,
1105
    SRW = 1089,
1106
    SRW8  = 1090,
1107
    SRW8o = 1091,
1108
    SRWI  = 1092,
1109
    SRWIo = 1093,
1110
    SRWo  = 1094,
1111
    STB = 1095,
1112
    STB8  = 1096,
1113
    STBCIX  = 1097,
1114
    STBCX = 1098,
1115
    STBU  = 1099,
1116
    STBU8 = 1100,
1117
    STBUX = 1101,
1118
    STBUX8  = 1102,
1119
    STBX  = 1103,
1120
    STBX8 = 1104,
1121
    STD = 1105,
1122
    STDBRX  = 1106,
1123
    STDCIX  = 1107,
1124
    STDCX = 1108,
1125
    STDU  = 1109,
1126
    STDUX = 1110,
1127
    STDX  = 1111,
1128
    STFD  = 1112,
1129
    STFDU = 1113,
1130
    STFDUX  = 1114,
1131
    STFDX = 1115,
1132
    STFIWX  = 1116,
1133
    STFS  = 1117,
1134
    STFSU = 1118,
1135
    STFSUX  = 1119,
1136
    STFSX = 1120,
1137
    STH = 1121,
1138
    STH8  = 1122,
1139
    STHBRX  = 1123,
1140
    STHCIX  = 1124,
1141
    STHCX = 1125,
1142
    STHU  = 1126,
1143
    STHU8 = 1127,
1144
    STHUX = 1128,
1145
    STHUX8  = 1129,
1146
    STHX  = 1130,
1147
    STHX8 = 1131,
1148
    STMW  = 1132,
1149
    STSWI = 1133,
1150
    STVEBX  = 1134,
1151
    STVEHX  = 1135,
1152
    STVEWX  = 1136,
1153
    STVX  = 1137,
1154
    STVXL = 1138,
1155
    STW = 1139,
1156
    STW8  = 1140,
1157
    STWBRX  = 1141,
1158
    STWCIX  = 1142,
1159
    STWCX = 1143,
1160
    STWU  = 1144,
1161
    STWU8 = 1145,
1162
    STWUX = 1146,
1163
    STWUX8  = 1147,
1164
    STWX  = 1148,
1165
    STWX8 = 1149,
1166
    STXSDX  = 1150,
1167
    STXSIWX = 1151,
1168
    STXSSPX = 1152,
1169
    STXVD2X = 1153,
1170
    STXVW4X = 1154,
1171
    SUBF  = 1155,
1172
    SUBF8 = 1156,
1173
    SUBF8o  = 1157,
1174
    SUBFC = 1158,
1175
    SUBFC8  = 1159,
1176
    SUBFC8o = 1160,
1177
    SUBFCo  = 1161,
1178
    SUBFE = 1162,
1179
    SUBFE8  = 1163,
1180
    SUBFE8o = 1164,
1181
    SUBFEo  = 1165,
1182
    SUBFIC  = 1166,
1183
    SUBFIC8 = 1167,
1184
    SUBFME  = 1168,
1185
    SUBFME8 = 1169,
1186
    SUBFME8o  = 1170,
1187
    SUBFMEo = 1171,
1188
    SUBFZE  = 1172,
1189
    SUBFZE8 = 1173,
1190
    SUBFZE8o  = 1174,
1191
    SUBFZEo = 1175,
1192
    SUBFo = 1176,
1193
    SUBI  = 1177,
1194
    SUBIC = 1178,
1195
    SUBICo  = 1179,
1196
    SUBIS = 1180,
1197
    SYNC  = 1181,
1198
    TABORT  = 1182,
1199
    TABORTDC  = 1183,
1200
    TABORTDCI = 1184,
1201
    TABORTWC  = 1185,
1202
    TABORTWCI = 1186,
1203
    TAILB = 1187,
1204
    TAILB8  = 1188,
1205
    TAILBA  = 1189,
1206
    TAILBA8 = 1190,
1207
    TAILBCTR  = 1191,
1208
    TAILBCTR8 = 1192,
1209
    TBEGIN  = 1193,
1210
    TCHECK  = 1194,
1211
    TCHECK_RET  = 1195,
1212
    TCRETURNai  = 1196,
1213
    TCRETURNai8 = 1197,
1214
    TCRETURNdi  = 1198,
1215
    TCRETURNdi8 = 1199,
1216
    TCRETURNri  = 1200,
1217
    TCRETURNri8 = 1201,
1218
    TD  = 1202,
1219
    TDI = 1203,
1220
    TEND  = 1204,
1221
    TLBIA = 1205,
1222
    TLBIE = 1206,
1223
    TLBIEL  = 1207,
1224
    TLBIVAX = 1208,
1225
    TLBLD = 1209,
1226
    TLBLI = 1210,
1227
    TLBRE = 1211,
1228
    TLBRE2  = 1212,
1229
    TLBSX = 1213,
1230
    TLBSX2  = 1214,
1231
    TLBSX2D = 1215,
1232
    TLBSYNC = 1216,
1233
    TLBWE = 1217,
1234
    TLBWE2  = 1218,
1235
    TRAP  = 1219,
1236
    TRECHKPT  = 1220,
1237
    TRECLAIM  = 1221,
1238
    TSR = 1222,
1239
    TW  = 1223,
1240
    TWI = 1224,
1241
    UPDATE_VRSAVE = 1225,
1242
    UpdateGBR = 1226,
1243
    VADDCUQ = 1227,
1244
    VADDCUW = 1228,
1245
    VADDECUQ  = 1229,
1246
    VADDEUQM  = 1230,
1247
    VADDFP  = 1231,
1248
    VADDSBS = 1232,
1249
    VADDSHS = 1233,
1250
    VADDSWS = 1234,
1251
    VADDUBM = 1235,
1252
    VADDUBS = 1236,
1253
    VADDUDM = 1237,
1254
    VADDUHM = 1238,
1255
    VADDUHS = 1239,
1256
    VADDUQM = 1240,
1257
    VADDUWM = 1241,
1258
    VADDUWS = 1242,
1259
    VAND  = 1243,
1260
    VANDC = 1244,
1261
    VAVGSB  = 1245,
1262
    VAVGSH  = 1246,
1263
    VAVGSW  = 1247,
1264
    VAVGUB  = 1248,
1265
    VAVGUH  = 1249,
1266
    VAVGUW  = 1250,
1267
    VBPERMQ = 1251,
1268
    VCFSX = 1252,
1269
    VCFSX_0 = 1253,
1270
    VCFUX = 1254,
1271
    VCFUX_0 = 1255,
1272
    VCIPHER = 1256,
1273
    VCIPHERLAST = 1257,
1274
    VCLZB = 1258,
1275
    VCLZD = 1259,
1276
    VCLZH = 1260,
1277
    VCLZW = 1261,
1278
    VCMPBFP = 1262,
1279
    VCMPBFPo  = 1263,
1280
    VCMPEQFP  = 1264,
1281
    VCMPEQFPo = 1265,
1282
    VCMPEQUB  = 1266,
1283
    VCMPEQUBo = 1267,
1284
    VCMPEQUD  = 1268,
1285
    VCMPEQUDo = 1269,
1286
    VCMPEQUH  = 1270,
1287
    VCMPEQUHo = 1271,
1288
    VCMPEQUW  = 1272,
1289
    VCMPEQUWo = 1273,
1290
    VCMPGEFP  = 1274,
1291
    VCMPGEFPo = 1275,
1292
    VCMPGTFP  = 1276,
1293
    VCMPGTFPo = 1277,
1294
    VCMPGTSB  = 1278,
1295
    VCMPGTSBo = 1279,
1296
    VCMPGTSD  = 1280,
1297
    VCMPGTSDo = 1281,
1298
    VCMPGTSH  = 1282,
1299
    VCMPGTSHo = 1283,
1300
    VCMPGTSW  = 1284,
1301
    VCMPGTSWo = 1285,
1302
    VCMPGTUB  = 1286,
1303
    VCMPGTUBo = 1287,
1304
    VCMPGTUD  = 1288,
1305
    VCMPGTUDo = 1289,
1306
    VCMPGTUH  = 1290,
1307
    VCMPGTUHo = 1291,
1308
    VCMPGTUW  = 1292,
1309
    VCMPGTUWo = 1293,
1310
    VCTSXS  = 1294,
1311
    VCTSXS_0  = 1295,
1312
    VCTUXS  = 1296,
1313
    VCTUXS_0  = 1297,
1314
    VEQV  = 1298,
1315
    VEXPTEFP  = 1299,
1316
    VGBBD = 1300,
1317
    VLOGEFP = 1301,
1318
    VMADDFP = 1302,
1319
    VMAXFP  = 1303,
1320
    VMAXSB  = 1304,
1321
    VMAXSD  = 1305,
1322
    VMAXSH  = 1306,
1323
    VMAXSW  = 1307,
1324
    VMAXUB  = 1308,
1325
    VMAXUD  = 1309,
1326
    VMAXUH  = 1310,
1327
    VMAXUW  = 1311,
1328
    VMHADDSHS = 1312,
1329
    VMHRADDSHS  = 1313,
1330
    VMINFP  = 1314,
1331
    VMINSB  = 1315,
1332
    VMINSD  = 1316,
1333
    VMINSH  = 1317,
1334
    VMINSW  = 1318,
1335
    VMINUB  = 1319,
1336
    VMINUD  = 1320,
1337
    VMINUH  = 1321,
1338
    VMINUW  = 1322,
1339
    VMLADDUHM = 1323,
1340
    VMRGEW  = 1324,
1341
    VMRGHB  = 1325,
1342
    VMRGHH  = 1326,
1343
    VMRGHW  = 1327,
1344
    VMRGLB  = 1328,
1345
    VMRGLH  = 1329,
1346
    VMRGLW  = 1330,
1347
    VMRGOW  = 1331,
1348
    VMSUMMBM  = 1332,
1349
    VMSUMSHM  = 1333,
1350
    VMSUMSHS  = 1334,
1351
    VMSUMUBM  = 1335,
1352
    VMSUMUHM  = 1336,
1353
    VMSUMUHS  = 1337,
1354
    VMULESB = 1338,
1355
    VMULESH = 1339,
1356
    VMULESW = 1340,
1357
    VMULEUB = 1341,
1358
    VMULEUH = 1342,
1359
    VMULEUW = 1343,
1360
    VMULOSB = 1344,
1361
    VMULOSH = 1345,
1362
    VMULOSW = 1346,
1363
    VMULOUB = 1347,
1364
    VMULOUH = 1348,
1365
    VMULOUW = 1349,
1366
    VMULUWM = 1350,
1367
    VNAND = 1351,
1368
    VNCIPHER  = 1352,
1369
    VNCIPHERLAST  = 1353,
1370
    VNMSUBFP  = 1354,
1371
    VNOR  = 1355,
1372
    VOR = 1356,
1373
    VORC  = 1357,
1374
    VPERM = 1358,
1375
    VPERMXOR  = 1359,
1376
    VPKPX = 1360,
1377
    VPKSDSS = 1361,
1378
    VPKSDUS = 1362,
1379
    VPKSHSS = 1363,
1380
    VPKSHUS = 1364,
1381
    VPKSWSS = 1365,
1382
    VPKSWUS = 1366,
1383
    VPKUDUM = 1367,
1384
    VPKUDUS = 1368,
1385
    VPKUHUM = 1369,
1386
    VPKUHUS = 1370,
1387
    VPKUWUM = 1371,
1388
    VPKUWUS = 1372,
1389
    VPMSUMB = 1373,
1390
    VPMSUMD = 1374,
1391
    VPMSUMH = 1375,
1392
    VPMSUMW = 1376,
1393
    VPOPCNTB  = 1377,
1394
    VPOPCNTD  = 1378,
1395
    VPOPCNTH  = 1379,
1396
    VPOPCNTW  = 1380,
1397
    VREFP = 1381,
1398
    VRFIM = 1382,
1399
    VRFIN = 1383,
1400
    VRFIP = 1384,
1401
    VRFIZ = 1385,
1402
    VRLB  = 1386,
1403
    VRLD  = 1387,
1404
    VRLH  = 1388,
1405
    VRLW  = 1389,
1406
    VRSQRTEFP = 1390,
1407
    VSBOX = 1391,
1408
    VSEL  = 1392,
1409
    VSHASIGMAD  = 1393,
1410
    VSHASIGMAW  = 1394,
1411
    VSL = 1395,
1412
    VSLB  = 1396,
1413
    VSLD  = 1397,
1414
    VSLDOI  = 1398,
1415
    VSLH  = 1399,
1416
    VSLO  = 1400,
1417
    VSLW  = 1401,
1418
    VSPLTB  = 1402,
1419
    VSPLTH  = 1403,
1420
    VSPLTISB  = 1404,
1421
    VSPLTISH  = 1405,
1422
    VSPLTISW  = 1406,
1423
    VSPLTW  = 1407,
1424
    VSR = 1408,
1425
    VSRAB = 1409,
1426
    VSRAD = 1410,
1427
    VSRAH = 1411,
1428
    VSRAW = 1412,
1429
    VSRB  = 1413,
1430
    VSRD  = 1414,
1431
    VSRH  = 1415,
1432
    VSRO  = 1416,
1433
    VSRW  = 1417,
1434
    VSUBCUQ = 1418,
1435
    VSUBCUW = 1419,
1436
    VSUBECUQ  = 1420,
1437
    VSUBEUQM  = 1421,
1438
    VSUBFP  = 1422,
1439
    VSUBSBS = 1423,
1440
    VSUBSHS = 1424,
1441
    VSUBSWS = 1425,
1442
    VSUBUBM = 1426,
1443
    VSUBUBS = 1427,
1444
    VSUBUDM = 1428,
1445
    VSUBUHM = 1429,
1446
    VSUBUHS = 1430,
1447
    VSUBUQM = 1431,
1448
    VSUBUWM = 1432,
1449
    VSUBUWS = 1433,
1450
    VSUM2SWS  = 1434,
1451
    VSUM4SBS  = 1435,
1452
    VSUM4SHS  = 1436,
1453
    VSUM4UBS  = 1437,
1454
    VSUMSWS = 1438,
1455
    VUPKHPX = 1439,
1456
    VUPKHSB = 1440,
1457
    VUPKHSH = 1441,
1458
    VUPKHSW = 1442,
1459
    VUPKLPX = 1443,
1460
    VUPKLSB = 1444,
1461
    VUPKLSH = 1445,
1462
    VUPKLSW = 1446,
1463
    VXOR  = 1447,
1464
    V_SET0  = 1448,
1465
    V_SET0B = 1449,
1466
    V_SET0H = 1450,
1467
    V_SETALLONES  = 1451,
1468
    V_SETALLONESB = 1452,
1469
    V_SETALLONESH = 1453,
1470
    WAIT  = 1454,
1471
    WRTEE = 1455,
1472
    WRTEEI  = 1456,
1473
    XOR = 1457,
1474
    XOR8  = 1458,
1475
    XOR8o = 1459,
1476
    XORI  = 1460,
1477
    XORI8 = 1461,
1478
    XORIS = 1462,
1479
    XORIS8  = 1463,
1480
    XORo  = 1464,
1481
    XSABSDP = 1465,
1482
    XSADDDP = 1466,
1483
    XSADDSP = 1467,
1484
    XSCMPODP  = 1468,
1485
    XSCMPUDP  = 1469,
1486
    XSCPSGNDP = 1470,
1487
    XSCVDPSP  = 1471,
1488
    XSCVDPSPN = 1472,
1489
    XSCVDPSXDS  = 1473,
1490
    XSCVDPSXWS  = 1474,
1491
    XSCVDPUXDS  = 1475,
1492
    XSCVDPUXWS  = 1476,
1493
    XSCVSPDP  = 1477,
1494
    XSCVSPDPN = 1478,
1495
    XSCVSXDDP = 1479,
1496
    XSCVSXDSP = 1480,
1497
    XSCVUXDDP = 1481,
1498
    XSCVUXDSP = 1482,
1499
    XSDIVDP = 1483,
1500
    XSDIVSP = 1484,
1501
    XSMADDADP = 1485,
1502
    XSMADDASP = 1486,
1503
    XSMADDMDP = 1487,
1504
    XSMADDMSP = 1488,
1505
    XSMAXDP = 1489,
1506
    XSMINDP = 1490,
1507
    XSMSUBADP = 1491,
1508
    XSMSUBASP = 1492,
1509
    XSMSUBMDP = 1493,
1510
    XSMSUBMSP = 1494,
1511
    XSMULDP = 1495,
1512
    XSMULSP = 1496,
1513
    XSNABSDP  = 1497,
1514
    XSNEGDP = 1498,
1515
    XSNMADDADP  = 1499,
1516
    XSNMADDASP  = 1500,
1517
    XSNMADDMDP  = 1501,
1518
    XSNMADDMSP  = 1502,
1519
    XSNMSUBADP  = 1503,
1520
    XSNMSUBASP  = 1504,
1521
    XSNMSUBMDP  = 1505,
1522
    XSNMSUBMSP  = 1506,
1523
    XSRDPI  = 1507,
1524
    XSRDPIC = 1508,
1525
    XSRDPIM = 1509,
1526
    XSRDPIP = 1510,
1527
    XSRDPIZ = 1511,
1528
    XSREDP  = 1512,
1529
    XSRESP  = 1513,
1530
    XSRSQRTEDP  = 1514,
1531
    XSRSQRTESP  = 1515,
1532
    XSSQRTDP  = 1516,
1533
    XSSQRTSP  = 1517,
1534
    XSSUBDP = 1518,
1535
    XSSUBSP = 1519,
1536
    XSTDIVDP  = 1520,
1537
    XSTSQRTDP = 1521,
1538
    XVABSDP = 1522,
1539
    XVABSSP = 1523,
1540
    XVADDDP = 1524,
1541
    XVADDSP = 1525,
1542
    XVCMPEQDP = 1526,
1543
    XVCMPEQDPo  = 1527,
1544
    XVCMPEQSP = 1528,
1545
    XVCMPEQSPo  = 1529,
1546
    XVCMPGEDP = 1530,
1547
    XVCMPGEDPo  = 1531,
1548
    XVCMPGESP = 1532,
1549
    XVCMPGESPo  = 1533,
1550
    XVCMPGTDP = 1534,
1551
    XVCMPGTDPo  = 1535,
1552
    XVCMPGTSP = 1536,
1553
    XVCMPGTSPo  = 1537,
1554
    XVCPSGNDP = 1538,
1555
    XVCPSGNSP = 1539,
1556
    XVCVDPSP  = 1540,
1557
    XVCVDPSXDS  = 1541,
1558
    XVCVDPSXWS  = 1542,
1559
    XVCVDPUXDS  = 1543,
1560
    XVCVDPUXWS  = 1544,
1561
    XVCVSPDP  = 1545,
1562
    XVCVSPSXDS  = 1546,
1563
    XVCVSPSXWS  = 1547,
1564
    XVCVSPUXDS  = 1548,
1565
    XVCVSPUXWS  = 1549,
1566
    XVCVSXDDP = 1550,
1567
    XVCVSXDSP = 1551,
1568
    XVCVSXWDP = 1552,
1569
    XVCVSXWSP = 1553,
1570
    XVCVUXDDP = 1554,
1571
    XVCVUXDSP = 1555,
1572
    XVCVUXWDP = 1556,
1573
    XVCVUXWSP = 1557,
1574
    XVDIVDP = 1558,
1575
    XVDIVSP = 1559,
1576
    XVMADDADP = 1560,
1577
    XVMADDASP = 1561,
1578
    XVMADDMDP = 1562,
1579
    XVMADDMSP = 1563,
1580
    XVMAXDP = 1564,
1581
    XVMAXSP = 1565,
1582
    XVMINDP = 1566,
1583
    XVMINSP = 1567,
1584
    XVMSUBADP = 1568,
1585
    XVMSUBASP = 1569,
1586
    XVMSUBMDP = 1570,
1587
    XVMSUBMSP = 1571,
1588
    XVMULDP = 1572,
1589
    XVMULSP = 1573,
1590
    XVNABSDP  = 1574,
1591
    XVNABSSP  = 1575,
1592
    XVNEGDP = 1576,
1593
    XVNEGSP = 1577,
1594
    XVNMADDADP  = 1578,
1595
    XVNMADDASP  = 1579,
1596
    XVNMADDMDP  = 1580,
1597
    XVNMADDMSP  = 1581,
1598
    XVNMSUBADP  = 1582,
1599
    XVNMSUBASP  = 1583,
1600
    XVNMSUBMDP  = 1584,
1601
    XVNMSUBMSP  = 1585,
1602
    XVRDPI  = 1586,
1603
    XVRDPIC = 1587,
1604
    XVRDPIM = 1588,
1605
    XVRDPIP = 1589,
1606
    XVRDPIZ = 1590,
1607
    XVREDP  = 1591,
1608
    XVRESP  = 1592,
1609
    XVRSPI  = 1593,
1610
    XVRSPIC = 1594,
1611
    XVRSPIM = 1595,
1612
    XVRSPIP = 1596,
1613
    XVRSPIZ = 1597,
1614
    XVRSQRTEDP  = 1598,
1615
    XVRSQRTESP  = 1599,
1616
    XVSQRTDP  = 1600,
1617
    XVSQRTSP  = 1601,
1618
    XVSUBDP = 1602,
1619
    XVSUBSP = 1603,
1620
    XVTDIVDP  = 1604,
1621
    XVTDIVSP  = 1605,
1622
    XVTSQRTDP = 1606,
1623
    XVTSQRTSP = 1607,
1624
    XXLAND  = 1608,
1625
    XXLANDC = 1609,
1626
    XXLEQV  = 1610,
1627
    XXLNAND = 1611,
1628
    XXLNOR  = 1612,
1629
    XXLOR = 1613,
1630
    XXLORC  = 1614,
1631
    XXLORf  = 1615,
1632
    XXLXOR  = 1616,
1633
    XXMRGHW = 1617,
1634
    XXMRGLW = 1618,
1635
    XXPERMDI  = 1619,
1636
    XXSEL = 1620,
1637
    XXSLDWI = 1621,
1638
    XXSPLTW = 1622,
1639
    gBC = 1623,
1640
    gBCA  = 1624,
1641
    gBCCTR  = 1625,
1642
    gBCCTRL = 1626,
1643
    gBCL  = 1627,
1644
    gBCLA = 1628,
1645
    gBCLR = 1629,
1646
    gBCLRL  = 1630,
1647
    INSTRUCTION_LIST_END = 1631
1648
  };
1649
1650
namespace Sched {
1651
  enum {
1652
    NoInstrModel  = 0,
1653
    IIC_IntSimple = 1,
1654
    IIC_IntGeneral  = 2,
1655
    IIC_BrB = 3,
1656
    IIC_VecFP = 4,
1657
    IIC_IntCompare  = 5,
1658
    IIC_BrCR  = 6,
1659
    IIC_LdStDCBF  = 7,
1660
    IIC_LdStLoad  = 8,
1661
    IIC_IntDivD = 9,
1662
    IIC_IntDivW = 10,
1663
    IIC_FPGeneral = 11,
1664
    IIC_FPAddSub  = 12,
1665
    IIC_FPCompare = 13,
1666
    IIC_FPDivD  = 14,
1667
    IIC_FPDivS  = 15,
1668
    IIC_FPFused = 16,
1669
    IIC_FPSqrtD = 17,
1670
    IIC_FPSqrtS = 18,
1671
    IIC_LdStICBI  = 19,
1672
    IIC_IntISEL = 20,
1673
    IIC_SprISYNC  = 21,
1674
    IIC_LdStLWARX = 22,
1675
    IIC_LdStLoadUpd = 23,
1676
    IIC_LdStLoadUpdX  = 24,
1677
    IIC_LdStLD  = 25,
1678
    IIC_LdStLDARX = 26,
1679
    IIC_LdStLDU = 27,
1680
    IIC_LdStLDUX  = 28,
1681
    IIC_LdStLFD = 29,
1682
    IIC_LdStLFDU  = 30,
1683
    IIC_LdStLFDUX = 31,
1684
    IIC_LdStLHA = 32,
1685
    IIC_LdStLHAU  = 33,
1686
    IIC_LdStLHAUX = 34,
1687
    IIC_LdStLMW = 35,
1688
    IIC_LdStLWA = 36,
1689
    IIC_BrMCR = 37,
1690
    IIC_SprMFCR = 38,
1691
    IIC_SprMFSPR  = 39,
1692
    IIC_IntMFFS = 40,
1693
    IIC_SprMFMSR  = 41,
1694
    IIC_SprMFCRF  = 42,
1695
    IIC_SprMFSR = 43,
1696
    IIC_SprMFTB = 44,
1697
    IIC_LdStStore = 45,
1698
    IIC_VecGeneral  = 46,
1699
    IIC_LdStSync  = 47,
1700
    IIC_BrMCRX  = 48,
1701
    IIC_SprMTSPR  = 49,
1702
    IIC_IntMTFSB0 = 50,
1703
    IIC_SprMTMSR  = 51,
1704
    IIC_SprMTMSRD = 52,
1705
    IIC_SprMTSR = 53,
1706
    IIC_IntMulHW  = 54,
1707
    IIC_IntMulHWU = 55,
1708
    IIC_IntMulHD  = 56,
1709
    IIC_IntMulLI  = 57,
1710
    IIC_VecPerm = 58,
1711
    IIC_LdStSTFD  = 59,
1712
    IIC_LdStSTFDU = 60,
1713
    IIC_SprRFI  = 61,
1714
    IIC_IntRFID = 62,
1715
    IIC_IntRotateD  = 63,
1716
    IIC_IntRotateDI = 64,
1717
    IIC_IntRotate = 65,
1718
    IIC_SprSLBIA  = 66,
1719
    IIC_SprSLBIE  = 67,
1720
    IIC_SprSLBMFEE  = 68,
1721
    IIC_SprSLBMTE = 69,
1722
    IIC_IntShift  = 70,
1723
    IIC_LdStSTWCX = 71,
1724
    IIC_LdStStoreUpd  = 72,
1725
    IIC_LdStSTD = 73,
1726
    IIC_LdStSTDCX = 74,
1727
    IIC_LdStSTDU  = 75,
1728
    IIC_LdStSTDUX = 76,
1729
    IIC_IntTrapD  = 77,
1730
    IIC_SprTLBIA  = 78,
1731
    IIC_SprTLBIE  = 79,
1732
    IIC_SprTLBIEL = 80,
1733
    IIC_SprTLBSYNC  = 81,
1734
    IIC_IntTrapW  = 82,
1735
    IIC_VecFPCompare  = 83,
1736
    SCHED_LIST_END = 84
1737
  };
1738
} // end Sched namespace
1739
} // end PPC namespace
1740
} // end llvm namespace 
1741
#endif // GET_INSTRINFO_ENUM
1742
1743
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
1744
|*                                                                            *|
1745
|* Target Instruction Descriptors                                             *|
1746
|*                                                                            *|
1747
|* Automatically generated file, do not edit!                                 *|
1748
|*                                                                            *|
1749
\*===----------------------------------------------------------------------===*/
1750
1751
1752
#ifdef GET_INSTRINFO_MC_DESC
1753
#undef GET_INSTRINFO_MC_DESC
1754
namespace llvm_ks {
1755
1756
static const MCPhysReg ImplicitList1[] = { PPC::CR0, 0 };
1757
static const MCPhysReg ImplicitList2[] = { PPC::CARRY, 0 };
1758
static const MCPhysReg ImplicitList3[] = { PPC::CARRY, PPC::CR0, 0 };
1759
static const MCPhysReg ImplicitList4[] = { PPC::X0, PPC::X3, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
1760
static const MCPhysReg ImplicitList5[] = { PPC::R0, PPC::R3, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
1761
static const MCPhysReg ImplicitList6[] = { PPC::R1, 0 };
1762
static const MCPhysReg ImplicitList7[] = { PPC::CTR, 0 };
1763
static const MCPhysReg ImplicitList8[] = { PPC::CTR8, 0 };
1764
static const MCPhysReg ImplicitList9[] = { PPC::CTR, PPC::RM, 0 };
1765
static const MCPhysReg ImplicitList10[] = { PPC::LR, 0 };
1766
static const MCPhysReg ImplicitList11[] = { PPC::CTR8, PPC::RM, 0 };
1767
static const MCPhysReg ImplicitList12[] = { PPC::LR8, 0 };
1768
static const MCPhysReg ImplicitList13[] = { PPC::RM, 0 };
1769
static const MCPhysReg ImplicitList14[] = { PPC::LR, PPC::RM, 0 };
1770
static const MCPhysReg ImplicitList15[] = { PPC::LR8, PPC::X2, 0 };
1771
static const MCPhysReg ImplicitList16[] = { PPC::CTR, PPC::LR, PPC::RM, 0 };
1772
static const MCPhysReg ImplicitList17[] = { PPC::CTR8, PPC::LR8, PPC::RM, 0 };
1773
static const MCPhysReg ImplicitList18[] = { PPC::LR8, PPC::RM, 0 };
1774
static const MCPhysReg ImplicitList19[] = { PPC::CR1EQ, 0 };
1775
static const MCPhysReg ImplicitList20[] = { PPC::X1, 0 };
1776
static const MCPhysReg ImplicitList21[] = { PPC::CR1, 0 };
1777
static const MCPhysReg ImplicitList22[] = { PPC::X0, PPC::X4, PPC::X5, PPC::X6, PPC::X7, PPC::X8, PPC::X9, PPC::X10, PPC::X11, PPC::X12, PPC::LR8, PPC::CTR8, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
1778
static const MCPhysReg ImplicitList23[] = { PPC::R0, PPC::R4, PPC::R5, PPC::R6, PPC::R7, PPC::R8, PPC::R9, PPC::R10, PPC::R11, PPC::R12, PPC::LR, PPC::CTR, PPC::CR0, PPC::CR1, PPC::CR5, PPC::CR6, PPC::CR7, 0 };
1779
static const MCPhysReg ImplicitList24[] = { PPC::CR6, 0 };
1780
static const MCPhysReg ImplicitList25[] = { PPC::LR, PPC::CTR, 0 };
1781
1782
static const MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1783
static const MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1784
static const MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1785
static const MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1786
static const MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1787
static const MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1788
static const MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1789
static const MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1790
static const MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1791
static const MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1792
static const MCOperandInfo OperandInfo12[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1793
static const MCOperandInfo OperandInfo13[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1794
static const MCOperandInfo OperandInfo14[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1795
static const MCOperandInfo OperandInfo15[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1796
static const MCOperandInfo OperandInfo16[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1797
static const MCOperandInfo OperandInfo17[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1798
static const MCOperandInfo OperandInfo18[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1799
static const MCOperandInfo OperandInfo19[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1800
static const MCOperandInfo OperandInfo20[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1801
static const MCOperandInfo OperandInfo21[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1802
static const MCOperandInfo OperandInfo22[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1803
static const MCOperandInfo OperandInfo23[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1804
static const MCOperandInfo OperandInfo24[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1805
static const MCOperandInfo OperandInfo25[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1806
static const MCOperandInfo OperandInfo26[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1807
static const MCOperandInfo OperandInfo27[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1808
static const MCOperandInfo OperandInfo28[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1809
static const MCOperandInfo OperandInfo29[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1810
static const MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1811
static const MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1812
static const MCOperandInfo OperandInfo32[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1813
static const MCOperandInfo OperandInfo33[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1814
static const MCOperandInfo OperandInfo34[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1815
static const MCOperandInfo OperandInfo35[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1816
static const MCOperandInfo OperandInfo36[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1817
static const MCOperandInfo OperandInfo37[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1818
static const MCOperandInfo OperandInfo38[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1819
static const MCOperandInfo OperandInfo39[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1820
static const MCOperandInfo OperandInfo40[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1821
static const MCOperandInfo OperandInfo41[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1822
static const MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1823
static const MCOperandInfo OperandInfo43[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1824
static const MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1825
static const MCOperandInfo OperandInfo45[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1826
static const MCOperandInfo OperandInfo46[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1827
static const MCOperandInfo OperandInfo47[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1828
static const MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1829
static const MCOperandInfo OperandInfo49[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1830
static const MCOperandInfo OperandInfo50[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1831
static const MCOperandInfo OperandInfo51[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1832
static const MCOperandInfo OperandInfo52[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1833
static const MCOperandInfo OperandInfo53[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1834
static const MCOperandInfo OperandInfo54[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1835
static const MCOperandInfo OperandInfo55[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1836
static const MCOperandInfo OperandInfo56[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1837
static const MCOperandInfo OperandInfo57[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1838
static const MCOperandInfo OperandInfo58[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1839
static const MCOperandInfo OperandInfo59[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1840
static const MCOperandInfo OperandInfo60[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1841
static const MCOperandInfo OperandInfo61[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1842
static const MCOperandInfo OperandInfo62[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1843
static const MCOperandInfo OperandInfo63[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1844
static const MCOperandInfo OperandInfo64[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1845
static const MCOperandInfo OperandInfo65[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1846
static const MCOperandInfo OperandInfo66[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1847
static const MCOperandInfo OperandInfo67[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1848
static const MCOperandInfo OperandInfo68[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
1849
static const MCOperandInfo OperandInfo69[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
1850
static const MCOperandInfo OperandInfo70[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1851
static const MCOperandInfo OperandInfo71[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1852
static const MCOperandInfo OperandInfo72[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1853
static const MCOperandInfo OperandInfo73[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1854
static const MCOperandInfo OperandInfo74[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1855
static const MCOperandInfo OperandInfo75[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1856
static const MCOperandInfo OperandInfo76[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1857
static const MCOperandInfo OperandInfo77[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
1858
static const MCOperandInfo OperandInfo78[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1859
static const MCOperandInfo OperandInfo79[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1860
static const MCOperandInfo OperandInfo80[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1861
static const MCOperandInfo OperandInfo81[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, };
1862
static const MCOperandInfo OperandInfo82[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1863
static const MCOperandInfo OperandInfo83[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1864
static const MCOperandInfo OperandInfo84[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1865
static const MCOperandInfo OperandInfo85[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1866
static const MCOperandInfo OperandInfo86[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1867
static const MCOperandInfo OperandInfo87[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1868
static const MCOperandInfo OperandInfo88[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1869
static const MCOperandInfo OperandInfo89[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1870
static const MCOperandInfo OperandInfo90[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1871
static const MCOperandInfo OperandInfo91[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1872
static const MCOperandInfo OperandInfo92[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1873
static const MCOperandInfo OperandInfo93[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1874
static const MCOperandInfo OperandInfo94[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1875
static const MCOperandInfo OperandInfo95[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1876
static const MCOperandInfo OperandInfo96[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRSAVERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1877
static const MCOperandInfo OperandInfo97[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1878
static const MCOperandInfo OperandInfo98[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1879
static const MCOperandInfo OperandInfo99[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1880
static const MCOperandInfo OperandInfo100[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1881
static const MCOperandInfo OperandInfo101[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1882
static const MCOperandInfo OperandInfo102[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1883
static const MCOperandInfo OperandInfo103[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1884
static const MCOperandInfo OperandInfo104[] = { { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1885
static const MCOperandInfo OperandInfo105[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1886
static const MCOperandInfo OperandInfo106[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1887
static const MCOperandInfo OperandInfo107[] = { { PPC::VRSAVERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1888
static const MCOperandInfo OperandInfo108[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1889
static const MCOperandInfo OperandInfo109[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1890
static const MCOperandInfo OperandInfo110[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1891
static const MCOperandInfo OperandInfo111[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1892
static const MCOperandInfo OperandInfo112[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1893
static const MCOperandInfo OperandInfo113[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1894
static const MCOperandInfo OperandInfo114[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1895
static const MCOperandInfo OperandInfo115[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1896
static const MCOperandInfo OperandInfo116[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1897
static const MCOperandInfo OperandInfo117[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1898
static const MCOperandInfo OperandInfo118[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1899
static const MCOperandInfo OperandInfo119[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1900
static const MCOperandInfo OperandInfo120[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1901
static const MCOperandInfo OperandInfo121[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1902
static const MCOperandInfo OperandInfo122[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1903
static const MCOperandInfo OperandInfo123[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1904
static const MCOperandInfo OperandInfo124[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1905
static const MCOperandInfo OperandInfo125[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1906
static const MCOperandInfo OperandInfo126[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1907
static const MCOperandInfo OperandInfo127[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1908
static const MCOperandInfo OperandInfo128[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1909
static const MCOperandInfo OperandInfo129[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1910
static const MCOperandInfo OperandInfo130[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1911
static const MCOperandInfo OperandInfo131[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1912
static const MCOperandInfo OperandInfo132[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1913
static const MCOperandInfo OperandInfo133[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1914
static const MCOperandInfo OperandInfo134[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1915
static const MCOperandInfo OperandInfo135[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1916
static const MCOperandInfo OperandInfo136[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1917
static const MCOperandInfo OperandInfo137[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1918
static const MCOperandInfo OperandInfo138[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1919
static const MCOperandInfo OperandInfo139[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1920
static const MCOperandInfo OperandInfo140[] = { { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1921
static const MCOperandInfo OperandInfo141[] = { { PPC::VRSAVERCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1922
static const MCOperandInfo OperandInfo142[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1923
static const MCOperandInfo OperandInfo143[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1924
static const MCOperandInfo OperandInfo144[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1925
static const MCOperandInfo OperandInfo145[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1926
static const MCOperandInfo OperandInfo146[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1927
static const MCOperandInfo OperandInfo147[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1928
static const MCOperandInfo OperandInfo148[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1929
static const MCOperandInfo OperandInfo149[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1930
static const MCOperandInfo OperandInfo150[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1931
static const MCOperandInfo OperandInfo151[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1932
static const MCOperandInfo OperandInfo152[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1933
static const MCOperandInfo OperandInfo153[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1934
static const MCOperandInfo OperandInfo154[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1935
static const MCOperandInfo OperandInfo155[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1936
static const MCOperandInfo OperandInfo156[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1937
static const MCOperandInfo OperandInfo157[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1938
static const MCOperandInfo OperandInfo158[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1939
static const MCOperandInfo OperandInfo159[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1940
static const MCOperandInfo OperandInfo160[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1941
static const MCOperandInfo OperandInfo161[] = { { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1942
static const MCOperandInfo OperandInfo162[] = { { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1943
static const MCOperandInfo OperandInfo163[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRC_NOR0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1944
static const MCOperandInfo OperandInfo164[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RC_NOX0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1945
static const MCOperandInfo OperandInfo165[] = { { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QBRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1946
static const MCOperandInfo OperandInfo166[] = { { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1947
static const MCOperandInfo OperandInfo167[] = { { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::QSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1948
static const MCOperandInfo OperandInfo168[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1949
static const MCOperandInfo OperandInfo169[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1950
static const MCOperandInfo OperandInfo170[] = { { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1951
static const MCOperandInfo OperandInfo171[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
1952
static const MCOperandInfo OperandInfo172[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
1953
static const MCOperandInfo OperandInfo173[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1954
static const MCOperandInfo OperandInfo174[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1955
static const MCOperandInfo OperandInfo175[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
1956
static const MCOperandInfo OperandInfo176[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1957
static const MCOperandInfo OperandInfo177[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, };
1958
static const MCOperandInfo OperandInfo178[] = { { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, { PPC::F4RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { 1, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { 0, 0|(1<<MCOI::LookupPtrRegClass), MCOI::OPERAND_UNKNOWN, 0 }, };
1959
static const MCOperandInfo OperandInfo179[] = { { PPC::CRRC0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1960
static const MCOperandInfo OperandInfo180[] = { { PPC::CRRC0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1961
static const MCOperandInfo OperandInfo181[] = { { PPC::CRRC0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1962
static const MCOperandInfo OperandInfo182[] = { { PPC::CRRC0RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1963
static const MCOperandInfo OperandInfo183[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1964
static const MCOperandInfo OperandInfo184[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1965
static const MCOperandInfo OperandInfo185[] = { { PPC::CTRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1966
static const MCOperandInfo OperandInfo186[] = { { PPC::CTRRC8RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1967
static const MCOperandInfo OperandInfo187[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1968
static const MCOperandInfo OperandInfo188[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::G8RCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1969
static const MCOperandInfo OperandInfo189[] = { { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
1970
static const MCOperandInfo OperandInfo190[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1971
static const MCOperandInfo OperandInfo191[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::GPRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1972
static const MCOperandInfo OperandInfo192[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1973
static const MCOperandInfo OperandInfo193[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1974
static const MCOperandInfo OperandInfo194[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1975
static const MCOperandInfo OperandInfo195[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1976
static const MCOperandInfo OperandInfo196[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1977
static const MCOperandInfo OperandInfo197[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1978
static const MCOperandInfo OperandInfo198[] = { { PPC::VRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1979
static const MCOperandInfo OperandInfo199[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1980
static const MCOperandInfo OperandInfo200[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1981
static const MCOperandInfo OperandInfo201[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1982
static const MCOperandInfo OperandInfo202[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1983
static const MCOperandInfo OperandInfo203[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1984
static const MCOperandInfo OperandInfo204[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1985
static const MCOperandInfo OperandInfo205[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1986
static const MCOperandInfo OperandInfo206[] = { { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1987
static const MCOperandInfo OperandInfo207[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1988
static const MCOperandInfo OperandInfo208[] = { { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1989
static const MCOperandInfo OperandInfo209[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSFRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1990
static const MCOperandInfo OperandInfo210[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1991
static const MCOperandInfo OperandInfo211[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1992
static const MCOperandInfo OperandInfo212[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, ((0 << 16) | (1 << MCOI::TIED_TO)) }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1993
static const MCOperandInfo OperandInfo213[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1994
static const MCOperandInfo OperandInfo214[] = { { PPC::CRRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1995
static const MCOperandInfo OperandInfo215[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1996
static const MCOperandInfo OperandInfo216[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
1997
static const MCOperandInfo OperandInfo217[] = { { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { PPC::VSRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1998
static const MCOperandInfo OperandInfo218[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
1999
static const MCOperandInfo OperandInfo219[] = { { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, { PPC::CRBITRCRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_IMMEDIATE, 0 }, };
2000
2001
extern const MCInstrDesc PPCInsts[] = {
2002
  { 0,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #0 = PHI
2003
  { 1,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1 = INLINEASM
2004
  { 2,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #2 = CFI_INSTRUCTION
2005
  { 3,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #3 = EH_LABEL
2006
  { 4,  1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #4 = GC_LABEL
2007
  { 5,  0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #5 = KILL
2008
  { 6,  3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #6 = EXTRACT_SUBREG
2009
  { 7,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr },  // Inst #7 = INSERT_SUBREG
2010
  { 8,  1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #8 = IMPLICIT_DEF
2011
  { 9,  4,  1,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6, -1 ,nullptr },  // Inst #9 = SUBREG_TO_REG
2012
  { 10, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #10 = COPY_TO_REGCLASS
2013
  { 11, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #11 = DBG_VALUE
2014
  { 12, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #12 = REG_SEQUENCE
2015
  { 13, 2,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7, -1 ,nullptr },  // Inst #13 = COPY
2016
  { 14, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #14 = BUNDLE
2017
  { 15, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #15 = LIFETIME_START
2018
  { 16, 1,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #16 = LIFETIME_END
2019
  { 17, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #17 = STACKMAP
2020
  { 18, 6,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9, -1 ,nullptr },  // Inst #18 = PATCHPOINT
2021
  { 19, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #19 = LOAD_STACK_GUARD
2022
  { 20, 0,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Call)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #20 = STATEPOINT
2023
  { 21, 2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11, -1 ,nullptr },  // Inst #21 = LOCAL_ESCAPE
2024
  { 22, 1,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #22 = FAULTING_LOAD_OP
2025
  { 23, 3,  1,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo12, -1 ,nullptr },  // Inst #23 = G_ADD
2026
  { 24, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #24 = ADD4
2027
  { 25, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #25 = ADD4TLS
2028
  { 26, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #26 = ADD4o
2029
  { 27, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #27 = ADD8
2030
  { 28, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #28 = ADD8TLS
2031
  { 29, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #29 = ADD8TLS_
2032
  { 30, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #30 = ADD8o
2033
  { 31, 3,  1,  4,  2,  0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList2, OperandInfo13, -1 ,nullptr },  // Inst #31 = ADDC
2034
  { 32, 3,  1,  4,  2,  0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList2, OperandInfo15, -1 ,nullptr },  // Inst #32 = ADDC8
2035
  { 33, 3,  1,  4,  2,  0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList3, OperandInfo15, -1 ,nullptr },  // Inst #33 = ADDC8o
2036
  { 34, 3,  1,  4,  2,  0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList3, OperandInfo13, -1 ,nullptr },  // Inst #34 = ADDCo
2037
  { 35, 3,  1,  4,  2,  0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo13, -1 ,nullptr },  // Inst #35 = ADDE
2038
  { 36, 3,  1,  4,  2,  0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo15, -1 ,nullptr },  // Inst #36 = ADDE8
2039
  { 37, 3,  1,  4,  2,  0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo15, -1 ,nullptr },  // Inst #37 = ADDE8o
2040
  { 38, 3,  1,  4,  2,  0|(1ULL<<MCID::Commutable), 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo13, -1 ,nullptr },  // Inst #38 = ADDEo
2041
  { 39, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #39 = ADDI
2042
  { 40, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #40 = ADDI8
2043
  { 41, 3,  1,  4,  2,  0, 0xcULL, nullptr, ImplicitList2, OperandInfo14, -1 ,nullptr },  // Inst #41 = ADDIC
2044
  { 42, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList2, OperandInfo16, -1 ,nullptr },  // Inst #42 = ADDIC8
2045
  { 43, 3,  1,  4,  2,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, ImplicitList3, OperandInfo14, -1 ,nullptr },  // Inst #43 = ADDICo
2046
  { 44, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #44 = ADDIS
2047
  { 45, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #45 = ADDIS8
2048
  { 46, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #46 = ADDISdtprelHA
2049
  { 47, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #47 = ADDISdtprelHA32
2050
  { 48, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #48 = ADDISgotTprelHA
2051
  { 49, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #49 = ADDIStlsgdHA
2052
  { 50, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #50 = ADDIStlsldHA
2053
  { 51, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #51 = ADDIStocHA
2054
  { 52, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #52 = ADDIdtprelL
2055
  { 53, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #53 = ADDIdtprelL32
2056
  { 54, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #54 = ADDItlsgdL
2057
  { 55, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #55 = ADDItlsgdL32
2058
  { 56, 4,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList4, OperandInfo19, -1 ,nullptr },  // Inst #56 = ADDItlsgdLADDR
2059
  { 57, 4,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList5, OperandInfo20, -1 ,nullptr },  // Inst #57 = ADDItlsgdLADDR32
2060
  { 58, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #58 = ADDItlsldL
2061
  { 59, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #59 = ADDItlsldL32
2062
  { 60, 4,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList4, OperandInfo19, -1 ,nullptr },  // Inst #60 = ADDItlsldLADDR
2063
  { 61, 4,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList5, OperandInfo20, -1 ,nullptr },  // Inst #61 = ADDItlsldLADDR32
2064
  { 62, 3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo18, -1 ,nullptr },  // Inst #62 = ADDItocL
2065
  { 63, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo21, -1 ,nullptr },  // Inst #63 = ADDME
2066
  { 64, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo22, -1 ,nullptr },  // Inst #64 = ADDME8
2067
  { 65, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo22, -1 ,nullptr },  // Inst #65 = ADDME8o
2068
  { 66, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo21, -1 ,nullptr },  // Inst #66 = ADDMEo
2069
  { 67, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo21, -1 ,nullptr },  // Inst #67 = ADDZE
2070
  { 68, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo22, -1 ,nullptr },  // Inst #68 = ADDZE8
2071
  { 69, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo22, -1 ,nullptr },  // Inst #69 = ADDZE8o
2072
  { 70, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo21, -1 ,nullptr },  // Inst #70 = ADDZEo
2073
  { 71, 1,  0,  4,  0,  0, 0x0ULL, ImplicitList6, ImplicitList6, OperandInfo5, -1 ,nullptr },  // Inst #71 = ADJCALLSTACKDOWN
2074
  { 72, 2,  0,  4,  0,  0, 0x0ULL, ImplicitList6, ImplicitList6, OperandInfo7, -1 ,nullptr },  // Inst #72 = ADJCALLSTACKUP
2075
  { 73, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #73 = AND
2076
  { 74, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #74 = AND8
2077
  { 75, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #75 = AND8o
2078
  { 76, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #76 = ANDC
2079
  { 77, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #77 = ANDC8
2080
  { 78, 3,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #78 = ANDC8o
2081
  { 79, 3,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #79 = ANDCo
2082
  { 80, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #80 = ANDISo
2083
  { 81, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo16, -1 ,nullptr },  // Inst #81 = ANDISo8
2084
  { 82, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo14, -1 ,nullptr },  // Inst #82 = ANDIo
2085
  { 83, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo16, -1 ,nullptr },  // Inst #83 = ANDIo8
2086
  { 84, 2,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #84 = ANDIo_1_EQ_BIT
2087
  { 85, 2,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #85 = ANDIo_1_EQ_BIT8
2088
  { 86, 2,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo23, -1 ,nullptr },  // Inst #86 = ANDIo_1_GT_BIT
2089
  { 87, 2,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo24, -1 ,nullptr },  // Inst #87 = ANDIo_1_GT_BIT8
2090
  { 88, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #88 = ANDo
2091
  { 89, 5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr },  // Inst #89 = ATOMIC_CMP_SWAP_I16
2092
  { 90, 5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr },  // Inst #90 = ATOMIC_CMP_SWAP_I32
2093
  { 91, 5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo26, -1 ,nullptr },  // Inst #91 = ATOMIC_CMP_SWAP_I64
2094
  { 92, 5,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo25, -1 ,nullptr },  // Inst #92 = ATOMIC_CMP_SWAP_I8
2095
  { 93, 4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #93 = ATOMIC_LOAD_ADD_I16
2096
  { 94, 4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #94 = ATOMIC_LOAD_ADD_I32
2097
  { 95, 4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #95 = ATOMIC_LOAD_ADD_I64
2098
  { 96, 4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #96 = ATOMIC_LOAD_ADD_I8
2099
  { 97, 4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #97 = ATOMIC_LOAD_AND_I16
2100
  { 98, 4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #98 = ATOMIC_LOAD_AND_I32
2101
  { 99, 4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #99 = ATOMIC_LOAD_AND_I64
2102
  { 100,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #100 = ATOMIC_LOAD_AND_I8
2103
  { 101,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #101 = ATOMIC_LOAD_NAND_I16
2104
  { 102,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #102 = ATOMIC_LOAD_NAND_I32
2105
  { 103,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #103 = ATOMIC_LOAD_NAND_I64
2106
  { 104,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #104 = ATOMIC_LOAD_NAND_I8
2107
  { 105,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #105 = ATOMIC_LOAD_OR_I16
2108
  { 106,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #106 = ATOMIC_LOAD_OR_I32
2109
  { 107,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #107 = ATOMIC_LOAD_OR_I64
2110
  { 108,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #108 = ATOMIC_LOAD_OR_I8
2111
  { 109,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #109 = ATOMIC_LOAD_SUB_I16
2112
  { 110,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #110 = ATOMIC_LOAD_SUB_I32
2113
  { 111,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #111 = ATOMIC_LOAD_SUB_I64
2114
  { 112,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #112 = ATOMIC_LOAD_SUB_I8
2115
  { 113,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #113 = ATOMIC_LOAD_XOR_I16
2116
  { 114,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #114 = ATOMIC_LOAD_XOR_I32
2117
  { 115,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #115 = ATOMIC_LOAD_XOR_I64
2118
  { 116,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #116 = ATOMIC_LOAD_XOR_I8
2119
  { 117,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #117 = ATOMIC_SWAP_I16
2120
  { 118,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #118 = ATOMIC_SWAP_I32
2121
  { 119,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo28, -1 ,nullptr },  // Inst #119 = ATOMIC_SWAP_I64
2122
  { 120,  4,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo27, -1 ,nullptr },  // Inst #120 = ATOMIC_SWAP_I8
2123
  { 121,  0,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #121 = ATTN
2124
  { 122,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #122 = B
2125
  { 123,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #123 = BA
2126
  { 124,  2,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #124 = BC
2127
  { 125,  3,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #125 = BCC
2128
  { 126,  3,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo30, -1 ,nullptr },  // Inst #126 = BCCA
2129
  { 127,  2,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #127 = BCCCTR
2130
  { 128,  2,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList8, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #128 = BCCCTR8
2131
  { 129,  2,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList10, OperandInfo31, -1 ,nullptr },  // Inst #129 = BCCCTRL
2132
  { 130,  2,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList12, OperandInfo31, -1 ,nullptr },  // Inst #130 = BCCCTRL8
2133
  { 131,  3,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, ImplicitList10, OperandInfo30, -1 ,nullptr },  // Inst #131 = BCCL
2134
  { 132,  3,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, ImplicitList10, OperandInfo30, -1 ,nullptr },  // Inst #132 = BCCLA
2135
  { 133,  2,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, nullptr, OperandInfo31, -1 ,nullptr },  // Inst #133 = BCCLR
2136
  { 134,  2,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList10, OperandInfo31, -1 ,nullptr },  // Inst #134 = BCCLRL
2137
  { 135,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #135 = BCCTR
2138
  { 136,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList8, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #136 = BCCTR8
2139
  { 137,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList8, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #137 = BCCTR8n
2140
  { 138,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList10, OperandInfo32, -1 ,nullptr },  // Inst #138 = BCCTRL
2141
  { 139,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList12, OperandInfo32, -1 ,nullptr },  // Inst #139 = BCCTRL8
2142
  { 140,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, ImplicitList12, OperandInfo32, -1 ,nullptr },  // Inst #140 = BCCTRL8n
2143
  { 141,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList10, OperandInfo32, -1 ,nullptr },  // Inst #141 = BCCTRLn
2144
  { 142,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #142 = BCCTRn
2145
  { 143,  2,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, ImplicitList10, OperandInfo29, -1 ,nullptr },  // Inst #143 = BCL
2146
  { 144,  1,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #144 = BCLR
2147
  { 145,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList10, OperandInfo32, -1 ,nullptr },  // Inst #145 = BCLRL
2148
  { 146,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList10, OperandInfo32, -1 ,nullptr },  // Inst #146 = BCLRLn
2149
  { 147,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #147 = BCLRn
2150
  { 148,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, ImplicitList10, OperandInfo5, -1 ,nullptr },  // Inst #148 = BCLalways
2151
  { 149,  2,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, ImplicitList10, OperandInfo29, -1 ,nullptr },  // Inst #149 = BCLn
2152
  { 150,  0,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, nullptr, nullptr, -1 ,nullptr },  // Inst #150 = BCTR
2153
  { 151,  0,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList8, nullptr, nullptr, -1 ,nullptr },  // Inst #151 = BCTR8
2154
  { 152,  0,  0,  4,  3,  0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList9, ImplicitList10, nullptr, -1 ,nullptr },  // Inst #152 = BCTRL
2155
  { 153,  0,  0,  4,  3,  0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList11, ImplicitList12, nullptr, -1 ,nullptr },  // Inst #153 = BCTRL8
2156
  { 154,  2,  0,  8,  3,  0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList11, ImplicitList15, OperandInfo33, -1 ,nullptr },  // Inst #154 = BCTRL8_LDinto_toc
2157
  { 155,  2,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator), 0x38ULL, nullptr, nullptr, OperandInfo29, -1 ,nullptr },  // Inst #155 = BCn
2158
  { 156,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #156 = BDNZ
2159
  { 157,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList8, ImplicitList8, OperandInfo5, -1 ,nullptr },  // Inst #157 = BDNZ8
2160
  { 158,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #158 = BDNZA
2161
  { 159,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #159 = BDNZAm
2162
  { 160,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #160 = BDNZAp
2163
  { 161,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #161 = BDNZL
2164
  { 162,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #162 = BDNZLA
2165
  { 163,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #163 = BDNZLAm
2166
  { 164,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #164 = BDNZLAp
2167
  { 165,  0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #165 = BDNZLR
2168
  { 166,  0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList17, ImplicitList8, nullptr, -1 ,nullptr },  // Inst #166 = BDNZLR8
2169
  { 167,  0,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #167 = BDNZLRL
2170
  { 168,  0,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #168 = BDNZLRLm
2171
  { 169,  0,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #169 = BDNZLRLp
2172
  { 170,  0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #170 = BDNZLRm
2173
  { 171,  0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #171 = BDNZLRp
2174
  { 172,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #172 = BDNZLm
2175
  { 173,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #173 = BDNZLp
2176
  { 174,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #174 = BDNZm
2177
  { 175,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #175 = BDNZp
2178
  { 176,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #176 = BDZ
2179
  { 177,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList8, ImplicitList8, OperandInfo5, -1 ,nullptr },  // Inst #177 = BDZ8
2180
  { 178,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #178 = BDZA
2181
  { 179,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #179 = BDZAm
2182
  { 180,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #180 = BDZAp
2183
  { 181,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #181 = BDZL
2184
  { 182,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #182 = BDZLA
2185
  { 183,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #183 = BDZLAm
2186
  { 184,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #184 = BDZLAp
2187
  { 185,  0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #185 = BDZLR
2188
  { 186,  0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList17, ImplicitList8, nullptr, -1 ,nullptr },  // Inst #186 = BDZLR8
2189
  { 187,  0,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #187 = BDZLRL
2190
  { 188,  0,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #188 = BDZLRLm
2191
  { 189,  0,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #189 = BDZLRLp
2192
  { 190,  0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #190 = BDZLRm
2193
  { 191,  0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, nullptr, -1 ,nullptr },  // Inst #191 = BDZLRp
2194
  { 192,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #192 = BDZLm
2195
  { 193,  1,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #193 = BDZLp
2196
  { 194,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #194 = BDZm
2197
  { 195,  1,  0,  4,  3,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList7, ImplicitList7, OperandInfo5, -1 ,nullptr },  // Inst #195 = BDZp
2198
  { 196,  1,  0,  4,  3,  0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList13, ImplicitList10, OperandInfo5, -1 ,nullptr },  // Inst #196 = BL
2199
  { 197,  1,  0,  4,  3,  0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList13, ImplicitList12, OperandInfo5, -1 ,nullptr },  // Inst #197 = BL8
2200
  { 198,  1,  0,  8,  3,  0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList13, ImplicitList12, OperandInfo5, -1 ,nullptr },  // Inst #198 = BL8_NOP
2201
  { 199,  2,  0,  8,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, ImplicitList12, OperandInfo7, -1 ,nullptr },  // Inst #199 = BL8_NOP_TLS
2202
  { 200,  2,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, ImplicitList12, OperandInfo7, -1 ,nullptr },  // Inst #200 = BL8_TLS
2203
  { 201,  2,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, ImplicitList12, OperandInfo7, -1 ,nullptr },  // Inst #201 = BL8_TLS_
2204
  { 202,  1,  0,  4,  3,  0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList13, ImplicitList10, OperandInfo5, -1 ,nullptr },  // Inst #202 = BLA
2205
  { 203,  1,  0,  4,  3,  0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList13, ImplicitList12, OperandInfo5, -1 ,nullptr },  // Inst #203 = BLA8
2206
  { 204,  1,  0,  8,  3,  0|(1ULL<<MCID::Call), 0x38ULL, ImplicitList13, ImplicitList12, OperandInfo5, -1 ,nullptr },  // Inst #204 = BLA8_NOP
2207
  { 205,  0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList14, nullptr, nullptr, -1 ,nullptr },  // Inst #205 = BLR
2208
  { 206,  0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x38ULL, ImplicitList18, nullptr, nullptr, -1 ,nullptr },  // Inst #206 = BLR8
2209
  { 207,  0,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList14, ImplicitList10, nullptr, -1 ,nullptr },  // Inst #207 = BLRL
2210
  { 208,  2,  0,  4,  3,  0|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, ImplicitList10, OperandInfo7, -1 ,nullptr },  // Inst #208 = BL_TLS
2211
  { 209,  3,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #209 = BPERMD
2212
  { 210,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #210 = BRINC
2213
  { 211,  0,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #211 = CLRBHRB
2214
  { 212,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #212 = CLRLSLDI
2215
  { 213,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #213 = CLRLSLDIo
2216
  { 214,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #214 = CLRLSLWI
2217
  { 215,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #215 = CLRLSLWIo
2218
  { 216,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #216 = CLRRDI
2219
  { 217,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #217 = CLRRDIo
2220
  { 218,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #218 = CLRRWI
2221
  { 219,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #219 = CLRRWIo
2222
  { 220,  3,  1,  4,  2,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #220 = CMPB
2223
  { 221,  3,  1,  4,  2,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #221 = CMPB8
2224
  { 222,  3,  1,  4,  5,  0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #222 = CMPD
2225
  { 223,  3,  1,  4,  5,  0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #223 = CMPDI
2226
  { 224,  3,  1,  4,  5,  0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #224 = CMPLD
2227
  { 225,  3,  1,  4,  5,  0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #225 = CMPLDI
2228
  { 226,  3,  1,  4,  5,  0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #226 = CMPLW
2229
  { 227,  3,  1,  4,  5,  0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #227 = CMPLWI
2230
  { 228,  3,  1,  4,  5,  0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #228 = CMPW
2231
  { 229,  3,  1,  4,  5,  0|(1ULL<<MCID::Compare), 0x8ULL, nullptr, nullptr, OperandInfo39, -1 ,nullptr },  // Inst #229 = CMPWI
2232
  { 230,  2,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #230 = CNTLZD
2233
  { 231,  2,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #231 = CNTLZDo
2234
  { 232,  2,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #232 = CNTLZW
2235
  { 233,  2,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #233 = CNTLZW8
2236
  { 234,  2,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #234 = CNTLZW8o
2237
  { 235,  2,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #235 = CNTLZWo
2238
  { 236,  0,  0,  4,  6,  0, 0x0ULL, nullptr, ImplicitList19, nullptr, -1 ,nullptr },  // Inst #236 = CR6SET
2239
  { 237,  0,  0,  4,  6,  0, 0x0ULL, nullptr, ImplicitList19, nullptr, -1 ,nullptr },  // Inst #237 = CR6UNSET
2240
  { 238,  3,  1,  4,  6,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #238 = CRAND
2241
  { 239,  3,  1,  4,  6,  0, 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #239 = CRANDC
2242
  { 240,  3,  1,  4,  6,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #240 = CREQV
2243
  { 241,  3,  1,  4,  6,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #241 = CRNAND
2244
  { 242,  3,  1,  4,  6,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #242 = CRNOR
2245
  { 243,  3,  1,  4,  6,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #243 = CROR
2246
  { 244,  3,  1,  4,  6,  0, 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #244 = CRORC
2247
  { 245,  1,  1,  4,  6,  0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #245 = CRSET
2248
  { 246,  1,  1,  4,  6,  0, 0x0ULL, nullptr, nullptr, OperandInfo32, -1 ,nullptr },  // Inst #246 = CRUNSET
2249
  { 247,  3,  1,  4,  6,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #247 = CRXOR
2250
  { 248,  2,  0,  4,  7,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #248 = DCBA
2251
  { 249,  2,  0,  4,  7,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #249 = DCBF
2252
  { 250,  2,  0,  4,  7,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #250 = DCBI
2253
  { 251,  2,  0,  4,  7,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #251 = DCBST
2254
  { 252,  3,  0,  4,  7,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #252 = DCBT
2255
  { 253,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #253 = DCBTCT
2256
  { 254,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #254 = DCBTDS
2257
  { 255,  3,  0,  4,  7,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x2ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #255 = DCBTST
2258
  { 256,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #256 = DCBTSTCT
2259
  { 257,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr },  // Inst #257 = DCBTSTDS
2260
  { 258,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #258 = DCBTSTT
2261
  { 259,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #259 = DCBTSTx
2262
  { 260,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #260 = DCBTT
2263
  { 261,  2,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #261 = DCBTx
2264
  { 262,  2,  0,  4,  7,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #262 = DCBZ
2265
  { 263,  2,  0,  4,  7,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #263 = DCBZL
2266
  { 264,  2,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #264 = DCCCI
2267
  { 265,  3,  1,  4,  9,  0, 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #265 = DIVD
2268
  { 266,  3,  1,  4,  9,  0, 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #266 = DIVDE
2269
  { 267,  3,  1,  4,  9,  0, 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #267 = DIVDEU
2270
  { 268,  3,  1,  4,  9,  0, 0xdULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #268 = DIVDEUo
2271
  { 269,  3,  1,  4,  9,  0, 0xdULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #269 = DIVDEo
2272
  { 270,  3,  1,  4,  9,  0, 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #270 = DIVDU
2273
  { 271,  3,  1,  4,  9,  0, 0xdULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #271 = DIVDUo
2274
  { 272,  3,  1,  4,  9,  0, 0xdULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #272 = DIVDo
2275
  { 273,  3,  1,  4,  10, 0, 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #273 = DIVW
2276
  { 274,  3,  1,  4,  10, 0, 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #274 = DIVWE
2277
  { 275,  3,  1,  4,  10, 0, 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #275 = DIVWEU
2278
  { 276,  3,  1,  4,  10, 0, 0xdULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #276 = DIVWEUo
2279
  { 277,  3,  1,  4,  10, 0, 0xdULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #277 = DIVWEo
2280
  { 278,  3,  1,  4,  10, 0, 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #278 = DIVWU
2281
  { 279,  3,  1,  4,  10, 0, 0xdULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #279 = DIVWUo
2282
  { 280,  3,  1,  4,  10, 0, 0xdULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #280 = DIVWo
2283
  { 281,  1,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, PPC::DeprecatedDST ,nullptr },  // Inst #281 = DSS
2284
  { 282,  0,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, PPC::DeprecatedDST ,nullptr },  // Inst #282 = DSSALL
2285
  { 283,  3,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, PPC::DeprecatedDST ,nullptr },  // Inst #283 = DST
2286
  { 284,  3,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, PPC::DeprecatedDST ,nullptr },  // Inst #284 = DST64
2287
  { 285,  3,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, PPC::DeprecatedDST ,nullptr },  // Inst #285 = DSTST
2288
  { 286,  3,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, PPC::DeprecatedDST ,nullptr },  // Inst #286 = DSTST64
2289
  { 287,  3,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, PPC::DeprecatedDST ,nullptr },  // Inst #287 = DSTSTT
2290
  { 288,  3,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, PPC::DeprecatedDST ,nullptr },  // Inst #288 = DSTSTT64
2291
  { 289,  3,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, PPC::DeprecatedDST ,nullptr },  // Inst #289 = DSTT
2292
  { 290,  3,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo45, PPC::DeprecatedDST ,nullptr },  // Inst #290 = DSTT64
2293
  { 291,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList6, ImplicitList6, OperandInfo46, -1 ,nullptr },  // Inst #291 = DYNALLOC
2294
  { 292,  4,  1,  4,  0,  0, 0x0ULL, ImplicitList20, ImplicitList20, OperandInfo47, -1 ,nullptr },  // Inst #292 = DYNALLOC8
2295
  { 293,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #293 = DYNAREAOFFSET
2296
  { 294,  3,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo48, -1 ,nullptr },  // Inst #294 = DYNAREAOFFSET8
2297
  { 295,  1,  0,  4,  0,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #295 = EH_SjLj_LongJmp32
2298
  { 296,  1,  0,  4,  0,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo10, -1 ,nullptr },  // Inst #296 = EH_SjLj_LongJmp64
2299
  { 297,  2,  1,  4,  0,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo49, -1 ,nullptr },  // Inst #297 = EH_SjLj_SetJmp32
2300
  { 298,  2,  1,  4,  0,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList8, OperandInfo49, -1 ,nullptr },  // Inst #298 = EH_SjLj_SetJmp64
2301
  { 299,  1,  0,  4,  0,  0|(1ULL<<MCID::Branch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #299 = EH_SjLj_Setup
2302
  { 300,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #300 = EQV
2303
  { 301,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #301 = EQV8
2304
  { 302,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #302 = EQV8o
2305
  { 303,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #303 = EQVo
2306
  { 304,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #304 = EVABS
2307
  { 305,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #305 = EVADDIW
2308
  { 306,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #306 = EVADDSMIAAW
2309
  { 307,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #307 = EVADDSSIAAW
2310
  { 308,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #308 = EVADDUMIAAW
2311
  { 309,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #309 = EVADDUSIAAW
2312
  { 310,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #310 = EVADDW
2313
  { 311,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #311 = EVAND
2314
  { 312,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #312 = EVANDC
2315
  { 313,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #313 = EVCMPEQ
2316
  { 314,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #314 = EVCMPGTS
2317
  { 315,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #315 = EVCMPGTU
2318
  { 316,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #316 = EVCMPLTS
2319
  { 317,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #317 = EVCMPLTU
2320
  { 318,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #318 = EVCNTLSW
2321
  { 319,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #319 = EVCNTLZW
2322
  { 320,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #320 = EVDIVWS
2323
  { 321,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #321 = EVDIVWU
2324
  { 322,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #322 = EVEQV
2325
  { 323,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #323 = EVEXTSB
2326
  { 324,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #324 = EVEXTSH
2327
  { 325,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #325 = EVLDD
2328
  { 326,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #326 = EVLDDX
2329
  { 327,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #327 = EVLDH
2330
  { 328,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #328 = EVLDHX
2331
  { 329,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #329 = EVLDW
2332
  { 330,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #330 = EVLDWX
2333
  { 331,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #331 = EVLHHESPLAT
2334
  { 332,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #332 = EVLHHESPLATX
2335
  { 333,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #333 = EVLHHOSSPLAT
2336
  { 334,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #334 = EVLHHOSSPLATX
2337
  { 335,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #335 = EVLHHOUSPLAT
2338
  { 336,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #336 = EVLHHOUSPLATX
2339
  { 337,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #337 = EVLWHE
2340
  { 338,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #338 = EVLWHEX
2341
  { 339,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #339 = EVLWHOS
2342
  { 340,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #340 = EVLWHOSX
2343
  { 341,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #341 = EVLWHOU
2344
  { 342,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #342 = EVLWHOUX
2345
  { 343,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #343 = EVLWHSPLAT
2346
  { 344,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #344 = EVLWHSPLATX
2347
  { 345,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #345 = EVLWWSPLAT
2348
  { 346,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #346 = EVLWWSPLATX
2349
  { 347,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #347 = EVMERGEHI
2350
  { 348,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #348 = EVMERGEHILO
2351
  { 349,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #349 = EVMERGELO
2352
  { 350,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #350 = EVMERGELOHI
2353
  { 351,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #351 = EVMHEGSMFAA
2354
  { 352,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #352 = EVMHEGSMFAN
2355
  { 353,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #353 = EVMHEGSMIAA
2356
  { 354,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #354 = EVMHEGSMIAN
2357
  { 355,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #355 = EVMHEGUMIAA
2358
  { 356,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #356 = EVMHEGUMIAN
2359
  { 357,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #357 = EVMHESMF
2360
  { 358,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #358 = EVMHESMFA
2361
  { 359,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #359 = EVMHESMFAAW
2362
  { 360,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #360 = EVMHESMFANW
2363
  { 361,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #361 = EVMHESMI
2364
  { 362,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #362 = EVMHESMIA
2365
  { 363,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #363 = EVMHESMIAAW
2366
  { 364,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #364 = EVMHESMIANW
2367
  { 365,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #365 = EVMHESSF
2368
  { 366,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #366 = EVMHESSFA
2369
  { 367,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #367 = EVMHESSFAAW
2370
  { 368,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #368 = EVMHESSFANW
2371
  { 369,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #369 = EVMHESSIAAW
2372
  { 370,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #370 = EVMHESSIANW
2373
  { 371,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #371 = EVMHEUMI
2374
  { 372,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #372 = EVMHEUMIA
2375
  { 373,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #373 = EVMHEUMIAAW
2376
  { 374,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #374 = EVMHEUMIANW
2377
  { 375,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #375 = EVMHEUSIAAW
2378
  { 376,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #376 = EVMHEUSIANW
2379
  { 377,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #377 = EVMHOGSMFAA
2380
  { 378,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #378 = EVMHOGSMFAN
2381
  { 379,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #379 = EVMHOGSMIAA
2382
  { 380,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #380 = EVMHOGSMIAN
2383
  { 381,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #381 = EVMHOGUMIAA
2384
  { 382,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #382 = EVMHOGUMIAN
2385
  { 383,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #383 = EVMHOSMF
2386
  { 384,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #384 = EVMHOSMFA
2387
  { 385,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #385 = EVMHOSMFAAW
2388
  { 386,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #386 = EVMHOSMFANW
2389
  { 387,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #387 = EVMHOSMI
2390
  { 388,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #388 = EVMHOSMIA
2391
  { 389,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #389 = EVMHOSMIAAW
2392
  { 390,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #390 = EVMHOSMIANW
2393
  { 391,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #391 = EVMHOSSF
2394
  { 392,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #392 = EVMHOSSFA
2395
  { 393,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #393 = EVMHOSSFAAW
2396
  { 394,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #394 = EVMHOSSFANW
2397
  { 395,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #395 = EVMHOSSIAAW
2398
  { 396,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #396 = EVMHOSSIANW
2399
  { 397,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #397 = EVMHOUMI
2400
  { 398,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #398 = EVMHOUMIA
2401
  { 399,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #399 = EVMHOUMIAAW
2402
  { 400,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #400 = EVMHOUMIANW
2403
  { 401,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #401 = EVMHOUSIAAW
2404
  { 402,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #402 = EVMHOUSIANW
2405
  { 403,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #403 = EVMRA
2406
  { 404,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #404 = EVMWHSMF
2407
  { 405,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #405 = EVMWHSMFA
2408
  { 406,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #406 = EVMWHSMI
2409
  { 407,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #407 = EVMWHSMIA
2410
  { 408,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #408 = EVMWHSSF
2411
  { 409,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #409 = EVMWHSSFA
2412
  { 410,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #410 = EVMWHUMI
2413
  { 411,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #411 = EVMWHUMIA
2414
  { 412,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #412 = EVMWLSMIAAW
2415
  { 413,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #413 = EVMWLSMIANW
2416
  { 414,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #414 = EVMWLSSIAAW
2417
  { 415,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #415 = EVMWLSSIANW
2418
  { 416,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #416 = EVMWLUMI
2419
  { 417,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #417 = EVMWLUMIA
2420
  { 418,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #418 = EVMWLUMIAAW
2421
  { 419,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #419 = EVMWLUMIANW
2422
  { 420,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #420 = EVMWLUSIAAW
2423
  { 421,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #421 = EVMWLUSIANW
2424
  { 422,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #422 = EVMWSMF
2425
  { 423,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #423 = EVMWSMFA
2426
  { 424,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #424 = EVMWSMFAA
2427
  { 425,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #425 = EVMWSMFAN
2428
  { 426,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #426 = EVMWSMI
2429
  { 427,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #427 = EVMWSMIA
2430
  { 428,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #428 = EVMWSMIAA
2431
  { 429,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #429 = EVMWSMIAN
2432
  { 430,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #430 = EVMWSSF
2433
  { 431,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #431 = EVMWSSFA
2434
  { 432,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #432 = EVMWSSFAA
2435
  { 433,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #433 = EVMWSSFAN
2436
  { 434,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #434 = EVMWUMI
2437
  { 435,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #435 = EVMWUMIA
2438
  { 436,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #436 = EVMWUMIAA
2439
  { 437,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #437 = EVMWUMIAN
2440
  { 438,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #438 = EVNAND
2441
  { 439,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #439 = EVNEG
2442
  { 440,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #440 = EVNOR
2443
  { 441,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #441 = EVOR
2444
  { 442,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #442 = EVORC
2445
  { 443,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #443 = EVRLW
2446
  { 444,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #444 = EVRLWI
2447
  { 445,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #445 = EVRNDW
2448
  { 446,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #446 = EVSLW
2449
  { 447,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #447 = EVSLWI
2450
  { 448,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #448 = EVSPLATFI
2451
  { 449,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #449 = EVSPLATI
2452
  { 450,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #450 = EVSRWIS
2453
  { 451,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #451 = EVSRWIU
2454
  { 452,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #452 = EVSRWS
2455
  { 453,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #453 = EVSRWU
2456
  { 454,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #454 = EVSTDD
2457
  { 455,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #455 = EVSTDDX
2458
  { 456,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #456 = EVSTDH
2459
  { 457,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #457 = EVSTDHX
2460
  { 458,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #458 = EVSTDW
2461
  { 459,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #459 = EVSTDWX
2462
  { 460,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #460 = EVSTWHE
2463
  { 461,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #461 = EVSTWHEX
2464
  { 462,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #462 = EVSTWHO
2465
  { 463,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #463 = EVSTWHOX
2466
  { 464,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #464 = EVSTWWE
2467
  { 465,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #465 = EVSTWWEX
2468
  { 466,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #466 = EVSTWWO
2469
  { 467,  3,  0,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #467 = EVSTWWOX
2470
  { 468,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #468 = EVSUBFSMIAAW
2471
  { 469,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #469 = EVSUBFSSIAAW
2472
  { 470,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #470 = EVSUBFUMIAAW
2473
  { 471,  2,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #471 = EVSUBFUSIAAW
2474
  { 472,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #472 = EVSUBFW
2475
  { 473,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #473 = EVSUBIFW
2476
  { 474,  3,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #474 = EVXOR
2477
  { 475,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #475 = EXTLDI
2478
  { 476,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #476 = EXTLDIo
2479
  { 477,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #477 = EXTLWI
2480
  { 478,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #478 = EXTLWIo
2481
  { 479,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #479 = EXTRDI
2482
  { 480,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #480 = EXTRDIo
2483
  { 481,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #481 = EXTRWI
2484
  { 482,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #482 = EXTRWIo
2485
  { 483,  2,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #483 = EXTSB
2486
  { 484,  2,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #484 = EXTSB8
2487
  { 485,  2,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #485 = EXTSB8_32_64
2488
  { 486,  2,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #486 = EXTSB8o
2489
  { 487,  2,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #487 = EXTSBo
2490
  { 488,  2,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #488 = EXTSH
2491
  { 489,  2,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #489 = EXTSH8
2492
  { 490,  2,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #490 = EXTSH8_32_64
2493
  { 491,  2,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #491 = EXTSH8o
2494
  { 492,  2,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #492 = EXTSHo
2495
  { 493,  2,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #493 = EXTSW
2496
  { 494,  2,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr },  // Inst #494 = EXTSW_32_64
2497
  { 495,  2,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo53, -1 ,nullptr },  // Inst #495 = EXTSW_32_64o
2498
  { 496,  2,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #496 = EXTSWo
2499
  { 497,  0,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #497 = EnforceIEIO
2500
  { 498,  2,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #498 = FABSD
2501
  { 499,  2,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #499 = FABSDo
2502
  { 500,  2,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #500 = FABSS
2503
  { 501,  2,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo55, -1 ,nullptr },  // Inst #501 = FABSSo
2504
  { 502,  3,  1,  4,  12, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #502 = FADD
2505
  { 503,  3,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #503 = FADDS
2506
  { 504,  3,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo57, -1 ,nullptr },  // Inst #504 = FADDSo
2507
  { 505,  3,  1,  4,  12, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo56, -1 ,nullptr },  // Inst #505 = FADDo
2508
  { 506,  3,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList13, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #506 = FADDrtz
2509
  { 507,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #507 = FCFID
2510
  { 508,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #508 = FCFIDS
2511
  { 509,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo58, -1 ,nullptr },  // Inst #509 = FCFIDSo
2512
  { 510,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #510 = FCFIDU
2513
  { 511,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #511 = FCFIDUS
2514
  { 512,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo58, -1 ,nullptr },  // Inst #512 = FCFIDUSo
2515
  { 513,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #513 = FCFIDUo
2516
  { 514,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #514 = FCFIDo
2517
  { 515,  3,  1,  4,  13, 0|(1ULL<<MCID::Compare), 0x18ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #515 = FCMPUD
2518
  { 516,  3,  1,  4,  13, 0|(1ULL<<MCID::Compare), 0x18ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #516 = FCMPUS
2519
  { 517,  3,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #517 = FCPSGND
2520
  { 518,  3,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo56, -1 ,nullptr },  // Inst #518 = FCPSGNDo
2521
  { 519,  3,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #519 = FCPSGNS
2522
  { 520,  3,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo57, -1 ,nullptr },  // Inst #520 = FCPSGNSo
2523
  { 521,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #521 = FCTID
2524
  { 522,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #522 = FCTIDUZ
2525
  { 523,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #523 = FCTIDUZo
2526
  { 524,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #524 = FCTIDZ
2527
  { 525,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #525 = FCTIDZo
2528
  { 526,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #526 = FCTIDo
2529
  { 527,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #527 = FCTIW
2530
  { 528,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #528 = FCTIWUZ
2531
  { 529,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #529 = FCTIWUZo
2532
  { 530,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #530 = FCTIWZ
2533
  { 531,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #531 = FCTIWZo
2534
  { 532,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #532 = FCTIWo
2535
  { 533,  3,  1,  4,  14, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #533 = FDIV
2536
  { 534,  3,  1,  4,  15, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #534 = FDIVS
2537
  { 535,  3,  1,  4,  15, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo57, -1 ,nullptr },  // Inst #535 = FDIVSo
2538
  { 536,  3,  1,  4,  14, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo56, -1 ,nullptr },  // Inst #536 = FDIVo
2539
  { 537,  4,  1,  4,  16, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #537 = FMADD
2540
  { 538,  4,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #538 = FMADDS
2541
  { 539,  4,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo62, -1 ,nullptr },  // Inst #539 = FMADDSo
2542
  { 540,  4,  1,  4,  16, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo61, -1 ,nullptr },  // Inst #540 = FMADDo
2543
  { 541,  2,  1,  4,  11, 0, 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #541 = FMR
2544
  { 542,  2,  1,  4,  11, 0, 0x0ULL, nullptr, ImplicitList21, OperandInfo55, -1 ,nullptr },  // Inst #542 = FMRo
2545
  { 543,  4,  1,  4,  16, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #543 = FMSUB
2546
  { 544,  4,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #544 = FMSUBS
2547
  { 545,  4,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo62, -1 ,nullptr },  // Inst #545 = FMSUBSo
2548
  { 546,  4,  1,  4,  16, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo61, -1 ,nullptr },  // Inst #546 = FMSUBo
2549
  { 547,  3,  1,  4,  16, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #547 = FMUL
2550
  { 548,  3,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #548 = FMULS
2551
  { 549,  3,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo57, -1 ,nullptr },  // Inst #549 = FMULSo
2552
  { 550,  3,  1,  4,  16, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo56, -1 ,nullptr },  // Inst #550 = FMULo
2553
  { 551,  2,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #551 = FNABSD
2554
  { 552,  2,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #552 = FNABSDo
2555
  { 553,  2,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #553 = FNABSS
2556
  { 554,  2,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo55, -1 ,nullptr },  // Inst #554 = FNABSSo
2557
  { 555,  2,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #555 = FNEGD
2558
  { 556,  2,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #556 = FNEGDo
2559
  { 557,  2,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #557 = FNEGS
2560
  { 558,  2,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo55, -1 ,nullptr },  // Inst #558 = FNEGSo
2561
  { 559,  4,  1,  4,  16, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #559 = FNMADD
2562
  { 560,  4,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #560 = FNMADDS
2563
  { 561,  4,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo62, -1 ,nullptr },  // Inst #561 = FNMADDSo
2564
  { 562,  4,  1,  4,  16, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo61, -1 ,nullptr },  // Inst #562 = FNMADDo
2565
  { 563,  4,  1,  4,  16, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #563 = FNMSUB
2566
  { 564,  4,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #564 = FNMSUBS
2567
  { 565,  4,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo62, -1 ,nullptr },  // Inst #565 = FNMSUBSo
2568
  { 566,  4,  1,  4,  16, 0|(1ULL<<MCID::Commutable), 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo61, -1 ,nullptr },  // Inst #566 = FNMSUBo
2569
  { 567,  2,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #567 = FRE
2570
  { 568,  2,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #568 = FRES
2571
  { 569,  2,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo55, -1 ,nullptr },  // Inst #569 = FRESo
2572
  { 570,  2,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #570 = FREo
2573
  { 571,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #571 = FRIMD
2574
  { 572,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #572 = FRIMDo
2575
  { 573,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #573 = FRIMS
2576
  { 574,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo55, -1 ,nullptr },  // Inst #574 = FRIMSo
2577
  { 575,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #575 = FRIND
2578
  { 576,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #576 = FRINDo
2579
  { 577,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #577 = FRINS
2580
  { 578,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo55, -1 ,nullptr },  // Inst #578 = FRINSo
2581
  { 579,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #579 = FRIPD
2582
  { 580,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #580 = FRIPDo
2583
  { 581,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #581 = FRIPS
2584
  { 582,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo55, -1 ,nullptr },  // Inst #582 = FRIPSo
2585
  { 583,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #583 = FRIZD
2586
  { 584,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #584 = FRIZDo
2587
  { 585,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #585 = FRIZS
2588
  { 586,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo55, -1 ,nullptr },  // Inst #586 = FRIZSo
2589
  { 587,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #587 = FRSP
2590
  { 588,  2,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo58, -1 ,nullptr },  // Inst #588 = FRSPo
2591
  { 589,  2,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #589 = FRSQRTE
2592
  { 590,  2,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #590 = FRSQRTES
2593
  { 591,  2,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo55, -1 ,nullptr },  // Inst #591 = FRSQRTESo
2594
  { 592,  2,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #592 = FRSQRTEo
2595
  { 593,  4,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #593 = FSELD
2596
  { 594,  4,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo61, -1 ,nullptr },  // Inst #594 = FSELDo
2597
  { 595,  4,  1,  4,  11, 0, 0x18ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #595 = FSELS
2598
  { 596,  4,  1,  4,  11, 0, 0x18ULL, nullptr, ImplicitList21, OperandInfo63, -1 ,nullptr },  // Inst #596 = FSELSo
2599
  { 597,  2,  1,  4,  17, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo54, -1 ,nullptr },  // Inst #597 = FSQRT
2600
  { 598,  2,  1,  4,  18, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #598 = FSQRTS
2601
  { 599,  2,  1,  4,  18, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo55, -1 ,nullptr },  // Inst #599 = FSQRTSo
2602
  { 600,  2,  1,  4,  17, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo54, -1 ,nullptr },  // Inst #600 = FSQRTo
2603
  { 601,  3,  1,  4,  12, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo56, -1 ,nullptr },  // Inst #601 = FSUB
2604
  { 602,  3,  1,  4,  11, 0, 0x18ULL, ImplicitList13, nullptr, OperandInfo57, -1 ,nullptr },  // Inst #602 = FSUBS
2605
  { 603,  3,  1,  4,  11, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo57, -1 ,nullptr },  // Inst #603 = FSUBSo
2606
  { 604,  3,  1,  4,  12, 0, 0x18ULL, ImplicitList13, ImplicitList21, OperandInfo56, -1 ,nullptr },  // Inst #604 = FSUBo
2607
  { 605,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList22, OperandInfo16, -1 ,nullptr },  // Inst #605 = GETtlsADDR
2608
  { 606,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList23, OperandInfo14, -1 ,nullptr },  // Inst #606 = GETtlsADDR32
2609
  { 607,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList22, OperandInfo16, -1 ,nullptr },  // Inst #607 = GETtlsldADDR
2610
  { 608,  3,  1,  4,  0,  0|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList23, OperandInfo14, -1 ,nullptr },  // Inst #608 = GETtlsldADDR32
2611
  { 609,  2,  0,  4,  19, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo41, -1 ,nullptr },  // Inst #609 = ICBI
2612
  { 610,  3,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr },  // Inst #610 = ICBT
2613
  { 611,  2,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #611 = ICCCI
2614
  { 612,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #612 = INSLWI
2615
  { 613,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #613 = INSLWIo
2616
  { 614,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #614 = INSRDI
2617
  { 615,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #615 = INSRDIo
2618
  { 616,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #616 = INSRWI
2619
  { 617,  4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo35, -1 ,nullptr },  // Inst #617 = INSRWIo
2620
  { 618,  4,  1,  4,  20, 0|(1ULL<<MCID::Select), 0x8ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #618 = ISEL
2621
  { 619,  4,  1,  4,  20, 0|(1ULL<<MCID::Select), 0x8ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #619 = ISEL8
2622
  { 620,  0,  0,  4,  21, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #620 = ISYNC
2623
  { 621,  3,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo17, -1 ,nullptr },  // Inst #621 = LA
2624
  { 622,  3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #622 = LAx
2625
  { 623,  3,  1,  4,  22, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #623 = LBARX
2626
  { 624,  3,  1,  4,  22, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #624 = LBARXL
2627
  { 625,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #625 = LBZ
2628
  { 626,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #626 = LBZ8
2629
  { 627,  3,  1,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #627 = LBZCIX
2630
  { 628,  4,  2,  4,  23, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #628 = LBZU
2631
  { 629,  4,  2,  4,  23, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #629 = LBZU8
2632
  { 630,  4,  2,  4,  24, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #630 = LBZUX
2633
  { 631,  4,  2,  4,  24, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #631 = LBZUX8
2634
  { 632,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #632 = LBZX
2635
  { 633,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #633 = LBZX8
2636
  { 634,  3,  1,  4,  25, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #634 = LD
2637
  { 635,  3,  1,  4,  26, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #635 = LDARX
2638
  { 636,  3,  1,  4,  26, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #636 = LDARXL
2639
  { 637,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #637 = LDBRX
2640
  { 638,  3,  1,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #638 = LDCIX
2641
  { 639,  4,  2,  4,  27, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #639 = LDU
2642
  { 640,  4,  2,  4,  28, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #640 = LDUX
2643
  { 641,  3,  1,  4,  25, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #641 = LDX
2644
  { 642,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #642 = LDgotTprelL
2645
  { 643,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr },  // Inst #643 = LDgotTprelL32
2646
  { 644,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #644 = LDtoc
2647
  { 645,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #645 = LDtocBA
2648
  { 646,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #646 = LDtocCPT
2649
  { 647,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #647 = LDtocJTI
2650
  { 648,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr },  // Inst #648 = LDtocL
2651
  { 649,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #649 = LFD
2652
  { 650,  4,  2,  4,  30, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr },  // Inst #650 = LFDU
2653
  { 651,  4,  2,  4,  31, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr },  // Inst #651 = LFDUX
2654
  { 652,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #652 = LFDX
2655
  { 653,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #653 = LFIWAX
2656
  { 654,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #654 = LFIWZX
2657
  { 655,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #655 = LFS
2658
  { 656,  4,  2,  4,  30, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr },  // Inst #656 = LFSU
2659
  { 657,  4,  2,  4,  31, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo82, -1 ,nullptr },  // Inst #657 = LFSUX
2660
  { 658,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #658 = LFSX
2661
  { 659,  3,  1,  4,  32, 0|(1ULL<<MCID::MayLoad), 0x14ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #659 = LHA
2662
  { 660,  3,  1,  4,  32, 0|(1ULL<<MCID::MayLoad), 0x14ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #660 = LHA8
2663
  { 661,  3,  1,  4,  22, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #661 = LHARX
2664
  { 662,  3,  1,  4,  22, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #662 = LHARXL
2665
  { 663,  4,  2,  4,  33, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #663 = LHAU
2666
  { 664,  4,  2,  4,  33, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #664 = LHAU8
2667
  { 665,  4,  2,  4,  34, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #665 = LHAUX
2668
  { 666,  4,  2,  4,  34, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #666 = LHAUX8
2669
  { 667,  3,  1,  4,  32, 0|(1ULL<<MCID::MayLoad), 0x14ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #667 = LHAX
2670
  { 668,  3,  1,  4,  32, 0|(1ULL<<MCID::MayLoad), 0x14ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #668 = LHAX8
2671
  { 669,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #669 = LHBRX
2672
  { 670,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #670 = LHBRX8
2673
  { 671,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #671 = LHZ
2674
  { 672,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #672 = LHZ8
2675
  { 673,  3,  1,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #673 = LHZCIX
2676
  { 674,  4,  2,  4,  23, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #674 = LHZU
2677
  { 675,  4,  2,  4,  23, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #675 = LHZU8
2678
  { 676,  4,  2,  4,  24, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #676 = LHZUX
2679
  { 677,  4,  2,  4,  24, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #677 = LHZUX8
2680
  { 678,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #678 = LHZX
2681
  { 679,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #679 = LHZX8
2682
  { 680,  2,  1,  4,  1,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #680 = LI
2683
  { 681,  2,  1,  4,  1,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #681 = LI8
2684
  { 682,  2,  1,  4,  1,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #682 = LIS
2685
  { 683,  2,  1,  4,  1,  0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x8ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #683 = LIS8
2686
  { 684,  3,  1,  4,  35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #684 = LMW
2687
  { 685,  3,  1,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #685 = LSWI
2688
  { 686,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #686 = LVEBX
2689
  { 687,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #687 = LVEHX
2690
  { 688,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #688 = LVEWX
2691
  { 689,  3,  1,  4,  8,  0, 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #689 = LVSL
2692
  { 690,  3,  1,  4,  8,  0, 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #690 = LVSR
2693
  { 691,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #691 = LVX
2694
  { 692,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #692 = LVXL
2695
  { 693,  3,  1,  4,  36, 0|(1ULL<<MCID::MayLoad), 0x14ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #693 = LWA
2696
  { 694,  3,  1,  4,  22, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #694 = LWARX
2697
  { 695,  3,  1,  4,  22, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #695 = LWARXL
2698
  { 696,  4,  2,  4,  34, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #696 = LWAUX
2699
  { 697,  3,  1,  4,  32, 0|(1ULL<<MCID::MayLoad), 0x14ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #697 = LWAX
2700
  { 698,  3,  1,  4,  32, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x14ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #698 = LWAX_32
2701
  { 699,  3,  1,  4,  36, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x14ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #699 = LWA_32
2702
  { 700,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #700 = LWBRX
2703
  { 701,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #701 = LWBRX8
2704
  { 702,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #702 = LWZ
2705
  { 703,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #703 = LWZ8
2706
  { 704,  3,  1,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #704 = LWZCIX
2707
  { 705,  4,  2,  4,  23, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr },  // Inst #705 = LWZU
2708
  { 706,  4,  2,  4,  23, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #706 = LWZU8
2709
  { 707,  4,  2,  4,  24, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #707 = LWZUX
2710
  { 708,  4,  2,  4,  24, 0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #708 = LWZUX8
2711
  { 709,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #709 = LWZX
2712
  { 710,  3,  1,  4,  8,  0|(1ULL<<MCID::MayLoad), 0x10ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #710 = LWZX8
2713
  { 711,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #711 = LWZtoc
2714
  { 712,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #712 = LXSDX
2715
  { 713,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #713 = LXSIWAX
2716
  { 714,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #714 = LXSIWZX
2717
  { 715,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #715 = LXSSPX
2718
  { 716,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #716 = LXVD2X
2719
  { 717,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #717 = LXVDSX
2720
  { 718,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #718 = LXVW4X
2721
  { 719,  1,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #719 = MBAR
2722
  { 720,  2,  1,  4,  37, 0, 0x21ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #720 = MCRF
2723
  { 721,  2,  1,  4,  37, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr },  // Inst #721 = MCRFS
2724
  { 722,  3,  1,  4,  3,  0, 0x1ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #722 = MFBHRBE
2725
  { 723,  1,  1,  4,  38, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #723 = MFCR
2726
  { 724,  1,  1,  4,  38, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x20ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #724 = MFCR8
2727
  { 725,  1,  1,  4,  39, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, ImplicitList7, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #725 = MFCTR
2728
  { 726,  1,  1,  4,  39, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, ImplicitList8, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #726 = MFCTR8
2729
  { 727,  2,  1,  4,  39, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #727 = MFDCR
2730
  { 728,  1,  1,  4,  40, 0, 0x1aULL, ImplicitList13, nullptr, OperandInfo94, -1 ,nullptr },  // Inst #728 = MFFS
2731
  { 729,  1,  1,  4,  40, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, ImplicitList13, ImplicitList21, OperandInfo94, -1 ,nullptr },  // Inst #729 = MFFSo
2732
  { 730,  1,  1,  4,  39, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, ImplicitList10, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #730 = MFLR
2733
  { 731,  1,  1,  4,  39, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, ImplicitList12, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #731 = MFLR8
2734
  { 732,  1,  1,  4,  41, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #732 = MFMSR
2735
  { 733,  2,  1,  4,  42, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x21ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #733 = MFOCRF
2736
  { 734,  2,  1,  4,  42, 0|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x21ULL, nullptr, nullptr, OperandInfo85, -1 ,nullptr },  // Inst #734 = MFOCRF8
2737
  { 735,  2,  1,  4,  39, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #735 = MFSPR
2738
  { 736,  2,  1,  4,  39, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr },  // Inst #736 = MFSPR8
2739
  { 737,  2,  1,  4,  43, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #737 = MFSR
2740
  { 738,  2,  1,  4,  43, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #738 = MFSRIN
2741
  { 739,  2,  1,  4,  44, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #739 = MFTB
2742
  { 740,  1,  1,  4,  44, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo93, -1 ,nullptr },  // Inst #740 = MFTB8
2743
  { 741,  1,  1,  4,  2,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #741 = MFVRSAVE
2744
  { 742,  2,  1,  4,  2,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, nullptr, OperandInfo96, -1 ,nullptr },  // Inst #742 = MFVRSAVEv
2745
  { 743,  1,  1,  4,  45, 0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #743 = MFVSCR
2746
  { 744,  2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo98, -1 ,nullptr },  // Inst #744 = MFVSRD
2747
  { 745,  2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo99, -1 ,nullptr },  // Inst #745 = MFVSRWZ
2748
  { 746,  0,  0,  4,  47, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #746 = MSYNC
2749
  { 747,  2,  0,  4,  48, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x20ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #747 = MTCRF
2750
  { 748,  2,  0,  4,  48, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x20ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #748 = MTCRF8
2751
  { 749,  1,  0,  4,  49, 0, 0x9ULL, nullptr, ImplicitList7, OperandInfo92, -1 ,nullptr },  // Inst #749 = MTCTR
2752
  { 750,  1,  0,  4,  49, 0, 0x9ULL, nullptr, ImplicitList8, OperandInfo93, -1 ,nullptr },  // Inst #750 = MTCTR8
2753
  { 751,  1,  0,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, ImplicitList8, OperandInfo93, -1 ,nullptr },  // Inst #751 = MTCTR8loop
2754
  { 752,  1,  0,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, ImplicitList7, OperandInfo92, -1 ,nullptr },  // Inst #752 = MTCTRloop
2755
  { 753,  2,  0,  4,  49, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #753 = MTDCR
2756
  { 754,  1,  0,  4,  50, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList13, ImplicitList13, OperandInfo5, -1 ,nullptr },  // Inst #754 = MTFSB0
2757
  { 755,  1,  0,  4,  50, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList13, ImplicitList13, OperandInfo5, -1 ,nullptr },  // Inst #755 = MTFSB1
2758
  { 756,  4,  0,  4,  40, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #756 = MTFSF
2759
  { 757,  3,  1,  4,  40, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #757 = MTFSFI
2760
  { 758,  3,  1,  4,  40, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo103, -1 ,nullptr },  // Inst #758 = MTFSFIo
2761
  { 759,  2,  0,  4,  50, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x1aULL, ImplicitList13, ImplicitList13, OperandInfo104, -1 ,nullptr },  // Inst #759 = MTFSFb
2762
  { 760,  4,  0,  4,  40, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr },  // Inst #760 = MTFSFo
2763
  { 761,  1,  0,  4,  49, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, ImplicitList10, OperandInfo92, -1 ,nullptr },  // Inst #761 = MTLR
2764
  { 762,  1,  0,  4,  49, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x9ULL, nullptr, ImplicitList12, OperandInfo93, -1 ,nullptr },  // Inst #762 = MTLR8
2765
  { 763,  2,  0,  4,  51, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #763 = MTMSR
2766
  { 764,  2,  0,  4,  52, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #764 = MTMSRD
2767
  { 765,  2,  1,  4,  48, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x21ULL, nullptr, nullptr, OperandInfo105, -1 ,nullptr },  // Inst #765 = MTOCRF
2768
  { 766,  2,  1,  4,  48, 0|(1ULL<<MCID::ExtraDefRegAllocReq), 0x21ULL, nullptr, nullptr, OperandInfo106, -1 ,nullptr },  // Inst #766 = MTOCRF8
2769
  { 767,  2,  0,  4,  49, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr },  // Inst #767 = MTSPR
2770
  { 768,  2,  0,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo101, -1 ,nullptr },  // Inst #768 = MTSPR8
2771
  { 769,  2,  0,  4,  53, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84, -1 ,nullptr },  // Inst #769 = MTSR
2772
  { 770,  2,  0,  4,  53, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #770 = MTSRIN
2773
  { 771,  1,  0,  4,  2,  0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #771 = MTVRSAVE
2774
  { 772,  2,  1,  4,  2,  0|(1ULL<<MCID::UnmodeledSideEffects), 0xaULL, nullptr, nullptr, OperandInfo107, -1 ,nullptr },  // Inst #772 = MTVRSAVEv
2775
  { 773,  1,  0,  4,  8,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #773 = MTVSCR
2776
  { 774,  2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo108, -1 ,nullptr },  // Inst #774 = MTVSRD
2777
  { 775,  2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #775 = MTVSRWA
2778
  { 776,  2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo109, -1 ,nullptr },  // Inst #776 = MTVSRWZ
2779
  { 777,  3,  1,  4,  54, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #777 = MULHD
2780
  { 778,  3,  1,  4,  55, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #778 = MULHDU
2781
  { 779,  3,  1,  4,  55, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #779 = MULHDUo
2782
  { 780,  3,  1,  4,  54, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #780 = MULHDo
2783
  { 781,  3,  1,  4,  54, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #781 = MULHW
2784
  { 782,  3,  1,  4,  55, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #782 = MULHWU
2785
  { 783,  3,  1,  4,  55, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #783 = MULHWUo
2786
  { 784,  3,  1,  4,  54, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #784 = MULHWo
2787
  { 785,  3,  1,  4,  56, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #785 = MULLD
2788
  { 786,  3,  1,  4,  56, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #786 = MULLDo
2789
  { 787,  3,  1,  4,  57, 0, 0x8ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #787 = MULLI
2790
  { 788,  3,  1,  4,  57, 0, 0x8ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #788 = MULLI8
2791
  { 789,  3,  1,  4,  54, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #789 = MULLW
2792
  { 790,  3,  1,  4,  54, 0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #790 = MULLWo
2793
  { 791,  0,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, ImplicitList10, nullptr, -1 ,nullptr },  // Inst #791 = MoveGOTtoLR
2794
  { 792,  0,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, ImplicitList10, nullptr, -1 ,nullptr },  // Inst #792 = MovePCtoLR
2795
  { 793,  0,  0,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, ImplicitList12, nullptr, -1 ,nullptr },  // Inst #793 = MovePCtoLR8
2796
  { 794,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #794 = NAND
2797
  { 795,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #795 = NAND8
2798
  { 796,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #796 = NAND8o
2799
  { 797,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #797 = NANDo
2800
  { 798,  2,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #798 = NEG
2801
  { 799,  2,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #799 = NEG8
2802
  { 800,  2,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo22, -1 ,nullptr },  // Inst #800 = NEG8o
2803
  { 801,  2,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo21, -1 ,nullptr },  // Inst #801 = NEGo
2804
  { 802,  0,  0,  4,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #802 = NOP
2805
  { 803,  0,  0,  4,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #803 = NOP_GT_PWR6
2806
  { 804,  0,  0,  4,  1,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x8ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #804 = NOP_GT_PWR7
2807
  { 805,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #805 = NOR
2808
  { 806,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #806 = NOR8
2809
  { 807,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #807 = NOR8o
2810
  { 808,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #808 = NORo
2811
  { 809,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #809 = OR
2812
  { 810,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #810 = OR8
2813
  { 811,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #811 = OR8o
2814
  { 812,  3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #812 = ORC
2815
  { 813,  3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #813 = ORC8
2816
  { 814,  3,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #814 = ORC8o
2817
  { 815,  3,  1,  4,  1,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #815 = ORCo
2818
  { 816,  3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #816 = ORI
2819
  { 817,  3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #817 = ORI8
2820
  { 818,  3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #818 = ORIS
2821
  { 819,  3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #819 = ORIS8
2822
  { 820,  3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #820 = ORo
2823
  { 821,  2,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo22, -1 ,nullptr },  // Inst #821 = POPCNTD
2824
  { 822,  2,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #822 = POPCNTW
2825
  { 823,  1,  1,  4,  0,  0, 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #823 = PPC32GOT
2826
  { 824,  2,  2,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #824 = PPC32PICGOT
2827
  { 825,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #825 = QVALIGNI
2828
  { 826,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #826 = QVALIGNIb
2829
  { 827,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo112, -1 ,nullptr },  // Inst #827 = QVALIGNIs
2830
  { 828,  3,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo113, -1 ,nullptr },  // Inst #828 = QVESPLATI
2831
  { 829,  3,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #829 = QVESPLATIb
2832
  { 830,  3,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo115, -1 ,nullptr },  // Inst #830 = QVESPLATIs
2833
  { 831,  2,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #831 = QVFABS
2834
  { 832,  2,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #832 = QVFABSs
2835
  { 833,  3,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #833 = QVFADD
2836
  { 834,  3,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #834 = QVFADDS
2837
  { 835,  3,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #835 = QVFADDSs
2838
  { 836,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #836 = QVFCFID
2839
  { 837,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #837 = QVFCFIDS
2840
  { 838,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #838 = QVFCFIDU
2841
  { 839,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #839 = QVFCFIDUS
2842
  { 840,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #840 = QVFCFIDb
2843
  { 841,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #841 = QVFCMPEQ
2844
  { 842,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #842 = QVFCMPEQb
2845
  { 843,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #843 = QVFCMPEQbs
2846
  { 844,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #844 = QVFCMPGT
2847
  { 845,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #845 = QVFCMPGTb
2848
  { 846,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #846 = QVFCMPGTbs
2849
  { 847,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #847 = QVFCMPLT
2850
  { 848,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #848 = QVFCMPLTb
2851
  { 849,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #849 = QVFCMPLTbs
2852
  { 850,  3,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #850 = QVFCPSGN
2853
  { 851,  3,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #851 = QVFCPSGNs
2854
  { 852,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #852 = QVFCTID
2855
  { 853,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #853 = QVFCTIDU
2856
  { 854,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #854 = QVFCTIDUZ
2857
  { 855,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #855 = QVFCTIDZ
2858
  { 856,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #856 = QVFCTIDb
2859
  { 857,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #857 = QVFCTIW
2860
  { 858,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #858 = QVFCTIWU
2861
  { 859,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #859 = QVFCTIWUZ
2862
  { 860,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #860 = QVFCTIWZ
2863
  { 861,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #861 = QVFLOGICAL
2864
  { 862,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #862 = QVFLOGICALb
2865
  { 863,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #863 = QVFLOGICALs
2866
  { 864,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #864 = QVFMADD
2867
  { 865,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #865 = QVFMADDS
2868
  { 866,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #866 = QVFMADDSs
2869
  { 867,  2,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #867 = QVFMR
2870
  { 868,  2,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo120, -1 ,nullptr },  // Inst #868 = QVFMRb
2871
  { 869,  2,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #869 = QVFMRs
2872
  { 870,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #870 = QVFMSUB
2873
  { 871,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #871 = QVFMSUBS
2874
  { 872,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #872 = QVFMSUBSs
2875
  { 873,  3,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #873 = QVFMUL
2876
  { 874,  3,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #874 = QVFMULS
2877
  { 875,  3,  1,  4,  11, 0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #875 = QVFMULSs
2878
  { 876,  2,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #876 = QVFNABS
2879
  { 877,  2,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #877 = QVFNABSs
2880
  { 878,  2,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #878 = QVFNEG
2881
  { 879,  2,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #879 = QVFNEGs
2882
  { 880,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #880 = QVFNMADD
2883
  { 881,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #881 = QVFNMADDS
2884
  { 882,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #882 = QVFNMADDSs
2885
  { 883,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #883 = QVFNMSUB
2886
  { 884,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #884 = QVFNMSUBS
2887
  { 885,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo124, -1 ,nullptr },  // Inst #885 = QVFNMSUBSs
2888
  { 886,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #886 = QVFPERM
2889
  { 887,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #887 = QVFPERMs
2890
  { 888,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #888 = QVFRE
2891
  { 889,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #889 = QVFRES
2892
  { 890,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #890 = QVFRESs
2893
  { 891,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #891 = QVFRIM
2894
  { 892,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #892 = QVFRIMs
2895
  { 893,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #893 = QVFRIN
2896
  { 894,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #894 = QVFRINs
2897
  { 895,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #895 = QVFRIP
2898
  { 896,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #896 = QVFRIPs
2899
  { 897,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #897 = QVFRIZ
2900
  { 898,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #898 = QVFRIZs
2901
  { 899,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #899 = QVFRSP
2902
  { 900,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #900 = QVFRSPs
2903
  { 901,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #901 = QVFRSQRTE
2904
  { 902,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo116, -1 ,nullptr },  // Inst #902 = QVFRSQRTES
2905
  { 903,  2,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo117, -1 ,nullptr },  // Inst #903 = QVFRSQRTESs
2906
  { 904,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #904 = QVFSEL
2907
  { 905,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #905 = QVFSELb
2908
  { 906,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #906 = QVFSELbb
2909
  { 907,  4,  1,  4,  58, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo129, -1 ,nullptr },  // Inst #907 = QVFSELbs
2910
  { 908,  3,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #908 = QVFSUB
2911
  { 909,  3,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #909 = QVFSUBS
2912
  { 910,  3,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo119, -1 ,nullptr },  // Inst #910 = QVFSUBSs
2913
  { 911,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #911 = QVFTSTNAN
2914
  { 912,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo121, -1 ,nullptr },  // Inst #912 = QVFTSTNANb
2915
  { 913,  3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #913 = QVFTSTNANbs
2916
  { 914,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #914 = QVFXMADD
2917
  { 915,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #915 = QVFXMADDS
2918
  { 916,  3,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #916 = QVFXMUL
2919
  { 917,  3,  1,  4,  11, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #917 = QVFXMULS
2920
  { 918,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #918 = QVFXXCPNMADD
2921
  { 919,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #919 = QVFXXCPNMADDS
2922
  { 920,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #920 = QVFXXMADD
2923
  { 921,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #921 = QVFXXMADDS
2924
  { 922,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #922 = QVFXXNPMADD
2925
  { 923,  4,  1,  4,  16, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #923 = QVFXXNPMADDS
2926
  { 924,  2,  1,  4,  58, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, ImplicitList13, nullptr, OperandInfo130, -1 ,nullptr },  // Inst #924 = QVGPCI
2927
  { 925,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #925 = QVLFCDUX
2928
  { 926,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #926 = QVLFCDUXA
2929
  { 927,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #927 = QVLFCDX
2930
  { 928,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #928 = QVLFCDXA
2931
  { 929,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #929 = QVLFCSUX
2932
  { 930,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #930 = QVLFCSUXA
2933
  { 931,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #931 = QVLFCSX
2934
  { 932,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #932 = QVLFCSXA
2935
  { 933,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #933 = QVLFCSXs
2936
  { 934,  4,  2,  4,  30, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo133, -1 ,nullptr },  // Inst #934 = QVLFDUX
2937
  { 935,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #935 = QVLFDUXA
2938
  { 936,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #936 = QVLFDX
2939
  { 937,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #937 = QVLFDXA
2940
  { 938,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #938 = QVLFDXb
2941
  { 939,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #939 = QVLFIWAX
2942
  { 940,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #940 = QVLFIWAXA
2943
  { 941,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #941 = QVLFIWZX
2944
  { 942,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #942 = QVLFIWZXA
2945
  { 943,  4,  2,  4,  30, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo135, -1 ,nullptr },  // Inst #943 = QVLFSUX
2946
  { 944,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #944 = QVLFSUXA
2947
  { 945,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #945 = QVLFSX
2948
  { 946,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #946 = QVLFSXA
2949
  { 947,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #947 = QVLFSXb
2950
  { 948,  3,  1,  4,  29, 0|(1ULL<<MCID::MayLoad), 0x0ULL, ImplicitList13, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #948 = QVLFSXs
2951
  { 949,  3,  1,  4,  29, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #949 = QVLPCLDX
2952
  { 950,  3,  1,  4,  29, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #950 = QVLPCLSX
2953
  { 951,  2,  1,  4,  29, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo136, -1 ,nullptr },  // Inst #951 = QVLPCLSXint
2954
  { 952,  3,  1,  4,  29, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #952 = QVLPCRDX
2955
  { 953,  3,  1,  4,  29, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #953 = QVLPCRSX
2956
  { 954,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #954 = QVSTFCDUX
2957
  { 955,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #955 = QVSTFCDUXA
2958
  { 956,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #956 = QVSTFCDUXI
2959
  { 957,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #957 = QVSTFCDUXIA
2960
  { 958,  3,  0,  4,  59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #958 = QVSTFCDX
2961
  { 959,  3,  0,  4,  59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #959 = QVSTFCDXA
2962
  { 960,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #960 = QVSTFCDXI
2963
  { 961,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #961 = QVSTFCDXIA
2964
  { 962,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #962 = QVSTFCSUX
2965
  { 963,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #963 = QVSTFCSUXA
2966
  { 964,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #964 = QVSTFCSUXI
2967
  { 965,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #965 = QVSTFCSUXIA
2968
  { 966,  3,  0,  4,  59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #966 = QVSTFCSX
2969
  { 967,  3,  0,  4,  59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #967 = QVSTFCSXA
2970
  { 968,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #968 = QVSTFCSXI
2971
  { 969,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #969 = QVSTFCSXIA
2972
  { 970,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #970 = QVSTFCSXs
2973
  { 971,  4,  1,  4,  60, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #971 = QVSTFDUX
2974
  { 972,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #972 = QVSTFDUXA
2975
  { 973,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #973 = QVSTFDUXI
2976
  { 974,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #974 = QVSTFDUXIA
2977
  { 975,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #975 = QVSTFDX
2978
  { 976,  3,  0,  4,  59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #976 = QVSTFDXA
2979
  { 977,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #977 = QVSTFDXI
2980
  { 978,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #978 = QVSTFDXIA
2981
  { 979,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo134, -1 ,nullptr },  // Inst #979 = QVSTFDXb
2982
  { 980,  3,  0,  4,  59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #980 = QVSTFIWX
2983
  { 981,  3,  0,  4,  59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #981 = QVSTFIWXA
2984
  { 982,  4,  1,  4,  60, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #982 = QVSTFSUX
2985
  { 983,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #983 = QVSTFSUXA
2986
  { 984,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #984 = QVSTFSUXI
2987
  { 985,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #985 = QVSTFSUXIA
2988
  { 986,  4,  1,  4,  60, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo137, -1 ,nullptr },  // Inst #986 = QVSTFSUXs
2989
  { 987,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #987 = QVSTFSX
2990
  { 988,  3,  0,  4,  59, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #988 = QVSTFSXA
2991
  { 989,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #989 = QVSTFSXI
2992
  { 990,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo131, -1 ,nullptr },  // Inst #990 = QVSTFSXIA
2993
  { 991,  3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo132, -1 ,nullptr },  // Inst #991 = QVSTFSXs
2994
  { 992,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #992 = RESTORE_CR
2995
  { 993,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #993 = RESTORE_CRBIT
2996
  { 994,  3,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #994 = RESTORE_VRSAVE
2997
  { 995,  0,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #995 = RFCI
2998
  { 996,  0,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #996 = RFDI
2999
  { 997,  1,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #997 = RFEBB
3000
  { 998,  0,  0,  4,  61, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #998 = RFI
3001
  { 999,  0,  0,  4,  62, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #999 = RFID
3002
  { 1000, 0,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1000 = RFMCI
3003
  { 1001, 4,  1,  4,  63, 0, 0x8ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #1001 = RLDCL
3004
  { 1002, 4,  1,  4,  63, 0, 0x8ULL, nullptr, ImplicitList1, OperandInfo142, -1 ,nullptr },  // Inst #1002 = RLDCLo
3005
  { 1003, 4,  1,  4,  63, 0, 0x8ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr },  // Inst #1003 = RLDCR
3006
  { 1004, 4,  1,  4,  63, 0, 0x8ULL, nullptr, ImplicitList1, OperandInfo142, -1 ,nullptr },  // Inst #1004 = RLDCRo
3007
  { 1005, 4,  1,  4,  64, 0, 0x8ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1005 = RLDIC
3008
  { 1006, 4,  1,  4,  64, 0, 0x8ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1006 = RLDICL
3009
  { 1007, 4,  1,  4,  64, 0, 0x8ULL, nullptr, nullptr, OperandInfo143, -1 ,nullptr },  // Inst #1007 = RLDICL_32_64
3010
  { 1008, 4,  1,  4,  64, 0, 0x8ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #1008 = RLDICLo
3011
  { 1009, 4,  1,  4,  64, 0, 0x8ULL, nullptr, nullptr, OperandInfo34, -1 ,nullptr },  // Inst #1009 = RLDICR
3012
  { 1010, 4,  1,  4,  64, 0, 0x8ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #1010 = RLDICRo
3013
  { 1011, 4,  1,  4,  64, 0, 0x8ULL, nullptr, ImplicitList1, OperandInfo34, -1 ,nullptr },  // Inst #1011 = RLDICo
3014
  { 1012, 5,  1,  4,  64, 0, 0x8ULL, nullptr, nullptr, OperandInfo144, -1 ,nullptr },  // Inst #1012 = RLDIMI
3015
  { 1013, 5,  1,  4,  64, 0, 0x8ULL, nullptr, ImplicitList1, OperandInfo144, -1 ,nullptr },  // Inst #1013 = RLDIMIo
3016
  { 1014, 6,  1,  4,  65, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, nullptr, OperandInfo145, -1 ,nullptr },  // Inst #1014 = RLWIMI
3017
  { 1015, 6,  1,  4,  65, 0, 0xcULL, nullptr, nullptr, OperandInfo146, -1 ,nullptr },  // Inst #1015 = RLWIMI8
3018
  { 1016, 6,  1,  4,  65, 0, 0xcULL, nullptr, ImplicitList1, OperandInfo146, -1 ,nullptr },  // Inst #1016 = RLWIMI8o
3019
  { 1017, 4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1017 = RLWIMIbm
3020
  { 1018, 6,  1,  4,  65, 0|(1ULL<<MCID::Commutable), 0xcULL, nullptr, ImplicitList1, OperandInfo145, -1 ,nullptr },  // Inst #1018 = RLWIMIo
3021
  { 1019, 4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1019 = RLWIMIobm
3022
  { 1020, 5,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo148, -1 ,nullptr },  // Inst #1020 = RLWINM
3023
  { 1021, 5,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo149, -1 ,nullptr },  // Inst #1021 = RLWINM8
3024
  { 1022, 5,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo149, -1 ,nullptr },  // Inst #1022 = RLWINM8o
3025
  { 1023, 4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1023 = RLWINMbm
3026
  { 1024, 5,  1,  4,  2,  0, 0xcULL, nullptr, ImplicitList1, OperandInfo148, -1 ,nullptr },  // Inst #1024 = RLWINMo
3027
  { 1025, 4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1025 = RLWINMobm
3028
  { 1026, 5,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo150, -1 ,nullptr },  // Inst #1026 = RLWNM
3029
  { 1027, 5,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo151, -1 ,nullptr },  // Inst #1027 = RLWNM8
3030
  { 1028, 5,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo151, -1 ,nullptr },  // Inst #1028 = RLWNM8o
3031
  { 1029, 4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1029 = RLWNMbm
3032
  { 1030, 5,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo150, -1 ,nullptr },  // Inst #1030 = RLWNMo
3033
  { 1031, 4,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo147, -1 ,nullptr },  // Inst #1031 = RLWNMobm
3034
  { 1032, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #1032 = ROTRDI
3035
  { 1033, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #1033 = ROTRDIo
3036
  { 1034, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1034 = ROTRWI
3037
  { 1035, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1035 = ROTRWIo
3038
  { 1036, 2,  2,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #1036 = ReadTB
3039
  { 1037, 1,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1037 = SC
3040
  { 1038, 5,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1038 = SELECT_CC_F4
3041
  { 1039, 5,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #1039 = SELECT_CC_F8
3042
  { 1040, 5,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr },  // Inst #1040 = SELECT_CC_I4
3043
  { 1041, 5,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr },  // Inst #1041 = SELECT_CC_I8
3044
  { 1042, 5,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList13, nullptr, OperandInfo156, -1 ,nullptr },  // Inst #1042 = SELECT_CC_QBRC
3045
  { 1043, 5,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList13, nullptr, OperandInfo157, -1 ,nullptr },  // Inst #1043 = SELECT_CC_QFRC
3046
  { 1044, 5,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList13, nullptr, OperandInfo158, -1 ,nullptr },  // Inst #1044 = SELECT_CC_QSRC
3047
  { 1045, 5,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo159, -1 ,nullptr },  // Inst #1045 = SELECT_CC_VRRC
3048
  { 1046, 5,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo153, -1 ,nullptr },  // Inst #1046 = SELECT_CC_VSFRC
3049
  { 1047, 5,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #1047 = SELECT_CC_VSRC
3050
  { 1048, 5,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr },  // Inst #1048 = SELECT_CC_VSSRC
3051
  { 1049, 4,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #1049 = SELECT_F4
3052
  { 1050, 4,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #1050 = SELECT_F8
3053
  { 1051, 4,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #1051 = SELECT_I4
3054
  { 1052, 4,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #1052 = SELECT_I8
3055
  { 1053, 4,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList13, nullptr, OperandInfo165, -1 ,nullptr },  // Inst #1053 = SELECT_QBRC
3056
  { 1054, 4,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList13, nullptr, OperandInfo166, -1 ,nullptr },  // Inst #1054 = SELECT_QFRC
3057
  { 1055, 4,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x0ULL, ImplicitList13, nullptr, OperandInfo167, -1 ,nullptr },  // Inst #1055 = SELECT_QSRC
3058
  { 1056, 4,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr },  // Inst #1056 = SELECT_VRRC
3059
  { 1057, 4,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr },  // Inst #1057 = SELECT_VSFRC
3060
  { 1058, 4,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr },  // Inst #1058 = SELECT_VSRC
3061
  { 1059, 4,  1,  4,  0,  0|(1ULL<<MCID::UsesCustomInserter), 0x2ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #1059 = SELECT_VSSRC
3062
  { 1060, 0,  0,  4,  66, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1060 = SLBIA
3063
  { 1061, 1,  0,  4,  67, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #1061 = SLBIE
3064
  { 1062, 2,  1,  4,  68, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #1062 = SLBMFEE
3065
  { 1063, 2,  0,  4,  69, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #1063 = SLBMTE
3066
  { 1064, 3,  1,  4,  63, 0, 0x8ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr },  // Inst #1064 = SLD
3067
  { 1065, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #1065 = SLDI
3068
  { 1066, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #1066 = SLDIo
3069
  { 1067, 3,  1,  4,  63, 0, 0x8ULL, nullptr, ImplicitList1, OperandInfo170, -1 ,nullptr },  // Inst #1067 = SLDo
3070
  { 1068, 3,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #1068 = SLW
3071
  { 1069, 3,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #1069 = SLW8
3072
  { 1070, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #1070 = SLW8o
3073
  { 1071, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1071 = SLWI
3074
  { 1072, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1072 = SLWIo
3075
  { 1073, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #1073 = SLWo
3076
  { 1074, 3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo139, -1 ,nullptr },  // Inst #1074 = SPILL_CR
3077
  { 1075, 3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo140, -1 ,nullptr },  // Inst #1075 = SPILL_CRBIT
3078
  { 1076, 3,  0,  4,  0,  0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr },  // Inst #1076 = SPILL_VRSAVE
3079
  { 1077, 3,  1,  4,  63, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo170, -1 ,nullptr },  // Inst #1077 = SRAD
3080
  { 1078, 3,  1,  4,  64, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo16, -1 ,nullptr },  // Inst #1078 = SRADI
3081
  { 1079, 3,  1,  4,  64, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo16, -1 ,nullptr },  // Inst #1079 = SRADIo
3082
  { 1080, 3,  1,  4,  63, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo170, -1 ,nullptr },  // Inst #1080 = SRADo
3083
  { 1081, 3,  1,  4,  70, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo13, -1 ,nullptr },  // Inst #1081 = SRAW
3084
  { 1082, 3,  1,  4,  70, 0, 0x8ULL, nullptr, ImplicitList2, OperandInfo14, -1 ,nullptr },  // Inst #1082 = SRAWI
3085
  { 1083, 3,  1,  4,  70, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo14, -1 ,nullptr },  // Inst #1083 = SRAWIo
3086
  { 1084, 3,  1,  4,  70, 0, 0x8ULL, nullptr, ImplicitList3, OperandInfo13, -1 ,nullptr },  // Inst #1084 = SRAWo
3087
  { 1085, 3,  1,  4,  63, 0, 0x8ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr },  // Inst #1085 = SRD
3088
  { 1086, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #1086 = SRDI
3089
  { 1087, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #1087 = SRDIo
3090
  { 1088, 3,  1,  4,  63, 0, 0x8ULL, nullptr, ImplicitList1, OperandInfo170, -1 ,nullptr },  // Inst #1088 = SRDo
3091
  { 1089, 3,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #1089 = SRW
3092
  { 1090, 3,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #1090 = SRW8
3093
  { 1091, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #1091 = SRW8o
3094
  { 1092, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1092 = SRWI
3095
  { 1093, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1093 = SRWIo
3096
  { 1094, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #1094 = SRWo
3097
  { 1095, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #1095 = STB
3098
  { 1096, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #1096 = STB8
3099
  { 1097, 3,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #1097 = STBCIX
3100
  { 1098, 3,  0,  4,  71, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr },  // Inst #1098 = STBCX
3101
  { 1099, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #1099 = STBU
3102
  { 1100, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1100 = STBU8
3103
  { 1101, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1101 = STBUX
3104
  { 1102, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1102 = STBUX8
3105
  { 1103, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #1103 = STBX
3106
  { 1104, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #1104 = STBX8
3107
  { 1105, 3,  0,  4,  73, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #1105 = STD
3108
  { 1106, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #1106 = STDBRX
3109
  { 1107, 3,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #1107 = STDCIX
3110
  { 1108, 3,  0,  4,  74, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr },  // Inst #1108 = STDCX
3111
  { 1109, 4,  1,  4,  75, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1109 = STDU
3112
  { 1110, 4,  1,  4,  76, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1110 = STDUX
3113
  { 1111, 3,  0,  4,  73, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #1111 = STDX
3114
  { 1112, 3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo76, -1 ,nullptr },  // Inst #1112 = STFD
3115
  { 1113, 4,  1,  4,  60, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo175, -1 ,nullptr },  // Inst #1113 = STFDU
3116
  { 1114, 4,  1,  4,  60, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo176, -1 ,nullptr },  // Inst #1114 = STFDUX
3117
  { 1115, 3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #1115 = STFDX
3118
  { 1116, 3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr },  // Inst #1116 = STFIWX
3119
  { 1117, 3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr },  // Inst #1117 = STFS
3120
  { 1118, 4,  1,  4,  60, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #1118 = STFSU
3121
  { 1119, 4,  1,  4,  60, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo178, -1 ,nullptr },  // Inst #1119 = STFSUX
3122
  { 1120, 3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr },  // Inst #1120 = STFSX
3123
  { 1121, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #1121 = STH
3124
  { 1122, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #1122 = STH8
3125
  { 1123, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #1123 = STHBRX
3126
  { 1124, 3,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #1124 = STHCIX
3127
  { 1125, 3,  0,  4,  71, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr },  // Inst #1125 = STHCX
3128
  { 1126, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #1126 = STHU
3129
  { 1127, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1127 = STHU8
3130
  { 1128, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1128 = STHUX
3131
  { 1129, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1129 = STHUX8
3132
  { 1130, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #1130 = STHX
3133
  { 1131, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #1131 = STHX8
3134
  { 1132, 3,  0,  4,  35, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #1132 = STMW
3135
  { 1133, 3,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1133 = STSWI
3136
  { 1134, 3,  0,  4,  45, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1134 = STVEBX
3137
  { 1135, 3,  0,  4,  45, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1135 = STVEHX
3138
  { 1136, 3,  0,  4,  45, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1136 = STVEWX
3139
  { 1137, 3,  0,  4,  45, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1137 = STVX
3140
  { 1138, 3,  0,  4,  45, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1138 = STVXL
3141
  { 1139, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #1139 = STW
3142
  { 1140, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #1140 = STW8
3143
  { 1141, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #1141 = STWBRX
3144
  { 1142, 3,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #1142 = STWCIX
3145
  { 1143, 3,  0,  4,  71, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr },  // Inst #1143 = STWCX
3146
  { 1144, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #1144 = STWU
3147
  { 1145, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x10ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #1145 = STWU8
3148
  { 1146, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo173, -1 ,nullptr },  // Inst #1146 = STWUX
3149
  { 1147, 4,  1,  4,  72, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo174, -1 ,nullptr },  // Inst #1147 = STWUX8
3150
  { 1148, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #1148 = STWX
3151
  { 1149, 3,  0,  4,  45, 0|(1ULL<<MCID::MayStore), 0x14ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr },  // Inst #1149 = STWX8
3152
  { 1150, 3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #1150 = STXSDX
3153
  { 1151, 3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr },  // Inst #1151 = STXSIWX
3154
  { 1152, 3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, nullptr, nullptr, OperandInfo88, -1 ,nullptr },  // Inst #1152 = STXSSPX
3155
  { 1153, 3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #1153 = STXVD2X
3156
  { 1154, 3,  0,  4,  59, 0|(1ULL<<MCID::MayStore), 0x0ULL, ImplicitList13, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #1154 = STXVW4X
3157
  { 1155, 3,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #1155 = SUBF
3158
  { 1156, 3,  1,  4,  2,  0, 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #1156 = SUBF8
3159
  { 1157, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #1157 = SUBF8o
3160
  { 1158, 3,  1,  4,  2,  0, 0xcULL, nullptr, ImplicitList2, OperandInfo13, -1 ,nullptr },  // Inst #1158 = SUBFC
3161
  { 1159, 3,  1,  4,  2,  0, 0xcULL, nullptr, ImplicitList2, OperandInfo15, -1 ,nullptr },  // Inst #1159 = SUBFC8
3162
  { 1160, 3,  1,  4,  2,  0, 0xcULL, nullptr, ImplicitList2, OperandInfo15, -1 ,nullptr },  // Inst #1160 = SUBFC8o
3163
  { 1161, 3,  1,  4,  2,  0, 0xcULL, nullptr, ImplicitList3, OperandInfo13, -1 ,nullptr },  // Inst #1161 = SUBFCo
3164
  { 1162, 3,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo13, -1 ,nullptr },  // Inst #1162 = SUBFE
3165
  { 1163, 3,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo15, -1 ,nullptr },  // Inst #1163 = SUBFE8
3166
  { 1164, 3,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo15, -1 ,nullptr },  // Inst #1164 = SUBFE8o
3167
  { 1165, 3,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo13, -1 ,nullptr },  // Inst #1165 = SUBFEo
3168
  { 1166, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList2, OperandInfo14, -1 ,nullptr },  // Inst #1166 = SUBFIC
3169
  { 1167, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList2, OperandInfo16, -1 ,nullptr },  // Inst #1167 = SUBFIC8
3170
  { 1168, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo21, -1 ,nullptr },  // Inst #1168 = SUBFME
3171
  { 1169, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo22, -1 ,nullptr },  // Inst #1169 = SUBFME8
3172
  { 1170, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo22, -1 ,nullptr },  // Inst #1170 = SUBFME8o
3173
  { 1171, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo21, -1 ,nullptr },  // Inst #1171 = SUBFMEo
3174
  { 1172, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo21, -1 ,nullptr },  // Inst #1172 = SUBFZE
3175
  { 1173, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList2, OperandInfo22, -1 ,nullptr },  // Inst #1173 = SUBFZE8
3176
  { 1174, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo22, -1 ,nullptr },  // Inst #1174 = SUBFZE8o
3177
  { 1175, 2,  1,  4,  2,  0, 0x8ULL, ImplicitList2, ImplicitList3, OperandInfo21, -1 ,nullptr },  // Inst #1175 = SUBFZEo
3178
  { 1176, 3,  1,  4,  2,  0, 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #1176 = SUBFo
3179
  { 1177, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1177 = SUBI
3180
  { 1178, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1178 = SUBIC
3181
  { 1179, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1179 = SUBICo
3182
  { 1180, 3,  0,  0,  0,  0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1180 = SUBIS
3183
  { 1181, 1,  0,  4,  47, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1181 = SYNC
3184
  { 1182, 2,  1,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo179, -1 ,nullptr },  // Inst #1182 = TABORT
3185
  { 1183, 4,  1,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1183 = TABORTDC
3186
  { 1184, 4,  1,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1184 = TABORTDCI
3187
  { 1185, 4,  1,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo180, -1 ,nullptr },  // Inst #1185 = TABORTWC
3188
  { 1186, 4,  1,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1186 = TABORTWCI
3189
  { 1187, 1,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #1187 = TAILB
3190
  { 1188, 1,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #1188 = TAILB8
3191
  { 1189, 1,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #1189 = TAILBA
3192
  { 1190, 1,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, nullptr, OperandInfo5, -1 ,nullptr },  // Inst #1190 = TAILBA8
3193
  { 1191, 0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, nullptr, nullptr, -1 ,nullptr },  // Inst #1191 = TAILBCTR
3194
  { 1192, 0,  0,  4,  3,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, nullptr, nullptr, -1 ,nullptr },  // Inst #1192 = TAILBCTR8
3195
  { 1193, 2,  1,  4,  49, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1193 = TBEGIN
3196
  { 1194, 1,  0,  4,  49, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1194 = TCHECK
3197
  { 1195, 1,  1,  4,  0,  0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UsesCustomInserter)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1195 = TCHECK_RET
3198
  { 1196, 2,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList13, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1196 = TCRETURNai
3199
  { 1197, 2,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList13, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1197 = TCRETURNai8
3200
  { 1198, 2,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList13, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1198 = TCRETURNdi
3201
  { 1199, 2,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList13, nullptr, OperandInfo184, -1 ,nullptr },  // Inst #1199 = TCRETURNdi8
3202
  { 1200, 2,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList13, nullptr, OperandInfo185, -1 ,nullptr },  // Inst #1200 = TCRETURNri
3203
  { 1201, 2,  0,  4,  0,  0|(1ULL<<MCID::Return)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList13, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1201 = TCRETURNri8
3204
  { 1202, 3,  0,  4,  77, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo187, -1 ,nullptr },  // Inst #1202 = TD
3205
  { 1203, 3,  0,  4,  77, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo188, -1 ,nullptr },  // Inst #1203 = TDI
3206
  { 1204, 2,  1,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1204 = TEND
3207
  { 1205, 0,  0,  4,  78, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1205 = TLBIA
3208
  { 1206, 2,  0,  4,  79, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #1206 = TLBIE
3209
  { 1207, 1,  0,  4,  80, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #1207 = TLBIEL
3210
  { 1208, 2,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #1208 = TLBIVAX
3211
  { 1209, 1,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #1209 = TLBLD
3212
  { 1210, 1,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #1210 = TLBLI
3213
  { 1211, 0,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1211 = TLBRE
3214
  { 1212, 3,  1,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1212 = TLBRE2
3215
  { 1213, 2,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #1213 = TLBSX
3216
  { 1214, 3,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #1214 = TLBSX2
3217
  { 1215, 3,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #1215 = TLBSX2D
3218
  { 1216, 0,  0,  4,  81, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1216 = TLBSYNC
3219
  { 1217, 0,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1217 = TLBWE
3220
  { 1218, 3,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1218 = TLBWE2
3221
  { 1219, 0,  0,  4,  8,  0|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1219 = TRAP
3222
  { 1220, 1,  1,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1220 = TRECHKPT
3223
  { 1221, 2,  1,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo190, -1 ,nullptr },  // Inst #1221 = TRECLAIM
3224
  { 1222, 2,  1,  4,  49, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1222 = TSR
3225
  { 1223, 3,  0,  4,  82, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr },  // Inst #1223 = TW
3226
  { 1224, 3,  0,  4,  82, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo191, -1 ,nullptr },  // Inst #1224 = TWI
3227
  { 1225, 2,  1,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo21, -1 ,nullptr },  // Inst #1225 = UPDATE_VRSAVE
3228
  { 1226, 3,  2,  4,  0,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #1226 = UpdateGBR
3229
  { 1227, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1227 = VADDCUQ
3230
  { 1228, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1228 = VADDCUW
3231
  { 1229, 4,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1229 = VADDECUQ
3232
  { 1230, 4,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1230 = VADDEUQM
3233
  { 1231, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1231 = VADDFP
3234
  { 1232, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1232 = VADDSBS
3235
  { 1233, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1233 = VADDSHS
3236
  { 1234, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1234 = VADDSWS
3237
  { 1235, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1235 = VADDUBM
3238
  { 1236, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1236 = VADDUBS
3239
  { 1237, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1237 = VADDUDM
3240
  { 1238, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1238 = VADDUHM
3241
  { 1239, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1239 = VADDUHS
3242
  { 1240, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1240 = VADDUQM
3243
  { 1241, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1241 = VADDUWM
3244
  { 1242, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1242 = VADDUWS
3245
  { 1243, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1243 = VAND
3246
  { 1244, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1244 = VANDC
3247
  { 1245, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1245 = VAVGSB
3248
  { 1246, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1246 = VAVGSH
3249
  { 1247, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1247 = VAVGSW
3250
  { 1248, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1248 = VAVGUB
3251
  { 1249, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1249 = VAVGUH
3252
  { 1250, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1250 = VAVGUW
3253
  { 1251, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1251 = VBPERMQ
3254
  { 1252, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1252 = VCFSX
3255
  { 1253, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1253 = VCFSX_0
3256
  { 1254, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1254 = VCFUX
3257
  { 1255, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1255 = VCFUX_0
3258
  { 1256, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1256 = VCIPHER
3259
  { 1257, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1257 = VCIPHERLAST
3260
  { 1258, 2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1258 = VCLZB
3261
  { 1259, 2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1259 = VCLZD
3262
  { 1260, 2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1260 = VCLZH
3263
  { 1261, 2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1261 = VCLZW
3264
  { 1262, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1262 = VCMPBFP
3265
  { 1263, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1263 = VCMPBFPo
3266
  { 1264, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1264 = VCMPEQFP
3267
  { 1265, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1265 = VCMPEQFPo
3268
  { 1266, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1266 = VCMPEQUB
3269
  { 1267, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1267 = VCMPEQUBo
3270
  { 1268, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1268 = VCMPEQUD
3271
  { 1269, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1269 = VCMPEQUDo
3272
  { 1270, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1270 = VCMPEQUH
3273
  { 1271, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1271 = VCMPEQUHo
3274
  { 1272, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1272 = VCMPEQUW
3275
  { 1273, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1273 = VCMPEQUWo
3276
  { 1274, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1274 = VCMPGEFP
3277
  { 1275, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1275 = VCMPGEFPo
3278
  { 1276, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1276 = VCMPGTFP
3279
  { 1277, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1277 = VCMPGTFPo
3280
  { 1278, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1278 = VCMPGTSB
3281
  { 1279, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1279 = VCMPGTSBo
3282
  { 1280, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1280 = VCMPGTSD
3283
  { 1281, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1281 = VCMPGTSDo
3284
  { 1282, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1282 = VCMPGTSH
3285
  { 1283, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1283 = VCMPGTSHo
3286
  { 1284, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1284 = VCMPGTSW
3287
  { 1285, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1285 = VCMPGTSWo
3288
  { 1286, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1286 = VCMPGTUB
3289
  { 1287, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1287 = VCMPGTUBo
3290
  { 1288, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1288 = VCMPGTUD
3291
  { 1289, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1289 = VCMPGTUDo
3292
  { 1290, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1290 = VCMPGTUH
3293
  { 1291, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1291 = VCMPGTUHo
3294
  { 1292, 3,  1,  4,  83, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1292 = VCMPGTUW
3295
  { 1293, 3,  1,  4,  83, 0, 0x28ULL, nullptr, ImplicitList24, OperandInfo192, -1 ,nullptr },  // Inst #1293 = VCMPGTUWo
3296
  { 1294, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1294 = VCTSXS
3297
  { 1295, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1295 = VCTSXS_0
3298
  { 1296, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1296 = VCTUXS
3299
  { 1297, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1297 = VCTUXS_0
3300
  { 1298, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1298 = VEQV
3301
  { 1299, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1299 = VEXPTEFP
3302
  { 1300, 2,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1300 = VGBBD
3303
  { 1301, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1301 = VLOGEFP
3304
  { 1302, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1302 = VMADDFP
3305
  { 1303, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1303 = VMAXFP
3306
  { 1304, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1304 = VMAXSB
3307
  { 1305, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1305 = VMAXSD
3308
  { 1306, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1306 = VMAXSH
3309
  { 1307, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1307 = VMAXSW
3310
  { 1308, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1308 = VMAXUB
3311
  { 1309, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1309 = VMAXUD
3312
  { 1310, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1310 = VMAXUH
3313
  { 1311, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1311 = VMAXUW
3314
  { 1312, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1312 = VMHADDSHS
3315
  { 1313, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1313 = VMHRADDSHS
3316
  { 1314, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1314 = VMINFP
3317
  { 1315, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1315 = VMINSB
3318
  { 1316, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1316 = VMINSD
3319
  { 1317, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1317 = VMINSH
3320
  { 1318, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1318 = VMINSW
3321
  { 1319, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1319 = VMINUB
3322
  { 1320, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1320 = VMINUD
3323
  { 1321, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1321 = VMINUH
3324
  { 1322, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1322 = VMINUW
3325
  { 1323, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1323 = VMLADDUHM
3326
  { 1324, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1324 = VMRGEW
3327
  { 1325, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1325 = VMRGHB
3328
  { 1326, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1326 = VMRGHH
3329
  { 1327, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1327 = VMRGHW
3330
  { 1328, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1328 = VMRGLB
3331
  { 1329, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1329 = VMRGLH
3332
  { 1330, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1330 = VMRGLW
3333
  { 1331, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1331 = VMRGOW
3334
  { 1332, 4,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1332 = VMSUMMBM
3335
  { 1333, 4,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1333 = VMSUMSHM
3336
  { 1334, 4,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1334 = VMSUMSHS
3337
  { 1335, 4,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1335 = VMSUMUBM
3338
  { 1336, 4,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1336 = VMSUMUHM
3339
  { 1337, 4,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1337 = VMSUMUHS
3340
  { 1338, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1338 = VMULESB
3341
  { 1339, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1339 = VMULESH
3342
  { 1340, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1340 = VMULESW
3343
  { 1341, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1341 = VMULEUB
3344
  { 1342, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1342 = VMULEUH
3345
  { 1343, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1343 = VMULEUW
3346
  { 1344, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1344 = VMULOSB
3347
  { 1345, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1345 = VMULOSH
3348
  { 1346, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1346 = VMULOSW
3349
  { 1347, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1347 = VMULOUB
3350
  { 1348, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1348 = VMULOUH
3351
  { 1349, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1349 = VMULOUW
3352
  { 1350, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1350 = VMULUWM
3353
  { 1351, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1351 = VNAND
3354
  { 1352, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1352 = VNCIPHER
3355
  { 1353, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1353 = VNCIPHERLAST
3356
  { 1354, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1354 = VNMSUBFP
3357
  { 1355, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1355 = VNOR
3358
  { 1356, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1356 = VOR
3359
  { 1357, 3,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1357 = VORC
3360
  { 1358, 4,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1358 = VPERM
3361
  { 1359, 4,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1359 = VPERMXOR
3362
  { 1360, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1360 = VPKPX
3363
  { 1361, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1361 = VPKSDSS
3364
  { 1362, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1362 = VPKSDUS
3365
  { 1363, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1363 = VPKSHSS
3366
  { 1364, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1364 = VPKSHUS
3367
  { 1365, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1365 = VPKSWSS
3368
  { 1366, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1366 = VPKSWUS
3369
  { 1367, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1367 = VPKUDUM
3370
  { 1368, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1368 = VPKUDUS
3371
  { 1369, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1369 = VPKUHUM
3372
  { 1370, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1370 = VPKUHUS
3373
  { 1371, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1371 = VPKUWUM
3374
  { 1372, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1372 = VPKUWUS
3375
  { 1373, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1373 = VPMSUMB
3376
  { 1374, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1374 = VPMSUMD
3377
  { 1375, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1375 = VPMSUMH
3378
  { 1376, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1376 = VPMSUMW
3379
  { 1377, 2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1377 = VPOPCNTB
3380
  { 1378, 2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1378 = VPOPCNTD
3381
  { 1379, 2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1379 = VPOPCNTH
3382
  { 1380, 2,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1380 = VPOPCNTW
3383
  { 1381, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1381 = VREFP
3384
  { 1382, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1382 = VRFIM
3385
  { 1383, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1383 = VRFIN
3386
  { 1384, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1384 = VRFIP
3387
  { 1385, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1385 = VRFIZ
3388
  { 1386, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1386 = VRLB
3389
  { 1387, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1387 = VRLD
3390
  { 1388, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1388 = VRLH
3391
  { 1389, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1389 = VRLW
3392
  { 1390, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1390 = VRSQRTEFP
3393
  { 1391, 2,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1391 = VSBOX
3394
  { 1392, 4,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1392 = VSEL
3395
  { 1393, 4,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1393 = VSHASIGMAD
3396
  { 1394, 4,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo196, -1 ,nullptr },  // Inst #1394 = VSHASIGMAW
3397
  { 1395, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1395 = VSL
3398
  { 1396, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1396 = VSLB
3399
  { 1397, 3,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1397 = VSLD
3400
  { 1398, 4,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo197, -1 ,nullptr },  // Inst #1398 = VSLDOI
3401
  { 1399, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1399 = VSLH
3402
  { 1400, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1400 = VSLO
3403
  { 1401, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1401 = VSLW
3404
  { 1402, 3,  1,  4,  58, 0, 0x28ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1402 = VSPLTB
3405
  { 1403, 3,  1,  4,  58, 0, 0x28ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1403 = VSPLTH
3406
  { 1404, 2,  1,  4,  58, 0, 0x28ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #1404 = VSPLTISB
3407
  { 1405, 2,  1,  4,  58, 0, 0x28ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #1405 = VSPLTISH
3408
  { 1406, 2,  1,  4,  58, 0, 0x28ULL, nullptr, nullptr, OperandInfo198, -1 ,nullptr },  // Inst #1406 = VSPLTISW
3409
  { 1407, 3,  1,  4,  58, 0, 0x28ULL, nullptr, nullptr, OperandInfo194, -1 ,nullptr },  // Inst #1407 = VSPLTW
3410
  { 1408, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1408 = VSR
3411
  { 1409, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1409 = VSRAB
3412
  { 1410, 3,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1410 = VSRAD
3413
  { 1411, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1411 = VSRAH
3414
  { 1412, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1412 = VSRAW
3415
  { 1413, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1413 = VSRB
3416
  { 1414, 3,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1414 = VSRD
3417
  { 1415, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1415 = VSRH
3418
  { 1416, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1416 = VSRO
3419
  { 1417, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1417 = VSRW
3420
  { 1418, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1418 = VSUBCUQ
3421
  { 1419, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1419 = VSUBCUW
3422
  { 1420, 4,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1420 = VSUBECUQ
3423
  { 1421, 4,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo193, -1 ,nullptr },  // Inst #1421 = VSUBEUQM
3424
  { 1422, 3,  1,  4,  46, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1422 = VSUBFP
3425
  { 1423, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1423 = VSUBSBS
3426
  { 1424, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1424 = VSUBSHS
3427
  { 1425, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1425 = VSUBSWS
3428
  { 1426, 3,  1,  4,  46, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1426 = VSUBUBM
3429
  { 1427, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1427 = VSUBUBS
3430
  { 1428, 3,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1428 = VSUBUDM
3431
  { 1429, 3,  1,  4,  46, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1429 = VSUBUHM
3432
  { 1430, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1430 = VSUBUHS
3433
  { 1431, 3,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1431 = VSUBUQM
3434
  { 1432, 3,  1,  4,  46, 0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1432 = VSUBUWM
3435
  { 1433, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1433 = VSUBUWS
3436
  { 1434, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1434 = VSUM2SWS
3437
  { 1435, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1435 = VSUM4SBS
3438
  { 1436, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1436 = VSUM4SHS
3439
  { 1437, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1437 = VSUM4UBS
3440
  { 1438, 3,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1438 = VSUMSWS
3441
  { 1439, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1439 = VUPKHPX
3442
  { 1440, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1440 = VUPKHSB
3443
  { 1441, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1441 = VUPKHSH
3444
  { 1442, 2,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1442 = VUPKHSW
3445
  { 1443, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1443 = VUPKLPX
3446
  { 1444, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1444 = VUPKLSB
3447
  { 1445, 2,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1445 = VUPKLSH
3448
  { 1446, 2,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo195, -1 ,nullptr },  // Inst #1446 = VUPKLSW
3449
  { 1447, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x28ULL, nullptr, nullptr, OperandInfo192, -1 ,nullptr },  // Inst #1447 = VXOR
3450
  { 1448, 1,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1448 = V_SET0
3451
  { 1449, 1,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1449 = V_SET0B
3452
  { 1450, 1,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1450 = V_SET0H
3453
  { 1451, 1,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1451 = V_SETALLONES
3454
  { 1452, 1,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1452 = V_SETALLONESB
3455
  { 1453, 1,  1,  4,  4,  0, 0x28ULL, nullptr, nullptr, OperandInfo97, -1 ,nullptr },  // Inst #1453 = V_SETALLONESH
3456
  { 1454, 1,  0,  4,  8,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1454 = WAIT
3457
  { 1455, 1,  0,  4,  51, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr },  // Inst #1455 = WRTEE
3458
  { 1456, 1,  0,  4,  51, 0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1456 = WRTEEI
3459
  { 1457, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo13, -1 ,nullptr },  // Inst #1457 = XOR
3460
  { 1458, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, nullptr, OperandInfo15, -1 ,nullptr },  // Inst #1458 = XOR8
3461
  { 1459, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo15, -1 ,nullptr },  // Inst #1459 = XOR8o
3462
  { 1460, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1460 = XORI
3463
  { 1461, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #1461 = XORI8
3464
  { 1462, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo14, -1 ,nullptr },  // Inst #1462 = XORIS
3465
  { 1463, 3,  1,  4,  1,  0, 0x8ULL, nullptr, nullptr, OperandInfo16, -1 ,nullptr },  // Inst #1463 = XORIS8
3466
  { 1464, 3,  1,  4,  1,  0|(1ULL<<MCID::Commutable), 0x8ULL, nullptr, ImplicitList1, OperandInfo13, -1 ,nullptr },  // Inst #1464 = XORo
3467
  { 1465, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1465 = XSABSDP
3468
  { 1466, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1466 = XSADDDP
3469
  { 1467, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1467 = XSADDSP
3470
  { 1468, 3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1468 = XSCMPODP
3471
  { 1469, 3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1469 = XSCMPUDP
3472
  { 1470, 3,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1470 = XSCPSGNDP
3473
  { 1471, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1471 = XSCVDPSP
3474
  { 1472, 2,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo203, -1 ,nullptr },  // Inst #1472 = XSCVDPSPN
3475
  { 1473, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1473 = XSCVDPSXDS
3476
  { 1474, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1474 = XSCVDPSXWS
3477
  { 1475, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1475 = XSCVDPUXDS
3478
  { 1476, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1476 = XSCVDPUXWS
3479
  { 1477, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1477 = XSCVSPDP
3480
  { 1478, 2,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo204, -1 ,nullptr },  // Inst #1478 = XSCVSPDPN
3481
  { 1479, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1479 = XSCVSXDDP
3482
  { 1480, 2,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1480 = XSCVSXDSP
3483
  { 1481, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1481 = XSCVUXDDP
3484
  { 1482, 2,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo205, -1 ,nullptr },  // Inst #1482 = XSCVUXDSP
3485
  { 1483, 3,  1,  4,  14, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1483 = XSDIVDP
3486
  { 1484, 3,  1,  4,  15, 0, 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1484 = XSDIVSP
3487
  { 1485, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1485 = XSMADDADP
3488
  { 1486, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1486 = XSMADDASP
3489
  { 1487, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1487 = XSMADDMDP
3490
  { 1488, 4,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1488 = XSMADDMSP
3491
  { 1489, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1489 = XSMAXDP
3492
  { 1490, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1490 = XSMINDP
3493
  { 1491, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1491 = XSMSUBADP
3494
  { 1492, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1492 = XSMSUBASP
3495
  { 1493, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1493 = XSMSUBMDP
3496
  { 1494, 4,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1494 = XSMSUBMSP
3497
  { 1495, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1495 = XSMULDP
3498
  { 1496, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1496 = XSMULSP
3499
  { 1497, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1497 = XSNABSDP
3500
  { 1498, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1498 = XSNEGDP
3501
  { 1499, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1499 = XSNMADDADP
3502
  { 1500, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1500 = XSNMADDASP
3503
  { 1501, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1501 = XSNMADDMDP
3504
  { 1502, 4,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1502 = XSNMADDMSP
3505
  { 1503, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1503 = XSNMSUBADP
3506
  { 1504, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1504 = XSNMSUBASP
3507
  { 1505, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo206, -1 ,nullptr },  // Inst #1505 = XSNMSUBMDP
3508
  { 1506, 4,  1,  4,  4,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo207, -1 ,nullptr },  // Inst #1506 = XSNMSUBMSP
3509
  { 1507, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1507 = XSRDPI
3510
  { 1508, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1508 = XSRDPIC
3511
  { 1509, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1509 = XSRDPIM
3512
  { 1510, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1510 = XSRDPIP
3513
  { 1511, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1511 = XSRDPIZ
3514
  { 1512, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1512 = XSREDP
3515
  { 1513, 2,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #1513 = XSRESP
3516
  { 1514, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1514 = XSRSQRTEDP
3517
  { 1515, 2,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #1515 = XSRSQRTESP
3518
  { 1516, 2,  1,  4,  17, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1516 = XSSQRTDP
3519
  { 1517, 2,  1,  4,  18, 0, 0x0ULL, nullptr, nullptr, OperandInfo208, -1 ,nullptr },  // Inst #1517 = XSSQRTSP
3520
  { 1518, 3,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1518 = XSSUBDP
3521
  { 1519, 3,  1,  4,  4,  0, 0x0ULL, nullptr, nullptr, OperandInfo201, -1 ,nullptr },  // Inst #1519 = XSSUBSP
3522
  { 1520, 3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo202, -1 ,nullptr },  // Inst #1520 = XSTDIVDP
3523
  { 1521, 2,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo209, -1 ,nullptr },  // Inst #1521 = XSTSQRTDP
3524
  { 1522, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1522 = XVABSDP
3525
  { 1523, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1523 = XVABSSP
3526
  { 1524, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1524 = XVADDDP
3527
  { 1525, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1525 = XVADDSP
3528
  { 1526, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1526 = XVCMPEQDP
3529
  { 1527, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, ImplicitList24, OperandInfo211, -1 ,nullptr },  // Inst #1527 = XVCMPEQDPo
3530
  { 1528, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1528 = XVCMPEQSP
3531
  { 1529, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, ImplicitList24, OperandInfo211, -1 ,nullptr },  // Inst #1529 = XVCMPEQSPo
3532
  { 1530, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1530 = XVCMPGEDP
3533
  { 1531, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, ImplicitList24, OperandInfo211, -1 ,nullptr },  // Inst #1531 = XVCMPGEDPo
3534
  { 1532, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1532 = XVCMPGESP
3535
  { 1533, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, ImplicitList24, OperandInfo211, -1 ,nullptr },  // Inst #1533 = XVCMPGESPo
3536
  { 1534, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1534 = XVCMPGTDP
3537
  { 1535, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, ImplicitList24, OperandInfo211, -1 ,nullptr },  // Inst #1535 = XVCMPGTDPo
3538
  { 1536, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1536 = XVCMPGTSP
3539
  { 1537, 3,  1,  4,  83, 0, 0x0ULL, ImplicitList13, ImplicitList24, OperandInfo211, -1 ,nullptr },  // Inst #1537 = XVCMPGTSPo
3540
  { 1538, 3,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1538 = XVCPSGNDP
3541
  { 1539, 3,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1539 = XVCPSGNSP
3542
  { 1540, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1540 = XVCVDPSP
3543
  { 1541, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1541 = XVCVDPSXDS
3544
  { 1542, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1542 = XVCVDPSXWS
3545
  { 1543, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1543 = XVCVDPUXDS
3546
  { 1544, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1544 = XVCVDPUXWS
3547
  { 1545, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1545 = XVCVSPDP
3548
  { 1546, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1546 = XVCVSPSXDS
3549
  { 1547, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1547 = XVCVSPSXWS
3550
  { 1548, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1548 = XVCVSPUXDS
3551
  { 1549, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1549 = XVCVSPUXWS
3552
  { 1550, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1550 = XVCVSXDDP
3553
  { 1551, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1551 = XVCVSXDSP
3554
  { 1552, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1552 = XVCVSXWDP
3555
  { 1553, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1553 = XVCVSXWSP
3556
  { 1554, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1554 = XVCVUXDDP
3557
  { 1555, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1555 = XVCVUXDSP
3558
  { 1556, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1556 = XVCVUXWDP
3559
  { 1557, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1557 = XVCVUXWSP
3560
  { 1558, 3,  1,  4,  14, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1558 = XVDIVDP
3561
  { 1559, 3,  1,  4,  15, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1559 = XVDIVSP
3562
  { 1560, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1560 = XVMADDADP
3563
  { 1561, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1561 = XVMADDASP
3564
  { 1562, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1562 = XVMADDMDP
3565
  { 1563, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1563 = XVMADDMSP
3566
  { 1564, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1564 = XVMAXDP
3567
  { 1565, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1565 = XVMAXSP
3568
  { 1566, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1566 = XVMINDP
3569
  { 1567, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1567 = XVMINSP
3570
  { 1568, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1568 = XVMSUBADP
3571
  { 1569, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1569 = XVMSUBASP
3572
  { 1570, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1570 = XVMSUBMDP
3573
  { 1571, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1571 = XVMSUBMSP
3574
  { 1572, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1572 = XVMULDP
3575
  { 1573, 3,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1573 = XVMULSP
3576
  { 1574, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1574 = XVNABSDP
3577
  { 1575, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1575 = XVNABSSP
3578
  { 1576, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1576 = XVNEGDP
3579
  { 1577, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1577 = XVNEGSP
3580
  { 1578, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1578 = XVNMADDADP
3581
  { 1579, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1579 = XVNMADDASP
3582
  { 1580, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1580 = XVNMADDMDP
3583
  { 1581, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1581 = XVNMADDMSP
3584
  { 1582, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1582 = XVNMSUBADP
3585
  { 1583, 4,  1,  4,  4,  0|(1ULL<<MCID::Commutable), 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1583 = XVNMSUBASP
3586
  { 1584, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1584 = XVNMSUBMDP
3587
  { 1585, 4,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo212, -1 ,nullptr },  // Inst #1585 = XVNMSUBMSP
3588
  { 1586, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1586 = XVRDPI
3589
  { 1587, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1587 = XVRDPIC
3590
  { 1588, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1588 = XVRDPIM
3591
  { 1589, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1589 = XVRDPIP
3592
  { 1590, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1590 = XVRDPIZ
3593
  { 1591, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1591 = XVREDP
3594
  { 1592, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1592 = XVRESP
3595
  { 1593, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1593 = XVRSPI
3596
  { 1594, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1594 = XVRSPIC
3597
  { 1595, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1595 = XVRSPIM
3598
  { 1596, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1596 = XVRSPIP
3599
  { 1597, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1597 = XVRSPIZ
3600
  { 1598, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1598 = XVRSQRTEDP
3601
  { 1599, 2,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1599 = XVRSQRTESP
3602
  { 1600, 2,  1,  4,  17, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1600 = XVSQRTDP
3603
  { 1601, 2,  1,  4,  18, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo210, -1 ,nullptr },  // Inst #1601 = XVSQRTSP
3604
  { 1602, 3,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1602 = XVSUBDP
3605
  { 1603, 3,  1,  4,  4,  0, 0x0ULL, ImplicitList13, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1603 = XVSUBSP
3606
  { 1604, 3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo213, -1 ,nullptr },  // Inst #1604 = XVTDIVDP
3607
  { 1605, 3,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo213, -1 ,nullptr },  // Inst #1605 = XVTDIVSP
3608
  { 1606, 2,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo214, -1 ,nullptr },  // Inst #1606 = XVTSQRTDP
3609
  { 1607, 2,  1,  4,  13, 0, 0x0ULL, ImplicitList13, nullptr, OperandInfo214, -1 ,nullptr },  // Inst #1607 = XVTSQRTSP
3610
  { 1608, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1608 = XXLAND
3611
  { 1609, 3,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1609 = XXLANDC
3612
  { 1610, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1610 = XXLEQV
3613
  { 1611, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1611 = XXLNAND
3614
  { 1612, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1612 = XXLNOR
3615
  { 1613, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1613 = XXLOR
3616
  { 1614, 3,  1,  4,  46, 0, 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1614 = XXLORC
3617
  { 1615, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr },  // Inst #1615 = XXLORf
3618
  { 1616, 3,  1,  4,  46, 0|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1616 = XXLXOR
3619
  { 1617, 3,  1,  4,  58, 0, 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1617 = XXMRGHW
3620
  { 1618, 3,  1,  4,  58, 0, 0x0ULL, nullptr, nullptr, OperandInfo211, -1 ,nullptr },  // Inst #1618 = XXMRGLW
3621
  { 1619, 4,  1,  4,  58, 0, 0x0ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr },  // Inst #1619 = XXPERMDI
3622
  { 1620, 4,  1,  4,  58, 0, 0x0ULL, nullptr, nullptr, OperandInfo216, -1 ,nullptr },  // Inst #1620 = XXSEL
3623
  { 1621, 4,  1,  4,  58, 0, 0x0ULL, nullptr, nullptr, OperandInfo215, -1 ,nullptr },  // Inst #1621 = XXSLDWI
3624
  { 1622, 3,  1,  4,  58, 0, 0x0ULL, nullptr, nullptr, OperandInfo217, -1 ,nullptr },  // Inst #1622 = XXSPLTW
3625
  { 1623, 3,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo218, -1 ,nullptr },  // Inst #1623 = gBC
3626
  { 1624, 3,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList7, OperandInfo218, -1 ,nullptr },  // Inst #1624 = gBCA
3627
  { 1625, 3,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, OperandInfo219, -1 ,nullptr },  // Inst #1625 = gBCCTR
3628
  { 1626, 3,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList25, OperandInfo219, -1 ,nullptr },  // Inst #1626 = gBCCTRL
3629
  { 1627, 3,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList25, OperandInfo218, -1 ,nullptr },  // Inst #1627 = gBCL
3630
  { 1628, 3,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, ImplicitList25, OperandInfo218, -1 ,nullptr },  // Inst #1628 = gBCLA
3631
  { 1629, 3,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList7, OperandInfo219, -1 ,nullptr },  // Inst #1629 = gBCLR
3632
  { 1630, 3,  0,  4,  3,  0|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList16, ImplicitList25, OperandInfo219, -1 ,nullptr },  // Inst #1630 = gBCLRL
3633
};
3634
3635
5.77k
static inline void InitPPCMCInstrInfo(MCInstrInfo *II) {
3636
5.77k
  II->InitMCInstrInfo(PPCInsts, NULL, NULL, 1631);
3637
5.77k
}
3638
3639
} // end llvm namespace 
3640
#endif // GET_INSTRINFO_MC_DESC
3641
3642
3643
#ifdef GET_INSTRINFO_HEADER
3644
#undef GET_INSTRINFO_HEADER
3645
namespace llvm_ks {
3646
struct PPCGenInstrInfo : public TargetInstrInfo {
3647
  explicit PPCGenInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1, int CatchRetOpcode = -1);
3648
  ~PPCGenInstrInfo() override {}
3649
};
3650
} // end llvm namespace 
3651
#endif // GET_INSTRINFO_HEADER
3652
3653
3654
#ifdef GET_INSTRINFO_OPERAND_ENUM
3655
#undef GET_INSTRINFO_OPERAND_ENUM
3656
namespace llvm_ks {
3657
namespace PPC {
3658
namespace OpName { 
3659
enum {
3660
OPERAND_LAST
3661
};
3662
} // end namespace OpName
3663
} // end namespace PPC
3664
} // end namespace llvm_ks
3665
#endif //GET_INSTRINFO_OPERAND_ENUM
3666
#ifdef GET_INSTRINFO_NAMED_OPS
3667
#undef GET_INSTRINFO_NAMED_OPS
3668
namespace llvm_ks {
3669
namespace PPC {
3670
LLVM_READONLY
3671
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {
3672
  return -1;
3673
}
3674
} // end namespace PPC
3675
} // end namespace llvm_ks
3676
#endif //GET_INSTRINFO_NAMED_OPS
3677
3678
#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM
3679
#undef GET_INSTRINFO_OPERAND_TYPES_ENUM
3680
namespace llvm_ks {
3681
namespace PPC {
3682
namespace OpTypes { 
3683
enum OperandType {
3684
  abscalltarget = 0,
3685
  abscondbrtarget = 1,
3686
  absdirectbrtarget = 2,
3687
  calltarget = 3,
3688
  condbrtarget = 4,
3689
  crbitm = 5,
3690
  directbrtarget = 6,
3691
  dispRI = 7,
3692
  dispRIX = 8,
3693
  dispSPE2 = 9,
3694
  dispSPE4 = 10,
3695
  dispSPE8 = 11,
3696
  f32imm = 12,
3697
  f64imm = 13,
3698
  i16imm = 14,
3699
  i1imm = 15,
3700
  i32imm = 16,
3701
  i64imm = 17,
3702
  i8imm = 18,
3703
  imm32SExt16 = 19,
3704
  imm64SExt16 = 20,
3705
  imm64ZExt32 = 21,
3706
  memr = 22,
3707
  memri = 23,
3708
  memrix = 24,
3709
  memrr = 25,
3710
  pred = 26,
3711
  ptr_rc_idx = 27,
3712
  ptr_rc_nor0 = 28,
3713
  s16imm = 29,
3714
  s16imm64 = 30,
3715
  s17imm = 31,
3716
  s17imm64 = 32,
3717
  s5imm = 33,
3718
  spe2dis = 34,
3719
  spe4dis = 35,
3720
  spe8dis = 36,
3721
  tlscall = 37,
3722
  tlscall32 = 38,
3723
  tlsgd = 39,
3724
  tlsgd32 = 40,
3725
  tlsreg = 41,
3726
  tlsreg32 = 42,
3727
  tocentry = 43,
3728
  tocentry32 = 44,
3729
  u10imm = 45,
3730
  u12imm = 46,
3731
  u16imm = 47,
3732
  u16imm64 = 48,
3733
  u1imm = 49,
3734
  u2imm = 50,
3735
  u3imm = 51,
3736
  u4imm = 52,
3737
  u5imm = 53,
3738
  u6imm = 54,
3739
  OPERAND_TYPE_LIST_END
3740
};
3741
} // end namespace OpTypes
3742
} // end namespace PPC
3743
} // end namespace llvm_ks
3744
#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM
3745
#ifdef GET_INSTRMAP_INFO
3746
#undef GET_INSTRMAP_INFO
3747
namespace llvm_ks {
3748
3749
namespace PPC {
3750
3751
enum IsVSXFMAAlt {
3752
  IsVSXFMAAlt_1
3753
};
3754
3755
enum RC {
3756
  RC_0,
3757
  RC_1
3758
};
3759
3760
// getAltVSXFMAOpcode
3761
LLVM_READONLY
3762
int getAltVSXFMAOpcode(uint16_t Opcode) {
3763
static const uint16_t getAltVSXFMAOpcodeTable[][2] = {
3764
  { PPC::XSMADDADP, PPC::XSMADDMDP },
3765
  { PPC::XSMADDASP, PPC::XSMADDMSP },
3766
  { PPC::XSMSUBADP, PPC::XSMSUBMDP },
3767
  { PPC::XSMSUBASP, PPC::XSMSUBMSP },
3768
  { PPC::XSNMADDADP, PPC::XSNMADDMDP },
3769
  { PPC::XSNMADDASP, PPC::XSNMADDMSP },
3770
  { PPC::XSNMSUBADP, PPC::XSNMSUBMDP },
3771
  { PPC::XSNMSUBASP, PPC::XSNMSUBMSP },
3772
  { PPC::XVMADDADP, PPC::XVMADDMDP },
3773
  { PPC::XVMADDASP, PPC::XVMADDMSP },
3774
  { PPC::XVMSUBADP, PPC::XVMSUBMDP },
3775
  { PPC::XVMSUBASP, PPC::XVMSUBMSP },
3776
  { PPC::XVNMADDADP, PPC::XVNMADDMDP },
3777
  { PPC::XVNMADDASP, PPC::XVNMADDMSP },
3778
  { PPC::XVNMSUBADP, PPC::XVNMSUBMDP },
3779
  { PPC::XVNMSUBASP, PPC::XVNMSUBMSP },
3780
}; // End of getAltVSXFMAOpcodeTable
3781
3782
  unsigned mid;
3783
  unsigned start = 0;
3784
  unsigned end = 16;
3785
  while (start < end) {
3786
    mid = start + (end - start)/2;
3787
    if (Opcode == getAltVSXFMAOpcodeTable[mid][0]) {
3788
      break;
3789
    }
3790
    if (Opcode < getAltVSXFMAOpcodeTable[mid][0])
3791
      end = mid;
3792
    else
3793
      start = mid + 1;
3794
  }
3795
  if (start == end)
3796
    return -1; // Instruction doesn't exist in this table.
3797
3798
  return getAltVSXFMAOpcodeTable[mid][1];
3799
}
3800
3801
// getNonRecordFormOpcode
3802
LLVM_READONLY
3803
int getNonRecordFormOpcode(uint16_t Opcode) {
3804
static const uint16_t getNonRecordFormOpcodeTable[][2] = {
3805
  { PPC::ADD4o, PPC::ADD4 },
3806
  { PPC::ADD8o, PPC::ADD8 },
3807
  { PPC::ADDC8o, PPC::ADDC8 },
3808
  { PPC::ADDCo, PPC::ADDC },
3809
  { PPC::ADDE8o, PPC::ADDE8 },
3810
  { PPC::ADDEo, PPC::ADDE },
3811
  { PPC::ADDICo, PPC::ADDIC },
3812
  { PPC::ADDME8o, PPC::ADDME8 },
3813
  { PPC::ADDMEo, PPC::ADDME },
3814
  { PPC::ADDZE8o, PPC::ADDZE8 },
3815
  { PPC::ADDZEo, PPC::ADDZE },
3816
  { PPC::AND8o, PPC::AND8 },
3817
  { PPC::ANDC8o, PPC::ANDC8 },
3818
  { PPC::ANDCo, PPC::ANDC },
3819
  { PPC::ANDo, PPC::AND },
3820
  { PPC::CNTLZDo, PPC::CNTLZD },
3821
  { PPC::CNTLZW8o, PPC::CNTLZW8 },
3822
  { PPC::CNTLZWo, PPC::CNTLZW },
3823
  { PPC::DIVDUo, PPC::DIVDU },
3824
  { PPC::DIVDo, PPC::DIVD },
3825
  { PPC::DIVWUo, PPC::DIVWU },
3826
  { PPC::DIVWo, PPC::DIVW },
3827
  { PPC::EQV8o, PPC::EQV8 },
3828
  { PPC::EQVo, PPC::EQV },
3829
  { PPC::EXTSB8o, PPC::EXTSB8 },
3830
  { PPC::EXTSBo, PPC::EXTSB },
3831
  { PPC::EXTSH8o, PPC::EXTSH8 },
3832
  { PPC::EXTSHo, PPC::EXTSH },
3833
  { PPC::EXTSW_32_64o, PPC::EXTSW_32_64 },
3834
  { PPC::EXTSWo, PPC::EXTSW },
3835
  { PPC::FABSDo, PPC::FABSD },
3836
  { PPC::FABSSo, PPC::FABSS },
3837
  { PPC::FADDSo, PPC::FADDS },
3838
  { PPC::FADDo, PPC::FADD },
3839
  { PPC::FCFIDSo, PPC::FCFIDS },
3840
  { PPC::FCFIDUSo, PPC::FCFIDUS },
3841
  { PPC::FCFIDUo, PPC::FCFIDU },
3842
  { PPC::FCFIDo, PPC::FCFID },
3843
  { PPC::FCPSGNDo, PPC::FCPSGND },
3844
  { PPC::FCPSGNSo, PPC::FCPSGNS },
3845
  { PPC::FCTIDUZo, PPC::FCTIDUZ },
3846
  { PPC::FCTIDZo, PPC::FCTIDZ },
3847
  { PPC::FCTIDo, PPC::FCTID },
3848
  { PPC::FCTIWUZo, PPC::FCTIWUZ },
3849
  { PPC::FCTIWZo, PPC::FCTIWZ },
3850
  { PPC::FCTIWo, PPC::FCTIW },
3851
  { PPC::FDIVSo, PPC::FDIVS },
3852
  { PPC::FDIVo, PPC::FDIV },
3853
  { PPC::FMADDSo, PPC::FMADDS },
3854
  { PPC::FMADDo, PPC::FMADD },
3855
  { PPC::FMRo, PPC::FMR },
3856
  { PPC::FMSUBSo, PPC::FMSUBS },
3857
  { PPC::FMSUBo, PPC::FMSUB },
3858
  { PPC::FMULSo, PPC::FMULS },
3859
  { PPC::FMULo, PPC::FMUL },
3860
  { PPC::FNABSDo, PPC::FNABSD },
3861
  { PPC::FNABSSo, PPC::FNABSS },
3862
  { PPC::FNEGDo, PPC::FNEGD },
3863
  { PPC::FNEGSo, PPC::FNEGS },
3864
  { PPC::FNMADDSo, PPC::FNMADDS },
3865
  { PPC::FNMADDo, PPC::FNMADD },
3866
  { PPC::FNMSUBSo, PPC::FNMSUBS },
3867
  { PPC::FNMSUBo, PPC::FNMSUB },
3868
  { PPC::FRESo, PPC::FRES },
3869
  { PPC::FREo, PPC::FRE },
3870
  { PPC::FRIMDo, PPC::FRIMD },
3871
  { PPC::FRIMSo, PPC::FRIMS },
3872
  { PPC::FRINDo, PPC::FRIND },
3873
  { PPC::FRINSo, PPC::FRINS },
3874
  { PPC::FRIPDo, PPC::FRIPD },
3875
  { PPC::FRIPSo, PPC::FRIPS },
3876
  { PPC::FRIZDo, PPC::FRIZD },
3877
  { PPC::FRIZSo, PPC::FRIZS },
3878
  { PPC::FRSPo, PPC::FRSP },
3879
  { PPC::FRSQRTESo, PPC::FRSQRTES },
3880
  { PPC::FRSQRTEo, PPC::FRSQRTE },
3881
  { PPC::FSELDo, PPC::FSELD },
3882
  { PPC::FSELSo, PPC::FSELS },
3883
  { PPC::FSQRTSo, PPC::FSQRTS },
3884
  { PPC::FSQRTo, PPC::FSQRT },
3885
  { PPC::FSUBSo, PPC::FSUBS },
3886
  { PPC::FSUBo, PPC::FSUB },
3887
  { PPC::MULHDUo, PPC::MULHDU },
3888
  { PPC::MULHDo, PPC::MULHD },
3889
  { PPC::MULHWUo, PPC::MULHWU },
3890
  { PPC::MULHWo, PPC::MULHW },
3891
  { PPC::MULLDo, PPC::MULLD },
3892
  { PPC::MULLWo, PPC::MULLW },
3893
  { PPC::NAND8o, PPC::NAND8 },
3894
  { PPC::NANDo, PPC::NAND },
3895
  { PPC::NEG8o, PPC::NEG8 },
3896
  { PPC::NEGo, PPC::NEG },
3897
  { PPC::NOR8o, PPC::NOR8 },
3898
  { PPC::NORo, PPC::NOR },
3899
  { PPC::OR8o, PPC::OR8 },
3900
  { PPC::ORC8o, PPC::ORC8 },
3901
  { PPC::ORCo, PPC::ORC },
3902
  { PPC::ORo, PPC::OR },
3903
  { PPC::RLDCLo, PPC::RLDCL },
3904
  { PPC::RLDCRo, PPC::RLDCR },
3905
  { PPC::RLDICLo, PPC::RLDICL },
3906
  { PPC::RLDICRo, PPC::RLDICR },
3907
  { PPC::RLDICo, PPC::RLDIC },
3908
  { PPC::RLDIMIo, PPC::RLDIMI },
3909
  { PPC::RLWIMI8o, PPC::RLWIMI8 },
3910
  { PPC::RLWIMIo, PPC::RLWIMI },
3911
  { PPC::RLWINM8o, PPC::RLWINM8 },
3912
  { PPC::RLWINMo, PPC::RLWINM },
3913
  { PPC::RLWNM8o, PPC::RLWNM8 },
3914
  { PPC::RLWNMo, PPC::RLWNM },
3915
  { PPC::SLDo, PPC::SLD },
3916
  { PPC::SLW8o, PPC::SLW8 },
3917
  { PPC::SLWo, PPC::SLW },
3918
  { PPC::SRADIo, PPC::SRADI },
3919
  { PPC::SRADo, PPC::SRAD },
3920
  { PPC::SRAWIo, PPC::SRAWI },
3921
  { PPC::SRAWo, PPC::SRAW },
3922
  { PPC::SRDo, PPC::SRD },
3923
  { PPC::SRW8o, PPC::SRW8 },
3924
  { PPC::SRWo, PPC::SRW },
3925
  { PPC::SUBF8o, PPC::SUBF8 },
3926
  { PPC::SUBFC8o, PPC::SUBFC8 },
3927
  { PPC::SUBFCo, PPC::SUBFC },
3928
  { PPC::SUBFE8o, PPC::SUBFE8 },
3929
  { PPC::SUBFEo, PPC::SUBFE },
3930
  { PPC::SUBFME8o, PPC::SUBFME8 },
3931
  { PPC::SUBFMEo, PPC::SUBFME },
3932
  { PPC::SUBFZE8o, PPC::SUBFZE8 },
3933
  { PPC::SUBFZEo, PPC::SUBFZE },
3934
  { PPC::SUBFo, PPC::SUBF },
3935
  { PPC::XOR8o, PPC::XOR8 },
3936
  { PPC::XORo, PPC::XOR },
3937
}; // End of getNonRecordFormOpcodeTable
3938
3939
  unsigned mid;
3940
  unsigned start = 0;
3941
  unsigned end = 132;
3942
  while (start < end) {
3943
    mid = start + (end - start)/2;
3944
    if (Opcode == getNonRecordFormOpcodeTable[mid][0]) {
3945
      break;
3946
    }
3947
    if (Opcode < getNonRecordFormOpcodeTable[mid][0])
3948
      end = mid;
3949
    else
3950
      start = mid + 1;
3951
  }
3952
  if (start == end)
3953
    return -1; // Instruction doesn't exist in this table.
3954
3955
  return getNonRecordFormOpcodeTable[mid][1];
3956
}
3957
3958
// getRecordFormOpcode
3959
LLVM_READONLY
3960
int getRecordFormOpcode(uint16_t Opcode) {
3961
static const uint16_t getRecordFormOpcodeTable[][2] = {
3962
  { PPC::ADD4, PPC::ADD4o },
3963
  { PPC::ADD8, PPC::ADD8o },
3964
  { PPC::ADDC, PPC::ADDCo },
3965
  { PPC::ADDC8, PPC::ADDC8o },
3966
  { PPC::ADDE, PPC::ADDEo },
3967
  { PPC::ADDE8, PPC::ADDE8o },
3968
  { PPC::ADDIC, PPC::ADDICo },
3969
  { PPC::ADDME, PPC::ADDMEo },
3970
  { PPC::ADDME8, PPC::ADDME8o },
3971
  { PPC::ADDZE, PPC::ADDZEo },
3972
  { PPC::ADDZE8, PPC::ADDZE8o },
3973
  { PPC::AND, PPC::ANDo },
3974
  { PPC::AND8, PPC::AND8o },
3975
  { PPC::ANDC, PPC::ANDCo },
3976
  { PPC::ANDC8, PPC::ANDC8o },
3977
  { PPC::CNTLZD, PPC::CNTLZDo },
3978
  { PPC::CNTLZW, PPC::CNTLZWo },
3979
  { PPC::CNTLZW8, PPC::CNTLZW8o },
3980
  { PPC::DIVD, PPC::DIVDo },
3981
  { PPC::DIVDU, PPC::DIVDUo },
3982
  { PPC::DIVW, PPC::DIVWo },
3983
  { PPC::DIVWU, PPC::DIVWUo },
3984
  { PPC::EQV, PPC::EQVo },
3985
  { PPC::EQV8, PPC::EQV8o },
3986
  { PPC::EXTSB, PPC::EXTSBo },
3987
  { PPC::EXTSB8, PPC::EXTSB8o },
3988
  { PPC::EXTSH, PPC::EXTSHo },
3989
  { PPC::EXTSH8, PPC::EXTSH8o },
3990
  { PPC::EXTSW, PPC::EXTSWo },
3991
  { PPC::EXTSW_32_64, PPC::EXTSW_32_64o },
3992
  { PPC::FABSD, PPC::FABSDo },
3993
  { PPC::FABSS, PPC::FABSSo },
3994
  { PPC::FADD, PPC::FADDo },
3995
  { PPC::FADDS, PPC::FADDSo },
3996
  { PPC::FCFID, PPC::FCFIDo },
3997
  { PPC::FCFIDS, PPC::FCFIDSo },
3998
  { PPC::FCFIDU, PPC::FCFIDUo },
3999
  { PPC::FCFIDUS, PPC::FCFIDUSo },
4000
  { PPC::FCPSGND, PPC::FCPSGNDo },
4001
  { PPC::FCPSGNS, PPC::FCPSGNSo },
4002
  { PPC::FCTID, PPC::FCTIDo },
4003
  { PPC::FCTIDUZ, PPC::FCTIDUZo },
4004
  { PPC::FCTIDZ, PPC::FCTIDZo },
4005
  { PPC::FCTIW, PPC::FCTIWo },
4006
  { PPC::FCTIWUZ, PPC::FCTIWUZo },
4007
  { PPC::FCTIWZ, PPC::FCTIWZo },
4008
  { PPC::FDIV, PPC::FDIVo },
4009
  { PPC::FDIVS, PPC::FDIVSo },
4010
  { PPC::FMADD, PPC::FMADDo },
4011
  { PPC::FMADDS, PPC::FMADDSo },
4012
  { PPC::FMR, PPC::FMRo },
4013
  { PPC::FMSUB, PPC::FMSUBo },
4014
  { PPC::FMSUBS, PPC::FMSUBSo },
4015
  { PPC::FMUL, PPC::FMULo },
4016
  { PPC::FMULS, PPC::FMULSo },
4017
  { PPC::FNABSD, PPC::FNABSDo },
4018
  { PPC::FNABSS, PPC::FNABSSo },
4019
  { PPC::FNEGD, PPC::FNEGDo },
4020
  { PPC::FNEGS, PPC::FNEGSo },
4021
  { PPC::FNMADD, PPC::FNMADDo },
4022
  { PPC::FNMADDS, PPC::FNMADDSo },
4023
  { PPC::FNMSUB, PPC::FNMSUBo },
4024
  { PPC::FNMSUBS, PPC::FNMSUBSo },
4025
  { PPC::FRE, PPC::FREo },
4026
  { PPC::FRES, PPC::FRESo },
4027
  { PPC::FRIMD, PPC::FRIMDo },
4028
  { PPC::FRIMS, PPC::FRIMSo },
4029
  { PPC::FRIND, PPC::FRINDo },
4030
  { PPC::FRINS, PPC::FRINSo },
4031
  { PPC::FRIPD, PPC::FRIPDo },
4032
  { PPC::FRIPS, PPC::FRIPSo },
4033
  { PPC::FRIZD, PPC::FRIZDo },
4034
  { PPC::FRIZS, PPC::FRIZSo },
4035
  { PPC::FRSP, PPC::FRSPo },
4036
  { PPC::FRSQRTE, PPC::FRSQRTEo },
4037
  { PPC::FRSQRTES, PPC::FRSQRTESo },
4038
  { PPC::FSELD, PPC::FSELDo },
4039
  { PPC::FSELS, PPC::FSELSo },
4040
  { PPC::FSQRT, PPC::FSQRTo },
4041
  { PPC::FSQRTS, PPC::FSQRTSo },
4042
  { PPC::FSUB, PPC::FSUBo },
4043
  { PPC::FSUBS, PPC::FSUBSo },
4044
  { PPC::MULHD, PPC::MULHDo },
4045
  { PPC::MULHDU, PPC::MULHDUo },
4046
  { PPC::MULHW, PPC::MULHWo },
4047
  { PPC::MULHWU, PPC::MULHWUo },
4048
  { PPC::MULLD, PPC::MULLDo },
4049
  { PPC::MULLW, PPC::MULLWo },
4050
  { PPC::NAND, PPC::NANDo },
4051
  { PPC::NAND8, PPC::NAND8o },
4052
  { PPC::NEG, PPC::NEGo },
4053
  { PPC::NEG8, PPC::NEG8o },
4054
  { PPC::NOR, PPC::NORo },
4055
  { PPC::NOR8, PPC::NOR8o },
4056
  { PPC::OR, PPC::ORo },
4057
  { PPC::OR8, PPC::OR8o },
4058
  { PPC::ORC, PPC::ORCo },
4059
  { PPC::ORC8, PPC::ORC8o },
4060
  { PPC::RLDCL, PPC::RLDCLo },
4061
  { PPC::RLDCR, PPC::RLDCRo },
4062
  { PPC::RLDIC, PPC::RLDICo },
4063
  { PPC::RLDICL, PPC::RLDICLo },
4064
  { PPC::RLDICR, PPC::RLDICRo },
4065
  { PPC::RLDIMI, PPC::RLDIMIo },
4066
  { PPC::RLWIMI, PPC::RLWIMIo },
4067
  { PPC::RLWIMI8, PPC::RLWIMI8o },
4068
  { PPC::RLWINM, PPC::RLWINMo },
4069
  { PPC::RLWINM8, PPC::RLWINM8o },
4070
  { PPC::RLWNM, PPC::RLWNMo },
4071
  { PPC::RLWNM8, PPC::RLWNM8o },
4072
  { PPC::SLD, PPC::SLDo },
4073
  { PPC::SLW, PPC::SLWo },
4074
  { PPC::SLW8, PPC::SLW8o },
4075
  { PPC::SRAD, PPC::SRADo },
4076
  { PPC::SRADI, PPC::SRADIo },
4077
  { PPC::SRAW, PPC::SRAWo },
4078
  { PPC::SRAWI, PPC::SRAWIo },
4079
  { PPC::SRD, PPC::SRDo },
4080
  { PPC::SRW, PPC::SRWo },
4081
  { PPC::SRW8, PPC::SRW8o },
4082
  { PPC::SUBF, PPC::SUBFo },
4083
  { PPC::SUBF8, PPC::SUBF8o },
4084
  { PPC::SUBFC, PPC::SUBFCo },
4085
  { PPC::SUBFC8, PPC::SUBFC8o },
4086
  { PPC::SUBFE, PPC::SUBFEo },
4087
  { PPC::SUBFE8, PPC::SUBFE8o },
4088
  { PPC::SUBFME, PPC::SUBFMEo },
4089
  { PPC::SUBFME8, PPC::SUBFME8o },
4090
  { PPC::SUBFZE, PPC::SUBFZEo },
4091
  { PPC::SUBFZE8, PPC::SUBFZE8o },
4092
  { PPC::XOR, PPC::XORo },
4093
  { PPC::XOR8, PPC::XOR8o },
4094
}; // End of getRecordFormOpcodeTable
4095
4096
  unsigned mid;
4097
  unsigned start = 0;
4098
  unsigned end = 132;
4099
  while (start < end) {
4100
    mid = start + (end - start)/2;
4101
    if (Opcode == getRecordFormOpcodeTable[mid][0]) {
4102
      break;
4103
    }
4104
    if (Opcode < getRecordFormOpcodeTable[mid][0])
4105
      end = mid;
4106
    else
4107
      start = mid + 1;
4108
  }
4109
  if (start == end)
4110
    return -1; // Instruction doesn't exist in this table.
4111
4112
  return getRecordFormOpcodeTable[mid][1];
4113
}
4114
4115
} // End PPC namespace
4116
} // End llvm namespace
4117
#endif // GET_INSTRMAP_INFO
4118