/src/keystone/llvm/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc
Line | Count | Source |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t AArch64MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 1.59k | const MCSubtargetInfo &STI) const { |
12 | 1.59k | static const uint64_t InstBits[] = { |
13 | 1.59k | UINT64_C(0), |
14 | 1.59k | UINT64_C(0), |
15 | 1.59k | UINT64_C(0), |
16 | 1.59k | UINT64_C(0), |
17 | 1.59k | UINT64_C(0), |
18 | 1.59k | UINT64_C(0), |
19 | 1.59k | UINT64_C(0), |
20 | 1.59k | UINT64_C(0), |
21 | 1.59k | UINT64_C(0), |
22 | 1.59k | UINT64_C(0), |
23 | 1.59k | UINT64_C(0), |
24 | 1.59k | UINT64_C(0), |
25 | 1.59k | UINT64_C(0), |
26 | 1.59k | UINT64_C(0), |
27 | 1.59k | UINT64_C(0), |
28 | 1.59k | UINT64_C(0), |
29 | 1.59k | UINT64_C(0), |
30 | 1.59k | UINT64_C(0), |
31 | 1.59k | UINT64_C(0), |
32 | 1.59k | UINT64_C(0), |
33 | 1.59k | UINT64_C(0), |
34 | 1.59k | UINT64_C(0), |
35 | 1.59k | UINT64_C(0), |
36 | 1.59k | UINT64_C(0), |
37 | 1.59k | UINT64_C(1310767104), // ABSv16i8 |
38 | 1.59k | UINT64_C(1591785472), // ABSv1i64 |
39 | 1.59k | UINT64_C(245413888), // ABSv2i32 |
40 | 1.59k | UINT64_C(1323350016), // ABSv2i64 |
41 | 1.59k | UINT64_C(241219584), // ABSv4i16 |
42 | 1.59k | UINT64_C(1319155712), // ABSv4i32 |
43 | 1.59k | UINT64_C(1314961408), // ABSv8i16 |
44 | 1.59k | UINT64_C(237025280), // ABSv8i8 |
45 | 1.59k | UINT64_C(973078528), // ADCSWr |
46 | 1.59k | UINT64_C(3120562176), // ADCSXr |
47 | 1.59k | UINT64_C(436207616), // ADCWr |
48 | 1.59k | UINT64_C(2583691264), // ADCXr |
49 | 1.59k | UINT64_C(245383168), // ADDHNv2i64_v2i32 |
50 | 1.59k | UINT64_C(1319124992), // ADDHNv2i64_v4i32 |
51 | 1.59k | UINT64_C(241188864), // ADDHNv4i32_v4i16 |
52 | 1.59k | UINT64_C(1314930688), // ADDHNv4i32_v8i16 |
53 | 1.59k | UINT64_C(1310736384), // ADDHNv8i16_v16i8 |
54 | 1.59k | UINT64_C(236994560), // ADDHNv8i16_v8i8 |
55 | 1.59k | UINT64_C(1310768128), // ADDPv16i8 |
56 | 1.59k | UINT64_C(245414912), // ADDPv2i32 |
57 | 1.59k | UINT64_C(1323351040), // ADDPv2i64 |
58 | 1.59k | UINT64_C(1592899584), // ADDPv2i64p |
59 | 1.59k | UINT64_C(241220608), // ADDPv4i16 |
60 | 1.59k | UINT64_C(1319156736), // ADDPv4i32 |
61 | 1.59k | UINT64_C(1314962432), // ADDPv8i16 |
62 | 1.59k | UINT64_C(237026304), // ADDPv8i8 |
63 | 1.59k | UINT64_C(822083584), // ADDSWri |
64 | 1.59k | UINT64_C(0), // ADDSWrr |
65 | 1.59k | UINT64_C(721420288), // ADDSWrs |
66 | 1.59k | UINT64_C(723517440), // ADDSWrx |
67 | 1.59k | UINT64_C(2969567232), // ADDSXri |
68 | 1.59k | UINT64_C(0), // ADDSXrr |
69 | 1.59k | UINT64_C(2868903936), // ADDSXrs |
70 | 1.59k | UINT64_C(2871001088), // ADDSXrx |
71 | 1.59k | UINT64_C(2871025664), // ADDSXrx64 |
72 | 1.59k | UINT64_C(1311881216), // ADDVv16i8v |
73 | 1.59k | UINT64_C(242333696), // ADDVv4i16v |
74 | 1.59k | UINT64_C(1320269824), // ADDVv4i32v |
75 | 1.59k | UINT64_C(1316075520), // ADDVv8i16v |
76 | 1.59k | UINT64_C(238139392), // ADDVv8i8v |
77 | 1.59k | UINT64_C(285212672), // ADDWri |
78 | 1.59k | UINT64_C(0), // ADDWrr |
79 | 1.59k | UINT64_C(184549376), // ADDWrs |
80 | 1.59k | UINT64_C(186646528), // ADDWrx |
81 | 1.59k | UINT64_C(2432696320), // ADDXri |
82 | 1.59k | UINT64_C(0), // ADDXrr |
83 | 1.59k | UINT64_C(2332033024), // ADDXrs |
84 | 1.59k | UINT64_C(2334130176), // ADDXrx |
85 | 1.59k | UINT64_C(2334154752), // ADDXrx64 |
86 | 1.59k | UINT64_C(1310753792), // ADDv16i8 |
87 | 1.59k | UINT64_C(1591772160), // ADDv1i64 |
88 | 1.59k | UINT64_C(245400576), // ADDv2i32 |
89 | 1.59k | UINT64_C(1323336704), // ADDv2i64 |
90 | 1.59k | UINT64_C(241206272), // ADDv4i16 |
91 | 1.59k | UINT64_C(1319142400), // ADDv4i32 |
92 | 1.59k | UINT64_C(1314948096), // ADDv8i16 |
93 | 1.59k | UINT64_C(237011968), // ADDv8i8 |
94 | 1.59k | UINT64_C(0), // ADJCALLSTACKDOWN |
95 | 1.59k | UINT64_C(0), // ADJCALLSTACKUP |
96 | 1.59k | UINT64_C(268435456), // ADR |
97 | 1.59k | UINT64_C(2415919104), // ADRP |
98 | 1.59k | UINT64_C(1311266816), // AESDrr |
99 | 1.59k | UINT64_C(1311262720), // AESErr |
100 | 1.59k | UINT64_C(1311275008), // AESIMCrr |
101 | 1.59k | UINT64_C(1311270912), // AESMCrr |
102 | 1.59k | UINT64_C(1912602624), // ANDSWri |
103 | 1.59k | UINT64_C(0), // ANDSWrr |
104 | 1.59k | UINT64_C(1778384896), // ANDSWrs |
105 | 1.59k | UINT64_C(4060086272), // ANDSXri |
106 | 1.59k | UINT64_C(0), // ANDSXrr |
107 | 1.59k | UINT64_C(3925868544), // ANDSXrs |
108 | 1.59k | UINT64_C(301989888), // ANDWri |
109 | 1.59k | UINT64_C(0), // ANDWrr |
110 | 1.59k | UINT64_C(167772160), // ANDWrs |
111 | 1.59k | UINT64_C(2449473536), // ANDXri |
112 | 1.59k | UINT64_C(0), // ANDXrr |
113 | 1.59k | UINT64_C(2315255808), // ANDXrs |
114 | 1.59k | UINT64_C(1310727168), // ANDv16i8 |
115 | 1.59k | UINT64_C(236985344), // ANDv8i8 |
116 | 1.59k | UINT64_C(448800768), // ASRVWr |
117 | 1.59k | UINT64_C(2596284416), // ASRVXr |
118 | 1.59k | UINT64_C(335544320), // B |
119 | 1.59k | UINT64_C(855638016), // BFMWri |
120 | 1.59k | UINT64_C(3007315968), // BFMXri |
121 | 1.59k | UINT64_C(0), // BICSWrr |
122 | 1.59k | UINT64_C(1780482048), // BICSWrs |
123 | 1.59k | UINT64_C(0), // BICSXrr |
124 | 1.59k | UINT64_C(3927965696), // BICSXrs |
125 | 1.59k | UINT64_C(0), // BICWrr |
126 | 1.59k | UINT64_C(169869312), // BICWrs |
127 | 1.59k | UINT64_C(0), // BICXrr |
128 | 1.59k | UINT64_C(2317352960), // BICXrs |
129 | 1.59k | UINT64_C(1314921472), // BICv16i8 |
130 | 1.59k | UINT64_C(788534272), // BICv2i32 |
131 | 1.59k | UINT64_C(788567040), // BICv4i16 |
132 | 1.59k | UINT64_C(1862276096), // BICv4i32 |
133 | 1.59k | UINT64_C(1862308864), // BICv8i16 |
134 | 1.59k | UINT64_C(241179648), // BICv8i8 |
135 | 1.59k | UINT64_C(1860180992), // BIFv16i8 |
136 | 1.59k | UINT64_C(786439168), // BIFv8i8 |
137 | 1.59k | UINT64_C(1855986688), // BITv16i8 |
138 | 1.59k | UINT64_C(782244864), // BITv8i8 |
139 | 1.59k | UINT64_C(2483027968), // BL |
140 | 1.59k | UINT64_C(3594452992), // BLR |
141 | 1.59k | UINT64_C(3592355840), // BR |
142 | 1.59k | UINT64_C(3558866944), // BRK |
143 | 1.59k | UINT64_C(1851792384), // BSLv16i8 |
144 | 1.59k | UINT64_C(778050560), // BSLv8i8 |
145 | 1.59k | UINT64_C(1409286144), // Bcc |
146 | 1.59k | UINT64_C(148962304), // CASALb |
147 | 1.59k | UINT64_C(3370187776), // CASALd |
148 | 1.59k | UINT64_C(1222704128), // CASALh |
149 | 1.59k | UINT64_C(2296445952), // CASALs |
150 | 1.59k | UINT64_C(148929536), // CASAb |
151 | 1.59k | UINT64_C(3370155008), // CASAd |
152 | 1.59k | UINT64_C(1222671360), // CASAh |
153 | 1.59k | UINT64_C(2296413184), // CASAs |
154 | 1.59k | UINT64_C(144768000), // CASLb |
155 | 1.59k | UINT64_C(3365993472), // CASLd |
156 | 1.59k | UINT64_C(1218509824), // CASLh |
157 | 1.59k | UINT64_C(2292251648), // CASLs |
158 | 1.59k | UINT64_C(1214315520), // CASPALd |
159 | 1.59k | UINT64_C(140573696), // CASPALs |
160 | 1.59k | UINT64_C(1214282752), // CASPAd |
161 | 1.59k | UINT64_C(140540928), // CASPAs |
162 | 1.59k | UINT64_C(1210121216), // CASPLd |
163 | 1.59k | UINT64_C(136379392), // CASPLs |
164 | 1.59k | UINT64_C(1210088448), // CASPd |
165 | 1.59k | UINT64_C(136346624), // CASPs |
166 | 1.59k | UINT64_C(144735232), // CASb |
167 | 1.59k | UINT64_C(3365960704), // CASd |
168 | 1.59k | UINT64_C(1218477056), // CASh |
169 | 1.59k | UINT64_C(2292218880), // CASs |
170 | 1.59k | UINT64_C(889192448), // CBNZW |
171 | 1.59k | UINT64_C(3036676096), // CBNZX |
172 | 1.59k | UINT64_C(872415232), // CBZW |
173 | 1.59k | UINT64_C(3019898880), // CBZX |
174 | 1.59k | UINT64_C(977274880), // CCMNWi |
175 | 1.59k | UINT64_C(977272832), // CCMNWr |
176 | 1.59k | UINT64_C(3124758528), // CCMNXi |
177 | 1.59k | UINT64_C(3124756480), // CCMNXr |
178 | 1.59k | UINT64_C(2051016704), // CCMPWi |
179 | 1.59k | UINT64_C(2051014656), // CCMPWr |
180 | 1.59k | UINT64_C(4198500352), // CCMPXi |
181 | 1.59k | UINT64_C(4198498304), // CCMPXr |
182 | 1.59k | UINT64_C(3573755999), // CLREX |
183 | 1.59k | UINT64_C(1522537472), // CLSWr |
184 | 1.59k | UINT64_C(3670021120), // CLSXr |
185 | 1.59k | UINT64_C(1310738432), // CLSv16i8 |
186 | 1.59k | UINT64_C(245385216), // CLSv2i32 |
187 | 1.59k | UINT64_C(241190912), // CLSv4i16 |
188 | 1.59k | UINT64_C(1319127040), // CLSv4i32 |
189 | 1.59k | UINT64_C(1314932736), // CLSv8i16 |
190 | 1.59k | UINT64_C(236996608), // CLSv8i8 |
191 | 1.59k | UINT64_C(1522536448), // CLZWr |
192 | 1.59k | UINT64_C(3670020096), // CLZXr |
193 | 1.59k | UINT64_C(1847609344), // CLZv16i8 |
194 | 1.59k | UINT64_C(782256128), // CLZv2i32 |
195 | 1.59k | UINT64_C(778061824), // CLZv4i16 |
196 | 1.59k | UINT64_C(1855997952), // CLZv4i32 |
197 | 1.59k | UINT64_C(1851803648), // CLZv8i16 |
198 | 1.59k | UINT64_C(773867520), // CLZv8i8 |
199 | 1.59k | UINT64_C(1847626752), // CMEQv16i8 |
200 | 1.59k | UINT64_C(1310758912), // CMEQv16i8rz |
201 | 1.59k | UINT64_C(2128645120), // CMEQv1i64 |
202 | 1.59k | UINT64_C(1591777280), // CMEQv1i64rz |
203 | 1.59k | UINT64_C(782273536), // CMEQv2i32 |
204 | 1.59k | UINT64_C(245405696), // CMEQv2i32rz |
205 | 1.59k | UINT64_C(1860209664), // CMEQv2i64 |
206 | 1.59k | UINT64_C(1323341824), // CMEQv2i64rz |
207 | 1.59k | UINT64_C(778079232), // CMEQv4i16 |
208 | 1.59k | UINT64_C(241211392), // CMEQv4i16rz |
209 | 1.59k | UINT64_C(1856015360), // CMEQv4i32 |
210 | 1.59k | UINT64_C(1319147520), // CMEQv4i32rz |
211 | 1.59k | UINT64_C(1851821056), // CMEQv8i16 |
212 | 1.59k | UINT64_C(1314953216), // CMEQv8i16rz |
213 | 1.59k | UINT64_C(773884928), // CMEQv8i8 |
214 | 1.59k | UINT64_C(237017088), // CMEQv8i8rz |
215 | 1.59k | UINT64_C(1310735360), // CMGEv16i8 |
216 | 1.59k | UINT64_C(1847625728), // CMGEv16i8rz |
217 | 1.59k | UINT64_C(1591753728), // CMGEv1i64 |
218 | 1.59k | UINT64_C(2128644096), // CMGEv1i64rz |
219 | 1.59k | UINT64_C(245382144), // CMGEv2i32 |
220 | 1.59k | UINT64_C(782272512), // CMGEv2i32rz |
221 | 1.59k | UINT64_C(1323318272), // CMGEv2i64 |
222 | 1.59k | UINT64_C(1860208640), // CMGEv2i64rz |
223 | 1.59k | UINT64_C(241187840), // CMGEv4i16 |
224 | 1.59k | UINT64_C(778078208), // CMGEv4i16rz |
225 | 1.59k | UINT64_C(1319123968), // CMGEv4i32 |
226 | 1.59k | UINT64_C(1856014336), // CMGEv4i32rz |
227 | 1.59k | UINT64_C(1314929664), // CMGEv8i16 |
228 | 1.59k | UINT64_C(1851820032), // CMGEv8i16rz |
229 | 1.59k | UINT64_C(236993536), // CMGEv8i8 |
230 | 1.59k | UINT64_C(773883904), // CMGEv8i8rz |
231 | 1.59k | UINT64_C(1310733312), // CMGTv16i8 |
232 | 1.59k | UINT64_C(1310754816), // CMGTv16i8rz |
233 | 1.59k | UINT64_C(1591751680), // CMGTv1i64 |
234 | 1.59k | UINT64_C(1591773184), // CMGTv1i64rz |
235 | 1.59k | UINT64_C(245380096), // CMGTv2i32 |
236 | 1.59k | UINT64_C(245401600), // CMGTv2i32rz |
237 | 1.59k | UINT64_C(1323316224), // CMGTv2i64 |
238 | 1.59k | UINT64_C(1323337728), // CMGTv2i64rz |
239 | 1.59k | UINT64_C(241185792), // CMGTv4i16 |
240 | 1.59k | UINT64_C(241207296), // CMGTv4i16rz |
241 | 1.59k | UINT64_C(1319121920), // CMGTv4i32 |
242 | 1.59k | UINT64_C(1319143424), // CMGTv4i32rz |
243 | 1.59k | UINT64_C(1314927616), // CMGTv8i16 |
244 | 1.59k | UINT64_C(1314949120), // CMGTv8i16rz |
245 | 1.59k | UINT64_C(236991488), // CMGTv8i8 |
246 | 1.59k | UINT64_C(237012992), // CMGTv8i8rz |
247 | 1.59k | UINT64_C(1847604224), // CMHIv16i8 |
248 | 1.59k | UINT64_C(2128622592), // CMHIv1i64 |
249 | 1.59k | UINT64_C(782251008), // CMHIv2i32 |
250 | 1.59k | UINT64_C(1860187136), // CMHIv2i64 |
251 | 1.59k | UINT64_C(778056704), // CMHIv4i16 |
252 | 1.59k | UINT64_C(1855992832), // CMHIv4i32 |
253 | 1.59k | UINT64_C(1851798528), // CMHIv8i16 |
254 | 1.59k | UINT64_C(773862400), // CMHIv8i8 |
255 | 1.59k | UINT64_C(1847606272), // CMHSv16i8 |
256 | 1.59k | UINT64_C(2128624640), // CMHSv1i64 |
257 | 1.59k | UINT64_C(782253056), // CMHSv2i32 |
258 | 1.59k | UINT64_C(1860189184), // CMHSv2i64 |
259 | 1.59k | UINT64_C(778058752), // CMHSv4i16 |
260 | 1.59k | UINT64_C(1855994880), // CMHSv4i32 |
261 | 1.59k | UINT64_C(1851800576), // CMHSv8i16 |
262 | 1.59k | UINT64_C(773864448), // CMHSv8i8 |
263 | 1.59k | UINT64_C(1847629824), // CMLEv16i8rz |
264 | 1.59k | UINT64_C(2128648192), // CMLEv1i64rz |
265 | 1.59k | UINT64_C(782276608), // CMLEv2i32rz |
266 | 1.59k | UINT64_C(1860212736), // CMLEv2i64rz |
267 | 1.59k | UINT64_C(778082304), // CMLEv4i16rz |
268 | 1.59k | UINT64_C(1856018432), // CMLEv4i32rz |
269 | 1.59k | UINT64_C(1851824128), // CMLEv8i16rz |
270 | 1.59k | UINT64_C(773888000), // CMLEv8i8rz |
271 | 1.59k | UINT64_C(1310763008), // CMLTv16i8rz |
272 | 1.59k | UINT64_C(1591781376), // CMLTv1i64rz |
273 | 1.59k | UINT64_C(245409792), // CMLTv2i32rz |
274 | 1.59k | UINT64_C(1323345920), // CMLTv2i64rz |
275 | 1.59k | UINT64_C(241215488), // CMLTv4i16rz |
276 | 1.59k | UINT64_C(1319151616), // CMLTv4i32rz |
277 | 1.59k | UINT64_C(1314957312), // CMLTv8i16rz |
278 | 1.59k | UINT64_C(237021184), // CMLTv8i8rz |
279 | 1.59k | UINT64_C(1310755840), // CMTSTv16i8 |
280 | 1.59k | UINT64_C(1591774208), // CMTSTv1i64 |
281 | 1.59k | UINT64_C(245402624), // CMTSTv2i32 |
282 | 1.59k | UINT64_C(1323338752), // CMTSTv2i64 |
283 | 1.59k | UINT64_C(241208320), // CMTSTv4i16 |
284 | 1.59k | UINT64_C(1319144448), // CMTSTv4i32 |
285 | 1.59k | UINT64_C(1314950144), // CMTSTv8i16 |
286 | 1.59k | UINT64_C(237014016), // CMTSTv8i8 |
287 | 1.59k | UINT64_C(1310742528), // CNTv16i8 |
288 | 1.59k | UINT64_C(237000704), // CNTv8i8 |
289 | 1.59k | UINT64_C(1577190400), // CPYi16 |
290 | 1.59k | UINT64_C(1577321472), // CPYi32 |
291 | 1.59k | UINT64_C(1577583616), // CPYi64 |
292 | 1.59k | UINT64_C(1577124864), // CPYi8 |
293 | 1.59k | UINT64_C(448806912), // CRC32Brr |
294 | 1.59k | UINT64_C(448811008), // CRC32CBrr |
295 | 1.59k | UINT64_C(448812032), // CRC32CHrr |
296 | 1.59k | UINT64_C(448813056), // CRC32CWrr |
297 | 1.59k | UINT64_C(2596297728), // CRC32CXrr |
298 | 1.59k | UINT64_C(448807936), // CRC32Hrr |
299 | 1.59k | UINT64_C(448808960), // CRC32Wrr |
300 | 1.59k | UINT64_C(2596293632), // CRC32Xrr |
301 | 1.59k | UINT64_C(444596224), // CSELWr |
302 | 1.59k | UINT64_C(2592079872), // CSELXr |
303 | 1.59k | UINT64_C(444597248), // CSINCWr |
304 | 1.59k | UINT64_C(2592080896), // CSINCXr |
305 | 1.59k | UINT64_C(1518338048), // CSINVWr |
306 | 1.59k | UINT64_C(3665821696), // CSINVXr |
307 | 1.59k | UINT64_C(1518339072), // CSNEGWr |
308 | 1.59k | UINT64_C(3665822720), // CSNEGXr |
309 | 1.59k | UINT64_C(3567255553), // DCPS1 |
310 | 1.59k | UINT64_C(3567255554), // DCPS2 |
311 | 1.59k | UINT64_C(3567255555), // DCPS3 |
312 | 1.59k | UINT64_C(3573756095), // DMB |
313 | 1.59k | UINT64_C(3602842592), // DRPS |
314 | 1.59k | UINT64_C(3573756063), // DSB |
315 | 1.59k | UINT64_C(1308691456), // DUPv16i8gpr |
316 | 1.59k | UINT64_C(1308689408), // DUPv16i8lane |
317 | 1.59k | UINT64_C(235146240), // DUPv2i32gpr |
318 | 1.59k | UINT64_C(235144192), // DUPv2i32lane |
319 | 1.59k | UINT64_C(1309150208), // DUPv2i64gpr |
320 | 1.59k | UINT64_C(1309148160), // DUPv2i64lane |
321 | 1.59k | UINT64_C(235015168), // DUPv4i16gpr |
322 | 1.59k | UINT64_C(235013120), // DUPv4i16lane |
323 | 1.59k | UINT64_C(1308888064), // DUPv4i32gpr |
324 | 1.59k | UINT64_C(1308886016), // DUPv4i32lane |
325 | 1.59k | UINT64_C(1308756992), // DUPv8i16gpr |
326 | 1.59k | UINT64_C(1308754944), // DUPv8i16lane |
327 | 1.59k | UINT64_C(234949632), // DUPv8i8gpr |
328 | 1.59k | UINT64_C(234947584), // DUPv8i8lane |
329 | 1.59k | UINT64_C(0), // EONWrr |
330 | 1.59k | UINT64_C(1243611136), // EONWrs |
331 | 1.59k | UINT64_C(0), // EONXrr |
332 | 1.59k | UINT64_C(3391094784), // EONXrs |
333 | 1.59k | UINT64_C(1375731712), // EORWri |
334 | 1.59k | UINT64_C(0), // EORWrr |
335 | 1.59k | UINT64_C(1241513984), // EORWrs |
336 | 1.59k | UINT64_C(3523215360), // EORXri |
337 | 1.59k | UINT64_C(0), // EORXrr |
338 | 1.59k | UINT64_C(3388997632), // EORXrs |
339 | 1.59k | UINT64_C(1847598080), // EORv16i8 |
340 | 1.59k | UINT64_C(773856256), // EORv8i8 |
341 | 1.59k | UINT64_C(3600745440), // ERET |
342 | 1.59k | UINT64_C(327155712), // EXTRWrri |
343 | 1.59k | UINT64_C(2478833664), // EXTRXrri |
344 | 1.59k | UINT64_C(1845493760), // EXTv16i8 |
345 | 1.59k | UINT64_C(771751936), // EXTv8i8 |
346 | 1.59k | UINT64_C(0), // F128CSEL |
347 | 1.59k | UINT64_C(2126517248), // FABD16 |
348 | 1.59k | UINT64_C(2124469248), // FABD32 |
349 | 1.59k | UINT64_C(2128663552), // FABD64 |
350 | 1.59k | UINT64_C(782291968), // FABDv2f32 |
351 | 1.59k | UINT64_C(1860228096), // FABDv2f64 |
352 | 1.59k | UINT64_C(784339968), // FABDv4f16 |
353 | 1.59k | UINT64_C(1856033792), // FABDv4f32 |
354 | 1.59k | UINT64_C(1858081792), // FABDv8f16 |
355 | 1.59k | UINT64_C(509657088), // FABSDr |
356 | 1.59k | UINT64_C(518045696), // FABSHr |
357 | 1.59k | UINT64_C(505462784), // FABSSr |
358 | 1.59k | UINT64_C(245430272), // FABSv2f32 |
359 | 1.59k | UINT64_C(1323366400), // FABSv2f64 |
360 | 1.59k | UINT64_C(251197440), // FABSv4f16 |
361 | 1.59k | UINT64_C(1319172096), // FABSv4f32 |
362 | 1.59k | UINT64_C(1324939264), // FABSv8f16 |
363 | 1.59k | UINT64_C(2118134784), // FACGE16 |
364 | 1.59k | UINT64_C(2116086784), // FACGE32 |
365 | 1.59k | UINT64_C(2120281088), // FACGE64 |
366 | 1.59k | UINT64_C(773909504), // FACGEv2f32 |
367 | 1.59k | UINT64_C(1851845632), // FACGEv2f64 |
368 | 1.59k | UINT64_C(775957504), // FACGEv4f16 |
369 | 1.59k | UINT64_C(1847651328), // FACGEv4f32 |
370 | 1.59k | UINT64_C(1849699328), // FACGEv8f16 |
371 | 1.59k | UINT64_C(2126523392), // FACGT16 |
372 | 1.59k | UINT64_C(2124475392), // FACGT32 |
373 | 1.59k | UINT64_C(2128669696), // FACGT64 |
374 | 1.59k | UINT64_C(782298112), // FACGTv2f32 |
375 | 1.59k | UINT64_C(1860234240), // FACGTv2f64 |
376 | 1.59k | UINT64_C(784346112), // FACGTv4f16 |
377 | 1.59k | UINT64_C(1856039936), // FACGTv4f32 |
378 | 1.59k | UINT64_C(1858087936), // FACGTv8f16 |
379 | 1.59k | UINT64_C(509618176), // FADDDrr |
380 | 1.59k | UINT64_C(518006784), // FADDHrr |
381 | 1.59k | UINT64_C(773903360), // FADDPv2f32 |
382 | 1.59k | UINT64_C(1851839488), // FADDPv2f64 |
383 | 1.59k | UINT64_C(1580259328), // FADDPv2i16p |
384 | 1.59k | UINT64_C(2117130240), // FADDPv2i32p |
385 | 1.59k | UINT64_C(2121324544), // FADDPv2i64p |
386 | 1.59k | UINT64_C(775951360), // FADDPv4f16 |
387 | 1.59k | UINT64_C(1847645184), // FADDPv4f32 |
388 | 1.59k | UINT64_C(1849693184), // FADDPv8f16 |
389 | 1.59k | UINT64_C(505423872), // FADDSrr |
390 | 1.59k | UINT64_C(237032448), // FADDv2f32 |
391 | 1.59k | UINT64_C(1314968576), // FADDv2f64 |
392 | 1.59k | UINT64_C(239080448), // FADDv4f16 |
393 | 1.59k | UINT64_C(1310774272), // FADDv4f32 |
394 | 1.59k | UINT64_C(1312822272), // FADDv8f16 |
395 | 1.59k | UINT64_C(509608960), // FCCMPDrr |
396 | 1.59k | UINT64_C(509608976), // FCCMPEDrr |
397 | 1.59k | UINT64_C(517997584), // FCCMPEHrr |
398 | 1.59k | UINT64_C(505414672), // FCCMPESrr |
399 | 1.59k | UINT64_C(517997568), // FCCMPHrr |
400 | 1.59k | UINT64_C(505414656), // FCCMPSrr |
401 | 1.59k | UINT64_C(1581261824), // FCMEQ16 |
402 | 1.59k | UINT64_C(1579213824), // FCMEQ32 |
403 | 1.59k | UINT64_C(1583408128), // FCMEQ64 |
404 | 1.59k | UINT64_C(1593366528), // FCMEQv1i16rz |
405 | 1.59k | UINT64_C(1587599360), // FCMEQv1i32rz |
406 | 1.59k | UINT64_C(1591793664), // FCMEQv1i64rz |
407 | 1.59k | UINT64_C(237036544), // FCMEQv2f32 |
408 | 1.59k | UINT64_C(1314972672), // FCMEQv2f64 |
409 | 1.59k | UINT64_C(245422080), // FCMEQv2i32rz |
410 | 1.59k | UINT64_C(1323358208), // FCMEQv2i64rz |
411 | 1.59k | UINT64_C(239084544), // FCMEQv4f16 |
412 | 1.59k | UINT64_C(1310778368), // FCMEQv4f32 |
413 | 1.59k | UINT64_C(251189248), // FCMEQv4i16rz |
414 | 1.59k | UINT64_C(1319163904), // FCMEQv4i32rz |
415 | 1.59k | UINT64_C(1312826368), // FCMEQv8f16 |
416 | 1.59k | UINT64_C(1324931072), // FCMEQv8i16rz |
417 | 1.59k | UINT64_C(2118132736), // FCMGE16 |
418 | 1.59k | UINT64_C(2116084736), // FCMGE32 |
419 | 1.59k | UINT64_C(2120279040), // FCMGE64 |
420 | 1.59k | UINT64_C(2130233344), // FCMGEv1i16rz |
421 | 1.59k | UINT64_C(2124466176), // FCMGEv1i32rz |
422 | 1.59k | UINT64_C(2128660480), // FCMGEv1i64rz |
423 | 1.59k | UINT64_C(773907456), // FCMGEv2f32 |
424 | 1.59k | UINT64_C(1851843584), // FCMGEv2f64 |
425 | 1.59k | UINT64_C(782288896), // FCMGEv2i32rz |
426 | 1.59k | UINT64_C(1860225024), // FCMGEv2i64rz |
427 | 1.59k | UINT64_C(775955456), // FCMGEv4f16 |
428 | 1.59k | UINT64_C(1847649280), // FCMGEv4f32 |
429 | 1.59k | UINT64_C(788056064), // FCMGEv4i16rz |
430 | 1.59k | UINT64_C(1856030720), // FCMGEv4i32rz |
431 | 1.59k | UINT64_C(1849697280), // FCMGEv8f16 |
432 | 1.59k | UINT64_C(1861797888), // FCMGEv8i16rz |
433 | 1.59k | UINT64_C(2126521344), // FCMGT16 |
434 | 1.59k | UINT64_C(2124473344), // FCMGT32 |
435 | 1.59k | UINT64_C(2128667648), // FCMGT64 |
436 | 1.59k | UINT64_C(1593362432), // FCMGTv1i16rz |
437 | 1.59k | UINT64_C(1587595264), // FCMGTv1i32rz |
438 | 1.59k | UINT64_C(1591789568), // FCMGTv1i64rz |
439 | 1.59k | UINT64_C(782296064), // FCMGTv2f32 |
440 | 1.59k | UINT64_C(1860232192), // FCMGTv2f64 |
441 | 1.59k | UINT64_C(245417984), // FCMGTv2i32rz |
442 | 1.59k | UINT64_C(1323354112), // FCMGTv2i64rz |
443 | 1.59k | UINT64_C(784344064), // FCMGTv4f16 |
444 | 1.59k | UINT64_C(1856037888), // FCMGTv4f32 |
445 | 1.59k | UINT64_C(251185152), // FCMGTv4i16rz |
446 | 1.59k | UINT64_C(1319159808), // FCMGTv4i32rz |
447 | 1.59k | UINT64_C(1858085888), // FCMGTv8f16 |
448 | 1.59k | UINT64_C(1324926976), // FCMGTv8i16rz |
449 | 1.59k | UINT64_C(2130237440), // FCMLEv1i16rz |
450 | 1.59k | UINT64_C(2124470272), // FCMLEv1i32rz |
451 | 1.59k | UINT64_C(2128664576), // FCMLEv1i64rz |
452 | 1.59k | UINT64_C(782292992), // FCMLEv2i32rz |
453 | 1.59k | UINT64_C(1860229120), // FCMLEv2i64rz |
454 | 1.59k | UINT64_C(788060160), // FCMLEv4i16rz |
455 | 1.59k | UINT64_C(1856034816), // FCMLEv4i32rz |
456 | 1.59k | UINT64_C(1861801984), // FCMLEv8i16rz |
457 | 1.59k | UINT64_C(1593370624), // FCMLTv1i16rz |
458 | 1.59k | UINT64_C(1587603456), // FCMLTv1i32rz |
459 | 1.59k | UINT64_C(1591797760), // FCMLTv1i64rz |
460 | 1.59k | UINT64_C(245426176), // FCMLTv2i32rz |
461 | 1.59k | UINT64_C(1323362304), // FCMLTv2i64rz |
462 | 1.59k | UINT64_C(251193344), // FCMLTv4i16rz |
463 | 1.59k | UINT64_C(1319168000), // FCMLTv4i32rz |
464 | 1.59k | UINT64_C(1324935168), // FCMLTv8i16rz |
465 | 1.59k | UINT64_C(509616136), // FCMPDri |
466 | 1.59k | UINT64_C(509616128), // FCMPDrr |
467 | 1.59k | UINT64_C(509616152), // FCMPEDri |
468 | 1.59k | UINT64_C(509616144), // FCMPEDrr |
469 | 1.59k | UINT64_C(518004760), // FCMPEHri |
470 | 1.59k | UINT64_C(518004752), // FCMPEHrr |
471 | 1.59k | UINT64_C(505421848), // FCMPESri |
472 | 1.59k | UINT64_C(505421840), // FCMPESrr |
473 | 1.59k | UINT64_C(518004744), // FCMPHri |
474 | 1.59k | UINT64_C(518004736), // FCMPHrr |
475 | 1.59k | UINT64_C(505421832), // FCMPSri |
476 | 1.59k | UINT64_C(505421824), // FCMPSrr |
477 | 1.59k | UINT64_C(509611008), // FCSELDrrr |
478 | 1.59k | UINT64_C(517999616), // FCSELHrrr |
479 | 1.59k | UINT64_C(505416704), // FCSELSrrr |
480 | 1.59k | UINT64_C(509870080), // FCVTASUWDr |
481 | 1.59k | UINT64_C(518258688), // FCVTASUWHr |
482 | 1.59k | UINT64_C(505675776), // FCVTASUWSr |
483 | 1.59k | UINT64_C(2657353728), // FCVTASUXDr |
484 | 1.59k | UINT64_C(2665742336), // FCVTASUXHr |
485 | 1.59k | UINT64_C(2653159424), // FCVTASUXSr |
486 | 1.59k | UINT64_C(1585039360), // FCVTASv1f16 |
487 | 1.59k | UINT64_C(1579272192), // FCVTASv1i32 |
488 | 1.59k | UINT64_C(1583466496), // FCVTASv1i64 |
489 | 1.59k | UINT64_C(237094912), // FCVTASv2f32 |
490 | 1.59k | UINT64_C(1315031040), // FCVTASv2f64 |
491 | 1.59k | UINT64_C(242862080), // FCVTASv4f16 |
492 | 1.59k | UINT64_C(1310836736), // FCVTASv4f32 |
493 | 1.59k | UINT64_C(1316603904), // FCVTASv8f16 |
494 | 1.59k | UINT64_C(509935616), // FCVTAUUWDr |
495 | 1.59k | UINT64_C(518324224), // FCVTAUUWHr |
496 | 1.59k | UINT64_C(505741312), // FCVTAUUWSr |
497 | 1.59k | UINT64_C(2657419264), // FCVTAUUXDr |
498 | 1.59k | UINT64_C(2665807872), // FCVTAUUXHr |
499 | 1.59k | UINT64_C(2653224960), // FCVTAUUXSr |
500 | 1.59k | UINT64_C(2121910272), // FCVTAUv1f16 |
501 | 1.59k | UINT64_C(2116143104), // FCVTAUv1i32 |
502 | 1.59k | UINT64_C(2120337408), // FCVTAUv1i64 |
503 | 1.59k | UINT64_C(773965824), // FCVTAUv2f32 |
504 | 1.59k | UINT64_C(1851901952), // FCVTAUv2f64 |
505 | 1.59k | UINT64_C(779732992), // FCVTAUv4f16 |
506 | 1.59k | UINT64_C(1847707648), // FCVTAUv4f32 |
507 | 1.59k | UINT64_C(1853474816), // FCVTAUv8f16 |
508 | 1.59k | UINT64_C(518176768), // FCVTDHr |
509 | 1.59k | UINT64_C(505593856), // FCVTDSr |
510 | 1.59k | UINT64_C(509853696), // FCVTHDr |
511 | 1.59k | UINT64_C(505659392), // FCVTHSr |
512 | 1.59k | UINT64_C(241268736), // FCVTLv2i32 |
513 | 1.59k | UINT64_C(237074432), // FCVTLv4i16 |
514 | 1.59k | UINT64_C(1315010560), // FCVTLv4i32 |
515 | 1.59k | UINT64_C(1310816256), // FCVTLv8i16 |
516 | 1.59k | UINT64_C(510656512), // FCVTMSUWDr |
517 | 1.59k | UINT64_C(519045120), // FCVTMSUWHr |
518 | 1.59k | UINT64_C(506462208), // FCVTMSUWSr |
519 | 1.59k | UINT64_C(2658140160), // FCVTMSUXDr |
520 | 1.59k | UINT64_C(2666528768), // FCVTMSUXHr |
521 | 1.59k | UINT64_C(2653945856), // FCVTMSUXSr |
522 | 1.59k | UINT64_C(1585035264), // FCVTMSv1f16 |
523 | 1.59k | UINT64_C(1579268096), // FCVTMSv1i32 |
524 | 1.59k | UINT64_C(1583462400), // FCVTMSv1i64 |
525 | 1.59k | UINT64_C(237090816), // FCVTMSv2f32 |
526 | 1.59k | UINT64_C(1315026944), // FCVTMSv2f64 |
527 | 1.59k | UINT64_C(242857984), // FCVTMSv4f16 |
528 | 1.59k | UINT64_C(1310832640), // FCVTMSv4f32 |
529 | 1.59k | UINT64_C(1316599808), // FCVTMSv8f16 |
530 | 1.59k | UINT64_C(510722048), // FCVTMUUWDr |
531 | 1.59k | UINT64_C(519110656), // FCVTMUUWHr |
532 | 1.59k | UINT64_C(506527744), // FCVTMUUWSr |
533 | 1.59k | UINT64_C(2658205696), // FCVTMUUXDr |
534 | 1.59k | UINT64_C(2666594304), // FCVTMUUXHr |
535 | 1.59k | UINT64_C(2654011392), // FCVTMUUXSr |
536 | 1.59k | UINT64_C(2121906176), // FCVTMUv1f16 |
537 | 1.59k | UINT64_C(2116139008), // FCVTMUv1i32 |
538 | 1.59k | UINT64_C(2120333312), // FCVTMUv1i64 |
539 | 1.59k | UINT64_C(773961728), // FCVTMUv2f32 |
540 | 1.59k | UINT64_C(1851897856), // FCVTMUv2f64 |
541 | 1.59k | UINT64_C(779728896), // FCVTMUv4f16 |
542 | 1.59k | UINT64_C(1847703552), // FCVTMUv4f32 |
543 | 1.59k | UINT64_C(1853470720), // FCVTMUv8f16 |
544 | 1.59k | UINT64_C(509607936), // FCVTNSUWDr |
545 | 1.59k | UINT64_C(517996544), // FCVTNSUWHr |
546 | 1.59k | UINT64_C(505413632), // FCVTNSUWSr |
547 | 1.59k | UINT64_C(2657091584), // FCVTNSUXDr |
548 | 1.59k | UINT64_C(2665480192), // FCVTNSUXHr |
549 | 1.59k | UINT64_C(2652897280), // FCVTNSUXSr |
550 | 1.59k | UINT64_C(1585031168), // FCVTNSv1f16 |
551 | 1.59k | UINT64_C(1579264000), // FCVTNSv1i32 |
552 | 1.59k | UINT64_C(1583458304), // FCVTNSv1i64 |
553 | 1.59k | UINT64_C(237086720), // FCVTNSv2f32 |
554 | 1.59k | UINT64_C(1315022848), // FCVTNSv2f64 |
555 | 1.59k | UINT64_C(242853888), // FCVTNSv4f16 |
556 | 1.59k | UINT64_C(1310828544), // FCVTNSv4f32 |
557 | 1.59k | UINT64_C(1316595712), // FCVTNSv8f16 |
558 | 1.59k | UINT64_C(509673472), // FCVTNUUWDr |
559 | 1.59k | UINT64_C(518062080), // FCVTNUUWHr |
560 | 1.59k | UINT64_C(505479168), // FCVTNUUWSr |
561 | 1.59k | UINT64_C(2657157120), // FCVTNUUXDr |
562 | 1.59k | UINT64_C(2665545728), // FCVTNUUXHr |
563 | 1.59k | UINT64_C(2652962816), // FCVTNUUXSr |
564 | 1.59k | UINT64_C(2121902080), // FCVTNUv1f16 |
565 | 1.59k | UINT64_C(2116134912), // FCVTNUv1i32 |
566 | 1.59k | UINT64_C(2120329216), // FCVTNUv1i64 |
567 | 1.59k | UINT64_C(773957632), // FCVTNUv2f32 |
568 | 1.59k | UINT64_C(1851893760), // FCVTNUv2f64 |
569 | 1.59k | UINT64_C(779724800), // FCVTNUv4f16 |
570 | 1.59k | UINT64_C(1847699456), // FCVTNUv4f32 |
571 | 1.59k | UINT64_C(1853466624), // FCVTNUv8f16 |
572 | 1.59k | UINT64_C(241264640), // FCVTNv2i32 |
573 | 1.59k | UINT64_C(237070336), // FCVTNv4i16 |
574 | 1.59k | UINT64_C(1315006464), // FCVTNv4i32 |
575 | 1.59k | UINT64_C(1310812160), // FCVTNv8i16 |
576 | 1.59k | UINT64_C(510132224), // FCVTPSUWDr |
577 | 1.59k | UINT64_C(518520832), // FCVTPSUWHr |
578 | 1.59k | UINT64_C(505937920), // FCVTPSUWSr |
579 | 1.59k | UINT64_C(2657615872), // FCVTPSUXDr |
580 | 1.59k | UINT64_C(2666004480), // FCVTPSUXHr |
581 | 1.59k | UINT64_C(2653421568), // FCVTPSUXSr |
582 | 1.59k | UINT64_C(1593419776), // FCVTPSv1f16 |
583 | 1.59k | UINT64_C(1587652608), // FCVTPSv1i32 |
584 | 1.59k | UINT64_C(1591846912), // FCVTPSv1i64 |
585 | 1.59k | UINT64_C(245475328), // FCVTPSv2f32 |
586 | 1.59k | UINT64_C(1323411456), // FCVTPSv2f64 |
587 | 1.59k | UINT64_C(251242496), // FCVTPSv4f16 |
588 | 1.59k | UINT64_C(1319217152), // FCVTPSv4f32 |
589 | 1.59k | UINT64_C(1324984320), // FCVTPSv8f16 |
590 | 1.59k | UINT64_C(510197760), // FCVTPUUWDr |
591 | 1.59k | UINT64_C(518586368), // FCVTPUUWHr |
592 | 1.59k | UINT64_C(506003456), // FCVTPUUWSr |
593 | 1.59k | UINT64_C(2657681408), // FCVTPUUXDr |
594 | 1.59k | UINT64_C(2666070016), // FCVTPUUXHr |
595 | 1.59k | UINT64_C(2653487104), // FCVTPUUXSr |
596 | 1.59k | UINT64_C(2130290688), // FCVTPUv1f16 |
597 | 1.59k | UINT64_C(2124523520), // FCVTPUv1i32 |
598 | 1.59k | UINT64_C(2128717824), // FCVTPUv1i64 |
599 | 1.59k | UINT64_C(782346240), // FCVTPUv2f32 |
600 | 1.59k | UINT64_C(1860282368), // FCVTPUv2f64 |
601 | 1.59k | UINT64_C(788113408), // FCVTPUv4f16 |
602 | 1.59k | UINT64_C(1856088064), // FCVTPUv4f32 |
603 | 1.59k | UINT64_C(1861855232), // FCVTPUv8f16 |
604 | 1.59k | UINT64_C(509755392), // FCVTSDr |
605 | 1.59k | UINT64_C(518144000), // FCVTSHr |
606 | 1.59k | UINT64_C(2120312832), // FCVTXNv1i64 |
607 | 1.59k | UINT64_C(778135552), // FCVTXNv2f32 |
608 | 1.59k | UINT64_C(1851877376), // FCVTXNv4f32 |
609 | 1.59k | UINT64_C(509116416), // FCVTZSSWDri |
610 | 1.59k | UINT64_C(517505024), // FCVTZSSWHri |
611 | 1.59k | UINT64_C(504922112), // FCVTZSSWSri |
612 | 1.59k | UINT64_C(2656567296), // FCVTZSSXDri |
613 | 1.59k | UINT64_C(2664955904), // FCVTZSSXHri |
614 | 1.59k | UINT64_C(2652372992), // FCVTZSSXSri |
615 | 1.59k | UINT64_C(511180800), // FCVTZSUWDr |
616 | 1.59k | UINT64_C(519569408), // FCVTZSUWHr |
617 | 1.59k | UINT64_C(506986496), // FCVTZSUWSr |
618 | 1.59k | UINT64_C(2658664448), // FCVTZSUXDr |
619 | 1.59k | UINT64_C(2667053056), // FCVTZSUXHr |
620 | 1.59k | UINT64_C(2654470144), // FCVTZSUXSr |
621 | 1.59k | UINT64_C(509116416), // FCVTZS_IntSWDri |
622 | 1.59k | UINT64_C(517505024), // FCVTZS_IntSWHri |
623 | 1.59k | UINT64_C(504922112), // FCVTZS_IntSWSri |
624 | 1.59k | UINT64_C(2656567296), // FCVTZS_IntSXDri |
625 | 1.59k | UINT64_C(2664955904), // FCVTZS_IntSXHri |
626 | 1.59k | UINT64_C(2652372992), // FCVTZS_IntSXSri |
627 | 1.59k | UINT64_C(511180800), // FCVTZS_IntUWDr |
628 | 1.59k | UINT64_C(519569408), // FCVTZS_IntUWHr |
629 | 1.59k | UINT64_C(506986496), // FCVTZS_IntUWSr |
630 | 1.59k | UINT64_C(2658664448), // FCVTZS_IntUXDr |
631 | 1.59k | UINT64_C(2667053056), // FCVTZS_IntUXHr |
632 | 1.59k | UINT64_C(2654470144), // FCVTZS_IntUXSr |
633 | 1.59k | UINT64_C(245479424), // FCVTZS_Intv2f32 |
634 | 1.59k | UINT64_C(1323415552), // FCVTZS_Intv2f64 |
635 | 1.59k | UINT64_C(251246592), // FCVTZS_Intv4f16 |
636 | 1.59k | UINT64_C(1319221248), // FCVTZS_Intv4f32 |
637 | 1.59k | UINT64_C(1324988416), // FCVTZS_Intv8f16 |
638 | 1.59k | UINT64_C(1598094336), // FCVTZSd |
639 | 1.59k | UINT64_C(1594948608), // FCVTZSh |
640 | 1.59k | UINT64_C(1595997184), // FCVTZSs |
641 | 1.59k | UINT64_C(1593423872), // FCVTZSv1f16 |
642 | 1.59k | UINT64_C(1587656704), // FCVTZSv1i32 |
643 | 1.59k | UINT64_C(1591851008), // FCVTZSv1i64 |
644 | 1.59k | UINT64_C(245479424), // FCVTZSv2f32 |
645 | 1.59k | UINT64_C(1323415552), // FCVTZSv2f64 |
646 | 1.59k | UINT64_C(253819904), // FCVTZSv2i32_shift |
647 | 1.59k | UINT64_C(1329658880), // FCVTZSv2i64_shift |
648 | 1.59k | UINT64_C(251246592), // FCVTZSv4f16 |
649 | 1.59k | UINT64_C(1319221248), // FCVTZSv4f32 |
650 | 1.59k | UINT64_C(252771328), // FCVTZSv4i16_shift |
651 | 1.59k | UINT64_C(1327561728), // FCVTZSv4i32_shift |
652 | 1.59k | UINT64_C(1324988416), // FCVTZSv8f16 |
653 | 1.59k | UINT64_C(1326513152), // FCVTZSv8i16_shift |
654 | 1.59k | UINT64_C(509181952), // FCVTZUSWDri |
655 | 1.59k | UINT64_C(517570560), // FCVTZUSWHri |
656 | 1.59k | UINT64_C(504987648), // FCVTZUSWSri |
657 | 1.59k | UINT64_C(2656632832), // FCVTZUSXDri |
658 | 1.59k | UINT64_C(2665021440), // FCVTZUSXHri |
659 | 1.59k | UINT64_C(2652438528), // FCVTZUSXSri |
660 | 1.59k | UINT64_C(511246336), // FCVTZUUWDr |
661 | 1.59k | UINT64_C(519634944), // FCVTZUUWHr |
662 | 1.59k | UINT64_C(507052032), // FCVTZUUWSr |
663 | 1.59k | UINT64_C(2658729984), // FCVTZUUXDr |
664 | 1.59k | UINT64_C(2667118592), // FCVTZUUXHr |
665 | 1.59k | UINT64_C(2654535680), // FCVTZUUXSr |
666 | 1.59k | UINT64_C(509181952), // FCVTZU_IntSWDri |
667 | 1.59k | UINT64_C(517570560), // FCVTZU_IntSWHri |
668 | 1.59k | UINT64_C(504987648), // FCVTZU_IntSWSri |
669 | 1.59k | UINT64_C(2656632832), // FCVTZU_IntSXDri |
670 | 1.59k | UINT64_C(2665021440), // FCVTZU_IntSXHri |
671 | 1.59k | UINT64_C(2652438528), // FCVTZU_IntSXSri |
672 | 1.59k | UINT64_C(511246336), // FCVTZU_IntUWDr |
673 | 1.59k | UINT64_C(519634944), // FCVTZU_IntUWHr |
674 | 1.59k | UINT64_C(507052032), // FCVTZU_IntUWSr |
675 | 1.59k | UINT64_C(2658729984), // FCVTZU_IntUXDr |
676 | 1.59k | UINT64_C(2667118592), // FCVTZU_IntUXHr |
677 | 1.59k | UINT64_C(2654535680), // FCVTZU_IntUXSr |
678 | 1.59k | UINT64_C(782350336), // FCVTZU_Intv2f32 |
679 | 1.59k | UINT64_C(1860286464), // FCVTZU_Intv2f64 |
680 | 1.59k | UINT64_C(788117504), // FCVTZU_Intv4f16 |
681 | 1.59k | UINT64_C(1856092160), // FCVTZU_Intv4f32 |
682 | 1.59k | UINT64_C(1861859328), // FCVTZU_Intv8f16 |
683 | 1.59k | UINT64_C(2134965248), // FCVTZUd |
684 | 1.59k | UINT64_C(2131819520), // FCVTZUh |
685 | 1.59k | UINT64_C(2132868096), // FCVTZUs |
686 | 1.59k | UINT64_C(2130294784), // FCVTZUv1f16 |
687 | 1.59k | UINT64_C(2124527616), // FCVTZUv1i32 |
688 | 1.59k | UINT64_C(2128721920), // FCVTZUv1i64 |
689 | 1.59k | UINT64_C(782350336), // FCVTZUv2f32 |
690 | 1.59k | UINT64_C(1860286464), // FCVTZUv2f64 |
691 | 1.59k | UINT64_C(790690816), // FCVTZUv2i32_shift |
692 | 1.59k | UINT64_C(1866529792), // FCVTZUv2i64_shift |
693 | 1.59k | UINT64_C(788117504), // FCVTZUv4f16 |
694 | 1.59k | UINT64_C(1856092160), // FCVTZUv4f32 |
695 | 1.59k | UINT64_C(789642240), // FCVTZUv4i16_shift |
696 | 1.59k | UINT64_C(1864432640), // FCVTZUv4i32_shift |
697 | 1.59k | UINT64_C(1861859328), // FCVTZUv8f16 |
698 | 1.59k | UINT64_C(1863384064), // FCVTZUv8i16_shift |
699 | 1.59k | UINT64_C(509614080), // FDIVDrr |
700 | 1.59k | UINT64_C(518002688), // FDIVHrr |
701 | 1.59k | UINT64_C(505419776), // FDIVSrr |
702 | 1.59k | UINT64_C(773913600), // FDIVv2f32 |
703 | 1.59k | UINT64_C(1851849728), // FDIVv2f64 |
704 | 1.59k | UINT64_C(775961600), // FDIVv4f16 |
705 | 1.59k | UINT64_C(1847655424), // FDIVv4f32 |
706 | 1.59k | UINT64_C(1849703424), // FDIVv8f16 |
707 | 1.59k | UINT64_C(524288000), // FMADDDrrr |
708 | 1.59k | UINT64_C(532676608), // FMADDHrrr |
709 | 1.59k | UINT64_C(520093696), // FMADDSrrr |
710 | 1.59k | UINT64_C(509626368), // FMAXDrr |
711 | 1.59k | UINT64_C(518014976), // FMAXHrr |
712 | 1.59k | UINT64_C(509634560), // FMAXNMDrr |
713 | 1.59k | UINT64_C(518023168), // FMAXNMHrr |
714 | 1.59k | UINT64_C(773899264), // FMAXNMPv2f32 |
715 | 1.59k | UINT64_C(1851835392), // FMAXNMPv2f64 |
716 | 1.59k | UINT64_C(1580255232), // FMAXNMPv2i16p |
717 | 1.59k | UINT64_C(2117126144), // FMAXNMPv2i32p |
718 | 1.59k | UINT64_C(2121320448), // FMAXNMPv2i64p |
719 | 1.59k | UINT64_C(775947264), // FMAXNMPv4f16 |
720 | 1.59k | UINT64_C(1847641088), // FMAXNMPv4f32 |
721 | 1.59k | UINT64_C(1849689088), // FMAXNMPv8f16 |
722 | 1.59k | UINT64_C(505440256), // FMAXNMSrr |
723 | 1.59k | UINT64_C(238077952), // FMAXNMVv4i16v |
724 | 1.59k | UINT64_C(1848690688), // FMAXNMVv4i32v |
725 | 1.59k | UINT64_C(1311819776), // FMAXNMVv8i16v |
726 | 1.59k | UINT64_C(237028352), // FMAXNMv2f32 |
727 | 1.59k | UINT64_C(1314964480), // FMAXNMv2f64 |
728 | 1.59k | UINT64_C(239076352), // FMAXNMv4f16 |
729 | 1.59k | UINT64_C(1310770176), // FMAXNMv4f32 |
730 | 1.59k | UINT64_C(1312818176), // FMAXNMv8f16 |
731 | 1.59k | UINT64_C(773911552), // FMAXPv2f32 |
732 | 1.59k | UINT64_C(1851847680), // FMAXPv2f64 |
733 | 1.59k | UINT64_C(1580267520), // FMAXPv2i16p |
734 | 1.59k | UINT64_C(2117138432), // FMAXPv2i32p |
735 | 1.59k | UINT64_C(2121332736), // FMAXPv2i64p |
736 | 1.59k | UINT64_C(775959552), // FMAXPv4f16 |
737 | 1.59k | UINT64_C(1847653376), // FMAXPv4f32 |
738 | 1.59k | UINT64_C(1849701376), // FMAXPv8f16 |
739 | 1.59k | UINT64_C(505432064), // FMAXSrr |
740 | 1.59k | UINT64_C(238090240), // FMAXVv4i16v |
741 | 1.59k | UINT64_C(1848702976), // FMAXVv4i32v |
742 | 1.59k | UINT64_C(1311832064), // FMAXVv8i16v |
743 | 1.59k | UINT64_C(237040640), // FMAXv2f32 |
744 | 1.59k | UINT64_C(1314976768), // FMAXv2f64 |
745 | 1.59k | UINT64_C(239088640), // FMAXv4f16 |
746 | 1.59k | UINT64_C(1310782464), // FMAXv4f32 |
747 | 1.59k | UINT64_C(1312830464), // FMAXv8f16 |
748 | 1.59k | UINT64_C(509630464), // FMINDrr |
749 | 1.59k | UINT64_C(518019072), // FMINHrr |
750 | 1.59k | UINT64_C(509638656), // FMINNMDrr |
751 | 1.59k | UINT64_C(518027264), // FMINNMHrr |
752 | 1.59k | UINT64_C(782287872), // FMINNMPv2f32 |
753 | 1.59k | UINT64_C(1860224000), // FMINNMPv2f64 |
754 | 1.59k | UINT64_C(1588643840), // FMINNMPv2i16p |
755 | 1.59k | UINT64_C(2125514752), // FMINNMPv2i32p |
756 | 1.59k | UINT64_C(2129709056), // FMINNMPv2i64p |
757 | 1.59k | UINT64_C(784335872), // FMINNMPv4f16 |
758 | 1.59k | UINT64_C(1856029696), // FMINNMPv4f32 |
759 | 1.59k | UINT64_C(1858077696), // FMINNMPv8f16 |
760 | 1.59k | UINT64_C(505444352), // FMINNMSrr |
761 | 1.59k | UINT64_C(246466560), // FMINNMVv4i16v |
762 | 1.59k | UINT64_C(1857079296), // FMINNMVv4i32v |
763 | 1.59k | UINT64_C(1320208384), // FMINNMVv8i16v |
764 | 1.59k | UINT64_C(245416960), // FMINNMv2f32 |
765 | 1.59k | UINT64_C(1323353088), // FMINNMv2f64 |
766 | 1.59k | UINT64_C(247464960), // FMINNMv4f16 |
767 | 1.59k | UINT64_C(1319158784), // FMINNMv4f32 |
768 | 1.59k | UINT64_C(1321206784), // FMINNMv8f16 |
769 | 1.59k | UINT64_C(782300160), // FMINPv2f32 |
770 | 1.59k | UINT64_C(1860236288), // FMINPv2f64 |
771 | 1.59k | UINT64_C(1588656128), // FMINPv2i16p |
772 | 1.59k | UINT64_C(2125527040), // FMINPv2i32p |
773 | 1.59k | UINT64_C(2129721344), // FMINPv2i64p |
774 | 1.59k | UINT64_C(784348160), // FMINPv4f16 |
775 | 1.59k | UINT64_C(1856041984), // FMINPv4f32 |
776 | 1.59k | UINT64_C(1858089984), // FMINPv8f16 |
777 | 1.59k | UINT64_C(505436160), // FMINSrr |
778 | 1.59k | UINT64_C(246478848), // FMINVv4i16v |
779 | 1.59k | UINT64_C(1857091584), // FMINVv4i32v |
780 | 1.59k | UINT64_C(1320220672), // FMINVv8i16v |
781 | 1.59k | UINT64_C(245429248), // FMINv2f32 |
782 | 1.59k | UINT64_C(1323365376), // FMINv2f64 |
783 | 1.59k | UINT64_C(247477248), // FMINv4f16 |
784 | 1.59k | UINT64_C(1319171072), // FMINv4f32 |
785 | 1.59k | UINT64_C(1321219072), // FMINv8f16 |
786 | 1.59k | UINT64_C(1593839616), // FMLAv1i16_indexed |
787 | 1.59k | UINT64_C(1602228224), // FMLAv1i32_indexed |
788 | 1.59k | UINT64_C(1606422528), // FMLAv1i64_indexed |
789 | 1.59k | UINT64_C(237030400), // FMLAv2f32 |
790 | 1.59k | UINT64_C(1314966528), // FMLAv2f64 |
791 | 1.59k | UINT64_C(260050944), // FMLAv2i32_indexed |
792 | 1.59k | UINT64_C(1337987072), // FMLAv2i64_indexed |
793 | 1.59k | UINT64_C(239078400), // FMLAv4f16 |
794 | 1.59k | UINT64_C(1310772224), // FMLAv4f32 |
795 | 1.59k | UINT64_C(251662336), // FMLAv4i16_indexed |
796 | 1.59k | UINT64_C(1333792768), // FMLAv4i32_indexed |
797 | 1.59k | UINT64_C(1312820224), // FMLAv8f16 |
798 | 1.59k | UINT64_C(1325404160), // FMLAv8i16_indexed |
799 | 1.59k | UINT64_C(1593856000), // FMLSv1i16_indexed |
800 | 1.59k | UINT64_C(1602244608), // FMLSv1i32_indexed |
801 | 1.59k | UINT64_C(1606438912), // FMLSv1i64_indexed |
802 | 1.59k | UINT64_C(245419008), // FMLSv2f32 |
803 | 1.59k | UINT64_C(1323355136), // FMLSv2f64 |
804 | 1.59k | UINT64_C(260067328), // FMLSv2i32_indexed |
805 | 1.59k | UINT64_C(1338003456), // FMLSv2i64_indexed |
806 | 1.59k | UINT64_C(247467008), // FMLSv4f16 |
807 | 1.59k | UINT64_C(1319160832), // FMLSv4f32 |
808 | 1.59k | UINT64_C(251678720), // FMLSv4i16_indexed |
809 | 1.59k | UINT64_C(1333809152), // FMLSv4i32_indexed |
810 | 1.59k | UINT64_C(1321208832), // FMLSv8f16 |
811 | 1.59k | UINT64_C(1325420544), // FMLSv8i16_indexed |
812 | 1.59k | UINT64_C(0), |
813 | 1.59k | UINT64_C(2662203392), // FMOVDXHighr |
814 | 1.59k | UINT64_C(2657484800), // FMOVDXr |
815 | 1.59k | UINT64_C(509612032), // FMOVDi |
816 | 1.59k | UINT64_C(509624320), // FMOVDr |
817 | 1.59k | UINT64_C(518389760), // FMOVHWr |
818 | 1.59k | UINT64_C(2665873408), // FMOVHXr |
819 | 1.59k | UINT64_C(518000640), // FMOVHi |
820 | 1.59k | UINT64_C(518012928), // FMOVHr |
821 | 1.59k | UINT64_C(0), |
822 | 1.59k | UINT64_C(505806848), // FMOVSWr |
823 | 1.59k | UINT64_C(505417728), // FMOVSi |
824 | 1.59k | UINT64_C(505430016), // FMOVSr |
825 | 1.59k | UINT64_C(518455296), // FMOVWHr |
826 | 1.59k | UINT64_C(505872384), // FMOVWSr |
827 | 1.59k | UINT64_C(2662268928), // FMOVXDHighr |
828 | 1.59k | UINT64_C(2657550336), // FMOVXDr |
829 | 1.59k | UINT64_C(2665938944), // FMOVXHr |
830 | 1.59k | UINT64_C(251720704), // FMOVv2f32_ns |
831 | 1.59k | UINT64_C(1862333440), // FMOVv2f64_ns |
832 | 1.59k | UINT64_C(251722752), // FMOVv4f16_ns |
833 | 1.59k | UINT64_C(1325462528), // FMOVv4f32_ns |
834 | 1.59k | UINT64_C(1325464576), // FMOVv8f16_ns |
835 | 1.59k | UINT64_C(524320768), // FMSUBDrrr |
836 | 1.59k | UINT64_C(532709376), // FMSUBHrrr |
837 | 1.59k | UINT64_C(520126464), // FMSUBSrrr |
838 | 1.59k | UINT64_C(509609984), // FMULDrr |
839 | 1.59k | UINT64_C(517998592), // FMULHrr |
840 | 1.59k | UINT64_C(505415680), // FMULSrr |
841 | 1.59k | UINT64_C(1581259776), // FMULX16 |
842 | 1.59k | UINT64_C(1579211776), // FMULX32 |
843 | 1.59k | UINT64_C(1583406080), // FMULX64 |
844 | 1.59k | UINT64_C(2130743296), // FMULXv1i16_indexed |
845 | 1.59k | UINT64_C(2139131904), // FMULXv1i32_indexed |
846 | 1.59k | UINT64_C(2143326208), // FMULXv1i64_indexed |
847 | 1.59k | UINT64_C(237034496), // FMULXv2f32 |
848 | 1.59k | UINT64_C(1314970624), // FMULXv2f64 |
849 | 1.59k | UINT64_C(796954624), // FMULXv2i32_indexed |
850 | 1.59k | UINT64_C(1874890752), // FMULXv2i64_indexed |
851 | 1.59k | UINT64_C(239082496), // FMULXv4f16 |
852 | 1.59k | UINT64_C(1310776320), // FMULXv4f32 |
853 | 1.59k | UINT64_C(788566016), // FMULXv4i16_indexed |
854 | 1.59k | UINT64_C(1870696448), // FMULXv4i32_indexed |
855 | 1.59k | UINT64_C(1312824320), // FMULXv8f16 |
856 | 1.59k | UINT64_C(1862307840), // FMULXv8i16_indexed |
857 | 1.59k | UINT64_C(1593872384), // FMULv1i16_indexed |
858 | 1.59k | UINT64_C(1602260992), // FMULv1i32_indexed |
859 | 1.59k | UINT64_C(1606455296), // FMULv1i64_indexed |
860 | 1.59k | UINT64_C(773905408), // FMULv2f32 |
861 | 1.59k | UINT64_C(1851841536), // FMULv2f64 |
862 | 1.59k | UINT64_C(260083712), // FMULv2i32_indexed |
863 | 1.59k | UINT64_C(1338019840), // FMULv2i64_indexed |
864 | 1.59k | UINT64_C(775953408), // FMULv4f16 |
865 | 1.59k | UINT64_C(1847647232), // FMULv4f32 |
866 | 1.59k | UINT64_C(251695104), // FMULv4i16_indexed |
867 | 1.59k | UINT64_C(1333825536), // FMULv4i32_indexed |
868 | 1.59k | UINT64_C(1849695232), // FMULv8f16 |
869 | 1.59k | UINT64_C(1325436928), // FMULv8i16_indexed |
870 | 1.59k | UINT64_C(509689856), // FNEGDr |
871 | 1.59k | UINT64_C(518078464), // FNEGHr |
872 | 1.59k | UINT64_C(505495552), // FNEGSr |
873 | 1.59k | UINT64_C(782301184), // FNEGv2f32 |
874 | 1.59k | UINT64_C(1860237312), // FNEGv2f64 |
875 | 1.59k | UINT64_C(788068352), // FNEGv4f16 |
876 | 1.59k | UINT64_C(1856043008), // FNEGv4f32 |
877 | 1.59k | UINT64_C(1861810176), // FNEGv8f16 |
878 | 1.59k | UINT64_C(526385152), // FNMADDDrrr |
879 | 1.59k | UINT64_C(534773760), // FNMADDHrrr |
880 | 1.59k | UINT64_C(522190848), // FNMADDSrrr |
881 | 1.59k | UINT64_C(526417920), // FNMSUBDrrr |
882 | 1.59k | UINT64_C(534806528), // FNMSUBHrrr |
883 | 1.59k | UINT64_C(522223616), // FNMSUBSrrr |
884 | 1.59k | UINT64_C(509642752), // FNMULDrr |
885 | 1.59k | UINT64_C(518031360), // FNMULHrr |
886 | 1.59k | UINT64_C(505448448), // FNMULSrr |
887 | 1.59k | UINT64_C(1593432064), // FRECPEv1f16 |
888 | 1.59k | UINT64_C(1587664896), // FRECPEv1i32 |
889 | 1.59k | UINT64_C(1591859200), // FRECPEv1i64 |
890 | 1.59k | UINT64_C(245487616), // FRECPEv2f32 |
891 | 1.59k | UINT64_C(1323423744), // FRECPEv2f64 |
892 | 1.59k | UINT64_C(251254784), // FRECPEv4f16 |
893 | 1.59k | UINT64_C(1319229440), // FRECPEv4f32 |
894 | 1.59k | UINT64_C(1324996608), // FRECPEv8f16 |
895 | 1.59k | UINT64_C(1581267968), // FRECPS16 |
896 | 1.59k | UINT64_C(1579219968), // FRECPS32 |
897 | 1.59k | UINT64_C(1583414272), // FRECPS64 |
898 | 1.59k | UINT64_C(237042688), // FRECPSv2f32 |
899 | 1.59k | UINT64_C(1314978816), // FRECPSv2f64 |
900 | 1.59k | UINT64_C(239090688), // FRECPSv4f16 |
901 | 1.59k | UINT64_C(1310784512), // FRECPSv4f32 |
902 | 1.59k | UINT64_C(1312832512), // FRECPSv8f16 |
903 | 1.59k | UINT64_C(1593440256), // FRECPXv1f16 |
904 | 1.59k | UINT64_C(1587673088), // FRECPXv1i32 |
905 | 1.59k | UINT64_C(1591867392), // FRECPXv1i64 |
906 | 1.59k | UINT64_C(510017536), // FRINTADr |
907 | 1.59k | UINT64_C(518406144), // FRINTAHr |
908 | 1.59k | UINT64_C(505823232), // FRINTASr |
909 | 1.59k | UINT64_C(773949440), // FRINTAv2f32 |
910 | 1.59k | UINT64_C(1851885568), // FRINTAv2f64 |
911 | 1.59k | UINT64_C(779716608), // FRINTAv4f16 |
912 | 1.59k | UINT64_C(1847691264), // FRINTAv4f32 |
913 | 1.59k | UINT64_C(1853458432), // FRINTAv8f16 |
914 | 1.59k | UINT64_C(510115840), // FRINTIDr |
915 | 1.59k | UINT64_C(518504448), // FRINTIHr |
916 | 1.59k | UINT64_C(505921536), // FRINTISr |
917 | 1.59k | UINT64_C(782342144), // FRINTIv2f32 |
918 | 1.59k | UINT64_C(1860278272), // FRINTIv2f64 |
919 | 1.59k | UINT64_C(788109312), // FRINTIv4f16 |
920 | 1.59k | UINT64_C(1856083968), // FRINTIv4f32 |
921 | 1.59k | UINT64_C(1861851136), // FRINTIv8f16 |
922 | 1.59k | UINT64_C(509952000), // FRINTMDr |
923 | 1.59k | UINT64_C(518340608), // FRINTMHr |
924 | 1.59k | UINT64_C(505757696), // FRINTMSr |
925 | 1.59k | UINT64_C(237082624), // FRINTMv2f32 |
926 | 1.59k | UINT64_C(1315018752), // FRINTMv2f64 |
927 | 1.59k | UINT64_C(242849792), // FRINTMv4f16 |
928 | 1.59k | UINT64_C(1310824448), // FRINTMv4f32 |
929 | 1.59k | UINT64_C(1316591616), // FRINTMv8f16 |
930 | 1.59k | UINT64_C(509886464), // FRINTNDr |
931 | 1.59k | UINT64_C(518275072), // FRINTNHr |
932 | 1.59k | UINT64_C(505692160), // FRINTNSr |
933 | 1.59k | UINT64_C(237078528), // FRINTNv2f32 |
934 | 1.59k | UINT64_C(1315014656), // FRINTNv2f64 |
935 | 1.59k | UINT64_C(242845696), // FRINTNv4f16 |
936 | 1.59k | UINT64_C(1310820352), // FRINTNv4f32 |
937 | 1.59k | UINT64_C(1316587520), // FRINTNv8f16 |
938 | 1.59k | UINT64_C(509919232), // FRINTPDr |
939 | 1.59k | UINT64_C(518307840), // FRINTPHr |
940 | 1.59k | UINT64_C(505724928), // FRINTPSr |
941 | 1.59k | UINT64_C(245467136), // FRINTPv2f32 |
942 | 1.59k | UINT64_C(1323403264), // FRINTPv2f64 |
943 | 1.59k | UINT64_C(251234304), // FRINTPv4f16 |
944 | 1.59k | UINT64_C(1319208960), // FRINTPv4f32 |
945 | 1.59k | UINT64_C(1324976128), // FRINTPv8f16 |
946 | 1.59k | UINT64_C(510083072), // FRINTXDr |
947 | 1.59k | UINT64_C(518471680), // FRINTXHr |
948 | 1.59k | UINT64_C(505888768), // FRINTXSr |
949 | 1.59k | UINT64_C(773953536), // FRINTXv2f32 |
950 | 1.59k | UINT64_C(1851889664), // FRINTXv2f64 |
951 | 1.59k | UINT64_C(779720704), // FRINTXv4f16 |
952 | 1.59k | UINT64_C(1847695360), // FRINTXv4f32 |
953 | 1.59k | UINT64_C(1853462528), // FRINTXv8f16 |
954 | 1.59k | UINT64_C(509984768), // FRINTZDr |
955 | 1.59k | UINT64_C(518373376), // FRINTZHr |
956 | 1.59k | UINT64_C(505790464), // FRINTZSr |
957 | 1.59k | UINT64_C(245471232), // FRINTZv2f32 |
958 | 1.59k | UINT64_C(1323407360), // FRINTZv2f64 |
959 | 1.59k | UINT64_C(251238400), // FRINTZv4f16 |
960 | 1.59k | UINT64_C(1319213056), // FRINTZv4f32 |
961 | 1.59k | UINT64_C(1324980224), // FRINTZv8f16 |
962 | 1.59k | UINT64_C(2130302976), // FRSQRTEv1f16 |
963 | 1.59k | UINT64_C(2124535808), // FRSQRTEv1i32 |
964 | 1.59k | UINT64_C(2128730112), // FRSQRTEv1i64 |
965 | 1.59k | UINT64_C(782358528), // FRSQRTEv2f32 |
966 | 1.59k | UINT64_C(1860294656), // FRSQRTEv2f64 |
967 | 1.59k | UINT64_C(788125696), // FRSQRTEv4f16 |
968 | 1.59k | UINT64_C(1856100352), // FRSQRTEv4f32 |
969 | 1.59k | UINT64_C(1861867520), // FRSQRTEv8f16 |
970 | 1.59k | UINT64_C(1589656576), // FRSQRTS16 |
971 | 1.59k | UINT64_C(1587608576), // FRSQRTS32 |
972 | 1.59k | UINT64_C(1591802880), // FRSQRTS64 |
973 | 1.59k | UINT64_C(245431296), // FRSQRTSv2f32 |
974 | 1.59k | UINT64_C(1323367424), // FRSQRTSv2f64 |
975 | 1.59k | UINT64_C(247479296), // FRSQRTSv4f16 |
976 | 1.59k | UINT64_C(1319173120), // FRSQRTSv4f32 |
977 | 1.59k | UINT64_C(1321221120), // FRSQRTSv8f16 |
978 | 1.59k | UINT64_C(509722624), // FSQRTDr |
979 | 1.59k | UINT64_C(518111232), // FSQRTHr |
980 | 1.59k | UINT64_C(505528320), // FSQRTSr |
981 | 1.59k | UINT64_C(782366720), // FSQRTv2f32 |
982 | 1.59k | UINT64_C(1860302848), // FSQRTv2f64 |
983 | 1.59k | UINT64_C(788133888), // FSQRTv4f16 |
984 | 1.59k | UINT64_C(1856108544), // FSQRTv4f32 |
985 | 1.59k | UINT64_C(1861875712), // FSQRTv8f16 |
986 | 1.59k | UINT64_C(509622272), // FSUBDrr |
987 | 1.59k | UINT64_C(518010880), // FSUBHrr |
988 | 1.59k | UINT64_C(505427968), // FSUBSrr |
989 | 1.59k | UINT64_C(245421056), // FSUBv2f32 |
990 | 1.59k | UINT64_C(1323357184), // FSUBv2f64 |
991 | 1.59k | UINT64_C(247469056), // FSUBv4f16 |
992 | 1.59k | UINT64_C(1319162880), // FSUBv4f32 |
993 | 1.59k | UINT64_C(1321210880), // FSUBv8f16 |
994 | 1.59k | UINT64_C(3573751839), // HINT |
995 | 1.59k | UINT64_C(3560964096), // HLT |
996 | 1.59k | UINT64_C(3556769794), // HVC |
997 | 1.59k | UINT64_C(1308761088), // INSvi16gpr |
998 | 1.59k | UINT64_C(1845625856), // INSvi16lane |
999 | 1.59k | UINT64_C(1308892160), // INSvi32gpr |
1000 | 1.59k | UINT64_C(1845756928), // INSvi32lane |
1001 | 1.59k | UINT64_C(1309154304), // INSvi64gpr |
1002 | 1.59k | UINT64_C(1846019072), // INSvi64lane |
1003 | 1.59k | UINT64_C(1308695552), // INSvi8gpr |
1004 | 1.59k | UINT64_C(1845560320), // INSvi8lane |
1005 | 1.59k | UINT64_C(3573756127), // ISB |
1006 | 1.59k | UINT64_C(1279270912), // LD1Fourv16b |
1007 | 1.59k | UINT64_C(1287659520), // LD1Fourv16b_POST |
1008 | 1.59k | UINT64_C(205532160), // LD1Fourv1d |
1009 | 1.59k | UINT64_C(213920768), // LD1Fourv1d_POST |
1010 | 1.59k | UINT64_C(1279273984), // LD1Fourv2d |
1011 | 1.59k | UINT64_C(1287662592), // LD1Fourv2d_POST |
1012 | 1.59k | UINT64_C(205531136), // LD1Fourv2s |
1013 | 1.59k | UINT64_C(213919744), // LD1Fourv2s_POST |
1014 | 1.59k | UINT64_C(205530112), // LD1Fourv4h |
1015 | 1.59k | UINT64_C(213918720), // LD1Fourv4h_POST |
1016 | 1.59k | UINT64_C(1279272960), // LD1Fourv4s |
1017 | 1.59k | UINT64_C(1287661568), // LD1Fourv4s_POST |
1018 | 1.59k | UINT64_C(205529088), // LD1Fourv8b |
1019 | 1.59k | UINT64_C(213917696), // LD1Fourv8b_POST |
1020 | 1.59k | UINT64_C(1279271936), // LD1Fourv8h |
1021 | 1.59k | UINT64_C(1287660544), // LD1Fourv8h_POST |
1022 | 1.59k | UINT64_C(1279291392), // LD1Onev16b |
1023 | 1.59k | UINT64_C(1287680000), // LD1Onev16b_POST |
1024 | 1.59k | UINT64_C(205552640), // LD1Onev1d |
1025 | 1.59k | UINT64_C(213941248), // LD1Onev1d_POST |
1026 | 1.59k | UINT64_C(1279294464), // LD1Onev2d |
1027 | 1.59k | UINT64_C(1287683072), // LD1Onev2d_POST |
1028 | 1.59k | UINT64_C(205551616), // LD1Onev2s |
1029 | 1.59k | UINT64_C(213940224), // LD1Onev2s_POST |
1030 | 1.59k | UINT64_C(205550592), // LD1Onev4h |
1031 | 1.59k | UINT64_C(213939200), // LD1Onev4h_POST |
1032 | 1.59k | UINT64_C(1279293440), // LD1Onev4s |
1033 | 1.59k | UINT64_C(1287682048), // LD1Onev4s_POST |
1034 | 1.59k | UINT64_C(205549568), // LD1Onev8b |
1035 | 1.59k | UINT64_C(213938176), // LD1Onev8b_POST |
1036 | 1.59k | UINT64_C(1279292416), // LD1Onev8h |
1037 | 1.59k | UINT64_C(1287681024), // LD1Onev8h_POST |
1038 | 1.59k | UINT64_C(1296089088), // LD1Rv16b |
1039 | 1.59k | UINT64_C(1304477696), // LD1Rv16b_POST |
1040 | 1.59k | UINT64_C(222350336), // LD1Rv1d |
1041 | 1.59k | UINT64_C(230738944), // LD1Rv1d_POST |
1042 | 1.59k | UINT64_C(1296092160), // LD1Rv2d |
1043 | 1.59k | UINT64_C(1304480768), // LD1Rv2d_POST |
1044 | 1.59k | UINT64_C(222349312), // LD1Rv2s |
1045 | 1.59k | UINT64_C(230737920), // LD1Rv2s_POST |
1046 | 1.59k | UINT64_C(222348288), // LD1Rv4h |
1047 | 1.59k | UINT64_C(230736896), // LD1Rv4h_POST |
1048 | 1.59k | UINT64_C(1296091136), // LD1Rv4s |
1049 | 1.59k | UINT64_C(1304479744), // LD1Rv4s_POST |
1050 | 1.59k | UINT64_C(222347264), // LD1Rv8b |
1051 | 1.59k | UINT64_C(230735872), // LD1Rv8b_POST |
1052 | 1.59k | UINT64_C(1296090112), // LD1Rv8h |
1053 | 1.59k | UINT64_C(1304478720), // LD1Rv8h_POST |
1054 | 1.59k | UINT64_C(1279287296), // LD1Threev16b |
1055 | 1.59k | UINT64_C(1287675904), // LD1Threev16b_POST |
1056 | 1.59k | UINT64_C(205548544), // LD1Threev1d |
1057 | 1.59k | UINT64_C(213937152), // LD1Threev1d_POST |
1058 | 1.59k | UINT64_C(1279290368), // LD1Threev2d |
1059 | 1.59k | UINT64_C(1287678976), // LD1Threev2d_POST |
1060 | 1.59k | UINT64_C(205547520), // LD1Threev2s |
1061 | 1.59k | UINT64_C(213936128), // LD1Threev2s_POST |
1062 | 1.59k | UINT64_C(205546496), // LD1Threev4h |
1063 | 1.59k | UINT64_C(213935104), // LD1Threev4h_POST |
1064 | 1.59k | UINT64_C(1279289344), // LD1Threev4s |
1065 | 1.59k | UINT64_C(1287677952), // LD1Threev4s_POST |
1066 | 1.59k | UINT64_C(205545472), // LD1Threev8b |
1067 | 1.59k | UINT64_C(213934080), // LD1Threev8b_POST |
1068 | 1.59k | UINT64_C(1279288320), // LD1Threev8h |
1069 | 1.59k | UINT64_C(1287676928), // LD1Threev8h_POST |
1070 | 1.59k | UINT64_C(1279303680), // LD1Twov16b |
1071 | 1.59k | UINT64_C(1287692288), // LD1Twov16b_POST |
1072 | 1.59k | UINT64_C(205564928), // LD1Twov1d |
1073 | 1.59k | UINT64_C(213953536), // LD1Twov1d_POST |
1074 | 1.59k | UINT64_C(1279306752), // LD1Twov2d |
1075 | 1.59k | UINT64_C(1287695360), // LD1Twov2d_POST |
1076 | 1.59k | UINT64_C(205563904), // LD1Twov2s |
1077 | 1.59k | UINT64_C(213952512), // LD1Twov2s_POST |
1078 | 1.59k | UINT64_C(205562880), // LD1Twov4h |
1079 | 1.59k | UINT64_C(213951488), // LD1Twov4h_POST |
1080 | 1.59k | UINT64_C(1279305728), // LD1Twov4s |
1081 | 1.59k | UINT64_C(1287694336), // LD1Twov4s_POST |
1082 | 1.59k | UINT64_C(205561856), // LD1Twov8b |
1083 | 1.59k | UINT64_C(213950464), // LD1Twov8b_POST |
1084 | 1.59k | UINT64_C(1279304704), // LD1Twov8h |
1085 | 1.59k | UINT64_C(1287693312), // LD1Twov8h_POST |
1086 | 1.59k | UINT64_C(222314496), // LD1i16 |
1087 | 1.59k | UINT64_C(230703104), // LD1i16_POST |
1088 | 1.59k | UINT64_C(222330880), // LD1i32 |
1089 | 1.59k | UINT64_C(230719488), // LD1i32_POST |
1090 | 1.59k | UINT64_C(222331904), // LD1i64 |
1091 | 1.59k | UINT64_C(230720512), // LD1i64_POST |
1092 | 1.59k | UINT64_C(222298112), // LD1i8 |
1093 | 1.59k | UINT64_C(230686720), // LD1i8_POST |
1094 | 1.59k | UINT64_C(1298186240), // LD2Rv16b |
1095 | 1.59k | UINT64_C(1306574848), // LD2Rv16b_POST |
1096 | 1.59k | UINT64_C(224447488), // LD2Rv1d |
1097 | 1.59k | UINT64_C(232836096), // LD2Rv1d_POST |
1098 | 1.59k | UINT64_C(1298189312), // LD2Rv2d |
1099 | 1.59k | UINT64_C(1306577920), // LD2Rv2d_POST |
1100 | 1.59k | UINT64_C(224446464), // LD2Rv2s |
1101 | 1.59k | UINT64_C(232835072), // LD2Rv2s_POST |
1102 | 1.59k | UINT64_C(224445440), // LD2Rv4h |
1103 | 1.59k | UINT64_C(232834048), // LD2Rv4h_POST |
1104 | 1.59k | UINT64_C(1298188288), // LD2Rv4s |
1105 | 1.59k | UINT64_C(1306576896), // LD2Rv4s_POST |
1106 | 1.59k | UINT64_C(224444416), // LD2Rv8b |
1107 | 1.59k | UINT64_C(232833024), // LD2Rv8b_POST |
1108 | 1.59k | UINT64_C(1298187264), // LD2Rv8h |
1109 | 1.59k | UINT64_C(1306575872), // LD2Rv8h_POST |
1110 | 1.59k | UINT64_C(1279295488), // LD2Twov16b |
1111 | 1.59k | UINT64_C(1287684096), // LD2Twov16b_POST |
1112 | 1.59k | UINT64_C(1279298560), // LD2Twov2d |
1113 | 1.59k | UINT64_C(1287687168), // LD2Twov2d_POST |
1114 | 1.59k | UINT64_C(205555712), // LD2Twov2s |
1115 | 1.59k | UINT64_C(213944320), // LD2Twov2s_POST |
1116 | 1.59k | UINT64_C(205554688), // LD2Twov4h |
1117 | 1.59k | UINT64_C(213943296), // LD2Twov4h_POST |
1118 | 1.59k | UINT64_C(1279297536), // LD2Twov4s |
1119 | 1.59k | UINT64_C(1287686144), // LD2Twov4s_POST |
1120 | 1.59k | UINT64_C(205553664), // LD2Twov8b |
1121 | 1.59k | UINT64_C(213942272), // LD2Twov8b_POST |
1122 | 1.59k | UINT64_C(1279296512), // LD2Twov8h |
1123 | 1.59k | UINT64_C(1287685120), // LD2Twov8h_POST |
1124 | 1.59k | UINT64_C(224411648), // LD2i16 |
1125 | 1.59k | UINT64_C(232800256), // LD2i16_POST |
1126 | 1.59k | UINT64_C(224428032), // LD2i32 |
1127 | 1.59k | UINT64_C(232816640), // LD2i32_POST |
1128 | 1.59k | UINT64_C(224429056), // LD2i64 |
1129 | 1.59k | UINT64_C(232817664), // LD2i64_POST |
1130 | 1.59k | UINT64_C(224395264), // LD2i8 |
1131 | 1.59k | UINT64_C(232783872), // LD2i8_POST |
1132 | 1.59k | UINT64_C(1296097280), // LD3Rv16b |
1133 | 1.59k | UINT64_C(1304485888), // LD3Rv16b_POST |
1134 | 1.59k | UINT64_C(222358528), // LD3Rv1d |
1135 | 1.59k | UINT64_C(230747136), // LD3Rv1d_POST |
1136 | 1.59k | UINT64_C(1296100352), // LD3Rv2d |
1137 | 1.59k | UINT64_C(1304488960), // LD3Rv2d_POST |
1138 | 1.59k | UINT64_C(222357504), // LD3Rv2s |
1139 | 1.59k | UINT64_C(230746112), // LD3Rv2s_POST |
1140 | 1.59k | UINT64_C(222356480), // LD3Rv4h |
1141 | 1.59k | UINT64_C(230745088), // LD3Rv4h_POST |
1142 | 1.59k | UINT64_C(1296099328), // LD3Rv4s |
1143 | 1.59k | UINT64_C(1304487936), // LD3Rv4s_POST |
1144 | 1.59k | UINT64_C(222355456), // LD3Rv8b |
1145 | 1.59k | UINT64_C(230744064), // LD3Rv8b_POST |
1146 | 1.59k | UINT64_C(1296098304), // LD3Rv8h |
1147 | 1.59k | UINT64_C(1304486912), // LD3Rv8h_POST |
1148 | 1.59k | UINT64_C(1279279104), // LD3Threev16b |
1149 | 1.59k | UINT64_C(1287667712), // LD3Threev16b_POST |
1150 | 1.59k | UINT64_C(1279282176), // LD3Threev2d |
1151 | 1.59k | UINT64_C(1287670784), // LD3Threev2d_POST |
1152 | 1.59k | UINT64_C(205539328), // LD3Threev2s |
1153 | 1.59k | UINT64_C(213927936), // LD3Threev2s_POST |
1154 | 1.59k | UINT64_C(205538304), // LD3Threev4h |
1155 | 1.59k | UINT64_C(213926912), // LD3Threev4h_POST |
1156 | 1.59k | UINT64_C(1279281152), // LD3Threev4s |
1157 | 1.59k | UINT64_C(1287669760), // LD3Threev4s_POST |
1158 | 1.59k | UINT64_C(205537280), // LD3Threev8b |
1159 | 1.59k | UINT64_C(213925888), // LD3Threev8b_POST |
1160 | 1.59k | UINT64_C(1279280128), // LD3Threev8h |
1161 | 1.59k | UINT64_C(1287668736), // LD3Threev8h_POST |
1162 | 1.59k | UINT64_C(222322688), // LD3i16 |
1163 | 1.59k | UINT64_C(230711296), // LD3i16_POST |
1164 | 1.59k | UINT64_C(222339072), // LD3i32 |
1165 | 1.59k | UINT64_C(230727680), // LD3i32_POST |
1166 | 1.59k | UINT64_C(222340096), // LD3i64 |
1167 | 1.59k | UINT64_C(230728704), // LD3i64_POST |
1168 | 1.59k | UINT64_C(222306304), // LD3i8 |
1169 | 1.59k | UINT64_C(230694912), // LD3i8_POST |
1170 | 1.59k | UINT64_C(1279262720), // LD4Fourv16b |
1171 | 1.59k | UINT64_C(1287651328), // LD4Fourv16b_POST |
1172 | 1.59k | UINT64_C(1279265792), // LD4Fourv2d |
1173 | 1.59k | UINT64_C(1287654400), // LD4Fourv2d_POST |
1174 | 1.59k | UINT64_C(205522944), // LD4Fourv2s |
1175 | 1.59k | UINT64_C(213911552), // LD4Fourv2s_POST |
1176 | 1.59k | UINT64_C(205521920), // LD4Fourv4h |
1177 | 1.59k | UINT64_C(213910528), // LD4Fourv4h_POST |
1178 | 1.59k | UINT64_C(1279264768), // LD4Fourv4s |
1179 | 1.59k | UINT64_C(1287653376), // LD4Fourv4s_POST |
1180 | 1.59k | UINT64_C(205520896), // LD4Fourv8b |
1181 | 1.59k | UINT64_C(213909504), // LD4Fourv8b_POST |
1182 | 1.59k | UINT64_C(1279263744), // LD4Fourv8h |
1183 | 1.59k | UINT64_C(1287652352), // LD4Fourv8h_POST |
1184 | 1.59k | UINT64_C(1298194432), // LD4Rv16b |
1185 | 1.59k | UINT64_C(1306583040), // LD4Rv16b_POST |
1186 | 1.59k | UINT64_C(224455680), // LD4Rv1d |
1187 | 1.59k | UINT64_C(232844288), // LD4Rv1d_POST |
1188 | 1.59k | UINT64_C(1298197504), // LD4Rv2d |
1189 | 1.59k | UINT64_C(1306586112), // LD4Rv2d_POST |
1190 | 1.59k | UINT64_C(224454656), // LD4Rv2s |
1191 | 1.59k | UINT64_C(232843264), // LD4Rv2s_POST |
1192 | 1.59k | UINT64_C(224453632), // LD4Rv4h |
1193 | 1.59k | UINT64_C(232842240), // LD4Rv4h_POST |
1194 | 1.59k | UINT64_C(1298196480), // LD4Rv4s |
1195 | 1.59k | UINT64_C(1306585088), // LD4Rv4s_POST |
1196 | 1.59k | UINT64_C(224452608), // LD4Rv8b |
1197 | 1.59k | UINT64_C(232841216), // LD4Rv8b_POST |
1198 | 1.59k | UINT64_C(1298195456), // LD4Rv8h |
1199 | 1.59k | UINT64_C(1306584064), // LD4Rv8h_POST |
1200 | 1.59k | UINT64_C(224419840), // LD4i16 |
1201 | 1.59k | UINT64_C(232808448), // LD4i16_POST |
1202 | 1.59k | UINT64_C(224436224), // LD4i32 |
1203 | 1.59k | UINT64_C(232824832), // LD4i32_POST |
1204 | 1.59k | UINT64_C(224437248), // LD4i64 |
1205 | 1.59k | UINT64_C(232825856), // LD4i64_POST |
1206 | 1.59k | UINT64_C(224403456), // LD4i8 |
1207 | 1.59k | UINT64_C(232792064), // LD4i8_POST |
1208 | 1.59k | UINT64_C(954204160), // LDADDALb |
1209 | 1.59k | UINT64_C(4175429632), // LDADDALd |
1210 | 1.59k | UINT64_C(2027945984), // LDADDALh |
1211 | 1.59k | UINT64_C(3101687808), // LDADDALs |
1212 | 1.59k | UINT64_C(950009856), // LDADDAb |
1213 | 1.59k | UINT64_C(4171235328), // LDADDAd |
1214 | 1.59k | UINT64_C(2023751680), // LDADDAh |
1215 | 1.59k | UINT64_C(3097493504), // LDADDAs |
1216 | 1.59k | UINT64_C(945815552), // LDADDLb |
1217 | 1.59k | UINT64_C(4167041024), // LDADDLd |
1218 | 1.59k | UINT64_C(2019557376), // LDADDLh |
1219 | 1.59k | UINT64_C(3093299200), // LDADDLs |
1220 | 1.59k | UINT64_C(941621248), // LDADDb |
1221 | 1.59k | UINT64_C(4162846720), // LDADDd |
1222 | 1.59k | UINT64_C(2015363072), // LDADDh |
1223 | 1.59k | UINT64_C(3089104896), // LDADDs |
1224 | 1.59k | UINT64_C(148896768), // LDARB |
1225 | 1.59k | UINT64_C(1222638592), // LDARH |
1226 | 1.59k | UINT64_C(2296380416), // LDARW |
1227 | 1.59k | UINT64_C(3370122240), // LDARX |
1228 | 1.59k | UINT64_C(2288025600), // LDAXPW |
1229 | 1.59k | UINT64_C(3361767424), // LDAXPX |
1230 | 1.59k | UINT64_C(140508160), // LDAXRB |
1231 | 1.59k | UINT64_C(1214249984), // LDAXRH |
1232 | 1.59k | UINT64_C(2287991808), // LDAXRW |
1233 | 1.59k | UINT64_C(3361733632), // LDAXRX |
1234 | 1.59k | UINT64_C(954208256), // LDCLRALb |
1235 | 1.59k | UINT64_C(4175433728), // LDCLRALd |
1236 | 1.59k | UINT64_C(2027950080), // LDCLRALh |
1237 | 1.59k | UINT64_C(3101691904), // LDCLRALs |
1238 | 1.59k | UINT64_C(950013952), // LDCLRAb |
1239 | 1.59k | UINT64_C(4171239424), // LDCLRAd |
1240 | 1.59k | UINT64_C(2023755776), // LDCLRAh |
1241 | 1.59k | UINT64_C(3097497600), // LDCLRAs |
1242 | 1.59k | UINT64_C(945819648), // LDCLRLb |
1243 | 1.59k | UINT64_C(4167045120), // LDCLRLd |
1244 | 1.59k | UINT64_C(2019561472), // LDCLRLh |
1245 | 1.59k | UINT64_C(3093303296), // LDCLRLs |
1246 | 1.59k | UINT64_C(941625344), // LDCLRb |
1247 | 1.59k | UINT64_C(4162850816), // LDCLRd |
1248 | 1.59k | UINT64_C(2015367168), // LDCLRh |
1249 | 1.59k | UINT64_C(3089108992), // LDCLRs |
1250 | 1.59k | UINT64_C(954212352), // LDEORALb |
1251 | 1.59k | UINT64_C(4175437824), // LDEORALd |
1252 | 1.59k | UINT64_C(2027954176), // LDEORALh |
1253 | 1.59k | UINT64_C(3101696000), // LDEORALs |
1254 | 1.59k | UINT64_C(950018048), // LDEORAb |
1255 | 1.59k | UINT64_C(4171243520), // LDEORAd |
1256 | 1.59k | UINT64_C(2023759872), // LDEORAh |
1257 | 1.59k | UINT64_C(3097501696), // LDEORAs |
1258 | 1.59k | UINT64_C(945823744), // LDEORLb |
1259 | 1.59k | UINT64_C(4167049216), // LDEORLd |
1260 | 1.59k | UINT64_C(2019565568), // LDEORLh |
1261 | 1.59k | UINT64_C(3093307392), // LDEORLs |
1262 | 1.59k | UINT64_C(941629440), // LDEORb |
1263 | 1.59k | UINT64_C(4162854912), // LDEORd |
1264 | 1.59k | UINT64_C(2015371264), // LDEORh |
1265 | 1.59k | UINT64_C(3089113088), // LDEORs |
1266 | 1.59k | UINT64_C(148864000), // LDLARB |
1267 | 1.59k | UINT64_C(1222605824), // LDLARH |
1268 | 1.59k | UINT64_C(2296347648), // LDLARW |
1269 | 1.59k | UINT64_C(3370089472), // LDLARX |
1270 | 1.59k | UINT64_C(1816133632), // LDNPDi |
1271 | 1.59k | UINT64_C(2889875456), // LDNPQi |
1272 | 1.59k | UINT64_C(742391808), // LDNPSi |
1273 | 1.59k | UINT64_C(675282944), // LDNPWi |
1274 | 1.59k | UINT64_C(2822766592), // LDNPXi |
1275 | 1.59k | UINT64_C(1832910848), // LDPDi |
1276 | 1.59k | UINT64_C(1824522240), // LDPDpost |
1277 | 1.59k | UINT64_C(1841299456), // LDPDpre |
1278 | 1.59k | UINT64_C(2906652672), // LDPQi |
1279 | 1.59k | UINT64_C(2898264064), // LDPQpost |
1280 | 1.59k | UINT64_C(2915041280), // LDPQpre |
1281 | 1.59k | UINT64_C(1765801984), // LDPSWi |
1282 | 1.59k | UINT64_C(1757413376), // LDPSWpost |
1283 | 1.59k | UINT64_C(1774190592), // LDPSWpre |
1284 | 1.59k | UINT64_C(759169024), // LDPSi |
1285 | 1.59k | UINT64_C(750780416), // LDPSpost |
1286 | 1.59k | UINT64_C(767557632), // LDPSpre |
1287 | 1.59k | UINT64_C(692060160), // LDPWi |
1288 | 1.59k | UINT64_C(683671552), // LDPWpost |
1289 | 1.59k | UINT64_C(700448768), // LDPWpre |
1290 | 1.59k | UINT64_C(2839543808), // LDPXi |
1291 | 1.59k | UINT64_C(2831155200), // LDPXpost |
1292 | 1.59k | UINT64_C(2847932416), // LDPXpre |
1293 | 1.59k | UINT64_C(943719424), // LDRBBpost |
1294 | 1.59k | UINT64_C(943721472), // LDRBBpre |
1295 | 1.59k | UINT64_C(945833984), // LDRBBroW |
1296 | 1.59k | UINT64_C(945842176), // LDRBBroX |
1297 | 1.59k | UINT64_C(960495616), // LDRBBui |
1298 | 1.59k | UINT64_C(1010828288), // LDRBpost |
1299 | 1.59k | UINT64_C(1010830336), // LDRBpre |
1300 | 1.59k | UINT64_C(1012942848), // LDRBroW |
1301 | 1.59k | UINT64_C(1012951040), // LDRBroX |
1302 | 1.59k | UINT64_C(1027604480), // LDRBui |
1303 | 1.59k | UINT64_C(1543503872), // LDRDl |
1304 | 1.59k | UINT64_C(4232053760), // LDRDpost |
1305 | 1.59k | UINT64_C(4232055808), // LDRDpre |
1306 | 1.59k | UINT64_C(4234168320), // LDRDroW |
1307 | 1.59k | UINT64_C(4234176512), // LDRDroX |
1308 | 1.59k | UINT64_C(4248829952), // LDRDui |
1309 | 1.59k | UINT64_C(2017461248), // LDRHHpost |
1310 | 1.59k | UINT64_C(2017463296), // LDRHHpre |
1311 | 1.59k | UINT64_C(2019575808), // LDRHHroW |
1312 | 1.59k | UINT64_C(2019584000), // LDRHHroX |
1313 | 1.59k | UINT64_C(2034237440), // LDRHHui |
1314 | 1.59k | UINT64_C(2084570112), // LDRHpost |
1315 | 1.59k | UINT64_C(2084572160), // LDRHpre |
1316 | 1.59k | UINT64_C(2086684672), // LDRHroW |
1317 | 1.59k | UINT64_C(2086692864), // LDRHroX |
1318 | 1.59k | UINT64_C(2101346304), // LDRHui |
1319 | 1.59k | UINT64_C(2617245696), // LDRQl |
1320 | 1.59k | UINT64_C(1019216896), // LDRQpost |
1321 | 1.59k | UINT64_C(1019218944), // LDRQpre |
1322 | 1.59k | UINT64_C(1021331456), // LDRQroW |
1323 | 1.59k | UINT64_C(1021339648), // LDRQroX |
1324 | 1.59k | UINT64_C(1035993088), // LDRQui |
1325 | 1.59k | UINT64_C(952108032), // LDRSBWpost |
1326 | 1.59k | UINT64_C(952110080), // LDRSBWpre |
1327 | 1.59k | UINT64_C(954222592), // LDRSBWroW |
1328 | 1.59k | UINT64_C(954230784), // LDRSBWroX |
1329 | 1.59k | UINT64_C(968884224), // LDRSBWui |
1330 | 1.59k | UINT64_C(947913728), // LDRSBXpost |
1331 | 1.59k | UINT64_C(947915776), // LDRSBXpre |
1332 | 1.59k | UINT64_C(950028288), // LDRSBXroW |
1333 | 1.59k | UINT64_C(950036480), // LDRSBXroX |
1334 | 1.59k | UINT64_C(964689920), // LDRSBXui |
1335 | 1.59k | UINT64_C(2025849856), // LDRSHWpost |
1336 | 1.59k | UINT64_C(2025851904), // LDRSHWpre |
1337 | 1.59k | UINT64_C(2027964416), // LDRSHWroW |
1338 | 1.59k | UINT64_C(2027972608), // LDRSHWroX |
1339 | 1.59k | UINT64_C(2042626048), // LDRSHWui |
1340 | 1.59k | UINT64_C(2021655552), // LDRSHXpost |
1341 | 1.59k | UINT64_C(2021657600), // LDRSHXpre |
1342 | 1.59k | UINT64_C(2023770112), // LDRSHXroW |
1343 | 1.59k | UINT64_C(2023778304), // LDRSHXroX |
1344 | 1.59k | UINT64_C(2038431744), // LDRSHXui |
1345 | 1.59k | UINT64_C(2550136832), // LDRSWl |
1346 | 1.59k | UINT64_C(3095397376), // LDRSWpost |
1347 | 1.59k | UINT64_C(3095399424), // LDRSWpre |
1348 | 1.59k | UINT64_C(3097511936), // LDRSWroW |
1349 | 1.59k | UINT64_C(3097520128), // LDRSWroX |
1350 | 1.59k | UINT64_C(3112173568), // LDRSWui |
1351 | 1.59k | UINT64_C(469762048), // LDRSl |
1352 | 1.59k | UINT64_C(3158311936), // LDRSpost |
1353 | 1.59k | UINT64_C(3158313984), // LDRSpre |
1354 | 1.59k | UINT64_C(3160426496), // LDRSroW |
1355 | 1.59k | UINT64_C(3160434688), // LDRSroX |
1356 | 1.59k | UINT64_C(3175088128), // LDRSui |
1357 | 1.59k | UINT64_C(402653184), // LDRWl |
1358 | 1.59k | UINT64_C(3091203072), // LDRWpost |
1359 | 1.59k | UINT64_C(3091205120), // LDRWpre |
1360 | 1.59k | UINT64_C(3093317632), // LDRWroW |
1361 | 1.59k | UINT64_C(3093325824), // LDRWroX |
1362 | 1.59k | UINT64_C(3107979264), // LDRWui |
1363 | 1.59k | UINT64_C(1476395008), // LDRXl |
1364 | 1.59k | UINT64_C(4164944896), // LDRXpost |
1365 | 1.59k | UINT64_C(4164946944), // LDRXpre |
1366 | 1.59k | UINT64_C(4167059456), // LDRXroW |
1367 | 1.59k | UINT64_C(4167067648), // LDRXroX |
1368 | 1.59k | UINT64_C(4181721088), // LDRXui |
1369 | 1.59k | UINT64_C(954216448), // LDSETALb |
1370 | 1.59k | UINT64_C(4175441920), // LDSETALd |
1371 | 1.59k | UINT64_C(2027958272), // LDSETALh |
1372 | 1.59k | UINT64_C(3101700096), // LDSETALs |
1373 | 1.59k | UINT64_C(950022144), // LDSETAb |
1374 | 1.59k | UINT64_C(4171247616), // LDSETAd |
1375 | 1.59k | UINT64_C(2023763968), // LDSETAh |
1376 | 1.59k | UINT64_C(3097505792), // LDSETAs |
1377 | 1.59k | UINT64_C(945827840), // LDSETLb |
1378 | 1.59k | UINT64_C(4167053312), // LDSETLd |
1379 | 1.59k | UINT64_C(2019569664), // LDSETLh |
1380 | 1.59k | UINT64_C(3093311488), // LDSETLs |
1381 | 1.59k | UINT64_C(941633536), // LDSETb |
1382 | 1.59k | UINT64_C(4162859008), // LDSETd |
1383 | 1.59k | UINT64_C(2015375360), // LDSETh |
1384 | 1.59k | UINT64_C(3089117184), // LDSETs |
1385 | 1.59k | UINT64_C(954220544), // LDSMAXALb |
1386 | 1.59k | UINT64_C(4175446016), // LDSMAXALd |
1387 | 1.59k | UINT64_C(2027962368), // LDSMAXALh |
1388 | 1.59k | UINT64_C(3101704192), // LDSMAXALs |
1389 | 1.59k | UINT64_C(950026240), // LDSMAXAb |
1390 | 1.59k | UINT64_C(4171251712), // LDSMAXAd |
1391 | 1.59k | UINT64_C(2023768064), // LDSMAXAh |
1392 | 1.59k | UINT64_C(3097509888), // LDSMAXAs |
1393 | 1.59k | UINT64_C(945831936), // LDSMAXLb |
1394 | 1.59k | UINT64_C(4167057408), // LDSMAXLd |
1395 | 1.59k | UINT64_C(2019573760), // LDSMAXLh |
1396 | 1.59k | UINT64_C(3093315584), // LDSMAXLs |
1397 | 1.59k | UINT64_C(941637632), // LDSMAXb |
1398 | 1.59k | UINT64_C(4162863104), // LDSMAXd |
1399 | 1.59k | UINT64_C(2015379456), // LDSMAXh |
1400 | 1.59k | UINT64_C(3089121280), // LDSMAXs |
1401 | 1.59k | UINT64_C(954224640), // LDSMINALb |
1402 | 1.59k | UINT64_C(4175450112), // LDSMINALd |
1403 | 1.59k | UINT64_C(2027966464), // LDSMINALh |
1404 | 1.59k | UINT64_C(3101708288), // LDSMINALs |
1405 | 1.59k | UINT64_C(950030336), // LDSMINAb |
1406 | 1.59k | UINT64_C(4171255808), // LDSMINAd |
1407 | 1.59k | UINT64_C(2023772160), // LDSMINAh |
1408 | 1.59k | UINT64_C(3097513984), // LDSMINAs |
1409 | 1.59k | UINT64_C(945836032), // LDSMINLb |
1410 | 1.59k | UINT64_C(4167061504), // LDSMINLd |
1411 | 1.59k | UINT64_C(2019577856), // LDSMINLh |
1412 | 1.59k | UINT64_C(3093319680), // LDSMINLs |
1413 | 1.59k | UINT64_C(941641728), // LDSMINb |
1414 | 1.59k | UINT64_C(4162867200), // LDSMINd |
1415 | 1.59k | UINT64_C(2015383552), // LDSMINh |
1416 | 1.59k | UINT64_C(3089125376), // LDSMINs |
1417 | 1.59k | UINT64_C(943720448), // LDTRBi |
1418 | 1.59k | UINT64_C(2017462272), // LDTRHi |
1419 | 1.59k | UINT64_C(952109056), // LDTRSBWi |
1420 | 1.59k | UINT64_C(947914752), // LDTRSBXi |
1421 | 1.59k | UINT64_C(2025850880), // LDTRSHWi |
1422 | 1.59k | UINT64_C(2021656576), // LDTRSHXi |
1423 | 1.59k | UINT64_C(3095398400), // LDTRSWi |
1424 | 1.59k | UINT64_C(3091204096), // LDTRWi |
1425 | 1.59k | UINT64_C(4164945920), // LDTRXi |
1426 | 1.59k | UINT64_C(954228736), // LDUMAXALb |
1427 | 1.59k | UINT64_C(4175454208), // LDUMAXALd |
1428 | 1.59k | UINT64_C(2027970560), // LDUMAXALh |
1429 | 1.59k | UINT64_C(3101712384), // LDUMAXALs |
1430 | 1.59k | UINT64_C(950034432), // LDUMAXAb |
1431 | 1.59k | UINT64_C(4171259904), // LDUMAXAd |
1432 | 1.59k | UINT64_C(2023776256), // LDUMAXAh |
1433 | 1.59k | UINT64_C(3097518080), // LDUMAXAs |
1434 | 1.59k | UINT64_C(945840128), // LDUMAXLb |
1435 | 1.59k | UINT64_C(4167065600), // LDUMAXLd |
1436 | 1.59k | UINT64_C(2019581952), // LDUMAXLh |
1437 | 1.59k | UINT64_C(3093323776), // LDUMAXLs |
1438 | 1.59k | UINT64_C(941645824), // LDUMAXb |
1439 | 1.59k | UINT64_C(4162871296), // LDUMAXd |
1440 | 1.59k | UINT64_C(2015387648), // LDUMAXh |
1441 | 1.59k | UINT64_C(3089129472), // LDUMAXs |
1442 | 1.59k | UINT64_C(954232832), // LDUMINALb |
1443 | 1.59k | UINT64_C(4175458304), // LDUMINALd |
1444 | 1.59k | UINT64_C(2027974656), // LDUMINALh |
1445 | 1.59k | UINT64_C(3101716480), // LDUMINALs |
1446 | 1.59k | UINT64_C(950038528), // LDUMINAb |
1447 | 1.59k | UINT64_C(4171264000), // LDUMINAd |
1448 | 1.59k | UINT64_C(2023780352), // LDUMINAh |
1449 | 1.59k | UINT64_C(3097522176), // LDUMINAs |
1450 | 1.59k | UINT64_C(945844224), // LDUMINLb |
1451 | 1.59k | UINT64_C(4167069696), // LDUMINLd |
1452 | 1.59k | UINT64_C(2019586048), // LDUMINLh |
1453 | 1.59k | UINT64_C(3093327872), // LDUMINLs |
1454 | 1.59k | UINT64_C(941649920), // LDUMINb |
1455 | 1.59k | UINT64_C(4162875392), // LDUMINd |
1456 | 1.59k | UINT64_C(2015391744), // LDUMINh |
1457 | 1.59k | UINT64_C(3089133568), // LDUMINs |
1458 | 1.59k | UINT64_C(943718400), // LDURBBi |
1459 | 1.59k | UINT64_C(1010827264), // LDURBi |
1460 | 1.59k | UINT64_C(4232052736), // LDURDi |
1461 | 1.59k | UINT64_C(2017460224), // LDURHHi |
1462 | 1.59k | UINT64_C(2084569088), // LDURHi |
1463 | 1.59k | UINT64_C(1019215872), // LDURQi |
1464 | 1.59k | UINT64_C(952107008), // LDURSBWi |
1465 | 1.59k | UINT64_C(947912704), // LDURSBXi |
1466 | 1.59k | UINT64_C(2025848832), // LDURSHWi |
1467 | 1.59k | UINT64_C(2021654528), // LDURSHXi |
1468 | 1.59k | UINT64_C(3095396352), // LDURSWi |
1469 | 1.59k | UINT64_C(3158310912), // LDURSi |
1470 | 1.59k | UINT64_C(3091202048), // LDURWi |
1471 | 1.59k | UINT64_C(4164943872), // LDURXi |
1472 | 1.59k | UINT64_C(2287992832), // LDXPW |
1473 | 1.59k | UINT64_C(3361734656), // LDXPX |
1474 | 1.59k | UINT64_C(140475392), // LDXRB |
1475 | 1.59k | UINT64_C(1214217216), // LDXRH |
1476 | 1.59k | UINT64_C(2287959040), // LDXRW |
1477 | 1.59k | UINT64_C(3361700864), // LDXRX |
1478 | 1.59k | UINT64_C(0), // LOADgot |
1479 | 1.59k | UINT64_C(448798720), // LSLVWr |
1480 | 1.59k | UINT64_C(2596282368), // LSLVXr |
1481 | 1.59k | UINT64_C(448799744), // LSRVWr |
1482 | 1.59k | UINT64_C(2596283392), // LSRVXr |
1483 | 1.59k | UINT64_C(452984832), // MADDWrrr |
1484 | 1.59k | UINT64_C(2600468480), // MADDXrrr |
1485 | 1.59k | UINT64_C(1310757888), // MLAv16i8 |
1486 | 1.59k | UINT64_C(245404672), // MLAv2i32 |
1487 | 1.59k | UINT64_C(796917760), // MLAv2i32_indexed |
1488 | 1.59k | UINT64_C(241210368), // MLAv4i16 |
1489 | 1.59k | UINT64_C(792723456), // MLAv4i16_indexed |
1490 | 1.59k | UINT64_C(1319146496), // MLAv4i32 |
1491 | 1.59k | UINT64_C(1870659584), // MLAv4i32_indexed |
1492 | 1.59k | UINT64_C(1314952192), // MLAv8i16 |
1493 | 1.59k | UINT64_C(1866465280), // MLAv8i16_indexed |
1494 | 1.59k | UINT64_C(237016064), // MLAv8i8 |
1495 | 1.59k | UINT64_C(1847628800), // MLSv16i8 |
1496 | 1.59k | UINT64_C(782275584), // MLSv2i32 |
1497 | 1.59k | UINT64_C(796934144), // MLSv2i32_indexed |
1498 | 1.59k | UINT64_C(778081280), // MLSv4i16 |
1499 | 1.59k | UINT64_C(792739840), // MLSv4i16_indexed |
1500 | 1.59k | UINT64_C(1856017408), // MLSv4i32 |
1501 | 1.59k | UINT64_C(1870675968), // MLSv4i32_indexed |
1502 | 1.59k | UINT64_C(1851823104), // MLSv8i16 |
1503 | 1.59k | UINT64_C(1866481664), // MLSv8i16_indexed |
1504 | 1.59k | UINT64_C(773886976), // MLSv8i8 |
1505 | 1.59k | UINT64_C(788587520), // MOVID |
1506 | 1.59k | UINT64_C(1325458432), // MOVIv16b_ns |
1507 | 1.59k | UINT64_C(1862329344), // MOVIv2d_ns |
1508 | 1.59k | UINT64_C(251659264), // MOVIv2i32 |
1509 | 1.59k | UINT64_C(251708416), // MOVIv2s_msl |
1510 | 1.59k | UINT64_C(251692032), // MOVIv4i16 |
1511 | 1.59k | UINT64_C(1325401088), // MOVIv4i32 |
1512 | 1.59k | UINT64_C(1325450240), // MOVIv4s_msl |
1513 | 1.59k | UINT64_C(251716608), // MOVIv8b_ns |
1514 | 1.59k | UINT64_C(1325433856), // MOVIv8i16 |
1515 | 1.59k | UINT64_C(1920991232), // MOVKWi |
1516 | 1.59k | UINT64_C(4068474880), // MOVKXi |
1517 | 1.59k | UINT64_C(310378496), // MOVNWi |
1518 | 1.59k | UINT64_C(2457862144), // MOVNXi |
1519 | 1.59k | UINT64_C(1384120320), // MOVZWi |
1520 | 1.59k | UINT64_C(3531603968), // MOVZXi |
1521 | 1.59k | UINT64_C(0), // MOVaddr |
1522 | 1.59k | UINT64_C(0), // MOVaddrBA |
1523 | 1.59k | UINT64_C(0), // MOVaddrCP |
1524 | 1.59k | UINT64_C(0), // MOVaddrEXT |
1525 | 1.59k | UINT64_C(0), // MOVaddrJT |
1526 | 1.59k | UINT64_C(0), // MOVaddrTLS |
1527 | 1.59k | UINT64_C(0), // MOVi32imm |
1528 | 1.59k | UINT64_C(0), // MOVi64imm |
1529 | 1.59k | UINT64_C(3575644160), // MRS |
1530 | 1.59k | UINT64_C(3573547008), // MSR |
1531 | 1.59k | UINT64_C(3573563423), // MSRpstateImm1 |
1532 | 1.59k | UINT64_C(3573563423), // MSRpstateImm4 |
1533 | 1.59k | UINT64_C(453017600), // MSUBWrrr |
1534 | 1.59k | UINT64_C(2600501248), // MSUBXrrr |
1535 | 1.59k | UINT64_C(1310759936), // MULv16i8 |
1536 | 1.59k | UINT64_C(245406720), // MULv2i32 |
1537 | 1.59k | UINT64_C(260079616), // MULv2i32_indexed |
1538 | 1.59k | UINT64_C(241212416), // MULv4i16 |
1539 | 1.59k | UINT64_C(255885312), // MULv4i16_indexed |
1540 | 1.59k | UINT64_C(1319148544), // MULv4i32 |
1541 | 1.59k | UINT64_C(1333821440), // MULv4i32_indexed |
1542 | 1.59k | UINT64_C(1314954240), // MULv8i16 |
1543 | 1.59k | UINT64_C(1329627136), // MULv8i16_indexed |
1544 | 1.59k | UINT64_C(237018112), // MULv8i8 |
1545 | 1.59k | UINT64_C(788530176), // MVNIv2i32 |
1546 | 1.59k | UINT64_C(788579328), // MVNIv2s_msl |
1547 | 1.59k | UINT64_C(788562944), // MVNIv4i16 |
1548 | 1.59k | UINT64_C(1862272000), // MVNIv4i32 |
1549 | 1.59k | UINT64_C(1862321152), // MVNIv4s_msl |
1550 | 1.59k | UINT64_C(1862304768), // MVNIv8i16 |
1551 | 1.59k | UINT64_C(1847638016), // NEGv16i8 |
1552 | 1.59k | UINT64_C(2128656384), // NEGv1i64 |
1553 | 1.59k | UINT64_C(782284800), // NEGv2i32 |
1554 | 1.59k | UINT64_C(1860220928), // NEGv2i64 |
1555 | 1.59k | UINT64_C(778090496), // NEGv4i16 |
1556 | 1.59k | UINT64_C(1856026624), // NEGv4i32 |
1557 | 1.59k | UINT64_C(1851832320), // NEGv8i16 |
1558 | 1.59k | UINT64_C(773896192), // NEGv8i8 |
1559 | 1.59k | UINT64_C(1847613440), // NOTv16i8 |
1560 | 1.59k | UINT64_C(773871616), // NOTv8i8 |
1561 | 1.59k | UINT64_C(0), // ORNWrr |
1562 | 1.59k | UINT64_C(706740224), // ORNWrs |
1563 | 1.59k | UINT64_C(0), // ORNXrr |
1564 | 1.59k | UINT64_C(2854223872), // ORNXrs |
1565 | 1.59k | UINT64_C(1323310080), // ORNv16i8 |
1566 | 1.59k | UINT64_C(249568256), // ORNv8i8 |
1567 | 1.59k | UINT64_C(838860800), // ORRWri |
1568 | 1.59k | UINT64_C(0), // ORRWrr |
1569 | 1.59k | UINT64_C(704643072), // ORRWrs |
1570 | 1.59k | UINT64_C(2986344448), // ORRXri |
1571 | 1.59k | UINT64_C(0), // ORRXrr |
1572 | 1.59k | UINT64_C(2852126720), // ORRXrs |
1573 | 1.59k | UINT64_C(1319115776), // ORRv16i8 |
1574 | 1.59k | UINT64_C(251663360), // ORRv2i32 |
1575 | 1.59k | UINT64_C(251696128), // ORRv4i16 |
1576 | 1.59k | UINT64_C(1325405184), // ORRv4i32 |
1577 | 1.59k | UINT64_C(1325437952), // ORRv8i16 |
1578 | 1.59k | UINT64_C(245373952), // ORRv8i8 |
1579 | 1.59k | UINT64_C(1310777344), // PMULLv16i8 |
1580 | 1.59k | UINT64_C(249618432), // PMULLv1i64 |
1581 | 1.59k | UINT64_C(1323360256), // PMULLv2i64 |
1582 | 1.59k | UINT64_C(237035520), // PMULLv8i8 |
1583 | 1.59k | UINT64_C(1847630848), // PMULv16i8 |
1584 | 1.59k | UINT64_C(773889024), // PMULv8i8 |
1585 | 1.59k | UINT64_C(3623878656), // PRFMl |
1586 | 1.59k | UINT64_C(4171253760), // PRFMroW |
1587 | 1.59k | UINT64_C(4171261952), // PRFMroX |
1588 | 1.59k | UINT64_C(4185915392), // PRFMui |
1589 | 1.59k | UINT64_C(4169138176), // PRFUMi |
1590 | 1.59k | UINT64_C(782254080), // RADDHNv2i64_v2i32 |
1591 | 1.59k | UINT64_C(1855995904), // RADDHNv2i64_v4i32 |
1592 | 1.59k | UINT64_C(778059776), // RADDHNv4i32_v4i16 |
1593 | 1.59k | UINT64_C(1851801600), // RADDHNv4i32_v8i16 |
1594 | 1.59k | UINT64_C(1847607296), // RADDHNv8i16_v16i8 |
1595 | 1.59k | UINT64_C(773865472), // RADDHNv8i16_v8i8 |
1596 | 1.59k | UINT64_C(1522532352), // RBITWr |
1597 | 1.59k | UINT64_C(3670016000), // RBITXr |
1598 | 1.59k | UINT64_C(1851807744), // RBITv16i8 |
1599 | 1.59k | UINT64_C(778065920), // RBITv8i8 |
1600 | 1.59k | UINT64_C(3596550144), // RET |
1601 | 1.59k | UINT64_C(0), // RET_ReallyLR |
1602 | 1.59k | UINT64_C(1522533376), // REV16Wr |
1603 | 1.59k | UINT64_C(3670017024), // REV16Xr |
1604 | 1.59k | UINT64_C(1310726144), // REV16v16i8 |
1605 | 1.59k | UINT64_C(236984320), // REV16v8i8 |
1606 | 1.59k | UINT64_C(3670018048), // REV32Xr |
1607 | 1.59k | UINT64_C(1847592960), // REV32v16i8 |
1608 | 1.59k | UINT64_C(778045440), // REV32v4i16 |
1609 | 1.59k | UINT64_C(1851787264), // REV32v8i16 |
1610 | 1.59k | UINT64_C(773851136), // REV32v8i8 |
1611 | 1.59k | UINT64_C(1310722048), // REV64v16i8 |
1612 | 1.59k | UINT64_C(245368832), // REV64v2i32 |
1613 | 1.59k | UINT64_C(241174528), // REV64v4i16 |
1614 | 1.59k | UINT64_C(1319110656), // REV64v4i32 |
1615 | 1.59k | UINT64_C(1314916352), // REV64v8i16 |
1616 | 1.59k | UINT64_C(236980224), // REV64v8i8 |
1617 | 1.59k | UINT64_C(1522534400), // REVWr |
1618 | 1.59k | UINT64_C(3670019072), // REVXr |
1619 | 1.59k | UINT64_C(448801792), // RORVWr |
1620 | 1.59k | UINT64_C(2596285440), // RORVXr |
1621 | 1.59k | UINT64_C(1325960192), // RSHRNv16i8_shift |
1622 | 1.59k | UINT64_C(253791232), // RSHRNv2i32_shift |
1623 | 1.59k | UINT64_C(252742656), // RSHRNv4i16_shift |
1624 | 1.59k | UINT64_C(1327533056), // RSHRNv4i32_shift |
1625 | 1.59k | UINT64_C(1326484480), // RSHRNv8i16_shift |
1626 | 1.59k | UINT64_C(252218368), // RSHRNv8i8_shift |
1627 | 1.59k | UINT64_C(782262272), // RSUBHNv2i64_v2i32 |
1628 | 1.59k | UINT64_C(1856004096), // RSUBHNv2i64_v4i32 |
1629 | 1.59k | UINT64_C(778067968), // RSUBHNv4i32_v4i16 |
1630 | 1.59k | UINT64_C(1851809792), // RSUBHNv4i32_v8i16 |
1631 | 1.59k | UINT64_C(1847615488), // RSUBHNv8i16_v16i8 |
1632 | 1.59k | UINT64_C(773873664), // RSUBHNv8i16_v8i8 |
1633 | 1.59k | UINT64_C(1310740480), // SABALv16i8_v8i16 |
1634 | 1.59k | UINT64_C(245387264), // SABALv2i32_v2i64 |
1635 | 1.59k | UINT64_C(241192960), // SABALv4i16_v4i32 |
1636 | 1.59k | UINT64_C(1319129088), // SABALv4i32_v2i64 |
1637 | 1.59k | UINT64_C(1314934784), // SABALv8i16_v4i32 |
1638 | 1.59k | UINT64_C(236998656), // SABALv8i8_v8i16 |
1639 | 1.59k | UINT64_C(1310751744), // SABAv16i8 |
1640 | 1.59k | UINT64_C(245398528), // SABAv2i32 |
1641 | 1.59k | UINT64_C(241204224), // SABAv4i16 |
1642 | 1.59k | UINT64_C(1319140352), // SABAv4i32 |
1643 | 1.59k | UINT64_C(1314946048), // SABAv8i16 |
1644 | 1.59k | UINT64_C(237009920), // SABAv8i8 |
1645 | 1.59k | UINT64_C(1310748672), // SABDLv16i8_v8i16 |
1646 | 1.59k | UINT64_C(245395456), // SABDLv2i32_v2i64 |
1647 | 1.59k | UINT64_C(241201152), // SABDLv4i16_v4i32 |
1648 | 1.59k | UINT64_C(1319137280), // SABDLv4i32_v2i64 |
1649 | 1.59k | UINT64_C(1314942976), // SABDLv8i16_v4i32 |
1650 | 1.59k | UINT64_C(237006848), // SABDLv8i8_v8i16 |
1651 | 1.59k | UINT64_C(1310749696), // SABDv16i8 |
1652 | 1.59k | UINT64_C(245396480), // SABDv2i32 |
1653 | 1.59k | UINT64_C(241202176), // SABDv4i16 |
1654 | 1.59k | UINT64_C(1319138304), // SABDv4i32 |
1655 | 1.59k | UINT64_C(1314944000), // SABDv8i16 |
1656 | 1.59k | UINT64_C(237007872), // SABDv8i8 |
1657 | 1.59k | UINT64_C(1310746624), // SADALPv16i8_v8i16 |
1658 | 1.59k | UINT64_C(245393408), // SADALPv2i32_v1i64 |
1659 | 1.59k | UINT64_C(241199104), // SADALPv4i16_v2i32 |
1660 | 1.59k | UINT64_C(1319135232), // SADALPv4i32_v2i64 |
1661 | 1.59k | UINT64_C(1314940928), // SADALPv8i16_v4i32 |
1662 | 1.59k | UINT64_C(237004800), // SADALPv8i8_v4i16 |
1663 | 1.59k | UINT64_C(1310730240), // SADDLPv16i8_v8i16 |
1664 | 1.59k | UINT64_C(245377024), // SADDLPv2i32_v1i64 |
1665 | 1.59k | UINT64_C(241182720), // SADDLPv4i16_v2i32 |
1666 | 1.59k | UINT64_C(1319118848), // SADDLPv4i32_v2i64 |
1667 | 1.59k | UINT64_C(1314924544), // SADDLPv8i16_v4i32 |
1668 | 1.59k | UINT64_C(236988416), // SADDLPv8i8_v4i16 |
1669 | 1.59k | UINT64_C(1311782912), // SADDLVv16i8v |
1670 | 1.59k | UINT64_C(242235392), // SADDLVv4i16v |
1671 | 1.59k | UINT64_C(1320171520), // SADDLVv4i32v |
1672 | 1.59k | UINT64_C(1315977216), // SADDLVv8i16v |
1673 | 1.59k | UINT64_C(238041088), // SADDLVv8i8v |
1674 | 1.59k | UINT64_C(1310720000), // SADDLv16i8_v8i16 |
1675 | 1.59k | UINT64_C(245366784), // SADDLv2i32_v2i64 |
1676 | 1.59k | UINT64_C(241172480), // SADDLv4i16_v4i32 |
1677 | 1.59k | UINT64_C(1319108608), // SADDLv4i32_v2i64 |
1678 | 1.59k | UINT64_C(1314914304), // SADDLv8i16_v4i32 |
1679 | 1.59k | UINT64_C(236978176), // SADDLv8i8_v8i16 |
1680 | 1.59k | UINT64_C(1310724096), // SADDWv16i8_v8i16 |
1681 | 1.59k | UINT64_C(245370880), // SADDWv2i32_v2i64 |
1682 | 1.59k | UINT64_C(241176576), // SADDWv4i16_v4i32 |
1683 | 1.59k | UINT64_C(1319112704), // SADDWv4i32_v2i64 |
1684 | 1.59k | UINT64_C(1314918400), // SADDWv8i16_v4i32 |
1685 | 1.59k | UINT64_C(236982272), // SADDWv8i8_v8i16 |
1686 | 1.59k | UINT64_C(2046820352), // SBCSWr |
1687 | 1.59k | UINT64_C(4194304000), // SBCSXr |
1688 | 1.59k | UINT64_C(1509949440), // SBCWr |
1689 | 1.59k | UINT64_C(3657433088), // SBCXr |
1690 | 1.59k | UINT64_C(318767104), // SBFMWri |
1691 | 1.59k | UINT64_C(2470445056), // SBFMXri |
1692 | 1.59k | UINT64_C(507674624), // SCVTFSWDri |
1693 | 1.59k | UINT64_C(516063232), // SCVTFSWHri |
1694 | 1.59k | UINT64_C(503480320), // SCVTFSWSri |
1695 | 1.59k | UINT64_C(2655125504), // SCVTFSXDri |
1696 | 1.59k | UINT64_C(2663514112), // SCVTFSXHri |
1697 | 1.59k | UINT64_C(2650931200), // SCVTFSXSri |
1698 | 1.59k | UINT64_C(509739008), // SCVTFUWDri |
1699 | 1.59k | UINT64_C(518127616), // SCVTFUWHri |
1700 | 1.59k | UINT64_C(505544704), // SCVTFUWSri |
1701 | 1.59k | UINT64_C(2657222656), // SCVTFUXDri |
1702 | 1.59k | UINT64_C(2665611264), // SCVTFUXHri |
1703 | 1.59k | UINT64_C(2653028352), // SCVTFUXSri |
1704 | 1.59k | UINT64_C(1598088192), // SCVTFd |
1705 | 1.59k | UINT64_C(1594942464), // SCVTFh |
1706 | 1.59k | UINT64_C(1595991040), // SCVTFs |
1707 | 1.59k | UINT64_C(1585043456), // SCVTFv1i16 |
1708 | 1.59k | UINT64_C(1579276288), // SCVTFv1i32 |
1709 | 1.59k | UINT64_C(1583470592), // SCVTFv1i64 |
1710 | 1.59k | UINT64_C(237099008), // SCVTFv2f32 |
1711 | 1.59k | UINT64_C(1315035136), // SCVTFv2f64 |
1712 | 1.59k | UINT64_C(253813760), // SCVTFv2i32_shift |
1713 | 1.59k | UINT64_C(1329652736), // SCVTFv2i64_shift |
1714 | 1.59k | UINT64_C(242866176), // SCVTFv4f16 |
1715 | 1.59k | UINT64_C(1310840832), // SCVTFv4f32 |
1716 | 1.59k | UINT64_C(252765184), // SCVTFv4i16_shift |
1717 | 1.59k | UINT64_C(1327555584), // SCVTFv4i32_shift |
1718 | 1.59k | UINT64_C(1316608000), // SCVTFv8f16 |
1719 | 1.59k | UINT64_C(1326507008), // SCVTFv8i16_shift |
1720 | 1.59k | UINT64_C(448793600), // SDIVWr |
1721 | 1.59k | UINT64_C(2596277248), // SDIVXr |
1722 | 1.59k | UINT64_C(448793600), // SDIV_IntWr |
1723 | 1.59k | UINT64_C(2596277248), // SDIV_IntXr |
1724 | 1.59k | UINT64_C(1577058304), // SHA1Crrr |
1725 | 1.59k | UINT64_C(1579681792), // SHA1Hrr |
1726 | 1.59k | UINT64_C(1577066496), // SHA1Mrrr |
1727 | 1.59k | UINT64_C(1577062400), // SHA1Prrr |
1728 | 1.59k | UINT64_C(1577070592), // SHA1SU0rrr |
1729 | 1.59k | UINT64_C(1579685888), // SHA1SU1rr |
1730 | 1.59k | UINT64_C(1577078784), // SHA256H2rrr |
1731 | 1.59k | UINT64_C(1577074688), // SHA256Hrrr |
1732 | 1.59k | UINT64_C(1579689984), // SHA256SU0rr |
1733 | 1.59k | UINT64_C(1577082880), // SHA256SU1rrr |
1734 | 1.59k | UINT64_C(1310721024), // SHADDv16i8 |
1735 | 1.59k | UINT64_C(245367808), // SHADDv2i32 |
1736 | 1.59k | UINT64_C(241173504), // SHADDv4i16 |
1737 | 1.59k | UINT64_C(1319109632), // SHADDv4i32 |
1738 | 1.59k | UINT64_C(1314915328), // SHADDv8i16 |
1739 | 1.59k | UINT64_C(236979200), // SHADDv8i8 |
1740 | 1.59k | UINT64_C(1847670784), // SHLLv16i8 |
1741 | 1.59k | UINT64_C(782317568), // SHLLv2i32 |
1742 | 1.59k | UINT64_C(778123264), // SHLLv4i16 |
1743 | 1.59k | UINT64_C(1856059392), // SHLLv4i32 |
1744 | 1.59k | UINT64_C(1851865088), // SHLLv8i16 |
1745 | 1.59k | UINT64_C(773928960), // SHLLv8i8 |
1746 | 1.59k | UINT64_C(1598051328), // SHLd |
1747 | 1.59k | UINT64_C(1325945856), // SHLv16i8_shift |
1748 | 1.59k | UINT64_C(253776896), // SHLv2i32_shift |
1749 | 1.59k | UINT64_C(1329615872), // SHLv2i64_shift |
1750 | 1.59k | UINT64_C(252728320), // SHLv4i16_shift |
1751 | 1.59k | UINT64_C(1327518720), // SHLv4i32_shift |
1752 | 1.59k | UINT64_C(1326470144), // SHLv8i16_shift |
1753 | 1.59k | UINT64_C(252204032), // SHLv8i8_shift |
1754 | 1.59k | UINT64_C(1325958144), // SHRNv16i8_shift |
1755 | 1.59k | UINT64_C(253789184), // SHRNv2i32_shift |
1756 | 1.59k | UINT64_C(252740608), // SHRNv4i16_shift |
1757 | 1.59k | UINT64_C(1327531008), // SHRNv4i32_shift |
1758 | 1.59k | UINT64_C(1326482432), // SHRNv8i16_shift |
1759 | 1.59k | UINT64_C(252216320), // SHRNv8i8_shift |
1760 | 1.59k | UINT64_C(1310729216), // SHSUBv16i8 |
1761 | 1.59k | UINT64_C(245376000), // SHSUBv2i32 |
1762 | 1.59k | UINT64_C(241181696), // SHSUBv4i16 |
1763 | 1.59k | UINT64_C(1319117824), // SHSUBv4i32 |
1764 | 1.59k | UINT64_C(1314923520), // SHSUBv8i16 |
1765 | 1.59k | UINT64_C(236987392), // SHSUBv8i8 |
1766 | 1.59k | UINT64_C(2134922240), // SLId |
1767 | 1.59k | UINT64_C(1862816768), // SLIv16i8_shift |
1768 | 1.59k | UINT64_C(790647808), // SLIv2i32_shift |
1769 | 1.59k | UINT64_C(1866486784), // SLIv2i64_shift |
1770 | 1.59k | UINT64_C(789599232), // SLIv4i16_shift |
1771 | 1.59k | UINT64_C(1864389632), // SLIv4i32_shift |
1772 | 1.59k | UINT64_C(1863341056), // SLIv8i16_shift |
1773 | 1.59k | UINT64_C(789074944), // SLIv8i8_shift |
1774 | 1.59k | UINT64_C(2602565632), // SMADDLrrr |
1775 | 1.59k | UINT64_C(1310761984), // SMAXPv16i8 |
1776 | 1.59k | UINT64_C(245408768), // SMAXPv2i32 |
1777 | 1.59k | UINT64_C(241214464), // SMAXPv4i16 |
1778 | 1.59k | UINT64_C(1319150592), // SMAXPv4i32 |
1779 | 1.59k | UINT64_C(1314956288), // SMAXPv8i16 |
1780 | 1.59k | UINT64_C(237020160), // SMAXPv8i8 |
1781 | 1.59k | UINT64_C(1311811584), // SMAXVv16i8v |
1782 | 1.59k | UINT64_C(242264064), // SMAXVv4i16v |
1783 | 1.59k | UINT64_C(1320200192), // SMAXVv4i32v |
1784 | 1.59k | UINT64_C(1316005888), // SMAXVv8i16v |
1785 | 1.59k | UINT64_C(238069760), // SMAXVv8i8v |
1786 | 1.59k | UINT64_C(1310745600), // SMAXv16i8 |
1787 | 1.59k | UINT64_C(245392384), // SMAXv2i32 |
1788 | 1.59k | UINT64_C(241198080), // SMAXv4i16 |
1789 | 1.59k | UINT64_C(1319134208), // SMAXv4i32 |
1790 | 1.59k | UINT64_C(1314939904), // SMAXv8i16 |
1791 | 1.59k | UINT64_C(237003776), // SMAXv8i8 |
1792 | 1.59k | UINT64_C(3556769795), // SMC |
1793 | 1.59k | UINT64_C(1310764032), // SMINPv16i8 |
1794 | 1.59k | UINT64_C(245410816), // SMINPv2i32 |
1795 | 1.59k | UINT64_C(241216512), // SMINPv4i16 |
1796 | 1.59k | UINT64_C(1319152640), // SMINPv4i32 |
1797 | 1.59k | UINT64_C(1314958336), // SMINPv8i16 |
1798 | 1.59k | UINT64_C(237022208), // SMINPv8i8 |
1799 | 1.59k | UINT64_C(1311877120), // SMINVv16i8v |
1800 | 1.59k | UINT64_C(242329600), // SMINVv4i16v |
1801 | 1.59k | UINT64_C(1320265728), // SMINVv4i32v |
1802 | 1.59k | UINT64_C(1316071424), // SMINVv8i16v |
1803 | 1.59k | UINT64_C(238135296), // SMINVv8i8v |
1804 | 1.59k | UINT64_C(1310747648), // SMINv16i8 |
1805 | 1.59k | UINT64_C(245394432), // SMINv2i32 |
1806 | 1.59k | UINT64_C(241200128), // SMINv4i16 |
1807 | 1.59k | UINT64_C(1319136256), // SMINv4i32 |
1808 | 1.59k | UINT64_C(1314941952), // SMINv8i16 |
1809 | 1.59k | UINT64_C(237005824), // SMINv8i8 |
1810 | 1.59k | UINT64_C(1310752768), // SMLALv16i8_v8i16 |
1811 | 1.59k | UINT64_C(260055040), // SMLALv2i32_indexed |
1812 | 1.59k | UINT64_C(245399552), // SMLALv2i32_v2i64 |
1813 | 1.59k | UINT64_C(255860736), // SMLALv4i16_indexed |
1814 | 1.59k | UINT64_C(241205248), // SMLALv4i16_v4i32 |
1815 | 1.59k | UINT64_C(1333796864), // SMLALv4i32_indexed |
1816 | 1.59k | UINT64_C(1319141376), // SMLALv4i32_v2i64 |
1817 | 1.59k | UINT64_C(1329602560), // SMLALv8i16_indexed |
1818 | 1.59k | UINT64_C(1314947072), // SMLALv8i16_v4i32 |
1819 | 1.59k | UINT64_C(237010944), // SMLALv8i8_v8i16 |
1820 | 1.59k | UINT64_C(1310760960), // SMLSLv16i8_v8i16 |
1821 | 1.59k | UINT64_C(260071424), // SMLSLv2i32_indexed |
1822 | 1.59k | UINT64_C(245407744), // SMLSLv2i32_v2i64 |
1823 | 1.59k | UINT64_C(255877120), // SMLSLv4i16_indexed |
1824 | 1.59k | UINT64_C(241213440), // SMLSLv4i16_v4i32 |
1825 | 1.59k | UINT64_C(1333813248), // SMLSLv4i32_indexed |
1826 | 1.59k | UINT64_C(1319149568), // SMLSLv4i32_v2i64 |
1827 | 1.59k | UINT64_C(1329618944), // SMLSLv8i16_indexed |
1828 | 1.59k | UINT64_C(1314955264), // SMLSLv8i16_v4i32 |
1829 | 1.59k | UINT64_C(237019136), // SMLSLv8i8_v8i16 |
1830 | 1.59k | UINT64_C(235023360), // SMOVvi16to32 |
1831 | 1.59k | UINT64_C(1308765184), // SMOVvi16to64 |
1832 | 1.59k | UINT64_C(1308896256), // SMOVvi32to64 |
1833 | 1.59k | UINT64_C(234957824), // SMOVvi8to32 |
1834 | 1.59k | UINT64_C(1308699648), // SMOVvi8to64 |
1835 | 1.59k | UINT64_C(2602598400), // SMSUBLrrr |
1836 | 1.59k | UINT64_C(2604662784), // SMULHrr |
1837 | 1.59k | UINT64_C(1310769152), // SMULLv16i8_v8i16 |
1838 | 1.59k | UINT64_C(260087808), // SMULLv2i32_indexed |
1839 | 1.59k | UINT64_C(245415936), // SMULLv2i32_v2i64 |
1840 | 1.59k | UINT64_C(255893504), // SMULLv4i16_indexed |
1841 | 1.59k | UINT64_C(241221632), // SMULLv4i16_v4i32 |
1842 | 1.59k | UINT64_C(1333829632), // SMULLv4i32_indexed |
1843 | 1.59k | UINT64_C(1319157760), // SMULLv4i32_v2i64 |
1844 | 1.59k | UINT64_C(1329635328), // SMULLv8i16_indexed |
1845 | 1.59k | UINT64_C(1314963456), // SMULLv8i16_v4i32 |
1846 | 1.59k | UINT64_C(237027328), // SMULLv8i8_v8i16 |
1847 | 1.59k | UINT64_C(1310750720), // SQABSv16i8 |
1848 | 1.59k | UINT64_C(1583380480), // SQABSv1i16 |
1849 | 1.59k | UINT64_C(1587574784), // SQABSv1i32 |
1850 | 1.59k | UINT64_C(1591769088), // SQABSv1i64 |
1851 | 1.59k | UINT64_C(1579186176), // SQABSv1i8 |
1852 | 1.59k | UINT64_C(245397504), // SQABSv2i32 |
1853 | 1.59k | UINT64_C(1323333632), // SQABSv2i64 |
1854 | 1.59k | UINT64_C(241203200), // SQABSv4i16 |
1855 | 1.59k | UINT64_C(1319139328), // SQABSv4i32 |
1856 | 1.59k | UINT64_C(1314945024), // SQABSv8i16 |
1857 | 1.59k | UINT64_C(237008896), // SQABSv8i8 |
1858 | 1.59k | UINT64_C(1310723072), // SQADDv16i8 |
1859 | 1.59k | UINT64_C(1583352832), // SQADDv1i16 |
1860 | 1.59k | UINT64_C(1587547136), // SQADDv1i32 |
1861 | 1.59k | UINT64_C(1591741440), // SQADDv1i64 |
1862 | 1.59k | UINT64_C(1579158528), // SQADDv1i8 |
1863 | 1.59k | UINT64_C(245369856), // SQADDv2i32 |
1864 | 1.59k | UINT64_C(1323305984), // SQADDv2i64 |
1865 | 1.59k | UINT64_C(241175552), // SQADDv4i16 |
1866 | 1.59k | UINT64_C(1319111680), // SQADDv4i32 |
1867 | 1.59k | UINT64_C(1314917376), // SQADDv8i16 |
1868 | 1.59k | UINT64_C(236981248), // SQADDv8i8 |
1869 | 1.59k | UINT64_C(1583386624), // SQDMLALi16 |
1870 | 1.59k | UINT64_C(1587580928), // SQDMLALi32 |
1871 | 1.59k | UINT64_C(1598042112), // SQDMLALv1i32_indexed |
1872 | 1.59k | UINT64_C(1602236416), // SQDMLALv1i64_indexed |
1873 | 1.59k | UINT64_C(260059136), // SQDMLALv2i32_indexed |
1874 | 1.59k | UINT64_C(245403648), // SQDMLALv2i32_v2i64 |
1875 | 1.59k | UINT64_C(255864832), // SQDMLALv4i16_indexed |
1876 | 1.59k | UINT64_C(241209344), // SQDMLALv4i16_v4i32 |
1877 | 1.59k | UINT64_C(1333800960), // SQDMLALv4i32_indexed |
1878 | 1.59k | UINT64_C(1319145472), // SQDMLALv4i32_v2i64 |
1879 | 1.59k | UINT64_C(1329606656), // SQDMLALv8i16_indexed |
1880 | 1.59k | UINT64_C(1314951168), // SQDMLALv8i16_v4i32 |
1881 | 1.59k | UINT64_C(1583394816), // SQDMLSLi16 |
1882 | 1.59k | UINT64_C(1587589120), // SQDMLSLi32 |
1883 | 1.59k | UINT64_C(1598058496), // SQDMLSLv1i32_indexed |
1884 | 1.59k | UINT64_C(1602252800), // SQDMLSLv1i64_indexed |
1885 | 1.59k | UINT64_C(260075520), // SQDMLSLv2i32_indexed |
1886 | 1.59k | UINT64_C(245411840), // SQDMLSLv2i32_v2i64 |
1887 | 1.59k | UINT64_C(255881216), // SQDMLSLv4i16_indexed |
1888 | 1.59k | UINT64_C(241217536), // SQDMLSLv4i16_v4i32 |
1889 | 1.59k | UINT64_C(1333817344), // SQDMLSLv4i32_indexed |
1890 | 1.59k | UINT64_C(1319153664), // SQDMLSLv4i32_v2i64 |
1891 | 1.59k | UINT64_C(1329623040), // SQDMLSLv8i16_indexed |
1892 | 1.59k | UINT64_C(1314959360), // SQDMLSLv8i16_v4i32 |
1893 | 1.59k | UINT64_C(1583395840), // SQDMULHv1i16 |
1894 | 1.59k | UINT64_C(1598078976), // SQDMULHv1i16_indexed |
1895 | 1.59k | UINT64_C(1587590144), // SQDMULHv1i32 |
1896 | 1.59k | UINT64_C(1602273280), // SQDMULHv1i32_indexed |
1897 | 1.59k | UINT64_C(245412864), // SQDMULHv2i32 |
1898 | 1.59k | UINT64_C(260096000), // SQDMULHv2i32_indexed |
1899 | 1.59k | UINT64_C(241218560), // SQDMULHv4i16 |
1900 | 1.59k | UINT64_C(255901696), // SQDMULHv4i16_indexed |
1901 | 1.59k | UINT64_C(1319154688), // SQDMULHv4i32 |
1902 | 1.59k | UINT64_C(1333837824), // SQDMULHv4i32_indexed |
1903 | 1.59k | UINT64_C(1314960384), // SQDMULHv8i16 |
1904 | 1.59k | UINT64_C(1329643520), // SQDMULHv8i16_indexed |
1905 | 1.59k | UINT64_C(1583403008), // SQDMULLi16 |
1906 | 1.59k | UINT64_C(1587597312), // SQDMULLi32 |
1907 | 1.59k | UINT64_C(1598074880), // SQDMULLv1i32_indexed |
1908 | 1.59k | UINT64_C(1602269184), // SQDMULLv1i64_indexed |
1909 | 1.59k | UINT64_C(260091904), // SQDMULLv2i32_indexed |
1910 | 1.59k | UINT64_C(245420032), // SQDMULLv2i32_v2i64 |
1911 | 1.59k | UINT64_C(255897600), // SQDMULLv4i16_indexed |
1912 | 1.59k | UINT64_C(241225728), // SQDMULLv4i16_v4i32 |
1913 | 1.59k | UINT64_C(1333833728), // SQDMULLv4i32_indexed |
1914 | 1.59k | UINT64_C(1319161856), // SQDMULLv4i32_v2i64 |
1915 | 1.59k | UINT64_C(1329639424), // SQDMULLv8i16_indexed |
1916 | 1.59k | UINT64_C(1314967552), // SQDMULLv8i16_v4i32 |
1917 | 1.59k | UINT64_C(1847621632), // SQNEGv16i8 |
1918 | 1.59k | UINT64_C(2120251392), // SQNEGv1i16 |
1919 | 1.59k | UINT64_C(2124445696), // SQNEGv1i32 |
1920 | 1.59k | UINT64_C(2128640000), // SQNEGv1i64 |
1921 | 1.59k | UINT64_C(2116057088), // SQNEGv1i8 |
1922 | 1.59k | UINT64_C(782268416), // SQNEGv2i32 |
1923 | 1.59k | UINT64_C(1860204544), // SQNEGv2i64 |
1924 | 1.59k | UINT64_C(778074112), // SQNEGv4i16 |
1925 | 1.59k | UINT64_C(1856010240), // SQNEGv4i32 |
1926 | 1.59k | UINT64_C(1851815936), // SQNEGv8i16 |
1927 | 1.59k | UINT64_C(773879808), // SQNEGv8i8 |
1928 | 1.59k | UINT64_C(2134953984), // SQRDMLAHi16_indexed |
1929 | 1.59k | UINT64_C(2139148288), // SQRDMLAHi32_indexed |
1930 | 1.59k | UINT64_C(2118157312), // SQRDMLAHv1i16 |
1931 | 1.59k | UINT64_C(2122351616), // SQRDMLAHv1i32 |
1932 | 1.59k | UINT64_C(780174336), // SQRDMLAHv2i32 |
1933 | 1.59k | UINT64_C(796971008), // SQRDMLAHv2i32_indexed |
1934 | 1.59k | UINT64_C(775980032), // SQRDMLAHv4i16 |
1935 | 1.59k | UINT64_C(792776704), // SQRDMLAHv4i16_indexed |
1936 | 1.59k | UINT64_C(1853916160), // SQRDMLAHv4i32 |
1937 | 1.59k | UINT64_C(1870712832), // SQRDMLAHv4i32_indexed |
1938 | 1.59k | UINT64_C(1849721856), // SQRDMLAHv8i16 |
1939 | 1.59k | UINT64_C(1866518528), // SQRDMLAHv8i16_indexed |
1940 | 1.59k | UINT64_C(2134962176), // SQRDMLSHi16_indexed |
1941 | 1.59k | UINT64_C(2139156480), // SQRDMLSHi32_indexed |
1942 | 1.59k | UINT64_C(2118159360), // SQRDMLSHv1i16 |
1943 | 1.59k | UINT64_C(2122353664), // SQRDMLSHv1i32 |
1944 | 1.59k | UINT64_C(780176384), // SQRDMLSHv2i32 |
1945 | 1.59k | UINT64_C(796979200), // SQRDMLSHv2i32_indexed |
1946 | 1.59k | UINT64_C(775982080), // SQRDMLSHv4i16 |
1947 | 1.59k | UINT64_C(792784896), // SQRDMLSHv4i16_indexed |
1948 | 1.59k | UINT64_C(1853918208), // SQRDMLSHv4i32 |
1949 | 1.59k | UINT64_C(1870721024), // SQRDMLSHv4i32_indexed |
1950 | 1.59k | UINT64_C(1849723904), // SQRDMLSHv8i16 |
1951 | 1.59k | UINT64_C(1866526720), // SQRDMLSHv8i16_indexed |
1952 | 1.59k | UINT64_C(2120266752), // SQRDMULHv1i16 |
1953 | 1.59k | UINT64_C(1598083072), // SQRDMULHv1i16_indexed |
1954 | 1.59k | UINT64_C(2124461056), // SQRDMULHv1i32 |
1955 | 1.59k | UINT64_C(1602277376), // SQRDMULHv1i32_indexed |
1956 | 1.59k | UINT64_C(782283776), // SQRDMULHv2i32 |
1957 | 1.59k | UINT64_C(260100096), // SQRDMULHv2i32_indexed |
1958 | 1.59k | UINT64_C(778089472), // SQRDMULHv4i16 |
1959 | 1.59k | UINT64_C(255905792), // SQRDMULHv4i16_indexed |
1960 | 1.59k | UINT64_C(1856025600), // SQRDMULHv4i32 |
1961 | 1.59k | UINT64_C(1333841920), // SQRDMULHv4i32_indexed |
1962 | 1.59k | UINT64_C(1851831296), // SQRDMULHv8i16 |
1963 | 1.59k | UINT64_C(1329647616), // SQRDMULHv8i16_indexed |
1964 | 1.59k | UINT64_C(1310743552), // SQRSHLv16i8 |
1965 | 1.59k | UINT64_C(1583373312), // SQRSHLv1i16 |
1966 | 1.59k | UINT64_C(1587567616), // SQRSHLv1i32 |
1967 | 1.59k | UINT64_C(1591761920), // SQRSHLv1i64 |
1968 | 1.59k | UINT64_C(1579179008), // SQRSHLv1i8 |
1969 | 1.59k | UINT64_C(245390336), // SQRSHLv2i32 |
1970 | 1.59k | UINT64_C(1323326464), // SQRSHLv2i64 |
1971 | 1.59k | UINT64_C(241196032), // SQRSHLv4i16 |
1972 | 1.59k | UINT64_C(1319132160), // SQRSHLv4i32 |
1973 | 1.59k | UINT64_C(1314937856), // SQRSHLv8i16 |
1974 | 1.59k | UINT64_C(237001728), // SQRSHLv8i8 |
1975 | 1.59k | UINT64_C(1594399744), // SQRSHRNb |
1976 | 1.59k | UINT64_C(1594924032), // SQRSHRNh |
1977 | 1.59k | UINT64_C(1595972608), // SQRSHRNs |
1978 | 1.59k | UINT64_C(1325964288), // SQRSHRNv16i8_shift |
1979 | 1.59k | UINT64_C(253795328), // SQRSHRNv2i32_shift |
1980 | 1.59k | UINT64_C(252746752), // SQRSHRNv4i16_shift |
1981 | 1.59k | UINT64_C(1327537152), // SQRSHRNv4i32_shift |
1982 | 1.59k | UINT64_C(1326488576), // SQRSHRNv8i16_shift |
1983 | 1.59k | UINT64_C(252222464), // SQRSHRNv8i8_shift |
1984 | 1.59k | UINT64_C(2131266560), // SQRSHRUNb |
1985 | 1.59k | UINT64_C(2131790848), // SQRSHRUNh |
1986 | 1.59k | UINT64_C(2132839424), // SQRSHRUNs |
1987 | 1.59k | UINT64_C(1862831104), // SQRSHRUNv16i8_shift |
1988 | 1.59k | UINT64_C(790662144), // SQRSHRUNv2i32_shift |
1989 | 1.59k | UINT64_C(789613568), // SQRSHRUNv4i16_shift |
1990 | 1.59k | UINT64_C(1864403968), // SQRSHRUNv4i32_shift |
1991 | 1.59k | UINT64_C(1863355392), // SQRSHRUNv8i16_shift |
1992 | 1.59k | UINT64_C(789089280), // SQRSHRUNv8i8_shift |
1993 | 1.59k | UINT64_C(2131256320), // SQSHLUb |
1994 | 1.59k | UINT64_C(2134926336), // SQSHLUd |
1995 | 1.59k | UINT64_C(2131780608), // SQSHLUh |
1996 | 1.59k | UINT64_C(2132829184), // SQSHLUs |
1997 | 1.59k | UINT64_C(1862820864), // SQSHLUv16i8_shift |
1998 | 1.59k | UINT64_C(790651904), // SQSHLUv2i32_shift |
1999 | 1.59k | UINT64_C(1866490880), // SQSHLUv2i64_shift |
2000 | 1.59k | UINT64_C(789603328), // SQSHLUv4i16_shift |
2001 | 1.59k | UINT64_C(1864393728), // SQSHLUv4i32_shift |
2002 | 1.59k | UINT64_C(1863345152), // SQSHLUv8i16_shift |
2003 | 1.59k | UINT64_C(789079040), // SQSHLUv8i8_shift |
2004 | 1.59k | UINT64_C(1594389504), // SQSHLb |
2005 | 1.59k | UINT64_C(1598059520), // SQSHLd |
2006 | 1.59k | UINT64_C(1594913792), // SQSHLh |
2007 | 1.59k | UINT64_C(1595962368), // SQSHLs |
2008 | 1.59k | UINT64_C(1310739456), // SQSHLv16i8 |
2009 | 1.59k | UINT64_C(1325954048), // SQSHLv16i8_shift |
2010 | 1.59k | UINT64_C(1583369216), // SQSHLv1i16 |
2011 | 1.59k | UINT64_C(1587563520), // SQSHLv1i32 |
2012 | 1.59k | UINT64_C(1591757824), // SQSHLv1i64 |
2013 | 1.59k | UINT64_C(1579174912), // SQSHLv1i8 |
2014 | 1.59k | UINT64_C(245386240), // SQSHLv2i32 |
2015 | 1.59k | UINT64_C(253785088), // SQSHLv2i32_shift |
2016 | 1.59k | UINT64_C(1323322368), // SQSHLv2i64 |
2017 | 1.59k | UINT64_C(1329624064), // SQSHLv2i64_shift |
2018 | 1.59k | UINT64_C(241191936), // SQSHLv4i16 |
2019 | 1.59k | UINT64_C(252736512), // SQSHLv4i16_shift |
2020 | 1.59k | UINT64_C(1319128064), // SQSHLv4i32 |
2021 | 1.59k | UINT64_C(1327526912), // SQSHLv4i32_shift |
2022 | 1.59k | UINT64_C(1314933760), // SQSHLv8i16 |
2023 | 1.59k | UINT64_C(1326478336), // SQSHLv8i16_shift |
2024 | 1.59k | UINT64_C(236997632), // SQSHLv8i8 |
2025 | 1.59k | UINT64_C(252212224), // SQSHLv8i8_shift |
2026 | 1.59k | UINT64_C(1594397696), // SQSHRNb |
2027 | 1.59k | UINT64_C(1594921984), // SQSHRNh |
2028 | 1.59k | UINT64_C(1595970560), // SQSHRNs |
2029 | 1.59k | UINT64_C(1325962240), // SQSHRNv16i8_shift |
2030 | 1.59k | UINT64_C(253793280), // SQSHRNv2i32_shift |
2031 | 1.59k | UINT64_C(252744704), // SQSHRNv4i16_shift |
2032 | 1.59k | UINT64_C(1327535104), // SQSHRNv4i32_shift |
2033 | 1.59k | UINT64_C(1326486528), // SQSHRNv8i16_shift |
2034 | 1.59k | UINT64_C(252220416), // SQSHRNv8i8_shift |
2035 | 1.59k | UINT64_C(2131264512), // SQSHRUNb |
2036 | 1.59k | UINT64_C(2131788800), // SQSHRUNh |
2037 | 1.59k | UINT64_C(2132837376), // SQSHRUNs |
2038 | 1.59k | UINT64_C(1862829056), // SQSHRUNv16i8_shift |
2039 | 1.59k | UINT64_C(790660096), // SQSHRUNv2i32_shift |
2040 | 1.59k | UINT64_C(789611520), // SQSHRUNv4i16_shift |
2041 | 1.59k | UINT64_C(1864401920), // SQSHRUNv4i32_shift |
2042 | 1.59k | UINT64_C(1863353344), // SQSHRUNv8i16_shift |
2043 | 1.59k | UINT64_C(789087232), // SQSHRUNv8i8_shift |
2044 | 1.59k | UINT64_C(1310731264), // SQSUBv16i8 |
2045 | 1.59k | UINT64_C(1583361024), // SQSUBv1i16 |
2046 | 1.59k | UINT64_C(1587555328), // SQSUBv1i32 |
2047 | 1.59k | UINT64_C(1591749632), // SQSUBv1i64 |
2048 | 1.59k | UINT64_C(1579166720), // SQSUBv1i8 |
2049 | 1.59k | UINT64_C(245378048), // SQSUBv2i32 |
2050 | 1.59k | UINT64_C(1323314176), // SQSUBv2i64 |
2051 | 1.59k | UINT64_C(241183744), // SQSUBv4i16 |
2052 | 1.59k | UINT64_C(1319119872), // SQSUBv4i32 |
2053 | 1.59k | UINT64_C(1314925568), // SQSUBv8i16 |
2054 | 1.59k | UINT64_C(236989440), // SQSUBv8i8 |
2055 | 1.59k | UINT64_C(1310803968), // SQXTNv16i8 |
2056 | 1.59k | UINT64_C(1583433728), // SQXTNv1i16 |
2057 | 1.59k | UINT64_C(1587628032), // SQXTNv1i32 |
2058 | 1.59k | UINT64_C(1579239424), // SQXTNv1i8 |
2059 | 1.59k | UINT64_C(245450752), // SQXTNv2i32 |
2060 | 1.59k | UINT64_C(241256448), // SQXTNv4i16 |
2061 | 1.59k | UINT64_C(1319192576), // SQXTNv4i32 |
2062 | 1.59k | UINT64_C(1314998272), // SQXTNv8i16 |
2063 | 1.59k | UINT64_C(237062144), // SQXTNv8i8 |
2064 | 1.59k | UINT64_C(1847666688), // SQXTUNv16i8 |
2065 | 1.59k | UINT64_C(2120296448), // SQXTUNv1i16 |
2066 | 1.59k | UINT64_C(2124490752), // SQXTUNv1i32 |
2067 | 1.59k | UINT64_C(2116102144), // SQXTUNv1i8 |
2068 | 1.59k | UINT64_C(782313472), // SQXTUNv2i32 |
2069 | 1.59k | UINT64_C(778119168), // SQXTUNv4i16 |
2070 | 1.59k | UINT64_C(1856055296), // SQXTUNv4i32 |
2071 | 1.59k | UINT64_C(1851860992), // SQXTUNv8i16 |
2072 | 1.59k | UINT64_C(773924864), // SQXTUNv8i8 |
2073 | 1.59k | UINT64_C(1310725120), // SRHADDv16i8 |
2074 | 1.59k | UINT64_C(245371904), // SRHADDv2i32 |
2075 | 1.59k | UINT64_C(241177600), // SRHADDv4i16 |
2076 | 1.59k | UINT64_C(1319113728), // SRHADDv4i32 |
2077 | 1.59k | UINT64_C(1314919424), // SRHADDv8i16 |
2078 | 1.59k | UINT64_C(236983296), // SRHADDv8i8 |
2079 | 1.59k | UINT64_C(2134918144), // SRId |
2080 | 1.59k | UINT64_C(1862812672), // SRIv16i8_shift |
2081 | 1.59k | UINT64_C(790643712), // SRIv2i32_shift |
2082 | 1.59k | UINT64_C(1866482688), // SRIv2i64_shift |
2083 | 1.59k | UINT64_C(789595136), // SRIv4i16_shift |
2084 | 1.59k | UINT64_C(1864385536), // SRIv4i32_shift |
2085 | 1.59k | UINT64_C(1863336960), // SRIv8i16_shift |
2086 | 1.59k | UINT64_C(789070848), // SRIv8i8_shift |
2087 | 1.59k | UINT64_C(1310741504), // SRSHLv16i8 |
2088 | 1.59k | UINT64_C(1591759872), // SRSHLv1i64 |
2089 | 1.59k | UINT64_C(245388288), // SRSHLv2i32 |
2090 | 1.59k | UINT64_C(1323324416), // SRSHLv2i64 |
2091 | 1.59k | UINT64_C(241193984), // SRSHLv4i16 |
2092 | 1.59k | UINT64_C(1319130112), // SRSHLv4i32 |
2093 | 1.59k | UINT64_C(1314935808), // SRSHLv8i16 |
2094 | 1.59k | UINT64_C(236999680), // SRSHLv8i8 |
2095 | 1.59k | UINT64_C(1598039040), // SRSHRd |
2096 | 1.59k | UINT64_C(1325933568), // SRSHRv16i8_shift |
2097 | 1.59k | UINT64_C(253764608), // SRSHRv2i32_shift |
2098 | 1.59k | UINT64_C(1329603584), // SRSHRv2i64_shift |
2099 | 1.59k | UINT64_C(252716032), // SRSHRv4i16_shift |
2100 | 1.59k | UINT64_C(1327506432), // SRSHRv4i32_shift |
2101 | 1.59k | UINT64_C(1326457856), // SRSHRv8i16_shift |
2102 | 1.59k | UINT64_C(252191744), // SRSHRv8i8_shift |
2103 | 1.59k | UINT64_C(1598043136), // SRSRAd |
2104 | 1.59k | UINT64_C(1325937664), // SRSRAv16i8_shift |
2105 | 1.59k | UINT64_C(253768704), // SRSRAv2i32_shift |
2106 | 1.59k | UINT64_C(1329607680), // SRSRAv2i64_shift |
2107 | 1.59k | UINT64_C(252720128), // SRSRAv4i16_shift |
2108 | 1.59k | UINT64_C(1327510528), // SRSRAv4i32_shift |
2109 | 1.59k | UINT64_C(1326461952), // SRSRAv8i16_shift |
2110 | 1.59k | UINT64_C(252195840), // SRSRAv8i8_shift |
2111 | 1.59k | UINT64_C(1325966336), // SSHLLv16i8_shift |
2112 | 1.59k | UINT64_C(253797376), // SSHLLv2i32_shift |
2113 | 1.59k | UINT64_C(252748800), // SSHLLv4i16_shift |
2114 | 1.59k | UINT64_C(1327539200), // SSHLLv4i32_shift |
2115 | 1.59k | UINT64_C(1326490624), // SSHLLv8i16_shift |
2116 | 1.59k | UINT64_C(252224512), // SSHLLv8i8_shift |
2117 | 1.59k | UINT64_C(1310737408), // SSHLv16i8 |
2118 | 1.59k | UINT64_C(1591755776), // SSHLv1i64 |
2119 | 1.59k | UINT64_C(245384192), // SSHLv2i32 |
2120 | 1.59k | UINT64_C(1323320320), // SSHLv2i64 |
2121 | 1.59k | UINT64_C(241189888), // SSHLv4i16 |
2122 | 1.59k | UINT64_C(1319126016), // SSHLv4i32 |
2123 | 1.59k | UINT64_C(1314931712), // SSHLv8i16 |
2124 | 1.59k | UINT64_C(236995584), // SSHLv8i8 |
2125 | 1.59k | UINT64_C(1598030848), // SSHRd |
2126 | 1.59k | UINT64_C(1325925376), // SSHRv16i8_shift |
2127 | 1.59k | UINT64_C(253756416), // SSHRv2i32_shift |
2128 | 1.59k | UINT64_C(1329595392), // SSHRv2i64_shift |
2129 | 1.59k | UINT64_C(252707840), // SSHRv4i16_shift |
2130 | 1.59k | UINT64_C(1327498240), // SSHRv4i32_shift |
2131 | 1.59k | UINT64_C(1326449664), // SSHRv8i16_shift |
2132 | 1.59k | UINT64_C(252183552), // SSHRv8i8_shift |
2133 | 1.59k | UINT64_C(1598034944), // SSRAd |
2134 | 1.59k | UINT64_C(1325929472), // SSRAv16i8_shift |
2135 | 1.59k | UINT64_C(253760512), // SSRAv2i32_shift |
2136 | 1.59k | UINT64_C(1329599488), // SSRAv2i64_shift |
2137 | 1.59k | UINT64_C(252711936), // SSRAv4i16_shift |
2138 | 1.59k | UINT64_C(1327502336), // SSRAv4i32_shift |
2139 | 1.59k | UINT64_C(1326453760), // SSRAv8i16_shift |
2140 | 1.59k | UINT64_C(252187648), // SSRAv8i8_shift |
2141 | 1.59k | UINT64_C(1310728192), // SSUBLv16i8_v8i16 |
2142 | 1.59k | UINT64_C(245374976), // SSUBLv2i32_v2i64 |
2143 | 1.59k | UINT64_C(241180672), // SSUBLv4i16_v4i32 |
2144 | 1.59k | UINT64_C(1319116800), // SSUBLv4i32_v2i64 |
2145 | 1.59k | UINT64_C(1314922496), // SSUBLv8i16_v4i32 |
2146 | 1.59k | UINT64_C(236986368), // SSUBLv8i8_v8i16 |
2147 | 1.59k | UINT64_C(1310732288), // SSUBWv16i8_v8i16 |
2148 | 1.59k | UINT64_C(245379072), // SSUBWv2i32_v2i64 |
2149 | 1.59k | UINT64_C(241184768), // SSUBWv4i16_v4i32 |
2150 | 1.59k | UINT64_C(1319120896), // SSUBWv4i32_v2i64 |
2151 | 1.59k | UINT64_C(1314926592), // SSUBWv8i16_v4i32 |
2152 | 1.59k | UINT64_C(236990464), // SSUBWv8i8_v8i16 |
2153 | 1.59k | UINT64_C(1275076608), // ST1Fourv16b |
2154 | 1.59k | UINT64_C(1283465216), // ST1Fourv16b_POST |
2155 | 1.59k | UINT64_C(201337856), // ST1Fourv1d |
2156 | 1.59k | UINT64_C(209726464), // ST1Fourv1d_POST |
2157 | 1.59k | UINT64_C(1275079680), // ST1Fourv2d |
2158 | 1.59k | UINT64_C(1283468288), // ST1Fourv2d_POST |
2159 | 1.59k | UINT64_C(201336832), // ST1Fourv2s |
2160 | 1.59k | UINT64_C(209725440), // ST1Fourv2s_POST |
2161 | 1.59k | UINT64_C(201335808), // ST1Fourv4h |
2162 | 1.59k | UINT64_C(209724416), // ST1Fourv4h_POST |
2163 | 1.59k | UINT64_C(1275078656), // ST1Fourv4s |
2164 | 1.59k | UINT64_C(1283467264), // ST1Fourv4s_POST |
2165 | 1.59k | UINT64_C(201334784), // ST1Fourv8b |
2166 | 1.59k | UINT64_C(209723392), // ST1Fourv8b_POST |
2167 | 1.59k | UINT64_C(1275077632), // ST1Fourv8h |
2168 | 1.59k | UINT64_C(1283466240), // ST1Fourv8h_POST |
2169 | 1.59k | UINT64_C(1275097088), // ST1Onev16b |
2170 | 1.59k | UINT64_C(1283485696), // ST1Onev16b_POST |
2171 | 1.59k | UINT64_C(201358336), // ST1Onev1d |
2172 | 1.59k | UINT64_C(209746944), // ST1Onev1d_POST |
2173 | 1.59k | UINT64_C(1275100160), // ST1Onev2d |
2174 | 1.59k | UINT64_C(1283488768), // ST1Onev2d_POST |
2175 | 1.59k | UINT64_C(201357312), // ST1Onev2s |
2176 | 1.59k | UINT64_C(209745920), // ST1Onev2s_POST |
2177 | 1.59k | UINT64_C(201356288), // ST1Onev4h |
2178 | 1.59k | UINT64_C(209744896), // ST1Onev4h_POST |
2179 | 1.59k | UINT64_C(1275099136), // ST1Onev4s |
2180 | 1.59k | UINT64_C(1283487744), // ST1Onev4s_POST |
2181 | 1.59k | UINT64_C(201355264), // ST1Onev8b |
2182 | 1.59k | UINT64_C(209743872), // ST1Onev8b_POST |
2183 | 1.59k | UINT64_C(1275098112), // ST1Onev8h |
2184 | 1.59k | UINT64_C(1283486720), // ST1Onev8h_POST |
2185 | 1.59k | UINT64_C(1275092992), // ST1Threev16b |
2186 | 1.59k | UINT64_C(1283481600), // ST1Threev16b_POST |
2187 | 1.59k | UINT64_C(201354240), // ST1Threev1d |
2188 | 1.59k | UINT64_C(209742848), // ST1Threev1d_POST |
2189 | 1.59k | UINT64_C(1275096064), // ST1Threev2d |
2190 | 1.59k | UINT64_C(1283484672), // ST1Threev2d_POST |
2191 | 1.59k | UINT64_C(201353216), // ST1Threev2s |
2192 | 1.59k | UINT64_C(209741824), // ST1Threev2s_POST |
2193 | 1.59k | UINT64_C(201352192), // ST1Threev4h |
2194 | 1.59k | UINT64_C(209740800), // ST1Threev4h_POST |
2195 | 1.59k | UINT64_C(1275095040), // ST1Threev4s |
2196 | 1.59k | UINT64_C(1283483648), // ST1Threev4s_POST |
2197 | 1.59k | UINT64_C(201351168), // ST1Threev8b |
2198 | 1.59k | UINT64_C(209739776), // ST1Threev8b_POST |
2199 | 1.59k | UINT64_C(1275094016), // ST1Threev8h |
2200 | 1.59k | UINT64_C(1283482624), // ST1Threev8h_POST |
2201 | 1.59k | UINT64_C(1275109376), // ST1Twov16b |
2202 | 1.59k | UINT64_C(1283497984), // ST1Twov16b_POST |
2203 | 1.59k | UINT64_C(201370624), // ST1Twov1d |
2204 | 1.59k | UINT64_C(209759232), // ST1Twov1d_POST |
2205 | 1.59k | UINT64_C(1275112448), // ST1Twov2d |
2206 | 1.59k | UINT64_C(1283501056), // ST1Twov2d_POST |
2207 | 1.59k | UINT64_C(201369600), // ST1Twov2s |
2208 | 1.59k | UINT64_C(209758208), // ST1Twov2s_POST |
2209 | 1.59k | UINT64_C(201368576), // ST1Twov4h |
2210 | 1.59k | UINT64_C(209757184), // ST1Twov4h_POST |
2211 | 1.59k | UINT64_C(1275111424), // ST1Twov4s |
2212 | 1.59k | UINT64_C(1283500032), // ST1Twov4s_POST |
2213 | 1.59k | UINT64_C(201367552), // ST1Twov8b |
2214 | 1.59k | UINT64_C(209756160), // ST1Twov8b_POST |
2215 | 1.59k | UINT64_C(1275110400), // ST1Twov8h |
2216 | 1.59k | UINT64_C(1283499008), // ST1Twov8h_POST |
2217 | 1.59k | UINT64_C(218120192), // ST1i16 |
2218 | 1.59k | UINT64_C(226508800), // ST1i16_POST |
2219 | 1.59k | UINT64_C(218136576), // ST1i32 |
2220 | 1.59k | UINT64_C(226525184), // ST1i32_POST |
2221 | 1.59k | UINT64_C(218137600), // ST1i64 |
2222 | 1.59k | UINT64_C(226526208), // ST1i64_POST |
2223 | 1.59k | UINT64_C(218103808), // ST1i8 |
2224 | 1.59k | UINT64_C(226492416), // ST1i8_POST |
2225 | 1.59k | UINT64_C(1275101184), // ST2Twov16b |
2226 | 1.59k | UINT64_C(1283489792), // ST2Twov16b_POST |
2227 | 1.59k | UINT64_C(1275104256), // ST2Twov2d |
2228 | 1.59k | UINT64_C(1283492864), // ST2Twov2d_POST |
2229 | 1.59k | UINT64_C(201361408), // ST2Twov2s |
2230 | 1.59k | UINT64_C(209750016), // ST2Twov2s_POST |
2231 | 1.59k | UINT64_C(201360384), // ST2Twov4h |
2232 | 1.59k | UINT64_C(209748992), // ST2Twov4h_POST |
2233 | 1.59k | UINT64_C(1275103232), // ST2Twov4s |
2234 | 1.59k | UINT64_C(1283491840), // ST2Twov4s_POST |
2235 | 1.59k | UINT64_C(201359360), // ST2Twov8b |
2236 | 1.59k | UINT64_C(209747968), // ST2Twov8b_POST |
2237 | 1.59k | UINT64_C(1275102208), // ST2Twov8h |
2238 | 1.59k | UINT64_C(1283490816), // ST2Twov8h_POST |
2239 | 1.59k | UINT64_C(220217344), // ST2i16 |
2240 | 1.59k | UINT64_C(228605952), // ST2i16_POST |
2241 | 1.59k | UINT64_C(220233728), // ST2i32 |
2242 | 1.59k | UINT64_C(228622336), // ST2i32_POST |
2243 | 1.59k | UINT64_C(220234752), // ST2i64 |
2244 | 1.59k | UINT64_C(228623360), // ST2i64_POST |
2245 | 1.59k | UINT64_C(220200960), // ST2i8 |
2246 | 1.59k | UINT64_C(228589568), // ST2i8_POST |
2247 | 1.59k | UINT64_C(1275084800), // ST3Threev16b |
2248 | 1.59k | UINT64_C(1283473408), // ST3Threev16b_POST |
2249 | 1.59k | UINT64_C(1275087872), // ST3Threev2d |
2250 | 1.59k | UINT64_C(1283476480), // ST3Threev2d_POST |
2251 | 1.59k | UINT64_C(201345024), // ST3Threev2s |
2252 | 1.59k | UINT64_C(209733632), // ST3Threev2s_POST |
2253 | 1.59k | UINT64_C(201344000), // ST3Threev4h |
2254 | 1.59k | UINT64_C(209732608), // ST3Threev4h_POST |
2255 | 1.59k | UINT64_C(1275086848), // ST3Threev4s |
2256 | 1.59k | UINT64_C(1283475456), // ST3Threev4s_POST |
2257 | 1.59k | UINT64_C(201342976), // ST3Threev8b |
2258 | 1.59k | UINT64_C(209731584), // ST3Threev8b_POST |
2259 | 1.59k | UINT64_C(1275085824), // ST3Threev8h |
2260 | 1.59k | UINT64_C(1283474432), // ST3Threev8h_POST |
2261 | 1.59k | UINT64_C(218128384), // ST3i16 |
2262 | 1.59k | UINT64_C(226516992), // ST3i16_POST |
2263 | 1.59k | UINT64_C(218144768), // ST3i32 |
2264 | 1.59k | UINT64_C(226533376), // ST3i32_POST |
2265 | 1.59k | UINT64_C(218145792), // ST3i64 |
2266 | 1.59k | UINT64_C(226534400), // ST3i64_POST |
2267 | 1.59k | UINT64_C(218112000), // ST3i8 |
2268 | 1.59k | UINT64_C(226500608), // ST3i8_POST |
2269 | 1.59k | UINT64_C(1275068416), // ST4Fourv16b |
2270 | 1.59k | UINT64_C(1283457024), // ST4Fourv16b_POST |
2271 | 1.59k | UINT64_C(1275071488), // ST4Fourv2d |
2272 | 1.59k | UINT64_C(1283460096), // ST4Fourv2d_POST |
2273 | 1.59k | UINT64_C(201328640), // ST4Fourv2s |
2274 | 1.59k | UINT64_C(209717248), // ST4Fourv2s_POST |
2275 | 1.59k | UINT64_C(201327616), // ST4Fourv4h |
2276 | 1.59k | UINT64_C(209716224), // ST4Fourv4h_POST |
2277 | 1.59k | UINT64_C(1275070464), // ST4Fourv4s |
2278 | 1.59k | UINT64_C(1283459072), // ST4Fourv4s_POST |
2279 | 1.59k | UINT64_C(201326592), // ST4Fourv8b |
2280 | 1.59k | UINT64_C(209715200), // ST4Fourv8b_POST |
2281 | 1.59k | UINT64_C(1275069440), // ST4Fourv8h |
2282 | 1.59k | UINT64_C(1283458048), // ST4Fourv8h_POST |
2283 | 1.59k | UINT64_C(220225536), // ST4i16 |
2284 | 1.59k | UINT64_C(228614144), // ST4i16_POST |
2285 | 1.59k | UINT64_C(220241920), // ST4i32 |
2286 | 1.59k | UINT64_C(228630528), // ST4i32_POST |
2287 | 1.59k | UINT64_C(220242944), // ST4i64 |
2288 | 1.59k | UINT64_C(228631552), // ST4i64_POST |
2289 | 1.59k | UINT64_C(220209152), // ST4i8 |
2290 | 1.59k | UINT64_C(228597760), // ST4i8_POST |
2291 | 1.59k | UINT64_C(144669696), // STLLRB |
2292 | 1.59k | UINT64_C(1218411520), // STLLRH |
2293 | 1.59k | UINT64_C(2292153344), // STLLRW |
2294 | 1.59k | UINT64_C(3365895168), // STLLRX |
2295 | 1.59k | UINT64_C(144702464), // STLRB |
2296 | 1.59k | UINT64_C(1218444288), // STLRH |
2297 | 1.59k | UINT64_C(2292186112), // STLRW |
2298 | 1.59k | UINT64_C(3365927936), // STLRX |
2299 | 1.59k | UINT64_C(2283831296), // STLXPW |
2300 | 1.59k | UINT64_C(3357573120), // STLXPX |
2301 | 1.59k | UINT64_C(134250496), // STLXRB |
2302 | 1.59k | UINT64_C(1207992320), // STLXRH |
2303 | 1.59k | UINT64_C(2281734144), // STLXRW |
2304 | 1.59k | UINT64_C(3355475968), // STLXRX |
2305 | 1.59k | UINT64_C(1811939328), // STNPDi |
2306 | 1.59k | UINT64_C(2885681152), // STNPQi |
2307 | 1.59k | UINT64_C(738197504), // STNPSi |
2308 | 1.59k | UINT64_C(671088640), // STNPWi |
2309 | 1.59k | UINT64_C(2818572288), // STNPXi |
2310 | 1.59k | UINT64_C(1828716544), // STPDi |
2311 | 1.59k | UINT64_C(1820327936), // STPDpost |
2312 | 1.59k | UINT64_C(1837105152), // STPDpre |
2313 | 1.59k | UINT64_C(2902458368), // STPQi |
2314 | 1.59k | UINT64_C(2894069760), // STPQpost |
2315 | 1.59k | UINT64_C(2910846976), // STPQpre |
2316 | 1.59k | UINT64_C(754974720), // STPSi |
2317 | 1.59k | UINT64_C(746586112), // STPSpost |
2318 | 1.59k | UINT64_C(763363328), // STPSpre |
2319 | 1.59k | UINT64_C(687865856), // STPWi |
2320 | 1.59k | UINT64_C(679477248), // STPWpost |
2321 | 1.59k | UINT64_C(696254464), // STPWpre |
2322 | 1.59k | UINT64_C(2835349504), // STPXi |
2323 | 1.59k | UINT64_C(2826960896), // STPXpost |
2324 | 1.59k | UINT64_C(2843738112), // STPXpre |
2325 | 1.59k | UINT64_C(939525120), // STRBBpost |
2326 | 1.59k | UINT64_C(939527168), // STRBBpre |
2327 | 1.59k | UINT64_C(941639680), // STRBBroW |
2328 | 1.59k | UINT64_C(941647872), // STRBBroX |
2329 | 1.59k | UINT64_C(956301312), // STRBBui |
2330 | 1.59k | UINT64_C(1006633984), // STRBpost |
2331 | 1.59k | UINT64_C(1006636032), // STRBpre |
2332 | 1.59k | UINT64_C(1008748544), // STRBroW |
2333 | 1.59k | UINT64_C(1008756736), // STRBroX |
2334 | 1.59k | UINT64_C(1023410176), // STRBui |
2335 | 1.59k | UINT64_C(4227859456), // STRDpost |
2336 | 1.59k | UINT64_C(4227861504), // STRDpre |
2337 | 1.59k | UINT64_C(4229974016), // STRDroW |
2338 | 1.59k | UINT64_C(4229982208), // STRDroX |
2339 | 1.59k | UINT64_C(4244635648), // STRDui |
2340 | 1.59k | UINT64_C(2013266944), // STRHHpost |
2341 | 1.59k | UINT64_C(2013268992), // STRHHpre |
2342 | 1.59k | UINT64_C(2015381504), // STRHHroW |
2343 | 1.59k | UINT64_C(2015389696), // STRHHroX |
2344 | 1.59k | UINT64_C(2030043136), // STRHHui |
2345 | 1.59k | UINT64_C(2080375808), // STRHpost |
2346 | 1.59k | UINT64_C(2080377856), // STRHpre |
2347 | 1.59k | UINT64_C(2082490368), // STRHroW |
2348 | 1.59k | UINT64_C(2082498560), // STRHroX |
2349 | 1.59k | UINT64_C(2097152000), // STRHui |
2350 | 1.59k | UINT64_C(1015022592), // STRQpost |
2351 | 1.59k | UINT64_C(1015024640), // STRQpre |
2352 | 1.59k | UINT64_C(1017137152), // STRQroW |
2353 | 1.59k | UINT64_C(1017145344), // STRQroX |
2354 | 1.59k | UINT64_C(1031798784), // STRQui |
2355 | 1.59k | UINT64_C(3154117632), // STRSpost |
2356 | 1.59k | UINT64_C(3154119680), // STRSpre |
2357 | 1.59k | UINT64_C(3156232192), // STRSroW |
2358 | 1.59k | UINT64_C(3156240384), // STRSroX |
2359 | 1.59k | UINT64_C(3170893824), // STRSui |
2360 | 1.59k | UINT64_C(3087008768), // STRWpost |
2361 | 1.59k | UINT64_C(3087010816), // STRWpre |
2362 | 1.59k | UINT64_C(3089123328), // STRWroW |
2363 | 1.59k | UINT64_C(3089131520), // STRWroX |
2364 | 1.59k | UINT64_C(3103784960), // STRWui |
2365 | 1.59k | UINT64_C(4160750592), // STRXpost |
2366 | 1.59k | UINT64_C(4160752640), // STRXpre |
2367 | 1.59k | UINT64_C(4162865152), // STRXroW |
2368 | 1.59k | UINT64_C(4162873344), // STRXroX |
2369 | 1.59k | UINT64_C(4177526784), // STRXui |
2370 | 1.59k | UINT64_C(939526144), // STTRBi |
2371 | 1.59k | UINT64_C(2013267968), // STTRHi |
2372 | 1.59k | UINT64_C(3087009792), // STTRWi |
2373 | 1.59k | UINT64_C(4160751616), // STTRXi |
2374 | 1.59k | UINT64_C(939524096), // STURBBi |
2375 | 1.59k | UINT64_C(1006632960), // STURBi |
2376 | 1.59k | UINT64_C(4227858432), // STURDi |
2377 | 1.59k | UINT64_C(2013265920), // STURHHi |
2378 | 1.59k | UINT64_C(2080374784), // STURHi |
2379 | 1.59k | UINT64_C(1015021568), // STURQi |
2380 | 1.59k | UINT64_C(3154116608), // STURSi |
2381 | 1.59k | UINT64_C(3087007744), // STURWi |
2382 | 1.59k | UINT64_C(4160749568), // STURXi |
2383 | 1.59k | UINT64_C(2283798528), // STXPW |
2384 | 1.59k | UINT64_C(3357540352), // STXPX |
2385 | 1.59k | UINT64_C(134217728), // STXRB |
2386 | 1.59k | UINT64_C(1207959552), // STXRH |
2387 | 1.59k | UINT64_C(2281701376), // STXRW |
2388 | 1.59k | UINT64_C(3355443200), // STXRX |
2389 | 1.59k | UINT64_C(245391360), // SUBHNv2i64_v2i32 |
2390 | 1.59k | UINT64_C(1319133184), // SUBHNv2i64_v4i32 |
2391 | 1.59k | UINT64_C(241197056), // SUBHNv4i32_v4i16 |
2392 | 1.59k | UINT64_C(1314938880), // SUBHNv4i32_v8i16 |
2393 | 1.59k | UINT64_C(1310744576), // SUBHNv8i16_v16i8 |
2394 | 1.59k | UINT64_C(237002752), // SUBHNv8i16_v8i8 |
2395 | 1.59k | UINT64_C(1895825408), // SUBSWri |
2396 | 1.59k | UINT64_C(0), // SUBSWrr |
2397 | 1.59k | UINT64_C(1795162112), // SUBSWrs |
2398 | 1.59k | UINT64_C(1797259264), // SUBSWrx |
2399 | 1.59k | UINT64_C(4043309056), // SUBSXri |
2400 | 1.59k | UINT64_C(0), // SUBSXrr |
2401 | 1.59k | UINT64_C(3942645760), // SUBSXrs |
2402 | 1.59k | UINT64_C(3944742912), // SUBSXrx |
2403 | 1.59k | UINT64_C(3944767488), // SUBSXrx64 |
2404 | 1.59k | UINT64_C(1358954496), // SUBWri |
2405 | 1.59k | UINT64_C(0), // SUBWrr |
2406 | 1.59k | UINT64_C(1258291200), // SUBWrs |
2407 | 1.59k | UINT64_C(1260388352), // SUBWrx |
2408 | 1.59k | UINT64_C(3506438144), // SUBXri |
2409 | 1.59k | UINT64_C(0), // SUBXrr |
2410 | 1.59k | UINT64_C(3405774848), // SUBXrs |
2411 | 1.59k | UINT64_C(3407872000), // SUBXrx |
2412 | 1.59k | UINT64_C(3407896576), // SUBXrx64 |
2413 | 1.59k | UINT64_C(1847624704), // SUBv16i8 |
2414 | 1.59k | UINT64_C(2128643072), // SUBv1i64 |
2415 | 1.59k | UINT64_C(782271488), // SUBv2i32 |
2416 | 1.59k | UINT64_C(1860207616), // SUBv2i64 |
2417 | 1.59k | UINT64_C(778077184), // SUBv4i16 |
2418 | 1.59k | UINT64_C(1856013312), // SUBv4i32 |
2419 | 1.59k | UINT64_C(1851819008), // SUBv8i16 |
2420 | 1.59k | UINT64_C(773882880), // SUBv8i8 |
2421 | 1.59k | UINT64_C(1310734336), // SUQADDv16i8 |
2422 | 1.59k | UINT64_C(1583364096), // SUQADDv1i16 |
2423 | 1.59k | UINT64_C(1587558400), // SUQADDv1i32 |
2424 | 1.59k | UINT64_C(1591752704), // SUQADDv1i64 |
2425 | 1.59k | UINT64_C(1579169792), // SUQADDv1i8 |
2426 | 1.59k | UINT64_C(245381120), // SUQADDv2i32 |
2427 | 1.59k | UINT64_C(1323317248), // SUQADDv2i64 |
2428 | 1.59k | UINT64_C(241186816), // SUQADDv4i16 |
2429 | 1.59k | UINT64_C(1319122944), // SUQADDv4i32 |
2430 | 1.59k | UINT64_C(1314928640), // SUQADDv8i16 |
2431 | 1.59k | UINT64_C(236992512), // SUQADDv8i8 |
2432 | 1.59k | UINT64_C(3556769793), // SVC |
2433 | 1.59k | UINT64_C(954236928), // SWPALb |
2434 | 1.59k | UINT64_C(4175462400), // SWPALd |
2435 | 1.59k | UINT64_C(2027978752), // SWPALh |
2436 | 1.59k | UINT64_C(3101720576), // SWPALs |
2437 | 1.59k | UINT64_C(950042624), // SWPAb |
2438 | 1.59k | UINT64_C(4171268096), // SWPAd |
2439 | 1.59k | UINT64_C(2023784448), // SWPAh |
2440 | 1.59k | UINT64_C(3097526272), // SWPAs |
2441 | 1.59k | UINT64_C(945848320), // SWPLb |
2442 | 1.59k | UINT64_C(4167073792), // SWPLd |
2443 | 1.59k | UINT64_C(2019590144), // SWPLh |
2444 | 1.59k | UINT64_C(3093331968), // SWPLs |
2445 | 1.59k | UINT64_C(941654016), // SWPb |
2446 | 1.59k | UINT64_C(4162879488), // SWPd |
2447 | 1.59k | UINT64_C(2015395840), // SWPh |
2448 | 1.59k | UINT64_C(3089137664), // SWPs |
2449 | 1.59k | UINT64_C(3576168448), // SYSLxt |
2450 | 1.59k | UINT64_C(3574071296), // SYSxt |
2451 | 1.59k | UINT64_C(1308647424), // TBLv16i8Four |
2452 | 1.59k | UINT64_C(1308622848), // TBLv16i8One |
2453 | 1.59k | UINT64_C(1308639232), // TBLv16i8Three |
2454 | 1.59k | UINT64_C(1308631040), // TBLv16i8Two |
2455 | 1.59k | UINT64_C(234905600), // TBLv8i8Four |
2456 | 1.59k | UINT64_C(234881024), // TBLv8i8One |
2457 | 1.59k | UINT64_C(234897408), // TBLv8i8Three |
2458 | 1.59k | UINT64_C(234889216), // TBLv8i8Two |
2459 | 1.59k | UINT64_C(922746880), // TBNZW |
2460 | 1.59k | UINT64_C(3070230528), // TBNZX |
2461 | 1.59k | UINT64_C(1308651520), // TBXv16i8Four |
2462 | 1.59k | UINT64_C(1308626944), // TBXv16i8One |
2463 | 1.59k | UINT64_C(1308643328), // TBXv16i8Three |
2464 | 1.59k | UINT64_C(1308635136), // TBXv16i8Two |
2465 | 1.59k | UINT64_C(234909696), // TBXv8i8Four |
2466 | 1.59k | UINT64_C(234885120), // TBXv8i8One |
2467 | 1.59k | UINT64_C(234901504), // TBXv8i8Three |
2468 | 1.59k | UINT64_C(234893312), // TBXv8i8Two |
2469 | 1.59k | UINT64_C(905969664), // TBZW |
2470 | 1.59k | UINT64_C(3053453312), // TBZX |
2471 | 1.59k | UINT64_C(0), // TCRETURNdi |
2472 | 1.59k | UINT64_C(0), // TCRETURNri |
2473 | 1.59k | UINT64_C(0), // TLSDESCCALL |
2474 | 1.59k | UINT64_C(0), // TLSDESC_CALLSEQ |
2475 | 1.59k | UINT64_C(1308633088), // TRN1v16i8 |
2476 | 1.59k | UINT64_C(243279872), // TRN1v2i32 |
2477 | 1.59k | UINT64_C(1321216000), // TRN1v2i64 |
2478 | 1.59k | UINT64_C(239085568), // TRN1v4i16 |
2479 | 1.59k | UINT64_C(1317021696), // TRN1v4i32 |
2480 | 1.59k | UINT64_C(1312827392), // TRN1v8i16 |
2481 | 1.59k | UINT64_C(234891264), // TRN1v8i8 |
2482 | 1.59k | UINT64_C(1308649472), // TRN2v16i8 |
2483 | 1.59k | UINT64_C(243296256), // TRN2v2i32 |
2484 | 1.59k | UINT64_C(1321232384), // TRN2v2i64 |
2485 | 1.59k | UINT64_C(239101952), // TRN2v4i16 |
2486 | 1.59k | UINT64_C(1317038080), // TRN2v4i32 |
2487 | 1.59k | UINT64_C(1312843776), // TRN2v8i16 |
2488 | 1.59k | UINT64_C(234907648), // TRN2v8i8 |
2489 | 1.59k | UINT64_C(1847611392), // UABALv16i8_v8i16 |
2490 | 1.59k | UINT64_C(782258176), // UABALv2i32_v2i64 |
2491 | 1.59k | UINT64_C(778063872), // UABALv4i16_v4i32 |
2492 | 1.59k | UINT64_C(1856000000), // UABALv4i32_v2i64 |
2493 | 1.59k | UINT64_C(1851805696), // UABALv8i16_v4i32 |
2494 | 1.59k | UINT64_C(773869568), // UABALv8i8_v8i16 |
2495 | 1.59k | UINT64_C(1847622656), // UABAv16i8 |
2496 | 1.59k | UINT64_C(782269440), // UABAv2i32 |
2497 | 1.59k | UINT64_C(778075136), // UABAv4i16 |
2498 | 1.59k | UINT64_C(1856011264), // UABAv4i32 |
2499 | 1.59k | UINT64_C(1851816960), // UABAv8i16 |
2500 | 1.59k | UINT64_C(773880832), // UABAv8i8 |
2501 | 1.59k | UINT64_C(1847619584), // UABDLv16i8_v8i16 |
2502 | 1.59k | UINT64_C(782266368), // UABDLv2i32_v2i64 |
2503 | 1.59k | UINT64_C(778072064), // UABDLv4i16_v4i32 |
2504 | 1.59k | UINT64_C(1856008192), // UABDLv4i32_v2i64 |
2505 | 1.59k | UINT64_C(1851813888), // UABDLv8i16_v4i32 |
2506 | 1.59k | UINT64_C(773877760), // UABDLv8i8_v8i16 |
2507 | 1.59k | UINT64_C(1847620608), // UABDv16i8 |
2508 | 1.59k | UINT64_C(782267392), // UABDv2i32 |
2509 | 1.59k | UINT64_C(778073088), // UABDv4i16 |
2510 | 1.59k | UINT64_C(1856009216), // UABDv4i32 |
2511 | 1.59k | UINT64_C(1851814912), // UABDv8i16 |
2512 | 1.59k | UINT64_C(773878784), // UABDv8i8 |
2513 | 1.59k | UINT64_C(1847617536), // UADALPv16i8_v8i16 |
2514 | 1.59k | UINT64_C(782264320), // UADALPv2i32_v1i64 |
2515 | 1.59k | UINT64_C(778070016), // UADALPv4i16_v2i32 |
2516 | 1.59k | UINT64_C(1856006144), // UADALPv4i32_v2i64 |
2517 | 1.59k | UINT64_C(1851811840), // UADALPv8i16_v4i32 |
2518 | 1.59k | UINT64_C(773875712), // UADALPv8i8_v4i16 |
2519 | 1.59k | UINT64_C(1847601152), // UADDLPv16i8_v8i16 |
2520 | 1.59k | UINT64_C(782247936), // UADDLPv2i32_v1i64 |
2521 | 1.59k | UINT64_C(778053632), // UADDLPv4i16_v2i32 |
2522 | 1.59k | UINT64_C(1855989760), // UADDLPv4i32_v2i64 |
2523 | 1.59k | UINT64_C(1851795456), // UADDLPv8i16_v4i32 |
2524 | 1.59k | UINT64_C(773859328), // UADDLPv8i8_v4i16 |
2525 | 1.59k | UINT64_C(1848653824), // UADDLVv16i8v |
2526 | 1.59k | UINT64_C(779106304), // UADDLVv4i16v |
2527 | 1.59k | UINT64_C(1857042432), // UADDLVv4i32v |
2528 | 1.59k | UINT64_C(1852848128), // UADDLVv8i16v |
2529 | 1.59k | UINT64_C(774912000), // UADDLVv8i8v |
2530 | 1.59k | UINT64_C(1847590912), // UADDLv16i8_v8i16 |
2531 | 1.59k | UINT64_C(782237696), // UADDLv2i32_v2i64 |
2532 | 1.59k | UINT64_C(778043392), // UADDLv4i16_v4i32 |
2533 | 1.59k | UINT64_C(1855979520), // UADDLv4i32_v2i64 |
2534 | 1.59k | UINT64_C(1851785216), // UADDLv8i16_v4i32 |
2535 | 1.59k | UINT64_C(773849088), // UADDLv8i8_v8i16 |
2536 | 1.59k | UINT64_C(1847595008), // UADDWv16i8_v8i16 |
2537 | 1.59k | UINT64_C(782241792), // UADDWv2i32_v2i64 |
2538 | 1.59k | UINT64_C(778047488), // UADDWv4i16_v4i32 |
2539 | 1.59k | UINT64_C(1855983616), // UADDWv4i32_v2i64 |
2540 | 1.59k | UINT64_C(1851789312), // UADDWv8i16_v4i32 |
2541 | 1.59k | UINT64_C(773853184), // UADDWv8i8_v8i16 |
2542 | 1.59k | UINT64_C(1392508928), // UBFMWri |
2543 | 1.59k | UINT64_C(3544186880), // UBFMXri |
2544 | 1.59k | UINT64_C(507740160), // UCVTFSWDri |
2545 | 1.59k | UINT64_C(516128768), // UCVTFSWHri |
2546 | 1.59k | UINT64_C(503545856), // UCVTFSWSri |
2547 | 1.59k | UINT64_C(2655191040), // UCVTFSXDri |
2548 | 1.59k | UINT64_C(2663579648), // UCVTFSXHri |
2549 | 1.59k | UINT64_C(2650996736), // UCVTFSXSri |
2550 | 1.59k | UINT64_C(509804544), // UCVTFUWDri |
2551 | 1.59k | UINT64_C(518193152), // UCVTFUWHri |
2552 | 1.59k | UINT64_C(505610240), // UCVTFUWSri |
2553 | 1.59k | UINT64_C(2657288192), // UCVTFUXDri |
2554 | 1.59k | UINT64_C(2665676800), // UCVTFUXHri |
2555 | 1.59k | UINT64_C(2653093888), // UCVTFUXSri |
2556 | 1.59k | UINT64_C(2134959104), // UCVTFd |
2557 | 1.59k | UINT64_C(2131813376), // UCVTFh |
2558 | 1.59k | UINT64_C(2132861952), // UCVTFs |
2559 | 1.59k | UINT64_C(2121914368), // UCVTFv1i16 |
2560 | 1.59k | UINT64_C(2116147200), // UCVTFv1i32 |
2561 | 1.59k | UINT64_C(2120341504), // UCVTFv1i64 |
2562 | 1.59k | UINT64_C(773969920), // UCVTFv2f32 |
2563 | 1.59k | UINT64_C(1851906048), // UCVTFv2f64 |
2564 | 1.59k | UINT64_C(790684672), // UCVTFv2i32_shift |
2565 | 1.59k | UINT64_C(1866523648), // UCVTFv2i64_shift |
2566 | 1.59k | UINT64_C(779737088), // UCVTFv4f16 |
2567 | 1.59k | UINT64_C(1847711744), // UCVTFv4f32 |
2568 | 1.59k | UINT64_C(789636096), // UCVTFv4i16_shift |
2569 | 1.59k | UINT64_C(1864426496), // UCVTFv4i32_shift |
2570 | 1.59k | UINT64_C(1853478912), // UCVTFv8f16 |
2571 | 1.59k | UINT64_C(1863377920), // UCVTFv8i16_shift |
2572 | 1.59k | UINT64_C(448792576), // UDIVWr |
2573 | 1.59k | UINT64_C(2596276224), // UDIVXr |
2574 | 1.59k | UINT64_C(448792576), // UDIV_IntWr |
2575 | 1.59k | UINT64_C(2596276224), // UDIV_IntXr |
2576 | 1.59k | UINT64_C(1847591936), // UHADDv16i8 |
2577 | 1.59k | UINT64_C(782238720), // UHADDv2i32 |
2578 | 1.59k | UINT64_C(778044416), // UHADDv4i16 |
2579 | 1.59k | UINT64_C(1855980544), // UHADDv4i32 |
2580 | 1.59k | UINT64_C(1851786240), // UHADDv8i16 |
2581 | 1.59k | UINT64_C(773850112), // UHADDv8i8 |
2582 | 1.59k | UINT64_C(1847600128), // UHSUBv16i8 |
2583 | 1.59k | UINT64_C(782246912), // UHSUBv2i32 |
2584 | 1.59k | UINT64_C(778052608), // UHSUBv4i16 |
2585 | 1.59k | UINT64_C(1855988736), // UHSUBv4i32 |
2586 | 1.59k | UINT64_C(1851794432), // UHSUBv8i16 |
2587 | 1.59k | UINT64_C(773858304), // UHSUBv8i8 |
2588 | 1.59k | UINT64_C(2610954240), // UMADDLrrr |
2589 | 1.59k | UINT64_C(1847632896), // UMAXPv16i8 |
2590 | 1.59k | UINT64_C(782279680), // UMAXPv2i32 |
2591 | 1.59k | UINT64_C(778085376), // UMAXPv4i16 |
2592 | 1.59k | UINT64_C(1856021504), // UMAXPv4i32 |
2593 | 1.59k | UINT64_C(1851827200), // UMAXPv8i16 |
2594 | 1.59k | UINT64_C(773891072), // UMAXPv8i8 |
2595 | 1.59k | UINT64_C(1848682496), // UMAXVv16i8v |
2596 | 1.59k | UINT64_C(779134976), // UMAXVv4i16v |
2597 | 1.59k | UINT64_C(1857071104), // UMAXVv4i32v |
2598 | 1.59k | UINT64_C(1852876800), // UMAXVv8i16v |
2599 | 1.59k | UINT64_C(774940672), // UMAXVv8i8v |
2600 | 1.59k | UINT64_C(1847616512), // UMAXv16i8 |
2601 | 1.59k | UINT64_C(782263296), // UMAXv2i32 |
2602 | 1.59k | UINT64_C(778068992), // UMAXv4i16 |
2603 | 1.59k | UINT64_C(1856005120), // UMAXv4i32 |
2604 | 1.59k | UINT64_C(1851810816), // UMAXv8i16 |
2605 | 1.59k | UINT64_C(773874688), // UMAXv8i8 |
2606 | 1.59k | UINT64_C(1847634944), // UMINPv16i8 |
2607 | 1.59k | UINT64_C(782281728), // UMINPv2i32 |
2608 | 1.59k | UINT64_C(778087424), // UMINPv4i16 |
2609 | 1.59k | UINT64_C(1856023552), // UMINPv4i32 |
2610 | 1.59k | UINT64_C(1851829248), // UMINPv8i16 |
2611 | 1.59k | UINT64_C(773893120), // UMINPv8i8 |
2612 | 1.59k | UINT64_C(1848748032), // UMINVv16i8v |
2613 | 1.59k | UINT64_C(779200512), // UMINVv4i16v |
2614 | 1.59k | UINT64_C(1857136640), // UMINVv4i32v |
2615 | 1.59k | UINT64_C(1852942336), // UMINVv8i16v |
2616 | 1.59k | UINT64_C(775006208), // UMINVv8i8v |
2617 | 1.59k | UINT64_C(1847618560), // UMINv16i8 |
2618 | 1.59k | UINT64_C(782265344), // UMINv2i32 |
2619 | 1.59k | UINT64_C(778071040), // UMINv4i16 |
2620 | 1.59k | UINT64_C(1856007168), // UMINv4i32 |
2621 | 1.59k | UINT64_C(1851812864), // UMINv8i16 |
2622 | 1.59k | UINT64_C(773876736), // UMINv8i8 |
2623 | 1.59k | UINT64_C(1847623680), // UMLALv16i8_v8i16 |
2624 | 1.59k | UINT64_C(796925952), // UMLALv2i32_indexed |
2625 | 1.59k | UINT64_C(782270464), // UMLALv2i32_v2i64 |
2626 | 1.59k | UINT64_C(792731648), // UMLALv4i16_indexed |
2627 | 1.59k | UINT64_C(778076160), // UMLALv4i16_v4i32 |
2628 | 1.59k | UINT64_C(1870667776), // UMLALv4i32_indexed |
2629 | 1.59k | UINT64_C(1856012288), // UMLALv4i32_v2i64 |
2630 | 1.59k | UINT64_C(1866473472), // UMLALv8i16_indexed |
2631 | 1.59k | UINT64_C(1851817984), // UMLALv8i16_v4i32 |
2632 | 1.59k | UINT64_C(773881856), // UMLALv8i8_v8i16 |
2633 | 1.59k | UINT64_C(1847631872), // UMLSLv16i8_v8i16 |
2634 | 1.59k | UINT64_C(796942336), // UMLSLv2i32_indexed |
2635 | 1.59k | UINT64_C(782278656), // UMLSLv2i32_v2i64 |
2636 | 1.59k | UINT64_C(792748032), // UMLSLv4i16_indexed |
2637 | 1.59k | UINT64_C(778084352), // UMLSLv4i16_v4i32 |
2638 | 1.59k | UINT64_C(1870684160), // UMLSLv4i32_indexed |
2639 | 1.59k | UINT64_C(1856020480), // UMLSLv4i32_v2i64 |
2640 | 1.59k | UINT64_C(1866489856), // UMLSLv8i16_indexed |
2641 | 1.59k | UINT64_C(1851826176), // UMLSLv8i16_v4i32 |
2642 | 1.59k | UINT64_C(773890048), // UMLSLv8i8_v8i16 |
2643 | 1.59k | UINT64_C(235027456), // UMOVvi16 |
2644 | 1.59k | UINT64_C(235158528), // UMOVvi32 |
2645 | 1.59k | UINT64_C(1309162496), // UMOVvi64 |
2646 | 1.59k | UINT64_C(234961920), // UMOVvi8 |
2647 | 1.59k | UINT64_C(2610987008), // UMSUBLrrr |
2648 | 1.59k | UINT64_C(2613051392), // UMULHrr |
2649 | 1.59k | UINT64_C(1847640064), // UMULLv16i8_v8i16 |
2650 | 1.59k | UINT64_C(796958720), // UMULLv2i32_indexed |
2651 | 1.59k | UINT64_C(782286848), // UMULLv2i32_v2i64 |
2652 | 1.59k | UINT64_C(792764416), // UMULLv4i16_indexed |
2653 | 1.59k | UINT64_C(778092544), // UMULLv4i16_v4i32 |
2654 | 1.59k | UINT64_C(1870700544), // UMULLv4i32_indexed |
2655 | 1.59k | UINT64_C(1856028672), // UMULLv4i32_v2i64 |
2656 | 1.59k | UINT64_C(1866506240), // UMULLv8i16_indexed |
2657 | 1.59k | UINT64_C(1851834368), // UMULLv8i16_v4i32 |
2658 | 1.59k | UINT64_C(773898240), // UMULLv8i8_v8i16 |
2659 | 1.59k | UINT64_C(1847593984), // UQADDv16i8 |
2660 | 1.59k | UINT64_C(2120223744), // UQADDv1i16 |
2661 | 1.59k | UINT64_C(2124418048), // UQADDv1i32 |
2662 | 1.59k | UINT64_C(2128612352), // UQADDv1i64 |
2663 | 1.59k | UINT64_C(2116029440), // UQADDv1i8 |
2664 | 1.59k | UINT64_C(782240768), // UQADDv2i32 |
2665 | 1.59k | UINT64_C(1860176896), // UQADDv2i64 |
2666 | 1.59k | UINT64_C(778046464), // UQADDv4i16 |
2667 | 1.59k | UINT64_C(1855982592), // UQADDv4i32 |
2668 | 1.59k | UINT64_C(1851788288), // UQADDv8i16 |
2669 | 1.59k | UINT64_C(773852160), // UQADDv8i8 |
2670 | 1.59k | UINT64_C(1847614464), // UQRSHLv16i8 |
2671 | 1.59k | UINT64_C(2120244224), // UQRSHLv1i16 |
2672 | 1.59k | UINT64_C(2124438528), // UQRSHLv1i32 |
2673 | 1.59k | UINT64_C(2128632832), // UQRSHLv1i64 |
2674 | 1.59k | UINT64_C(2116049920), // UQRSHLv1i8 |
2675 | 1.59k | UINT64_C(782261248), // UQRSHLv2i32 |
2676 | 1.59k | UINT64_C(1860197376), // UQRSHLv2i64 |
2677 | 1.59k | UINT64_C(778066944), // UQRSHLv4i16 |
2678 | 1.59k | UINT64_C(1856003072), // UQRSHLv4i32 |
2679 | 1.59k | UINT64_C(1851808768), // UQRSHLv8i16 |
2680 | 1.59k | UINT64_C(773872640), // UQRSHLv8i8 |
2681 | 1.59k | UINT64_C(2131270656), // UQRSHRNb |
2682 | 1.59k | UINT64_C(2131794944), // UQRSHRNh |
2683 | 1.59k | UINT64_C(2132843520), // UQRSHRNs |
2684 | 1.59k | UINT64_C(1862835200), // UQRSHRNv16i8_shift |
2685 | 1.59k | UINT64_C(790666240), // UQRSHRNv2i32_shift |
2686 | 1.59k | UINT64_C(789617664), // UQRSHRNv4i16_shift |
2687 | 1.59k | UINT64_C(1864408064), // UQRSHRNv4i32_shift |
2688 | 1.59k | UINT64_C(1863359488), // UQRSHRNv8i16_shift |
2689 | 1.59k | UINT64_C(789093376), // UQRSHRNv8i8_shift |
2690 | 1.59k | UINT64_C(2131260416), // UQSHLb |
2691 | 1.59k | UINT64_C(2134930432), // UQSHLd |
2692 | 1.59k | UINT64_C(2131784704), // UQSHLh |
2693 | 1.59k | UINT64_C(2132833280), // UQSHLs |
2694 | 1.59k | UINT64_C(1847610368), // UQSHLv16i8 |
2695 | 1.59k | UINT64_C(1862824960), // UQSHLv16i8_shift |
2696 | 1.59k | UINT64_C(2120240128), // UQSHLv1i16 |
2697 | 1.59k | UINT64_C(2124434432), // UQSHLv1i32 |
2698 | 1.59k | UINT64_C(2128628736), // UQSHLv1i64 |
2699 | 1.59k | UINT64_C(2116045824), // UQSHLv1i8 |
2700 | 1.59k | UINT64_C(782257152), // UQSHLv2i32 |
2701 | 1.59k | UINT64_C(790656000), // UQSHLv2i32_shift |
2702 | 1.59k | UINT64_C(1860193280), // UQSHLv2i64 |
2703 | 1.59k | UINT64_C(1866494976), // UQSHLv2i64_shift |
2704 | 1.59k | UINT64_C(778062848), // UQSHLv4i16 |
2705 | 1.59k | UINT64_C(789607424), // UQSHLv4i16_shift |
2706 | 1.59k | UINT64_C(1855998976), // UQSHLv4i32 |
2707 | 1.59k | UINT64_C(1864397824), // UQSHLv4i32_shift |
2708 | 1.59k | UINT64_C(1851804672), // UQSHLv8i16 |
2709 | 1.59k | UINT64_C(1863349248), // UQSHLv8i16_shift |
2710 | 1.59k | UINT64_C(773868544), // UQSHLv8i8 |
2711 | 1.59k | UINT64_C(789083136), // UQSHLv8i8_shift |
2712 | 1.59k | UINT64_C(2131268608), // UQSHRNb |
2713 | 1.59k | UINT64_C(2131792896), // UQSHRNh |
2714 | 1.59k | UINT64_C(2132841472), // UQSHRNs |
2715 | 1.59k | UINT64_C(1862833152), // UQSHRNv16i8_shift |
2716 | 1.59k | UINT64_C(790664192), // UQSHRNv2i32_shift |
2717 | 1.59k | UINT64_C(789615616), // UQSHRNv4i16_shift |
2718 | 1.59k | UINT64_C(1864406016), // UQSHRNv4i32_shift |
2719 | 1.59k | UINT64_C(1863357440), // UQSHRNv8i16_shift |
2720 | 1.59k | UINT64_C(789091328), // UQSHRNv8i8_shift |
2721 | 1.59k | UINT64_C(1847602176), // UQSUBv16i8 |
2722 | 1.59k | UINT64_C(2120231936), // UQSUBv1i16 |
2723 | 1.59k | UINT64_C(2124426240), // UQSUBv1i32 |
2724 | 1.59k | UINT64_C(2128620544), // UQSUBv1i64 |
2725 | 1.59k | UINT64_C(2116037632), // UQSUBv1i8 |
2726 | 1.59k | UINT64_C(782248960), // UQSUBv2i32 |
2727 | 1.59k | UINT64_C(1860185088), // UQSUBv2i64 |
2728 | 1.59k | UINT64_C(778054656), // UQSUBv4i16 |
2729 | 1.59k | UINT64_C(1855990784), // UQSUBv4i32 |
2730 | 1.59k | UINT64_C(1851796480), // UQSUBv8i16 |
2731 | 1.59k | UINT64_C(773860352), // UQSUBv8i8 |
2732 | 1.59k | UINT64_C(1847674880), // UQXTNv16i8 |
2733 | 1.59k | UINT64_C(2120304640), // UQXTNv1i16 |
2734 | 1.59k | UINT64_C(2124498944), // UQXTNv1i32 |
2735 | 1.59k | UINT64_C(2116110336), // UQXTNv1i8 |
2736 | 1.59k | UINT64_C(782321664), // UQXTNv2i32 |
2737 | 1.59k | UINT64_C(778127360), // UQXTNv4i16 |
2738 | 1.59k | UINT64_C(1856063488), // UQXTNv4i32 |
2739 | 1.59k | UINT64_C(1851869184), // UQXTNv8i16 |
2740 | 1.59k | UINT64_C(773933056), // UQXTNv8i8 |
2741 | 1.59k | UINT64_C(245483520), // URECPEv2i32 |
2742 | 1.59k | UINT64_C(1319225344), // URECPEv4i32 |
2743 | 1.59k | UINT64_C(1847596032), // URHADDv16i8 |
2744 | 1.59k | UINT64_C(782242816), // URHADDv2i32 |
2745 | 1.59k | UINT64_C(778048512), // URHADDv4i16 |
2746 | 1.59k | UINT64_C(1855984640), // URHADDv4i32 |
2747 | 1.59k | UINT64_C(1851790336), // URHADDv8i16 |
2748 | 1.59k | UINT64_C(773854208), // URHADDv8i8 |
2749 | 1.59k | UINT64_C(1847612416), // URSHLv16i8 |
2750 | 1.59k | UINT64_C(2128630784), // URSHLv1i64 |
2751 | 1.59k | UINT64_C(782259200), // URSHLv2i32 |
2752 | 1.59k | UINT64_C(1860195328), // URSHLv2i64 |
2753 | 1.59k | UINT64_C(778064896), // URSHLv4i16 |
2754 | 1.59k | UINT64_C(1856001024), // URSHLv4i32 |
2755 | 1.59k | UINT64_C(1851806720), // URSHLv8i16 |
2756 | 1.59k | UINT64_C(773870592), // URSHLv8i8 |
2757 | 1.59k | UINT64_C(2134909952), // URSHRd |
2758 | 1.59k | UINT64_C(1862804480), // URSHRv16i8_shift |
2759 | 1.59k | UINT64_C(790635520), // URSHRv2i32_shift |
2760 | 1.59k | UINT64_C(1866474496), // URSHRv2i64_shift |
2761 | 1.59k | UINT64_C(789586944), // URSHRv4i16_shift |
2762 | 1.59k | UINT64_C(1864377344), // URSHRv4i32_shift |
2763 | 1.59k | UINT64_C(1863328768), // URSHRv8i16_shift |
2764 | 1.59k | UINT64_C(789062656), // URSHRv8i8_shift |
2765 | 1.59k | UINT64_C(782354432), // URSQRTEv2i32 |
2766 | 1.59k | UINT64_C(1856096256), // URSQRTEv4i32 |
2767 | 1.59k | UINT64_C(2134914048), // URSRAd |
2768 | 1.59k | UINT64_C(1862808576), // URSRAv16i8_shift |
2769 | 1.59k | UINT64_C(790639616), // URSRAv2i32_shift |
2770 | 1.59k | UINT64_C(1866478592), // URSRAv2i64_shift |
2771 | 1.59k | UINT64_C(789591040), // URSRAv4i16_shift |
2772 | 1.59k | UINT64_C(1864381440), // URSRAv4i32_shift |
2773 | 1.59k | UINT64_C(1863332864), // URSRAv8i16_shift |
2774 | 1.59k | UINT64_C(789066752), // URSRAv8i8_shift |
2775 | 1.59k | UINT64_C(1862837248), // USHLLv16i8_shift |
2776 | 1.59k | UINT64_C(790668288), // USHLLv2i32_shift |
2777 | 1.59k | UINT64_C(789619712), // USHLLv4i16_shift |
2778 | 1.59k | UINT64_C(1864410112), // USHLLv4i32_shift |
2779 | 1.59k | UINT64_C(1863361536), // USHLLv8i16_shift |
2780 | 1.59k | UINT64_C(789095424), // USHLLv8i8_shift |
2781 | 1.59k | UINT64_C(1847608320), // USHLv16i8 |
2782 | 1.59k | UINT64_C(2128626688), // USHLv1i64 |
2783 | 1.59k | UINT64_C(782255104), // USHLv2i32 |
2784 | 1.59k | UINT64_C(1860191232), // USHLv2i64 |
2785 | 1.59k | UINT64_C(778060800), // USHLv4i16 |
2786 | 1.59k | UINT64_C(1855996928), // USHLv4i32 |
2787 | 1.59k | UINT64_C(1851802624), // USHLv8i16 |
2788 | 1.59k | UINT64_C(773866496), // USHLv8i8 |
2789 | 1.59k | UINT64_C(2134901760), // USHRd |
2790 | 1.59k | UINT64_C(1862796288), // USHRv16i8_shift |
2791 | 1.59k | UINT64_C(790627328), // USHRv2i32_shift |
2792 | 1.59k | UINT64_C(1866466304), // USHRv2i64_shift |
2793 | 1.59k | UINT64_C(789578752), // USHRv4i16_shift |
2794 | 1.59k | UINT64_C(1864369152), // USHRv4i32_shift |
2795 | 1.59k | UINT64_C(1863320576), // USHRv8i16_shift |
2796 | 1.59k | UINT64_C(789054464), // USHRv8i8_shift |
2797 | 1.59k | UINT64_C(1847605248), // USQADDv16i8 |
2798 | 1.59k | UINT64_C(2120235008), // USQADDv1i16 |
2799 | 1.59k | UINT64_C(2124429312), // USQADDv1i32 |
2800 | 1.59k | UINT64_C(2128623616), // USQADDv1i64 |
2801 | 1.59k | UINT64_C(2116040704), // USQADDv1i8 |
2802 | 1.59k | UINT64_C(782252032), // USQADDv2i32 |
2803 | 1.59k | UINT64_C(1860188160), // USQADDv2i64 |
2804 | 1.59k | UINT64_C(778057728), // USQADDv4i16 |
2805 | 1.59k | UINT64_C(1855993856), // USQADDv4i32 |
2806 | 1.59k | UINT64_C(1851799552), // USQADDv8i16 |
2807 | 1.59k | UINT64_C(773863424), // USQADDv8i8 |
2808 | 1.59k | UINT64_C(2134905856), // USRAd |
2809 | 1.59k | UINT64_C(1862800384), // USRAv16i8_shift |
2810 | 1.59k | UINT64_C(790631424), // USRAv2i32_shift |
2811 | 1.59k | UINT64_C(1866470400), // USRAv2i64_shift |
2812 | 1.59k | UINT64_C(789582848), // USRAv4i16_shift |
2813 | 1.59k | UINT64_C(1864373248), // USRAv4i32_shift |
2814 | 1.59k | UINT64_C(1863324672), // USRAv8i16_shift |
2815 | 1.59k | UINT64_C(789058560), // USRAv8i8_shift |
2816 | 1.59k | UINT64_C(1847599104), // USUBLv16i8_v8i16 |
2817 | 1.59k | UINT64_C(782245888), // USUBLv2i32_v2i64 |
2818 | 1.59k | UINT64_C(778051584), // USUBLv4i16_v4i32 |
2819 | 1.59k | UINT64_C(1855987712), // USUBLv4i32_v2i64 |
2820 | 1.59k | UINT64_C(1851793408), // USUBLv8i16_v4i32 |
2821 | 1.59k | UINT64_C(773857280), // USUBLv8i8_v8i16 |
2822 | 1.59k | UINT64_C(1847603200), // USUBWv16i8_v8i16 |
2823 | 1.59k | UINT64_C(782249984), // USUBWv2i32_v2i64 |
2824 | 1.59k | UINT64_C(778055680), // USUBWv4i16_v4i32 |
2825 | 1.59k | UINT64_C(1855991808), // USUBWv4i32_v2i64 |
2826 | 1.59k | UINT64_C(1851797504), // USUBWv8i16_v4i32 |
2827 | 1.59k | UINT64_C(773861376), // USUBWv8i8_v8i16 |
2828 | 1.59k | UINT64_C(1308628992), // UZP1v16i8 |
2829 | 1.59k | UINT64_C(243275776), // UZP1v2i32 |
2830 | 1.59k | UINT64_C(1321211904), // UZP1v2i64 |
2831 | 1.59k | UINT64_C(239081472), // UZP1v4i16 |
2832 | 1.59k | UINT64_C(1317017600), // UZP1v4i32 |
2833 | 1.59k | UINT64_C(1312823296), // UZP1v8i16 |
2834 | 1.59k | UINT64_C(234887168), // UZP1v8i8 |
2835 | 1.59k | UINT64_C(1308645376), // UZP2v16i8 |
2836 | 1.59k | UINT64_C(243292160), // UZP2v2i32 |
2837 | 1.59k | UINT64_C(1321228288), // UZP2v2i64 |
2838 | 1.59k | UINT64_C(239097856), // UZP2v4i16 |
2839 | 1.59k | UINT64_C(1317033984), // UZP2v4i32 |
2840 | 1.59k | UINT64_C(1312839680), // UZP2v8i16 |
2841 | 1.59k | UINT64_C(234903552), // UZP2v8i8 |
2842 | 1.59k | UINT64_C(1310795776), // XTNv16i8 |
2843 | 1.59k | UINT64_C(245442560), // XTNv2i32 |
2844 | 1.59k | UINT64_C(241248256), // XTNv4i16 |
2845 | 1.59k | UINT64_C(1319184384), // XTNv4i32 |
2846 | 1.59k | UINT64_C(1314990080), // XTNv8i16 |
2847 | 1.59k | UINT64_C(237053952), // XTNv8i8 |
2848 | 1.59k | UINT64_C(1308637184), // ZIP1v16i8 |
2849 | 1.59k | UINT64_C(243283968), // ZIP1v2i32 |
2850 | 1.59k | UINT64_C(1321220096), // ZIP1v2i64 |
2851 | 1.59k | UINT64_C(239089664), // ZIP1v4i16 |
2852 | 1.59k | UINT64_C(1317025792), // ZIP1v4i32 |
2853 | 1.59k | UINT64_C(1312831488), // ZIP1v8i16 |
2854 | 1.59k | UINT64_C(234895360), // ZIP1v8i8 |
2855 | 1.59k | UINT64_C(1308653568), // ZIP2v16i8 |
2856 | 1.59k | UINT64_C(243300352), // ZIP2v2i32 |
2857 | 1.59k | UINT64_C(1321236480), // ZIP2v2i64 |
2858 | 1.59k | UINT64_C(239106048), // ZIP2v4i16 |
2859 | 1.59k | UINT64_C(1317042176), // ZIP2v4i32 |
2860 | 1.59k | UINT64_C(1312847872), // ZIP2v8i16 |
2861 | 1.59k | UINT64_C(234911744), // ZIP2v8i8 |
2862 | 1.59k | UINT64_C(0) |
2863 | 1.59k | }; |
2864 | 1.59k | const unsigned opcode = MI.getOpcode(); |
2865 | 1.59k | uint64_t Value = InstBits[opcode]; |
2866 | 1.59k | uint64_t op = 0; |
2867 | 1.59k | (void)op; // suppress warning |
2868 | 1.59k | switch (opcode) { |
2869 | 0 | case AArch64::ADDSWrr: |
2870 | 0 | case AArch64::ADDSXrr: |
2871 | 0 | case AArch64::ADDWrr: |
2872 | 0 | case AArch64::ADDXrr: |
2873 | 0 | case AArch64::ADJCALLSTACKDOWN: |
2874 | 0 | case AArch64::ADJCALLSTACKUP: |
2875 | 0 | case AArch64::ANDSWrr: |
2876 | 0 | case AArch64::ANDSXrr: |
2877 | 0 | case AArch64::ANDWrr: |
2878 | 0 | case AArch64::ANDXrr: |
2879 | 0 | case AArch64::BICSWrr: |
2880 | 0 | case AArch64::BICSXrr: |
2881 | 0 | case AArch64::BICWrr: |
2882 | 0 | case AArch64::BICXrr: |
2883 | 0 | case AArch64::DRPS: |
2884 | 0 | case AArch64::EONWrr: |
2885 | 0 | case AArch64::EONXrr: |
2886 | 0 | case AArch64::EORWrr: |
2887 | 0 | case AArch64::EORXrr: |
2888 | 0 | case AArch64::ERET: |
2889 | 0 | case AArch64::F128CSEL: |
2890 | 0 | case AArch64::LOADgot: |
2891 | 0 | case AArch64::MOVaddr: |
2892 | 0 | case AArch64::MOVaddrBA: |
2893 | 0 | case AArch64::MOVaddrCP: |
2894 | 0 | case AArch64::MOVaddrEXT: |
2895 | 0 | case AArch64::MOVaddrJT: |
2896 | 0 | case AArch64::MOVaddrTLS: |
2897 | 0 | case AArch64::MOVi32imm: |
2898 | 0 | case AArch64::MOVi64imm: |
2899 | 0 | case AArch64::ORNWrr: |
2900 | 0 | case AArch64::ORNXrr: |
2901 | 0 | case AArch64::ORRWrr: |
2902 | 0 | case AArch64::ORRXrr: |
2903 | 0 | case AArch64::RET_ReallyLR: |
2904 | 0 | case AArch64::SUBSWrr: |
2905 | 0 | case AArch64::SUBSXrr: |
2906 | 0 | case AArch64::SUBWrr: |
2907 | 0 | case AArch64::SUBXrr: |
2908 | 0 | case AArch64::TCRETURNdi: |
2909 | 0 | case AArch64::TCRETURNri: |
2910 | 0 | case AArch64::TLSDESCCALL: |
2911 | 0 | case AArch64::TLSDESC_CALLSEQ: { |
2912 | 0 | break; |
2913 | 0 | } |
2914 | 93 | case AArch64::CLREX: |
2915 | 93 | case AArch64::DMB: |
2916 | 93 | case AArch64::DSB: |
2917 | 222 | case AArch64::ISB: { |
2918 | | // op: CRm |
2919 | 222 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
2920 | 222 | Value |= (op & UINT64_C(15)) << 8; |
2921 | 222 | break; |
2922 | 93 | } |
2923 | 0 | case AArch64::ABSv16i8: |
2924 | 0 | case AArch64::ABSv1i64: |
2925 | 0 | case AArch64::ABSv2i32: |
2926 | 0 | case AArch64::ABSv2i64: |
2927 | 0 | case AArch64::ABSv4i16: |
2928 | 0 | case AArch64::ABSv4i32: |
2929 | 0 | case AArch64::ABSv8i16: |
2930 | 0 | case AArch64::ABSv8i8: |
2931 | 0 | case AArch64::ADDPv2i64p: |
2932 | 0 | case AArch64::ADDVv16i8v: |
2933 | 0 | case AArch64::ADDVv4i16v: |
2934 | 0 | case AArch64::ADDVv4i32v: |
2935 | 0 | case AArch64::ADDVv8i16v: |
2936 | 0 | case AArch64::ADDVv8i8v: |
2937 | 0 | case AArch64::AESIMCrr: |
2938 | 0 | case AArch64::AESMCrr: |
2939 | 0 | case AArch64::CLSWr: |
2940 | 0 | case AArch64::CLSXr: |
2941 | 0 | case AArch64::CLSv16i8: |
2942 | 0 | case AArch64::CLSv2i32: |
2943 | 0 | case AArch64::CLSv4i16: |
2944 | 0 | case AArch64::CLSv4i32: |
2945 | 0 | case AArch64::CLSv8i16: |
2946 | 0 | case AArch64::CLSv8i8: |
2947 | 0 | case AArch64::CLZWr: |
2948 | 0 | case AArch64::CLZXr: |
2949 | 0 | case AArch64::CLZv16i8: |
2950 | 0 | case AArch64::CLZv2i32: |
2951 | 0 | case AArch64::CLZv4i16: |
2952 | 0 | case AArch64::CLZv4i32: |
2953 | 0 | case AArch64::CLZv8i16: |
2954 | 0 | case AArch64::CLZv8i8: |
2955 | 0 | case AArch64::CMEQv16i8rz: |
2956 | 0 | case AArch64::CMEQv1i64rz: |
2957 | 0 | case AArch64::CMEQv2i32rz: |
2958 | 0 | case AArch64::CMEQv2i64rz: |
2959 | 0 | case AArch64::CMEQv4i16rz: |
2960 | 0 | case AArch64::CMEQv4i32rz: |
2961 | 0 | case AArch64::CMEQv8i16rz: |
2962 | 0 | case AArch64::CMEQv8i8rz: |
2963 | 0 | case AArch64::CMGEv16i8rz: |
2964 | 0 | case AArch64::CMGEv1i64rz: |
2965 | 0 | case AArch64::CMGEv2i32rz: |
2966 | 0 | case AArch64::CMGEv2i64rz: |
2967 | 0 | case AArch64::CMGEv4i16rz: |
2968 | 0 | case AArch64::CMGEv4i32rz: |
2969 | 0 | case AArch64::CMGEv8i16rz: |
2970 | 0 | case AArch64::CMGEv8i8rz: |
2971 | 0 | case AArch64::CMGTv16i8rz: |
2972 | 0 | case AArch64::CMGTv1i64rz: |
2973 | 0 | case AArch64::CMGTv2i32rz: |
2974 | 0 | case AArch64::CMGTv2i64rz: |
2975 | 0 | case AArch64::CMGTv4i16rz: |
2976 | 0 | case AArch64::CMGTv4i32rz: |
2977 | 0 | case AArch64::CMGTv8i16rz: |
2978 | 0 | case AArch64::CMGTv8i8rz: |
2979 | 0 | case AArch64::CMLEv16i8rz: |
2980 | 0 | case AArch64::CMLEv1i64rz: |
2981 | 0 | case AArch64::CMLEv2i32rz: |
2982 | 0 | case AArch64::CMLEv2i64rz: |
2983 | 0 | case AArch64::CMLEv4i16rz: |
2984 | 0 | case AArch64::CMLEv4i32rz: |
2985 | 0 | case AArch64::CMLEv8i16rz: |
2986 | 0 | case AArch64::CMLEv8i8rz: |
2987 | 0 | case AArch64::CMLTv16i8rz: |
2988 | 0 | case AArch64::CMLTv1i64rz: |
2989 | 0 | case AArch64::CMLTv2i32rz: |
2990 | 0 | case AArch64::CMLTv2i64rz: |
2991 | 0 | case AArch64::CMLTv4i16rz: |
2992 | 0 | case AArch64::CMLTv4i32rz: |
2993 | 0 | case AArch64::CMLTv8i16rz: |
2994 | 0 | case AArch64::CMLTv8i8rz: |
2995 | 0 | case AArch64::CNTv16i8: |
2996 | 0 | case AArch64::CNTv8i8: |
2997 | 0 | case AArch64::DUPv16i8gpr: |
2998 | 0 | case AArch64::DUPv2i32gpr: |
2999 | 0 | case AArch64::DUPv2i64gpr: |
3000 | 0 | case AArch64::DUPv4i16gpr: |
3001 | 0 | case AArch64::DUPv4i32gpr: |
3002 | 0 | case AArch64::DUPv8i16gpr: |
3003 | 0 | case AArch64::DUPv8i8gpr: |
3004 | 0 | case AArch64::FABSDr: |
3005 | 0 | case AArch64::FABSHr: |
3006 | 0 | case AArch64::FABSSr: |
3007 | 0 | case AArch64::FABSv2f32: |
3008 | 0 | case AArch64::FABSv2f64: |
3009 | 0 | case AArch64::FABSv4f16: |
3010 | 0 | case AArch64::FABSv4f32: |
3011 | 0 | case AArch64::FABSv8f16: |
3012 | 0 | case AArch64::FADDPv2i16p: |
3013 | 0 | case AArch64::FADDPv2i32p: |
3014 | 0 | case AArch64::FADDPv2i64p: |
3015 | 0 | case AArch64::FCMEQv1i16rz: |
3016 | 0 | case AArch64::FCMEQv1i32rz: |
3017 | 0 | case AArch64::FCMEQv1i64rz: |
3018 | 0 | case AArch64::FCMEQv2i32rz: |
3019 | 0 | case AArch64::FCMEQv2i64rz: |
3020 | 0 | case AArch64::FCMEQv4i16rz: |
3021 | 0 | case AArch64::FCMEQv4i32rz: |
3022 | 0 | case AArch64::FCMEQv8i16rz: |
3023 | 0 | case AArch64::FCMGEv1i16rz: |
3024 | 0 | case AArch64::FCMGEv1i32rz: |
3025 | 0 | case AArch64::FCMGEv1i64rz: |
3026 | 0 | case AArch64::FCMGEv2i32rz: |
3027 | 0 | case AArch64::FCMGEv2i64rz: |
3028 | 0 | case AArch64::FCMGEv4i16rz: |
3029 | 0 | case AArch64::FCMGEv4i32rz: |
3030 | 0 | case AArch64::FCMGEv8i16rz: |
3031 | 0 | case AArch64::FCMGTv1i16rz: |
3032 | 0 | case AArch64::FCMGTv1i32rz: |
3033 | 0 | case AArch64::FCMGTv1i64rz: |
3034 | 0 | case AArch64::FCMGTv2i32rz: |
3035 | 0 | case AArch64::FCMGTv2i64rz: |
3036 | 0 | case AArch64::FCMGTv4i16rz: |
3037 | 0 | case AArch64::FCMGTv4i32rz: |
3038 | 0 | case AArch64::FCMGTv8i16rz: |
3039 | 0 | case AArch64::FCMLEv1i16rz: |
3040 | 0 | case AArch64::FCMLEv1i32rz: |
3041 | 0 | case AArch64::FCMLEv1i64rz: |
3042 | 0 | case AArch64::FCMLEv2i32rz: |
3043 | 0 | case AArch64::FCMLEv2i64rz: |
3044 | 0 | case AArch64::FCMLEv4i16rz: |
3045 | 0 | case AArch64::FCMLEv4i32rz: |
3046 | 0 | case AArch64::FCMLEv8i16rz: |
3047 | 0 | case AArch64::FCMLTv1i16rz: |
3048 | 0 | case AArch64::FCMLTv1i32rz: |
3049 | 0 | case AArch64::FCMLTv1i64rz: |
3050 | 0 | case AArch64::FCMLTv2i32rz: |
3051 | 0 | case AArch64::FCMLTv2i64rz: |
3052 | 0 | case AArch64::FCMLTv4i16rz: |
3053 | 0 | case AArch64::FCMLTv4i32rz: |
3054 | 0 | case AArch64::FCMLTv8i16rz: |
3055 | 0 | case AArch64::FCVTASUWDr: |
3056 | 0 | case AArch64::FCVTASUWHr: |
3057 | 0 | case AArch64::FCVTASUWSr: |
3058 | 0 | case AArch64::FCVTASUXDr: |
3059 | 0 | case AArch64::FCVTASUXHr: |
3060 | 0 | case AArch64::FCVTASUXSr: |
3061 | 0 | case AArch64::FCVTASv1f16: |
3062 | 0 | case AArch64::FCVTASv1i32: |
3063 | 0 | case AArch64::FCVTASv1i64: |
3064 | 0 | case AArch64::FCVTASv2f32: |
3065 | 0 | case AArch64::FCVTASv2f64: |
3066 | 0 | case AArch64::FCVTASv4f16: |
3067 | 0 | case AArch64::FCVTASv4f32: |
3068 | 0 | case AArch64::FCVTASv8f16: |
3069 | 0 | case AArch64::FCVTAUUWDr: |
3070 | 0 | case AArch64::FCVTAUUWHr: |
3071 | 0 | case AArch64::FCVTAUUWSr: |
3072 | 0 | case AArch64::FCVTAUUXDr: |
3073 | 0 | case AArch64::FCVTAUUXHr: |
3074 | 0 | case AArch64::FCVTAUUXSr: |
3075 | 0 | case AArch64::FCVTAUv1f16: |
3076 | 0 | case AArch64::FCVTAUv1i32: |
3077 | 0 | case AArch64::FCVTAUv1i64: |
3078 | 0 | case AArch64::FCVTAUv2f32: |
3079 | 0 | case AArch64::FCVTAUv2f64: |
3080 | 0 | case AArch64::FCVTAUv4f16: |
3081 | 0 | case AArch64::FCVTAUv4f32: |
3082 | 0 | case AArch64::FCVTAUv8f16: |
3083 | 0 | case AArch64::FCVTDHr: |
3084 | 0 | case AArch64::FCVTDSr: |
3085 | 0 | case AArch64::FCVTHDr: |
3086 | 0 | case AArch64::FCVTHSr: |
3087 | 0 | case AArch64::FCVTLv2i32: |
3088 | 0 | case AArch64::FCVTLv4i16: |
3089 | 0 | case AArch64::FCVTLv4i32: |
3090 | 0 | case AArch64::FCVTLv8i16: |
3091 | 0 | case AArch64::FCVTMSUWDr: |
3092 | 0 | case AArch64::FCVTMSUWHr: |
3093 | 0 | case AArch64::FCVTMSUWSr: |
3094 | 0 | case AArch64::FCVTMSUXDr: |
3095 | 0 | case AArch64::FCVTMSUXHr: |
3096 | 0 | case AArch64::FCVTMSUXSr: |
3097 | 0 | case AArch64::FCVTMSv1f16: |
3098 | 0 | case AArch64::FCVTMSv1i32: |
3099 | 0 | case AArch64::FCVTMSv1i64: |
3100 | 0 | case AArch64::FCVTMSv2f32: |
3101 | 0 | case AArch64::FCVTMSv2f64: |
3102 | 0 | case AArch64::FCVTMSv4f16: |
3103 | 0 | case AArch64::FCVTMSv4f32: |
3104 | 0 | case AArch64::FCVTMSv8f16: |
3105 | 0 | case AArch64::FCVTMUUWDr: |
3106 | 0 | case AArch64::FCVTMUUWHr: |
3107 | 0 | case AArch64::FCVTMUUWSr: |
3108 | 0 | case AArch64::FCVTMUUXDr: |
3109 | 0 | case AArch64::FCVTMUUXHr: |
3110 | 0 | case AArch64::FCVTMUUXSr: |
3111 | 0 | case AArch64::FCVTMUv1f16: |
3112 | 0 | case AArch64::FCVTMUv1i32: |
3113 | 0 | case AArch64::FCVTMUv1i64: |
3114 | 0 | case AArch64::FCVTMUv2f32: |
3115 | 0 | case AArch64::FCVTMUv2f64: |
3116 | 0 | case AArch64::FCVTMUv4f16: |
3117 | 0 | case AArch64::FCVTMUv4f32: |
3118 | 0 | case AArch64::FCVTMUv8f16: |
3119 | 0 | case AArch64::FCVTNSUWDr: |
3120 | 0 | case AArch64::FCVTNSUWHr: |
3121 | 0 | case AArch64::FCVTNSUWSr: |
3122 | 0 | case AArch64::FCVTNSUXDr: |
3123 | 0 | case AArch64::FCVTNSUXHr: |
3124 | 0 | case AArch64::FCVTNSUXSr: |
3125 | 0 | case AArch64::FCVTNSv1f16: |
3126 | 0 | case AArch64::FCVTNSv1i32: |
3127 | 0 | case AArch64::FCVTNSv1i64: |
3128 | 0 | case AArch64::FCVTNSv2f32: |
3129 | 0 | case AArch64::FCVTNSv2f64: |
3130 | 0 | case AArch64::FCVTNSv4f16: |
3131 | 0 | case AArch64::FCVTNSv4f32: |
3132 | 0 | case AArch64::FCVTNSv8f16: |
3133 | 0 | case AArch64::FCVTNUUWDr: |
3134 | 0 | case AArch64::FCVTNUUWHr: |
3135 | 0 | case AArch64::FCVTNUUWSr: |
3136 | 0 | case AArch64::FCVTNUUXDr: |
3137 | 0 | case AArch64::FCVTNUUXHr: |
3138 | 0 | case AArch64::FCVTNUUXSr: |
3139 | 0 | case AArch64::FCVTNUv1f16: |
3140 | 0 | case AArch64::FCVTNUv1i32: |
3141 | 0 | case AArch64::FCVTNUv1i64: |
3142 | 0 | case AArch64::FCVTNUv2f32: |
3143 | 0 | case AArch64::FCVTNUv2f64: |
3144 | 0 | case AArch64::FCVTNUv4f16: |
3145 | 0 | case AArch64::FCVTNUv4f32: |
3146 | 0 | case AArch64::FCVTNUv8f16: |
3147 | 0 | case AArch64::FCVTNv2i32: |
3148 | 0 | case AArch64::FCVTNv4i16: |
3149 | 0 | case AArch64::FCVTPSUWDr: |
3150 | 0 | case AArch64::FCVTPSUWHr: |
3151 | 0 | case AArch64::FCVTPSUWSr: |
3152 | 0 | case AArch64::FCVTPSUXDr: |
3153 | 0 | case AArch64::FCVTPSUXHr: |
3154 | 0 | case AArch64::FCVTPSUXSr: |
3155 | 0 | case AArch64::FCVTPSv1f16: |
3156 | 0 | case AArch64::FCVTPSv1i32: |
3157 | 0 | case AArch64::FCVTPSv1i64: |
3158 | 0 | case AArch64::FCVTPSv2f32: |
3159 | 0 | case AArch64::FCVTPSv2f64: |
3160 | 0 | case AArch64::FCVTPSv4f16: |
3161 | 0 | case AArch64::FCVTPSv4f32: |
3162 | 0 | case AArch64::FCVTPSv8f16: |
3163 | 0 | case AArch64::FCVTPUUWDr: |
3164 | 0 | case AArch64::FCVTPUUWHr: |
3165 | 0 | case AArch64::FCVTPUUWSr: |
3166 | 0 | case AArch64::FCVTPUUXDr: |
3167 | 0 | case AArch64::FCVTPUUXHr: |
3168 | 0 | case AArch64::FCVTPUUXSr: |
3169 | 0 | case AArch64::FCVTPUv1f16: |
3170 | 0 | case AArch64::FCVTPUv1i32: |
3171 | 0 | case AArch64::FCVTPUv1i64: |
3172 | 0 | case AArch64::FCVTPUv2f32: |
3173 | 0 | case AArch64::FCVTPUv2f64: |
3174 | 0 | case AArch64::FCVTPUv4f16: |
3175 | 0 | case AArch64::FCVTPUv4f32: |
3176 | 0 | case AArch64::FCVTPUv8f16: |
3177 | 0 | case AArch64::FCVTSDr: |
3178 | 0 | case AArch64::FCVTSHr: |
3179 | 0 | case AArch64::FCVTXNv1i64: |
3180 | 0 | case AArch64::FCVTXNv2f32: |
3181 | 0 | case AArch64::FCVTZSUWDr: |
3182 | 0 | case AArch64::FCVTZSUWHr: |
3183 | 0 | case AArch64::FCVTZSUWSr: |
3184 | 0 | case AArch64::FCVTZSUXDr: |
3185 | 0 | case AArch64::FCVTZSUXHr: |
3186 | 0 | case AArch64::FCVTZSUXSr: |
3187 | 0 | case AArch64::FCVTZS_IntUWDr: |
3188 | 0 | case AArch64::FCVTZS_IntUWHr: |
3189 | 0 | case AArch64::FCVTZS_IntUWSr: |
3190 | 0 | case AArch64::FCVTZS_IntUXDr: |
3191 | 0 | case AArch64::FCVTZS_IntUXHr: |
3192 | 0 | case AArch64::FCVTZS_IntUXSr: |
3193 | 0 | case AArch64::FCVTZS_Intv2f32: |
3194 | 0 | case AArch64::FCVTZS_Intv2f64: |
3195 | 0 | case AArch64::FCVTZS_Intv4f16: |
3196 | 0 | case AArch64::FCVTZS_Intv4f32: |
3197 | 0 | case AArch64::FCVTZS_Intv8f16: |
3198 | 0 | case AArch64::FCVTZSv1f16: |
3199 | 0 | case AArch64::FCVTZSv1i32: |
3200 | 0 | case AArch64::FCVTZSv1i64: |
3201 | 0 | case AArch64::FCVTZSv2f32: |
3202 | 0 | case AArch64::FCVTZSv2f64: |
3203 | 0 | case AArch64::FCVTZSv4f16: |
3204 | 0 | case AArch64::FCVTZSv4f32: |
3205 | 0 | case AArch64::FCVTZSv8f16: |
3206 | 0 | case AArch64::FCVTZUUWDr: |
3207 | 0 | case AArch64::FCVTZUUWHr: |
3208 | 0 | case AArch64::FCVTZUUWSr: |
3209 | 0 | case AArch64::FCVTZUUXDr: |
3210 | 0 | case AArch64::FCVTZUUXHr: |
3211 | 0 | case AArch64::FCVTZUUXSr: |
3212 | 0 | case AArch64::FCVTZU_IntUWDr: |
3213 | 0 | case AArch64::FCVTZU_IntUWHr: |
3214 | 0 | case AArch64::FCVTZU_IntUWSr: |
3215 | 0 | case AArch64::FCVTZU_IntUXDr: |
3216 | 0 | case AArch64::FCVTZU_IntUXHr: |
3217 | 0 | case AArch64::FCVTZU_IntUXSr: |
3218 | 0 | case AArch64::FCVTZU_Intv2f32: |
3219 | 0 | case AArch64::FCVTZU_Intv2f64: |
3220 | 0 | case AArch64::FCVTZU_Intv4f16: |
3221 | 0 | case AArch64::FCVTZU_Intv4f32: |
3222 | 0 | case AArch64::FCVTZU_Intv8f16: |
3223 | 0 | case AArch64::FCVTZUv1f16: |
3224 | 0 | case AArch64::FCVTZUv1i32: |
3225 | 0 | case AArch64::FCVTZUv1i64: |
3226 | 0 | case AArch64::FCVTZUv2f32: |
3227 | 0 | case AArch64::FCVTZUv2f64: |
3228 | 0 | case AArch64::FCVTZUv4f16: |
3229 | 0 | case AArch64::FCVTZUv4f32: |
3230 | 0 | case AArch64::FCVTZUv8f16: |
3231 | 0 | case AArch64::FMAXNMPv2i16p: |
3232 | 0 | case AArch64::FMAXNMPv2i32p: |
3233 | 0 | case AArch64::FMAXNMPv2i64p: |
3234 | 0 | case AArch64::FMAXNMVv4i16v: |
3235 | 0 | case AArch64::FMAXNMVv4i32v: |
3236 | 0 | case AArch64::FMAXNMVv8i16v: |
3237 | 0 | case AArch64::FMAXPv2i16p: |
3238 | 0 | case AArch64::FMAXPv2i32p: |
3239 | 0 | case AArch64::FMAXPv2i64p: |
3240 | 0 | case AArch64::FMAXVv4i16v: |
3241 | 0 | case AArch64::FMAXVv4i32v: |
3242 | 0 | case AArch64::FMAXVv8i16v: |
3243 | 0 | case AArch64::FMINNMPv2i16p: |
3244 | 0 | case AArch64::FMINNMPv2i32p: |
3245 | 0 | case AArch64::FMINNMPv2i64p: |
3246 | 0 | case AArch64::FMINNMVv4i16v: |
3247 | 0 | case AArch64::FMINNMVv4i32v: |
3248 | 0 | case AArch64::FMINNMVv8i16v: |
3249 | 0 | case AArch64::FMINPv2i16p: |
3250 | 0 | case AArch64::FMINPv2i32p: |
3251 | 0 | case AArch64::FMINPv2i64p: |
3252 | 0 | case AArch64::FMINVv4i16v: |
3253 | 0 | case AArch64::FMINVv4i32v: |
3254 | 0 | case AArch64::FMINVv8i16v: |
3255 | 0 | case AArch64::FMOVDXHighr: |
3256 | 0 | case AArch64::FMOVDXr: |
3257 | 0 | case AArch64::FMOVDr: |
3258 | 0 | case AArch64::FMOVHWr: |
3259 | 0 | case AArch64::FMOVHXr: |
3260 | 0 | case AArch64::FMOVHr: |
3261 | 0 | case AArch64::FMOVSWr: |
3262 | 0 | case AArch64::FMOVSr: |
3263 | 0 | case AArch64::FMOVWHr: |
3264 | 0 | case AArch64::FMOVWSr: |
3265 | 0 | case AArch64::FMOVXDHighr: |
3266 | 0 | case AArch64::FMOVXDr: |
3267 | 0 | case AArch64::FMOVXHr: |
3268 | 0 | case AArch64::FNEGDr: |
3269 | 0 | case AArch64::FNEGHr: |
3270 | 0 | case AArch64::FNEGSr: |
3271 | 0 | case AArch64::FNEGv2f32: |
3272 | 0 | case AArch64::FNEGv2f64: |
3273 | 0 | case AArch64::FNEGv4f16: |
3274 | 0 | case AArch64::FNEGv4f32: |
3275 | 0 | case AArch64::FNEGv8f16: |
3276 | 0 | case AArch64::FRECPEv1f16: |
3277 | 0 | case AArch64::FRECPEv1i32: |
3278 | 0 | case AArch64::FRECPEv1i64: |
3279 | 0 | case AArch64::FRECPEv2f32: |
3280 | 0 | case AArch64::FRECPEv2f64: |
3281 | 0 | case AArch64::FRECPEv4f16: |
3282 | 0 | case AArch64::FRECPEv4f32: |
3283 | 0 | case AArch64::FRECPEv8f16: |
3284 | 0 | case AArch64::FRECPXv1f16: |
3285 | 0 | case AArch64::FRECPXv1i32: |
3286 | 0 | case AArch64::FRECPXv1i64: |
3287 | 0 | case AArch64::FRINTADr: |
3288 | 0 | case AArch64::FRINTAHr: |
3289 | 0 | case AArch64::FRINTASr: |
3290 | 0 | case AArch64::FRINTAv2f32: |
3291 | 0 | case AArch64::FRINTAv2f64: |
3292 | 0 | case AArch64::FRINTAv4f16: |
3293 | 0 | case AArch64::FRINTAv4f32: |
3294 | 0 | case AArch64::FRINTAv8f16: |
3295 | 0 | case AArch64::FRINTIDr: |
3296 | 0 | case AArch64::FRINTIHr: |
3297 | 0 | case AArch64::FRINTISr: |
3298 | 0 | case AArch64::FRINTIv2f32: |
3299 | 0 | case AArch64::FRINTIv2f64: |
3300 | 0 | case AArch64::FRINTIv4f16: |
3301 | 0 | case AArch64::FRINTIv4f32: |
3302 | 0 | case AArch64::FRINTIv8f16: |
3303 | 0 | case AArch64::FRINTMDr: |
3304 | 0 | case AArch64::FRINTMHr: |
3305 | 0 | case AArch64::FRINTMSr: |
3306 | 0 | case AArch64::FRINTMv2f32: |
3307 | 0 | case AArch64::FRINTMv2f64: |
3308 | 0 | case AArch64::FRINTMv4f16: |
3309 | 0 | case AArch64::FRINTMv4f32: |
3310 | 0 | case AArch64::FRINTMv8f16: |
3311 | 0 | case AArch64::FRINTNDr: |
3312 | 0 | case AArch64::FRINTNHr: |
3313 | 0 | case AArch64::FRINTNSr: |
3314 | 0 | case AArch64::FRINTNv2f32: |
3315 | 0 | case AArch64::FRINTNv2f64: |
3316 | 0 | case AArch64::FRINTNv4f16: |
3317 | 0 | case AArch64::FRINTNv4f32: |
3318 | 0 | case AArch64::FRINTNv8f16: |
3319 | 0 | case AArch64::FRINTPDr: |
3320 | 0 | case AArch64::FRINTPHr: |
3321 | 0 | case AArch64::FRINTPSr: |
3322 | 0 | case AArch64::FRINTPv2f32: |
3323 | 0 | case AArch64::FRINTPv2f64: |
3324 | 0 | case AArch64::FRINTPv4f16: |
3325 | 0 | case AArch64::FRINTPv4f32: |
3326 | 0 | case AArch64::FRINTPv8f16: |
3327 | 0 | case AArch64::FRINTXDr: |
3328 | 0 | case AArch64::FRINTXHr: |
3329 | 0 | case AArch64::FRINTXSr: |
3330 | 0 | case AArch64::FRINTXv2f32: |
3331 | 0 | case AArch64::FRINTXv2f64: |
3332 | 0 | case AArch64::FRINTXv4f16: |
3333 | 0 | case AArch64::FRINTXv4f32: |
3334 | 0 | case AArch64::FRINTXv8f16: |
3335 | 0 | case AArch64::FRINTZDr: |
3336 | 0 | case AArch64::FRINTZHr: |
3337 | 0 | case AArch64::FRINTZSr: |
3338 | 0 | case AArch64::FRINTZv2f32: |
3339 | 0 | case AArch64::FRINTZv2f64: |
3340 | 0 | case AArch64::FRINTZv4f16: |
3341 | 0 | case AArch64::FRINTZv4f32: |
3342 | 0 | case AArch64::FRINTZv8f16: |
3343 | 0 | case AArch64::FRSQRTEv1f16: |
3344 | 0 | case AArch64::FRSQRTEv1i32: |
3345 | 0 | case AArch64::FRSQRTEv1i64: |
3346 | 0 | case AArch64::FRSQRTEv2f32: |
3347 | 0 | case AArch64::FRSQRTEv2f64: |
3348 | 0 | case AArch64::FRSQRTEv4f16: |
3349 | 0 | case AArch64::FRSQRTEv4f32: |
3350 | 0 | case AArch64::FRSQRTEv8f16: |
3351 | 0 | case AArch64::FSQRTDr: |
3352 | 0 | case AArch64::FSQRTHr: |
3353 | 0 | case AArch64::FSQRTSr: |
3354 | 0 | case AArch64::FSQRTv2f32: |
3355 | 0 | case AArch64::FSQRTv2f64: |
3356 | 0 | case AArch64::FSQRTv4f16: |
3357 | 0 | case AArch64::FSQRTv4f32: |
3358 | 0 | case AArch64::FSQRTv8f16: |
3359 | 0 | case AArch64::NEGv16i8: |
3360 | 0 | case AArch64::NEGv1i64: |
3361 | 0 | case AArch64::NEGv2i32: |
3362 | 0 | case AArch64::NEGv2i64: |
3363 | 0 | case AArch64::NEGv4i16: |
3364 | 0 | case AArch64::NEGv4i32: |
3365 | 0 | case AArch64::NEGv8i16: |
3366 | 0 | case AArch64::NEGv8i8: |
3367 | 0 | case AArch64::NOTv16i8: |
3368 | 0 | case AArch64::NOTv8i8: |
3369 | 0 | case AArch64::RBITWr: |
3370 | 0 | case AArch64::RBITXr: |
3371 | 0 | case AArch64::RBITv16i8: |
3372 | 0 | case AArch64::RBITv8i8: |
3373 | 0 | case AArch64::REV16Wr: |
3374 | 0 | case AArch64::REV16Xr: |
3375 | 0 | case AArch64::REV16v16i8: |
3376 | 0 | case AArch64::REV16v8i8: |
3377 | 0 | case AArch64::REV32Xr: |
3378 | 0 | case AArch64::REV32v16i8: |
3379 | 0 | case AArch64::REV32v4i16: |
3380 | 0 | case AArch64::REV32v8i16: |
3381 | 0 | case AArch64::REV32v8i8: |
3382 | 0 | case AArch64::REV64v16i8: |
3383 | 0 | case AArch64::REV64v2i32: |
3384 | 0 | case AArch64::REV64v4i16: |
3385 | 0 | case AArch64::REV64v4i32: |
3386 | 0 | case AArch64::REV64v8i16: |
3387 | 0 | case AArch64::REV64v8i8: |
3388 | 0 | case AArch64::REVWr: |
3389 | 0 | case AArch64::REVXr: |
3390 | 0 | case AArch64::SADDLPv16i8_v8i16: |
3391 | 0 | case AArch64::SADDLPv2i32_v1i64: |
3392 | 0 | case AArch64::SADDLPv4i16_v2i32: |
3393 | 0 | case AArch64::SADDLPv4i32_v2i64: |
3394 | 0 | case AArch64::SADDLPv8i16_v4i32: |
3395 | 0 | case AArch64::SADDLPv8i8_v4i16: |
3396 | 0 | case AArch64::SADDLVv16i8v: |
3397 | 0 | case AArch64::SADDLVv4i16v: |
3398 | 0 | case AArch64::SADDLVv4i32v: |
3399 | 0 | case AArch64::SADDLVv8i16v: |
3400 | 0 | case AArch64::SADDLVv8i8v: |
3401 | 0 | case AArch64::SCVTFUWDri: |
3402 | 0 | case AArch64::SCVTFUWHri: |
3403 | 0 | case AArch64::SCVTFUWSri: |
3404 | 0 | case AArch64::SCVTFUXDri: |
3405 | 0 | case AArch64::SCVTFUXHri: |
3406 | 0 | case AArch64::SCVTFUXSri: |
3407 | 0 | case AArch64::SCVTFv1i16: |
3408 | 0 | case AArch64::SCVTFv1i32: |
3409 | 0 | case AArch64::SCVTFv1i64: |
3410 | 0 | case AArch64::SCVTFv2f32: |
3411 | 0 | case AArch64::SCVTFv2f64: |
3412 | 0 | case AArch64::SCVTFv4f16: |
3413 | 0 | case AArch64::SCVTFv4f32: |
3414 | 0 | case AArch64::SCVTFv8f16: |
3415 | 0 | case AArch64::SHA1Hrr: |
3416 | 0 | case AArch64::SHLLv16i8: |
3417 | 0 | case AArch64::SHLLv2i32: |
3418 | 0 | case AArch64::SHLLv4i16: |
3419 | 0 | case AArch64::SHLLv4i32: |
3420 | 0 | case AArch64::SHLLv8i16: |
3421 | 0 | case AArch64::SHLLv8i8: |
3422 | 0 | case AArch64::SMAXVv16i8v: |
3423 | 0 | case AArch64::SMAXVv4i16v: |
3424 | 0 | case AArch64::SMAXVv4i32v: |
3425 | 0 | case AArch64::SMAXVv8i16v: |
3426 | 0 | case AArch64::SMAXVv8i8v: |
3427 | 0 | case AArch64::SMINVv16i8v: |
3428 | 0 | case AArch64::SMINVv4i16v: |
3429 | 0 | case AArch64::SMINVv4i32v: |
3430 | 0 | case AArch64::SMINVv8i16v: |
3431 | 0 | case AArch64::SMINVv8i8v: |
3432 | 0 | case AArch64::SQABSv16i8: |
3433 | 0 | case AArch64::SQABSv1i16: |
3434 | 0 | case AArch64::SQABSv1i32: |
3435 | 0 | case AArch64::SQABSv1i64: |
3436 | 0 | case AArch64::SQABSv1i8: |
3437 | 0 | case AArch64::SQABSv2i32: |
3438 | 0 | case AArch64::SQABSv2i64: |
3439 | 0 | case AArch64::SQABSv4i16: |
3440 | 0 | case AArch64::SQABSv4i32: |
3441 | 0 | case AArch64::SQABSv8i16: |
3442 | 0 | case AArch64::SQABSv8i8: |
3443 | 0 | case AArch64::SQNEGv16i8: |
3444 | 0 | case AArch64::SQNEGv1i16: |
3445 | 0 | case AArch64::SQNEGv1i32: |
3446 | 0 | case AArch64::SQNEGv1i64: |
3447 | 0 | case AArch64::SQNEGv1i8: |
3448 | 0 | case AArch64::SQNEGv2i32: |
3449 | 0 | case AArch64::SQNEGv2i64: |
3450 | 0 | case AArch64::SQNEGv4i16: |
3451 | 0 | case AArch64::SQNEGv4i32: |
3452 | 0 | case AArch64::SQNEGv8i16: |
3453 | 0 | case AArch64::SQNEGv8i8: |
3454 | 0 | case AArch64::SQXTNv1i16: |
3455 | 0 | case AArch64::SQXTNv1i32: |
3456 | 0 | case AArch64::SQXTNv1i8: |
3457 | 0 | case AArch64::SQXTNv2i32: |
3458 | 0 | case AArch64::SQXTNv4i16: |
3459 | 0 | case AArch64::SQXTNv8i8: |
3460 | 0 | case AArch64::SQXTUNv1i16: |
3461 | 0 | case AArch64::SQXTUNv1i32: |
3462 | 0 | case AArch64::SQXTUNv1i8: |
3463 | 0 | case AArch64::SQXTUNv2i32: |
3464 | 0 | case AArch64::SQXTUNv4i16: |
3465 | 0 | case AArch64::SQXTUNv8i8: |
3466 | 0 | case AArch64::UADDLPv16i8_v8i16: |
3467 | 0 | case AArch64::UADDLPv2i32_v1i64: |
3468 | 0 | case AArch64::UADDLPv4i16_v2i32: |
3469 | 0 | case AArch64::UADDLPv4i32_v2i64: |
3470 | 0 | case AArch64::UADDLPv8i16_v4i32: |
3471 | 0 | case AArch64::UADDLPv8i8_v4i16: |
3472 | 0 | case AArch64::UADDLVv16i8v: |
3473 | 0 | case AArch64::UADDLVv4i16v: |
3474 | 0 | case AArch64::UADDLVv4i32v: |
3475 | 0 | case AArch64::UADDLVv8i16v: |
3476 | 0 | case AArch64::UADDLVv8i8v: |
3477 | 0 | case AArch64::UCVTFUWDri: |
3478 | 0 | case AArch64::UCVTFUWHri: |
3479 | 0 | case AArch64::UCVTFUWSri: |
3480 | 0 | case AArch64::UCVTFUXDri: |
3481 | 0 | case AArch64::UCVTFUXHri: |
3482 | 0 | case AArch64::UCVTFUXSri: |
3483 | 0 | case AArch64::UCVTFv1i16: |
3484 | 0 | case AArch64::UCVTFv1i32: |
3485 | 0 | case AArch64::UCVTFv1i64: |
3486 | 0 | case AArch64::UCVTFv2f32: |
3487 | 0 | case AArch64::UCVTFv2f64: |
3488 | 0 | case AArch64::UCVTFv4f16: |
3489 | 0 | case AArch64::UCVTFv4f32: |
3490 | 0 | case AArch64::UCVTFv8f16: |
3491 | 0 | case AArch64::UMAXVv16i8v: |
3492 | 0 | case AArch64::UMAXVv4i16v: |
3493 | 0 | case AArch64::UMAXVv4i32v: |
3494 | 0 | case AArch64::UMAXVv8i16v: |
3495 | 0 | case AArch64::UMAXVv8i8v: |
3496 | 0 | case AArch64::UMINVv16i8v: |
3497 | 0 | case AArch64::UMINVv4i16v: |
3498 | 0 | case AArch64::UMINVv4i32v: |
3499 | 0 | case AArch64::UMINVv8i16v: |
3500 | 0 | case AArch64::UMINVv8i8v: |
3501 | 0 | case AArch64::UQXTNv1i16: |
3502 | 0 | case AArch64::UQXTNv1i32: |
3503 | 0 | case AArch64::UQXTNv1i8: |
3504 | 0 | case AArch64::UQXTNv2i32: |
3505 | 0 | case AArch64::UQXTNv4i16: |
3506 | 0 | case AArch64::UQXTNv8i8: |
3507 | 0 | case AArch64::URECPEv2i32: |
3508 | 0 | case AArch64::URECPEv4i32: |
3509 | 0 | case AArch64::URSQRTEv2i32: |
3510 | 0 | case AArch64::URSQRTEv4i32: |
3511 | 0 | case AArch64::XTNv2i32: |
3512 | 0 | case AArch64::XTNv4i16: |
3513 | 0 | case AArch64::XTNv8i8: { |
3514 | | // op: Rd |
3515 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3516 | 0 | Value |= op & UINT64_C(31); |
3517 | | // op: Rn |
3518 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3519 | 0 | Value |= (op & UINT64_C(31)) << 5; |
3520 | 0 | break; |
3521 | 0 | } |
3522 | 0 | case AArch64::FMULXv1i16_indexed: |
3523 | 0 | case AArch64::FMULXv4i16_indexed: |
3524 | 0 | case AArch64::FMULXv8i16_indexed: |
3525 | 0 | case AArch64::FMULv1i16_indexed: |
3526 | 0 | case AArch64::FMULv4i16_indexed: |
3527 | 0 | case AArch64::FMULv8i16_indexed: |
3528 | 0 | case AArch64::MULv4i16_indexed: |
3529 | 0 | case AArch64::MULv8i16_indexed: |
3530 | 0 | case AArch64::SMULLv4i16_indexed: |
3531 | 0 | case AArch64::SMULLv8i16_indexed: |
3532 | 0 | case AArch64::SQDMULHv1i16_indexed: |
3533 | 0 | case AArch64::SQDMULHv4i16_indexed: |
3534 | 0 | case AArch64::SQDMULHv8i16_indexed: |
3535 | 0 | case AArch64::SQDMULLv1i32_indexed: |
3536 | 0 | case AArch64::SQDMULLv4i16_indexed: |
3537 | 0 | case AArch64::SQDMULLv8i16_indexed: |
3538 | 0 | case AArch64::SQRDMULHv1i16_indexed: |
3539 | 0 | case AArch64::SQRDMULHv4i16_indexed: |
3540 | 0 | case AArch64::SQRDMULHv8i16_indexed: |
3541 | 0 | case AArch64::UMULLv4i16_indexed: |
3542 | 0 | case AArch64::UMULLv8i16_indexed: { |
3543 | | // op: Rd |
3544 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
3545 | 0 | Value |= op & UINT64_C(31); |
3546 | | // op: Rn |
3547 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
3548 | 0 | Value |= (op & UINT64_C(31)) << 5; |
3549 | | // op: Rm |
3550 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
3551 | 0 | Value |= (op & UINT64_C(15)) << 16; |
3552 | | // op: idx |
3553 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
3554 | 0 | Value |= (op & UINT64_C(3)) << 20; |
3555 | 0 | Value |= (op & UINT64_C(4)) << 9; |
3556 | 0 | break; |
3557 | 0 | } |
3558 | 0 | case AArch64::ADCSWr: |
3559 | 0 | case AArch64::ADCSXr: |
3560 | 0 | case AArch64::ADCWr: |
3561 | 0 | case AArch64::ADCXr: |
3562 | 0 | case AArch64::ADDHNv2i64_v2i32: |
3563 | 0 | case AArch64::ADDHNv4i32_v4i16: |
3564 | 0 | case AArch64::ADDHNv8i16_v8i8: |
3565 | 0 | case AArch64::ADDPv16i8: |
3566 | 0 | case AArch64::ADDPv2i32: |
3567 | 0 | case AArch64::ADDPv2i64: |
3568 | 0 | case AArch64::ADDPv4i16: |
3569 | 0 | case AArch64::ADDPv4i32: |
3570 | 0 | case AArch64::ADDPv8i16: |
3571 | 0 | case AArch64::ADDPv8i8: |
3572 | 0 | case AArch64::ADDv16i8: |
3573 | 0 | case AArch64::ADDv1i64: |
3574 | 0 | case AArch64::ADDv2i32: |
3575 | 0 | case AArch64::ADDv2i64: |
3576 | 0 | case AArch64::ADDv4i16: |
3577 | 0 | case AArch64::ADDv4i32: |
3578 | 0 | case AArch64::ADDv8i16: |
3579 | 0 | case AArch64::ADDv8i8: |
3580 | 0 | case AArch64::ANDv16i8: |
3581 | 0 | case AArch64::ANDv8i8: |
3582 | 0 | case AArch64::ASRVWr: |
3583 | 0 | case AArch64::ASRVXr: |
3584 | 0 | case AArch64::BICv16i8: |
3585 | 0 | case AArch64::BICv8i8: |
3586 | 0 | case AArch64::BIFv16i8: |
3587 | 0 | case AArch64::BIFv8i8: |
3588 | 0 | case AArch64::CMEQv16i8: |
3589 | 0 | case AArch64::CMEQv1i64: |
3590 | 0 | case AArch64::CMEQv2i32: |
3591 | 0 | case AArch64::CMEQv2i64: |
3592 | 0 | case AArch64::CMEQv4i16: |
3593 | 0 | case AArch64::CMEQv4i32: |
3594 | 0 | case AArch64::CMEQv8i16: |
3595 | 0 | case AArch64::CMEQv8i8: |
3596 | 0 | case AArch64::CMGEv16i8: |
3597 | 0 | case AArch64::CMGEv1i64: |
3598 | 0 | case AArch64::CMGEv2i32: |
3599 | 0 | case AArch64::CMGEv2i64: |
3600 | 0 | case AArch64::CMGEv4i16: |
3601 | 0 | case AArch64::CMGEv4i32: |
3602 | 0 | case AArch64::CMGEv8i16: |
3603 | 0 | case AArch64::CMGEv8i8: |
3604 | 0 | case AArch64::CMGTv16i8: |
3605 | 0 | case AArch64::CMGTv1i64: |
3606 | 0 | case AArch64::CMGTv2i32: |
3607 | 0 | case AArch64::CMGTv2i64: |
3608 | 0 | case AArch64::CMGTv4i16: |
3609 | 0 | case AArch64::CMGTv4i32: |
3610 | 0 | case AArch64::CMGTv8i16: |
3611 | 0 | case AArch64::CMGTv8i8: |
3612 | 0 | case AArch64::CMHIv16i8: |
3613 | 0 | case AArch64::CMHIv1i64: |
3614 | 0 | case AArch64::CMHIv2i32: |
3615 | 0 | case AArch64::CMHIv2i64: |
3616 | 0 | case AArch64::CMHIv4i16: |
3617 | 0 | case AArch64::CMHIv4i32: |
3618 | 0 | case AArch64::CMHIv8i16: |
3619 | 0 | case AArch64::CMHIv8i8: |
3620 | 0 | case AArch64::CMHSv16i8: |
3621 | 0 | case AArch64::CMHSv1i64: |
3622 | 0 | case AArch64::CMHSv2i32: |
3623 | 0 | case AArch64::CMHSv2i64: |
3624 | 0 | case AArch64::CMHSv4i16: |
3625 | 0 | case AArch64::CMHSv4i32: |
3626 | 0 | case AArch64::CMHSv8i16: |
3627 | 0 | case AArch64::CMHSv8i8: |
3628 | 0 | case AArch64::CMTSTv16i8: |
3629 | 0 | case AArch64::CMTSTv1i64: |
3630 | 0 | case AArch64::CMTSTv2i32: |
3631 | 0 | case AArch64::CMTSTv2i64: |
3632 | 0 | case AArch64::CMTSTv4i16: |
3633 | 0 | case AArch64::CMTSTv4i32: |
3634 | 0 | case AArch64::CMTSTv8i16: |
3635 | 0 | case AArch64::CMTSTv8i8: |
3636 | 0 | case AArch64::CRC32Brr: |
3637 | 0 | case AArch64::CRC32CBrr: |
3638 | 0 | case AArch64::CRC32CHrr: |
3639 | 0 | case AArch64::CRC32CWrr: |
3640 | 0 | case AArch64::CRC32CXrr: |
3641 | 0 | case AArch64::CRC32Hrr: |
3642 | 0 | case AArch64::CRC32Wrr: |
3643 | 0 | case AArch64::CRC32Xrr: |
3644 | 0 | case AArch64::EORv16i8: |
3645 | 0 | case AArch64::EORv8i8: |
3646 | 0 | case AArch64::FABD16: |
3647 | 0 | case AArch64::FABD32: |
3648 | 0 | case AArch64::FABD64: |
3649 | 0 | case AArch64::FABDv2f32: |
3650 | 0 | case AArch64::FABDv2f64: |
3651 | 0 | case AArch64::FABDv4f16: |
3652 | 0 | case AArch64::FABDv4f32: |
3653 | 0 | case AArch64::FABDv8f16: |
3654 | 0 | case AArch64::FACGE16: |
3655 | 0 | case AArch64::FACGE32: |
3656 | 0 | case AArch64::FACGE64: |
3657 | 0 | case AArch64::FACGEv2f32: |
3658 | 0 | case AArch64::FACGEv2f64: |
3659 | 0 | case AArch64::FACGEv4f16: |
3660 | 0 | case AArch64::FACGEv4f32: |
3661 | 0 | case AArch64::FACGEv8f16: |
3662 | 0 | case AArch64::FACGT16: |
3663 | 0 | case AArch64::FACGT32: |
3664 | 0 | case AArch64::FACGT64: |
3665 | 0 | case AArch64::FACGTv2f32: |
3666 | 0 | case AArch64::FACGTv2f64: |
3667 | 0 | case AArch64::FACGTv4f16: |
3668 | 0 | case AArch64::FACGTv4f32: |
3669 | 0 | case AArch64::FACGTv8f16: |
3670 | 0 | case AArch64::FADDDrr: |
3671 | 0 | case AArch64::FADDHrr: |
3672 | 0 | case AArch64::FADDPv2f32: |
3673 | 0 | case AArch64::FADDPv2f64: |
3674 | 0 | case AArch64::FADDPv4f16: |
3675 | 0 | case AArch64::FADDPv4f32: |
3676 | 0 | case AArch64::FADDPv8f16: |
3677 | 0 | case AArch64::FADDSrr: |
3678 | 0 | case AArch64::FADDv2f32: |
3679 | 0 | case AArch64::FADDv2f64: |
3680 | 0 | case AArch64::FADDv4f16: |
3681 | 0 | case AArch64::FADDv4f32: |
3682 | 0 | case AArch64::FADDv8f16: |
3683 | 0 | case AArch64::FCMEQ16: |
3684 | 0 | case AArch64::FCMEQ32: |
3685 | 0 | case AArch64::FCMEQ64: |
3686 | 0 | case AArch64::FCMEQv2f32: |
3687 | 0 | case AArch64::FCMEQv2f64: |
3688 | 0 | case AArch64::FCMEQv4f16: |
3689 | 0 | case AArch64::FCMEQv4f32: |
3690 | 0 | case AArch64::FCMEQv8f16: |
3691 | 0 | case AArch64::FCMGE16: |
3692 | 0 | case AArch64::FCMGE32: |
3693 | 0 | case AArch64::FCMGE64: |
3694 | 0 | case AArch64::FCMGEv2f32: |
3695 | 0 | case AArch64::FCMGEv2f64: |
3696 | 0 | case AArch64::FCMGEv4f16: |
3697 | 0 | case AArch64::FCMGEv4f32: |
3698 | 0 | case AArch64::FCMGEv8f16: |
3699 | 0 | case AArch64::FCMGT16: |
3700 | 0 | case AArch64::FCMGT32: |
3701 | 0 | case AArch64::FCMGT64: |
3702 | 0 | case AArch64::FCMGTv2f32: |
3703 | 0 | case AArch64::FCMGTv2f64: |
3704 | 0 | case AArch64::FCMGTv4f16: |
3705 | 0 | case AArch64::FCMGTv4f32: |
3706 | 0 | case AArch64::FCMGTv8f16: |
3707 | 0 | case AArch64::FDIVDrr: |
3708 | 0 | case AArch64::FDIVHrr: |
3709 | 0 | case AArch64::FDIVSrr: |
3710 | 0 | case AArch64::FDIVv2f32: |
3711 | 0 | case AArch64::FDIVv2f64: |
3712 | 0 | case AArch64::FDIVv4f16: |
3713 | 0 | case AArch64::FDIVv4f32: |
3714 | 0 | case AArch64::FDIVv8f16: |
3715 | 0 | case AArch64::FMAXDrr: |
3716 | 0 | case AArch64::FMAXHrr: |
3717 | 0 | case AArch64::FMAXNMDrr: |
3718 | 0 | case AArch64::FMAXNMHrr: |
3719 | 0 | case AArch64::FMAXNMPv2f32: |
3720 | 0 | case AArch64::FMAXNMPv2f64: |
3721 | 0 | case AArch64::FMAXNMPv4f16: |
3722 | 0 | case AArch64::FMAXNMPv4f32: |
3723 | 0 | case AArch64::FMAXNMPv8f16: |
3724 | 0 | case AArch64::FMAXNMSrr: |
3725 | 0 | case AArch64::FMAXNMv2f32: |
3726 | 0 | case AArch64::FMAXNMv2f64: |
3727 | 0 | case AArch64::FMAXNMv4f16: |
3728 | 0 | case AArch64::FMAXNMv4f32: |
3729 | 0 | case AArch64::FMAXNMv8f16: |
3730 | 0 | case AArch64::FMAXPv2f32: |
3731 | 0 | case AArch64::FMAXPv2f64: |
3732 | 0 | case AArch64::FMAXPv4f16: |
3733 | 0 | case AArch64::FMAXPv4f32: |
3734 | 0 | case AArch64::FMAXPv8f16: |
3735 | 0 | case AArch64::FMAXSrr: |
3736 | 0 | case AArch64::FMAXv2f32: |
3737 | 0 | case AArch64::FMAXv2f64: |
3738 | 0 | case AArch64::FMAXv4f16: |
3739 | 0 | case AArch64::FMAXv4f32: |
3740 | 0 | case AArch64::FMAXv8f16: |
3741 | 0 | case AArch64::FMINDrr: |
3742 | 0 | case AArch64::FMINHrr: |
3743 | 0 | case AArch64::FMINNMDrr: |
3744 | 0 | case AArch64::FMINNMHrr: |
3745 | 0 | case AArch64::FMINNMPv2f32: |
3746 | 0 | case AArch64::FMINNMPv2f64: |
3747 | 0 | case AArch64::FMINNMPv4f16: |
3748 | 0 | case AArch64::FMINNMPv4f32: |
3749 | 0 | case AArch64::FMINNMPv8f16: |
3750 | 0 | case AArch64::FMINNMSrr: |
3751 | 0 | case AArch64::FMINNMv2f32: |
3752 | 0 | case AArch64::FMINNMv2f64: |
3753 | 0 | case AArch64::FMINNMv4f16: |
3754 | 0 | case AArch64::FMINNMv4f32: |
3755 | 0 | case AArch64::FMINNMv8f16: |
3756 | 0 | case AArch64::FMINPv2f32: |
3757 | 0 | case AArch64::FMINPv2f64: |
3758 | 0 | case AArch64::FMINPv4f16: |
3759 | 0 | case AArch64::FMINPv4f32: |
3760 | 0 | case AArch64::FMINPv8f16: |
3761 | 0 | case AArch64::FMINSrr: |
3762 | 0 | case AArch64::FMINv2f32: |
3763 | 0 | case AArch64::FMINv2f64: |
3764 | 0 | case AArch64::FMINv4f16: |
3765 | 0 | case AArch64::FMINv4f32: |
3766 | 0 | case AArch64::FMINv8f16: |
3767 | 0 | case AArch64::FMULDrr: |
3768 | 0 | case AArch64::FMULHrr: |
3769 | 0 | case AArch64::FMULSrr: |
3770 | 0 | case AArch64::FMULX16: |
3771 | 0 | case AArch64::FMULX32: |
3772 | 0 | case AArch64::FMULX64: |
3773 | 0 | case AArch64::FMULXv2f32: |
3774 | 0 | case AArch64::FMULXv2f64: |
3775 | 0 | case AArch64::FMULXv4f16: |
3776 | 0 | case AArch64::FMULXv4f32: |
3777 | 0 | case AArch64::FMULXv8f16: |
3778 | 0 | case AArch64::FMULv2f32: |
3779 | 0 | case AArch64::FMULv2f64: |
3780 | 0 | case AArch64::FMULv4f16: |
3781 | 0 | case AArch64::FMULv4f32: |
3782 | 0 | case AArch64::FMULv8f16: |
3783 | 0 | case AArch64::FNMULDrr: |
3784 | 0 | case AArch64::FNMULHrr: |
3785 | 0 | case AArch64::FNMULSrr: |
3786 | 0 | case AArch64::FRECPS16: |
3787 | 0 | case AArch64::FRECPS32: |
3788 | 0 | case AArch64::FRECPS64: |
3789 | 0 | case AArch64::FRECPSv2f32: |
3790 | 0 | case AArch64::FRECPSv2f64: |
3791 | 0 | case AArch64::FRECPSv4f16: |
3792 | 0 | case AArch64::FRECPSv4f32: |
3793 | 0 | case AArch64::FRECPSv8f16: |
3794 | 0 | case AArch64::FRSQRTS16: |
3795 | 0 | case AArch64::FRSQRTS32: |
3796 | 0 | case AArch64::FRSQRTS64: |
3797 | 0 | case AArch64::FRSQRTSv2f32: |
3798 | 0 | case AArch64::FRSQRTSv2f64: |
3799 | 0 | case AArch64::FRSQRTSv4f16: |
3800 | 0 | case AArch64::FRSQRTSv4f32: |
3801 | 0 | case AArch64::FRSQRTSv8f16: |
3802 | 0 | case AArch64::FSUBDrr: |
3803 | 0 | case AArch64::FSUBHrr: |
3804 | 0 | case AArch64::FSUBSrr: |
3805 | 0 | case AArch64::FSUBv2f32: |
3806 | 0 | case AArch64::FSUBv2f64: |
3807 | 0 | case AArch64::FSUBv4f16: |
3808 | 0 | case AArch64::FSUBv4f32: |
3809 | 0 | case AArch64::FSUBv8f16: |
3810 | 0 | case AArch64::LSLVWr: |
3811 | 0 | case AArch64::LSLVXr: |
3812 | 0 | case AArch64::LSRVWr: |
3813 | 0 | case AArch64::LSRVXr: |
3814 | 0 | case AArch64::MULv16i8: |
3815 | 0 | case AArch64::MULv2i32: |
3816 | 0 | case AArch64::MULv4i16: |
3817 | 0 | case AArch64::MULv4i32: |
3818 | 0 | case AArch64::MULv8i16: |
3819 | 0 | case AArch64::MULv8i8: |
3820 | 0 | case AArch64::ORNv16i8: |
3821 | 0 | case AArch64::ORNv8i8: |
3822 | 0 | case AArch64::ORRv16i8: |
3823 | 0 | case AArch64::ORRv8i8: |
3824 | 0 | case AArch64::PMULLv16i8: |
3825 | 0 | case AArch64::PMULLv1i64: |
3826 | 0 | case AArch64::PMULLv2i64: |
3827 | 0 | case AArch64::PMULLv8i8: |
3828 | 0 | case AArch64::PMULv16i8: |
3829 | 0 | case AArch64::PMULv8i8: |
3830 | 0 | case AArch64::RADDHNv2i64_v2i32: |
3831 | 0 | case AArch64::RADDHNv4i32_v4i16: |
3832 | 0 | case AArch64::RADDHNv8i16_v8i8: |
3833 | 0 | case AArch64::RORVWr: |
3834 | 0 | case AArch64::RORVXr: |
3835 | 0 | case AArch64::RSUBHNv2i64_v2i32: |
3836 | 0 | case AArch64::RSUBHNv4i32_v4i16: |
3837 | 0 | case AArch64::RSUBHNv8i16_v8i8: |
3838 | 0 | case AArch64::SABDLv16i8_v8i16: |
3839 | 0 | case AArch64::SABDLv2i32_v2i64: |
3840 | 0 | case AArch64::SABDLv4i16_v4i32: |
3841 | 0 | case AArch64::SABDLv4i32_v2i64: |
3842 | 0 | case AArch64::SABDLv8i16_v4i32: |
3843 | 0 | case AArch64::SABDLv8i8_v8i16: |
3844 | 0 | case AArch64::SABDv16i8: |
3845 | 0 | case AArch64::SABDv2i32: |
3846 | 0 | case AArch64::SABDv4i16: |
3847 | 0 | case AArch64::SABDv4i32: |
3848 | 0 | case AArch64::SABDv8i16: |
3849 | 0 | case AArch64::SABDv8i8: |
3850 | 0 | case AArch64::SADDLv16i8_v8i16: |
3851 | 0 | case AArch64::SADDLv2i32_v2i64: |
3852 | 0 | case AArch64::SADDLv4i16_v4i32: |
3853 | 0 | case AArch64::SADDLv4i32_v2i64: |
3854 | 0 | case AArch64::SADDLv8i16_v4i32: |
3855 | 0 | case AArch64::SADDLv8i8_v8i16: |
3856 | 0 | case AArch64::SADDWv16i8_v8i16: |
3857 | 0 | case AArch64::SADDWv2i32_v2i64: |
3858 | 0 | case AArch64::SADDWv4i16_v4i32: |
3859 | 0 | case AArch64::SADDWv4i32_v2i64: |
3860 | 0 | case AArch64::SADDWv8i16_v4i32: |
3861 | 0 | case AArch64::SADDWv8i8_v8i16: |
3862 | 0 | case AArch64::SBCSWr: |
3863 | 0 | case AArch64::SBCSXr: |
3864 | 0 | case AArch64::SBCWr: |
3865 | 0 | case AArch64::SBCXr: |
3866 | 0 | case AArch64::SDIVWr: |
3867 | 0 | case AArch64::SDIVXr: |
3868 | 0 | case AArch64::SDIV_IntWr: |
3869 | 0 | case AArch64::SDIV_IntXr: |
3870 | 0 | case AArch64::SHADDv16i8: |
3871 | 0 | case AArch64::SHADDv2i32: |
3872 | 0 | case AArch64::SHADDv4i16: |
3873 | 0 | case AArch64::SHADDv4i32: |
3874 | 0 | case AArch64::SHADDv8i16: |
3875 | 0 | case AArch64::SHADDv8i8: |
3876 | 0 | case AArch64::SHSUBv16i8: |
3877 | 0 | case AArch64::SHSUBv2i32: |
3878 | 0 | case AArch64::SHSUBv4i16: |
3879 | 0 | case AArch64::SHSUBv4i32: |
3880 | 0 | case AArch64::SHSUBv8i16: |
3881 | 0 | case AArch64::SHSUBv8i8: |
3882 | 0 | case AArch64::SMAXPv16i8: |
3883 | 0 | case AArch64::SMAXPv2i32: |
3884 | 0 | case AArch64::SMAXPv4i16: |
3885 | 0 | case AArch64::SMAXPv4i32: |
3886 | 0 | case AArch64::SMAXPv8i16: |
3887 | 0 | case AArch64::SMAXPv8i8: |
3888 | 0 | case AArch64::SMAXv16i8: |
3889 | 0 | case AArch64::SMAXv2i32: |
3890 | 0 | case AArch64::SMAXv4i16: |
3891 | 0 | case AArch64::SMAXv4i32: |
3892 | 0 | case AArch64::SMAXv8i16: |
3893 | 0 | case AArch64::SMAXv8i8: |
3894 | 0 | case AArch64::SMINPv16i8: |
3895 | 0 | case AArch64::SMINPv2i32: |
3896 | 0 | case AArch64::SMINPv4i16: |
3897 | 0 | case AArch64::SMINPv4i32: |
3898 | 0 | case AArch64::SMINPv8i16: |
3899 | 0 | case AArch64::SMINPv8i8: |
3900 | 0 | case AArch64::SMINv16i8: |
3901 | 0 | case AArch64::SMINv2i32: |
3902 | 0 | case AArch64::SMINv4i16: |
3903 | 0 | case AArch64::SMINv4i32: |
3904 | 0 | case AArch64::SMINv8i16: |
3905 | 0 | case AArch64::SMINv8i8: |
3906 | 0 | case AArch64::SMULLv16i8_v8i16: |
3907 | 0 | case AArch64::SMULLv2i32_v2i64: |
3908 | 0 | case AArch64::SMULLv4i16_v4i32: |
3909 | 0 | case AArch64::SMULLv4i32_v2i64: |
3910 | 0 | case AArch64::SMULLv8i16_v4i32: |
3911 | 0 | case AArch64::SMULLv8i8_v8i16: |
3912 | 0 | case AArch64::SQADDv16i8: |
3913 | 0 | case AArch64::SQADDv1i16: |
3914 | 0 | case AArch64::SQADDv1i32: |
3915 | 0 | case AArch64::SQADDv1i64: |
3916 | 0 | case AArch64::SQADDv1i8: |
3917 | 0 | case AArch64::SQADDv2i32: |
3918 | 0 | case AArch64::SQADDv2i64: |
3919 | 0 | case AArch64::SQADDv4i16: |
3920 | 0 | case AArch64::SQADDv4i32: |
3921 | 0 | case AArch64::SQADDv8i16: |
3922 | 0 | case AArch64::SQADDv8i8: |
3923 | 0 | case AArch64::SQDMULHv1i16: |
3924 | 0 | case AArch64::SQDMULHv1i32: |
3925 | 0 | case AArch64::SQDMULHv2i32: |
3926 | 0 | case AArch64::SQDMULHv4i16: |
3927 | 0 | case AArch64::SQDMULHv4i32: |
3928 | 0 | case AArch64::SQDMULHv8i16: |
3929 | 0 | case AArch64::SQDMULLi16: |
3930 | 0 | case AArch64::SQDMULLi32: |
3931 | 0 | case AArch64::SQDMULLv2i32_v2i64: |
3932 | 0 | case AArch64::SQDMULLv4i16_v4i32: |
3933 | 0 | case AArch64::SQDMULLv4i32_v2i64: |
3934 | 0 | case AArch64::SQDMULLv8i16_v4i32: |
3935 | 0 | case AArch64::SQRDMULHv1i16: |
3936 | 0 | case AArch64::SQRDMULHv1i32: |
3937 | 0 | case AArch64::SQRDMULHv2i32: |
3938 | 0 | case AArch64::SQRDMULHv4i16: |
3939 | 0 | case AArch64::SQRDMULHv4i32: |
3940 | 0 | case AArch64::SQRDMULHv8i16: |
3941 | 0 | case AArch64::SQRSHLv16i8: |
3942 | 0 | case AArch64::SQRSHLv1i16: |
3943 | 0 | case AArch64::SQRSHLv1i32: |
3944 | 0 | case AArch64::SQRSHLv1i64: |
3945 | 0 | case AArch64::SQRSHLv1i8: |
3946 | 0 | case AArch64::SQRSHLv2i32: |
3947 | 0 | case AArch64::SQRSHLv2i64: |
3948 | 0 | case AArch64::SQRSHLv4i16: |
3949 | 0 | case AArch64::SQRSHLv4i32: |
3950 | 0 | case AArch64::SQRSHLv8i16: |
3951 | 0 | case AArch64::SQRSHLv8i8: |
3952 | 0 | case AArch64::SQSHLv16i8: |
3953 | 0 | case AArch64::SQSHLv1i16: |
3954 | 0 | case AArch64::SQSHLv1i32: |
3955 | 0 | case AArch64::SQSHLv1i64: |
3956 | 0 | case AArch64::SQSHLv1i8: |
3957 | 0 | case AArch64::SQSHLv2i32: |
3958 | 0 | case AArch64::SQSHLv2i64: |
3959 | 0 | case AArch64::SQSHLv4i16: |
3960 | 0 | case AArch64::SQSHLv4i32: |
3961 | 0 | case AArch64::SQSHLv8i16: |
3962 | 0 | case AArch64::SQSHLv8i8: |
3963 | 0 | case AArch64::SQSUBv16i8: |
3964 | 0 | case AArch64::SQSUBv1i16: |
3965 | 0 | case AArch64::SQSUBv1i32: |
3966 | 0 | case AArch64::SQSUBv1i64: |
3967 | 0 | case AArch64::SQSUBv1i8: |
3968 | 0 | case AArch64::SQSUBv2i32: |
3969 | 0 | case AArch64::SQSUBv2i64: |
3970 | 0 | case AArch64::SQSUBv4i16: |
3971 | 0 | case AArch64::SQSUBv4i32: |
3972 | 0 | case AArch64::SQSUBv8i16: |
3973 | 0 | case AArch64::SQSUBv8i8: |
3974 | 0 | case AArch64::SRHADDv16i8: |
3975 | 0 | case AArch64::SRHADDv2i32: |
3976 | 0 | case AArch64::SRHADDv4i16: |
3977 | 0 | case AArch64::SRHADDv4i32: |
3978 | 0 | case AArch64::SRHADDv8i16: |
3979 | 0 | case AArch64::SRHADDv8i8: |
3980 | 0 | case AArch64::SRSHLv16i8: |
3981 | 0 | case AArch64::SRSHLv1i64: |
3982 | 0 | case AArch64::SRSHLv2i32: |
3983 | 0 | case AArch64::SRSHLv2i64: |
3984 | 0 | case AArch64::SRSHLv4i16: |
3985 | 0 | case AArch64::SRSHLv4i32: |
3986 | 0 | case AArch64::SRSHLv8i16: |
3987 | 0 | case AArch64::SRSHLv8i8: |
3988 | 0 | case AArch64::SSHLv16i8: |
3989 | 0 | case AArch64::SSHLv1i64: |
3990 | 0 | case AArch64::SSHLv2i32: |
3991 | 0 | case AArch64::SSHLv2i64: |
3992 | 0 | case AArch64::SSHLv4i16: |
3993 | 0 | case AArch64::SSHLv4i32: |
3994 | 0 | case AArch64::SSHLv8i16: |
3995 | 0 | case AArch64::SSHLv8i8: |
3996 | 0 | case AArch64::SSUBLv16i8_v8i16: |
3997 | 0 | case AArch64::SSUBLv2i32_v2i64: |
3998 | 0 | case AArch64::SSUBLv4i16_v4i32: |
3999 | 0 | case AArch64::SSUBLv4i32_v2i64: |
4000 | 0 | case AArch64::SSUBLv8i16_v4i32: |
4001 | 0 | case AArch64::SSUBLv8i8_v8i16: |
4002 | 0 | case AArch64::SSUBWv16i8_v8i16: |
4003 | 0 | case AArch64::SSUBWv2i32_v2i64: |
4004 | 0 | case AArch64::SSUBWv4i16_v4i32: |
4005 | 0 | case AArch64::SSUBWv4i32_v2i64: |
4006 | 0 | case AArch64::SSUBWv8i16_v4i32: |
4007 | 0 | case AArch64::SSUBWv8i8_v8i16: |
4008 | 0 | case AArch64::SUBHNv2i64_v2i32: |
4009 | 0 | case AArch64::SUBHNv4i32_v4i16: |
4010 | 0 | case AArch64::SUBHNv8i16_v8i8: |
4011 | 0 | case AArch64::SUBv16i8: |
4012 | 0 | case AArch64::SUBv1i64: |
4013 | 0 | case AArch64::SUBv2i32: |
4014 | 0 | case AArch64::SUBv2i64: |
4015 | 0 | case AArch64::SUBv4i16: |
4016 | 0 | case AArch64::SUBv4i32: |
4017 | 0 | case AArch64::SUBv8i16: |
4018 | 0 | case AArch64::SUBv8i8: |
4019 | 0 | case AArch64::TRN1v16i8: |
4020 | 0 | case AArch64::TRN1v2i32: |
4021 | 0 | case AArch64::TRN1v2i64: |
4022 | 0 | case AArch64::TRN1v4i16: |
4023 | 0 | case AArch64::TRN1v4i32: |
4024 | 0 | case AArch64::TRN1v8i16: |
4025 | 0 | case AArch64::TRN1v8i8: |
4026 | 0 | case AArch64::TRN2v16i8: |
4027 | 0 | case AArch64::TRN2v2i32: |
4028 | 0 | case AArch64::TRN2v2i64: |
4029 | 0 | case AArch64::TRN2v4i16: |
4030 | 0 | case AArch64::TRN2v4i32: |
4031 | 0 | case AArch64::TRN2v8i16: |
4032 | 0 | case AArch64::TRN2v8i8: |
4033 | 0 | case AArch64::UABDLv16i8_v8i16: |
4034 | 0 | case AArch64::UABDLv2i32_v2i64: |
4035 | 0 | case AArch64::UABDLv4i16_v4i32: |
4036 | 0 | case AArch64::UABDLv4i32_v2i64: |
4037 | 0 | case AArch64::UABDLv8i16_v4i32: |
4038 | 0 | case AArch64::UABDLv8i8_v8i16: |
4039 | 0 | case AArch64::UABDv16i8: |
4040 | 0 | case AArch64::UABDv2i32: |
4041 | 0 | case AArch64::UABDv4i16: |
4042 | 0 | case AArch64::UABDv4i32: |
4043 | 0 | case AArch64::UABDv8i16: |
4044 | 0 | case AArch64::UABDv8i8: |
4045 | 0 | case AArch64::UADDLv16i8_v8i16: |
4046 | 0 | case AArch64::UADDLv2i32_v2i64: |
4047 | 0 | case AArch64::UADDLv4i16_v4i32: |
4048 | 0 | case AArch64::UADDLv4i32_v2i64: |
4049 | 0 | case AArch64::UADDLv8i16_v4i32: |
4050 | 0 | case AArch64::UADDLv8i8_v8i16: |
4051 | 0 | case AArch64::UADDWv16i8_v8i16: |
4052 | 0 | case AArch64::UADDWv2i32_v2i64: |
4053 | 0 | case AArch64::UADDWv4i16_v4i32: |
4054 | 0 | case AArch64::UADDWv4i32_v2i64: |
4055 | 0 | case AArch64::UADDWv8i16_v4i32: |
4056 | 0 | case AArch64::UADDWv8i8_v8i16: |
4057 | 0 | case AArch64::UDIVWr: |
4058 | 0 | case AArch64::UDIVXr: |
4059 | 0 | case AArch64::UDIV_IntWr: |
4060 | 0 | case AArch64::UDIV_IntXr: |
4061 | 0 | case AArch64::UHADDv16i8: |
4062 | 0 | case AArch64::UHADDv2i32: |
4063 | 0 | case AArch64::UHADDv4i16: |
4064 | 0 | case AArch64::UHADDv4i32: |
4065 | 0 | case AArch64::UHADDv8i16: |
4066 | 0 | case AArch64::UHADDv8i8: |
4067 | 0 | case AArch64::UHSUBv16i8: |
4068 | 0 | case AArch64::UHSUBv2i32: |
4069 | 0 | case AArch64::UHSUBv4i16: |
4070 | 0 | case AArch64::UHSUBv4i32: |
4071 | 0 | case AArch64::UHSUBv8i16: |
4072 | 0 | case AArch64::UHSUBv8i8: |
4073 | 0 | case AArch64::UMAXPv16i8: |
4074 | 0 | case AArch64::UMAXPv2i32: |
4075 | 0 | case AArch64::UMAXPv4i16: |
4076 | 0 | case AArch64::UMAXPv4i32: |
4077 | 0 | case AArch64::UMAXPv8i16: |
4078 | 0 | case AArch64::UMAXPv8i8: |
4079 | 0 | case AArch64::UMAXv16i8: |
4080 | 0 | case AArch64::UMAXv2i32: |
4081 | 0 | case AArch64::UMAXv4i16: |
4082 | 0 | case AArch64::UMAXv4i32: |
4083 | 0 | case AArch64::UMAXv8i16: |
4084 | 0 | case AArch64::UMAXv8i8: |
4085 | 0 | case AArch64::UMINPv16i8: |
4086 | 0 | case AArch64::UMINPv2i32: |
4087 | 0 | case AArch64::UMINPv4i16: |
4088 | 0 | case AArch64::UMINPv4i32: |
4089 | 0 | case AArch64::UMINPv8i16: |
4090 | 0 | case AArch64::UMINPv8i8: |
4091 | 0 | case AArch64::UMINv16i8: |
4092 | 0 | case AArch64::UMINv2i32: |
4093 | 0 | case AArch64::UMINv4i16: |
4094 | 0 | case AArch64::UMINv4i32: |
4095 | 0 | case AArch64::UMINv8i16: |
4096 | 0 | case AArch64::UMINv8i8: |
4097 | 0 | case AArch64::UMULLv16i8_v8i16: |
4098 | 0 | case AArch64::UMULLv2i32_v2i64: |
4099 | 0 | case AArch64::UMULLv4i16_v4i32: |
4100 | 0 | case AArch64::UMULLv4i32_v2i64: |
4101 | 0 | case AArch64::UMULLv8i16_v4i32: |
4102 | 0 | case AArch64::UMULLv8i8_v8i16: |
4103 | 0 | case AArch64::UQADDv16i8: |
4104 | 0 | case AArch64::UQADDv1i16: |
4105 | 0 | case AArch64::UQADDv1i32: |
4106 | 0 | case AArch64::UQADDv1i64: |
4107 | 0 | case AArch64::UQADDv1i8: |
4108 | 0 | case AArch64::UQADDv2i32: |
4109 | 0 | case AArch64::UQADDv2i64: |
4110 | 0 | case AArch64::UQADDv4i16: |
4111 | 0 | case AArch64::UQADDv4i32: |
4112 | 0 | case AArch64::UQADDv8i16: |
4113 | 0 | case AArch64::UQADDv8i8: |
4114 | 0 | case AArch64::UQRSHLv16i8: |
4115 | 0 | case AArch64::UQRSHLv1i16: |
4116 | 0 | case AArch64::UQRSHLv1i32: |
4117 | 0 | case AArch64::UQRSHLv1i64: |
4118 | 0 | case AArch64::UQRSHLv1i8: |
4119 | 0 | case AArch64::UQRSHLv2i32: |
4120 | 0 | case AArch64::UQRSHLv2i64: |
4121 | 0 | case AArch64::UQRSHLv4i16: |
4122 | 0 | case AArch64::UQRSHLv4i32: |
4123 | 0 | case AArch64::UQRSHLv8i16: |
4124 | 0 | case AArch64::UQRSHLv8i8: |
4125 | 0 | case AArch64::UQSHLv16i8: |
4126 | 0 | case AArch64::UQSHLv1i16: |
4127 | 0 | case AArch64::UQSHLv1i32: |
4128 | 0 | case AArch64::UQSHLv1i64: |
4129 | 0 | case AArch64::UQSHLv1i8: |
4130 | 0 | case AArch64::UQSHLv2i32: |
4131 | 0 | case AArch64::UQSHLv2i64: |
4132 | 0 | case AArch64::UQSHLv4i16: |
4133 | 0 | case AArch64::UQSHLv4i32: |
4134 | 0 | case AArch64::UQSHLv8i16: |
4135 | 0 | case AArch64::UQSHLv8i8: |
4136 | 0 | case AArch64::UQSUBv16i8: |
4137 | 0 | case AArch64::UQSUBv1i16: |
4138 | 0 | case AArch64::UQSUBv1i32: |
4139 | 0 | case AArch64::UQSUBv1i64: |
4140 | 0 | case AArch64::UQSUBv1i8: |
4141 | 0 | case AArch64::UQSUBv2i32: |
4142 | 0 | case AArch64::UQSUBv2i64: |
4143 | 0 | case AArch64::UQSUBv4i16: |
4144 | 0 | case AArch64::UQSUBv4i32: |
4145 | 0 | case AArch64::UQSUBv8i16: |
4146 | 0 | case AArch64::UQSUBv8i8: |
4147 | 0 | case AArch64::URHADDv16i8: |
4148 | 0 | case AArch64::URHADDv2i32: |
4149 | 0 | case AArch64::URHADDv4i16: |
4150 | 0 | case AArch64::URHADDv4i32: |
4151 | 0 | case AArch64::URHADDv8i16: |
4152 | 0 | case AArch64::URHADDv8i8: |
4153 | 0 | case AArch64::URSHLv16i8: |
4154 | 0 | case AArch64::URSHLv1i64: |
4155 | 0 | case AArch64::URSHLv2i32: |
4156 | 0 | case AArch64::URSHLv2i64: |
4157 | 0 | case AArch64::URSHLv4i16: |
4158 | 0 | case AArch64::URSHLv4i32: |
4159 | 0 | case AArch64::URSHLv8i16: |
4160 | 0 | case AArch64::URSHLv8i8: |
4161 | 0 | case AArch64::USHLv16i8: |
4162 | 0 | case AArch64::USHLv1i64: |
4163 | 0 | case AArch64::USHLv2i32: |
4164 | 0 | case AArch64::USHLv2i64: |
4165 | 0 | case AArch64::USHLv4i16: |
4166 | 0 | case AArch64::USHLv4i32: |
4167 | 0 | case AArch64::USHLv8i16: |
4168 | 0 | case AArch64::USHLv8i8: |
4169 | 0 | case AArch64::USUBLv16i8_v8i16: |
4170 | 0 | case AArch64::USUBLv2i32_v2i64: |
4171 | 0 | case AArch64::USUBLv4i16_v4i32: |
4172 | 0 | case AArch64::USUBLv4i32_v2i64: |
4173 | 0 | case AArch64::USUBLv8i16_v4i32: |
4174 | 0 | case AArch64::USUBLv8i8_v8i16: |
4175 | 0 | case AArch64::USUBWv16i8_v8i16: |
4176 | 0 | case AArch64::USUBWv2i32_v2i64: |
4177 | 0 | case AArch64::USUBWv4i16_v4i32: |
4178 | 0 | case AArch64::USUBWv4i32_v2i64: |
4179 | 0 | case AArch64::USUBWv8i16_v4i32: |
4180 | 0 | case AArch64::USUBWv8i8_v8i16: |
4181 | 0 | case AArch64::UZP1v16i8: |
4182 | 0 | case AArch64::UZP1v2i32: |
4183 | 0 | case AArch64::UZP1v2i64: |
4184 | 0 | case AArch64::UZP1v4i16: |
4185 | 0 | case AArch64::UZP1v4i32: |
4186 | 0 | case AArch64::UZP1v8i16: |
4187 | 0 | case AArch64::UZP1v8i8: |
4188 | 0 | case AArch64::UZP2v16i8: |
4189 | 0 | case AArch64::UZP2v2i32: |
4190 | 0 | case AArch64::UZP2v2i64: |
4191 | 0 | case AArch64::UZP2v4i16: |
4192 | 0 | case AArch64::UZP2v4i32: |
4193 | 0 | case AArch64::UZP2v8i16: |
4194 | 0 | case AArch64::UZP2v8i8: |
4195 | 0 | case AArch64::ZIP1v16i8: |
4196 | 0 | case AArch64::ZIP1v2i32: |
4197 | 0 | case AArch64::ZIP1v2i64: |
4198 | 0 | case AArch64::ZIP1v4i16: |
4199 | 0 | case AArch64::ZIP1v4i32: |
4200 | 0 | case AArch64::ZIP1v8i16: |
4201 | 0 | case AArch64::ZIP1v8i8: |
4202 | 0 | case AArch64::ZIP2v16i8: |
4203 | 0 | case AArch64::ZIP2v2i32: |
4204 | 0 | case AArch64::ZIP2v2i64: |
4205 | 0 | case AArch64::ZIP2v4i16: |
4206 | 0 | case AArch64::ZIP2v4i32: |
4207 | 0 | case AArch64::ZIP2v8i16: |
4208 | 0 | case AArch64::ZIP2v8i8: { |
4209 | | // op: Rd |
4210 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4211 | 0 | Value |= op & UINT64_C(31); |
4212 | | // op: Rn |
4213 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4214 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4215 | | // op: Rm |
4216 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4217 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4218 | 0 | break; |
4219 | 0 | } |
4220 | 0 | case AArch64::FMADDDrrr: |
4221 | 0 | case AArch64::FMADDHrrr: |
4222 | 0 | case AArch64::FMADDSrrr: |
4223 | 0 | case AArch64::FMSUBDrrr: |
4224 | 0 | case AArch64::FMSUBHrrr: |
4225 | 0 | case AArch64::FMSUBSrrr: |
4226 | 0 | case AArch64::FNMADDDrrr: |
4227 | 0 | case AArch64::FNMADDHrrr: |
4228 | 0 | case AArch64::FNMADDSrrr: |
4229 | 0 | case AArch64::FNMSUBDrrr: |
4230 | 0 | case AArch64::FNMSUBHrrr: |
4231 | 0 | case AArch64::FNMSUBSrrr: |
4232 | 0 | case AArch64::MADDWrrr: |
4233 | 0 | case AArch64::MADDXrrr: |
4234 | 0 | case AArch64::MSUBWrrr: |
4235 | 0 | case AArch64::MSUBXrrr: |
4236 | 0 | case AArch64::SMADDLrrr: |
4237 | 0 | case AArch64::SMSUBLrrr: |
4238 | 0 | case AArch64::UMADDLrrr: |
4239 | 0 | case AArch64::UMSUBLrrr: { |
4240 | | // op: Rd |
4241 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4242 | 0 | Value |= op & UINT64_C(31); |
4243 | | // op: Rn |
4244 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4245 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4246 | | // op: Rm |
4247 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4248 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4249 | | // op: Ra |
4250 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4251 | 0 | Value |= (op & UINT64_C(31)) << 10; |
4252 | 0 | break; |
4253 | 0 | } |
4254 | 0 | case AArch64::CSELWr: |
4255 | 0 | case AArch64::CSELXr: |
4256 | 0 | case AArch64::CSINCWr: |
4257 | 0 | case AArch64::CSINCXr: |
4258 | 0 | case AArch64::CSINVWr: |
4259 | 0 | case AArch64::CSINVXr: |
4260 | 0 | case AArch64::CSNEGWr: |
4261 | 0 | case AArch64::CSNEGXr: |
4262 | 0 | case AArch64::FCSELDrrr: |
4263 | 0 | case AArch64::FCSELHrrr: |
4264 | 0 | case AArch64::FCSELSrrr: { |
4265 | | // op: Rd |
4266 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4267 | 0 | Value |= op & UINT64_C(31); |
4268 | | // op: Rn |
4269 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4270 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4271 | | // op: Rm |
4272 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4273 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4274 | | // op: cond |
4275 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4276 | 0 | Value |= (op & UINT64_C(15)) << 12; |
4277 | 0 | break; |
4278 | 0 | } |
4279 | 0 | case AArch64::ADDSXrx64: |
4280 | 0 | case AArch64::ADDXrx64: |
4281 | 0 | case AArch64::SUBSXrx64: |
4282 | 0 | case AArch64::SUBXrx64: { |
4283 | | // op: Rd |
4284 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4285 | 0 | Value |= op & UINT64_C(31); |
4286 | | // op: Rn |
4287 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4288 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4289 | | // op: Rm |
4290 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4291 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4292 | | // op: ext |
4293 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4294 | 0 | Value |= (op & UINT64_C(32)) << 10; |
4295 | 0 | Value |= (op & UINT64_C(7)) << 10; |
4296 | 0 | break; |
4297 | 0 | } |
4298 | 0 | case AArch64::ADDSWrx: |
4299 | 0 | case AArch64::ADDSXrx: |
4300 | 0 | case AArch64::ADDWrx: |
4301 | 0 | case AArch64::ADDXrx: |
4302 | 0 | case AArch64::SUBSWrx: |
4303 | 0 | case AArch64::SUBSXrx: |
4304 | 0 | case AArch64::SUBWrx: |
4305 | 0 | case AArch64::SUBXrx: { |
4306 | | // op: Rd |
4307 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4308 | 0 | Value |= op & UINT64_C(31); |
4309 | | // op: Rn |
4310 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4311 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4312 | | // op: Rm |
4313 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4314 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4315 | | // op: ext |
4316 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4317 | 0 | Value |= (op & UINT64_C(63)) << 10; |
4318 | 0 | break; |
4319 | 0 | } |
4320 | 0 | case AArch64::FMULXv1i64_indexed: |
4321 | 0 | case AArch64::FMULXv2i64_indexed: |
4322 | 0 | case AArch64::FMULv1i64_indexed: |
4323 | 0 | case AArch64::FMULv2i64_indexed: { |
4324 | | // op: Rd |
4325 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4326 | 0 | Value |= op & UINT64_C(31); |
4327 | | // op: Rn |
4328 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4329 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4330 | | // op: Rm |
4331 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4332 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4333 | | // op: idx |
4334 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4335 | 0 | Value |= (op & UINT64_C(1)) << 11; |
4336 | 0 | break; |
4337 | 0 | } |
4338 | 0 | case AArch64::FMULXv1i32_indexed: |
4339 | 0 | case AArch64::FMULXv2i32_indexed: |
4340 | 0 | case AArch64::FMULXv4i32_indexed: |
4341 | 0 | case AArch64::FMULv1i32_indexed: |
4342 | 0 | case AArch64::FMULv2i32_indexed: |
4343 | 0 | case AArch64::FMULv4i32_indexed: |
4344 | 0 | case AArch64::MULv2i32_indexed: |
4345 | 0 | case AArch64::MULv4i32_indexed: |
4346 | 0 | case AArch64::SMULLv2i32_indexed: |
4347 | 0 | case AArch64::SMULLv4i32_indexed: |
4348 | 0 | case AArch64::SQDMULHv1i32_indexed: |
4349 | 0 | case AArch64::SQDMULHv2i32_indexed: |
4350 | 0 | case AArch64::SQDMULHv4i32_indexed: |
4351 | 0 | case AArch64::SQDMULLv1i64_indexed: |
4352 | 0 | case AArch64::SQDMULLv2i32_indexed: |
4353 | 0 | case AArch64::SQDMULLv4i32_indexed: |
4354 | 0 | case AArch64::SQRDMULHv1i32_indexed: |
4355 | 0 | case AArch64::SQRDMULHv2i32_indexed: |
4356 | 0 | case AArch64::SQRDMULHv4i32_indexed: |
4357 | 0 | case AArch64::UMULLv2i32_indexed: |
4358 | 0 | case AArch64::UMULLv4i32_indexed: { |
4359 | | // op: Rd |
4360 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4361 | 0 | Value |= op & UINT64_C(31); |
4362 | | // op: Rn |
4363 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4364 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4365 | | // op: Rm |
4366 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4367 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4368 | | // op: idx |
4369 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4370 | 0 | Value |= (op & UINT64_C(1)) << 21; |
4371 | 0 | Value |= (op & UINT64_C(2)) << 10; |
4372 | 0 | break; |
4373 | 0 | } |
4374 | 0 | case AArch64::EXTv16i8: { |
4375 | | // op: Rd |
4376 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4377 | 0 | Value |= op & UINT64_C(31); |
4378 | | // op: Rn |
4379 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4380 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4381 | | // op: Rm |
4382 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4383 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4384 | | // op: imm |
4385 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4386 | 0 | Value |= (op & UINT64_C(15)) << 11; |
4387 | 0 | break; |
4388 | 0 | } |
4389 | 0 | case AArch64::EXTRWrri: { |
4390 | | // op: Rd |
4391 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4392 | 0 | Value |= op & UINT64_C(31); |
4393 | | // op: Rn |
4394 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4395 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4396 | | // op: Rm |
4397 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4398 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4399 | | // op: imm |
4400 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4401 | 0 | Value |= (op & UINT64_C(31)) << 10; |
4402 | 0 | break; |
4403 | 0 | } |
4404 | 0 | case AArch64::EXTRXrri: { |
4405 | | // op: Rd |
4406 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4407 | 0 | Value |= op & UINT64_C(31); |
4408 | | // op: Rn |
4409 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4410 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4411 | | // op: Rm |
4412 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4413 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4414 | | // op: imm |
4415 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4416 | 0 | Value |= (op & UINT64_C(63)) << 10; |
4417 | 0 | break; |
4418 | 0 | } |
4419 | 0 | case AArch64::EXTv8i8: { |
4420 | | // op: Rd |
4421 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4422 | 0 | Value |= op & UINT64_C(31); |
4423 | | // op: Rn |
4424 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4425 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4426 | | // op: Rm |
4427 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4428 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4429 | | // op: imm |
4430 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4431 | 0 | Value |= (op & UINT64_C(7)) << 11; |
4432 | 0 | break; |
4433 | 0 | } |
4434 | 0 | case AArch64::SMULHrr: |
4435 | 0 | case AArch64::UMULHrr: { |
4436 | | // op: Rd |
4437 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4438 | 0 | Value |= op & UINT64_C(31); |
4439 | | // op: Rn |
4440 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4441 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4442 | | // op: Rm |
4443 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4444 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4445 | 0 | Value = fixMulHigh(MI, Value, STI); |
4446 | 0 | break; |
4447 | 0 | } |
4448 | 0 | case AArch64::DUPv2i64lane: |
4449 | 0 | case AArch64::UMOVvi64: { |
4450 | | // op: Rd |
4451 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4452 | 0 | Value |= op & UINT64_C(31); |
4453 | | // op: Rn |
4454 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4455 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4456 | | // op: idx |
4457 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4458 | 0 | Value |= (op & UINT64_C(1)) << 20; |
4459 | 0 | break; |
4460 | 0 | } |
4461 | 0 | case AArch64::DUPv16i8lane: |
4462 | 0 | case AArch64::DUPv8i8lane: |
4463 | 0 | case AArch64::SMOVvi8to32: |
4464 | 0 | case AArch64::SMOVvi8to64: |
4465 | 0 | case AArch64::UMOVvi8: { |
4466 | | // op: Rd |
4467 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4468 | 0 | Value |= op & UINT64_C(31); |
4469 | | // op: Rn |
4470 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4471 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4472 | | // op: idx |
4473 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4474 | 0 | Value |= (op & UINT64_C(15)) << 17; |
4475 | 0 | break; |
4476 | 0 | } |
4477 | 0 | case AArch64::DUPv2i32lane: |
4478 | 0 | case AArch64::DUPv4i32lane: |
4479 | 0 | case AArch64::SMOVvi32to64: |
4480 | 0 | case AArch64::UMOVvi32: { |
4481 | | // op: Rd |
4482 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4483 | 0 | Value |= op & UINT64_C(31); |
4484 | | // op: Rn |
4485 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4486 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4487 | | // op: idx |
4488 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4489 | 0 | Value |= (op & UINT64_C(3)) << 19; |
4490 | 0 | break; |
4491 | 0 | } |
4492 | 0 | case AArch64::DUPv4i16lane: |
4493 | 0 | case AArch64::DUPv8i16lane: |
4494 | 0 | case AArch64::SMOVvi16to32: |
4495 | 0 | case AArch64::SMOVvi16to64: |
4496 | 0 | case AArch64::UMOVvi16: { |
4497 | | // op: Rd |
4498 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4499 | 0 | Value |= op & UINT64_C(31); |
4500 | | // op: Rn |
4501 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4502 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4503 | | // op: idx |
4504 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4505 | 0 | Value |= (op & UINT64_C(7)) << 18; |
4506 | 0 | break; |
4507 | 0 | } |
4508 | 0 | case AArch64::ADDSWri: |
4509 | 0 | case AArch64::ADDSXri: |
4510 | 0 | case AArch64::ADDWri: |
4511 | 0 | case AArch64::ADDXri: |
4512 | 0 | case AArch64::SUBSWri: |
4513 | 0 | case AArch64::SUBSXri: |
4514 | 0 | case AArch64::SUBWri: |
4515 | 0 | case AArch64::SUBXri: { |
4516 | | // op: Rd |
4517 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4518 | 0 | Value |= op & UINT64_C(31); |
4519 | | // op: Rn |
4520 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4521 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4522 | | // op: imm |
4523 | 0 | op = getAddSubImmOpValue(MI, 2, Fixups, STI); |
4524 | 0 | Value |= (op & UINT64_C(16383)) << 10; |
4525 | 0 | break; |
4526 | 0 | } |
4527 | 0 | case AArch64::ANDSWri: |
4528 | 0 | case AArch64::ANDWri: |
4529 | 0 | case AArch64::EORWri: |
4530 | 0 | case AArch64::ORRWri: { |
4531 | | // op: Rd |
4532 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4533 | 0 | Value |= op & UINT64_C(31); |
4534 | | // op: Rn |
4535 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4536 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4537 | | // op: imm |
4538 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4539 | 0 | Value |= (op & UINT64_C(4095)) << 10; |
4540 | 0 | break; |
4541 | 0 | } |
4542 | 0 | case AArch64::ANDSXri: |
4543 | 0 | case AArch64::ANDXri: |
4544 | 0 | case AArch64::EORXri: |
4545 | 0 | case AArch64::ORRXri: { |
4546 | | // op: Rd |
4547 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4548 | 0 | Value |= op & UINT64_C(31); |
4549 | | // op: Rn |
4550 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4551 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4552 | | // op: imm |
4553 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4554 | 0 | Value |= (op & UINT64_C(8191)) << 10; |
4555 | 0 | break; |
4556 | 0 | } |
4557 | 0 | case AArch64::SHLv4i16_shift: |
4558 | 0 | case AArch64::SHLv8i16_shift: |
4559 | 0 | case AArch64::SQSHLUh: |
4560 | 0 | case AArch64::SQSHLUv4i16_shift: |
4561 | 0 | case AArch64::SQSHLUv8i16_shift: |
4562 | 0 | case AArch64::SQSHLh: |
4563 | 0 | case AArch64::SQSHLv4i16_shift: |
4564 | 0 | case AArch64::SQSHLv8i16_shift: |
4565 | 0 | case AArch64::SSHLLv4i16_shift: |
4566 | 0 | case AArch64::SSHLLv8i16_shift: |
4567 | 0 | case AArch64::UQSHLh: |
4568 | 0 | case AArch64::UQSHLv4i16_shift: |
4569 | 0 | case AArch64::UQSHLv8i16_shift: |
4570 | 0 | case AArch64::USHLLv4i16_shift: |
4571 | 0 | case AArch64::USHLLv8i16_shift: { |
4572 | | // op: Rd |
4573 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4574 | 0 | Value |= op & UINT64_C(31); |
4575 | | // op: Rn |
4576 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4577 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4578 | | // op: imm |
4579 | 0 | op = getVecShiftL16OpValue(MI, 2, Fixups, STI); |
4580 | 0 | Value |= (op & UINT64_C(15)) << 16; |
4581 | 0 | break; |
4582 | 0 | } |
4583 | 0 | case AArch64::SHLv2i32_shift: |
4584 | 0 | case AArch64::SHLv4i32_shift: |
4585 | 0 | case AArch64::SQSHLUs: |
4586 | 0 | case AArch64::SQSHLUv2i32_shift: |
4587 | 0 | case AArch64::SQSHLUv4i32_shift: |
4588 | 0 | case AArch64::SQSHLs: |
4589 | 0 | case AArch64::SQSHLv2i32_shift: |
4590 | 0 | case AArch64::SQSHLv4i32_shift: |
4591 | 0 | case AArch64::SSHLLv2i32_shift: |
4592 | 0 | case AArch64::SSHLLv4i32_shift: |
4593 | 0 | case AArch64::UQSHLs: |
4594 | 0 | case AArch64::UQSHLv2i32_shift: |
4595 | 0 | case AArch64::UQSHLv4i32_shift: |
4596 | 0 | case AArch64::USHLLv2i32_shift: |
4597 | 0 | case AArch64::USHLLv4i32_shift: { |
4598 | | // op: Rd |
4599 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4600 | 0 | Value |= op & UINT64_C(31); |
4601 | | // op: Rn |
4602 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4603 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4604 | | // op: imm |
4605 | 0 | op = getVecShiftL32OpValue(MI, 2, Fixups, STI); |
4606 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4607 | 0 | break; |
4608 | 0 | } |
4609 | 0 | case AArch64::SHLd: |
4610 | 0 | case AArch64::SHLv2i64_shift: |
4611 | 0 | case AArch64::SQSHLUd: |
4612 | 0 | case AArch64::SQSHLUv2i64_shift: |
4613 | 0 | case AArch64::SQSHLd: |
4614 | 0 | case AArch64::SQSHLv2i64_shift: |
4615 | 0 | case AArch64::UQSHLd: |
4616 | 0 | case AArch64::UQSHLv2i64_shift: { |
4617 | | // op: Rd |
4618 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4619 | 0 | Value |= op & UINT64_C(31); |
4620 | | // op: Rn |
4621 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4622 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4623 | | // op: imm |
4624 | 0 | op = getVecShiftL64OpValue(MI, 2, Fixups, STI); |
4625 | 0 | Value |= (op & UINT64_C(63)) << 16; |
4626 | 0 | break; |
4627 | 0 | } |
4628 | 0 | case AArch64::SHLv16i8_shift: |
4629 | 0 | case AArch64::SHLv8i8_shift: |
4630 | 0 | case AArch64::SQSHLUb: |
4631 | 0 | case AArch64::SQSHLUv16i8_shift: |
4632 | 0 | case AArch64::SQSHLUv8i8_shift: |
4633 | 0 | case AArch64::SQSHLb: |
4634 | 0 | case AArch64::SQSHLv16i8_shift: |
4635 | 0 | case AArch64::SQSHLv8i8_shift: |
4636 | 0 | case AArch64::SSHLLv16i8_shift: |
4637 | 0 | case AArch64::SSHLLv8i8_shift: |
4638 | 0 | case AArch64::UQSHLb: |
4639 | 0 | case AArch64::UQSHLv16i8_shift: |
4640 | 0 | case AArch64::UQSHLv8i8_shift: |
4641 | 0 | case AArch64::USHLLv16i8_shift: |
4642 | 0 | case AArch64::USHLLv8i8_shift: { |
4643 | | // op: Rd |
4644 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4645 | 0 | Value |= op & UINT64_C(31); |
4646 | | // op: Rn |
4647 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4648 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4649 | | // op: imm |
4650 | 0 | op = getVecShiftL8OpValue(MI, 2, Fixups, STI); |
4651 | 0 | Value |= (op & UINT64_C(7)) << 16; |
4652 | 0 | break; |
4653 | 0 | } |
4654 | 0 | case AArch64::FCVTZSh: |
4655 | 0 | case AArch64::FCVTZSv4i16_shift: |
4656 | 0 | case AArch64::FCVTZSv8i16_shift: |
4657 | 0 | case AArch64::FCVTZUh: |
4658 | 0 | case AArch64::FCVTZUv4i16_shift: |
4659 | 0 | case AArch64::FCVTZUv8i16_shift: |
4660 | 0 | case AArch64::SCVTFh: |
4661 | 0 | case AArch64::SCVTFv4i16_shift: |
4662 | 0 | case AArch64::SCVTFv8i16_shift: |
4663 | 0 | case AArch64::SQRSHRNh: |
4664 | 0 | case AArch64::SQRSHRUNh: |
4665 | 0 | case AArch64::SQSHRNh: |
4666 | 0 | case AArch64::SQSHRUNh: |
4667 | 0 | case AArch64::SRSHRv4i16_shift: |
4668 | 0 | case AArch64::SRSHRv8i16_shift: |
4669 | 0 | case AArch64::SSHRv4i16_shift: |
4670 | 0 | case AArch64::SSHRv8i16_shift: |
4671 | 0 | case AArch64::UCVTFh: |
4672 | 0 | case AArch64::UCVTFv4i16_shift: |
4673 | 0 | case AArch64::UCVTFv8i16_shift: |
4674 | 0 | case AArch64::UQRSHRNh: |
4675 | 0 | case AArch64::UQSHRNh: |
4676 | 0 | case AArch64::URSHRv4i16_shift: |
4677 | 0 | case AArch64::URSHRv8i16_shift: |
4678 | 0 | case AArch64::USHRv4i16_shift: |
4679 | 0 | case AArch64::USHRv8i16_shift: { |
4680 | | // op: Rd |
4681 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4682 | 0 | Value |= op & UINT64_C(31); |
4683 | | // op: Rn |
4684 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4685 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4686 | | // op: imm |
4687 | 0 | op = getVecShiftR16OpValue(MI, 2, Fixups, STI); |
4688 | 0 | Value |= (op & UINT64_C(15)) << 16; |
4689 | 0 | break; |
4690 | 0 | } |
4691 | 0 | case AArch64::RSHRNv8i8_shift: |
4692 | 0 | case AArch64::SHRNv8i8_shift: |
4693 | 0 | case AArch64::SQRSHRNv8i8_shift: |
4694 | 0 | case AArch64::SQRSHRUNv8i8_shift: |
4695 | 0 | case AArch64::SQSHRNv8i8_shift: |
4696 | 0 | case AArch64::SQSHRUNv8i8_shift: |
4697 | 0 | case AArch64::UQRSHRNv8i8_shift: |
4698 | 0 | case AArch64::UQSHRNv8i8_shift: { |
4699 | | // op: Rd |
4700 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4701 | 0 | Value |= op & UINT64_C(31); |
4702 | | // op: Rn |
4703 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4704 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4705 | | // op: imm |
4706 | 0 | op = getVecShiftR16OpValue(MI, 2, Fixups, STI); |
4707 | 0 | Value |= (op & UINT64_C(7)) << 16; |
4708 | 0 | break; |
4709 | 0 | } |
4710 | 0 | case AArch64::RSHRNv4i16_shift: |
4711 | 0 | case AArch64::SHRNv4i16_shift: |
4712 | 0 | case AArch64::SQRSHRNv4i16_shift: |
4713 | 0 | case AArch64::SQRSHRUNv4i16_shift: |
4714 | 0 | case AArch64::SQSHRNv4i16_shift: |
4715 | 0 | case AArch64::SQSHRUNv4i16_shift: |
4716 | 0 | case AArch64::UQRSHRNv4i16_shift: |
4717 | 0 | case AArch64::UQSHRNv4i16_shift: { |
4718 | | // op: Rd |
4719 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4720 | 0 | Value |= op & UINT64_C(31); |
4721 | | // op: Rn |
4722 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4723 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4724 | | // op: imm |
4725 | 0 | op = getVecShiftR32OpValue(MI, 2, Fixups, STI); |
4726 | 0 | Value |= (op & UINT64_C(15)) << 16; |
4727 | 0 | break; |
4728 | 0 | } |
4729 | 0 | case AArch64::FCVTZSs: |
4730 | 0 | case AArch64::FCVTZSv2i32_shift: |
4731 | 0 | case AArch64::FCVTZSv4i32_shift: |
4732 | 0 | case AArch64::FCVTZUs: |
4733 | 0 | case AArch64::FCVTZUv2i32_shift: |
4734 | 0 | case AArch64::FCVTZUv4i32_shift: |
4735 | 0 | case AArch64::SCVTFs: |
4736 | 0 | case AArch64::SCVTFv2i32_shift: |
4737 | 0 | case AArch64::SCVTFv4i32_shift: |
4738 | 0 | case AArch64::SQRSHRNs: |
4739 | 0 | case AArch64::SQRSHRUNs: |
4740 | 0 | case AArch64::SQSHRNs: |
4741 | 0 | case AArch64::SQSHRUNs: |
4742 | 0 | case AArch64::SRSHRv2i32_shift: |
4743 | 0 | case AArch64::SRSHRv4i32_shift: |
4744 | 0 | case AArch64::SSHRv2i32_shift: |
4745 | 0 | case AArch64::SSHRv4i32_shift: |
4746 | 0 | case AArch64::UCVTFs: |
4747 | 0 | case AArch64::UCVTFv2i32_shift: |
4748 | 0 | case AArch64::UCVTFv4i32_shift: |
4749 | 0 | case AArch64::UQRSHRNs: |
4750 | 0 | case AArch64::UQSHRNs: |
4751 | 0 | case AArch64::URSHRv2i32_shift: |
4752 | 0 | case AArch64::URSHRv4i32_shift: |
4753 | 0 | case AArch64::USHRv2i32_shift: |
4754 | 0 | case AArch64::USHRv4i32_shift: { |
4755 | | // op: Rd |
4756 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4757 | 0 | Value |= op & UINT64_C(31); |
4758 | | // op: Rn |
4759 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4760 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4761 | | // op: imm |
4762 | 0 | op = getVecShiftR32OpValue(MI, 2, Fixups, STI); |
4763 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4764 | 0 | break; |
4765 | 0 | } |
4766 | 0 | case AArch64::RSHRNv2i32_shift: |
4767 | 0 | case AArch64::SHRNv2i32_shift: |
4768 | 0 | case AArch64::SQRSHRNv2i32_shift: |
4769 | 0 | case AArch64::SQRSHRUNv2i32_shift: |
4770 | 0 | case AArch64::SQSHRNv2i32_shift: |
4771 | 0 | case AArch64::SQSHRUNv2i32_shift: |
4772 | 0 | case AArch64::UQRSHRNv2i32_shift: |
4773 | 0 | case AArch64::UQSHRNv2i32_shift: { |
4774 | | // op: Rd |
4775 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4776 | 0 | Value |= op & UINT64_C(31); |
4777 | | // op: Rn |
4778 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4779 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4780 | | // op: imm |
4781 | 0 | op = getVecShiftR64OpValue(MI, 2, Fixups, STI); |
4782 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4783 | 0 | break; |
4784 | 0 | } |
4785 | 0 | case AArch64::FCVTZSd: |
4786 | 0 | case AArch64::FCVTZSv2i64_shift: |
4787 | 0 | case AArch64::FCVTZUd: |
4788 | 0 | case AArch64::FCVTZUv2i64_shift: |
4789 | 0 | case AArch64::SCVTFd: |
4790 | 0 | case AArch64::SCVTFv2i64_shift: |
4791 | 0 | case AArch64::SRSHRd: |
4792 | 0 | case AArch64::SRSHRv2i64_shift: |
4793 | 0 | case AArch64::SSHRd: |
4794 | 0 | case AArch64::SSHRv2i64_shift: |
4795 | 0 | case AArch64::UCVTFd: |
4796 | 0 | case AArch64::UCVTFv2i64_shift: |
4797 | 0 | case AArch64::URSHRd: |
4798 | 0 | case AArch64::URSHRv2i64_shift: |
4799 | 0 | case AArch64::USHRd: |
4800 | 0 | case AArch64::USHRv2i64_shift: { |
4801 | | // op: Rd |
4802 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4803 | 0 | Value |= op & UINT64_C(31); |
4804 | | // op: Rn |
4805 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4806 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4807 | | // op: imm |
4808 | 0 | op = getVecShiftR64OpValue(MI, 2, Fixups, STI); |
4809 | 0 | Value |= (op & UINT64_C(63)) << 16; |
4810 | 0 | break; |
4811 | 0 | } |
4812 | 0 | case AArch64::SQRSHRNb: |
4813 | 0 | case AArch64::SQRSHRUNb: |
4814 | 0 | case AArch64::SQSHRNb: |
4815 | 0 | case AArch64::SQSHRUNb: |
4816 | 0 | case AArch64::SRSHRv16i8_shift: |
4817 | 0 | case AArch64::SRSHRv8i8_shift: |
4818 | 0 | case AArch64::SSHRv16i8_shift: |
4819 | 0 | case AArch64::SSHRv8i8_shift: |
4820 | 0 | case AArch64::UQRSHRNb: |
4821 | 0 | case AArch64::UQSHRNb: |
4822 | 0 | case AArch64::URSHRv16i8_shift: |
4823 | 0 | case AArch64::URSHRv8i8_shift: |
4824 | 0 | case AArch64::USHRv16i8_shift: |
4825 | 0 | case AArch64::USHRv8i8_shift: { |
4826 | | // op: Rd |
4827 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4828 | 0 | Value |= op & UINT64_C(31); |
4829 | | // op: Rn |
4830 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4831 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4832 | | // op: imm |
4833 | 0 | op = getVecShiftR8OpValue(MI, 2, Fixups, STI); |
4834 | 0 | Value |= (op & UINT64_C(7)) << 16; |
4835 | 0 | break; |
4836 | 0 | } |
4837 | 0 | case AArch64::SBFMWri: |
4838 | 0 | case AArch64::UBFMWri: { |
4839 | | // op: Rd |
4840 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4841 | 0 | Value |= op & UINT64_C(31); |
4842 | | // op: Rn |
4843 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4844 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4845 | | // op: immr |
4846 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4847 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4848 | | // op: imms |
4849 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4850 | 0 | Value |= (op & UINT64_C(31)) << 10; |
4851 | 0 | break; |
4852 | 0 | } |
4853 | 0 | case AArch64::SBFMXri: |
4854 | 0 | case AArch64::UBFMXri: { |
4855 | | // op: Rd |
4856 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4857 | 0 | Value |= op & UINT64_C(31); |
4858 | | // op: Rn |
4859 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4860 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4861 | | // op: immr |
4862 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4863 | 0 | Value |= (op & UINT64_C(63)) << 16; |
4864 | | // op: imms |
4865 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4866 | 0 | Value |= (op & UINT64_C(63)) << 10; |
4867 | 0 | break; |
4868 | 0 | } |
4869 | 0 | case AArch64::FCVTZSSWDri: |
4870 | 0 | case AArch64::FCVTZSSWHri: |
4871 | 0 | case AArch64::FCVTZSSWSri: |
4872 | 0 | case AArch64::FCVTZS_IntSWDri: |
4873 | 0 | case AArch64::FCVTZS_IntSWHri: |
4874 | 0 | case AArch64::FCVTZS_IntSWSri: |
4875 | 0 | case AArch64::FCVTZUSWDri: |
4876 | 0 | case AArch64::FCVTZUSWHri: |
4877 | 0 | case AArch64::FCVTZUSWSri: |
4878 | 0 | case AArch64::FCVTZU_IntSWDri: |
4879 | 0 | case AArch64::FCVTZU_IntSWHri: |
4880 | 0 | case AArch64::FCVTZU_IntSWSri: |
4881 | 0 | case AArch64::SCVTFSWDri: |
4882 | 0 | case AArch64::SCVTFSWHri: |
4883 | 0 | case AArch64::SCVTFSWSri: |
4884 | 0 | case AArch64::UCVTFSWDri: |
4885 | 0 | case AArch64::UCVTFSWHri: |
4886 | 0 | case AArch64::UCVTFSWSri: { |
4887 | | // op: Rd |
4888 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4889 | 0 | Value |= op & UINT64_C(31); |
4890 | | // op: Rn |
4891 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4892 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4893 | | // op: scale |
4894 | 0 | op = getFixedPointScaleOpValue(MI, 2, Fixups, STI); |
4895 | 0 | Value |= (op & UINT64_C(31)) << 10; |
4896 | 0 | break; |
4897 | 0 | } |
4898 | 0 | case AArch64::FCVTZSSXDri: |
4899 | 0 | case AArch64::FCVTZSSXHri: |
4900 | 0 | case AArch64::FCVTZSSXSri: |
4901 | 0 | case AArch64::FCVTZS_IntSXDri: |
4902 | 0 | case AArch64::FCVTZS_IntSXHri: |
4903 | 0 | case AArch64::FCVTZS_IntSXSri: |
4904 | 0 | case AArch64::FCVTZUSXDri: |
4905 | 0 | case AArch64::FCVTZUSXHri: |
4906 | 0 | case AArch64::FCVTZUSXSri: |
4907 | 0 | case AArch64::FCVTZU_IntSXDri: |
4908 | 0 | case AArch64::FCVTZU_IntSXHri: |
4909 | 0 | case AArch64::FCVTZU_IntSXSri: |
4910 | 0 | case AArch64::SCVTFSXDri: |
4911 | 0 | case AArch64::SCVTFSXHri: |
4912 | 0 | case AArch64::SCVTFSXSri: |
4913 | 0 | case AArch64::UCVTFSXDri: |
4914 | 0 | case AArch64::UCVTFSXHri: |
4915 | 0 | case AArch64::UCVTFSXSri: { |
4916 | | // op: Rd |
4917 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4918 | 0 | Value |= op & UINT64_C(31); |
4919 | | // op: Rn |
4920 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4921 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4922 | | // op: scale |
4923 | 0 | op = getFixedPointScaleOpValue(MI, 2, Fixups, STI); |
4924 | 0 | Value |= (op & UINT64_C(63)) << 10; |
4925 | 0 | break; |
4926 | 0 | } |
4927 | 0 | case AArch64::BFMWri: { |
4928 | | // op: Rd |
4929 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4930 | 0 | Value |= op & UINT64_C(31); |
4931 | | // op: Rn |
4932 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4933 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4934 | | // op: immr |
4935 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4936 | 0 | Value |= (op & UINT64_C(31)) << 16; |
4937 | | // op: imms |
4938 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
4939 | 0 | Value |= (op & UINT64_C(31)) << 10; |
4940 | 0 | break; |
4941 | 0 | } |
4942 | 0 | case AArch64::BFMXri: { |
4943 | | // op: Rd |
4944 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4945 | 0 | Value |= op & UINT64_C(31); |
4946 | | // op: Rn |
4947 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4948 | 0 | Value |= (op & UINT64_C(31)) << 5; |
4949 | | // op: immr |
4950 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
4951 | 0 | Value |= (op & UINT64_C(63)) << 16; |
4952 | | // op: imms |
4953 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
4954 | 0 | Value |= (op & UINT64_C(63)) << 10; |
4955 | 0 | break; |
4956 | 0 | } |
4957 | 0 | case AArch64::FMOVDi: |
4958 | 0 | case AArch64::FMOVHi: |
4959 | 0 | case AArch64::FMOVSi: { |
4960 | | // op: Rd |
4961 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4962 | 0 | Value |= op & UINT64_C(31); |
4963 | | // op: imm |
4964 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
4965 | 0 | Value |= (op & UINT64_C(255)) << 13; |
4966 | 0 | break; |
4967 | 0 | } |
4968 | 0 | case AArch64::MOVNWi: |
4969 | 0 | case AArch64::MOVNXi: { |
4970 | | // op: Rd |
4971 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4972 | 0 | Value |= op & UINT64_C(31); |
4973 | | // op: imm |
4974 | 0 | op = getMoveWideImmOpValue(MI, 1, Fixups, STI); |
4975 | 0 | Value |= (op & UINT64_C(65535)) << 5; |
4976 | | // op: shift |
4977 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4978 | 0 | Value |= (op & UINT64_C(48)) << 17; |
4979 | 0 | break; |
4980 | 0 | } |
4981 | 0 | case AArch64::MOVZWi: |
4982 | 0 | case AArch64::MOVZXi: { |
4983 | | // op: Rd |
4984 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4985 | 0 | Value |= op & UINT64_C(31); |
4986 | | // op: imm |
4987 | 0 | op = getMoveWideImmOpValue(MI, 1, Fixups, STI); |
4988 | 0 | Value |= (op & UINT64_C(65535)) << 5; |
4989 | | // op: shift |
4990 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
4991 | 0 | Value |= (op & UINT64_C(48)) << 17; |
4992 | 0 | Value = fixMOVZ(MI, Value, STI); |
4993 | 0 | break; |
4994 | 0 | } |
4995 | 0 | case AArch64::MOVKWi: |
4996 | 0 | case AArch64::MOVKXi: { |
4997 | | // op: Rd |
4998 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
4999 | 0 | Value |= op & UINT64_C(31); |
5000 | | // op: imm |
5001 | 0 | op = getMoveWideImmOpValue(MI, 2, Fixups, STI); |
5002 | 0 | Value |= (op & UINT64_C(65535)) << 5; |
5003 | | // op: shift |
5004 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5005 | 0 | Value |= (op & UINT64_C(48)) << 17; |
5006 | 0 | break; |
5007 | 0 | } |
5008 | 0 | case AArch64::FMOVv2f32_ns: |
5009 | 0 | case AArch64::FMOVv2f64_ns: |
5010 | 0 | case AArch64::FMOVv4f16_ns: |
5011 | 0 | case AArch64::FMOVv4f32_ns: |
5012 | 0 | case AArch64::FMOVv8f16_ns: |
5013 | 0 | case AArch64::MOVID: |
5014 | 0 | case AArch64::MOVIv16b_ns: |
5015 | 0 | case AArch64::MOVIv2d_ns: |
5016 | 0 | case AArch64::MOVIv8b_ns: { |
5017 | | // op: Rd |
5018 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5019 | 0 | Value |= op & UINT64_C(31); |
5020 | | // op: imm8 |
5021 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5022 | 0 | Value |= (op & UINT64_C(224)) << 11; |
5023 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5024 | 0 | break; |
5025 | 0 | } |
5026 | 0 | case AArch64::MOVIv2s_msl: |
5027 | 0 | case AArch64::MOVIv4s_msl: |
5028 | 0 | case AArch64::MVNIv2s_msl: |
5029 | 0 | case AArch64::MVNIv4s_msl: { |
5030 | | // op: Rd |
5031 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5032 | 0 | Value |= op & UINT64_C(31); |
5033 | | // op: imm8 |
5034 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5035 | 0 | Value |= (op & UINT64_C(224)) << 11; |
5036 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5037 | | // op: shift |
5038 | 0 | op = getMoveVecShifterOpValue(MI, 2, Fixups, STI); |
5039 | 0 | Value |= (op & UINT64_C(1)) << 12; |
5040 | 0 | break; |
5041 | 0 | } |
5042 | 0 | case AArch64::MOVIv4i16: |
5043 | 0 | case AArch64::MOVIv8i16: |
5044 | 0 | case AArch64::MVNIv4i16: |
5045 | 0 | case AArch64::MVNIv8i16: { |
5046 | | // op: Rd |
5047 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5048 | 0 | Value |= op & UINT64_C(31); |
5049 | | // op: imm8 |
5050 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5051 | 0 | Value |= (op & UINT64_C(224)) << 11; |
5052 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5053 | | // op: shift |
5054 | 0 | op = getVecShifterOpValue(MI, 2, Fixups, STI); |
5055 | 0 | Value |= (op & UINT64_C(1)) << 13; |
5056 | 0 | break; |
5057 | 0 | } |
5058 | 0 | case AArch64::MOVIv2i32: |
5059 | 0 | case AArch64::MOVIv4i32: |
5060 | 0 | case AArch64::MVNIv2i32: |
5061 | 0 | case AArch64::MVNIv4i32: { |
5062 | | // op: Rd |
5063 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5064 | 0 | Value |= op & UINT64_C(31); |
5065 | | // op: imm8 |
5066 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5067 | 0 | Value |= (op & UINT64_C(224)) << 11; |
5068 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5069 | | // op: shift |
5070 | 0 | op = getVecShifterOpValue(MI, 2, Fixups, STI); |
5071 | 0 | Value |= (op & UINT64_C(3)) << 13; |
5072 | 0 | break; |
5073 | 0 | } |
5074 | 0 | case AArch64::AESDrr: |
5075 | 0 | case AArch64::AESErr: |
5076 | 0 | case AArch64::FCVTNv4i32: |
5077 | 0 | case AArch64::FCVTNv8i16: |
5078 | 0 | case AArch64::FCVTXNv4f32: |
5079 | 0 | case AArch64::SADALPv16i8_v8i16: |
5080 | 0 | case AArch64::SADALPv2i32_v1i64: |
5081 | 0 | case AArch64::SADALPv4i16_v2i32: |
5082 | 0 | case AArch64::SADALPv4i32_v2i64: |
5083 | 0 | case AArch64::SADALPv8i16_v4i32: |
5084 | 0 | case AArch64::SADALPv8i8_v4i16: |
5085 | 0 | case AArch64::SHA1SU1rr: |
5086 | 0 | case AArch64::SHA256SU0rr: |
5087 | 0 | case AArch64::SQXTNv16i8: |
5088 | 0 | case AArch64::SQXTNv4i32: |
5089 | 0 | case AArch64::SQXTNv8i16: |
5090 | 0 | case AArch64::SQXTUNv16i8: |
5091 | 0 | case AArch64::SQXTUNv4i32: |
5092 | 0 | case AArch64::SQXTUNv8i16: |
5093 | 0 | case AArch64::SUQADDv16i8: |
5094 | 0 | case AArch64::SUQADDv1i16: |
5095 | 0 | case AArch64::SUQADDv1i32: |
5096 | 0 | case AArch64::SUQADDv1i64: |
5097 | 0 | case AArch64::SUQADDv1i8: |
5098 | 0 | case AArch64::SUQADDv2i32: |
5099 | 0 | case AArch64::SUQADDv2i64: |
5100 | 0 | case AArch64::SUQADDv4i16: |
5101 | 0 | case AArch64::SUQADDv4i32: |
5102 | 0 | case AArch64::SUQADDv8i16: |
5103 | 0 | case AArch64::SUQADDv8i8: |
5104 | 0 | case AArch64::UADALPv16i8_v8i16: |
5105 | 0 | case AArch64::UADALPv2i32_v1i64: |
5106 | 0 | case AArch64::UADALPv4i16_v2i32: |
5107 | 0 | case AArch64::UADALPv4i32_v2i64: |
5108 | 0 | case AArch64::UADALPv8i16_v4i32: |
5109 | 0 | case AArch64::UADALPv8i8_v4i16: |
5110 | 0 | case AArch64::UQXTNv16i8: |
5111 | 0 | case AArch64::UQXTNv4i32: |
5112 | 0 | case AArch64::UQXTNv8i16: |
5113 | 0 | case AArch64::USQADDv16i8: |
5114 | 0 | case AArch64::USQADDv1i16: |
5115 | 0 | case AArch64::USQADDv1i32: |
5116 | 0 | case AArch64::USQADDv1i64: |
5117 | 0 | case AArch64::USQADDv1i8: |
5118 | 0 | case AArch64::USQADDv2i32: |
5119 | 0 | case AArch64::USQADDv2i64: |
5120 | 0 | case AArch64::USQADDv4i16: |
5121 | 0 | case AArch64::USQADDv4i32: |
5122 | 0 | case AArch64::USQADDv8i16: |
5123 | 0 | case AArch64::USQADDv8i8: |
5124 | 0 | case AArch64::XTNv16i8: |
5125 | 0 | case AArch64::XTNv4i32: |
5126 | 0 | case AArch64::XTNv8i16: { |
5127 | | // op: Rd |
5128 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5129 | 0 | Value |= op & UINT64_C(31); |
5130 | | // op: Rn |
5131 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5132 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5133 | 0 | break; |
5134 | 0 | } |
5135 | 0 | case AArch64::FMLAv1i16_indexed: |
5136 | 0 | case AArch64::FMLAv4i16_indexed: |
5137 | 0 | case AArch64::FMLAv8i16_indexed: |
5138 | 0 | case AArch64::FMLSv1i16_indexed: |
5139 | 0 | case AArch64::FMLSv4i16_indexed: |
5140 | 0 | case AArch64::FMLSv8i16_indexed: |
5141 | 0 | case AArch64::MLAv4i16_indexed: |
5142 | 0 | case AArch64::MLAv8i16_indexed: |
5143 | 0 | case AArch64::MLSv4i16_indexed: |
5144 | 0 | case AArch64::MLSv8i16_indexed: |
5145 | 0 | case AArch64::SMLALv4i16_indexed: |
5146 | 0 | case AArch64::SMLALv8i16_indexed: |
5147 | 0 | case AArch64::SMLSLv4i16_indexed: |
5148 | 0 | case AArch64::SMLSLv8i16_indexed: |
5149 | 0 | case AArch64::SQDMLALv1i32_indexed: |
5150 | 0 | case AArch64::SQDMLALv4i16_indexed: |
5151 | 0 | case AArch64::SQDMLALv8i16_indexed: |
5152 | 0 | case AArch64::SQDMLSLv1i32_indexed: |
5153 | 0 | case AArch64::SQDMLSLv4i16_indexed: |
5154 | 0 | case AArch64::SQDMLSLv8i16_indexed: |
5155 | 0 | case AArch64::SQRDMLAHi16_indexed: |
5156 | 0 | case AArch64::SQRDMLAHv4i16_indexed: |
5157 | 0 | case AArch64::SQRDMLAHv8i16_indexed: |
5158 | 0 | case AArch64::SQRDMLSHi16_indexed: |
5159 | 0 | case AArch64::SQRDMLSHv4i16_indexed: |
5160 | 0 | case AArch64::SQRDMLSHv8i16_indexed: |
5161 | 0 | case AArch64::UMLALv4i16_indexed: |
5162 | 0 | case AArch64::UMLALv8i16_indexed: |
5163 | 0 | case AArch64::UMLSLv4i16_indexed: |
5164 | 0 | case AArch64::UMLSLv8i16_indexed: { |
5165 | | // op: Rd |
5166 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5167 | 0 | Value |= op & UINT64_C(31); |
5168 | | // op: Rn |
5169 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5170 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5171 | | // op: Rm |
5172 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5173 | 0 | Value |= (op & UINT64_C(15)) << 16; |
5174 | | // op: idx |
5175 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
5176 | 0 | Value |= (op & UINT64_C(3)) << 20; |
5177 | 0 | Value |= (op & UINT64_C(4)) << 9; |
5178 | 0 | break; |
5179 | 0 | } |
5180 | 0 | case AArch64::ADDHNv2i64_v4i32: |
5181 | 0 | case AArch64::ADDHNv4i32_v8i16: |
5182 | 0 | case AArch64::ADDHNv8i16_v16i8: |
5183 | 0 | case AArch64::BITv16i8: |
5184 | 0 | case AArch64::BITv8i8: |
5185 | 0 | case AArch64::BSLv16i8: |
5186 | 0 | case AArch64::BSLv8i8: |
5187 | 0 | case AArch64::FMLAv2f32: |
5188 | 0 | case AArch64::FMLAv2f64: |
5189 | 0 | case AArch64::FMLAv4f16: |
5190 | 0 | case AArch64::FMLAv4f32: |
5191 | 0 | case AArch64::FMLAv8f16: |
5192 | 0 | case AArch64::FMLSv2f32: |
5193 | 0 | case AArch64::FMLSv2f64: |
5194 | 0 | case AArch64::FMLSv4f16: |
5195 | 0 | case AArch64::FMLSv4f32: |
5196 | 0 | case AArch64::FMLSv8f16: |
5197 | 0 | case AArch64::MLAv16i8: |
5198 | 0 | case AArch64::MLAv2i32: |
5199 | 0 | case AArch64::MLAv4i16: |
5200 | 0 | case AArch64::MLAv4i32: |
5201 | 0 | case AArch64::MLAv8i16: |
5202 | 0 | case AArch64::MLAv8i8: |
5203 | 0 | case AArch64::MLSv16i8: |
5204 | 0 | case AArch64::MLSv2i32: |
5205 | 0 | case AArch64::MLSv4i16: |
5206 | 0 | case AArch64::MLSv4i32: |
5207 | 0 | case AArch64::MLSv8i16: |
5208 | 0 | case AArch64::MLSv8i8: |
5209 | 0 | case AArch64::RADDHNv2i64_v4i32: |
5210 | 0 | case AArch64::RADDHNv4i32_v8i16: |
5211 | 0 | case AArch64::RADDHNv8i16_v16i8: |
5212 | 0 | case AArch64::RSUBHNv2i64_v4i32: |
5213 | 0 | case AArch64::RSUBHNv4i32_v8i16: |
5214 | 0 | case AArch64::RSUBHNv8i16_v16i8: |
5215 | 0 | case AArch64::SABALv16i8_v8i16: |
5216 | 0 | case AArch64::SABALv2i32_v2i64: |
5217 | 0 | case AArch64::SABALv4i16_v4i32: |
5218 | 0 | case AArch64::SABALv4i32_v2i64: |
5219 | 0 | case AArch64::SABALv8i16_v4i32: |
5220 | 0 | case AArch64::SABALv8i8_v8i16: |
5221 | 0 | case AArch64::SABAv16i8: |
5222 | 0 | case AArch64::SABAv2i32: |
5223 | 0 | case AArch64::SABAv4i16: |
5224 | 0 | case AArch64::SABAv4i32: |
5225 | 0 | case AArch64::SABAv8i16: |
5226 | 0 | case AArch64::SABAv8i8: |
5227 | 0 | case AArch64::SHA1Crrr: |
5228 | 0 | case AArch64::SHA1Mrrr: |
5229 | 0 | case AArch64::SHA1Prrr: |
5230 | 0 | case AArch64::SHA1SU0rrr: |
5231 | 0 | case AArch64::SHA256H2rrr: |
5232 | 0 | case AArch64::SHA256Hrrr: |
5233 | 0 | case AArch64::SHA256SU1rrr: |
5234 | 0 | case AArch64::SMLALv16i8_v8i16: |
5235 | 0 | case AArch64::SMLALv2i32_v2i64: |
5236 | 0 | case AArch64::SMLALv4i16_v4i32: |
5237 | 0 | case AArch64::SMLALv4i32_v2i64: |
5238 | 0 | case AArch64::SMLALv8i16_v4i32: |
5239 | 0 | case AArch64::SMLALv8i8_v8i16: |
5240 | 0 | case AArch64::SMLSLv16i8_v8i16: |
5241 | 0 | case AArch64::SMLSLv2i32_v2i64: |
5242 | 0 | case AArch64::SMLSLv4i16_v4i32: |
5243 | 0 | case AArch64::SMLSLv4i32_v2i64: |
5244 | 0 | case AArch64::SMLSLv8i16_v4i32: |
5245 | 0 | case AArch64::SMLSLv8i8_v8i16: |
5246 | 0 | case AArch64::SQDMLALi16: |
5247 | 0 | case AArch64::SQDMLALi32: |
5248 | 0 | case AArch64::SQDMLALv2i32_v2i64: |
5249 | 0 | case AArch64::SQDMLALv4i16_v4i32: |
5250 | 0 | case AArch64::SQDMLALv4i32_v2i64: |
5251 | 0 | case AArch64::SQDMLALv8i16_v4i32: |
5252 | 0 | case AArch64::SQDMLSLi16: |
5253 | 0 | case AArch64::SQDMLSLi32: |
5254 | 0 | case AArch64::SQDMLSLv2i32_v2i64: |
5255 | 0 | case AArch64::SQDMLSLv4i16_v4i32: |
5256 | 0 | case AArch64::SQDMLSLv4i32_v2i64: |
5257 | 0 | case AArch64::SQDMLSLv8i16_v4i32: |
5258 | 0 | case AArch64::SQRDMLAHv1i16: |
5259 | 0 | case AArch64::SQRDMLAHv1i32: |
5260 | 0 | case AArch64::SQRDMLAHv2i32: |
5261 | 0 | case AArch64::SQRDMLAHv4i16: |
5262 | 0 | case AArch64::SQRDMLAHv4i32: |
5263 | 0 | case AArch64::SQRDMLAHv8i16: |
5264 | 0 | case AArch64::SQRDMLSHv1i16: |
5265 | 0 | case AArch64::SQRDMLSHv1i32: |
5266 | 0 | case AArch64::SQRDMLSHv2i32: |
5267 | 0 | case AArch64::SQRDMLSHv4i16: |
5268 | 0 | case AArch64::SQRDMLSHv4i32: |
5269 | 0 | case AArch64::SQRDMLSHv8i16: |
5270 | 0 | case AArch64::SUBHNv2i64_v4i32: |
5271 | 0 | case AArch64::SUBHNv4i32_v8i16: |
5272 | 0 | case AArch64::SUBHNv8i16_v16i8: |
5273 | 0 | case AArch64::UABALv16i8_v8i16: |
5274 | 0 | case AArch64::UABALv2i32_v2i64: |
5275 | 0 | case AArch64::UABALv4i16_v4i32: |
5276 | 0 | case AArch64::UABALv4i32_v2i64: |
5277 | 0 | case AArch64::UABALv8i16_v4i32: |
5278 | 0 | case AArch64::UABALv8i8_v8i16: |
5279 | 0 | case AArch64::UABAv16i8: |
5280 | 0 | case AArch64::UABAv2i32: |
5281 | 0 | case AArch64::UABAv4i16: |
5282 | 0 | case AArch64::UABAv4i32: |
5283 | 0 | case AArch64::UABAv8i16: |
5284 | 0 | case AArch64::UABAv8i8: |
5285 | 0 | case AArch64::UMLALv16i8_v8i16: |
5286 | 0 | case AArch64::UMLALv2i32_v2i64: |
5287 | 0 | case AArch64::UMLALv4i16_v4i32: |
5288 | 0 | case AArch64::UMLALv4i32_v2i64: |
5289 | 0 | case AArch64::UMLALv8i16_v4i32: |
5290 | 0 | case AArch64::UMLALv8i8_v8i16: |
5291 | 0 | case AArch64::UMLSLv16i8_v8i16: |
5292 | 0 | case AArch64::UMLSLv2i32_v2i64: |
5293 | 0 | case AArch64::UMLSLv4i16_v4i32: |
5294 | 0 | case AArch64::UMLSLv4i32_v2i64: |
5295 | 0 | case AArch64::UMLSLv8i16_v4i32: |
5296 | 0 | case AArch64::UMLSLv8i8_v8i16: { |
5297 | | // op: Rd |
5298 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5299 | 0 | Value |= op & UINT64_C(31); |
5300 | | // op: Rn |
5301 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5302 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5303 | | // op: Rm |
5304 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5305 | 0 | Value |= (op & UINT64_C(31)) << 16; |
5306 | 0 | break; |
5307 | 0 | } |
5308 | 0 | case AArch64::FMLAv1i64_indexed: |
5309 | 0 | case AArch64::FMLAv2i64_indexed: |
5310 | 0 | case AArch64::FMLSv1i64_indexed: |
5311 | 0 | case AArch64::FMLSv2i64_indexed: { |
5312 | | // op: Rd |
5313 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5314 | 0 | Value |= op & UINT64_C(31); |
5315 | | // op: Rn |
5316 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5317 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5318 | | // op: Rm |
5319 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5320 | 0 | Value |= (op & UINT64_C(31)) << 16; |
5321 | | // op: idx |
5322 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
5323 | 0 | Value |= (op & UINT64_C(1)) << 11; |
5324 | 0 | break; |
5325 | 0 | } |
5326 | 0 | case AArch64::FMLAv1i32_indexed: |
5327 | 0 | case AArch64::FMLAv2i32_indexed: |
5328 | 0 | case AArch64::FMLAv4i32_indexed: |
5329 | 0 | case AArch64::FMLSv1i32_indexed: |
5330 | 0 | case AArch64::FMLSv2i32_indexed: |
5331 | 0 | case AArch64::FMLSv4i32_indexed: |
5332 | 0 | case AArch64::MLAv2i32_indexed: |
5333 | 0 | case AArch64::MLAv4i32_indexed: |
5334 | 0 | case AArch64::MLSv2i32_indexed: |
5335 | 0 | case AArch64::MLSv4i32_indexed: |
5336 | 0 | case AArch64::SMLALv2i32_indexed: |
5337 | 0 | case AArch64::SMLALv4i32_indexed: |
5338 | 0 | case AArch64::SMLSLv2i32_indexed: |
5339 | 0 | case AArch64::SMLSLv4i32_indexed: |
5340 | 0 | case AArch64::SQDMLALv1i64_indexed: |
5341 | 0 | case AArch64::SQDMLALv2i32_indexed: |
5342 | 0 | case AArch64::SQDMLALv4i32_indexed: |
5343 | 0 | case AArch64::SQDMLSLv1i64_indexed: |
5344 | 0 | case AArch64::SQDMLSLv2i32_indexed: |
5345 | 0 | case AArch64::SQDMLSLv4i32_indexed: |
5346 | 0 | case AArch64::SQRDMLAHi32_indexed: |
5347 | 0 | case AArch64::SQRDMLAHv2i32_indexed: |
5348 | 0 | case AArch64::SQRDMLAHv4i32_indexed: |
5349 | 0 | case AArch64::SQRDMLSHi32_indexed: |
5350 | 0 | case AArch64::SQRDMLSHv2i32_indexed: |
5351 | 0 | case AArch64::SQRDMLSHv4i32_indexed: |
5352 | 0 | case AArch64::UMLALv2i32_indexed: |
5353 | 0 | case AArch64::UMLALv4i32_indexed: |
5354 | 0 | case AArch64::UMLSLv2i32_indexed: |
5355 | 0 | case AArch64::UMLSLv4i32_indexed: { |
5356 | | // op: Rd |
5357 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5358 | 0 | Value |= op & UINT64_C(31); |
5359 | | // op: Rn |
5360 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5361 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5362 | | // op: Rm |
5363 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5364 | 0 | Value |= (op & UINT64_C(31)) << 16; |
5365 | | // op: idx |
5366 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
5367 | 0 | Value |= (op & UINT64_C(1)) << 21; |
5368 | 0 | Value |= (op & UINT64_C(2)) << 10; |
5369 | 0 | break; |
5370 | 0 | } |
5371 | 0 | case AArch64::SLIv4i16_shift: |
5372 | 0 | case AArch64::SLIv8i16_shift: { |
5373 | | // op: Rd |
5374 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5375 | 0 | Value |= op & UINT64_C(31); |
5376 | | // op: Rn |
5377 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5378 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5379 | | // op: imm |
5380 | 0 | op = getVecShiftL16OpValue(MI, 3, Fixups, STI); |
5381 | 0 | Value |= (op & UINT64_C(15)) << 16; |
5382 | 0 | break; |
5383 | 0 | } |
5384 | 0 | case AArch64::SLIv2i32_shift: |
5385 | 0 | case AArch64::SLIv4i32_shift: { |
5386 | | // op: Rd |
5387 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5388 | 0 | Value |= op & UINT64_C(31); |
5389 | | // op: Rn |
5390 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5391 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5392 | | // op: imm |
5393 | 0 | op = getVecShiftL32OpValue(MI, 3, Fixups, STI); |
5394 | 0 | Value |= (op & UINT64_C(31)) << 16; |
5395 | 0 | break; |
5396 | 0 | } |
5397 | 0 | case AArch64::SLId: |
5398 | 0 | case AArch64::SLIv2i64_shift: { |
5399 | | // op: Rd |
5400 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5401 | 0 | Value |= op & UINT64_C(31); |
5402 | | // op: Rn |
5403 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5404 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5405 | | // op: imm |
5406 | 0 | op = getVecShiftL64OpValue(MI, 3, Fixups, STI); |
5407 | 0 | Value |= (op & UINT64_C(63)) << 16; |
5408 | 0 | break; |
5409 | 0 | } |
5410 | 0 | case AArch64::SLIv16i8_shift: |
5411 | 0 | case AArch64::SLIv8i8_shift: { |
5412 | | // op: Rd |
5413 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5414 | 0 | Value |= op & UINT64_C(31); |
5415 | | // op: Rn |
5416 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5417 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5418 | | // op: imm |
5419 | 0 | op = getVecShiftL8OpValue(MI, 3, Fixups, STI); |
5420 | 0 | Value |= (op & UINT64_C(7)) << 16; |
5421 | 0 | break; |
5422 | 0 | } |
5423 | 0 | case AArch64::SRIv4i16_shift: |
5424 | 0 | case AArch64::SRIv8i16_shift: |
5425 | 0 | case AArch64::SRSRAv4i16_shift: |
5426 | 0 | case AArch64::SRSRAv8i16_shift: |
5427 | 0 | case AArch64::SSRAv4i16_shift: |
5428 | 0 | case AArch64::SSRAv8i16_shift: |
5429 | 0 | case AArch64::URSRAv4i16_shift: |
5430 | 0 | case AArch64::URSRAv8i16_shift: |
5431 | 0 | case AArch64::USRAv4i16_shift: |
5432 | 0 | case AArch64::USRAv8i16_shift: { |
5433 | | // op: Rd |
5434 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5435 | 0 | Value |= op & UINT64_C(31); |
5436 | | // op: Rn |
5437 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5438 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5439 | | // op: imm |
5440 | 0 | op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
5441 | 0 | Value |= (op & UINT64_C(15)) << 16; |
5442 | 0 | break; |
5443 | 0 | } |
5444 | 0 | case AArch64::RSHRNv16i8_shift: |
5445 | 0 | case AArch64::SHRNv16i8_shift: |
5446 | 0 | case AArch64::SQRSHRNv16i8_shift: |
5447 | 0 | case AArch64::SQRSHRUNv16i8_shift: |
5448 | 0 | case AArch64::SQSHRNv16i8_shift: |
5449 | 0 | case AArch64::SQSHRUNv16i8_shift: |
5450 | 0 | case AArch64::UQRSHRNv16i8_shift: |
5451 | 0 | case AArch64::UQSHRNv16i8_shift: { |
5452 | | // op: Rd |
5453 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5454 | 0 | Value |= op & UINT64_C(31); |
5455 | | // op: Rn |
5456 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5457 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5458 | | // op: imm |
5459 | 0 | op = getVecShiftR16OpValue(MI, 3, Fixups, STI); |
5460 | 0 | Value |= (op & UINT64_C(7)) << 16; |
5461 | 0 | break; |
5462 | 0 | } |
5463 | 0 | case AArch64::RSHRNv8i16_shift: |
5464 | 0 | case AArch64::SHRNv8i16_shift: |
5465 | 0 | case AArch64::SQRSHRNv8i16_shift: |
5466 | 0 | case AArch64::SQRSHRUNv8i16_shift: |
5467 | 0 | case AArch64::SQSHRNv8i16_shift: |
5468 | 0 | case AArch64::SQSHRUNv8i16_shift: |
5469 | 0 | case AArch64::UQRSHRNv8i16_shift: |
5470 | 0 | case AArch64::UQSHRNv8i16_shift: { |
5471 | | // op: Rd |
5472 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5473 | 0 | Value |= op & UINT64_C(31); |
5474 | | // op: Rn |
5475 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5476 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5477 | | // op: imm |
5478 | 0 | op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
5479 | 0 | Value |= (op & UINT64_C(15)) << 16; |
5480 | 0 | break; |
5481 | 0 | } |
5482 | 0 | case AArch64::SRIv2i32_shift: |
5483 | 0 | case AArch64::SRIv4i32_shift: |
5484 | 0 | case AArch64::SRSRAv2i32_shift: |
5485 | 0 | case AArch64::SRSRAv4i32_shift: |
5486 | 0 | case AArch64::SSRAv2i32_shift: |
5487 | 0 | case AArch64::SSRAv4i32_shift: |
5488 | 0 | case AArch64::URSRAv2i32_shift: |
5489 | 0 | case AArch64::URSRAv4i32_shift: |
5490 | 0 | case AArch64::USRAv2i32_shift: |
5491 | 0 | case AArch64::USRAv4i32_shift: { |
5492 | | // op: Rd |
5493 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5494 | 0 | Value |= op & UINT64_C(31); |
5495 | | // op: Rn |
5496 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5497 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5498 | | // op: imm |
5499 | 0 | op = getVecShiftR32OpValue(MI, 3, Fixups, STI); |
5500 | 0 | Value |= (op & UINT64_C(31)) << 16; |
5501 | 0 | break; |
5502 | 0 | } |
5503 | 0 | case AArch64::RSHRNv4i32_shift: |
5504 | 0 | case AArch64::SHRNv4i32_shift: |
5505 | 0 | case AArch64::SQRSHRNv4i32_shift: |
5506 | 0 | case AArch64::SQRSHRUNv4i32_shift: |
5507 | 0 | case AArch64::SQSHRNv4i32_shift: |
5508 | 0 | case AArch64::SQSHRUNv4i32_shift: |
5509 | 0 | case AArch64::UQRSHRNv4i32_shift: |
5510 | 0 | case AArch64::UQSHRNv4i32_shift: { |
5511 | | // op: Rd |
5512 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5513 | 0 | Value |= op & UINT64_C(31); |
5514 | | // op: Rn |
5515 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5516 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5517 | | // op: imm |
5518 | 0 | op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
5519 | 0 | Value |= (op & UINT64_C(31)) << 16; |
5520 | 0 | break; |
5521 | 0 | } |
5522 | 0 | case AArch64::SRId: |
5523 | 0 | case AArch64::SRIv2i64_shift: |
5524 | 0 | case AArch64::SRSRAd: |
5525 | 0 | case AArch64::SRSRAv2i64_shift: |
5526 | 0 | case AArch64::SSRAd: |
5527 | 0 | case AArch64::SSRAv2i64_shift: |
5528 | 0 | case AArch64::URSRAd: |
5529 | 0 | case AArch64::URSRAv2i64_shift: |
5530 | 0 | case AArch64::USRAd: |
5531 | 0 | case AArch64::USRAv2i64_shift: { |
5532 | | // op: Rd |
5533 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5534 | 0 | Value |= op & UINT64_C(31); |
5535 | | // op: Rn |
5536 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5537 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5538 | | // op: imm |
5539 | 0 | op = getVecShiftR64OpValue(MI, 3, Fixups, STI); |
5540 | 0 | Value |= (op & UINT64_C(63)) << 16; |
5541 | 0 | break; |
5542 | 0 | } |
5543 | 0 | case AArch64::SRIv16i8_shift: |
5544 | 0 | case AArch64::SRIv8i8_shift: |
5545 | 0 | case AArch64::SRSRAv16i8_shift: |
5546 | 0 | case AArch64::SRSRAv8i8_shift: |
5547 | 0 | case AArch64::SSRAv16i8_shift: |
5548 | 0 | case AArch64::SSRAv8i8_shift: |
5549 | 0 | case AArch64::URSRAv16i8_shift: |
5550 | 0 | case AArch64::URSRAv8i8_shift: |
5551 | 0 | case AArch64::USRAv16i8_shift: |
5552 | 0 | case AArch64::USRAv8i8_shift: { |
5553 | | // op: Rd |
5554 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5555 | 0 | Value |= op & UINT64_C(31); |
5556 | | // op: Rn |
5557 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5558 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5559 | | // op: imm |
5560 | 0 | op = getVecShiftR8OpValue(MI, 3, Fixups, STI); |
5561 | 0 | Value |= (op & UINT64_C(7)) << 16; |
5562 | 0 | break; |
5563 | 0 | } |
5564 | 0 | case AArch64::INSvi64gpr: { |
5565 | | // op: Rd |
5566 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5567 | 0 | Value |= op & UINT64_C(31); |
5568 | | // op: Rn |
5569 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5570 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5571 | | // op: idx |
5572 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5573 | 0 | Value |= (op & UINT64_C(1)) << 20; |
5574 | 0 | break; |
5575 | 0 | } |
5576 | 0 | case AArch64::INSvi64lane: { |
5577 | | // op: Rd |
5578 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5579 | 0 | Value |= op & UINT64_C(31); |
5580 | | // op: Rn |
5581 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5582 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5583 | | // op: idx |
5584 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5585 | 0 | Value |= (op & UINT64_C(1)) << 20; |
5586 | | // op: idx2 |
5587 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
5588 | 0 | Value |= (op & UINT64_C(1)) << 14; |
5589 | 0 | break; |
5590 | 0 | } |
5591 | 0 | case AArch64::INSvi8gpr: { |
5592 | | // op: Rd |
5593 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5594 | 0 | Value |= op & UINT64_C(31); |
5595 | | // op: Rn |
5596 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5597 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5598 | | // op: idx |
5599 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5600 | 0 | Value |= (op & UINT64_C(15)) << 17; |
5601 | 0 | break; |
5602 | 0 | } |
5603 | 0 | case AArch64::INSvi8lane: { |
5604 | | // op: Rd |
5605 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5606 | 0 | Value |= op & UINT64_C(31); |
5607 | | // op: Rn |
5608 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5609 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5610 | | // op: idx |
5611 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5612 | 0 | Value |= (op & UINT64_C(15)) << 17; |
5613 | | // op: idx2 |
5614 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
5615 | 0 | Value |= (op & UINT64_C(15)) << 11; |
5616 | 0 | break; |
5617 | 0 | } |
5618 | 0 | case AArch64::INSvi32gpr: { |
5619 | | // op: Rd |
5620 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5621 | 0 | Value |= op & UINT64_C(31); |
5622 | | // op: Rn |
5623 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5624 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5625 | | // op: idx |
5626 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5627 | 0 | Value |= (op & UINT64_C(3)) << 19; |
5628 | 0 | break; |
5629 | 0 | } |
5630 | 0 | case AArch64::INSvi32lane: { |
5631 | | // op: Rd |
5632 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5633 | 0 | Value |= op & UINT64_C(31); |
5634 | | // op: Rn |
5635 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5636 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5637 | | // op: idx |
5638 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5639 | 0 | Value |= (op & UINT64_C(3)) << 19; |
5640 | | // op: idx2 |
5641 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
5642 | 0 | Value |= (op & UINT64_C(3)) << 13; |
5643 | 0 | break; |
5644 | 0 | } |
5645 | 0 | case AArch64::INSvi16gpr: { |
5646 | | // op: Rd |
5647 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5648 | 0 | Value |= op & UINT64_C(31); |
5649 | | // op: Rn |
5650 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5651 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5652 | | // op: idx |
5653 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5654 | 0 | Value |= (op & UINT64_C(7)) << 18; |
5655 | 0 | break; |
5656 | 0 | } |
5657 | 0 | case AArch64::INSvi16lane: { |
5658 | | // op: Rd |
5659 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5660 | 0 | Value |= op & UINT64_C(31); |
5661 | | // op: Rn |
5662 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5663 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5664 | | // op: idx |
5665 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5666 | 0 | Value |= (op & UINT64_C(7)) << 18; |
5667 | | // op: idx2 |
5668 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
5669 | 0 | Value |= (op & UINT64_C(7)) << 12; |
5670 | 0 | break; |
5671 | 0 | } |
5672 | 0 | case AArch64::BICv4i16: |
5673 | 0 | case AArch64::BICv8i16: |
5674 | 0 | case AArch64::ORRv4i16: |
5675 | 0 | case AArch64::ORRv8i16: { |
5676 | | // op: Rd |
5677 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5678 | 0 | Value |= op & UINT64_C(31); |
5679 | | // op: imm8 |
5680 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5681 | 0 | Value |= (op & UINT64_C(224)) << 11; |
5682 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5683 | | // op: shift |
5684 | 0 | op = getVecShifterOpValue(MI, 3, Fixups, STI); |
5685 | 0 | Value |= (op & UINT64_C(1)) << 13; |
5686 | 0 | break; |
5687 | 0 | } |
5688 | 0 | case AArch64::BICv2i32: |
5689 | 0 | case AArch64::BICv4i32: |
5690 | 0 | case AArch64::ORRv2i32: |
5691 | 0 | case AArch64::ORRv4i32: { |
5692 | | // op: Rd |
5693 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5694 | 0 | Value |= op & UINT64_C(31); |
5695 | | // op: imm8 |
5696 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5697 | 0 | Value |= (op & UINT64_C(224)) << 11; |
5698 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5699 | | // op: shift |
5700 | 0 | op = getVecShifterOpValue(MI, 3, Fixups, STI); |
5701 | 0 | Value |= (op & UINT64_C(3)) << 13; |
5702 | 0 | break; |
5703 | 0 | } |
5704 | 0 | case AArch64::FCMPDrr: |
5705 | 0 | case AArch64::FCMPEDrr: |
5706 | 0 | case AArch64::FCMPEHrr: |
5707 | 0 | case AArch64::FCMPESrr: |
5708 | 0 | case AArch64::FCMPHrr: |
5709 | 0 | case AArch64::FCMPSrr: { |
5710 | | // op: Rm |
5711 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5712 | 0 | Value |= (op & UINT64_C(31)) << 16; |
5713 | | // op: Rn |
5714 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5715 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5716 | 0 | break; |
5717 | 0 | } |
5718 | 0 | case AArch64::BLR: |
5719 | 0 | case AArch64::BR: |
5720 | 0 | case AArch64::RET: { |
5721 | | // op: Rn |
5722 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5723 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5724 | 0 | break; |
5725 | 0 | } |
5726 | 0 | case AArch64::CCMNWr: |
5727 | 0 | case AArch64::CCMNXr: |
5728 | 0 | case AArch64::CCMPWr: |
5729 | 0 | case AArch64::CCMPXr: |
5730 | 0 | case AArch64::FCCMPDrr: |
5731 | 0 | case AArch64::FCCMPEDrr: |
5732 | 0 | case AArch64::FCCMPEHrr: |
5733 | 0 | case AArch64::FCCMPESrr: |
5734 | 0 | case AArch64::FCCMPHrr: |
5735 | 0 | case AArch64::FCCMPSrr: { |
5736 | | // op: Rn |
5737 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5738 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5739 | | // op: Rm |
5740 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5741 | 0 | Value |= (op & UINT64_C(31)) << 16; |
5742 | | // op: nzcv |
5743 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5744 | 0 | Value |= op & UINT64_C(15); |
5745 | | // op: cond |
5746 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5747 | 0 | Value |= (op & UINT64_C(15)) << 12; |
5748 | 0 | break; |
5749 | 0 | } |
5750 | 0 | case AArch64::CCMNWi: |
5751 | 0 | case AArch64::CCMNXi: |
5752 | 0 | case AArch64::CCMPWi: |
5753 | 0 | case AArch64::CCMPXi: { |
5754 | | // op: Rn |
5755 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5756 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5757 | | // op: imm |
5758 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5759 | 0 | Value |= (op & UINT64_C(31)) << 16; |
5760 | | // op: nzcv |
5761 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5762 | 0 | Value |= op & UINT64_C(15); |
5763 | | // op: cond |
5764 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5765 | 0 | Value |= (op & UINT64_C(15)) << 12; |
5766 | 0 | break; |
5767 | 0 | } |
5768 | 0 | case AArch64::FCMPDri: |
5769 | 0 | case AArch64::FCMPEDri: |
5770 | 0 | case AArch64::FCMPEHri: |
5771 | 0 | case AArch64::FCMPESri: |
5772 | 0 | case AArch64::FCMPHri: |
5773 | 0 | case AArch64::FCMPSri: { |
5774 | | // op: Rn |
5775 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5776 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5777 | 0 | Value = fixOneOperandFPComparison(MI, Value, STI); |
5778 | 0 | break; |
5779 | 0 | } |
5780 | 0 | case AArch64::LDADDALb: |
5781 | 0 | case AArch64::LDADDALd: |
5782 | 0 | case AArch64::LDADDALh: |
5783 | 0 | case AArch64::LDADDALs: |
5784 | 0 | case AArch64::LDADDAb: |
5785 | 0 | case AArch64::LDADDAd: |
5786 | 0 | case AArch64::LDADDAh: |
5787 | 0 | case AArch64::LDADDAs: |
5788 | 0 | case AArch64::LDADDLb: |
5789 | 0 | case AArch64::LDADDLd: |
5790 | 0 | case AArch64::LDADDLh: |
5791 | 0 | case AArch64::LDADDLs: |
5792 | 0 | case AArch64::LDADDb: |
5793 | 0 | case AArch64::LDADDd: |
5794 | 0 | case AArch64::LDADDh: |
5795 | 0 | case AArch64::LDADDs: |
5796 | 0 | case AArch64::LDCLRALb: |
5797 | 0 | case AArch64::LDCLRALd: |
5798 | 0 | case AArch64::LDCLRALh: |
5799 | 0 | case AArch64::LDCLRALs: |
5800 | 0 | case AArch64::LDCLRAb: |
5801 | 0 | case AArch64::LDCLRAd: |
5802 | 0 | case AArch64::LDCLRAh: |
5803 | 0 | case AArch64::LDCLRAs: |
5804 | 0 | case AArch64::LDCLRLb: |
5805 | 0 | case AArch64::LDCLRLd: |
5806 | 0 | case AArch64::LDCLRLh: |
5807 | 0 | case AArch64::LDCLRLs: |
5808 | 0 | case AArch64::LDCLRb: |
5809 | 0 | case AArch64::LDCLRd: |
5810 | 0 | case AArch64::LDCLRh: |
5811 | 0 | case AArch64::LDCLRs: |
5812 | 0 | case AArch64::LDEORALb: |
5813 | 0 | case AArch64::LDEORALd: |
5814 | 0 | case AArch64::LDEORALh: |
5815 | 0 | case AArch64::LDEORALs: |
5816 | 0 | case AArch64::LDEORAb: |
5817 | 0 | case AArch64::LDEORAd: |
5818 | 0 | case AArch64::LDEORAh: |
5819 | 0 | case AArch64::LDEORAs: |
5820 | 0 | case AArch64::LDEORLb: |
5821 | 0 | case AArch64::LDEORLd: |
5822 | 0 | case AArch64::LDEORLh: |
5823 | 0 | case AArch64::LDEORLs: |
5824 | 0 | case AArch64::LDEORb: |
5825 | 0 | case AArch64::LDEORd: |
5826 | 0 | case AArch64::LDEORh: |
5827 | 0 | case AArch64::LDEORs: |
5828 | 0 | case AArch64::LDSETALb: |
5829 | 0 | case AArch64::LDSETALd: |
5830 | 0 | case AArch64::LDSETALh: |
5831 | 0 | case AArch64::LDSETALs: |
5832 | 0 | case AArch64::LDSETAb: |
5833 | 0 | case AArch64::LDSETAd: |
5834 | 0 | case AArch64::LDSETAh: |
5835 | 0 | case AArch64::LDSETAs: |
5836 | 0 | case AArch64::LDSETLb: |
5837 | 0 | case AArch64::LDSETLd: |
5838 | 0 | case AArch64::LDSETLh: |
5839 | 0 | case AArch64::LDSETLs: |
5840 | 0 | case AArch64::LDSETb: |
5841 | 0 | case AArch64::LDSETd: |
5842 | 0 | case AArch64::LDSETh: |
5843 | 0 | case AArch64::LDSETs: |
5844 | 0 | case AArch64::LDSMAXALb: |
5845 | 0 | case AArch64::LDSMAXALd: |
5846 | 0 | case AArch64::LDSMAXALh: |
5847 | 0 | case AArch64::LDSMAXALs: |
5848 | 0 | case AArch64::LDSMAXAb: |
5849 | 0 | case AArch64::LDSMAXAd: |
5850 | 0 | case AArch64::LDSMAXAh: |
5851 | 0 | case AArch64::LDSMAXAs: |
5852 | 0 | case AArch64::LDSMAXLb: |
5853 | 0 | case AArch64::LDSMAXLd: |
5854 | 0 | case AArch64::LDSMAXLh: |
5855 | 0 | case AArch64::LDSMAXLs: |
5856 | 0 | case AArch64::LDSMAXb: |
5857 | 0 | case AArch64::LDSMAXd: |
5858 | 0 | case AArch64::LDSMAXh: |
5859 | 0 | case AArch64::LDSMAXs: |
5860 | 0 | case AArch64::LDSMINALb: |
5861 | 0 | case AArch64::LDSMINALd: |
5862 | 0 | case AArch64::LDSMINALh: |
5863 | 0 | case AArch64::LDSMINALs: |
5864 | 0 | case AArch64::LDSMINAb: |
5865 | 0 | case AArch64::LDSMINAd: |
5866 | 0 | case AArch64::LDSMINAh: |
5867 | 0 | case AArch64::LDSMINAs: |
5868 | 0 | case AArch64::LDSMINLb: |
5869 | 0 | case AArch64::LDSMINLd: |
5870 | 0 | case AArch64::LDSMINLh: |
5871 | 0 | case AArch64::LDSMINLs: |
5872 | 0 | case AArch64::LDSMINb: |
5873 | 0 | case AArch64::LDSMINd: |
5874 | 0 | case AArch64::LDSMINh: |
5875 | 0 | case AArch64::LDSMINs: |
5876 | 0 | case AArch64::LDUMAXALb: |
5877 | 0 | case AArch64::LDUMAXALd: |
5878 | 0 | case AArch64::LDUMAXALh: |
5879 | 0 | case AArch64::LDUMAXALs: |
5880 | 0 | case AArch64::LDUMAXAb: |
5881 | 0 | case AArch64::LDUMAXAd: |
5882 | 0 | case AArch64::LDUMAXAh: |
5883 | 0 | case AArch64::LDUMAXAs: |
5884 | 0 | case AArch64::LDUMAXLb: |
5885 | 0 | case AArch64::LDUMAXLd: |
5886 | 0 | case AArch64::LDUMAXLh: |
5887 | 0 | case AArch64::LDUMAXLs: |
5888 | 0 | case AArch64::LDUMAXb: |
5889 | 0 | case AArch64::LDUMAXd: |
5890 | 0 | case AArch64::LDUMAXh: |
5891 | 0 | case AArch64::LDUMAXs: |
5892 | 0 | case AArch64::LDUMINALb: |
5893 | 0 | case AArch64::LDUMINALd: |
5894 | 0 | case AArch64::LDUMINALh: |
5895 | 0 | case AArch64::LDUMINALs: |
5896 | 0 | case AArch64::LDUMINAb: |
5897 | 0 | case AArch64::LDUMINAd: |
5898 | 0 | case AArch64::LDUMINAh: |
5899 | 0 | case AArch64::LDUMINAs: |
5900 | 0 | case AArch64::LDUMINLb: |
5901 | 0 | case AArch64::LDUMINLd: |
5902 | 0 | case AArch64::LDUMINLh: |
5903 | 0 | case AArch64::LDUMINLs: |
5904 | 0 | case AArch64::LDUMINb: |
5905 | 0 | case AArch64::LDUMINd: |
5906 | 0 | case AArch64::LDUMINh: |
5907 | 0 | case AArch64::LDUMINs: |
5908 | 0 | case AArch64::SWPALb: |
5909 | 0 | case AArch64::SWPALd: |
5910 | 0 | case AArch64::SWPALh: |
5911 | 0 | case AArch64::SWPALs: |
5912 | 0 | case AArch64::SWPAb: |
5913 | 0 | case AArch64::SWPAd: |
5914 | 0 | case AArch64::SWPAh: |
5915 | 0 | case AArch64::SWPAs: |
5916 | 0 | case AArch64::SWPLb: |
5917 | 0 | case AArch64::SWPLd: |
5918 | 0 | case AArch64::SWPLh: |
5919 | 0 | case AArch64::SWPLs: |
5920 | 0 | case AArch64::SWPb: |
5921 | 0 | case AArch64::SWPd: |
5922 | 0 | case AArch64::SWPh: |
5923 | 0 | case AArch64::SWPs: { |
5924 | | // op: Rs |
5925 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5926 | 0 | Value |= (op & UINT64_C(31)) << 16; |
5927 | | // op: Rn |
5928 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5929 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5930 | | // op: Rt |
5931 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
5932 | 0 | Value |= op & UINT64_C(31); |
5933 | 0 | break; |
5934 | 0 | } |
5935 | 0 | case AArch64::CASALb: |
5936 | 0 | case AArch64::CASALd: |
5937 | 0 | case AArch64::CASALh: |
5938 | 0 | case AArch64::CASALs: |
5939 | 0 | case AArch64::CASAb: |
5940 | 0 | case AArch64::CASAd: |
5941 | 0 | case AArch64::CASAh: |
5942 | 0 | case AArch64::CASAs: |
5943 | 0 | case AArch64::CASLb: |
5944 | 0 | case AArch64::CASLd: |
5945 | 0 | case AArch64::CASLh: |
5946 | 0 | case AArch64::CASLs: |
5947 | 0 | case AArch64::CASPALd: |
5948 | 0 | case AArch64::CASPALs: |
5949 | 0 | case AArch64::CASPAd: |
5950 | 0 | case AArch64::CASPAs: |
5951 | 0 | case AArch64::CASPLd: |
5952 | 0 | case AArch64::CASPLs: |
5953 | 0 | case AArch64::CASPd: |
5954 | 0 | case AArch64::CASPs: |
5955 | 0 | case AArch64::CASb: |
5956 | 0 | case AArch64::CASd: |
5957 | 0 | case AArch64::CASh: |
5958 | 0 | case AArch64::CASs: { |
5959 | | // op: Rs |
5960 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
5961 | 0 | Value |= (op & UINT64_C(31)) << 16; |
5962 | | // op: Rn |
5963 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
5964 | 0 | Value |= (op & UINT64_C(31)) << 5; |
5965 | | // op: Rt |
5966 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
5967 | 0 | Value |= op & UINT64_C(31); |
5968 | 0 | break; |
5969 | 0 | } |
5970 | 0 | case AArch64::LDRBBroW: |
5971 | 0 | case AArch64::LDRBBroX: |
5972 | 0 | case AArch64::LDRBroW: |
5973 | 0 | case AArch64::LDRBroX: |
5974 | 0 | case AArch64::LDRDroW: |
5975 | 0 | case AArch64::LDRDroX: |
5976 | 0 | case AArch64::LDRHHroW: |
5977 | 0 | case AArch64::LDRHHroX: |
5978 | 0 | case AArch64::LDRHroW: |
5979 | 0 | case AArch64::LDRHroX: |
5980 | 0 | case AArch64::LDRQroW: |
5981 | 0 | case AArch64::LDRQroX: |
5982 | 0 | case AArch64::LDRSBWroW: |
5983 | 0 | case AArch64::LDRSBWroX: |
5984 | 0 | case AArch64::LDRSBXroW: |
5985 | 0 | case AArch64::LDRSBXroX: |
5986 | 0 | case AArch64::LDRSHWroW: |
5987 | 0 | case AArch64::LDRSHWroX: |
5988 | 0 | case AArch64::LDRSHXroW: |
5989 | 0 | case AArch64::LDRSHXroX: |
5990 | 0 | case AArch64::LDRSWroW: |
5991 | 0 | case AArch64::LDRSWroX: |
5992 | 0 | case AArch64::LDRSroW: |
5993 | 0 | case AArch64::LDRSroX: |
5994 | 0 | case AArch64::LDRWroW: |
5995 | 0 | case AArch64::LDRWroX: |
5996 | 0 | case AArch64::LDRXroW: |
5997 | 0 | case AArch64::LDRXroX: |
5998 | 0 | case AArch64::PRFMroW: |
5999 | 0 | case AArch64::PRFMroX: |
6000 | 0 | case AArch64::STRBBroW: |
6001 | 0 | case AArch64::STRBBroX: |
6002 | 0 | case AArch64::STRBroW: |
6003 | 0 | case AArch64::STRBroX: |
6004 | 0 | case AArch64::STRDroW: |
6005 | 0 | case AArch64::STRDroX: |
6006 | 0 | case AArch64::STRHHroW: |
6007 | 0 | case AArch64::STRHHroX: |
6008 | 0 | case AArch64::STRHroW: |
6009 | 0 | case AArch64::STRHroX: |
6010 | 0 | case AArch64::STRQroW: |
6011 | 0 | case AArch64::STRQroX: |
6012 | 0 | case AArch64::STRSroW: |
6013 | 0 | case AArch64::STRSroX: |
6014 | 0 | case AArch64::STRWroW: |
6015 | 0 | case AArch64::STRWroX: |
6016 | 0 | case AArch64::STRXroW: |
6017 | 0 | case AArch64::STRXroX: { |
6018 | | // op: Rt |
6019 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6020 | 0 | Value |= op & UINT64_C(31); |
6021 | | // op: Rn |
6022 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6023 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6024 | | // op: Rm |
6025 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6026 | 0 | Value |= (op & UINT64_C(31)) << 16; |
6027 | | // op: extend |
6028 | 0 | op = getMemExtendOpValue(MI, 3, Fixups, STI); |
6029 | 0 | Value |= (op & UINT64_C(2)) << 14; |
6030 | 0 | Value |= (op & UINT64_C(1)) << 12; |
6031 | 0 | break; |
6032 | 0 | } |
6033 | 0 | case AArch64::LDRQui: |
6034 | 0 | case AArch64::STRQui: { |
6035 | | // op: Rt |
6036 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6037 | 0 | Value |= op & UINT64_C(31); |
6038 | | // op: Rn |
6039 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6040 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6041 | | // op: offset |
6042 | 0 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale16>(MI, 2, Fixups, STI); |
6043 | 0 | Value |= (op & UINT64_C(4095)) << 10; |
6044 | 0 | break; |
6045 | 0 | } |
6046 | 0 | case AArch64::LDRBBui: |
6047 | 0 | case AArch64::LDRBui: |
6048 | 0 | case AArch64::LDRSBWui: |
6049 | 0 | case AArch64::LDRSBXui: |
6050 | 0 | case AArch64::STRBBui: |
6051 | 0 | case AArch64::STRBui: { |
6052 | | // op: Rt |
6053 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6054 | 0 | Value |= op & UINT64_C(31); |
6055 | | // op: Rn |
6056 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6057 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6058 | | // op: offset |
6059 | 0 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale1>(MI, 2, Fixups, STI); |
6060 | 0 | Value |= (op & UINT64_C(4095)) << 10; |
6061 | 0 | break; |
6062 | 0 | } |
6063 | 0 | case AArch64::LDRHHui: |
6064 | 0 | case AArch64::LDRHui: |
6065 | 0 | case AArch64::LDRSHWui: |
6066 | 0 | case AArch64::LDRSHXui: |
6067 | 0 | case AArch64::STRHHui: |
6068 | 0 | case AArch64::STRHui: { |
6069 | | // op: Rt |
6070 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6071 | 0 | Value |= op & UINT64_C(31); |
6072 | | // op: Rn |
6073 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6074 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6075 | | // op: offset |
6076 | 0 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale2>(MI, 2, Fixups, STI); |
6077 | 0 | Value |= (op & UINT64_C(4095)) << 10; |
6078 | 0 | break; |
6079 | 0 | } |
6080 | 0 | case AArch64::LDRSWui: |
6081 | 0 | case AArch64::LDRSui: |
6082 | 0 | case AArch64::LDRWui: |
6083 | 0 | case AArch64::STRSui: |
6084 | 0 | case AArch64::STRWui: { |
6085 | | // op: Rt |
6086 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6087 | 0 | Value |= op & UINT64_C(31); |
6088 | | // op: Rn |
6089 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6090 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6091 | | // op: offset |
6092 | 0 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale4>(MI, 2, Fixups, STI); |
6093 | 0 | Value |= (op & UINT64_C(4095)) << 10; |
6094 | 0 | break; |
6095 | 0 | } |
6096 | 0 | case AArch64::LDRDui: |
6097 | 0 | case AArch64::LDRXui: |
6098 | 0 | case AArch64::PRFMui: |
6099 | 0 | case AArch64::STRDui: |
6100 | 0 | case AArch64::STRXui: { |
6101 | | // op: Rt |
6102 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6103 | 0 | Value |= op & UINT64_C(31); |
6104 | | // op: Rn |
6105 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6106 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6107 | | // op: offset |
6108 | 0 | op = getLdStUImm12OpValue<AArch64::fixup_aarch64_ldst_imm12_scale8>(MI, 2, Fixups, STI); |
6109 | 0 | Value |= (op & UINT64_C(4095)) << 10; |
6110 | 0 | break; |
6111 | 0 | } |
6112 | 0 | case AArch64::LDTRBi: |
6113 | 0 | case AArch64::LDTRHi: |
6114 | 0 | case AArch64::LDTRSBWi: |
6115 | 0 | case AArch64::LDTRSBXi: |
6116 | 0 | case AArch64::LDTRSHWi: |
6117 | 0 | case AArch64::LDTRSHXi: |
6118 | 0 | case AArch64::LDTRSWi: |
6119 | 0 | case AArch64::LDTRWi: |
6120 | 0 | case AArch64::LDTRXi: |
6121 | 0 | case AArch64::LDURBBi: |
6122 | 0 | case AArch64::LDURBi: |
6123 | 0 | case AArch64::LDURDi: |
6124 | 0 | case AArch64::LDURHHi: |
6125 | 0 | case AArch64::LDURHi: |
6126 | 0 | case AArch64::LDURQi: |
6127 | 0 | case AArch64::LDURSBWi: |
6128 | 0 | case AArch64::LDURSBXi: |
6129 | 0 | case AArch64::LDURSHWi: |
6130 | 0 | case AArch64::LDURSHXi: |
6131 | 0 | case AArch64::LDURSWi: |
6132 | 0 | case AArch64::LDURSi: |
6133 | 0 | case AArch64::LDURWi: |
6134 | 0 | case AArch64::LDURXi: |
6135 | 0 | case AArch64::PRFUMi: |
6136 | 0 | case AArch64::STTRBi: |
6137 | 0 | case AArch64::STTRHi: |
6138 | 0 | case AArch64::STTRWi: |
6139 | 0 | case AArch64::STTRXi: |
6140 | 0 | case AArch64::STURBBi: |
6141 | 0 | case AArch64::STURBi: |
6142 | 0 | case AArch64::STURDi: |
6143 | 0 | case AArch64::STURHHi: |
6144 | 0 | case AArch64::STURHi: |
6145 | 0 | case AArch64::STURQi: |
6146 | 0 | case AArch64::STURSi: |
6147 | 0 | case AArch64::STURWi: |
6148 | 0 | case AArch64::STURXi: { |
6149 | | // op: Rt |
6150 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6151 | 0 | Value |= op & UINT64_C(31); |
6152 | | // op: Rn |
6153 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6154 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6155 | | // op: offset |
6156 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6157 | 0 | Value |= (op & UINT64_C(511)) << 12; |
6158 | 0 | break; |
6159 | 0 | } |
6160 | 0 | case AArch64::LDARB: |
6161 | 0 | case AArch64::LDARH: |
6162 | 0 | case AArch64::LDARW: |
6163 | 0 | case AArch64::LDARX: |
6164 | 0 | case AArch64::LDAXRB: |
6165 | 0 | case AArch64::LDAXRH: |
6166 | 0 | case AArch64::LDAXRW: |
6167 | 0 | case AArch64::LDAXRX: |
6168 | 0 | case AArch64::LDLARB: |
6169 | 0 | case AArch64::LDLARH: |
6170 | 0 | case AArch64::LDLARW: |
6171 | 0 | case AArch64::LDLARX: |
6172 | 0 | case AArch64::LDXRB: |
6173 | 0 | case AArch64::LDXRH: |
6174 | 0 | case AArch64::LDXRW: |
6175 | 0 | case AArch64::LDXRX: |
6176 | 0 | case AArch64::STLLRB: |
6177 | 0 | case AArch64::STLLRH: |
6178 | 0 | case AArch64::STLLRW: |
6179 | 0 | case AArch64::STLLRX: |
6180 | 0 | case AArch64::STLRB: |
6181 | 0 | case AArch64::STLRH: |
6182 | 0 | case AArch64::STLRW: |
6183 | 0 | case AArch64::STLRX: { |
6184 | | // op: Rt |
6185 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6186 | 0 | Value |= op & UINT64_C(31); |
6187 | | // op: Rn |
6188 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6189 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6190 | 0 | Value = fixLoadStoreExclusive<0,0>(MI, Value, STI); |
6191 | 0 | break; |
6192 | 0 | } |
6193 | 0 | case AArch64::LDNPDi: |
6194 | 0 | case AArch64::LDNPQi: |
6195 | 0 | case AArch64::LDNPSi: |
6196 | 0 | case AArch64::LDNPWi: |
6197 | 0 | case AArch64::LDNPXi: |
6198 | 0 | case AArch64::LDPDi: |
6199 | 0 | case AArch64::LDPQi: |
6200 | 0 | case AArch64::LDPSWi: |
6201 | 0 | case AArch64::LDPSi: |
6202 | 0 | case AArch64::LDPWi: |
6203 | 0 | case AArch64::LDPXi: |
6204 | 0 | case AArch64::STNPDi: |
6205 | 0 | case AArch64::STNPQi: |
6206 | 0 | case AArch64::STNPSi: |
6207 | 0 | case AArch64::STNPWi: |
6208 | 0 | case AArch64::STNPXi: |
6209 | 0 | case AArch64::STPDi: |
6210 | 0 | case AArch64::STPQi: |
6211 | 0 | case AArch64::STPSi: |
6212 | 0 | case AArch64::STPWi: |
6213 | 0 | case AArch64::STPXi: { |
6214 | | // op: Rt |
6215 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6216 | 0 | Value |= op & UINT64_C(31); |
6217 | | // op: Rt2 |
6218 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6219 | 0 | Value |= (op & UINT64_C(31)) << 10; |
6220 | | // op: Rn |
6221 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6222 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6223 | | // op: offset |
6224 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6225 | 0 | Value |= (op & UINT64_C(127)) << 15; |
6226 | 0 | break; |
6227 | 0 | } |
6228 | 0 | case AArch64::LDAXPW: |
6229 | 0 | case AArch64::LDAXPX: |
6230 | 0 | case AArch64::LDXPW: |
6231 | 0 | case AArch64::LDXPX: { |
6232 | | // op: Rt |
6233 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6234 | 0 | Value |= op & UINT64_C(31); |
6235 | | // op: Rt2 |
6236 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6237 | 0 | Value |= (op & UINT64_C(31)) << 10; |
6238 | | // op: Rn |
6239 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6240 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6241 | 0 | Value = fixLoadStoreExclusive<0,1>(MI, Value, STI); |
6242 | 0 | break; |
6243 | 0 | } |
6244 | 0 | case AArch64::TBNZW: |
6245 | 0 | case AArch64::TBNZX: |
6246 | 0 | case AArch64::TBZW: |
6247 | 0 | case AArch64::TBZX: { |
6248 | | // op: Rt |
6249 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6250 | 0 | Value |= op & UINT64_C(31); |
6251 | | // op: bit_off |
6252 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6253 | 0 | Value |= (op & UINT64_C(31)) << 19; |
6254 | | // op: target |
6255 | 0 | op = getTestBranchTargetOpValue(MI, 2, Fixups, STI); |
6256 | 0 | Value |= (op & UINT64_C(16383)) << 5; |
6257 | 0 | break; |
6258 | 0 | } |
6259 | 0 | case AArch64::LDRDl: |
6260 | 0 | case AArch64::LDRQl: |
6261 | 0 | case AArch64::LDRSWl: |
6262 | 0 | case AArch64::LDRSl: |
6263 | 1 | case AArch64::LDRWl: |
6264 | 1 | case AArch64::LDRXl: |
6265 | 1 | case AArch64::PRFMl: { |
6266 | | // op: Rt |
6267 | 1 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6268 | 1 | Value |= op & UINT64_C(31); |
6269 | | // op: label |
6270 | 1 | op = getLoadLiteralOpValue(MI, 1, Fixups, STI); |
6271 | 1 | Value |= (op & UINT64_C(524287)) << 5; |
6272 | 1 | break; |
6273 | 1 | } |
6274 | 0 | case AArch64::SYSLxt: { |
6275 | | // op: Rt |
6276 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6277 | 0 | Value |= op & UINT64_C(31); |
6278 | | // op: op1 |
6279 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6280 | 0 | Value |= (op & UINT64_C(7)) << 16; |
6281 | | // op: Cn |
6282 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6283 | 0 | Value |= (op & UINT64_C(15)) << 12; |
6284 | | // op: Cm |
6285 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6286 | 0 | Value |= (op & UINT64_C(15)) << 8; |
6287 | | // op: op2 |
6288 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6289 | 0 | Value |= (op & UINT64_C(7)) << 5; |
6290 | 0 | break; |
6291 | 1 | } |
6292 | 0 | case AArch64::MRS: { |
6293 | | // op: Rt |
6294 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6295 | 0 | Value |= op & UINT64_C(31); |
6296 | | // op: systemreg |
6297 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6298 | 0 | Value |= (op & UINT64_C(65535)) << 5; |
6299 | 0 | break; |
6300 | 1 | } |
6301 | 0 | case AArch64::CBNZW: |
6302 | 0 | case AArch64::CBNZX: |
6303 | 0 | case AArch64::CBZW: |
6304 | 0 | case AArch64::CBZX: { |
6305 | | // op: Rt |
6306 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6307 | 0 | Value |= op & UINT64_C(31); |
6308 | | // op: target |
6309 | 0 | op = getCondBranchTargetOpValue(MI, 1, Fixups, STI); |
6310 | 0 | Value |= (op & UINT64_C(524287)) << 5; |
6311 | 0 | break; |
6312 | 0 | } |
6313 | 0 | case AArch64::LDRBBpost: |
6314 | 0 | case AArch64::LDRBBpre: |
6315 | 0 | case AArch64::LDRBpost: |
6316 | 0 | case AArch64::LDRBpre: |
6317 | 0 | case AArch64::LDRDpost: |
6318 | 0 | case AArch64::LDRDpre: |
6319 | 0 | case AArch64::LDRHHpost: |
6320 | 0 | case AArch64::LDRHHpre: |
6321 | 0 | case AArch64::LDRHpost: |
6322 | 0 | case AArch64::LDRHpre: |
6323 | 0 | case AArch64::LDRQpost: |
6324 | 0 | case AArch64::LDRQpre: |
6325 | 0 | case AArch64::LDRSBWpost: |
6326 | 0 | case AArch64::LDRSBWpre: |
6327 | 0 | case AArch64::LDRSBXpost: |
6328 | 0 | case AArch64::LDRSBXpre: |
6329 | 0 | case AArch64::LDRSHWpost: |
6330 | 0 | case AArch64::LDRSHWpre: |
6331 | 0 | case AArch64::LDRSHXpost: |
6332 | 0 | case AArch64::LDRSHXpre: |
6333 | 0 | case AArch64::LDRSWpost: |
6334 | 0 | case AArch64::LDRSWpre: |
6335 | 0 | case AArch64::LDRSpost: |
6336 | 0 | case AArch64::LDRSpre: |
6337 | 0 | case AArch64::LDRWpost: |
6338 | 0 | case AArch64::LDRWpre: |
6339 | 0 | case AArch64::LDRXpost: |
6340 | 0 | case AArch64::LDRXpre: |
6341 | 0 | case AArch64::STRBBpost: |
6342 | 0 | case AArch64::STRBBpre: |
6343 | 0 | case AArch64::STRBpost: |
6344 | 0 | case AArch64::STRBpre: |
6345 | 0 | case AArch64::STRDpost: |
6346 | 0 | case AArch64::STRDpre: |
6347 | 0 | case AArch64::STRHHpost: |
6348 | 0 | case AArch64::STRHHpre: |
6349 | 0 | case AArch64::STRHpost: |
6350 | 0 | case AArch64::STRHpre: |
6351 | 0 | case AArch64::STRQpost: |
6352 | 0 | case AArch64::STRQpre: |
6353 | 0 | case AArch64::STRSpost: |
6354 | 0 | case AArch64::STRSpre: |
6355 | 0 | case AArch64::STRWpost: |
6356 | 0 | case AArch64::STRWpre: |
6357 | 0 | case AArch64::STRXpost: |
6358 | 0 | case AArch64::STRXpre: { |
6359 | | // op: Rt |
6360 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6361 | 0 | Value |= op & UINT64_C(31); |
6362 | | // op: Rn |
6363 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6364 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6365 | | // op: offset |
6366 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6367 | 0 | Value |= (op & UINT64_C(511)) << 12; |
6368 | 0 | break; |
6369 | 0 | } |
6370 | 0 | case AArch64::LDPDpost: |
6371 | 0 | case AArch64::LDPDpre: |
6372 | 0 | case AArch64::LDPQpost: |
6373 | 0 | case AArch64::LDPQpre: |
6374 | 0 | case AArch64::LDPSWpost: |
6375 | 0 | case AArch64::LDPSWpre: |
6376 | 0 | case AArch64::LDPSpost: |
6377 | 0 | case AArch64::LDPSpre: |
6378 | 0 | case AArch64::LDPWpost: |
6379 | 0 | case AArch64::LDPWpre: |
6380 | 0 | case AArch64::LDPXpost: |
6381 | 0 | case AArch64::LDPXpre: |
6382 | 0 | case AArch64::STPDpost: |
6383 | 0 | case AArch64::STPDpre: |
6384 | 0 | case AArch64::STPQpost: |
6385 | 0 | case AArch64::STPQpre: |
6386 | 0 | case AArch64::STPSpost: |
6387 | 0 | case AArch64::STPSpre: |
6388 | 0 | case AArch64::STPWpost: |
6389 | 0 | case AArch64::STPWpre: |
6390 | 0 | case AArch64::STPXpost: |
6391 | 0 | case AArch64::STPXpre: { |
6392 | | // op: Rt |
6393 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6394 | 0 | Value |= op & UINT64_C(31); |
6395 | | // op: Rt2 |
6396 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6397 | 0 | Value |= (op & UINT64_C(31)) << 10; |
6398 | | // op: Rn |
6399 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6400 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6401 | | // op: offset |
6402 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6403 | 0 | Value |= (op & UINT64_C(127)) << 15; |
6404 | 0 | break; |
6405 | 0 | } |
6406 | 0 | case AArch64::MSR: { |
6407 | | // op: Rt |
6408 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6409 | 0 | Value |= op & UINT64_C(31); |
6410 | | // op: systemreg |
6411 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6412 | 0 | Value |= (op & UINT64_C(65535)) << 5; |
6413 | 0 | break; |
6414 | 0 | } |
6415 | 0 | case AArch64::SYSxt: { |
6416 | | // op: Rt |
6417 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6418 | 0 | Value |= op & UINT64_C(31); |
6419 | | // op: op1 |
6420 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6421 | 0 | Value |= (op & UINT64_C(7)) << 16; |
6422 | | // op: Cn |
6423 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6424 | 0 | Value |= (op & UINT64_C(15)) << 12; |
6425 | | // op: Cm |
6426 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6427 | 0 | Value |= (op & UINT64_C(15)) << 8; |
6428 | | // op: op2 |
6429 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6430 | 0 | Value |= (op & UINT64_C(7)) << 5; |
6431 | 0 | break; |
6432 | 0 | } |
6433 | 0 | case AArch64::TBLv16i8Four: |
6434 | 0 | case AArch64::TBLv16i8One: |
6435 | 0 | case AArch64::TBLv16i8Three: |
6436 | 0 | case AArch64::TBLv16i8Two: |
6437 | 0 | case AArch64::TBLv8i8Four: |
6438 | 0 | case AArch64::TBLv8i8One: |
6439 | 0 | case AArch64::TBLv8i8Three: |
6440 | 0 | case AArch64::TBLv8i8Two: { |
6441 | | // op: Vd |
6442 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6443 | 0 | Value |= op & UINT64_C(31); |
6444 | | // op: Vn |
6445 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6446 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6447 | | // op: Vm |
6448 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6449 | 0 | Value |= (op & UINT64_C(31)) << 16; |
6450 | 0 | break; |
6451 | 0 | } |
6452 | 0 | case AArch64::TBXv16i8Four: |
6453 | 0 | case AArch64::TBXv16i8One: |
6454 | 0 | case AArch64::TBXv16i8Three: |
6455 | 0 | case AArch64::TBXv16i8Two: |
6456 | 0 | case AArch64::TBXv8i8Four: |
6457 | 0 | case AArch64::TBXv8i8One: |
6458 | 0 | case AArch64::TBXv8i8Three: |
6459 | 0 | case AArch64::TBXv8i8Two: { |
6460 | | // op: Vd |
6461 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6462 | 0 | Value |= op & UINT64_C(31); |
6463 | | // op: Vn |
6464 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6465 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6466 | | // op: Vm |
6467 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6468 | 0 | Value |= (op & UINT64_C(31)) << 16; |
6469 | 0 | break; |
6470 | 0 | } |
6471 | 0 | case AArch64::LD1Fourv16b: |
6472 | 0 | case AArch64::LD1Fourv1d: |
6473 | 0 | case AArch64::LD1Fourv2d: |
6474 | 0 | case AArch64::LD1Fourv2s: |
6475 | 0 | case AArch64::LD1Fourv4h: |
6476 | 0 | case AArch64::LD1Fourv4s: |
6477 | 0 | case AArch64::LD1Fourv8b: |
6478 | 0 | case AArch64::LD1Fourv8h: |
6479 | 0 | case AArch64::LD1Onev16b: |
6480 | 0 | case AArch64::LD1Onev1d: |
6481 | 0 | case AArch64::LD1Onev2d: |
6482 | 0 | case AArch64::LD1Onev2s: |
6483 | 0 | case AArch64::LD1Onev4h: |
6484 | 0 | case AArch64::LD1Onev4s: |
6485 | 0 | case AArch64::LD1Onev8b: |
6486 | 0 | case AArch64::LD1Onev8h: |
6487 | 0 | case AArch64::LD1Rv16b: |
6488 | 0 | case AArch64::LD1Rv1d: |
6489 | 0 | case AArch64::LD1Rv2d: |
6490 | 0 | case AArch64::LD1Rv2s: |
6491 | 0 | case AArch64::LD1Rv4h: |
6492 | 0 | case AArch64::LD1Rv4s: |
6493 | 0 | case AArch64::LD1Rv8b: |
6494 | 0 | case AArch64::LD1Rv8h: |
6495 | 0 | case AArch64::LD1Threev16b: |
6496 | 0 | case AArch64::LD1Threev1d: |
6497 | 0 | case AArch64::LD1Threev2d: |
6498 | 0 | case AArch64::LD1Threev2s: |
6499 | 0 | case AArch64::LD1Threev4h: |
6500 | 0 | case AArch64::LD1Threev4s: |
6501 | 0 | case AArch64::LD1Threev8b: |
6502 | 0 | case AArch64::LD1Threev8h: |
6503 | 0 | case AArch64::LD1Twov16b: |
6504 | 0 | case AArch64::LD1Twov1d: |
6505 | 0 | case AArch64::LD1Twov2d: |
6506 | 0 | case AArch64::LD1Twov2s: |
6507 | 0 | case AArch64::LD1Twov4h: |
6508 | 0 | case AArch64::LD1Twov4s: |
6509 | 0 | case AArch64::LD1Twov8b: |
6510 | 0 | case AArch64::LD1Twov8h: |
6511 | 0 | case AArch64::LD2Rv16b: |
6512 | 0 | case AArch64::LD2Rv1d: |
6513 | 0 | case AArch64::LD2Rv2d: |
6514 | 0 | case AArch64::LD2Rv2s: |
6515 | 0 | case AArch64::LD2Rv4h: |
6516 | 0 | case AArch64::LD2Rv4s: |
6517 | 0 | case AArch64::LD2Rv8b: |
6518 | 0 | case AArch64::LD2Rv8h: |
6519 | 0 | case AArch64::LD2Twov16b: |
6520 | 0 | case AArch64::LD2Twov2d: |
6521 | 0 | case AArch64::LD2Twov2s: |
6522 | 0 | case AArch64::LD2Twov4h: |
6523 | 0 | case AArch64::LD2Twov4s: |
6524 | 0 | case AArch64::LD2Twov8b: |
6525 | 0 | case AArch64::LD2Twov8h: |
6526 | 0 | case AArch64::LD3Rv16b: |
6527 | 0 | case AArch64::LD3Rv1d: |
6528 | 0 | case AArch64::LD3Rv2d: |
6529 | 0 | case AArch64::LD3Rv2s: |
6530 | 0 | case AArch64::LD3Rv4h: |
6531 | 0 | case AArch64::LD3Rv4s: |
6532 | 0 | case AArch64::LD3Rv8b: |
6533 | 0 | case AArch64::LD3Rv8h: |
6534 | 0 | case AArch64::LD3Threev16b: |
6535 | 0 | case AArch64::LD3Threev2d: |
6536 | 0 | case AArch64::LD3Threev2s: |
6537 | 0 | case AArch64::LD3Threev4h: |
6538 | 0 | case AArch64::LD3Threev4s: |
6539 | 0 | case AArch64::LD3Threev8b: |
6540 | 0 | case AArch64::LD3Threev8h: |
6541 | 0 | case AArch64::LD4Fourv16b: |
6542 | 0 | case AArch64::LD4Fourv2d: |
6543 | 0 | case AArch64::LD4Fourv2s: |
6544 | 0 | case AArch64::LD4Fourv4h: |
6545 | 0 | case AArch64::LD4Fourv4s: |
6546 | 0 | case AArch64::LD4Fourv8b: |
6547 | 0 | case AArch64::LD4Fourv8h: |
6548 | 0 | case AArch64::LD4Rv16b: |
6549 | 0 | case AArch64::LD4Rv1d: |
6550 | 0 | case AArch64::LD4Rv2d: |
6551 | 0 | case AArch64::LD4Rv2s: |
6552 | 0 | case AArch64::LD4Rv4h: |
6553 | 0 | case AArch64::LD4Rv4s: |
6554 | 0 | case AArch64::LD4Rv8b: |
6555 | 0 | case AArch64::LD4Rv8h: |
6556 | 0 | case AArch64::ST1Fourv16b: |
6557 | 0 | case AArch64::ST1Fourv1d: |
6558 | 0 | case AArch64::ST1Fourv2d: |
6559 | 0 | case AArch64::ST1Fourv2s: |
6560 | 0 | case AArch64::ST1Fourv4h: |
6561 | 0 | case AArch64::ST1Fourv4s: |
6562 | 0 | case AArch64::ST1Fourv8b: |
6563 | 0 | case AArch64::ST1Fourv8h: |
6564 | 0 | case AArch64::ST1Onev16b: |
6565 | 0 | case AArch64::ST1Onev1d: |
6566 | 0 | case AArch64::ST1Onev2d: |
6567 | 0 | case AArch64::ST1Onev2s: |
6568 | 0 | case AArch64::ST1Onev4h: |
6569 | 0 | case AArch64::ST1Onev4s: |
6570 | 0 | case AArch64::ST1Onev8b: |
6571 | 0 | case AArch64::ST1Onev8h: |
6572 | 0 | case AArch64::ST1Threev16b: |
6573 | 0 | case AArch64::ST1Threev1d: |
6574 | 0 | case AArch64::ST1Threev2d: |
6575 | 0 | case AArch64::ST1Threev2s: |
6576 | 0 | case AArch64::ST1Threev4h: |
6577 | 0 | case AArch64::ST1Threev4s: |
6578 | 0 | case AArch64::ST1Threev8b: |
6579 | 0 | case AArch64::ST1Threev8h: |
6580 | 0 | case AArch64::ST1Twov16b: |
6581 | 0 | case AArch64::ST1Twov1d: |
6582 | 0 | case AArch64::ST1Twov2d: |
6583 | 0 | case AArch64::ST1Twov2s: |
6584 | 0 | case AArch64::ST1Twov4h: |
6585 | 0 | case AArch64::ST1Twov4s: |
6586 | 0 | case AArch64::ST1Twov8b: |
6587 | 0 | case AArch64::ST1Twov8h: |
6588 | 0 | case AArch64::ST2Twov16b: |
6589 | 0 | case AArch64::ST2Twov2d: |
6590 | 0 | case AArch64::ST2Twov2s: |
6591 | 0 | case AArch64::ST2Twov4h: |
6592 | 0 | case AArch64::ST2Twov4s: |
6593 | 0 | case AArch64::ST2Twov8b: |
6594 | 0 | case AArch64::ST2Twov8h: |
6595 | 0 | case AArch64::ST3Threev16b: |
6596 | 0 | case AArch64::ST3Threev2d: |
6597 | 0 | case AArch64::ST3Threev2s: |
6598 | 0 | case AArch64::ST3Threev4h: |
6599 | 0 | case AArch64::ST3Threev4s: |
6600 | 0 | case AArch64::ST3Threev8b: |
6601 | 0 | case AArch64::ST3Threev8h: |
6602 | 0 | case AArch64::ST4Fourv16b: |
6603 | 0 | case AArch64::ST4Fourv2d: |
6604 | 0 | case AArch64::ST4Fourv2s: |
6605 | 0 | case AArch64::ST4Fourv4h: |
6606 | 0 | case AArch64::ST4Fourv4s: |
6607 | 0 | case AArch64::ST4Fourv8b: |
6608 | 0 | case AArch64::ST4Fourv8h: { |
6609 | | // op: Vt |
6610 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6611 | 0 | Value |= op & UINT64_C(31); |
6612 | | // op: Rn |
6613 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6614 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6615 | 0 | break; |
6616 | 0 | } |
6617 | 0 | case AArch64::ST1i64: |
6618 | 0 | case AArch64::ST2i64: |
6619 | 0 | case AArch64::ST3i64: |
6620 | 0 | case AArch64::ST4i64: { |
6621 | | // op: Vt |
6622 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6623 | 0 | Value |= op & UINT64_C(31); |
6624 | | // op: Rn |
6625 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6626 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6627 | | // op: idx |
6628 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6629 | 0 | Value |= (op & UINT64_C(1)) << 30; |
6630 | 0 | break; |
6631 | 0 | } |
6632 | 0 | case AArch64::ST1i32: |
6633 | 0 | case AArch64::ST2i32: |
6634 | 0 | case AArch64::ST3i32: |
6635 | 0 | case AArch64::ST4i32: { |
6636 | | // op: Vt |
6637 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6638 | 0 | Value |= op & UINT64_C(31); |
6639 | | // op: Rn |
6640 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6641 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6642 | | // op: idx |
6643 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6644 | 0 | Value |= (op & UINT64_C(2)) << 29; |
6645 | 0 | Value |= (op & UINT64_C(1)) << 12; |
6646 | 0 | break; |
6647 | 0 | } |
6648 | 0 | case AArch64::ST1i16: |
6649 | 0 | case AArch64::ST2i16: |
6650 | 0 | case AArch64::ST3i16: |
6651 | 0 | case AArch64::ST4i16: { |
6652 | | // op: Vt |
6653 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6654 | 0 | Value |= op & UINT64_C(31); |
6655 | | // op: Rn |
6656 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6657 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6658 | | // op: idx |
6659 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6660 | 0 | Value |= (op & UINT64_C(4)) << 28; |
6661 | 0 | Value |= (op & UINT64_C(3)) << 11; |
6662 | 0 | break; |
6663 | 0 | } |
6664 | 0 | case AArch64::ST1i8: |
6665 | 0 | case AArch64::ST2i8: |
6666 | 0 | case AArch64::ST3i8: |
6667 | 0 | case AArch64::ST4i8: { |
6668 | | // op: Vt |
6669 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
6670 | 0 | Value |= op & UINT64_C(31); |
6671 | | // op: Rn |
6672 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6673 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6674 | | // op: idx |
6675 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6676 | 0 | Value |= (op & UINT64_C(8)) << 27; |
6677 | 0 | Value |= (op & UINT64_C(7)) << 10; |
6678 | 0 | break; |
6679 | 0 | } |
6680 | 0 | case AArch64::LD1Fourv16b_POST: |
6681 | 0 | case AArch64::LD1Fourv1d_POST: |
6682 | 0 | case AArch64::LD1Fourv2d_POST: |
6683 | 0 | case AArch64::LD1Fourv2s_POST: |
6684 | 0 | case AArch64::LD1Fourv4h_POST: |
6685 | 0 | case AArch64::LD1Fourv4s_POST: |
6686 | 0 | case AArch64::LD1Fourv8b_POST: |
6687 | 0 | case AArch64::LD1Fourv8h_POST: |
6688 | 0 | case AArch64::LD1Onev16b_POST: |
6689 | 0 | case AArch64::LD1Onev1d_POST: |
6690 | 0 | case AArch64::LD1Onev2d_POST: |
6691 | 0 | case AArch64::LD1Onev2s_POST: |
6692 | 0 | case AArch64::LD1Onev4h_POST: |
6693 | 0 | case AArch64::LD1Onev4s_POST: |
6694 | 0 | case AArch64::LD1Onev8b_POST: |
6695 | 0 | case AArch64::LD1Onev8h_POST: |
6696 | 0 | case AArch64::LD1Rv16b_POST: |
6697 | 0 | case AArch64::LD1Rv1d_POST: |
6698 | 0 | case AArch64::LD1Rv2d_POST: |
6699 | 0 | case AArch64::LD1Rv2s_POST: |
6700 | 0 | case AArch64::LD1Rv4h_POST: |
6701 | 0 | case AArch64::LD1Rv4s_POST: |
6702 | 0 | case AArch64::LD1Rv8b_POST: |
6703 | 0 | case AArch64::LD1Rv8h_POST: |
6704 | 0 | case AArch64::LD1Threev16b_POST: |
6705 | 0 | case AArch64::LD1Threev1d_POST: |
6706 | 0 | case AArch64::LD1Threev2d_POST: |
6707 | 0 | case AArch64::LD1Threev2s_POST: |
6708 | 0 | case AArch64::LD1Threev4h_POST: |
6709 | 0 | case AArch64::LD1Threev4s_POST: |
6710 | 0 | case AArch64::LD1Threev8b_POST: |
6711 | 0 | case AArch64::LD1Threev8h_POST: |
6712 | 0 | case AArch64::LD1Twov16b_POST: |
6713 | 0 | case AArch64::LD1Twov1d_POST: |
6714 | 0 | case AArch64::LD1Twov2d_POST: |
6715 | 0 | case AArch64::LD1Twov2s_POST: |
6716 | 0 | case AArch64::LD1Twov4h_POST: |
6717 | 0 | case AArch64::LD1Twov4s_POST: |
6718 | 0 | case AArch64::LD1Twov8b_POST: |
6719 | 0 | case AArch64::LD1Twov8h_POST: |
6720 | 0 | case AArch64::LD2Rv16b_POST: |
6721 | 0 | case AArch64::LD2Rv1d_POST: |
6722 | 0 | case AArch64::LD2Rv2d_POST: |
6723 | 0 | case AArch64::LD2Rv2s_POST: |
6724 | 0 | case AArch64::LD2Rv4h_POST: |
6725 | 0 | case AArch64::LD2Rv4s_POST: |
6726 | 0 | case AArch64::LD2Rv8b_POST: |
6727 | 0 | case AArch64::LD2Rv8h_POST: |
6728 | 0 | case AArch64::LD2Twov16b_POST: |
6729 | 0 | case AArch64::LD2Twov2d_POST: |
6730 | 0 | case AArch64::LD2Twov2s_POST: |
6731 | 0 | case AArch64::LD2Twov4h_POST: |
6732 | 0 | case AArch64::LD2Twov4s_POST: |
6733 | 0 | case AArch64::LD2Twov8b_POST: |
6734 | 0 | case AArch64::LD2Twov8h_POST: |
6735 | 0 | case AArch64::LD3Rv16b_POST: |
6736 | 0 | case AArch64::LD3Rv1d_POST: |
6737 | 0 | case AArch64::LD3Rv2d_POST: |
6738 | 0 | case AArch64::LD3Rv2s_POST: |
6739 | 0 | case AArch64::LD3Rv4h_POST: |
6740 | 0 | case AArch64::LD3Rv4s_POST: |
6741 | 0 | case AArch64::LD3Rv8b_POST: |
6742 | 0 | case AArch64::LD3Rv8h_POST: |
6743 | 0 | case AArch64::LD3Threev16b_POST: |
6744 | 0 | case AArch64::LD3Threev2d_POST: |
6745 | 0 | case AArch64::LD3Threev2s_POST: |
6746 | 0 | case AArch64::LD3Threev4h_POST: |
6747 | 0 | case AArch64::LD3Threev4s_POST: |
6748 | 0 | case AArch64::LD3Threev8b_POST: |
6749 | 0 | case AArch64::LD3Threev8h_POST: |
6750 | 0 | case AArch64::LD4Fourv16b_POST: |
6751 | 0 | case AArch64::LD4Fourv2d_POST: |
6752 | 0 | case AArch64::LD4Fourv2s_POST: |
6753 | 0 | case AArch64::LD4Fourv4h_POST: |
6754 | 0 | case AArch64::LD4Fourv4s_POST: |
6755 | 0 | case AArch64::LD4Fourv8b_POST: |
6756 | 0 | case AArch64::LD4Fourv8h_POST: |
6757 | 0 | case AArch64::LD4Rv16b_POST: |
6758 | 0 | case AArch64::LD4Rv1d_POST: |
6759 | 0 | case AArch64::LD4Rv2d_POST: |
6760 | 0 | case AArch64::LD4Rv2s_POST: |
6761 | 0 | case AArch64::LD4Rv4h_POST: |
6762 | 0 | case AArch64::LD4Rv4s_POST: |
6763 | 0 | case AArch64::LD4Rv8b_POST: |
6764 | 0 | case AArch64::LD4Rv8h_POST: |
6765 | 0 | case AArch64::ST1Fourv16b_POST: |
6766 | 0 | case AArch64::ST1Fourv1d_POST: |
6767 | 0 | case AArch64::ST1Fourv2d_POST: |
6768 | 0 | case AArch64::ST1Fourv2s_POST: |
6769 | 0 | case AArch64::ST1Fourv4h_POST: |
6770 | 0 | case AArch64::ST1Fourv4s_POST: |
6771 | 0 | case AArch64::ST1Fourv8b_POST: |
6772 | 0 | case AArch64::ST1Fourv8h_POST: |
6773 | 0 | case AArch64::ST1Onev16b_POST: |
6774 | 0 | case AArch64::ST1Onev1d_POST: |
6775 | 0 | case AArch64::ST1Onev2d_POST: |
6776 | 0 | case AArch64::ST1Onev2s_POST: |
6777 | 0 | case AArch64::ST1Onev4h_POST: |
6778 | 0 | case AArch64::ST1Onev4s_POST: |
6779 | 0 | case AArch64::ST1Onev8b_POST: |
6780 | 0 | case AArch64::ST1Onev8h_POST: |
6781 | 0 | case AArch64::ST1Threev16b_POST: |
6782 | 0 | case AArch64::ST1Threev1d_POST: |
6783 | 0 | case AArch64::ST1Threev2d_POST: |
6784 | 0 | case AArch64::ST1Threev2s_POST: |
6785 | 0 | case AArch64::ST1Threev4h_POST: |
6786 | 0 | case AArch64::ST1Threev4s_POST: |
6787 | 0 | case AArch64::ST1Threev8b_POST: |
6788 | 0 | case AArch64::ST1Threev8h_POST: |
6789 | 0 | case AArch64::ST1Twov16b_POST: |
6790 | 0 | case AArch64::ST1Twov1d_POST: |
6791 | 0 | case AArch64::ST1Twov2d_POST: |
6792 | 0 | case AArch64::ST1Twov2s_POST: |
6793 | 0 | case AArch64::ST1Twov4h_POST: |
6794 | 0 | case AArch64::ST1Twov4s_POST: |
6795 | 0 | case AArch64::ST1Twov8b_POST: |
6796 | 0 | case AArch64::ST1Twov8h_POST: |
6797 | 0 | case AArch64::ST2Twov16b_POST: |
6798 | 0 | case AArch64::ST2Twov2d_POST: |
6799 | 0 | case AArch64::ST2Twov2s_POST: |
6800 | 0 | case AArch64::ST2Twov4h_POST: |
6801 | 0 | case AArch64::ST2Twov4s_POST: |
6802 | 0 | case AArch64::ST2Twov8b_POST: |
6803 | 0 | case AArch64::ST2Twov8h_POST: |
6804 | 0 | case AArch64::ST3Threev16b_POST: |
6805 | 0 | case AArch64::ST3Threev2d_POST: |
6806 | 0 | case AArch64::ST3Threev2s_POST: |
6807 | 0 | case AArch64::ST3Threev4h_POST: |
6808 | 0 | case AArch64::ST3Threev4s_POST: |
6809 | 0 | case AArch64::ST3Threev8b_POST: |
6810 | 0 | case AArch64::ST3Threev8h_POST: |
6811 | 0 | case AArch64::ST4Fourv16b_POST: |
6812 | 0 | case AArch64::ST4Fourv2d_POST: |
6813 | 0 | case AArch64::ST4Fourv2s_POST: |
6814 | 0 | case AArch64::ST4Fourv4h_POST: |
6815 | 0 | case AArch64::ST4Fourv4s_POST: |
6816 | 0 | case AArch64::ST4Fourv8b_POST: |
6817 | 0 | case AArch64::ST4Fourv8h_POST: { |
6818 | | // op: Vt |
6819 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6820 | 0 | Value |= op & UINT64_C(31); |
6821 | | // op: Rn |
6822 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6823 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6824 | | // op: Xm |
6825 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6826 | 0 | Value |= (op & UINT64_C(31)) << 16; |
6827 | 0 | break; |
6828 | 0 | } |
6829 | 0 | case AArch64::LD1i64: |
6830 | 0 | case AArch64::LD2i64: |
6831 | 0 | case AArch64::LD3i64: |
6832 | 0 | case AArch64::LD4i64: { |
6833 | | // op: Vt |
6834 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6835 | 0 | Value |= op & UINT64_C(31); |
6836 | | // op: Rn |
6837 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6838 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6839 | | // op: idx |
6840 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6841 | 0 | Value |= (op & UINT64_C(1)) << 30; |
6842 | 0 | break; |
6843 | 0 | } |
6844 | 0 | case AArch64::ST1i64_POST: |
6845 | 0 | case AArch64::ST2i64_POST: |
6846 | 0 | case AArch64::ST3i64_POST: |
6847 | 0 | case AArch64::ST4i64_POST: { |
6848 | | // op: Vt |
6849 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6850 | 0 | Value |= op & UINT64_C(31); |
6851 | | // op: Rn |
6852 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6853 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6854 | | // op: idx |
6855 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6856 | 0 | Value |= (op & UINT64_C(1)) << 30; |
6857 | | // op: Xm |
6858 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6859 | 0 | Value |= (op & UINT64_C(31)) << 16; |
6860 | 0 | break; |
6861 | 0 | } |
6862 | 0 | case AArch64::LD1i32: |
6863 | 0 | case AArch64::LD2i32: |
6864 | 0 | case AArch64::LD3i32: |
6865 | 0 | case AArch64::LD4i32: { |
6866 | | // op: Vt |
6867 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6868 | 0 | Value |= op & UINT64_C(31); |
6869 | | // op: Rn |
6870 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6871 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6872 | | // op: idx |
6873 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6874 | 0 | Value |= (op & UINT64_C(2)) << 29; |
6875 | 0 | Value |= (op & UINT64_C(1)) << 12; |
6876 | 0 | break; |
6877 | 0 | } |
6878 | 0 | case AArch64::ST1i32_POST: |
6879 | 0 | case AArch64::ST2i32_POST: |
6880 | 0 | case AArch64::ST3i32_POST: |
6881 | 0 | case AArch64::ST4i32_POST: { |
6882 | | // op: Vt |
6883 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6884 | 0 | Value |= op & UINT64_C(31); |
6885 | | // op: Rn |
6886 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6887 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6888 | | // op: idx |
6889 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6890 | 0 | Value |= (op & UINT64_C(2)) << 29; |
6891 | 0 | Value |= (op & UINT64_C(1)) << 12; |
6892 | | // op: Xm |
6893 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6894 | 0 | Value |= (op & UINT64_C(31)) << 16; |
6895 | 0 | break; |
6896 | 0 | } |
6897 | 0 | case AArch64::LD1i16: |
6898 | 0 | case AArch64::LD2i16: |
6899 | 0 | case AArch64::LD3i16: |
6900 | 0 | case AArch64::LD4i16: { |
6901 | | // op: Vt |
6902 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6903 | 0 | Value |= op & UINT64_C(31); |
6904 | | // op: Rn |
6905 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6906 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6907 | | // op: idx |
6908 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6909 | 0 | Value |= (op & UINT64_C(4)) << 28; |
6910 | 0 | Value |= (op & UINT64_C(3)) << 11; |
6911 | 0 | break; |
6912 | 0 | } |
6913 | 0 | case AArch64::ST1i16_POST: |
6914 | 0 | case AArch64::ST2i16_POST: |
6915 | 0 | case AArch64::ST3i16_POST: |
6916 | 0 | case AArch64::ST4i16_POST: { |
6917 | | // op: Vt |
6918 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6919 | 0 | Value |= op & UINT64_C(31); |
6920 | | // op: Rn |
6921 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6922 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6923 | | // op: idx |
6924 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6925 | 0 | Value |= (op & UINT64_C(4)) << 28; |
6926 | 0 | Value |= (op & UINT64_C(3)) << 11; |
6927 | | // op: Xm |
6928 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6929 | 0 | Value |= (op & UINT64_C(31)) << 16; |
6930 | 0 | break; |
6931 | 0 | } |
6932 | 0 | case AArch64::LD1i8: |
6933 | 0 | case AArch64::LD2i8: |
6934 | 0 | case AArch64::LD3i8: |
6935 | 0 | case AArch64::LD4i8: { |
6936 | | // op: Vt |
6937 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6938 | 0 | Value |= op & UINT64_C(31); |
6939 | | // op: Rn |
6940 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6941 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6942 | | // op: idx |
6943 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6944 | 0 | Value |= (op & UINT64_C(8)) << 27; |
6945 | 0 | Value |= (op & UINT64_C(7)) << 10; |
6946 | 0 | break; |
6947 | 0 | } |
6948 | 0 | case AArch64::ST1i8_POST: |
6949 | 0 | case AArch64::ST2i8_POST: |
6950 | 0 | case AArch64::ST3i8_POST: |
6951 | 0 | case AArch64::ST4i8_POST: { |
6952 | | // op: Vt |
6953 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
6954 | 0 | Value |= op & UINT64_C(31); |
6955 | | // op: Rn |
6956 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6957 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6958 | | // op: idx |
6959 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6960 | 0 | Value |= (op & UINT64_C(8)) << 27; |
6961 | 0 | Value |= (op & UINT64_C(7)) << 10; |
6962 | | // op: Xm |
6963 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6964 | 0 | Value |= (op & UINT64_C(31)) << 16; |
6965 | 0 | break; |
6966 | 0 | } |
6967 | 0 | case AArch64::LD1i64_POST: |
6968 | 0 | case AArch64::LD2i64_POST: |
6969 | 0 | case AArch64::LD3i64_POST: |
6970 | 0 | case AArch64::LD4i64_POST: { |
6971 | | // op: Vt |
6972 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6973 | 0 | Value |= op & UINT64_C(31); |
6974 | | // op: Rn |
6975 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6976 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6977 | | // op: idx |
6978 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6979 | 0 | Value |= (op & UINT64_C(1)) << 30; |
6980 | | // op: Xm |
6981 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
6982 | 0 | Value |= (op & UINT64_C(31)) << 16; |
6983 | 0 | break; |
6984 | 0 | } |
6985 | 0 | case AArch64::LD1i32_POST: |
6986 | 0 | case AArch64::LD2i32_POST: |
6987 | 0 | case AArch64::LD3i32_POST: |
6988 | 0 | case AArch64::LD4i32_POST: { |
6989 | | // op: Vt |
6990 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
6991 | 0 | Value |= op & UINT64_C(31); |
6992 | | // op: Rn |
6993 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
6994 | 0 | Value |= (op & UINT64_C(31)) << 5; |
6995 | | // op: idx |
6996 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
6997 | 0 | Value |= (op & UINT64_C(2)) << 29; |
6998 | 0 | Value |= (op & UINT64_C(1)) << 12; |
6999 | | // op: Xm |
7000 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
7001 | 0 | Value |= (op & UINT64_C(31)) << 16; |
7002 | 0 | break; |
7003 | 0 | } |
7004 | 0 | case AArch64::LD1i16_POST: |
7005 | 0 | case AArch64::LD2i16_POST: |
7006 | 0 | case AArch64::LD3i16_POST: |
7007 | 0 | case AArch64::LD4i16_POST: { |
7008 | | // op: Vt |
7009 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7010 | 0 | Value |= op & UINT64_C(31); |
7011 | | // op: Rn |
7012 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
7013 | 0 | Value |= (op & UINT64_C(31)) << 5; |
7014 | | // op: idx |
7015 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7016 | 0 | Value |= (op & UINT64_C(4)) << 28; |
7017 | 0 | Value |= (op & UINT64_C(3)) << 11; |
7018 | | // op: Xm |
7019 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
7020 | 0 | Value |= (op & UINT64_C(31)) << 16; |
7021 | 0 | break; |
7022 | 0 | } |
7023 | 0 | case AArch64::LD1i8_POST: |
7024 | 0 | case AArch64::LD2i8_POST: |
7025 | 0 | case AArch64::LD3i8_POST: |
7026 | 0 | case AArch64::LD4i8_POST: { |
7027 | | // op: Vt |
7028 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7029 | 0 | Value |= op & UINT64_C(31); |
7030 | | // op: Rn |
7031 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
7032 | 0 | Value |= (op & UINT64_C(31)) << 5; |
7033 | | // op: idx |
7034 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7035 | 0 | Value |= (op & UINT64_C(8)) << 27; |
7036 | 0 | Value |= (op & UINT64_C(7)) << 10; |
7037 | | // op: Xm |
7038 | 0 | op = getMachineOpValue(MI, MI.getOperand(5), Fixups, STI); |
7039 | 0 | Value |= (op & UINT64_C(31)) << 16; |
7040 | 0 | break; |
7041 | 0 | } |
7042 | 0 | case AArch64::STLXRB: |
7043 | 0 | case AArch64::STLXRH: |
7044 | 0 | case AArch64::STLXRW: |
7045 | 0 | case AArch64::STLXRX: |
7046 | 0 | case AArch64::STXRB: |
7047 | 0 | case AArch64::STXRH: |
7048 | 0 | case AArch64::STXRW: |
7049 | 0 | case AArch64::STXRX: { |
7050 | | // op: Ws |
7051 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7052 | 0 | Value |= (op & UINT64_C(31)) << 16; |
7053 | | // op: Rt |
7054 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7055 | 0 | Value |= op & UINT64_C(31); |
7056 | | // op: Rn |
7057 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7058 | 0 | Value |= (op & UINT64_C(31)) << 5; |
7059 | 0 | Value = fixLoadStoreExclusive<1,0>(MI, Value, STI); |
7060 | 0 | break; |
7061 | 0 | } |
7062 | 0 | case AArch64::STLXPW: |
7063 | 0 | case AArch64::STLXPX: |
7064 | 0 | case AArch64::STXPW: |
7065 | 0 | case AArch64::STXPX: { |
7066 | | // op: Ws |
7067 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7068 | 0 | Value |= (op & UINT64_C(31)) << 16; |
7069 | | // op: Rt |
7070 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7071 | 0 | Value |= op & UINT64_C(31); |
7072 | | // op: Rt2 |
7073 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7074 | 0 | Value |= (op & UINT64_C(31)) << 10; |
7075 | | // op: Rn |
7076 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7077 | 0 | Value |= (op & UINT64_C(31)) << 5; |
7078 | 0 | break; |
7079 | 0 | } |
7080 | 0 | case AArch64::ADR: |
7081 | 0 | case AArch64::ADRP: { |
7082 | | // op: Xd |
7083 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7084 | 0 | Value |= op & UINT64_C(31); |
7085 | | // op: label |
7086 | 0 | op = getAdrLabelOpValue(MI, 1, Fixups, STI); |
7087 | 0 | Value |= (op & UINT64_C(3)) << 29; |
7088 | 0 | Value |= (op & UINT64_C(2097148)) << 3; |
7089 | 0 | break; |
7090 | 0 | } |
7091 | 761 | case AArch64::B: |
7092 | 996 | case AArch64::BL: { |
7093 | | // op: addr |
7094 | 996 | op = getBranchTargetOpValue(MI, 0, Fixups, STI); |
7095 | 996 | Value |= op & UINT64_C(67108863); |
7096 | 996 | break; |
7097 | 761 | } |
7098 | 323 | case AArch64::Bcc: { |
7099 | | // op: cond |
7100 | 323 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7101 | 323 | Value |= op & UINT64_C(15); |
7102 | | // op: target |
7103 | 323 | op = getCondBranchTargetOpValue(MI, 1, Fixups, STI); |
7104 | 323 | Value |= (op & UINT64_C(524287)) << 5; |
7105 | 323 | break; |
7106 | 761 | } |
7107 | 0 | case AArch64::CPYi64: { |
7108 | | // op: dst |
7109 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7110 | 0 | Value |= op & UINT64_C(31); |
7111 | | // op: src |
7112 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7113 | 0 | Value |= (op & UINT64_C(31)) << 5; |
7114 | | // op: idx |
7115 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7116 | 0 | Value |= (op & UINT64_C(1)) << 20; |
7117 | 0 | break; |
7118 | 761 | } |
7119 | 0 | case AArch64::CPYi8: { |
7120 | | // op: dst |
7121 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7122 | 0 | Value |= op & UINT64_C(31); |
7123 | | // op: src |
7124 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7125 | 0 | Value |= (op & UINT64_C(31)) << 5; |
7126 | | // op: idx |
7127 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7128 | 0 | Value |= (op & UINT64_C(15)) << 17; |
7129 | 0 | break; |
7130 | 761 | } |
7131 | 0 | case AArch64::CPYi32: { |
7132 | | // op: dst |
7133 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7134 | 0 | Value |= op & UINT64_C(31); |
7135 | | // op: src |
7136 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7137 | 0 | Value |= (op & UINT64_C(31)) << 5; |
7138 | | // op: idx |
7139 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7140 | 0 | Value |= (op & UINT64_C(3)) << 19; |
7141 | 0 | break; |
7142 | 761 | } |
7143 | 0 | case AArch64::CPYi16: { |
7144 | | // op: dst |
7145 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7146 | 0 | Value |= op & UINT64_C(31); |
7147 | | // op: src |
7148 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7149 | 0 | Value |= (op & UINT64_C(31)) << 5; |
7150 | | // op: idx |
7151 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7152 | 0 | Value |= (op & UINT64_C(7)) << 18; |
7153 | 0 | break; |
7154 | 761 | } |
7155 | 0 | case AArch64::ADDSWrs: |
7156 | 0 | case AArch64::ADDSXrs: |
7157 | 0 | case AArch64::ADDWrs: |
7158 | 0 | case AArch64::ADDXrs: |
7159 | 0 | case AArch64::ANDSWrs: |
7160 | 0 | case AArch64::ANDSXrs: |
7161 | 0 | case AArch64::ANDWrs: |
7162 | 0 | case AArch64::ANDXrs: |
7163 | 0 | case AArch64::BICSWrs: |
7164 | 0 | case AArch64::BICSXrs: |
7165 | 0 | case AArch64::BICWrs: |
7166 | 0 | case AArch64::BICXrs: |
7167 | 0 | case AArch64::EONWrs: |
7168 | 0 | case AArch64::EONXrs: |
7169 | 0 | case AArch64::EORWrs: |
7170 | 0 | case AArch64::EORXrs: |
7171 | 0 | case AArch64::ORNWrs: |
7172 | 0 | case AArch64::ORNXrs: |
7173 | 0 | case AArch64::ORRWrs: |
7174 | 0 | case AArch64::ORRXrs: |
7175 | 0 | case AArch64::SUBSWrs: |
7176 | 0 | case AArch64::SUBSXrs: |
7177 | 0 | case AArch64::SUBWrs: |
7178 | 0 | case AArch64::SUBXrs: { |
7179 | | // op: dst |
7180 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7181 | 0 | Value |= op & UINT64_C(31); |
7182 | | // op: src1 |
7183 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7184 | 0 | Value |= (op & UINT64_C(31)) << 5; |
7185 | | // op: src2 |
7186 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
7187 | 0 | Value |= (op & UINT64_C(31)) << 16; |
7188 | | // op: shift |
7189 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
7190 | 0 | Value |= (op & UINT64_C(192)) << 16; |
7191 | 0 | Value |= (op & UINT64_C(63)) << 10; |
7192 | 0 | break; |
7193 | 0 | } |
7194 | 42 | case AArch64::HINT: { |
7195 | | // op: imm |
7196 | 42 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7197 | 42 | Value |= (op & UINT64_C(127)) << 5; |
7198 | 42 | break; |
7199 | 0 | } |
7200 | 0 | case AArch64::BRK: |
7201 | 0 | case AArch64::DCPS1: |
7202 | 0 | case AArch64::DCPS2: |
7203 | 0 | case AArch64::DCPS3: |
7204 | 0 | case AArch64::HLT: |
7205 | 0 | case AArch64::HVC: |
7206 | 10 | case AArch64::SMC: |
7207 | 10 | case AArch64::SVC: { |
7208 | | // op: imm |
7209 | 10 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7210 | 10 | Value |= (op & UINT64_C(65535)) << 5; |
7211 | 10 | break; |
7212 | 10 | } |
7213 | 0 | case AArch64::MSRpstateImm1: { |
7214 | | // op: pstatefield |
7215 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7216 | 0 | Value |= (op & UINT64_C(56)) << 13; |
7217 | 0 | Value |= (op & UINT64_C(7)) << 5; |
7218 | | // op: imm |
7219 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7220 | 0 | Value |= (op & UINT64_C(1)) << 8; |
7221 | 0 | break; |
7222 | 10 | } |
7223 | 0 | case AArch64::MSRpstateImm4: { |
7224 | | // op: pstatefield |
7225 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
7226 | 0 | Value |= (op & UINT64_C(56)) << 13; |
7227 | 0 | Value |= (op & UINT64_C(7)) << 5; |
7228 | | // op: imm |
7229 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
7230 | 0 | Value |= (op & UINT64_C(15)) << 8; |
7231 | 0 | break; |
7232 | 10 | } |
7233 | 0 | default: |
7234 | 0 | std::string msg; |
7235 | 0 | raw_string_ostream Msg(msg); |
7236 | 0 | Msg << "Not supported instr: " << MI; |
7237 | 0 | report_fatal_error(Msg.str()); |
7238 | 1.59k | } |
7239 | 1.59k | return Value; |
7240 | 1.59k | } |
7241 | | |