/src/keystone/llvm/lib/Target/AArch64/AArch64GenRegisterInfo.inc

Source
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* Target Register Enum Values                                                *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
namespace llvm_ks {

class MCRegisterClass;
extern const MCRegisterClass AArch64MCRegisterClasses[];

namespace AArch64 {
enum {
  NoRegister,
  FP = 1,
  LR = 2,
  NZCV = 3,
  SP = 4,
  WSP = 5,
  WZR = 6,
  XZR = 7,
  B0 = 8,
  B1 = 9,
  B2 = 10,
  B3 = 11,
  B4 = 12,
  B5 = 13,
  B6 = 14,
  B7 = 15,
  B8 = 16,
  B9 = 17,
  B10 = 18,
  B11 = 19,
  B12 = 20,
  B13 = 21,
  B14 = 22,
  B15 = 23,
  B16 = 24,
  B17 = 25,
  B18 = 26,
  B19 = 27,
  B20 = 28,
  B21 = 29,
  B22 = 30,
  B23 = 31,
  B24 = 32,
  B25 = 33,
  B26 = 34,
  B27 = 35,
  B28 = 36,
  B29 = 37,
  B30 = 38,
  B31 = 39,
  D0 = 40,
  D1 = 41,
  D2 = 42,
  D3 = 43,
  D4 = 44,
  D5 = 45,
  D6 = 46,
  D7 = 47,
  D8 = 48,
  D9 = 49,
  D10 = 50,
  D11 = 51,
  D12 = 52,
  D13 = 53,
  D14 = 54,
  D15 = 55,
  D16 = 56,
  D17 = 57,
  D18 = 58,
  D19 = 59,
  D20 = 60,
  D21 = 61,
  D22 = 62,
  D23 = 63,
  D24 = 64,
  D25 = 65,
  D26 = 66,
  D27 = 67,
  D28 = 68,
  D29 = 69,
  D30 = 70,
  D31 = 71,
  H0 = 72,
  H1 = 73,
  H2 = 74,
  H3 = 75,
  H4 = 76,
  H5 = 77,
  H6 = 78,
  H7 = 79,
  H8 = 80,
  H9 = 81,
  H10 = 82,
  H11 = 83,
  H12 = 84,
  H13 = 85,
  H14 = 86,
  H15 = 87,
  H16 = 88,
  H17 = 89,
  H18 = 90,
  H19 = 91,
  H20 = 92,
  H21 = 93,
  H22 = 94,
  H23 = 95,
  H24 = 96,
  H25 = 97,
  H26 = 98,
  H27 = 99,
  H28 = 100,
  H29 = 101,
  H30 = 102,
  H31 = 103,
  Q0 = 104,
  Q1 = 105,
  Q2 = 106,
  Q3 = 107,
  Q4 = 108,
  Q5 = 109,
  Q6 = 110,
  Q7 = 111,
  Q8 = 112,
  Q9 = 113,
  Q10 = 114,
  Q11 = 115,
  Q12 = 116,
  Q13 = 117,
  Q14 = 118,
  Q15 = 119,
  Q16 = 120,
  Q17 = 121,
  Q18 = 122,
  Q19 = 123,
  Q20 = 124,
  Q21 = 125,
  Q22 = 126,
  Q23 = 127,
  Q24 = 128,
  Q25 = 129,
  Q26 = 130,
  Q27 = 131,
  Q28 = 132,
  Q29 = 133,
  Q30 = 134,
  Q31 = 135,
  S0 = 136,
  S1 = 137,
  S2 = 138,
  S3 = 139,
  S4 = 140,
  S5 = 141,
  S6 = 142,
  S7 = 143,
  S8 = 144,
  S9 = 145,
  S10 = 146,
  S11 = 147,
  S12 = 148,
  S13 = 149,
  S14 = 150,
  S15 = 151,
  S16 = 152,
  S17 = 153,
  S18 = 154,
  S19 = 155,
  S20 = 156,
  S21 = 157,
  S22 = 158,
  S23 = 159,
  S24 = 160,
  S25 = 161,
  S26 = 162,
  S27 = 163,
  S28 = 164,
  S29 = 165,
  S30 = 166,
  S31 = 167,
  W0 = 168,
  W1 = 169,
  W2 = 170,
  W3 = 171,
  W4 = 172,
  W5 = 173,
  W6 = 174,
  W7 = 175,
  W8 = 176,
  W9 = 177,
  W10 = 178,
  W11 = 179,
  W12 = 180,
  W13 = 181,
  W14 = 182,
  W15 = 183,
  W16 = 184,
  W17 = 185,
  W18 = 186,
  W19 = 187,
  W20 = 188,
  W21 = 189,
  W22 = 190,
  W23 = 191,
  W24 = 192,
  W25 = 193,
  W26 = 194,
  W27 = 195,
  W28 = 196,
  W29 = 197,
  W30 = 198,
  X0 = 199,
  X1 = 200,
  X2 = 201,
  X3 = 202,
  X4 = 203,
  X5 = 204,
  X6 = 205,
  X7 = 206,
  X8 = 207,
  X9 = 208,
  X10 = 209,
  X11 = 210,
  X12 = 211,
  X13 = 212,
  X14 = 213,
  X15 = 214,
  X16 = 215,
  X17 = 216,
  X18 = 217,
  X19 = 218,
  X20 = 219,
  X21 = 220,
  X22 = 221,
  X23 = 222,
  X24 = 223,
  X25 = 224,
  X26 = 225,
  X27 = 226,
  X28 = 227,
  D0_D1 = 228,
  D1_D2 = 229,
  D2_D3 = 230,
  D3_D4 = 231,
  D4_D5 = 232,
  D5_D6 = 233,
  D6_D7 = 234,
  D7_D8 = 235,
  D8_D9 = 236,
  D9_D10 = 237,
  D10_D11 = 238,
  D11_D12 = 239,
  D12_D13 = 240,
  D13_D14 = 241,
  D14_D15 = 242,
  D15_D16 = 243,
  D16_D17 = 244,
  D17_D18 = 245,
  D18_D19 = 246,
  D19_D20 = 247,
  D20_D21 = 248,
  D21_D22 = 249,
  D22_D23 = 250,
  D23_D24 = 251,
  D24_D25 = 252,
  D25_D26 = 253,
  D26_D27 = 254,
  D27_D28 = 255,
  D28_D29 = 256,
  D29_D30 = 257,
  D30_D31 = 258,
  D31_D0 = 259,
  D0_D1_D2_D3 = 260,
  D1_D2_D3_D4 = 261,
  D2_D3_D4_D5 = 262,
  D3_D4_D5_D6 = 263,
  D4_D5_D6_D7 = 264,
  D5_D6_D7_D8 = 265,
  D6_D7_D8_D9 = 266,
  D7_D8_D9_D10 = 267,
  D8_D9_D10_D11 = 268,
  D9_D10_D11_D12 = 269,
  D10_D11_D12_D13 = 270,
  D11_D12_D13_D14 = 271,
  D12_D13_D14_D15 = 272,
  D13_D14_D15_D16 = 273,
  D14_D15_D16_D17 = 274,
  D15_D16_D17_D18 = 275,
  D16_D17_D18_D19 = 276,
  D17_D18_D19_D20 = 277,
  D18_D19_D20_D21 = 278,
  D19_D20_D21_D22 = 279,
  D20_D21_D22_D23 = 280,
  D21_D22_D23_D24 = 281,
  D22_D23_D24_D25 = 282,
  D23_D24_D25_D26 = 283,
  D24_D25_D26_D27 = 284,
  D25_D26_D27_D28 = 285,
  D26_D27_D28_D29 = 286,
  D27_D28_D29_D30 = 287,
  D28_D29_D30_D31 = 288,
  D29_D30_D31_D0 = 289,
  D30_D31_D0_D1 = 290,
  D31_D0_D1_D2 = 291,
  D0_D1_D2 = 292,
  D1_D2_D3 = 293,
  D2_D3_D4 = 294,
  D3_D4_D5 = 295,
  D4_D5_D6 = 296,
  D5_D6_D7 = 297,
  D6_D7_D8 = 298,
  D7_D8_D9 = 299,
  D8_D9_D10 = 300,
  D9_D10_D11 = 301,
  D10_D11_D12 = 302,
  D11_D12_D13 = 303,
  D12_D13_D14 = 304,
  D13_D14_D15 = 305,
  D14_D15_D16 = 306,
  D15_D16_D17 = 307,
  D16_D17_D18 = 308,
  D17_D18_D19 = 309,
  D18_D19_D20 = 310,
  D19_D20_D21 = 311,
  D20_D21_D22 = 312,
  D21_D22_D23 = 313,
  D22_D23_D24 = 314,
  D23_D24_D25 = 315,
  D24_D25_D26 = 316,
  D25_D26_D27 = 317,
  D26_D27_D28 = 318,
  D27_D28_D29 = 319,
  D28_D29_D30 = 320,
  D29_D30_D31 = 321,
  D30_D31_D0 = 322,
  D31_D0_D1 = 323,
  Q0_Q1 = 324,
  Q1_Q2 = 325,
  Q2_Q3 = 326,
  Q3_Q4 = 327,
  Q4_Q5 = 328,
  Q5_Q6 = 329,
  Q6_Q7 = 330,
  Q7_Q8 = 331,
  Q8_Q9 = 332,
  Q9_Q10 = 333,
  Q10_Q11 = 334,
  Q11_Q12 = 335,
  Q12_Q13 = 336,
  Q13_Q14 = 337,
  Q14_Q15 = 338,
  Q15_Q16 = 339,
  Q16_Q17 = 340,
  Q17_Q18 = 341,
  Q18_Q19 = 342,
  Q19_Q20 = 343,
  Q20_Q21 = 344,
  Q21_Q22 = 345,
  Q22_Q23 = 346,
  Q23_Q24 = 347,
  Q24_Q25 = 348,
  Q25_Q26 = 349,
  Q26_Q27 = 350,
  Q27_Q28 = 351,
  Q28_Q29 = 352,
  Q29_Q30 = 353,
  Q30_Q31 = 354,
  Q31_Q0 = 355,
  Q0_Q1_Q2_Q3 = 356,
  Q1_Q2_Q3_Q4 = 357,
  Q2_Q3_Q4_Q5 = 358,
  Q3_Q4_Q5_Q6 = 359,
  Q4_Q5_Q6_Q7 = 360,
  Q5_Q6_Q7_Q8 = 361,
  Q6_Q7_Q8_Q9 = 362,
  Q7_Q8_Q9_Q10 = 363,
  Q8_Q9_Q10_Q11 = 364,
  Q9_Q10_Q11_Q12 = 365,
  Q10_Q11_Q12_Q13 = 366,
  Q11_Q12_Q13_Q14 = 367,
  Q12_Q13_Q14_Q15 = 368,
  Q13_Q14_Q15_Q16 = 369,
  Q14_Q15_Q16_Q17 = 370,
  Q15_Q16_Q17_Q18 = 371,
  Q16_Q17_Q18_Q19 = 372,
  Q17_Q18_Q19_Q20 = 373,
  Q18_Q19_Q20_Q21 = 374,
  Q19_Q20_Q21_Q22 = 375,
  Q20_Q21_Q22_Q23 = 376,
  Q21_Q22_Q23_Q24 = 377,
  Q22_Q23_Q24_Q25 = 378,
  Q23_Q24_Q25_Q26 = 379,
  Q24_Q25_Q26_Q27 = 380,
  Q25_Q26_Q27_Q28 = 381,
  Q26_Q27_Q28_Q29 = 382,
  Q27_Q28_Q29_Q30 = 383,
  Q28_Q29_Q30_Q31 = 384,
  Q29_Q30_Q31_Q0 = 385,
  Q30_Q31_Q0_Q1 = 386,
  Q31_Q0_Q1_Q2 = 387,
  Q0_Q1_Q2 = 388,
  Q1_Q2_Q3 = 389,
  Q2_Q3_Q4 = 390,
  Q3_Q4_Q5 = 391,
  Q4_Q5_Q6 = 392,
  Q5_Q6_Q7 = 393,
  Q6_Q7_Q8 = 394,
  Q7_Q8_Q9 = 395,
  Q8_Q9_Q10 = 396,
  Q9_Q10_Q11 = 397,
  Q10_Q11_Q12 = 398,
  Q11_Q12_Q13 = 399,
  Q12_Q13_Q14 = 400,
  Q13_Q14_Q15 = 401,
  Q14_Q15_Q16 = 402,
  Q15_Q16_Q17 = 403,
  Q16_Q17_Q18 = 404,
  Q17_Q18_Q19 = 405,
  Q18_Q19_Q20 = 406,
  Q19_Q20_Q21 = 407,
  Q20_Q21_Q22 = 408,
  Q21_Q22_Q23 = 409,
  Q22_Q23_Q24 = 410,
  Q23_Q24_Q25 = 411,
  Q24_Q25_Q26 = 412,
  Q25_Q26_Q27 = 413,
  Q26_Q27_Q28 = 414,
  Q27_Q28_Q29 = 415,
  Q28_Q29_Q30 = 416,
  Q29_Q30_Q31 = 417,
  Q30_Q31_Q0 = 418,
  Q31_Q0_Q1 = 419,
  WZR_W0 = 420,
  W30_WZR = 421,
  W0_W1 = 422,
  W1_W2 = 423,
  W2_W3 = 424,
  W3_W4 = 425,
  W4_W5 = 426,
  W5_W6 = 427,
  W6_W7 = 428,
  W7_W8 = 429,
  W8_W9 = 430,
  W9_W10 = 431,
  W10_W11 = 432,
  W11_W12 = 433,
  W12_W13 = 434,
  W13_W14 = 435,
  W14_W15 = 436,
  W15_W16 = 437,
  W16_W17 = 438,
  W17_W18 = 439,
  W18_W19 = 440,
  W19_W20 = 441,
  W20_W21 = 442,
  W21_W22 = 443,
  W22_W23 = 444,
  W23_W24 = 445,
  W24_W25 = 446,
  W25_W26 = 447,
  W26_W27 = 448,
  W27_W28 = 449,
  W28_W29 = 450,
  W29_W30 = 451,
  FP_LR = 452,
  LR_XZR = 453,
  XZR_X0 = 454,
  X28_FP = 455,
  X0_X1 = 456,
  X1_X2 = 457,
  X2_X3 = 458,
  X3_X4 = 459,
  X4_X5 = 460,
  X5_X6 = 461,
  X6_X7 = 462,
  X7_X8 = 463,
  X8_X9 = 464,
  X9_X10 = 465,
  X10_X11 = 466,
  X11_X12 = 467,
  X12_X13 = 468,
  X13_X14 = 469,
  X14_X15 = 470,
  X15_X16 = 471,
  X16_X17 = 472,
  X17_X18 = 473,
  X18_X19 = 474,
  X19_X20 = 475,
  X20_X21 = 476,
  X21_X22 = 477,
  X22_X23 = 478,
  X23_X24 = 479,
  X24_X25 = 480,
  X25_X26 = 481,
  X26_X27 = 482,
  X27_X28 = 483,
  NUM_TARGET_REGS   // 484
};
}

// Register classes
namespace AArch64 {
enum {
  FPR8RegClassID = 0,
  FPR16RegClassID = 1,
  GPR32allRegClassID = 2,
  FPR32RegClassID = 3,
  GPR32RegClassID = 4,
  GPR32spRegClassID = 5,
  GPR32commonRegClassID = 6,
  CCRRegClassID = 7,
  GPR32sponlyRegClassID = 8,
  WSeqPairsClassRegClassID = 9,
  WSeqPairsClass_with_sube32_in_GPR32commonRegClassID = 10,
  WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 11,
  WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID = 12,
  GPR64allRegClassID = 13,
  FPR64RegClassID = 14,
  GPR64RegClassID = 15,
  GPR64spRegClassID = 16,
  GPR64commonRegClassID = 17,
  tcGPR64RegClassID = 18,
  GPR64sponlyRegClassID = 19,
  DDRegClassID = 20,
  XSeqPairsClassRegClassID = 21,
  XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID = 22,
  XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 23,
  XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID = 24,
  XSeqPairsClass_with_sube64_in_tcGPR64RegClassID = 25,
  XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 26,
  XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID = 27,
  FPR128RegClassID = 28,
  FPR128_loRegClassID = 29,
  DDDRegClassID = 30,
  DDDDRegClassID = 31,
  QQRegClassID = 32,
  QQ_with_qsub0_in_FPR128_loRegClassID = 33,
  QQ_with_qsub1_in_FPR128_loRegClassID = 34,
  QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID = 35,
  QQQRegClassID = 36,
  QQQ_with_qsub0_in_FPR128_loRegClassID = 37,
  QQQ_with_qsub1_in_FPR128_loRegClassID = 38,
  QQQ_with_qsub2_in_FPR128_loRegClassID = 39,
  QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID = 40,
  QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 41,
  QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID = 42,
  QQQQRegClassID = 43,
  QQQQ_with_qsub0_in_FPR128_loRegClassID = 44,
  QQQQ_with_qsub1_in_FPR128_loRegClassID = 45,
  QQQQ_with_qsub2_in_FPR128_loRegClassID = 46,
  QQQQ_with_qsub3_in_FPR128_loRegClassID = 47,
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID = 48,
  QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 49,
  QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 50,
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID = 51,
  QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 52,
  QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID = 53,

  };
}

// Register alternate name indices
namespace AArch64 {
enum {
  NoRegAltName, // 0
  vlist1, // 1
  vreg, // 2
  NUM_TARGET_REG_ALT_NAMES = 3
};
}

// Subregister indices
namespace AArch64 {
enum {
  NoSubRegister,
  bsub, // 1
  dsub, // 2
  dsub0,  // 3
  dsub1,  // 4
  dsub2,  // 5
  dsub3,  // 6
  hsub, // 7
  qhisub, // 8
  qsub, // 9
  qsub0,  // 10
  qsub1,  // 11
  qsub2,  // 12
  qsub3,  // 13
  ssub, // 14
  sub_32, // 15
  sube32, // 16
  sube64, // 17
  subo32, // 18
  subo64, // 19
  dsub1_then_bsub,  // 20
  dsub1_then_hsub,  // 21
  dsub1_then_ssub,  // 22
  dsub3_then_bsub,  // 23
  dsub3_then_hsub,  // 24
  dsub3_then_ssub,  // 25
  dsub2_then_bsub,  // 26
  dsub2_then_hsub,  // 27
  dsub2_then_ssub,  // 28
  qsub1_then_bsub,  // 29
  qsub1_then_dsub,  // 30
  qsub1_then_hsub,  // 31
  qsub1_then_ssub,  // 32
  qsub3_then_bsub,  // 33
  qsub3_then_dsub,  // 34
  qsub3_then_hsub,  // 35
  qsub3_then_ssub,  // 36
  qsub2_then_bsub,  // 37
  qsub2_then_dsub,  // 38
  qsub2_then_hsub,  // 39
  qsub2_then_ssub,  // 40
  subo64_then_sub_32, // 41
  dsub0_dsub1,  // 42
  dsub0_dsub1_dsub2,  // 43
  dsub1_dsub2,  // 44
  dsub1_dsub2_dsub3,  // 45
  dsub2_dsub3,  // 46
  dsub_qsub1_then_dsub, // 47
  dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub, // 48
  dsub_qsub1_then_dsub_qsub2_then_dsub, // 49
  qsub0_qsub1,  // 50
  qsub0_qsub1_qsub2,  // 51
  qsub1_qsub2,  // 52
  qsub1_qsub2_qsub3,  // 53
  qsub2_qsub3,  // 54
  qsub1_then_dsub_qsub2_then_dsub,  // 55
  qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub,  // 56
  qsub2_then_dsub_qsub3_then_dsub,  // 57
  sub_32_subo64_then_sub_32,  // 58
  NUM_TARGET_SUBREGS
};
}
} // End llvm namespace
#endif // GET_REGINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|* MC Register Information                                                    *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
namespace llvm_ks {

extern const MCPhysReg AArch64RegDiffLists[] = {
  /* 0 */ 0, 1, 0,
  /* 3 */ 65185, 1, 1, 1, 0,
  /* 8 */ 65281, 1, 1, 1, 0,
  /* 13 */ 5, 29, 1, 1, 0,
  /* 18 */ 65340, 419, 30, 1, 1, 0,
  /* 24 */ 65153, 1, 1, 0,
  /* 28 */ 65249, 1, 1, 0,
  /* 32 */ 5, 1, 29, 1, 0,
  /* 37 */ 5, 30, 1, 0,
  /* 41 */ 1, 413, 1, 32, 1, 0,
  /* 47 */ 31, 222, 1, 33, 1, 0,
  /* 53 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 218, 1, 0,
  /* 68 */ 65284, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 250, 1, 0,
  /* 83 */ 256, 1, 0,
  /* 86 */ 446, 1, 0,
  /* 89 */ 450, 1, 0,
  /* 92 */ 65117, 1, 0,
  /* 95 */ 65151, 1, 0,
  /* 98 */ 65217, 1, 0,
  /* 101 */ 65282, 1, 0,
  /* 104 */ 65313, 1, 0,
  /* 107 */ 64, 64, 65440, 64, 123, 1, 62, 65503, 34, 65503, 34, 65503, 1, 63, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
  /* 130 */ 219, 1, 62, 65503, 34, 65503, 34, 65503, 1, 0,
  /* 140 */ 64, 64, 65440, 64, 124, 31, 33, 65504, 62, 65503, 34, 65503, 1, 33, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
  /* 163 */ 220, 31, 33, 65504, 62, 65503, 34, 65503, 1, 0,
  /* 173 */ 63, 65503, 34, 65503, 1, 64, 63, 65503, 34, 65503, 1, 0,
  /* 185 */ 64, 64, 65440, 64, 123, 1, 63, 1, 65503, 1, 62, 65503, 1, 33, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
  /* 208 */ 219, 1, 63, 1, 65503, 1, 62, 65503, 1, 0,
  /* 218 */ 64, 65504, 63, 65503, 1, 33, 64, 65504, 63, 65503, 1, 0,
  /* 230 */ 65503, 1, 128, 65503, 1, 0,
  /* 236 */ 31, 221, 2, 32, 2, 0,
  /* 242 */ 255, 2, 0,
  /* 245 */ 65340, 449, 1, 1, 3, 0,
  /* 251 */ 451, 3, 0,
  /* 254 */ 65084, 3, 0,
  /* 257 */ 4, 0,
  /* 259 */ 5, 0,
  /* 261 */ 31, 222, 1, 5, 28, 0,
  /* 267 */ 228, 28, 0,
  /* 270 */ 5, 1, 1, 29, 0,
  /* 275 */ 64, 64, 65440, 64, 123, 1, 62, 1, 65503, 34, 65503, 1, 29, 34, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
  /* 298 */ 219, 1, 62, 1, 65503, 34, 65503, 1, 29, 0,
  /* 308 */ 5, 1, 30, 0,
  /* 312 */ 63, 1, 65503, 1, 30, 34, 63, 1, 65503, 1, 30, 0,
  /* 324 */ 5, 31, 0,
  /* 327 */ 65504, 31, 97, 65504, 31, 0,
  /* 333 */ 32, 0,
  /* 335 */ 4, 33, 0,
  /* 338 */ 64178, 33, 0,
  /* 341 */ 34, 0,
  /* 343 */ 0, 65, 0,
  /* 346 */ 96, 0,
  /* 348 */ 65122, 162, 0,
  /* 351 */ 196, 0,
  /* 353 */ 65316, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 219, 0,
  /* 365 */ 65316, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 251, 0,
  /* 377 */ 65089, 65535, 193, 65505, 252, 0,
  /* 383 */ 65085, 196, 65341, 196, 253, 0,
  /* 389 */ 65308, 65505, 65341, 196, 253, 0,
  /* 395 */ 65279, 65505, 32, 65505, 253, 0,
  /* 401 */ 65085, 196, 65345, 65535, 415, 0,
  /* 407 */ 65339, 0,
  /* 409 */ 65313, 65344, 0,
  /* 412 */ 65374, 0,
  /* 414 */ 65405, 0,
  /* 416 */ 65437, 0,
  /* 418 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 218, 64, 32, 1, 65440, 0,
  /* 439 */ 65252, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 250, 64, 32, 1, 65440, 0,
  /* 460 */ 65252, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 250, 64, 32, 65505, 65440, 0,
  /* 481 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65441, 65471, 64, 65441, 0,
  /* 513 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65473, 64, 65441, 0,
  /* 535 */ 65469, 0,
  /* 537 */ 65348, 96, 65472, 65472, 1, 96, 65472, 65472, 0,
  /* 546 */ 65348, 96, 65472, 65472, 33, 96, 65472, 65472, 0,
  /* 555 */ 65472, 96, 65472, 65472, 0,
  /* 560 */ 65284, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65441, 64, 65473, 65439, 64, 65473, 0,
  /* 592 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 217, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
  /* 624 */ 65284, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 97, 65472, 96, 65472, 65472, 65, 65472, 96, 65472, 65472, 249, 32, 32, 32, 64, 65473, 64, 65473, 65439, 64, 65473, 0,
  /* 656 */ 65316, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 249, 64, 65441, 64, 65473, 0,
  /* 678 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 217, 64, 65473, 64, 65473, 0,
  /* 700 */ 65316, 96, 65472, 65472, 33, 96, 65472, 65472, 33, 96, 65472, 65472, 1, 96, 65472, 65472, 249, 64, 65473, 64, 65473, 0,
  /* 722 */ 65501, 0,
  /* 724 */ 65284, 96, 65472, 65472, 1, 96, 65472, 65472, 33, 96, 65472, 65472, 250, 65505, 0,
  /* 739 */ 65533, 0,
  /* 741 */ 65535, 0,
};

extern const unsigned AArch64LaneMaskLists[] = {
  /* 0 */ 0x00000000, ~0u,
  /* 2 */ 0x00000040, 0x00000001, ~0u,
  /* 5 */ 0x00000040, 0x00000100, 0x00000080, 0x00000001, ~0u,
  /* 10 */ 0x00000040, 0x00000100, 0x00000001, ~0u,
  /* 14 */ 0x00000200, 0x00000001, ~0u,
  /* 17 */ 0x00000200, 0x00000800, 0x00000400, 0x00000001, ~0u,
  /* 22 */ 0x00000200, 0x00000800, 0x00000001, ~0u,
  /* 26 */ 0x00001000, 0x00000008, ~0u,
  /* 29 */ 0x00000020, 0x00000010, ~0u,
  /* 32 */ 0x00000010, 0x00000020, ~0u,
  /* 35 */ 0x00000100, 0x00000080, 0x00000001, 0x00000040, ~0u,
  /* 40 */ 0x00000100, 0x00000001, 0x00000040, ~0u,
  /* 44 */ 0x00000001, 0x00000040, 0x00000100, 0x00000080, ~0u,
  /* 49 */ 0x00000080, 0x00000001, 0x00000040, 0x00000100, ~0u,
  /* 54 */ 0x00000800, 0x00000400, 0x00000001, 0x00000200, ~0u,
  /* 59 */ 0x00000800, 0x00000001, 0x00000200, ~0u,
  /* 63 */ 0x00000001, 0x00000200, 0x00000800, 0x00000400, ~0u,
  /* 68 */ 0x00000400, 0x00000001, 0x00000200, 0x00000800, ~0u,
  /* 73 */ 0x00000008, 0x00001000, ~0u,
};

extern const uint16_t AArch64SubRegIdxLists[] = {
  /* 0 */ 2, 14, 7, 1, 0,
  /* 5 */ 15, 0,
  /* 7 */ 16, 18, 0,
  /* 10 */ 3, 14, 7, 1, 4, 22, 21, 20, 0,
  /* 19 */ 3, 14, 7, 1, 4, 22, 21, 20, 5, 28, 27, 26, 42, 44, 0,
  /* 34 */ 3, 14, 7, 1, 4, 22, 21, 20, 5, 28, 27, 26, 6, 25, 24, 23, 42, 43, 44, 45, 46, 0,
  /* 56 */ 10, 2, 14, 7, 1, 11, 30, 32, 31, 29, 47, 0,
  /* 68 */ 10, 2, 14, 7, 1, 11, 30, 32, 31, 29, 12, 38, 40, 39, 37, 47, 49, 50, 52, 55, 0,
  /* 89 */ 10, 2, 14, 7, 1, 11, 30, 32, 31, 29, 12, 38, 40, 39, 37, 13, 34, 36, 35, 33, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 0,
  /* 121 */ 17, 15, 19, 41, 58, 0,
};

extern const MCRegisterInfo::SubRegCoveredBits AArch64SubRegIdxRanges[] = {
  { 65535, 65535 },
  { 0, 8 }, // bsub
  { 0, 32 },  // dsub
  { 0, 64 },  // dsub0
  { 0, 64 },  // dsub1
  { 0, 64 },  // dsub2
  { 0, 64 },  // dsub3
  { 0, 16 },  // hsub
  { 0, 64 },  // qhisub
  { 0, 64 },  // qsub
  { 0, 128 }, // qsub0
  { 0, 128 }, // qsub1
  { 0, 128 }, // qsub2
  { 0, 128 }, // qsub3
  { 0, 32 },  // ssub
  { 0, 32 },  // sub_32
  { 0, 32 },  // sube32
  { 0, 64 },  // sube64
  { 0, 32 },  // subo32
  { 0, 64 },  // subo64
  { 0, 8 }, // dsub1_then_bsub
  { 0, 16 },  // dsub1_then_hsub
  { 0, 32 },  // dsub1_then_ssub
  { 0, 8 }, // dsub3_then_bsub
  { 0, 16 },  // dsub3_then_hsub
  { 0, 32 },  // dsub3_then_ssub
  { 0, 8 }, // dsub2_then_bsub
  { 0, 16 },  // dsub2_then_hsub
  { 0, 32 },  // dsub2_then_ssub
  { 0, 8 }, // qsub1_then_bsub
  { 0, 32 },  // qsub1_then_dsub
  { 0, 16 },  // qsub1_then_hsub
  { 0, 32 },  // qsub1_then_ssub
  { 0, 8 }, // qsub3_then_bsub
  { 0, 32 },  // qsub3_then_dsub
  { 0, 16 },  // qsub3_then_hsub
  { 0, 32 },  // qsub3_then_ssub
  { 0, 8 }, // qsub2_then_bsub
  { 0, 32 },  // qsub2_then_dsub
  { 0, 16 },  // qsub2_then_hsub
  { 0, 32 },  // qsub2_then_ssub
  { 0, 32 },  // subo64_then_sub_32
  { 65535, 128 }, // dsub0_dsub1
  { 65535, 192 }, // dsub0_dsub1_dsub2
  { 65535, 128 }, // dsub1_dsub2
  { 65535, 192 }, // dsub1_dsub2_dsub3
  { 65535, 128 }, // dsub2_dsub3
  { 65535, 64 },  // dsub_qsub1_then_dsub
  { 65535, 128 }, // dsub_qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
  { 65535, 96 },  // dsub_qsub1_then_dsub_qsub2_then_dsub
  { 65535, 256 }, // qsub0_qsub1
  { 65535, 384 }, // qsub0_qsub1_qsub2
  { 65535, 256 }, // qsub1_qsub2
  { 65535, 384 }, // qsub1_qsub2_qsub3
  { 65535, 256 }, // qsub2_qsub3
  { 65535, 64 },  // qsub1_then_dsub_qsub2_then_dsub
  { 65535, 96 },  // qsub1_then_dsub_qsub2_then_dsub_qsub3_then_dsub
  { 65535, 64 },  // qsub2_then_dsub_qsub3_then_dsub
  { 65535, 64 },  // sub_32_subo64_then_sub_32
};

extern const char AArch64RegStrings[] = {
  /* 0 */ 'B', '1', '0', 0,
  /* 4 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
  /* 17 */ 'H', '1', '0', 0,
  /* 21 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
  /* 34 */ 'S', '1', '0', 0,
  /* 38 */ 'W', '9', '_', 'W', '1', '0', 0,
  /* 45 */ 'X', '9', '_', 'X', '1', '0', 0,
  /* 52 */ 'B', '2', '0', 0,
  /* 56 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
  /* 72 */ 'H', '2', '0', 0,
  /* 76 */ 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', 0,
  /* 92 */ 'S', '2', '0', 0,
  /* 96 */ 'W', '1', '9', '_', 'W', '2', '0', 0,
  /* 104 */ 'X', '1', '9', '_', 'X', '2', '0', 0,
  /* 112 */ 'B', '3', '0', 0,
  /* 116 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
  /* 132 */ 'H', '3', '0', 0,
  /* 136 */ 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', 0,
  /* 152 */ 'S', '3', '0', 0,
  /* 156 */ 'W', '2', '9', '_', 'W', '3', '0', 0,
  /* 164 */ 'B', '0', 0,
  /* 167 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', 0,
  /* 182 */ 'H', '0', 0,
  /* 185 */ 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', 0,
  /* 200 */ 'S', '0', 0,
  /* 203 */ 'W', 'Z', 'R', '_', 'W', '0', 0,
  /* 210 */ 'X', 'Z', 'R', '_', 'X', '0', 0,
  /* 217 */ 'B', '1', '1', 0,
  /* 221 */ 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
  /* 235 */ 'H', '1', '1', 0,
  /* 239 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
  /* 253 */ 'S', '1', '1', 0,
  /* 257 */ 'W', '1', '0', '_', 'W', '1', '1', 0,
  /* 265 */ 'X', '1', '0', '_', 'X', '1', '1', 0,
  /* 273 */ 'B', '2', '1', 0,
  /* 277 */ 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
  /* 293 */ 'H', '2', '1', 0,
  /* 297 */ 'Q', '1', '8', '_', 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', 0,
  /* 313 */ 'S', '2', '1', 0,
  /* 317 */ 'W', '2', '0', '_', 'W', '2', '1', 0,
  /* 325 */ 'X', '2', '0', '_', 'X', '2', '1', 0,
  /* 333 */ 'B', '3', '1', 0,
  /* 337 */ 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
  /* 353 */ 'H', '3', '1', 0,
  /* 357 */ 'Q', '2', '8', '_', 'Q', '2', '9', '_', 'Q', '3', '0', '_', 'Q', '3', '1', 0,
  /* 373 */ 'S', '3', '1', 0,
  /* 377 */ 'B', '1', 0,
  /* 380 */ 'D', '3', '0', '_', 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', 0,
  /* 394 */ 'H', '1', 0,
  /* 397 */ 'Q', '3', '0', '_', 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', 0,
  /* 411 */ 'S', '1', 0,
  /* 414 */ 'W', '0', '_', 'W', '1', 0,
  /* 420 */ 'X', '0', '_', 'X', '1', 0,
  /* 426 */ 'B', '1', '2', 0,
  /* 430 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
  /* 445 */ 'H', '1', '2', 0,
  /* 449 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
  /* 464 */ 'S', '1', '2', 0,
  /* 468 */ 'W', '1', '1', '_', 'W', '1', '2', 0,
  /* 476 */ 'X', '1', '1', '_', 'X', '1', '2', 0,
  /* 484 */ 'B', '2', '2', 0,
  /* 488 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
  /* 504 */ 'H', '2', '2', 0,
  /* 508 */ 'Q', '1', '9', '_', 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', 0,
  /* 524 */ 'S', '2', '2', 0,
  /* 528 */ 'W', '2', '1', '_', 'W', '2', '2', 0,
  /* 536 */ 'X', '2', '1', '_', 'X', '2', '2', 0,
  /* 544 */ 'B', '2', 0,
  /* 547 */ 'D', '3', '1', '_', 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
  /* 560 */ 'H', '2', 0,
  /* 563 */ 'Q', '3', '1', '_', 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', 0,
  /* 576 */ 'S', '2', 0,
  /* 579 */ 'W', '1', '_', 'W', '2', 0,
  /* 585 */ 'X', '1', '_', 'X', '2', 0,
  /* 591 */ 'B', '1', '3', 0,
  /* 595 */ 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
  /* 611 */ 'H', '1', '3', 0,
  /* 615 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
  /* 631 */ 'S', '1', '3', 0,
  /* 635 */ 'W', '1', '2', '_', 'W', '1', '3', 0,
  /* 643 */ 'X', '1', '2', '_', 'X', '1', '3', 0,
  /* 651 */ 'B', '2', '3', 0,
  /* 655 */ 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
  /* 671 */ 'H', '2', '3', 0,
  /* 675 */ 'Q', '2', '0', '_', 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', 0,
  /* 691 */ 'S', '2', '3', 0,
  /* 695 */ 'W', '2', '2', '_', 'W', '2', '3', 0,
  /* 703 */ 'X', '2', '2', '_', 'X', '2', '3', 0,
  /* 711 */ 'B', '3', 0,
  /* 714 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
  /* 726 */ 'H', '3', 0,
  /* 729 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
  /* 741 */ 'S', '3', 0,
  /* 744 */ 'W', '2', '_', 'W', '3', 0,
  /* 750 */ 'X', '2', '_', 'X', '3', 0,
  /* 756 */ 'B', '1', '4', 0,
  /* 760 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
  /* 776 */ 'H', '1', '4', 0,
  /* 780 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
  /* 796 */ 'S', '1', '4', 0,
  /* 800 */ 'W', '1', '3', '_', 'W', '1', '4', 0,
  /* 808 */ 'X', '1', '3', '_', 'X', '1', '4', 0,
  /* 816 */ 'B', '2', '4', 0,
  /* 820 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
  /* 836 */ 'H', '2', '4', 0,
  /* 840 */ 'Q', '2', '1', '_', 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', 0,
  /* 856 */ 'S', '2', '4', 0,
  /* 860 */ 'W', '2', '3', '_', 'W', '2', '4', 0,
  /* 868 */ 'X', '2', '3', '_', 'X', '2', '4', 0,
  /* 876 */ 'B', '4', 0,
  /* 879 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
  /* 891 */ 'H', '4', 0,
  /* 894 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
  /* 906 */ 'S', '4', 0,
  /* 909 */ 'W', '3', '_', 'W', '4', 0,
  /* 915 */ 'X', '3', '_', 'X', '4', 0,
  /* 921 */ 'B', '1', '5', 0,
  /* 925 */ 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
  /* 941 */ 'H', '1', '5', 0,
  /* 945 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
  /* 961 */ 'S', '1', '5', 0,
  /* 965 */ 'W', '1', '4', '_', 'W', '1', '5', 0,
  /* 973 */ 'X', '1', '4', '_', 'X', '1', '5', 0,
  /* 981 */ 'B', '2', '5', 0,
  /* 985 */ 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
  /* 1001 */ 'H', '2', '5', 0,
  /* 1005 */ 'Q', '2', '2', '_', 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', 0,
  /* 1021 */ 'S', '2', '5', 0,
  /* 1025 */ 'W', '2', '4', '_', 'W', '2', '5', 0,
  /* 1033 */ 'X', '2', '4', '_', 'X', '2', '5', 0,
  /* 1041 */ 'B', '5', 0,
  /* 1044 */ 'D', '2', '_', 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
  /* 1056 */ 'H', '5', 0,
  /* 1059 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
  /* 1071 */ 'S', '5', 0,
  /* 1074 */ 'W', '4', '_', 'W', '5', 0,
  /* 1080 */ 'X', '4', '_', 'X', '5', 0,
  /* 1086 */ 'B', '1', '6', 0,
  /* 1090 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
  /* 1106 */ 'H', '1', '6', 0,
  /* 1110 */ 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', 0,
  /* 1126 */ 'S', '1', '6', 0,
  /* 1130 */ 'W', '1', '5', '_', 'W', '1', '6', 0,
  /* 1138 */ 'X', '1', '5', '_', 'X', '1', '6', 0,
  /* 1146 */ 'B', '2', '6', 0,
  /* 1150 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
  /* 1166 */ 'H', '2', '6', 0,
  /* 1170 */ 'Q', '2', '3', '_', 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', 0,
  /* 1186 */ 'S', '2', '6', 0,
  /* 1190 */ 'W', '2', '5', '_', 'W', '2', '6', 0,
  /* 1198 */ 'X', '2', '5', '_', 'X', '2', '6', 0,
  /* 1206 */ 'B', '6', 0,
  /* 1209 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
  /* 1221 */ 'H', '6', 0,
  /* 1224 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
  /* 1236 */ 'S', '6', 0,
  /* 1239 */ 'W', '5', '_', 'W', '6', 0,
  /* 1245 */ 'X', '5', '_', 'X', '6', 0,
  /* 1251 */ 'B', '1', '7', 0,
  /* 1255 */ 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
  /* 1271 */ 'H', '1', '7', 0,
  /* 1275 */ 'Q', '1', '4', '_', 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', 0,
  /* 1291 */ 'S', '1', '7', 0,
  /* 1295 */ 'W', '1', '6', '_', 'W', '1', '7', 0,
  /* 1303 */ 'X', '1', '6', '_', 'X', '1', '7', 0,
  /* 1311 */ 'B', '2', '7', 0,
  /* 1315 */ 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
  /* 1331 */ 'H', '2', '7', 0,
  /* 1335 */ 'Q', '2', '4', '_', 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', 0,
  /* 1351 */ 'S', '2', '7', 0,
  /* 1355 */ 'W', '2', '6', '_', 'W', '2', '7', 0,
  /* 1363 */ 'X', '2', '6', '_', 'X', '2', '7', 0,
  /* 1371 */ 'B', '7', 0,
  /* 1374 */ 'D', '4', '_', 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
  /* 1386 */ 'H', '7', 0,
  /* 1389 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
  /* 1401 */ 'S', '7', 0,
  /* 1404 */ 'W', '6', '_', 'W', '7', 0,
  /* 1410 */ 'X', '6', '_', 'X', '7', 0,
  /* 1416 */ 'B', '1', '8', 0,
  /* 1420 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
  /* 1436 */ 'H', '1', '8', 0,
  /* 1440 */ 'Q', '1', '5', '_', 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', 0,
  /* 1456 */ 'S', '1', '8', 0,
  /* 1460 */ 'W', '1', '7', '_', 'W', '1', '8', 0,
  /* 1468 */ 'X', '1', '7', '_', 'X', '1', '8', 0,
  /* 1476 */ 'B', '2', '8', 0,
  /* 1480 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
  /* 1496 */ 'H', '2', '8', 0,
  /* 1500 */ 'Q', '2', '5', '_', 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', 0,
  /* 1516 */ 'S', '2', '8', 0,
  /* 1520 */ 'W', '2', '7', '_', 'W', '2', '8', 0,
  /* 1528 */ 'X', '2', '7', '_', 'X', '2', '8', 0,
  /* 1536 */ 'B', '8', 0,
  /* 1539 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
  /* 1551 */ 'H', '8', 0,
  /* 1554 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
  /* 1566 */ 'S', '8', 0,
  /* 1569 */ 'W', '7', '_', 'W', '8', 0,
  /* 1575 */ 'X', '7', '_', 'X', '8', 0,
  /* 1581 */ 'B', '1', '9', 0,
  /* 1585 */ 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
  /* 1601 */ 'H', '1', '9', 0,
  /* 1605 */ 'Q', '1', '6', '_', 'Q', '1', '7', '_', 'Q', '1', '8', '_', 'Q', '1', '9', 0,
  /* 1621 */ 'S', '1', '9', 0,
  /* 1625 */ 'W', '1', '8', '_', 'W', '1', '9', 0,
  /* 1633 */ 'X', '1', '8', '_', 'X', '1', '9', 0,
  /* 1641 */ 'B', '2', '9', 0,
  /* 1645 */ 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
  /* 1661 */ 'H', '2', '9', 0,
  /* 1665 */ 'Q', '2', '6', '_', 'Q', '2', '7', '_', 'Q', '2', '8', '_', 'Q', '2', '9', 0,
  /* 1681 */ 'S', '2', '9', 0,
  /* 1685 */ 'W', '2', '8', '_', 'W', '2', '9', 0,
  /* 1693 */ 'B', '9', 0,
  /* 1696 */ 'D', '6', '_', 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
  /* 1708 */ 'H', '9', 0,
  /* 1711 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
  /* 1723 */ 'S', '9', 0,
  /* 1726 */ 'W', '8', '_', 'W', '9', 0,
  /* 1732 */ 'X', '8', '_', 'X', '9', 0,
  /* 1738 */ 'X', '2', '8', '_', 'F', 'P', 0,
  /* 1745 */ 'W', 'S', 'P', 0,
  /* 1749 */ 'F', 'P', '_', 'L', 'R', 0,
  /* 1755 */ 'W', '3', '0', '_', 'W', 'Z', 'R', 0,
  /* 1763 */ 'L', 'R', '_', 'X', 'Z', 'R', 0,
  /* 1770 */ 'N', 'Z', 'C', 'V', 0,
};

extern const MCRegisterDesc AArch64RegDesc[] = { // Descriptors
  { 3, 0, 0, 0, 0, 0 },
  { 1742, 351, 251, 5, 11857, 27 },
  { 1752, 351, 89, 5, 11857, 27 },
  { 1770, 2, 2, 4, 11857, 0 },
  { 1746, 1, 2, 5, 3984, 27 },
  { 1745, 2, 741, 4, 3984, 0 },
  { 1759, 2, 41, 4, 4112, 0 },
  { 1766, 741, 86, 5, 4112, 27 },
  { 164, 2, 140, 4, 11825, 0 },
  { 377, 2, 185, 4, 11825, 0 },
  { 544, 2, 275, 4, 11825, 0 },
  { 711, 2, 107, 4, 11825, 0 },
  { 876, 2, 107, 4, 11825, 0 },
  { 1041, 2, 107, 4, 11825, 0 },
  { 1206, 2, 107, 4, 11825, 0 },
  { 1371, 2, 107, 4, 11825, 0 },
  { 1536, 2, 107, 4, 11825, 0 },
  { 1693, 2, 107, 4, 11825, 0 },
  { 0, 2, 107, 4, 11825, 0 },
  { 217, 2, 107, 4, 11825, 0 },
  { 426, 2, 107, 4, 11825, 0 },
  { 591, 2, 107, 4, 11825, 0 },
  { 756, 2, 107, 4, 11825, 0 },
  { 921, 2, 107, 4, 11825, 0 },
  { 1086, 2, 107, 4, 11825, 0 },
  { 1251, 2, 107, 4, 11825, 0 },
  { 1416, 2, 107, 4, 11825, 0 },
  { 1581, 2, 107, 4, 11825, 0 },
  { 52, 2, 107, 4, 11825, 0 },
  { 273, 2, 107, 4, 11825, 0 },
  { 484, 2, 107, 4, 11825, 0 },
  { 651, 2, 107, 4, 11825, 0 },
  { 816, 2, 107, 4, 11825, 0 },
  { 981, 2, 107, 4, 11825, 0 },
  { 1146, 2, 107, 4, 11825, 0 },
  { 1311, 2, 107, 4, 11825, 0 },
  { 1476, 2, 107, 4, 11825, 0 },
  { 1641, 2, 107, 4, 11825, 0 },
  { 112, 2, 107, 4, 11825, 0 },
  { 333, 2, 107, 4, 11825, 0 },
  { 179, 542, 143, 1, 11553, 3 },
  { 391, 542, 188, 1, 11553, 3 },
  { 557, 542, 278, 1, 11553, 3 },
  { 723, 542, 110, 1, 11553, 3 },
  { 888, 542, 110, 1, 11553, 3 },
  { 1053, 542, 110, 1, 11553, 3 },
  { 1218, 542, 110, 1, 11553, 3 },
  { 1383, 542, 110, 1, 11553, 3 },
  { 1548, 542, 110, 1, 11553, 3 },
  { 1705, 542, 110, 1, 11553, 3 },
  { 13, 542, 110, 1, 11553, 3 },
  { 231, 542, 110, 1, 11553, 3 },
  { 441, 542, 110, 1, 11553, 3 },
  { 607, 542, 110, 1, 11553, 3 },
  { 772, 542, 110, 1, 11553, 3 },
  { 937, 542, 110, 1, 11553, 3 },
  { 1102, 542, 110, 1, 11553, 3 },
  { 1267, 542, 110, 1, 11553, 3 },
  { 1432, 542, 110, 1, 11553, 3 },
  { 1597, 542, 110, 1, 11553, 3 },
  { 68, 542, 110, 1, 11553, 3 },
  { 289, 542, 110, 1, 11553, 3 },
  { 500, 542, 110, 1, 11553, 3 },
  { 667, 542, 110, 1, 11553, 3 },
  { 832, 542, 110, 1, 11553, 3 },
  { 997, 542, 110, 1, 11553, 3 },
  { 1162, 542, 110, 1, 11553, 3 },
  { 1327, 542, 110, 1, 11553, 3 },
  { 1492, 542, 110, 1, 11553, 3 },
  { 1657, 542, 110, 1, 11553, 3 },
  { 128, 542, 110, 1, 11553, 3 },
  { 349, 542, 110, 1, 11553, 3 },
  { 182, 544, 141, 3, 8561, 3 },
  { 394, 544, 186, 3, 8561, 3 },
  { 560, 544, 276, 3, 8561, 3 },
  { 726, 544, 108, 3, 8561, 3 },
  { 891, 544, 108, 3, 8561, 3 },
  { 1056, 544, 108, 3, 8561, 3 },
  { 1221, 544, 108, 3, 8561, 3 },
  { 1386, 544, 108, 3, 8561, 3 },
  { 1551, 544, 108, 3, 8561, 3 },
  { 1708, 544, 108, 3, 8561, 3 },
  { 17, 544, 108, 3, 8561, 3 },
  { 235, 544, 108, 3, 8561, 3 },
  { 445, 544, 108, 3, 8561, 3 },
  { 611, 544, 108, 3, 8561, 3 },
  { 776, 544, 108, 3, 8561, 3 },
  { 941, 544, 108, 3, 8561, 3 },
  { 1106, 544, 108, 3, 8561, 3 },
  { 1271, 544, 108, 3, 8561, 3 },
  { 1436, 544, 108, 3, 8561, 3 },
  { 1601, 544, 108, 3, 8561, 3 },
  { 72, 544, 108, 3, 8561, 3 },
  { 293, 544, 108, 3, 8561, 3 },
  { 504, 544, 108, 3, 8561, 3 },
  { 671, 544, 108, 3, 8561, 3 },
  { 836, 544, 108, 3, 8561, 3 },
  { 1001, 544, 108, 3, 8561, 3 },
  { 1166, 544, 108, 3, 8561, 3 },
  { 1331, 544, 108, 3, 8561, 3 },
  { 1496, 544, 108, 3, 8561, 3 },
  { 1661, 544, 108, 3, 8561, 3 },
  { 132, 544, 108, 3, 8561, 3 },
  { 353, 544, 108, 3, 8561, 3 },
  { 197, 555, 163, 0, 6657, 3 },
  { 408, 555, 208, 0, 6657, 3 },
  { 573, 555, 298, 0, 6657, 3 },
  { 738, 555, 130, 0, 6657, 3 },
  { 903, 555, 130, 0, 6657, 3 },
  { 1068, 555, 130, 0, 6657, 3 },
  { 1233, 555, 130, 0, 6657, 3 },
  { 1398, 555, 130, 0, 6657, 3 },
  { 1563, 555, 130, 0, 6657, 3 },
  { 1720, 555, 130, 0, 6657, 3 },
  { 30, 555, 130, 0, 6657, 3 },
  { 249, 555, 130, 0, 6657, 3 },
  { 460, 555, 130, 0, 6657, 3 },
  { 627, 555, 130, 0, 6657, 3 },
  { 792, 555, 130, 0, 6657, 3 },
  { 957, 555, 130, 0, 6657, 3 },
  { 1122, 555, 130, 0, 6657, 3 },
  { 1287, 555, 130, 0, 6657, 3 },
  { 1452, 555, 130, 0, 6657, 3 },
  { 1617, 555, 130, 0, 6657, 3 },
  { 88, 555, 130, 0, 6657, 3 },
  { 309, 555, 130, 0, 6657, 3 },
  { 520, 555, 130, 0, 6657, 3 },
  { 687, 555, 130, 0, 6657, 3 },
  { 852, 555, 130, 0, 6657, 3 },
  { 1017, 555, 130, 0, 6657, 3 },
  { 1182, 555, 130, 0, 6657, 3 },
  { 1347, 555, 130, 0, 6657, 3 },
  { 1512, 555, 130, 0, 6657, 3 },
  { 1677, 555, 130, 0, 6657, 3 },
  { 148, 555, 130, 0, 6657, 3 },
  { 369, 555, 130, 0, 6657, 3 },
  { 200, 543, 142, 2, 6625, 3 },
  { 411, 543, 187, 2, 6625, 3 },
  { 576, 543, 277, 2, 6625, 3 },
  { 741, 543, 109, 2, 6625, 3 },
  { 906, 543, 109, 2, 6625, 3 },
  { 1071, 543, 109, 2, 6625, 3 },
  { 1236, 543, 109, 2, 6625, 3 },
  { 1401, 543, 109, 2, 6625, 3 },
  { 1566, 543, 109, 2, 6625, 3 },
  { 1723, 543, 109, 2, 6625, 3 },
  { 34, 543, 109, 2, 6625, 3 },
  { 253, 543, 109, 2, 6625, 3 },
  { 464, 543, 109, 2, 6625, 3 },
  { 631, 543, 109, 2, 6625, 3 },
  { 796, 543, 109, 2, 6625, 3 },
  { 961, 543, 109, 2, 6625, 3 },
  { 1126, 543, 109, 2, 6625, 3 },
  { 1291, 543, 109, 2, 6625, 3 },
  { 1456, 543, 109, 2, 6625, 3 },
  { 1621, 543, 109, 2, 6625, 3 },
  { 92, 543, 109, 2, 6625, 3 },
  { 313, 543, 109, 2, 6625, 3 },
  { 524, 543, 109, 2, 6625, 3 },
  { 691, 543, 109, 2, 6625, 3 },
  { 856, 543, 109, 2, 6625, 3 },
  { 1021, 543, 109, 2, 6625, 3 },
  { 1186, 543, 109, 2, 6625, 3 },
  { 1351, 543, 109, 2, 6625, 3 },
  { 1516, 543, 109, 2, 6625, 3 },
  { 1681, 543, 109, 2, 6625, 3 },
  { 152, 543, 109, 2, 6625, 3 },
  { 373, 543, 109, 2, 6625, 3 },
  { 207, 2, 236, 4, 6625, 0 },
  { 417, 2, 47, 4, 6625, 0 },
  { 582, 2, 47, 4, 6625, 0 },
  { 747, 2, 47, 4, 6625, 0 },
  { 912, 2, 47, 4, 6625, 0 },
  { 1077, 2, 47, 4, 6625, 0 },
  { 1242, 2, 47, 4, 6625, 0 },
  { 1407, 2, 47, 4, 6625, 0 },
  { 1572, 2, 47, 4, 6625, 0 },
  { 1729, 2, 47, 4, 6625, 0 },
  { 41, 2, 47, 4, 6625, 0 },
  { 261, 2, 47, 4, 6625, 0 },
  { 472, 2, 47, 4, 6625, 0 },
  { 639, 2, 47, 4, 6625, 0 },
  { 804, 2, 47, 4, 6625, 0 },
  { 969, 2, 47, 4, 6625, 0 },
  { 1134, 2, 47, 4, 6625, 0 },
  { 1299, 2, 47, 4, 6625, 0 },
  { 1464, 2, 47, 4, 6625, 0 },
  { 1629, 2, 47, 4, 6625, 0 },
  { 100, 2, 47, 4, 6625, 0 },
  { 321, 2, 47, 4, 6625, 0 },
  { 532, 2, 47, 4, 6625, 0 },
  { 699, 2, 47, 4, 6625, 0 },
  { 864, 2, 47, 4, 6625, 0 },
  { 1029, 2, 47, 4, 6625, 0 },
  { 1194, 2, 47, 4, 6625, 0 },
  { 1359, 2, 47, 4, 6625, 0 },
  { 1524, 2, 261, 4, 6625, 0 },
  { 1689, 2, 245, 4, 6513, 0 },
  { 160, 2, 18, 4, 6513, 0 },
  { 214, 737, 242, 5, 6593, 27 },
  { 423, 737, 83, 5, 6593, 27 },
  { 588, 737, 83, 5, 6593, 27 },
  { 753, 737, 83, 5, 6593, 27 },
  { 918, 737, 83, 5, 6593, 27 },
  { 1083, 737, 83, 5, 6593, 27 },
  { 1248, 737, 83, 5, 6593, 27 },
  { 1413, 737, 83, 5, 6593, 27 },
  { 1578, 737, 83, 5, 6593, 27 },
  { 1735, 737, 83, 5, 6593, 27 },
  { 48, 737, 83, 5, 6593, 27 },
  { 269, 737, 83, 5, 6593, 27 },
  { 480, 737, 83, 5, 6593, 27 },
  { 647, 737, 83, 5, 6593, 27 },
  { 812, 737, 83, 5, 6593, 27 },
  { 977, 737, 83, 5, 6593, 27 },
  { 1142, 737, 83, 5, 6593, 27 },
  { 1307, 737, 83, 5, 6593, 27 },
  { 1472, 737, 83, 5, 6593, 27 },
  { 1637, 737, 83, 5, 6593, 27 },
  { 108, 737, 83, 5, 6593, 27 },
  { 329, 737, 83, 5, 6593, 27 },
  { 540, 737, 83, 5, 6593, 27 },
  { 707, 737, 83, 5, 6593, 27 },
  { 872, 737, 83, 5, 6593, 27 },
  { 1037, 737, 83, 5, 6593, 27 },
  { 1202, 737, 83, 5, 6593, 27 },
  { 1367, 737, 83, 5, 6593, 27 },
  { 1532, 737, 267, 5, 6593, 27 },
  { 388, 546, 218, 10, 1665, 37 },
  { 554, 546, 312, 10, 1665, 37 },
  { 720, 546, 173, 10, 1665, 37 },
  { 885, 546, 173, 10, 1665, 37 },
  { 1050, 546, 173, 10, 1665, 37 },
  { 1215, 546, 173, 10, 1665, 37 },
  { 1380, 546, 173, 10, 1665, 37 },
  { 1545, 546, 173, 10, 1665, 37 },
  { 1702, 546, 173, 10, 1665, 37 },
  { 10, 546, 173, 10, 1665, 37 },
  { 227, 546, 173, 10, 1665, 37 },
  { 437, 546, 173, 10, 1665, 37 },
  { 603, 546, 173, 10, 1665, 37 },
  { 768, 546, 173, 10, 1665, 37 },
  { 933, 546, 173, 10, 1665, 37 },
  { 1098, 546, 173, 10, 1665, 37 },
  { 1263, 546, 173, 10, 1665, 37 },
  { 1428, 546, 173, 10, 1665, 37 },
  { 1593, 546, 173, 10, 1665, 37 },
  { 64, 546, 173, 10, 1665, 37 },
  { 285, 546, 173, 10, 1665, 37 },
  { 496, 546, 173, 10, 1665, 37 },
  { 663, 546, 173, 10, 1665, 37 },
  { 828, 546, 173, 10, 1665, 37 },
  { 993, 546, 173, 10, 1665, 37 },
  { 1158, 546, 173, 10, 1665, 37 },
  { 1323, 546, 173, 10, 1665, 37 },
  { 1488, 546, 173, 10, 1665, 37 },
  { 1653, 546, 173, 10, 1665, 37 },
  { 124, 546, 173, 10, 1665, 37 },
  { 345, 546, 173, 10, 1665, 37 },
  { 175, 537, 173, 10, 5184, 2 },
  { 714, 678, 346, 34, 129, 44 },
  { 879, 678, 346, 34, 129, 44 },
  { 1044, 678, 346, 34, 129, 44 },
  { 1209, 678, 346, 34, 129, 44 },
  { 1374, 678, 346, 34, 129, 44 },
  { 1539, 678, 346, 34, 129, 44 },
  { 1696, 678, 346, 34, 129, 44 },
  { 4, 678, 346, 34, 129, 44 },
  { 221, 678, 346, 34, 129, 44 },
  { 430, 678, 346, 34, 129, 44 },
  { 595, 678, 346, 34, 129, 44 },
  { 760, 678, 346, 34, 129, 44 },
  { 925, 678, 346, 34, 129, 44 },
  { 1090, 678, 346, 34, 129, 44 },
  { 1255, 678, 346, 34, 129, 44 },
  { 1420, 678, 346, 34, 129, 44 },
  { 1585, 678, 346, 34, 129, 44 },
  { 56, 678, 346, 34, 129, 44 },
  { 277, 678, 346, 34, 129, 44 },
  { 488, 678, 346, 34, 129, 44 },
  { 655, 678, 346, 34, 129, 44 },
  { 820, 678, 346, 34, 129, 44 },
  { 985, 678, 346, 34, 129, 44 },
  { 1150, 678, 346, 34, 129, 44 },
  { 1315, 678, 346, 34, 129, 44 },
  { 1480, 678, 346, 34, 129, 44 },
  { 1645, 678, 346, 34, 129, 44 },
  { 116, 678, 346, 34, 129, 44 },
  { 337, 678, 346, 34, 129, 44 },
  { 167, 700, 346, 34, 208, 49 },
  { 380, 513, 346, 34, 512, 35 },
  { 547, 656, 346, 34, 4320, 5 },
  { 551, 53, 327, 19, 449, 50 },
  { 717, 53, 230, 19, 449, 50 },
  { 882, 53, 230, 19, 449, 50 },
  { 1047, 53, 230, 19, 449, 50 },
  { 1212, 53, 230, 19, 449, 50 },
  { 1377, 53, 230, 19, 449, 50 },
  { 1542, 53, 230, 19, 449, 50 },
  { 1699, 53, 230, 19, 449, 50 },
  { 7, 53, 230, 19, 449, 50 },
  { 224, 53, 230, 19, 449, 50 },
  { 433, 53, 230, 19, 449, 50 },
  { 599, 53, 230, 19, 449, 50 },
  { 764, 53, 230, 19, 449, 50 },
  { 929, 53, 230, 19, 449, 50 },
  { 1094, 53, 230, 19, 449, 50 },
  { 1259, 53, 230, 19, 449, 50 },
  { 1424, 53, 230, 19, 449, 50 },
  { 1589, 53, 230, 19, 449, 50 },
  { 60, 53, 230, 19, 449, 50 },
  { 281, 53, 230, 19, 449, 50 },
  { 492, 53, 230, 19, 449, 50 },
  { 659, 53, 230, 19, 449, 50 },
  { 824, 53, 230, 19, 449, 50 },
  { 989, 53, 230, 19, 449, 50 },
  { 1154, 53, 230, 19, 449, 50 },
  { 1319, 53, 230, 19, 449, 50 },
  { 1484, 53, 230, 19, 449, 50 },
  { 1649, 53, 230, 19, 449, 50 },
  { 120, 53, 230, 19, 449, 50 },
  { 341, 53, 230, 19, 449, 50 },
  { 171, 68, 230, 19, 592, 40 },
  { 384, 724, 230, 19, 4928, 10 },
  { 405, 353, 224, 56, 1569, 56 },
  { 570, 353, 318, 56, 1569, 56 },
  { 735, 353, 179, 56, 1569, 56 },
  { 900, 353, 179, 56, 1569, 56 },
  { 1065, 353, 179, 56, 1569, 56 },
  { 1230, 353, 179, 56, 1569, 56 },
  { 1395, 353, 179, 56, 1569, 56 },
  { 1560, 353, 179, 56, 1569, 56 },
  { 1717, 353, 179, 56, 1569, 56 },
  { 27, 353, 179, 56, 1569, 56 },
  { 245, 353, 179, 56, 1569, 56 },
  { 456, 353, 179, 56, 1569, 56 },
  { 623, 353, 179, 56, 1569, 56 },
  { 788, 353, 179, 56, 1569, 56 },
  { 953, 353, 179, 56, 1569, 56 },
  { 1118, 353, 179, 56, 1569, 56 },
  { 1283, 353, 179, 56, 1569, 56 },
  { 1448, 353, 179, 56, 1569, 56 },
  { 1613, 353, 179, 56, 1569, 56 },
  { 84, 353, 179, 56, 1569, 56 },
  { 305, 353, 179, 56, 1569, 56 },
  { 516, 353, 179, 56, 1569, 56 },
  { 683, 353, 179, 56, 1569, 56 },
  { 848, 353, 179, 56, 1569, 56 },
  { 1013, 353, 179, 56, 1569, 56 },
  { 1178, 353, 179, 56, 1569, 56 },
  { 1343, 353, 179, 56, 1569, 56 },
  { 1508, 353, 179, 56, 1569, 56 },
  { 1673, 353, 179, 56, 1569, 56 },
  { 144, 353, 179, 56, 1569, 56 },
  { 365, 353, 179, 56, 1569, 56 },
  { 193, 365, 179, 56, 5184, 14 },
  { 729, 592, 2, 89, 49, 63 },
  { 894, 592, 2, 89, 49, 63 },
  { 1059, 592, 2, 89, 49, 63 },
  { 1224, 592, 2, 89, 49, 63 },
  { 1389, 592, 2, 89, 49, 63 },
  { 1554, 592, 2, 89, 49, 63 },
  { 1711, 592, 2, 89, 49, 63 },
  { 21, 592, 2, 89, 49, 63 },
  { 239, 592, 2, 89, 49, 63 },
  { 449, 592, 2, 89, 49, 63 },
  { 615, 592, 2, 89, 49, 63 },
  { 780, 592, 2, 89, 49, 63 },
  { 945, 592, 2, 89, 49, 63 },
  { 1110, 592, 2, 89, 49, 63 },
  { 1275, 592, 2, 89, 49, 63 },
  { 1440, 592, 2, 89, 49, 63 },
  { 1605, 592, 2, 89, 49, 63 },
  { 76, 592, 2, 89, 49, 63 },
  { 297, 592, 2, 89, 49, 63 },
  { 508, 592, 2, 89, 49, 63 },
  { 675, 592, 2, 89, 49, 63 },
  { 840, 592, 2, 89, 49, 63 },
  { 1005, 592, 2, 89, 49, 63 },
  { 1170, 592, 2, 89, 49, 63 },
  { 1335, 592, 2, 89, 49, 63 },
  { 1500, 592, 2, 89, 49, 63 },
  { 1665, 592, 2, 89, 49, 63 },
  { 136, 592, 2, 89, 49, 63 },
  { 357, 592, 2, 89, 49, 63 },
  { 185, 624, 2, 89, 208, 68 },
  { 397, 481, 2, 89, 512, 54 },
  { 563, 560, 2, 89, 4320, 17 },
  { 567, 418, 330, 68, 385, 69 },
  { 732, 418, 127, 68, 385, 69 },
  { 897, 418, 127, 68, 385, 69 },
  { 1062, 418, 127, 68, 385, 69 },
  { 1227, 418, 127, 68, 385, 69 },
  { 1392, 418, 127, 68, 385, 69 },
  { 1557, 418, 127, 68, 385, 69 },
  { 1714, 418, 127, 68, 385, 69 },
  { 24, 418, 127, 68, 385, 69 },
  { 242, 418, 127, 68, 385, 69 },
  { 452, 418, 127, 68, 385, 69 },
  { 619, 418, 127, 68, 385, 69 },
  { 784, 418, 127, 68, 385, 69 },
  { 949, 418, 127, 68, 385, 69 },
  { 1114, 418, 127, 68, 385, 69 },
  { 1279, 418, 127, 68, 385, 69 },
  { 1444, 418, 127, 68, 385, 69 },
  { 1609, 418, 127, 68, 385, 69 },
  { 80, 418, 127, 68, 385, 69 },
  { 301, 418, 127, 68, 385, 69 },
  { 512, 418, 127, 68, 385, 69 },
  { 679, 418, 127, 68, 385, 69 },
  { 844, 418, 127, 68, 385, 69 },
  { 1009, 418, 127, 68, 385, 69 },
  { 1174, 418, 127, 68, 385, 69 },
  { 1339, 418, 127, 68, 385, 69 },
  { 1504, 418, 127, 68, 385, 69 },
  { 1669, 418, 127, 68, 385, 69 },
  { 140, 418, 127, 68, 385, 69 },
  { 361, 418, 127, 68, 385, 69 },
  { 189, 439, 127, 68, 592, 59 },
  { 401, 460, 127, 68, 4928, 22 },
  { 203, 348, 341, 7, 5360, 32 },
  { 1755, 409, 333, 7, 3968, 32 },
  { 414, 101, 341, 7, 1521, 32 },
  { 579, 101, 341, 7, 1521, 32 },
  { 744, 101, 341, 7, 1521, 32 },
  { 909, 101, 341, 7, 1521, 32 },
  { 1074, 101, 341, 7, 1521, 32 },
  { 1239, 101, 341, 7, 1521, 32 },
  { 1404, 101, 341, 7, 1521, 32 },
  { 1569, 101, 341, 7, 1521, 32 },
  { 1726, 101, 341, 7, 1521, 32 },
  { 38, 101, 341, 7, 1521, 32 },
  { 257, 101, 341, 7, 1521, 32 },
  { 468, 101, 341, 7, 1521, 32 },
  { 635, 101, 341, 7, 1521, 32 },
  { 800, 101, 341, 7, 1521, 32 },
  { 965, 101, 341, 7, 1521, 32 },
  { 1130, 101, 341, 7, 1521, 32 },
  { 1295, 101, 341, 7, 1521, 32 },
  { 1460, 101, 341, 7, 1521, 32 },
  { 1625, 101, 341, 7, 1521, 32 },
  { 96, 101, 341, 7, 1521, 32 },
  { 317, 101, 341, 7, 1521, 32 },
  { 528, 101, 341, 7, 1521, 32 },
  { 695, 101, 341, 7, 1521, 32 },
  { 860, 101, 341, 7, 1521, 32 },
  { 1025, 101, 341, 7, 1521, 32 },
  { 1190, 101, 341, 7, 1521, 32 },
  { 1355, 101, 341, 7, 1521, 32 },
  { 1520, 101, 341, 7, 1521, 32 },
  { 1685, 101, 259, 7, 5488, 29 },
  { 156, 101, 1, 7, 0, 32 },
  { 1749, 383, 2, 121, 0, 73 },
  { 1763, 401, 2, 121, 4065, 73 },
  { 210, 377, 2, 121, 5411, 73 },
  { 1738, 389, 2, 121, 5488, 26 },
  { 420, 395, 2, 121, 1473, 73 },
  { 585, 395, 2, 121, 1473, 73 },
  { 750, 395, 2, 121, 1473, 73 },
  { 915, 395, 2, 121, 1473, 73 },
  { 1080, 395, 2, 121, 1473, 73 },
  { 1245, 395, 2, 121, 1473, 73 },
  { 1410, 395, 2, 121, 1473, 73 },
  { 1575, 395, 2, 121, 1473, 73 },
  { 1732, 395, 2, 121, 1473, 73 },
  { 45, 395, 2, 121, 1473, 73 },
  { 265, 395, 2, 121, 1473, 73 },
  { 476, 395, 2, 121, 1473, 73 },
  { 643, 395, 2, 121, 1473, 73 },
  { 808, 395, 2, 121, 1473, 73 },
  { 973, 395, 2, 121, 1473, 73 },
  { 1138, 395, 2, 121, 1473, 73 },
  { 1303, 395, 2, 121, 1473, 73 },
  { 1468, 395, 2, 121, 1473, 73 },
  { 1633, 395, 2, 121, 1473, 73 },
  { 104, 395, 2, 121, 1473, 73 },
  { 325, 395, 2, 121, 1473, 73 },
  { 536, 395, 2, 121, 1473, 73 },
  { 703, 395, 2, 121, 1473, 73 },
  { 868, 395, 2, 121, 1473, 73 },
  { 1033, 395, 2, 121, 1473, 73 },
  { 1198, 395, 2, 121, 1473, 73 },
  { 1363, 395, 2, 121, 1473, 73 },
  { 1528, 395, 2, 121, 1473, 73 },
};

extern const MCPhysReg AArch64RegUnitRoots[][2] = {
  { AArch64::W29 },
  { AArch64::W30 },
  { AArch64::NZCV },
  { AArch64::WSP },
  { AArch64::WZR },
  { AArch64::B0 },
  { AArch64::B1 },
  { AArch64::B2 },
  { AArch64::B3 },
  { AArch64::B4 },
  { AArch64::B5 },
  { AArch64::B6 },
  { AArch64::B7 },
  { AArch64::B8 },
  { AArch64::B9 },
  { AArch64::B10 },
  { AArch64::B11 },
  { AArch64::B12 },
  { AArch64::B13 },
  { AArch64::B14 },
  { AArch64::B15 },
  { AArch64::B16 },
  { AArch64::B17 },
  { AArch64::B18 },
  { AArch64::B19 },
  { AArch64::B20 },
  { AArch64::B21 },
  { AArch64::B22 },
  { AArch64::B23 },
  { AArch64::B24 },
  { AArch64::B25 },
  { AArch64::B26 },
  { AArch64::B27 },
  { AArch64::B28 },
  { AArch64::B29 },
  { AArch64::B30 },
  { AArch64::B31 },
  { AArch64::W0 },
  { AArch64::W1 },
  { AArch64::W2 },
  { AArch64::W3 },
  { AArch64::W4 },
  { AArch64::W5 },
  { AArch64::W6 },
  { AArch64::W7 },
  { AArch64::W8 },
  { AArch64::W9 },
  { AArch64::W10 },
  { AArch64::W11 },
  { AArch64::W12 },
  { AArch64::W13 },
  { AArch64::W14 },
  { AArch64::W15 },
  { AArch64::W16 },
  { AArch64::W17 },
  { AArch64::W18 },
  { AArch64::W19 },
  { AArch64::W20 },
  { AArch64::W21 },
  { AArch64::W22 },
  { AArch64::W23 },
  { AArch64::W24 },
  { AArch64::W25 },
  { AArch64::W26 },
  { AArch64::W27 },
  { AArch64::W28 },
};

namespace {     // Register classes...
  // FPR8 Register Class...
  const MCPhysReg FPR8[] = {
    AArch64::B0, AArch64::B1, AArch64::B2, AArch64::B3, AArch64::B4, AArch64::B5, AArch64::B6, AArch64::B7, AArch64::B8, AArch64::B9, AArch64::B10, AArch64::B11, AArch64::B12, AArch64::B13, AArch64::B14, AArch64::B15, AArch64::B16, AArch64::B17, AArch64::B18, AArch64::B19, AArch64::B20, AArch64::B21, AArch64::B22, AArch64::B23, AArch64::B24, AArch64::B25, AArch64::B26, AArch64::B27, AArch64::B28, AArch64::B29, AArch64::B30, AArch64::B31, 
  };

  // FPR8 Bit set.
  const uint8_t FPR8Bits[] = {
    0x00, 0xff, 0xff, 0xff, 0xff, 
  };

  // FPR16 Register Class...
  const MCPhysReg FPR16[] = {
    AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::H8, AArch64::H9, AArch64::H10, AArch64::H11, AArch64::H12, AArch64::H13, AArch64::H14, AArch64::H15, AArch64::H16, AArch64::H17, AArch64::H18, AArch64::H19, AArch64::H20, AArch64::H21, AArch64::H22, AArch64::H23, AArch64::H24, AArch64::H25, AArch64::H26, AArch64::H27, AArch64::H28, AArch64::H29, AArch64::H30, AArch64::H31, 
  };

  // FPR16 Bit set.
  const uint8_t FPR16Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
  };

  // GPR32all Register Class...
  const MCPhysReg GPR32all[] = {
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, AArch64::WSP, 
  };

  // GPR32all Bit set.
  const uint8_t GPR32allBits[] = {
    0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
  };

  // FPR32 Register Class...
  const MCPhysReg FPR32[] = {
    AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11, AArch64::S12, AArch64::S13, AArch64::S14, AArch64::S15, AArch64::S16, AArch64::S17, AArch64::S18, AArch64::S19, AArch64::S20, AArch64::S21, AArch64::S22, AArch64::S23, AArch64::S24, AArch64::S25, AArch64::S26, AArch64::S27, AArch64::S28, AArch64::S29, AArch64::S30, AArch64::S31, 
  };

  // FPR32 Bit set.
  const uint8_t FPR32Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
  };

  // GPR32 Register Class...
  const MCPhysReg GPR32[] = {
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WZR, 
  };

  // GPR32 Bit set.
  const uint8_t GPR32Bits[] = {
    0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
  };

  // GPR32sp Register Class...
  const MCPhysReg GPR32sp[] = {
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, AArch64::WSP, 
  };

  // GPR32sp Bit set.
  const uint8_t GPR32spBits[] = {
    0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
  };

  // GPR32common Register Class...
  const MCPhysReg GPR32common[] = {
    AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::W8, AArch64::W9, AArch64::W10, AArch64::W11, AArch64::W12, AArch64::W13, AArch64::W14, AArch64::W15, AArch64::W16, AArch64::W17, AArch64::W18, AArch64::W19, AArch64::W20, AArch64::W21, AArch64::W22, AArch64::W23, AArch64::W24, AArch64::W25, AArch64::W26, AArch64::W27, AArch64::W28, AArch64::W29, AArch64::W30, 
  };

  // GPR32common Bit set.
  const uint8_t GPR32commonBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0x7f, 
  };

  // CCR Register Class...
  const MCPhysReg CCR[] = {
    AArch64::NZCV, 
  };

  // CCR Bit set.
  const uint8_t CCRBits[] = {
    0x08, 
  };

  // GPR32sponly Register Class...
  const MCPhysReg GPR32sponly[] = {
    AArch64::WSP, 
  };

  // GPR32sponly Bit set.
  const uint8_t GPR32sponlyBits[] = {
    0x20, 
  };

  // WSeqPairsClass Register Class...
  const MCPhysReg WSeqPairsClass[] = {
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, AArch64::WZR_W0, 
  };

  // WSeqPairsClass Bit set.
  const uint8_t WSeqPairsClassBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // WSeqPairsClass_with_sube32_in_GPR32common Register Class...
  const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common[] = {
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::W30_WZR, 
  };

  // WSeqPairsClass_with_sube32_in_GPR32common Bit set.
  const uint8_t WSeqPairsClass_with_sube32_in_GPR32commonBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // WSeqPairsClass_with_subo32_in_GPR32common Register Class...
  const MCPhysReg WSeqPairsClass_with_subo32_in_GPR32common[] = {
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, AArch64::WZR_W0, 
  };

  // WSeqPairsClass_with_subo32_in_GPR32common Bit set.
  const uint8_t WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Register Class...
  const MCPhysReg WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common[] = {
    AArch64::W0_W1, AArch64::W1_W2, AArch64::W2_W3, AArch64::W3_W4, AArch64::W4_W5, AArch64::W5_W6, AArch64::W6_W7, AArch64::W7_W8, AArch64::W8_W9, AArch64::W9_W10, AArch64::W10_W11, AArch64::W11_W12, AArch64::W12_W13, AArch64::W13_W14, AArch64::W14_W15, AArch64::W15_W16, AArch64::W16_W17, AArch64::W17_W18, AArch64::W18_W19, AArch64::W19_W20, AArch64::W20_W21, AArch64::W21_W22, AArch64::W22_W23, AArch64::W23_W24, AArch64::W24_W25, AArch64::W25_W26, AArch64::W26_W27, AArch64::W27_W28, AArch64::W28_W29, AArch64::W29_W30, 
  };

  // WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common Bit set.
  const uint8_t WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // GPR64all Register Class...
  const MCPhysReg GPR64all[] = {
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, AArch64::SP, 
  };

  // GPR64all Bit set.
  const uint8_t GPR64allBits[] = {
    0x96, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
  };

  // FPR64 Register Class...
  const MCPhysReg FPR64[] = {
    AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::D8, AArch64::D9, AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::D16, AArch64::D17, AArch64::D18, AArch64::D19, AArch64::D20, AArch64::D21, AArch64::D22, AArch64::D23, AArch64::D24, AArch64::D25, AArch64::D26, AArch64::D27, AArch64::D28, AArch64::D29, AArch64::D30, AArch64::D31, 
  };

  // FPR64 Bit set.
  const uint8_t FPR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
  };

  // GPR64 Register Class...
  const MCPhysReg GPR64[] = {
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::XZR, 
  };

  // GPR64 Bit set.
  const uint8_t GPR64Bits[] = {
    0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
  };

  // GPR64sp Register Class...
  const MCPhysReg GPR64sp[] = {
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, AArch64::SP, 
  };

  // GPR64sp Bit set.
  const uint8_t GPR64spBits[] = {
    0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
  };

  // GPR64common Register Class...
  const MCPhysReg GPR64common[] = {
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28, AArch64::FP, AArch64::LR, 
  };

  // GPR64common Bit set.
  const uint8_t GPR64commonBits[] = {
    0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x0f, 
  };

  // tcGPR64 Register Class...
  const MCPhysReg tcGPR64[] = {
    AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::X9, AArch64::X10, AArch64::X11, AArch64::X12, AArch64::X13, AArch64::X14, AArch64::X15, AArch64::X16, AArch64::X17, AArch64::X18, 
  };

  // tcGPR64 Bit set.
  const uint8_t tcGPR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0x03, 
  };

  // GPR64sponly Register Class...
  const MCPhysReg GPR64sponly[] = {
    AArch64::SP, 
  };

  // GPR64sponly Bit set.
  const uint8_t GPR64sponlyBits[] = {
    0x10, 
  };

  // DD Register Class...
  const MCPhysReg DD[] = {
    AArch64::D0_D1, AArch64::D1_D2, AArch64::D2_D3, AArch64::D3_D4, AArch64::D4_D5, AArch64::D5_D6, AArch64::D6_D7, AArch64::D7_D8, AArch64::D8_D9, AArch64::D9_D10, AArch64::D10_D11, AArch64::D11_D12, AArch64::D12_D13, AArch64::D13_D14, AArch64::D14_D15, AArch64::D15_D16, AArch64::D16_D17, AArch64::D17_D18, AArch64::D18_D19, AArch64::D19_D20, AArch64::D20_D21, AArch64::D21_D22, AArch64::D22_D23, AArch64::D23_D24, AArch64::D24_D25, AArch64::D25_D26, AArch64::D26_D27, AArch64::D27_D28, AArch64::D28_D29, AArch64::D29_D30, AArch64::D30_D31, AArch64::D31_D0, 
  };

  // DD Bit set.
  const uint8_t DDBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // XSeqPairsClass Register Class...
  const MCPhysReg XSeqPairsClass[] = {
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, AArch64::XZR_X0, 
  };

  // XSeqPairsClass Bit set.
  const uint8_t XSeqPairsClassBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // XSeqPairsClass_with_sub_32_in_GPR32common Register Class...
  const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common[] = {
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::LR_XZR, 
  };

  // XSeqPairsClass_with_sub_32_in_GPR32common Bit set.
  const uint8_t XSeqPairsClass_with_sub_32_in_GPR32commonBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // XSeqPairsClass_with_subo64_in_GPR64common Register Class...
  const MCPhysReg XSeqPairsClass_with_subo64_in_GPR64common[] = {
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, AArch64::XZR_X0, 
  };

  // XSeqPairsClass_with_subo64_in_GPR64common Bit set.
  const uint8_t XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Register Class...
  const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common[] = {
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, AArch64::X19_X20, AArch64::X20_X21, AArch64::X21_X22, AArch64::X22_X23, AArch64::X23_X24, AArch64::X24_X25, AArch64::X25_X26, AArch64::X26_X27, AArch64::X27_X28, AArch64::X28_FP, AArch64::FP_LR, 
  };

  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common Bit set.
  const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x90, 0xff, 0xff, 0xff, 0x0f, 
  };

  // XSeqPairsClass_with_sube64_in_tcGPR64 Register Class...
  const MCPhysReg XSeqPairsClass_with_sube64_in_tcGPR64[] = {
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::X18_X19, 
  };

  // XSeqPairsClass_with_sube64_in_tcGPR64 Bit set.
  const uint8_t XSeqPairsClass_with_sube64_in_tcGPR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x07, 
  };

  // XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
  const MCPhysReg XSeqPairsClass_with_subo64_in_tcGPR64[] = {
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, AArch64::XZR_X0, 
  };

  // XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
  const uint8_t XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0xff, 0xff, 0x03, 
  };

  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Register Class...
  const MCPhysReg XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64[] = {
    AArch64::X0_X1, AArch64::X1_X2, AArch64::X2_X3, AArch64::X3_X4, AArch64::X4_X5, AArch64::X5_X6, AArch64::X6_X7, AArch64::X7_X8, AArch64::X8_X9, AArch64::X9_X10, AArch64::X10_X11, AArch64::X11_X12, AArch64::X12_X13, AArch64::X13_X14, AArch64::X14_X15, AArch64::X15_X16, AArch64::X16_X17, AArch64::X17_X18, 
  };

  // XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64 Bit set.
  const uint8_t XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0x03, 
  };

  // FPR128 Register Class...
  const MCPhysReg FPR128[] = {
    AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, AArch64::Q16, AArch64::Q17, AArch64::Q18, AArch64::Q19, AArch64::Q20, AArch64::Q21, AArch64::Q22, AArch64::Q23, AArch64::Q24, AArch64::Q25, AArch64::Q26, AArch64::Q27, AArch64::Q28, AArch64::Q29, AArch64::Q30, AArch64::Q31, 
  };

  // FPR128 Bit set.
  const uint8_t FPR128Bits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 
  };

  // FPR128_lo Register Class...
  const MCPhysReg FPR128_lo[] = {
    AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::Q8, AArch64::Q9, AArch64::Q10, AArch64::Q11, AArch64::Q12, AArch64::Q13, AArch64::Q14, AArch64::Q15, 
  };

  // FPR128_lo Bit set.
  const uint8_t FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 
  };

  // DDD Register Class...
  const MCPhysReg DDD[] = {
    AArch64::D0_D1_D2, AArch64::D1_D2_D3, AArch64::D2_D3_D4, AArch64::D3_D4_D5, AArch64::D4_D5_D6, AArch64::D5_D6_D7, AArch64::D6_D7_D8, AArch64::D7_D8_D9, AArch64::D8_D9_D10, AArch64::D9_D10_D11, AArch64::D10_D11_D12, AArch64::D11_D12_D13, AArch64::D12_D13_D14, AArch64::D13_D14_D15, AArch64::D14_D15_D16, AArch64::D15_D16_D17, AArch64::D16_D17_D18, AArch64::D17_D18_D19, AArch64::D18_D19_D20, AArch64::D19_D20_D21, AArch64::D20_D21_D22, AArch64::D21_D22_D23, AArch64::D22_D23_D24, AArch64::D23_D24_D25, AArch64::D24_D25_D26, AArch64::D25_D26_D27, AArch64::D26_D27_D28, AArch64::D27_D28_D29, AArch64::D28_D29_D30, AArch64::D29_D30_D31, AArch64::D30_D31_D0, AArch64::D31_D0_D1, 
  };

  // DDD Bit set.
  const uint8_t DDDBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // DDDD Register Class...
  const MCPhysReg DDDD[] = {
    AArch64::D0_D1_D2_D3, AArch64::D1_D2_D3_D4, AArch64::D2_D3_D4_D5, AArch64::D3_D4_D5_D6, AArch64::D4_D5_D6_D7, AArch64::D5_D6_D7_D8, AArch64::D6_D7_D8_D9, AArch64::D7_D8_D9_D10, AArch64::D8_D9_D10_D11, AArch64::D9_D10_D11_D12, AArch64::D10_D11_D12_D13, AArch64::D11_D12_D13_D14, AArch64::D12_D13_D14_D15, AArch64::D13_D14_D15_D16, AArch64::D14_D15_D16_D17, AArch64::D15_D16_D17_D18, AArch64::D16_D17_D18_D19, AArch64::D17_D18_D19_D20, AArch64::D18_D19_D20_D21, AArch64::D19_D20_D21_D22, AArch64::D20_D21_D22_D23, AArch64::D21_D22_D23_D24, AArch64::D22_D23_D24_D25, AArch64::D23_D24_D25_D26, AArch64::D24_D25_D26_D27, AArch64::D25_D26_D27_D28, AArch64::D26_D27_D28_D29, AArch64::D27_D28_D29_D30, AArch64::D28_D29_D30_D31, AArch64::D29_D30_D31_D0, AArch64::D30_D31_D0_D1, AArch64::D31_D0_D1_D2, 
  };

  // DDDD Bit set.
  const uint8_t DDDDBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // QQ Register Class...
  const MCPhysReg QQ[] = {
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, AArch64::Q16_Q17, AArch64::Q17_Q18, AArch64::Q18_Q19, AArch64::Q19_Q20, AArch64::Q20_Q21, AArch64::Q21_Q22, AArch64::Q22_Q23, AArch64::Q23_Q24, AArch64::Q24_Q25, AArch64::Q25_Q26, AArch64::Q26_Q27, AArch64::Q27_Q28, AArch64::Q28_Q29, AArch64::Q29_Q30, AArch64::Q30_Q31, AArch64::Q31_Q0, 
  };

  // QQ Bit set.
  const uint8_t QQBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // QQ_with_qsub0_in_FPR128_lo Register Class...
  const MCPhysReg QQ_with_qsub0_in_FPR128_lo[] = {
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q15_Q16, 
  };

  // QQ_with_qsub0_in_FPR128_lo Bit set.
  const uint8_t QQ_with_qsub0_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
  };

  // QQ_with_qsub1_in_FPR128_lo Register Class...
  const MCPhysReg QQ_with_qsub1_in_FPR128_lo[] = {
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, AArch64::Q31_Q0, 
  };

  // QQ_with_qsub1_in_FPR128_lo Bit set.
  const uint8_t QQ_with_qsub1_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, 
  };

  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Register Class...
  const MCPhysReg QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo[] = {
    AArch64::Q0_Q1, AArch64::Q1_Q2, AArch64::Q2_Q3, AArch64::Q3_Q4, AArch64::Q4_Q5, AArch64::Q5_Q6, AArch64::Q6_Q7, AArch64::Q7_Q8, AArch64::Q8_Q9, AArch64::Q9_Q10, AArch64::Q10_Q11, AArch64::Q11_Q12, AArch64::Q12_Q13, AArch64::Q13_Q14, AArch64::Q14_Q15, 
  };

  // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo Bit set.
  const uint8_t QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
  };

  // QQQ Register Class...
  const MCPhysReg QQQ[] = {
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, AArch64::Q16_Q17_Q18, AArch64::Q17_Q18_Q19, AArch64::Q18_Q19_Q20, AArch64::Q19_Q20_Q21, AArch64::Q20_Q21_Q22, AArch64::Q21_Q22_Q23, AArch64::Q22_Q23_Q24, AArch64::Q23_Q24_Q25, AArch64::Q24_Q25_Q26, AArch64::Q25_Q26_Q27, AArch64::Q26_Q27_Q28, AArch64::Q27_Q28_Q29, AArch64::Q28_Q29_Q30, AArch64::Q29_Q30_Q31, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
  };

  // QQQ Bit set.
  const uint8_t QQQBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // QQQ_with_qsub0_in_FPR128_lo Register Class...
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q15_Q16_Q17, 
  };

  // QQQ_with_qsub0_in_FPR128_lo Bit set.
  const uint8_t QQQ_with_qsub0_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
  };

  // QQQ_with_qsub1_in_FPR128_lo Register Class...
  const MCPhysReg QQQ_with_qsub1_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, AArch64::Q31_Q0_Q1, 
  };

  // QQQ_with_qsub1_in_FPR128_lo Bit set.
  const uint8_t QQQ_with_qsub1_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, 
  };

  // QQQ_with_qsub2_in_FPR128_lo Register Class...
  const MCPhysReg QQQ_with_qsub2_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q30_Q31_Q0, AArch64::Q31_Q0_Q1, 
  };

  // QQQ_with_qsub2_in_FPR128_lo Bit set.
  const uint8_t QQQ_with_qsub2_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, 
  };

  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Register Class...
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q14_Q15_Q16, 
  };

  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo Bit set.
  const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
  };

  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
  const MCPhysReg QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, AArch64::Q31_Q0_Q1, 
  };

  // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
  const uint8_t QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, 
  };

  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Register Class...
  const MCPhysReg QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2, AArch64::Q1_Q2_Q3, AArch64::Q2_Q3_Q4, AArch64::Q3_Q4_Q5, AArch64::Q4_Q5_Q6, AArch64::Q5_Q6_Q7, AArch64::Q6_Q7_Q8, AArch64::Q7_Q8_Q9, AArch64::Q8_Q9_Q10, AArch64::Q9_Q10_Q11, AArch64::Q10_Q11_Q12, AArch64::Q11_Q12_Q13, AArch64::Q12_Q13_Q14, AArch64::Q13_Q14_Q15, 
  };

  // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo Bit set.
  const uint8_t QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 
  };

  // QQQQ Register Class...
  const MCPhysReg QQQQ[] = {
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, AArch64::Q16_Q17_Q18_Q19, AArch64::Q17_Q18_Q19_Q20, AArch64::Q18_Q19_Q20_Q21, AArch64::Q19_Q20_Q21_Q22, AArch64::Q20_Q21_Q22_Q23, AArch64::Q21_Q22_Q23_Q24, AArch64::Q22_Q23_Q24_Q25, AArch64::Q23_Q24_Q25_Q26, AArch64::Q24_Q25_Q26_Q27, AArch64::Q25_Q26_Q27_Q28, AArch64::Q26_Q27_Q28_Q29, AArch64::Q27_Q28_Q29_Q30, AArch64::Q28_Q29_Q30_Q31, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
  };

  // QQQQ Bit set.
  const uint8_t QQQQBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f, 
  };

  // QQQQ_with_qsub0_in_FPR128_lo Register Class...
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q15_Q16_Q17_Q18, 
  };

  // QQQQ_with_qsub0_in_FPR128_lo Bit set.
  const uint8_t QQQQ_with_qsub0_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f, 
  };

  // QQQQ_with_qsub1_in_FPR128_lo Register Class...
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, AArch64::Q31_Q0_Q1_Q2, 
  };

  // QQQQ_with_qsub1_in_FPR128_lo Bit set.
  const uint8_t QQQQ_with_qsub1_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x08, 
  };

  // QQQQ_with_qsub2_in_FPR128_lo Register Class...
  const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
  };

  // QQQQ_with_qsub2_in_FPR128_lo Bit set.
  const uint8_t QQQQ_with_qsub2_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x0c, 
  };

  // QQQQ_with_qsub3_in_FPR128_lo Register Class...
  const MCPhysReg QQQQ_with_qsub3_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q29_Q30_Q31_Q0, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
  };

  // QQQQ_with_qsub3_in_FPR128_lo Bit set.
  const uint8_t QQQQ_with_qsub3_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0e, 
  };

  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Register Class...
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q14_Q15_Q16_Q17, 
  };

  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo Bit set.
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 
  };

  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, AArch64::Q31_Q0_Q1_Q2, 
  };

  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
  const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 0x00, 0x08, 
  };

  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
  const MCPhysReg QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q30_Q31_Q0_Q1, AArch64::Q31_Q0_Q1_Q2, 
  };

  // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
  const uint8_t QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x0c, 
  };

  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Register Class...
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q13_Q14_Q15_Q16, 
  };

  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo Bit set.
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x03, 
  };

  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
  const MCPhysReg QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, AArch64::Q31_Q0_Q1_Q2, 
  };

  // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
  const uint8_t QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 0x00, 0x08, 
  };

  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Register Class...
  const MCPhysReg QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo[] = {
    AArch64::Q0_Q1_Q2_Q3, AArch64::Q1_Q2_Q3_Q4, AArch64::Q2_Q3_Q4_Q5, AArch64::Q3_Q4_Q5_Q6, AArch64::Q4_Q5_Q6_Q7, AArch64::Q5_Q6_Q7_Q8, AArch64::Q6_Q7_Q8_Q9, AArch64::Q7_Q8_Q9_Q10, AArch64::Q8_Q9_Q10_Q11, AArch64::Q9_Q10_Q11_Q12, AArch64::Q10_Q11_Q12_Q13, AArch64::Q11_Q12_Q13_Q14, AArch64::Q12_Q13_Q14_Q15, 
  };

  // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo Bit set.
  const uint8_t QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits[] = {
    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x01, 
  };

}

extern const char AArch64RegClassStrings[] = {
  /* 0 */ 'F', 'P', 'R', '3', '2', 0,
  /* 6 */ 'G', 'P', 'R', '3', '2', 0,
  /* 12 */ 'F', 'P', 'R', '6', '4', 0,
  /* 18 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
  /* 56 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 't', 'c', 'G', 'P', 'R', '6', '4', 0,
  /* 140 */ 'F', 'P', 'R', '1', '6', 0,
  /* 146 */ 'F', 'P', 'R', '1', '2', '8', 0,
  /* 153 */ 'F', 'P', 'R', '8', 0,
  /* 158 */ 'D', 'D', 'D', 'D', 0,
  /* 163 */ 'Q', 'Q', 'Q', 'Q', 0,
  /* 168 */ 'C', 'C', 'R', 0,
  /* 172 */ 'G', 'P', 'R', '3', '2', 'a', 'l', 'l', 0,
  /* 181 */ 'G', 'P', 'R', '6', '4', 'a', 'l', 'l', 0,
  /* 190 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
  /* 232 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
  /* 274 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'e', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', 0,
  /* 362 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', '3', '2', '_', 'i', 'n', '_', 'G', 'P', 'R', '3', '2', 'c', 'o', 'm', 'm', 'o', 'n', '_', 'a', 'n', 'd', '_', 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', 'o', '6', '4', '_', 'i', 'n', '_', 'G', 'P', 'R', '6', '4', 'c', 'o', 'm', 'm', 'o', 'n', 0,
  /* 450 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
  /* 479 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
  /* 541 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
  /* 601 */ 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
  /* 659 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
  /* 721 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
  /* 783 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
  /* 843 */ 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
  /* 903 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '0', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
  /* 965 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '1', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
  /* 1027 */ 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '2', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', '_', 'a', 'n', 'd', '_', 'Q', 'Q', 'Q', 'Q', '_', 'w', 'i', 't', 'h', '_', 'q', 's', 'u', 'b', '3', '_', 'i', 'n', '_', 'F', 'P', 'R', '1', '2', '8', '_', 'l', 'o', 0,
  /* 1089 */ 'G', 'P', 'R', '3', '2', 's', 'p', 0,
  /* 1097 */ 'G', 'P', 'R', '6', '4', 's', 'p', 0,
  /* 1105 */ 'W', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
  /* 1120 */ 'X', 'S', 'e', 'q', 'P', 'a', 'i', 'r', 's', 'C', 'l', 'a', 's', 's', 0,
  /* 1135 */ 'G', 'P', 'R', '3', '2', 's', 'p', 'o', 'n', 'l', 'y', 0,
  /* 1147 */ 'G', 'P', 'R', '6', '4', 's', 'p', 'o', 'n', 'l', 'y', 0,
};

extern const MCRegisterClass AArch64MCRegisterClasses[] = {
  { FPR8, FPR8Bits, 153, 32, sizeof(FPR8Bits), AArch64::FPR8RegClassID, 1, 1, 1, 1 },
  { FPR16, FPR16Bits, 140, 32, sizeof(FPR16Bits), AArch64::FPR16RegClassID, 2, 2, 1, 1 },
  { GPR32all, GPR32allBits, 172, 33, sizeof(GPR32allBits), AArch64::GPR32allRegClassID, 4, 4, 1, 1 },
  { FPR32, FPR32Bits, 0, 32, sizeof(FPR32Bits), AArch64::FPR32RegClassID, 4, 4, 1, 1 },
  { GPR32, GPR32Bits, 6, 32, sizeof(GPR32Bits), AArch64::GPR32RegClassID, 4, 4, 1, 1 },
  { GPR32sp, GPR32spBits, 1089, 32, sizeof(GPR32spBits), AArch64::GPR32spRegClassID, 4, 4, 1, 1 },
  { GPR32common, GPR32commonBits, 220, 31, sizeof(GPR32commonBits), AArch64::GPR32commonRegClassID, 4, 4, 1, 1 },
  { CCR, CCRBits, 168, 1, sizeof(CCRBits), AArch64::CCRRegClassID, 4, 4, -1, 0 },
  { GPR32sponly, GPR32sponlyBits, 1135, 1, sizeof(GPR32sponlyBits), AArch64::GPR32sponlyRegClassID, 4, 4, 1, 1 },
  { WSeqPairsClass, WSeqPairsClassBits, 1105, 32, sizeof(WSeqPairsClassBits), AArch64::WSeqPairsClassRegClassID, 8, 4, 1, 1 },
  { WSeqPairsClass_with_sube32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32commonBits, 232, 31, sizeof(WSeqPairsClass_with_sube32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32commonRegClassID, 8, 4, 1, 1 },
  { WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_subo32_in_GPR32commonBits, 320, 31, sizeof(WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 8, 4, 1, 1 },
  { WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32common, WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits, 274, 30, sizeof(WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonBits), AArch64::WSeqPairsClass_with_sube32_in_GPR32common_and_WSeqPairsClass_with_subo32_in_GPR32commonRegClassID, 8, 4, 1, 1 },
  { GPR64all, GPR64allBits, 181, 33, sizeof(GPR64allBits), AArch64::GPR64allRegClassID, 8, 8, 1, 1 },
  { FPR64, FPR64Bits, 12, 32, sizeof(FPR64Bits), AArch64::FPR64RegClassID, 8, 8, 1, 1 },
  { GPR64, GPR64Bits, 50, 32, sizeof(GPR64Bits), AArch64::GPR64RegClassID, 8, 8, 1, 1 },
  { GPR64sp, GPR64spBits, 1097, 32, sizeof(GPR64spBits), AArch64::GPR64spRegClassID, 8, 8, 1, 1 },
  { GPR64common, GPR64commonBits, 438, 31, sizeof(GPR64commonBits), AArch64::GPR64commonRegClassID, 8, 8, 1, 1 },
  { tcGPR64, tcGPR64Bits, 48, 19, sizeof(tcGPR64Bits), AArch64::tcGPR64RegClassID, 8, 8, 1, 1 },
  { GPR64sponly, GPR64sponlyBits, 1147, 1, sizeof(GPR64sponlyBits), AArch64::GPR64sponlyRegClassID, 8, 8, 1, 1 },
  { DD, DDBits, 160, 32, sizeof(DDBits), AArch64::DDRegClassID, 16, 8, 1, 1 },
  { XSeqPairsClass, XSeqPairsClassBits, 1120, 32, sizeof(XSeqPairsClassBits), AArch64::XSeqPairsClassRegClassID, 16, 8, 1, 1 },
  { XSeqPairsClass_with_sub_32_in_GPR32common, XSeqPairsClass_with_sub_32_in_GPR32commonBits, 190, 31, sizeof(XSeqPairsClass_with_sub_32_in_GPR32commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32commonRegClassID, 16, 8, 1, 1 },
  { XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_subo64_in_GPR64commonBits, 408, 31, sizeof(XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 16, 8, 1, 1 },
  { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64common, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits, 362, 30, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonBits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_GPR64commonRegClassID, 16, 8, 1, 1 },
  { XSeqPairsClass_with_sube64_in_tcGPR64, XSeqPairsClass_with_sube64_in_tcGPR64Bits, 18, 19, sizeof(XSeqPairsClass_with_sube64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sube64_in_tcGPR64RegClassID, 16, 8, 1, 1 },
  { XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_subo64_in_tcGPR64Bits, 102, 19, sizeof(XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 16, 8, 1, 1 },
  { XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64, XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits, 56, 18, sizeof(XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64Bits), AArch64::XSeqPairsClass_with_sub_32_in_GPR32common_and_XSeqPairsClass_with_subo64_in_tcGPR64RegClassID, 16, 8, 1, 1 },
  { FPR128, FPR128Bits, 146, 32, sizeof(FPR128Bits), AArch64::FPR128RegClassID, 16, 16, 1, 1 },
  { FPR128_lo, FPR128_loBits, 469, 16, sizeof(FPR128_loBits), AArch64::FPR128_loRegClassID, 16, 16, 1, 1 },
  { DDD, DDDBits, 159, 32, sizeof(DDDBits), AArch64::DDDRegClassID, 24, 8, 1, 1 },
  { DDDD, DDDDBits, 158, 32, sizeof(DDDDBits), AArch64::DDDDRegClassID, 32, 8, 1, 1 },
  { QQ, QQBits, 165, 32, sizeof(QQBits), AArch64::QQRegClassID, 32, 16, 1, 1 },
  { QQ_with_qsub0_in_FPR128_lo, QQ_with_qsub0_in_FPR128_loBits, 452, 16, sizeof(QQ_with_qsub0_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_loRegClassID, 32, 16, 1, 1 },
  { QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub1_in_FPR128_loBits, 514, 16, sizeof(QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 },
  { QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo, QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits, 601, 15, sizeof(QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loBits), AArch64::QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClassID, 32, 16, 1, 1 },
  { QQQ, QQQBits, 164, 32, sizeof(QQQBits), AArch64::QQQRegClassID, 48, 16, 1, 1 },
  { QQQ_with_qsub0_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_loBits, 451, 16, sizeof(QQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_loRegClassID, 48, 16, 1, 1 },
  { QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_loBits, 513, 16, sizeof(QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 },
  { QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub2_in_FPR128_loBits, 693, 16, sizeof(QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits, 541, 15, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClassID, 48, 16, 1, 1 },
  { QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 843, 15, sizeof(QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
  { QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo, QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits, 783, 14, sizeof(QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClassID, 48, 16, 1, 1 },
  { QQQQ, QQQQBits, 163, 32, sizeof(QQQQBits), AArch64::QQQQRegClassID, 64, 16, 1, 1 },
  { QQQQ_with_qsub0_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_loBits, 450, 16, sizeof(QQQQ_with_qsub0_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_loRegClassID, 64, 16, 1, 1 },
  { QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_loBits, 512, 16, sizeof(QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 },
  { QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_loBits, 692, 16, sizeof(QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
  { QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub3_in_FPR128_loBits, 936, 16, sizeof(QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits, 479, 15, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClassID, 64, 16, 1, 1 },
  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 721, 15, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
  { QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 1027, 15, sizeof(QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits, 659, 14, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClassID, 64, 16, 1, 1 },
  { QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 965, 14, sizeof(QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
  { QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo, QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits, 903, 13, sizeof(QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loBits), AArch64::QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClassID, 64, 16, 1, 1 },
};

// AArch64 Dwarf<->LLVM register mappings.
extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0Dwarf2L[] = {
  { 0U, AArch64::W0 },
  { 1U, AArch64::W1 },
  { 2U, AArch64::W2 },
  { 3U, AArch64::W3 },
  { 4U, AArch64::W4 },
  { 5U, AArch64::W5 },
  { 6U, AArch64::W6 },
  { 7U, AArch64::W7 },
  { 8U, AArch64::W8 },
  { 9U, AArch64::W9 },
  { 10U, AArch64::W10 },
  { 11U, AArch64::W11 },
  { 12U, AArch64::W12 },
  { 13U, AArch64::W13 },
  { 14U, AArch64::W14 },
  { 15U, AArch64::W15 },
  { 16U, AArch64::W16 },
  { 17U, AArch64::W17 },
  { 18U, AArch64::W18 },
  { 19U, AArch64::W19 },
  { 20U, AArch64::W20 },
  { 21U, AArch64::W21 },
  { 22U, AArch64::W22 },
  { 23U, AArch64::W23 },
  { 24U, AArch64::W24 },
  { 25U, AArch64::W25 },
  { 26U, AArch64::W26 },
  { 27U, AArch64::W27 },
  { 28U, AArch64::W28 },
  { 29U, AArch64::W29 },
  { 30U, AArch64::W30 },
  { 31U, AArch64::WSP },
  { 64U, AArch64::B0 },
  { 65U, AArch64::B1 },
  { 66U, AArch64::B2 },
  { 67U, AArch64::B3 },
  { 68U, AArch64::B4 },
  { 69U, AArch64::B5 },
  { 70U, AArch64::B6 },
  { 71U, AArch64::B7 },
  { 72U, AArch64::B8 },
  { 73U, AArch64::B9 },
  { 74U, AArch64::B10 },
  { 75U, AArch64::B11 },
  { 76U, AArch64::B12 },
  { 77U, AArch64::B13 },
  { 78U, AArch64::B14 },
  { 79U, AArch64::B15 },
  { 80U, AArch64::B16 },
  { 81U, AArch64::B17 },
  { 82U, AArch64::B18 },
  { 83U, AArch64::B19 },
  { 84U, AArch64::B20 },
  { 85U, AArch64::B21 },
  { 86U, AArch64::B22 },
  { 87U, AArch64::B23 },
  { 88U, AArch64::B24 },
  { 89U, AArch64::B25 },
  { 90U, AArch64::B26 },
  { 91U, AArch64::B27 },
  { 92U, AArch64::B28 },
  { 93U, AArch64::B29 },
  { 94U, AArch64::B30 },
  { 95U, AArch64::B31 },
};
extern const unsigned AArch64DwarfFlavour0Dwarf2LSize = array_lengthof(AArch64DwarfFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0Dwarf2L[] = {
  { 0U, AArch64::W0 },
  { 1U, AArch64::W1 },
  { 2U, AArch64::W2 },
  { 3U, AArch64::W3 },
  { 4U, AArch64::W4 },
  { 5U, AArch64::W5 },
  { 6U, AArch64::W6 },
  { 7U, AArch64::W7 },
  { 8U, AArch64::W8 },
  { 9U, AArch64::W9 },
  { 10U, AArch64::W10 },
  { 11U, AArch64::W11 },
  { 12U, AArch64::W12 },
  { 13U, AArch64::W13 },
  { 14U, AArch64::W14 },
  { 15U, AArch64::W15 },
  { 16U, AArch64::W16 },
  { 17U, AArch64::W17 },
  { 18U, AArch64::W18 },
  { 19U, AArch64::W19 },
  { 20U, AArch64::W20 },
  { 21U, AArch64::W21 },
  { 22U, AArch64::W22 },
  { 23U, AArch64::W23 },
  { 24U, AArch64::W24 },
  { 25U, AArch64::W25 },
  { 26U, AArch64::W26 },
  { 27U, AArch64::W27 },
  { 28U, AArch64::W28 },
  { 29U, AArch64::W29 },
  { 30U, AArch64::W30 },
  { 31U, AArch64::WSP },
  { 64U, AArch64::B0 },
  { 65U, AArch64::B1 },
  { 66U, AArch64::B2 },
  { 67U, AArch64::B3 },
  { 68U, AArch64::B4 },
  { 69U, AArch64::B5 },
  { 70U, AArch64::B6 },
  { 71U, AArch64::B7 },
  { 72U, AArch64::B8 },
  { 73U, AArch64::B9 },
  { 74U, AArch64::B10 },
  { 75U, AArch64::B11 },
  { 76U, AArch64::B12 },
  { 77U, AArch64::B13 },
  { 78U, AArch64::B14 },
  { 79U, AArch64::B15 },
  { 80U, AArch64::B16 },
  { 81U, AArch64::B17 },
  { 82U, AArch64::B18 },
  { 83U, AArch64::B19 },
  { 84U, AArch64::B20 },
  { 85U, AArch64::B21 },
  { 86U, AArch64::B22 },
  { 87U, AArch64::B23 },
  { 88U, AArch64::B24 },
  { 89U, AArch64::B25 },
  { 90U, AArch64::B26 },
  { 91U, AArch64::B27 },
  { 92U, AArch64::B28 },
  { 93U, AArch64::B29 },
  { 94U, AArch64::B30 },
  { 95U, AArch64::B31 },
};
extern const unsigned AArch64EHFlavour0Dwarf2LSize = array_lengthof(AArch64EHFlavour0Dwarf2L);

extern const MCRegisterInfo::DwarfLLVMRegPair AArch64DwarfFlavour0L2Dwarf[] = {
  { AArch64::FP, 29U },
  { AArch64::LR, 30U },
  { AArch64::SP, 31U },
  { AArch64::WSP, 31U },
  { AArch64::WZR, 31U },
  { AArch64::XZR, 31U },
  { AArch64::B0, 64U },
  { AArch64::B1, 65U },
  { AArch64::B2, 66U },
  { AArch64::B3, 67U },
  { AArch64::B4, 68U },
  { AArch64::B5, 69U },
  { AArch64::B6, 70U },
  { AArch64::B7, 71U },
  { AArch64::B8, 72U },
  { AArch64::B9, 73U },
  { AArch64::B10, 74U },
  { AArch64::B11, 75U },
  { AArch64::B12, 76U },
  { AArch64::B13, 77U },
  { AArch64::B14, 78U },
  { AArch64::B15, 79U },
  { AArch64::B16, 80U },
  { AArch64::B17, 81U },
  { AArch64::B18, 82U },
  { AArch64::B19, 83U },
  { AArch64::B20, 84U },
  { AArch64::B21, 85U },
  { AArch64::B22, 86U },
  { AArch64::B23, 87U },
  { AArch64::B24, 88U },
  { AArch64::B25, 89U },
  { AArch64::B26, 90U },
  { AArch64::B27, 91U },
  { AArch64::B28, 92U },
  { AArch64::B29, 93U },
  { AArch64::B30, 94U },
  { AArch64::B31, 95U },
  { AArch64::D0, 64U },
  { AArch64::D1, 65U },
  { AArch64::D2, 66U },
  { AArch64::D3, 67U },
  { AArch64::D4, 68U },
  { AArch64::D5, 69U },
  { AArch64::D6, 70U },
  { AArch64::D7, 71U },
  { AArch64::D8, 72U },
  { AArch64::D9, 73U },
  { AArch64::D10, 74U },
  { AArch64::D11, 75U },
  { AArch64::D12, 76U },
  { AArch64::D13, 77U },
  { AArch64::D14, 78U },
  { AArch64::D15, 79U },
  { AArch64::D16, 80U },
  { AArch64::D17, 81U },
  { AArch64::D18, 82U },
  { AArch64::D19, 83U },
  { AArch64::D20, 84U },
  { AArch64::D21, 85U },
  { AArch64::D22, 86U },
  { AArch64::D23, 87U },
  { AArch64::D24, 88U },
  { AArch64::D25, 89U },
  { AArch64::D26, 90U },
  { AArch64::D27, 91U },
  { AArch64::D28, 92U },
  { AArch64::D29, 93U },
  { AArch64::D30, 94U },
  { AArch64::D31, 95U },
  { AArch64::H0, 64U },
  { AArch64::H1, 65U },
  { AArch64::H2, 66U },
  { AArch64::H3, 67U },
  { AArch64::H4, 68U },
  { AArch64::H5, 69U },
  { AArch64::H6, 70U },
  { AArch64::H7, 71U },
  { AArch64::H8, 72U },
  { AArch64::H9, 73U },
  { AArch64::H10, 74U },
  { AArch64::H11, 75U },
  { AArch64::H12, 76U },
  { AArch64::H13, 77U },
  { AArch64::H14, 78U },
  { AArch64::H15, 79U },
  { AArch64::H16, 80U },
  { AArch64::H17, 81U },
  { AArch64::H18, 82U },
  { AArch64::H19, 83U },
  { AArch64::H20, 84U },
  { AArch64::H21, 85U },
  { AArch64::H22, 86U },
  { AArch64::H23, 87U },
  { AArch64::H24, 88U },
  { AArch64::H25, 89U },
  { AArch64::H26, 90U },
  { AArch64::H27, 91U },
  { AArch64::H28, 92U },
  { AArch64::H29, 93U },
  { AArch64::H30, 94U },
  { AArch64::H31, 95U },
  { AArch64::Q0, 64U },
  { AArch64::Q1, 65U },
  { AArch64::Q2, 66U },
  { AArch64::Q3, 67U },
  { AArch64::Q4, 68U },
  { AArch64::Q5, 69U },
  { AArch64::Q6, 70U },
  { AArch64::Q7, 71U },
  { AArch64::Q8, 72U },
  { AArch64::Q9, 73U },
  { AArch64::Q10, 74U },
  { AArch64::Q11, 75U },
  { AArch64::Q12, 76U },
  { AArch64::Q13, 77U },
  { AArch64::Q14, 78U },
  { AArch64::Q15, 79U },
  { AArch64::Q16, 80U },
  { AArch64::Q17, 81U },
  { AArch64::Q18, 82U },
  { AArch64::Q19, 83U },
  { AArch64::Q20, 84U },
  { AArch64::Q21, 85U },
  { AArch64::Q22, 86U },
  { AArch64::Q23, 87U },
  { AArch64::Q24, 88U },
  { AArch64::Q25, 89U },
  { AArch64::Q26, 90U },
  { AArch64::Q27, 91U },
  { AArch64::Q28, 92U },
  { AArch64::Q29, 93U },
  { AArch64::Q30, 94U },
  { AArch64::Q31, 95U },
  { AArch64::S0, 64U },
  { AArch64::S1, 65U },
  { AArch64::S2, 66U },
  { AArch64::S3, 67U },
  { AArch64::S4, 68U },
  { AArch64::S5, 69U },
  { AArch64::S6, 70U },
  { AArch64::S7, 71U },
  { AArch64::S8, 72U },
  { AArch64::S9, 73U },
  { AArch64::S10, 74U },
  { AArch64::S11, 75U },
  { AArch64::S12, 76U },
  { AArch64::S13, 77U },
  { AArch64::S14, 78U },
  { AArch64::S15, 79U },
  { AArch64::S16, 80U },
  { AArch64::S17, 81U },
  { AArch64::S18, 82U },
  { AArch64::S19, 83U },
  { AArch64::S20, 84U },
  { AArch64::S21, 85U },
  { AArch64::S22, 86U },
  { AArch64::S23, 87U },
  { AArch64::S24, 88U },
  { AArch64::S25, 89U },
  { AArch64::S26, 90U },
  { AArch64::S27, 91U },
  { AArch64::S28, 92U },
  { AArch64::S29, 93U },
  { AArch64::S30, 94U },
  { AArch64::S31, 95U },
  { AArch64::W0, 0U },
  { AArch64::W1, 1U },
  { AArch64::W2, 2U },
  { AArch64::W3, 3U },
  { AArch64::W4, 4U },
  { AArch64::W5, 5U },
  { AArch64::W6, 6U },
  { AArch64::W7, 7U },
  { AArch64::W8, 8U },
  { AArch64::W9, 9U },
  { AArch64::W10, 10U },
  { AArch64::W11, 11U },
  { AArch64::W12, 12U },
  { AArch64::W13, 13U },
  { AArch64::W14, 14U },
  { AArch64::W15, 15U },
  { AArch64::W16, 16U },
  { AArch64::W17, 17U },
  { AArch64::W18, 18U },
  { AArch64::W19, 19U },
  { AArch64::W20, 20U },
  { AArch64::W21, 21U },
  { AArch64::W22, 22U },
  { AArch64::W23, 23U },
  { AArch64::W24, 24U },
  { AArch64::W25, 25U },
  { AArch64::W26, 26U },
  { AArch64::W27, 27U },
  { AArch64::W28, 28U },
  { AArch64::W29, 29U },
  { AArch64::W30, 30U },
  { AArch64::X0, 0U },
  { AArch64::X1, 1U },
  { AArch64::X2, 2U },
  { AArch64::X3, 3U },
  { AArch64::X4, 4U },
  { AArch64::X5, 5U },
  { AArch64::X6, 6U },
  { AArch64::X7, 7U },
  { AArch64::X8, 8U },
  { AArch64::X9, 9U },
  { AArch64::X10, 10U },
  { AArch64::X11, 11U },
  { AArch64::X12, 12U },
  { AArch64::X13, 13U },
  { AArch64::X14, 14U },
  { AArch64::X15, 15U },
  { AArch64::X16, 16U },
  { AArch64::X17, 17U },
  { AArch64::X18, 18U },
  { AArch64::X19, 19U },
  { AArch64::X20, 20U },
  { AArch64::X21, 21U },
  { AArch64::X22, 22U },
  { AArch64::X23, 23U },
  { AArch64::X24, 24U },
  { AArch64::X25, 25U },
  { AArch64::X26, 26U },
  { AArch64::X27, 27U },
  { AArch64::X28, 28U },
};
extern const unsigned AArch64DwarfFlavour0L2DwarfSize = array_lengthof(AArch64DwarfFlavour0L2Dwarf);

extern const MCRegisterInfo::DwarfLLVMRegPair AArch64EHFlavour0L2Dwarf[] = {
  { AArch64::FP, 29U },
  { AArch64::LR, 30U },
  { AArch64::SP, 31U },
  { AArch64::WSP, 31U },
  { AArch64::WZR, 31U },
  { AArch64::XZR, 31U },
  { AArch64::B0, 64U },
  { AArch64::B1, 65U },
  { AArch64::B2, 66U },
  { AArch64::B3, 67U },
  { AArch64::B4, 68U },
  { AArch64::B5, 69U },
  { AArch64::B6, 70U },
  { AArch64::B7, 71U },
  { AArch64::B8, 72U },
  { AArch64::B9, 73U },
  { AArch64::B10, 74U },
  { AArch64::B11, 75U },
  { AArch64::B12, 76U },
  { AArch64::B13, 77U },
  { AArch64::B14, 78U },
  { AArch64::B15, 79U },
  { AArch64::B16, 80U },
  { AArch64::B17, 81U },
  { AArch64::B18, 82U },
  { AArch64::B19, 83U },
  { AArch64::B20, 84U },
  { AArch64::B21, 85U },
  { AArch64::B22, 86U },
  { AArch64::B23, 87U },
  { AArch64::B24, 88U },
  { AArch64::B25, 89U },
  { AArch64::B26, 90U },
  { AArch64::B27, 91U },
  { AArch64::B28, 92U },
  { AArch64::B29, 93U },
  { AArch64::B30, 94U },
  { AArch64::B31, 95U },
  { AArch64::D0, 64U },
  { AArch64::D1, 65U },
  { AArch64::D2, 66U },
  { AArch64::D3, 67U },
  { AArch64::D4, 68U },
  { AArch64::D5, 69U },
  { AArch64::D6, 70U },
  { AArch64::D7, 71U },
  { AArch64::D8, 72U },
  { AArch64::D9, 73U },
  { AArch64::D10, 74U },
  { AArch64::D11, 75U },
  { AArch64::D12, 76U },
  { AArch64::D13, 77U },
  { AArch64::D14, 78U },
  { AArch64::D15, 79U },
  { AArch64::D16, 80U },
  { AArch64::D17, 81U },
  { AArch64::D18, 82U },
  { AArch64::D19, 83U },
  { AArch64::D20, 84U },
  { AArch64::D21, 85U },
  { AArch64::D22, 86U },
  { AArch64::D23, 87U },
  { AArch64::D24, 88U },
  { AArch64::D25, 89U },
  { AArch64::D26, 90U },
  { AArch64::D27, 91U },
  { AArch64::D28, 92U },
  { AArch64::D29, 93U },
  { AArch64::D30, 94U },
  { AArch64::D31, 95U },
  { AArch64::H0, 64U },
  { AArch64::H1, 65U },
  { AArch64::H2, 66U },
  { AArch64::H3, 67U },
  { AArch64::H4, 68U },
  { AArch64::H5, 69U },
  { AArch64::H6, 70U },
  { AArch64::H7, 71U },
  { AArch64::H8, 72U },
  { AArch64::H9, 73U },
  { AArch64::H10, 74U },
  { AArch64::H11, 75U },
  { AArch64::H12, 76U },
  { AArch64::H13, 77U },
  { AArch64::H14, 78U },
  { AArch64::H15, 79U },
  { AArch64::H16, 80U },
  { AArch64::H17, 81U },
  { AArch64::H18, 82U },
  { AArch64::H19, 83U },
  { AArch64::H20, 84U },
  { AArch64::H21, 85U },
  { AArch64::H22, 86U },
  { AArch64::H23, 87U },
  { AArch64::H24, 88U },
  { AArch64::H25, 89U },
  { AArch64::H26, 90U },
  { AArch64::H27, 91U },
  { AArch64::H28, 92U },
  { AArch64::H29, 93U },
  { AArch64::H30, 94U },
  { AArch64::H31, 95U },
  { AArch64::Q0, 64U },
  { AArch64::Q1, 65U },
  { AArch64::Q2, 66U },
  { AArch64::Q3, 67U },
  { AArch64::Q4, 68U },
  { AArch64::Q5, 69U },
  { AArch64::Q6, 70U },
  { AArch64::Q7, 71U },
  { AArch64::Q8, 72U },
  { AArch64::Q9, 73U },
  { AArch64::Q10, 74U },
  { AArch64::Q11, 75U },
  { AArch64::Q12, 76U },
  { AArch64::Q13, 77U },
  { AArch64::Q14, 78U },
  { AArch64::Q15, 79U },
  { AArch64::Q16, 80U },
  { AArch64::Q17, 81U },
  { AArch64::Q18, 82U },
  { AArch64::Q19, 83U },
  { AArch64::Q20, 84U },
  { AArch64::Q21, 85U },
  { AArch64::Q22, 86U },
  { AArch64::Q23, 87U },
  { AArch64::Q24, 88U },
  { AArch64::Q25, 89U },
  { AArch64::Q26, 90U },
  { AArch64::Q27, 91U },
  { AArch64::Q28, 92U },
  { AArch64::Q29, 93U },
  { AArch64::Q30, 94U },
  { AArch64::Q31, 95U },
  { AArch64::S0, 64U },
  { AArch64::S1, 65U },
  { AArch64::S2, 66U },
  { AArch64::S3, 67U },
  { AArch64::S4, 68U },
  { AArch64::S5, 69U },
  { AArch64::S6, 70U },
  { AArch64::S7, 71U },
  { AArch64::S8, 72U },
  { AArch64::S9, 73U },
  { AArch64::S10, 74U },
  { AArch64::S11, 75U },
  { AArch64::S12, 76U },
  { AArch64::S13, 77U },
  { AArch64::S14, 78U },
  { AArch64::S15, 79U },
  { AArch64::S16, 80U },
  { AArch64::S17, 81U },
  { AArch64::S18, 82U },
  { AArch64::S19, 83U },
  { AArch64::S20, 84U },
  { AArch64::S21, 85U },
  { AArch64::S22, 86U },
  { AArch64::S23, 87U },
  { AArch64::S24, 88U },
  { AArch64::S25, 89U },
  { AArch64::S26, 90U },
  { AArch64::S27, 91U },
  { AArch64::S28, 92U },
  { AArch64::S29, 93U },
  { AArch64::S30, 94U },
  { AArch64::S31, 95U },
  { AArch64::W0, 0U },
  { AArch64::W1, 1U },
  { AArch64::W2, 2U },
  { AArch64::W3, 3U },
  { AArch64::W4, 4U },
  { AArch64::W5, 5U },
  { AArch64::W6, 6U },
  { AArch64::W7, 7U },
  { AArch64::W8, 8U },
  { AArch64::W9, 9U },
  { AArch64::W10, 10U },
  { AArch64::W11, 11U },
  { AArch64::W12, 12U },
  { AArch64::W13, 13U },
  { AArch64::W14, 14U },
  { AArch64::W15, 15U },
  { AArch64::W16, 16U },
  { AArch64::W17, 17U },
  { AArch64::W18, 18U },
  { AArch64::W19, 19U },
  { AArch64::W20, 20U },
  { AArch64::W21, 21U },
  { AArch64::W22, 22U },
  { AArch64::W23, 23U },
  { AArch64::W24, 24U },
  { AArch64::W25, 25U },
  { AArch64::W26, 26U },
  { AArch64::W27, 27U },
  { AArch64::W28, 28U },
  { AArch64::W29, 29U },
  { AArch64::W30, 30U },
  { AArch64::X0, 0U },
  { AArch64::X1, 1U },
  { AArch64::X2, 2U },
  { AArch64::X3, 3U },
  { AArch64::X4, 4U },
  { AArch64::X5, 5U },
  { AArch64::X6, 6U },
  { AArch64::X7, 7U },
  { AArch64::X8, 8U },
  { AArch64::X9, 9U },
  { AArch64::X10, 10U },
  { AArch64::X11, 11U },
  { AArch64::X12, 12U },
  { AArch64::X13, 13U },
  { AArch64::X14, 14U },
  { AArch64::X15, 15U },
  { AArch64::X16, 16U },
  { AArch64::X17, 17U },
  { AArch64::X18, 18U },
  { AArch64::X19, 19U },
  { AArch64::X20, 20U },
  { AArch64::X21, 21U },
  { AArch64::X22, 22U },
  { AArch64::X23, 23U },
  { AArch64::X24, 24U },
  { AArch64::X25, 25U },
  { AArch64::X26, 26U },
  { AArch64::X27, 27U },
  { AArch64::X28, 28U },
};
extern const unsigned AArch64EHFlavour0L2DwarfSize = array_lengthof(AArch64EHFlavour0L2Dwarf);

extern const uint16_t AArch64RegEncodingTable[] = {
  0,
  29,
  30,
  0,
  31,
  31,
  31,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
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  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  0,
  1,
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  3,
  4,
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  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
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  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
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  27,
  28,
  29,
  30,
  31,
  0,
  1,
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  3,
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  11,
  12,
  13,
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  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
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  8,
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  10,
  11,
  12,
  13,
  14,
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  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  30,
  31,
  31,
  30,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
  28,
  29,
  29,
  30,
  31,
  28,
  0,
  1,
  2,
  3,
  4,
  5,
  6,
  7,
  8,
  9,
  10,
  11,
  12,
  13,
  14,
  15,
  16,
  17,
  18,
  19,
  20,
  21,
  22,
  23,
  24,
  25,
  26,
  27,
};
static inline void InitAArch64MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
  RI->InitMCRegisterInfo(AArch64RegDesc, 484, RA, PC, AArch64MCRegisterClasses, 54, AArch64RegUnitRoots, 66, AArch64RegDiffLists, AArch64LaneMaskLists, AArch64RegStrings, AArch64RegClassStrings, AArch64SubRegIdxLists, 59,
AArch64SubRegIdxRanges, AArch64RegEncodingTable);

  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(AArch64DwarfFlavour0Dwarf2L, AArch64DwarfFlavour0Dwarf2LSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapDwarfRegsToLLVMRegs(AArch64EHFlavour0Dwarf2L, AArch64EHFlavour0Dwarf2LSize, true);
    break;
  }
  switch (DwarfFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(AArch64DwarfFlavour0L2Dwarf, AArch64DwarfFlavour0L2DwarfSize, false);
    break;
  }
  switch (EHFlavour) {
  default:
    llvm_unreachable("Unknown DWARF flavour");
  case 0:
    RI->mapLLVMRegsToDwarfRegs(AArch64EHFlavour0L2Dwarf, AArch64EHFlavour0L2DwarfSize, true);
    break;
  }
}

} // End llvm namespace
#endif // GET_REGINFO_MC_DESC

Coverage Report

Created: 2026-06-08 07:05