/src/keystone/llvm/lib/Target/Sparc/SparcGenRegisterInfo.inc

Line	Count	Source
1		/===- TableGen'erated file -------------------------------------- C++ --===\
2		\|* *\|
3		\|* Target Register Enum Values *\|
4		\|* *\|
5		\|* Automatically generated file, do not edit! *\|
6		\|* *\|
7		\===----------------------------------------------------------------------===/
8
9
10		#ifdef GET_REGINFO_ENUM
11		#undef GET_REGINFO_ENUM
12		namespace llvm_ks {
13
14		class MCRegisterClass;
15		extern const MCRegisterClass SPMCRegisterClasses[];
16
17		namespace SP {
18		enum {
19		NoRegister,
20		CANRESTORE = 1,
21		CANSAVE = 2,
22		CLEANWIN = 3,
23		CWP = 4,
24		FSR = 5,
25		ICC = 6,
26		OTHERWIN = 7,
27		PIL = 8,
28		PSR = 9,
29		PSTATE = 10,
30		TBA = 11,
31		TBR = 12,
32		TICK = 13,
33		TL = 14,
34		TNPC = 15,
35		TPC = 16,
36		TSTATE = 17,
37		TT = 18,
38		WIM = 19,
39		WSTATE = 20,
40		Y = 21,
41		ASR1 = 22,
42		ASR2 = 23,
43		ASR3 = 24,
44		ASR4 = 25,
45		ASR5 = 26,
46		ASR6 = 27,
47		ASR7 = 28,
48		ASR8 = 29,
49		ASR9 = 30,
50		ASR10 = 31,
51		ASR11 = 32,
52		ASR12 = 33,
53		ASR13 = 34,
54		ASR14 = 35,
55		ASR15 = 36,
56		ASR16 = 37,
57		ASR17 = 38,
58		ASR18 = 39,
59		ASR19 = 40,
60		ASR20 = 41,
61		ASR21 = 42,
62		ASR22 = 43,
63		ASR23 = 44,
64		ASR24 = 45,
65		ASR25 = 46,
66		ASR26 = 47,
67		ASR27 = 48,
68		ASR28 = 49,
69		ASR29 = 50,
70		ASR30 = 51,
71		ASR31 = 52,
72		D0 = 53,
73		D1 = 54,
74		D2 = 55,
75		D3 = 56,
76		D4 = 57,
77		D5 = 58,
78		D6 = 59,
79		D7 = 60,
80		D8 = 61,
81		D9 = 62,
82		D10 = 63,
83		D11 = 64,
84		D12 = 65,
85		D13 = 66,
86		D14 = 67,
87		D15 = 68,
88		D16 = 69,
89		D17 = 70,
90		D18 = 71,
91		D19 = 72,
92		D20 = 73,
93		D21 = 74,
94		D22 = 75,
95		D23 = 76,
96		D24 = 77,
97		D25 = 78,
98		D26 = 79,
99		D27 = 80,
100		D28 = 81,
101		D29 = 82,
102		D30 = 83,
103		D31 = 84,
104		F0 = 85,
105		F1 = 86,
106		F2 = 87,
107		F3 = 88,
108		F4 = 89,
109		F5 = 90,
110		F6 = 91,
111		F7 = 92,
112		F8 = 93,
113		F9 = 94,
114		F10 = 95,
115		F11 = 96,
116		F12 = 97,
117		F13 = 98,
118		F14 = 99,
119		F15 = 100,
120		F16 = 101,
121		F17 = 102,
122		F18 = 103,
123		F19 = 104,
124		F20 = 105,
125		F21 = 106,
126		F22 = 107,
127		F23 = 108,
128		F24 = 109,
129		F25 = 110,
130		F26 = 111,
131		F27 = 112,
132		F28 = 113,
133		F29 = 114,
134		F30 = 115,
135		F31 = 116,
136		FCC0 = 117,
137		FCC1 = 118,
138		FCC2 = 119,
139		FCC3 = 120,
140		G0 = 121,
141		G1 = 122,
142		G2 = 123,
143		G3 = 124,
144		G4 = 125,
145		G5 = 126,
146		G6 = 127,
147		G7 = 128,
148		I0 = 129,
149		I1 = 130,
150		I2 = 131,
151		I3 = 132,
152		I4 = 133,
153		I5 = 134,
154		I6 = 135,
155		I7 = 136,
156		L0 = 137,
157		L1 = 138,
158		L2 = 139,
159		L3 = 140,
160		L4 = 141,
161		L5 = 142,
162		L6 = 143,
163		L7 = 144,
164		O0 = 145,
165		O1 = 146,
166		O2 = 147,
167		O3 = 148,
168		O4 = 149,
169		O5 = 150,
170		O6 = 151,
171		O7 = 152,
172		Q0 = 153,
173		Q1 = 154,
174		Q2 = 155,
175		Q3 = 156,
176		Q4 = 157,
177		Q5 = 158,
178		Q6 = 159,
179		Q7 = 160,
180		Q8 = 161,
181		Q9 = 162,
182		Q10 = 163,
183		Q11 = 164,
184		Q12 = 165,
185		Q13 = 166,
186		Q14 = 167,
187		Q15 = 168,
188		G0_G1 = 169,
189		G2_G3 = 170,
190		G4_G5 = 171,
191		G6_G7 = 172,
192		I0_I1 = 173,
193		I2_I3 = 174,
194		I4_I5 = 175,
195		I6_I7 = 176,
196		L0_L1 = 177,
197		L2_L3 = 178,
198		L4_L5 = 179,
199		L6_L7 = 180,
200		O0_O1 = 181,
201		O2_O3 = 182,
202		O4_O5 = 183,
203		O6_O7 = 184,
204		NUM_TARGET_REGS // 185
205		};
206		}
207
208		// Register classes
209		namespace SP {
210		enum {
211		FCCRegsRegClassID = 0,
212		ASRRegsRegClassID = 1,
213		FPRegsRegClassID = 2,
214		IntRegsRegClassID = 3,
215		DFPRegsRegClassID = 4,
216		I64RegsRegClassID = 5,
217		DFPRegs_with_sub_evenRegClassID = 6,
218		IntPairRegClassID = 7,
219		PRRegsRegClassID = 8,
220		QFPRegsRegClassID = 9,
221		QFPRegs_with_sub_evenRegClassID = 10,
222
223		};
224		}
225
226		// Subregister indices
227		namespace SP {
228		enum {
229		NoSubRegister,
230		sub_even, // 1
231		sub_even64, // 2
232		sub_odd, // 3
233		sub_odd64, // 4
234		sub_odd64_then_sub_even, // 5
235		sub_odd64_then_sub_odd, // 6
236		NUM_TARGET_SUBREGS
237		};
238		}
239		} // End llvm namespace
240		#endif // GET_REGINFO_ENUM
241
242		/===- TableGen'erated file -------------------------------------- C++ --===\
243		\|* *\|
244		\|* MC Register Information *\|
245		\|* *\|
246		\|* Automatically generated file, do not edit! *\|
247		\|* *\|
248		\===----------------------------------------------------------------------===/
249
250
251		#ifdef GET_REGINFO_MC_DESC
252		#undef GET_REGINFO_MC_DESC
253		namespace llvm_ks {
254
255		extern const MCPhysReg SparcRegDiffLists[] = {
256		/* 0 */ 64976, 1, 1, 1, 0,
257		/* 5 */ 32, 1, 0,
258		/* 8 */ 65436, 32, 1, 65504, 33, 1, 0,
259		/* 15 */ 34, 1, 0,
260		/* 18 */ 65437, 34, 1, 65502, 35, 1, 0,
261		/* 25 */ 36, 1, 0,
262		/* 28 */ 65438, 36, 1, 65500, 37, 1, 0,
263		/* 35 */ 38, 1, 0,
264		/* 38 */ 65439, 38, 1, 65498, 39, 1, 0,
265		/* 45 */ 40, 1, 0,
266		/* 48 */ 65440, 40, 1, 65496, 41, 1, 0,
267		/* 55 */ 42, 1, 0,
268		/* 58 */ 65441, 42, 1, 65494, 43, 1, 0,
269		/* 65 */ 44, 1, 0,
270		/* 68 */ 65442, 44, 1, 65492, 45, 1, 0,
271		/* 75 */ 46, 1, 0,
272		/* 78 */ 65443, 46, 1, 65490, 47, 1, 0,
273		/* 85 */ 65298, 1, 0,
274		/* 88 */ 65302, 1, 0,
275		/* 91 */ 65444, 1, 0,
276		/* 94 */ 65445, 1, 0,
277		/* 97 */ 65446, 1, 0,
278		/* 100 */ 65447, 1, 0,
279		/* 103 */ 65448, 1, 0,
280		/* 106 */ 65449, 1, 0,
281		/* 109 */ 65450, 1, 0,
282		/* 112 */ 65451, 1, 0,
283		/* 115 */ 65482, 1, 0,
284		/* 118 */ 65488, 1, 0,
285		/* 121 */ 65489, 1, 0,
286		/* 124 */ 65490, 1, 0,
287		/* 127 */ 65491, 1, 0,
288		/* 130 */ 65492, 1, 0,
289		/* 133 */ 65493, 1, 0,
290		/* 136 */ 65494, 1, 0,
291		/* 139 */ 65495, 1, 0,
292		/* 142 */ 65496, 1, 0,
293		/* 145 */ 65497, 1, 0,
294		/* 148 */ 65498, 1, 0,
295		/* 151 */ 65499, 1, 0,
296		/* 154 */ 65500, 1, 0,
297		/* 157 */ 65501, 1, 0,
298		/* 160 */ 65502, 1, 0,
299		/* 163 */ 65503, 1, 0,
300		/* 166 */ 15, 0,
301		/* 168 */ 32, 0,
302		/* 170 */ 33, 0,
303		/* 172 */ 34, 0,
304		/* 174 */ 35, 0,
305		/* 176 */ 36, 0,
306		/* 178 */ 37, 0,
307		/* 180 */ 38, 0,
308		/* 182 */ 39, 0,
309		/* 184 */ 40, 0,
310		/* 186 */ 41, 0,
311		/* 188 */ 42, 0,
312		/* 190 */ 43, 0,
313		/* 192 */ 44, 0,
314		/* 194 */ 45, 0,
315		/* 196 */ 46, 0,
316		/* 198 */ 47, 0,
317		/* 200 */ 48, 0,
318		/* 202 */ 84, 0,
319		/* 204 */ 85, 0,
320		/* 206 */ 86, 0,
321		/* 208 */ 87, 0,
322		/* 210 */ 88, 0,
323		/* 212 */ 89, 0,
324		/* 214 */ 90, 0,
325		/* 216 */ 91, 0,
326		/* 218 */ 65488, 92, 0,
327		/* 221 */ 65489, 92, 0,
328		/* 224 */ 65489, 93, 0,
329		/* 227 */ 65490, 93, 0,
330		/* 230 */ 65491, 93, 0,
331		/* 233 */ 65491, 94, 0,
332		/* 236 */ 65492, 94, 0,
333		/* 239 */ 65493, 94, 0,
334		/* 242 */ 65493, 95, 0,
335		/* 245 */ 65494, 95, 0,
336		/* 248 */ 65495, 95, 0,
337		/* 251 */ 65495, 96, 0,
338		/* 254 */ 65496, 96, 0,
339		/* 257 */ 65497, 96, 0,
340		/* 260 */ 65497, 97, 0,
341		/* 263 */ 65498, 97, 0,
342		/* 266 */ 65499, 97, 0,
343		/* 269 */ 65499, 98, 0,
344		/* 272 */ 65500, 98, 0,
345		/* 275 */ 65501, 98, 0,
346		/* 278 */ 65501, 99, 0,
347		/* 281 */ 65502, 99, 0,
348		/* 284 */ 65503, 99, 0,
349		/* 287 */ 65503, 100, 0,
350		/* 290 */ 65504, 100, 0,
351		/* 293 */ 65503, 0,
352		/* 295 */ 65519, 0,
353		/* 297 */ 65535, 0,
354		};
355
356		extern const unsigned SparcLaneMaskLists[] = {
357		/* 0 */ 0x00000000, ~0u,
358		/* 2 */ 0x00000001, 0x00000002, ~0u,
359		/* 5 */ 0x00000001, 0x00000002, 0x00000004, 0x00000008, ~0u,
360		/* 10 */ 0x00000003, 0x0000000C, ~0u,
361		};
362
363		extern const uint16_t SparcSubRegIdxLists[] = {
364		/* 0 */ 1, 3, 0,
365		/* 3 */ 2, 4, 0,
366		/* 6 */ 2, 1, 3, 4, 5, 6, 0,
367		};
368
369		extern const MCRegisterInfo::SubRegCoveredBits SparcSubRegIdxRanges[] = {
370		{ 65535, 65535 },
371		{ 0, 32 }, // sub_even
372		{ 0, 64 }, // sub_even64
373		{ 32, 32 }, // sub_odd
374		{ 64, 64 }, // sub_odd64
375		{ 64, 32 }, // sub_odd64_then_sub_even
376		{ 96, 32 }, // sub_odd64_then_sub_odd
377		};
378
379		extern const char SparcRegStrings[] = {
380		/* 0 */ 'D', '1', '0', 0,
381		/* 4 */ 'F', '1', '0', 0,
382		/* 8 */ 'Q', '1', '0', 0,
383		/* 12 */ 'A', 'S', 'R', '1', '0', 0,
384		/* 18 */ 'D', '2', '0', 0,
385		/* 22 */ 'F', '2', '0', 0,
386		/* 26 */ 'A', 'S', 'R', '2', '0', 0,
387		/* 32 */ 'D', '3', '0', 0,
388		/* 36 */ 'F', '3', '0', 0,
389		/* 40 */ 'A', 'S', 'R', '3', '0', 0,
390		/* 46 */ 'F', 'C', 'C', '0', 0,
391		/* 51 */ 'D', '0', 0,
392		/* 54 */ 'F', '0', 0,
393		/* 57 */ 'G', '0', 0,
394		/* 60 */ 'I', '0', 0,
395		/* 63 */ 'L', '0', 0,
396		/* 66 */ 'O', '0', 0,
397		/* 69 */ 'Q', '0', 0,
398		/* 72 */ 'D', '1', '1', 0,
399		/* 76 */ 'F', '1', '1', 0,
400		/* 80 */ 'Q', '1', '1', 0,
401		/* 84 */ 'A', 'S', 'R', '1', '1', 0,
402		/* 90 */ 'D', '2', '1', 0,
403		/* 94 */ 'F', '2', '1', 0,
404		/* 98 */ 'A', 'S', 'R', '2', '1', 0,
405		/* 104 */ 'D', '3', '1', 0,
406		/* 108 */ 'F', '3', '1', 0,
407		/* 112 */ 'A', 'S', 'R', '3', '1', 0,
408		/* 118 */ 'F', 'C', 'C', '1', 0,
409		/* 123 */ 'D', '1', 0,
410		/* 126 */ 'F', '1', 0,
411		/* 129 */ 'G', '0', '_', 'G', '1', 0,
412		/* 135 */ 'I', '0', '_', 'I', '1', 0,
413		/* 141 */ 'L', '0', '_', 'L', '1', 0,
414		/* 147 */ 'O', '0', '_', 'O', '1', 0,
415		/* 153 */ 'Q', '1', 0,
416		/* 156 */ 'A', 'S', 'R', '1', 0,
417		/* 161 */ 'D', '1', '2', 0,
418		/* 165 */ 'F', '1', '2', 0,
419		/* 169 */ 'Q', '1', '2', 0,
420		/* 173 */ 'A', 'S', 'R', '1', '2', 0,
421		/* 179 */ 'D', '2', '2', 0,
422		/* 183 */ 'F', '2', '2', 0,
423		/* 187 */ 'A', 'S', 'R', '2', '2', 0,
424		/* 193 */ 'F', 'C', 'C', '2', 0,
425		/* 198 */ 'D', '2', 0,
426		/* 201 */ 'F', '2', 0,
427		/* 204 */ 'G', '2', 0,
428		/* 207 */ 'I', '2', 0,
429		/* 210 */ 'L', '2', 0,
430		/* 213 */ 'O', '2', 0,
431		/* 216 */ 'Q', '2', 0,
432		/* 219 */ 'A', 'S', 'R', '2', 0,
433		/* 224 */ 'D', '1', '3', 0,
434		/* 228 */ 'F', '1', '3', 0,
435		/* 232 */ 'Q', '1', '3', 0,
436		/* 236 */ 'A', 'S', 'R', '1', '3', 0,
437		/* 242 */ 'D', '2', '3', 0,
438		/* 246 */ 'F', '2', '3', 0,
439		/* 250 */ 'A', 'S', 'R', '2', '3', 0,
440		/* 256 */ 'F', 'C', 'C', '3', 0,
441		/* 261 */ 'D', '3', 0,
442		/* 264 */ 'F', '3', 0,
443		/* 267 */ 'G', '2', '_', 'G', '3', 0,
444		/* 273 */ 'I', '2', '_', 'I', '3', 0,
445		/* 279 */ 'L', '2', '_', 'L', '3', 0,
446		/* 285 */ 'O', '2', '_', 'O', '3', 0,
447		/* 291 */ 'Q', '3', 0,
448		/* 294 */ 'A', 'S', 'R', '3', 0,
449		/* 299 */ 'D', '1', '4', 0,
450		/* 303 */ 'F', '1', '4', 0,
451		/* 307 */ 'Q', '1', '4', 0,
452		/* 311 */ 'A', 'S', 'R', '1', '4', 0,
453		/* 317 */ 'D', '2', '4', 0,
454		/* 321 */ 'F', '2', '4', 0,
455		/* 325 */ 'A', 'S', 'R', '2', '4', 0,
456		/* 331 */ 'D', '4', 0,
457		/* 334 */ 'F', '4', 0,
458		/* 337 */ 'G', '4', 0,
459		/* 340 */ 'I', '4', 0,
460		/* 343 */ 'L', '4', 0,
461		/* 346 */ 'O', '4', 0,
462		/* 349 */ 'Q', '4', 0,
463		/* 352 */ 'A', 'S', 'R', '4', 0,
464		/* 357 */ 'D', '1', '5', 0,
465		/* 361 */ 'F', '1', '5', 0,
466		/* 365 */ 'Q', '1', '5', 0,
467		/* 369 */ 'A', 'S', 'R', '1', '5', 0,
468		/* 375 */ 'D', '2', '5', 0,
469		/* 379 */ 'F', '2', '5', 0,
470		/* 383 */ 'A', 'S', 'R', '2', '5', 0,
471		/* 389 */ 'D', '5', 0,
472		/* 392 */ 'F', '5', 0,
473		/* 395 */ 'G', '4', '_', 'G', '5', 0,
474		/* 401 */ 'I', '4', '_', 'I', '5', 0,
475		/* 407 */ 'L', '4', '_', 'L', '5', 0,
476		/* 413 */ 'O', '4', '_', 'O', '5', 0,
477		/* 419 */ 'Q', '5', 0,
478		/* 422 */ 'A', 'S', 'R', '5', 0,
479		/* 427 */ 'D', '1', '6', 0,
480		/* 431 */ 'F', '1', '6', 0,
481		/* 435 */ 'A', 'S', 'R', '1', '6', 0,
482		/* 441 */ 'D', '2', '6', 0,
483		/* 445 */ 'F', '2', '6', 0,
484		/* 449 */ 'A', 'S', 'R', '2', '6', 0,
485		/* 455 */ 'D', '6', 0,
486		/* 458 */ 'F', '6', 0,
487		/* 461 */ 'G', '6', 0,
488		/* 464 */ 'I', '6', 0,
489		/* 467 */ 'L', '6', 0,
490		/* 470 */ 'O', '6', 0,
491		/* 473 */ 'Q', '6', 0,
492		/* 476 */ 'A', 'S', 'R', '6', 0,
493		/* 481 */ 'D', '1', '7', 0,
494		/* 485 */ 'F', '1', '7', 0,
495		/* 489 */ 'A', 'S', 'R', '1', '7', 0,
496		/* 495 */ 'D', '2', '7', 0,
497		/* 499 */ 'F', '2', '7', 0,
498		/* 503 */ 'A', 'S', 'R', '2', '7', 0,
499		/* 509 */ 'D', '7', 0,
500		/* 512 */ 'F', '7', 0,
501		/* 515 */ 'G', '6', '_', 'G', '7', 0,
502		/* 521 */ 'I', '6', '_', 'I', '7', 0,
503		/* 527 */ 'L', '6', '_', 'L', '7', 0,
504		/* 533 */ 'O', '6', '_', 'O', '7', 0,
505		/* 539 */ 'Q', '7', 0,
506		/* 542 */ 'A', 'S', 'R', '7', 0,
507		/* 547 */ 'D', '1', '8', 0,
508		/* 551 */ 'F', '1', '8', 0,
509		/* 555 */ 'A', 'S', 'R', '1', '8', 0,
510		/* 561 */ 'D', '2', '8', 0,
511		/* 565 */ 'F', '2', '8', 0,
512		/* 569 */ 'A', 'S', 'R', '2', '8', 0,
513		/* 575 */ 'D', '8', 0,
514		/* 578 */ 'F', '8', 0,
515		/* 581 */ 'Q', '8', 0,
516		/* 584 */ 'A', 'S', 'R', '8', 0,
517		/* 589 */ 'D', '1', '9', 0,
518		/* 593 */ 'F', '1', '9', 0,
519		/* 597 */ 'A', 'S', 'R', '1', '9', 0,
520		/* 603 */ 'D', '2', '9', 0,
521		/* 607 */ 'F', '2', '9', 0,
522		/* 611 */ 'A', 'S', 'R', '2', '9', 0,
523		/* 617 */ 'D', '9', 0,
524		/* 620 */ 'F', '9', 0,
525		/* 623 */ 'Q', '9', 0,
526		/* 626 */ 'A', 'S', 'R', '9', 0,
527		/* 631 */ 'T', 'B', 'A', 0,
528		/* 635 */ 'I', 'C', 'C', 0,
529		/* 639 */ 'T', 'N', 'P', 'C', 0,
530		/* 644 */ 'T', 'P', 'C', 0,
531		/* 648 */ 'C', 'A', 'N', 'R', 'E', 'S', 'T', 'O', 'R', 'E', 0,
532		/* 659 */ 'P', 'S', 'T', 'A', 'T', 'E', 0,
533		/* 666 */ 'T', 'S', 'T', 'A', 'T', 'E', 0,
534		/* 673 */ 'W', 'S', 'T', 'A', 'T', 'E', 0,
535		/* 680 */ 'C', 'A', 'N', 'S', 'A', 'V', 'E', 0,
536		/* 688 */ 'T', 'I', 'C', 'K', 0,
537		/* 693 */ 'P', 'I', 'L', 0,
538		/* 697 */ 'T', 'L', 0,
539		/* 700 */ 'W', 'I', 'M', 0,
540		/* 704 */ 'C', 'L', 'E', 'A', 'N', 'W', 'I', 'N', 0,
541		/* 713 */ 'O', 'T', 'H', 'E', 'R', 'W', 'I', 'N', 0,
542		/* 722 */ 'C', 'W', 'P', 0,
543		/* 726 */ 'T', 'B', 'R', 0,
544		/* 730 */ 'F', 'S', 'R', 0,
545		/* 734 */ 'P', 'S', 'R', 0,
546		/* 738 */ 'T', 'T', 0,
547		/* 741 */ 'Y', 0,
548		};
549
550		extern const MCRegisterDesc SparcRegDesc[] = { // Descriptors
551		{ 3, 0, 0, 0, 0, 0 },
552		{ 648, 4, 4, 2, 4753, 0 },
553		{ 680, 4, 4, 2, 4753, 0 },
554		{ 704, 4, 4, 2, 4753, 0 },
555		{ 722, 4, 4, 2, 4753, 0 },
556		{ 730, 4, 4, 2, 4753, 0 },
557		{ 635, 4, 4, 2, 4753, 0 },
558		{ 713, 4, 4, 2, 4753, 0 },
559		{ 693, 4, 4, 2, 4753, 0 },
560		{ 734, 4, 4, 2, 4753, 0 },
561		{ 659, 4, 4, 2, 4753, 0 },
562		{ 631, 4, 4, 2, 4753, 0 },
563		{ 726, 4, 4, 2, 4753, 0 },
564		{ 688, 4, 4, 2, 4753, 0 },
565		{ 697, 4, 4, 2, 4753, 0 },
566		{ 639, 4, 4, 2, 4753, 0 },
567		{ 644, 4, 4, 2, 4753, 0 },
568		{ 666, 4, 4, 2, 4753, 0 },
569		{ 738, 4, 4, 2, 4753, 0 },
570		{ 700, 4, 4, 2, 4753, 0 },
571		{ 673, 4, 4, 2, 4753, 0 },
572		{ 741, 4, 4, 2, 4753, 0 },
573		{ 156, 4, 4, 2, 4753, 0 },
574		{ 219, 4, 4, 2, 4753, 0 },
575		{ 294, 4, 4, 2, 4753, 0 },
576		{ 352, 4, 4, 2, 4753, 0 },
577		{ 422, 4, 4, 2, 4753, 0 },
578		{ 476, 4, 4, 2, 4753, 0 },
579		{ 542, 4, 4, 2, 4753, 0 },
580		{ 584, 4, 4, 2, 4753, 0 },
581		{ 626, 4, 4, 2, 4753, 0 },
582		{ 12, 4, 4, 2, 4753, 0 },
583		{ 84, 4, 4, 2, 4753, 0 },
584		{ 173, 4, 4, 2, 4753, 0 },
585		{ 236, 4, 4, 2, 4753, 0 },
586		{ 311, 4, 4, 2, 4753, 0 },
587		{ 369, 4, 4, 2, 4753, 0 },
588		{ 435, 4, 4, 2, 4753, 0 },
589		{ 489, 4, 4, 2, 4753, 0 },
590		{ 555, 4, 4, 2, 4753, 0 },
591		{ 597, 4, 4, 2, 4753, 0 },
592		{ 26, 4, 4, 2, 4753, 0 },
593		{ 98, 4, 4, 2, 4753, 0 },
594		{ 187, 4, 4, 2, 4753, 0 },
595		{ 250, 4, 4, 2, 4753, 0 },
596		{ 325, 4, 4, 2, 4753, 0 },
597		{ 383, 4, 4, 2, 4753, 0 },
598		{ 449, 4, 4, 2, 4753, 0 },
599		{ 503, 4, 4, 2, 4753, 0 },
600		{ 569, 4, 4, 2, 4753, 0 },
601		{ 611, 4, 4, 2, 4753, 0 },
602		{ 40, 4, 4, 2, 4753, 0 },
603		{ 112, 4, 4, 2, 4753, 0 },
604		{ 51, 5, 288, 0, 1842, 2 },
605		{ 123, 12, 279, 0, 1842, 2 },
606		{ 198, 15, 279, 0, 1842, 2 },
607		{ 261, 22, 270, 0, 1842, 2 },
608		{ 331, 25, 270, 0, 1842, 2 },
609		{ 389, 32, 261, 0, 1842, 2 },
610		{ 455, 35, 261, 0, 1842, 2 },
611		{ 509, 42, 252, 0, 1842, 2 },
612		{ 575, 45, 252, 0, 1842, 2 },
613		{ 617, 52, 243, 0, 1842, 2 },
614		{ 0, 55, 243, 0, 1842, 2 },
615		{ 72, 62, 234, 0, 1842, 2 },
616		{ 161, 65, 234, 0, 1842, 2 },
617		{ 224, 72, 225, 0, 1842, 2 },
618		{ 299, 75, 225, 0, 1842, 2 },
619		{ 357, 82, 219, 0, 1842, 2 },
620		{ 427, 4, 219, 2, 2657, 0 },
621		{ 481, 4, 216, 2, 2657, 0 },
622		{ 547, 4, 216, 2, 2657, 0 },
623		{ 589, 4, 214, 2, 2657, 0 },
624		{ 18, 4, 214, 2, 2657, 0 },
625		{ 90, 4, 212, 2, 2657, 0 },
626		{ 179, 4, 212, 2, 2657, 0 },
627		{ 242, 4, 210, 2, 2657, 0 },
628		{ 317, 4, 210, 2, 2657, 0 },
629		{ 375, 4, 208, 2, 2657, 0 },
630		{ 441, 4, 208, 2, 2657, 0 },
631		{ 495, 4, 206, 2, 2657, 0 },
632		{ 561, 4, 206, 2, 2657, 0 },
633		{ 603, 4, 204, 2, 2657, 0 },
634		{ 32, 4, 204, 2, 2657, 0 },
635		{ 104, 4, 202, 2, 2657, 0 },
636		{ 54, 4, 290, 2, 4689, 0 },
637		{ 126, 4, 287, 2, 4689, 0 },
638		{ 201, 4, 284, 2, 4689, 0 },
639		{ 264, 4, 281, 2, 4689, 0 },
640		{ 334, 4, 281, 2, 4689, 0 },
641		{ 392, 4, 278, 2, 4689, 0 },
642		{ 458, 4, 275, 2, 4689, 0 },
643		{ 512, 4, 272, 2, 4689, 0 },
644		{ 578, 4, 272, 2, 4689, 0 },
645		{ 620, 4, 269, 2, 4689, 0 },
646		{ 4, 4, 266, 2, 4689, 0 },
647		{ 76, 4, 263, 2, 4689, 0 },
648		{ 165, 4, 263, 2, 4689, 0 },
649		{ 228, 4, 260, 2, 4689, 0 },
650		{ 303, 4, 257, 2, 4689, 0 },
651		{ 361, 4, 254, 2, 4689, 0 },
652		{ 431, 4, 254, 2, 4689, 0 },
653		{ 485, 4, 251, 2, 4689, 0 },
654		{ 551, 4, 248, 2, 4689, 0 },
655		{ 593, 4, 245, 2, 4689, 0 },
656		{ 22, 4, 245, 2, 4689, 0 },
657		{ 94, 4, 242, 2, 4689, 0 },
658		{ 183, 4, 239, 2, 4689, 0 },
659		{ 246, 4, 236, 2, 4689, 0 },
660		{ 321, 4, 236, 2, 4689, 0 },
661		{ 379, 4, 233, 2, 4689, 0 },
662		{ 445, 4, 230, 2, 4689, 0 },
663		{ 499, 4, 227, 2, 4689, 0 },
664		{ 565, 4, 227, 2, 4689, 0 },
665		{ 607, 4, 224, 2, 4689, 0 },
666		{ 36, 4, 221, 2, 4689, 0 },
667		{ 108, 4, 218, 2, 4689, 0 },
668		{ 46, 4, 4, 2, 4721, 0 },
669		{ 118, 4, 4, 2, 4721, 0 },
670		{ 193, 4, 4, 2, 4721, 0 },
671		{ 256, 4, 4, 2, 4721, 0 },
672		{ 57, 4, 200, 2, 4721, 0 },
673		{ 132, 4, 198, 2, 4721, 0 },
674		{ 204, 4, 198, 2, 4721, 0 },
675		{ 270, 4, 196, 2, 4721, 0 },
676		{ 337, 4, 196, 2, 4721, 0 },
677		{ 398, 4, 194, 2, 4721, 0 },
678		{ 461, 4, 194, 2, 4721, 0 },
679		{ 518, 4, 192, 2, 4721, 0 },
680		{ 60, 4, 192, 2, 4721, 0 },
681		{ 138, 4, 190, 2, 4721, 0 },
682		{ 207, 4, 190, 2, 4721, 0 },
683		{ 276, 4, 188, 2, 4721, 0 },
684		{ 340, 4, 188, 2, 4721, 0 },
685		{ 404, 4, 186, 2, 4721, 0 },
686		{ 464, 4, 186, 2, 4721, 0 },
687		{ 524, 4, 184, 2, 4721, 0 },
688		{ 63, 4, 184, 2, 4721, 0 },
689		{ 144, 4, 182, 2, 4721, 0 },
690		{ 210, 4, 182, 2, 4721, 0 },
691		{ 282, 4, 180, 2, 4721, 0 },
692		{ 343, 4, 180, 2, 4721, 0 },
693		{ 410, 4, 178, 2, 4721, 0 },
694		{ 467, 4, 178, 2, 4721, 0 },
695		{ 530, 4, 176, 2, 4721, 0 },
696		{ 66, 4, 176, 2, 4721, 0 },
697		{ 150, 4, 174, 2, 4721, 0 },
698		{ 213, 4, 174, 2, 4721, 0 },
699		{ 288, 4, 172, 2, 4721, 0 },
700		{ 346, 4, 172, 2, 4721, 0 },
701		{ 416, 4, 170, 2, 4721, 0 },
702		{ 470, 4, 170, 2, 4721, 0 },
703		{ 536, 4, 168, 2, 4721, 0 },
704		{ 69, 8, 4, 6, 4, 5 },
705		{ 153, 18, 4, 6, 4, 5 },
706		{ 216, 28, 4, 6, 4, 5 },
707		{ 291, 38, 4, 6, 4, 5 },
708		{ 349, 48, 4, 6, 4, 5 },
709		{ 419, 58, 4, 6, 4, 5 },
710		{ 473, 68, 4, 6, 4, 5 },
711		{ 539, 78, 4, 6, 4, 5 },
712		{ 581, 91, 4, 3, 1362, 10 },
713		{ 623, 94, 4, 3, 1362, 10 },
714		{ 8, 97, 4, 3, 1362, 10 },
715		{ 80, 100, 4, 3, 1362, 10 },
716		{ 169, 103, 4, 3, 1362, 10 },
717		{ 232, 106, 4, 3, 1362, 10 },
718		{ 307, 109, 4, 3, 1362, 10 },
719		{ 365, 112, 4, 3, 1362, 10 },
720		{ 129, 118, 4, 0, 1410, 2 },
721		{ 267, 121, 4, 0, 1410, 2 },
722		{ 395, 124, 4, 0, 1410, 2 },
723		{ 515, 127, 4, 0, 1410, 2 },
724		{ 135, 130, 4, 0, 1410, 2 },
725		{ 273, 133, 4, 0, 1410, 2 },
726		{ 401, 136, 4, 0, 1410, 2 },
727		{ 521, 139, 4, 0, 1410, 2 },
728		{ 141, 142, 4, 0, 1410, 2 },
729		{ 279, 145, 4, 0, 1410, 2 },
730		{ 407, 148, 4, 0, 1410, 2 },
731		{ 527, 151, 4, 0, 1410, 2 },
732		{ 147, 154, 4, 0, 1410, 2 },
733		{ 285, 157, 4, 0, 1410, 2 },
734		{ 413, 160, 4, 0, 1410, 2 },
735		{ 533, 163, 4, 0, 1410, 2 },
736		};
737
738		extern const MCPhysReg SparcRegUnitRoots[][2] = {
739		{ SP::CANRESTORE },
740		{ SP::CANSAVE },
741		{ SP::CLEANWIN },
742		{ SP::CWP },
743		{ SP::FSR },
744		{ SP::ICC },
745		{ SP::OTHERWIN },
746		{ SP::PIL },
747		{ SP::PSR },
748		{ SP::PSTATE },
749		{ SP::TBA },
750		{ SP::TBR },
751		{ SP::TICK },
752		{ SP::TL },
753		{ SP::TNPC },
754		{ SP::TPC },
755		{ SP::TSTATE },
756		{ SP::TT },
757		{ SP::WIM },
758		{ SP::WSTATE },
759		{ SP::Y },
760		{ SP::ASR1 },
761		{ SP::ASR2 },
762		{ SP::ASR3 },
763		{ SP::ASR4 },
764		{ SP::ASR5 },
765		{ SP::ASR6 },
766		{ SP::ASR7 },
767		{ SP::ASR8 },
768		{ SP::ASR9 },
769		{ SP::ASR10 },
770		{ SP::ASR11 },
771		{ SP::ASR12 },
772		{ SP::ASR13 },
773		{ SP::ASR14 },
774		{ SP::ASR15 },
775		{ SP::ASR16 },
776		{ SP::ASR17 },
777		{ SP::ASR18 },
778		{ SP::ASR19 },
779		{ SP::ASR20 },
780		{ SP::ASR21 },
781		{ SP::ASR22 },
782		{ SP::ASR23 },
783		{ SP::ASR24 },
784		{ SP::ASR25 },
785		{ SP::ASR26 },
786		{ SP::ASR27 },
787		{ SP::ASR28 },
788		{ SP::ASR29 },
789		{ SP::ASR30 },
790		{ SP::ASR31 },
791		{ SP::F0 },
792		{ SP::F1 },
793		{ SP::F2 },
794		{ SP::F3 },
795		{ SP::F4 },
796		{ SP::F5 },
797		{ SP::F6 },
798		{ SP::F7 },
799		{ SP::F8 },
800		{ SP::F9 },
801		{ SP::F10 },
802		{ SP::F11 },
803		{ SP::F12 },
804		{ SP::F13 },
805		{ SP::F14 },
806		{ SP::F15 },
807		{ SP::F16 },
808		{ SP::F17 },
809		{ SP::F18 },
810		{ SP::F19 },
811		{ SP::F20 },
812		{ SP::F21 },
813		{ SP::F22 },
814		{ SP::F23 },
815		{ SP::F24 },
816		{ SP::F25 },
817		{ SP::F26 },
818		{ SP::F27 },
819		{ SP::F28 },
820		{ SP::F29 },
821		{ SP::F30 },
822		{ SP::F31 },
823		{ SP::D16 },
824		{ SP::D17 },
825		{ SP::D18 },
826		{ SP::D19 },
827		{ SP::D20 },
828		{ SP::D21 },
829		{ SP::D22 },
830		{ SP::D23 },
831		{ SP::D24 },
832		{ SP::D25 },
833		{ SP::D26 },
834		{ SP::D27 },
835		{ SP::D28 },
836		{ SP::D29 },
837		{ SP::D30 },
838		{ SP::D31 },
839		{ SP::FCC0 },
840		{ SP::FCC1 },
841		{ SP::FCC2 },
842		{ SP::FCC3 },
843		{ SP::G0 },
844		{ SP::G1 },
845		{ SP::G2 },
846		{ SP::G3 },
847		{ SP::G4 },
848		{ SP::G5 },
849		{ SP::G6 },
850		{ SP::G7 },
851		{ SP::I0 },
852		{ SP::I1 },
853		{ SP::I2 },
854		{ SP::I3 },
855		{ SP::I4 },
856		{ SP::I5 },
857		{ SP::I6 },
858		{ SP::I7 },
859		{ SP::L0 },
860		{ SP::L1 },
861		{ SP::L2 },
862		{ SP::L3 },
863		{ SP::L4 },
864		{ SP::L5 },
865		{ SP::L6 },
866		{ SP::L7 },
867		{ SP::O0 },
868		{ SP::O1 },
869		{ SP::O2 },
870		{ SP::O3 },
871		{ SP::O4 },
872		{ SP::O5 },
873		{ SP::O6 },
874		{ SP::O7 },
875		};
876
877		namespace { // Register classes...
878		// FCCRegs Register Class...
879		const MCPhysReg FCCRegs[] = {
880		SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3,
881		};
882
883		// FCCRegs Bit set.
884		const uint8_t FCCRegsBits[] = {
885		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
886		};
887
888		// ASRRegs Register Class...
889		const MCPhysReg ASRRegs[] = {
890		SP::Y, SP::ASR1, SP::ASR2, SP::ASR3, SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7, SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11, SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15, SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19, SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23, SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27, SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31,
891		};
892
893		// ASRRegs Bit set.
894		const uint8_t ASRRegsBits[] = {
895		0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
896		};
897
898		// FPRegs Register Class...
899		const MCPhysReg FPRegs[] = {
900		SP::F0, SP::F1, SP::F2, SP::F3, SP::F4, SP::F5, SP::F6, SP::F7, SP::F8, SP::F9, SP::F10, SP::F11, SP::F12, SP::F13, SP::F14, SP::F15, SP::F16, SP::F17, SP::F18, SP::F19, SP::F20, SP::F21, SP::F22, SP::F23, SP::F24, SP::F25, SP::F26, SP::F27, SP::F28, SP::F29, SP::F30, SP::F31,
901		};
902
903		// FPRegs Bit set.
904		const uint8_t FPRegsBits[] = {
905		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
906		};
907
908		// IntRegs Register Class...
909		const MCPhysReg IntRegs[] = {
910		SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
911		};
912
913		// IntRegs Bit set.
914		const uint8_t IntRegsBits[] = {
915		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
916		};
917
918		// DFPRegs Register Class...
919		const MCPhysReg DFPRegs[] = {
920		SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15, SP::D16, SP::D17, SP::D18, SP::D19, SP::D20, SP::D21, SP::D22, SP::D23, SP::D24, SP::D25, SP::D26, SP::D27, SP::D28, SP::D29, SP::D30, SP::D31,
921		};
922
923		// DFPRegs Bit set.
924		const uint8_t DFPRegsBits[] = {
925		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
926		};
927
928		// I64Regs Register Class...
929		const MCPhysReg I64Regs[] = {
930		SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5, SP::I6, SP::I7, SP::G0, SP::G1, SP::G2, SP::G3, SP::G4, SP::G5, SP::G6, SP::G7, SP::L0, SP::L1, SP::L2, SP::L3, SP::L4, SP::L5, SP::L6, SP::L7, SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5, SP::O6, SP::O7,
931		};
932
933		// I64Regs Bit set.
934		const uint8_t I64RegsBits[] = {
935		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
936		};
937
938		// DFPRegs_with_sub_even Register Class...
939		const MCPhysReg DFPRegs_with_sub_even[] = {
940		SP::D0, SP::D1, SP::D2, SP::D3, SP::D4, SP::D5, SP::D6, SP::D7, SP::D8, SP::D9, SP::D10, SP::D11, SP::D12, SP::D13, SP::D14, SP::D15,
941		};
942
943		// DFPRegs_with_sub_even Bit set.
944		const uint8_t DFPRegs_with_sub_evenBits[] = {
945		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
946		};
947
948		// IntPair Register Class...
949		const MCPhysReg IntPair[] = {
950		SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7, SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7, SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7, SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
951		};
952
953		// IntPair Bit set.
954		const uint8_t IntPairBits[] = {
955		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
956		};
957
958		// PRRegs Register Class...
959		const MCPhysReg PRRegs[] = {
960		SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE, SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN, SP::OTHERWIN, SP::WSTATE,
961		};
962
963		// PRRegs Bit set.
964		const uint8_t PRRegsBits[] = {
965		0x9e, 0xed, 0x17,
966		};
967
968		// QFPRegs Register Class...
969		const MCPhysReg QFPRegs[] = {
970		SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7, SP::Q8, SP::Q9, SP::Q10, SP::Q11, SP::Q12, SP::Q13, SP::Q14, SP::Q15,
971		};
972
973		// QFPRegs Bit set.
974		const uint8_t QFPRegsBits[] = {
975		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
976		};
977
978		// QFPRegs_with_sub_even Register Class...
979		const MCPhysReg QFPRegs_with_sub_even[] = {
980		SP::Q0, SP::Q1, SP::Q2, SP::Q3, SP::Q4, SP::Q5, SP::Q6, SP::Q7,
981		};
982
983		// QFPRegs_with_sub_even Bit set.
984		const uint8_t QFPRegs_with_sub_evenBits[] = {
985		0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
986		};
987
988		}
989
990		extern const char SparcRegClassStrings[] = {
991		/* 0 */ 'D', 'F', 'P', 'R', 'e', 'g', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'e', 'v', 'e', 'n', 0,
992		/* 22 */ 'Q', 'F', 'P', 'R', 'e', 'g', 's', '_', 'w', 'i', 't', 'h', '_', 's', 'u', 'b', '_', 'e', 'v', 'e', 'n', 0,
993		/* 44 */ 'I', 'n', 't', 'P', 'a', 'i', 'r', 0,
994		/* 52 */ 'I', '6', '4', 'R', 'e', 'g', 's', 0,
995		/* 60 */ 'F', 'C', 'C', 'R', 'e', 'g', 's', 0,
996		/* 68 */ 'D', 'F', 'P', 'R', 'e', 'g', 's', 0,
997		/* 76 */ 'Q', 'F', 'P', 'R', 'e', 'g', 's', 0,
998		/* 84 */ 'P', 'R', 'R', 'e', 'g', 's', 0,
999		/* 91 */ 'A', 'S', 'R', 'R', 'e', 'g', 's', 0,
1000		/* 99 */ 'I', 'n', 't', 'R', 'e', 'g', 's', 0,
1001		};
1002
1003		extern const MCRegisterClass SparcMCRegisterClasses[] = {
1004		{ FCCRegs, FCCRegsBits, 60, 4, sizeof(FCCRegsBits), SP::FCCRegsRegClassID, 0, 0, 1, 1 },
1005		{ ASRRegs, ASRRegsBits, 91, 32, sizeof(ASRRegsBits), SP::ASRRegsRegClassID, 4, 4, 1, 0 },
1006		{ FPRegs, FPRegsBits, 69, 32, sizeof(FPRegsBits), SP::FPRegsRegClassID, 4, 4, 1, 1 },
1007		{ IntRegs, IntRegsBits, 99, 32, sizeof(IntRegsBits), SP::IntRegsRegClassID, 4, 4, 1, 1 },
1008		{ DFPRegs, DFPRegsBits, 68, 32, sizeof(DFPRegsBits), SP::DFPRegsRegClassID, 8, 8, 1, 1 },
1009		{ I64Regs, I64RegsBits, 52, 32, sizeof(I64RegsBits), SP::I64RegsRegClassID, 8, 8, 1, 1 },
1010		{ DFPRegs_with_sub_even, DFPRegs_with_sub_evenBits, 0, 16, sizeof(DFPRegs_with_sub_evenBits), SP::DFPRegs_with_sub_evenRegClassID, 8, 8, 1, 1 },
1011		{ IntPair, IntPairBits, 44, 16, sizeof(IntPairBits), SP::IntPairRegClassID, 8, 8, 1, 1 },
1012		{ PRRegs, PRRegsBits, 84, 15, sizeof(PRRegsBits), SP::PRRegsRegClassID, 8, 8, 1, 1 },
1013		{ QFPRegs, QFPRegsBits, 76, 16, sizeof(QFPRegsBits), SP::QFPRegsRegClassID, 16, 16, 1, 1 },
1014		{ QFPRegs_with_sub_even, QFPRegs_with_sub_evenBits, 22, 8, sizeof(QFPRegs_with_sub_evenBits), SP::QFPRegs_with_sub_evenRegClassID, 16, 16, 1, 1 },
1015		};
1016
1017		// SP Dwarf<->LLVM register mappings.
1018		extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0Dwarf2L[] = {
1019		{ 0U, SP::G0 },
1020		{ 1U, SP::G1 },
1021		{ 2U, SP::G2 },
1022		{ 3U, SP::G3 },
1023		{ 4U, SP::G4 },
1024		{ 5U, SP::G5 },
1025		{ 6U, SP::G6 },
1026		{ 7U, SP::G7 },
1027		{ 8U, SP::O0 },
1028		{ 9U, SP::O1 },
1029		{ 10U, SP::O2 },
1030		{ 11U, SP::O3 },
1031		{ 12U, SP::O4 },
1032		{ 13U, SP::O5 },
1033		{ 14U, SP::O6 },
1034		{ 15U, SP::O7 },
1035		{ 16U, SP::L0 },
1036		{ 17U, SP::L1 },
1037		{ 18U, SP::L2 },
1038		{ 19U, SP::L3 },
1039		{ 20U, SP::L4 },
1040		{ 21U, SP::L5 },
1041		{ 22U, SP::L6 },
1042		{ 23U, SP::L7 },
1043		{ 24U, SP::I0 },
1044		{ 25U, SP::I1 },
1045		{ 26U, SP::I2 },
1046		{ 27U, SP::I3 },
1047		{ 28U, SP::I4 },
1048		{ 29U, SP::I5 },
1049		{ 30U, SP::I6 },
1050		{ 31U, SP::I7 },
1051		{ 32U, SP::F0 },
1052		{ 33U, SP::F1 },
1053		{ 34U, SP::F2 },
1054		{ 35U, SP::F3 },
1055		{ 36U, SP::F4 },
1056		{ 37U, SP::F5 },
1057		{ 38U, SP::F6 },
1058		{ 39U, SP::F7 },
1059		{ 40U, SP::F8 },
1060		{ 41U, SP::F9 },
1061		{ 42U, SP::F10 },
1062		{ 43U, SP::F11 },
1063		{ 44U, SP::F12 },
1064		{ 45U, SP::F13 },
1065		{ 46U, SP::F14 },
1066		{ 47U, SP::F15 },
1067		{ 48U, SP::F16 },
1068		{ 49U, SP::F17 },
1069		{ 50U, SP::F18 },
1070		{ 51U, SP::F19 },
1071		{ 52U, SP::F20 },
1072		{ 53U, SP::F21 },
1073		{ 54U, SP::F22 },
1074		{ 55U, SP::F23 },
1075		{ 56U, SP::F24 },
1076		{ 57U, SP::F25 },
1077		{ 58U, SP::F26 },
1078		{ 59U, SP::F27 },
1079		{ 60U, SP::F28 },
1080		{ 61U, SP::F29 },
1081		{ 62U, SP::F30 },
1082		{ 63U, SP::F31 },
1083		{ 64U, SP::Y },
1084		{ 72U, SP::D0 },
1085		{ 73U, SP::D1 },
1086		{ 74U, SP::D2 },
1087		{ 75U, SP::D3 },
1088		{ 76U, SP::D4 },
1089		{ 77U, SP::D5 },
1090		{ 78U, SP::D6 },
1091		{ 79U, SP::D7 },
1092		{ 80U, SP::D8 },
1093		{ 81U, SP::D9 },
1094		{ 82U, SP::D10 },
1095		{ 83U, SP::D11 },
1096		{ 84U, SP::D12 },
1097		{ 85U, SP::D13 },
1098		{ 86U, SP::D14 },
1099		{ 87U, SP::D15 },
1100		};
1101		extern const unsigned SPDwarfFlavour0Dwarf2LSize = array_lengthof(SPDwarfFlavour0Dwarf2L);
1102
1103		extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0Dwarf2L[] = {
1104		{ 0U, SP::G0 },
1105		{ 1U, SP::G1 },
1106		{ 2U, SP::G2 },
1107		{ 3U, SP::G3 },
1108		{ 4U, SP::G4 },
1109		{ 5U, SP::G5 },
1110		{ 6U, SP::G6 },
1111		{ 7U, SP::G7 },
1112		{ 8U, SP::O0 },
1113		{ 9U, SP::O1 },
1114		{ 10U, SP::O2 },
1115		{ 11U, SP::O3 },
1116		{ 12U, SP::O4 },
1117		{ 13U, SP::O5 },
1118		{ 14U, SP::O6 },
1119		{ 15U, SP::O7 },
1120		{ 16U, SP::L0 },
1121		{ 17U, SP::L1 },
1122		{ 18U, SP::L2 },
1123		{ 19U, SP::L3 },
1124		{ 20U, SP::L4 },
1125		{ 21U, SP::L5 },
1126		{ 22U, SP::L6 },
1127		{ 23U, SP::L7 },
1128		{ 24U, SP::I0 },
1129		{ 25U, SP::I1 },
1130		{ 26U, SP::I2 },
1131		{ 27U, SP::I3 },
1132		{ 28U, SP::I4 },
1133		{ 29U, SP::I5 },
1134		{ 30U, SP::I6 },
1135		{ 31U, SP::I7 },
1136		{ 32U, SP::F0 },
1137		{ 33U, SP::F1 },
1138		{ 34U, SP::F2 },
1139		{ 35U, SP::F3 },
1140		{ 36U, SP::F4 },
1141		{ 37U, SP::F5 },
1142		{ 38U, SP::F6 },
1143		{ 39U, SP::F7 },
1144		{ 40U, SP::F8 },
1145		{ 41U, SP::F9 },
1146		{ 42U, SP::F10 },
1147		{ 43U, SP::F11 },
1148		{ 44U, SP::F12 },
1149		{ 45U, SP::F13 },
1150		{ 46U, SP::F14 },
1151		{ 47U, SP::F15 },
1152		{ 48U, SP::F16 },
1153		{ 49U, SP::F17 },
1154		{ 50U, SP::F18 },
1155		{ 51U, SP::F19 },
1156		{ 52U, SP::F20 },
1157		{ 53U, SP::F21 },
1158		{ 54U, SP::F22 },
1159		{ 55U, SP::F23 },
1160		{ 56U, SP::F24 },
1161		{ 57U, SP::F25 },
1162		{ 58U, SP::F26 },
1163		{ 59U, SP::F27 },
1164		{ 60U, SP::F28 },
1165		{ 61U, SP::F29 },
1166		{ 62U, SP::F30 },
1167		{ 63U, SP::F31 },
1168		{ 64U, SP::Y },
1169		{ 72U, SP::D0 },
1170		{ 73U, SP::D1 },
1171		{ 74U, SP::D2 },
1172		{ 75U, SP::D3 },
1173		{ 76U, SP::D4 },
1174		{ 77U, SP::D5 },
1175		{ 78U, SP::D6 },
1176		{ 79U, SP::D7 },
1177		{ 80U, SP::D8 },
1178		{ 81U, SP::D9 },
1179		{ 82U, SP::D10 },
1180		{ 83U, SP::D11 },
1181		{ 84U, SP::D12 },
1182		{ 85U, SP::D13 },
1183		{ 86U, SP::D14 },
1184		{ 87U, SP::D15 },
1185		};
1186		extern const unsigned SPEHFlavour0Dwarf2LSize = array_lengthof(SPEHFlavour0Dwarf2L);
1187
1188		extern const MCRegisterInfo::DwarfLLVMRegPair SPDwarfFlavour0L2Dwarf[] = {
1189		{ SP::Y, 64U },
1190		{ SP::D0, 72U },
1191		{ SP::D1, 73U },
1192		{ SP::D2, 74U },
1193		{ SP::D3, 75U },
1194		{ SP::D4, 76U },
1195		{ SP::D5, 77U },
1196		{ SP::D6, 78U },
1197		{ SP::D7, 79U },
1198		{ SP::D8, 80U },
1199		{ SP::D9, 81U },
1200		{ SP::D10, 82U },
1201		{ SP::D11, 83U },
1202		{ SP::D12, 84U },
1203		{ SP::D13, 85U },
1204		{ SP::D14, 86U },
1205		{ SP::D15, 87U },
1206		{ SP::F0, 32U },
1207		{ SP::F1, 33U },
1208		{ SP::F2, 34U },
1209		{ SP::F3, 35U },
1210		{ SP::F4, 36U },
1211		{ SP::F5, 37U },
1212		{ SP::F6, 38U },
1213		{ SP::F7, 39U },
1214		{ SP::F8, 40U },
1215		{ SP::F9, 41U },
1216		{ SP::F10, 42U },
1217		{ SP::F11, 43U },
1218		{ SP::F12, 44U },
1219		{ SP::F13, 45U },
1220		{ SP::F14, 46U },
1221		{ SP::F15, 47U },
1222		{ SP::F16, 48U },
1223		{ SP::F17, 49U },
1224		{ SP::F18, 50U },
1225		{ SP::F19, 51U },
1226		{ SP::F20, 52U },
1227		{ SP::F21, 53U },
1228		{ SP::F22, 54U },
1229		{ SP::F23, 55U },
1230		{ SP::F24, 56U },
1231		{ SP::F25, 57U },
1232		{ SP::F26, 58U },
1233		{ SP::F27, 59U },
1234		{ SP::F28, 60U },
1235		{ SP::F29, 61U },
1236		{ SP::F30, 62U },
1237		{ SP::F31, 63U },
1238		{ SP::G0, 0U },
1239		{ SP::G1, 1U },
1240		{ SP::G2, 2U },
1241		{ SP::G3, 3U },
1242		{ SP::G4, 4U },
1243		{ SP::G5, 5U },
1244		{ SP::G6, 6U },
1245		{ SP::G7, 7U },
1246		{ SP::I0, 24U },
1247		{ SP::I1, 25U },
1248		{ SP::I2, 26U },
1249		{ SP::I3, 27U },
1250		{ SP::I4, 28U },
1251		{ SP::I5, 29U },
1252		{ SP::I6, 30U },
1253		{ SP::I7, 31U },
1254		{ SP::L0, 16U },
1255		{ SP::L1, 17U },
1256		{ SP::L2, 18U },
1257		{ SP::L3, 19U },
1258		{ SP::L4, 20U },
1259		{ SP::L5, 21U },
1260		{ SP::L6, 22U },
1261		{ SP::L7, 23U },
1262		{ SP::O0, 8U },
1263		{ SP::O1, 9U },
1264		{ SP::O2, 10U },
1265		{ SP::O3, 11U },
1266		{ SP::O4, 12U },
1267		{ SP::O5, 13U },
1268		{ SP::O6, 14U },
1269		{ SP::O7, 15U },
1270		};
1271		extern const unsigned SPDwarfFlavour0L2DwarfSize = array_lengthof(SPDwarfFlavour0L2Dwarf);
1272
1273		extern const MCRegisterInfo::DwarfLLVMRegPair SPEHFlavour0L2Dwarf[] = {
1274		{ SP::Y, 64U },
1275		{ SP::D0, 72U },
1276		{ SP::D1, 73U },
1277		{ SP::D2, 74U },
1278		{ SP::D3, 75U },
1279		{ SP::D4, 76U },
1280		{ SP::D5, 77U },
1281		{ SP::D6, 78U },
1282		{ SP::D7, 79U },
1283		{ SP::D8, 80U },
1284		{ SP::D9, 81U },
1285		{ SP::D10, 82U },
1286		{ SP::D11, 83U },
1287		{ SP::D12, 84U },
1288		{ SP::D13, 85U },
1289		{ SP::D14, 86U },
1290		{ SP::D15, 87U },
1291		{ SP::F0, 32U },
1292		{ SP::F1, 33U },
1293		{ SP::F2, 34U },
1294		{ SP::F3, 35U },
1295		{ SP::F4, 36U },
1296		{ SP::F5, 37U },
1297		{ SP::F6, 38U },
1298		{ SP::F7, 39U },
1299		{ SP::F8, 40U },
1300		{ SP::F9, 41U },
1301		{ SP::F10, 42U },
1302		{ SP::F11, 43U },
1303		{ SP::F12, 44U },
1304		{ SP::F13, 45U },
1305		{ SP::F14, 46U },
1306		{ SP::F15, 47U },
1307		{ SP::F16, 48U },
1308		{ SP::F17, 49U },
1309		{ SP::F18, 50U },
1310		{ SP::F19, 51U },
1311		{ SP::F20, 52U },
1312		{ SP::F21, 53U },
1313		{ SP::F22, 54U },
1314		{ SP::F23, 55U },
1315		{ SP::F24, 56U },
1316		{ SP::F25, 57U },
1317		{ SP::F26, 58U },
1318		{ SP::F27, 59U },
1319		{ SP::F28, 60U },
1320		{ SP::F29, 61U },
1321		{ SP::F30, 62U },
1322		{ SP::F31, 63U },
1323		{ SP::G0, 0U },
1324		{ SP::G1, 1U },
1325		{ SP::G2, 2U },
1326		{ SP::G3, 3U },
1327		{ SP::G4, 4U },
1328		{ SP::G5, 5U },
1329		{ SP::G6, 6U },
1330		{ SP::G7, 7U },
1331		{ SP::I0, 24U },
1332		{ SP::I1, 25U },
1333		{ SP::I2, 26U },
1334		{ SP::I3, 27U },
1335		{ SP::I4, 28U },
1336		{ SP::I5, 29U },
1337		{ SP::I6, 30U },
1338		{ SP::I7, 31U },
1339		{ SP::L0, 16U },
1340		{ SP::L1, 17U },
1341		{ SP::L2, 18U },
1342		{ SP::L3, 19U },
1343		{ SP::L4, 20U },
1344		{ SP::L5, 21U },
1345		{ SP::L6, 22U },
1346		{ SP::L7, 23U },
1347		{ SP::O0, 8U },
1348		{ SP::O1, 9U },
1349		{ SP::O2, 10U },
1350		{ SP::O3, 11U },
1351		{ SP::O4, 12U },
1352		{ SP::O5, 13U },
1353		{ SP::O6, 14U },
1354		{ SP::O7, 15U },
1355		};
1356		extern const unsigned SPEHFlavour0L2DwarfSize = array_lengthof(SPEHFlavour0L2Dwarf);
1357
1358		extern const uint16_t SparcRegEncodingTable[] = {
1359		0,
1360		11,
1361		10,
1362		12,
1363		9,
1364		0,
1365		0,
1366		13,
1367		8,
1368		0,
1369		6,
1370		5,
1371		0,
1372		4,
1373		7,
1374		1,
1375		0,
1376		2,
1377		3,
1378		0,
1379		14,
1380		0,
1381		1,
1382		2,
1383		3,
1384		4,
1385		5,
1386		6,
1387		7,
1388		8,
1389		9,
1390		10,
1391		11,
1392		12,
1393		13,
1394		14,
1395		15,
1396		16,
1397		17,
1398		18,
1399		19,
1400		20,
1401		21,
1402		22,
1403		23,
1404		24,
1405		25,
1406		26,
1407		27,
1408		28,
1409		29,
1410		30,
1411		31,
1412		0,
1413		2,
1414		4,
1415		6,
1416		8,
1417		10,
1418		12,
1419		14,
1420		16,
1421		18,
1422		20,
1423		22,
1424		24,
1425		26,
1426		28,
1427		30,
1428		1,
1429		3,
1430		5,
1431		7,
1432		9,
1433		11,
1434		13,
1435		15,
1436		17,
1437		19,
1438		21,
1439		23,
1440		25,
1441		27,
1442		29,
1443		31,
1444		0,
1445		1,
1446		2,
1447		3,
1448		4,
1449		5,
1450		6,
1451		7,
1452		8,
1453		9,
1454		10,
1455		11,
1456		12,
1457		13,
1458		14,
1459		15,
1460		16,
1461		17,
1462		18,
1463		19,
1464		20,
1465		21,
1466		22,
1467		23,
1468		24,
1469		25,
1470		26,
1471		27,
1472		28,
1473		29,
1474		30,
1475		31,
1476		0,
1477		1,
1478		2,
1479		3,
1480		0,
1481		1,
1482		2,
1483		3,
1484		4,
1485		5,
1486		6,
1487		7,
1488		24,
1489		25,
1490		26,
1491		27,
1492		28,
1493		29,
1494		30,
1495		31,
1496		16,
1497		17,
1498		18,
1499		19,
1500		20,
1501		21,
1502		22,
1503		23,
1504		8,
1505		9,
1506		10,
1507		11,
1508		12,
1509		13,
1510		14,
1511		15,
1512		0,
1513		4,
1514		8,
1515		12,
1516		16,
1517		20,
1518		24,
1519		28,
1520		1,
1521		5,
1522		9,
1523		13,
1524		17,
1525		21,
1526		25,
1527		29,
1528		0,
1529		2,
1530		4,
1531		6,
1532		24,
1533		26,
1534		28,
1535		30,
1536		16,
1537		18,
1538		20,
1539		22,
1540		8,
1541		10,
1542		12,
1543		14,
1544		};
1545	12.9k	static inline void InitSparcMCRegisterInfo(MCRegisterInfo *RI, unsigned RA, unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {
1546	12.9k	RI->InitMCRegisterInfo(SparcRegDesc, 185, RA, PC, SparcMCRegisterClasses, 11, SparcRegUnitRoots, 136, SparcRegDiffLists, SparcLaneMaskLists, SparcRegStrings, SparcRegClassStrings, SparcSubRegIdxLists, 7,
1547	12.9k	SparcSubRegIdxRanges, SparcRegEncodingTable);
1548
1549	12.9k	switch (DwarfFlavour) {
1550	0	default:
1551	0	llvm_unreachable("Unknown DWARF flavour");
1552	12.9k	case 0:
1553	12.9k	RI->mapDwarfRegsToLLVMRegs(SPDwarfFlavour0Dwarf2L, SPDwarfFlavour0Dwarf2LSize, false);
1554	12.9k	break;
1555	12.9k	}
1556	12.9k	switch (EHFlavour) {
1557	0	default:
1558	0	llvm_unreachable("Unknown DWARF flavour");
1559	12.9k	case 0:
1560	12.9k	RI->mapDwarfRegsToLLVMRegs(SPEHFlavour0Dwarf2L, SPEHFlavour0Dwarf2LSize, true);
1561	12.9k	break;
1562	12.9k	}
1563	12.9k	switch (DwarfFlavour) {
1564	0	default:
1565	0	llvm_unreachable("Unknown DWARF flavour");
1566	12.9k	case 0:
1567	12.9k	RI->mapLLVMRegsToDwarfRegs(SPDwarfFlavour0L2Dwarf, SPDwarfFlavour0L2DwarfSize, false);
1568	12.9k	break;
1569	12.9k	}
1570	12.9k	switch (EHFlavour) {
1571	0	default:
1572	0	llvm_unreachable("Unknown DWARF flavour");
1573	12.9k	case 0:
1574	12.9k	RI->mapLLVMRegsToDwarfRegs(SPEHFlavour0L2Dwarf, SPEHFlavour0L2DwarfSize, true);
1575	12.9k	break;
1576	12.9k	}
1577	12.9k	}
1578
1579		} // End llvm namespace
1580		#endif // GET_REGINFO_MC_DESC

Coverage Report

Created: 2026-06-08 07:05