/src/keystone/llvm/lib/Target/Sparc/SparcGenMCCodeEmitter.inc
Line | Count | Source |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Machine Code Emitter *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | uint64_t SparcMCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI, |
10 | | SmallVectorImpl<MCFixup> &Fixups, |
11 | 6.32k | const MCSubtargetInfo &STI) const { |
12 | 6.32k | static const uint64_t InstBits[] = { |
13 | 6.32k | UINT64_C(0), |
14 | 6.32k | UINT64_C(0), |
15 | 6.32k | UINT64_C(0), |
16 | 6.32k | UINT64_C(0), |
17 | 6.32k | UINT64_C(0), |
18 | 6.32k | UINT64_C(0), |
19 | 6.32k | UINT64_C(0), |
20 | 6.32k | UINT64_C(0), |
21 | 6.32k | UINT64_C(0), |
22 | 6.32k | UINT64_C(0), |
23 | 6.32k | UINT64_C(0), |
24 | 6.32k | UINT64_C(0), |
25 | 6.32k | UINT64_C(0), |
26 | 6.32k | UINT64_C(0), |
27 | 6.32k | UINT64_C(0), |
28 | 6.32k | UINT64_C(0), |
29 | 6.32k | UINT64_C(0), |
30 | 6.32k | UINT64_C(0), |
31 | 6.32k | UINT64_C(0), |
32 | 6.32k | UINT64_C(0), |
33 | 6.32k | UINT64_C(0), |
34 | 6.32k | UINT64_C(0), |
35 | 6.32k | UINT64_C(0), |
36 | 6.32k | UINT64_C(0), |
37 | 6.32k | UINT64_C(2155880448), // ADDCCri |
38 | 6.32k | UINT64_C(2155872256), // ADDCCrr |
39 | 6.32k | UINT64_C(2151686144), // ADDCri |
40 | 6.32k | UINT64_C(2151677952), // ADDCrr |
41 | 6.32k | UINT64_C(2160074752), // ADDEri |
42 | 6.32k | UINT64_C(2160066560), // ADDErr |
43 | 6.32k | UINT64_C(2175795744), // ADDXC |
44 | 6.32k | UINT64_C(2175795808), // ADDXCCC |
45 | 6.32k | UINT64_C(2147491840), // ADDXri |
46 | 6.32k | UINT64_C(2147483648), // ADDXrr |
47 | 6.32k | UINT64_C(2147491840), // ADDri |
48 | 6.32k | UINT64_C(2147483648), // ADDrr |
49 | 6.32k | UINT64_C(0), |
50 | 6.32k | UINT64_C(0), |
51 | 6.32k | UINT64_C(2175795968), // ALIGNADDR |
52 | 6.32k | UINT64_C(2175796032), // ALIGNADDRL |
53 | 6.32k | UINT64_C(2156404736), // ANDCCri |
54 | 6.32k | UINT64_C(2156396544), // ANDCCrr |
55 | 6.32k | UINT64_C(2158501888), // ANDNCCri |
56 | 6.32k | UINT64_C(2158493696), // ANDNCCrr |
57 | 6.32k | UINT64_C(2150113280), // ANDNri |
58 | 6.32k | UINT64_C(2150105088), // ANDNrr |
59 | 6.32k | UINT64_C(2150105088), // ANDXNrr |
60 | 6.32k | UINT64_C(2148016128), // ANDXri |
61 | 6.32k | UINT64_C(2148007936), // ANDXrr |
62 | 6.32k | UINT64_C(2148016128), // ANDri |
63 | 6.32k | UINT64_C(2148007936), // ANDrr |
64 | 6.32k | UINT64_C(2175795776), // ARRAY16 |
65 | 6.32k | UINT64_C(2175795840), // ARRAY32 |
66 | 6.32k | UINT64_C(2175795712), // ARRAY8 |
67 | 6.32k | UINT64_C(0), |
68 | 6.32k | UINT64_C(0), |
69 | 6.32k | UINT64_C(0), |
70 | 6.32k | UINT64_C(0), |
71 | 6.32k | UINT64_C(0), |
72 | 6.32k | UINT64_C(0), |
73 | 6.32k | UINT64_C(0), |
74 | 6.32k | UINT64_C(0), |
75 | 6.32k | UINT64_C(0), |
76 | 6.32k | UINT64_C(0), |
77 | 6.32k | UINT64_C(0), |
78 | 6.32k | UINT64_C(0), |
79 | 6.32k | UINT64_C(0), |
80 | 6.32k | UINT64_C(0), |
81 | 6.32k | UINT64_C(0), |
82 | 6.32k | UINT64_C(0), |
83 | 6.32k | UINT64_C(0), |
84 | 6.32k | UINT64_C(0), |
85 | 6.32k | UINT64_C(0), |
86 | 6.32k | UINT64_C(0), |
87 | 6.32k | UINT64_C(0), |
88 | 6.32k | UINT64_C(276824064), // BA |
89 | 6.32k | UINT64_C(8388608), // BCOND |
90 | 6.32k | UINT64_C(545259520), // BCONDA |
91 | 6.32k | UINT64_C(2176851968), // BINDri |
92 | 6.32k | UINT64_C(2176843776), // BINDrr |
93 | 6.32k | UINT64_C(2175796000), // BMASK |
94 | 6.32k | UINT64_C(21495808), // BPFCC |
95 | 6.32k | UINT64_C(558366720), // BPFCCA |
96 | 6.32k | UINT64_C(557842432), // BPFCCANT |
97 | 6.32k | UINT64_C(20971520), // BPFCCNT |
98 | 6.32k | UINT64_C(784334848), // BPGEZapn |
99 | 6.32k | UINT64_C(784859136), // BPGEZapt |
100 | 6.32k | UINT64_C(247463936), // BPGEZnapn |
101 | 6.32k | UINT64_C(247988224), // BPGEZnapt |
102 | 6.32k | UINT64_C(750780416), // BPGZapn |
103 | 6.32k | UINT64_C(751304704), // BPGZapt |
104 | 6.32k | UINT64_C(213909504), // BPGZnapn |
105 | 6.32k | UINT64_C(214433792), // BPGZnapt |
106 | 6.32k | UINT64_C(4718592), // BPICC |
107 | 6.32k | UINT64_C(541589504), // BPICCA |
108 | 6.32k | UINT64_C(541065216), // BPICCANT |
109 | 6.32k | UINT64_C(4194304), // BPICCNT |
110 | 6.32k | UINT64_C(616562688), // BPLEZapn |
111 | 6.32k | UINT64_C(617086976), // BPLEZapt |
112 | 6.32k | UINT64_C(79691776), // BPLEZnapn |
113 | 6.32k | UINT64_C(80216064), // BPLEZnapt |
114 | 6.32k | UINT64_C(650117120), // BPLZapn |
115 | 6.32k | UINT64_C(650641408), // BPLZapt |
116 | 6.32k | UINT64_C(113246208), // BPLZnapn |
117 | 6.32k | UINT64_C(113770496), // BPLZnapt |
118 | 6.32k | UINT64_C(717225984), // BPNZapn |
119 | 6.32k | UINT64_C(717750272), // BPNZapt |
120 | 6.32k | UINT64_C(180355072), // BPNZnapn |
121 | 6.32k | UINT64_C(180879360), // BPNZnapt |
122 | 6.32k | UINT64_C(6815744), // BPXCC |
123 | 6.32k | UINT64_C(543686656), // BPXCCA |
124 | 6.32k | UINT64_C(543162368), // BPXCCANT |
125 | 6.32k | UINT64_C(6291456), // BPXCCNT |
126 | 6.32k | UINT64_C(583008256), // BPZapn |
127 | 6.32k | UINT64_C(583532544), // BPZapt |
128 | 6.32k | UINT64_C(46137344), // BPZnapn |
129 | 6.32k | UINT64_C(46661632), // BPZnapt |
130 | 6.32k | UINT64_C(2175796096), // BSHUFFLE |
131 | 6.32k | UINT64_C(1073741824), // CALL |
132 | 6.32k | UINT64_C(2680168448), // CALLri |
133 | 6.32k | UINT64_C(2680160256), // CALLrr |
134 | 6.32k | UINT64_C(3253735424), // CASXrr |
135 | 6.32k | UINT64_C(3252686848), // CASrr |
136 | 6.32k | UINT64_C(2175796128), // CMASK16 |
137 | 6.32k | UINT64_C(2175796192), // CMASK32 |
138 | 6.32k | UINT64_C(2175796064), // CMASK8 |
139 | 6.32k | UINT64_C(2157977600), // CMPri |
140 | 6.32k | UINT64_C(2157969408), // CMPrr |
141 | 6.32k | UINT64_C(2175795328), // EDGE16 |
142 | 6.32k | UINT64_C(2175795392), // EDGE16L |
143 | 6.32k | UINT64_C(2175795424), // EDGE16LN |
144 | 6.32k | UINT64_C(2175795360), // EDGE16N |
145 | 6.32k | UINT64_C(2175795456), // EDGE32 |
146 | 6.32k | UINT64_C(2175795520), // EDGE32L |
147 | 6.32k | UINT64_C(2175795552), // EDGE32LN |
148 | 6.32k | UINT64_C(2175795488), // EDGE32N |
149 | 6.32k | UINT64_C(2175795200), // EDGE8 |
150 | 6.32k | UINT64_C(2175795264), // EDGE8L |
151 | 6.32k | UINT64_C(2175795296), // EDGE8LN |
152 | 6.32k | UINT64_C(2175795232), // EDGE8N |
153 | 6.32k | UINT64_C(2174746944), // FABSD |
154 | 6.32k | UINT64_C(2174746976), // FABSQ |
155 | 6.32k | UINT64_C(2174746912), // FABSS |
156 | 6.32k | UINT64_C(2174748736), // FADDD |
157 | 6.32k | UINT64_C(2174748768), // FADDQ |
158 | 6.32k | UINT64_C(2174748704), // FADDS |
159 | 6.32k | UINT64_C(2175797504), // FALIGNADATA |
160 | 6.32k | UINT64_C(2175798784), // FAND |
161 | 6.32k | UINT64_C(2175798528), // FANDNOT1 |
162 | 6.32k | UINT64_C(2175798560), // FANDNOT1S |
163 | 6.32k | UINT64_C(2175798400), // FANDNOT2 |
164 | 6.32k | UINT64_C(2175798432), // FANDNOT2S |
165 | 6.32k | UINT64_C(2175798816), // FANDS |
166 | 6.32k | UINT64_C(25165824), // FBCOND |
167 | 6.32k | UINT64_C(562036736), // FBCONDA |
168 | 6.32k | UINT64_C(2175797376), // FCHKSM16 |
169 | 6.32k | UINT64_C(2175273536), // FCMPD |
170 | 6.32k | UINT64_C(2175796544), // FCMPEQ16 |
171 | 6.32k | UINT64_C(2175796672), // FCMPEQ32 |
172 | 6.32k | UINT64_C(2175796480), // FCMPGT16 |
173 | 6.32k | UINT64_C(2175796608), // FCMPGT32 |
174 | 6.32k | UINT64_C(2175796224), // FCMPLE16 |
175 | 6.32k | UINT64_C(2175796352), // FCMPLE32 |
176 | 6.32k | UINT64_C(2175796288), // FCMPNE16 |
177 | 6.32k | UINT64_C(2175796416), // FCMPNE32 |
178 | 6.32k | UINT64_C(2175273568), // FCMPQ |
179 | 6.32k | UINT64_C(2175273504), // FCMPS |
180 | 6.32k | UINT64_C(2174749120), // FDIVD |
181 | 6.32k | UINT64_C(2174749152), // FDIVQ |
182 | 6.32k | UINT64_C(2174749088), // FDIVS |
183 | 6.32k | UINT64_C(2174750144), // FDMULQ |
184 | 6.32k | UINT64_C(2174753344), // FDTOI |
185 | 6.32k | UINT64_C(2174753216), // FDTOQ |
186 | 6.32k | UINT64_C(2174752960), // FDTOS |
187 | 6.32k | UINT64_C(2174750784), // FDTOX |
188 | 6.32k | UINT64_C(2175797664), // FEXPAND |
189 | 6.32k | UINT64_C(2174749760), // FHADDD |
190 | 6.32k | UINT64_C(2174749728), // FHADDS |
191 | 6.32k | UINT64_C(2174749888), // FHSUBD |
192 | 6.32k | UINT64_C(2174749856), // FHSUBS |
193 | 6.32k | UINT64_C(2174753024), // FITOD |
194 | 6.32k | UINT64_C(2174753152), // FITOQ |
195 | 6.32k | UINT64_C(2174752896), // FITOS |
196 | 6.32k | UINT64_C(2175806016), // FLCMPD |
197 | 6.32k | UINT64_C(2175805984), // FLCMPS |
198 | 6.32k | UINT64_C(2178416640), // FLUSH |
199 | 6.32k | UINT64_C(2170028032), // FLUSHW |
200 | 6.32k | UINT64_C(2178424832), // FLUSHri |
201 | 6.32k | UINT64_C(2178416640), // FLUSHrr |
202 | 6.32k | UINT64_C(2175797248), // FMEAN16 |
203 | 6.32k | UINT64_C(2174746688), // FMOVD |
204 | 6.32k | UINT64_C(2175270976), // FMOVD_FCC |
205 | 6.32k | UINT64_C(2175279168), // FMOVD_ICC |
206 | 6.32k | UINT64_C(2175283264), // FMOVD_XCC |
207 | 6.32k | UINT64_C(2174746720), // FMOVQ |
208 | 6.32k | UINT64_C(2175271008), // FMOVQ_FCC |
209 | 6.32k | UINT64_C(2175279200), // FMOVQ_ICC |
210 | 6.32k | UINT64_C(2175283296), // FMOVQ_XCC |
211 | 6.32k | UINT64_C(2175278272), // FMOVRGEZD |
212 | 6.32k | UINT64_C(2175278304), // FMOVRGEZQ |
213 | 6.32k | UINT64_C(2175278240), // FMOVRGEZS |
214 | 6.32k | UINT64_C(2175277248), // FMOVRGZD |
215 | 6.32k | UINT64_C(2175277280), // FMOVRGZQ |
216 | 6.32k | UINT64_C(2175277216), // FMOVRGZS |
217 | 6.32k | UINT64_C(2175273152), // FMOVRLEZD |
218 | 6.32k | UINT64_C(2175273184), // FMOVRLEZQ |
219 | 6.32k | UINT64_C(2175273120), // FMOVRLEZS |
220 | 6.32k | UINT64_C(2175274176), // FMOVRLZD |
221 | 6.32k | UINT64_C(2175274208), // FMOVRLZQ |
222 | 6.32k | UINT64_C(2175274144), // FMOVRLZS |
223 | 6.32k | UINT64_C(2175276224), // FMOVRNZD |
224 | 6.32k | UINT64_C(2175276256), // FMOVRNZQ |
225 | 6.32k | UINT64_C(2175276192), // FMOVRNZS |
226 | 6.32k | UINT64_C(2175272128), // FMOVRZD |
227 | 6.32k | UINT64_C(2175272160), // FMOVRZQ |
228 | 6.32k | UINT64_C(2175272096), // FMOVRZS |
229 | 6.32k | UINT64_C(2174746656), // FMOVS |
230 | 6.32k | UINT64_C(2175270944), // FMOVS_FCC |
231 | 6.32k | UINT64_C(2175279136), // FMOVS_ICC |
232 | 6.32k | UINT64_C(2175283232), // FMOVS_XCC |
233 | 6.32k | UINT64_C(2175796928), // FMUL8SUX16 |
234 | 6.32k | UINT64_C(2175796960), // FMUL8ULX16 |
235 | 6.32k | UINT64_C(2175796768), // FMUL8X16 |
236 | 6.32k | UINT64_C(2175796896), // FMUL8X16AL |
237 | 6.32k | UINT64_C(2175796832), // FMUL8X16AU |
238 | 6.32k | UINT64_C(2174748992), // FMULD |
239 | 6.32k | UINT64_C(2175796992), // FMULD8SUX16 |
240 | 6.32k | UINT64_C(2175797024), // FMULD8ULX16 |
241 | 6.32k | UINT64_C(2174749024), // FMULQ |
242 | 6.32k | UINT64_C(2174748960), // FMULS |
243 | 6.32k | UINT64_C(2174749248), // FNADDD |
244 | 6.32k | UINT64_C(2174749216), // FNADDS |
245 | 6.32k | UINT64_C(2175798720), // FNAND |
246 | 6.32k | UINT64_C(2175798752), // FNANDS |
247 | 6.32k | UINT64_C(2174746816), // FNEGD |
248 | 6.32k | UINT64_C(2174746848), // FNEGQ |
249 | 6.32k | UINT64_C(2174746784), // FNEGS |
250 | 6.32k | UINT64_C(2174750272), // FNHADDD |
251 | 6.32k | UINT64_C(2174750240), // FNHADDS |
252 | 6.32k | UINT64_C(2174749504), // FNMULD |
253 | 6.32k | UINT64_C(2174749472), // FNMULS |
254 | 6.32k | UINT64_C(2175798336), // FNOR |
255 | 6.32k | UINT64_C(2175798368), // FNORS |
256 | 6.32k | UINT64_C(2175798592), // FNOT1 |
257 | 6.32k | UINT64_C(2175798624), // FNOT1S |
258 | 6.32k | UINT64_C(2175798464), // FNOT2 |
259 | 6.32k | UINT64_C(2175798496), // FNOT2S |
260 | 6.32k | UINT64_C(2174750496), // FNSMULD |
261 | 6.32k | UINT64_C(2175799232), // FONE |
262 | 6.32k | UINT64_C(2175799264), // FONES |
263 | 6.32k | UINT64_C(2175799168), // FOR |
264 | 6.32k | UINT64_C(2175799104), // FORNOT1 |
265 | 6.32k | UINT64_C(2175799136), // FORNOT1S |
266 | 6.32k | UINT64_C(2175798976), // FORNOT2 |
267 | 6.32k | UINT64_C(2175799008), // FORNOT2S |
268 | 6.32k | UINT64_C(2175799200), // FORS |
269 | 6.32k | UINT64_C(2175797088), // FPACK16 |
270 | 6.32k | UINT64_C(2175797056), // FPACK32 |
271 | 6.32k | UINT64_C(2175797152), // FPACKFIX |
272 | 6.32k | UINT64_C(2175797760), // FPADD16 |
273 | 6.32k | UINT64_C(2175797792), // FPADD16S |
274 | 6.32k | UINT64_C(2175797824), // FPADD32 |
275 | 6.32k | UINT64_C(2175797856), // FPADD32S |
276 | 6.32k | UINT64_C(2175797312), // FPADD64 |
277 | 6.32k | UINT64_C(2175797600), // FPMERGE |
278 | 6.32k | UINT64_C(2175797888), // FPSUB16 |
279 | 6.32k | UINT64_C(2175797920), // FPSUB16S |
280 | 6.32k | UINT64_C(2175797952), // FPSUB32 |
281 | 6.32k | UINT64_C(2175797984), // FPSUB32S |
282 | 6.32k | UINT64_C(2174753120), // FQTOD |
283 | 6.32k | UINT64_C(2174753376), // FQTOI |
284 | 6.32k | UINT64_C(2174752992), // FQTOS |
285 | 6.32k | UINT64_C(2174750816), // FQTOX |
286 | 6.32k | UINT64_C(2175796512), // FSLAS16 |
287 | 6.32k | UINT64_C(2175796640), // FSLAS32 |
288 | 6.32k | UINT64_C(2175796256), // FSLL16 |
289 | 6.32k | UINT64_C(2175796384), // FSLL32 |
290 | 6.32k | UINT64_C(2174749984), // FSMULD |
291 | 6.32k | UINT64_C(2174747968), // FSQRTD |
292 | 6.32k | UINT64_C(2174748000), // FSQRTQ |
293 | 6.32k | UINT64_C(2174747936), // FSQRTS |
294 | 6.32k | UINT64_C(2175796576), // FSRA16 |
295 | 6.32k | UINT64_C(2175796704), // FSRA32 |
296 | 6.32k | UINT64_C(2175798912), // FSRC1 |
297 | 6.32k | UINT64_C(2175798944), // FSRC1S |
298 | 6.32k | UINT64_C(2175799040), // FSRC2 |
299 | 6.32k | UINT64_C(2175799072), // FSRC2S |
300 | 6.32k | UINT64_C(2175796320), // FSRL16 |
301 | 6.32k | UINT64_C(2175796448), // FSRL32 |
302 | 6.32k | UINT64_C(2174753056), // FSTOD |
303 | 6.32k | UINT64_C(2174753312), // FSTOI |
304 | 6.32k | UINT64_C(2174753184), // FSTOQ |
305 | 6.32k | UINT64_C(2174750752), // FSTOX |
306 | 6.32k | UINT64_C(2174748864), // FSUBD |
307 | 6.32k | UINT64_C(2174748896), // FSUBQ |
308 | 6.32k | UINT64_C(2174748832), // FSUBS |
309 | 6.32k | UINT64_C(2175798848), // FXNOR |
310 | 6.32k | UINT64_C(2175798880), // FXNORS |
311 | 6.32k | UINT64_C(2175798656), // FXOR |
312 | 6.32k | UINT64_C(2175798688), // FXORS |
313 | 6.32k | UINT64_C(2174750976), // FXTOD |
314 | 6.32k | UINT64_C(2174751104), // FXTOQ |
315 | 6.32k | UINT64_C(2174750848), // FXTOS |
316 | 6.32k | UINT64_C(2175798272), // FZERO |
317 | 6.32k | UINT64_C(2175798304), // FZEROS |
318 | 6.32k | UINT64_C(0), |
319 | 6.32k | UINT64_C(2176851968), // JMPLri |
320 | 6.32k | UINT64_C(2176843776), // JMPLrr |
321 | 6.32k | UINT64_C(3229614080), // LDArr |
322 | 6.32k | UINT64_C(3231186944), // LDDArr |
323 | 6.32k | UINT64_C(3247964160), // LDDFArr |
324 | 6.32k | UINT64_C(3239583744), // LDDFri |
325 | 6.32k | UINT64_C(3239575552), // LDDFrr |
326 | 6.32k | UINT64_C(3222806528), // LDDri |
327 | 6.32k | UINT64_C(3222798336), // LDDrr |
328 | 6.32k | UINT64_C(3246391296), // LDFArr |
329 | 6.32k | UINT64_C(3238535168), // LDFSRri |
330 | 6.32k | UINT64_C(3238526976), // LDFSRrr |
331 | 6.32k | UINT64_C(3238010880), // LDFri |
332 | 6.32k | UINT64_C(3238002688), // LDFrr |
333 | 6.32k | UINT64_C(3247439872), // LDQFArr |
334 | 6.32k | UINT64_C(3239059456), // LDQFri |
335 | 6.32k | UINT64_C(3239051264), // LDQFrr |
336 | 6.32k | UINT64_C(3234332672), // LDSBArr |
337 | 6.32k | UINT64_C(3225952256), // LDSBri |
338 | 6.32k | UINT64_C(3225944064), // LDSBrr |
339 | 6.32k | UINT64_C(3234856960), // LDSHArr |
340 | 6.32k | UINT64_C(3226476544), // LDSHri |
341 | 6.32k | UINT64_C(3226468352), // LDSHrr |
342 | 6.32k | UINT64_C(3236429824), // LDSTUBArr |
343 | 6.32k | UINT64_C(3228049408), // LDSTUBri |
344 | 6.32k | UINT64_C(3228041216), // LDSTUBrr |
345 | 6.32k | UINT64_C(3225427968), // LDSWri |
346 | 6.32k | UINT64_C(3225419776), // LDSWrr |
347 | 6.32k | UINT64_C(3230138368), // LDUBArr |
348 | 6.32k | UINT64_C(3221757952), // LDUBri |
349 | 6.32k | UINT64_C(3221749760), // LDUBrr |
350 | 6.32k | UINT64_C(3230662656), // LDUHArr |
351 | 6.32k | UINT64_C(3222282240), // LDUHri |
352 | 6.32k | UINT64_C(3222274048), // LDUHrr |
353 | 6.32k | UINT64_C(3272089600), // LDXFSRri |
354 | 6.32k | UINT64_C(3272081408), // LDXFSRrr |
355 | 6.32k | UINT64_C(3227000832), // LDXri |
356 | 6.32k | UINT64_C(3226992640), // LDXrr |
357 | 6.32k | UINT64_C(3221233664), // LDri |
358 | 6.32k | UINT64_C(3221225472), // LDrr |
359 | 6.32k | UINT64_C(2147491840), // LEAX_ADDri |
360 | 6.32k | UINT64_C(2147491840), // LEA_ADDri |
361 | 6.32k | UINT64_C(2175795936), // LZCNT |
362 | 6.32k | UINT64_C(2168709120), // MEMBARi |
363 | 6.32k | UINT64_C(2175803904), // MOVDTOX |
364 | 6.32k | UINT64_C(2170560512), // MOVFCCri |
365 | 6.32k | UINT64_C(2170552320), // MOVFCCrr |
366 | 6.32k | UINT64_C(2170822656), // MOVICCri |
367 | 6.32k | UINT64_C(2170814464), // MOVICCrr |
368 | 6.32k | UINT64_C(2172140544), // MOVRGEZri |
369 | 6.32k | UINT64_C(2172132352), // MOVRGEZrr |
370 | 6.32k | UINT64_C(2172139520), // MOVRGZri |
371 | 6.32k | UINT64_C(2172131328), // MOVRGZrr |
372 | 6.32k | UINT64_C(2172135424), // MOVRLEZri |
373 | 6.32k | UINT64_C(2172127232), // MOVRLEZrr |
374 | 6.32k | UINT64_C(2172136448), // MOVRLZri |
375 | 6.32k | UINT64_C(2172128256), // MOVRLZrr |
376 | 6.32k | UINT64_C(2172138496), // MOVRNZri |
377 | 6.32k | UINT64_C(2172130304), // MOVRNZrr |
378 | 6.32k | UINT64_C(2172134400), // MOVRRZri |
379 | 6.32k | UINT64_C(2172126208), // MOVRRZrr |
380 | 6.32k | UINT64_C(2175804000), // MOVSTOSW |
381 | 6.32k | UINT64_C(2175803936), // MOVSTOUW |
382 | 6.32k | UINT64_C(2175804192), // MOVWTOS |
383 | 6.32k | UINT64_C(2170826752), // MOVXCCri |
384 | 6.32k | UINT64_C(2170818560), // MOVXCCrr |
385 | 6.32k | UINT64_C(2175804160), // MOVXTOD |
386 | 6.32k | UINT64_C(2166366208), // MULSCCri |
387 | 6.32k | UINT64_C(2166358016), // MULSCCrr |
388 | 6.32k | UINT64_C(2152210432), // MULXri |
389 | 6.32k | UINT64_C(2152202240), // MULXrr |
390 | 6.32k | UINT64_C(16777216), // NOP |
391 | 6.32k | UINT64_C(2156929024), // ORCCri |
392 | 6.32k | UINT64_C(2156920832), // ORCCrr |
393 | 6.32k | UINT64_C(2159026176), // ORNCCri |
394 | 6.32k | UINT64_C(2159017984), // ORNCCrr |
395 | 6.32k | UINT64_C(2150637568), // ORNri |
396 | 6.32k | UINT64_C(2150629376), // ORNrr |
397 | 6.32k | UINT64_C(2150629376), // ORXNrr |
398 | 6.32k | UINT64_C(2148540416), // ORXri |
399 | 6.32k | UINT64_C(2148532224), // ORXrr |
400 | 6.32k | UINT64_C(2148540416), // ORri |
401 | 6.32k | UINT64_C(2148532224), // ORrr |
402 | 6.32k | UINT64_C(2175797184), // PDIST |
403 | 6.32k | UINT64_C(2175797216), // PDISTN |
404 | 6.32k | UINT64_C(2171600896), // POPCrr |
405 | 6.32k | UINT64_C(2168455168), // RDASR |
406 | 6.32k | UINT64_C(2169503744), // RDPR |
407 | 6.32k | UINT64_C(2168979456), // RDPSR |
408 | 6.32k | UINT64_C(2170028032), // RDTBR |
409 | 6.32k | UINT64_C(2169503744), // RDWIM |
410 | 6.32k | UINT64_C(2179473408), // RESTOREri |
411 | 6.32k | UINT64_C(2179465216), // RESTORErr |
412 | 6.32k | UINT64_C(2177359872), // RET |
413 | 6.32k | UINT64_C(2177097728), // RETL |
414 | 6.32k | UINT64_C(2177376256), // RETTri |
415 | 6.32k | UINT64_C(2177368064), // RETTrr |
416 | 6.32k | UINT64_C(2178949120), // SAVEri |
417 | 6.32k | UINT64_C(2178940928), // SAVErr |
418 | 6.32k | UINT64_C(2163744768), // SDIVCCri |
419 | 6.32k | UINT64_C(2163736576), // SDIVCCrr |
420 | 6.32k | UINT64_C(2171084800), // SDIVXri |
421 | 6.32k | UINT64_C(2171076608), // SDIVXrr |
422 | 6.32k | UINT64_C(2155356160), // SDIVri |
423 | 6.32k | UINT64_C(2155347968), // SDIVrr |
424 | 6.32k | UINT64_C(0), |
425 | 6.32k | UINT64_C(0), |
426 | 6.32k | UINT64_C(0), |
427 | 6.32k | UINT64_C(0), |
428 | 6.32k | UINT64_C(0), |
429 | 6.32k | UINT64_C(0), |
430 | 6.32k | UINT64_C(0), |
431 | 6.32k | UINT64_C(0), |
432 | 6.32k | UINT64_C(0), |
433 | 6.32k | UINT64_C(16777216), // SETHIXi |
434 | 6.32k | UINT64_C(16777216), // SETHIi |
435 | 6.32k | UINT64_C(2175799296), // SHUTDOWN |
436 | 6.32k | UINT64_C(2175799328), // SIAM |
437 | 6.32k | UINT64_C(2166894592), // SLLXri |
438 | 6.32k | UINT64_C(2166886400), // SLLXrr |
439 | 6.32k | UINT64_C(2166890496), // SLLri |
440 | 6.32k | UINT64_C(2166882304), // SLLrr |
441 | 6.32k | UINT64_C(2161647616), // SMULCCri |
442 | 6.32k | UINT64_C(2161639424), // SMULCCrr |
443 | 6.32k | UINT64_C(2153259008), // SMULri |
444 | 6.32k | UINT64_C(2153250816), // SMULrr |
445 | 6.32k | UINT64_C(2167943168), // SRAXri |
446 | 6.32k | UINT64_C(2167934976), // SRAXrr |
447 | 6.32k | UINT64_C(2167939072), // SRAri |
448 | 6.32k | UINT64_C(2167930880), // SRArr |
449 | 6.32k | UINT64_C(2167418880), // SRLXri |
450 | 6.32k | UINT64_C(2167410688), // SRLXrr |
451 | 6.32k | UINT64_C(2167414784), // SRLri |
452 | 6.32k | UINT64_C(2167406592), // SRLrr |
453 | 6.32k | UINT64_C(3231711232), // STArr |
454 | 6.32k | UINT64_C(2168700928), // STBAR |
455 | 6.32k | UINT64_C(3232235520), // STBArr |
456 | 6.32k | UINT64_C(3223855104), // STBri |
457 | 6.32k | UINT64_C(3223846912), // STBrr |
458 | 6.32k | UINT64_C(3233284096), // STDArr |
459 | 6.32k | UINT64_C(3250061312), // STDFArr |
460 | 6.32k | UINT64_C(3241680896), // STDFri |
461 | 6.32k | UINT64_C(3241672704), // STDFrr |
462 | 6.32k | UINT64_C(3224903680), // STDri |
463 | 6.32k | UINT64_C(3224895488), // STDrr |
464 | 6.32k | UINT64_C(3248488448), // STFArr |
465 | 6.32k | UINT64_C(3240632320), // STFSRri |
466 | 6.32k | UINT64_C(3240624128), // STFSRrr |
467 | 6.32k | UINT64_C(3240108032), // STFri |
468 | 6.32k | UINT64_C(3240099840), // STFrr |
469 | 6.32k | UINT64_C(3232759808), // STHArr |
470 | 6.32k | UINT64_C(3224379392), // STHri |
471 | 6.32k | UINT64_C(3224371200), // STHrr |
472 | 6.32k | UINT64_C(3249537024), // STQFArr |
473 | 6.32k | UINT64_C(3241156608), // STQFri |
474 | 6.32k | UINT64_C(3241148416), // STQFrr |
475 | 6.32k | UINT64_C(3274186752), // STXFSRri |
476 | 6.32k | UINT64_C(3274178560), // STXFSRrr |
477 | 6.32k | UINT64_C(3228573696), // STXri |
478 | 6.32k | UINT64_C(3228565504), // STXrr |
479 | 6.32k | UINT64_C(3223330816), // STri |
480 | 6.32k | UINT64_C(3223322624), // STrr |
481 | 6.32k | UINT64_C(2157977600), // SUBCCri |
482 | 6.32k | UINT64_C(2157969408), // SUBCCrr |
483 | 6.32k | UINT64_C(2153783296), // SUBCri |
484 | 6.32k | UINT64_C(2153775104), // SUBCrr |
485 | 6.32k | UINT64_C(2162171904), // SUBEri |
486 | 6.32k | UINT64_C(2162163712), // SUBErr |
487 | 6.32k | UINT64_C(2149588992), // SUBXri |
488 | 6.32k | UINT64_C(2149580800), // SUBXrr |
489 | 6.32k | UINT64_C(2149588992), // SUBri |
490 | 6.32k | UINT64_C(2149580800), // SUBrr |
491 | 6.32k | UINT64_C(3237478400), // SWAPArr |
492 | 6.32k | UINT64_C(3229097984), // SWAPri |
493 | 6.32k | UINT64_C(3229089792), // SWAPrr |
494 | 6.32k | UINT64_C(2177916931), // TA3 |
495 | 6.32k | UINT64_C(2446336005), // TA5 |
496 | 6.32k | UINT64_C(2165317632), // TADDCCTVri |
497 | 6.32k | UINT64_C(2165309440), // TADDCCTVrr |
498 | 6.32k | UINT64_C(2164269056), // TADDCCri |
499 | 6.32k | UINT64_C(2164260864), // TADDCCrr |
500 | 6.32k | UINT64_C(2177900544), // TICCri |
501 | 6.32k | UINT64_C(2177892352), // TICCrr |
502 | 6.32k | UINT64_C(2147483648), // TLS_ADDXrr |
503 | 6.32k | UINT64_C(2147483648), // TLS_ADDrr |
504 | 6.32k | UINT64_C(1073741824), // TLS_CALL |
505 | 6.32k | UINT64_C(3226992640), // TLS_LDXrr |
506 | 6.32k | UINT64_C(3221225472), // TLS_LDrr |
507 | 6.32k | UINT64_C(2165841920), // TSUBCCTVri |
508 | 6.32k | UINT64_C(2165833728), // TSUBCCTVrr |
509 | 6.32k | UINT64_C(2164793344), // TSUBCCri |
510 | 6.32k | UINT64_C(2164785152), // TSUBCCrr |
511 | 6.32k | UINT64_C(2177904640), // TXCCri |
512 | 6.32k | UINT64_C(2177896448), // TXCCrr |
513 | 6.32k | UINT64_C(2163220480), // UDIVCCri |
514 | 6.32k | UINT64_C(2163212288), // UDIVCCrr |
515 | 6.32k | UINT64_C(2154307584), // UDIVXri |
516 | 6.32k | UINT64_C(2154299392), // UDIVXrr |
517 | 6.32k | UINT64_C(2154831872), // UDIVri |
518 | 6.32k | UINT64_C(2154823680), // UDIVrr |
519 | 6.32k | UINT64_C(2161123328), // UMULCCri |
520 | 6.32k | UINT64_C(2161115136), // UMULCCrr |
521 | 6.32k | UINT64_C(2175795904), // UMULXHI |
522 | 6.32k | UINT64_C(2152734720), // UMULri |
523 | 6.32k | UINT64_C(2152726528), // UMULrr |
524 | 6.32k | UINT64_C(0), // UNIMP |
525 | 6.32k | UINT64_C(2175273536), // V9FCMPD |
526 | 6.32k | UINT64_C(2175273664), // V9FCMPED |
527 | 6.32k | UINT64_C(2175273696), // V9FCMPEQ |
528 | 6.32k | UINT64_C(2175273632), // V9FCMPES |
529 | 6.32k | UINT64_C(2175273568), // V9FCMPQ |
530 | 6.32k | UINT64_C(2175273504), // V9FCMPS |
531 | 6.32k | UINT64_C(2175270976), // V9FMOVD_FCC |
532 | 6.32k | UINT64_C(2175271008), // V9FMOVQ_FCC |
533 | 6.32k | UINT64_C(2175270944), // V9FMOVS_FCC |
534 | 6.32k | UINT64_C(2170560512), // V9MOVFCCri |
535 | 6.32k | UINT64_C(2170552320), // V9MOVFCCrr |
536 | 6.32k | UINT64_C(2172657664), // WRASRri |
537 | 6.32k | UINT64_C(2172649472), // WRASRrr |
538 | 6.32k | UINT64_C(2173706240), // WRPRri |
539 | 6.32k | UINT64_C(2173698048), // WRPRrr |
540 | 6.32k | UINT64_C(2173181952), // WRPSRri |
541 | 6.32k | UINT64_C(2173173760), // WRPSRrr |
542 | 6.32k | UINT64_C(2174230528), // WRTBRri |
543 | 6.32k | UINT64_C(2174222336), // WRTBRrr |
544 | 6.32k | UINT64_C(2173706240), // WRWIMri |
545 | 6.32k | UINT64_C(2173698048), // WRWIMrr |
546 | 6.32k | UINT64_C(2175804064), // XMULX |
547 | 6.32k | UINT64_C(2175804128), // XMULXHI |
548 | 6.32k | UINT64_C(2159550464), // XNORCCri |
549 | 6.32k | UINT64_C(2159542272), // XNORCCrr |
550 | 6.32k | UINT64_C(2151153664), // XNORXrr |
551 | 6.32k | UINT64_C(2151161856), // XNORri |
552 | 6.32k | UINT64_C(2151153664), // XNORrr |
553 | 6.32k | UINT64_C(2157453312), // XORCCri |
554 | 6.32k | UINT64_C(2157445120), // XORCCrr |
555 | 6.32k | UINT64_C(2149064704), // XORXri |
556 | 6.32k | UINT64_C(2149056512), // XORXrr |
557 | 6.32k | UINT64_C(2149064704), // XORri |
558 | 6.32k | UINT64_C(2149056512), // XORrr |
559 | 6.32k | UINT64_C(0) |
560 | 6.32k | }; |
561 | 6.32k | const unsigned opcode = MI.getOpcode(); |
562 | 6.32k | uint64_t Value = InstBits[opcode]; |
563 | 6.32k | uint64_t op = 0; |
564 | 6.32k | (void)op; // suppress warning |
565 | 6.32k | switch (opcode) { |
566 | 10 | case SP::FLUSH: |
567 | 10 | case SP::FLUSHW: |
568 | 169 | case SP::NOP: |
569 | 169 | case SP::SHUTDOWN: |
570 | 169 | case SP::SIAM: |
571 | 169 | case SP::STBAR: |
572 | 169 | case SP::TA3: |
573 | 169 | case SP::TA5: { |
574 | 169 | break; |
575 | 169 | } |
576 | 0 | case SP::BPFCC: |
577 | 0 | case SP::BPFCCA: |
578 | 0 | case SP::BPFCCANT: |
579 | 0 | case SP::BPFCCNT: { |
580 | | // op: cc |
581 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
582 | 0 | Value |= (op & UINT64_C(3)) << 20; |
583 | | // op: cond |
584 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
585 | 0 | Value |= (op & UINT64_C(15)) << 25; |
586 | | // op: imm19 |
587 | 0 | op = getBranchPredTargetOpValue(MI, 0, Fixups, STI); |
588 | 0 | Value |= op & UINT64_C(524287); |
589 | 0 | break; |
590 | 0 | } |
591 | 0 | case SP::BPICC: |
592 | 0 | case SP::BPICCA: |
593 | 0 | case SP::BPICCANT: |
594 | 0 | case SP::BPICCNT: |
595 | 2 | case SP::BPXCC: |
596 | 2 | case SP::BPXCCA: |
597 | 2 | case SP::BPXCCANT: |
598 | 2 | case SP::BPXCCNT: { |
599 | | // op: cond |
600 | 2 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
601 | 2 | Value |= (op & UINT64_C(15)) << 25; |
602 | | // op: imm19 |
603 | 2 | op = getBranchPredTargetOpValue(MI, 0, Fixups, STI); |
604 | 2 | Value |= op & UINT64_C(524287); |
605 | 2 | break; |
606 | 2 | } |
607 | 39 | case SP::CALL: |
608 | 39 | case SP::TLS_CALL: { |
609 | | // op: disp |
610 | 39 | op = getCallTargetOpValue(MI, 0, Fixups, STI); |
611 | 39 | Value |= op & UINT64_C(1073741823); |
612 | 39 | break; |
613 | 39 | } |
614 | 0 | case SP::BPGEZapn: |
615 | 0 | case SP::BPGEZapt: |
616 | 0 | case SP::BPGEZnapn: |
617 | 0 | case SP::BPGEZnapt: |
618 | 0 | case SP::BPGZapn: |
619 | 0 | case SP::BPGZapt: |
620 | 0 | case SP::BPGZnapn: |
621 | 0 | case SP::BPGZnapt: |
622 | 0 | case SP::BPLEZapn: |
623 | 0 | case SP::BPLEZapt: |
624 | 0 | case SP::BPLEZnapn: |
625 | 0 | case SP::BPLEZnapt: |
626 | 0 | case SP::BPLZapn: |
627 | 0 | case SP::BPLZapt: |
628 | 0 | case SP::BPLZnapn: |
629 | 0 | case SP::BPLZnapt: |
630 | 0 | case SP::BPNZapn: |
631 | 0 | case SP::BPNZapt: |
632 | 0 | case SP::BPNZnapn: |
633 | 0 | case SP::BPNZnapt: |
634 | 0 | case SP::BPZapn: |
635 | 0 | case SP::BPZapt: |
636 | 0 | case SP::BPZnapn: |
637 | 0 | case SP::BPZnapt: { |
638 | | // op: imm16 |
639 | 0 | op = getBranchOnRegTargetOpValue(MI, 1, Fixups, STI); |
640 | 0 | Value |= (op & UINT64_C(49152)) << 6; |
641 | 0 | Value |= op & UINT64_C(16383); |
642 | | // op: rs1 |
643 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
644 | 0 | Value |= (op & UINT64_C(31)) << 14; |
645 | 0 | break; |
646 | 0 | } |
647 | 19 | case SP::BA: { |
648 | | // op: imm22 |
649 | 19 | op = getBranchTargetOpValue(MI, 0, Fixups, STI); |
650 | 19 | Value |= op & UINT64_C(4194303); |
651 | 19 | break; |
652 | 0 | } |
653 | 4.61k | case SP::BCOND: |
654 | 4.61k | case SP::BCONDA: |
655 | 4.68k | case SP::FBCOND: |
656 | 4.68k | case SP::FBCONDA: { |
657 | | // op: imm22 |
658 | 4.68k | op = getBranchTargetOpValue(MI, 0, Fixups, STI); |
659 | 4.68k | Value |= op & UINT64_C(4194303); |
660 | | // op: cond |
661 | 4.68k | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
662 | 4.68k | Value |= (op & UINT64_C(15)) << 25; |
663 | 4.68k | break; |
664 | 4.68k | } |
665 | 0 | case SP::UNIMP: { |
666 | | // op: imm22 |
667 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
668 | 0 | Value |= op & UINT64_C(4194303); |
669 | 0 | break; |
670 | 4.68k | } |
671 | 0 | case SP::SETHIXi: |
672 | 0 | case SP::SETHIi: { |
673 | | // op: imm22 |
674 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
675 | 0 | Value |= op & UINT64_C(4194303); |
676 | | // op: rd |
677 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
678 | 0 | Value |= (op & UINT64_C(31)) << 25; |
679 | 0 | break; |
680 | 0 | } |
681 | 0 | case SP::FONE: |
682 | 0 | case SP::FONES: |
683 | 0 | case SP::FZERO: |
684 | 0 | case SP::FZEROS: |
685 | 0 | case SP::RDPSR: |
686 | 0 | case SP::RDTBR: |
687 | 0 | case SP::RDWIM: { |
688 | | // op: rd |
689 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
690 | 0 | Value |= (op & UINT64_C(31)) << 25; |
691 | 0 | break; |
692 | 0 | } |
693 | 0 | case SP::V9MOVFCCrr: { |
694 | | // op: rd |
695 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
696 | 0 | Value |= (op & UINT64_C(31)) << 25; |
697 | | // op: cc |
698 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
699 | 0 | Value |= (op & UINT64_C(3)) << 11; |
700 | | // op: cond |
701 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
702 | 0 | Value |= (op & UINT64_C(15)) << 14; |
703 | | // op: rs2 |
704 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
705 | 0 | Value |= op & UINT64_C(31); |
706 | 0 | break; |
707 | 0 | } |
708 | 0 | case SP::V9MOVFCCri: { |
709 | | // op: rd |
710 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
711 | 0 | Value |= (op & UINT64_C(31)) << 25; |
712 | | // op: cc |
713 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
714 | 0 | Value |= (op & UINT64_C(3)) << 11; |
715 | | // op: cond |
716 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
717 | 0 | Value |= (op & UINT64_C(15)) << 14; |
718 | | // op: simm11 |
719 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
720 | 0 | Value |= op & UINT64_C(2047); |
721 | 0 | break; |
722 | 0 | } |
723 | 0 | case SP::FMOVD_FCC: |
724 | 0 | case SP::FMOVD_ICC: |
725 | 0 | case SP::FMOVD_XCC: |
726 | 0 | case SP::FMOVQ_FCC: |
727 | 0 | case SP::FMOVQ_ICC: |
728 | 0 | case SP::FMOVQ_XCC: |
729 | 0 | case SP::FMOVS_FCC: |
730 | 0 | case SP::FMOVS_ICC: |
731 | 0 | case SP::FMOVS_XCC: |
732 | 0 | case SP::MOVFCCrr: |
733 | 0 | case SP::MOVICCrr: |
734 | 0 | case SP::MOVXCCrr: { |
735 | | // op: rd |
736 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
737 | 0 | Value |= (op & UINT64_C(31)) << 25; |
738 | | // op: cond |
739 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
740 | 0 | Value |= (op & UINT64_C(15)) << 14; |
741 | | // op: rs2 |
742 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
743 | 0 | Value |= op & UINT64_C(31); |
744 | 0 | break; |
745 | 0 | } |
746 | 0 | case SP::MOVFCCri: |
747 | 0 | case SP::MOVICCri: |
748 | 0 | case SP::MOVXCCri: { |
749 | | // op: rd |
750 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
751 | 0 | Value |= (op & UINT64_C(31)) << 25; |
752 | | // op: cond |
753 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
754 | 0 | Value |= (op & UINT64_C(15)) << 14; |
755 | | // op: simm11 |
756 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
757 | 0 | Value |= op & UINT64_C(2047); |
758 | 0 | break; |
759 | 0 | } |
760 | 0 | case SP::V9FMOVD_FCC: |
761 | 0 | case SP::V9FMOVQ_FCC: |
762 | 0 | case SP::V9FMOVS_FCC: { |
763 | | // op: rd |
764 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
765 | 0 | Value |= (op & UINT64_C(31)) << 25; |
766 | | // op: cond |
767 | 0 | op = getMachineOpValue(MI, MI.getOperand(4), Fixups, STI); |
768 | 0 | Value |= (op & UINT64_C(15)) << 14; |
769 | | // op: opf_cc |
770 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
771 | 0 | Value |= (op & UINT64_C(3)) << 11; |
772 | | // op: rs2 |
773 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
774 | 0 | Value |= op & UINT64_C(31); |
775 | 0 | break; |
776 | 0 | } |
777 | 0 | case SP::FNOT1: |
778 | 0 | case SP::FNOT1S: |
779 | 0 | case SP::FSRC1: |
780 | 0 | case SP::FSRC1S: |
781 | 0 | case SP::RDASR: |
782 | 0 | case SP::RDPR: { |
783 | | // op: rd |
784 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
785 | 0 | Value |= (op & UINT64_C(31)) << 25; |
786 | | // op: rs1 |
787 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
788 | 0 | Value |= (op & UINT64_C(31)) << 14; |
789 | 0 | break; |
790 | 0 | } |
791 | 0 | case SP::LDArr: |
792 | 0 | case SP::LDDArr: |
793 | 0 | case SP::LDDFArr: |
794 | 0 | case SP::LDFArr: |
795 | 0 | case SP::LDQFArr: |
796 | 0 | case SP::LDSBArr: |
797 | 0 | case SP::LDSHArr: |
798 | 0 | case SP::LDSTUBArr: |
799 | 0 | case SP::LDUBArr: |
800 | 0 | case SP::LDUHArr: |
801 | 0 | case SP::SWAPArr: { |
802 | | // op: rd |
803 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
804 | 0 | Value |= (op & UINT64_C(31)) << 25; |
805 | | // op: rs1 |
806 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
807 | 0 | Value |= (op & UINT64_C(31)) << 14; |
808 | | // op: asi |
809 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
810 | 0 | Value |= (op & UINT64_C(255)) << 5; |
811 | | // op: rs2 |
812 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
813 | 0 | Value |= op & UINT64_C(31); |
814 | 0 | break; |
815 | 0 | } |
816 | 0 | case SP::ADDCCrr: |
817 | 0 | case SP::ADDCrr: |
818 | 0 | case SP::ADDErr: |
819 | 0 | case SP::ADDXC: |
820 | 0 | case SP::ADDXCCC: |
821 | 0 | case SP::ADDXrr: |
822 | 0 | case SP::ADDrr: |
823 | 0 | case SP::ALIGNADDR: |
824 | 0 | case SP::ALIGNADDRL: |
825 | 0 | case SP::ANDCCrr: |
826 | 0 | case SP::ANDNCCrr: |
827 | 0 | case SP::ANDNrr: |
828 | 0 | case SP::ANDXNrr: |
829 | 0 | case SP::ANDXrr: |
830 | 0 | case SP::ANDrr: |
831 | 0 | case SP::ARRAY16: |
832 | 0 | case SP::ARRAY32: |
833 | 0 | case SP::ARRAY8: |
834 | 0 | case SP::BMASK: |
835 | 0 | case SP::BSHUFFLE: |
836 | 0 | case SP::CASXrr: |
837 | 0 | case SP::CASrr: |
838 | 0 | case SP::EDGE16: |
839 | 0 | case SP::EDGE16L: |
840 | 0 | case SP::EDGE16LN: |
841 | 0 | case SP::EDGE16N: |
842 | 0 | case SP::EDGE32: |
843 | 0 | case SP::EDGE32L: |
844 | 0 | case SP::EDGE32LN: |
845 | 0 | case SP::EDGE32N: |
846 | 0 | case SP::EDGE8: |
847 | 0 | case SP::EDGE8L: |
848 | 0 | case SP::EDGE8LN: |
849 | 0 | case SP::EDGE8N: |
850 | 0 | case SP::FADDD: |
851 | 0 | case SP::FADDQ: |
852 | 0 | case SP::FADDS: |
853 | 0 | case SP::FALIGNADATA: |
854 | 0 | case SP::FAND: |
855 | 0 | case SP::FANDNOT1: |
856 | 0 | case SP::FANDNOT1S: |
857 | 0 | case SP::FANDNOT2: |
858 | 0 | case SP::FANDNOT2S: |
859 | 0 | case SP::FANDS: |
860 | 0 | case SP::FCHKSM16: |
861 | 0 | case SP::FCMPEQ16: |
862 | 0 | case SP::FCMPEQ32: |
863 | 0 | case SP::FCMPGT16: |
864 | 0 | case SP::FCMPGT32: |
865 | 0 | case SP::FCMPLE16: |
866 | 0 | case SP::FCMPLE32: |
867 | 0 | case SP::FCMPNE16: |
868 | 0 | case SP::FCMPNE32: |
869 | 0 | case SP::FDIVD: |
870 | 0 | case SP::FDIVQ: |
871 | 0 | case SP::FDIVS: |
872 | 0 | case SP::FDMULQ: |
873 | 0 | case SP::FHADDD: |
874 | 0 | case SP::FHADDS: |
875 | 0 | case SP::FHSUBD: |
876 | 0 | case SP::FHSUBS: |
877 | 0 | case SP::FLCMPD: |
878 | 0 | case SP::FLCMPS: |
879 | 0 | case SP::FMEAN16: |
880 | 0 | case SP::FMOVRGEZD: |
881 | 0 | case SP::FMOVRGEZQ: |
882 | 0 | case SP::FMOVRGEZS: |
883 | 0 | case SP::FMOVRGZD: |
884 | 0 | case SP::FMOVRGZQ: |
885 | 0 | case SP::FMOVRGZS: |
886 | 0 | case SP::FMOVRLEZD: |
887 | 0 | case SP::FMOVRLEZQ: |
888 | 0 | case SP::FMOVRLEZS: |
889 | 0 | case SP::FMOVRLZD: |
890 | 0 | case SP::FMOVRLZQ: |
891 | 0 | case SP::FMOVRLZS: |
892 | 0 | case SP::FMOVRNZD: |
893 | 0 | case SP::FMOVRNZQ: |
894 | 0 | case SP::FMOVRNZS: |
895 | 0 | case SP::FMOVRZD: |
896 | 0 | case SP::FMOVRZQ: |
897 | 0 | case SP::FMOVRZS: |
898 | 0 | case SP::FMUL8SUX16: |
899 | 0 | case SP::FMUL8ULX16: |
900 | 0 | case SP::FMUL8X16: |
901 | 0 | case SP::FMUL8X16AL: |
902 | 0 | case SP::FMUL8X16AU: |
903 | 0 | case SP::FMULD: |
904 | 0 | case SP::FMULD8SUX16: |
905 | 0 | case SP::FMULD8ULX16: |
906 | 0 | case SP::FMULQ: |
907 | 0 | case SP::FMULS: |
908 | 0 | case SP::FNADDD: |
909 | 0 | case SP::FNADDS: |
910 | 0 | case SP::FNAND: |
911 | 0 | case SP::FNANDS: |
912 | 0 | case SP::FNHADDD: |
913 | 0 | case SP::FNHADDS: |
914 | 0 | case SP::FNMULD: |
915 | 0 | case SP::FNMULS: |
916 | 0 | case SP::FNOR: |
917 | 0 | case SP::FNORS: |
918 | 0 | case SP::FNSMULD: |
919 | 0 | case SP::FOR: |
920 | 0 | case SP::FORNOT1: |
921 | 0 | case SP::FORNOT1S: |
922 | 0 | case SP::FORNOT2: |
923 | 0 | case SP::FORNOT2S: |
924 | 0 | case SP::FORS: |
925 | 0 | case SP::FPACK32: |
926 | 0 | case SP::FPADD16: |
927 | 0 | case SP::FPADD16S: |
928 | 0 | case SP::FPADD32: |
929 | 0 | case SP::FPADD32S: |
930 | 0 | case SP::FPADD64: |
931 | 0 | case SP::FPMERGE: |
932 | 0 | case SP::FPSUB16: |
933 | 0 | case SP::FPSUB16S: |
934 | 0 | case SP::FPSUB32: |
935 | 0 | case SP::FPSUB32S: |
936 | 0 | case SP::FSLAS16: |
937 | 0 | case SP::FSLAS32: |
938 | 0 | case SP::FSLL16: |
939 | 0 | case SP::FSLL32: |
940 | 0 | case SP::FSMULD: |
941 | 0 | case SP::FSRA16: |
942 | 0 | case SP::FSRA32: |
943 | 0 | case SP::FSRL16: |
944 | 0 | case SP::FSRL32: |
945 | 0 | case SP::FSUBD: |
946 | 0 | case SP::FSUBQ: |
947 | 0 | case SP::FSUBS: |
948 | 0 | case SP::FXNOR: |
949 | 0 | case SP::FXNORS: |
950 | 0 | case SP::FXOR: |
951 | 0 | case SP::FXORS: |
952 | 1.17k | case SP::JMPLrr: |
953 | 1.17k | case SP::LDDFrr: |
954 | 1.17k | case SP::LDDrr: |
955 | 1.17k | case SP::LDFrr: |
956 | 1.17k | case SP::LDQFrr: |
957 | 1.17k | case SP::LDSBrr: |
958 | 1.17k | case SP::LDSHrr: |
959 | 1.17k | case SP::LDSTUBrr: |
960 | 1.17k | case SP::LDSWrr: |
961 | 1.17k | case SP::LDUBrr: |
962 | 1.17k | case SP::LDUHrr: |
963 | 1.17k | case SP::LDXrr: |
964 | 1.17k | case SP::LDrr: |
965 | 1.17k | case SP::MOVRGEZrr: |
966 | 1.17k | case SP::MOVRGZrr: |
967 | 1.17k | case SP::MOVRLEZrr: |
968 | 1.17k | case SP::MOVRLZrr: |
969 | 1.17k | case SP::MOVRNZrr: |
970 | 1.17k | case SP::MOVRRZrr: |
971 | 1.17k | case SP::MULSCCrr: |
972 | 1.17k | case SP::MULXrr: |
973 | 1.17k | case SP::ORCCrr: |
974 | 1.17k | case SP::ORNCCrr: |
975 | 1.17k | case SP::ORNrr: |
976 | 1.17k | case SP::ORXNrr: |
977 | 1.17k | case SP::ORXrr: |
978 | 1.17k | case SP::ORrr: |
979 | 1.17k | case SP::PDIST: |
980 | 1.17k | case SP::PDISTN: |
981 | 1.17k | case SP::RESTORErr: |
982 | 1.26k | case SP::SAVErr: |
983 | 1.26k | case SP::SDIVCCrr: |
984 | 1.26k | case SP::SDIVXrr: |
985 | 1.26k | case SP::SDIVrr: |
986 | 1.26k | case SP::SLLXrr: |
987 | 1.26k | case SP::SLLrr: |
988 | 1.26k | case SP::SMULCCrr: |
989 | 1.26k | case SP::SMULrr: |
990 | 1.26k | case SP::SRAXrr: |
991 | 1.26k | case SP::SRArr: |
992 | 1.26k | case SP::SRLXrr: |
993 | 1.26k | case SP::SRLrr: |
994 | 1.26k | case SP::SUBCCrr: |
995 | 1.26k | case SP::SUBCrr: |
996 | 1.26k | case SP::SUBErr: |
997 | 1.26k | case SP::SUBXrr: |
998 | 1.26k | case SP::SUBrr: |
999 | 1.26k | case SP::SWAPrr: |
1000 | 1.26k | case SP::TADDCCTVrr: |
1001 | 1.26k | case SP::TADDCCrr: |
1002 | 1.26k | case SP::TLS_ADDXrr: |
1003 | 1.26k | case SP::TLS_ADDrr: |
1004 | 1.26k | case SP::TLS_LDXrr: |
1005 | 1.26k | case SP::TLS_LDrr: |
1006 | 1.26k | case SP::TSUBCCTVrr: |
1007 | 1.26k | case SP::TSUBCCrr: |
1008 | 1.26k | case SP::UDIVCCrr: |
1009 | 1.26k | case SP::UDIVXrr: |
1010 | 1.26k | case SP::UDIVrr: |
1011 | 1.26k | case SP::UMULCCrr: |
1012 | 1.26k | case SP::UMULXHI: |
1013 | 1.26k | case SP::UMULrr: |
1014 | 1.26k | case SP::V9FCMPD: |
1015 | 1.26k | case SP::V9FCMPED: |
1016 | 1.26k | case SP::V9FCMPEQ: |
1017 | 1.26k | case SP::V9FCMPES: |
1018 | 1.26k | case SP::V9FCMPQ: |
1019 | 1.26k | case SP::V9FCMPS: |
1020 | 1.26k | case SP::WRASRrr: |
1021 | 1.26k | case SP::WRPRrr: |
1022 | 1.26k | case SP::XMULX: |
1023 | 1.26k | case SP::XMULXHI: |
1024 | 1.26k | case SP::XNORCCrr: |
1025 | 1.26k | case SP::XNORXrr: |
1026 | 1.26k | case SP::XNORrr: |
1027 | 1.26k | case SP::XORCCrr: |
1028 | 1.26k | case SP::XORXrr: |
1029 | 1.26k | case SP::XORrr: { |
1030 | | // op: rd |
1031 | 1.26k | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1032 | 1.26k | Value |= (op & UINT64_C(31)) << 25; |
1033 | | // op: rs1 |
1034 | 1.26k | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1035 | 1.26k | Value |= (op & UINT64_C(31)) << 14; |
1036 | | // op: rs2 |
1037 | 1.26k | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1038 | 1.26k | Value |= op & UINT64_C(31); |
1039 | 1.26k | break; |
1040 | 1.26k | } |
1041 | 0 | case SP::SLLXri: |
1042 | 0 | case SP::SRAXri: |
1043 | 0 | case SP::SRLXri: { |
1044 | | // op: rd |
1045 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1046 | 0 | Value |= (op & UINT64_C(31)) << 25; |
1047 | | // op: rs1 |
1048 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1049 | 0 | Value |= (op & UINT64_C(31)) << 14; |
1050 | | // op: shcnt |
1051 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1052 | 0 | Value |= op & UINT64_C(63); |
1053 | 0 | break; |
1054 | 0 | } |
1055 | 0 | case SP::MOVRGEZri: |
1056 | 0 | case SP::MOVRGZri: |
1057 | 0 | case SP::MOVRLEZri: |
1058 | 0 | case SP::MOVRLZri: |
1059 | 0 | case SP::MOVRNZri: |
1060 | 0 | case SP::MOVRRZri: { |
1061 | | // op: rd |
1062 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1063 | 0 | Value |= (op & UINT64_C(31)) << 25; |
1064 | | // op: rs1 |
1065 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1066 | 0 | Value |= (op & UINT64_C(31)) << 14; |
1067 | | // op: simm10 |
1068 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1069 | 0 | Value |= op & UINT64_C(1023); |
1070 | 0 | break; |
1071 | 0 | } |
1072 | 0 | case SP::ADDCCri: |
1073 | 0 | case SP::ADDCri: |
1074 | 0 | case SP::ADDEri: |
1075 | 0 | case SP::ADDXri: |
1076 | 0 | case SP::ADDri: |
1077 | 0 | case SP::ANDCCri: |
1078 | 0 | case SP::ANDNCCri: |
1079 | 0 | case SP::ANDNri: |
1080 | 0 | case SP::ANDXri: |
1081 | 0 | case SP::ANDri: |
1082 | 21 | case SP::JMPLri: |
1083 | 21 | case SP::LDDFri: |
1084 | 21 | case SP::LDDri: |
1085 | 21 | case SP::LDFri: |
1086 | 21 | case SP::LDQFri: |
1087 | 21 | case SP::LDSBri: |
1088 | 21 | case SP::LDSHri: |
1089 | 21 | case SP::LDSTUBri: |
1090 | 21 | case SP::LDSWri: |
1091 | 21 | case SP::LDUBri: |
1092 | 21 | case SP::LDUHri: |
1093 | 21 | case SP::LDXri: |
1094 | 21 | case SP::LDri: |
1095 | 21 | case SP::LEAX_ADDri: |
1096 | 21 | case SP::LEA_ADDri: |
1097 | 21 | case SP::MULSCCri: |
1098 | 21 | case SP::MULXri: |
1099 | 21 | case SP::ORCCri: |
1100 | 21 | case SP::ORNCCri: |
1101 | 21 | case SP::ORNri: |
1102 | 21 | case SP::ORXri: |
1103 | 21 | case SP::ORri: |
1104 | 21 | case SP::RESTOREri: |
1105 | 21 | case SP::SAVEri: |
1106 | 21 | case SP::SDIVCCri: |
1107 | 21 | case SP::SDIVXri: |
1108 | 21 | case SP::SDIVri: |
1109 | 21 | case SP::SLLri: |
1110 | 21 | case SP::SMULCCri: |
1111 | 21 | case SP::SMULri: |
1112 | 21 | case SP::SRAri: |
1113 | 21 | case SP::SRLri: |
1114 | 21 | case SP::SUBCCri: |
1115 | 21 | case SP::SUBCri: |
1116 | 21 | case SP::SUBEri: |
1117 | 21 | case SP::SUBXri: |
1118 | 21 | case SP::SUBri: |
1119 | 21 | case SP::SWAPri: |
1120 | 21 | case SP::TADDCCTVri: |
1121 | 21 | case SP::TADDCCri: |
1122 | 21 | case SP::TSUBCCTVri: |
1123 | 21 | case SP::TSUBCCri: |
1124 | 21 | case SP::UDIVCCri: |
1125 | 21 | case SP::UDIVXri: |
1126 | 21 | case SP::UDIVri: |
1127 | 21 | case SP::UMULCCri: |
1128 | 21 | case SP::UMULri: |
1129 | 21 | case SP::WRASRri: |
1130 | 21 | case SP::WRPRri: |
1131 | 21 | case SP::XNORCCri: |
1132 | 21 | case SP::XNORri: |
1133 | 21 | case SP::XORCCri: |
1134 | 21 | case SP::XORXri: |
1135 | 21 | case SP::XORri: { |
1136 | | // op: rd |
1137 | 21 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1138 | 21 | Value |= (op & UINT64_C(31)) << 25; |
1139 | | // op: rs1 |
1140 | 21 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1141 | 21 | Value |= (op & UINT64_C(31)) << 14; |
1142 | | // op: simm13 |
1143 | 21 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1144 | 21 | Value |= op & UINT64_C(8191); |
1145 | 21 | break; |
1146 | 21 | } |
1147 | 0 | case SP::FABSD: |
1148 | 0 | case SP::FABSQ: |
1149 | 0 | case SP::FABSS: |
1150 | 0 | case SP::FDTOI: |
1151 | 0 | case SP::FDTOQ: |
1152 | 0 | case SP::FDTOS: |
1153 | 0 | case SP::FDTOX: |
1154 | 0 | case SP::FEXPAND: |
1155 | 0 | case SP::FITOD: |
1156 | 0 | case SP::FITOQ: |
1157 | 0 | case SP::FITOS: |
1158 | 0 | case SP::FMOVD: |
1159 | 0 | case SP::FMOVQ: |
1160 | 0 | case SP::FMOVS: |
1161 | 0 | case SP::FNEGD: |
1162 | 0 | case SP::FNEGQ: |
1163 | 0 | case SP::FNEGS: |
1164 | 0 | case SP::FNOT2: |
1165 | 0 | case SP::FNOT2S: |
1166 | 0 | case SP::FPACK16: |
1167 | 0 | case SP::FPACKFIX: |
1168 | 0 | case SP::FQTOD: |
1169 | 0 | case SP::FQTOI: |
1170 | 0 | case SP::FQTOS: |
1171 | 0 | case SP::FQTOX: |
1172 | 0 | case SP::FSQRTD: |
1173 | 0 | case SP::FSQRTQ: |
1174 | 0 | case SP::FSQRTS: |
1175 | 0 | case SP::FSRC2: |
1176 | 0 | case SP::FSRC2S: |
1177 | 0 | case SP::FSTOD: |
1178 | 0 | case SP::FSTOI: |
1179 | 0 | case SP::FSTOQ: |
1180 | 0 | case SP::FSTOX: |
1181 | 0 | case SP::FXTOD: |
1182 | 0 | case SP::FXTOQ: |
1183 | 0 | case SP::FXTOS: |
1184 | 0 | case SP::LZCNT: |
1185 | 0 | case SP::MOVDTOX: |
1186 | 0 | case SP::MOVSTOSW: |
1187 | 0 | case SP::MOVSTOUW: |
1188 | 0 | case SP::MOVWTOS: |
1189 | 0 | case SP::MOVXTOD: |
1190 | 0 | case SP::POPCrr: { |
1191 | | // op: rd |
1192 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1193 | 0 | Value |= (op & UINT64_C(31)) << 25; |
1194 | | // op: rs2 |
1195 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1196 | 0 | Value |= op & UINT64_C(31); |
1197 | 0 | break; |
1198 | 0 | } |
1199 | 0 | case SP::STArr: |
1200 | 0 | case SP::STBArr: |
1201 | 0 | case SP::STDArr: |
1202 | 0 | case SP::STDFArr: |
1203 | 0 | case SP::STFArr: |
1204 | 0 | case SP::STHArr: |
1205 | 0 | case SP::STQFArr: { |
1206 | | // op: rd |
1207 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1208 | 0 | Value |= (op & UINT64_C(31)) << 25; |
1209 | | // op: rs1 |
1210 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1211 | 0 | Value |= (op & UINT64_C(31)) << 14; |
1212 | | // op: asi |
1213 | 0 | op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI); |
1214 | 0 | Value |= (op & UINT64_C(255)) << 5; |
1215 | | // op: rs2 |
1216 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1217 | 0 | Value |= op & UINT64_C(31); |
1218 | 0 | break; |
1219 | 0 | } |
1220 | 0 | case SP::STBrr: |
1221 | 0 | case SP::STDFrr: |
1222 | 0 | case SP::STDrr: |
1223 | 0 | case SP::STFrr: |
1224 | 0 | case SP::STHrr: |
1225 | 0 | case SP::STQFrr: |
1226 | 0 | case SP::STXrr: |
1227 | 0 | case SP::STrr: { |
1228 | | // op: rd |
1229 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1230 | 0 | Value |= (op & UINT64_C(31)) << 25; |
1231 | | // op: rs1 |
1232 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1233 | 0 | Value |= (op & UINT64_C(31)) << 14; |
1234 | | // op: rs2 |
1235 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1236 | 0 | Value |= op & UINT64_C(31); |
1237 | 0 | break; |
1238 | 0 | } |
1239 | 0 | case SP::STBri: |
1240 | 0 | case SP::STDFri: |
1241 | 0 | case SP::STDri: |
1242 | 0 | case SP::STFri: |
1243 | 0 | case SP::STHri: |
1244 | 0 | case SP::STQFri: |
1245 | 0 | case SP::STXri: |
1246 | 0 | case SP::STri: { |
1247 | | // op: rd |
1248 | 0 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1249 | 0 | Value |= (op & UINT64_C(31)) << 25; |
1250 | | // op: rs1 |
1251 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1252 | 0 | Value |= (op & UINT64_C(31)) << 14; |
1253 | | // op: simm13 |
1254 | 0 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1255 | 0 | Value |= op & UINT64_C(8191); |
1256 | 0 | break; |
1257 | 0 | } |
1258 | 60 | case SP::TICCri: |
1259 | 60 | case SP::TXCCri: { |
1260 | | // op: rs1 |
1261 | 60 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1262 | 60 | Value |= (op & UINT64_C(31)) << 14; |
1263 | | // op: cond |
1264 | 60 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1265 | 60 | Value |= (op & UINT64_C(15)) << 25; |
1266 | | // op: imm |
1267 | 60 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1268 | 60 | Value |= op & UINT64_C(255); |
1269 | 60 | break; |
1270 | 60 | } |
1271 | 22 | case SP::TICCrr: |
1272 | 22 | case SP::TXCCrr: { |
1273 | | // op: rs1 |
1274 | 22 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1275 | 22 | Value |= (op & UINT64_C(31)) << 14; |
1276 | | // op: cond |
1277 | 22 | op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI); |
1278 | 22 | Value |= (op & UINT64_C(15)) << 25; |
1279 | | // op: rs2 |
1280 | 22 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1281 | 22 | Value |= op & UINT64_C(31); |
1282 | 22 | break; |
1283 | 22 | } |
1284 | 0 | case SP::BINDrr: |
1285 | 0 | case SP::CALLrr: |
1286 | 0 | case SP::CMPrr: |
1287 | 0 | case SP::FCMPD: |
1288 | 0 | case SP::FCMPQ: |
1289 | 0 | case SP::FCMPS: |
1290 | 1 | case SP::FLUSHrr: |
1291 | 1 | case SP::LDFSRrr: |
1292 | 1 | case SP::LDXFSRrr: |
1293 | 18 | case SP::RETTrr: |
1294 | 18 | case SP::STFSRrr: |
1295 | 18 | case SP::STXFSRrr: |
1296 | 18 | case SP::WRPSRrr: |
1297 | 18 | case SP::WRTBRrr: |
1298 | 18 | case SP::WRWIMrr: { |
1299 | | // op: rs1 |
1300 | 18 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1301 | 18 | Value |= (op & UINT64_C(31)) << 14; |
1302 | | // op: rs2 |
1303 | 18 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1304 | 18 | Value |= op & UINT64_C(31); |
1305 | 18 | break; |
1306 | 18 | } |
1307 | 0 | case SP::BINDri: |
1308 | 0 | case SP::CALLri: |
1309 | 0 | case SP::CMPri: |
1310 | 3 | case SP::FLUSHri: |
1311 | 3 | case SP::LDFSRri: |
1312 | 3 | case SP::LDXFSRri: |
1313 | 6 | case SP::RETTri: |
1314 | 6 | case SP::STFSRri: |
1315 | 6 | case SP::STXFSRri: |
1316 | 6 | case SP::WRPSRri: |
1317 | 6 | case SP::WRTBRri: |
1318 | 6 | case SP::WRWIMri: { |
1319 | | // op: rs1 |
1320 | 6 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1321 | 6 | Value |= (op & UINT64_C(31)) << 14; |
1322 | | // op: simm13 |
1323 | 6 | op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI); |
1324 | 6 | Value |= op & UINT64_C(8191); |
1325 | 6 | break; |
1326 | 6 | } |
1327 | 0 | case SP::CMASK16: |
1328 | 0 | case SP::CMASK32: |
1329 | 0 | case SP::CMASK8: { |
1330 | | // op: rs2 |
1331 | 0 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1332 | 0 | Value |= op & UINT64_C(31); |
1333 | 0 | break; |
1334 | 0 | } |
1335 | 0 | case SP::MEMBARi: |
1336 | 12 | case SP::RET: |
1337 | 13 | case SP::RETL: { |
1338 | | // op: simm13 |
1339 | 13 | op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI); |
1340 | 13 | Value |= op & UINT64_C(8191); |
1341 | 13 | break; |
1342 | 12 | } |
1343 | 0 | default: |
1344 | 0 | std::string msg; |
1345 | 0 | raw_string_ostream Msg(msg); |
1346 | 0 | Msg << "Not supported instr: " << MI; |
1347 | 0 | report_fatal_error(Msg.str()); |
1348 | 6.32k | } |
1349 | 6.32k | return Value; |
1350 | 6.32k | } |
1351 | | |