/src/keystone/llvm/lib/Target/ARM/ARMFeatures.h
Line | Count | Source |
1 | | //===-- ARMFeatures.h - Checks for ARM instruction features -----*- C++ -*-===// |
2 | | // |
3 | | // The LLVM Compiler Infrastructure |
4 | | // |
5 | | // This file is distributed under the University of Illinois Open Source |
6 | | // License. See LICENSE.TXT for details. |
7 | | // |
8 | | //===----------------------------------------------------------------------===// |
9 | | // |
10 | | // This file contains the code shared between ARM CodeGen and ARM MC |
11 | | // |
12 | | //===----------------------------------------------------------------------===// |
13 | | |
14 | | #ifndef LLVM_LIB_TARGET_ARM_ARMFEATURES_H |
15 | | #define LLVM_LIB_TARGET_ARM_ARMFEATURES_H |
16 | | |
17 | | #include "MCTargetDesc/ARMMCTargetDesc.h" |
18 | | |
19 | | namespace llvm_ks { |
20 | | |
21 | | template<typename InstrType> // could be MachineInstr or MCInst |
22 | | bool IsCPSRDead(InstrType *Instr); |
23 | | |
24 | | template<typename InstrType> // could be MachineInstr or MCInst |
25 | 373 | inline bool isV8EligibleForIT(InstrType *Instr) { |
26 | 373 | switch (Instr->getOpcode()) { |
27 | 281 | default: |
28 | 281 | return false; |
29 | 9 | case ARM::tADC: |
30 | 15 | case ARM::tADDi3: |
31 | 22 | case ARM::tADDi8: |
32 | 25 | case ARM::tADDrr: |
33 | 28 | case ARM::tAND: |
34 | 28 | case ARM::tASRri: |
35 | 28 | case ARM::tASRrr: |
36 | 28 | case ARM::tBIC: |
37 | 28 | case ARM::tEOR: |
38 | 28 | case ARM::tLSLri: |
39 | 28 | case ARM::tLSLrr: |
40 | 28 | case ARM::tLSRri: |
41 | 28 | case ARM::tLSRrr: |
42 | 28 | case ARM::tMOVi8: |
43 | 28 | case ARM::tMUL: |
44 | 28 | case ARM::tMVN: |
45 | 28 | case ARM::tORR: |
46 | 28 | case ARM::tROR: |
47 | 28 | case ARM::tRSB: |
48 | 29 | case ARM::tSBC: |
49 | 29 | case ARM::tSUBi3: |
50 | 29 | case ARM::tSUBi8: |
51 | 30 | case ARM::tSUBrr: |
52 | | // Outside of an IT block, these set CPSR. |
53 | 30 | return IsCPSRDead(Instr); |
54 | 0 | case ARM::tADDrSPi: |
55 | 0 | case ARM::tCMNz: |
56 | 0 | case ARM::tCMPi8: |
57 | 0 | case ARM::tCMPr: |
58 | 7 | case ARM::tLDRBi: |
59 | 15 | case ARM::tLDRBr: |
60 | 15 | case ARM::tLDRHi: |
61 | 21 | case ARM::tLDRHr: |
62 | 21 | case ARM::tLDRSB: |
63 | 21 | case ARM::tLDRSH: |
64 | 23 | case ARM::tLDRi: |
65 | 53 | case ARM::tLDRr: |
66 | 53 | case ARM::tLDRspi: |
67 | 53 | case ARM::tSTRBi: |
68 | 53 | case ARM::tSTRBr: |
69 | 53 | case ARM::tSTRHi: |
70 | 53 | case ARM::tSTRHr: |
71 | 53 | case ARM::tSTRi: |
72 | 53 | case ARM::tSTRr: |
73 | 53 | case ARM::tSTRspi: |
74 | 53 | case ARM::tTST: |
75 | 53 | return true; |
76 | | // there are some "conditionally deprecated" opcodes |
77 | 1 | case ARM::tADDspr: |
78 | 3 | case ARM::tBLXr: |
79 | 3 | return Instr->getOperand(2).getReg() != ARM::PC; |
80 | | // ADD PC, SP and BLX PC were always unpredictable, |
81 | | // now on top of it they're deprecated |
82 | 1 | case ARM::tADDrSP: |
83 | 2 | case ARM::tBX: |
84 | 2 | return Instr->getOperand(0).getReg() != ARM::PC; |
85 | 4 | case ARM::tADDhirr: |
86 | 4 | return Instr->getOperand(0).getReg() != ARM::PC && |
87 | 4 | Instr->getOperand(2).getReg() != ARM::PC; |
88 | 0 | case ARM::tCMPhir: |
89 | 0 | case ARM::tMOVr: |
90 | 0 | return Instr->getOperand(0).getReg() != ARM::PC && |
91 | 0 | Instr->getOperand(1).getReg() != ARM::PC; |
92 | 373 | } |
93 | 373 | } |
94 | | |
95 | | } |
96 | | |
97 | | #endif |