/src/aom/aom_dsp/x86/sad4d_avx2.c

Source
/*
 * Copyright (c) 2016, Alliance for Open Media. All rights reserved.
 *
 * This source code is subject to the terms of the BSD 2 Clause License and
 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
 * was not distributed with this source code in the LICENSE file, you can
 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
 * Media Patent License 1.0 was not distributed with this source code in the
 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
 */
#include <immintrin.h>  // AVX2

#include "config/aom_dsp_rtcd.h"

#include "aom/aom_integer.h"
#include "aom_dsp/x86/synonyms_avx2.h"

static AOM_FORCE_INLINE void aggregate_and_store_sum(uint32_t res[4],
                                                     const __m256i *sum_ref0,
                                                     const __m256i *sum_ref1,
                                                     const __m256i *sum_ref2,
                                                     const __m256i *sum_ref3) {
  // In sum_ref-i the result is saved in the first 4 bytes and the other 4
  // bytes are zeroed.
  // merge sum_ref0 and sum_ref1 also sum_ref2 and sum_ref3
  // 0, 0, 1, 1
  __m256i sum_ref01 = _mm256_castps_si256(_mm256_shuffle_ps(
      _mm256_castsi256_ps(*sum_ref0), _mm256_castsi256_ps(*sum_ref1),
      _MM_SHUFFLE(2, 0, 2, 0)));
  // 2, 2, 3, 3
  __m256i sum_ref23 = _mm256_castps_si256(_mm256_shuffle_ps(
      _mm256_castsi256_ps(*sum_ref2), _mm256_castsi256_ps(*sum_ref3),
      _MM_SHUFFLE(2, 0, 2, 0)));

  // sum adjacent 32 bit integers
  __m256i sum_ref0123 = _mm256_hadd_epi32(sum_ref01, sum_ref23);

  // add the low 128 bit to the high 128 bit
  __m128i sum = _mm_add_epi32(_mm256_castsi256_si128(sum_ref0123),
                              _mm256_extractf128_si256(sum_ref0123, 1));

  _mm_storeu_si128((__m128i *)(res), sum);
}

static AOM_FORCE_INLINE void aom_sadMxNx4d_avx2(
    int M, int N, const uint8_t *src, int src_stride,
    const uint8_t *const ref[4], int ref_stride, uint32_t res[4]) {
  __m256i src_reg, ref0_reg, ref1_reg, ref2_reg, ref3_reg;
  __m256i sum_ref0, sum_ref1, sum_ref2, sum_ref3;
  int i, j;
  const uint8_t *ref0, *ref1, *ref2, *ref3;

  ref0 = ref[0];
  ref1 = ref[1];
  ref2 = ref[2];
  ref3 = ref[3];
  sum_ref0 = _mm256_setzero_si256();
  sum_ref2 = _mm256_setzero_si256();
  sum_ref1 = _mm256_setzero_si256();
  sum_ref3 = _mm256_setzero_si256();

  for (i = 0; i < N; i++) {
    for (j = 0; j < M; j += 32) {
      // load src and all refs
      src_reg = _mm256_loadu_si256((const __m256i *)(src + j));
      ref0_reg = _mm256_loadu_si256((const __m256i *)(ref0 + j));
      ref1_reg = _mm256_loadu_si256((const __m256i *)(ref1 + j));
      ref2_reg = _mm256_loadu_si256((const __m256i *)(ref2 + j));
      ref3_reg = _mm256_loadu_si256((const __m256i *)(ref3 + j));

      // sum of the absolute differences between every ref-i to src
      ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
      ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
      ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
      ref3_reg = _mm256_sad_epu8(ref3_reg, src_reg);
      // sum every ref-i
      sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
      sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
      sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
      sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);
    }
    src += src_stride;
    ref0 += ref_stride;
    ref1 += ref_stride;
    ref2 += ref_stride;
    ref3 += ref_stride;
  }

  aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &sum_ref3);
}

static AOM_FORCE_INLINE void aom_sadMxNx3d_avx2(
    int M, int N, const uint8_t *src, int src_stride,
    const uint8_t *const ref[4], int ref_stride, uint32_t res[4]) {
  __m256i src_reg, ref0_reg, ref1_reg, ref2_reg;
  __m256i sum_ref0, sum_ref1, sum_ref2;
  int i, j;
  const uint8_t *ref0, *ref1, *ref2;
  const __m256i zero = _mm256_setzero_si256();

  ref0 = ref[0];
  ref1 = ref[1];
  ref2 = ref[2];
  sum_ref0 = _mm256_setzero_si256();
  sum_ref2 = _mm256_setzero_si256();
  sum_ref1 = _mm256_setzero_si256();

  for (i = 0; i < N; i++) {
    for (j = 0; j < M; j += 32) {
      // load src and all refs
      src_reg = _mm256_loadu_si256((const __m256i *)(src + j));
      ref0_reg = _mm256_loadu_si256((const __m256i *)(ref0 + j));
      ref1_reg = _mm256_loadu_si256((const __m256i *)(ref1 + j));
      ref2_reg = _mm256_loadu_si256((const __m256i *)(ref2 + j));

      // sum of the absolute differences between every ref-i to src
      ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
      ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
      ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
      // sum every ref-i
      sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
      sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
      sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
    }
    src += src_stride;
    ref0 += ref_stride;
    ref1 += ref_stride;
    ref2 += ref_stride;
  }
  aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &zero);
}

#define SADMXN_AVX2(m, n)                                                      \
  void aom_sad##m##x##n##x4d_avx2(const uint8_t *src, int src_stride,          \
                                  const uint8_t *const ref[4], int ref_stride, \
                                  uint32_t res[4]) {                           \
    aom_sadMxNx4d_avx2(m, n, src, src_stride, ref, ref_stride, res);           \
  }                                                                            \
  void aom_sad##m##x##n##x3d_avx2(const uint8_t *src, int src_stride,          \
                                  const uint8_t *const ref[4], int ref_stride, \
                                  uint32_t res[4]) {                           \
    aom_sadMxNx3d_avx2(m, n, src, src_stride, ref, ref_stride, res);           \
  }

SADMXN_AVX2(32, 16)
SADMXN_AVX2(32, 32)
SADMXN_AVX2(32, 64)

#if !CONFIG_HIGHWAY
SADMXN_AVX2(64, 32)
SADMXN_AVX2(64, 64)
SADMXN_AVX2(64, 128)

SADMXN_AVX2(128, 64)
SADMXN_AVX2(128, 128)
#endif

#if !CONFIG_REALTIME_ONLY
SADMXN_AVX2(32, 8)
SADMXN_AVX2(64, 16)
#endif  // !CONFIG_REALTIME_ONLY

#define SAD_SKIP_MXN_AVX2(m, n)                                             \
  void aom_sad_skip_##m##x##n##x4d_avx2(const uint8_t *src, int src_stride, \
                                        const uint8_t *const ref[4],        \
                                        int ref_stride, uint32_t res[4]) {  \
    aom_sadMxNx4d_avx2(m, ((n) >> 1), src, 2 * src_stride, ref,             \
                       2 * ref_stride, res);                                \
    res[0] <<= 1;                                                           \
    res[1] <<= 1;                                                           \
    res[2] <<= 1;                                                           \
    res[3] <<= 1;                                                           \
  }

SAD_SKIP_MXN_AVX2(32, 16)
SAD_SKIP_MXN_AVX2(32, 32)
SAD_SKIP_MXN_AVX2(32, 64)

#if !CONFIG_HIGHWAY
SAD_SKIP_MXN_AVX2(64, 32)
SAD_SKIP_MXN_AVX2(64, 64)
SAD_SKIP_MXN_AVX2(64, 128)

SAD_SKIP_MXN_AVX2(128, 64)
SAD_SKIP_MXN_AVX2(128, 128)
#endif

#if !CONFIG_REALTIME_ONLY
SAD_SKIP_MXN_AVX2(64, 16)
#endif  // !CONFIG_REALTIME_ONLY

static AOM_FORCE_INLINE void aom_sad16xNx3d_avx2(int N, const uint8_t *src,
                                                 int src_stride,
                                                 const uint8_t *const ref[4],
                                                 int ref_stride,
                                                 uint32_t res[4]) {
  __m256i src_reg, ref0_reg, ref1_reg, ref2_reg;
  __m256i sum_ref0, sum_ref1, sum_ref2;
  const uint8_t *ref0, *ref1, *ref2;
  const __m256i zero = _mm256_setzero_si256();
  assert(N % 2 == 0);

  ref0 = ref[0];
  ref1 = ref[1];
  ref2 = ref[2];
  sum_ref0 = _mm256_setzero_si256();
  sum_ref2 = _mm256_setzero_si256();
  sum_ref1 = _mm256_setzero_si256();

  for (int i = 0; i < N; i += 2) {
    // load src and all refs
    src_reg = yy_loadu2_128(src + src_stride, src);
    ref0_reg = yy_loadu2_128(ref0 + ref_stride, ref0);
    ref1_reg = yy_loadu2_128(ref1 + ref_stride, ref1);
    ref2_reg = yy_loadu2_128(ref2 + ref_stride, ref2);

    // sum of the absolute differences between every ref-i to src
    ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
    ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
    ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);

    // sum every ref-i
    sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
    sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
    sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);

    src += 2 * src_stride;
    ref0 += 2 * ref_stride;
    ref1 += 2 * ref_stride;
    ref2 += 2 * ref_stride;
  }

  aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &zero);
}

static AOM_FORCE_INLINE void aom_sad16xNx4d_avx2(int N, const uint8_t *src,
                                                 int src_stride,
                                                 const uint8_t *const ref[4],
                                                 int ref_stride,
                                                 uint32_t res[4]) {
  __m256i src_reg, ref0_reg, ref1_reg, ref2_reg, ref3_reg;
  __m256i sum_ref0, sum_ref1, sum_ref2, sum_ref3;
  const uint8_t *ref0, *ref1, *ref2, *ref3;
  assert(N % 2 == 0);

  ref0 = ref[0];
  ref1 = ref[1];
  ref2 = ref[2];
  ref3 = ref[3];

  sum_ref0 = _mm256_setzero_si256();
  sum_ref2 = _mm256_setzero_si256();
  sum_ref1 = _mm256_setzero_si256();
  sum_ref3 = _mm256_setzero_si256();

  for (int i = 0; i < N; i += 2) {
    // load src and all refs
    src_reg = yy_loadu2_128(src + src_stride, src);
    ref0_reg = yy_loadu2_128(ref0 + ref_stride, ref0);
    ref1_reg = yy_loadu2_128(ref1 + ref_stride, ref1);
    ref2_reg = yy_loadu2_128(ref2 + ref_stride, ref2);
    ref3_reg = yy_loadu2_128(ref3 + ref_stride, ref3);

    // sum of the absolute differences between every ref-i to src
    ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
    ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
    ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
    ref3_reg = _mm256_sad_epu8(ref3_reg, src_reg);

    // sum every ref-i
    sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
    sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
    sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
    sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);

    src += 2 * src_stride;
    ref0 += 2 * ref_stride;
    ref1 += 2 * ref_stride;
    ref2 += 2 * ref_stride;
    ref3 += 2 * ref_stride;
  }

  aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &sum_ref3);
}

#define SAD16XNX3_AVX2(n)                                                   \
  void aom_sad16x##n##x3d_avx2(const uint8_t *src, int src_stride,          \
                               const uint8_t *const ref[4], int ref_stride, \
                               uint32_t res[4]) {                           \
    aom_sad16xNx3d_avx2(n, src, src_stride, ref, ref_stride, res);          \
  }
#define SAD16XNX4_AVX2(n)                                                   \
  void aom_sad16x##n##x4d_avx2(const uint8_t *src, int src_stride,          \
                               const uint8_t *const ref[4], int ref_stride, \
                               uint32_t res[4]) {                           \
    aom_sad16xNx4d_avx2(n, src, src_stride, ref, ref_stride, res);          \
  }

SAD16XNX4_AVX2(32)
SAD16XNX4_AVX2(16)
SAD16XNX4_AVX2(8)

SAD16XNX3_AVX2(32)
SAD16XNX3_AVX2(16)
SAD16XNX3_AVX2(8)

#if !CONFIG_REALTIME_ONLY
SAD16XNX3_AVX2(64)
SAD16XNX3_AVX2(4)

SAD16XNX4_AVX2(64)
SAD16XNX4_AVX2(4)

#endif  // !CONFIG_REALTIME_ONLY

#define SAD_SKIP_16XN_AVX2(n)                                                 \
  void aom_sad_skip_16x##n##x4d_avx2(const uint8_t *src, int src_stride,      \
                                     const uint8_t *const ref[4],             \
                                     int ref_stride, uint32_t res[4]) {       \
    aom_sad16xNx4d_avx2(((n) >> 1), src, 2 * src_stride, ref, 2 * ref_stride, \
                        res);                                                 \
    res[0] <<= 1;                                                             \
    res[1] <<= 1;                                                             \
    res[2] <<= 1;                                                             \
    res[3] <<= 1;                                                             \
  }

SAD_SKIP_16XN_AVX2(32)
SAD_SKIP_16XN_AVX2(16)

#if !CONFIG_REALTIME_ONLY
SAD_SKIP_16XN_AVX2(64)
#endif  // !CONFIG_REALTIME_ONLY

Coverage Report

Created: 2026-09-07 06:44

Line	Count	Source
1		/*
2		* Copyright (c) 2016, Alliance for Open Media. All rights reserved.
3		*
4		* This source code is subject to the terms of the BSD 2 Clause License and
5		* the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6		* was not distributed with this source code in the LICENSE file, you can
7		* obtain it at www.aomedia.org/license/software. If the Alliance for Open
8		* Media Patent License 1.0 was not distributed with this source code in the
9		* PATENTS file, you can obtain it at www.aomedia.org/license/patent.
10		*/
11		#include <immintrin.h> // AVX2
12
13		#include "config/aom_dsp_rtcd.h"
14
15		#include "aom/aom_integer.h"
16		#include "aom_dsp/x86/synonyms_avx2.h"
17
18		static AOM_FORCE_INLINE void aggregate_and_store_sum(uint32_t res[4],
19		const __m256i *sum_ref0,
20		const __m256i *sum_ref1,
21		const __m256i *sum_ref2,
22	0	const __m256i *sum_ref3) {
23		// In sum_ref-i the result is saved in the first 4 bytes and the other 4
24		// bytes are zeroed.
25		// merge sum_ref0 and sum_ref1 also sum_ref2 and sum_ref3
26		// 0, 0, 1, 1
27	0	__m256i sum_ref01 = _mm256_castps_si256(_mm256_shuffle_ps(
28	0	_mm256_castsi256_ps(sum_ref0), _mm256_castsi256_ps(sum_ref1),
29	0	_MM_SHUFFLE(2, 0, 2, 0)));
30		// 2, 2, 3, 3
31	0	__m256i sum_ref23 = _mm256_castps_si256(_mm256_shuffle_ps(
32	0	_mm256_castsi256_ps(sum_ref2), _mm256_castsi256_ps(sum_ref3),
33	0	_MM_SHUFFLE(2, 0, 2, 0)));
34
35		// sum adjacent 32 bit integers
36	0	__m256i sum_ref0123 = _mm256_hadd_epi32(sum_ref01, sum_ref23);
37
38		// add the low 128 bit to the high 128 bit
39	0	__m128i sum = _mm_add_epi32(_mm256_castsi256_si128(sum_ref0123),
40	0	_mm256_extractf128_si256(sum_ref0123, 1));
41
42	0	_mm_storeu_si128((__m128i *)(res), sum);
43	0	}
44
45		static AOM_FORCE_INLINE void aom_sadMxNx4d_avx2(
46		int M, int N, const uint8_t *src, int src_stride,
47	0	const uint8_t *const ref[4], int ref_stride, uint32_t res[4]) {
48	0	__m256i src_reg, ref0_reg, ref1_reg, ref2_reg, ref3_reg;
49	0	__m256i sum_ref0, sum_ref1, sum_ref2, sum_ref3;
50	0	int i, j;
51	0	const uint8_t ref0, ref1, ref2, ref3;
52
53	0	ref0 = ref[0];
54	0	ref1 = ref[1];
55	0	ref2 = ref[2];
56	0	ref3 = ref[3];
57	0	sum_ref0 = _mm256_setzero_si256();
58	0	sum_ref2 = _mm256_setzero_si256();
59	0	sum_ref1 = _mm256_setzero_si256();
60	0	sum_ref3 = _mm256_setzero_si256();
61
62	0	for (i = 0; i < N; i++) {
63	0	for (j = 0; j < M; j += 32) {
64		// load src and all refs
65	0	src_reg = _mm256_loadu_si256((const __m256i *)(src + j));
66	0	ref0_reg = _mm256_loadu_si256((const __m256i *)(ref0 + j));
67	0	ref1_reg = _mm256_loadu_si256((const __m256i *)(ref1 + j));
68	0	ref2_reg = _mm256_loadu_si256((const __m256i *)(ref2 + j));
69	0	ref3_reg = _mm256_loadu_si256((const __m256i *)(ref3 + j));
70
71		// sum of the absolute differences between every ref-i to src
72	0	ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
73	0	ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
74	0	ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
75	0	ref3_reg = _mm256_sad_epu8(ref3_reg, src_reg);
76		// sum every ref-i
77	0	sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
78	0	sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
79	0	sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
80	0	sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);
81	0	}
82	0	src += src_stride;
83	0	ref0 += ref_stride;
84	0	ref1 += ref_stride;
85	0	ref2 += ref_stride;
86	0	ref3 += ref_stride;
87	0	}
88
89	0	aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &sum_ref3);
90	0	}
91
92		static AOM_FORCE_INLINE void aom_sadMxNx3d_avx2(
93		int M, int N, const uint8_t *src, int src_stride,
94	0	const uint8_t *const ref[4], int ref_stride, uint32_t res[4]) {
95	0	__m256i src_reg, ref0_reg, ref1_reg, ref2_reg;
96	0	__m256i sum_ref0, sum_ref1, sum_ref2;
97	0	int i, j;
98	0	const uint8_t ref0, ref1, *ref2;
99	0	const __m256i zero = _mm256_setzero_si256();
100
101	0	ref0 = ref[0];
102	0	ref1 = ref[1];
103	0	ref2 = ref[2];
104	0	sum_ref0 = _mm256_setzero_si256();
105	0	sum_ref2 = _mm256_setzero_si256();
106	0	sum_ref1 = _mm256_setzero_si256();
107
108	0	for (i = 0; i < N; i++) {
109	0	for (j = 0; j < M; j += 32) {
110		// load src and all refs
111	0	src_reg = _mm256_loadu_si256((const __m256i *)(src + j));
112	0	ref0_reg = _mm256_loadu_si256((const __m256i *)(ref0 + j));
113	0	ref1_reg = _mm256_loadu_si256((const __m256i *)(ref1 + j));
114	0	ref2_reg = _mm256_loadu_si256((const __m256i *)(ref2 + j));
115
116		// sum of the absolute differences between every ref-i to src
117	0	ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
118	0	ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
119	0	ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
120		// sum every ref-i
121	0	sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
122	0	sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
123	0	sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
124	0	}
125	0	src += src_stride;
126	0	ref0 += ref_stride;
127	0	ref1 += ref_stride;
128	0	ref2 += ref_stride;
129	0	}
130	0	aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &zero);
131	0	}
132
133		#define SADMXN_AVX2(m, n) \
134		void aom_sad##m##x##n##x4d_avx2(const uint8_t *src, int src_stride, \
135		const uint8_t *const ref[4], int ref_stride, \
136	0	uint32_t res[4]) { \
137	0	aom_sadMxNx4d_avx2(m, n, src, src_stride, ref, ref_stride, res); \
138	0	} \ Unexecuted instantiation: aom_sad32x16x4d_avx2 Unexecuted instantiation: aom_sad32x32x4d_avx2 Unexecuted instantiation: aom_sad32x64x4d_avx2 Unexecuted instantiation: aom_sad64x32x4d_avx2 Unexecuted instantiation: aom_sad64x64x4d_avx2 Unexecuted instantiation: aom_sad64x128x4d_avx2 Unexecuted instantiation: aom_sad128x64x4d_avx2 Unexecuted instantiation: aom_sad128x128x4d_avx2 Unexecuted instantiation: aom_sad32x8x4d_avx2 Unexecuted instantiation: aom_sad64x16x4d_avx2
139		void aom_sad##m##x##n##x3d_avx2(const uint8_t *src, int src_stride, \
140		const uint8_t *const ref[4], int ref_stride, \
141	0	uint32_t res[4]) { \
142	0	aom_sadMxNx3d_avx2(m, n, src, src_stride, ref, ref_stride, res); \
143	0	} Unexecuted instantiation: aom_sad32x16x3d_avx2 Unexecuted instantiation: aom_sad32x32x3d_avx2 Unexecuted instantiation: aom_sad32x64x3d_avx2 Unexecuted instantiation: aom_sad64x32x3d_avx2 Unexecuted instantiation: aom_sad64x64x3d_avx2 Unexecuted instantiation: aom_sad64x128x3d_avx2 Unexecuted instantiation: aom_sad128x64x3d_avx2 Unexecuted instantiation: aom_sad128x128x3d_avx2 Unexecuted instantiation: aom_sad32x8x3d_avx2 Unexecuted instantiation: aom_sad64x16x3d_avx2
144
145		SADMXN_AVX2(32, 16)
146		SADMXN_AVX2(32, 32)
147		SADMXN_AVX2(32, 64)
148
149		#if !CONFIG_HIGHWAY
150		SADMXN_AVX2(64, 32)
151		SADMXN_AVX2(64, 64)
152		SADMXN_AVX2(64, 128)
153
154		SADMXN_AVX2(128, 64)
155		SADMXN_AVX2(128, 128)
156		#endif
157
158		#if !CONFIG_REALTIME_ONLY
159		SADMXN_AVX2(32, 8)
160		SADMXN_AVX2(64, 16)
161		#endif // !CONFIG_REALTIME_ONLY
162
163		#define SAD_SKIP_MXN_AVX2(m, n) \
164		void aom_sad_skip_##m##x##n##x4d_avx2(const uint8_t *src, int src_stride, \
165		const uint8_t *const ref[4], \
166	0	int ref_stride, uint32_t res[4]) { \
167	0	aom_sadMxNx4d_avx2(m, ((n) >> 1), src, 2 * src_stride, ref, \
168	0	2 * ref_stride, res); \
169	0	res[0] <<= 1; \
170	0	res[1] <<= 1; \
171	0	res[2] <<= 1; \
172	0	res[3] <<= 1; \
173	0	} Unexecuted instantiation: aom_sad_skip_32x16x4d_avx2 Unexecuted instantiation: aom_sad_skip_32x32x4d_avx2 Unexecuted instantiation: aom_sad_skip_32x64x4d_avx2 Unexecuted instantiation: aom_sad_skip_64x32x4d_avx2 Unexecuted instantiation: aom_sad_skip_64x64x4d_avx2 Unexecuted instantiation: aom_sad_skip_64x128x4d_avx2 Unexecuted instantiation: aom_sad_skip_128x64x4d_avx2 Unexecuted instantiation: aom_sad_skip_128x128x4d_avx2 Unexecuted instantiation: aom_sad_skip_64x16x4d_avx2
174
175		SAD_SKIP_MXN_AVX2(32, 16)
176		SAD_SKIP_MXN_AVX2(32, 32)
177		SAD_SKIP_MXN_AVX2(32, 64)
178
179		#if !CONFIG_HIGHWAY
180		SAD_SKIP_MXN_AVX2(64, 32)
181		SAD_SKIP_MXN_AVX2(64, 64)
182		SAD_SKIP_MXN_AVX2(64, 128)
183
184		SAD_SKIP_MXN_AVX2(128, 64)
185		SAD_SKIP_MXN_AVX2(128, 128)
186		#endif
187
188		#if !CONFIG_REALTIME_ONLY
189		SAD_SKIP_MXN_AVX2(64, 16)
190		#endif // !CONFIG_REALTIME_ONLY
191
192		static AOM_FORCE_INLINE void aom_sad16xNx3d_avx2(int N, const uint8_t *src,
193		int src_stride,
194		const uint8_t *const ref[4],
195		int ref_stride,
196	0	uint32_t res[4]) {
197	0	__m256i src_reg, ref0_reg, ref1_reg, ref2_reg;
198	0	__m256i sum_ref0, sum_ref1, sum_ref2;
199	0	const uint8_t ref0, ref1, *ref2;
200	0	const __m256i zero = _mm256_setzero_si256();
201	0	assert(N % 2 == 0);
202
203	0	ref0 = ref[0];
204	0	ref1 = ref[1];
205	0	ref2 = ref[2];
206	0	sum_ref0 = _mm256_setzero_si256();
207	0	sum_ref2 = _mm256_setzero_si256();
208	0	sum_ref1 = _mm256_setzero_si256();
209
210	0	for (int i = 0; i < N; i += 2) {
211		// load src and all refs
212	0	src_reg = yy_loadu2_128(src + src_stride, src);
213	0	ref0_reg = yy_loadu2_128(ref0 + ref_stride, ref0);
214	0	ref1_reg = yy_loadu2_128(ref1 + ref_stride, ref1);
215	0	ref2_reg = yy_loadu2_128(ref2 + ref_stride, ref2);
216
217		// sum of the absolute differences between every ref-i to src
218	0	ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
219	0	ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
220	0	ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
221
222		// sum every ref-i
223	0	sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
224	0	sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
225	0	sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
226
227	0	src += 2 * src_stride;
228	0	ref0 += 2 * ref_stride;
229	0	ref1 += 2 * ref_stride;
230	0	ref2 += 2 * ref_stride;
231	0	}
232
233	0	aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &zero);
234	0	}
235
236		static AOM_FORCE_INLINE void aom_sad16xNx4d_avx2(int N, const uint8_t *src,
237		int src_stride,
238		const uint8_t *const ref[4],
239		int ref_stride,
240	0	uint32_t res[4]) {
241	0	__m256i src_reg, ref0_reg, ref1_reg, ref2_reg, ref3_reg;
242	0	__m256i sum_ref0, sum_ref1, sum_ref2, sum_ref3;
243	0	const uint8_t ref0, ref1, ref2, ref3;
244	0	assert(N % 2 == 0);
245
246	0	ref0 = ref[0];
247	0	ref1 = ref[1];
248	0	ref2 = ref[2];
249	0	ref3 = ref[3];
250
251	0	sum_ref0 = _mm256_setzero_si256();
252	0	sum_ref2 = _mm256_setzero_si256();
253	0	sum_ref1 = _mm256_setzero_si256();
254	0	sum_ref3 = _mm256_setzero_si256();
255
256	0	for (int i = 0; i < N; i += 2) {
257		// load src and all refs
258	0	src_reg = yy_loadu2_128(src + src_stride, src);
259	0	ref0_reg = yy_loadu2_128(ref0 + ref_stride, ref0);
260	0	ref1_reg = yy_loadu2_128(ref1 + ref_stride, ref1);
261	0	ref2_reg = yy_loadu2_128(ref2 + ref_stride, ref2);
262	0	ref3_reg = yy_loadu2_128(ref3 + ref_stride, ref3);
263
264		// sum of the absolute differences between every ref-i to src
265	0	ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
266	0	ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
267	0	ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
268	0	ref3_reg = _mm256_sad_epu8(ref3_reg, src_reg);
269
270		// sum every ref-i
271	0	sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
272	0	sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
273	0	sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
274	0	sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);
275
276	0	src += 2 * src_stride;
277	0	ref0 += 2 * ref_stride;
278	0	ref1 += 2 * ref_stride;
279	0	ref2 += 2 * ref_stride;
280	0	ref3 += 2 * ref_stride;
281	0	}
282
283	0	aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &sum_ref3);
284	0	}
285
286		#define SAD16XNX3_AVX2(n) \
287		void aom_sad16x##n##x3d_avx2(const uint8_t *src, int src_stride, \
288		const uint8_t *const ref[4], int ref_stride, \
289	0	uint32_t res[4]) { \
290	0	aom_sad16xNx3d_avx2(n, src, src_stride, ref, ref_stride, res); \
291	0	} Unexecuted instantiation: aom_sad16x32x3d_avx2 Unexecuted instantiation: aom_sad16x16x3d_avx2 Unexecuted instantiation: aom_sad16x8x3d_avx2 Unexecuted instantiation: aom_sad16x64x3d_avx2 Unexecuted instantiation: aom_sad16x4x3d_avx2
292		#define SAD16XNX4_AVX2(n) \
293		void aom_sad16x##n##x4d_avx2(const uint8_t *src, int src_stride, \
294		const uint8_t *const ref[4], int ref_stride, \
295	0	uint32_t res[4]) { \
296	0	aom_sad16xNx4d_avx2(n, src, src_stride, ref, ref_stride, res); \
297	0	} Unexecuted instantiation: aom_sad16x32x4d_avx2 Unexecuted instantiation: aom_sad16x16x4d_avx2 Unexecuted instantiation: aom_sad16x8x4d_avx2 Unexecuted instantiation: aom_sad16x64x4d_avx2 Unexecuted instantiation: aom_sad16x4x4d_avx2
298
299		SAD16XNX4_AVX2(32)
300		SAD16XNX4_AVX2(16)
301		SAD16XNX4_AVX2(8)
302
303		SAD16XNX3_AVX2(32)
304		SAD16XNX3_AVX2(16)
305		SAD16XNX3_AVX2(8)
306
307		#if !CONFIG_REALTIME_ONLY
308		SAD16XNX3_AVX2(64)
309		SAD16XNX3_AVX2(4)
310
311		SAD16XNX4_AVX2(64)
312		SAD16XNX4_AVX2(4)
313
314		#endif // !CONFIG_REALTIME_ONLY
315
316		#define SAD_SKIP_16XN_AVX2(n) \
317		void aom_sad_skip_16x##n##x4d_avx2(const uint8_t *src, int src_stride, \
318		const uint8_t *const ref[4], \
319	0	int ref_stride, uint32_t res[4]) { \
320	0	aom_sad16xNx4d_avx2(((n) >> 1), src, 2 * src_stride, ref, 2 * ref_stride, \
321	0	res); \
322	0	res[0] <<= 1; \
323	0	res[1] <<= 1; \
324	0	res[2] <<= 1; \
325	0	res[3] <<= 1; \
326	0	} Unexecuted instantiation: aom_sad_skip_16x32x4d_avx2 Unexecuted instantiation: aom_sad_skip_16x16x4d_avx2 Unexecuted instantiation: aom_sad_skip_16x64x4d_avx2
327
328		SAD_SKIP_16XN_AVX2(32)
329		SAD_SKIP_16XN_AVX2(16)
330
331		#if !CONFIG_REALTIME_ONLY
332		SAD_SKIP_16XN_AVX2(64)
333		#endif // !CONFIG_REALTIME_ONLY