Coverage Report

Created: 2026-09-07 06:44

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/aom/av1/encoder/x86/wedge_utils_avx2.c
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Source
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/*
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 * Copyright (c) 2018, Alliance for Open Media. All rights reserved.
3
 *
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 * This source code is subject to the terms of the BSD 2 Clause License and
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 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
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 * was not distributed with this source code in the LICENSE file, you can
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 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
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 * Media Patent License 1.0 was not distributed with this source code in the
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 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
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 */
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12
#include <assert.h>
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#include <immintrin.h>
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#include <smmintrin.h>
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#include "aom_dsp/x86/synonyms.h"
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#include "aom_dsp/x86/synonyms_avx2.h"
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#include "aom/aom_integer.h"
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#include "av1/common/reconinter.h"
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22
0
#define MAX_MASK_VALUE (1 << WEDGE_WEIGHT_BITS)
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/**
25
 * See av1_wedge_sse_from_residuals_c
26
 */
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uint64_t av1_wedge_sse_from_residuals_avx2(const int16_t *r1, const int16_t *d,
28
0
                                           const uint8_t *m, int N) {
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0
  int n = -N;
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31
0
  uint64_t csse;
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33
0
  const __m256i v_mask_max_w = _mm256_set1_epi16(MAX_MASK_VALUE);
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0
  const __m256i v_zext_q = _mm256_set1_epi64x(~0u);
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36
0
  __m256i v_acc0_q = _mm256_setzero_si256();
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38
0
  assert(N % 64 == 0);
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40
0
  r1 += N;
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0
  d += N;
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0
  m += N;
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44
0
  do {
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0
    const __m256i v_r0_w = _mm256_lddqu_si256((__m256i *)(r1 + n));
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0
    const __m256i v_d0_w = _mm256_lddqu_si256((__m256i *)(d + n));
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0
    const __m128i v_m01_b = _mm_lddqu_si128((__m128i *)(m + n));
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0
    const __m256i v_rd0l_w = _mm256_unpacklo_epi16(v_d0_w, v_r0_w);
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0
    const __m256i v_rd0h_w = _mm256_unpackhi_epi16(v_d0_w, v_r0_w);
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0
    const __m256i v_m0_w = _mm256_cvtepu8_epi16(v_m01_b);
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0
    const __m256i v_m0l_w = _mm256_unpacklo_epi16(v_m0_w, v_mask_max_w);
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0
    const __m256i v_m0h_w = _mm256_unpackhi_epi16(v_m0_w, v_mask_max_w);
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0
    const __m256i v_t0l_d = _mm256_madd_epi16(v_rd0l_w, v_m0l_w);
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0
    const __m256i v_t0h_d = _mm256_madd_epi16(v_rd0h_w, v_m0h_w);
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0
    const __m256i v_t0_w = _mm256_packs_epi32(v_t0l_d, v_t0h_d);
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0
    const __m256i v_sq0_d = _mm256_madd_epi16(v_t0_w, v_t0_w);
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0
    const __m256i v_sum0_q = _mm256_add_epi64(
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0
        _mm256_and_si256(v_sq0_d, v_zext_q), _mm256_srli_epi64(v_sq0_d, 32));
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66
0
    v_acc0_q = _mm256_add_epi64(v_acc0_q, v_sum0_q);
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0
    n += 16;
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0
  } while (n);
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0
  v_acc0_q = _mm256_add_epi64(v_acc0_q, _mm256_srli_si256(v_acc0_q, 8));
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0
  __m128i v_acc_q_0 = _mm256_castsi256_si128(v_acc0_q);
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0
  __m128i v_acc_q_1 = _mm256_extracti128_si256(v_acc0_q, 1);
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0
  v_acc_q_0 = _mm_add_epi64(v_acc_q_0, v_acc_q_1);
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0
#if AOM_ARCH_X86_64
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0
  csse = (uint64_t)_mm_extract_epi64(v_acc_q_0, 0);
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#else
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  xx_storel_64(&csse, v_acc_q_0);
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#endif
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0
  return ROUND_POWER_OF_TWO(csse, 2 * WEDGE_WEIGHT_BITS);
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0
}
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/**
85
 * See av1_wedge_sign_from_residuals_c
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 */
87
int8_t av1_wedge_sign_from_residuals_avx2(const int16_t *ds, const uint8_t *m,
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0
                                          int N, int64_t limit) {
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0
  int64_t acc;
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0
  __m256i v_acc0_d = _mm256_setzero_si256();
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92
  // Input size limited to 8192 by the use of 32 bit accumulators and m
93
  // being between [0, 64]. Overflow might happen at larger sizes,
94
  // though it is practically impossible on real video input.
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0
  assert(N < 8192);
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0
  assert(N % 64 == 0);
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98
0
  do {
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0
    const __m256i v_m01_b = _mm256_lddqu_si256((__m256i *)(m));
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0
    const __m256i v_m23_b = _mm256_lddqu_si256((__m256i *)(m + 32));
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0
    const __m256i v_d0_w = _mm256_lddqu_si256((__m256i *)(ds));
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0
    const __m256i v_d1_w = _mm256_lddqu_si256((__m256i *)(ds + 16));
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0
    const __m256i v_d2_w = _mm256_lddqu_si256((__m256i *)(ds + 32));
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0
    const __m256i v_d3_w = _mm256_lddqu_si256((__m256i *)(ds + 48));
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107
0
    const __m256i v_m0_w =
108
0
        _mm256_cvtepu8_epi16(_mm256_castsi256_si128(v_m01_b));
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0
    const __m256i v_m1_w =
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0
        _mm256_cvtepu8_epi16(_mm256_extracti128_si256(v_m01_b, 1));
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0
    const __m256i v_m2_w =
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0
        _mm256_cvtepu8_epi16(_mm256_castsi256_si128(v_m23_b));
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0
    const __m256i v_m3_w =
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0
        _mm256_cvtepu8_epi16(_mm256_extracti128_si256(v_m23_b, 1));
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116
0
    const __m256i v_p0_d = _mm256_madd_epi16(v_d0_w, v_m0_w);
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0
    const __m256i v_p1_d = _mm256_madd_epi16(v_d1_w, v_m1_w);
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0
    const __m256i v_p2_d = _mm256_madd_epi16(v_d2_w, v_m2_w);
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0
    const __m256i v_p3_d = _mm256_madd_epi16(v_d3_w, v_m3_w);
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0
    const __m256i v_p01_d = _mm256_add_epi32(v_p0_d, v_p1_d);
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0
    const __m256i v_p23_d = _mm256_add_epi32(v_p2_d, v_p3_d);
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124
0
    const __m256i v_p0123_d = _mm256_add_epi32(v_p01_d, v_p23_d);
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0
    v_acc0_d = _mm256_add_epi32(v_acc0_d, v_p0123_d);
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128
0
    ds += 64;
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0
    m += 64;
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131
0
    N -= 64;
132
0
  } while (N);
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134
0
  __m256i v_sign_d = _mm256_srai_epi32(v_acc0_d, 31);
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0
  v_acc0_d = _mm256_add_epi64(_mm256_unpacklo_epi32(v_acc0_d, v_sign_d),
136
0
                              _mm256_unpackhi_epi32(v_acc0_d, v_sign_d));
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138
0
  __m256i v_acc_q = _mm256_add_epi64(v_acc0_d, _mm256_srli_si256(v_acc0_d, 8));
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140
0
  __m128i v_acc_q_0 = _mm256_castsi256_si128(v_acc_q);
141
0
  __m128i v_acc_q_1 = _mm256_extracti128_si256(v_acc_q, 1);
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0
  v_acc_q_0 = _mm_add_epi64(v_acc_q_0, v_acc_q_1);
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144
0
#if AOM_ARCH_X86_64
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0
  acc = _mm_extract_epi64(v_acc_q_0, 0);
146
#else
147
  xx_storel_64(&acc, v_acc_q_0);
148
#endif
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150
0
  return acc > limit;
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0
}
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153
/**
154
 * av1_wedge_compute_delta_squares_c
155
 */
156
void av1_wedge_compute_delta_squares_avx2(int16_t *d, const int16_t *a,
157
0
                                          const int16_t *b, int N) {
158
0
  const __m256i v_neg_w = _mm256_set1_epi32((int)0xffff0001);
159
160
0
  assert(N % 64 == 0);
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162
0
  do {
163
0
    const __m256i v_a0_w = _mm256_lddqu_si256((__m256i *)(a));
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0
    const __m256i v_b0_w = _mm256_lddqu_si256((__m256i *)(b));
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0
    const __m256i v_a1_w = _mm256_lddqu_si256((__m256i *)(a + 16));
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0
    const __m256i v_b1_w = _mm256_lddqu_si256((__m256i *)(b + 16));
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0
    const __m256i v_a2_w = _mm256_lddqu_si256((__m256i *)(a + 32));
168
0
    const __m256i v_b2_w = _mm256_lddqu_si256((__m256i *)(b + 32));
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0
    const __m256i v_a3_w = _mm256_lddqu_si256((__m256i *)(a + 48));
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0
    const __m256i v_b3_w = _mm256_lddqu_si256((__m256i *)(b + 48));
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172
0
    const __m256i v_ab0l_w = _mm256_unpacklo_epi16(v_a0_w, v_b0_w);
173
0
    const __m256i v_ab0h_w = _mm256_unpackhi_epi16(v_a0_w, v_b0_w);
174
0
    const __m256i v_ab1l_w = _mm256_unpacklo_epi16(v_a1_w, v_b1_w);
175
0
    const __m256i v_ab1h_w = _mm256_unpackhi_epi16(v_a1_w, v_b1_w);
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0
    const __m256i v_ab2l_w = _mm256_unpacklo_epi16(v_a2_w, v_b2_w);
177
0
    const __m256i v_ab2h_w = _mm256_unpackhi_epi16(v_a2_w, v_b2_w);
178
0
    const __m256i v_ab3l_w = _mm256_unpacklo_epi16(v_a3_w, v_b3_w);
179
0
    const __m256i v_ab3h_w = _mm256_unpackhi_epi16(v_a3_w, v_b3_w);
180
181
    // Negate top word of pairs
182
0
    const __m256i v_abl0n_w = _mm256_sign_epi16(v_ab0l_w, v_neg_w);
183
0
    const __m256i v_abh0n_w = _mm256_sign_epi16(v_ab0h_w, v_neg_w);
184
0
    const __m256i v_abl1n_w = _mm256_sign_epi16(v_ab1l_w, v_neg_w);
185
0
    const __m256i v_abh1n_w = _mm256_sign_epi16(v_ab1h_w, v_neg_w);
186
0
    const __m256i v_abl2n_w = _mm256_sign_epi16(v_ab2l_w, v_neg_w);
187
0
    const __m256i v_abh2n_w = _mm256_sign_epi16(v_ab2h_w, v_neg_w);
188
0
    const __m256i v_abl3n_w = _mm256_sign_epi16(v_ab3l_w, v_neg_w);
189
0
    const __m256i v_abh3n_w = _mm256_sign_epi16(v_ab3h_w, v_neg_w);
190
191
0
    const __m256i v_r0l_w = _mm256_madd_epi16(v_ab0l_w, v_abl0n_w);
192
0
    const __m256i v_r0h_w = _mm256_madd_epi16(v_ab0h_w, v_abh0n_w);
193
0
    const __m256i v_r1l_w = _mm256_madd_epi16(v_ab1l_w, v_abl1n_w);
194
0
    const __m256i v_r1h_w = _mm256_madd_epi16(v_ab1h_w, v_abh1n_w);
195
0
    const __m256i v_r2l_w = _mm256_madd_epi16(v_ab2l_w, v_abl2n_w);
196
0
    const __m256i v_r2h_w = _mm256_madd_epi16(v_ab2h_w, v_abh2n_w);
197
0
    const __m256i v_r3l_w = _mm256_madd_epi16(v_ab3l_w, v_abl3n_w);
198
0
    const __m256i v_r3h_w = _mm256_madd_epi16(v_ab3h_w, v_abh3n_w);
199
200
0
    const __m256i v_r0_w = _mm256_packs_epi32(v_r0l_w, v_r0h_w);
201
0
    const __m256i v_r1_w = _mm256_packs_epi32(v_r1l_w, v_r1h_w);
202
0
    const __m256i v_r2_w = _mm256_packs_epi32(v_r2l_w, v_r2h_w);
203
0
    const __m256i v_r3_w = _mm256_packs_epi32(v_r3l_w, v_r3h_w);
204
205
0
    _mm256_store_si256((__m256i *)(d), v_r0_w);
206
0
    _mm256_store_si256((__m256i *)(d + 16), v_r1_w);
207
0
    _mm256_store_si256((__m256i *)(d + 32), v_r2_w);
208
0
    _mm256_store_si256((__m256i *)(d + 48), v_r3_w);
209
210
0
    a += 64;
211
0
    b += 64;
212
0
    d += 64;
213
0
    N -= 64;
214
0
  } while (N);
215
0
}