/src/aom/aom_dsp/x86/sad4d_avx2.c

Source
/*
 * Copyright (c) 2016, Alliance for Open Media. All rights reserved.
 *
 * This source code is subject to the terms of the BSD 2 Clause License and
 * the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
 * was not distributed with this source code in the LICENSE file, you can
 * obtain it at www.aomedia.org/license/software. If the Alliance for Open
 * Media Patent License 1.0 was not distributed with this source code in the
 * PATENTS file, you can obtain it at www.aomedia.org/license/patent.
 */
#include <immintrin.h>  // AVX2

#include "config/aom_dsp_rtcd.h"

#include "aom/aom_integer.h"
#include "aom_dsp/x86/synonyms_avx2.h"

static AOM_FORCE_INLINE void aggregate_and_store_sum(uint32_t res[4],
                                                     const __m256i *sum_ref0,
                                                     const __m256i *sum_ref1,
                                                     const __m256i *sum_ref2,
                                                     const __m256i *sum_ref3) {
  // In sum_ref-i the result is saved in the first 4 bytes and the other 4
  // bytes are zeroed.
  // merge sum_ref0 and sum_ref1 also sum_ref2 and sum_ref3
  // 0, 0, 1, 1
  __m256i sum_ref01 = _mm256_castps_si256(_mm256_shuffle_ps(
      _mm256_castsi256_ps(*sum_ref0), _mm256_castsi256_ps(*sum_ref1),
      _MM_SHUFFLE(2, 0, 2, 0)));
  // 2, 2, 3, 3
  __m256i sum_ref23 = _mm256_castps_si256(_mm256_shuffle_ps(
      _mm256_castsi256_ps(*sum_ref2), _mm256_castsi256_ps(*sum_ref3),
      _MM_SHUFFLE(2, 0, 2, 0)));

  // sum adjacent 32 bit integers
  __m256i sum_ref0123 = _mm256_hadd_epi32(sum_ref01, sum_ref23);

  // add the low 128 bit to the high 128 bit
  __m128i sum = _mm_add_epi32(_mm256_castsi256_si128(sum_ref0123),
                              _mm256_extractf128_si256(sum_ref0123, 1));

  _mm_storeu_si128((__m128i *)(res), sum);
}

static AOM_FORCE_INLINE void aom_sadMxNx4d_avx2(
    int M, int N, const uint8_t *src, int src_stride,
    const uint8_t *const ref[4], int ref_stride, uint32_t res[4]) {
  __m256i src_reg, ref0_reg, ref1_reg, ref2_reg, ref3_reg;
  __m256i sum_ref0, sum_ref1, sum_ref2, sum_ref3;
  int i, j;
  const uint8_t *ref0, *ref1, *ref2, *ref3;

  ref0 = ref[0];
  ref1 = ref[1];
  ref2 = ref[2];
  ref3 = ref[3];

  src_reg = _mm256_loadu_si256((const __m256i *)src);
  sum_ref0 =
      _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)ref0), src_reg);
  sum_ref1 =
      _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)ref1), src_reg);
  sum_ref2 =
      _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)ref2), src_reg);
  sum_ref3 =
      _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)ref3), src_reg);
  for (j = 32; j < M; j += 32) {
    src_reg = _mm256_loadu_si256((const __m256i *)(src + j));
    ref0_reg = _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)(ref0 + j)),
                               src_reg);
    ref1_reg = _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)(ref1 + j)),
                               src_reg);
    ref2_reg = _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)(ref2 + j)),
                               src_reg);
    ref3_reg = _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)(ref3 + j)),
                               src_reg);
    sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
    sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
    sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
    sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);
  }
  src += src_stride;
  ref0 += ref_stride;
  ref1 += ref_stride;
  ref2 += ref_stride;
  ref3 += ref_stride;

#if defined(__GNUC__) && !defined(__clang__)
#pragma GCC unroll 2
#endif
  for (i = 1; i < N; i++) {
    for (j = 0; j < M; j += 32) {
      // load src and all refs
      src_reg = _mm256_loadu_si256((const __m256i *)(src + j));
      ref0_reg = _mm256_loadu_si256((const __m256i *)(ref0 + j));
      ref1_reg = _mm256_loadu_si256((const __m256i *)(ref1 + j));
      ref2_reg = _mm256_loadu_si256((const __m256i *)(ref2 + j));
      ref3_reg = _mm256_loadu_si256((const __m256i *)(ref3 + j));

      // sum of the absolute differences between every ref-i to src
      ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
      ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
      ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
      ref3_reg = _mm256_sad_epu8(ref3_reg, src_reg);
      // sum every ref-i
      sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
      sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
      sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
      sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);
    }
    src += src_stride;
    ref0 += ref_stride;
    ref1 += ref_stride;
    ref2 += ref_stride;
    ref3 += ref_stride;
  }

  aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &sum_ref3);
}

static AOM_FORCE_INLINE void aom_sadMxNx3d_avx2(
    int M, int N, const uint8_t *src, int src_stride,
    const uint8_t *const ref[4], int ref_stride, uint32_t res[4]) {
  __m256i src_reg, ref0_reg, ref1_reg, ref2_reg;
  __m256i sum_ref0, sum_ref1, sum_ref2;
  int i, j;
  const uint8_t *ref0, *ref1, *ref2;
  const __m256i zero = _mm256_setzero_si256();

  ref0 = ref[0];
  ref1 = ref[1];
  ref2 = ref[2];
  sum_ref0 = _mm256_setzero_si256();
  sum_ref2 = _mm256_setzero_si256();
  sum_ref1 = _mm256_setzero_si256();

  for (i = 0; i < N; i++) {
    for (j = 0; j < M; j += 32) {
      // load src and all refs
      src_reg = _mm256_loadu_si256((const __m256i *)(src + j));
      ref0_reg = _mm256_loadu_si256((const __m256i *)(ref0 + j));
      ref1_reg = _mm256_loadu_si256((const __m256i *)(ref1 + j));
      ref2_reg = _mm256_loadu_si256((const __m256i *)(ref2 + j));

      // sum of the absolute differences between every ref-i to src
      ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
      ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
      ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
      // sum every ref-i
      sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
      sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
      sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
    }
    src += src_stride;
    ref0 += ref_stride;
    ref1 += ref_stride;
    ref2 += ref_stride;
  }
  aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &zero);
}

#define SADMXN_AVX2(m, n)                                                      \
  void aom_sad##m##x##n##x4d_avx2(const uint8_t *src, int src_stride,          \
                                  const uint8_t *const ref[4], int ref_stride, \
                                  uint32_t res[4]) {                           \
    aom_sadMxNx4d_avx2(m, n, src, src_stride, ref, ref_stride, res);           \
  }                                                                            \
  void aom_sad##m##x##n##x3d_avx2(const uint8_t *src, int src_stride,          \
                                  const uint8_t *const ref[4], int ref_stride, \
                                  uint32_t res[4]) {                           \
    aom_sadMxNx3d_avx2(m, n, src, src_stride, ref, ref_stride, res);           \
  }

SADMXN_AVX2(32, 16)
SADMXN_AVX2(32, 32)
SADMXN_AVX2(32, 64)

#if !CONFIG_HIGHWAY
SADMXN_AVX2(64, 32)
SADMXN_AVX2(64, 64)
SADMXN_AVX2(64, 128)

SADMXN_AVX2(128, 64)
SADMXN_AVX2(128, 128)
#endif

#if !CONFIG_REALTIME_ONLY
SADMXN_AVX2(32, 8)
SADMXN_AVX2(64, 16)
#endif  // !CONFIG_REALTIME_ONLY

#define SAD_SKIP_MXN_AVX2(m, n)                                             \
  void aom_sad_skip_##m##x##n##x4d_avx2(const uint8_t *src, int src_stride, \
                                        const uint8_t *const ref[4],        \
                                        int ref_stride, uint32_t res[4]) {  \
    aom_sadMxNx4d_avx2(m, ((n) >> 1), src, 2 * src_stride, ref,             \
                       2 * ref_stride, res);                                \
    res[0] <<= 1;                                                           \
    res[1] <<= 1;                                                           \
    res[2] <<= 1;                                                           \
    res[3] <<= 1;                                                           \
  }

SAD_SKIP_MXN_AVX2(32, 16)
SAD_SKIP_MXN_AVX2(32, 32)
SAD_SKIP_MXN_AVX2(32, 64)

#if !CONFIG_HIGHWAY
SAD_SKIP_MXN_AVX2(64, 32)
SAD_SKIP_MXN_AVX2(64, 64)
SAD_SKIP_MXN_AVX2(64, 128)

SAD_SKIP_MXN_AVX2(128, 64)
SAD_SKIP_MXN_AVX2(128, 128)
#endif

#if !CONFIG_REALTIME_ONLY
SAD_SKIP_MXN_AVX2(64, 16)
#endif  // !CONFIG_REALTIME_ONLY

static AOM_FORCE_INLINE void aom_sad16xNx3d_avx2(int N, const uint8_t *src,
                                                 int src_stride,
                                                 const uint8_t *const ref[4],
                                                 int ref_stride,
                                                 uint32_t res[4]) {
  __m256i src_reg, ref0_reg, ref1_reg, ref2_reg;
  __m256i sum_ref0, sum_ref1, sum_ref2;
  const uint8_t *ref0, *ref1, *ref2;
  const __m256i zero = _mm256_setzero_si256();
  assert(N % 2 == 0);

  ref0 = ref[0];
  ref1 = ref[1];
  ref2 = ref[2];

  src_reg = yy_loadu2_128(src + src_stride, src);
  sum_ref0 = _mm256_sad_epu8(yy_loadu2_128(ref0 + ref_stride, ref0), src_reg);
  sum_ref1 = _mm256_sad_epu8(yy_loadu2_128(ref1 + ref_stride, ref1), src_reg);
  sum_ref2 = _mm256_sad_epu8(yy_loadu2_128(ref2 + ref_stride, ref2), src_reg);
  src += 2 * src_stride;
  ref0 += 2 * ref_stride;
  ref1 += 2 * ref_stride;
  ref2 += 2 * ref_stride;

#if defined(__GNUC__) && !defined(__clang__)
#pragma GCC unroll 2
#endif
  for (int i = 2; i < N; i += 2) {
    // load src and all refs
    src_reg = yy_loadu2_128(src + src_stride, src);
    ref0_reg = yy_loadu2_128(ref0 + ref_stride, ref0);
    ref1_reg = yy_loadu2_128(ref1 + ref_stride, ref1);
    ref2_reg = yy_loadu2_128(ref2 + ref_stride, ref2);

    // sum of the absolute differences between every ref-i to src
    ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
    ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
    ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);

    // sum every ref-i
    sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
    sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
    sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);

    src += 2 * src_stride;
    ref0 += 2 * ref_stride;
    ref1 += 2 * ref_stride;
    ref2 += 2 * ref_stride;
  }

  aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &zero);
}

static AOM_FORCE_INLINE void aom_sad16xNx4d_avx2(int N, const uint8_t *src,
                                                 int src_stride,
                                                 const uint8_t *const ref[4],
                                                 int ref_stride,
                                                 uint32_t res[4]) {
  __m256i src_reg, ref0_reg, ref1_reg, ref2_reg, ref3_reg;
  __m256i sum_ref0, sum_ref1, sum_ref2, sum_ref3;
  const uint8_t *ref0, *ref1, *ref2, *ref3;
  assert(N % 2 == 0);

  ref0 = ref[0];
  ref1 = ref[1];
  ref2 = ref[2];
  ref3 = ref[3];

  src_reg = yy_loadu2_128(src + src_stride, src);
  sum_ref0 = _mm256_sad_epu8(yy_loadu2_128(ref0 + ref_stride, ref0), src_reg);
  sum_ref1 = _mm256_sad_epu8(yy_loadu2_128(ref1 + ref_stride, ref1), src_reg);
  sum_ref2 = _mm256_sad_epu8(yy_loadu2_128(ref2 + ref_stride, ref2), src_reg);
  sum_ref3 = _mm256_sad_epu8(yy_loadu2_128(ref3 + ref_stride, ref3), src_reg);
  src += 2 * src_stride;
  ref0 += 2 * ref_stride;
  ref1 += 2 * ref_stride;
  ref2 += 2 * ref_stride;
  ref3 += 2 * ref_stride;
#if defined(__GNUC__) && !defined(__clang__)
  __asm__(""
          : "+r"(src), "+r"(ref0), "+r"(ref1), "+r"(ref2), "+r"(ref3),
            "+x"(sum_ref0), "+x"(sum_ref1), "+x"(sum_ref2), "+x"(sum_ref3));
#pragma GCC unroll 2
#endif
  for (int i = 2; i < N; i += 2) {
    // load src and all refs
    src_reg = yy_loadu2_128(src + src_stride, src);
    ref0_reg = yy_loadu2_128(ref0 + ref_stride, ref0);
    ref1_reg = yy_loadu2_128(ref1 + ref_stride, ref1);
    ref2_reg = yy_loadu2_128(ref2 + ref_stride, ref2);
    ref3_reg = yy_loadu2_128(ref3 + ref_stride, ref3);

    // sum of the absolute differences between every ref-i to src
    ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
    ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
    ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
    ref3_reg = _mm256_sad_epu8(ref3_reg, src_reg);

    // sum every ref-i
    sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
    sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
    sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
    sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);

    src += 2 * src_stride;
    ref0 += 2 * ref_stride;
    ref1 += 2 * ref_stride;
    ref2 += 2 * ref_stride;
    ref3 += 2 * ref_stride;
#if defined(__GNUC__) && !defined(__clang__)
    __asm__(""
            : "+r"(src), "+r"(ref0), "+r"(ref1), "+r"(ref2), "+r"(ref3),
              "+x"(sum_ref0), "+x"(sum_ref1), "+x"(sum_ref2), "+x"(sum_ref3));
#endif
  }

  aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &sum_ref3);
}

#define SAD16XNX3_AVX2(n)                                                   \
  void aom_sad16x##n##x3d_avx2(const uint8_t *src, int src_stride,          \
                               const uint8_t *const ref[4], int ref_stride, \
                               uint32_t res[4]) {                           \
    aom_sad16xNx3d_avx2(n, src, src_stride, ref, ref_stride, res);          \
  }
#define SAD16XNX4_AVX2(n)                                                   \
  void aom_sad16x##n##x4d_avx2(const uint8_t *src, int src_stride,          \
                               const uint8_t *const ref[4], int ref_stride, \
                               uint32_t res[4]) {                           \
    aom_sad16xNx4d_avx2(n, src, src_stride, ref, ref_stride, res);          \
  }

SAD16XNX4_AVX2(32)
SAD16XNX4_AVX2(16)
SAD16XNX4_AVX2(8)

SAD16XNX3_AVX2(32)
SAD16XNX3_AVX2(16)
SAD16XNX3_AVX2(8)

#if !CONFIG_REALTIME_ONLY
SAD16XNX3_AVX2(64)
SAD16XNX3_AVX2(4)

SAD16XNX4_AVX2(64)
SAD16XNX4_AVX2(4)

#endif  // !CONFIG_REALTIME_ONLY

#define SAD_SKIP_16XN_AVX2(n)                                                 \
  void aom_sad_skip_16x##n##x4d_avx2(const uint8_t *src, int src_stride,      \
                                     const uint8_t *const ref[4],             \
                                     int ref_stride, uint32_t res[4]) {       \
    aom_sad16xNx4d_avx2(((n) >> 1), src, 2 * src_stride, ref, 2 * ref_stride, \
                        res);                                                 \
    res[0] <<= 1;                                                             \
    res[1] <<= 1;                                                             \
    res[2] <<= 1;                                                             \
    res[3] <<= 1;                                                             \
  }

SAD_SKIP_16XN_AVX2(32)
SAD_SKIP_16XN_AVX2(16)

#if !CONFIG_REALTIME_ONLY
SAD_SKIP_16XN_AVX2(64)
#endif  // !CONFIG_REALTIME_ONLY

Coverage Report

Created: 2026-11-12 08:20

Line	Count	Source
1		/*
2		* Copyright (c) 2016, Alliance for Open Media. All rights reserved.
3		*
4		* This source code is subject to the terms of the BSD 2 Clause License and
5		* the Alliance for Open Media Patent License 1.0. If the BSD 2 Clause License
6		* was not distributed with this source code in the LICENSE file, you can
7		* obtain it at www.aomedia.org/license/software. If the Alliance for Open
8		* Media Patent License 1.0 was not distributed with this source code in the
9		* PATENTS file, you can obtain it at www.aomedia.org/license/patent.
10		*/
11		#include <immintrin.h> // AVX2
12
13		#include "config/aom_dsp_rtcd.h"
14
15		#include "aom/aom_integer.h"
16		#include "aom_dsp/x86/synonyms_avx2.h"
17
18		static AOM_FORCE_INLINE void aggregate_and_store_sum(uint32_t res[4],
19		const __m256i *sum_ref0,
20		const __m256i *sum_ref1,
21		const __m256i *sum_ref2,
22	0	const __m256i *sum_ref3) {
23		// In sum_ref-i the result is saved in the first 4 bytes and the other 4
24		// bytes are zeroed.
25		// merge sum_ref0 and sum_ref1 also sum_ref2 and sum_ref3
26		// 0, 0, 1, 1
27	0	__m256i sum_ref01 = _mm256_castps_si256(_mm256_shuffle_ps(
28	0	_mm256_castsi256_ps(sum_ref0), _mm256_castsi256_ps(sum_ref1),
29	0	_MM_SHUFFLE(2, 0, 2, 0)));
30		// 2, 2, 3, 3
31	0	__m256i sum_ref23 = _mm256_castps_si256(_mm256_shuffle_ps(
32	0	_mm256_castsi256_ps(sum_ref2), _mm256_castsi256_ps(sum_ref3),
33	0	_MM_SHUFFLE(2, 0, 2, 0)));
34
35		// sum adjacent 32 bit integers
36	0	__m256i sum_ref0123 = _mm256_hadd_epi32(sum_ref01, sum_ref23);
37
38		// add the low 128 bit to the high 128 bit
39	0	__m128i sum = _mm_add_epi32(_mm256_castsi256_si128(sum_ref0123),
40	0	_mm256_extractf128_si256(sum_ref0123, 1));
41
42	0	_mm_storeu_si128((__m128i *)(res), sum);
43	0	}
44
45		static AOM_FORCE_INLINE void aom_sadMxNx4d_avx2(
46		int M, int N, const uint8_t *src, int src_stride,
47	0	const uint8_t *const ref[4], int ref_stride, uint32_t res[4]) {
48	0	__m256i src_reg, ref0_reg, ref1_reg, ref2_reg, ref3_reg;
49	0	__m256i sum_ref0, sum_ref1, sum_ref2, sum_ref3;
50	0	int i, j;
51	0	const uint8_t ref0, ref1, ref2, ref3;
52
53	0	ref0 = ref[0];
54	0	ref1 = ref[1];
55	0	ref2 = ref[2];
56	0	ref3 = ref[3];
57
58	0	src_reg = _mm256_loadu_si256((const __m256i *)src);
59	0	sum_ref0 =
60	0	_mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)ref0), src_reg);
61	0	sum_ref1 =
62	0	_mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)ref1), src_reg);
63	0	sum_ref2 =
64	0	_mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)ref2), src_reg);
65	0	sum_ref3 =
66	0	_mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)ref3), src_reg);
67	0	for (j = 32; j < M; j += 32) {
68	0	src_reg = _mm256_loadu_si256((const __m256i *)(src + j));
69	0	ref0_reg = _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)(ref0 + j)),
70	0	src_reg);
71	0	ref1_reg = _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)(ref1 + j)),
72	0	src_reg);
73	0	ref2_reg = _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)(ref2 + j)),
74	0	src_reg);
75	0	ref3_reg = _mm256_sad_epu8(_mm256_loadu_si256((const __m256i *)(ref3 + j)),
76	0	src_reg);
77	0	sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
78	0	sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
79	0	sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
80	0	sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);
81	0	}
82	0	src += src_stride;
83	0	ref0 += ref_stride;
84	0	ref1 += ref_stride;
85	0	ref2 += ref_stride;
86	0	ref3 += ref_stride;
87
88		#if defined(__GNUC__) && !defined(__clang__)
89		#pragma GCC unroll 2
90		#endif
91	0	for (i = 1; i < N; i++) {
92	0	for (j = 0; j < M; j += 32) {
93		// load src and all refs
94	0	src_reg = _mm256_loadu_si256((const __m256i *)(src + j));
95	0	ref0_reg = _mm256_loadu_si256((const __m256i *)(ref0 + j));
96	0	ref1_reg = _mm256_loadu_si256((const __m256i *)(ref1 + j));
97	0	ref2_reg = _mm256_loadu_si256((const __m256i *)(ref2 + j));
98	0	ref3_reg = _mm256_loadu_si256((const __m256i *)(ref3 + j));
99
100		// sum of the absolute differences between every ref-i to src
101	0	ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
102	0	ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
103	0	ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
104	0	ref3_reg = _mm256_sad_epu8(ref3_reg, src_reg);
105		// sum every ref-i
106	0	sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
107	0	sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
108	0	sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
109	0	sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);
110	0	}
111	0	src += src_stride;
112	0	ref0 += ref_stride;
113	0	ref1 += ref_stride;
114	0	ref2 += ref_stride;
115	0	ref3 += ref_stride;
116	0	}
117
118	0	aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &sum_ref3);
119	0	}
120
121		static AOM_FORCE_INLINE void aom_sadMxNx3d_avx2(
122		int M, int N, const uint8_t *src, int src_stride,
123	0	const uint8_t *const ref[4], int ref_stride, uint32_t res[4]) {
124	0	__m256i src_reg, ref0_reg, ref1_reg, ref2_reg;
125	0	__m256i sum_ref0, sum_ref1, sum_ref2;
126	0	int i, j;
127	0	const uint8_t ref0, ref1, *ref2;
128	0	const __m256i zero = _mm256_setzero_si256();
129
130	0	ref0 = ref[0];
131	0	ref1 = ref[1];
132	0	ref2 = ref[2];
133	0	sum_ref0 = _mm256_setzero_si256();
134	0	sum_ref2 = _mm256_setzero_si256();
135	0	sum_ref1 = _mm256_setzero_si256();
136
137	0	for (i = 0; i < N; i++) {
138	0	for (j = 0; j < M; j += 32) {
139		// load src and all refs
140	0	src_reg = _mm256_loadu_si256((const __m256i *)(src + j));
141	0	ref0_reg = _mm256_loadu_si256((const __m256i *)(ref0 + j));
142	0	ref1_reg = _mm256_loadu_si256((const __m256i *)(ref1 + j));
143	0	ref2_reg = _mm256_loadu_si256((const __m256i *)(ref2 + j));
144
145		// sum of the absolute differences between every ref-i to src
146	0	ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
147	0	ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
148	0	ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
149		// sum every ref-i
150	0	sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
151	0	sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
152	0	sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
153	0	}
154	0	src += src_stride;
155	0	ref0 += ref_stride;
156	0	ref1 += ref_stride;
157	0	ref2 += ref_stride;
158	0	}
159	0	aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &zero);
160	0	}
161
162		#define SADMXN_AVX2(m, n) \
163		void aom_sad##m##x##n##x4d_avx2(const uint8_t *src, int src_stride, \
164		const uint8_t *const ref[4], int ref_stride, \
165	0	uint32_t res[4]) { \
166	0	aom_sadMxNx4d_avx2(m, n, src, src_stride, ref, ref_stride, res); \
167	0	} \ Unexecuted instantiation: aom_sad32x16x4d_avx2 Unexecuted instantiation: aom_sad32x32x4d_avx2 Unexecuted instantiation: aom_sad32x64x4d_avx2 Unexecuted instantiation: aom_sad64x32x4d_avx2 Unexecuted instantiation: aom_sad64x64x4d_avx2 Unexecuted instantiation: aom_sad64x128x4d_avx2 Unexecuted instantiation: aom_sad128x64x4d_avx2 Unexecuted instantiation: aom_sad128x128x4d_avx2 Unexecuted instantiation: aom_sad32x8x4d_avx2 Unexecuted instantiation: aom_sad64x16x4d_avx2
168		void aom_sad##m##x##n##x3d_avx2(const uint8_t *src, int src_stride, \
169		const uint8_t *const ref[4], int ref_stride, \
170	0	uint32_t res[4]) { \
171	0	aom_sadMxNx3d_avx2(m, n, src, src_stride, ref, ref_stride, res); \
172	0	} Unexecuted instantiation: aom_sad32x16x3d_avx2 Unexecuted instantiation: aom_sad32x32x3d_avx2 Unexecuted instantiation: aom_sad32x64x3d_avx2 Unexecuted instantiation: aom_sad64x32x3d_avx2 Unexecuted instantiation: aom_sad64x64x3d_avx2 Unexecuted instantiation: aom_sad64x128x3d_avx2 Unexecuted instantiation: aom_sad128x64x3d_avx2 Unexecuted instantiation: aom_sad128x128x3d_avx2 Unexecuted instantiation: aom_sad32x8x3d_avx2 Unexecuted instantiation: aom_sad64x16x3d_avx2
173
174		SADMXN_AVX2(32, 16)
175		SADMXN_AVX2(32, 32)
176		SADMXN_AVX2(32, 64)
177
178		#if !CONFIG_HIGHWAY
179		SADMXN_AVX2(64, 32)
180		SADMXN_AVX2(64, 64)
181		SADMXN_AVX2(64, 128)
182
183		SADMXN_AVX2(128, 64)
184		SADMXN_AVX2(128, 128)
185		#endif
186
187		#if !CONFIG_REALTIME_ONLY
188		SADMXN_AVX2(32, 8)
189		SADMXN_AVX2(64, 16)
190		#endif // !CONFIG_REALTIME_ONLY
191
192		#define SAD_SKIP_MXN_AVX2(m, n) \
193		void aom_sad_skip_##m##x##n##x4d_avx2(const uint8_t *src, int src_stride, \
194		const uint8_t *const ref[4], \
195	0	int ref_stride, uint32_t res[4]) { \
196	0	aom_sadMxNx4d_avx2(m, ((n) >> 1), src, 2 * src_stride, ref, \
197	0	2 * ref_stride, res); \
198	0	res[0] <<= 1; \
199	0	res[1] <<= 1; \
200	0	res[2] <<= 1; \
201	0	res[3] <<= 1; \
202	0	} Unexecuted instantiation: aom_sad_skip_32x16x4d_avx2 Unexecuted instantiation: aom_sad_skip_32x32x4d_avx2 Unexecuted instantiation: aom_sad_skip_32x64x4d_avx2 Unexecuted instantiation: aom_sad_skip_64x32x4d_avx2 Unexecuted instantiation: aom_sad_skip_64x64x4d_avx2 Unexecuted instantiation: aom_sad_skip_64x128x4d_avx2 Unexecuted instantiation: aom_sad_skip_128x64x4d_avx2 Unexecuted instantiation: aom_sad_skip_128x128x4d_avx2 Unexecuted instantiation: aom_sad_skip_64x16x4d_avx2
203
204		SAD_SKIP_MXN_AVX2(32, 16)
205		SAD_SKIP_MXN_AVX2(32, 32)
206		SAD_SKIP_MXN_AVX2(32, 64)
207
208		#if !CONFIG_HIGHWAY
209		SAD_SKIP_MXN_AVX2(64, 32)
210		SAD_SKIP_MXN_AVX2(64, 64)
211		SAD_SKIP_MXN_AVX2(64, 128)
212
213		SAD_SKIP_MXN_AVX2(128, 64)
214		SAD_SKIP_MXN_AVX2(128, 128)
215		#endif
216
217		#if !CONFIG_REALTIME_ONLY
218		SAD_SKIP_MXN_AVX2(64, 16)
219		#endif // !CONFIG_REALTIME_ONLY
220
221		static AOM_FORCE_INLINE void aom_sad16xNx3d_avx2(int N, const uint8_t *src,
222		int src_stride,
223		const uint8_t *const ref[4],
224		int ref_stride,
225	0	uint32_t res[4]) {
226	0	__m256i src_reg, ref0_reg, ref1_reg, ref2_reg;
227	0	__m256i sum_ref0, sum_ref1, sum_ref2;
228	0	const uint8_t ref0, ref1, *ref2;
229	0	const __m256i zero = _mm256_setzero_si256();
230	0	assert(N % 2 == 0);
231
232	0	ref0 = ref[0];
233	0	ref1 = ref[1];
234	0	ref2 = ref[2];
235
236	0	src_reg = yy_loadu2_128(src + src_stride, src);
237	0	sum_ref0 = _mm256_sad_epu8(yy_loadu2_128(ref0 + ref_stride, ref0), src_reg);
238	0	sum_ref1 = _mm256_sad_epu8(yy_loadu2_128(ref1 + ref_stride, ref1), src_reg);
239	0	sum_ref2 = _mm256_sad_epu8(yy_loadu2_128(ref2 + ref_stride, ref2), src_reg);
240	0	src += 2 * src_stride;
241	0	ref0 += 2 * ref_stride;
242	0	ref1 += 2 * ref_stride;
243	0	ref2 += 2 * ref_stride;
244
245		#if defined(__GNUC__) && !defined(__clang__)
246		#pragma GCC unroll 2
247		#endif
248	0	for (int i = 2; i < N; i += 2) {
249		// load src and all refs
250	0	src_reg = yy_loadu2_128(src + src_stride, src);
251	0	ref0_reg = yy_loadu2_128(ref0 + ref_stride, ref0);
252	0	ref1_reg = yy_loadu2_128(ref1 + ref_stride, ref1);
253	0	ref2_reg = yy_loadu2_128(ref2 + ref_stride, ref2);
254
255		// sum of the absolute differences between every ref-i to src
256	0	ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
257	0	ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
258	0	ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
259
260		// sum every ref-i
261	0	sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
262	0	sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
263	0	sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
264
265	0	src += 2 * src_stride;
266	0	ref0 += 2 * ref_stride;
267	0	ref1 += 2 * ref_stride;
268	0	ref2 += 2 * ref_stride;
269	0	}
270
271	0	aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &zero);
272	0	}
273
274		static AOM_FORCE_INLINE void aom_sad16xNx4d_avx2(int N, const uint8_t *src,
275		int src_stride,
276		const uint8_t *const ref[4],
277		int ref_stride,
278	0	uint32_t res[4]) {
279	0	__m256i src_reg, ref0_reg, ref1_reg, ref2_reg, ref3_reg;
280	0	__m256i sum_ref0, sum_ref1, sum_ref2, sum_ref3;
281	0	const uint8_t ref0, ref1, ref2, ref3;
282	0	assert(N % 2 == 0);
283
284	0	ref0 = ref[0];
285	0	ref1 = ref[1];
286	0	ref2 = ref[2];
287	0	ref3 = ref[3];
288
289	0	src_reg = yy_loadu2_128(src + src_stride, src);
290	0	sum_ref0 = _mm256_sad_epu8(yy_loadu2_128(ref0 + ref_stride, ref0), src_reg);
291	0	sum_ref1 = _mm256_sad_epu8(yy_loadu2_128(ref1 + ref_stride, ref1), src_reg);
292	0	sum_ref2 = _mm256_sad_epu8(yy_loadu2_128(ref2 + ref_stride, ref2), src_reg);
293	0	sum_ref3 = _mm256_sad_epu8(yy_loadu2_128(ref3 + ref_stride, ref3), src_reg);
294	0	src += 2 * src_stride;
295	0	ref0 += 2 * ref_stride;
296	0	ref1 += 2 * ref_stride;
297	0	ref2 += 2 * ref_stride;
298	0	ref3 += 2 * ref_stride;
299		#if defined(__GNUC__) && !defined(__clang__)
300		__asm__(""
301		: "+r"(src), "+r"(ref0), "+r"(ref1), "+r"(ref2), "+r"(ref3),
302		"+x"(sum_ref0), "+x"(sum_ref1), "+x"(sum_ref2), "+x"(sum_ref3));
303		#pragma GCC unroll 2
304		#endif
305	0	for (int i = 2; i < N; i += 2) {
306		// load src and all refs
307	0	src_reg = yy_loadu2_128(src + src_stride, src);
308	0	ref0_reg = yy_loadu2_128(ref0 + ref_stride, ref0);
309	0	ref1_reg = yy_loadu2_128(ref1 + ref_stride, ref1);
310	0	ref2_reg = yy_loadu2_128(ref2 + ref_stride, ref2);
311	0	ref3_reg = yy_loadu2_128(ref3 + ref_stride, ref3);
312
313		// sum of the absolute differences between every ref-i to src
314	0	ref0_reg = _mm256_sad_epu8(ref0_reg, src_reg);
315	0	ref1_reg = _mm256_sad_epu8(ref1_reg, src_reg);
316	0	ref2_reg = _mm256_sad_epu8(ref2_reg, src_reg);
317	0	ref3_reg = _mm256_sad_epu8(ref3_reg, src_reg);
318
319		// sum every ref-i
320	0	sum_ref0 = _mm256_add_epi32(sum_ref0, ref0_reg);
321	0	sum_ref1 = _mm256_add_epi32(sum_ref1, ref1_reg);
322	0	sum_ref2 = _mm256_add_epi32(sum_ref2, ref2_reg);
323	0	sum_ref3 = _mm256_add_epi32(sum_ref3, ref3_reg);
324
325	0	src += 2 * src_stride;
326	0	ref0 += 2 * ref_stride;
327	0	ref1 += 2 * ref_stride;
328	0	ref2 += 2 * ref_stride;
329	0	ref3 += 2 * ref_stride;
330		#if defined(__GNUC__) && !defined(__clang__)
331		__asm__(""
332		: "+r"(src), "+r"(ref0), "+r"(ref1), "+r"(ref2), "+r"(ref3),
333		"+x"(sum_ref0), "+x"(sum_ref1), "+x"(sum_ref2), "+x"(sum_ref3));
334		#endif
335	0	}
336
337	0	aggregate_and_store_sum(res, &sum_ref0, &sum_ref1, &sum_ref2, &sum_ref3);
338	0	}
339
340		#define SAD16XNX3_AVX2(n) \
341		void aom_sad16x##n##x3d_avx2(const uint8_t *src, int src_stride, \
342		const uint8_t *const ref[4], int ref_stride, \
343	0	uint32_t res[4]) { \
344	0	aom_sad16xNx3d_avx2(n, src, src_stride, ref, ref_stride, res); \
345	0	} Unexecuted instantiation: aom_sad16x32x3d_avx2 Unexecuted instantiation: aom_sad16x16x3d_avx2 Unexecuted instantiation: aom_sad16x8x3d_avx2 Unexecuted instantiation: aom_sad16x64x3d_avx2 Unexecuted instantiation: aom_sad16x4x3d_avx2
346		#define SAD16XNX4_AVX2(n) \
347		void aom_sad16x##n##x4d_avx2(const uint8_t *src, int src_stride, \
348		const uint8_t *const ref[4], int ref_stride, \
349	0	uint32_t res[4]) { \
350	0	aom_sad16xNx4d_avx2(n, src, src_stride, ref, ref_stride, res); \
351	0	} Unexecuted instantiation: aom_sad16x32x4d_avx2 Unexecuted instantiation: aom_sad16x16x4d_avx2 Unexecuted instantiation: aom_sad16x8x4d_avx2 Unexecuted instantiation: aom_sad16x64x4d_avx2 Unexecuted instantiation: aom_sad16x4x4d_avx2
352
353		SAD16XNX4_AVX2(32)
354		SAD16XNX4_AVX2(16)
355		SAD16XNX4_AVX2(8)
356
357		SAD16XNX3_AVX2(32)
358		SAD16XNX3_AVX2(16)
359		SAD16XNX3_AVX2(8)
360
361		#if !CONFIG_REALTIME_ONLY
362		SAD16XNX3_AVX2(64)
363		SAD16XNX3_AVX2(4)
364
365		SAD16XNX4_AVX2(64)
366		SAD16XNX4_AVX2(4)
367
368		#endif // !CONFIG_REALTIME_ONLY
369
370		#define SAD_SKIP_16XN_AVX2(n) \
371		void aom_sad_skip_16x##n##x4d_avx2(const uint8_t *src, int src_stride, \
372		const uint8_t *const ref[4], \
373	0	int ref_stride, uint32_t res[4]) { \
374	0	aom_sad16xNx4d_avx2(((n) >> 1), src, 2 * src_stride, ref, 2 * ref_stride, \
375	0	res); \
376	0	res[0] <<= 1; \
377	0	res[1] <<= 1; \
378	0	res[2] <<= 1; \
379	0	res[3] <<= 1; \
380	0	} Unexecuted instantiation: aom_sad_skip_16x32x4d_avx2 Unexecuted instantiation: aom_sad_skip_16x16x4d_avx2 Unexecuted instantiation: aom_sad_skip_16x64x4d_avx2
381
382		SAD_SKIP_16XN_AVX2(32)
383		SAD_SKIP_16XN_AVX2(16)
384
385		#if !CONFIG_REALTIME_ONLY
386		SAD_SKIP_16XN_AVX2(64)
387		#endif // !CONFIG_REALTIME_ONLY