/src/libavc/encoder/ih264e_api.c
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1 | | /****************************************************************************** |
2 | | * |
3 | | * Copyright (C) 2015 The Android Open Source Project |
4 | | * |
5 | | * Licensed under the Apache License, Version 2.0 (the "License"); |
6 | | * you may not use this file except in compliance with the License. |
7 | | * You may obtain a copy of the License at: |
8 | | * |
9 | | * http://www.apache.org/licenses/LICENSE-2.0 |
10 | | * |
11 | | * Unless required by applicable law or agreed to in writing, software |
12 | | * distributed under the License is distributed on an "AS IS" BASIS, |
13 | | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
14 | | * See the License for the specific language governing permissions and |
15 | | * limitations under the License. |
16 | | * |
17 | | ***************************************************************************** |
18 | | * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore |
19 | | */ |
20 | | |
21 | | /** |
22 | | ******************************************************************************* |
23 | | * @file |
24 | | * ih264e_api.c |
25 | | * |
26 | | * @brief |
27 | | * Contains api function definitions for H264 encoder |
28 | | * |
29 | | * @author |
30 | | * ittiam |
31 | | * |
32 | | * @par List of Functions: |
33 | | * - api_check_struct_sanity |
34 | | * - ih264e_codec_update_config |
35 | | * - ih264e_set_default_params |
36 | | * - ih264e_init |
37 | | * - ih264e_get_num_rec |
38 | | * - ih264e_fill_num_mem_rec |
39 | | * - ih264e_init_mem_rec |
40 | | * - ih264e_retrieve_memrec |
41 | | * - ih264e_set_flush_mode |
42 | | * - ih264e_get_buf_info |
43 | | * - ih264e_set_dimensions |
44 | | * - ih264e_set_frame_rate |
45 | | * - ih264e_set_bit_rate |
46 | | * - ih264e_set_frame_type |
47 | | * - ih264e_set_qp |
48 | | * - ih264e_set_enc_mode |
49 | | * - ih264e_set_vbv_params |
50 | | * - ih264_set_air_params |
51 | | * - ih264_set_me_params |
52 | | * - ih264_set_ipe_params |
53 | | * - ih264_set_gop_params |
54 | | * - ih264_set_profile_params |
55 | | * - ih264_set_deblock_params |
56 | | * - ih264e_set_num_cores |
57 | | * - ih264e_reset |
58 | | * - ih264e_ctl |
59 | | * - ih264e_api_function |
60 | | * |
61 | | * @remarks |
62 | | * none |
63 | | * |
64 | | ******************************************************************************* |
65 | | */ |
66 | | |
67 | | /*****************************************************************************/ |
68 | | /* File Includes */ |
69 | | /*****************************************************************************/ |
70 | | |
71 | | /* System Include Files */ |
72 | | #include <stdio.h> |
73 | | #include <stddef.h> |
74 | | #include <stdlib.h> |
75 | | #include <string.h> |
76 | | #include <assert.h> |
77 | | |
78 | | /* User Include Files */ |
79 | | #include "ih264e_config.h" |
80 | | #include "ih264_typedefs.h" |
81 | | #include "iv2.h" |
82 | | #include "ive2.h" |
83 | | #include "ithread.h" |
84 | | |
85 | | #include "ih264_debug.h" |
86 | | #include "ih264_macros.h" |
87 | | #include "ih264_error.h" |
88 | | #include "ih264_defs.h" |
89 | | #include "ih264_mem_fns.h" |
90 | | #include "ih264_padding.h" |
91 | | #include "ih264_structs.h" |
92 | | #include "ih264_size_defs.h" |
93 | | #include "ih264_trans_quant_itrans_iquant.h" |
94 | | #include "ih264_inter_pred_filters.h" |
95 | | #include "ih264_intra_pred_filters.h" |
96 | | #include "ih264_deblk_edge_filters.h" |
97 | | #include "ih264_common_tables.h" |
98 | | #include "ih264_cavlc_tables.h" |
99 | | #include "ih264_cabac_tables.h" |
100 | | #include "ih264_buf_mgr.h" |
101 | | #include "ih264_list.h" |
102 | | #include "ih264_dpb_mgr.h" |
103 | | #include "ih264_platform_macros.h" |
104 | | |
105 | | #include "ime_defs.h" |
106 | | #include "ime_distortion_metrics.h" |
107 | | #include "ime_structs.h" |
108 | | |
109 | | #include "irc_mem_req_and_acq.h" |
110 | | #include "irc_cntrl_param.h" |
111 | | #include "irc_frame_info_collector.h" |
112 | | #include "irc_rate_control_api.h" |
113 | | |
114 | | #include "ih264e.h" |
115 | | #include "ih264e_error.h" |
116 | | #include "ih264e_version.h" |
117 | | #include "ih264e_defs.h" |
118 | | #include "ih264e_globals.h" |
119 | | #include "ih264e_time_stamp.h" |
120 | | #include "ih264e_modify_frm_rate.h" |
121 | | #include "ih264e_rate_control.h" |
122 | | #include "ih264e_rc_mem_interface.h" |
123 | | #include "ih264e_bitstream.h" |
124 | | #include "ih264e_cabac_structs.h" |
125 | | #include "ih264e_structs.h" |
126 | | #include "ih264e_utils.h" |
127 | | #include "ih264e_core_coding.h" |
128 | | #include "ih264e_cavlc.h" |
129 | | #include "ih264e_master.h" |
130 | | #include "ih264e_fmt_conv.h" |
131 | | #include "ih264e_platform_macros.h" |
132 | | |
133 | | |
134 | | /*****************************************************************************/ |
135 | | /* Function Definitions */ |
136 | | /*****************************************************************************/ |
137 | | |
138 | | /** |
139 | | ******************************************************************************* |
140 | | * |
141 | | * @brief |
142 | | * Used to test arguments for corresponding API call |
143 | | * |
144 | | * @par Description: |
145 | | * For each command the arguments are validated |
146 | | * |
147 | | * @param[in] ps_handle |
148 | | * Codec handle at API level |
149 | | * |
150 | | * @param[in] pv_api_ip |
151 | | * Pointer to input structure |
152 | | * |
153 | | * @param[out] pv_api_op |
154 | | * Pointer to output structure |
155 | | * |
156 | | * @returns error status |
157 | | * |
158 | | * @remarks none |
159 | | * |
160 | | ******************************************************************************* |
161 | | */ |
162 | | static IV_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle, |
163 | | void *pv_api_ip, |
164 | | void *pv_api_op) |
165 | 174k | { |
166 | | /* api call */ |
167 | 174k | WORD32 command = IV_CMD_NA; |
168 | | |
169 | | /* input structure expected by the api call */ |
170 | 174k | UWORD32 *pu4_api_ip = pv_api_ip; |
171 | | |
172 | | /* output structure expected by the api call */ |
173 | 174k | UWORD32 *pu4_api_op = pv_api_op; |
174 | | |
175 | | /* temp var */ |
176 | 174k | WORD32 i, j; |
177 | | |
178 | 174k | if (NULL == pv_api_op || NULL == pv_api_ip) |
179 | 0 | { |
180 | 0 | return (IV_FAIL); |
181 | 0 | } |
182 | | |
183 | | /* get command */ |
184 | 174k | command = pu4_api_ip[1]; |
185 | | |
186 | | /* set error code */ |
187 | 174k | pu4_api_op[1] = 0; |
188 | | |
189 | | /* error checks on handle */ |
190 | 174k | switch (command) |
191 | 174k | { |
192 | 3.92k | case IV_CMD_GET_NUM_MEM_REC: |
193 | 11.7k | case IV_CMD_FILL_NUM_MEM_REC: |
194 | 11.7k | break; |
195 | | |
196 | 3.91k | case IV_CMD_INIT: |
197 | 3.91k | if (ps_handle == NULL) |
198 | 0 | { |
199 | 0 | *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; |
200 | 0 | *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL; |
201 | 0 | return IV_FAIL; |
202 | 0 | } |
203 | | |
204 | 3.91k | if (ps_handle->u4_size != sizeof(iv_obj_t)) |
205 | 0 | { |
206 | 0 | *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; |
207 | 0 | *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT; |
208 | 0 | return IV_FAIL; |
209 | 0 | } |
210 | 3.91k | break; |
211 | | |
212 | 3.91k | case IVE_CMD_QUEUE_INPUT: |
213 | 0 | case IVE_CMD_QUEUE_OUTPUT: |
214 | 0 | case IVE_CMD_DEQUEUE_OUTPUT: |
215 | 0 | case IVE_CMD_GET_RECON: |
216 | 3.90k | case IV_CMD_RETRIEVE_MEMREC: |
217 | 92.5k | case IVE_CMD_VIDEO_CTL: |
218 | 158k | case IVE_CMD_VIDEO_ENCODE: |
219 | | |
220 | 158k | if (ps_handle == NULL) |
221 | 0 | { |
222 | 0 | *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; |
223 | 0 | *(pu4_api_op + 1) |= IVE_ERR_HANDLE_NULL; |
224 | 0 | return IV_FAIL; |
225 | 0 | } |
226 | | |
227 | 158k | if (ps_handle->u4_size != sizeof(iv_obj_t)) |
228 | 0 | { |
229 | 0 | *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; |
230 | 0 | *(pu4_api_op + 1) |= IVE_ERR_HANDLE_STRUCT_SIZE_INCORRECT; |
231 | 0 | return IV_FAIL; |
232 | 0 | } |
233 | | |
234 | 158k | if (ps_handle->pv_fxns != ih264e_api_function) |
235 | 0 | { |
236 | 0 | *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; |
237 | 0 | *(pu4_api_op + 1) |= IVE_ERR_API_FUNCTION_PTR_NULL; |
238 | 0 | return IV_FAIL; |
239 | 0 | } |
240 | | |
241 | 158k | if (ps_handle->pv_codec_handle == NULL) |
242 | 0 | { |
243 | 0 | *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; |
244 | 0 | *(pu4_api_op + 1) |= IVE_ERR_INVALID_CODEC_HANDLE; |
245 | 0 | return IV_FAIL; |
246 | 0 | } |
247 | 158k | break; |
248 | | |
249 | 158k | default: |
250 | 0 | *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; |
251 | 0 | *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD; |
252 | 0 | return IV_FAIL; |
253 | 174k | } |
254 | | |
255 | | /* error checks on input output structures */ |
256 | 174k | switch (command) |
257 | 174k | { |
258 | 3.92k | case IV_CMD_GET_NUM_MEM_REC: |
259 | 3.92k | { |
260 | 3.92k | ih264e_num_mem_rec_ip_t *ps_ip = pv_api_ip; |
261 | 3.92k | ih264e_num_mem_rec_op_t *ps_op = pv_api_op; |
262 | | |
263 | 3.92k | ps_op->s_ive_op.u4_error_code = 0; |
264 | | |
265 | 3.92k | if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_num_mem_rec_ip_t)) |
266 | 0 | { |
267 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
268 | 0 | ps_op->s_ive_op.u4_error_code |= |
269 | 0 | IVE_ERR_IP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT; |
270 | 0 | return (IV_FAIL); |
271 | 0 | } |
272 | | |
273 | 3.92k | if (ps_op->s_ive_op.u4_size != sizeof(ih264e_num_mem_rec_op_t)) |
274 | 0 | { |
275 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
276 | 0 | ps_op->s_ive_op.u4_error_code |= |
277 | 0 | IVE_ERR_OP_GET_MEM_REC_API_STRUCT_SIZE_INCORRECT; |
278 | 0 | return (IV_FAIL); |
279 | 0 | } |
280 | 3.92k | break; |
281 | 3.92k | } |
282 | | |
283 | 7.83k | case IV_CMD_FILL_NUM_MEM_REC: |
284 | 7.83k | { |
285 | 7.83k | ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip; |
286 | 7.83k | ih264e_fill_mem_rec_op_t *ps_op = pv_api_op; |
287 | | |
288 | 7.83k | iv_mem_rec_t *ps_mem_rec = NULL; |
289 | | |
290 | 7.83k | WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd); |
291 | 7.83k | WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht); |
292 | | |
293 | 7.83k | ps_op->s_ive_op.u4_error_code = 0; |
294 | | |
295 | 7.83k | if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_fill_mem_rec_ip_t)) |
296 | 0 | { |
297 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
298 | 0 | ps_op->s_ive_op.u4_error_code |= |
299 | 0 | IVE_ERR_IP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT; |
300 | 0 | return (IV_FAIL); |
301 | 0 | } |
302 | | |
303 | 7.83k | if (ps_op->s_ive_op.u4_size != sizeof(ih264e_fill_mem_rec_op_t)) |
304 | 0 | { |
305 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
306 | 0 | ps_op->s_ive_op.u4_error_code |= |
307 | 0 | IVE_ERR_OP_FILL_MEM_REC_API_STRUCT_SIZE_INCORRECT; |
308 | 0 | return (IV_FAIL); |
309 | 0 | } |
310 | | |
311 | 7.83k | if (max_wd < MIN_WD || max_wd > MAX_WD) |
312 | 3 | { |
313 | 3 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
314 | 3 | ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED; |
315 | 3 | return (IV_FAIL); |
316 | 3 | } |
317 | | |
318 | 7.82k | if (max_ht < MIN_HT || max_ht > MAX_HT) |
319 | 4 | { |
320 | 4 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
321 | 4 | ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED; |
322 | 4 | return (IV_FAIL); |
323 | 4 | } |
324 | | |
325 | | /* verify number of mem rec ptr */ |
326 | 7.82k | if (NULL == ps_ip->s_ive_ip.ps_mem_rec) |
327 | 0 | { |
328 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
329 | 0 | ps_op->s_ive_op.u4_error_code |= |
330 | 0 | IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL; |
331 | 0 | return (IV_FAIL); |
332 | 0 | } |
333 | | |
334 | | /* verify number of mem records */ |
335 | 7.82k | if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT) |
336 | 0 | { |
337 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
338 | 0 | ps_op->s_ive_op.u4_error_code |= |
339 | 0 | IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT; |
340 | 0 | return IV_FAIL; |
341 | 0 | } |
342 | | |
343 | | /* check mem records sizes are correct */ |
344 | 7.82k | ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec; |
345 | 406k | for (i = 0; i < MEM_REC_CNT; i++) |
346 | 399k | { |
347 | 399k | if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) |
348 | 0 | { |
349 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
350 | 0 | ps_op->s_ive_op.u4_error_code |= |
351 | 0 | IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT; |
352 | 0 | return IV_FAIL; |
353 | 0 | } |
354 | 399k | } |
355 | 7.82k | break; |
356 | 7.82k | } |
357 | | |
358 | 7.82k | case IV_CMD_INIT: |
359 | 3.91k | { |
360 | 3.91k | ih264e_init_ip_t *ps_ip = pv_api_ip; |
361 | 3.91k | ih264e_init_op_t *ps_op = pv_api_op; |
362 | | |
363 | 3.91k | iv_mem_rec_t *ps_mem_rec = NULL; |
364 | | |
365 | 3.91k | WORD32 max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd); |
366 | 3.91k | WORD32 max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht); |
367 | | |
368 | 3.91k | ps_op->s_ive_op.u4_error_code = 0; |
369 | | |
370 | 3.91k | if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_init_ip_t)) |
371 | 0 | { |
372 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
373 | 0 | ps_op->s_ive_op.u4_error_code |= |
374 | 0 | IVE_ERR_IP_INIT_API_STRUCT_SIZE_INCORRECT; |
375 | 0 | return (IV_FAIL); |
376 | 0 | } |
377 | | |
378 | 3.91k | if (ps_op->s_ive_op.u4_size != sizeof(ih264e_init_op_t)) |
379 | 0 | { |
380 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
381 | 0 | ps_op->s_ive_op.u4_error_code |= |
382 | 0 | IVE_ERR_OP_INIT_API_STRUCT_SIZE_INCORRECT; |
383 | 0 | return (IV_FAIL); |
384 | 0 | } |
385 | | |
386 | 3.91k | if (max_wd < MIN_WD || max_wd > MAX_WD) |
387 | 0 | { |
388 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
389 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_WIDTH_NOT_SUPPORTED; |
390 | 0 | return (IV_FAIL); |
391 | 0 | } |
392 | | |
393 | 3.91k | if (max_ht < MIN_HT || max_ht > MAX_HT) |
394 | 0 | { |
395 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
396 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_HEIGHT_NOT_SUPPORTED; |
397 | 0 | return (IV_FAIL); |
398 | 0 | } |
399 | | |
400 | 3.91k | if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_PIC_CNT || |
401 | 3.91k | ps_ip->s_ive_ip.u4_max_ref_cnt < MIN_REF_PIC_CNT) |
402 | 0 | { |
403 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
404 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED; |
405 | 0 | return (IV_FAIL); |
406 | 0 | } |
407 | | |
408 | 3.91k | if (ps_ip->s_ive_ip.u4_max_reorder_cnt != 0) |
409 | 0 | { |
410 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
411 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED; |
412 | 0 | return (IV_FAIL); |
413 | 0 | } |
414 | | |
415 | 3.91k | if ((ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_10) |
416 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_1B) |
417 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_11) |
418 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_12) |
419 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_13) |
420 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_20) |
421 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_21) |
422 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_22) |
423 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_30) |
424 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_31) |
425 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_32) |
426 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_40) |
427 | 3.91k | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_41) |
428 | 0 | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_42) |
429 | 0 | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_50) |
430 | 0 | && (ps_ip->s_ive_ip.u4_max_level != IH264_LEVEL_51)) |
431 | 0 | { |
432 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
433 | 0 | ps_op->s_ive_op.u4_error_code |= |
434 | 0 | IH264E_CODEC_LEVEL_NOT_SUPPORTED; |
435 | 0 | return (IV_FAIL); |
436 | 0 | } |
437 | | |
438 | 3.91k | if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P) |
439 | 2.32k | && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE) |
440 | 1.79k | && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV) |
441 | 1.05k | && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU)) |
442 | 0 | { |
443 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
444 | 0 | ps_op->s_ive_op.u4_error_code |= |
445 | 0 | IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED; |
446 | 0 | return (IV_FAIL); |
447 | 0 | } |
448 | | |
449 | 3.91k | if ((ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420P) |
450 | 0 | && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_UV) |
451 | 0 | && (ps_ip->s_ive_ip.e_recon_color_fmt != IV_YUV_420SP_VU)) |
452 | 0 | { |
453 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
454 | 0 | ps_op->s_ive_op.u4_error_code |= |
455 | 0 | IH264E_RECON_CHROMA_FORMAT_NOT_SUPPORTED; |
456 | 0 | return (IV_FAIL); |
457 | 0 | } |
458 | | |
459 | 3.91k | if ((ps_ip->s_ive_ip.e_rc_mode != IVE_RC_NONE) |
460 | 2.29k | && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_STORAGE) |
461 | 1.01k | && (ps_ip->s_ive_ip.e_rc_mode != IVE_RC_CBR_NON_LOW_DELAY)) |
462 | 12 | { |
463 | 12 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
464 | 12 | ps_op->s_ive_op.u4_error_code |= |
465 | 12 | IH264E_RATE_CONTROL_MODE_NOT_SUPPORTED; |
466 | 12 | return (IV_FAIL); |
467 | 12 | } |
468 | | |
469 | 3.90k | if (ps_ip->s_ive_ip.u4_max_framerate > DEFAULT_MAX_FRAMERATE) |
470 | 0 | { |
471 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
472 | 0 | ps_op->s_ive_op.u4_error_code |= |
473 | 0 | IH264E_FRAME_RATE_NOT_SUPPORTED; |
474 | 0 | return (IV_FAIL); |
475 | 0 | } |
476 | | |
477 | 3.90k | if (ps_ip->s_ive_ip.u4_max_bitrate > DEFAULT_MAX_BITRATE) |
478 | 0 | { |
479 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
480 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_BITRATE_NOT_SUPPORTED; |
481 | 0 | return (IV_FAIL); |
482 | 0 | } |
483 | | |
484 | 3.90k | if (ps_ip->s_ive_ip.u4_num_bframes > MAX_NUM_BFRAMES) |
485 | 0 | { |
486 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
487 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED; |
488 | 0 | return (IV_FAIL); |
489 | 0 | } |
490 | | |
491 | 3.90k | if (ps_ip->s_ive_ip.u4_num_bframes |
492 | 2.34k | && (ps_ip->s_ive_ip.u4_max_ref_cnt < 2)) |
493 | 0 | { |
494 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
495 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_BFRAMES_NOT_SUPPORTED; |
496 | 0 | return (IV_FAIL); |
497 | 0 | } |
498 | | |
499 | 3.90k | if (ps_ip->s_ive_ip.e_content_type != IV_PROGRESSIVE) |
500 | 0 | { |
501 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
502 | 0 | ps_op->s_ive_op.u4_error_code |= |
503 | 0 | IH264E_CONTENT_TYPE_NOT_SUPPORTED; |
504 | 0 | return (IV_FAIL); |
505 | 0 | } |
506 | | |
507 | 3.90k | if (ps_ip->s_ive_ip.u4_max_srch_rng_x > DEFAULT_MAX_SRCH_RANGE_X) |
508 | 0 | { |
509 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
510 | 0 | ps_op->s_ive_op.u4_error_code |= |
511 | 0 | IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED; |
512 | 0 | return (IV_FAIL); |
513 | 0 | } |
514 | | |
515 | 3.90k | if (ps_ip->s_ive_ip.u4_max_srch_rng_y > DEFAULT_MAX_SRCH_RANGE_Y) |
516 | 0 | { |
517 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
518 | 0 | ps_op->s_ive_op.u4_error_code |= |
519 | 0 | IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED; |
520 | 0 | return (IV_FAIL); |
521 | 0 | } |
522 | | |
523 | 3.90k | if ((ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_NONE) |
524 | 0 | && (ps_ip->s_ive_ip.e_slice_mode != IVE_SLICE_MODE_BLOCKS)) |
525 | 0 | { |
526 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
527 | 0 | ps_op->s_ive_op.u4_error_code |= |
528 | 0 | IH264E_SLICE_TYPE_INPUT_INVALID; |
529 | 0 | return (IV_FAIL); |
530 | 0 | } |
531 | | |
532 | 3.90k | if (ps_ip->s_ive_ip.e_slice_mode == IVE_SLICE_MODE_BLOCKS) |
533 | 0 | { |
534 | 0 | if (ps_ip->s_ive_ip.u4_slice_param == 0 |
535 | 0 | || ps_ip->s_ive_ip.u4_slice_param > ((UWORD32)max_ht >> 4)) |
536 | 0 | { |
537 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
538 | 0 | ps_op->s_ive_op.u4_error_code |= |
539 | 0 | IH264E_SLICE_PARAM_INPUT_INVALID; |
540 | 0 | return (IV_FAIL); |
541 | 0 | } |
542 | 0 | } |
543 | | |
544 | 3.90k | if (NULL == ps_ip->s_ive_ip.ps_mem_rec) |
545 | 0 | { |
546 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
547 | 0 | ps_op->s_ive_op.u4_error_code |= |
548 | 0 | IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL; |
549 | 0 | return (IV_FAIL); |
550 | 0 | } |
551 | | |
552 | | /* verify number of mem records */ |
553 | 3.90k | if (ps_ip->s_ive_ip.u4_num_mem_rec != MEM_REC_CNT) |
554 | 0 | { |
555 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
556 | 0 | ps_op->s_ive_op.u4_error_code |= |
557 | 0 | IVE_ERR_NUM_MEM_REC_NOT_SUFFICIENT; |
558 | 0 | return (IV_FAIL); |
559 | 0 | } |
560 | | |
561 | 3.90k | ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec; |
562 | | |
563 | | /* check memrecords sizes are correct */ |
564 | 203k | for (i = 0; i <((WORD32)ps_ip->s_ive_ip.u4_num_mem_rec); i++) |
565 | 199k | { |
566 | 199k | if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) |
567 | 0 | { |
568 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
569 | 0 | ps_op->s_ive_op.u4_error_code |= |
570 | 0 | IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT; |
571 | 0 | return IV_FAIL; |
572 | 0 | } |
573 | | |
574 | | /* check memrecords pointers are not NULL */ |
575 | 199k | if (ps_mem_rec[i].pv_base == NULL) |
576 | 0 | { |
577 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
578 | 0 | ps_op->s_ive_op.u4_error_code |= |
579 | 0 | IVE_ERR_MEM_REC_BASE_POINTER_NULL; |
580 | 0 | return IV_FAIL; |
581 | 0 | } |
582 | 199k | } |
583 | | |
584 | | /* verify memtabs for overlapping regions */ |
585 | 3.90k | { |
586 | 3.90k | void *start[MEM_REC_CNT]; |
587 | 3.90k | void *end[MEM_REC_CNT]; |
588 | | |
589 | 3.90k | start[0] = (ps_mem_rec[0].pv_base); |
590 | 3.90k | end[0] = ((UWORD8 *) ps_mem_rec[0].pv_base) |
591 | 3.90k | + ps_mem_rec[0].u4_mem_size - 1; |
592 | | |
593 | 199k | for (i = 1; i < MEM_REC_CNT; i++) |
594 | 195k | { |
595 | | /* This array is populated to check memtab overlap */ |
596 | 195k | start[i] = (ps_mem_rec[i].pv_base); |
597 | 195k | end[i] = ((UWORD8 *) ps_mem_rec[i].pv_base) |
598 | 195k | + ps_mem_rec[i].u4_mem_size - 1; |
599 | | |
600 | 5.17M | for (j = 0; j < i; j++) |
601 | 4.98M | { |
602 | 4.98M | if ((start[i] >= start[j]) && (start[i] <= end[j])) |
603 | 0 | { |
604 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
605 | 0 | << IVE_UNSUPPORTEDPARAM; |
606 | 0 | ps_op->s_ive_op.u4_error_code |= |
607 | 0 | IVE_ERR_MEM_REC_OVERLAP_ERR; |
608 | 0 | return IV_FAIL; |
609 | 0 | } |
610 | | |
611 | 4.98M | if ((end[i] >= start[j]) && (end[i] <= end[j])) |
612 | 0 | { |
613 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
614 | 0 | << IVE_UNSUPPORTEDPARAM; |
615 | 0 | ps_op->s_ive_op.u4_error_code |= |
616 | 0 | IVE_ERR_MEM_REC_OVERLAP_ERR; |
617 | 0 | return IV_FAIL; |
618 | 0 | } |
619 | | |
620 | 4.98M | if ((start[i] < start[j]) && (end[i] > end[j])) |
621 | 0 | { |
622 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
623 | 0 | << IVE_UNSUPPORTEDPARAM; |
624 | 0 | ps_op->s_ive_op.u4_error_code |= |
625 | 0 | IVE_ERR_MEM_REC_OVERLAP_ERR; |
626 | 0 | return IV_FAIL; |
627 | 0 | } |
628 | 4.98M | } |
629 | 195k | } |
630 | 3.90k | } |
631 | | |
632 | | /* re-validate mem records with init config */ |
633 | 3.90k | { |
634 | | /* mem records */ |
635 | 3.90k | iv_mem_rec_t s_mem_rec_ittiam_api[MEM_REC_CNT]; |
636 | | |
637 | | /* api interface structs */ |
638 | 3.90k | ih264e_fill_mem_rec_ip_t s_ip; |
639 | 3.90k | ih264e_fill_mem_rec_op_t s_op; |
640 | | |
641 | | /* error status */ |
642 | 3.90k | IV_STATUS_T e_status; |
643 | | |
644 | | /* temp var */ |
645 | 3.90k | WORD32 i; |
646 | | |
647 | 3.90k | s_ip.s_ive_ip.u4_size = sizeof(ih264e_fill_mem_rec_ip_t); |
648 | 3.90k | s_op.s_ive_op.u4_size = sizeof(ih264e_fill_mem_rec_op_t); |
649 | | |
650 | 3.90k | s_ip.s_ive_ip.e_cmd = IV_CMD_FILL_NUM_MEM_REC; |
651 | 3.90k | s_ip.s_ive_ip.ps_mem_rec = s_mem_rec_ittiam_api; |
652 | 3.90k | s_ip.s_ive_ip.u4_max_wd = max_wd; |
653 | 3.90k | s_ip.s_ive_ip.u4_max_ht = max_ht; |
654 | 3.90k | s_ip.s_ive_ip.u4_num_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec; |
655 | 3.90k | s_ip.s_ive_ip.u4_max_level = ps_ip->s_ive_ip.u4_max_level; |
656 | 3.90k | s_ip.s_ive_ip.u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt; |
657 | 3.90k | s_ip.s_ive_ip.u4_max_reorder_cnt = |
658 | 3.90k | ps_ip->s_ive_ip.u4_max_reorder_cnt; |
659 | 3.90k | s_ip.s_ive_ip.e_color_format = ps_ip->s_ive_ip.e_inp_color_fmt; |
660 | 3.90k | s_ip.s_ive_ip.u4_max_srch_rng_x = |
661 | 3.90k | ps_ip->s_ive_ip.u4_max_srch_rng_x; |
662 | 3.90k | s_ip.s_ive_ip.u4_max_srch_rng_y = |
663 | 3.90k | ps_ip->s_ive_ip.u4_max_srch_rng_y; |
664 | 3.90k | s_ip.s_ive_ip.u4_keep_threads_active = ps_ip->s_ive_ip.u4_keep_threads_active; |
665 | | |
666 | 203k | for (i = 0; i < MEM_REC_CNT; i++) |
667 | 199k | { |
668 | 199k | s_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t); |
669 | 199k | } |
670 | | |
671 | | /* fill mem records */ |
672 | 3.90k | e_status = ih264e_api_function(NULL, (void *) &s_ip, |
673 | 3.90k | (void *) &s_op); |
674 | | |
675 | 3.90k | if (IV_FAIL == e_status) |
676 | 0 | { |
677 | 0 | ps_op->s_ive_op.u4_error_code = s_op.s_ive_op.u4_error_code; |
678 | 0 | return (IV_FAIL); |
679 | 0 | } |
680 | | |
681 | | /* verify mem records */ |
682 | 203k | for (i = 0; i < MEM_REC_CNT; i++) |
683 | 199k | { |
684 | 199k | if (ps_mem_rec[i].u4_mem_size |
685 | 199k | < s_mem_rec_ittiam_api[i].u4_mem_size) |
686 | 0 | { |
687 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
688 | 0 | << IVE_UNSUPPORTEDPARAM; |
689 | 0 | ps_op->s_ive_op.u4_error_code |= |
690 | 0 | IVE_ERR_MEM_REC_INSUFFICIENT_SIZE; |
691 | |
|
692 | 0 | return IV_FAIL; |
693 | 0 | } |
694 | | |
695 | 199k | if (ps_mem_rec[i].u4_mem_alignment |
696 | 199k | != s_mem_rec_ittiam_api[i].u4_mem_alignment) |
697 | 0 | { |
698 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
699 | 0 | << IVE_UNSUPPORTEDPARAM; |
700 | 0 | ps_op->s_ive_op.u4_error_code |= |
701 | 0 | IVE_ERR_MEM_REC_ALIGNMENT_ERR; |
702 | |
|
703 | 0 | return IV_FAIL; |
704 | 0 | } |
705 | | |
706 | 199k | if (ps_mem_rec[i].e_mem_type |
707 | 199k | != s_mem_rec_ittiam_api[i].e_mem_type) |
708 | 0 | { |
709 | 0 | UWORD32 check = IV_SUCCESS; |
710 | 0 | UWORD32 diff = s_mem_rec_ittiam_api[i].e_mem_type |
711 | 0 | - ps_mem_rec[i].e_mem_type; |
712 | |
|
713 | 0 | if ((ps_mem_rec[i].e_mem_type |
714 | 0 | <= IV_EXTERNAL_CACHEABLE_SCRATCH_MEM) |
715 | 0 | && (s_mem_rec_ittiam_api[i].e_mem_type |
716 | 0 | >= IV_INTERNAL_NONCACHEABLE_PERSISTENT_MEM)) |
717 | 0 | { |
718 | 0 | check = IV_FAIL; |
719 | 0 | } |
720 | |
|
721 | 0 | if (3 != (s_mem_rec_ittiam_api[i].e_mem_type % 4)) |
722 | 0 | { |
723 | | /* It is not IV_EXTERNAL_NONCACHEABLE_PERSISTENT_MEM or |
724 | | * IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM */ |
725 | |
|
726 | 0 | if ((diff < 1) || (diff > 3)) |
727 | 0 | { |
728 | | /* Difference between 1 and 3 is okay for all cases other than the |
729 | | * two filtered with the MOD condition above */ |
730 | 0 | check = IV_FAIL; |
731 | 0 | } |
732 | 0 | } |
733 | 0 | else |
734 | 0 | { |
735 | 0 | if (diff == 1) |
736 | 0 | { |
737 | | /* This particular case is when codec asked for External Persistent, |
738 | | * but got Internal Scratch */ |
739 | 0 | check = IV_FAIL; |
740 | 0 | } |
741 | 0 | if ((diff != 2) && (diff != 3)) |
742 | 0 | { |
743 | 0 | check = IV_FAIL; |
744 | 0 | } |
745 | 0 | } |
746 | |
|
747 | 0 | if (check == IV_FAIL) |
748 | 0 | { |
749 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
750 | 0 | << IVE_UNSUPPORTEDPARAM; |
751 | 0 | ps_op->s_ive_op.u4_error_code |= |
752 | 0 | IVE_ERR_MEM_REC_INCORRECT_TYPE; |
753 | |
|
754 | 0 | return IV_FAIL; |
755 | 0 | } |
756 | 0 | } |
757 | 199k | } |
758 | 3.90k | } |
759 | 3.90k | break; |
760 | 3.90k | } |
761 | | |
762 | 3.90k | case IVE_CMD_QUEUE_INPUT: |
763 | 0 | case IVE_CMD_QUEUE_OUTPUT: |
764 | 0 | case IVE_CMD_DEQUEUE_OUTPUT: |
765 | 0 | case IVE_CMD_GET_RECON: |
766 | 0 | break; |
767 | | |
768 | 3.90k | case IV_CMD_RETRIEVE_MEMREC: |
769 | 3.90k | { |
770 | 3.90k | ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip; |
771 | 3.90k | ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op; |
772 | | |
773 | 3.90k | iv_mem_rec_t *ps_mem_rec = NULL; |
774 | | |
775 | 3.90k | ps_op->s_ive_op.u4_error_code = 0; |
776 | | |
777 | 3.90k | if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_retrieve_mem_rec_ip_t)) |
778 | 0 | { |
779 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
780 | 0 | ps_op->s_ive_op.u4_error_code |= |
781 | 0 | IVE_ERR_IP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT; |
782 | 0 | return (IV_FAIL); |
783 | 0 | } |
784 | | |
785 | 3.90k | if (ps_op->s_ive_op.u4_size != sizeof(ih264e_retrieve_mem_rec_op_t)) |
786 | 0 | { |
787 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
788 | 0 | ps_op->s_ive_op.u4_error_code |= |
789 | 0 | IVE_ERR_OP_RETRIEVE_MEM_REC_API_STRUCT_SIZE_INCORRECT; |
790 | 0 | return (IV_FAIL); |
791 | 0 | } |
792 | | |
793 | 3.90k | if (NULL == ps_ip->s_ive_ip.ps_mem_rec) |
794 | 0 | { |
795 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
796 | 0 | ps_op->s_ive_op.u4_error_code |= |
797 | 0 | IVE_ERR_FILL_NUM_MEM_RECS_POINTER_NULL; |
798 | 0 | return (IV_FAIL); |
799 | 0 | } |
800 | | |
801 | 3.90k | ps_mem_rec = ps_ip->s_ive_ip.ps_mem_rec; |
802 | | |
803 | | /* check memrecords sizes are correct */ |
804 | 203k | for (i = 0; i < MEM_REC_CNT; i++) |
805 | 199k | { |
806 | 199k | if (ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t)) |
807 | 0 | { |
808 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
809 | 0 | ps_op->s_ive_op.u4_error_code |= |
810 | 0 | IVE_ERR_MEM_REC_STRUCT_SIZE_INCORRECT; |
811 | 0 | return IV_FAIL; |
812 | 0 | } |
813 | 199k | } |
814 | 3.90k | break; |
815 | 3.90k | } |
816 | | |
817 | 66.0k | case IVE_CMD_VIDEO_ENCODE: |
818 | 66.0k | { |
819 | 66.0k | ih264e_video_encode_ip_t *ps_ip = pv_api_ip; |
820 | 66.0k | ih264e_video_encode_op_t *ps_op = pv_api_op; |
821 | | |
822 | 66.0k | if (ps_ip->s_ive_ip.u4_size != sizeof(ih264e_video_encode_ip_t)) |
823 | 0 | { |
824 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
825 | 0 | ps_op->s_ive_op.u4_error_code |= |
826 | 0 | IVE_ERR_IP_ENCODE_API_STRUCT_SIZE_INCORRECT; |
827 | 0 | return (IV_FAIL); |
828 | 0 | } |
829 | | |
830 | 66.0k | if (ps_op->s_ive_op.u4_size != sizeof(ih264e_video_encode_op_t)) |
831 | 0 | { |
832 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
833 | 0 | ps_op->s_ive_op.u4_error_code |= |
834 | 0 | IVE_ERR_OP_ENCODE_API_STRUCT_SIZE_INCORRECT; |
835 | 0 | return (IV_FAIL); |
836 | 0 | } |
837 | | |
838 | 66.0k | break; |
839 | 66.0k | } |
840 | | |
841 | 88.6k | case IVE_CMD_VIDEO_CTL: |
842 | 88.6k | { |
843 | | /* ptr to input structure */ |
844 | 88.6k | WORD32 *pu4_ptr_cmd = pv_api_ip; |
845 | | |
846 | | /* sub command */ |
847 | 88.6k | WORD32 sub_command = pu4_ptr_cmd[2]; |
848 | | |
849 | 88.6k | switch (sub_command) |
850 | 88.6k | { |
851 | 3.90k | case IVE_CMD_CTL_SETDEFAULT: |
852 | 3.90k | { |
853 | 3.90k | ih264e_ctl_setdefault_ip_t *ps_ip = pv_api_ip; |
854 | 3.90k | ih264e_ctl_setdefault_op_t *ps_op = pv_api_op; |
855 | | |
856 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
857 | 3.90k | != sizeof(ih264e_ctl_setdefault_ip_t)) |
858 | 0 | { |
859 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
860 | 0 | << IVE_UNSUPPORTEDPARAM; |
861 | 0 | ps_op->s_ive_op.u4_error_code |= |
862 | 0 | IVE_ERR_IP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT; |
863 | 0 | return IV_FAIL; |
864 | 0 | } |
865 | | |
866 | 3.90k | if (ps_op->s_ive_op.u4_size |
867 | 3.90k | != sizeof(ih264e_ctl_setdefault_op_t)) |
868 | 0 | { |
869 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
870 | 0 | << IVE_UNSUPPORTEDPARAM; |
871 | 0 | ps_op->s_ive_op.u4_error_code |= |
872 | 0 | IVE_ERR_OP_CTL_SETDEF_API_STRUCT_SIZE_INCORRECT; |
873 | 0 | return IV_FAIL; |
874 | 0 | } |
875 | 3.90k | break; |
876 | 3.90k | } |
877 | | |
878 | 3.90k | case IVE_CMD_CTL_GETBUFINFO: |
879 | 3.90k | { |
880 | 3.90k | codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle); |
881 | | |
882 | 3.90k | ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip; |
883 | 3.90k | ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op; |
884 | | |
885 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
886 | 3.90k | != sizeof(ih264e_ctl_getbufinfo_ip_t)) |
887 | 0 | { |
888 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
889 | 0 | << IVE_UNSUPPORTEDPARAM; |
890 | 0 | ps_op->s_ive_op.u4_error_code |= |
891 | 0 | IVE_ERR_IP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT; |
892 | 0 | return IV_FAIL; |
893 | 0 | } |
894 | | |
895 | 3.90k | if (ps_op->s_ive_op.u4_size |
896 | 3.90k | != sizeof(ih264e_ctl_getbufinfo_op_t)) |
897 | 0 | { |
898 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
899 | 0 | << IVE_UNSUPPORTEDPARAM; |
900 | 0 | ps_op->s_ive_op.u4_error_code |= |
901 | 0 | IVE_ERR_OP_CTL_GETBUFINFO_API_STRUCT_SIZE_INCORRECT; |
902 | 0 | return IV_FAIL; |
903 | 0 | } |
904 | | |
905 | 3.90k | if (ps_ip->s_ive_ip.u4_max_wd < MIN_WD) |
906 | 46 | { |
907 | 46 | ps_op->s_ive_op.u4_error_code |= 1 |
908 | 46 | << IVE_UNSUPPORTEDPARAM; |
909 | 46 | ps_op->s_ive_op.u4_error_code |= |
910 | 46 | IH264E_WIDTH_NOT_SUPPORTED; |
911 | 46 | return (IV_FAIL); |
912 | 46 | } |
913 | | |
914 | 3.86k | if (ps_ip->s_ive_ip.u4_max_wd > ps_codec->s_cfg.u4_max_wd) |
915 | 0 | { |
916 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
917 | 0 | << IVE_UNSUPPORTEDPARAM; |
918 | 0 | ps_op->s_ive_op.u4_error_code |= |
919 | 0 | IH264E_WIDTH_NOT_SUPPORTED; |
920 | 0 | return (IV_FAIL); |
921 | 0 | } |
922 | | |
923 | 3.86k | if (ps_ip->s_ive_ip.u4_max_ht < MIN_HT) |
924 | 12 | { |
925 | 12 | ps_op->s_ive_op.u4_error_code |= 1 |
926 | 12 | << IVE_UNSUPPORTEDPARAM; |
927 | 12 | ps_op->s_ive_op.u4_error_code |= |
928 | 12 | IH264E_HEIGHT_NOT_SUPPORTED; |
929 | 12 | return (IV_FAIL); |
930 | 12 | } |
931 | | |
932 | 3.84k | if (ps_ip->s_ive_ip.u4_max_ht > ps_codec->s_cfg.u4_max_ht) |
933 | 0 | { |
934 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
935 | 0 | << IVE_UNSUPPORTEDPARAM; |
936 | 0 | ps_op->s_ive_op.u4_error_code |= |
937 | 0 | IH264E_HEIGHT_NOT_SUPPORTED; |
938 | 0 | return (IV_FAIL); |
939 | 0 | } |
940 | | |
941 | 3.84k | if ((ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420P) |
942 | 2.27k | && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_422ILE) |
943 | 1.75k | && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_UV) |
944 | 1.03k | && (ps_ip->s_ive_ip.e_inp_color_fmt != IV_YUV_420SP_VU)) |
945 | 0 | { |
946 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
947 | 0 | << IVE_UNSUPPORTEDPARAM; |
948 | 0 | ps_op->s_ive_op.u4_error_code |= |
949 | 0 | IH264E_INPUT_CHROMA_FORMAT_NOT_SUPPORTED; |
950 | 0 | return (IV_FAIL); |
951 | 0 | } |
952 | 3.84k | break; |
953 | 3.84k | } |
954 | | |
955 | 3.90k | case IVE_CMD_CTL_GETVERSION: |
956 | 3.90k | { |
957 | 3.90k | ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip; |
958 | 3.90k | ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op; |
959 | | |
960 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
961 | 3.90k | != sizeof(ih264e_ctl_getversioninfo_ip_t)) |
962 | 0 | { |
963 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
964 | 0 | << IVE_UNSUPPORTEDPARAM; |
965 | 0 | ps_op->s_ive_op.u4_error_code |= |
966 | 0 | IVE_ERR_IP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT; |
967 | 0 | return IV_FAIL; |
968 | 0 | } |
969 | | |
970 | 3.90k | if (ps_op->s_ive_op.u4_size |
971 | 3.90k | != sizeof(ih264e_ctl_getversioninfo_op_t)) |
972 | 0 | { |
973 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
974 | 0 | << IVE_UNSUPPORTEDPARAM; |
975 | 0 | ps_op->s_ive_op.u4_error_code |= |
976 | 0 | IVE_ERR_OP_CTL_GETVERSION_API_STRUCT_SIZE_INCORRECT; |
977 | 0 | return IV_FAIL; |
978 | 0 | } |
979 | | |
980 | 3.90k | if (ps_ip->s_ive_ip.pu1_version == NULL) |
981 | 0 | { |
982 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
983 | 0 | << IVE_UNSUPPORTEDPARAM; |
984 | 0 | ps_op->s_ive_op.u4_error_code |= |
985 | 0 | IVE_ERR_CTL_GET_VERSION_BUFFER_IS_NULL; |
986 | 0 | return IV_FAIL; |
987 | 0 | } |
988 | | |
989 | 3.90k | break; |
990 | 3.90k | } |
991 | | |
992 | 3.90k | case IVE_CMD_CTL_FLUSH: |
993 | 0 | { |
994 | 0 | ih264e_ctl_flush_ip_t *ps_ip = pv_api_ip; |
995 | 0 | ih264e_ctl_flush_op_t *ps_op = pv_api_op; |
996 | |
|
997 | 0 | if (ps_ip->s_ive_ip.u4_size |
998 | 0 | != sizeof(ih264e_ctl_flush_ip_t)) |
999 | 0 | { |
1000 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1001 | 0 | << IVE_UNSUPPORTEDPARAM; |
1002 | 0 | ps_op->s_ive_op.u4_error_code |= |
1003 | 0 | IVE_ERR_IP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT; |
1004 | 0 | return IV_FAIL; |
1005 | 0 | } |
1006 | | |
1007 | 0 | if (ps_op->s_ive_op.u4_size |
1008 | 0 | != sizeof(ih264e_ctl_flush_op_t)) |
1009 | 0 | { |
1010 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1011 | 0 | << IVE_UNSUPPORTEDPARAM; |
1012 | 0 | ps_op->s_ive_op.u4_error_code |= |
1013 | 0 | IVE_ERR_OP_CTL_FLUSH_API_STRUCT_SIZE_INCORRECT; |
1014 | 0 | return IV_FAIL; |
1015 | 0 | } |
1016 | | |
1017 | 0 | break; |
1018 | 0 | } |
1019 | | |
1020 | 0 | case IVE_CMD_CTL_RESET: |
1021 | 0 | { |
1022 | 0 | ih264e_ctl_reset_ip_t *ps_ip = pv_api_ip; |
1023 | 0 | ih264e_ctl_reset_op_t *ps_op = pv_api_op; |
1024 | |
|
1025 | 0 | if (ps_ip->s_ive_ip.u4_size |
1026 | 0 | != sizeof(ih264e_ctl_reset_ip_t)) |
1027 | 0 | { |
1028 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1029 | 0 | << IVE_UNSUPPORTEDPARAM; |
1030 | 0 | ps_op->s_ive_op.u4_error_code |= |
1031 | 0 | IVE_ERR_IP_CTL_RESET_API_STRUCT_SIZE_INCORRECT; |
1032 | 0 | return IV_FAIL; |
1033 | 0 | } |
1034 | | |
1035 | 0 | if (ps_op->s_ive_op.u4_size |
1036 | 0 | != sizeof(ih264e_ctl_reset_op_t)) |
1037 | 0 | { |
1038 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1039 | 0 | << IVE_UNSUPPORTEDPARAM; |
1040 | 0 | ps_op->s_ive_op.u4_error_code |= |
1041 | 0 | IVE_ERR_OP_CTL_RESET_API_STRUCT_SIZE_INCORRECT; |
1042 | 0 | return IV_FAIL; |
1043 | 0 | } |
1044 | | |
1045 | 0 | break; |
1046 | 0 | } |
1047 | | |
1048 | 3.90k | case IVE_CMD_CTL_SET_NUM_CORES: |
1049 | 3.90k | { |
1050 | 3.90k | ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip; |
1051 | 3.90k | ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op; |
1052 | | |
1053 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
1054 | 3.90k | != sizeof(ih264e_ctl_set_num_cores_ip_t)) |
1055 | 0 | { |
1056 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1057 | 0 | << IVE_UNSUPPORTEDPARAM; |
1058 | 0 | ps_op->s_ive_op.u4_error_code |= |
1059 | 0 | IVE_ERR_IP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT; |
1060 | 0 | return IV_FAIL; |
1061 | 0 | } |
1062 | | |
1063 | 3.90k | if (ps_op->s_ive_op.u4_size |
1064 | 3.90k | != sizeof(ih264e_ctl_set_num_cores_op_t)) |
1065 | 0 | { |
1066 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1067 | 0 | << IVE_UNSUPPORTEDPARAM; |
1068 | 0 | ps_op->s_ive_op.u4_error_code |= |
1069 | 0 | IVE_ERR_OP_CTL_SETCORES_API_STRUCT_SIZE_INCORRECT; |
1070 | 0 | return IV_FAIL; |
1071 | 0 | } |
1072 | | |
1073 | 3.90k | if ((ps_ip->s_ive_ip.u4_num_cores < 1) |
1074 | 3.90k | || (ps_ip->s_ive_ip.u4_num_cores > MAX_NUM_CORES)) |
1075 | 0 | { |
1076 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1077 | 0 | << IVE_UNSUPPORTEDPARAM; |
1078 | 0 | ps_op->s_ive_op.u4_error_code |= |
1079 | 0 | IH264E_INVALID_NUM_CORES; |
1080 | 0 | return IV_FAIL; |
1081 | 0 | } |
1082 | | |
1083 | 3.90k | break; |
1084 | 3.90k | } |
1085 | | |
1086 | 3.90k | case IVE_CMD_CTL_SET_DIMENSIONS: |
1087 | 3.90k | { |
1088 | 3.90k | codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle); |
1089 | | |
1090 | 3.90k | ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip; |
1091 | 3.90k | ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op; |
1092 | | |
1093 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
1094 | 3.90k | != sizeof(ih264e_ctl_set_dimensions_ip_t)) |
1095 | 0 | { |
1096 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1097 | 0 | << IVE_UNSUPPORTEDPARAM; |
1098 | 0 | ps_op->s_ive_op.u4_error_code |= |
1099 | 0 | IVE_ERR_IP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT; |
1100 | 0 | return IV_FAIL; |
1101 | 0 | } |
1102 | | |
1103 | 3.90k | if (ps_op->s_ive_op.u4_size |
1104 | 3.90k | != sizeof(ih264e_ctl_set_dimensions_op_t)) |
1105 | 0 | { |
1106 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1107 | 0 | << IVE_UNSUPPORTEDPARAM; |
1108 | 0 | ps_op->s_ive_op.u4_error_code |= |
1109 | 0 | IVE_ERR_OP_CTL_SETDIM_API_STRUCT_SIZE_INCORRECT; |
1110 | 0 | return IV_FAIL; |
1111 | 0 | } |
1112 | | |
1113 | 3.90k | if (ps_ip->s_ive_ip.u4_wd < MIN_WD) |
1114 | 46 | { |
1115 | 46 | ps_op->s_ive_op.u4_error_code |= 1 |
1116 | 46 | << IVE_UNSUPPORTEDPARAM; |
1117 | 46 | ps_op->s_ive_op.u4_error_code |= |
1118 | 46 | IH264E_WIDTH_NOT_SUPPORTED; |
1119 | 46 | return (IV_FAIL); |
1120 | 46 | } |
1121 | | |
1122 | 3.86k | if (ps_ip->s_ive_ip.u4_wd > ps_codec->s_cfg.u4_max_wd) |
1123 | 0 | { |
1124 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1125 | 0 | << IVE_UNSUPPORTEDPARAM; |
1126 | 0 | ps_op->s_ive_op.u4_error_code |= |
1127 | 0 | IH264E_WIDTH_NOT_SUPPORTED; |
1128 | 0 | return (IV_FAIL); |
1129 | 0 | } |
1130 | | |
1131 | 3.86k | if (ps_ip->s_ive_ip.u4_ht < MIN_HT) |
1132 | 12 | { |
1133 | 12 | ps_op->s_ive_op.u4_error_code |= 1 |
1134 | 12 | << IVE_UNSUPPORTEDPARAM; |
1135 | 12 | ps_op->s_ive_op.u4_error_code |= |
1136 | 12 | IH264E_HEIGHT_NOT_SUPPORTED; |
1137 | 12 | return (IV_FAIL); |
1138 | 12 | } |
1139 | | |
1140 | 3.84k | if (ps_ip->s_ive_ip.u4_ht > ps_codec->s_cfg.u4_max_ht) |
1141 | 0 | { |
1142 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1143 | 0 | << IVE_UNSUPPORTEDPARAM; |
1144 | 0 | ps_op->s_ive_op.u4_error_code |= |
1145 | 0 | IH264E_HEIGHT_NOT_SUPPORTED; |
1146 | 0 | return (IV_FAIL); |
1147 | 0 | } |
1148 | | |
1149 | 3.84k | if(ps_ip->s_ive_ip.u4_wd & 1) |
1150 | 44 | { |
1151 | 44 | ps_op->s_ive_op.u4_error_code |= 1 |
1152 | 44 | << IVE_UNSUPPORTEDPARAM; |
1153 | 44 | ps_op->s_ive_op.u4_error_code |= |
1154 | 44 | IH264E_WIDTH_NOT_SUPPORTED; |
1155 | 44 | return (IV_FAIL); |
1156 | 44 | } |
1157 | | |
1158 | 3.80k | if(ps_ip->s_ive_ip.u4_ht & 1) |
1159 | 26 | { |
1160 | 26 | ps_op->s_ive_op.u4_error_code |= 1 |
1161 | 26 | << IVE_UNSUPPORTEDPARAM; |
1162 | 26 | ps_op->s_ive_op.u4_error_code |= |
1163 | 26 | IH264E_HEIGHT_NOT_SUPPORTED; |
1164 | 26 | return (IV_FAIL); |
1165 | 26 | } |
1166 | | |
1167 | 3.77k | break; |
1168 | 3.80k | } |
1169 | | |
1170 | 4.69k | case IVE_CMD_CTL_SET_FRAMERATE: |
1171 | 4.69k | { |
1172 | 4.69k | ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip; |
1173 | 4.69k | ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op; |
1174 | | |
1175 | 4.69k | if (ps_ip->s_ive_ip.u4_size |
1176 | 4.69k | != sizeof(ih264e_ctl_set_frame_rate_ip_t)) |
1177 | 0 | { |
1178 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1179 | 0 | << IVE_UNSUPPORTEDPARAM; |
1180 | 0 | ps_op->s_ive_op.u4_error_code |= |
1181 | 0 | IVE_ERR_IP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT; |
1182 | 0 | return IV_FAIL; |
1183 | 0 | } |
1184 | | |
1185 | 4.69k | if (ps_op->s_ive_op.u4_size |
1186 | 4.69k | != sizeof(ih264e_ctl_set_frame_rate_op_t)) |
1187 | 0 | { |
1188 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1189 | 0 | << IVE_UNSUPPORTEDPARAM; |
1190 | 0 | ps_op->s_ive_op.u4_error_code |= |
1191 | 0 | IVE_ERR_OP_CTL_SETFRAMERATE_API_STRUCT_SIZE_INCORRECT; |
1192 | 0 | return IV_FAIL; |
1193 | 0 | } |
1194 | | |
1195 | 4.69k | if (((ps_ip->s_ive_ip.u4_src_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE) |
1196 | 3.14k | || ((ps_ip->s_ive_ip.u4_tgt_frame_rate * 1000) > DEFAULT_MAX_FRAMERATE)) |
1197 | 1.55k | { |
1198 | 1.55k | ps_op->s_ive_op.u4_error_code |= 1 |
1199 | 1.55k | << IVE_UNSUPPORTEDPARAM; |
1200 | 1.55k | ps_op->s_ive_op.u4_error_code |= |
1201 | 1.55k | IH264E_FRAME_RATE_NOT_SUPPORTED; |
1202 | 1.55k | return (IV_FAIL); |
1203 | 1.55k | } |
1204 | | |
1205 | 3.14k | if ((ps_ip->s_ive_ip.u4_src_frame_rate == 0) |
1206 | 2.24k | || (ps_ip->s_ive_ip.u4_tgt_frame_rate == 0)) |
1207 | 896 | { |
1208 | 896 | ps_op->s_ive_op.u4_error_code |= 1 |
1209 | 896 | << IVE_UNSUPPORTEDPARAM; |
1210 | 896 | ps_op->s_ive_op.u4_error_code |= |
1211 | 896 | IH264E_FRAME_RATE_NOT_SUPPORTED; |
1212 | 896 | return (IV_FAIL); |
1213 | 896 | } |
1214 | | |
1215 | 2.24k | if (ps_ip->s_ive_ip.u4_tgt_frame_rate |
1216 | 2.24k | > ps_ip->s_ive_ip.u4_src_frame_rate) |
1217 | 0 | { |
1218 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1219 | 0 | << IVE_UNSUPPORTEDPARAM; |
1220 | 0 | ps_op->s_ive_op.u4_error_code |= |
1221 | 0 | IH264E_TGT_FRAME_RATE_EXCEEDS_SRC_FRAME_RATE; |
1222 | 0 | return (IV_FAIL); |
1223 | 0 | } |
1224 | | |
1225 | 2.24k | break; |
1226 | 2.24k | } |
1227 | | |
1228 | 4.86k | case IVE_CMD_CTL_SET_BITRATE: |
1229 | 4.86k | { |
1230 | 4.86k | ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip; |
1231 | 4.86k | ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op; |
1232 | | |
1233 | 4.86k | if (ps_ip->s_ive_ip.u4_size |
1234 | 4.86k | != sizeof(ih264e_ctl_set_bitrate_ip_t)) |
1235 | 0 | { |
1236 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1237 | 0 | << IVE_UNSUPPORTEDPARAM; |
1238 | 0 | ps_op->s_ive_op.u4_error_code |= |
1239 | 0 | IVE_ERR_IP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT; |
1240 | 0 | return IV_FAIL; |
1241 | 0 | } |
1242 | | |
1243 | 4.86k | if (ps_op->s_ive_op.u4_size |
1244 | 4.86k | != sizeof(ih264e_ctl_set_bitrate_op_t)) |
1245 | 0 | { |
1246 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1247 | 0 | << IVE_UNSUPPORTEDPARAM; |
1248 | 0 | ps_op->s_ive_op.u4_error_code |= |
1249 | 0 | IVE_ERR_OP_CTL_SETBITRATE_API_STRUCT_SIZE_INCORRECT; |
1250 | 0 | return IV_FAIL; |
1251 | 0 | } |
1252 | | |
1253 | 4.86k | if ((ps_ip->s_ive_ip.u4_target_bitrate > DEFAULT_MAX_BITRATE) |
1254 | 4.86k | || (ps_ip->s_ive_ip.u4_target_bitrate == 0)) |
1255 | 395 | { |
1256 | 395 | ps_op->s_ive_op.u4_error_code |= 1 |
1257 | 395 | << IVE_UNSUPPORTEDPARAM; |
1258 | 395 | ps_op->s_ive_op.u4_error_code |= |
1259 | 395 | IH264E_BITRATE_NOT_SUPPORTED; |
1260 | 395 | return (IV_FAIL); |
1261 | 395 | } |
1262 | | |
1263 | 4.47k | break; |
1264 | 4.86k | } |
1265 | | |
1266 | 4.47k | case IVE_CMD_CTL_SET_FRAMETYPE: |
1267 | 937 | { |
1268 | 937 | ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip; |
1269 | 937 | ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op; |
1270 | | |
1271 | 937 | if (ps_ip->s_ive_ip.u4_size |
1272 | 937 | != sizeof(ih264e_ctl_set_frame_type_ip_t)) |
1273 | 0 | { |
1274 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1275 | 0 | << IVE_UNSUPPORTEDPARAM; |
1276 | 0 | ps_op->s_ive_op.u4_error_code |= |
1277 | 0 | IVE_ERR_IP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT; |
1278 | 0 | return IV_FAIL; |
1279 | 0 | } |
1280 | | |
1281 | 937 | if (ps_op->s_ive_op.u4_size |
1282 | 937 | != sizeof(ih264e_ctl_set_frame_type_op_t)) |
1283 | 0 | { |
1284 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1285 | 0 | << IVE_UNSUPPORTEDPARAM; |
1286 | 0 | ps_op->s_ive_op.u4_error_code |= |
1287 | 0 | IVE_ERR_OP_CTL_SETFRAMETYPE_API_STRUCT_SIZE_INCORRECT; |
1288 | 0 | return IV_FAIL; |
1289 | 0 | } |
1290 | | |
1291 | 937 | if ((ps_ip->s_ive_ip.e_frame_type != IV_NA_FRAME) |
1292 | 937 | && (ps_ip->s_ive_ip.e_frame_type != IV_I_FRAME) |
1293 | 937 | && (ps_ip->s_ive_ip.e_frame_type != IV_P_FRAME) |
1294 | 937 | && (ps_ip->s_ive_ip.e_frame_type != IV_IDR_FRAME)) |
1295 | 0 | { |
1296 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1297 | 0 | << IVE_UNSUPPORTEDPARAM; |
1298 | 0 | ps_op->s_ive_op.u4_error_code |= |
1299 | 0 | IH264E_INVALID_FORCE_FRAME_INPUT; |
1300 | 0 | return IV_FAIL; |
1301 | 0 | } |
1302 | 937 | break; |
1303 | 937 | } |
1304 | | |
1305 | 3.90k | case IVE_CMD_CTL_SET_ME_PARAMS: |
1306 | 3.90k | { |
1307 | 3.90k | codec_t *ps_codec = (codec_t *) (ps_handle->pv_codec_handle); |
1308 | | |
1309 | 3.90k | ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip; |
1310 | 3.90k | ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op; |
1311 | | |
1312 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
1313 | 3.90k | != sizeof(ih264e_ctl_set_me_params_ip_t)) |
1314 | 0 | { |
1315 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1316 | 0 | << IVE_UNSUPPORTEDPARAM; |
1317 | 0 | ps_op->s_ive_op.u4_error_code |= |
1318 | 0 | IVE_ERR_IP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT; |
1319 | 0 | return IV_FAIL; |
1320 | 0 | } |
1321 | | |
1322 | 3.90k | if (ps_op->s_ive_op.u4_size |
1323 | 3.90k | != sizeof(ih264e_ctl_set_me_params_op_t)) |
1324 | 0 | { |
1325 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1326 | 0 | << IVE_UNSUPPORTEDPARAM; |
1327 | 0 | ps_op->s_ive_op.u4_error_code |= |
1328 | 0 | IVE_ERR_OP_CTL_SETMEPARAMS_API_STRUCT_SIZE_INCORRECT; |
1329 | 0 | return IV_FAIL; |
1330 | 0 | } |
1331 | | |
1332 | 3.90k | if (ps_ip->s_ive_ip.u4_me_speed_preset != DMND_SRCH) |
1333 | 2.85k | { |
1334 | 2.85k | ps_op->s_ive_op.u4_error_code |= 1 |
1335 | 2.85k | << IVE_UNSUPPORTEDPARAM; |
1336 | 2.85k | ps_op->s_ive_op.u4_error_code |= |
1337 | 2.85k | IH264E_INVALID_ME_SPEED_PRESET; |
1338 | 2.85k | return IV_FAIL; |
1339 | 2.85k | } |
1340 | | |
1341 | 1.05k | if ((ps_ip->s_ive_ip.u4_enable_hpel != 0) |
1342 | 662 | && (ps_ip->s_ive_ip.u4_enable_hpel != 1)) |
1343 | 0 | { |
1344 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1345 | 0 | << IVE_UNSUPPORTEDPARAM; |
1346 | 0 | ps_op->s_ive_op.u4_error_code |= |
1347 | 0 | IH264E_INVALID_HALFPEL_OPTION; |
1348 | 0 | return IV_FAIL; |
1349 | 0 | } |
1350 | | |
1351 | 1.05k | if ((ps_ip->s_ive_ip.u4_enable_qpel != 0) |
1352 | 626 | && (ps_ip->s_ive_ip.u4_enable_qpel != 1)) |
1353 | 0 | { |
1354 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1355 | 0 | << IVE_UNSUPPORTEDPARAM; |
1356 | 0 | ps_op->s_ive_op.u4_error_code |= |
1357 | 0 | IH264E_INVALID_QPEL_OPTION; |
1358 | 0 | return IV_FAIL; |
1359 | 0 | } |
1360 | | |
1361 | 1.05k | if ((ps_ip->s_ive_ip.u4_enable_fast_sad != 0) |
1362 | 0 | && (ps_ip->s_ive_ip.u4_enable_fast_sad != 1)) |
1363 | 0 | { |
1364 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1365 | 0 | << IVE_UNSUPPORTEDPARAM; |
1366 | 0 | ps_op->s_ive_op.u4_error_code |= |
1367 | 0 | IH264E_INVALID_FAST_SAD_OPTION; |
1368 | 0 | return IV_FAIL; |
1369 | 0 | } |
1370 | | |
1371 | 1.05k | if (ps_ip->s_ive_ip.u4_enable_alt_ref > 255) |
1372 | 0 | { |
1373 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1374 | 0 | << IVE_UNSUPPORTEDPARAM; |
1375 | 0 | ps_op->s_ive_op.u4_error_code |= |
1376 | 0 | IH264E_INVALID_ALT_REF_OPTION; |
1377 | 0 | return IV_FAIL; |
1378 | 0 | } |
1379 | | |
1380 | 1.05k | if (ps_ip->s_ive_ip.u4_srch_rng_x |
1381 | 1.05k | > ps_codec->s_cfg.u4_max_srch_rng_x) |
1382 | 0 | { |
1383 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1384 | 0 | << IVE_UNSUPPORTEDPARAM; |
1385 | 0 | ps_op->s_ive_op.u4_error_code |= |
1386 | 0 | IH264E_HORIZONTAL_SEARCH_RANGE_NOT_SUPPORTED; |
1387 | 0 | return (IV_FAIL); |
1388 | 0 | } |
1389 | | |
1390 | 1.05k | if (ps_ip->s_ive_ip.u4_srch_rng_y |
1391 | 1.05k | > ps_codec->s_cfg.u4_max_srch_rng_y) |
1392 | 0 | { |
1393 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1394 | 0 | << IVE_UNSUPPORTEDPARAM; |
1395 | 0 | ps_op->s_ive_op.u4_error_code |= |
1396 | 0 | IH264E_VERTICAL_SEARCH_RANGE_NOT_SUPPORTED; |
1397 | 0 | return (IV_FAIL); |
1398 | 0 | } |
1399 | | |
1400 | 1.05k | break; |
1401 | 1.05k | } |
1402 | | |
1403 | 3.90k | case IVE_CMD_CTL_SET_IPE_PARAMS: |
1404 | 3.90k | { |
1405 | 3.90k | ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip; |
1406 | 3.90k | ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op; |
1407 | | |
1408 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
1409 | 3.90k | != sizeof(ih264e_ctl_set_ipe_params_ip_t)) |
1410 | 0 | { |
1411 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1412 | 0 | << IVE_UNSUPPORTEDPARAM; |
1413 | 0 | ps_op->s_ive_op.u4_error_code |= |
1414 | 0 | IVE_ERR_IP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT; |
1415 | 0 | return IV_FAIL; |
1416 | 0 | } |
1417 | | |
1418 | 3.90k | if (ps_op->s_ive_op.u4_size |
1419 | 3.90k | != sizeof(ih264e_ctl_set_ipe_params_op_t)) |
1420 | 0 | { |
1421 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1422 | 0 | << IVE_UNSUPPORTEDPARAM; |
1423 | 0 | ps_op->s_ive_op.u4_error_code |= |
1424 | 0 | IVE_ERR_OP_CTL_SETIPEPARAMS_API_STRUCT_SIZE_INCORRECT; |
1425 | 0 | return IV_FAIL; |
1426 | 0 | } |
1427 | | |
1428 | 3.90k | if ((ps_ip->s_ive_ip.u4_enable_intra_4x4 != 0) |
1429 | 1.60k | && (ps_ip->s_ive_ip.u4_enable_intra_4x4 != 1)) |
1430 | 0 | { |
1431 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1432 | 0 | << IVE_UNSUPPORTEDPARAM; |
1433 | 0 | ps_op->s_ive_op.u4_error_code |= |
1434 | 0 | IH264E_INVALID_INTRA4x4_OPTION; |
1435 | 0 | return IV_FAIL; |
1436 | 0 | } |
1437 | | |
1438 | 3.90k | if ((ps_ip->s_ive_ip.u4_constrained_intra_pred != 0) |
1439 | 2.00k | && (ps_ip->s_ive_ip.u4_constrained_intra_pred != 1)) |
1440 | 0 | { |
1441 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1442 | 0 | << IVE_UNSUPPORTEDPARAM; |
1443 | 0 | ps_op->s_ive_op.u4_error_code |= |
1444 | 0 | IH264E_INVALID_CONSTRAINED_INTRA_PREDICTION_MODE; |
1445 | 0 | return IV_FAIL; |
1446 | 0 | } |
1447 | | |
1448 | 3.90k | if ((ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_CONFIG) |
1449 | 2.63k | && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_SLOWEST) |
1450 | 1.80k | && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_NORMAL) |
1451 | 1.08k | && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FAST) |
1452 | 548 | && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_HIGH_SPEED) |
1453 | 240 | && (ps_ip->s_ive_ip.u4_enc_speed_preset != IVE_FASTEST)) |
1454 | 0 | { |
1455 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1456 | 0 | << IVE_UNSUPPORTEDPARAM; |
1457 | 0 | ps_op->s_ive_op.u4_error_code |= |
1458 | 0 | IH264E_INVALID_ENC_SPEED_PRESET; |
1459 | 0 | return IV_FAIL; |
1460 | 0 | } |
1461 | | |
1462 | 3.90k | break; |
1463 | 3.90k | } |
1464 | | |
1465 | 3.90k | case IVE_CMD_CTL_SET_GOP_PARAMS: |
1466 | 3.90k | { |
1467 | 3.90k | ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip; |
1468 | 3.90k | ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op; |
1469 | | |
1470 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
1471 | 3.90k | != sizeof(ih264e_ctl_set_gop_params_ip_t)) |
1472 | 0 | { |
1473 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1474 | 0 | << IVE_UNSUPPORTEDPARAM; |
1475 | 0 | ps_op->s_ive_op.u4_error_code |= |
1476 | 0 | IVE_ERR_IP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT; |
1477 | 0 | return IV_FAIL; |
1478 | 0 | } |
1479 | | |
1480 | 3.90k | if (ps_op->s_ive_op.u4_size |
1481 | 3.90k | != sizeof(ih264e_ctl_set_gop_params_op_t)) |
1482 | 0 | { |
1483 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1484 | 0 | << IVE_UNSUPPORTEDPARAM; |
1485 | 0 | ps_op->s_ive_op.u4_error_code |= |
1486 | 0 | IVE_ERR_OP_CTL_SETGOPPARAMS_API_STRUCT_SIZE_INCORRECT; |
1487 | 0 | return IV_FAIL; |
1488 | 0 | } |
1489 | | |
1490 | 3.90k | if ((ps_ip->s_ive_ip.u4_i_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE) |
1491 | 3.90k | || (ps_ip->s_ive_ip.u4_i_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE)) |
1492 | 0 | { |
1493 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1494 | 0 | << IVE_UNSUPPORTEDPARAM; |
1495 | 0 | ps_op->s_ive_op.u4_error_code |= |
1496 | 0 | IH264E_INVALID_INTRA_FRAME_INTERVAL; |
1497 | 0 | return IV_FAIL; |
1498 | 0 | } |
1499 | | |
1500 | 3.90k | if ((ps_ip->s_ive_ip.u4_idr_frm_interval < DEFAULT_MIN_INTRA_FRAME_RATE) |
1501 | 3.90k | || (ps_ip->s_ive_ip.u4_idr_frm_interval > DEFAULT_MAX_INTRA_FRAME_RATE)) |
1502 | 0 | { |
1503 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1504 | 0 | << IVE_UNSUPPORTEDPARAM; |
1505 | 0 | ps_op->s_ive_op.u4_error_code |= |
1506 | 0 | IH264E_INVALID_IDR_FRAME_INTERVAL; |
1507 | 0 | return IV_FAIL; |
1508 | 0 | } |
1509 | | |
1510 | 3.90k | if((ps_ip->s_ive_ip.u4_idr_frm_interval > ps_ip->s_ive_ip.u4_i_frm_interval) && |
1511 | 1.09k | (ps_ip->s_ive_ip.u4_idr_frm_interval % ps_ip->s_ive_ip.u4_i_frm_interval != 0)) |
1512 | 732 | { |
1513 | 732 | ps_op->s_ive_op.u4_error_code |= 1 |
1514 | 732 | << IVE_UNSUPPORTEDPARAM; |
1515 | 732 | ps_op->s_ive_op.u4_error_code |= |
1516 | 732 | IH264E_INVALID_INTRA_FRAME_INTERVAL; |
1517 | 732 | return IV_FAIL; |
1518 | 732 | } |
1519 | | |
1520 | 3.17k | break; |
1521 | 3.90k | } |
1522 | | |
1523 | 3.90k | case IVE_CMD_CTL_SET_DEBLOCK_PARAMS: |
1524 | 3.90k | { |
1525 | 3.90k | ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip; |
1526 | 3.90k | ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op; |
1527 | | |
1528 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
1529 | 3.90k | != sizeof(ih264e_ctl_set_deblock_params_ip_t)) |
1530 | 0 | { |
1531 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1532 | 0 | << IVE_UNSUPPORTEDPARAM; |
1533 | 0 | ps_op->s_ive_op.u4_error_code |= |
1534 | 0 | IVE_ERR_IP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT; |
1535 | 0 | return IV_FAIL; |
1536 | 0 | } |
1537 | | |
1538 | 3.90k | if (ps_op->s_ive_op.u4_size |
1539 | 3.90k | != sizeof(ih264e_ctl_set_deblock_params_op_t)) |
1540 | 0 | { |
1541 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1542 | 0 | << IVE_UNSUPPORTEDPARAM; |
1543 | 0 | ps_op->s_ive_op.u4_error_code |= |
1544 | 0 | IVE_ERR_OP_CTL_SETDEBLKPARAMS_API_STRUCT_SIZE_INCORRECT; |
1545 | 0 | return IV_FAIL; |
1546 | 0 | } |
1547 | | |
1548 | 3.90k | if ((ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_0) |
1549 | 2.21k | && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_2) |
1550 | 1.57k | && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_3) |
1551 | 673 | && (ps_ip->s_ive_ip.u4_disable_deblock_level != DISABLE_DEBLK_LEVEL_4)) |
1552 | 673 | { |
1553 | 673 | ps_op->s_ive_op.u4_error_code |= 1 |
1554 | 673 | << IVE_UNSUPPORTEDPARAM; |
1555 | 673 | ps_op->s_ive_op.u4_error_code |= |
1556 | 673 | IH264E_INVALID_DEBLOCKING_TYPE_INPUT; |
1557 | 673 | return IV_FAIL; |
1558 | 673 | } |
1559 | | |
1560 | 3.23k | break; |
1561 | 3.90k | } |
1562 | | |
1563 | 3.90k | case IVE_CMD_CTL_SET_QP: |
1564 | 3.90k | { |
1565 | 3.90k | ih264e_ctl_set_qp_ip_t *ps_ip = pv_api_ip; |
1566 | 3.90k | ih264e_ctl_set_qp_op_t *ps_op = pv_api_op; |
1567 | | |
1568 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
1569 | 3.90k | != sizeof(ih264e_ctl_set_qp_ip_t)) |
1570 | 0 | { |
1571 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1572 | 0 | << IVE_UNSUPPORTEDPARAM; |
1573 | 0 | ps_op->s_ive_op.u4_error_code |= |
1574 | 0 | IVE_ERR_IP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT; |
1575 | 0 | return IV_FAIL; |
1576 | 0 | } |
1577 | | |
1578 | 3.90k | if (ps_op->s_ive_op.u4_size |
1579 | 3.90k | != sizeof(ih264e_ctl_set_qp_op_t)) |
1580 | 0 | { |
1581 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1582 | 0 | << IVE_UNSUPPORTEDPARAM; |
1583 | 0 | ps_op->s_ive_op.u4_error_code |= |
1584 | 0 | IVE_ERR_OP_CTL_SETQPPARAMS_API_STRUCT_SIZE_INCORRECT; |
1585 | 0 | return IV_FAIL; |
1586 | 0 | } |
1587 | | |
1588 | 3.90k | if ((ps_ip->s_ive_ip.u4_i_qp_max > MAX_H264_QP) |
1589 | 3.90k | || (ps_ip->s_ive_ip.u4_p_qp_max > MAX_H264_QP) |
1590 | 3.90k | || (ps_ip->s_ive_ip.u4_b_qp_max > MAX_H264_QP)) |
1591 | 0 | { |
1592 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1593 | 0 | << IVE_UNSUPPORTEDPARAM; |
1594 | 0 | ps_op->s_ive_op.u4_error_code |= |
1595 | 0 | IH264E_INVALID_MAX_FRAME_QP; |
1596 | 0 | return IV_FAIL; |
1597 | 0 | } |
1598 | | |
1599 | | /* We donot support QP < 4 */ |
1600 | 3.90k | if ((ps_ip->s_ive_ip.u4_i_qp_min < 4) |
1601 | 3.90k | || (ps_ip->s_ive_ip.u4_p_qp_min < 4) |
1602 | 3.90k | || (ps_ip->s_ive_ip.u4_b_qp_min < 4) |
1603 | 3.90k | || (ps_ip->s_ive_ip.u4_i_qp_min > ps_ip->s_ive_ip.u4_i_qp_max) |
1604 | 3.90k | || (ps_ip->s_ive_ip.u4_p_qp_min > ps_ip->s_ive_ip.u4_p_qp_max) |
1605 | 3.90k | || (ps_ip->s_ive_ip.u4_b_qp_min > ps_ip->s_ive_ip.u4_b_qp_max)) |
1606 | 0 | { |
1607 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1608 | 0 | << IVE_UNSUPPORTEDPARAM; |
1609 | 0 | ps_op->s_ive_op.u4_error_code |= |
1610 | 0 | IH264E_INVALID_MIN_FRAME_QP; |
1611 | 0 | return IV_FAIL; |
1612 | 0 | } |
1613 | | |
1614 | 3.90k | if ((ps_ip->s_ive_ip.u4_i_qp > ps_ip->s_ive_ip.u4_i_qp_max) |
1615 | 3.90k | || (ps_ip->s_ive_ip.u4_p_qp > ps_ip->s_ive_ip.u4_p_qp_max) |
1616 | 3.90k | || (ps_ip->s_ive_ip.u4_b_qp > ps_ip->s_ive_ip.u4_b_qp_max) |
1617 | 3.90k | || (ps_ip->s_ive_ip.u4_i_qp < ps_ip->s_ive_ip.u4_i_qp_min) |
1618 | 3.90k | || (ps_ip->s_ive_ip.u4_p_qp < ps_ip->s_ive_ip.u4_p_qp_min) |
1619 | 3.90k | || (ps_ip->s_ive_ip.u4_b_qp < ps_ip->s_ive_ip.u4_b_qp_min)) |
1620 | 0 | { |
1621 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
1622 | 0 | << IVE_UNSUPPORTEDPARAM; |
1623 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_INVALID_INIT_QP; |
1624 | 0 | return IV_FAIL; |
1625 | 0 | } |
1626 | | |
1627 | 3.90k | break; |
1628 | 3.90k | } |
1629 | | |
1630 | 3.90k | case IVE_CMD_CTL_SET_VUI_PARAMS: |
1631 | 3.90k | { |
1632 | 3.90k | ih264e_vui_ip_t *ps_ip = pv_api_ip; |
1633 | 3.90k | ih264e_vui_op_t *ps_op = pv_api_op; |
1634 | | |
1635 | 3.90k | if(ps_ip->u4_size != sizeof(ih264e_vui_ip_t)) |
1636 | 0 | { |
1637 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1638 | 0 | ps_op->u4_error_code |= |
1639 | 0 | IVE_ERR_IP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT; |
1640 | 0 | return IV_FAIL; |
1641 | 0 | } |
1642 | | |
1643 | 3.90k | if(ps_op->u4_size != sizeof(ih264e_vui_op_t)) |
1644 | 0 | { |
1645 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1646 | 0 | ps_op->u4_error_code |= |
1647 | 0 | IVE_ERR_OP_CTL_SET_VUI_STRUCT_SIZE_INCORRECT; |
1648 | 0 | return IV_FAIL; |
1649 | 0 | } |
1650 | | |
1651 | 3.90k | break; |
1652 | 3.90k | } |
1653 | | |
1654 | 3.90k | case IVE_CMD_CTL_SET_SEI_MDCV_PARAMS: |
1655 | 3.90k | { |
1656 | 3.90k | ih264e_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip; |
1657 | 3.90k | ih264e_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op; |
1658 | | |
1659 | 3.90k | if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_mdcv_params_ip_t)) |
1660 | 0 | { |
1661 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1662 | 0 | ps_op->u4_error_code |= |
1663 | 0 | IVE_ERR_IP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT; |
1664 | 0 | return IV_FAIL; |
1665 | 0 | } |
1666 | | |
1667 | 3.90k | if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_mdcv_params_op_t)) |
1668 | 0 | { |
1669 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1670 | 0 | ps_op->u4_error_code |= |
1671 | 0 | IVE_ERR_OP_CTL_SET_SEI_MDCV_STRUCT_SIZE_INCORRECT; |
1672 | 0 | return IV_FAIL; |
1673 | 0 | } |
1674 | | |
1675 | 3.90k | if((ps_ip->u1_sei_mdcv_params_present_flag != 0) |
1676 | 1.80k | && (ps_ip->u1_sei_mdcv_params_present_flag) != 1) |
1677 | 0 | { |
1678 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1679 | 0 | ps_op->u4_error_code |= |
1680 | 0 | IH264E_INVALID_SEI_MDCV_PARAMS; |
1681 | 0 | return IV_FAIL; |
1682 | 0 | } |
1683 | | |
1684 | 3.90k | if(1 == ps_ip->u1_sei_mdcv_params_present_flag) |
1685 | 1.80k | { |
1686 | | /* Check values for u2_display_primaries_x and u2_display_primaries_y */ |
1687 | 7.22k | for(i = 0; i < 3; i++) |
1688 | 5.41k | { |
1689 | 5.41k | if((ps_ip->au2_display_primaries_x[i] > |
1690 | 5.41k | DISPLAY_PRIMARIES_X_UPPER_LIMIT) || |
1691 | 5.41k | (ps_ip->au2_display_primaries_x[i] < |
1692 | 5.41k | DISPLAY_PRIMARIES_X_LOWER_LIMIT) || |
1693 | 5.41k | ((ps_ip->au2_display_primaries_x[i] % |
1694 | 5.41k | DISPLAY_PRIMARIES_X_DIVISION_FACTOR) != 0)) |
1695 | 0 | { |
1696 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1697 | 0 | ps_op->u4_error_code |= |
1698 | 0 | IH264E_INVALID_SEI_MDCV_PARAMS; |
1699 | 0 | return IV_FAIL; |
1700 | 0 | } |
1701 | | |
1702 | 5.41k | if((ps_ip->au2_display_primaries_y[i] > |
1703 | 5.41k | DISPLAY_PRIMARIES_Y_UPPER_LIMIT) || |
1704 | 5.41k | (ps_ip->au2_display_primaries_y[i] < |
1705 | 5.41k | DISPLAY_PRIMARIES_Y_LOWER_LIMIT) || |
1706 | 5.41k | ((ps_ip->au2_display_primaries_y[i] % |
1707 | 5.41k | DISPLAY_PRIMARIES_Y_DIVISION_FACTOR) != 0)) |
1708 | 0 | { |
1709 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1710 | 0 | ps_op->u4_error_code |= |
1711 | 0 | IH264E_INVALID_SEI_MDCV_PARAMS; |
1712 | 0 | return IV_FAIL; |
1713 | 0 | } |
1714 | 5.41k | } |
1715 | | |
1716 | 1.80k | if((ps_ip->u2_white_point_x > WHITE_POINT_X_UPPER_LIMIT) || |
1717 | 1.80k | (ps_ip->u2_white_point_x < WHITE_POINT_X_LOWER_LIMIT) || |
1718 | 1.80k | ((ps_ip->u2_white_point_x % WHITE_POINT_X_DIVISION_FACTOR) != 0)) |
1719 | 0 | { |
1720 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1721 | 0 | ps_op->u4_error_code |= |
1722 | 0 | IH264E_INVALID_SEI_MDCV_PARAMS; |
1723 | 0 | return IV_FAIL; |
1724 | 0 | } |
1725 | | |
1726 | 1.80k | if((ps_ip->u2_white_point_y > WHITE_POINT_Y_UPPER_LIMIT) || |
1727 | 1.80k | (ps_ip->u2_white_point_y < WHITE_POINT_Y_LOWER_LIMIT) || |
1728 | 1.80k | ((ps_ip->u2_white_point_y % WHITE_POINT_Y_DIVISION_FACTOR) != 0)) |
1729 | 0 | { |
1730 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1731 | 0 | ps_op->u4_error_code |= |
1732 | 0 | IH264E_INVALID_SEI_MDCV_PARAMS; |
1733 | 0 | return IV_FAIL; |
1734 | 0 | } |
1735 | | |
1736 | 1.80k | if((ps_ip->u4_max_display_mastering_luminance > |
1737 | 1.80k | MAX_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT) || |
1738 | 1.80k | (ps_ip->u4_max_display_mastering_luminance < |
1739 | 1.80k | MAX_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT) || |
1740 | 1.80k | ((ps_ip->u4_max_display_mastering_luminance % |
1741 | 1.80k | MAX_DISPLAY_MASTERING_LUMINANCE_DIVISION_FACTOR) != 0)) |
1742 | 0 | { |
1743 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1744 | 0 | ps_op->u4_error_code |= |
1745 | 0 | IH264E_INVALID_SEI_MDCV_PARAMS; |
1746 | 0 | return IV_FAIL; |
1747 | 0 | } |
1748 | | |
1749 | 1.80k | if((ps_ip->u4_min_display_mastering_luminance > |
1750 | 1.80k | MIN_DISPLAY_MASTERING_LUMINANCE_UPPER_LIMIT ) || |
1751 | 1.80k | (ps_ip->u4_min_display_mastering_luminance < |
1752 | 1.80k | MIN_DISPLAY_MASTERING_LUMINANCE_LOWER_LIMIT)) |
1753 | 0 | { |
1754 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1755 | 0 | ps_op->u4_error_code |= |
1756 | 0 | IH264E_INVALID_SEI_MDCV_PARAMS; |
1757 | 0 | return IV_FAIL; |
1758 | 0 | } |
1759 | | |
1760 | 1.80k | if(ps_ip->u4_max_display_mastering_luminance <= |
1761 | 1.80k | ps_ip->u4_min_display_mastering_luminance) |
1762 | 0 | { |
1763 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1764 | 0 | ps_op->u4_error_code |= |
1765 | 0 | IH264E_INVALID_SEI_MDCV_PARAMS; |
1766 | 0 | return IV_FAIL; |
1767 | 0 | } |
1768 | 1.80k | } |
1769 | 3.90k | break; |
1770 | 3.90k | } |
1771 | | |
1772 | 3.90k | case IVE_CMD_CTL_SET_SEI_CLL_PARAMS: |
1773 | 3.90k | { |
1774 | 3.90k | ih264e_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip; |
1775 | 3.90k | ih264e_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op; |
1776 | | |
1777 | 3.90k | if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_cll_params_ip_t)) |
1778 | 0 | { |
1779 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1780 | 0 | ps_op->u4_error_code |= |
1781 | 0 | IVE_ERR_IP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT; |
1782 | 0 | return IV_FAIL; |
1783 | 0 | } |
1784 | | |
1785 | 3.90k | if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_cll_params_op_t)) |
1786 | 0 | { |
1787 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1788 | 0 | ps_op->u4_error_code |= |
1789 | 0 | IVE_ERR_OP_CTL_SET_SEI_CLL_STRUCT_SIZE_INCORRECT; |
1790 | 0 | return IV_FAIL; |
1791 | 0 | } |
1792 | | |
1793 | 3.90k | if((ps_ip->u1_sei_cll_params_present_flag != 0) |
1794 | 1.63k | && (ps_ip->u1_sei_cll_params_present_flag != 1)) |
1795 | 0 | { |
1796 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1797 | 0 | ps_op->u4_error_code |= |
1798 | 0 | IH264E_INVALID_SEI_CLL_PARAMS; |
1799 | 0 | return IV_FAIL; |
1800 | 0 | } |
1801 | 3.90k | break; |
1802 | 3.90k | } |
1803 | | |
1804 | 3.90k | case IVE_CMD_CTL_SET_SEI_AVE_PARAMS: |
1805 | 3.90k | { |
1806 | 3.90k | ih264e_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip; |
1807 | 3.90k | ih264e_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op; |
1808 | | |
1809 | 3.90k | if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_ave_params_ip_t)) |
1810 | 0 | { |
1811 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1812 | 0 | ps_op->u4_error_code |= |
1813 | 0 | IVE_ERR_IP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT; |
1814 | 0 | return IV_FAIL; |
1815 | 0 | } |
1816 | | |
1817 | 3.90k | if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_ave_params_op_t)) |
1818 | 0 | { |
1819 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1820 | 0 | ps_op->u4_error_code |= |
1821 | 0 | IVE_ERR_OP_CTL_SET_SEI_AVE_STRUCT_SIZE_INCORRECT; |
1822 | 0 | return IV_FAIL; |
1823 | 0 | } |
1824 | | |
1825 | 3.90k | if((ps_ip->u1_sei_ave_params_present_flag != 0) |
1826 | 1.56k | && (ps_ip->u1_sei_ave_params_present_flag != 1)) |
1827 | 0 | { |
1828 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1829 | 0 | ps_op->u4_error_code |= |
1830 | 0 | IH264E_INVALID_SEI_AVE_PARAMS; |
1831 | 0 | return IV_FAIL; |
1832 | 0 | } |
1833 | | |
1834 | 3.90k | if(1 == ps_ip->u1_sei_ave_params_present_flag) |
1835 | 1.56k | { |
1836 | 1.56k | if((0 == ps_ip->u4_ambient_illuminance)) |
1837 | 0 | { |
1838 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1839 | 0 | ps_op->u4_error_code |= |
1840 | 0 | IH264E_INVALID_SEI_AVE_PARAMS; |
1841 | 0 | return IV_FAIL; |
1842 | 0 | } |
1843 | | |
1844 | 1.56k | if(ps_ip->u2_ambient_light_x > AMBIENT_LIGHT_X_UPPER_LIMIT) |
1845 | 0 | { |
1846 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1847 | 0 | ps_op->u4_error_code |= |
1848 | 0 | IH264E_INVALID_SEI_AVE_PARAMS; |
1849 | 0 | return IV_FAIL; |
1850 | 0 | } |
1851 | | |
1852 | 1.56k | if(ps_ip->u2_ambient_light_y > AMBIENT_LIGHT_Y_UPPER_LIMIT) |
1853 | 0 | { |
1854 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1855 | 0 | ps_op->u4_error_code |= |
1856 | 0 | IH264E_INVALID_SEI_AVE_PARAMS; |
1857 | 0 | return IV_FAIL; |
1858 | 0 | } |
1859 | 1.56k | } |
1860 | 3.90k | break; |
1861 | 3.90k | } |
1862 | | |
1863 | 3.90k | case IVE_CMD_CTL_SET_SEI_CCV_PARAMS: |
1864 | 3.90k | { |
1865 | 3.90k | ih264e_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip; |
1866 | 3.90k | ih264e_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op; |
1867 | | |
1868 | 3.90k | if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_ccv_params_ip_t)) |
1869 | 0 | { |
1870 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1871 | 0 | ps_op->u4_error_code |= |
1872 | 0 | IVE_ERR_IP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT; |
1873 | 0 | return IV_FAIL; |
1874 | 0 | } |
1875 | | |
1876 | 3.90k | if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_ccv_params_op_t)) |
1877 | 0 | { |
1878 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1879 | 0 | ps_op->u4_error_code |= |
1880 | 0 | IVE_ERR_OP_CTL_SET_SEI_CCV_STRUCT_SIZE_INCORRECT; |
1881 | 0 | return IV_FAIL; |
1882 | 0 | } |
1883 | | |
1884 | 3.90k | if((ps_ip->u1_sei_ccv_params_present_flag != 0) |
1885 | 1.30k | && (ps_ip->u1_sei_ccv_params_present_flag != 1)) |
1886 | 0 | { |
1887 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1888 | 0 | ps_op->u4_error_code |= |
1889 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
1890 | 0 | return IV_FAIL; |
1891 | 0 | } |
1892 | | |
1893 | | |
1894 | 3.90k | if(1 == ps_ip->u1_sei_ccv_params_present_flag) |
1895 | 1.30k | { |
1896 | 1.30k | if((ps_ip->u1_ccv_cancel_flag != 0) |
1897 | 0 | && (ps_ip->u1_ccv_cancel_flag != 1)) |
1898 | 0 | { |
1899 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1900 | 0 | ps_op->u4_error_code |= |
1901 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
1902 | 0 | return IV_FAIL; |
1903 | 0 | } |
1904 | | |
1905 | 1.30k | if(0 == ps_ip->u1_ccv_cancel_flag) |
1906 | 1.30k | { |
1907 | 1.30k | if((ps_ip->u1_ccv_persistence_flag != 0) |
1908 | 1.30k | && (ps_ip->u1_ccv_persistence_flag != 1)) |
1909 | 0 | { |
1910 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1911 | 0 | ps_op->u4_error_code |= |
1912 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
1913 | 0 | return IV_FAIL; |
1914 | 0 | } |
1915 | 1.30k | if((ps_ip->u1_ccv_primaries_present_flag != 0) |
1916 | 1.30k | && (ps_ip->u1_ccv_primaries_present_flag != 1)) |
1917 | 0 | { |
1918 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1919 | 0 | ps_op->u4_error_code |= |
1920 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
1921 | 0 | return IV_FAIL; |
1922 | 0 | } |
1923 | 1.30k | if((ps_ip->u1_ccv_min_luminance_value_present_flag != 0) |
1924 | 1.30k | && (ps_ip->u1_ccv_min_luminance_value_present_flag != 1)) |
1925 | 0 | { |
1926 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1927 | 0 | ps_op->u4_error_code |= |
1928 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
1929 | 0 | return IV_FAIL; |
1930 | 0 | } |
1931 | 1.30k | if((ps_ip->u1_ccv_max_luminance_value_present_flag != 0) |
1932 | 1.30k | && (ps_ip->u1_ccv_max_luminance_value_present_flag != 1)) |
1933 | 0 | { |
1934 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1935 | 0 | ps_op->u4_error_code |= |
1936 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
1937 | 0 | return IV_FAIL; |
1938 | 0 | } |
1939 | 1.30k | if((ps_ip->u1_ccv_avg_luminance_value_present_flag != 0) |
1940 | 1.30k | && (ps_ip->u1_ccv_avg_luminance_value_present_flag != 1)) |
1941 | 0 | { |
1942 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1943 | 0 | ps_op->u4_error_code |= |
1944 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
1945 | 0 | return IV_FAIL; |
1946 | 0 | } |
1947 | 1.30k | if((ps_ip->u1_ccv_primaries_present_flag == 0) |
1948 | 0 | && (ps_ip->u1_ccv_min_luminance_value_present_flag == 0) |
1949 | 0 | && (ps_ip->u1_ccv_max_luminance_value_present_flag == 0) |
1950 | 0 | && (ps_ip->u1_ccv_avg_luminance_value_present_flag == 0)) |
1951 | 0 | { |
1952 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1953 | 0 | ps_op->u4_error_code |= |
1954 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
1955 | 0 | return IV_FAIL; |
1956 | 0 | } |
1957 | | |
1958 | 1.30k | if((ps_ip->u1_ccv_reserved_zero_2bits != 0)) |
1959 | 0 | { |
1960 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1961 | 0 | ps_op->u4_error_code |= |
1962 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
1963 | 0 | return IV_FAIL; |
1964 | 0 | } |
1965 | | |
1966 | 1.30k | if(1 == ps_ip->u1_ccv_primaries_present_flag) |
1967 | 1.30k | { |
1968 | 5.22k | for(i = 0; i < 3; i++) |
1969 | 3.91k | { |
1970 | 3.91k | if((ps_ip->ai4_ccv_primaries_x[i] > |
1971 | 3.91k | CCV_PRIMARIES_X_UPPER_LIMIT) || |
1972 | 3.91k | (ps_ip->ai4_ccv_primaries_x[i] < |
1973 | 3.91k | CCV_PRIMARIES_X_LOWER_LIMIT)) |
1974 | 0 | { |
1975 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1976 | 0 | ps_op->u4_error_code |= |
1977 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
1978 | 0 | return IV_FAIL; |
1979 | 0 | } |
1980 | | |
1981 | 3.91k | if((ps_ip->ai4_ccv_primaries_y[i] > |
1982 | 3.91k | CCV_PRIMARIES_Y_UPPER_LIMIT) || |
1983 | 3.91k | (ps_ip->ai4_ccv_primaries_y[i] < |
1984 | 3.91k | CCV_PRIMARIES_Y_LOWER_LIMIT)) |
1985 | 0 | { |
1986 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
1987 | 0 | ps_op->u4_error_code |= |
1988 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
1989 | 0 | return IV_FAIL; |
1990 | 0 | } |
1991 | 3.91k | } |
1992 | 1.30k | } |
1993 | | |
1994 | 1.30k | if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) && |
1995 | 1.30k | (1 == ps_ip->u1_ccv_avg_luminance_value_present_flag)) |
1996 | 1.30k | { |
1997 | 1.30k | if((ps_ip->u4_ccv_avg_luminance_value < |
1998 | 1.30k | ps_ip->u4_ccv_min_luminance_value)) |
1999 | 0 | { |
2000 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
2001 | 0 | ps_op->u4_error_code |= |
2002 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
2003 | 0 | return IV_FAIL; |
2004 | 0 | } |
2005 | 1.30k | } |
2006 | | |
2007 | 1.30k | if((1 == ps_ip->u1_ccv_min_luminance_value_present_flag) && |
2008 | 1.30k | (1 == ps_ip->u1_ccv_max_luminance_value_present_flag)) |
2009 | 1.30k | { |
2010 | 1.30k | if((ps_ip->u4_ccv_max_luminance_value < |
2011 | 1.30k | ps_ip->u4_ccv_min_luminance_value)) |
2012 | 0 | { |
2013 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
2014 | 0 | ps_op->u4_error_code |= |
2015 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
2016 | 0 | return IV_FAIL; |
2017 | 0 | } |
2018 | 1.30k | } |
2019 | 1.30k | if((1 == ps_ip->u1_ccv_avg_luminance_value_present_flag) && |
2020 | 1.30k | (1 == ps_ip->u1_ccv_max_luminance_value_present_flag)) |
2021 | 1.30k | { |
2022 | 1.30k | if((ps_ip->u4_ccv_max_luminance_value < |
2023 | 1.30k | ps_ip->u4_ccv_avg_luminance_value)) |
2024 | 0 | { |
2025 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
2026 | 0 | ps_op->u4_error_code |= |
2027 | 0 | IH264E_INVALID_SEI_CCV_PARAMS; |
2028 | 0 | return IV_FAIL; |
2029 | 0 | } |
2030 | 1.30k | } |
2031 | 1.30k | } |
2032 | 1.30k | } |
2033 | 3.90k | break; |
2034 | 3.90k | } |
2035 | | |
2036 | 3.90k | case IVE_CMD_CTL_SET_SEI_SII_PARAMS: |
2037 | 3.90k | { |
2038 | 3.90k | ih264e_ctl_set_sei_sii_params_ip_t *ps_ip = pv_api_ip; |
2039 | 3.90k | ih264e_ctl_set_sei_sii_params_op_t *ps_op = pv_api_op; |
2040 | | |
2041 | 3.90k | if(ps_ip->u4_size != sizeof(ih264e_ctl_set_sei_sii_params_ip_t)) |
2042 | 0 | { |
2043 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
2044 | 0 | ps_op->u4_error_code |= IVE_ERR_IP_CTL_SET_SEI_SII_STRUCT_SIZE_INCORRECT; |
2045 | 0 | return IV_FAIL; |
2046 | 0 | } |
2047 | | |
2048 | 3.90k | if(ps_op->u4_size != sizeof(ih264e_ctl_set_sei_sii_params_op_t)) |
2049 | 0 | { |
2050 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
2051 | 0 | ps_op->u4_error_code |= IVE_ERR_OP_CTL_SET_SEI_SII_STRUCT_SIZE_INCORRECT; |
2052 | 0 | return IV_FAIL; |
2053 | 0 | } |
2054 | | |
2055 | | /* The below error check is based on H264 spec docs SII syntax */ |
2056 | 3.90k | if(0 != ps_ip->u4_sii_sub_layer_idx) |
2057 | 0 | { |
2058 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
2059 | 0 | ps_op->u4_error_code |= IH264E_INVALID_SEI_SII_PARAMS; |
2060 | 0 | return IV_FAIL; |
2061 | 0 | } |
2062 | | |
2063 | 3.90k | if(ps_ip->u1_sii_max_sub_layers_minus1 > 7) |
2064 | 0 | { |
2065 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
2066 | 0 | ps_op->u4_error_code |= IH264E_INVALID_SEI_SII_PARAMS; |
2067 | 0 | return IV_FAIL; |
2068 | 0 | } |
2069 | | |
2070 | 3.90k | if((ps_ip->u4_sii_sub_layer_idx > 0) && |
2071 | 0 | (ps_ip->u1_fixed_shutter_interval_within_cvs_flag == 1)) |
2072 | 0 | { |
2073 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
2074 | 0 | ps_op->u4_error_code |= IH264E_SEI_SII_FAILED_TO_MATCH_SPEC_COND; |
2075 | 0 | return IV_FAIL; |
2076 | 0 | } |
2077 | | |
2078 | 3.90k | if((ps_ip->u4_sii_sub_layer_idx > ps_ip->u1_sii_max_sub_layers_minus1) && |
2079 | 0 | (ps_ip->u1_fixed_shutter_interval_within_cvs_flag == 0)) |
2080 | 0 | { |
2081 | 0 | ps_op->u4_error_code |= 1 << IVE_UNSUPPORTEDPARAM; |
2082 | 0 | ps_op->u4_error_code |= IH264E_SEI_SII_FAILED_TO_MATCH_SPEC_COND; |
2083 | 0 | return IV_FAIL; |
2084 | 0 | } |
2085 | | |
2086 | 3.90k | break; |
2087 | 3.90k | } |
2088 | | |
2089 | 3.90k | case IVE_CMD_CTL_SET_ENC_MODE: |
2090 | 3.90k | { |
2091 | 3.90k | ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip; |
2092 | 3.90k | ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op; |
2093 | | |
2094 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
2095 | 3.90k | != sizeof(ih264e_ctl_set_enc_mode_ip_t)) |
2096 | 0 | { |
2097 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2098 | 0 | << IVE_UNSUPPORTEDPARAM; |
2099 | 0 | ps_op->s_ive_op.u4_error_code |= |
2100 | 0 | IVE_ERR_IP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT; |
2101 | 0 | return IV_FAIL; |
2102 | 0 | } |
2103 | | |
2104 | 3.90k | if (ps_op->s_ive_op.u4_size |
2105 | 3.90k | != sizeof(ih264e_ctl_set_enc_mode_op_t)) |
2106 | 0 | { |
2107 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2108 | 0 | << IVE_UNSUPPORTEDPARAM; |
2109 | 0 | ps_op->s_ive_op.u4_error_code |= |
2110 | 0 | IVE_ERR_OP_CTL_SETENCMODE_API_STRUCT_SIZE_INCORRECT; |
2111 | 0 | return IV_FAIL; |
2112 | 0 | } |
2113 | | |
2114 | 3.90k | if ((ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_HEADER) |
2115 | 0 | && (ps_ip->s_ive_ip.e_enc_mode != IVE_ENC_MODE_PICTURE)) |
2116 | 0 | { |
2117 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2118 | 0 | << IVE_UNSUPPORTEDPARAM; |
2119 | 0 | ps_op->s_ive_op.u4_error_code |= |
2120 | 0 | IH264E_INVALID_ENC_OPERATION_MODE; |
2121 | 0 | return IV_FAIL; |
2122 | 0 | } |
2123 | | |
2124 | 3.90k | break; |
2125 | 3.90k | } |
2126 | | |
2127 | 3.90k | case IVE_CMD_CTL_SET_VBV_PARAMS: |
2128 | 3.90k | { |
2129 | 3.90k | ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip; |
2130 | 3.90k | ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op; |
2131 | | |
2132 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
2133 | 3.90k | != sizeof(ih264e_ctl_set_vbv_params_ip_t)) |
2134 | 0 | { |
2135 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2136 | 0 | << IVE_UNSUPPORTEDPARAM; |
2137 | 0 | ps_op->s_ive_op.u4_error_code |= |
2138 | 0 | IVE_ERR_IP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT; |
2139 | 0 | return IV_FAIL; |
2140 | 0 | } |
2141 | | |
2142 | 3.90k | if (ps_op->s_ive_op.u4_size |
2143 | 3.90k | != sizeof(ih264e_ctl_set_vbv_params_op_t)) |
2144 | 0 | { |
2145 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2146 | 0 | << IVE_UNSUPPORTEDPARAM; |
2147 | 0 | ps_op->s_ive_op.u4_error_code |= |
2148 | 0 | IVE_ERR_OP_CTL_SETVBVPARAMS_API_STRUCT_SIZE_INCORRECT; |
2149 | 0 | return IV_FAIL; |
2150 | 0 | } |
2151 | | |
2152 | 3.90k | if ((ps_ip->s_ive_ip.u4_vbv_buffer_delay < DEFAULT_MIN_BUFFER_DELAY) |
2153 | 3.90k | || (ps_ip->s_ive_ip.u4_vbv_buffer_delay > DEFAULT_MAX_BUFFER_DELAY)) |
2154 | 0 | { |
2155 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2156 | 0 | << IVE_UNSUPPORTEDPARAM; |
2157 | 0 | ps_op->s_ive_op.u4_error_code |= |
2158 | 0 | IH264E_INVALID_BUFFER_DELAY; |
2159 | 0 | return IV_FAIL; |
2160 | 0 | } |
2161 | | |
2162 | 3.90k | break; |
2163 | 3.90k | } |
2164 | | |
2165 | 3.90k | case IVE_CMD_CTL_SET_AIR_PARAMS: |
2166 | 3.90k | { |
2167 | 3.90k | ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip; |
2168 | 3.90k | ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op; |
2169 | | |
2170 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
2171 | 3.90k | != sizeof(ih264e_ctl_set_air_params_ip_t)) |
2172 | 0 | { |
2173 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2174 | 0 | << IVE_UNSUPPORTEDPARAM; |
2175 | 0 | ps_op->s_ive_op.u4_error_code |= |
2176 | 0 | IVE_ERR_IP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT; |
2177 | 0 | return IV_FAIL; |
2178 | 0 | } |
2179 | | |
2180 | 3.90k | if (ps_op->s_ive_op.u4_size |
2181 | 3.90k | != sizeof(ih264e_ctl_set_air_params_op_t)) |
2182 | 0 | { |
2183 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2184 | 0 | << IVE_UNSUPPORTEDPARAM; |
2185 | 0 | ps_op->s_ive_op.u4_error_code |= |
2186 | 0 | IVE_ERR_OP_CTL_SETAIRPARAMS_API_STRUCT_SIZE_INCORRECT; |
2187 | 0 | return IV_FAIL; |
2188 | 0 | } |
2189 | | |
2190 | 3.90k | if ((ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_NONE) |
2191 | 1.63k | && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_CYCLIC) |
2192 | 779 | && (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_RANDOM)) |
2193 | 0 | { |
2194 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2195 | 0 | << IVE_UNSUPPORTEDPARAM; |
2196 | 0 | ps_op->s_ive_op.u4_error_code |= |
2197 | 0 | IH264E_INVALID_AIR_MODE; |
2198 | 0 | return IV_FAIL; |
2199 | 0 | } |
2200 | | |
2201 | 3.90k | if (ps_ip->s_ive_ip.e_air_mode != IVE_AIR_MODE_NONE && |
2202 | 1.63k | ps_ip->s_ive_ip.u4_air_refresh_period == 0) |
2203 | 0 | { |
2204 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2205 | 0 | << IVE_UNSUPPORTEDPARAM; |
2206 | 0 | ps_op->s_ive_op.u4_error_code |= |
2207 | 0 | IH264E_INVALID_AIR_REFRESH_PERIOD; |
2208 | 0 | return IV_FAIL; |
2209 | 0 | } |
2210 | | |
2211 | 3.90k | break; |
2212 | 3.90k | } |
2213 | | |
2214 | 3.90k | case IVE_CMD_CTL_SET_PROFILE_PARAMS: |
2215 | 3.90k | { |
2216 | 3.90k | ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip; |
2217 | 3.90k | ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op; |
2218 | | |
2219 | 3.90k | if (ps_ip->s_ive_ip.u4_size |
2220 | 3.90k | != sizeof(ih264e_ctl_set_profile_params_ip_t)) |
2221 | 0 | { |
2222 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2223 | 0 | << IVE_UNSUPPORTEDPARAM; |
2224 | 0 | ps_op->s_ive_op.u4_error_code |= |
2225 | 0 | IVE_ERR_IP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT; |
2226 | 0 | return IV_FAIL; |
2227 | 0 | } |
2228 | | |
2229 | 3.90k | if (ps_op->s_ive_op.u4_size |
2230 | 3.90k | != sizeof(ih264e_ctl_set_profile_params_op_t)) |
2231 | 0 | { |
2232 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2233 | 0 | << IVE_UNSUPPORTEDPARAM; |
2234 | 0 | ps_op->s_ive_op.u4_error_code |= |
2235 | 0 | IVE_ERR_OP_CTL_SETPROFILE_API_STRUCT_SIZE_INCORRECT; |
2236 | 0 | return IV_FAIL; |
2237 | 0 | } |
2238 | | |
2239 | 3.90k | if (ps_ip->s_ive_ip.e_profile != IV_PROFILE_BASE && |
2240 | 1.53k | ps_ip->s_ive_ip.e_profile != IV_PROFILE_MAIN) |
2241 | 0 | { |
2242 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2243 | 0 | << IVE_UNSUPPORTEDPARAM; |
2244 | 0 | ps_op->s_ive_op.u4_error_code |= |
2245 | 0 | IH264E_PROFILE_NOT_SUPPORTED; |
2246 | 0 | return IV_FAIL; |
2247 | 0 | } |
2248 | | |
2249 | 3.90k | if (ps_ip->s_ive_ip.u4_entropy_coding_mode > 1) |
2250 | 0 | { |
2251 | 0 | ps_op->s_ive_op.u4_error_code |= 1 |
2252 | 0 | << IVE_UNSUPPORTEDPARAM; |
2253 | 0 | ps_op->s_ive_op.u4_error_code |= |
2254 | 0 | IH264E_INVALID_ENTROPY_CODING_MODE; |
2255 | 0 | return IV_FAIL; |
2256 | 0 | } |
2257 | | |
2258 | 3.90k | break; |
2259 | 3.90k | } |
2260 | | |
2261 | 3.90k | default: |
2262 | 0 | *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; |
2263 | 0 | *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_SUB_CMD; |
2264 | 0 | return IV_FAIL; |
2265 | 88.6k | } |
2266 | | |
2267 | 81.3k | break; |
2268 | 88.6k | } |
2269 | | |
2270 | 81.3k | default: |
2271 | 0 | *(pu4_api_op + 1) |= 1 << IVE_UNSUPPORTEDPARAM; |
2272 | 0 | *(pu4_api_op + 1) |= IVE_ERR_INVALID_API_CMD; |
2273 | 0 | return IV_FAIL; |
2274 | 174k | } |
2275 | | |
2276 | 166k | return IV_SUCCESS; |
2277 | 174k | } |
2278 | | |
2279 | | /** |
2280 | | ******************************************************************************* |
2281 | | * |
2282 | | * @brief update encoder configuration parameters |
2283 | | * |
2284 | | * @par Description: |
2285 | | * updates encoder configuration parameters from the given config set. |
2286 | | * Initialize/reinitialize codec parameters according to new configurations. |
2287 | | * |
2288 | | * @param[in] ps_codec |
2289 | | * Pointer to codec context |
2290 | | * |
2291 | | * @param[in] ps_cfg |
2292 | | * Pointer to config param set |
2293 | | * |
2294 | | * @remarks none |
2295 | | * |
2296 | | ******************************************************************************* |
2297 | | */ |
2298 | | IH264E_ERROR_T ih264e_codec_update_config(codec_t *ps_codec, |
2299 | | cfg_params_t *ps_cfg) |
2300 | 73.5k | { |
2301 | | /* config params */ |
2302 | 73.5k | cfg_params_t *ps_curr_cfg = &ps_codec->s_cfg; |
2303 | | |
2304 | | /* error status */ |
2305 | 73.5k | IH264E_ERROR_T err = IH264E_SUCCESS; |
2306 | | |
2307 | | /* temp var */ |
2308 | 73.5k | UWORD32 u4_init_rc = 0; |
2309 | | |
2310 | | /***********************/ |
2311 | | /* UPDATE CODEC CONFIG */ |
2312 | | /***********************/ |
2313 | 73.5k | if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DIMENSIONS) |
2314 | 3.77k | { |
2315 | 3.77k | UWORD32 wd_aln = ALIGN16(ps_cfg->u4_wd); |
2316 | 3.77k | UWORD32 ht_aln = ALIGN16(ps_cfg->u4_ht); |
2317 | | |
2318 | 3.77k | if (ps_curr_cfg->u4_wd != wd_aln || ps_curr_cfg->u4_ht != ht_aln |
2319 | 3.77k | || ps_curr_cfg->u4_disp_wd != ps_cfg->u4_disp_wd |
2320 | 1.49k | || ps_curr_cfg->u4_disp_ht != ps_cfg->u4_disp_ht) |
2321 | 2.80k | { |
2322 | 2.80k | ps_curr_cfg->u4_wd = wd_aln; |
2323 | 2.80k | ps_curr_cfg->u4_ht = ht_aln; |
2324 | | |
2325 | 2.80k | ps_curr_cfg->u4_disp_wd = ps_cfg->u4_disp_wd; |
2326 | 2.80k | ps_curr_cfg->u4_disp_ht = ps_cfg->u4_disp_ht; |
2327 | | |
2328 | 2.80k | ps_curr_cfg->i4_wd_mbs = ps_curr_cfg->u4_wd >> 4; |
2329 | 2.80k | ps_curr_cfg->i4_ht_mbs = ps_curr_cfg->u4_ht >> 4; |
2330 | | |
2331 | 2.80k | ps_codec->i4_rec_strd = ALIGN16(ps_cfg->u4_wd) + PAD_WD; |
2332 | | |
2333 | | /* If number of MBs in a frame changes the air map also changes. |
2334 | | * Hence recompute air map also reset air pic cnt */ |
2335 | 2.80k | if (ps_codec->s_cfg.e_air_mode != IVE_AIR_MODE_NONE) |
2336 | 0 | { |
2337 | | /* re-init the air map */ |
2338 | 0 | ih264e_init_air_map(ps_codec); |
2339 | | |
2340 | | /* reset air counter */ |
2341 | 0 | ps_codec->i4_air_pic_cnt = -1; |
2342 | 0 | } |
2343 | | |
2344 | | /* initialize mv bank buffer manager */ |
2345 | 2.80k | err = ih264e_mv_buf_mgr_add_bufs(ps_codec); |
2346 | 2.80k | if (err != IH264E_SUCCESS) |
2347 | 0 | return err; |
2348 | | |
2349 | | /* initialize ref bank buffer manager */ |
2350 | 2.80k | err = ih264e_pic_buf_mgr_add_bufs(ps_codec); |
2351 | 2.80k | if (err != IH264E_SUCCESS) |
2352 | 0 | return err; |
2353 | | |
2354 | | /* since dimension changed, start new sequence by forcing IDR */ |
2355 | 2.80k | ps_codec->force_curr_frame_type = IV_IDR_FRAME; |
2356 | | |
2357 | | /* in case dimension changes, we need to reinitialize RC as the |
2358 | | * old model shall not fit further */ |
2359 | 2.80k | u4_init_rc = 1; |
2360 | | |
2361 | | /* when the dimension changes, the header needs to be regenerated */ |
2362 | 2.80k | ps_codec->i4_gen_header = 1; |
2363 | 2.80k | } |
2364 | 3.77k | } |
2365 | 69.7k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMERATE) |
2366 | 2.24k | { |
2367 | | /* temp var */ |
2368 | 2.24k | UWORD32 u4_src_ticks, u4_tgt_ticks; |
2369 | | |
2370 | 2.24k | u4_src_ticks = ih264e_frame_time_get_src_ticks( |
2371 | 2.24k | ps_codec->s_rate_control.pps_frame_time); |
2372 | | |
2373 | 2.24k | u4_tgt_ticks = ih264e_frame_time_get_tgt_ticks( |
2374 | 2.24k | ps_codec->s_rate_control.pps_frame_time); |
2375 | | |
2376 | | /* Change frame rate */ |
2377 | 2.24k | if (ps_codec->s_cfg.u4_src_frame_rate |
2378 | 2.24k | != ps_cfg->u4_src_frame_rate * 1000) |
2379 | 2.22k | { |
2380 | 2.22k | ps_codec->s_cfg.u4_src_frame_rate = ps_cfg->u4_src_frame_rate |
2381 | 2.22k | * 1000; |
2382 | | |
2383 | 2.22k | ih264e_frame_time_update_src_frame_rate( |
2384 | 2.22k | ps_codec->s_rate_control.pps_frame_time, |
2385 | 2.22k | ps_codec->s_cfg.u4_src_frame_rate); |
2386 | | |
2387 | 2.22k | ih264_time_stamp_update_frame_rate( |
2388 | 2.22k | ps_codec->s_rate_control.pps_time_stamp, |
2389 | 2.22k | ps_codec->s_cfg.u4_src_frame_rate); |
2390 | | |
2391 | 2.22k | irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api, |
2392 | 2.22k | ps_codec->s_cfg.u4_src_frame_rate, |
2393 | 2.22k | u4_src_ticks, u4_tgt_ticks); |
2394 | 2.22k | } |
2395 | | |
2396 | 2.24k | if (ps_codec->s_cfg.u4_tgt_frame_rate |
2397 | 2.24k | != ps_cfg->u4_tgt_frame_rate * 1000) |
2398 | 2.22k | { |
2399 | 2.22k | ps_codec->s_cfg.u4_tgt_frame_rate = ps_cfg->u4_tgt_frame_rate |
2400 | 2.22k | * 1000; |
2401 | | |
2402 | 2.22k | ih264e_frame_time_update_tgt_frame_rate( |
2403 | 2.22k | ps_codec->s_rate_control.pps_frame_time, |
2404 | 2.22k | ps_codec->s_cfg.u4_tgt_frame_rate); |
2405 | | |
2406 | 2.22k | irc_change_frame_rate(ps_codec->s_rate_control.pps_rate_control_api, |
2407 | 2.22k | ps_codec->s_cfg.u4_src_frame_rate, |
2408 | 2.22k | u4_src_ticks, u4_tgt_ticks); |
2409 | | |
2410 | 2.22k | irc_change_frm_rate_for_bit_alloc( |
2411 | 2.22k | ps_codec->s_rate_control.pps_rate_control_api, |
2412 | 2.22k | ps_codec->s_cfg.u4_tgt_frame_rate); |
2413 | 2.22k | } |
2414 | | |
2415 | 2.24k | } |
2416 | 67.5k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_BITRATE) |
2417 | 4.46k | { |
2418 | 4.46k | if (ps_curr_cfg->u4_target_bitrate != ps_cfg->u4_target_bitrate) |
2419 | 4.46k | { |
2420 | 4.46k | if (IVE_RC_NONE != ps_curr_cfg->e_rc_mode) |
2421 | 2.74k | irc_change_avg_bit_rate( |
2422 | 2.74k | ps_codec->s_rate_control.pps_rate_control_api, |
2423 | 2.74k | ps_cfg->u4_target_bitrate); |
2424 | | |
2425 | 4.46k | ps_curr_cfg->u4_target_bitrate = ps_cfg->u4_target_bitrate; |
2426 | 4.46k | } |
2427 | 4.46k | } |
2428 | 63.0k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_FRAMETYPE) |
2429 | 931 | { |
2430 | 931 | switch (ps_cfg->e_frame_type) |
2431 | 931 | { |
2432 | 0 | case IV_I_FRAME: |
2433 | 0 | ps_codec->force_curr_frame_type = IV_I_FRAME; |
2434 | 0 | break; |
2435 | | |
2436 | 931 | case IV_IDR_FRAME: |
2437 | 931 | ps_codec->force_curr_frame_type = IV_IDR_FRAME; |
2438 | 931 | break; |
2439 | | |
2440 | 0 | case IV_P_FRAME: |
2441 | 0 | default: |
2442 | 0 | break; |
2443 | 931 | } |
2444 | 931 | } |
2445 | 62.1k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ME_PARAMS) |
2446 | 1.05k | { |
2447 | 1.05k | if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG) |
2448 | 350 | { |
2449 | 350 | ps_codec->s_cfg.u4_enable_hpel = ps_cfg->u4_enable_hpel; |
2450 | 350 | ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad; |
2451 | 350 | ps_codec->s_cfg.u4_me_speed_preset = ps_cfg->u4_me_speed_preset; |
2452 | 350 | ps_codec->s_cfg.u4_enable_qpel = ps_cfg->u4_enable_qpel; |
2453 | 350 | } |
2454 | 703 | else if (ps_curr_cfg->u4_enc_speed_preset == IVE_FASTEST) |
2455 | 71 | { |
2456 | 71 | ps_codec->s_cfg.u4_enable_fast_sad = ps_cfg->u4_enable_fast_sad; |
2457 | 71 | } |
2458 | 1.05k | ps_codec->s_cfg.u4_srch_rng_x = ps_cfg->u4_srch_rng_x; |
2459 | 1.05k | ps_codec->s_cfg.u4_srch_rng_y = ps_cfg->u4_srch_rng_y; |
2460 | | |
2461 | 1.05k | if (ps_codec->s_cfg.u4_enable_alt_ref != ps_cfg->u4_enable_alt_ref) |
2462 | 0 | { |
2463 | 0 | ps_codec->s_cfg.u4_enable_alt_ref = ps_cfg->u4_enable_alt_ref; |
2464 | 0 | ps_codec->u4_is_curr_frm_ref = 1; |
2465 | 0 | } |
2466 | 1.05k | } |
2467 | 61.0k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_IPE_PARAMS) |
2468 | 3.90k | { |
2469 | 3.90k | ps_curr_cfg->u4_enc_speed_preset = ps_cfg->u4_enc_speed_preset; |
2470 | | |
2471 | 3.90k | ps_curr_cfg->u4_constrained_intra_pred = ps_cfg->u4_constrained_intra_pred; |
2472 | | |
2473 | 3.90k | if (ps_curr_cfg->u4_enc_speed_preset != IVE_CONFIG) |
2474 | 2.63k | { |
2475 | 2.63k | ih264e_speed_preset_side_effects(ps_codec); |
2476 | 2.63k | } |
2477 | 1.27k | else |
2478 | 1.27k | { |
2479 | 1.27k | ps_curr_cfg->u4_enable_intra_4x4 = ps_cfg->u4_enable_intra_4x4; |
2480 | 1.27k | } |
2481 | 3.90k | } |
2482 | 57.1k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_GOP_PARAMS) |
2483 | 3.17k | { |
2484 | 3.17k | if (ps_curr_cfg->u4_i_frm_interval != ps_cfg->u4_i_frm_interval) |
2485 | 3.15k | { |
2486 | 3.15k | ps_curr_cfg->u4_i_frm_interval = ps_cfg->u4_i_frm_interval; |
2487 | | |
2488 | | /* reset air counter */ |
2489 | 3.15k | ps_codec->i4_air_pic_cnt = -1; |
2490 | | |
2491 | | /* re-init air map */ |
2492 | 3.15k | ih264e_init_air_map(ps_codec); |
2493 | | |
2494 | | /* Effect intra frame interval change */ |
2495 | 3.15k | irc_change_intra_frm_int_call( |
2496 | 3.15k | ps_codec->s_rate_control.pps_rate_control_api, |
2497 | 3.15k | ps_curr_cfg->u4_i_frm_interval); |
2498 | 3.15k | } |
2499 | | |
2500 | 3.17k | ps_curr_cfg->u4_idr_frm_interval = ps_cfg->u4_idr_frm_interval; |
2501 | | |
2502 | 3.17k | } |
2503 | 54.0k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_DEBLOCK_PARAMS) |
2504 | 3.23k | { |
2505 | 3.23k | if (ps_curr_cfg->u4_enc_speed_preset == IVE_CONFIG) |
2506 | 1.04k | { |
2507 | 1.04k | ps_curr_cfg->u4_disable_deblock_level = |
2508 | 1.04k | ps_cfg->u4_disable_deblock_level; |
2509 | 1.04k | } |
2510 | 3.23k | } |
2511 | 50.7k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_QP) |
2512 | 3.90k | { |
2513 | 3.90k | UWORD8 au1_init_qp[MAX_PIC_TYPE]; |
2514 | 3.90k | UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE]; |
2515 | | |
2516 | 3.90k | ps_codec->s_cfg.u4_i_qp_max = ps_cfg->u4_i_qp_max; |
2517 | 3.90k | ps_codec->s_cfg.u4_i_qp_min = ps_cfg->u4_i_qp_min; |
2518 | 3.90k | ps_codec->s_cfg.u4_i_qp = ps_cfg->u4_i_qp; |
2519 | | |
2520 | 3.90k | ps_codec->s_cfg.u4_p_qp_max = ps_cfg->u4_p_qp_max; |
2521 | 3.90k | ps_codec->s_cfg.u4_p_qp_min = ps_cfg->u4_p_qp_min; |
2522 | 3.90k | ps_codec->s_cfg.u4_p_qp = ps_cfg->u4_p_qp; |
2523 | | |
2524 | 3.90k | ps_codec->s_cfg.u4_b_qp_max = ps_cfg->u4_b_qp_max; |
2525 | 3.90k | ps_codec->s_cfg.u4_b_qp_min = ps_cfg->u4_b_qp_min; |
2526 | 3.90k | ps_codec->s_cfg.u4_b_qp = ps_cfg->u4_b_qp; |
2527 | | |
2528 | | /* update rc lib with modified qp */ |
2529 | 3.90k | au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp]; |
2530 | 3.90k | au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp]; |
2531 | 3.90k | au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp]; |
2532 | | |
2533 | 3.90k | irc_change_init_qp(ps_codec->s_rate_control.pps_rate_control_api, |
2534 | 3.90k | au1_init_qp); |
2535 | | |
2536 | 3.90k | au1_min_max_qp[2 * I_PIC] = |
2537 | 3.90k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min]; |
2538 | 3.90k | au1_min_max_qp[2 * I_PIC + 1] = |
2539 | 3.90k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max]; |
2540 | | |
2541 | 3.90k | au1_min_max_qp[2 * P_PIC] = |
2542 | 3.90k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min]; |
2543 | 3.90k | au1_min_max_qp[2 * P_PIC + 1] = |
2544 | 3.90k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max]; |
2545 | | |
2546 | 3.90k | au1_min_max_qp[2 * B_PIC] = |
2547 | 3.90k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min]; |
2548 | 3.90k | au1_min_max_qp[2 * B_PIC + 1] = |
2549 | 3.90k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max]; |
2550 | | |
2551 | 3.90k | irc_change_min_max_qp(ps_codec->s_rate_control.pps_rate_control_api, |
2552 | 3.90k | au1_min_max_qp); |
2553 | 3.90k | } |
2554 | 46.8k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_ENC_MODE) |
2555 | 3.90k | { |
2556 | 3.90k | ps_codec->s_cfg.e_enc_mode = ps_cfg->e_enc_mode; |
2557 | | |
2558 | 3.90k | if (ps_codec->s_cfg.e_enc_mode == IVE_ENC_MODE_HEADER) |
2559 | 3.90k | { |
2560 | 3.90k | ps_codec->i4_header_mode = 1; |
2561 | 3.90k | ps_codec->s_cfg.e_enc_mode = IVE_ENC_MODE_PICTURE; |
2562 | 3.90k | } |
2563 | 0 | else |
2564 | 0 | { |
2565 | 0 | ps_codec->i4_header_mode = 0; |
2566 | 0 | } |
2567 | 3.90k | } |
2568 | 42.9k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VBV_PARAMS |
2569 | 3.90k | && IVE_RC_NONE != ps_codec->s_cfg.e_rc_mode) |
2570 | 2.28k | { |
2571 | 2.28k | ps_codec->s_cfg.u4_vbv_buf_size = ps_cfg->u4_vbv_buf_size; |
2572 | 2.28k | ps_codec->s_cfg.u4_vbv_buffer_delay = ps_cfg->u4_vbv_buffer_delay; |
2573 | | |
2574 | | // irc_change_buffer_delay(ps_codec->s_rate_control.pps_rate_control_api, ps_codec->s_cfg.u4_vbv_buffer_delay); |
2575 | | |
2576 | | // TODO: remove this when the support for changing buffer dynamically |
2577 | | // is yet to be added. |
2578 | 2.28k | u4_init_rc = 1; |
2579 | 2.28k | } |
2580 | 40.6k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_AIR_PARAMS) |
2581 | 3.90k | { |
2582 | 3.90k | if (ps_curr_cfg->e_air_mode != ps_cfg->e_air_mode |
2583 | 2.27k | || ps_curr_cfg->u4_air_refresh_period |
2584 | 2.27k | != ps_cfg->u4_air_refresh_period) |
2585 | 3.89k | { |
2586 | 3.89k | ps_curr_cfg->e_air_mode = ps_cfg->e_air_mode; |
2587 | 3.89k | ps_curr_cfg->u4_air_refresh_period = ps_cfg->u4_air_refresh_period; |
2588 | | |
2589 | 3.89k | ih264e_init_air_map(ps_codec); |
2590 | | |
2591 | | /* reset air counter */ |
2592 | 3.89k | ps_codec->i4_air_pic_cnt = -1; |
2593 | 3.89k | } |
2594 | 3.90k | } |
2595 | 36.7k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_PROFILE_PARAMS) |
2596 | 3.90k | { |
2597 | 3.90k | ps_codec->s_cfg.e_profile = ps_cfg->e_profile; |
2598 | 3.90k | ps_codec->s_cfg.u4_entropy_coding_mode = ps_cfg->u4_entropy_coding_mode; |
2599 | 3.90k | } |
2600 | 32.8k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_NUM_CORES) |
2601 | 3.90k | { |
2602 | 3.90k | ps_codec->s_cfg.u4_num_cores = ps_cfg->u4_num_cores; |
2603 | 3.90k | } |
2604 | 28.9k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_VUI_PARAMS) |
2605 | 3.90k | { |
2606 | 3.90k | ps_codec->s_cfg.s_vui = ps_cfg->s_vui; |
2607 | 3.90k | } |
2608 | | |
2609 | 25.0k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_MDCV_PARAMS) |
2610 | 3.90k | { |
2611 | 3.90k | ps_codec->s_cfg.s_sei.u1_sei_mdcv_params_present_flag = |
2612 | 3.90k | ps_cfg->s_sei.u1_sei_mdcv_params_present_flag; |
2613 | 3.90k | ps_codec->s_cfg.s_sei.s_sei_mdcv_params = ps_cfg->s_sei.s_sei_mdcv_params; |
2614 | 3.90k | } |
2615 | 21.1k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_CLL_PARAMS) |
2616 | 3.90k | { |
2617 | 3.90k | ps_codec->s_cfg.s_sei.u1_sei_cll_params_present_flag = |
2618 | 3.90k | ps_cfg->s_sei.u1_sei_cll_params_present_flag; |
2619 | 3.90k | ps_codec->s_cfg.s_sei.s_sei_cll_params = ps_cfg->s_sei.s_sei_cll_params; |
2620 | 3.90k | } |
2621 | 17.2k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_AVE_PARAMS) |
2622 | 3.90k | { |
2623 | 3.90k | ps_codec->s_cfg.s_sei.u1_sei_ave_params_present_flag = |
2624 | 3.90k | ps_cfg->s_sei.u1_sei_ave_params_present_flag; |
2625 | 3.90k | ps_codec->s_cfg.s_sei.s_sei_ave_params = ps_cfg->s_sei.s_sei_ave_params; |
2626 | 3.90k | } |
2627 | 13.3k | else if (ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_CCV_PARAMS) |
2628 | 3.90k | { |
2629 | 3.90k | ps_codec->s_cfg.s_sei.u1_sei_ccv_params_present_flag = |
2630 | 3.90k | ps_cfg->s_sei.u1_sei_ccv_params_present_flag; |
2631 | 3.90k | ps_codec->s_cfg.s_sei.s_sei_ccv_params = ps_cfg->s_sei.s_sei_ccv_params; |
2632 | 3.90k | } |
2633 | 9.43k | else if(ps_cfg->e_cmd == IVE_CMD_CTL_SET_SEI_SII_PARAMS) |
2634 | 3.90k | { |
2635 | 3.90k | ps_codec->s_cfg.s_sei.u1_sei_sii_params_present_flag = |
2636 | 3.90k | ps_cfg->s_sei.u1_sei_sii_params_present_flag; |
2637 | 3.90k | ps_codec->s_cfg.s_sei.s_sei_sii_params = ps_cfg->s_sei.s_sei_sii_params; |
2638 | 3.90k | } |
2639 | | |
2640 | | /* reset RC model */ |
2641 | 73.5k | if (u4_init_rc) |
2642 | 5.08k | { |
2643 | | /* init qp */ |
2644 | 5.08k | UWORD8 au1_init_qp[MAX_PIC_TYPE]; |
2645 | | |
2646 | | /* min max qp */ |
2647 | 5.08k | UWORD8 au1_min_max_qp[2 * MAX_PIC_TYPE]; |
2648 | | |
2649 | | /* init i,p,b qp */ |
2650 | 5.08k | au1_init_qp[0] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp]; |
2651 | 5.08k | au1_init_qp[1] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp]; |
2652 | 5.08k | au1_init_qp[2] = gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp]; |
2653 | | |
2654 | | /* init min max qp */ |
2655 | 5.08k | au1_min_max_qp[2 * I_PIC] = |
2656 | 5.08k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_min]; |
2657 | 5.08k | au1_min_max_qp[2 * I_PIC + 1] = |
2658 | 5.08k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_i_qp_max]; |
2659 | | |
2660 | 5.08k | au1_min_max_qp[2 * P_PIC] = |
2661 | 5.08k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_min]; |
2662 | 5.08k | au1_min_max_qp[2 * P_PIC + 1] = |
2663 | 5.08k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_p_qp_max]; |
2664 | | |
2665 | 5.08k | au1_min_max_qp[2 * B_PIC] = |
2666 | 5.08k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_min]; |
2667 | 5.08k | au1_min_max_qp[2 * B_PIC + 1] = |
2668 | 5.08k | gau1_h264_to_mpeg2_qmap[ps_codec->s_cfg.u4_b_qp_max]; |
2669 | | |
2670 | | /* get rc mode */ |
2671 | 5.08k | switch (ps_codec->s_cfg.e_rc_mode) |
2672 | 5.08k | { |
2673 | 2.13k | case IVE_RC_STORAGE: |
2674 | 2.13k | ps_codec->s_rate_control.e_rc_type = VBR_STORAGE; |
2675 | 2.13k | break; |
2676 | | |
2677 | 1.56k | case IVE_RC_CBR_NON_LOW_DELAY: |
2678 | 1.56k | ps_codec->s_rate_control.e_rc_type = CBR_NLDRC; |
2679 | 1.56k | break; |
2680 | | |
2681 | 0 | case IVE_RC_CBR_LOW_DELAY: |
2682 | 0 | ps_codec->s_rate_control.e_rc_type = CBR_LDRC; |
2683 | 0 | break; |
2684 | | |
2685 | 1.37k | case IVE_RC_NONE: |
2686 | 1.37k | ps_codec->s_rate_control.e_rc_type = CONST_QP; |
2687 | 1.37k | break; |
2688 | | |
2689 | 0 | default: |
2690 | 0 | break; |
2691 | 5.08k | } |
2692 | | |
2693 | | /* init rate control */ |
2694 | 5.08k | ih264e_rc_init(ps_codec->s_rate_control.pps_rate_control_api, |
2695 | 5.08k | ps_codec->s_rate_control.pps_frame_time, |
2696 | 5.08k | ps_codec->s_rate_control.pps_time_stamp, |
2697 | 5.08k | ps_codec->s_rate_control.pps_pd_frm_rate, |
2698 | 5.08k | ps_codec->s_cfg.u4_max_framerate, |
2699 | 5.08k | ps_codec->s_cfg.u4_src_frame_rate, |
2700 | 5.08k | ps_codec->s_cfg.u4_tgt_frame_rate, |
2701 | 5.08k | ps_codec->s_rate_control.e_rc_type, |
2702 | 5.08k | ps_codec->s_cfg.u4_target_bitrate, |
2703 | 5.08k | ps_codec->s_cfg.u4_max_bitrate, |
2704 | 5.08k | ps_codec->s_cfg.u4_vbv_buffer_delay, |
2705 | 5.08k | ps_codec->s_cfg.u4_i_frm_interval, |
2706 | 5.08k | ps_codec->s_cfg.u4_num_bframes + 1, au1_init_qp, |
2707 | 5.08k | ps_codec->s_cfg.u4_num_bframes + 2, au1_min_max_qp, |
2708 | 5.08k | ps_codec->s_cfg.u4_max_level); |
2709 | 5.08k | } |
2710 | | |
2711 | 73.5k | return err; |
2712 | 73.5k | } |
2713 | | |
2714 | | /** |
2715 | | ******************************************************************************* |
2716 | | * |
2717 | | * @brief |
2718 | | * Sets default encoder config parameters |
2719 | | * |
2720 | | * @par Description: |
2721 | | * Sets default dynamic parameters. Will be called in ih264e_init() to ensure |
2722 | | * that even if set_params is not called, codec continues to work |
2723 | | * |
2724 | | * @param[in] ps_cfg |
2725 | | * Pointer to encoder config params |
2726 | | * |
2727 | | * @returns error status |
2728 | | * |
2729 | | * @remarks none |
2730 | | * |
2731 | | ******************************************************************************* |
2732 | | */ |
2733 | | static WORD32 ih264e_set_default_params(cfg_params_t *ps_cfg) |
2734 | 7.81k | { |
2735 | 7.81k | WORD32 ret = IV_SUCCESS; |
2736 | | |
2737 | 7.81k | ps_cfg->u4_max_wd = MAX_WD; |
2738 | 7.81k | ps_cfg->u4_max_ht = MAX_HT; |
2739 | 7.81k | ps_cfg->u4_max_ref_cnt = MAX_REF_CNT; |
2740 | 7.81k | ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT; |
2741 | 7.81k | ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL; |
2742 | 7.81k | ps_cfg->e_inp_color_fmt = IV_YUV_420SP_UV; |
2743 | 7.81k | ps_cfg->u4_enable_recon = DEFAULT_RECON_ENABLE; |
2744 | 7.81k | ps_cfg->u4_enable_quality_metrics = DEFAULT_QUALITY_METRICS_ENABLE; |
2745 | 7.81k | ps_cfg->e_recon_color_fmt = IV_YUV_420P; |
2746 | 7.81k | ps_cfg->u4_enc_speed_preset = IVE_FASTEST; |
2747 | 7.81k | ps_cfg->e_rc_mode = DEFAULT_RC; |
2748 | 7.81k | ps_cfg->u4_max_framerate = DEFAULT_MAX_FRAMERATE; |
2749 | 7.81k | ps_cfg->u4_max_bitrate = DEFAULT_MAX_BITRATE; |
2750 | 7.81k | ps_cfg->u4_num_bframes = DEFAULT_MAX_NUM_BFRAMES; |
2751 | 7.81k | ps_cfg->e_content_type = IV_PROGRESSIVE; |
2752 | 7.81k | ps_cfg->u4_max_srch_rng_x = DEFAULT_MAX_SRCH_RANGE_X; |
2753 | 7.81k | ps_cfg->u4_max_srch_rng_y = DEFAULT_MAX_SRCH_RANGE_Y; |
2754 | 7.81k | ps_cfg->e_slice_mode = IVE_SLICE_MODE_NONE; |
2755 | 7.81k | ps_cfg->u4_slice_param = DEFAULT_SLICE_PARAM; |
2756 | 7.81k | ps_cfg->e_arch = ih264e_default_arch(); |
2757 | 7.81k | ps_cfg->e_soc = SOC_GENERIC; |
2758 | 7.81k | ps_cfg->u4_disp_wd = MAX_WD; |
2759 | 7.81k | ps_cfg->u4_disp_ht = MAX_HT; |
2760 | 7.81k | ps_cfg->u4_wd = MAX_WD; |
2761 | 7.81k | ps_cfg->u4_ht = MAX_HT; |
2762 | 7.81k | ps_cfg->u4_src_frame_rate = DEFAULT_SRC_FRAME_RATE; |
2763 | 7.81k | ps_cfg->u4_tgt_frame_rate = DEFAULT_TGT_FRAME_RATE; |
2764 | 7.81k | ps_cfg->u4_target_bitrate = DEFAULT_BITRATE; |
2765 | 7.81k | ps_cfg->e_frame_type = IV_NA_FRAME; |
2766 | 7.81k | ps_cfg->e_enc_mode = IVE_ENC_MODE_DEFAULT; |
2767 | 7.81k | ps_cfg->u4_i_qp = DEFAULT_I_QP; |
2768 | 7.81k | ps_cfg->u4_p_qp = DEFAULT_P_QP; |
2769 | 7.81k | ps_cfg->u4_b_qp = DEFAULT_B_QP; |
2770 | 7.81k | ps_cfg->u4_i_qp_min = DEFAULT_QP_MIN; |
2771 | 7.81k | ps_cfg->u4_i_qp_max = DEFAULT_QP_MAX; |
2772 | 7.81k | ps_cfg->u4_p_qp_min = DEFAULT_QP_MIN; |
2773 | 7.81k | ps_cfg->u4_p_qp_max = DEFAULT_QP_MAX; |
2774 | 7.81k | ps_cfg->u4_b_qp_min = DEFAULT_QP_MIN; |
2775 | 7.81k | ps_cfg->u4_b_qp_max = DEFAULT_QP_MAX; |
2776 | 7.81k | ps_cfg->e_air_mode = DEFAULT_AIR_MODE; |
2777 | 7.81k | ps_cfg->u4_air_refresh_period = DEFAULT_AIR_REFRESH_PERIOD; |
2778 | 7.81k | ps_cfg->u4_vbv_buffer_delay = DEFAULT_VBV_DELAY; |
2779 | 7.81k | ps_cfg->u4_vbv_buf_size = DEFAULT_VBV_SIZE; |
2780 | 7.81k | ps_cfg->u4_num_cores = DEFAULT_NUM_CORES; |
2781 | 7.81k | ps_cfg->u4_me_speed_preset = DEFAULT_ME_SPEED_PRESET; |
2782 | 7.81k | ps_cfg->u4_enable_hpel = DEFAULT_HPEL; |
2783 | 7.81k | ps_cfg->u4_enable_qpel = DEFAULT_QPEL; |
2784 | 7.81k | ps_cfg->u4_enable_intra_4x4 = DEFAULT_I4; |
2785 | 7.81k | ps_cfg->u4_enable_intra_8x8 = DEFAULT_I8; |
2786 | 7.81k | ps_cfg->u4_enable_intra_16x16 = DEFAULT_I16; |
2787 | 7.81k | ps_cfg->u4_enable_fast_sad = DEFAULT_ENABLE_FAST_SAD; |
2788 | 7.81k | ps_cfg->u4_enable_satqd = DEFAULT_ENABLE_SATQD; |
2789 | 7.81k | ps_cfg->i4_min_sad = |
2790 | 7.81k | (ps_cfg->u4_enable_satqd == DEFAULT_ENABLE_SATQD) ? |
2791 | 7.81k | DEFAULT_MIN_SAD_ENABLE : |
2792 | 7.81k | DEFAULT_MIN_SAD_DISABLE; |
2793 | 7.81k | ps_cfg->u4_srch_rng_x = DEFAULT_SRCH_RNG_X; |
2794 | 7.81k | ps_cfg->u4_srch_rng_y = DEFAULT_SRCH_RNG_Y; |
2795 | 7.81k | ps_cfg->u4_i_frm_interval = DEFAULT_I_INTERVAL; |
2796 | 7.81k | ps_cfg->u4_idr_frm_interval = DEFAULT_IDR_INTERVAL; |
2797 | 7.81k | ps_cfg->u4_disable_deblock_level = DEFAULT_DISABLE_DEBLK_LEVEL; |
2798 | 7.81k | ps_cfg->e_profile = DEFAULT_PROFILE; |
2799 | 7.81k | ps_cfg->u4_timestamp_low = 0; |
2800 | 7.81k | ps_cfg->u4_timestamp_high = 0; |
2801 | 7.81k | ps_cfg->u4_is_valid = 1; |
2802 | 7.81k | ps_cfg->e_cmd = IVE_CMD_CT_NA; |
2803 | 7.81k | ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4; |
2804 | 7.81k | ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4; |
2805 | 7.81k | ps_cfg->u4_entropy_coding_mode = DEFAULT_ENTROPY_CODING_MODE; |
2806 | 7.81k | ps_cfg->u4_weighted_prediction = 0; |
2807 | 7.81k | ps_cfg->u4_constrained_intra_pred = DEFAULT_CONSTRAINED_INTRAPRED; |
2808 | 7.81k | ps_cfg->u4_pic_info_type = 0; |
2809 | 7.81k | ps_cfg->u4_mb_info_type = 0; |
2810 | 7.81k | ps_cfg->s_vui.u1_video_signal_type_present_flag = 0; |
2811 | 7.81k | ps_cfg->s_vui.u1_colour_description_present_flag = 0; |
2812 | | |
2813 | 7.81k | return ret; |
2814 | 7.81k | } |
2815 | | |
2816 | | /** |
2817 | | ******************************************************************************* |
2818 | | * |
2819 | | * @brief |
2820 | | * Initialize encoder context. This will be called by init_mem_rec and during |
2821 | | * codec reset |
2822 | | * |
2823 | | * @par Description: |
2824 | | * Initializes the context |
2825 | | * |
2826 | | * @param[in] ps_codec |
2827 | | * Codec context pointer |
2828 | | * |
2829 | | * @returns error status |
2830 | | * |
2831 | | * @remarks none |
2832 | | * |
2833 | | ******************************************************************************* |
2834 | | */ |
2835 | | static WORD32 ih264e_init(codec_t *ps_codec) |
2836 | 3.90k | { |
2837 | | /* enc config param set */ |
2838 | 3.90k | cfg_params_t *ps_cfg = &(ps_codec->s_cfg); |
2839 | | |
2840 | | /* temp var */ |
2841 | 3.90k | WORD32 i; |
2842 | | |
2843 | | /* coded pic count */ |
2844 | 3.90k | ps_codec->i4_poc = 0; |
2845 | | |
2846 | | /* Number of API calls to encode are made */ |
2847 | 3.90k | ps_codec->i4_encode_api_call_cnt = -1; |
2848 | | |
2849 | | /* Indicates no header has been generated yet */ |
2850 | 3.90k | ps_codec->u4_header_generated = 0; |
2851 | | |
2852 | | /* Number of pictures encoded */ |
2853 | 3.90k | ps_codec->i4_pic_cnt = -1; |
2854 | | |
2855 | | /* Number of threads created */ |
2856 | 3.90k | ps_codec->i4_proc_thread_cnt = 0; |
2857 | | |
2858 | | /* ctl mutex init */ |
2859 | 3.90k | ithread_mutex_init(ps_codec->pv_ctl_mutex); |
2860 | | |
2861 | 3.90k | if (ps_codec->s_cfg.u4_keep_threads_active) |
2862 | 3.90k | { |
2863 | | /* thread pool mutex init */ |
2864 | 3.90k | ithread_mutex_init(ps_codec->s_thread_pool.pv_thread_pool_mutex); |
2865 | | |
2866 | | /* thread pool conditional init */ |
2867 | 3.90k | ithread_cond_init(ps_codec->s_thread_pool.pv_thread_pool_cond); |
2868 | 3.90k | } |
2869 | | |
2870 | | /* Set encoder chroma format */ |
2871 | 3.90k | ps_codec->e_codec_color_format = |
2872 | 3.90k | (ps_cfg->e_inp_color_fmt == IV_YUV_420SP_VU) ? |
2873 | 2.85k | IV_YUV_420SP_VU : IV_YUV_420SP_UV; |
2874 | | |
2875 | | /* Number of continuous frames where deblocking was disabled */ |
2876 | 3.90k | ps_codec->i4_disable_deblk_pic_cnt = 0; |
2877 | | |
2878 | | /* frame num */ |
2879 | 3.90k | ps_codec->i4_frame_num = 0; |
2880 | | |
2881 | | /* set the current frame type to I frame, since we are going to start encoding*/ |
2882 | 3.90k | ps_codec->force_curr_frame_type = IV_NA_FRAME; |
2883 | | |
2884 | | /* idr_pic_id */ |
2885 | 3.90k | ps_codec->i4_idr_pic_id = -1; |
2886 | | |
2887 | | /* Flush mode */ |
2888 | 3.90k | ps_codec->i4_flush_mode = 0; |
2889 | | |
2890 | | /* Encode header mode */ |
2891 | 3.90k | ps_codec->i4_header_mode = 0; |
2892 | | |
2893 | | /* Encode generate header */ |
2894 | 3.90k | ps_codec->i4_gen_header = 0; |
2895 | | |
2896 | | /* To signal successful completion of init */ |
2897 | 3.90k | ps_codec->i4_init_done = 1; |
2898 | | |
2899 | | /* To signal that at least one picture was decoded */ |
2900 | 3.90k | ps_codec->i4_first_pic_done = 0; |
2901 | | |
2902 | | /* Reset Codec */ |
2903 | 3.90k | ps_codec->i4_reset_flag = 0; |
2904 | | |
2905 | | /* Current error code */ |
2906 | 3.90k | ps_codec->i4_error_code = IH264E_SUCCESS; |
2907 | | |
2908 | | /* threshold residue */ |
2909 | 3.90k | ps_codec->u4_thres_resi = 1; |
2910 | | |
2911 | | /* inter gating enable */ |
2912 | 3.90k | ps_codec->u4_inter_gate = 0; |
2913 | | |
2914 | | /* entropy mutex init */ |
2915 | 3.90k | ithread_mutex_init(ps_codec->pv_entropy_mutex); |
2916 | | |
2917 | | /* sps id */ |
2918 | 3.90k | ps_codec->i4_sps_id = 0; |
2919 | | |
2920 | | /* sps id */ |
2921 | 3.90k | ps_codec->i4_pps_id = 0; |
2922 | | |
2923 | | /* Process thread created status */ |
2924 | 3.90k | memset(ps_codec->ai4_process_thread_created, 0, |
2925 | 3.90k | sizeof(ps_codec->ai4_process_thread_created)); |
2926 | | |
2927 | 3.90k | memset(&ps_codec->s_global_quality_stats, 0, sizeof(ps_codec->s_global_quality_stats)); |
2928 | | |
2929 | | /* Number of MBs processed together */ |
2930 | 3.90k | ps_codec->i4_proc_nmb = 8; |
2931 | | |
2932 | | /* Previous POC msb */ |
2933 | 3.90k | ps_codec->i4_prev_poc_msb = 0; |
2934 | | |
2935 | | /* Previous POC lsb */ |
2936 | 3.90k | ps_codec->i4_prev_poc_lsb = -1; |
2937 | | |
2938 | | /* max Previous POC lsb */ |
2939 | 3.90k | ps_codec->i4_max_prev_poc_lsb = -1; |
2940 | | |
2941 | | /* sps, pps status */ |
2942 | 3.90k | { |
2943 | 3.90k | sps_t *ps_sps = ps_codec->ps_sps_base; |
2944 | 3.90k | pps_t *ps_pps = ps_codec->ps_pps_base; |
2945 | | |
2946 | 132k | for (i = 0; i < MAX_SPS_CNT; i++) |
2947 | 128k | { |
2948 | 128k | ps_sps->i1_sps_valid = 0; |
2949 | 128k | ps_sps++; |
2950 | 128k | } |
2951 | | |
2952 | 1.00M | for (i = 0; i < MAX_PPS_CNT; i++) |
2953 | 1.00M | { |
2954 | 1.00M | ps_pps->i1_pps_valid = 0; |
2955 | 1.00M | ps_pps++; |
2956 | 1.00M | } |
2957 | 3.90k | } |
2958 | | |
2959 | 3.90k | { |
2960 | 3.90k | WORD32 max_mb_rows = ps_cfg->i4_ht_mbs; |
2961 | | |
2962 | 3.90k | WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS; |
2963 | 3.90k | WORD32 clz; |
2964 | | |
2965 | | /* Use next power of two number of entries*/ |
2966 | 3.90k | clz = CLZ(num_jobs); |
2967 | 3.90k | num_jobs = 1 << (32 - clz); |
2968 | | |
2969 | | /* init process jobq */ |
2970 | 3.90k | ps_codec->pv_proc_jobq = ih264_list_init( |
2971 | 3.90k | ps_codec->pv_proc_jobq_buf, |
2972 | 3.90k | ps_codec->i4_proc_jobq_buf_size, num_jobs, |
2973 | 3.90k | sizeof(job_t), 10); |
2974 | 3.90k | RETURN_IF((ps_codec->pv_proc_jobq == NULL), IV_FAIL); |
2975 | 3.90k | ih264_list_reset(ps_codec->pv_proc_jobq); |
2976 | | |
2977 | | /* init entropy jobq */ |
2978 | 3.90k | ps_codec->pv_entropy_jobq = ih264_list_init( |
2979 | 3.90k | ps_codec->pv_entropy_jobq_buf, |
2980 | 3.90k | ps_codec->i4_entropy_jobq_buf_size, num_jobs, |
2981 | 3.90k | sizeof(job_t), 10); |
2982 | 3.90k | RETURN_IF((ps_codec->pv_entropy_jobq == NULL), IV_FAIL); |
2983 | 3.90k | ih264_list_reset(ps_codec->pv_entropy_jobq); |
2984 | 3.90k | } |
2985 | | |
2986 | | /* Update the jobq context to all the threads */ |
2987 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
2988 | 31.2k | { |
2989 | 31.2k | ps_codec->as_process[i].pv_proc_jobq = ps_codec->pv_proc_jobq; |
2990 | 31.2k | ps_codec->as_process[i].pv_entropy_jobq = ps_codec->pv_entropy_jobq; |
2991 | | |
2992 | | /* i4_id always stays between 0 and MAX_PROCESS_THREADS */ |
2993 | 31.2k | ps_codec->as_process[i].i4_id = |
2994 | 31.2k | (i >= MAX_PROCESS_THREADS) ? |
2995 | 31.2k | (i - MAX_PROCESS_THREADS) : i; |
2996 | 31.2k | ps_codec->as_process[i].ps_codec = ps_codec; |
2997 | | |
2998 | 31.2k | ps_codec->as_process[i].s_entropy.pv_proc_jobq = ps_codec->pv_proc_jobq; |
2999 | 31.2k | ps_codec->as_process[i].s_entropy.pv_entropy_jobq = |
3000 | 31.2k | ps_codec->pv_entropy_jobq; |
3001 | 31.2k | ps_codec->as_process[i].s_entropy.i4_abs_pic_order_cnt = -1; |
3002 | 31.2k | } |
3003 | | |
3004 | | /* Initialize MV Bank buffer manager */ |
3005 | 3.90k | ps_codec->pv_mv_buf_mgr = ih264_buf_mgr_init(ps_codec->pv_mv_buf_mgr_base); |
3006 | | |
3007 | | /* Initialize Picture buffer manager for reference buffers*/ |
3008 | 3.90k | ps_codec->pv_ref_buf_mgr = ih264_buf_mgr_init( |
3009 | 3.90k | ps_codec->pv_ref_buf_mgr_base); |
3010 | | |
3011 | | /* Initialize Picture buffer manager for input buffers*/ |
3012 | 3.90k | ps_codec->pv_inp_buf_mgr = ih264_buf_mgr_init( |
3013 | 3.90k | ps_codec->pv_inp_buf_mgr_base); |
3014 | | |
3015 | | /* Initialize buffer manager for output buffers*/ |
3016 | 3.90k | ps_codec->pv_out_buf_mgr = ih264_buf_mgr_init( |
3017 | 3.90k | ps_codec->pv_out_buf_mgr_base); |
3018 | | |
3019 | | /* buffer cnt in buffer manager */ |
3020 | 3.90k | ps_codec->i4_inp_buf_cnt = 0; |
3021 | 3.90k | ps_codec->i4_out_buf_cnt = 0; |
3022 | 3.90k | ps_codec->i4_ref_buf_cnt = 0; |
3023 | | |
3024 | 3.90k | ps_codec->ps_pic_buf = (pic_buf_t *) ps_codec->pv_pic_buf_base; |
3025 | 3.90k | memset(ps_codec->ps_pic_buf, 0, BUF_MGR_MAX_CNT * sizeof(pic_buf_t)); |
3026 | | |
3027 | | /* Initialize dpb manager */ |
3028 | 3.90k | ih264_dpb_mgr_init((dpb_mgr_t*) ps_codec->pv_dpb_mgr); |
3029 | | |
3030 | 3.90k | memset(ps_codec->as_ref_set, 0, |
3031 | 3.90k | sizeof(ref_set_t) * (MAX_DPB_SIZE + MAX_CTXT_SETS)); |
3032 | 70.3k | for (i = 0; i < (MAX_DPB_SIZE + MAX_CTXT_SETS); i++) |
3033 | 66.4k | { |
3034 | 66.4k | ps_codec->as_ref_set[i].i4_pic_cnt = -1; |
3035 | 66.4k | } |
3036 | | |
3037 | | /* fn ptr init */ |
3038 | 3.90k | ih264e_init_function_ptr(ps_codec); |
3039 | | |
3040 | | /* reset status flags */ |
3041 | 7.81k | for (i = 0; i < MAX_CTXT_SETS; i++) |
3042 | 3.90k | { |
3043 | 3.90k | ps_codec->au4_entropy_thread_active[i] = 0; |
3044 | 3.90k | ps_codec->ai4_pic_cnt[i] = -1; |
3045 | | |
3046 | 3.90k | ps_codec->s_rate_control.pre_encode_skip[i] = 0; |
3047 | 3.90k | ps_codec->s_rate_control.post_encode_skip[i] = 0; |
3048 | 3.90k | } |
3049 | | |
3050 | 3.90k | ps_codec->s_rate_control.num_intra_in_prev_frame = 0; |
3051 | 3.90k | ps_codec->s_rate_control.i4_avg_activity = 0; |
3052 | | |
3053 | 3.90k | return IV_SUCCESS; |
3054 | 3.90k | } |
3055 | | |
3056 | | /** |
3057 | | ******************************************************************************* |
3058 | | * |
3059 | | * @brief |
3060 | | * Gets number of memory records required by the codec |
3061 | | * |
3062 | | * @par Description: |
3063 | | * Gets codec memory requirements |
3064 | | * |
3065 | | * @param[in] pv_api_ip |
3066 | | * Pointer to input argument structure |
3067 | | * |
3068 | | * @param[out] pv_api_op |
3069 | | * Pointer to output argument structure |
3070 | | * |
3071 | | * @returns status |
3072 | | * |
3073 | | * @remarks |
3074 | | * |
3075 | | ******************************************************************************* |
3076 | | */ |
3077 | | static WORD32 ih264e_get_num_rec(void *pv_api_ip, void *pv_api_op) |
3078 | 3.92k | { |
3079 | | /* api call I/O structures */ |
3080 | 3.92k | ih264e_num_mem_rec_op_t *ps_op = pv_api_op; |
3081 | | |
3082 | 3.92k | UNUSED(pv_api_ip); |
3083 | | |
3084 | 3.92k | ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT; |
3085 | | |
3086 | 3.92k | return IV_SUCCESS; |
3087 | 3.92k | } |
3088 | | |
3089 | | /** |
3090 | | ******************************************************************************* |
3091 | | * |
3092 | | * @brief |
3093 | | * Fills memory records of the codec |
3094 | | * |
3095 | | * @par Description: |
3096 | | * Fills codec memory requirements |
3097 | | * |
3098 | | * @param[in] pv_api_ip |
3099 | | * Pointer to input argument structure |
3100 | | * |
3101 | | * @param[out] pv_api_op |
3102 | | * Pointer to output argument structure |
3103 | | * |
3104 | | * @returns error status |
3105 | | * |
3106 | | * @remarks none |
3107 | | * |
3108 | | ******************************************************************************* |
3109 | | */ |
3110 | | static WORD32 ih264e_fill_num_mem_rec(void *pv_api_ip, void *pv_api_op) |
3111 | 7.82k | { |
3112 | | /* api call I/O structures */ |
3113 | 7.82k | ih264e_fill_mem_rec_ip_t *ps_ip = pv_api_ip; |
3114 | 7.82k | ih264e_fill_mem_rec_op_t *ps_op = pv_api_op; |
3115 | | |
3116 | | /* profile / level info */ |
3117 | 7.82k | WORD32 level; |
3118 | 7.82k | WORD32 num_reorder_frames; |
3119 | 7.82k | WORD32 num_ref_frames; |
3120 | | |
3121 | | /* mem records */ |
3122 | 7.82k | WORD32 no_of_mem_rec; |
3123 | 7.82k | iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec; |
3124 | | |
3125 | | /* frame dimensions */ |
3126 | 7.82k | WORD32 max_wd_luma, max_ht_luma; |
3127 | 7.82k | WORD32 max_mb_rows, max_mb_cols, max_mb_cnt; |
3128 | | |
3129 | | /* temp var */ |
3130 | 7.82k | WORD32 i; |
3131 | | |
3132 | | /* error status */ |
3133 | 7.82k | IV_STATUS_T status = IV_SUCCESS; |
3134 | | |
3135 | 7.82k | num_reorder_frames = ps_ip->s_ive_ip.u4_max_reorder_cnt; |
3136 | 7.82k | num_ref_frames = ps_ip->s_ive_ip.u4_max_ref_cnt; |
3137 | | |
3138 | | /* mem records */ |
3139 | 7.82k | ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec; |
3140 | 7.82k | no_of_mem_rec = ps_ip->s_ive_ip.u4_num_mem_rec; |
3141 | | |
3142 | | /* frame dimensions */ |
3143 | 7.82k | max_ht_luma = ps_ip->s_ive_ip.u4_max_ht; |
3144 | 7.82k | max_wd_luma = ps_ip->s_ive_ip.u4_max_wd; |
3145 | 7.82k | max_ht_luma = ALIGN16(max_ht_luma); |
3146 | 7.82k | max_wd_luma = ALIGN16(max_wd_luma); |
3147 | 7.82k | max_mb_rows = max_ht_luma / MB_SIZE; |
3148 | 7.82k | max_mb_cols = max_wd_luma / MB_SIZE; |
3149 | 7.82k | max_mb_cnt = max_mb_rows * max_mb_cols; |
3150 | | |
3151 | | /* profile / level info */ |
3152 | 7.82k | level = ih264e_get_min_level(max_wd_luma, max_ht_luma); |
3153 | | |
3154 | | /* validate params */ |
3155 | 7.82k | if ((level < MIN_LEVEL) || (level > MAX_LEVEL)) |
3156 | 0 | { |
3157 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED; |
3158 | 0 | level = MAX_LEVEL; |
3159 | 0 | } |
3160 | | |
3161 | 7.82k | if (num_ref_frames > MAX_REF_CNT) |
3162 | 0 | { |
3163 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED; |
3164 | 0 | num_ref_frames = MAX_REF_CNT; |
3165 | 0 | } |
3166 | | |
3167 | 7.82k | if (num_reorder_frames > MAX_REF_CNT) |
3168 | 0 | { |
3169 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED; |
3170 | 0 | num_reorder_frames = MAX_REF_CNT; |
3171 | 0 | } |
3172 | | |
3173 | | /* Set all memory records as persistent and alignment as 128 by default */ |
3174 | 7.82k | ps_mem_rec = ps_mem_rec_base; |
3175 | 406k | for (i = 0; i < no_of_mem_rec; i++) |
3176 | 399k | { |
3177 | 399k | ps_mem_rec->u4_mem_alignment = 128; |
3178 | 399k | ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM; |
3179 | 399k | ps_mem_rec++; |
3180 | 399k | } |
3181 | | |
3182 | | /************************************************************************ |
3183 | | * Request memory for h264 encoder handle * |
3184 | | ***********************************************************************/ |
3185 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_IV_OBJ]; |
3186 | 7.82k | { |
3187 | 7.82k | ps_mem_rec->u4_mem_size = sizeof(iv_obj_t); |
3188 | 7.82k | } |
3189 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_IV_OBJ, ps_mem_rec->u4_mem_size); |
3190 | | |
3191 | | /************************************************************************ |
3192 | | * Request memory for h264 encoder context * |
3193 | | ***********************************************************************/ |
3194 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC]; |
3195 | 7.82k | { |
3196 | 7.82k | ps_mem_rec->u4_mem_size = sizeof(codec_t); |
3197 | 7.82k | } |
3198 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CODEC, ps_mem_rec->u4_mem_size); |
3199 | | |
3200 | | /************************************************************************ |
3201 | | * Request memory for CABAC context * |
3202 | | ***********************************************************************/ |
3203 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC]; |
3204 | 7.82k | { |
3205 | 7.82k | ps_mem_rec->u4_mem_size = sizeof(cabac_ctxt_t); |
3206 | 7.82k | } |
3207 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC, ps_mem_rec->u4_mem_size); |
3208 | | |
3209 | | /************************************************************************ |
3210 | | * Request memory for CABAC MB info * |
3211 | | ***********************************************************************/ |
3212 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO]; |
3213 | 7.82k | { |
3214 | 7.82k | ps_mem_rec->u4_mem_size = ((max_mb_cols + 1) + 1) |
3215 | 7.82k | * sizeof(mb_info_ctxt_t); |
3216 | 7.82k | } |
3217 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CABAC_MB_INFO, ps_mem_rec->u4_mem_size); |
3218 | | |
3219 | | |
3220 | | /************************************************************************ |
3221 | | * Request memory for entropy context * |
3222 | | * In multi core encoding, each row is assumed to be launched on a * |
3223 | | * thread. The rows below can only start after its neighbors are coded * |
3224 | | * The status of an mb coded/uncoded is signaled via entropy map. * |
3225 | | * 1. One word32 to store skip run cnt * |
3226 | | * 2. mb entropy map (mb status entropy coded/uncoded). The size* |
3227 | | * of the entropy map is max mb cols. Further allocate one * |
3228 | | * more additional row to evade checking for row -1. * |
3229 | | * 3. size of bit stream buffer to store bit stream ctxt. * |
3230 | | * 4. Entropy coding is dependent on nnz coefficient count for * |
3231 | | * the neighbor blocks. It is sufficient to maintain one row * |
3232 | | * worth of nnz as entropy for lower row waits on entropy map* |
3233 | | ************************************************************************/ |
3234 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY]; |
3235 | 7.82k | { |
3236 | | /* total size of the mem record */ |
3237 | 7.82k | WORD32 total_size = 0; |
3238 | | |
3239 | | /* size of skip mb run */ |
3240 | 7.82k | total_size += sizeof(WORD32); |
3241 | 7.82k | total_size = ALIGN8(total_size); |
3242 | | |
3243 | | /* size in bytes to store entropy status of an entire frame */ |
3244 | 7.82k | total_size += (max_mb_cols * max_mb_rows); |
3245 | | /* add an additional 1 row of bytes to evade the special case of row 0 */ |
3246 | 7.82k | total_size += max_mb_cols; |
3247 | 7.82k | total_size = ALIGN128(total_size); |
3248 | | |
3249 | | /* size of bit stream buffer */ |
3250 | 7.82k | total_size += sizeof(bitstrm_t); |
3251 | 7.82k | total_size = ALIGN128(total_size); |
3252 | | |
3253 | | /* top nnz luma */ |
3254 | 7.82k | total_size += (max_mb_cols * 4 * sizeof(UWORD8)); |
3255 | 7.82k | total_size = ALIGN128(total_size); |
3256 | | |
3257 | | /* top nnz cbcr */ |
3258 | 7.82k | total_size += (max_mb_cols * 4 * sizeof(UWORD8)); |
3259 | 7.82k | total_size = ALIGN128(total_size); |
3260 | | |
3261 | | /* total size per each proc ctxt */ |
3262 | 7.82k | total_size *= MAX_CTXT_SETS; |
3263 | | |
3264 | 7.82k | ps_mem_rec->u4_mem_size = total_size; |
3265 | 7.82k | } |
3266 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY, ps_mem_rec->u4_mem_size); |
3267 | | |
3268 | | /************************************************************************ |
3269 | | * The residue coefficients that needs to be entropy coded are packed * |
3270 | | * at a buffer space by the proc threads. The entropy thread shall * |
3271 | | * read from the buffer space, unpack them and encode the same. The * |
3272 | | * buffer space required to pack a row of mbs are as follows. * |
3273 | | * Assuming transform_8x8_flag is disabled, * |
3274 | | * In the worst case, 1 mb contains 1 dc 4x4 luma sub block, followed * |
3275 | | * by 16 ac 4x4 luma sub blocks, 2 dc chroma 2x2 sub blocks, followed * |
3276 | | * by 8 ac 4x4 chroma sub blocks. * |
3277 | | * For the sake of simplicity we assume that all sub blocks are of * |
3278 | | * type 4x4. The packing of each 4x4 is depicted by the structure * |
3279 | | * tu_sblk_coeff_data_t * |
3280 | | ************************************************************************/ |
3281 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA]; |
3282 | 7.82k | { |
3283 | | /* temp var */ |
3284 | 7.82k | WORD32 size = 0; |
3285 | | |
3286 | | /* size of coeff data of 1 mb */ |
3287 | 7.82k | size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS; |
3288 | | |
3289 | | /* size of coeff data of 1 row of mb's */ |
3290 | 7.82k | size *= max_mb_cols; |
3291 | | |
3292 | | /* align to avoid any false sharing across threads */ |
3293 | 7.82k | size = ALIGN64(size); |
3294 | | |
3295 | | /* size for one full frame */ |
3296 | 7.82k | size *= max_mb_rows; |
3297 | | |
3298 | | /* size of each proc buffer set (ping, pong) */ |
3299 | 7.82k | size *= MAX_CTXT_SETS; |
3300 | | |
3301 | 7.82k | ps_mem_rec->u4_mem_size = size; |
3302 | 7.82k | } |
3303 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_COEFF_DATA, ps_mem_rec->u4_mem_size); |
3304 | | |
3305 | | /************************************************************************ |
3306 | | * while encoding an mb, the mb header data is signaled to the entropy* |
3307 | | * thread by writing to a buffer space. the size of header data per mb * |
3308 | | * is assumed to be 40 bytes * |
3309 | | * TODO: revisit this inference * |
3310 | | ************************************************************************/ |
3311 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA]; |
3312 | 7.82k | { |
3313 | | /* temp var */ |
3314 | 7.82k | WORD32 size; |
3315 | | |
3316 | | /* size per MB */ |
3317 | 7.82k | size = 40; |
3318 | | |
3319 | | /* size for 1 row of mbs */ |
3320 | 7.82k | size = size * max_mb_cols; |
3321 | | |
3322 | | /* align to avoid any false sharing across threads */ |
3323 | 7.82k | size = ALIGN64(size); |
3324 | | |
3325 | | /* size for one full frame */ |
3326 | 7.82k | size *= max_mb_rows; |
3327 | | |
3328 | | /* size of each proc buffer set (ping, pong) */ |
3329 | 7.82k | size *= MAX_CTXT_SETS; |
3330 | | |
3331 | 7.82k | ps_mem_rec->u4_mem_size = size; |
3332 | 7.82k | } |
3333 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_HEADER_DATA, ps_mem_rec->u4_mem_size); |
3334 | | |
3335 | | /************************************************************************ |
3336 | | * Size for holding mv_buf_t for each MV Bank. * |
3337 | | * Note this allocation is done for BUF_MGR_MAX_CNT instead of * |
3338 | | * MAX_DPB_SIZE or max_dpb_size for following reasons * |
3339 | | * max_dpb_size will be based on max_wd and max_ht * |
3340 | | * For higher max_wd and max_ht this number will be smaller than * |
3341 | | * MAX_DPB_SIZE But during actual initialization number of buffers * |
3342 | | * allocated can be more. * |
3343 | | * * |
3344 | | * One extra MV Bank is needed to hold current pics MV bank. * |
3345 | | * Since this is only a structure allocation and not actual buffer * |
3346 | | * allocation, it is allocated for BUF_MGR_MAX_CNT entries * |
3347 | | ************************************************************************/ |
3348 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK]; |
3349 | 7.82k | { |
3350 | | /* max luma samples */ |
3351 | 7.82k | WORD32 max_luma_samples = 0; |
3352 | | |
3353 | | /* determine max luma samples */ |
3354 | 133k | for (i = 0; i < 16; i++) |
3355 | 125k | if (level ==(WORD32)gas_ih264_lvl_tbl[i].u4_level_idc) |
3356 | 7.82k | max_luma_samples = gas_ih264_lvl_tbl[i].u4_max_fs |
3357 | 7.82k | << (BLK_SIZE + BLK_SIZE); |
3358 | | |
3359 | 7.82k | ps_mem_rec->u4_mem_size = ih264_buf_mgr_size(); |
3360 | | |
3361 | | /************************************************************************ |
3362 | | * Allocate for pu_map, enc_pu_t and pic_pu_idx for each MV bank * |
3363 | | * Note: Number of luma samples is not max_wd * max_ht here, instead it * |
3364 | | * is set to maximum number of luma samples allowed at the given level. * |
3365 | | * This is done to ensure that any stream with width and height lesser * |
3366 | | * than max_wd and max_ht is supported. Number of buffers required can * |
3367 | | * be greater for lower width and heights at a given level and this * |
3368 | | * increased number of buffers might require more memory than what * |
3369 | | * max_wd and max_ht buffer would have required Also note one extra * |
3370 | | * buffer is allocated to store current pictures MV bank. * |
3371 | | ***********************************************************************/ |
3372 | | |
3373 | 7.82k | ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(mv_buf_t); |
3374 | | |
3375 | 7.82k | ps_mem_rec->u4_mem_size += (num_ref_frames + num_reorder_frames |
3376 | 7.82k | + MAX_CTXT_SETS) |
3377 | 7.82k | * ih264e_get_pic_mv_bank_size(max_luma_samples); |
3378 | 7.82k | } |
3379 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBANK, ps_mem_rec->u4_mem_size); |
3380 | | |
3381 | | /************************************************************************ |
3382 | | * While encoding inter slices, to compute the cost of encoding an mb * |
3383 | | * with the mv's at hand, we employ the expression cost = sad + lambda * |
3384 | | * x mv_bits. Here mv_bits is the total number of bits taken to represe* |
3385 | | * nt the mv in the stream. The mv bits for all the possible mv are * |
3386 | | * stored in the look up table. The mem record for this look up table * |
3387 | | * is given below. * |
3388 | | ************************************************************************/ |
3389 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS]; |
3390 | 7.82k | { |
3391 | | /* max srch range x */ |
3392 | 7.82k | UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x; |
3393 | | |
3394 | | /* max srch range y */ |
3395 | 7.82k | UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y; |
3396 | | |
3397 | | /* max srch range */ |
3398 | 7.82k | UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y); |
3399 | | |
3400 | | /* due to subpel */ |
3401 | 7.82k | u4_max_srch_range <<= 2; |
3402 | | |
3403 | | /* due to mv on either direction */ |
3404 | 7.82k | u4_max_srch_range = (u4_max_srch_range << 1); |
3405 | | |
3406 | | /* due to pred mv + zero */ |
3407 | 7.82k | u4_max_srch_range = (u4_max_srch_range << 1) + 1; |
3408 | | |
3409 | 7.82k | u4_max_srch_range = ALIGN128(u4_max_srch_range); |
3410 | | |
3411 | 7.82k | ps_mem_rec->u4_mem_size = u4_max_srch_range; |
3412 | 7.82k | } |
3413 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MVBITS, ps_mem_rec->u4_mem_size); |
3414 | | |
3415 | | /************************************************************************ |
3416 | | * Frame level Intra Cost Map. During intra/inter analysis preserve the* |
3417 | | * intra mb cost for future complexity estimation. * |
3418 | | * NOTE: The cost map is a overlay on the previous frame. In case if an* |
3419 | | * mb is not intra analyzed, the cost here represents its collocated mb* |
3420 | | * intra cost. This traversal can go till the latest I frame at worse * |
3421 | | ************************************************************************/ |
3422 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_INTRA_COST]; |
3423 | 7.82k | { |
3424 | | /* total size of the mem record */ |
3425 | 7.82k | WORD32 total_size = 0; |
3426 | | |
3427 | | /* size in bytes to mb core coding status of an entire frame */ |
3428 | 7.82k | total_size = max_mb_cnt * sizeof(WORD32); |
3429 | | |
3430 | 7.82k | ps_mem_rec->u4_mem_size = total_size; |
3431 | 7.82k | } |
3432 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_INTRA_COST, ps_mem_rec->u4_mem_size); |
3433 | | |
3434 | | /************************************************************************ |
3435 | | * Request memory for SPS * |
3436 | | ***********************************************************************/ |
3437 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS]; |
3438 | 7.82k | { |
3439 | 7.82k | ps_mem_rec->u4_mem_size = MAX_SPS_CNT * sizeof(sps_t); |
3440 | 7.82k | } |
3441 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SPS, ps_mem_rec->u4_mem_size); |
3442 | | |
3443 | | /************************************************************************ |
3444 | | * Request memory for PPS * |
3445 | | ***********************************************************************/ |
3446 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS]; |
3447 | 7.82k | { |
3448 | 7.82k | ps_mem_rec->u4_mem_size = MAX_PPS_CNT * sizeof(pps_t); |
3449 | 7.82k | } |
3450 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PPS, ps_mem_rec->u4_mem_size); |
3451 | | |
3452 | | /************************************************************************ |
3453 | | * Request memory for Slice Header * |
3454 | | ***********************************************************************/ |
3455 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR]; |
3456 | 7.82k | { |
3457 | 7.82k | ps_mem_rec->u4_mem_size = MAX_CTXT_SETS * MAX_SLICE_HDR_CNT |
3458 | 7.82k | * sizeof(slice_header_t); |
3459 | 7.82k | } |
3460 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_HDR, ps_mem_rec->u4_mem_size); |
3461 | | |
3462 | | /************************************************************************ |
3463 | | * Request memory for Adaptive Intra Refresh * |
3464 | | ***********************************************************************/ |
3465 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP]; |
3466 | 7.82k | { |
3467 | | /* total size of the mem record */ |
3468 | 7.82k | WORD32 total_size = 0; |
3469 | | |
3470 | | /* intra coded map */ |
3471 | 7.82k | total_size += max_mb_cnt; |
3472 | 7.82k | total_size *= MAX_CTXT_SETS; |
3473 | | |
3474 | | /* mb refresh map */ |
3475 | 7.82k | total_size += sizeof(UWORD16) * max_mb_cnt; |
3476 | | |
3477 | | /* alignment */ |
3478 | 7.82k | total_size = ALIGN128(total_size); |
3479 | | |
3480 | 7.82k | ps_mem_rec->u4_mem_size = total_size; |
3481 | 7.82k | } |
3482 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_AIR_MAP, ps_mem_rec->u4_mem_size); |
3483 | | |
3484 | | /************************************************************************ |
3485 | | * In multi slice encoding, this memory record helps tracking the start* |
3486 | | * of slice with reference to mb. * |
3487 | | * MEM RECORD for holding * |
3488 | | * 1. mb slice map * |
3489 | | ************************************************************************/ |
3490 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP]; |
3491 | 7.82k | { |
3492 | | /* total size of the mem record */ |
3493 | 7.82k | WORD32 total_size = 0; |
3494 | | |
3495 | | /* size in bytes to slice index of all mbs of a frame */ |
3496 | 7.82k | total_size = ALIGN64(max_mb_cnt); |
3497 | | |
3498 | | /* ih264e_update_proc_ctxt can overread by 1 at the end */ |
3499 | 7.82k | total_size += 1; |
3500 | | |
3501 | | /* total size per each proc ctxt */ |
3502 | 7.82k | total_size *= MAX_CTXT_SETS; |
3503 | 7.82k | ps_mem_rec->u4_mem_size = total_size; |
3504 | 7.82k | } |
3505 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_SLICE_MAP, ps_mem_rec->u4_mem_size); |
3506 | | |
3507 | | /************************************************************************ |
3508 | | * Request memory to hold thread handles and synchronization variables * |
3509 | | ************************************************************************/ |
3510 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE]; |
3511 | 7.82k | { |
3512 | 7.82k | WORD32 thread_pool_size = 0; |
3513 | 7.82k | WORD32 handle_size = ithread_get_handle_size(); |
3514 | | |
3515 | 7.82k | if (ps_ip->s_ive_ip.u4_keep_threads_active) |
3516 | 7.82k | { |
3517 | 7.82k | thread_pool_size += ithread_get_mutex_lock_size(); |
3518 | 7.82k | thread_pool_size += ithread_get_cond_size(); |
3519 | 7.82k | } |
3520 | | |
3521 | 7.82k | ps_mem_rec->u4_mem_size = thread_pool_size + (MAX_PROCESS_THREADS * handle_size); |
3522 | 7.82k | } |
3523 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_THREAD_HANDLE, ps_mem_rec->u4_mem_size); |
3524 | | |
3525 | | /************************************************************************ |
3526 | | * Request memory to hold mutex for control calls * |
3527 | | ************************************************************************/ |
3528 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX]; |
3529 | 7.82k | { |
3530 | 7.82k | ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size(); |
3531 | 7.82k | } |
3532 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CTL_MUTEX, ps_mem_rec->u4_mem_size); |
3533 | | |
3534 | | /************************************************************************ |
3535 | | * Request memory to hold mutex for entropy calls * |
3536 | | ************************************************************************/ |
3537 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX]; |
3538 | 7.82k | { |
3539 | 7.82k | ps_mem_rec->u4_mem_size = ithread_get_mutex_lock_size(); |
3540 | 7.82k | } |
3541 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_MUTEX, ps_mem_rec->u4_mem_size); |
3542 | | |
3543 | | /************************************************************************ |
3544 | | * Request memory to hold process jobs * |
3545 | | ***********************************************************************/ |
3546 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ]; |
3547 | 7.82k | { |
3548 | | /* One process job per row of MBs */ |
3549 | | /* Allocate for two pictures, so that wrap around can be handled easily */ |
3550 | 7.82k | WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS; |
3551 | | |
3552 | 7.82k | WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t)); |
3553 | | |
3554 | 7.82k | ps_mem_rec->u4_mem_size = job_queue_size; |
3555 | 7.82k | } |
3556 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_JOBQ, ps_mem_rec->u4_mem_size); |
3557 | | |
3558 | | /************************************************************************ |
3559 | | * Request memory to hold entropy jobs * |
3560 | | ***********************************************************************/ |
3561 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ]; |
3562 | 7.82k | { |
3563 | | /* One process job per row of MBs */ |
3564 | | /* Allocate for two pictures, so that wrap around can be handled easily */ |
3565 | 7.82k | WORD32 num_jobs = max_mb_rows * MAX_CTXT_SETS; |
3566 | | |
3567 | 7.82k | WORD32 job_queue_size = ih264_list_size(num_jobs, sizeof(job_t)); |
3568 | | |
3569 | 7.82k | ps_mem_rec->u4_mem_size = job_queue_size; |
3570 | 7.82k | } |
3571 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ENTROPY_JOBQ, ps_mem_rec->u4_mem_size); |
3572 | | |
3573 | | /************************************************************************ |
3574 | | * In multi core encoding, each row is assumed to be launched on a * |
3575 | | * thread. The rows below can only start after its neighbors are coded * |
3576 | | * The status of an mb coded/uncoded is signaled via proc map. * |
3577 | | * MEM RECORD for holding * |
3578 | | * 1. mb proc map (mb status core coded/uncoded) * |
3579 | | ************************************************************************/ |
3580 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP]; |
3581 | 7.82k | { |
3582 | | /* total size of the mem record */ |
3583 | 7.82k | WORD32 total_size = 0; |
3584 | | |
3585 | | /* size in bytes to mb core coding status of an entire frame */ |
3586 | 7.82k | total_size = max_mb_cnt; |
3587 | | |
3588 | | /* add an additional 1 row of bytes to evade the special case of row 0 */ |
3589 | 7.82k | total_size += max_mb_cols; |
3590 | | |
3591 | | /* total size per each proc ctxt */ |
3592 | 7.82k | total_size *= MAX_CTXT_SETS; |
3593 | 7.82k | ps_mem_rec->u4_mem_size = total_size; |
3594 | 7.82k | } |
3595 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_MAP, ps_mem_rec->u4_mem_size); |
3596 | | |
3597 | | /************************************************************************ |
3598 | | * mem record for holding a particular MB is deblocked or not * |
3599 | | * 1. mb deblk map (mb status deblocked/not deblocked) * |
3600 | | ************************************************************************/ |
3601 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP]; |
3602 | 7.82k | { |
3603 | | /* total size of the mem record */ |
3604 | 7.82k | WORD32 total_size = 0; |
3605 | | |
3606 | | /* size in bytes to mb core coding status of an entire frame */ |
3607 | 7.82k | total_size = max_mb_cnt; |
3608 | | |
3609 | | /* add an additional 1 row of bytes to evade the special case of row 0 */ |
3610 | 7.82k | total_size += max_mb_cols; |
3611 | | |
3612 | 7.82k | total_size = ALIGN64(total_size); |
3613 | | |
3614 | | /* total size per each proc ctxt */ |
3615 | 7.82k | total_size *= MAX_CTXT_SETS; |
3616 | 7.82k | ps_mem_rec->u4_mem_size = total_size; |
3617 | 7.82k | } |
3618 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DBLK_MAP, ps_mem_rec->u4_mem_size); |
3619 | | |
3620 | | /************************************************************************ |
3621 | | * mem record for holding a particular MB's me is done or not * |
3622 | | * 1. mb me map * |
3623 | | ************************************************************************/ |
3624 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP]; |
3625 | 7.82k | { |
3626 | | /* total size of the mem record */ |
3627 | 7.82k | WORD32 total_size = 0; |
3628 | | |
3629 | | /* size in bytes to mb core coding status of an entire frame */ |
3630 | 7.82k | total_size = max_mb_cnt; |
3631 | | |
3632 | | /* add an additional 1 row of bytes to evade the special case of row 0 */ |
3633 | 7.82k | total_size += max_mb_cols; |
3634 | | |
3635 | | /* total size per each proc ctxt */ |
3636 | 7.82k | total_size *= MAX_CTXT_SETS; |
3637 | | |
3638 | 7.82k | ps_mem_rec->u4_mem_size = total_size; |
3639 | 7.82k | } |
3640 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_ME_MAP, ps_mem_rec->u4_mem_size); |
3641 | | |
3642 | | /************************************************************************ |
3643 | | * size for holding dpb manager context * |
3644 | | ************************************************************************/ |
3645 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR]; |
3646 | 7.82k | { |
3647 | 7.82k | ps_mem_rec->u4_mem_size = sizeof(dpb_mgr_t); |
3648 | 7.82k | } |
3649 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_DPB_MGR, ps_mem_rec->u4_mem_size); |
3650 | | |
3651 | | /************************************************************************ |
3652 | | * luma or chroma core coding involves mb estimation, error computation* |
3653 | | * between the estimated singnal and the actual signal, transform the * |
3654 | | * error, quantize the error, then inverse transform and inverse quant * |
3655 | | * ize the residue and add the result back to estimated signal. * |
3656 | | * To perform all these, a set of temporary buffers are needed. * |
3657 | | * MEM RECORD for holding scratch buffers * |
3658 | | * 1. prediction buffer used during mb mode analysis * |
3659 | | * 2 temp. reference buffer when intra 4x4 with rdopt on is * |
3660 | | * enabled * |
3661 | | * - when intra 4x4 is enabled, rdopt is on, to store the * |
3662 | | * reconstructed values and use them later this temp. buffer * |
3663 | | * is used. * |
3664 | | * 3. prediction buffer used during intra mode analysis * |
3665 | | * 4. prediction buffer used during intra 16x16 plane mode * |
3666 | | * analysis |
3667 | | * 5. prediction buffer used during intra chroma mode analysis * |
3668 | | * 6. prediction buffer used during intra chroma 16x16 plane * |
3669 | | * mode analysis |
3670 | | * 7. forward transform output buffer * |
3671 | | * - to store the error between estimated and the actual inp * |
3672 | | * ut and to store the fwd transformed quantized output * |
3673 | | * 8. forward transform output buffer * |
3674 | | * - when intra 4x4 is enabled, rdopt is on, to store the * |
3675 | | * fwd transform values and use them later this temp. buffer * |
3676 | | * is used. * |
3677 | | * 9. temporary buffer for inverse transform * |
3678 | | * - temporary buffer used in inverse transform and inverse * |
3679 | | * quantization * |
3680 | | * A. Buffers for holding half_x , half_y and half_xy planes * |
3681 | | ************************************************************************/ |
3682 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH]; |
3683 | 7.82k | { |
3684 | 7.82k | WORD32 total_size = 0; |
3685 | 7.82k | WORD32 i4_tmp_size; |
3686 | | |
3687 | | /* size to hold prediction buffer */ |
3688 | 7.82k | total_size += sizeof(UWORD8) * 16 * 16; |
3689 | 7.82k | total_size = ALIGN64(total_size); |
3690 | | |
3691 | | /* size to hold recon for intra 4x4 buffer */ |
3692 | 7.82k | total_size += sizeof(UWORD8) * 16 * 16; |
3693 | 7.82k | total_size = ALIGN64(total_size); |
3694 | | |
3695 | | /* prediction buffer intra 16x16 */ |
3696 | 7.82k | total_size += sizeof(UWORD8) * 16 * 16; |
3697 | 7.82k | total_size = ALIGN64(total_size); |
3698 | | |
3699 | | /* prediction buffer intra 16x16 plane*/ |
3700 | 7.82k | total_size += sizeof(UWORD8) * 16 * 16; |
3701 | 7.82k | total_size = ALIGN64(total_size); |
3702 | | |
3703 | | /* prediction buffer intra chroma*/ |
3704 | 7.82k | total_size += sizeof(UWORD8) * 16 * 8; |
3705 | 7.82k | total_size = ALIGN64(total_size); |
3706 | | |
3707 | | /* prediction buffer intra chroma plane*/ |
3708 | 7.82k | total_size += sizeof(UWORD8) * 16 * 8; |
3709 | 7.82k | total_size = ALIGN64(total_size); |
3710 | | |
3711 | | /* size to hold fwd transform output */ |
3712 | 7.82k | total_size += sizeof(WORD16) * SIZE_TRANS_BUFF; |
3713 | 7.82k | total_size = ALIGN64(total_size); |
3714 | | |
3715 | | /* size to hold fwd transform output */ |
3716 | 7.82k | total_size += sizeof(WORD16) * SIZE_TRANS_BUFF; |
3717 | 7.82k | total_size = ALIGN64(total_size); |
3718 | | |
3719 | | /* size to hold temporary data during inverse transform */ |
3720 | 7.82k | total_size += sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS; |
3721 | 7.82k | total_size = ALIGN64(total_size); |
3722 | | |
3723 | | /* Buffers for holding half_x , half_y and half_xy planes */ |
3724 | 7.82k | i4_tmp_size = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT); |
3725 | 7.82k | total_size += (ALIGN64(i4_tmp_size) * SUBPEL_BUFF_CNT); |
3726 | | |
3727 | | /* Allocate for each process thread */ |
3728 | 7.82k | total_size *= MAX_PROCESS_CTXT; |
3729 | | |
3730 | 7.82k | ps_mem_rec->u4_mem_size = total_size; |
3731 | 7.82k | } |
3732 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_PROC_SCRATCH, ps_mem_rec->u4_mem_size); |
3733 | | |
3734 | | /************************************************************************ |
3735 | | * When transform_8x8_flag is disabled, the size of a sub block is * |
3736 | | * 4x4 and when the transform_8x8_flag is enabled the size of the sub * |
3737 | | * block is 8x8. The threshold matrix and the forward scaling list * |
3738 | | * is of the size of the sub block. * |
3739 | | * MEM RECORD for holding * |
3740 | | * 1. quantization parameters for plane y, cb, cr * |
3741 | | * - threshold matrix for quantization * |
3742 | | * - forward weight matrix * |
3743 | | * - satqd threshold matrix * |
3744 | | ************************************************************************/ |
3745 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM]; |
3746 | 7.82k | { |
3747 | | /* total size of the mem record */ |
3748 | 7.82k | WORD32 total_size = 0; |
3749 | | |
3750 | | /* quantization parameter list for planes y,cb and cr */ |
3751 | 7.82k | total_size += ALIGN64(sizeof(quant_params_t)) * 3; |
3752 | | |
3753 | | /* size of threshold matrix for quantization |
3754 | | * (assuming the transform_8x8_flag is disabled). |
3755 | | * for all 3 planes */ |
3756 | 7.82k | total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3; |
3757 | | |
3758 | | /* size of forward weight matrix for quantization |
3759 | | * (assuming the transform_8x8_flag is disabled). |
3760 | | * for all 3 planes */ |
3761 | 7.82k | total_size += ALIGN64(sizeof(WORD16) * 4 * 4) * 3; |
3762 | | |
3763 | | /* Size for SATDQ threshold matrix for palnes y, cb and cr */ |
3764 | 7.82k | total_size += ALIGN64(sizeof(UWORD16) * 9) * 3; |
3765 | | |
3766 | | /* total size per each proc thread */ |
3767 | 7.82k | total_size *= MAX_PROCESS_CTXT; |
3768 | | |
3769 | 7.82k | ps_mem_rec->u4_mem_size = total_size; |
3770 | 7.82k | } |
3771 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_QUANT_PARAM, ps_mem_rec->u4_mem_size); |
3772 | | |
3773 | | /************************************************************************ |
3774 | | * While computing blocking strength for the current mb, the csbp, mb * |
3775 | | * type for the neighboring mbs are necessary. memtab for storing top * |
3776 | | * row mbtype and csbp is evaluated here. * |
3777 | | * * |
3778 | | * when encoding intra 4x4 or intra 8x8 the submb types are estimated * |
3779 | | * and sent. The estimation is dependent on neighbor mbs. For this * |
3780 | | * store the top row sub mb types for intra mbs * |
3781 | | * * |
3782 | | * During motion vector prediction, the curr mb mv is predicted from * |
3783 | | * neigbors left, top, top right and sometimes top left depending on * |
3784 | | * the availability. The top and top right content is accessed from * |
3785 | | * the memtab specified below. * |
3786 | | ************************************************************************/ |
3787 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO]; |
3788 | 7.82k | { |
3789 | | /* total size of the mem record */ |
3790 | 7.82k | WORD32 total_size = 0; |
3791 | | |
3792 | | /* size in bytes to store 1 row of mb_info_t */ |
3793 | | /* one additional mb, to avoid checking end of row condition */ |
3794 | 7.82k | total_size += (max_mb_cols + 1) * sizeof(mb_info_t); |
3795 | | |
3796 | | /* size in bytes to store 1 row of intra macroblock sub modes */ |
3797 | 7.82k | total_size += max_mb_cols * sizeof(UWORD8) * 16; |
3798 | | |
3799 | | /* size in bytes to store 1 row + 1 of enc_pu_t */ |
3800 | | /* one additional mb, to avoid checking end of row condition */ |
3801 | 7.82k | total_size += (max_mb_cols + 1) * sizeof(enc_pu_t); |
3802 | | |
3803 | | /* total size per proc ctxt */ |
3804 | 7.82k | total_size = ALIGN128(total_size); |
3805 | | |
3806 | | /* total size per each proc ctxt */ |
3807 | 7.82k | total_size *= MAX_CTXT_SETS; |
3808 | 7.82k | ps_mem_rec->u4_mem_size = total_size; |
3809 | 7.82k | } |
3810 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_TOP_ROW_SYN_INFO, ps_mem_rec->u4_mem_size); |
3811 | | |
3812 | | /************************************************************************ |
3813 | | * When transform_8x8_flag is disabled, the mb is partitioned into * |
3814 | | * 4 sub blocks. This corresponds to 1 vertical left edge and 1 * |
3815 | | * vertical inner edge, 1 horizontal top edge and 1 horizontal * |
3816 | | * inner edge per mb. Further, When transform_8x8_flag is enabled, * |
3817 | | * the mb is partitioned in to 16 sub blocks. This corresponds to * |
3818 | | * 1 vertical left edge and 3 vertical inner edges, 1 horizontal top * |
3819 | | * edge and 3 horizontal inner edges per mb. * |
3820 | | * MEM RECORD for holding * |
3821 | | * 1. vertical edge blocking strength * |
3822 | | * 2. horizontal edge blocking strength * |
3823 | | * 3. mb qp * |
3824 | | * all are frame level * |
3825 | | ************************************************************************/ |
3826 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP]; |
3827 | 7.82k | { |
3828 | | /* total size of the mem record */ |
3829 | 7.82k | WORD32 total_size = 0; |
3830 | | |
3831 | | /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/ |
3832 | 7.82k | WORD32 vert_bs_size, horz_bs_size, qp_size; |
3833 | | |
3834 | | /* vertical edge bs = total number of vertical edges * number of bytes per each edge */ |
3835 | | /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0), |
3836 | | * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */ |
3837 | 7.82k | vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4); |
3838 | | |
3839 | | /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */ |
3840 | | /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0), |
3841 | | * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */ |
3842 | 7.82k | horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4); |
3843 | | |
3844 | | /* qp of each mb requires 1 byte */ |
3845 | 7.82k | qp_size = ALIGN64(max_mb_cnt); |
3846 | | |
3847 | | /* total size */ |
3848 | 7.82k | total_size = vert_bs_size + horz_bs_size + qp_size; |
3849 | | |
3850 | | /* total size per each proc ctxt */ |
3851 | 7.82k | total_size *= MAX_CTXT_SETS; |
3852 | | |
3853 | 7.82k | ps_mem_rec->u4_mem_size = total_size; |
3854 | 7.82k | } |
3855 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BS_QP, ps_mem_rec->u4_mem_size); |
3856 | | |
3857 | | /************************************************************************ |
3858 | | * size for holding dpb manager context * |
3859 | | ************************************************************************/ |
3860 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC]; |
3861 | 7.82k | { |
3862 | 7.82k | ps_mem_rec->u4_mem_size = ih264_buf_mgr_size(); |
3863 | 7.82k | } |
3864 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_INP_PIC, ps_mem_rec->u4_mem_size); |
3865 | | |
3866 | | /************************************************************************ |
3867 | | * size for holding dpb manager context * |
3868 | | ************************************************************************/ |
3869 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT]; |
3870 | 7.82k | { |
3871 | 7.82k | ps_mem_rec->u4_mem_size = ih264_buf_mgr_size(); |
3872 | 7.82k | } |
3873 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_OUT, ps_mem_rec->u4_mem_size); |
3874 | | |
3875 | | /************************************************************************ |
3876 | | * Size for color space conversion * |
3877 | | ************************************************************************/ |
3878 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC]; |
3879 | 7.82k | { |
3880 | | /* We need a total a memory for a single frame of 420 sp, ie |
3881 | | * (wd * ht) for luma and (wd * ht / 2) for chroma*/ |
3882 | 7.82k | ps_mem_rec->u4_mem_size = MAX_CTXT_SETS |
3883 | 7.82k | * ((3 * max_ht_luma * max_wd_luma) >> 1); |
3884 | | /* Allocate an extra row, since inverse transform functions for |
3885 | | * chroma access(only read, not used) few extra bytes due to |
3886 | | * interleaved input |
3887 | | */ |
3888 | 7.82k | ps_mem_rec->u4_mem_size += max_wd_luma; |
3889 | 7.82k | } |
3890 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_CSC, ps_mem_rec->u4_mem_size); |
3891 | | |
3892 | | /************************************************************************ |
3893 | | * Size for holding pic_buf_t for each reference picture * |
3894 | | * Note this allocation is done for BUF_MGR_MAX_CNT instead of * |
3895 | | * MAX_DPB_SIZE or max_dpb_size for following reasons * |
3896 | | * max_dpb_size will be based on max_wd and max_ht * |
3897 | | * For higher max_wd and max_ht this number will be smaller than * |
3898 | | * MAX_DPB_SIZE But during actual initialization number of buffers * |
3899 | | * allocated can be more. * |
3900 | | * * |
3901 | | * Also to handle display depth application can allocate more than * |
3902 | | * what codec asks for in case of non-shared mode * |
3903 | | * Since this is only a structure allocation and not actual buffer * |
3904 | | * allocation, it is allocated for BUF_MGR_MAX_CNT entries * |
3905 | | ************************************************************************/ |
3906 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC]; |
3907 | 7.82k | { |
3908 | 7.82k | ps_mem_rec->u4_mem_size = ih264_buf_mgr_size(); |
3909 | 7.82k | ps_mem_rec->u4_mem_size += BUF_MGR_MAX_CNT * sizeof(pic_buf_t); |
3910 | | |
3911 | | /************************************************************************ |
3912 | | * Note: Number of luma samples is not max_wd * max_ht here, instead it * |
3913 | | * is set to maximum number of luma samples allowed at the given level. * |
3914 | | * This is done to ensure that any stream with width and height lesser * |
3915 | | * than max_wd and max_ht is supported. Number of buffers required can * |
3916 | | * be greater for lower width and heights at a given level and this * |
3917 | | * increased number of buffers might require more memory than what * |
3918 | | * max_wd and max_ht buffer would have required. Number of buffers is * |
3919 | | * doubled in order to return one frame at a time instead of sending * |
3920 | | * multiple outputs during dpb full case. Also note one extra buffer is * |
3921 | | * allocted to store current picture. * |
3922 | | * * |
3923 | | * Half-pel planes for each reference buffer are allocated along with * |
3924 | | * the reference buffer. So each reference buffer is 4 times the * |
3925 | | * required size. This way buffer management for the half-pel planes is * |
3926 | | * easier and while using the half-pel planes in MC, an offset can be * |
3927 | | * used from a single pointer * |
3928 | | ***********************************************************************/ |
3929 | 7.82k | ps_mem_rec->u4_mem_size += HPEL_PLANES_CNT |
3930 | 7.82k | * ih264e_get_total_pic_buf_size( |
3931 | 7.82k | max_wd_luma * max_ht_luma, level, |
3932 | 7.82k | PAD_WD, PAD_HT, num_ref_frames, |
3933 | 7.82k | num_reorder_frames); |
3934 | 7.82k | } |
3935 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_REF_PIC, ps_mem_rec->u4_mem_size); |
3936 | | |
3937 | | /************************************************************************ |
3938 | | * Request memory to hold mem recs to be returned during retrieve call * |
3939 | | ************************************************************************/ |
3940 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP]; |
3941 | 7.82k | { |
3942 | 7.82k | ps_mem_rec->u4_mem_size = MEM_REC_CNT * sizeof(iv_mem_rec_t); |
3943 | 7.82k | } |
3944 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_BACKUP, ps_mem_rec->u4_mem_size); |
3945 | | |
3946 | | /************************************************************************ |
3947 | | * size for memory required by NMB info structs and buffer for storing * |
3948 | | * half pel plane * |
3949 | | ************************************************************************/ |
3950 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB]; |
3951 | 7.82k | { |
3952 | 7.82k | ps_mem_rec->u4_mem_size = MAX_PROCESS_CTXT * max_mb_cols * |
3953 | 7.82k | (sizeof(mb_info_nmb_t) + MB_SIZE * MB_SIZE |
3954 | 7.82k | * sizeof(UWORD8)); |
3955 | 7.82k | } |
3956 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_MB_INFO_NMB, ps_mem_rec->u4_mem_size); |
3957 | | |
3958 | | /************************************************************************ |
3959 | | * RC mem records * |
3960 | | ************************************************************************/ |
3961 | 7.82k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC]; |
3962 | 7.82k | { |
3963 | 7.82k | ih264e_get_rate_control_mem_tab(NULL, ps_mem_rec, FILL_MEMTAB); |
3964 | 7.82k | } |
3965 | 7.82k | DEBUG("\nMemory record Id %d = %d \n", MEM_REC_RC, ps_mem_rec->u4_mem_size); |
3966 | | |
3967 | | /* Each memtab size is aligned to next multiple of 128 bytes */ |
3968 | | /* This is to ensure all the memtabs start at different cache lines */ |
3969 | 7.82k | ps_mem_rec = ps_mem_rec_base; |
3970 | 406k | for (i = 0; i < MEM_REC_CNT; i++) |
3971 | 399k | { |
3972 | 399k | ps_mem_rec->u4_mem_size = ALIGN128(ps_mem_rec->u4_mem_size); |
3973 | 399k | ps_mem_rec++; |
3974 | 399k | } |
3975 | | |
3976 | 7.82k | ps_op->s_ive_op.u4_num_mem_rec = MEM_REC_CNT; |
3977 | | |
3978 | 7.82k | DEBUG("Num mem recs in fill call : %d\n", ps_op->s_ive_op.u4_num_mem_rec); |
3979 | | |
3980 | 7.82k | return (status); |
3981 | 7.82k | } |
3982 | | |
3983 | | /** |
3984 | | ******************************************************************************* |
3985 | | * |
3986 | | * @brief |
3987 | | * Initializes from mem records passed to the codec |
3988 | | * |
3989 | | * @par Description: |
3990 | | * Initializes pointers based on mem records passed |
3991 | | * |
3992 | | * @param[in] ps_codec_obj |
3993 | | * Pointer to codec object at API level |
3994 | | * |
3995 | | * @param[in] pv_api_ip |
3996 | | * Pointer to input argument structure |
3997 | | * |
3998 | | * @param[out] pv_api_op |
3999 | | * Pointer to output argument structure |
4000 | | * |
4001 | | * @returns error status |
4002 | | * |
4003 | | * @remarks none |
4004 | | * |
4005 | | ******************************************************************************* |
4006 | | */ |
4007 | | static WORD32 ih264e_init_mem_rec(iv_obj_t *ps_codec_obj, |
4008 | | void *pv_api_ip, |
4009 | | void *pv_api_op) |
4010 | 3.90k | { |
4011 | | /* api call I/O structures */ |
4012 | 3.90k | ih264e_init_ip_t *ps_ip = pv_api_ip; |
4013 | 3.90k | ih264e_init_op_t *ps_op = pv_api_op; |
4014 | | |
4015 | | /* mem records */ |
4016 | 3.90k | iv_mem_rec_t *ps_mem_rec_base, *ps_mem_rec; |
4017 | | |
4018 | | /* codec variables */ |
4019 | 3.90k | codec_t * ps_codec; |
4020 | 3.90k | cabac_ctxt_t *ps_cabac; |
4021 | 3.90k | mb_info_ctxt_t *ps_mb_map_ctxt_inc; |
4022 | | |
4023 | 3.90k | cfg_params_t *ps_cfg; |
4024 | | |
4025 | | /* frame dimensions */ |
4026 | 3.90k | WORD32 max_wd_luma, max_ht_luma; |
4027 | 3.90k | WORD32 max_mb_rows, max_mb_cols, max_mb_cnt; |
4028 | | |
4029 | | /* temp var */ |
4030 | 3.90k | WORD32 i, j; |
4031 | 3.90k | WORD32 status = IV_SUCCESS; |
4032 | | |
4033 | | /* frame dimensions */ |
4034 | 3.90k | max_ht_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_ht); |
4035 | 3.90k | max_wd_luma = ALIGN16(ps_ip->s_ive_ip.u4_max_wd); |
4036 | 3.90k | max_mb_rows = max_ht_luma / MB_SIZE; |
4037 | 3.90k | max_mb_cols = max_wd_luma / MB_SIZE; |
4038 | 3.90k | max_mb_cnt = max_mb_rows * max_mb_cols; |
4039 | | |
4040 | | /* mem records */ |
4041 | 3.90k | ps_mem_rec_base = ps_ip->s_ive_ip.ps_mem_rec; |
4042 | | /* memset all allocated memory, except the first one. First buffer (i.e. i == MEM_REC_IV_OBJ) |
4043 | | is initialized by application before calling this init function */ |
4044 | 199k | for (i = MEM_REC_CODEC; i < MEM_REC_CNT; i++) |
4045 | 195k | { |
4046 | 195k | ps_mem_rec = &ps_mem_rec_base[i]; |
4047 | 195k | memset(ps_mem_rec->pv_base, 0, ps_mem_rec->u4_mem_size); |
4048 | 195k | } |
4049 | | |
4050 | | /* Init mem records */ |
4051 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_CODEC]; |
4052 | 3.90k | { |
4053 | 3.90k | ps_codec_obj->pv_codec_handle = ps_mem_rec->pv_base; |
4054 | 3.90k | ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle); |
4055 | 3.90k | } |
4056 | | /* Init mem records_cabac ctxt */ |
4057 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC]; |
4058 | 3.90k | { |
4059 | 3.90k | ps_cabac = (cabac_ctxt_t *)(ps_mem_rec->pv_base); |
4060 | 3.90k | } |
4061 | | |
4062 | | /* Init mem records mb info array for CABAC */ |
4063 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_CABAC_MB_INFO]; |
4064 | 3.90k | { |
4065 | 3.90k | ps_mb_map_ctxt_inc = (mb_info_ctxt_t *)(ps_mem_rec->pv_base); |
4066 | 3.90k | } |
4067 | | |
4068 | | /* Note this memset can not be done in init() call, since init will called |
4069 | | during reset as well. And calling this during reset will mean all pointers |
4070 | | need to reinitialized */ |
4071 | 3.90k | memset(ps_codec, 0, sizeof(codec_t)); |
4072 | 3.90k | memset(ps_cabac, 0, sizeof(cabac_ctxt_t)); |
4073 | | |
4074 | | /* Set default Config Params */ |
4075 | 3.90k | ps_cfg = &ps_codec->s_cfg; |
4076 | 3.90k | ih264e_set_default_params(ps_cfg); |
4077 | | |
4078 | | /* Update config params as per input */ |
4079 | 3.90k | ps_cfg->u4_max_wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd); |
4080 | 3.90k | ps_cfg->u4_max_ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht); |
4081 | | |
4082 | | /* Initialize dimensions to max dimensions during init */ |
4083 | 3.90k | ps_cfg->u4_wd = ps_cfg->u4_disp_wd = ps_cfg->u4_max_wd; |
4084 | 3.90k | ps_cfg->u4_ht = ps_cfg->u4_disp_ht = ps_cfg->u4_max_ht; |
4085 | | |
4086 | 3.90k | ps_cfg->i4_wd_mbs = ps_cfg->u4_max_wd >> 4; |
4087 | 3.90k | ps_cfg->i4_ht_mbs = ps_cfg->u4_max_ht >> 4; |
4088 | 3.90k | ps_cfg->u4_max_ref_cnt = ps_ip->s_ive_ip.u4_max_ref_cnt; |
4089 | 3.90k | ps_cfg->u4_max_reorder_cnt = ps_ip->s_ive_ip.u4_max_reorder_cnt; |
4090 | 3.90k | ps_cfg->u4_max_level = ps_ip->s_ive_ip.u4_max_level; |
4091 | 3.90k | ps_cfg->e_inp_color_fmt = ps_ip->s_ive_ip.e_inp_color_fmt; |
4092 | 3.90k | ps_cfg->e_recon_color_fmt = ps_ip->s_ive_ip.e_recon_color_fmt; |
4093 | 3.90k | ps_cfg->u4_max_framerate = ps_ip->s_ive_ip.u4_max_framerate; |
4094 | 3.90k | ps_cfg->u4_max_bitrate = ps_ip->s_ive_ip.u4_max_bitrate; |
4095 | 3.90k | ps_cfg->u4_num_bframes = ps_ip->s_ive_ip.u4_num_bframes; |
4096 | 3.90k | ps_cfg->e_content_type = ps_ip->s_ive_ip.e_content_type; |
4097 | 3.90k | ps_cfg->u4_max_srch_rng_x = ps_ip->s_ive_ip.u4_max_srch_rng_x; |
4098 | 3.90k | ps_cfg->u4_max_srch_rng_y = ps_ip->s_ive_ip.u4_max_srch_rng_y; |
4099 | 3.90k | ps_cfg->e_slice_mode = ps_ip->s_ive_ip.e_slice_mode; |
4100 | 3.90k | ps_cfg->u4_slice_param = ps_ip->s_ive_ip.u4_slice_param; |
4101 | 3.90k | ps_cfg->e_arch = ps_ip->s_ive_ip.e_arch; |
4102 | 3.90k | ps_cfg->e_soc = ps_ip->s_ive_ip.e_soc; |
4103 | 3.90k | ps_cfg->u4_enable_recon = ps_ip->s_ive_ip.u4_enable_recon; |
4104 | 3.90k | ps_cfg->e_rc_mode = ps_ip->s_ive_ip.e_rc_mode; |
4105 | 3.90k | ps_cfg->u4_keep_threads_active = ps_ip->s_ive_ip.u4_keep_threads_active; |
4106 | | |
4107 | | /* Validate params */ |
4108 | 3.90k | if ((ps_ip->s_ive_ip.u4_max_level < MIN_LEVEL) |
4109 | 3.90k | || (ps_ip->s_ive_ip.u4_max_level > MAX_LEVEL)) |
4110 | 0 | { |
4111 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_CODEC_LEVEL_NOT_SUPPORTED; |
4112 | 0 | ps_cfg->u4_max_level = DEFAULT_MAX_LEVEL; |
4113 | 0 | } |
4114 | | |
4115 | 3.90k | if (ps_ip->s_ive_ip.u4_max_ref_cnt > MAX_REF_CNT) |
4116 | 0 | { |
4117 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REF_UNSUPPORTED; |
4118 | 0 | ps_cfg->u4_max_ref_cnt = MAX_REF_CNT; |
4119 | 0 | } |
4120 | | |
4121 | 3.90k | if (ps_ip->s_ive_ip.u4_max_reorder_cnt > MAX_REF_CNT) |
4122 | 0 | { |
4123 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_NUM_REORDER_UNSUPPORTED; |
4124 | 0 | ps_cfg->u4_max_reorder_cnt = MAX_REF_CNT; |
4125 | 0 | } |
4126 | | |
4127 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_BACKUP]; |
4128 | 3.90k | { |
4129 | 3.90k | ps_codec->ps_mem_rec_backup = (iv_mem_rec_t *) ps_mem_rec->pv_base; |
4130 | | |
4131 | 3.90k | memcpy(ps_codec->ps_mem_rec_backup, ps_mem_rec_base, |
4132 | 3.90k | MEM_REC_CNT * sizeof(iv_mem_rec_t)); |
4133 | 3.90k | } |
4134 | | |
4135 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY]; |
4136 | 3.90k | { |
4137 | | /* temp var */ |
4138 | 3.90k | WORD32 size = 0, offset; |
4139 | | |
4140 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4141 | 31.2k | { |
4142 | 31.2k | if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) |
4143 | 31.2k | { |
4144 | | /* base ptr */ |
4145 | 31.2k | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4146 | | |
4147 | | /* reset size */ |
4148 | 31.2k | size = 0; |
4149 | | |
4150 | | /* skip mb run */ |
4151 | 31.2k | ps_codec->as_process[i].s_entropy.pi4_mb_skip_run = |
4152 | 31.2k | (void *) (pu1_buf + size); |
4153 | 31.2k | size += sizeof(WORD32); |
4154 | 31.2k | size = ALIGN8(size); |
4155 | | |
4156 | | /* entropy map */ |
4157 | 31.2k | ps_codec->as_process[i].s_entropy.pu1_entropy_map = |
4158 | 31.2k | (void *) (pu1_buf + size + max_mb_cols); |
4159 | | /* size in bytes to store entropy status of an entire frame */ |
4160 | 31.2k | size += (max_mb_cols * max_mb_rows); |
4161 | | /* add an additional 1 row of bytes to evade the special case of row 0 */ |
4162 | 31.2k | size += max_mb_cols; |
4163 | 31.2k | size = ALIGN128(size); |
4164 | | |
4165 | | /* bit stream ptr */ |
4166 | 31.2k | ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf |
4167 | 31.2k | + size); |
4168 | 31.2k | size += sizeof(bitstrm_t); |
4169 | 31.2k | size = ALIGN128(size); |
4170 | | |
4171 | | /* nnz luma */ |
4172 | 31.2k | ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma = |
4173 | 31.2k | (void *) (pu1_buf + size); |
4174 | 31.2k | size += (max_mb_cols * 4 * sizeof(UWORD8)); |
4175 | 31.2k | size = ALIGN128(size); |
4176 | | |
4177 | | /* nnz chroma */ |
4178 | 31.2k | ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr = |
4179 | 31.2k | (void *) (pu1_buf + size); |
4180 | 31.2k | size += (max_mb_cols * 4 * sizeof(UWORD8)); |
4181 | 31.2k | size = ALIGN128(size); |
4182 | 31.2k | offset = size; |
4183 | | /* cabac Context */ |
4184 | 31.2k | ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac; |
4185 | 31.2k | } |
4186 | 0 | else |
4187 | 0 | { |
4188 | | /* base ptr */ |
4189 | 0 | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4190 | | |
4191 | | /* reset size */ |
4192 | 0 | size = offset; |
4193 | | |
4194 | | /* skip mb run */ |
4195 | 0 | ps_codec->as_process[i].s_entropy.pi4_mb_skip_run = |
4196 | 0 | (void *) (pu1_buf + size); |
4197 | 0 | size += sizeof(WORD32); |
4198 | 0 | size = ALIGN8(size); |
4199 | | |
4200 | | /* entropy map */ |
4201 | 0 | ps_codec->as_process[i].s_entropy.pu1_entropy_map = |
4202 | 0 | (void *) (pu1_buf + size + max_mb_cols); |
4203 | | /* size in bytes to store entropy status of an entire frame */ |
4204 | 0 | size += (max_mb_cols * max_mb_rows); |
4205 | | /* add an additional 1 row of bytes to evade the special case of row 0 */ |
4206 | 0 | size += max_mb_cols; |
4207 | 0 | size = ALIGN128(size); |
4208 | | |
4209 | | /* bit stream ptr */ |
4210 | 0 | ps_codec->as_process[i].s_entropy.ps_bitstrm = (void *) (pu1_buf |
4211 | 0 | + size); |
4212 | 0 | size += sizeof(bitstrm_t); |
4213 | 0 | size = ALIGN128(size); |
4214 | | |
4215 | | /* nnz luma */ |
4216 | 0 | ps_codec->as_process[i].s_entropy.pu1_top_nnz_luma = |
4217 | 0 | (void *) (pu1_buf + size); |
4218 | 0 | size += (max_mb_cols * 4 * sizeof(UWORD8)); |
4219 | 0 | size = ALIGN128(size); |
4220 | | |
4221 | | /* nnz chroma */ |
4222 | 0 | ps_codec->as_process[i].s_entropy.pu1_top_nnz_cbcr = |
4223 | 0 | (void *) (pu1_buf + size); |
4224 | 0 | size += (max_mb_cols * 4 * sizeof(UWORD8)); |
4225 | 0 | size = ALIGN128(size); |
4226 | | /* cabac Context */ |
4227 | 0 | ps_codec->as_process[i].s_entropy.ps_cabac = ps_cabac; |
4228 | 0 | } |
4229 | 31.2k | } |
4230 | 3.90k | ps_codec->as_process[0].s_entropy.ps_cabac->ps_mb_map_ctxt_inc_base = |
4231 | 3.90k | ps_mb_map_ctxt_inc; |
4232 | 3.90k | } |
4233 | | |
4234 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_COEFF_DATA]; |
4235 | 3.90k | { |
4236 | | /* temp var */ |
4237 | 3.90k | WORD32 size = 0, size_of_row; |
4238 | 3.90k | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4239 | | |
4240 | | /* size of coeff data of 1 mb */ |
4241 | 3.90k | size += sizeof(tu_sblk_coeff_data_t) * MAX_4x4_SUBBLKS; |
4242 | | |
4243 | | /* size of coeff data of 1 row of mb's */ |
4244 | 3.90k | size *= max_mb_cols; |
4245 | | |
4246 | | /* align to avoid false sharing */ |
4247 | 3.90k | size = ALIGN64(size); |
4248 | 3.90k | size_of_row = size; |
4249 | | |
4250 | | /* size for one full frame */ |
4251 | 3.90k | size *= max_mb_rows; |
4252 | | |
4253 | 3.90k | ps_codec->u4_size_coeff_data = size_of_row; |
4254 | | |
4255 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4256 | 31.2k | { |
4257 | 31.2k | if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) |
4258 | 31.2k | { |
4259 | 31.2k | ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf; |
4260 | 31.2k | ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = |
4261 | 31.2k | pu1_buf; |
4262 | 31.2k | } |
4263 | 0 | else |
4264 | 0 | { |
4265 | 0 | ps_codec->as_process[i].pv_pic_mb_coeff_data = pu1_buf + size; |
4266 | 0 | ps_codec->as_process[i].s_entropy.pv_pic_mb_coeff_data = pu1_buf |
4267 | 0 | + size; |
4268 | 0 | } |
4269 | 31.2k | } |
4270 | 3.90k | } |
4271 | | |
4272 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_HEADER_DATA]; |
4273 | 3.90k | { |
4274 | | /* temp var */ |
4275 | 3.90k | WORD32 size, size_of_row; |
4276 | 3.90k | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4277 | | |
4278 | | /* size of header data of 1 mb */ |
4279 | 3.90k | size = sizeof(mb_hdr_t); |
4280 | | |
4281 | | /* size for 1 row of mbs */ |
4282 | 3.90k | size = size * max_mb_cols; |
4283 | | |
4284 | | /* align to avoid any false sharing across threads */ |
4285 | 3.90k | size = ALIGN64(size); |
4286 | 3.90k | size_of_row = size; |
4287 | | |
4288 | | /* size for one full frame */ |
4289 | 3.90k | size *= max_mb_rows; |
4290 | | |
4291 | 3.90k | ps_codec->u4_size_header_data = size_of_row; |
4292 | | |
4293 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4294 | 31.2k | { |
4295 | 31.2k | if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) |
4296 | 31.2k | { |
4297 | 31.2k | ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf; |
4298 | 31.2k | ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data = |
4299 | 31.2k | pu1_buf; |
4300 | 31.2k | } |
4301 | 0 | else |
4302 | 0 | { |
4303 | 0 | ps_codec->as_process[i].pv_pic_mb_header_data = pu1_buf + size; |
4304 | 0 | ps_codec->as_process[i].s_entropy.pv_pic_mb_header_data = |
4305 | 0 | pu1_buf + size; |
4306 | 0 | } |
4307 | 31.2k | } |
4308 | 3.90k | } |
4309 | | |
4310 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBANK]; |
4311 | 3.90k | { |
4312 | | /* size of buf mgr struct */ |
4313 | 3.90k | WORD32 size = ih264_buf_mgr_size(); |
4314 | | |
4315 | | /* temp var */ |
4316 | 3.90k | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4317 | | |
4318 | | /* mv buffer mgr */ |
4319 | 3.90k | ps_codec->pv_mv_buf_mgr_base = pu1_buf; |
4320 | | |
4321 | | /* mv bank */ |
4322 | 3.90k | ps_codec->pv_mv_bank_buf_base = pu1_buf + size; |
4323 | 3.90k | ps_codec->i4_total_mv_bank_size = ps_mem_rec->u4_mem_size - size; |
4324 | 3.90k | } |
4325 | | |
4326 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_MVBITS]; |
4327 | 3.90k | { |
4328 | | /* max srch range x */ |
4329 | 3.90k | UWORD32 u4_srch_range_x = ps_ip->s_ive_ip.u4_max_srch_rng_x; |
4330 | | |
4331 | | /* max srch range y */ |
4332 | 3.90k | UWORD32 u4_srch_range_y = ps_ip->s_ive_ip.u4_max_srch_rng_y; |
4333 | | |
4334 | | /* max srch range */ |
4335 | 3.90k | UWORD32 u4_max_srch_range = MAX(u4_srch_range_x, u4_srch_range_y); |
4336 | | |
4337 | | /* temp var */ |
4338 | 3.90k | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4339 | | |
4340 | | /* due to subpel */ |
4341 | 3.90k | u4_max_srch_range <<= 2; |
4342 | | |
4343 | | // /* due to mv on either direction */ |
4344 | | // u4_max_srch_range = (u4_max_srch_range << 1); |
4345 | | |
4346 | | /* due to pred mv + zero */ |
4347 | 3.90k | u4_max_srch_range = (u4_max_srch_range << 1) + 1; |
4348 | | |
4349 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4350 | 31.2k | { |
4351 | | /* me ctxt */ |
4352 | 31.2k | me_ctxt_t *ps_mem_ctxt = &(ps_codec->as_process[i].s_me_ctxt); |
4353 | | |
4354 | | /* init at zero mv */ |
4355 | 31.2k | ps_mem_ctxt->pu1_mv_bits = pu1_buf + u4_max_srch_range; |
4356 | 31.2k | } |
4357 | 3.90k | } |
4358 | | |
4359 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_INTRA_COST]; |
4360 | 3.90k | { |
4361 | 3.90k | ps_codec->pi4_mb_intra_cost = ps_mem_rec->pv_base; |
4362 | 3.90k | } |
4363 | | |
4364 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_SPS]; |
4365 | 3.90k | { |
4366 | 3.90k | ps_codec->ps_sps_base = (sps_t *) ps_mem_rec->pv_base; |
4367 | 3.90k | } |
4368 | | |
4369 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_PPS]; |
4370 | 3.90k | { |
4371 | 3.90k | ps_codec->ps_pps_base = (pps_t *) ps_mem_rec->pv_base; |
4372 | 3.90k | } |
4373 | | |
4374 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_HDR]; |
4375 | 3.90k | { |
4376 | 3.90k | ps_codec->ps_slice_hdr_base = ps_mem_rec->pv_base; |
4377 | | |
4378 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4379 | 31.2k | { |
4380 | 31.2k | if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) |
4381 | 31.2k | { |
4382 | 31.2k | ps_codec->as_process[i].ps_slice_hdr_base = ps_mem_rec->pv_base; |
4383 | 31.2k | } |
4384 | 0 | else |
4385 | 0 | { |
4386 | | /* temp var */ |
4387 | 0 | WORD32 size = MAX_SLICE_HDR_CNT * sizeof(slice_header_t); |
4388 | 0 | void *pv_buf = (UWORD8 *) ps_mem_rec->pv_base + size; |
4389 | |
|
4390 | 0 | ps_codec->as_process[i].ps_slice_hdr_base = pv_buf; |
4391 | 0 | } |
4392 | 31.2k | } |
4393 | 3.90k | } |
4394 | | |
4395 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_AIR_MAP]; |
4396 | 3.90k | { |
4397 | | /* temp var */ |
4398 | 3.90k | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4399 | | |
4400 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4401 | 31.2k | { |
4402 | 31.2k | if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) |
4403 | 31.2k | { |
4404 | 31.2k | ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf; |
4405 | 31.2k | } |
4406 | 0 | else |
4407 | 0 | { |
4408 | 0 | ps_codec->as_process[i].pu1_is_intra_coded = pu1_buf |
4409 | 0 | + max_mb_cnt; |
4410 | 0 | } |
4411 | 31.2k | } |
4412 | | |
4413 | 3.90k | ps_codec->pu2_intr_rfrsh_map = (UWORD16 *) (pu1_buf + max_mb_cnt * MAX_CTXT_SETS); |
4414 | 3.90k | } |
4415 | | |
4416 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_SLICE_MAP]; |
4417 | 3.90k | { |
4418 | | /* pointer to storage space */ |
4419 | 3.90k | UWORD8 *pu1_buf_ping, *pu1_buf_pong; |
4420 | | |
4421 | | /* init pointer */ |
4422 | 3.90k | pu1_buf_ping = ps_mem_rec->pv_base; |
4423 | 3.90k | pu1_buf_pong = pu1_buf_ping + ALIGN64(max_mb_cnt); |
4424 | | |
4425 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4426 | 31.2k | { |
4427 | 31.2k | if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) |
4428 | 31.2k | { |
4429 | 31.2k | ps_codec->as_process[i].pu1_slice_idx = pu1_buf_ping; |
4430 | 31.2k | } |
4431 | 0 | else |
4432 | 0 | { |
4433 | 0 | ps_codec->as_process[i].pu1_slice_idx = pu1_buf_pong; |
4434 | 0 | } |
4435 | 31.2k | } |
4436 | 3.90k | } |
4437 | | |
4438 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_THREAD_HANDLE]; |
4439 | 3.90k | { |
4440 | 3.90k | UWORD8 *pu1_buf = (UWORD8 *)ps_mem_rec->pv_base; |
4441 | 3.90k | WORD32 handle_size = ithread_get_handle_size(); |
4442 | | |
4443 | 3.90k | if (ps_ip->s_ive_ip.u4_keep_threads_active) |
4444 | 3.90k | { |
4445 | 3.90k | ps_codec->s_thread_pool.pv_thread_pool_mutex = (void *)pu1_buf; |
4446 | 3.90k | pu1_buf += ithread_get_mutex_lock_size(); |
4447 | | |
4448 | 3.90k | ps_codec->s_thread_pool.pv_thread_pool_cond = (void *)pu1_buf; |
4449 | 3.90k | pu1_buf += ithread_get_cond_size(); |
4450 | 3.90k | } |
4451 | | |
4452 | 35.1k | for (i = 0; i < MAX_PROCESS_THREADS; i++) |
4453 | 31.2k | { |
4454 | 31.2k | ps_codec->apv_proc_thread_handle[i] = (void *)(pu1_buf + (i * handle_size)); |
4455 | 31.2k | } |
4456 | 3.90k | } |
4457 | | |
4458 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_CTL_MUTEX]; |
4459 | 3.90k | { |
4460 | 3.90k | ps_codec->pv_ctl_mutex = ps_mem_rec->pv_base; |
4461 | 3.90k | } |
4462 | | |
4463 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_MUTEX]; |
4464 | 3.90k | { |
4465 | 3.90k | ps_codec->pv_entropy_mutex = ps_mem_rec->pv_base; |
4466 | 3.90k | } |
4467 | | |
4468 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_JOBQ]; |
4469 | 3.90k | { |
4470 | 3.90k | ps_codec->pv_proc_jobq_buf = ps_mem_rec->pv_base; |
4471 | 3.90k | ps_codec->i4_proc_jobq_buf_size = ps_mem_rec->u4_mem_size; |
4472 | 3.90k | } |
4473 | | |
4474 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_ENTROPY_JOBQ]; |
4475 | 3.90k | { |
4476 | 3.90k | ps_codec->pv_entropy_jobq_buf = ps_mem_rec->pv_base; |
4477 | 3.90k | ps_codec->i4_entropy_jobq_buf_size = ps_mem_rec->u4_mem_size; |
4478 | 3.90k | } |
4479 | | |
4480 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_MAP]; |
4481 | 3.90k | { |
4482 | | /* pointer to storage space */ |
4483 | 3.90k | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4484 | | |
4485 | | /* total size of the mem record */ |
4486 | 3.90k | WORD32 total_size = 0; |
4487 | | |
4488 | | /* size in bytes to mb core coding status of an entire frame */ |
4489 | 3.90k | total_size = max_mb_cnt; |
4490 | | |
4491 | | /* add an additional 1 row of bytes to evade the special case of row 0 */ |
4492 | 3.90k | total_size += max_mb_cols; |
4493 | | |
4494 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4495 | 31.2k | { |
4496 | 31.2k | if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) |
4497 | 31.2k | { |
4498 | 31.2k | ps_codec->as_process[i].pu1_proc_map = pu1_buf + max_mb_cols; |
4499 | 31.2k | } |
4500 | 0 | else |
4501 | 0 | { |
4502 | 0 | ps_codec->as_process[i].pu1_proc_map = pu1_buf + total_size |
4503 | 0 | + max_mb_cols; |
4504 | 0 | } |
4505 | 31.2k | } |
4506 | 3.90k | } |
4507 | | |
4508 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_DBLK_MAP]; |
4509 | 3.90k | { |
4510 | | /* pointer to storage space */ |
4511 | 3.90k | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4512 | | |
4513 | | /* total size of the mem record */ |
4514 | 3.90k | WORD32 total_size = 0; |
4515 | | |
4516 | | /* size in bytes to mb core coding status of an entire frame */ |
4517 | 3.90k | total_size = max_mb_cnt; |
4518 | | |
4519 | | /* add an additional 1 row of bytes to evade the special case of row 0 */ |
4520 | 3.90k | total_size += max_mb_cols; |
4521 | | |
4522 | | /*Align the memory offsets*/ |
4523 | 3.90k | total_size = ALIGN64(total_size); |
4524 | | |
4525 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4526 | 31.2k | { |
4527 | 31.2k | if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) |
4528 | 31.2k | { |
4529 | 31.2k | ps_codec->as_process[i].pu1_deblk_map = pu1_buf + max_mb_cols; |
4530 | | |
4531 | 31.2k | } |
4532 | 0 | else |
4533 | 0 | { |
4534 | 0 | ps_codec->as_process[i].pu1_deblk_map = pu1_buf + total_size |
4535 | 0 | + max_mb_cols; |
4536 | |
|
4537 | 0 | } |
4538 | 31.2k | } |
4539 | 3.90k | } |
4540 | | |
4541 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_ME_MAP]; |
4542 | 3.90k | { |
4543 | | /* pointer to storage space */ |
4544 | 3.90k | UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base; |
4545 | | |
4546 | | /* total size of the mem record */ |
4547 | 3.90k | WORD32 total_size = 0; |
4548 | | |
4549 | | /* size in bytes to mb core coding status of an entire frame */ |
4550 | 3.90k | total_size = max_mb_cnt; |
4551 | | |
4552 | | /* add an additional 1 row of bytes to evade the special case of row 0 */ |
4553 | 3.90k | total_size += max_mb_cols; |
4554 | | |
4555 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4556 | 31.2k | { |
4557 | 31.2k | if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) |
4558 | 31.2k | { |
4559 | 31.2k | ps_codec->as_process[i].pu1_me_map = pu1_buf + max_mb_cols; |
4560 | 31.2k | } |
4561 | 0 | else |
4562 | 0 | { |
4563 | 0 | ps_codec->as_process[i].pu1_me_map = pu1_buf + total_size |
4564 | 0 | + max_mb_cols; |
4565 | 0 | } |
4566 | 31.2k | } |
4567 | 3.90k | } |
4568 | | |
4569 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_DPB_MGR]; |
4570 | 3.90k | { |
4571 | 3.90k | ps_codec->pv_dpb_mgr = ps_mem_rec->pv_base; |
4572 | 3.90k | } |
4573 | | |
4574 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_PROC_SCRATCH]; |
4575 | 3.90k | { |
4576 | | /* pointer to storage space */ |
4577 | 3.90k | UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base; |
4578 | | |
4579 | | /* size of pred buffer, fwd transform output, temp buffer for inv tra */ |
4580 | 3.90k | WORD32 size_pred_luma, size_pred_chroma, size_fwd, size_inv, size_hp; |
4581 | | |
4582 | | /* temp var */ |
4583 | 3.90k | WORD32 size = 0; |
4584 | | |
4585 | | /* size to hold intra/inter prediction buffer */ |
4586 | 3.90k | size_pred_luma = sizeof(UWORD8) * 16 * 16; |
4587 | 3.90k | size_pred_chroma = sizeof(UWORD8) * 8 * 16; |
4588 | | |
4589 | | /* size to hold fwd transform output */ |
4590 | 3.90k | size_fwd = sizeof(WORD16) * SIZE_TRANS_BUFF; |
4591 | | |
4592 | | /* size to hold temporary data during inverse transform */ |
4593 | 3.90k | size_inv = sizeof(WORD32) * SIZE_TMP_BUFF_ITRANS; |
4594 | | |
4595 | | /* size to hold half pel plane buffers */ |
4596 | 3.90k | size_hp = sizeof(UWORD8) * (HP_BUFF_WD * HP_BUFF_HT); |
4597 | | |
4598 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4599 | 31.2k | { |
4600 | | /* prediction buffer */ |
4601 | 31.2k | ps_codec->as_process[i].pu1_pred_mb = (void *) (pu1_buf + size); |
4602 | 31.2k | ps_codec->as_process[i].i4_pred_strd = 16; |
4603 | 31.2k | size += size_pred_luma; |
4604 | 31.2k | size = ALIGN64(size); |
4605 | | |
4606 | | /* prediction buffer */ |
4607 | 31.2k | ps_codec->as_process[i].pu1_ref_mb_intra_4x4 = (void *) (pu1_buf |
4608 | 31.2k | + size); |
4609 | 31.2k | size += size_pred_luma; |
4610 | 31.2k | size = ALIGN64(size); |
4611 | | |
4612 | | /* prediction buffer intra 16x16 */ |
4613 | 31.2k | ps_codec->as_process[i].pu1_pred_mb_intra_16x16 = (void *) (pu1_buf |
4614 | 31.2k | + size); |
4615 | 31.2k | size += size_pred_luma; |
4616 | 31.2k | size = ALIGN64(size); |
4617 | | |
4618 | | /* prediction buffer intra 16x16 plane*/ |
4619 | 31.2k | ps_codec->as_process[i].pu1_pred_mb_intra_16x16_plane = |
4620 | 31.2k | (void *) (pu1_buf + size); |
4621 | 31.2k | size += size_pred_luma; |
4622 | 31.2k | size = ALIGN64(size); |
4623 | | |
4624 | | /* prediction buffer intra chroma*/ |
4625 | 31.2k | ps_codec->as_process[i].pu1_pred_mb_intra_chroma = (void *) (pu1_buf |
4626 | 31.2k | + size); |
4627 | 31.2k | size += size_pred_chroma; |
4628 | 31.2k | size = ALIGN64(size); |
4629 | | |
4630 | | /* prediction buffer intra chroma plane*/ |
4631 | 31.2k | ps_codec->as_process[i].pu1_pred_mb_intra_chroma_plane = |
4632 | 31.2k | (void *) (pu1_buf + size); |
4633 | 31.2k | size += size_pred_chroma; |
4634 | 31.2k | size = ALIGN64(size); |
4635 | | |
4636 | | /* Fwd transform output */ |
4637 | 31.2k | ps_codec->as_process[i].pi2_res_buf = (void *) (pu1_buf + size); |
4638 | 31.2k | ps_codec->as_process[i].i4_res_strd = 16; |
4639 | 31.2k | size += size_fwd; |
4640 | 31.2k | size = ALIGN64(size); |
4641 | | |
4642 | | /* Fwd transform output */ |
4643 | 31.2k | ps_codec->as_process[i].pi2_res_buf_intra_4x4 = (void *) (pu1_buf |
4644 | 31.2k | + size); |
4645 | 31.2k | size += size_fwd; |
4646 | 31.2k | size = ALIGN64(size); |
4647 | | |
4648 | | /* scratch buffer used during inverse transform */ |
4649 | 31.2k | ps_codec->as_process[i].pv_scratch_buff = (void *) (pu1_buf + size); |
4650 | 31.2k | size += size_inv; |
4651 | 31.2k | size = ALIGN64(size); |
4652 | | |
4653 | 156k | for (j = 0; j < SUBPEL_BUFF_CNT; j++) |
4654 | 124k | { |
4655 | 124k | ps_codec->as_process[i].apu1_subpel_buffs[j] = (pu1_buf + size); |
4656 | 124k | size += ALIGN64(size_hp); |
4657 | 124k | } |
4658 | 31.2k | } |
4659 | 3.90k | } |
4660 | | |
4661 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_QUANT_PARAM]; |
4662 | 3.90k | { |
4663 | | /* pointer to storage space */ |
4664 | 3.90k | UWORD8 *pu1_buf = (UWORD8 *) ps_mem_rec->pv_base; |
4665 | | |
4666 | | /* size of qp, threshold matrix, fwd scaling list for one plane */ |
4667 | 3.90k | WORD32 size_quant_param, size_thres_mat, size_fwd_weight_mat, |
4668 | 3.90k | size_satqd_weight_mat; |
4669 | | |
4670 | | /* temp var */ |
4671 | 3.90k | WORD32 total_size = 0; |
4672 | | |
4673 | | /* size of quantization parameter list of 1 plane */ |
4674 | 3.90k | size_quant_param = ALIGN64(sizeof(quant_params_t)); |
4675 | | |
4676 | | /* size of threshold matrix for quantization |
4677 | | * (assuming the transform_8x8_flag is disabled). |
4678 | | * for 1 plane */ |
4679 | 3.90k | size_thres_mat = ALIGN64(sizeof(WORD16) * 4 * 4); |
4680 | | |
4681 | | /* size of forward weight matrix for quantization |
4682 | | * (assuming the transform_8x8_flag is disabled). |
4683 | | * for 1 plane */ |
4684 | 3.90k | size_fwd_weight_mat = ALIGN64(sizeof(WORD16) * 4 * 4); |
4685 | | |
4686 | | /* size of SATQD matrix*/ |
4687 | 3.90k | size_satqd_weight_mat = ALIGN64(sizeof(UWORD16) * 9); |
4688 | | |
4689 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4690 | 31.2k | { |
4691 | 31.2k | quant_params_t **ps_qp_params = ps_codec->as_process[i].ps_qp_params; |
4692 | | |
4693 | | /* quantization param structure */ |
4694 | 31.2k | ps_qp_params[0] = (quant_params_t *) (pu1_buf + total_size); |
4695 | 31.2k | total_size = total_size + size_quant_param; |
4696 | 31.2k | ps_qp_params[1] = (quant_params_t *) (pu1_buf + total_size); |
4697 | 31.2k | total_size = total_size + size_quant_param; |
4698 | 31.2k | ps_qp_params[2] = (quant_params_t *) (pu1_buf + total_size); |
4699 | 31.2k | total_size = total_size + size_quant_param; |
4700 | | |
4701 | | /* threshold matrix for quantization */ |
4702 | 31.2k | ps_qp_params[0]->pu2_thres_mat = (void *) (pu1_buf + total_size); |
4703 | 31.2k | total_size = total_size + size_thres_mat; |
4704 | 31.2k | ps_qp_params[1]->pu2_thres_mat = (void *) (pu1_buf + total_size); |
4705 | 31.2k | total_size = total_size + size_thres_mat; |
4706 | 31.2k | ps_qp_params[2]->pu2_thres_mat = (void *) (pu1_buf + total_size); |
4707 | 31.2k | total_size = total_size + size_thres_mat; |
4708 | | |
4709 | | /* fwd weight matrix */ |
4710 | 31.2k | ps_qp_params[0]->pu2_weigh_mat = (void *) (pu1_buf + total_size); |
4711 | 31.2k | total_size = total_size + size_fwd_weight_mat; |
4712 | 31.2k | ps_qp_params[1]->pu2_weigh_mat = (void *) (pu1_buf + total_size); |
4713 | 31.2k | total_size = total_size + size_fwd_weight_mat; |
4714 | 31.2k | ps_qp_params[2]->pu2_weigh_mat = (void *) (pu1_buf + total_size); |
4715 | 31.2k | total_size = total_size + size_fwd_weight_mat; |
4716 | | |
4717 | | /* threshold matrix for SATQD */ |
4718 | 31.2k | ps_qp_params[0]->pu2_sad_thrsh = (void *) (pu1_buf + total_size); |
4719 | 31.2k | total_size = total_size + size_satqd_weight_mat; |
4720 | 31.2k | ps_qp_params[1]->pu2_sad_thrsh = (void *) (pu1_buf + total_size); |
4721 | 31.2k | total_size = total_size + size_satqd_weight_mat; |
4722 | 31.2k | ps_qp_params[2]->pu2_sad_thrsh = (void *) (pu1_buf + total_size); |
4723 | 31.2k | total_size = total_size + size_satqd_weight_mat; |
4724 | | |
4725 | 31.2k | total_size = ALIGN128(total_size); |
4726 | 31.2k | } |
4727 | 3.90k | } |
4728 | | |
4729 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_TOP_ROW_SYN_INFO]; |
4730 | 3.90k | { |
4731 | | /* total size of the mem record */ |
4732 | 3.90k | WORD32 total_size = 0, size_csbp, size_intra_modes, size_mv; |
4733 | | |
4734 | | /* pointer to buffer */ |
4735 | 3.90k | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4736 | | |
4737 | | /* size in bytes to store 1 row of mb_info_t */ |
4738 | | /* one additional mb, to avoid checking end of row condition */ |
4739 | 3.90k | size_csbp = (max_mb_cols + 1) * sizeof(mb_info_t); |
4740 | | |
4741 | | /* size in bytes to store 1 row of intra macroblock sub modes */ |
4742 | 3.90k | size_intra_modes = max_mb_cols * sizeof(UWORD8) * 16; |
4743 | | |
4744 | | /* size in bytes to store 1 row + 1 of enc_pu_t */ |
4745 | | /* one additional mb, to avoid checking end of row condition */ |
4746 | 3.90k | size_mv = (max_mb_cols + 1) * sizeof(enc_pu_t); |
4747 | | |
4748 | | /* total size per proc ctxt */ |
4749 | 3.90k | total_size = size_csbp + size_intra_modes + size_mv; |
4750 | | |
4751 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4752 | 31.2k | { |
4753 | 31.2k | if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) |
4754 | 31.2k | { |
4755 | 31.2k | ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base = |
4756 | 31.2k | (mb_info_t *) pu1_buf; |
4757 | 31.2k | ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf |
4758 | 31.2k | + size_csbp; |
4759 | 31.2k | ps_codec->as_process[i].ps_top_row_pu_base = |
4760 | 31.2k | (enc_pu_t *) (pu1_buf + size_csbp |
4761 | 31.2k | + size_intra_modes); |
4762 | 31.2k | } |
4763 | 0 | else |
4764 | 0 | { |
4765 | 0 | ps_codec->as_process[i].ps_top_row_mb_syntax_ele_base = |
4766 | 0 | (mb_info_t *) (pu1_buf + total_size); |
4767 | 0 | ps_codec->as_process[i].pu1_top_mb_intra_modes_base = pu1_buf |
4768 | 0 | + total_size + size_csbp; |
4769 | 0 | ps_codec->as_process[i].ps_top_row_pu_base = |
4770 | 0 | (enc_pu_t *) (pu1_buf + total_size + size_csbp |
4771 | 0 | + size_intra_modes); |
4772 | 0 | } |
4773 | 31.2k | } |
4774 | 3.90k | } |
4775 | | |
4776 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_BS_QP]; |
4777 | 3.90k | { |
4778 | 3.90k | UWORD8 *pu1_buf_ping, *pu1_buf_pong; |
4779 | | |
4780 | | /* total size of the mem record */ |
4781 | 3.90k | WORD32 total_size = 0; |
4782 | | |
4783 | | /* size in bytes to store vertical edge bs, horizontal edge bs and qp of every mb*/ |
4784 | 3.90k | WORD32 vert_bs_size, horz_bs_size, qp_size; |
4785 | | |
4786 | | /* vertical edge bs = total number of vertical edges * number of bytes per each edge */ |
4787 | | /* total num of v edges = total mb * 4 (assuming transform_8x8_flag = 0), |
4788 | | * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */ |
4789 | 3.90k | vert_bs_size = ALIGN64(max_mb_cnt * 4 * 4); |
4790 | | |
4791 | | /* horizontal edge bs = total number of horizontal edges * number of bytes per each edge */ |
4792 | | /* total num of h edges = total mb * 4 (assuming transform_8x8_flag = 0), |
4793 | | * each edge is formed by 4 pairs of subblks, requiring 4 bytes to storing bs */ |
4794 | 3.90k | horz_bs_size = ALIGN64(max_mb_cnt * 4 * 4); |
4795 | | |
4796 | | /* qp of each mb requires 1 byte */ |
4797 | 3.90k | qp_size = ALIGN64(max_mb_cnt); |
4798 | | |
4799 | | /* total size */ |
4800 | 3.90k | total_size = vert_bs_size + horz_bs_size + qp_size; |
4801 | | |
4802 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4803 | 31.2k | { |
4804 | 31.2k | if (i < MAX_PROCESS_CTXT / MAX_CTXT_SETS) |
4805 | 31.2k | { |
4806 | 31.2k | pu1_buf_ping = (UWORD8 *) ps_mem_rec->pv_base; |
4807 | | |
4808 | | /* vertical edge bs storage space */ |
4809 | 31.2k | ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs = |
4810 | 31.2k | (UWORD32 *) pu1_buf_ping; |
4811 | 31.2k | pu1_buf_ping += vert_bs_size; |
4812 | | |
4813 | | /* horizontal edge bs storage space */ |
4814 | 31.2k | ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs = |
4815 | 31.2k | (UWORD32 *) pu1_buf_ping; |
4816 | 31.2k | pu1_buf_ping += horz_bs_size; |
4817 | | |
4818 | | /* qp */ |
4819 | 31.2k | ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp = |
4820 | 31.2k | (UWORD8 *) pu1_buf_ping; |
4821 | 31.2k | pu1_buf_ping += qp_size; |
4822 | 31.2k | } |
4823 | 0 | else |
4824 | 0 | { |
4825 | 0 | pu1_buf_pong = (UWORD8 *) ps_mem_rec->pv_base; |
4826 | 0 | pu1_buf_pong += total_size; |
4827 | | |
4828 | | /* vertical edge bs storage space */ |
4829 | 0 | ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_vert_bs = |
4830 | 0 | (UWORD32 *) pu1_buf_pong; |
4831 | 0 | pu1_buf_pong += vert_bs_size; |
4832 | | |
4833 | | /* horizontal edge bs storage space */ |
4834 | 0 | ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu4_pic_horz_bs = |
4835 | 0 | (UWORD32 *) pu1_buf_pong; |
4836 | 0 | pu1_buf_pong += horz_bs_size; |
4837 | | |
4838 | | /* qp */ |
4839 | 0 | ps_codec->as_process[i].s_deblk_ctxt.s_bs_ctxt.pu1_pic_qp = |
4840 | 0 | (UWORD8 *) pu1_buf_pong; |
4841 | 0 | pu1_buf_pong += qp_size; |
4842 | 0 | } |
4843 | 31.2k | } |
4844 | 3.90k | } |
4845 | | |
4846 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_INP_PIC]; |
4847 | 3.90k | { |
4848 | 3.90k | ps_codec->pv_inp_buf_mgr_base = ps_mem_rec->pv_base; |
4849 | 3.90k | } |
4850 | | |
4851 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_OUT]; |
4852 | 3.90k | { |
4853 | 3.90k | ps_codec->pv_out_buf_mgr_base = ps_mem_rec->pv_base; |
4854 | 3.90k | } |
4855 | | |
4856 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_CSC]; |
4857 | 3.90k | { |
4858 | 3.90k | ps_codec->pu1_y_csc_buf_base = ps_mem_rec->pv_base; |
4859 | 3.90k | ps_codec->pu1_uv_csc_buf_base = (UWORD8 *) ps_mem_rec->pv_base |
4860 | 3.90k | + (max_ht_luma * max_wd_luma); |
4861 | 3.90k | } |
4862 | | |
4863 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_REF_PIC]; |
4864 | 3.90k | { |
4865 | | /* size of buf mgr struct */ |
4866 | 3.90k | WORD32 size = ih264_buf_mgr_size(); |
4867 | | |
4868 | | /* temp var */ |
4869 | 3.90k | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4870 | | |
4871 | | /* pic buffer mgr */ |
4872 | 3.90k | ps_codec->pv_ref_buf_mgr_base = pu1_buf; |
4873 | | |
4874 | | /* picture bank */ |
4875 | 3.90k | ps_codec->pv_pic_buf_base = pu1_buf + size; |
4876 | 3.90k | ps_codec->i4_total_pic_buf_size = ps_mem_rec->u4_mem_size - size; |
4877 | 3.90k | } |
4878 | | |
4879 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_MB_INFO_NMB]; |
4880 | 3.90k | { |
4881 | | /* temp var */ |
4882 | 3.90k | UWORD8 *pu1_buf = ps_mem_rec->pv_base; |
4883 | | |
4884 | | /* size of nmb ctxt */ |
4885 | 3.90k | WORD32 size = max_mb_cols * sizeof(mb_info_nmb_t); |
4886 | | |
4887 | 3.90k | WORD32 nmb_cntr, subpel_buf_size; |
4888 | | |
4889 | | /* init nmb info structure pointer in all proc ctxts */ |
4890 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4891 | 31.2k | { |
4892 | 31.2k | ps_codec->as_process[i].ps_nmb_info = (mb_info_nmb_t *) (pu1_buf); |
4893 | | |
4894 | 31.2k | pu1_buf += size; |
4895 | 31.2k | } |
4896 | | |
4897 | 3.90k | subpel_buf_size = MB_SIZE * MB_SIZE * sizeof(UWORD8); |
4898 | | |
4899 | | /* adjusting pointers for nmb halfpel buffer */ |
4900 | 35.1k | for (i = 0; i < MAX_PROCESS_CTXT; i++) |
4901 | 31.2k | { |
4902 | 31.2k | mb_info_nmb_t* ps_mb_info_nmb = |
4903 | 31.2k | &ps_codec->as_process[i].ps_nmb_info[0]; |
4904 | | |
4905 | 716k | for (nmb_cntr = 0; nmb_cntr < max_mb_cols; nmb_cntr++) |
4906 | 684k | { |
4907 | 684k | ps_mb_info_nmb[nmb_cntr].pu1_best_sub_pel_buf = pu1_buf; |
4908 | | |
4909 | 684k | pu1_buf = pu1_buf + subpel_buf_size; |
4910 | | |
4911 | 684k | ps_mb_info_nmb[nmb_cntr].u4_bst_spel_buf_strd = MB_SIZE; |
4912 | 684k | } |
4913 | 31.2k | } |
4914 | 3.90k | } |
4915 | | |
4916 | 3.90k | ps_mem_rec = &ps_mem_rec_base[MEM_REC_RC]; |
4917 | 3.90k | { |
4918 | 3.90k | ih264e_get_rate_control_mem_tab(&ps_codec->s_rate_control, ps_mem_rec, |
4919 | 3.90k | USE_BASE); |
4920 | 3.90k | } |
4921 | | |
4922 | | /* init codec ctxt */ |
4923 | 3.90k | status = ih264e_init(ps_codec); |
4924 | | |
4925 | 3.90k | return status; |
4926 | 3.90k | } |
4927 | | |
4928 | | /** |
4929 | | ******************************************************************************* |
4930 | | * |
4931 | | * @brief |
4932 | | * Retrieves mem records passed to the codec |
4933 | | * |
4934 | | * @par Description: |
4935 | | * Retrieves mem recs passed during init |
4936 | | * |
4937 | | * @param[in] ps_codec_obj |
4938 | | * Pointer to codec object at API level |
4939 | | * |
4940 | | * @param[in] pv_api_ip |
4941 | | * Pointer to input argument structure |
4942 | | * |
4943 | | * @param[out] pv_api_op |
4944 | | * Pointer to output argument structure |
4945 | | * |
4946 | | * @returns error status |
4947 | | * |
4948 | | * @remarks none |
4949 | | * |
4950 | | ******************************************************************************* |
4951 | | */ |
4952 | | static WORD32 ih264e_retrieve_memrec(iv_obj_t *ps_codec_obj, |
4953 | | void *pv_api_ip, |
4954 | | void *pv_api_op) |
4955 | 3.90k | { |
4956 | | /* codec ctxt */ |
4957 | 3.90k | codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle; |
4958 | | |
4959 | | /* ctrl call I/O structures */ |
4960 | 3.90k | ih264e_retrieve_mem_rec_ip_t *ps_ip = pv_api_ip; |
4961 | 3.90k | ih264e_retrieve_mem_rec_op_t *ps_op = pv_api_op; |
4962 | | |
4963 | 3.90k | if (ps_codec->i4_init_done != 1) |
4964 | 0 | { |
4965 | 0 | ps_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR; |
4966 | 0 | ps_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE; |
4967 | 0 | return IV_FAIL; |
4968 | 0 | } |
4969 | | |
4970 | 3.90k | if (ps_codec->s_cfg.u4_keep_threads_active) |
4971 | 3.90k | { |
4972 | 3.90k | ih264e_thread_pool_shutdown(ps_codec); |
4973 | 3.90k | ithread_cond_destroy(ps_codec->s_thread_pool.pv_thread_pool_cond); |
4974 | 3.90k | ithread_mutex_destroy(ps_codec->s_thread_pool.pv_thread_pool_mutex); |
4975 | 3.90k | } |
4976 | 0 | else |
4977 | 0 | { |
4978 | | /* join threads upon at end of sequence */ |
4979 | 0 | ih264e_join_threads(ps_codec); |
4980 | 0 | } |
4981 | | |
4982 | | /* collect list of memory records used by the encoder library */ |
4983 | 3.90k | memcpy(ps_ip->s_ive_ip.ps_mem_rec, ps_codec->ps_mem_rec_backup, |
4984 | 3.90k | MEM_REC_CNT * (sizeof(iv_mem_rec_t))); |
4985 | 3.90k | ps_op->s_ive_op.u4_num_mem_rec_filled = MEM_REC_CNT; |
4986 | | |
4987 | | /* clean up mutex memory */ |
4988 | 3.90k | ih264_list_free(ps_codec->pv_entropy_jobq); |
4989 | 3.90k | ih264_list_free(ps_codec->pv_proc_jobq); |
4990 | 3.90k | ithread_mutex_destroy(ps_codec->pv_ctl_mutex); |
4991 | 3.90k | ithread_mutex_destroy(ps_codec->pv_entropy_mutex); |
4992 | | |
4993 | 3.90k | ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_mv_buf_mgr); |
4994 | 3.90k | ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_ref_buf_mgr); |
4995 | 3.90k | ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_inp_buf_mgr); |
4996 | 3.90k | ih264_buf_mgr_free((buf_mgr_t *)ps_codec->pv_out_buf_mgr); |
4997 | | |
4998 | 3.90k | return IV_SUCCESS; |
4999 | 3.90k | } |
5000 | | |
5001 | | /** |
5002 | | ******************************************************************************* |
5003 | | * |
5004 | | * @brief |
5005 | | * Sets the encoder in flush mode. |
5006 | | * |
5007 | | * @par Description: |
5008 | | * Sets the encoder in flush mode |
5009 | | * |
5010 | | * @param[in] ps_codec_obj |
5011 | | * Pointer to codec object at API level |
5012 | | * |
5013 | | * @param[in] pv_api_ip |
5014 | | * Pointer to input argument structure |
5015 | | * |
5016 | | * @param[out] pv_api_op |
5017 | | * Pointer to output argument structure |
5018 | | * |
5019 | | * @returns error status |
5020 | | * |
5021 | | * @remarks This call has no real effect on encoder |
5022 | | * |
5023 | | ******************************************************************************* |
5024 | | */ |
5025 | | static WORD32 ih264e_set_flush_mode(iv_obj_t *ps_codec_obj, |
5026 | | void *pv_api_ip, |
5027 | | void *pv_api_op) |
5028 | 0 | { |
5029 | | /* codec ctxt */ |
5030 | 0 | codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle; |
5031 | | |
5032 | | /* ctrl call I/O structures */ |
5033 | 0 | ih264e_ctl_flush_op_t *ps_ctl_op = pv_api_op; |
5034 | |
|
5035 | 0 | UNUSED(pv_api_ip); |
5036 | |
|
5037 | 0 | ps_ctl_op->s_ive_op.u4_error_code = 0; |
5038 | | |
5039 | | /* signal flush frame control call */ |
5040 | 0 | ps_codec->i4_flush_mode = 1; |
5041 | |
|
5042 | 0 | return IV_SUCCESS; |
5043 | 0 | } |
5044 | | |
5045 | | /** |
5046 | | ******************************************************************************* |
5047 | | * |
5048 | | * @brief |
5049 | | * Gets encoder buffer requirements |
5050 | | * |
5051 | | * @par Description: |
5052 | | * Gets the encoder buffer requirements. Basing on max width and max height |
5053 | | * configuration settings, this routine, computes the sizes of necessary input, |
5054 | | * output buffers returns this info to callee. |
5055 | | * |
5056 | | * @param[in] ps_codec_obj |
5057 | | * Pointer to codec object at API level |
5058 | | * |
5059 | | * @param[in] pv_api_ip |
5060 | | * Pointer to input argument structure |
5061 | | * |
5062 | | * @param[out] pv_api_op |
5063 | | * Pointer to output argument structure |
5064 | | * |
5065 | | * @returns error status |
5066 | | * |
5067 | | * @remarks none |
5068 | | * |
5069 | | ******************************************************************************* |
5070 | | */ |
5071 | | static WORD32 ih264e_get_buf_info(iv_obj_t *ps_codec_obj, |
5072 | | void *pv_api_ip, |
5073 | | void *pv_api_op) |
5074 | 3.84k | { |
5075 | | /* ctrl call I/O structures */ |
5076 | 3.84k | ih264e_ctl_getbufinfo_ip_t *ps_ip = pv_api_ip; |
5077 | 3.84k | ih264e_ctl_getbufinfo_op_t *ps_op = pv_api_op; |
5078 | | |
5079 | | /* temp var */ |
5080 | 3.84k | WORD32 wd = ALIGN16(ps_ip->s_ive_ip.u4_max_wd); |
5081 | 3.84k | WORD32 ht = ALIGN16(ps_ip->s_ive_ip.u4_max_ht); |
5082 | 3.84k | WORD32 i; |
5083 | | |
5084 | 3.84k | UNUSED(ps_codec_obj); |
5085 | | |
5086 | 3.84k | ps_op->s_ive_op.u4_error_code = 0; |
5087 | | |
5088 | | /* Number of components in input buffers required for codec & |
5089 | | * Minimum sizes of each component in input buffer required */ |
5090 | 3.84k | if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420P) |
5091 | 1.57k | { |
5092 | 1.57k | ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420_COMP; |
5093 | | |
5094 | 1.57k | ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht; |
5095 | 1.57k | ps_op->s_ive_op.au4_min_in_buf_size[1] = (wd >> 1) * (ht >> 1); |
5096 | 1.57k | ps_op->s_ive_op.au4_min_in_buf_size[2] = (wd >> 1) * (ht >> 1); |
5097 | 1.57k | } |
5098 | 2.27k | else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_422ILE) |
5099 | 517 | { |
5100 | 517 | ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_422ILE_COMP; |
5101 | | |
5102 | 517 | ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2; |
5103 | 517 | ps_op->s_ive_op.au4_min_in_buf_size[1] = |
5104 | 517 | ps_op->s_ive_op.au4_min_in_buf_size[2] = 0; |
5105 | 517 | } |
5106 | 1.75k | else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGB_565) |
5107 | 0 | { |
5108 | 0 | ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGB565_COMP; |
5109 | |
|
5110 | 0 | ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 2; |
5111 | 0 | ps_op->s_ive_op.au4_min_in_buf_size[1] = |
5112 | 0 | ps_op->s_ive_op.au4_min_in_buf_size[2] = 0; |
5113 | 0 | } |
5114 | 1.75k | else if (ps_ip->s_ive_ip.e_inp_color_fmt == IV_RGBA_8888) |
5115 | 0 | { |
5116 | 0 | ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_RGBA8888_COMP; |
5117 | |
|
5118 | 0 | ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht * 4; |
5119 | 0 | ps_op->s_ive_op.au4_min_in_buf_size[1] = |
5120 | 0 | ps_op->s_ive_op.au4_min_in_buf_size[2] = 0; |
5121 | 0 | } |
5122 | 1.75k | else if ((ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_UV) |
5123 | 1.03k | || (ps_ip->s_ive_ip.e_inp_color_fmt == IV_YUV_420SP_VU)) |
5124 | 1.75k | { |
5125 | 1.75k | ps_op->s_ive_op.u4_inp_comp_cnt = MIN_RAW_BUFS_420SP_COMP; |
5126 | | |
5127 | 1.75k | ps_op->s_ive_op.au4_min_in_buf_size[0] = wd * ht; |
5128 | 1.75k | ps_op->s_ive_op.au4_min_in_buf_size[1] = wd * (ht >> 1); |
5129 | 1.75k | ps_op->s_ive_op.au4_min_in_buf_size[2] = 0; |
5130 | 1.75k | } |
5131 | | |
5132 | | /* Number of components in output buffers required for codec & |
5133 | | * Minimum sizes of each component in output buffer required */ |
5134 | 3.84k | ps_op->s_ive_op.u4_out_comp_cnt = MIN_BITS_BUFS_COMP; |
5135 | | |
5136 | 7.69k | for (i = 0; i < (WORD32) ps_op->s_ive_op.u4_out_comp_cnt; i++) |
5137 | 3.84k | { |
5138 | 3.84k | ps_op->s_ive_op.au4_min_out_buf_size[i] = MAX(((wd * ht * 3) >> 1), MIN_STREAM_SIZE); |
5139 | 3.84k | } |
5140 | | |
5141 | 3.84k | ps_op->s_ive_op.u4_min_inp_bufs = MIN_INP_BUFS; |
5142 | 3.84k | ps_op->s_ive_op.u4_min_out_bufs = MIN_OUT_BUFS; |
5143 | | |
5144 | 3.84k | return IV_SUCCESS; |
5145 | 3.84k | } |
5146 | | |
5147 | | /** |
5148 | | ******************************************************************************* |
5149 | | * |
5150 | | * @brief |
5151 | | * Sets the picture dimensions |
5152 | | * |
5153 | | * @par Description: |
5154 | | * Sets width, height, display width, display height and strides |
5155 | | * |
5156 | | * @param[in] pv_api_ip |
5157 | | * Pointer to input argument structure |
5158 | | * |
5159 | | * @param[out] pv_api_op |
5160 | | * Pointer to output argument structure |
5161 | | * |
5162 | | * @param[out] ps_cfg |
5163 | | * Pointer to config structure to be updated |
5164 | | * |
5165 | | * @returns error status |
5166 | | * |
5167 | | * @remarks none |
5168 | | * |
5169 | | ******************************************************************************* |
5170 | | */ |
5171 | | static IV_STATUS_T ih264e_set_dimensions(void *pv_api_ip, |
5172 | | void *pv_api_op, |
5173 | | cfg_params_t *ps_cfg) |
5174 | 3.77k | { |
5175 | | /* ctrl call I/O structures */ |
5176 | 3.77k | ih264e_ctl_set_dimensions_ip_t *ps_ip = pv_api_ip; |
5177 | 3.77k | ih264e_ctl_set_dimensions_op_t *ps_op = pv_api_op; |
5178 | | |
5179 | 3.77k | ps_op->s_ive_op.u4_error_code = 0; |
5180 | | |
5181 | 3.77k | ps_cfg->u4_wd = ALIGN16(ps_ip->s_ive_ip.u4_wd); |
5182 | 3.77k | ps_cfg->u4_ht = ALIGN16(ps_ip->s_ive_ip.u4_ht); |
5183 | 3.77k | ps_cfg->i4_wd_mbs = ps_cfg->u4_wd >> 4; |
5184 | 3.77k | ps_cfg->i4_ht_mbs = ps_cfg->u4_ht >> 4; |
5185 | 3.77k | ps_cfg->u4_disp_wd = ps_ip->s_ive_ip.u4_wd; |
5186 | 3.77k | ps_cfg->u4_disp_ht = ps_ip->s_ive_ip.u4_ht; |
5187 | | |
5188 | 3.77k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5189 | 3.77k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5190 | | |
5191 | 3.77k | return IV_SUCCESS; |
5192 | 3.77k | } |
5193 | | |
5194 | | /** |
5195 | | ******************************************************************************* |
5196 | | * |
5197 | | * @brief |
5198 | | * Sets source and target frame rates |
5199 | | * |
5200 | | * @par Description: |
5201 | | * Sets source and target frame rates |
5202 | | * |
5203 | | * @param[in] pv_api_ip |
5204 | | * Pointer to input argument structure |
5205 | | * |
5206 | | * @param[out] pv_api_op |
5207 | | * Pointer to output argument structure |
5208 | | * |
5209 | | * @param[out] ps_cfg |
5210 | | * Pointer to config structure to be updated |
5211 | | * |
5212 | | * @returns error status |
5213 | | * |
5214 | | * @remarks none |
5215 | | * |
5216 | | ******************************************************************************* |
5217 | | */ |
5218 | | static IV_STATUS_T ih264e_set_frame_rate(void *pv_api_ip, |
5219 | | void *pv_api_op, |
5220 | | cfg_params_t *ps_cfg) |
5221 | 2.24k | { |
5222 | | /* ctrl call I/O structures */ |
5223 | 2.24k | ih264e_ctl_set_frame_rate_ip_t *ps_ip = pv_api_ip; |
5224 | 2.24k | ih264e_ctl_set_frame_rate_op_t *ps_op = pv_api_op; |
5225 | | |
5226 | 2.24k | ps_op->s_ive_op.u4_error_code = 0; |
5227 | | |
5228 | 2.24k | ps_cfg->u4_src_frame_rate = ps_ip->s_ive_ip.u4_src_frame_rate; |
5229 | 2.24k | ps_cfg->u4_tgt_frame_rate = ps_ip->s_ive_ip.u4_tgt_frame_rate; |
5230 | | |
5231 | 2.24k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5232 | 2.24k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5233 | | |
5234 | 2.24k | return IV_SUCCESS; |
5235 | 2.24k | } |
5236 | | |
5237 | | /** |
5238 | | ******************************************************************************* |
5239 | | * |
5240 | | * @brief |
5241 | | * Sets target bit rate |
5242 | | * |
5243 | | * @par Description: |
5244 | | * Sets target bit rate |
5245 | | * |
5246 | | * @param[in] pv_api_ip |
5247 | | * Pointer to input argument structure |
5248 | | * |
5249 | | * @param[out] pv_api_op |
5250 | | * Pointer to output argument structure |
5251 | | * |
5252 | | * @param[out] ps_cfg |
5253 | | * Pointer to config structure to be updated |
5254 | | * |
5255 | | * @returns error status |
5256 | | * |
5257 | | * @remarks none |
5258 | | * |
5259 | | ******************************************************************************* |
5260 | | */ |
5261 | | static IV_STATUS_T ih264e_set_bit_rate(void *pv_api_ip, |
5262 | | void *pv_api_op, |
5263 | | cfg_params_t *ps_cfg) |
5264 | 4.47k | { |
5265 | | /* ctrl call I/O structures */ |
5266 | 4.47k | ih264e_ctl_set_bitrate_ip_t *ps_ip = pv_api_ip; |
5267 | 4.47k | ih264e_ctl_set_bitrate_op_t *ps_op = pv_api_op; |
5268 | | |
5269 | 4.47k | ps_op->s_ive_op.u4_error_code = 0; |
5270 | | |
5271 | 4.47k | ps_cfg->u4_target_bitrate = ps_ip->s_ive_ip.u4_target_bitrate; |
5272 | | |
5273 | 4.47k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5274 | 4.47k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5275 | | |
5276 | 4.47k | return IV_SUCCESS; |
5277 | 4.47k | } |
5278 | | |
5279 | | /** |
5280 | | ******************************************************************************* |
5281 | | * |
5282 | | * @brief |
5283 | | * Sets frame type |
5284 | | * |
5285 | | * @par Description: |
5286 | | * Sets frame type |
5287 | | * |
5288 | | * @param[in] pv_api_ip |
5289 | | * Pointer to input argument structure |
5290 | | * |
5291 | | * @param[out] pv_api_op |
5292 | | * Pointer to output argument structure |
5293 | | * |
5294 | | * @param[out] ps_cfg |
5295 | | * Pointer to config structure to be updated |
5296 | | * |
5297 | | * @returns error status |
5298 | | * |
5299 | | * @remarks not a sticky tag |
5300 | | * |
5301 | | ******************************************************************************* |
5302 | | */ |
5303 | | static IV_STATUS_T ih264e_set_frame_type(void *pv_api_ip, |
5304 | | void *pv_api_op, |
5305 | | cfg_params_t *ps_cfg) |
5306 | 937 | { |
5307 | | /* ctrl call I/O structures */ |
5308 | 937 | ih264e_ctl_set_frame_type_ip_t *ps_ip = pv_api_ip; |
5309 | 937 | ih264e_ctl_set_frame_type_op_t *ps_op = pv_api_op; |
5310 | | |
5311 | 937 | ps_op->s_ive_op.u4_error_code = 0; |
5312 | | |
5313 | 937 | ps_cfg->e_frame_type = ps_ip->s_ive_ip.e_frame_type; |
5314 | | |
5315 | 937 | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5316 | 937 | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5317 | | |
5318 | 937 | return IV_SUCCESS; |
5319 | 937 | } |
5320 | | |
5321 | | /** |
5322 | | ******************************************************************************* |
5323 | | * |
5324 | | * @brief |
5325 | | * Sets quantization params |
5326 | | * |
5327 | | * @par Description: |
5328 | | * Sets the max, min and default qp for I frame, P frame and B frame |
5329 | | * |
5330 | | * @param[in] pv_api_ip |
5331 | | * Pointer to input argument structure |
5332 | | * |
5333 | | * @param[out] pv_api_op |
5334 | | * Pointer to output argument structure |
5335 | | * |
5336 | | * @param[out] ps_cfg |
5337 | | * Pointer to config structure to be updated |
5338 | | * |
5339 | | * @returns error status |
5340 | | * |
5341 | | * @remarks none |
5342 | | * |
5343 | | ******************************************************************************* |
5344 | | */ |
5345 | | static IV_STATUS_T ih264e_set_qp(void *pv_api_ip, |
5346 | | void *pv_api_op, |
5347 | | cfg_params_t *ps_cfg) |
5348 | 3.90k | { |
5349 | | /* ctrl call I/O structures */ |
5350 | 3.90k | ih264e_ctl_set_qp_ip_t *ps_set_qp_ip = pv_api_ip; |
5351 | 3.90k | ih264e_ctl_set_qp_op_t *ps_set_qp_op = pv_api_op; |
5352 | | |
5353 | 3.90k | ps_set_qp_op->s_ive_op.u4_error_code = 0; |
5354 | | |
5355 | 3.90k | ps_cfg->u4_i_qp_max = ps_set_qp_ip->s_ive_ip.u4_i_qp_max; |
5356 | 3.90k | ps_cfg->u4_i_qp_min = ps_set_qp_ip->s_ive_ip.u4_i_qp_min; |
5357 | 3.90k | ps_cfg->u4_i_qp = ps_set_qp_ip->s_ive_ip.u4_i_qp; |
5358 | 3.90k | ps_cfg->u4_p_qp_max = ps_set_qp_ip->s_ive_ip.u4_p_qp_max; |
5359 | 3.90k | ps_cfg->u4_p_qp_min = ps_set_qp_ip->s_ive_ip.u4_p_qp_min; |
5360 | 3.90k | ps_cfg->u4_p_qp = ps_set_qp_ip->s_ive_ip.u4_p_qp; |
5361 | 3.90k | ps_cfg->u4_b_qp_max = ps_set_qp_ip->s_ive_ip.u4_b_qp_max; |
5362 | 3.90k | ps_cfg->u4_b_qp_min = ps_set_qp_ip->s_ive_ip.u4_b_qp_min; |
5363 | 3.90k | ps_cfg->u4_b_qp = ps_set_qp_ip->s_ive_ip.u4_b_qp; |
5364 | | |
5365 | 3.90k | ps_cfg->u4_timestamp_high = ps_set_qp_ip->s_ive_ip.u4_timestamp_high; |
5366 | 3.90k | ps_cfg->u4_timestamp_low = ps_set_qp_ip->s_ive_ip.u4_timestamp_low; |
5367 | | |
5368 | 3.90k | return IV_SUCCESS; |
5369 | 3.90k | } |
5370 | | |
5371 | | /** |
5372 | | ******************************************************************************* |
5373 | | * |
5374 | | * @brief |
5375 | | * Sets encoding mode |
5376 | | * |
5377 | | * @par Description: |
5378 | | * Sets encoding mode |
5379 | | * |
5380 | | * @param[in] pv_api_ip |
5381 | | * Pointer to input argument structure |
5382 | | * |
5383 | | * @param[out] pv_api_op |
5384 | | * Pointer to output argument structure |
5385 | | * |
5386 | | * @param[out] ps_cfg |
5387 | | * Pointer to config structure to be updated |
5388 | | * |
5389 | | * @returns error status |
5390 | | * |
5391 | | * @remarks none |
5392 | | * |
5393 | | ******************************************************************************* |
5394 | | */ |
5395 | | static IV_STATUS_T ih264e_set_enc_mode(void *pv_api_ip, |
5396 | | void *pv_api_op, |
5397 | | cfg_params_t *ps_cfg) |
5398 | 3.90k | { |
5399 | | /* ctrl call I/O structures */ |
5400 | 3.90k | ih264e_ctl_set_enc_mode_ip_t *ps_ip = pv_api_ip; |
5401 | 3.90k | ih264e_ctl_set_enc_mode_op_t *ps_op = pv_api_op; |
5402 | | |
5403 | 3.90k | ps_op->s_ive_op.u4_error_code = 0; |
5404 | | |
5405 | 3.90k | ps_cfg->e_enc_mode = ps_ip->s_ive_ip.e_enc_mode; |
5406 | | |
5407 | 3.90k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5408 | 3.90k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5409 | | |
5410 | 3.90k | return IV_SUCCESS; |
5411 | 3.90k | } |
5412 | | |
5413 | | /** |
5414 | | ******************************************************************************* |
5415 | | * |
5416 | | * @brief |
5417 | | * Sets vbv parameters |
5418 | | * |
5419 | | * @par Description: |
5420 | | * Sets vbv parameters |
5421 | | * |
5422 | | * @param[in] pv_api_ip |
5423 | | * Pointer to input argument structure |
5424 | | * |
5425 | | * @param[out] pv_api_op |
5426 | | * Pointer to output argument structure |
5427 | | * |
5428 | | * @param[out] ps_cfg |
5429 | | * Pointer to config structure to be updated |
5430 | | * |
5431 | | * @returns error status |
5432 | | * |
5433 | | * @remarks none |
5434 | | * |
5435 | | ******************************************************************************* |
5436 | | */ |
5437 | | static IV_STATUS_T ih264e_set_vbv_params(void *pv_api_ip, |
5438 | | void *pv_api_op, |
5439 | | cfg_params_t *ps_cfg) |
5440 | 3.90k | { |
5441 | | /* ctrl call I/O structures */ |
5442 | 3.90k | ih264e_ctl_set_vbv_params_ip_t *ps_ip = pv_api_ip; |
5443 | 3.90k | ih264e_ctl_set_vbv_params_op_t *ps_op = pv_api_op; |
5444 | | |
5445 | 3.90k | ps_op->s_ive_op.u4_error_code = 0; |
5446 | | |
5447 | 3.90k | ps_cfg->u4_vbv_buf_size = ps_ip->s_ive_ip.u4_vbv_buf_size; |
5448 | 3.90k | ps_cfg->u4_vbv_buffer_delay = ps_ip->s_ive_ip.u4_vbv_buffer_delay; |
5449 | | |
5450 | 3.90k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5451 | 3.90k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5452 | | |
5453 | 3.90k | return IV_SUCCESS; |
5454 | 3.90k | } |
5455 | | |
5456 | | /** |
5457 | | ******************************************************************************* |
5458 | | * |
5459 | | * @brief |
5460 | | * Sets AIR parameters |
5461 | | * |
5462 | | * @par Description: |
5463 | | * Sets AIR parameters |
5464 | | * |
5465 | | * @param[in] pv_api_ip |
5466 | | * Pointer to input argument structure |
5467 | | * |
5468 | | * @param[out] pv_api_op |
5469 | | * Pointer to output argument structure |
5470 | | * |
5471 | | * @param[out] ps_cfg |
5472 | | * Pointer to config structure to be updated |
5473 | | * |
5474 | | * @returns error status |
5475 | | * |
5476 | | * @remarks none |
5477 | | * |
5478 | | ******************************************************************************* |
5479 | | */ |
5480 | | static IV_STATUS_T ih264_set_air_params(void *pv_api_ip, |
5481 | | void *pv_api_op, |
5482 | | cfg_params_t *ps_cfg) |
5483 | 3.90k | { |
5484 | | /* ctrl call I/O structures */ |
5485 | 3.90k | ih264e_ctl_set_air_params_ip_t *ps_ip = pv_api_ip; |
5486 | 3.90k | ih264e_ctl_set_air_params_op_t *ps_op = pv_api_op; |
5487 | | |
5488 | 3.90k | ps_op->s_ive_op.u4_error_code = 0; |
5489 | | |
5490 | 3.90k | ps_cfg->e_air_mode = ps_ip->s_ive_ip.e_air_mode; |
5491 | 3.90k | ps_cfg->u4_air_refresh_period = ps_ip->s_ive_ip.u4_air_refresh_period; |
5492 | | |
5493 | 3.90k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5494 | 3.90k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5495 | | |
5496 | 3.90k | return IV_SUCCESS; |
5497 | 3.90k | } |
5498 | | |
5499 | | /** |
5500 | | ******************************************************************************* |
5501 | | * |
5502 | | * @brief |
5503 | | * Sets motion estimation parameters |
5504 | | * |
5505 | | * @par Description: |
5506 | | * Sets motion estimation parameters |
5507 | | * |
5508 | | * @param[in] pv_api_ip |
5509 | | * Pointer to input argument structure |
5510 | | * |
5511 | | * @param[out] pv_api_op |
5512 | | * Pointer to output argument structure |
5513 | | * |
5514 | | * @param[out] ps_cfg |
5515 | | * Pointer to config structure to be updated |
5516 | | * |
5517 | | * @returns error status |
5518 | | * |
5519 | | * @remarks none |
5520 | | * |
5521 | | ******************************************************************************* |
5522 | | */ |
5523 | | static IV_STATUS_T ih264_set_me_params(void *pv_api_ip, |
5524 | | void *pv_api_op, |
5525 | | cfg_params_t *ps_cfg) |
5526 | 1.05k | { |
5527 | | /* ctrl call I/O structures */ |
5528 | 1.05k | ih264e_ctl_set_me_params_ip_t *ps_ip = pv_api_ip; |
5529 | 1.05k | ih264e_ctl_set_me_params_op_t *ps_op = pv_api_op; |
5530 | | |
5531 | 1.05k | ps_op->s_ive_op.u4_error_code = 0; |
5532 | | |
5533 | 1.05k | ps_cfg->u4_enable_hpel = ps_ip->s_ive_ip.u4_enable_hpel; |
5534 | 1.05k | ps_cfg->u4_enable_qpel = ps_ip->s_ive_ip.u4_enable_qpel; |
5535 | 1.05k | ps_cfg->u4_enable_fast_sad = ps_ip->s_ive_ip.u4_enable_fast_sad; |
5536 | 1.05k | ps_cfg->u4_enable_alt_ref = ps_ip->s_ive_ip.u4_enable_alt_ref; |
5537 | 1.05k | ps_cfg->u4_srch_rng_x = ps_ip->s_ive_ip.u4_srch_rng_x; |
5538 | 1.05k | ps_cfg->u4_srch_rng_y = ps_ip->s_ive_ip.u4_srch_rng_y; |
5539 | 1.05k | ps_cfg->u4_me_speed_preset = ps_ip->s_ive_ip.u4_me_speed_preset; |
5540 | | |
5541 | 1.05k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5542 | 1.05k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5543 | | |
5544 | 1.05k | return IV_SUCCESS; |
5545 | 1.05k | } |
5546 | | |
5547 | | /** |
5548 | | ******************************************************************************* |
5549 | | * |
5550 | | * @brief |
5551 | | * Sets Intra/Inter Prediction estimation parameters |
5552 | | * |
5553 | | * @par Description: |
5554 | | * Sets Intra/Inter Prediction estimation parameters |
5555 | | * |
5556 | | * @param[in] pv_api_ip |
5557 | | * Pointer to input argument structure |
5558 | | * |
5559 | | * @param[out] pv_api_op |
5560 | | * Pointer to output argument structure |
5561 | | * |
5562 | | * @param[out] ps_cfg |
5563 | | * Pointer to config structure to be updated |
5564 | | * |
5565 | | * @returns error status |
5566 | | * |
5567 | | * @remarks none |
5568 | | * |
5569 | | ******************************************************************************* |
5570 | | */ |
5571 | | static IV_STATUS_T ih264_set_ipe_params(void *pv_api_ip, |
5572 | | void *pv_api_op, |
5573 | | cfg_params_t *ps_cfg) |
5574 | 3.90k | { |
5575 | | /* ctrl call I/O structures */ |
5576 | 3.90k | ih264e_ctl_set_ipe_params_ip_t *ps_ip = pv_api_ip; |
5577 | 3.90k | ih264e_ctl_set_ipe_params_op_t *ps_op = pv_api_op; |
5578 | | |
5579 | 3.90k | ps_op->s_ive_op.u4_error_code = 0; |
5580 | | |
5581 | 3.90k | ps_cfg->u4_enable_intra_4x4 = ps_ip->s_ive_ip.u4_enable_intra_4x4; |
5582 | 3.90k | ps_cfg->u4_enc_speed_preset = ps_ip->s_ive_ip.u4_enc_speed_preset; |
5583 | 3.90k | ps_cfg->u4_constrained_intra_pred = ps_ip->s_ive_ip.u4_constrained_intra_pred; |
5584 | | |
5585 | 3.90k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5586 | 3.90k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5587 | | |
5588 | 3.90k | return IV_SUCCESS; |
5589 | 3.90k | } |
5590 | | |
5591 | | /** |
5592 | | ******************************************************************************* |
5593 | | * |
5594 | | * @brief |
5595 | | * Sets GOP parameters |
5596 | | * |
5597 | | * @par Description: |
5598 | | * Sets GOP parameters |
5599 | | * |
5600 | | * @param[in] pv_api_ip |
5601 | | * Pointer to input argument structure |
5602 | | * |
5603 | | * @param[out] pv_api_op |
5604 | | * Pointer to output argument structure |
5605 | | * |
5606 | | * @param[out] ps_cfg |
5607 | | * Pointer to config structure to be updated |
5608 | | * |
5609 | | * @returns error status |
5610 | | * |
5611 | | * @remarks none |
5612 | | * |
5613 | | ******************************************************************************* |
5614 | | */ |
5615 | | static IV_STATUS_T ih264_set_gop_params(void *pv_api_ip, |
5616 | | void *pv_api_op, |
5617 | | cfg_params_t *ps_cfg) |
5618 | 3.17k | { |
5619 | | /* ctrl call I/O structures */ |
5620 | 3.17k | ih264e_ctl_set_gop_params_ip_t *ps_ip = pv_api_ip; |
5621 | 3.17k | ih264e_ctl_set_gop_params_op_t *ps_op = pv_api_op; |
5622 | | |
5623 | 3.17k | ps_op->s_ive_op.u4_error_code = 0; |
5624 | | |
5625 | 3.17k | ps_cfg->u4_i_frm_interval = ps_ip->s_ive_ip.u4_i_frm_interval; |
5626 | 3.17k | ps_cfg->u4_idr_frm_interval = ps_ip->s_ive_ip.u4_idr_frm_interval; |
5627 | 3.17k | if (ps_cfg->u4_idr_frm_interval < ps_cfg->u4_i_frm_interval) |
5628 | 1.36k | ps_cfg->u4_i_frm_interval = ps_cfg->u4_idr_frm_interval; |
5629 | | |
5630 | 3.17k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5631 | 3.17k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5632 | | |
5633 | 3.17k | return IV_SUCCESS; |
5634 | 3.17k | } |
5635 | | |
5636 | | /** |
5637 | | ******************************************************************************* |
5638 | | * |
5639 | | * @brief |
5640 | | * Sets profile parameters |
5641 | | * |
5642 | | * @par Description: |
5643 | | * Sets profile parameters |
5644 | | * |
5645 | | * @param[in] pv_api_ip |
5646 | | * Pointer to input argument structure |
5647 | | * |
5648 | | * @param[out] pv_api_op |
5649 | | * Pointer to output argument structure |
5650 | | * |
5651 | | * @param[out] ps_cfg |
5652 | | * Pointer to config structure to be updated |
5653 | | * |
5654 | | * @returns error status |
5655 | | * |
5656 | | * @remarks none |
5657 | | * |
5658 | | ******************************************************************************* |
5659 | | */ |
5660 | | static IV_STATUS_T ih264_set_profile_params(void *pv_api_ip, |
5661 | | void *pv_api_op, |
5662 | | cfg_params_t *ps_cfg) |
5663 | 3.90k | { |
5664 | | /* ctrl call I/O structures */ |
5665 | 3.90k | ih264e_ctl_set_profile_params_ip_t *ps_ip = pv_api_ip; |
5666 | 3.90k | ih264e_ctl_set_profile_params_op_t *ps_op = pv_api_op; |
5667 | | |
5668 | 3.90k | ps_op->s_ive_op.u4_error_code = 0; |
5669 | | |
5670 | 3.90k | ps_cfg->e_profile = ps_ip->s_ive_ip.e_profile; |
5671 | 3.90k | ps_cfg->u4_entropy_coding_mode = ps_ip->s_ive_ip.u4_entropy_coding_mode; |
5672 | | |
5673 | 3.90k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5674 | 3.90k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5675 | | |
5676 | 3.90k | return IV_SUCCESS; |
5677 | 3.90k | } |
5678 | | |
5679 | | /** |
5680 | | ******************************************************************************* |
5681 | | * |
5682 | | * @brief |
5683 | | * Sets disable deblock level |
5684 | | * |
5685 | | * @par Description: |
5686 | | * Sets disable deblock level. Level 0 means no disabling and level 4 means |
5687 | | * disable completely. 1, 2, 3 are intermediate levels that control amount |
5688 | | * of deblocking done. |
5689 | | * |
5690 | | * @param[in] ps_codec_obj |
5691 | | * Pointer to codec object at API level |
5692 | | * |
5693 | | * @param[in] pv_api_ip |
5694 | | * Pointer to input argument structure |
5695 | | * |
5696 | | * @param[out] pv_api_op |
5697 | | * Pointer to output argument structure |
5698 | | * |
5699 | | * @returns error status |
5700 | | * |
5701 | | * @remarks none |
5702 | | * |
5703 | | ******************************************************************************* |
5704 | | */ |
5705 | | static WORD32 ih264_set_deblock_params(void *pv_api_ip, |
5706 | | void *pv_api_op, |
5707 | | cfg_params_t *ps_cfg) |
5708 | 3.23k | { |
5709 | | /* ctrl call I/O structures */ |
5710 | 3.23k | ih264e_ctl_set_deblock_params_ip_t *ps_ip = pv_api_ip; |
5711 | 3.23k | ih264e_ctl_set_deblock_params_op_t *ps_op = pv_api_op; |
5712 | | |
5713 | 3.23k | ps_op->s_ive_op.u4_error_code = 0; |
5714 | | |
5715 | 3.23k | ps_cfg->u4_disable_deblock_level = ps_ip->s_ive_ip.u4_disable_deblock_level; |
5716 | | |
5717 | 3.23k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
5718 | 3.23k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
5719 | | |
5720 | 3.23k | return IV_SUCCESS; |
5721 | 3.23k | } |
5722 | | /** |
5723 | | ******************************************************************************* |
5724 | | * |
5725 | | * @brief |
5726 | | * Sets vui params |
5727 | | * |
5728 | | * @par Description: |
5729 | | * Video usability information |
5730 | | * |
5731 | | * @param[in] pv_api_ip |
5732 | | * Pointer to input argument structure |
5733 | | * |
5734 | | * @param[out] pv_api_op |
5735 | | * Pointer to output argument structure |
5736 | | * |
5737 | | * @param[out] ps_cfg |
5738 | | * Pointer to config structure to be updated |
5739 | | * |
5740 | | * @returns error status |
5741 | | * |
5742 | | * @remarks none |
5743 | | * |
5744 | | ******************************************************************************* |
5745 | | */ |
5746 | | static WORD32 ih264e_set_vui_params(void *pv_api_ip, |
5747 | | void *pv_api_op, |
5748 | | cfg_params_t *ps_cfg) |
5749 | 3.90k | { |
5750 | | /* ctrl call I/O structures */ |
5751 | 3.90k | ih264e_vui_ip_t *ps_ip = pv_api_ip; |
5752 | 3.90k | ih264e_vui_op_t *ps_op = pv_api_op; |
5753 | 3.90k | vui_t *ps_vui = &ps_cfg->s_vui; |
5754 | | |
5755 | 3.90k | ps_op->u4_error_code = 0; |
5756 | | |
5757 | 3.90k | ps_vui->u1_aspect_ratio_info_present_flag = ps_ip->u1_aspect_ratio_info_present_flag; |
5758 | 3.90k | ps_vui->u1_aspect_ratio_idc = ps_ip->u1_aspect_ratio_idc; |
5759 | 3.90k | ps_vui->u2_sar_width = ps_ip->u2_sar_width; |
5760 | 3.90k | ps_vui->u2_sar_height = ps_ip->u2_sar_height; |
5761 | 3.90k | ps_vui->u1_overscan_info_present_flag = ps_ip->u1_overscan_info_present_flag; |
5762 | 3.90k | ps_vui->u1_overscan_appropriate_flag = ps_ip->u1_overscan_appropriate_flag; |
5763 | 3.90k | ps_vui->u1_video_signal_type_present_flag = ps_ip->u1_video_signal_type_present_flag; |
5764 | 3.90k | ps_vui->u1_video_format = ps_ip->u1_video_format; |
5765 | 3.90k | ps_vui->u1_video_full_range_flag = ps_ip->u1_video_full_range_flag; |
5766 | 3.90k | ps_vui->u1_colour_description_present_flag = ps_ip->u1_colour_description_present_flag; |
5767 | 3.90k | ps_vui->u1_colour_primaries = ps_ip->u1_colour_primaries; |
5768 | 3.90k | ps_vui->u1_transfer_characteristics = ps_ip->u1_transfer_characteristics; |
5769 | 3.90k | ps_vui->u1_matrix_coefficients = ps_ip->u1_matrix_coefficients; |
5770 | 3.90k | ps_vui->u1_chroma_loc_info_present_flag = ps_ip->u1_chroma_loc_info_present_flag; |
5771 | 3.90k | ps_vui->u1_chroma_sample_loc_type_top_field = ps_ip->u1_chroma_sample_loc_type_top_field; |
5772 | 3.90k | ps_vui->u1_chroma_sample_loc_type_bottom_field = ps_ip->u1_chroma_sample_loc_type_bottom_field; |
5773 | 3.90k | ps_vui->u1_vui_timing_info_present_flag = ps_ip->u1_vui_timing_info_present_flag; |
5774 | 3.90k | ps_vui->u4_vui_num_units_in_tick = ps_ip->u4_vui_num_units_in_tick; |
5775 | 3.90k | ps_vui->u4_vui_time_scale = ps_ip->u4_vui_time_scale; |
5776 | 3.90k | ps_vui->u1_fixed_frame_rate_flag = ps_ip->u1_fixed_frame_rate_flag; |
5777 | 3.90k | ps_vui->u1_nal_hrd_parameters_present_flag = ps_ip->u1_nal_hrd_parameters_present_flag; |
5778 | 3.90k | ps_vui->u1_vcl_hrd_parameters_present_flag = ps_ip->u1_vcl_hrd_parameters_present_flag; |
5779 | 3.90k | ps_vui->u1_low_delay_hrd_flag = ps_ip->u1_low_delay_hrd_flag; |
5780 | 3.90k | ps_vui->u1_pic_struct_present_flag = ps_ip->u1_pic_struct_present_flag; |
5781 | 3.90k | ps_vui->u1_bitstream_restriction_flag = ps_ip->u1_bitstream_restriction_flag; |
5782 | 3.90k | ps_vui->u1_motion_vectors_over_pic_boundaries_flag = ps_ip->u1_motion_vectors_over_pic_boundaries_flag; |
5783 | 3.90k | ps_vui->u1_max_bytes_per_pic_denom = ps_ip->u1_max_bytes_per_pic_denom; |
5784 | 3.90k | ps_vui->u1_max_bits_per_mb_denom = ps_ip->u1_max_bits_per_mb_denom; |
5785 | 3.90k | ps_vui->u1_log2_max_mv_length_horizontal = ps_ip->u1_log2_max_mv_length_horizontal; |
5786 | 3.90k | ps_vui->u1_log2_max_mv_length_vertical = ps_ip->u1_log2_max_mv_length_vertical; |
5787 | 3.90k | ps_vui->u1_num_reorder_frames = ps_ip->u1_num_reorder_frames; |
5788 | 3.90k | ps_vui->u1_max_dec_frame_buffering = ps_ip->u1_max_dec_frame_buffering; |
5789 | | |
5790 | 3.90k | ps_cfg->u4_timestamp_high = -1; |
5791 | 3.90k | ps_cfg->u4_timestamp_low = -1; |
5792 | | |
5793 | 3.90k | return IV_SUCCESS; |
5794 | 3.90k | } |
5795 | | |
5796 | | /** |
5797 | | ******************************************************************************* |
5798 | | * |
5799 | | * @brief |
5800 | | * Sets Mastering display color volume sei params |
5801 | | * |
5802 | | * @par Description: |
5803 | | * Supplemental enhancement information |
5804 | | * |
5805 | | * @param[in] pv_api_ip |
5806 | | * Pointer to input argument structure |
5807 | | * |
5808 | | * @param[out] pv_api_op |
5809 | | * Pointer to output argument structure |
5810 | | * |
5811 | | * @param[out] ps_cfg |
5812 | | * Pointer to config structure to be updated |
5813 | | * |
5814 | | * @return error status |
5815 | | * |
5816 | | * @remarks none |
5817 | | * |
5818 | | ******************************************************************************* |
5819 | | */ |
5820 | | static WORD32 ih264e_set_sei_mdcv_params(void *pv_api_ip, |
5821 | | void *pv_api_op, |
5822 | | cfg_params_t *ps_cfg) |
5823 | 3.90k | { |
5824 | 3.90k | WORD32 i4_count; |
5825 | | /* ctrl call I/O structures */ |
5826 | 3.90k | ih264e_ctl_set_sei_mdcv_params_ip_t *ps_ip = pv_api_ip; |
5827 | 3.90k | ih264e_ctl_set_sei_mdcv_params_op_t *ps_op = pv_api_op; |
5828 | 3.90k | sei_params_t *ps_sei = &ps_cfg->s_sei; |
5829 | | |
5830 | 3.90k | ps_op->u4_error_code = 0; |
5831 | | |
5832 | 3.90k | ps_sei->u1_sei_mdcv_params_present_flag = ps_ip->u1_sei_mdcv_params_present_flag; |
5833 | 15.6k | for(i4_count = 0; i4_count < NUM_SEI_MDCV_PRIMARIES; i4_count++) |
5834 | 11.7k | { |
5835 | 11.7k | ps_sei->s_sei_mdcv_params.au2_display_primaries_x[i4_count] = |
5836 | 11.7k | ps_ip->au2_display_primaries_x[i4_count]; |
5837 | 11.7k | ps_sei->s_sei_mdcv_params.au2_display_primaries_y[i4_count] = |
5838 | 11.7k | ps_ip->au2_display_primaries_y[i4_count]; |
5839 | 11.7k | } |
5840 | | |
5841 | 3.90k | ps_sei->s_sei_mdcv_params.u2_white_point_x = ps_ip->u2_white_point_x; |
5842 | 3.90k | ps_sei->s_sei_mdcv_params.u2_white_point_y = ps_ip->u2_white_point_y; |
5843 | 3.90k | ps_sei->s_sei_mdcv_params.u4_max_display_mastering_luminance = |
5844 | 3.90k | ps_ip->u4_max_display_mastering_luminance; |
5845 | 3.90k | ps_sei->s_sei_mdcv_params.u4_min_display_mastering_luminance = |
5846 | 3.90k | ps_ip->u4_min_display_mastering_luminance; |
5847 | | |
5848 | 3.90k | ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high; |
5849 | 3.90k | ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low; |
5850 | | |
5851 | 3.90k | return IV_SUCCESS; |
5852 | 3.90k | } |
5853 | | |
5854 | | /** |
5855 | | ******************************************************************************* |
5856 | | * |
5857 | | * @brief |
5858 | | * Sets content light level sei params |
5859 | | * |
5860 | | * @par Description: |
5861 | | * Supplemental enhancement information |
5862 | | * |
5863 | | * @param[in] pv_api_ip |
5864 | | * Pointer to input argument structure |
5865 | | * |
5866 | | * @param[out] pv_api_op |
5867 | | * Pointer to output argument structure |
5868 | | * |
5869 | | * @param[out] ps_cfg |
5870 | | * Pointer to config structure to be updated |
5871 | | * |
5872 | | * @return error status |
5873 | | * |
5874 | | * @remarks none |
5875 | | * |
5876 | | ******************************************************************************* |
5877 | | */ |
5878 | | static WORD32 ih264e_set_sei_cll_params(void *pv_api_ip, |
5879 | | void *pv_api_op, |
5880 | | cfg_params_t *ps_cfg) |
5881 | 3.90k | { |
5882 | | /* ctrl call I/O structures */ |
5883 | 3.90k | ih264e_ctl_set_sei_cll_params_ip_t *ps_ip = pv_api_ip; |
5884 | 3.90k | ih264e_ctl_set_sei_cll_params_op_t *ps_op = pv_api_op; |
5885 | 3.90k | sei_params_t *ps_sei = &ps_cfg->s_sei; |
5886 | | |
5887 | 3.90k | ps_op->u4_error_code = 0; |
5888 | | |
5889 | 3.90k | ps_sei->u1_sei_cll_params_present_flag = ps_ip->u1_sei_cll_params_present_flag; |
5890 | | |
5891 | 3.90k | ps_sei->s_sei_cll_params.u2_max_content_light_level = ps_ip->u2_max_content_light_level; |
5892 | 3.90k | ps_sei->s_sei_cll_params.u2_max_pic_average_light_level = |
5893 | 3.90k | ps_ip->u2_max_pic_average_light_level; |
5894 | | |
5895 | 3.90k | ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high; |
5896 | 3.90k | ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low; |
5897 | | |
5898 | 3.90k | return IV_SUCCESS; |
5899 | 3.90k | } |
5900 | | |
5901 | | /** |
5902 | | ******************************************************************************* |
5903 | | * |
5904 | | * @brief |
5905 | | * Sets ambient viewing environment sei params |
5906 | | * |
5907 | | * @par Description: |
5908 | | * Supplemental enhancement information |
5909 | | * |
5910 | | * @param[in] pv_api_ip |
5911 | | * Pointer to input argument structure |
5912 | | * |
5913 | | * @param[out] pv_api_op |
5914 | | * Pointer to output argument structure |
5915 | | * |
5916 | | * @param[out] ps_cfg |
5917 | | * Pointer to config structure to be updated |
5918 | | * |
5919 | | * @return error status |
5920 | | * |
5921 | | * @remarks none |
5922 | | * |
5923 | | ******************************************************************************* |
5924 | | */ |
5925 | | static WORD32 ih264e_set_sei_ave_params(void *pv_api_ip, |
5926 | | void *pv_api_op, |
5927 | | cfg_params_t *ps_cfg) |
5928 | 3.90k | { |
5929 | | /* ctrl call I/O structures */ |
5930 | 3.90k | ih264e_ctl_set_sei_ave_params_ip_t *ps_ip = pv_api_ip; |
5931 | 3.90k | ih264e_ctl_set_sei_ave_params_op_t *ps_op = pv_api_op; |
5932 | 3.90k | sei_params_t *ps_sei = &ps_cfg->s_sei; |
5933 | | |
5934 | 3.90k | ps_op->u4_error_code = 0; |
5935 | | |
5936 | 3.90k | ps_sei->u1_sei_ave_params_present_flag = ps_ip->u1_sei_ave_params_present_flag; |
5937 | | |
5938 | 3.90k | ps_sei->s_sei_ave_params.u4_ambient_illuminance = ps_ip->u4_ambient_illuminance; |
5939 | 3.90k | ps_sei->s_sei_ave_params.u2_ambient_light_x = ps_ip->u2_ambient_light_x; |
5940 | 3.90k | ps_sei->s_sei_ave_params.u2_ambient_light_y = ps_ip->u2_ambient_light_y; |
5941 | | |
5942 | 3.90k | ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high; |
5943 | 3.90k | ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low; |
5944 | | |
5945 | 3.90k | return IV_SUCCESS; |
5946 | 3.90k | } |
5947 | | |
5948 | | /** |
5949 | | ******************************************************************************* |
5950 | | * |
5951 | | * @brief |
5952 | | * Sets content color volume sei params |
5953 | | * |
5954 | | * @par Description: |
5955 | | * Supplemental enhancement information |
5956 | | * |
5957 | | * @param[in] pv_api_ip |
5958 | | * Pointer to input argument structure |
5959 | | * |
5960 | | * @param[out] pv_api_op |
5961 | | * Pointer to output argument structure |
5962 | | * |
5963 | | * @param[out] ps_cfg |
5964 | | * Pointer to config structure to be updated |
5965 | | * |
5966 | | * @return error status |
5967 | | * |
5968 | | * @remarks none |
5969 | | * |
5970 | | ******************************************************************************* |
5971 | | */ |
5972 | | static WORD32 ih264e_set_sei_ccv_params(void *pv_api_ip, |
5973 | | void *pv_api_op, |
5974 | | cfg_params_t *ps_cfg) |
5975 | 3.90k | { |
5976 | 3.90k | WORD32 i4_count; |
5977 | | /* ctrl call I/O structures */ |
5978 | 3.90k | ih264e_ctl_set_sei_ccv_params_ip_t *ps_ip = pv_api_ip; |
5979 | 3.90k | ih264e_ctl_set_sei_ccv_params_op_t *ps_op = pv_api_op; |
5980 | 3.90k | sei_params_t *ps_sei = &ps_cfg->s_sei; |
5981 | | |
5982 | 3.90k | ps_op->u4_error_code = 0; |
5983 | | |
5984 | 3.90k | ps_sei->u1_sei_ccv_params_present_flag = ps_ip->u1_sei_ccv_params_present_flag; |
5985 | | |
5986 | 3.90k | ps_sei->s_sei_ccv_params.u1_ccv_cancel_flag = ps_ip->u1_ccv_cancel_flag; |
5987 | 3.90k | ps_sei->s_sei_ccv_params.u1_ccv_persistence_flag = ps_ip->u1_ccv_persistence_flag; |
5988 | 3.90k | ps_sei->s_sei_ccv_params.u1_ccv_primaries_present_flag = |
5989 | 3.90k | ps_ip->u1_ccv_primaries_present_flag; |
5990 | 3.90k | ps_sei->s_sei_ccv_params.u1_ccv_min_luminance_value_present_flag = |
5991 | 3.90k | ps_ip->u1_ccv_min_luminance_value_present_flag; |
5992 | 3.90k | ps_sei->s_sei_ccv_params.u1_ccv_max_luminance_value_present_flag = |
5993 | 3.90k | ps_ip->u1_ccv_max_luminance_value_present_flag; |
5994 | 3.90k | ps_sei->s_sei_ccv_params.u1_ccv_avg_luminance_value_present_flag = |
5995 | 3.90k | ps_ip->u1_ccv_avg_luminance_value_present_flag; |
5996 | 3.90k | ps_sei->s_sei_ccv_params.u1_ccv_reserved_zero_2bits = |
5997 | 3.90k | ps_ip->u1_ccv_reserved_zero_2bits; |
5998 | | |
5999 | 15.6k | for(i4_count = 0; i4_count < NUM_SEI_CCV_PRIMARIES; i4_count++) |
6000 | 11.7k | { |
6001 | 11.7k | ps_sei->s_sei_ccv_params.ai4_ccv_primaries_x[i4_count] = |
6002 | 11.7k | ps_ip->ai4_ccv_primaries_x[i4_count]; |
6003 | 11.7k | ps_sei->s_sei_ccv_params.ai4_ccv_primaries_y[i4_count] = |
6004 | 11.7k | ps_ip->ai4_ccv_primaries_y[i4_count]; |
6005 | 11.7k | } |
6006 | | |
6007 | 3.90k | ps_sei->s_sei_ccv_params.u4_ccv_min_luminance_value = ps_ip->u4_ccv_min_luminance_value; |
6008 | 3.90k | ps_sei->s_sei_ccv_params.u4_ccv_max_luminance_value = ps_ip->u4_ccv_max_luminance_value; |
6009 | 3.90k | ps_sei->s_sei_ccv_params.u4_ccv_avg_luminance_value = ps_ip->u4_ccv_avg_luminance_value; |
6010 | | |
6011 | 3.90k | ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high; |
6012 | 3.90k | ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low; |
6013 | | |
6014 | 3.90k | return IV_SUCCESS; |
6015 | 3.90k | } |
6016 | | |
6017 | | /** |
6018 | | ******************************************************************************* |
6019 | | * |
6020 | | * @brief |
6021 | | * Sets shutter interval info sei params |
6022 | | * |
6023 | | * @par Description: |
6024 | | * Supplemental enhancement information |
6025 | | * |
6026 | | * @param[in] pv_api_ip |
6027 | | * Pointer to input argument structure |
6028 | | * |
6029 | | * @param[out] pv_api_op |
6030 | | * Pointer to output argument structure |
6031 | | * |
6032 | | * @param[out] ps_cfg |
6033 | | * Pointer to config structure to be updated |
6034 | | * |
6035 | | * @return error status |
6036 | | * |
6037 | | * @remarks none |
6038 | | * |
6039 | | ******************************************************************************* |
6040 | | */ |
6041 | | static WORD32 ih264e_set_sei_sii_params(void *pv_api_ip, void *pv_api_op, cfg_params_t *ps_cfg) |
6042 | 3.90k | { |
6043 | | /* ctrl call I/O structures */ |
6044 | 3.90k | ih264e_ctl_set_sei_sii_params_ip_t *ps_ip = pv_api_ip; |
6045 | 3.90k | ih264e_ctl_set_sei_sii_params_op_t *ps_op = pv_api_op; |
6046 | 3.90k | sei_params_t *ps_sei = &ps_cfg->s_sei; |
6047 | | |
6048 | 3.90k | ps_op->u4_error_code = 0; |
6049 | 3.90k | ps_sei->u1_sei_sii_params_present_flag = ps_ip->u1_shutter_interval_info_present_flag; |
6050 | 3.90k | ps_sei->s_sei_sii_params.u4_sii_sub_layer_idx = ps_ip->u4_sii_sub_layer_idx; |
6051 | | |
6052 | 3.90k | if(0 == ps_sei->s_sei_sii_params.u4_sii_sub_layer_idx) |
6053 | 3.90k | { |
6054 | 3.90k | ps_sei->s_sei_sii_params.u1_shutter_interval_info_present_flag = |
6055 | 3.90k | ps_ip->u1_shutter_interval_info_present_flag; |
6056 | | |
6057 | 3.90k | if(1 == ps_sei->s_sei_sii_params.u1_shutter_interval_info_present_flag) |
6058 | 1.48k | { |
6059 | 1.48k | ps_sei->s_sei_sii_params.u4_sii_time_scale = ps_ip->u4_sii_time_scale; |
6060 | 1.48k | ps_sei->s_sei_sii_params.u1_fixed_shutter_interval_within_cvs_flag = |
6061 | 1.48k | ps_ip->u1_fixed_shutter_interval_within_cvs_flag; |
6062 | | |
6063 | 1.48k | if(1 == ps_sei->s_sei_sii_params.u1_fixed_shutter_interval_within_cvs_flag) |
6064 | 0 | { |
6065 | 0 | ps_sei->s_sei_sii_params.u4_sii_num_units_in_shutter_interval = |
6066 | 0 | ps_ip->u4_sii_num_units_in_shutter_interval; |
6067 | 0 | } |
6068 | 1.48k | else |
6069 | 1.48k | { |
6070 | 1.48k | int i; |
6071 | 1.48k | ps_sei->s_sei_sii_params.u1_sii_max_sub_layers_minus1 = |
6072 | 1.48k | ps_ip->u1_sii_max_sub_layers_minus1; |
6073 | | |
6074 | 13.3k | for(i = 0; i <= ps_ip->u1_sii_max_sub_layers_minus1; i++) |
6075 | 11.8k | { |
6076 | 11.8k | ps_sei->s_sei_sii_params.au4_sub_layer_num_units_in_shutter_interval[i] = |
6077 | 11.8k | ps_ip->au4_sub_layer_num_units_in_shutter_interval[i]; |
6078 | 11.8k | } |
6079 | 1.48k | } |
6080 | 1.48k | } |
6081 | 3.90k | } |
6082 | | |
6083 | 3.90k | ps_cfg->u4_timestamp_high = ps_ip->u4_timestamp_high; |
6084 | 3.90k | ps_cfg->u4_timestamp_low = ps_ip->u4_timestamp_low; |
6085 | | |
6086 | 3.90k | return IV_SUCCESS; |
6087 | 3.90k | } |
6088 | | |
6089 | | /** |
6090 | | ******************************************************************************* |
6091 | | * |
6092 | | * @brief |
6093 | | * Sets number of cores |
6094 | | * |
6095 | | * @par Description: |
6096 | | * Sets number of cores |
6097 | | * |
6098 | | * @param[in] ps_codec_obj |
6099 | | * Pointer to codec object at API level |
6100 | | * |
6101 | | * @param[in] pv_api_ip |
6102 | | * Pointer to input argument structure |
6103 | | * |
6104 | | * @param[out] pv_api_op |
6105 | | * Pointer to output argument structure |
6106 | | * |
6107 | | * @returns error status |
6108 | | * |
6109 | | * @remarks The number of encoder threads is limited to MAX_PROCESS_THREADS |
6110 | | * |
6111 | | ******************************************************************************* |
6112 | | */ |
6113 | | static WORD32 ih264e_set_num_cores(void *pv_api_ip, |
6114 | | void *pv_api_op, |
6115 | | cfg_params_t *ps_cfg) |
6116 | 3.90k | { |
6117 | | /* ctrl call I/O structures */ |
6118 | 3.90k | ih264e_ctl_set_num_cores_ip_t *ps_ip = pv_api_ip; |
6119 | 3.90k | ih264e_ctl_set_num_cores_op_t *ps_op = pv_api_op; |
6120 | | |
6121 | 3.90k | ps_op->s_ive_op.u4_error_code = 0; |
6122 | | |
6123 | 3.90k | ps_cfg->u4_num_cores = MIN(ps_ip->s_ive_ip.u4_num_cores, MAX_PROCESS_THREADS); |
6124 | | |
6125 | 3.90k | ps_cfg->u4_timestamp_high = ps_ip->s_ive_ip.u4_timestamp_high; |
6126 | 3.90k | ps_cfg->u4_timestamp_low = ps_ip->s_ive_ip.u4_timestamp_low; |
6127 | | |
6128 | 3.90k | return IV_SUCCESS; |
6129 | 3.90k | } |
6130 | | |
6131 | | /** |
6132 | | ******************************************************************************* |
6133 | | * |
6134 | | * @brief |
6135 | | * Resets encoder state |
6136 | | * |
6137 | | * @par Description: |
6138 | | * Resets encoder state by calling ih264e_init() |
6139 | | * |
6140 | | * @param[in] ps_codec_obj |
6141 | | * Pointer to codec object at API level |
6142 | | * |
6143 | | * @param[in] pv_api_ip |
6144 | | * Pointer to input argument structure |
6145 | | * |
6146 | | * @param[out] pv_api_op |
6147 | | * Pointer to output argument structure |
6148 | | * |
6149 | | * @returns error status |
6150 | | * |
6151 | | * @remarks none |
6152 | | * |
6153 | | ******************************************************************************* |
6154 | | */ |
6155 | | static WORD32 ih264e_reset(iv_obj_t *ps_codec_obj, |
6156 | | void *pv_api_ip, |
6157 | | void *pv_api_op) |
6158 | 0 | { |
6159 | | /* codec ctxt */ |
6160 | 0 | codec_t * ps_codec = (codec_t *) (ps_codec_obj->pv_codec_handle); |
6161 | | |
6162 | | /* ctrl call I/O structures */ |
6163 | 0 | ih264e_ctl_reset_op_t *ps_op = pv_api_op; |
6164 | |
|
6165 | 0 | UNUSED(pv_api_ip); |
6166 | |
|
6167 | 0 | ps_op->s_ive_op.u4_error_code = 0; |
6168 | |
|
6169 | 0 | if (ps_codec != NULL) |
6170 | 0 | { |
6171 | 0 | if (ps_codec->s_cfg.u4_keep_threads_active) |
6172 | 0 | { |
6173 | | /* Shutdown active threads before reinitialization */ |
6174 | 0 | ih264e_thread_pool_shutdown(ps_codec); |
6175 | 0 | } |
6176 | 0 | ih264e_init(ps_codec); |
6177 | 0 | } |
6178 | 0 | else |
6179 | 0 | { |
6180 | 0 | ps_op->s_ive_op.u4_error_code = IH264E_INIT_NOT_DONE; |
6181 | 0 | } |
6182 | |
|
6183 | 0 | return IV_SUCCESS; |
6184 | 0 | } |
6185 | | |
6186 | | /** |
6187 | | ******************************************************************************* |
6188 | | * |
6189 | | * @brief |
6190 | | * Codec control call |
6191 | | * |
6192 | | * @par Description: |
6193 | | * Codec control call which in turn calls appropriate calls based on sub-command |
6194 | | * |
6195 | | * @param[in] ps_codec_obj |
6196 | | * Pointer to codec object at API level |
6197 | | * |
6198 | | * @param[in] pv_api_ip |
6199 | | * Pointer to input argument structure |
6200 | | * |
6201 | | * @param[out] pv_api_op |
6202 | | * Pointer to output argument structure |
6203 | | * |
6204 | | * @returns error status |
6205 | | * |
6206 | | * @remarks none |
6207 | | * |
6208 | | ******************************************************************************* |
6209 | | */ |
6210 | | static WORD32 ih264e_ctl(iv_obj_t *ps_codec_obj, |
6211 | | void *pv_api_ip, |
6212 | | void *pv_api_op) |
6213 | 81.3k | { |
6214 | | /* codec ctxt */ |
6215 | 81.3k | codec_t *ps_codec = (codec_t *) ps_codec_obj->pv_codec_handle; |
6216 | | |
6217 | | /* ctrl call I/O structures */ |
6218 | 81.3k | ih264e_ctl_setdefault_ip_t *ps_ctl_ip = pv_api_ip; |
6219 | 81.3k | ih264e_ctl_setdefault_op_t *ps_ctl_op = pv_api_op; |
6220 | | |
6221 | | /* ctrl call sub cmd */ |
6222 | 81.3k | IVE_CONTROL_API_COMMAND_TYPE_T sub_cmd = ps_ctl_ip->s_ive_ip.e_sub_cmd; |
6223 | | |
6224 | | /* error status */ |
6225 | 81.3k | IV_STATUS_T ret = IV_SUCCESS; |
6226 | | |
6227 | | /* temp var */ |
6228 | 81.3k | WORD32 i; |
6229 | 81.3k | cfg_params_t *ps_cfg = NULL; |
6230 | | |
6231 | | /* control call is for configuring encoding params, this is not to be called |
6232 | | * before a successful init call */ |
6233 | 81.3k | if (ps_codec->i4_init_done != 1) |
6234 | 0 | { |
6235 | 0 | ps_ctl_op->s_ive_op.u4_error_code |= 1 << IVE_FATALERROR; |
6236 | 0 | ps_ctl_op->s_ive_op.u4_error_code |= IH264E_INIT_NOT_DONE; |
6237 | 0 | return IV_FAIL; |
6238 | 0 | } |
6239 | | |
6240 | | /* make it thread safe */ |
6241 | 81.3k | ithread_mutex_lock(ps_codec->pv_ctl_mutex); |
6242 | | |
6243 | | /* find a free config param set to hold current parameters */ |
6244 | 701k | for (i = 0; i < MAX_ACTIVE_CONFIG_PARAMS; i++) |
6245 | 701k | { |
6246 | 701k | if (0 == ps_codec->as_cfg[i].u4_is_valid) |
6247 | 81.3k | { |
6248 | 81.3k | ps_cfg = &ps_codec->as_cfg[i]; |
6249 | 81.3k | break; |
6250 | 81.3k | } |
6251 | 701k | } |
6252 | | |
6253 | | /* If all are invalid, then start overwriting from the head config params */ |
6254 | 81.3k | if (NULL == ps_cfg) |
6255 | 0 | { |
6256 | 0 | ps_cfg = &ps_codec->as_cfg[0]; |
6257 | 0 | } |
6258 | | |
6259 | 81.3k | ps_cfg->u4_is_valid = 1; |
6260 | | |
6261 | 81.3k | ps_cfg->e_cmd = sub_cmd; |
6262 | | |
6263 | 81.3k | switch (sub_cmd) |
6264 | 81.3k | { |
6265 | 3.77k | case IVE_CMD_CTL_SET_DIMENSIONS: |
6266 | 3.77k | ret = ih264e_set_dimensions(pv_api_ip, pv_api_op, ps_cfg); |
6267 | 3.77k | break; |
6268 | | |
6269 | 2.24k | case IVE_CMD_CTL_SET_FRAMERATE: |
6270 | 2.24k | ret = ih264e_set_frame_rate(pv_api_ip, pv_api_op, ps_cfg); |
6271 | 2.24k | break; |
6272 | | |
6273 | 4.47k | case IVE_CMD_CTL_SET_BITRATE: |
6274 | 4.47k | ret = ih264e_set_bit_rate(pv_api_ip, pv_api_op, ps_cfg); |
6275 | 4.47k | break; |
6276 | | |
6277 | 937 | case IVE_CMD_CTL_SET_FRAMETYPE: |
6278 | 937 | ret = ih264e_set_frame_type(pv_api_ip, pv_api_op, ps_cfg); |
6279 | 937 | break; |
6280 | | |
6281 | 3.90k | case IVE_CMD_CTL_SET_QP: |
6282 | 3.90k | ret = ih264e_set_qp(pv_api_ip, pv_api_op, ps_cfg); |
6283 | 3.90k | break; |
6284 | | |
6285 | 3.90k | case IVE_CMD_CTL_SET_ENC_MODE: |
6286 | 3.90k | ret = ih264e_set_enc_mode(pv_api_ip, pv_api_op, ps_cfg); |
6287 | 3.90k | break; |
6288 | | |
6289 | 3.90k | case IVE_CMD_CTL_SET_VBV_PARAMS: |
6290 | 3.90k | ret = ih264e_set_vbv_params(pv_api_ip, pv_api_op, ps_cfg); |
6291 | 3.90k | break; |
6292 | | |
6293 | 3.90k | case IVE_CMD_CTL_SET_AIR_PARAMS: |
6294 | 3.90k | ret = ih264_set_air_params(pv_api_ip, pv_api_op, ps_cfg); |
6295 | 3.90k | break; |
6296 | | |
6297 | 1.05k | case IVE_CMD_CTL_SET_ME_PARAMS: |
6298 | 1.05k | ret = ih264_set_me_params(pv_api_ip, pv_api_op, ps_cfg); |
6299 | 1.05k | break; |
6300 | | |
6301 | 3.90k | case IVE_CMD_CTL_SET_IPE_PARAMS: |
6302 | 3.90k | ret = ih264_set_ipe_params(pv_api_ip, pv_api_op, ps_cfg); |
6303 | 3.90k | break; |
6304 | | |
6305 | 3.17k | case IVE_CMD_CTL_SET_GOP_PARAMS: |
6306 | 3.17k | ret = ih264_set_gop_params(pv_api_ip, pv_api_op, ps_cfg); |
6307 | 3.17k | break; |
6308 | | |
6309 | 3.90k | case IVE_CMD_CTL_SET_PROFILE_PARAMS: |
6310 | 3.90k | ret = ih264_set_profile_params(pv_api_ip, pv_api_op, ps_cfg); |
6311 | 3.90k | break; |
6312 | | |
6313 | 3.23k | case IVE_CMD_CTL_SET_DEBLOCK_PARAMS: |
6314 | 3.23k | ret = ih264_set_deblock_params(pv_api_ip, pv_api_op, ps_cfg); |
6315 | 3.23k | break; |
6316 | | |
6317 | 3.90k | case IVE_CMD_CTL_SET_VUI_PARAMS: |
6318 | 3.90k | ret = ih264e_set_vui_params(pv_api_ip, pv_api_op, ps_cfg); |
6319 | 3.90k | break; |
6320 | | |
6321 | 3.90k | case IVE_CMD_CTL_SET_SEI_MDCV_PARAMS: |
6322 | 3.90k | ret = ih264e_set_sei_mdcv_params(pv_api_ip, pv_api_op, ps_cfg); |
6323 | 3.90k | break; |
6324 | | |
6325 | 3.90k | case IVE_CMD_CTL_SET_SEI_CLL_PARAMS: |
6326 | 3.90k | ret = ih264e_set_sei_cll_params(pv_api_ip, pv_api_op, ps_cfg); |
6327 | 3.90k | break; |
6328 | | |
6329 | 3.90k | case IVE_CMD_CTL_SET_SEI_AVE_PARAMS: |
6330 | 3.90k | ret = ih264e_set_sei_ave_params(pv_api_ip, pv_api_op, ps_cfg); |
6331 | 3.90k | break; |
6332 | | |
6333 | 3.90k | case IVE_CMD_CTL_SET_SEI_CCV_PARAMS: |
6334 | 3.90k | ret = ih264e_set_sei_ccv_params(pv_api_ip, pv_api_op, ps_cfg); |
6335 | 3.90k | break; |
6336 | | |
6337 | 3.90k | case IVE_CMD_CTL_SET_SEI_SII_PARAMS: |
6338 | 3.90k | ret = ih264e_set_sei_sii_params(pv_api_ip, pv_api_op, ps_cfg); |
6339 | 3.90k | break; |
6340 | | |
6341 | 0 | case IVE_CMD_CTL_RESET: |
6342 | | |
6343 | | /* invalidate config param struct as it is being served right away */ |
6344 | 0 | ps_codec->as_cfg[i].u4_is_valid = 0; |
6345 | |
|
6346 | 0 | ret = ih264e_reset(ps_codec_obj, pv_api_ip, pv_api_op); |
6347 | 0 | break; |
6348 | | |
6349 | 3.90k | case IVE_CMD_CTL_SETDEFAULT: |
6350 | 3.90k | { |
6351 | | /* ctrl call I/O structures */ |
6352 | 3.90k | ih264e_ctl_setdefault_op_t *ps_op = pv_api_op; |
6353 | | |
6354 | | /* invalidate config param struct as it is being served right away */ |
6355 | 3.90k | ps_codec->as_cfg[i].u4_is_valid = 0; |
6356 | | |
6357 | | /* error status */ |
6358 | 3.90k | ret = ih264e_set_default_params(ps_cfg); |
6359 | | |
6360 | 3.90k | ps_op->s_ive_op.u4_error_code = ret; |
6361 | | |
6362 | 3.90k | break; |
6363 | 0 | } |
6364 | | |
6365 | 0 | case IVE_CMD_CTL_FLUSH: |
6366 | | |
6367 | | /* invalidate config param struct as it is being served right away */ |
6368 | 0 | ps_codec->as_cfg[i].u4_is_valid = 0; |
6369 | |
|
6370 | 0 | ret = ih264e_set_flush_mode(ps_codec_obj, pv_api_ip, pv_api_op); |
6371 | 0 | break; |
6372 | | |
6373 | 3.84k | case IVE_CMD_CTL_GETBUFINFO: |
6374 | | |
6375 | | /* invalidate config param struct as it is being served right away */ |
6376 | 3.84k | ps_codec->as_cfg[i].u4_is_valid = 0; |
6377 | | |
6378 | 3.84k | ret = ih264e_get_buf_info(ps_codec_obj, pv_api_ip, pv_api_op); |
6379 | 3.84k | break; |
6380 | | |
6381 | 3.90k | case IVE_CMD_CTL_GETVERSION: |
6382 | 3.90k | { |
6383 | | /* ctrl call I/O structures */ |
6384 | 3.90k | ih264e_ctl_getversioninfo_ip_t *ps_ip = pv_api_ip; |
6385 | 3.90k | ih264e_ctl_getversioninfo_op_t *ps_op = pv_api_op; |
6386 | | |
6387 | | /* invalidate config param struct as it is being served right away */ |
6388 | 3.90k | ps_codec->as_cfg[i].u4_is_valid = 0; |
6389 | | |
6390 | | /* error status */ |
6391 | 3.90k | ps_op->s_ive_op.u4_error_code = IV_SUCCESS; |
6392 | | |
6393 | 3.90k | if (ps_ip->s_ive_ip.u4_version_bufsize <= 0) |
6394 | 0 | { |
6395 | 0 | ps_op->s_ive_op.u4_error_code = |
6396 | 0 | IH264E_CXA_VERS_BUF_INSUFFICIENT; |
6397 | 0 | ret = IV_FAIL; |
6398 | 0 | } |
6399 | 3.90k | else |
6400 | 3.90k | { |
6401 | 3.90k | ret = ih264e_get_version((CHAR *) ps_ip->s_ive_ip.pu1_version, |
6402 | 3.90k | ps_ip->s_ive_ip.u4_version_bufsize); |
6403 | | |
6404 | 3.90k | if (ret != IV_SUCCESS) |
6405 | 0 | { |
6406 | 0 | ps_op->s_ive_op.u4_error_code = |
6407 | 0 | IH264E_CXA_VERS_BUF_INSUFFICIENT; |
6408 | 0 | ret = IV_FAIL; |
6409 | 0 | } |
6410 | 3.90k | } |
6411 | 3.90k | break; |
6412 | 0 | } |
6413 | | |
6414 | 3.90k | case IVE_CMD_CTL_SET_NUM_CORES: |
6415 | 3.90k | ret = ih264e_set_num_cores(pv_api_ip, pv_api_op, ps_cfg); |
6416 | 3.90k | break; |
6417 | | |
6418 | 0 | default: |
6419 | | /* invalidate config param struct as it is being served right away */ |
6420 | 0 | ps_codec->as_cfg[i].u4_is_valid = 0; |
6421 | |
|
6422 | 0 | DEBUG("Warning !! unrecognized control api command \n"); |
6423 | 0 | break; |
6424 | 81.3k | } |
6425 | | |
6426 | 81.3k | ithread_mutex_unlock(ps_codec->pv_ctl_mutex); |
6427 | | |
6428 | 81.3k | return ret; |
6429 | 81.3k | } |
6430 | | |
6431 | | /** |
6432 | | ******************************************************************************* |
6433 | | * |
6434 | | * @brief |
6435 | | * Codec entry point function. All the function calls to the codec are done |
6436 | | * using this function with different values specified in command |
6437 | | * |
6438 | | * @par Description: |
6439 | | * Arguments are tested for validity and then based on the command |
6440 | | * appropriate function is called |
6441 | | * |
6442 | | * @param[in] ps_handle |
6443 | | * API level handle for codec |
6444 | | * |
6445 | | * @param[in] pv_api_ip |
6446 | | * Input argument structure |
6447 | | * |
6448 | | * @param[out] pv_api_op |
6449 | | * Output argument structure |
6450 | | * |
6451 | | * @returns error_status |
6452 | | * |
6453 | | * @remarks |
6454 | | * |
6455 | | ******************************************************************************* |
6456 | | */ |
6457 | | IV_STATUS_T ih264e_api_function(iv_obj_t *ps_handle, |
6458 | | void *pv_api_ip, |
6459 | | void *pv_api_op) |
6460 | 174k | { |
6461 | | /* api command */ |
6462 | 174k | WORD32 command = IV_CMD_NA; |
6463 | | |
6464 | | /* error status */ |
6465 | 174k | IV_STATUS_T e_status; |
6466 | 174k | WORD32 ret; |
6467 | | |
6468 | | /* tmp var */ |
6469 | 174k | WORD32 *pu4_ptr_cmd = (WORD32 *) pv_api_ip; |
6470 | | |
6471 | | /* validate input / output structures */ |
6472 | 174k | e_status = api_check_struct_sanity(ps_handle, pv_api_ip, pv_api_op); |
6473 | | |
6474 | 174k | if (e_status != IV_SUCCESS) |
6475 | 7.30k | { |
6476 | 7.30k | DEBUG("error code = %d\n", *((UWORD32 *)pv_api_op + 1)); |
6477 | 7.30k | return IV_FAIL; |
6478 | 7.30k | } |
6479 | | |
6480 | 166k | pu4_ptr_cmd++; |
6481 | | |
6482 | 166k | command = *pu4_ptr_cmd; |
6483 | | |
6484 | 166k | switch (command) |
6485 | 166k | { |
6486 | 3.92k | case IV_CMD_GET_NUM_MEM_REC: |
6487 | 3.92k | ret = ih264e_get_num_rec(pv_api_ip, pv_api_op); |
6488 | 3.92k | break; |
6489 | | |
6490 | 7.82k | case IV_CMD_FILL_NUM_MEM_REC: |
6491 | 7.82k | ret = ih264e_fill_num_mem_rec(pv_api_ip, pv_api_op); |
6492 | 7.82k | break; |
6493 | | |
6494 | 3.90k | case IV_CMD_INIT: |
6495 | 3.90k | ret = ih264e_init_mem_rec(ps_handle, pv_api_ip, pv_api_op); |
6496 | 3.90k | break; |
6497 | | |
6498 | 3.90k | case IV_CMD_RETRIEVE_MEMREC: |
6499 | 3.90k | ret = ih264e_retrieve_memrec(ps_handle, pv_api_ip, pv_api_op); |
6500 | 3.90k | break; |
6501 | | |
6502 | 81.3k | case IVE_CMD_VIDEO_CTL: |
6503 | 81.3k | ret = ih264e_ctl(ps_handle, pv_api_ip, pv_api_op); |
6504 | 81.3k | break; |
6505 | | |
6506 | 66.0k | case IVE_CMD_VIDEO_ENCODE: |
6507 | 66.0k | ret = ih264e_encode(ps_handle, pv_api_ip, pv_api_op); |
6508 | 66.0k | break; |
6509 | | |
6510 | 0 | default: |
6511 | 0 | ret = IV_FAIL; |
6512 | 0 | break; |
6513 | 166k | } |
6514 | | |
6515 | 166k | return (IV_STATUS_T) ret; |
6516 | 166k | } |