Coverage Report

Created: 2026-07-16 06:18

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/libavc/decoder/ih264d_api.c
Line
Count
Source
1
/******************************************************************************
2
 *
3
 * Copyright (C) 2015 The Android Open Source Project
4
 *
5
 * Licensed under the Apache License, Version 2.0 (the "License");
6
 * you may not use this file except in compliance with the License.
7
 * You may obtain a copy of the License at:
8
 *
9
 * http://www.apache.org/licenses/LICENSE-2.0
10
 *
11
 * Unless required by applicable law or agreed to in writing, software
12
 * distributed under the License is distributed on an "AS IS" BASIS,
13
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14
 * See the License for the specific language governing permissions and
15
 * limitations under the License.
16
 *
17
 *****************************************************************************
18
 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19
*/
20
21
/*****************************************************************************/
22
/*                                                                           */
23
/*  File Name         : ih264d_api.c                                         */
24
/*                                                                           */
25
/*  Description       : Has all  API related functions                       */
26
/*                                                                           */
27
/*                                                                           */
28
/*  List of Functions : api_check_struct_sanity                              */
29
/*          ih264d_set_processor                                             */
30
/*          ih264d_create                                                    */
31
/*          ih264d_delete                                                    */
32
/*          ih264d_init                                                      */
33
/*          ih264d_map_error                                                 */
34
/*          ih264d_video_decode                                              */
35
/*          ih264d_get_version                                               */
36
/*          ih264d_get_display_frame                                         */
37
/*          ih264d_set_display_frame                                         */
38
/*          ih264d_set_flush_mode                                            */
39
/*          ih264d_get_status                                                */
40
/*          ih264d_get_buf_info                                              */
41
/*          ih264d_set_params                                                */
42
/*          ih264d_set_default_params                                        */
43
/*          ih264d_reset                                                     */
44
/*          ih264d_ctl                                                       */
45
/*          ih264d_rel_display_frame                                         */
46
/*          ih264d_set_degrade                                               */
47
/*          ih264d_get_frame_dimensions                                      */
48
/*          ih264d_set_num_cores                                             */
49
/*          ih264d_fill_output_struct_from_context                           */
50
/*          ih264d_api_function                                              */
51
/*                                                                           */
52
/*  Issues / Problems : None                                                 */
53
/*                                                                           */
54
/*  Revision History  :                                                      */
55
/*                                                                           */
56
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
57
/*         14 10 2008   100356(SKV)     Draft                                */
58
/*                                                                           */
59
/*****************************************************************************/
60
#include "ih264_typedefs.h"
61
#include "ih264_macros.h"
62
#include "ih264_platform_macros.h"
63
#include "ih264d_tables.h"
64
#include "iv.h"
65
#include "ivd.h"
66
#include "ih264d.h"
67
#include "ih264d_defs.h"
68
69
#include <string.h>
70
#include <limits.h>
71
#include <stddef.h>
72
73
#include "ih264d_inter_pred.h"
74
75
#include "ih264d_structs.h"
76
#include "ih264d_nal.h"
77
#include "ih264d_error_handler.h"
78
79
#include "ih264d_defs.h"
80
81
#include "ithread.h"
82
#include "ih264d_parse_slice.h"
83
#include "ih264d_function_selector.h"
84
#include "ih264_error.h"
85
#include "ih264_disp_mgr.h"
86
#include "ih264_buf_mgr.h"
87
#include "ih264d_deblocking.h"
88
#include "ih264d_parse_cavlc.h"
89
#include "ih264d_parse_cabac.h"
90
#include "ih264d_utils.h"
91
#include "ih264d_format_conv.h"
92
#include "ih264d_parse_headers.h"
93
#include "ih264d_thread_compute_bs.h"
94
#include <assert.h>
95
96
97
/*********************/
98
/* Codec Versioning  */
99
/*********************/
100
//Move this to where it is used
101
#define CODEC_NAME              "H264VDEC"
102
#define CODEC_RELEASE_TYPE      "production"
103
#define CODEC_RELEASE_VER       "05.00"
104
#define CODEC_VENDOR            "ITTIAM"
105
0
#define MAXVERSION_STRLEN       511
106
#ifdef ANDROID
107
#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor)    \
108
    snprintf(version_string, MAXVERSION_STRLEN,                                                     \
109
             "@(#)Id:%s_%s Ver:%s Released by %s",                                                  \
110
             codec_name, codec_release_type, codec_release_ver, codec_vendor)
111
#else
112
#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor)    \
113
0
    snprintf(version_string, MAXVERSION_STRLEN,                                                     \
114
0
             "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s",                                   \
115
0
             codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__)
116
#endif
117
118
119
0
#define MIN_IN_BUFS             1
120
71.2k
#define MIN_OUT_BUFS_420        3
121
0
#define MIN_OUT_BUFS_422ILE     1
122
0
#define MIN_OUT_BUFS_RGB565     1
123
68.5k
#define MIN_OUT_BUFS_420SP      2
124
125
#define NUM_FRAMES_LIMIT_ENABLED 0
126
127
#if NUM_FRAMES_LIMIT_ENABLED
128
#define NUM_FRAMES_LIMIT 10000
129
#else
130
0
#define NUM_FRAMES_LIMIT 0x7FFFFFFF
131
#endif
132
133
134
UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height);
135
WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
136
                                   void *pv_api_ip,
137
                                   void *pv_api_op);
138
WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
139
                             void *pv_api_ip,
140
                             void *pv_api_op);
141
142
WORD32 ih264d_get_sei_mdcv_params(iv_obj_t *dec_hdl,
143
                                  void *pv_api_ip,
144
                                  void *pv_api_op);
145
146
WORD32 ih264d_get_sei_cll_params(iv_obj_t *dec_hdl,
147
                                 void *pv_api_ip,
148
                                 void *pv_api_op);
149
150
WORD32 ih264d_get_sei_ave_params(iv_obj_t *dec_hdl,
151
                                 void *pv_api_ip,
152
                                 void *pv_api_op);
153
154
WORD32 ih264d_get_sei_ccv_params(iv_obj_t *dec_hdl,
155
                                 void *pv_api_ip,
156
                                 void *pv_api_op);
157
158
WORD32 ih264d_get_sei_sii_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
159
160
WORD32 ih264d_get_sei_fgc_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
161
162
WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
163
164
WORD32 ih264d_deblock_display(dec_struct_t *ps_dec);
165
166
void ih264d_signal_decode_thread(dec_struct_t *ps_dec);
167
168
void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec);
169
void ih264d_decode_picture_thread(dec_struct_t *ps_dec);
170
171
WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
172
                          void *pv_api_ip,
173
                          void *pv_api_op);
174
175
void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
176
                                            ivd_video_decode_op_t *ps_dec_op);
177
178
/*!
179
 **************************************************************************
180
 * \if Function name : ih264d_export_sei_params \endif
181
 *
182
 * \brief
183
 *    Exports sei params from decoder to application.
184
 *
185
 * \return
186
 *    0 on Success and error code otherwise
187
 **************************************************************************
188
 */
189
190
void ih264d_export_sei_params(ivd_sei_decode_op_t *ps_sei_decode_op, dec_struct_t *ps_dec)
191
198k
{
192
198k
    WORD32 i4_status = IV_SUCCESS;
193
198k
    sei *ps_sei = (sei *)ps_dec->pv_disp_sei_params;
194
195
198k
    i4_status = ih264d_export_sei_mdcv_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
196
198k
    i4_status = ih264d_export_sei_cll_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
197
198k
    i4_status = ih264d_export_sei_ave_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
198
198k
    i4_status = ih264d_export_sei_ccv_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
199
198k
    i4_status = ih264d_export_sei_sii_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
200
198k
    i4_status = ih264d_export_sei_fgc_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
201
202
198k
    UNUSED(i4_status);
203
198k
}
204
205
static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
206
                                                    void *pv_api_ip,
207
                                                    void *pv_api_op)
208
0
{
209
0
    IVD_API_COMMAND_TYPE_T e_cmd;
210
0
    UWORD32 *pu4_api_ip;
211
0
    UWORD32 *pu4_api_op;
212
0
    UWORD32 i, j;
213
214
0
    if(NULL == pv_api_op)
215
0
        return (IV_FAIL);
216
217
0
    if(NULL == pv_api_ip)
218
0
        return (IV_FAIL);
219
220
0
    pu4_api_ip = (UWORD32 *)pv_api_ip;
221
0
    pu4_api_op = (UWORD32 *)pv_api_op;
222
0
    e_cmd = *(pu4_api_ip + 1);
223
224
    /* error checks on handle */
225
0
    switch((WORD32)e_cmd)
226
0
    {
227
0
        case IVD_CMD_CREATE:
228
0
            break;
229
230
0
        case IVD_CMD_REL_DISPLAY_FRAME:
231
0
        case IVD_CMD_SET_DISPLAY_FRAME:
232
0
        case IVD_CMD_GET_DISPLAY_FRAME:
233
0
        case IVD_CMD_VIDEO_DECODE:
234
0
        case IVD_CMD_DELETE:
235
0
        case IVD_CMD_VIDEO_CTL:
236
0
            if(ps_handle == NULL)
237
0
            {
238
0
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
239
0
                *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
240
0
                return IV_FAIL;
241
0
            }
242
243
0
            if(ps_handle->u4_size != sizeof(iv_obj_t))
244
0
            {
245
0
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
246
0
                *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
247
0
                return IV_FAIL;
248
0
            }
249
250
0
            if(ps_handle->pv_fxns != ih264d_api_function)
251
0
            {
252
0
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
253
0
                *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
254
0
                return IV_FAIL;
255
0
            }
256
257
0
            if(ps_handle->pv_codec_handle == NULL)
258
0
            {
259
0
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
260
0
                *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
261
0
                return IV_FAIL;
262
0
            }
263
0
            break;
264
0
        default:
265
0
            *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
266
0
            *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
267
0
            return IV_FAIL;
268
0
    }
269
270
0
    switch((WORD32)e_cmd)
271
0
    {
272
0
        case IVD_CMD_CREATE:
273
0
        {
274
0
            ih264d_create_ip_t *ps_ip = (ih264d_create_ip_t *)pv_api_ip;
275
0
            ih264d_create_op_t *ps_op = (ih264d_create_op_t *)pv_api_op;
276
277
278
0
            ps_op->s_ivd_create_op_t.u4_error_code = 0;
279
280
0
            if((ps_ip->s_ivd_create_ip_t.u4_size > sizeof(ih264d_create_ip_t))
281
0
                            || (ps_ip->s_ivd_create_ip_t.u4_size
282
0
                                            < sizeof(ivd_create_ip_t)))
283
0
            {
284
0
                ps_op->s_ivd_create_op_t.u4_error_code |= 1
285
0
                                << IVD_UNSUPPORTEDPARAM;
286
0
                ps_op->s_ivd_create_op_t.u4_error_code |=
287
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
288
0
                H264_DEC_DEBUG_PRINT("\n");
289
0
                return (IV_FAIL);
290
0
            }
291
292
0
            if((ps_op->s_ivd_create_op_t.u4_size != sizeof(ih264d_create_op_t))
293
0
                            && (ps_op->s_ivd_create_op_t.u4_size
294
0
                                            != sizeof(ivd_create_op_t)))
295
0
            {
296
0
                ps_op->s_ivd_create_op_t.u4_error_code |= 1
297
0
                                << IVD_UNSUPPORTEDPARAM;
298
0
                ps_op->s_ivd_create_op_t.u4_error_code |=
299
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
300
0
                H264_DEC_DEBUG_PRINT("\n");
301
0
                return (IV_FAIL);
302
0
            }
303
304
305
0
            if((ps_ip->s_ivd_create_ip_t.e_output_format != IV_YUV_420P)
306
0
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
307
0
                                            != IV_YUV_422ILE)
308
0
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
309
0
                                            != IV_RGB_565)
310
0
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
311
0
                                            != IV_YUV_420SP_UV)
312
0
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
313
0
                                            != IV_YUV_420SP_VU))
314
0
            {
315
0
                ps_op->s_ivd_create_op_t.u4_error_code |= 1
316
0
                                << IVD_UNSUPPORTEDPARAM;
317
0
                ps_op->s_ivd_create_op_t.u4_error_code |=
318
0
                                IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
319
0
                H264_DEC_DEBUG_PRINT("\n");
320
0
                return (IV_FAIL);
321
0
            }
322
323
0
        }
324
0
            break;
325
326
0
        case IVD_CMD_GET_DISPLAY_FRAME:
327
0
        {
328
0
            ih264d_get_display_frame_ip_t *ps_ip =
329
0
                            (ih264d_get_display_frame_ip_t *)pv_api_ip;
330
0
            ih264d_get_display_frame_op_t *ps_op =
331
0
                            (ih264d_get_display_frame_op_t *)pv_api_op;
332
333
0
            ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
334
335
0
            if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size
336
0
                            != sizeof(ih264d_get_display_frame_ip_t))
337
0
                            && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size
338
0
                                            != sizeof(ivd_get_display_frame_ip_t)))
339
0
            {
340
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
341
0
                                << IVD_UNSUPPORTEDPARAM;
342
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
343
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
344
0
                return (IV_FAIL);
345
0
            }
346
347
0
            if((ps_op->s_ivd_get_display_frame_op_t.u4_size
348
0
                            != sizeof(ih264d_get_display_frame_op_t))
349
0
                            && (ps_op->s_ivd_get_display_frame_op_t.u4_size
350
0
                                            != sizeof(ivd_get_display_frame_op_t)))
351
0
            {
352
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
353
0
                                << IVD_UNSUPPORTEDPARAM;
354
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
355
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
356
0
                return (IV_FAIL);
357
0
            }
358
0
        }
359
0
            break;
360
361
0
        case IVD_CMD_REL_DISPLAY_FRAME:
362
0
        {
363
0
            ih264d_rel_display_frame_ip_t *ps_ip =
364
0
                            (ih264d_rel_display_frame_ip_t *)pv_api_ip;
365
0
            ih264d_rel_display_frame_op_t *ps_op =
366
0
                            (ih264d_rel_display_frame_op_t *)pv_api_op;
367
368
0
            ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
369
370
0
            if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
371
0
                            != sizeof(ih264d_rel_display_frame_ip_t))
372
0
                            && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
373
0
                                            != sizeof(ivd_rel_display_frame_ip_t)))
374
0
            {
375
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
376
0
                                << IVD_UNSUPPORTEDPARAM;
377
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
378
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
379
0
                return (IV_FAIL);
380
0
            }
381
382
0
            if((ps_op->s_ivd_rel_display_frame_op_t.u4_size
383
0
                            != sizeof(ih264d_rel_display_frame_op_t))
384
0
                            && (ps_op->s_ivd_rel_display_frame_op_t.u4_size
385
0
                                            != sizeof(ivd_rel_display_frame_op_t)))
386
0
            {
387
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
388
0
                                << IVD_UNSUPPORTEDPARAM;
389
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
390
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
391
0
                return (IV_FAIL);
392
0
            }
393
394
0
        }
395
0
            break;
396
397
0
        case IVD_CMD_SET_DISPLAY_FRAME:
398
0
        {
399
0
            ih264d_set_display_frame_ip_t *ps_ip =
400
0
                            (ih264d_set_display_frame_ip_t *)pv_api_ip;
401
0
            ih264d_set_display_frame_op_t *ps_op =
402
0
                            (ih264d_set_display_frame_op_t *)pv_api_op;
403
0
            UWORD32 j;
404
405
0
            ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
406
407
0
            if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size
408
0
                            != sizeof(ih264d_set_display_frame_ip_t))
409
0
                            && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size
410
0
                                            != sizeof(ivd_set_display_frame_ip_t)))
411
0
            {
412
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
413
0
                                << IVD_UNSUPPORTEDPARAM;
414
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
415
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
416
0
                return (IV_FAIL);
417
0
            }
418
419
0
            if((ps_op->s_ivd_set_display_frame_op_t.u4_size
420
0
                            != sizeof(ih264d_set_display_frame_op_t))
421
0
                            && (ps_op->s_ivd_set_display_frame_op_t.u4_size
422
0
                                            != sizeof(ivd_set_display_frame_op_t)))
423
0
            {
424
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
425
0
                                << IVD_UNSUPPORTEDPARAM;
426
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
427
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
428
0
                return (IV_FAIL);
429
0
            }
430
431
0
            if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
432
0
            {
433
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
434
0
                                << IVD_UNSUPPORTEDPARAM;
435
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
436
0
                                IVD_DISP_FRM_ZERO_OP_BUFS;
437
0
                return IV_FAIL;
438
0
            }
439
440
0
            for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs;
441
0
                            j++)
442
0
            {
443
0
                if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs
444
0
                                == 0)
445
0
                {
446
0
                    ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
447
0
                                    << IVD_UNSUPPORTEDPARAM;
448
0
                    ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
449
0
                                    IVD_DISP_FRM_ZERO_OP_BUFS;
450
0
                    return IV_FAIL;
451
0
                }
452
453
0
                for(i = 0;
454
0
                                i
455
0
                                                < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;
456
0
                                i++)
457
0
                {
458
0
                    if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i]
459
0
                                    == NULL)
460
0
                    {
461
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
462
0
                                        << IVD_UNSUPPORTEDPARAM;
463
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
464
0
                                        IVD_DISP_FRM_OP_BUF_NULL;
465
0
                        return IV_FAIL;
466
0
                    }
467
468
0
                    if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i]
469
0
                                    == 0)
470
0
                    {
471
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
472
0
                                        << IVD_UNSUPPORTEDPARAM;
473
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
474
0
                                        IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
475
0
                        return IV_FAIL;
476
0
                    }
477
0
                }
478
0
            }
479
0
        }
480
0
            break;
481
482
0
        case IVD_CMD_VIDEO_DECODE:
483
0
        {
484
0
            ih264d_video_decode_ip_t *ps_ip =
485
0
                            (ih264d_video_decode_ip_t *)pv_api_ip;
486
0
            ih264d_video_decode_op_t *ps_op =
487
0
                            (ih264d_video_decode_op_t *)pv_api_op;
488
489
0
            H264_DEC_DEBUG_PRINT("The input bytes is: %d",
490
0
                                 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes);
491
0
            ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
492
493
0
            if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(ih264d_video_decode_ip_t) &&
494
0
               ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(ivd_video_decode_ip_t) &&
495
0
               ps_ip->s_ivd_video_decode_ip_t.u4_size !=
496
0
                   offsetof(ivd_video_decode_ip_t, s_out_buffer))
497
0
            {
498
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
499
0
                                << IVD_UNSUPPORTEDPARAM;
500
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |=
501
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
502
0
                return (IV_FAIL);
503
0
            }
504
505
0
            if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(ih264d_video_decode_op_t) &&
506
0
               ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(ivd_video_decode_op_t) &&
507
0
               ps_op->s_ivd_video_decode_op_t.u4_size !=
508
0
                   offsetof(ivd_video_decode_op_t, u4_output_present))
509
0
            {
510
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
511
0
                                << IVD_UNSUPPORTEDPARAM;
512
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |=
513
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
514
0
                return (IV_FAIL);
515
0
            }
516
517
0
            {
518
0
                dec_struct_t *ps_dec = (dec_struct_t *)(ps_handle->pv_codec_handle);
519
0
                if(ps_dec->u1_enable_mb_info)
520
0
                {
521
0
                    if(!ps_ip->pu1_8x8_blk_qp_map && !ps_ip->pu1_8x8_blk_type_map)
522
0
                    {
523
0
                        ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
524
0
                                        << IVD_UNSUPPORTEDPARAM;
525
0
                        ps_op->s_ivd_video_decode_op_t.u4_error_code |=
526
0
                                        IH264D_FRAME_INFO_OP_BUF_NULL;
527
0
                        return IV_FAIL;
528
0
                    }
529
0
                }
530
0
            }
531
0
        }
532
0
            break;
533
534
0
        case IVD_CMD_DELETE:
535
0
        {
536
0
            ih264d_delete_ip_t *ps_ip =
537
0
                            (ih264d_delete_ip_t *)pv_api_ip;
538
0
            ih264d_delete_op_t *ps_op =
539
0
                            (ih264d_delete_op_t *)pv_api_op;
540
541
0
            ps_op->s_ivd_delete_op_t.u4_error_code = 0;
542
543
0
            if(ps_ip->s_ivd_delete_ip_t.u4_size
544
0
                            != sizeof(ih264d_delete_ip_t))
545
0
            {
546
0
                ps_op->s_ivd_delete_op_t.u4_error_code |= 1
547
0
                                << IVD_UNSUPPORTEDPARAM;
548
0
                ps_op->s_ivd_delete_op_t.u4_error_code |=
549
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
550
0
                return (IV_FAIL);
551
0
            }
552
553
0
            if(ps_op->s_ivd_delete_op_t.u4_size
554
0
                            != sizeof(ih264d_delete_op_t))
555
0
            {
556
0
                ps_op->s_ivd_delete_op_t.u4_error_code |= 1
557
0
                                << IVD_UNSUPPORTEDPARAM;
558
0
                ps_op->s_ivd_delete_op_t.u4_error_code |=
559
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
560
0
                return (IV_FAIL);
561
0
            }
562
563
0
        }
564
0
            break;
565
566
0
        case IVD_CMD_VIDEO_CTL:
567
0
        {
568
0
            UWORD32 *pu4_ptr_cmd;
569
0
            UWORD32 sub_command;
570
571
0
            pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
572
0
            pu4_ptr_cmd += 2;
573
0
            sub_command = *pu4_ptr_cmd;
574
575
0
            switch(sub_command)
576
0
            {
577
0
                case IVD_CMD_CTL_SETPARAMS:
578
0
                {
579
0
                    ih264d_ctl_set_config_ip_t *ps_ip;
580
0
                    ih264d_ctl_set_config_op_t *ps_op;
581
0
                    ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip;
582
0
                    ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
583
584
0
                    if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size
585
0
                                    != sizeof(ih264d_ctl_set_config_ip_t))
586
0
                    {
587
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
588
0
                                        << IVD_UNSUPPORTEDPARAM;
589
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
590
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
591
0
                        return IV_FAIL;
592
0
                    }
593
0
                }
594
                    //no break; is needed here
595
0
                case IVD_CMD_CTL_SETDEFAULT:
596
0
                {
597
0
                    ih264d_ctl_set_config_op_t *ps_op;
598
0
                    ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
599
0
                    if(ps_op->s_ivd_ctl_set_config_op_t.u4_size
600
0
                                    != sizeof(ih264d_ctl_set_config_op_t))
601
0
                    {
602
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
603
0
                                        << IVD_UNSUPPORTEDPARAM;
604
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
605
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
606
0
                        return IV_FAIL;
607
0
                    }
608
0
                }
609
0
                    break;
610
611
0
                case IVD_CMD_CTL_GETPARAMS:
612
0
                {
613
0
                    ih264d_ctl_getstatus_ip_t *ps_ip;
614
0
                    ih264d_ctl_getstatus_op_t *ps_op;
615
616
0
                    ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip;
617
0
                    ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op;
618
0
                    if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size
619
0
                                    != sizeof(ih264d_ctl_getstatus_ip_t))
620
0
                    {
621
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
622
0
                                        << IVD_UNSUPPORTEDPARAM;
623
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
624
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
625
0
                        return IV_FAIL;
626
0
                    }
627
0
                    if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size
628
0
                                    != sizeof(ih264d_ctl_getstatus_op_t))
629
0
                    {
630
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
631
0
                                        << IVD_UNSUPPORTEDPARAM;
632
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
633
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
634
0
                        return IV_FAIL;
635
0
                    }
636
0
                }
637
0
                    break;
638
639
0
                case IVD_CMD_CTL_GETBUFINFO:
640
0
                {
641
0
                    ih264d_ctl_getbufinfo_ip_t *ps_ip;
642
0
                    ih264d_ctl_getbufinfo_op_t *ps_op;
643
0
                    ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip;
644
0
                    ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op;
645
646
0
                    if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size
647
0
                                    != sizeof(ih264d_ctl_getbufinfo_ip_t))
648
0
                    {
649
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
650
0
                                        << IVD_UNSUPPORTEDPARAM;
651
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
652
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
653
0
                        return IV_FAIL;
654
0
                    }
655
0
                    if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size
656
0
                                    != sizeof(ih264d_ctl_getbufinfo_op_t))
657
0
                    {
658
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
659
0
                                        << IVD_UNSUPPORTEDPARAM;
660
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
661
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
662
0
                        return IV_FAIL;
663
0
                    }
664
0
                }
665
0
                    break;
666
667
0
                case IVD_CMD_CTL_GETVERSION:
668
0
                {
669
0
                    ih264d_ctl_getversioninfo_ip_t *ps_ip;
670
0
                    ih264d_ctl_getversioninfo_op_t *ps_op;
671
0
                    ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip;
672
0
                    ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op;
673
0
                    if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size
674
0
                                    != sizeof(ih264d_ctl_getversioninfo_ip_t))
675
0
                    {
676
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
677
0
                                        << IVD_UNSUPPORTEDPARAM;
678
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
679
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
680
0
                        return IV_FAIL;
681
0
                    }
682
0
                    if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size
683
0
                                    != sizeof(ih264d_ctl_getversioninfo_op_t))
684
0
                    {
685
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
686
0
                                        << IVD_UNSUPPORTEDPARAM;
687
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
688
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
689
0
                        return IV_FAIL;
690
0
                    }
691
0
                }
692
0
                    break;
693
694
0
                case IVD_CMD_CTL_FLUSH:
695
0
                {
696
0
                    ih264d_ctl_flush_ip_t *ps_ip;
697
0
                    ih264d_ctl_flush_op_t *ps_op;
698
0
                    ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip;
699
0
                    ps_op = (ih264d_ctl_flush_op_t *)pv_api_op;
700
0
                    if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size
701
0
                                    != sizeof(ih264d_ctl_flush_ip_t))
702
0
                    {
703
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
704
0
                                        << IVD_UNSUPPORTEDPARAM;
705
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
706
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
707
0
                        return IV_FAIL;
708
0
                    }
709
0
                    if(ps_op->s_ivd_ctl_flush_op_t.u4_size
710
0
                                    != sizeof(ih264d_ctl_flush_op_t))
711
0
                    {
712
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
713
0
                                        << IVD_UNSUPPORTEDPARAM;
714
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
715
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
716
0
                        return IV_FAIL;
717
0
                    }
718
0
                }
719
0
                    break;
720
721
0
                case IVD_CMD_CTL_RESET:
722
0
                {
723
0
                    ih264d_ctl_reset_ip_t *ps_ip;
724
0
                    ih264d_ctl_reset_op_t *ps_op;
725
0
                    ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip;
726
0
                    ps_op = (ih264d_ctl_reset_op_t *)pv_api_op;
727
0
                    if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size
728
0
                                    != sizeof(ih264d_ctl_reset_ip_t))
729
0
                    {
730
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
731
0
                                        << IVD_UNSUPPORTEDPARAM;
732
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
733
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
734
0
                        return IV_FAIL;
735
0
                    }
736
0
                    if(ps_op->s_ivd_ctl_reset_op_t.u4_size
737
0
                                    != sizeof(ih264d_ctl_reset_op_t))
738
0
                    {
739
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
740
0
                                        << IVD_UNSUPPORTEDPARAM;
741
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
742
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
743
0
                        return IV_FAIL;
744
0
                    }
745
0
                }
746
0
                    break;
747
748
0
                case IH264D_CMD_CTL_DEGRADE:
749
0
                {
750
0
                    ih264d_ctl_degrade_ip_t *ps_ip;
751
0
                    ih264d_ctl_degrade_op_t *ps_op;
752
753
0
                    ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
754
0
                    ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
755
756
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t))
757
0
                    {
758
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
759
0
                        ps_op->u4_error_code |=
760
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
761
0
                        return IV_FAIL;
762
0
                    }
763
764
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t))
765
0
                    {
766
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
767
0
                        ps_op->u4_error_code |=
768
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
769
0
                        return IV_FAIL;
770
0
                    }
771
772
0
                    if((ps_ip->i4_degrade_pics < 0)
773
0
                                    || (ps_ip->i4_degrade_pics > 4)
774
0
                                    || (ps_ip->i4_nondegrade_interval < 0)
775
0
                                    || (ps_ip->i4_degrade_type < 0)
776
0
                                    || (ps_ip->i4_degrade_type > 15))
777
0
                    {
778
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
779
0
                        return IV_FAIL;
780
0
                    }
781
782
0
                    break;
783
0
                }
784
785
0
                case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
786
0
                {
787
0
                    ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
788
0
                    ih264d_ctl_get_frame_dimensions_op_t *ps_op;
789
790
0
                    ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
791
0
                    ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
792
793
0
                    if(ps_ip->u4_size
794
0
                                    != sizeof(ih264d_ctl_get_frame_dimensions_ip_t))
795
0
                    {
796
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
797
0
                        ps_op->u4_error_code |=
798
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
799
0
                        return IV_FAIL;
800
0
                    }
801
802
0
                    if(ps_op->u4_size
803
0
                                    != sizeof(ih264d_ctl_get_frame_dimensions_op_t))
804
0
                    {
805
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
806
0
                        ps_op->u4_error_code |=
807
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
808
0
                        return IV_FAIL;
809
0
                    }
810
811
0
                    break;
812
0
                }
813
0
                case IH264D_CMD_CTL_GET_VUI_PARAMS:
814
0
                {
815
0
                    ih264d_ctl_get_vui_params_ip_t *ps_ip;
816
0
                    ih264d_ctl_get_vui_params_op_t *ps_op;
817
818
0
                    ps_ip =
819
0
                                    (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
820
0
                    ps_op =
821
0
                                    (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
822
823
0
                    if(ps_ip->u4_size
824
0
                                    != sizeof(ih264d_ctl_get_vui_params_ip_t))
825
0
                    {
826
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
827
0
                        ps_op->u4_error_code |=
828
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
829
0
                        return IV_FAIL;
830
0
                    }
831
832
0
                    if(ps_op->u4_size
833
0
                                    != sizeof(ih264d_ctl_get_vui_params_op_t))
834
0
                    {
835
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
836
0
                        ps_op->u4_error_code |=
837
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
838
0
                        return IV_FAIL;
839
0
                    }
840
841
0
                    break;
842
0
                }
843
0
                case IH264D_CMD_CTL_GET_SEI_MDCV_PARAMS:
844
0
                {
845
0
                    ih264d_ctl_get_sei_mdcv_params_ip_t *ps_ip;
846
0
                    ih264d_ctl_get_sei_mdcv_params_op_t *ps_op;
847
848
0
                    ps_ip = (ih264d_ctl_get_sei_mdcv_params_ip_t *)pv_api_ip;
849
0
                    ps_op = (ih264d_ctl_get_sei_mdcv_params_op_t *)pv_api_op;
850
851
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_mdcv_params_ip_t))
852
0
                    {
853
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
854
0
                        ps_op->u4_error_code |=
855
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
856
0
                        return IV_FAIL;
857
0
                    }
858
859
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_mdcv_params_op_t))
860
0
                    {
861
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
862
0
                        ps_op->u4_error_code |=
863
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
864
0
                        return IV_FAIL;
865
0
                    }
866
867
0
                    break;
868
0
                }
869
870
0
                case IH264D_CMD_CTL_GET_SEI_CLL_PARAMS:
871
0
                {
872
0
                    ih264d_ctl_get_sei_cll_params_ip_t *ps_ip;
873
0
                    ih264d_ctl_get_sei_cll_params_op_t *ps_op;
874
875
0
                    ps_ip = (ih264d_ctl_get_sei_cll_params_ip_t *)pv_api_ip;
876
0
                    ps_op = (ih264d_ctl_get_sei_cll_params_op_t *)pv_api_op;
877
878
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_cll_params_ip_t))
879
0
                    {
880
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
881
0
                        ps_op->u4_error_code |=
882
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
883
0
                        return IV_FAIL;
884
0
                    }
885
886
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_cll_params_op_t))
887
0
                    {
888
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
889
0
                        ps_op->u4_error_code |=
890
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
891
0
                        return IV_FAIL;
892
0
                    }
893
894
0
                    break;
895
0
                }
896
897
0
                case IH264D_CMD_CTL_GET_SEI_AVE_PARAMS:
898
0
                {
899
0
                    ih264d_ctl_get_sei_ave_params_ip_t *ps_ip;
900
0
                    ih264d_ctl_get_sei_ave_params_op_t *ps_op;
901
902
0
                    ps_ip = (ih264d_ctl_get_sei_ave_params_ip_t *)pv_api_ip;
903
0
                    ps_op = (ih264d_ctl_get_sei_ave_params_op_t *)pv_api_op;
904
905
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_ave_params_ip_t))
906
0
                    {
907
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
908
0
                        ps_op->u4_error_code |=
909
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
910
0
                        return IV_FAIL;
911
0
                    }
912
913
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_ave_params_op_t))
914
0
                    {
915
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
916
0
                        ps_op->u4_error_code |=
917
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
918
0
                        return IV_FAIL;
919
0
                    }
920
921
0
                    break;
922
0
                }
923
924
0
                case IH264D_CMD_CTL_GET_SEI_CCV_PARAMS:
925
0
                {
926
0
                    ih264d_ctl_get_sei_ccv_params_ip_t *ps_ip;
927
0
                    ih264d_ctl_get_sei_ccv_params_op_t *ps_op;
928
929
0
                    ps_ip = (ih264d_ctl_get_sei_ccv_params_ip_t *)pv_api_ip;
930
0
                    ps_op = (ih264d_ctl_get_sei_ccv_params_op_t *)pv_api_op;
931
932
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_ccv_params_ip_t))
933
0
                    {
934
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
935
0
                        ps_op->u4_error_code |=
936
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
937
0
                        return IV_FAIL;
938
0
                    }
939
940
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_ccv_params_op_t))
941
0
                    {
942
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
943
0
                        ps_op->u4_error_code |=
944
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
945
0
                        return IV_FAIL;
946
0
                    }
947
948
0
                    break;
949
0
                }
950
951
0
                case IH264D_CMD_CTL_GET_SEI_SII_PARAMS:
952
0
                {
953
0
                    ih264d_ctl_get_sei_sii_params_ip_t *ps_ip;
954
0
                    ih264d_ctl_get_sei_sii_params_op_t *ps_op;
955
956
0
                    ps_ip = (ih264d_ctl_get_sei_sii_params_ip_t *) pv_api_ip;
957
0
                    ps_op = (ih264d_ctl_get_sei_sii_params_op_t *) pv_api_op;
958
959
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_sii_params_ip_t))
960
0
                    {
961
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
962
0
                        ps_op->u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
963
0
                        return IV_FAIL;
964
0
                    }
965
966
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_sii_params_op_t))
967
0
                    {
968
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
969
0
                        ps_op->u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
970
0
                        return IV_FAIL;
971
0
                    }
972
973
0
                    break;
974
0
                }
975
976
0
                case IH264D_CMD_CTL_GET_SEI_FGC_PARAMS:
977
0
                {
978
0
                    ih264d_ctl_get_sei_fgc_params_ip_t *ps_ip;
979
0
                    ih264d_ctl_get_sei_fgc_params_op_t *ps_op;
980
981
0
                    ps_ip = (ih264d_ctl_get_sei_fgc_params_ip_t *) pv_api_ip;
982
0
                    ps_op = (ih264d_ctl_get_sei_fgc_params_op_t *) pv_api_op;
983
984
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_fgc_params_ip_t))
985
0
                    {
986
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
987
0
                        ps_op->u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
988
0
                        return IV_FAIL;
989
0
                    }
990
991
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_fgc_params_op_t))
992
0
                    {
993
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
994
0
                        ps_op->u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
995
0
                        return IV_FAIL;
996
0
                    }
997
998
0
                    break;
999
0
                }
1000
1001
0
                case IH264D_CMD_CTL_SET_NUM_CORES:
1002
0
                {
1003
0
                    ih264d_ctl_set_num_cores_ip_t *ps_ip;
1004
0
                    ih264d_ctl_set_num_cores_op_t *ps_op;
1005
1006
0
                    ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
1007
0
                    ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
1008
1009
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t))
1010
0
                    {
1011
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1012
0
                        ps_op->u4_error_code |=
1013
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
1014
0
                        return IV_FAIL;
1015
0
                    }
1016
1017
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t))
1018
0
                    {
1019
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1020
0
                        ps_op->u4_error_code |=
1021
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
1022
0
                        return IV_FAIL;
1023
0
                    }
1024
1025
0
                    if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2)
1026
0
                                    && (ps_ip->u4_num_cores != 3)
1027
0
                                    && (ps_ip->u4_num_cores != 4))
1028
0
                    {
1029
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1030
0
                        return IV_FAIL;
1031
0
                    }
1032
0
                    break;
1033
0
                }
1034
0
                case IH264D_CMD_CTL_SET_PROCESSOR:
1035
0
                {
1036
0
                    ih264d_ctl_set_processor_ip_t *ps_ip;
1037
0
                    ih264d_ctl_set_processor_op_t *ps_op;
1038
1039
0
                    ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1040
0
                    ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1041
1042
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t))
1043
0
                    {
1044
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1045
0
                        ps_op->u4_error_code |=
1046
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
1047
0
                        return IV_FAIL;
1048
0
                    }
1049
1050
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t))
1051
0
                    {
1052
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1053
0
                        ps_op->u4_error_code |=
1054
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
1055
0
                        return IV_FAIL;
1056
0
                    }
1057
1058
0
                    break;
1059
0
                }
1060
0
                default:
1061
0
                    *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
1062
0
                    *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
1063
0
                    return IV_FAIL;
1064
0
                    break;
1065
0
            }
1066
0
        }
1067
0
            break;
1068
0
    }
1069
1070
0
    return IV_SUCCESS;
1071
0
}
1072
1073
1074
/**
1075
 *******************************************************************************
1076
 *
1077
 * @brief
1078
 *  Sets Processor type
1079
 *
1080
 * @par Description:
1081
 *  Sets Processor type
1082
 *
1083
 * @param[in] ps_codec_obj
1084
 *  Pointer to codec object at API level
1085
 *
1086
 * @param[in] pv_api_ip
1087
 *  Pointer to input argument structure
1088
 *
1089
 * @param[out] pv_api_op
1090
 *  Pointer to output argument structure
1091
 *
1092
 * @returns  Status
1093
 *
1094
 * @remarks
1095
 *
1096
 *
1097
 *******************************************************************************
1098
 */
1099
1100
WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1101
0
{
1102
0
    ih264d_ctl_set_processor_ip_t *ps_ip;
1103
0
    ih264d_ctl_set_processor_op_t *ps_op;
1104
0
    dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1105
1106
0
    ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1107
0
    ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1108
1109
0
    ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
1110
0
    ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
1111
1112
0
    ih264d_init_function_ptr(ps_codec);
1113
1114
0
    ps_op->u4_error_code = 0;
1115
0
    return IV_SUCCESS;
1116
0
}
1117
1118
1119
/**************************************************************************
1120
 * \if Function name : ih264d_init_decoder \endif
1121
 *
1122
 *
1123
 * \brief
1124
 *    Initializes the decoder
1125
 *
1126
 * \param apiVersion               : Version of the api being used.
1127
 * \param errorHandlingMechanism   : Mechanism to be used for errror handling.
1128
 * \param postFilteringType: Type of post filtering operation to be used.
1129
 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0].
1130
 * \param uc_dispBufs: Number of Display Buffers.
1131
 * \param p_NALBufAPI: Pointer to NAL Buffer API.
1132
 * \param p_DispBufAPI: Pointer to Display Buffer API.
1133
 * \param ih264d_dec_mem_manager  :Pointer to the function that will be called by decoder
1134
 *                        for memory allocation and freeing.
1135
 *
1136
 * \return
1137
 *    0 on Success and -1 on error
1138
 *
1139
 **************************************************************************
1140
 */
1141
void ih264d_init_decoder(void * ps_dec_params)
1142
0
{
1143
0
    dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params;
1144
0
    dec_slice_params_t *ps_cur_slice;
1145
0
    pocstruct_t *ps_prev_poc, *ps_cur_poc;
1146
0
    WORD32 size;
1147
1148
0
    size = sizeof(pred_info_t) * 2 * 32;
1149
0
    memset(ps_dec->ps_pred, 0 , size);
1150
1151
0
    size = sizeof(disp_mgr_t);
1152
0
    memset(ps_dec->pv_disp_buf_mgr, 0 , size);
1153
1154
0
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1155
0
    memset(ps_dec->pv_pic_buf_mgr, 0, size);
1156
1157
0
    size = sizeof(dec_err_status_t);
1158
0
    memset(ps_dec->ps_dec_err_status, 0, size);
1159
1160
0
    size = sizeof(sei);
1161
0
    memset(ps_dec->ps_sei, 0, size);
1162
1163
0
    size = sizeof(sei);
1164
0
    memset(ps_dec->ps_sei_parse, 0, size);
1165
1166
0
    size = sizeof(dpb_commands_t);
1167
0
    memset(ps_dec->ps_dpb_cmds, 0, size);
1168
1169
0
    size = sizeof(dec_bit_stream_t);
1170
0
    memset(ps_dec->ps_bitstrm, 0, size);
1171
1172
0
    size = sizeof(dec_slice_params_t);
1173
0
    memset(ps_dec->ps_cur_slice, 0, size);
1174
1175
0
    size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1176
0
    memset(ps_dec->pv_scratch_sps_pps, 0, size);
1177
1178
0
    size = sizeof(ctxt_inc_mb_info_t);
1179
0
    memset(ps_dec->ps_left_mb_ctxt_info, 0, size);
1180
1181
0
    size = (sizeof(neighbouradd_t) << 2);
1182
0
    memset(ps_dec->ps_left_mvpred_addr, 0 ,size);
1183
1184
0
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1185
0
    memset(ps_dec->pv_mv_buf_mgr, 0, size);
1186
1187
    /* Free any dynamic buffers that are allocated */
1188
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_dynamic);
1189
0
    ih264d_free_dynamic_bufs(ps_dec);
1190
1191
0
    {
1192
0
        UWORD8 i;
1193
0
        struct pic_buffer_t *ps_init_dpb;
1194
0
        ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0];
1195
0
        for(i = 0; i < 2 * MAX_REF_BUFS; i++)
1196
0
        {
1197
0
            ps_init_dpb->pu1_buf1 = NULL;
1198
0
            ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1199
0
            ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb;
1200
0
            ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb;
1201
0
            ps_init_dpb++;
1202
0
        }
1203
1204
0
        ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0];
1205
0
        for(i = 0; i < 2 * MAX_REF_BUFS; i++)
1206
0
        {
1207
0
            ps_init_dpb->pu1_buf1 = NULL;
1208
0
            ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1209
0
            ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb;
1210
0
            ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb;
1211
0
            ps_init_dpb++;
1212
0
        }
1213
0
    }
1214
1215
0
    ps_cur_slice = ps_dec->ps_cur_slice;
1216
0
    ps_dec->init_done = 0;
1217
1218
0
    ps_dec->u4_num_cores = 1;
1219
1220
0
    ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0;
1221
1222
0
    ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
1223
0
    ps_dec->u4_app_disable_deblk_frm = 0;
1224
0
    ps_dec->i4_degrade_type = 0;
1225
0
    ps_dec->i4_degrade_pics = 0;
1226
1227
0
    memset(ps_dec->ps_pps, 0,
1228
0
           ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
1229
0
    memset(ps_dec->ps_sps, 0,
1230
0
           ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
1231
1232
    /* Initialization of function pointers ih264d_deblock_picture function*/
1233
1234
0
    ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
1235
0
    ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
1236
1237
0
    ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec;
1238
1239
0
    ps_dec->u4_num_fld_in_frm = 0;
1240
1241
0
    ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1242
1243
    /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/
1244
0
    ps_dec->ps_sei->u1_is_valid = 0;
1245
1246
    /* decParams Initializations */
1247
0
    ps_dec->ps_cur_pps = NULL;
1248
0
    ps_dec->ps_cur_sps = NULL;
1249
0
    ps_dec->u1_init_dec_flag = 0;
1250
0
    ps_dec->u1_first_slice_in_stream = 1;
1251
0
    ps_dec->u1_last_pic_not_decoded = 0;
1252
0
    ps_dec->u4_app_disp_width = 0;
1253
0
    ps_dec->i4_header_decoded = 0;
1254
0
    ps_dec->u4_total_frames_decoded = 0;
1255
1256
0
    ps_dec->i4_error_code = 0;
1257
0
    ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1258
0
    ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0;
1259
1260
0
    ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS;
1261
0
    ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
1262
0
    ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
1263
0
    ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
1264
0
    ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
1265
1266
0
    ps_dec->u1_pr_sl_type = 0xFF;
1267
0
    ps_dec->u2_mbx = 0xffff;
1268
0
    ps_dec->u2_mby = 0;
1269
0
    ps_dec->u4_total_mbs_coded = 0;
1270
1271
    /* POC initializations */
1272
0
    ps_prev_poc = &ps_dec->s_prev_pic_poc;
1273
0
    ps_cur_poc = &ps_dec->s_cur_pic_poc;
1274
0
    ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
1275
0
    ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
1276
0
    ps_prev_poc->i4_delta_pic_order_cnt_bottom =
1277
0
                    ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
1278
0
    ps_prev_poc->i4_delta_pic_order_cnt[0] =
1279
0
                    ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
1280
0
    ps_prev_poc->i4_delta_pic_order_cnt[1] =
1281
0
                    ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
1282
0
    ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1283
0
    ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count =
1284
0
                    0;
1285
0
    ps_prev_poc->i4_bottom_field_order_count =
1286
0
                    ps_cur_poc->i4_bottom_field_order_count = 0;
1287
0
    ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
1288
0
    ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1289
0
    ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
1290
0
    ps_cur_slice->u1_mmco_equalto5 = 0;
1291
0
    ps_cur_slice->u2_frame_num = 0;
1292
1293
0
    ps_dec->i4_max_poc = 0;
1294
0
    ps_dec->i4_prev_max_display_seq = 0;
1295
0
    ps_dec->u4_recon_mb_grp = 4;
1296
0
    ps_dec->i4_reorder_depth = -1;
1297
1298
    /* Field PIC initializations */
1299
0
    ps_dec->u1_second_field = 0;
1300
0
    ps_dec->s_prev_seq_params.u1_eoseq_pending = 0;
1301
1302
    /* Set the cropping parameters as zero */
1303
0
    ps_dec->u2_crop_offset_y = 0;
1304
0
    ps_dec->u2_crop_offset_uv = 0;
1305
1306
    /* The Initial Frame Rate Info is not Present */
1307
0
    ps_dec->i4_vui_frame_rate = -1;
1308
0
    ps_dec->i4_pic_type = NA_SLICE;
1309
0
    ps_dec->i4_frametype = IV_NA_FRAME;
1310
0
    ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1311
1312
0
    ps_dec->u1_res_changed = 0;
1313
1314
1315
0
    ps_dec->u1_frame_decoded_flag = 0;
1316
1317
    /* Set the default frame seek mask mode */
1318
0
    ps_dec->u4_skip_frm_mask = SKIP_NONE;
1319
1320
    /********************************************************/
1321
    /* Initialize CAVLC residual decoding function pointers */
1322
    /********************************************************/
1323
0
    ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
1324
0
    ps_dec->pf_cavlc_4x4res_block[1] =
1325
0
                    ih264d_cavlc_4x4res_block_totalcoeff_2to10;
1326
0
    ps_dec->pf_cavlc_4x4res_block[2] =
1327
0
                    ih264d_cavlc_4x4res_block_totalcoeff_11to16;
1328
1329
0
    ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
1330
0
    ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
1331
1332
0
    ps_dec->pf_cavlc_parse_8x8block[0] =
1333
0
                    ih264d_cavlc_parse_8x8block_none_available;
1334
0
    ps_dec->pf_cavlc_parse_8x8block[1] =
1335
0
                    ih264d_cavlc_parse_8x8block_left_available;
1336
0
    ps_dec->pf_cavlc_parse_8x8block[2] =
1337
0
                    ih264d_cavlc_parse_8x8block_top_available;
1338
0
    ps_dec->pf_cavlc_parse_8x8block[3] =
1339
0
                    ih264d_cavlc_parse_8x8block_both_available;
1340
1341
    /***************************************************************************/
1342
    /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */
1343
    /***************************************************************************/
1344
0
    ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
1345
0
    ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
1346
1347
0
    ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
1348
0
    ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
1349
1350
0
    ps_dec->pf_fill_bs_xtra_left_edge[0] =
1351
0
                    ih264d_fill_bs_xtra_left_edge_cur_frm;
1352
0
    ps_dec->pf_fill_bs_xtra_left_edge[1] =
1353
0
                    ih264d_fill_bs_xtra_left_edge_cur_fld;
1354
1355
    /* Initialize Reference Pic Buffers */
1356
0
    ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr);
1357
1358
0
    ps_dec->u2_prv_frame_num = 0;
1359
0
    ps_dec->u1_top_bottom_decoded = 0;
1360
0
    ps_dec->u1_dangling_field = 0;
1361
1362
0
    ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
1363
1364
0
    ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0];
1365
0
    ps_dec->pi1_left_ref_idx_ctxt_inc =
1366
0
                    &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0];
1367
0
    ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb;
1368
1369
    /* ! */
1370
    /* Initializing flush frame u4_flag */
1371
0
    ps_dec->u1_flushfrm = 0;
1372
1373
0
    {
1374
0
        ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec;
1375
0
        ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec;
1376
0
        ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec;
1377
0
        ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec;
1378
0
    }
1379
1380
0
    memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
1381
0
    memset(ps_dec->u4_disp_buf_mapping, 0,
1382
0
           (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1383
0
    memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1384
0
           (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1385
0
    memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t));
1386
1387
0
    ih264d_init_arch(ps_dec);
1388
0
    ih264d_init_function_ptr(ps_dec);
1389
0
    ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
1390
0
    ps_dec->init_done = 1;
1391
1392
0
}
1393
1394
WORD32 ih264d_join_threads(dec_struct_t *ps_dec)
1395
0
{
1396
0
    if(ps_dec->i4_threads_active)
1397
0
    {
1398
        /* Wait for threads */
1399
0
        ps_dec->i4_break_threads = 1;
1400
0
        if(ps_dec->u4_dec_thread_created)
1401
0
        {
1402
0
            ithread_mutex_lock(ps_dec->apv_proc_start_mutex[0]);
1403
1404
0
            ps_dec->ai4_process_start[0] = PROC_START;
1405
1406
0
            ithread_cond_signal(ps_dec->apv_proc_start_condition[0]);
1407
1408
0
            ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[0]);
1409
1410
0
            ithread_join(ps_dec->pv_dec_thread_handle, NULL);
1411
1412
0
            ps_dec->u4_dec_thread_created = 0;
1413
0
        }
1414
1415
0
        if(ps_dec->u4_bs_deblk_thread_created)
1416
0
        {
1417
0
            ithread_mutex_lock(ps_dec->apv_proc_start_mutex[1]);
1418
1419
0
            ps_dec->ai4_process_start[1] = PROC_START;
1420
1421
0
            ithread_cond_signal(ps_dec->apv_proc_start_condition[1]);
1422
1423
0
            ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[1]);
1424
1425
0
            ithread_join(ps_dec->pv_bs_deblk_thread_handle, NULL);
1426
1427
0
            ps_dec->u4_bs_deblk_thread_created = 0;
1428
0
        }
1429
0
    }
1430
0
    return IV_SUCCESS;
1431
0
}
1432
1433
WORD32 ih264d_free_static_bufs(iv_obj_t *dec_hdl)
1434
0
{
1435
0
    dec_struct_t *ps_dec;
1436
1437
0
    void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1438
0
    void *pv_mem_ctxt;
1439
1440
0
    ps_dec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1441
0
    pf_aligned_free = ps_dec->pf_aligned_free;
1442
0
    pv_mem_ctxt = ps_dec->pv_mem_ctxt;
1443
1444
0
    if(ps_dec->i4_threads_active)
1445
0
    {
1446
1447
0
        ih264d_join_threads(ps_dec);
1448
1449
        // destroy mutex and condition variable for both the threads
1450
        // 1. ih264d_decode_picture_thread
1451
        // 2. ih264d_recon_deblk_thread
1452
0
        {
1453
0
            UWORD32 i;
1454
0
            for(i = 0; i < 2; i++)
1455
0
            {
1456
0
                ithread_cond_destroy(ps_dec->apv_proc_start_condition[i]);
1457
0
                ithread_cond_destroy(ps_dec->apv_proc_done_condition[i]);
1458
1459
0
                ithread_mutex_destroy(ps_dec->apv_proc_start_mutex[i]);
1460
0
                ithread_mutex_destroy(ps_dec->apv_proc_done_mutex[i]);
1461
0
            }
1462
0
        }
1463
0
        PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->apv_proc_start_mutex[0]);
1464
0
        PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->apv_proc_start_condition[0]);
1465
0
    }
1466
1467
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sps);
1468
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pps);
1469
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_dec_thread_handle);
1470
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_bs_deblk_thread_handle);
1471
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_mgr);
1472
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred);
1473
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_disp_buf_mgr);
1474
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_pic_buf_mgr);
1475
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pic_buf_base);
1476
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_err_status);
1477
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei);
1478
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei_parse);
1479
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_cmds);
1480
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_bitstrm);
1481
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_cur_slice);
1482
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_scratch_sps_pps);
1483
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_static);
1484
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ppv_map_ref_idx_to_poc_base);
1485
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_cabac_ctxt_table_t);
1486
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mb_ctxt_info);
1487
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_ref_buff_base);
1488
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_pred1);
1489
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_temp_mc_buffer);
1490
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_init_dpb_base);
1491
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_mbaff_wt_mat);
1492
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_wts_ofsts_mat);
1493
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mvpred_addr);
1494
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_mv_buf_mgr);
1495
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_col_mv_base);
1496
0
    PS_DEC_ALIGNED_FREE(ps_dec, dec_hdl->pv_codec_handle);
1497
1498
0
    if(dec_hdl)
1499
0
    {
1500
0
        pf_aligned_free(pv_mem_ctxt, dec_hdl);
1501
0
    }
1502
0
    return IV_SUCCESS;
1503
0
}
1504
/*****************************************************************************/
1505
/*                                                                           */
1506
/*  Function Name : ih264d_create                                              */
1507
/*                                                                           */
1508
/*  Description   : creates decoder                                          */
1509
/*                                                                           */
1510
/*  Inputs        :iv_obj_t decoder handle                                   */
1511
/*                :pv_api_ip pointer to input structure                      */
1512
/*                :pv_api_op pointer to output structure                     */
1513
/*  Outputs       :                                                          */
1514
/*  Returns       : void                                                     */
1515
/*                                                                           */
1516
/*  Issues        : none                                                     */
1517
/*                                                                           */
1518
/*  Revision History:                                                        */
1519
/*                                                                           */
1520
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1521
/*         22 10 2008    100356         Draft                                */
1522
/*                                                                           */
1523
/*****************************************************************************/
1524
WORD32 ih264d_allocate_static_bufs(iv_obj_t **dec_hdl, void *pv_api_ip, void *pv_api_op)
1525
0
{
1526
0
    ih264d_create_ip_t *ps_create_ip;
1527
0
    ih264d_create_op_t *ps_create_op;
1528
0
    void *pv_buf;
1529
0
    UWORD8 *pu1_buf;
1530
0
    dec_struct_t *ps_dec;
1531
0
    void *(*pf_aligned_alloc)(void *pv_mem_ctxt, WORD32 alignment, WORD32 size);
1532
0
    void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1533
0
    void *pv_mem_ctxt;
1534
0
    WORD32 size;
1535
1536
0
    ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1537
0
    ps_create_op = (ih264d_create_op_t *)pv_api_op;
1538
1539
0
    ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1540
1541
0
    pf_aligned_alloc = ps_create_ip->s_ivd_create_ip_t.pf_aligned_alloc;
1542
0
    pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1543
0
    pv_mem_ctxt  = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1544
1545
    /* Initialize return handle to NULL */
1546
0
    ps_create_op->s_ivd_create_op_t.pv_handle = NULL;
1547
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(iv_obj_t));
1548
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1549
0
    memset(pv_buf, 0, sizeof(iv_obj_t));
1550
0
    *dec_hdl = (iv_obj_t *)pv_buf;
1551
0
    ps_create_op->s_ivd_create_op_t.pv_handle = *dec_hdl;
1552
1553
0
    (*dec_hdl)->pv_codec_handle = NULL;
1554
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(dec_struct_t));
1555
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1556
0
    (*dec_hdl)->pv_codec_handle = (dec_struct_t *)pv_buf;
1557
0
    ps_dec = (dec_struct_t *)pv_buf;
1558
1559
0
    memset(ps_dec, 0, sizeof(dec_struct_t));
1560
1561
0
#ifndef LOGO_EN
1562
0
    ps_dec->u4_share_disp_buf = ps_create_ip->s_ivd_create_ip_t.u4_share_disp_buf;
1563
#else
1564
    ps_dec->u4_share_disp_buf = 0;
1565
#endif
1566
1567
0
    ps_dec->u1_chroma_format =
1568
0
                    (UWORD8)(ps_create_ip->s_ivd_create_ip_t.e_output_format);
1569
1570
0
    if((ps_dec->u1_chroma_format != IV_YUV_420P)
1571
0
                    && (ps_dec->u1_chroma_format
1572
0
                                    != IV_YUV_420SP_UV)
1573
0
                    && (ps_dec->u1_chroma_format
1574
0
                                    != IV_YUV_420SP_VU))
1575
0
    {
1576
0
        ps_dec->u4_share_disp_buf = 0;
1577
0
    }
1578
1579
0
    ps_dec->u1_enable_mb_info = ps_create_ip->u4_enable_frame_info;
1580
0
    ps_dec->pf_aligned_alloc = pf_aligned_alloc;
1581
0
    ps_dec->pf_aligned_free = pf_aligned_free;
1582
0
    ps_dec->pv_mem_ctxt = pv_mem_ctxt;
1583
0
    ps_dec->i4_threads_active = ps_create_ip->u4_keep_threads_active;
1584
1585
1586
0
    size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS);
1587
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1588
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1589
0
    memset(pv_buf, 0, size);
1590
0
    ps_dec->ps_sps = pv_buf;
1591
1592
0
    size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS;
1593
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1594
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1595
0
    memset(pv_buf, 0, size);
1596
0
    ps_dec->ps_pps = pv_buf;
1597
1598
0
    size = ithread_get_handle_size();
1599
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1600
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1601
0
    memset(pv_buf, 0, size);
1602
0
    ps_dec->pv_dec_thread_handle = pv_buf;
1603
1604
0
    size = ithread_get_handle_size();
1605
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1606
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1607
0
    memset(pv_buf, 0, size);
1608
0
    ps_dec->pv_bs_deblk_thread_handle = pv_buf;
1609
1610
0
    if(ps_dec->i4_threads_active)
1611
0
    {
1612
0
        UWORD32 i;
1613
        /* Request memory to hold mutex (start/done) for both threads */
1614
0
        size = ithread_get_mutex_lock_size() << 2;
1615
0
        pv_buf = pf_aligned_alloc(pv_mem_ctxt, 8, size);
1616
0
        RETURN_IF((NULL == pv_buf), IV_FAIL);
1617
0
        memset(pv_buf, 0, size);
1618
1619
        // init mutex variable for both the threads
1620
        // 1. ih264d_decode_picture_thread
1621
        // 2. ih264d_recon_deblk_thread
1622
0
        for(i = 0; i < 2; i++)
1623
0
        {
1624
0
            WORD32 ret;
1625
0
            WORD32 mutex_size = ithread_get_mutex_lock_size();
1626
1627
0
            ps_dec->apv_proc_start_mutex[i] =
1628
0
                            (UWORD8 *)pv_buf + (2 * i * mutex_size);
1629
0
            ps_dec->apv_proc_done_mutex[i] =
1630
0
                            (UWORD8 *)pv_buf + ((2 * i + 1) * mutex_size);
1631
1632
0
            ret = ithread_mutex_init(ps_dec->apv_proc_start_mutex[i]);
1633
0
            RETURN_IF((ret != IV_SUCCESS), ret);
1634
1635
0
            ret = ithread_mutex_init(ps_dec->apv_proc_done_mutex[i]);
1636
0
            RETURN_IF((ret != IV_SUCCESS), ret);
1637
0
        }
1638
1639
0
        size = ithread_get_cond_struct_size() << 2;
1640
0
        pv_buf = pf_aligned_alloc(pv_mem_ctxt, 8, size);
1641
0
        RETURN_IF((NULL == pv_buf), IV_FAIL);
1642
0
        memset(pv_buf, 0, size);
1643
1644
        // init condition variable for both the threads
1645
0
        for(i = 0; i < 2; i++)
1646
0
        {
1647
0
            WORD32 ret;
1648
0
            WORD32 cond_size = ithread_get_cond_struct_size();
1649
0
            ps_dec->apv_proc_start_condition[i] =
1650
0
                            (UWORD8 *)pv_buf + (2 * i * cond_size);
1651
0
            ps_dec->apv_proc_done_condition[i] =
1652
0
                            (UWORD8 *)pv_buf + ((2 * i + 1) * cond_size);
1653
1654
0
            ret = ithread_cond_init(ps_dec->apv_proc_start_condition[i]);
1655
0
            RETURN_IF((ret != IV_SUCCESS), ret);
1656
1657
0
            ret = ithread_cond_init(ps_dec->apv_proc_done_condition[i]);
1658
0
            RETURN_IF((ret != IV_SUCCESS), ret);
1659
0
        }
1660
0
    }
1661
1662
0
    size = sizeof(dpb_manager_t);
1663
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1664
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1665
0
    memset(pv_buf, 0, size);
1666
0
    ps_dec->ps_dpb_mgr = pv_buf;
1667
1668
0
    size = sizeof(pred_info_t) * 2 * 32;
1669
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1670
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1671
0
    memset(pv_buf, 0, size);
1672
0
    ps_dec->ps_pred = pv_buf;
1673
1674
0
    size = sizeof(disp_mgr_t);
1675
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1676
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1677
0
    memset(pv_buf, 0, size);
1678
0
    ps_dec->pv_disp_buf_mgr = pv_buf;
1679
1680
0
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1681
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1682
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1683
0
    memset(pv_buf, 0, size);
1684
0
    ps_dec->pv_pic_buf_mgr = pv_buf;
1685
1686
0
    size = sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2);
1687
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1688
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1689
0
    memset(pv_buf, 0, size);
1690
0
    ps_dec->ps_pic_buf_base = pv_buf;
1691
1692
0
    size = sizeof(dec_err_status_t);
1693
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1694
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1695
0
    memset(pv_buf, 0, size);
1696
0
    ps_dec->ps_dec_err_status = (dec_err_status_t *)pv_buf;
1697
1698
0
    size = sizeof(sei);
1699
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1700
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1701
0
    memset(pv_buf, 0, size);
1702
0
    ps_dec->ps_sei = (sei *)pv_buf;
1703
1704
0
    size = sizeof(sei);
1705
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1706
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1707
0
    memset(pv_buf, 0, size);
1708
0
    ps_dec->ps_sei_parse = (sei *)pv_buf;
1709
1710
0
    size = sizeof(dpb_commands_t);
1711
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1712
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1713
0
    memset(pv_buf, 0, size);
1714
0
    ps_dec->ps_dpb_cmds = (dpb_commands_t *)pv_buf;
1715
1716
0
    size = sizeof(dec_bit_stream_t);
1717
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1718
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1719
0
    memset(pv_buf, 0, size);
1720
0
    ps_dec->ps_bitstrm = (dec_bit_stream_t *)pv_buf;
1721
1722
0
    size = sizeof(dec_slice_params_t);
1723
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1724
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1725
0
    memset(pv_buf, 0, size);
1726
0
    ps_dec->ps_cur_slice = (dec_slice_params_t *)pv_buf;
1727
1728
0
    size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1729
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1730
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1731
0
    memset(pv_buf, 0, size);
1732
0
    ps_dec->pv_scratch_sps_pps = pv_buf;
1733
1734
1735
0
    ps_dec->u4_static_bits_buf_size = 256000;
1736
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, ps_dec->u4_static_bits_buf_size);
1737
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1738
0
    memset(pv_buf, 0, ps_dec->u4_static_bits_buf_size);
1739
0
    ps_dec->pu1_bits_buf_static = pv_buf;
1740
1741
1742
0
    size = ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC)
1743
0
                        * sizeof(void *));
1744
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1745
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1746
0
    ps_dec->ppv_map_ref_idx_to_poc_base = pv_buf;
1747
0
    memset(ps_dec->ppv_map_ref_idx_to_poc_base, 0, size);
1748
1749
0
    ps_dec->ppv_map_ref_idx_to_poc = ps_dec->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC;
1750
1751
1752
0
    size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
1753
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1754
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1755
0
    memset(pv_buf, 0, size);
1756
0
    ps_dec->p_cabac_ctxt_table_t = pv_buf;
1757
1758
1759
1760
0
    size = sizeof(ctxt_inc_mb_info_t);
1761
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1762
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1763
0
    memset(pv_buf, 0, size);
1764
0
    ps_dec->ps_left_mb_ctxt_info = pv_buf;
1765
1766
1767
1768
0
    size = MAX_REF_BUF_SIZE * 2;
1769
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1770
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1771
0
    memset(pv_buf, 0, size);
1772
0
    ps_dec->pu1_ref_buff_base = pv_buf;
1773
0
    ps_dec->pu1_ref_buff = ps_dec->pu1_ref_buff_base + MAX_REF_BUF_SIZE;
1774
1775
1776
0
    size = ((sizeof(WORD16)) * PRED_BUFFER_WIDTH
1777
0
                        * PRED_BUFFER_HEIGHT * 2);
1778
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1779
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1780
0
    memset(pv_buf, 0, size);
1781
0
    ps_dec->pi2_pred1 = pv_buf;
1782
1783
1784
0
    size = sizeof(UWORD8) * (MB_LUM_SIZE);
1785
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1786
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1787
0
    memset(pv_buf, 0, size);
1788
0
    ps_dec->pu1_temp_mc_buffer = pv_buf;
1789
1790
1791
1792
1793
0
    size = 8 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
1794
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1795
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1796
0
    memset(pv_buf, 0, size);
1797
1798
0
    ps_dec->pu1_init_dpb_base = pv_buf;
1799
0
    pu1_buf = pv_buf;
1800
0
    ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = (struct pic_buffer_t *)pu1_buf;
1801
1802
0
    pu1_buf += size / 2;
1803
0
    ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = (struct pic_buffer_t *)pu1_buf;
1804
1805
0
    size = (sizeof(UWORD32) * 2 * 3
1806
0
                        * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)) * 2);
1807
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1808
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1809
0
    memset(pv_buf, 0, size);
1810
0
    ps_dec->pu4_mbaff_wt_mat = pv_buf;
1811
1812
0
    size = sizeof(UWORD32) * 2 * 3
1813
0
                        * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1));
1814
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1815
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1816
0
    memset(pv_buf, 0, size);
1817
0
    ps_dec->pu4_wts_ofsts_mat = pv_buf;
1818
1819
1820
0
    size = (sizeof(neighbouradd_t) << 2);
1821
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1822
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1823
0
    memset(pv_buf, 0, size);
1824
0
    ps_dec->ps_left_mvpred_addr = pv_buf;
1825
1826
1827
0
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1828
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1829
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1830
0
    memset(pv_buf, 0, size);
1831
0
    ps_dec->pv_mv_buf_mgr = pv_buf;
1832
1833
1834
0
    size =  sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2);
1835
0
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1836
0
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1837
0
    ps_dec->ps_col_mv_base = pv_buf;
1838
0
    memset(ps_dec->ps_col_mv_base, 0, size);
1839
1840
0
    ih264d_init_decoder(ps_dec);
1841
1842
0
    return IV_SUCCESS;
1843
0
}
1844
1845
1846
/*****************************************************************************/
1847
/*                                                                           */
1848
/*  Function Name : ih264d_create                                              */
1849
/*                                                                           */
1850
/*  Description   : creates decoder                                          */
1851
/*                                                                           */
1852
/*  Inputs        :iv_obj_t decoder handle                                   */
1853
/*                :pv_api_ip pointer to input structure                      */
1854
/*                :pv_api_op pointer to output structure                     */
1855
/*  Outputs       :                                                          */
1856
/*  Returns       : void                                                     */
1857
/*                                                                           */
1858
/*  Issues        : none                                                     */
1859
/*                                                                           */
1860
/*  Revision History:                                                        */
1861
/*                                                                           */
1862
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1863
/*         22 10 2008    100356         Draft                                */
1864
/*                                                                           */
1865
/*****************************************************************************/
1866
WORD32 ih264d_create(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1867
0
{
1868
0
    ih264d_create_ip_t *ps_create_ip;
1869
0
    ih264d_create_op_t *ps_create_op;
1870
1871
0
    WORD32 ret;
1872
1873
0
    ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1874
0
    ps_create_op = (ih264d_create_op_t *)pv_api_op;
1875
1876
0
    ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1877
0
    dec_hdl = NULL;
1878
0
    ret = ih264d_allocate_static_bufs(&dec_hdl, pv_api_ip, pv_api_op);
1879
1880
    /* If allocation of some buffer fails, then free buffers allocated till then */
1881
0
    if(IV_FAIL == ret)
1882
0
    {
1883
0
        if(dec_hdl)
1884
0
        {
1885
0
            if(dec_hdl->pv_codec_handle)
1886
0
            {
1887
0
                ih264d_free_static_bufs(dec_hdl);
1888
0
            }
1889
0
            else
1890
0
            {
1891
0
                void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1892
0
                void *pv_mem_ctxt;
1893
1894
0
                pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1895
0
                pv_mem_ctxt  = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1896
0
                pf_aligned_free(pv_mem_ctxt, dec_hdl);
1897
0
            }
1898
0
        }
1899
0
        ps_create_op->s_ivd_create_op_t.u4_error_code = IVD_MEM_ALLOC_FAILED;
1900
0
        ps_create_op->s_ivd_create_op_t.u4_error_code |= 1 << IVD_FATALERROR;
1901
1902
0
        return IV_FAIL;
1903
0
    }
1904
1905
0
    return IV_SUCCESS;
1906
0
}
1907
1908
/*****************************************************************************/
1909
/*                                                                           */
1910
/*  Function Name :  ih264d_map_error                                        */
1911
/*                                                                           */
1912
/*  Description   :  Maps error codes to IVD error groups                    */
1913
/*                                                                           */
1914
/*  Inputs        :                                                          */
1915
/*  Globals       : <Does it use any global variables?>                      */
1916
/*  Outputs       :                                                          */
1917
/*  Returns       : void                                                     */
1918
/*                                                                           */
1919
/*  Issues        : none                                                     */
1920
/*                                                                           */
1921
/*  Revision History:                                                        */
1922
/*                                                                           */
1923
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1924
/*         22 10 2008    100356         Draft                                */
1925
/*                                                                           */
1926
/*****************************************************************************/
1927
UWORD32 ih264d_map_error(UWORD32 i4_err_status)
1928
85.6k
{
1929
85.6k
    UWORD32 temp = 0;
1930
1931
85.6k
    switch(i4_err_status)
1932
85.6k
    {
1933
0
        case ERROR_MEM_ALLOC_ISRAM_T:
1934
0
        case ERROR_MEM_ALLOC_SDRAM_T:
1935
0
        case ERROR_BUF_MGR:
1936
0
        case ERROR_MB_GROUP_ASSGN_T:
1937
0
        case ERROR_FRAME_LIMIT_OVER:
1938
0
        case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT:
1939
0
        case ERROR_PROFILE_NOT_SUPPORTED:
1940
0
        case ERROR_INIT_NOT_DONE:
1941
0
        case IVD_MEM_ALLOC_FAILED:
1942
605
        case ERROR_FEATURE_UNAVAIL:
1943
1.09k
        case IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED:
1944
1.09k
            temp = 1 << IVD_FATALERROR;
1945
1.09k
            H264_DEC_DEBUG_PRINT("\nFatal Error\n");
1946
1.09k
            break;
1947
1948
0
        case ERROR_DBP_MANAGER_T:
1949
0
        case ERROR_GAPS_IN_FRM_NUM:
1950
0
        case ERROR_UNKNOWN_NAL:
1951
0
        case ERROR_INV_MB_SLC_GRP_T:
1952
0
        case ERROR_MULTIPLE_SLC_GRP_T:
1953
0
        case ERROR_UNKNOWN_LEVEL:
1954
0
        case ERROR_UNAVAIL_PICBUF_T:
1955
0
        case ERROR_UNAVAIL_MVBUF_T:
1956
0
        case ERROR_UNAVAIL_DISPBUF_T:
1957
109
        case ERROR_NUM_REF:
1958
109
        case ERROR_REFIDX_ORDER_T:
1959
109
        case ERROR_PIC0_NOT_FOUND_T:
1960
109
        case ERROR_MB_TYPE:
1961
109
        case ERROR_SUB_MB_TYPE:
1962
109
        case ERROR_CBP:
1963
356
        case ERROR_REF_IDX:
1964
356
        case ERROR_NUM_MV:
1965
356
        case ERROR_CHROMA_PRED_MODE:
1966
356
        case ERROR_INTRAPRED:
1967
356
        case ERROR_NEXT_MB_ADDRESS_T:
1968
356
        case ERROR_MB_ADDRESS_T:
1969
356
        case ERROR_PIC1_NOT_FOUND_T:
1970
356
        case ERROR_CAVLC_NUM_COEFF_T:
1971
356
        case ERROR_CAVLC_SCAN_POS_T:
1972
356
        case ERROR_PRED_WEIGHT_TABLE_T:
1973
361
        case ERROR_CORRUPTED_SLICE:
1974
361
            temp = 1 << IVD_CORRUPTEDDATA;
1975
361
            break;
1976
1977
0
        case ERROR_NOT_SUPP_RESOLUTION:
1978
0
        case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT:
1979
0
            temp = 1 << IVD_UNSUPPORTEDINPUT;
1980
0
            break;
1981
1982
0
        case ERROR_INVALID_PIC_PARAM:
1983
4
        case ERROR_INVALID_SEQ_PARAM:
1984
4
        case ERROR_EGC_EXCEED_32_1_T:
1985
4
        case ERROR_EGC_EXCEED_32_2_T:
1986
4
        case ERROR_INV_RANGE_TEV_T:
1987
4
        case ERROR_INV_SLC_TYPE_T:
1988
76
        case ERROR_INV_POC_TYPE_T:
1989
298
        case ERROR_INV_RANGE_QP_T:
1990
1.19k
        case ERROR_INV_SPS_PPS_T:
1991
1.19k
        case ERROR_INV_SLICE_HDR_T:
1992
1.19k
        case ERROR_INV_SEI_MDCV_PARAMS:
1993
1.19k
        case ERROR_INV_SEI_CLL_PARAMS:
1994
1.20k
        case ERROR_INV_SEI_AVE_PARAMS:
1995
1.22k
        case ERROR_INV_SEI_CCV_PARAMS:
1996
1.22k
        case ERROR_INV_SEI_SII_PARAMS:
1997
1998
1.22k
            temp = 1 << IVD_CORRUPTEDHEADER;
1999
1.22k
            break;
2000
2001
0
        case ERROR_EOB_FLUSHBITS_T:
2002
422
        case ERROR_EOB_GETBITS_T:
2003
422
        case ERROR_EOB_GETBIT_T:
2004
422
        case ERROR_EOB_BYPASS_T:
2005
422
        case ERROR_EOB_DECISION_T:
2006
422
        case ERROR_EOB_TERMINATE_T:
2007
422
        case ERROR_EOB_READCOEFF4X4CAB_T:
2008
422
            temp = 1 << IVD_INSUFFICIENTDATA;
2009
422
            break;
2010
0
        case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED:
2011
0
        case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH:
2012
0
            temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR;
2013
0
            break;
2014
2015
0
        case ERROR_DANGLING_FIELD_IN_PIC:
2016
0
            temp = 1 << IVD_APPLIEDCONCEALMENT;
2017
0
            break;
2018
2019
85.6k
    }
2020
2021
85.6k
    return temp;
2022
2023
85.6k
}
2024
2025
UWORD32 ih264d_get_outbuf_size(WORD32 pic_wd,
2026
                               UWORD32 pic_ht,
2027
                               UWORD8 u1_chroma_format,
2028
                               UWORD32 *p_buf_size)
2029
139k
{
2030
139k
    UWORD32 u4_min_num_out_bufs = 0;
2031
2032
139k
    if(u1_chroma_format == IV_YUV_420P)
2033
71.2k
        u4_min_num_out_bufs = MIN_OUT_BUFS_420;
2034
68.5k
    else if(u1_chroma_format == IV_YUV_422ILE)
2035
0
        u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
2036
68.5k
    else if(u1_chroma_format == IV_RGB_565)
2037
0
        u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
2038
68.5k
    else if((u1_chroma_format == IV_YUV_420SP_UV)
2039
28.0k
                    || (u1_chroma_format == IV_YUV_420SP_VU))
2040
68.5k
        u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
2041
2042
139k
    if(u1_chroma_format == IV_YUV_420P)
2043
71.2k
    {
2044
71.2k
        p_buf_size[0] = (pic_wd * pic_ht);
2045
71.2k
        p_buf_size[1] = (pic_wd * pic_ht) >> 2;
2046
71.2k
        p_buf_size[2] = (pic_wd * pic_ht) >> 2;
2047
71.2k
    }
2048
68.5k
    else if(u1_chroma_format == IV_YUV_422ILE)
2049
0
    {
2050
0
        p_buf_size[0] = (pic_wd * pic_ht) * 2;
2051
0
        p_buf_size[1] = p_buf_size[2] = 0;
2052
0
    }
2053
68.5k
    else if(u1_chroma_format == IV_RGB_565)
2054
0
    {
2055
0
        p_buf_size[0] = (pic_wd * pic_ht) * 2;
2056
0
        p_buf_size[1] = p_buf_size[2] = 0;
2057
0
    }
2058
68.5k
    else if((u1_chroma_format == IV_YUV_420SP_UV)
2059
28.0k
                    || (u1_chroma_format == IV_YUV_420SP_VU))
2060
68.5k
    {
2061
68.5k
        p_buf_size[0] = (pic_wd * pic_ht);
2062
68.5k
        p_buf_size[1] = (pic_wd * pic_ht) >> 1;
2063
68.5k
        p_buf_size[2] = 0;
2064
68.5k
    }
2065
2066
139k
    return u4_min_num_out_bufs;
2067
139k
}
2068
2069
WORD32 check_app_out_buf_size(dec_struct_t *ps_dec)
2070
139k
{
2071
139k
    UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
2072
139k
    UWORD32 u4_min_num_out_bufs, i;
2073
139k
    UWORD32 pic_wd, pic_ht;
2074
2075
139k
    if(0 == ps_dec->u4_share_disp_buf)
2076
139k
    {
2077
139k
        pic_wd = ps_dec->u2_disp_width;
2078
139k
        pic_ht = ps_dec->u2_disp_height;
2079
2080
139k
    }
2081
0
    else
2082
0
    {
2083
0
        pic_wd = ps_dec->u2_frm_wd_y;
2084
0
        pic_ht = ps_dec->u2_frm_ht_y;
2085
0
    }
2086
2087
139k
    if(ps_dec->u4_app_disp_width > pic_wd)
2088
0
        pic_wd = ps_dec->u4_app_disp_width;
2089
2090
139k
    u4_min_num_out_bufs = ih264d_get_outbuf_size(pic_wd, pic_ht,
2091
139k
                                                 ps_dec->u1_chroma_format,
2092
139k
                                                 &au4_min_out_buf_size[0]);
2093
2094
2095
139k
    if(0 == ps_dec->u4_share_disp_buf)
2096
139k
    {
2097
139k
        if(ps_dec->ps_out_buffer->u4_num_bufs < u4_min_num_out_bufs)
2098
0
            return IV_FAIL;
2099
2100
486k
        for(i = 0; i < u4_min_num_out_bufs; i++)
2101
348k
        {
2102
348k
            if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i]
2103
348k
                            < au4_min_out_buf_size[i])
2104
1.39k
                return (IV_FAIL);
2105
348k
        }
2106
139k
    }
2107
0
    else
2108
0
    {
2109
0
        if(ps_dec->disp_bufs[0].u4_num_bufs < u4_min_num_out_bufs)
2110
0
            return IV_FAIL;
2111
2112
0
        for(i = 0; i < u4_min_num_out_bufs; i++)
2113
0
        {
2114
            /* We need to check only with the disp_buffer[0], because we have
2115
             * already ensured that all the buffers are of the same size in
2116
             * ih264d_set_display_frame.
2117
             */
2118
0
            if(ps_dec->disp_bufs[0].u4_bufsize[i] < au4_min_out_buf_size[i])
2119
0
                return (IV_FAIL);
2120
0
        }
2121
2122
0
    }
2123
2124
138k
    return (IV_SUCCESS);
2125
139k
}
2126
2127
2128
/*****************************************************************************/
2129
/*                                                                           */
2130
/*  Function Name :  ih264d_video_decode                                     */
2131
/*                                                                           */
2132
/*  Description   :  handle video decode API command                         */
2133
/*                                                                           */
2134
/*  Inputs        :iv_obj_t decoder handle                                   */
2135
/*                :pv_api_ip pointer to input structure                      */
2136
/*                :pv_api_op pointer to output structure                     */
2137
/*  Outputs       :                                                          */
2138
/*  Returns       : void                                                     */
2139
/*                                                                           */
2140
/*  Issues        : none                                                     */
2141
/*                                                                           */
2142
/*  Revision History:                                                        */
2143
/*                                                                           */
2144
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
2145
/*         22 10 2008    100356         Draft                                */
2146
/*                                                                           */
2147
/*****************************************************************************/
2148
2149
WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2150
0
{
2151
    /* ! */
2152
2153
0
    dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2154
2155
0
    WORD32 i4_err_status = 0;
2156
0
    UWORD8 *pu1_buf = NULL;
2157
0
    WORD32 buflen;
2158
0
    UWORD32 u4_max_ofst, u4_length_of_start_code = 0;
2159
2160
0
    UWORD32 bytes_consumed = 0;
2161
0
    UWORD32 cur_slice_is_nonref = 0;
2162
0
    UWORD32 u4_next_is_aud;
2163
0
    UWORD32 u4_first_start_code_found = 0;
2164
0
    WORD32 ret = 0,api_ret_value = IV_SUCCESS;
2165
0
    WORD32 header_data_left = 0,frame_data_left = 0;
2166
0
    UWORD8 *pu1_bitstrm_buf;
2167
0
    ih264d_video_decode_ip_t *ps_h264d_dec_ip;
2168
0
    ih264d_video_decode_op_t *ps_h264d_dec_op;
2169
0
    ivd_video_decode_ip_t *ps_dec_ip;
2170
0
    ivd_video_decode_op_t *ps_dec_op;
2171
2172
0
    ithread_set_name((void*)"Parse_thread");
2173
2174
0
    ps_h264d_dec_ip = (ih264d_video_decode_ip_t *)pv_api_ip;
2175
0
    ps_h264d_dec_op = (ih264d_video_decode_op_t *)pv_api_op;
2176
0
    ps_dec_ip = &ps_h264d_dec_ip->s_ivd_video_decode_ip_t;
2177
0
    ps_dec_op = &ps_h264d_dec_op->s_ivd_video_decode_op_t;
2178
2179
0
    {
2180
0
        UWORD32 u4_size;
2181
0
        u4_size = ps_dec_op->u4_size;
2182
0
        memset(ps_h264d_dec_op, 0, ps_dec_op->u4_size);
2183
0
        ps_dec_op->u4_size = u4_size;
2184
0
    }
2185
2186
0
    ps_dec->pv_dec_out = ps_dec_op;
2187
0
    if(ps_dec->init_done != 1)
2188
0
    {
2189
0
        return IV_FAIL;
2190
0
    }
2191
2192
    /*Data memory barries instruction,so that bitstream write by the application is complete*/
2193
0
    DATA_SYNC();
2194
2195
0
    if(0 == ps_dec->u1_flushfrm)
2196
0
    {
2197
0
        if(ps_dec_ip->pv_stream_buffer == NULL)
2198
0
        {
2199
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2200
0
            ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
2201
0
            return IV_FAIL;
2202
0
        }
2203
0
        if(ps_dec_ip->u4_num_Bytes <= 0)
2204
0
        {
2205
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2206
0
            ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV;
2207
0
            return IV_FAIL;
2208
2209
0
        }
2210
0
    }
2211
0
    ps_dec->u1_pic_decode_done = 0;
2212
2213
0
    if(ps_dec->i4_threads_active)
2214
0
    {
2215
0
        UWORD32 i;
2216
0
        ps_dec->i4_break_threads = 0;
2217
0
        for (i = 0; i < 2; i++)
2218
0
        {
2219
0
            ret = ithread_mutex_lock(ps_dec->apv_proc_start_mutex[i]);
2220
0
            RETURN_IF((ret != IV_SUCCESS), ret);
2221
2222
0
            ps_dec->ai4_process_start[i] = PROC_INIT;
2223
2224
0
            ret = ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[i]);
2225
0
            RETURN_IF((ret != IV_SUCCESS), ret);
2226
0
        }
2227
0
    }
2228
0
    else {
2229
0
        ps_dec->u4_dec_thread_created = 0;
2230
0
        ps_dec->u4_bs_deblk_thread_created = 0;
2231
0
    }
2232
2233
0
    ps_dec_op->u4_num_bytes_consumed = 0;
2234
0
    ps_dec_op->i4_reorder_depth = -1;
2235
0
    ps_dec_op->i4_display_index = DEFAULT_POC;
2236
0
    ps_dec->ps_out_buffer = NULL;
2237
2238
0
    if(ps_dec_ip->u4_size
2239
0
                    >= offsetof(ivd_video_decode_ip_t, s_out_buffer))
2240
0
        ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer;
2241
2242
0
    ps_dec->u4_fmt_conv_cur_row = 0;
2243
2244
0
    ps_dec->u4_output_present = 0;
2245
0
    ps_dec->s_disp_op.u4_error_code = 1;
2246
0
    ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS;
2247
0
    if(0 == ps_dec->u4_share_disp_buf
2248
0
                    && ps_dec->i4_decode_header == 0)
2249
0
    {
2250
0
        UWORD32 i;
2251
0
        if((ps_dec->ps_out_buffer->u4_num_bufs == 0) ||
2252
0
           (ps_dec->ps_out_buffer->u4_num_bufs > IVD_VIDDEC_MAX_IO_BUFFERS))
2253
0
        {
2254
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2255
0
            ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2256
0
            return IV_FAIL;
2257
0
        }
2258
2259
0
        for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++)
2260
0
        {
2261
0
            if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL)
2262
0
            {
2263
0
                ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2264
0
                ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2265
0
                return IV_FAIL;
2266
0
            }
2267
2268
0
            if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0)
2269
0
            {
2270
0
                ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2271
0
                ps_dec_op->u4_error_code |=
2272
0
                                IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2273
0
                return IV_FAIL;
2274
0
            }
2275
0
        }
2276
0
    }
2277
2278
0
    if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT)
2279
0
    {
2280
0
        ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER;
2281
0
        return IV_FAIL;
2282
0
    }
2283
2284
    /* ! */
2285
0
    ps_dec->u4_ts = ps_dec_ip->u4_ts;
2286
2287
0
    ps_dec_op->u4_error_code = 0;
2288
0
    ps_dec_op->e_pic_type = IV_NA_FRAME;
2289
0
    ps_dec_op->u4_output_present = 0;
2290
0
    ps_dec_op->u4_frame_decoded_flag = 0;
2291
2292
0
    ps_dec->i4_frametype = IV_NA_FRAME;
2293
0
    ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
2294
2295
0
    ps_dec->u4_slice_start_code_found = 0;
2296
2297
    /* In case the decoder is not in flush mode(in shared mode),
2298
     then decoder has to pick up a buffer to write current frame.
2299
     Check if a frame is available in such cases */
2300
2301
0
    if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1
2302
0
                    && ps_dec->u1_flushfrm == 0)
2303
0
    {
2304
0
        UWORD32 i;
2305
2306
0
        WORD32 disp_avail = 0, free_id;
2307
2308
        /* Check if at least one buffer is available with the codec */
2309
        /* If not then return to application with error */
2310
0
        for(i = 0; i < ps_dec->u1_pic_bufs; i++)
2311
0
        {
2312
0
            if(0 == ps_dec->u4_disp_buf_mapping[i]
2313
0
                            || 1 == ps_dec->u4_disp_buf_to_be_freed[i])
2314
0
            {
2315
0
                disp_avail = 1;
2316
0
                break;
2317
0
            }
2318
2319
0
        }
2320
2321
0
        if(0 == disp_avail)
2322
0
        {
2323
            /* If something is queued for display wait for that buffer to be returned */
2324
2325
0
            ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2326
0
            ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
2327
0
            return (IV_FAIL);
2328
0
        }
2329
2330
0
        while(1)
2331
0
        {
2332
0
            pic_buffer_t *ps_pic_buf;
2333
0
            ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free(
2334
0
                            (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id);
2335
2336
0
            if(ps_pic_buf == NULL)
2337
0
            {
2338
0
                UWORD32 display_queued = 0;
2339
2340
                /* check if any buffer was given for display which is not returned yet */
2341
0
                for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
2342
0
                {
2343
0
                    if(0 != ps_dec->u4_disp_buf_mapping[i])
2344
0
                    {
2345
0
                        display_queued = 1;
2346
0
                        break;
2347
0
                    }
2348
0
                }
2349
                /* If some buffer is queued for display, then codec has to singal an error and wait
2350
                 for that buffer to be returned.
2351
                 If nothing is queued for display then codec has ownership of all display buffers
2352
                 and it can reuse any of the existing buffers and continue decoding */
2353
2354
0
                if(1 == display_queued)
2355
0
                {
2356
                    /* If something is queued for display wait for that buffer to be returned */
2357
0
                    ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2358
0
                    ps_dec_op->u4_error_code |= (1
2359
0
                                    << IVD_UNSUPPORTEDPARAM);
2360
0
                    return (IV_FAIL);
2361
0
                }
2362
0
            }
2363
0
            else
2364
0
            {
2365
                /* If the buffer is with display, then mark it as in use and then look for a buffer again */
2366
0
                if(1 == ps_dec->u4_disp_buf_mapping[free_id])
2367
0
                {
2368
0
                    ih264_buf_mgr_set_status(
2369
0
                                    (buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2370
0
                                    free_id,
2371
0
                                    BUF_MGR_IO);
2372
0
                }
2373
0
                else
2374
0
                {
2375
                    /**
2376
                     *  Found a free buffer for present call. Release it now.
2377
                     *  Will be again obtained later.
2378
                     */
2379
0
                    ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2380
0
                                          free_id,
2381
0
                                          BUF_MGR_IO);
2382
0
                    break;
2383
0
                }
2384
0
            }
2385
0
        }
2386
2387
0
    }
2388
2389
0
    if(ps_dec->u1_enable_mb_info && (ps_dec->i4_header_decoded & DECODED_SPS_MASK))
2390
0
    {
2391
0
        UWORD32 blk_qp_map_size = ps_h264d_dec_ip->u4_8x8_blk_qp_map_size;
2392
0
        UWORD32 blk_type_map_size = ps_h264d_dec_ip->u4_8x8_blk_type_map_size;
2393
0
        UWORD32 blk_8x8_map_size = ps_dec->u4_total_mbs << 2;
2394
0
        if ((ps_h264d_dec_ip->pu1_8x8_blk_qp_map && blk_qp_map_size < blk_8x8_map_size) ||
2395
0
            (ps_h264d_dec_ip->pu1_8x8_blk_type_map && blk_type_map_size < blk_8x8_map_size))
2396
0
        {
2397
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2398
0
            ps_dec_op->u4_error_code |= IH264D_INSUFFICIENT_METADATA_BUFFER;
2399
0
            return IV_FAIL;
2400
0
        }
2401
0
    }
2402
2403
0
    if(ps_dec->u1_flushfrm)
2404
0
    {
2405
0
        if(ps_dec->u1_init_dec_flag == 0)
2406
0
        {
2407
            /*Come out of flush mode and return*/
2408
0
            ps_dec->u1_flushfrm = 0;
2409
0
            return (IV_FAIL);
2410
0
        }
2411
2412
2413
2414
0
        ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2415
0
                                      &(ps_dec->s_disp_op));
2416
0
        if(0 == ps_dec->s_disp_op.u4_error_code)
2417
0
        {
2418
            /* check output buffer size given by the application */
2419
0
            if(check_app_out_buf_size(ps_dec) != IV_SUCCESS)
2420
0
            {
2421
0
                ps_dec_op->u4_error_code= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2422
0
                return (IV_FAIL);
2423
0
            }
2424
2425
0
            ps_dec->u4_fmt_conv_cur_row = 0;
2426
0
            ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht;
2427
0
            ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2428
0
                                  ps_dec->u4_fmt_conv_cur_row,
2429
0
                                  ps_dec->u4_fmt_conv_num_rows);
2430
0
            ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2431
0
            ps_dec->u4_output_present = 1;
2432
2433
0
            if(ps_dec->u1_enable_mb_info)
2434
0
            {
2435
0
                UWORD32 disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2436
0
                if(ps_h264d_dec_ip->pu1_8x8_blk_qp_map)
2437
0
                {
2438
0
                    ps_h264d_dec_op->pu1_8x8_blk_qp_map = ps_h264d_dec_ip->pu1_8x8_blk_qp_map;
2439
0
                    ps_h264d_dec_op->u4_8x8_blk_qp_map_size = ps_dec->u4_total_mbs << 2;
2440
0
                    memcpy(ps_h264d_dec_op->pu1_8x8_blk_qp_map,
2441
0
                        ps_dec->as_buf_id_info_map[disp_buf_id].pu1_qp_map,
2442
0
                        ps_dec->u4_total_mbs << 2);
2443
0
                }
2444
0
                if(ps_h264d_dec_ip->pu1_8x8_blk_type_map)
2445
0
                {
2446
0
                    ps_h264d_dec_op->pu1_8x8_blk_type_map = ps_h264d_dec_ip->pu1_8x8_blk_type_map;
2447
0
                    ps_h264d_dec_op->u4_8x8_blk_type_map_size = ps_dec->u4_total_mbs << 2;
2448
0
                    memcpy(ps_h264d_dec_op->pu1_8x8_blk_type_map,
2449
0
                        ps_dec->as_buf_id_info_map[disp_buf_id].pu1_mb_type_map,
2450
0
                        ps_dec->u4_total_mbs << 2);
2451
0
                }
2452
0
            }
2453
0
        }
2454
0
        ih264d_export_sei_params(&ps_dec_op->s_sei_decode_op, ps_dec);
2455
2456
0
        ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2457
2458
0
        ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2459
0
        ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2460
0
        ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
2461
0
        ps_dec_op->i4_display_index = ps_dec->i4_display_index;
2462
2463
0
        ps_dec_op->u4_new_seq = 0;
2464
2465
0
        ps_dec_op->u4_output_present = ps_dec->u4_output_present;
2466
0
        ps_dec_op->u4_progressive_frame_flag =
2467
0
                        ps_dec->s_disp_op.u4_progressive_frame_flag;
2468
0
        ps_dec_op->e_output_format =
2469
0
                        ps_dec->s_disp_op.e_output_format;
2470
0
        ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
2471
0
        ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
2472
0
        ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
2473
0
        ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2474
2475
        /*In the case of flush ,since no frame is decoded set pic type as invalid*/
2476
0
        ps_dec_op->u4_is_ref_flag = -1;
2477
0
        ps_dec_op->e_pic_type = IV_NA_FRAME;
2478
0
        ps_dec_op->u4_frame_decoded_flag = 0;
2479
2480
0
        if(0 == ps_dec->s_disp_op.u4_error_code)
2481
0
        {
2482
0
            return (IV_SUCCESS);
2483
0
        }
2484
0
        else
2485
0
            return (IV_FAIL);
2486
2487
0
    }
2488
0
    if(ps_dec->u1_res_changed == 1)
2489
0
    {
2490
        /*if resolution has changed and all buffers have been flushed, reset decoder*/
2491
0
        ih264d_init_decoder(ps_dec);
2492
0
    }
2493
2494
0
    ps_dec->u4_cur_mb_addr = 0;
2495
0
    ps_dec->u4_total_mbs_coded = 0;
2496
0
    ps_dec->u2_cur_slice_num = 0;
2497
0
    ps_dec->cur_dec_mb_num = 0;
2498
0
    ps_dec->cur_recon_mb_num = 0;
2499
0
    ps_dec->u4_first_slice_in_pic = 1;
2500
0
    ps_dec->u1_slice_header_done = 0;
2501
0
    ps_dec->u1_dangling_field = 0;
2502
0
    ps_dec->u4_cur_bs_mb_num = 0;
2503
0
    ps_dec->u4_start_recon_deblk  = 0;
2504
0
    ps_dec->u4_sps_cnt_in_process = 0;
2505
2506
0
    DEBUG_THREADS_PRINTF(" Starting process call\n");
2507
2508
2509
0
    ps_dec->u4_pic_buf_got = 0;
2510
2511
0
    do
2512
0
    {
2513
0
        WORD32 buf_size;
2514
2515
0
        pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer
2516
0
                        + ps_dec_op->u4_num_bytes_consumed;
2517
2518
0
        u4_max_ofst = ps_dec_ip->u4_num_Bytes
2519
0
                        - ps_dec_op->u4_num_bytes_consumed;
2520
2521
        /* If dynamic bitstream buffer is not allocated and
2522
         * header decode is done, then allocate dynamic bitstream buffer
2523
         */
2524
0
        if((NULL == ps_dec->pu1_bits_buf_dynamic) &&
2525
0
           (ps_dec->i4_header_decoded & 1))
2526
0
        {
2527
0
            WORD32 size;
2528
2529
0
            void *pv_buf;
2530
0
            void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
2531
0
            size = MAX(256000, ps_dec->u2_pic_wd * ps_dec->u2_pic_ht * 3 / 2);
2532
0
            pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128,
2533
0
                                              size + EXTRA_BS_OFFSET);
2534
0
            RETURN_IF((NULL == pv_buf), IV_FAIL);
2535
0
            memset(pv_buf, 0, size + EXTRA_BS_OFFSET);
2536
0
            ps_dec->pu1_bits_buf_dynamic = pv_buf;
2537
0
            ps_dec->u4_dynamic_bits_buf_size = size;
2538
0
        }
2539
2540
0
        if(ps_dec->pu1_bits_buf_dynamic)
2541
0
        {
2542
0
            pu1_bitstrm_buf = ps_dec->pu1_bits_buf_dynamic;
2543
0
            buf_size = ps_dec->u4_dynamic_bits_buf_size;
2544
0
        }
2545
0
        else
2546
0
        {
2547
0
            pu1_bitstrm_buf = ps_dec->pu1_bits_buf_static;
2548
0
            buf_size = ps_dec->u4_static_bits_buf_size;
2549
0
        }
2550
2551
0
        u4_next_is_aud = 0;
2552
2553
0
        buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst,
2554
0
                                               &u4_length_of_start_code,
2555
0
                                               &u4_next_is_aud);
2556
2557
0
        if(buflen == -1)
2558
0
            buflen = 0;
2559
        /* Ignore bytes beyond the allocated size of intermediate buffer */
2560
        /* Since 8 bytes are read ahead, ensure 8 bytes are free at the
2561
        end of the buffer, which will be memset to 0 after emulation prevention */
2562
0
        buflen = MIN(buflen, buf_size - 8);
2563
2564
0
        bytes_consumed = buflen + u4_length_of_start_code;
2565
0
        ps_dec_op->u4_num_bytes_consumed += bytes_consumed;
2566
2567
0
        if(buflen)
2568
0
        {
2569
0
            memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code,
2570
0
                   buflen);
2571
            /* Decoder may read extra 8 bytes near end of the frame */
2572
0
            if((buflen + 8) < buf_size)
2573
0
            {
2574
0
                memset(pu1_bitstrm_buf + buflen, 0, 8);
2575
0
            }
2576
0
            u4_first_start_code_found = 1;
2577
2578
0
        }
2579
0
        else
2580
0
        {
2581
            /*start code not found*/
2582
2583
0
            if(u4_first_start_code_found == 0)
2584
0
            {
2585
                /*no start codes found in current process call*/
2586
2587
0
                ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND;
2588
0
                ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
2589
2590
0
                if(ps_dec->u4_pic_buf_got == 0)
2591
0
                {
2592
2593
0
                    ih264d_fill_output_struct_from_context(ps_dec,
2594
0
                                                           ps_dec_op);
2595
2596
0
                    ps_dec_op->u4_error_code = ps_dec->i4_error_code;
2597
0
                    ps_dec_op->u4_frame_decoded_flag = 0;
2598
2599
0
                    return (IV_FAIL);
2600
0
                }
2601
0
                else
2602
0
                {
2603
0
                    ps_dec->u1_pic_decode_done = 1;
2604
0
                    continue;
2605
0
                }
2606
0
            }
2607
0
            else
2608
0
            {
2609
                /* a start code has already been found earlier in the same process call*/
2610
0
                frame_data_left = 0;
2611
0
                header_data_left = 0;
2612
0
                continue;
2613
0
            }
2614
2615
0
        }
2616
2617
0
        ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op,
2618
0
                              pu1_bitstrm_buf, buflen);
2619
0
        if(ret != OK)
2620
0
        {
2621
0
            UWORD32 error =  ih264d_map_error(ret);
2622
0
            ps_dec_op->u4_error_code = error | ret;
2623
0
            api_ret_value = IV_FAIL;
2624
2625
0
            if((ret == IVD_RES_CHANGED)
2626
0
                            || (ret == IVD_MEM_ALLOC_FAILED)
2627
0
                            || (ret == ERROR_UNAVAIL_PICBUF_T)
2628
0
                            || (ret == ERROR_UNAVAIL_MVBUF_T)
2629
0
                            || (ret == ERROR_INV_SPS_PPS_T)
2630
0
                            || (ret == ERROR_FEATURE_UNAVAIL)
2631
0
                            || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
2632
0
                            || (ret == IVD_DISP_FRM_ZERO_OP_BUF_SIZE))
2633
0
            {
2634
0
                ps_dec->u4_slice_start_code_found = 0;
2635
0
                break;
2636
0
            }
2637
2638
0
            if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC))
2639
0
            {
2640
0
                ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2641
0
                api_ret_value = IV_FAIL;
2642
0
                break;
2643
0
            }
2644
2645
0
            if(ret == ERROR_IN_LAST_SLICE_OF_PIC)
2646
0
            {
2647
0
                api_ret_value = IV_FAIL;
2648
0
                break;
2649
0
            }
2650
2651
0
        }
2652
2653
0
        header_data_left = ((ps_dec->i4_decode_header == 1)
2654
0
                        && (ps_dec->i4_header_decoded != 3)
2655
0
                        && (ps_dec_op->u4_num_bytes_consumed
2656
0
                                        < ps_dec_ip->u4_num_Bytes));
2657
0
        frame_data_left = (((ps_dec->i4_decode_header == 0)
2658
0
                        && ((ps_dec->u1_pic_decode_done == 0)
2659
0
                                        || (u4_next_is_aud == 1)))
2660
0
                        && (ps_dec_op->u4_num_bytes_consumed
2661
0
                                        < ps_dec_ip->u4_num_Bytes));
2662
0
    }
2663
0
    while(( header_data_left == 1)||(frame_data_left == 1));
2664
2665
0
    if((ps_dec->u4_pic_buf_got == 1)
2666
0
            && (ret != IVD_MEM_ALLOC_FAILED)
2667
0
            && ps_dec->u4_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2668
0
    {
2669
        // last slice - missing/corruption
2670
0
        WORD32 num_mb_skipped;
2671
0
        WORD32 prev_slice_err;
2672
0
        pocstruct_t temp_poc;
2673
0
        WORD32 ret1;
2674
0
        WORD32 ht_in_mbs;
2675
0
        ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag);
2676
0
        num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2677
0
                            - ps_dec->u4_total_mbs_coded;
2678
2679
0
        if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0))
2680
0
            prev_slice_err = 1;
2681
0
        else
2682
0
            prev_slice_err = 2;
2683
2684
0
        if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_total_mbs_coded == 0))
2685
0
            prev_slice_err = 1;
2686
2687
0
        ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num,
2688
0
                                   &temp_poc, prev_slice_err);
2689
2690
0
        if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) ||
2691
0
                       (ret1 == ERROR_INV_SPS_PPS_T))
2692
0
        {
2693
0
            ret = ret1;
2694
0
        }
2695
0
    }
2696
2697
0
    if((ret == IVD_RES_CHANGED)
2698
0
                    || (ret == IVD_MEM_ALLOC_FAILED)
2699
0
                    || (ret == ERROR_UNAVAIL_PICBUF_T)
2700
0
                    || (ret == ERROR_UNAVAIL_MVBUF_T)
2701
0
                    || (ret == ERROR_INV_SPS_PPS_T))
2702
0
    {
2703
2704
        /* signal the decode thread */
2705
0
        ih264d_signal_decode_thread(ps_dec);
2706
        /* close deblock thread if it is not closed yet */
2707
0
        if(ps_dec->u4_num_cores == 3)
2708
0
        {
2709
0
            ih264d_signal_bs_deblk_thread(ps_dec);
2710
0
        }
2711
        /* dont consume bitstream for change in resolution case */
2712
0
        if(ret == IVD_RES_CHANGED)
2713
0
        {
2714
0
            ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2715
0
        }
2716
0
        return IV_FAIL;
2717
0
    }
2718
2719
2720
0
    if(ps_dec->u1_separate_parse)
2721
0
    {
2722
        /* If Format conversion is not complete,
2723
         complete it here */
2724
0
        if(ps_dec->u4_num_cores == 2)
2725
0
        {
2726
2727
            /*do deblocking of all mbs*/
2728
0
            if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0))
2729
0
            {
2730
0
                UWORD32 u4_num_mbs,u4_max_addr;
2731
0
                tfr_ctxt_t s_tfr_ctxt;
2732
0
                tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
2733
0
                pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr;
2734
2735
                /*BS is done for all mbs while parsing*/
2736
0
                u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1;
2737
0
                ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1;
2738
2739
2740
0
                ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt,
2741
0
                                           ps_dec->u2_frm_wd_in_mbs, 0);
2742
2743
2744
0
                u4_num_mbs = u4_max_addr
2745
0
                                - ps_dec->u4_cur_deblk_mb_num + 1;
2746
2747
0
                DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs);
2748
2749
0
                if(u4_num_mbs != 0)
2750
0
                    ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs,
2751
0
                                                   ps_tfr_cxt,1);
2752
2753
0
                ps_dec->u4_start_recon_deblk  = 0;
2754
2755
0
            }
2756
2757
0
        }
2758
2759
        /*signal the decode thread*/
2760
0
        ih264d_signal_decode_thread(ps_dec);
2761
        /* close deblock thread if it is not closed yet*/
2762
0
        if(ps_dec->u4_num_cores == 3)
2763
0
        {
2764
0
            ih264d_signal_bs_deblk_thread(ps_dec);
2765
0
        }
2766
0
    }
2767
2768
2769
0
    DATA_SYNC();
2770
2771
2772
0
    if((ps_dec_op->u4_error_code & 0xff)
2773
0
                    != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
2774
0
    {
2775
0
        ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2776
0
        ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2777
0
        ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
2778
0
    }
2779
2780
//Report if header (sps and pps) has not been decoded yet
2781
0
    if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3)
2782
0
    {
2783
0
        ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
2784
0
        api_ret_value = IV_FAIL;
2785
0
    }
2786
2787
0
    if((ps_dec->u4_pic_buf_got == 1)
2788
0
                    && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status))
2789
0
    {
2790
        /*
2791
         * For field pictures, set the bottom and top picture decoded u4_flag correctly.
2792
         */
2793
2794
0
        if(ps_dec->ps_cur_slice->u1_field_pic_flag)
2795
0
        {
2796
0
            if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag)
2797
0
            {
2798
0
                ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY;
2799
0
            }
2800
0
            else
2801
0
            {
2802
0
                ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY;
2803
0
            }
2804
0
        }
2805
0
        else
2806
0
        {
2807
0
                ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY;
2808
0
        }
2809
2810
        /* if new frame in not found (if we are still getting slices from previous frame)
2811
         * ih264d_deblock_display is not called. Such frames will not be added to reference /display
2812
         */
2813
0
        if ((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0)
2814
0
        {
2815
            /* Calling Function to deblock Picture and Display */
2816
0
            ret = ih264d_deblock_display(ps_dec);
2817
0
        }
2818
2819
2820
        /*set to complete ,as we dont support partial frame decode*/
2821
0
        if(ps_dec->i4_header_decoded == 3)
2822
0
        {
2823
0
            ps_dec->u4_total_mbs_coded = ps_dec->ps_cur_sps->u4_max_mb_addr + 1;
2824
0
        }
2825
2826
        /*Update the i4_frametype at the end of picture*/
2827
0
        if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
2828
0
        {
2829
0
            ps_dec->i4_frametype = IV_IDR_FRAME;
2830
0
        }
2831
0
        else if(ps_dec->i4_pic_type == B_SLICE)
2832
0
        {
2833
0
            ps_dec->i4_frametype = IV_B_FRAME;
2834
0
        }
2835
0
        else if(ps_dec->i4_pic_type == P_SLICE)
2836
0
        {
2837
0
            ps_dec->i4_frametype = IV_P_FRAME;
2838
0
        }
2839
0
        else if(ps_dec->i4_pic_type == I_SLICE)
2840
0
        {
2841
0
            ps_dec->i4_frametype = IV_I_FRAME;
2842
0
        }
2843
0
        else
2844
0
        {
2845
0
            H264_DEC_DEBUG_PRINT("Shouldn't come here\n");
2846
0
        }
2847
2848
        //Update the content type
2849
0
        ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag;
2850
2851
0
        ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2;
2852
0
        ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded
2853
0
                        - ps_dec->ps_cur_slice->u1_field_pic_flag;
2854
2855
0
    }
2856
2857
    /* close deblock thread if it is not closed yet*/
2858
0
    if(!ps_dec->i4_threads_active)
2859
0
    {
2860
0
        if(ps_dec->u4_num_cores == 3)
2861
0
        {
2862
0
            ih264d_signal_bs_deblk_thread(ps_dec);
2863
0
        }
2864
0
    }
2865
2866
2867
0
    {
2868
        /* In case the decoder is configured to run in low delay mode,
2869
         * then get display buffer and then format convert.
2870
         * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles
2871
         */
2872
2873
0
        if((IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode)
2874
0
                        && ps_dec->u1_init_dec_flag)
2875
0
        {
2876
2877
0
            ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2878
0
                                          &(ps_dec->s_disp_op));
2879
0
            if(0 == ps_dec->s_disp_op.u4_error_code)
2880
0
            {
2881
0
                ps_dec->u4_fmt_conv_cur_row = 0;
2882
0
                ps_dec->u4_output_present = 1;
2883
0
            }
2884
0
        }
2885
2886
0
        ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
2887
2888
        /* If Format conversion is not complete,
2889
         complete it here */
2890
0
        if(ps_dec->u4_output_present &&
2891
0
          (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht))
2892
0
        {
2893
0
            ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht
2894
0
                            - ps_dec->u4_fmt_conv_cur_row;
2895
0
            ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2896
0
                                  ps_dec->u4_fmt_conv_cur_row,
2897
0
                                  ps_dec->u4_fmt_conv_num_rows);
2898
0
            ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2899
0
        }
2900
2901
0
        ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2902
0
    }
2903
2904
0
    if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1)
2905
0
    {
2906
0
        ps_dec_op->u4_progressive_frame_flag = 1;
2907
0
        if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2908
0
        {
2909
0
            if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag)
2910
0
                            && (0 == ps_dec->ps_sps->u1_mb_aff_flag))
2911
0
                ps_dec_op->u4_progressive_frame_flag = 0;
2912
2913
0
        }
2914
0
    }
2915
2916
0
    if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded)
2917
0
    {
2918
0
        ps_dec->u1_top_bottom_decoded = 0;
2919
0
    }
2920
    /*--------------------------------------------------------------------*/
2921
    /* Do End of Pic processing.                                          */
2922
    /* Should be called only if frame was decoded in previous process call*/
2923
    /*--------------------------------------------------------------------*/
2924
0
    if(ps_dec->u4_pic_buf_got == 1)
2925
0
    {
2926
0
        if(1 == ps_dec->u1_last_pic_not_decoded)
2927
0
        {
2928
0
            ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec);
2929
2930
0
            if(ret != OK)
2931
0
                return ret;
2932
2933
0
            ret = ih264d_end_of_pic(ps_dec);
2934
0
            if(ret != OK)
2935
0
                return ret;
2936
0
        }
2937
0
        else
2938
0
        {
2939
0
            ret = ih264d_end_of_pic(ps_dec);
2940
0
            if(ret != OK)
2941
0
                return ret;
2942
0
        }
2943
2944
0
    }
2945
2946
0
    if(ps_dec->u1_enable_mb_info && ps_dec->u4_output_present)
2947
0
    {
2948
0
        UWORD32 disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2949
0
        if(ps_h264d_dec_ip->pu1_8x8_blk_qp_map)
2950
0
        {
2951
0
            ps_h264d_dec_op->pu1_8x8_blk_qp_map = ps_h264d_dec_ip->pu1_8x8_blk_qp_map;
2952
0
            ps_h264d_dec_op->u4_8x8_blk_qp_map_size = ps_dec->u4_total_mbs << 2;
2953
0
            memcpy(ps_h264d_dec_op->pu1_8x8_blk_qp_map,
2954
0
                ps_dec->as_buf_id_info_map[disp_buf_id].pu1_qp_map,
2955
0
                ps_dec->u4_total_mbs << 2);
2956
0
        }
2957
0
        if(ps_h264d_dec_ip->pu1_8x8_blk_type_map)
2958
0
        {
2959
0
            ps_h264d_dec_op->pu1_8x8_blk_type_map = ps_h264d_dec_ip->pu1_8x8_blk_type_map;
2960
0
            ps_h264d_dec_op->u4_8x8_blk_type_map_size = ps_dec->u4_total_mbs << 2;
2961
0
            memcpy(ps_h264d_dec_op->pu1_8x8_blk_type_map,
2962
0
                ps_dec->as_buf_id_info_map[disp_buf_id].pu1_mb_type_map,
2963
0
                ps_dec->u4_total_mbs << 2);
2964
0
        }
2965
0
    }
2966
2967
    /*Data memory barrier instruction,so that yuv write by the library is complete*/
2968
0
    DATA_SYNC();
2969
2970
0
    H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n",
2971
0
                         ps_dec_op->u4_num_bytes_consumed);
2972
0
    return api_ret_value;
2973
0
}
2974
2975
WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2976
0
{
2977
0
    char version_string[MAXVERSION_STRLEN + 1];
2978
0
    UWORD32 version_string_len;
2979
2980
0
    ivd_ctl_getversioninfo_ip_t *ps_ip;
2981
0
    ivd_ctl_getversioninfo_op_t *ps_op;
2982
2983
0
    ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip;
2984
0
    ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op;
2985
0
    UNUSED(dec_hdl);
2986
0
    ps_op->u4_error_code = IV_SUCCESS;
2987
2988
0
    VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
2989
0
            CODEC_VENDOR);
2990
2991
0
    if((WORD32)ps_ip->u4_version_buffer_size <= 0)
2992
0
    {
2993
0
        ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
2994
0
        return (IV_FAIL);
2995
0
    }
2996
2997
0
    version_string_len = strnlen(version_string, MAXVERSION_STRLEN) + 1;
2998
2999
0
    if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string)))
3000
0
    {
3001
0
        memcpy(ps_ip->pv_version_buffer, version_string, version_string_len);
3002
0
        ps_op->u4_error_code = IV_SUCCESS;
3003
0
    }
3004
0
    else
3005
0
    {
3006
0
        ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
3007
0
        return IV_FAIL;
3008
0
    }
3009
0
    return (IV_SUCCESS);
3010
0
}
3011
3012
/*****************************************************************************/
3013
/*                                                                           */
3014
/*  Function Name :   ih264d_get_display_frame                               */
3015
/*                                                                           */
3016
/*  Description   :                                                          */
3017
/*  Inputs        :iv_obj_t decoder handle                                   */
3018
/*                :pv_api_ip pointer to input structure                      */
3019
/*                :pv_api_op pointer to output structure                     */
3020
/*  Outputs       :                                                          */
3021
/*  Returns       : void                                                     */
3022
/*                                                                           */
3023
/*  Issues        : none                                                     */
3024
/*                                                                           */
3025
/*  Revision History:                                                        */
3026
/*                                                                           */
3027
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3028
/*         22 10 2008    100356         Draft                                */
3029
/*                                                                           */
3030
/*****************************************************************************/
3031
WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl,
3032
                                void *pv_api_ip,
3033
                                void *pv_api_op)
3034
0
{
3035
3036
0
    UNUSED(dec_hdl);
3037
0
    UNUSED(pv_api_ip);
3038
0
    UNUSED(pv_api_op);
3039
    // This function is no longer needed, output is returned in the process()
3040
0
    return IV_FAIL;
3041
0
}
3042
3043
/*****************************************************************************/
3044
/*                                                                           */
3045
/*  Function Name :  ih264d_set_display_frame                                */
3046
/*                                                                           */
3047
/*  Description   :                                                          */
3048
/*                                                                           */
3049
/*  Inputs        :iv_obj_t decoder handle                                   */
3050
/*                :pv_api_ip pointer to input structure                      */
3051
/*                :pv_api_op pointer to output structure                     */
3052
/*  Outputs       :                                                          */
3053
/*  Returns       : void                                                     */
3054
/*                                                                           */
3055
/*  Issues        : none                                                     */
3056
/*                                                                           */
3057
/*  Revision History:                                                        */
3058
/*                                                                           */
3059
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3060
/*         22 10 2008    100356         Draft                                */
3061
/*                                                                           */
3062
/*****************************************************************************/
3063
WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl,
3064
                                void *pv_api_ip,
3065
                                void *pv_api_op)
3066
0
{
3067
3068
0
    UWORD32 u4_disp_buf_size[3], u4_num_disp_bufs;
3069
0
    ivd_set_display_frame_ip_t *dec_disp_ip;
3070
0
    ivd_set_display_frame_op_t *dec_disp_op;
3071
3072
0
    UWORD32 i;
3073
0
    dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3074
3075
0
    dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
3076
0
    dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
3077
0
    dec_disp_op->u4_error_code = 0;
3078
3079
3080
0
    ps_dec->u4_num_disp_bufs = 0;
3081
0
    if(ps_dec->u4_share_disp_buf)
3082
0
    {
3083
0
        UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs;
3084
3085
0
        u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW);
3086
3087
0
        ps_dec->u4_num_disp_bufs = u4_num_bufs;
3088
3089
        /* Get the number and sizes of the first buffer. Compare this with the
3090
         * rest to make sure all the buffers are of the same size.
3091
         */
3092
0
        u4_num_disp_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs;
3093
3094
0
        u4_disp_buf_size[0] =
3095
0
          dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0];
3096
0
        u4_disp_buf_size[1] =
3097
0
          dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1];
3098
0
        u4_disp_buf_size[2] =
3099
0
          dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2];
3100
3101
0
        for(i = 0; i < u4_num_bufs; i++)
3102
0
        {
3103
0
            if(dec_disp_ip->s_disp_buffer[i].u4_num_bufs != u4_num_disp_bufs)
3104
0
            {
3105
0
                return IV_FAIL;
3106
0
            }
3107
3108
0
            if((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]
3109
0
                != u4_disp_buf_size[0])
3110
0
                || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]
3111
0
                    != u4_disp_buf_size[1])
3112
0
                || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]
3113
0
                    != u4_disp_buf_size[2]))
3114
0
            {
3115
0
                return IV_FAIL;
3116
0
            }
3117
3118
0
            ps_dec->disp_bufs[i].u4_num_bufs =
3119
0
                            dec_disp_ip->s_disp_buffer[i].u4_num_bufs;
3120
3121
0
            ps_dec->disp_bufs[i].buf[0] =
3122
0
                            dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
3123
0
            ps_dec->disp_bufs[i].buf[1] =
3124
0
                            dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
3125
0
            ps_dec->disp_bufs[i].buf[2] =
3126
0
                            dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
3127
3128
0
            ps_dec->disp_bufs[i].u4_bufsize[0] =
3129
0
                            dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0];
3130
0
            ps_dec->disp_bufs[i].u4_bufsize[1] =
3131
0
                            dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1];
3132
0
            ps_dec->disp_bufs[i].u4_bufsize[2] =
3133
0
                            dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2];
3134
3135
0
        }
3136
0
    }
3137
0
    return IV_SUCCESS;
3138
3139
0
}
3140
3141
/*****************************************************************************/
3142
/*                                                                           */
3143
/*  Function Name : ih264d_set_flush_mode                                    */
3144
/*                                                                           */
3145
/*  Description   :                                                          */
3146
/*                                                                           */
3147
/*  Inputs        :iv_obj_t decoder handle                                   */
3148
/*                :pv_api_ip pointer to input structure                      */
3149
/*                :pv_api_op pointer to output structure                     */
3150
/*  Globals       : <Does it use any global variables?>                      */
3151
/*  Outputs       :                                                          */
3152
/*  Returns       : void                                                     */
3153
/*                                                                           */
3154
/*  Issues        : none                                                     */
3155
/*                                                                           */
3156
/*  Revision History:                                                        */
3157
/*                                                                           */
3158
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3159
/*         22 10 2008    100356         Draft                                */
3160
/*                                                                           */
3161
/*****************************************************************************/
3162
WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3163
0
{
3164
0
    dec_struct_t * ps_dec;
3165
0
    ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op;
3166
0
    ps_ctl_op->u4_error_code = 0;
3167
3168
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3169
0
    ih264d_join_threads(ps_dec);
3170
0
    UNUSED(pv_api_ip);
3171
    /* ! */
3172
    /* Signal flush frame control call */
3173
0
    ps_dec->u1_flushfrm = 1;
3174
3175
0
    if(ps_dec->u1_init_dec_flag == 1)
3176
0
    {
3177
0
        ih264d_release_pics_in_dpb((void *)ps_dec, ps_dec->u1_pic_bufs);
3178
0
        ih264d_release_display_bufs(ps_dec);
3179
0
    }
3180
3181
0
    ps_ctl_op->u4_error_code = 0;
3182
3183
    /* Ignore dangling fields during flush */
3184
0
    ps_dec->u1_top_bottom_decoded = 0;
3185
3186
0
    return IV_SUCCESS;
3187
0
}
3188
3189
/*****************************************************************************/
3190
/*                                                                           */
3191
/*  Function Name : ih264d_get_status                                        */
3192
/*                                                                           */
3193
/*  Description   :                                                          */
3194
/*                                                                           */
3195
/*  Inputs        :iv_obj_t decoder handle                                   */
3196
/*                :pv_api_ip pointer to input structure                      */
3197
/*                :pv_api_op pointer to output structure                     */
3198
/*  Globals       : <Does it use any global variables?>                      */
3199
/*  Outputs       :                                                          */
3200
/*  Returns       : void                                                     */
3201
/*                                                                           */
3202
/*  Issues        : none                                                     */
3203
/*                                                                           */
3204
/*  Revision History:                                                        */
3205
/*                                                                           */
3206
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3207
/*         22 10 2008    100356         Draft                                */
3208
/*                                                                           */
3209
/*****************************************************************************/
3210
3211
WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3212
0
{
3213
3214
0
    UWORD32 i;
3215
0
    dec_struct_t * ps_dec;
3216
0
    UWORD32 pic_wd, pic_ht;
3217
0
    ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op;
3218
0
    UNUSED(pv_api_ip);
3219
0
    ps_ctl_op->u4_error_code = 0;
3220
3221
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3222
3223
3224
0
    if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3225
0
    {
3226
0
        ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height;
3227
0
        ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width;
3228
3229
0
        if(0 == ps_dec->u4_share_disp_buf)
3230
0
        {
3231
0
            pic_wd = ps_dec->u2_disp_width;
3232
0
            pic_ht = ps_dec->u2_disp_height;
3233
3234
0
        }
3235
0
        else
3236
0
        {
3237
0
            pic_wd = ps_dec->u2_frm_wd_y;
3238
0
            pic_ht = ps_dec->u2_frm_ht_y;
3239
0
        }
3240
0
    }
3241
0
    else
3242
0
    {
3243
0
        pic_wd = 0;
3244
0
        pic_ht = 0;
3245
3246
0
        ps_ctl_op->u4_pic_ht = pic_wd;
3247
0
        ps_ctl_op->u4_pic_wd = pic_ht;
3248
3249
0
        if(1 == ps_dec->u4_share_disp_buf)
3250
0
        {
3251
0
            pic_wd += (PAD_LEN_Y_H << 1);
3252
0
            pic_ht += (PAD_LEN_Y_V << 2);
3253
3254
0
        }
3255
3256
0
    }
3257
3258
0
    if(ps_dec->u4_app_disp_width > pic_wd)
3259
0
        pic_wd = ps_dec->u4_app_disp_width;
3260
0
    if(0 == ps_dec->u4_share_disp_buf)
3261
0
        ps_ctl_op->u4_num_disp_bufs = 1;
3262
0
    else
3263
0
    {
3264
0
        if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3265
0
        {
3266
0
            if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3267
0
               (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3268
0
            {
3269
0
                ps_ctl_op->u4_num_disp_bufs =
3270
0
                                ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3271
0
            }
3272
0
            else
3273
0
            {
3274
                /*if VUI is not present assume maximum possible refrence frames for the level,
3275
                 * as max reorder frames*/
3276
0
                ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3277
0
            }
3278
3279
0
            ps_ctl_op->u4_num_disp_bufs +=
3280
0
                            ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3281
0
        }
3282
0
        else
3283
0
        {
3284
0
            ps_ctl_op->u4_num_disp_bufs = 32;
3285
0
        }
3286
0
        ps_ctl_op->u4_num_disp_bufs = MAX(
3287
0
                        ps_ctl_op->u4_num_disp_bufs, 6);
3288
0
        ps_ctl_op->u4_num_disp_bufs = MIN(
3289
0
                        ps_ctl_op->u4_num_disp_bufs, 32);
3290
0
    }
3291
3292
0
    ps_ctl_op->u4_error_code = ps_dec->i4_error_code;
3293
3294
0
    ps_ctl_op->u4_frame_rate = 0; //make it proper
3295
0
    ps_ctl_op->u4_bit_rate = 0; //make it proper
3296
0
    ps_ctl_op->e_content_type = ps_dec->i4_content_type;
3297
0
    ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format;
3298
0
    ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3299
3300
0
    if(ps_dec->u1_chroma_format == IV_YUV_420P)
3301
0
    {
3302
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
3303
0
    }
3304
0
    else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3305
0
    {
3306
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
3307
0
    }
3308
0
    else if(ps_dec->u1_chroma_format == IV_RGB_565)
3309
0
    {
3310
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
3311
0
    }
3312
0
    else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3313
0
                    || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3314
0
    {
3315
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
3316
0
    }
3317
3318
0
    else
3319
0
    {
3320
        //Invalid chroma format; Error code may be updated, verify in testing if needed
3321
0
        ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL;
3322
0
        return IV_FAIL;
3323
0
    }
3324
3325
0
    for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3326
0
    {
3327
0
        ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
3328
0
    }
3329
3330
    /*!*/
3331
0
    if(ps_dec->u1_chroma_format == IV_YUV_420P)
3332
0
    {
3333
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3334
0
        ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3335
0
                        >> 2;
3336
0
        ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
3337
0
                        >> 2;
3338
0
    }
3339
0
    else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3340
0
    {
3341
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3342
0
                        * 2;
3343
0
        ps_ctl_op->u4_min_out_buf_size[1] =
3344
0
                        ps_ctl_op->u4_min_out_buf_size[2] = 0;
3345
0
    }
3346
0
    else if(ps_dec->u1_chroma_format == IV_RGB_565)
3347
0
    {
3348
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3349
0
                        * 2;
3350
0
        ps_ctl_op->u4_min_out_buf_size[1] =
3351
0
                        ps_ctl_op->u4_min_out_buf_size[2] = 0;
3352
0
    }
3353
0
    else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3354
0
                    || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3355
0
    {
3356
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3357
0
        ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3358
0
                        >> 1;
3359
0
        ps_ctl_op->u4_min_out_buf_size[2] = 0;
3360
0
    }
3361
3362
0
    ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3363
0
    return IV_SUCCESS;
3364
0
}
3365
3366
/*****************************************************************************/
3367
/*                                                                           */
3368
/*  Function Name :    ih264d_get_buf_info                                   */
3369
/*                                                                           */
3370
/*  Description   :                                                          */
3371
/*                                                                           */
3372
/*  Inputs        :iv_obj_t decoder handle                                   */
3373
/*                :pv_api_ip pointer to input structure                      */
3374
/*                :pv_api_op pointer to output structure                     */
3375
/*  Globals       : <Does it use any global variables?>                      */
3376
/*  Outputs       :                                                          */
3377
/*  Returns       : void                                                     */
3378
/*                                                                           */
3379
/*  Issues        : none                                                     */
3380
/*                                                                           */
3381
/*  Revision History:                                                        */
3382
/*                                                                           */
3383
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3384
/*         22 10 2008    100356         Draft                                */
3385
/*                                                                           */
3386
/*****************************************************************************/
3387
WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3388
0
{
3389
3390
0
    dec_struct_t * ps_dec;
3391
0
    UWORD8 i = 0; // Default for 420P format
3392
0
    UWORD16 pic_wd, pic_ht;
3393
0
    ivd_ctl_getbufinfo_op_t *ps_ctl_op =
3394
0
                    (ivd_ctl_getbufinfo_op_t*)pv_api_op;
3395
0
    UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
3396
0
    UNUSED(pv_api_ip);
3397
3398
0
    ps_ctl_op->u4_error_code = 0;
3399
3400
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3401
3402
0
    ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3403
3404
3405
0
    ps_ctl_op->u4_num_disp_bufs = 1;
3406
3407
3408
0
    pic_wd = 0;
3409
0
    pic_ht = 0;
3410
3411
0
    if(ps_dec->i4_header_decoded == 3)
3412
0
    {
3413
3414
0
        if(0 == ps_dec->u4_share_disp_buf)
3415
0
        {
3416
0
            pic_wd = ps_dec->u2_disp_width;
3417
0
            pic_ht = ps_dec->u2_disp_height;
3418
3419
0
        }
3420
0
        else
3421
0
        {
3422
0
            pic_wd = ps_dec->u2_frm_wd_y;
3423
0
            pic_ht = ps_dec->u2_frm_ht_y;
3424
0
        }
3425
3426
0
    }
3427
3428
0
    for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3429
0
    {
3430
0
        ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
3431
0
    }
3432
0
    if((WORD32)ps_dec->u4_app_disp_width > pic_wd)
3433
0
        pic_wd = ps_dec->u4_app_disp_width;
3434
3435
0
    if(0 == ps_dec->u4_share_disp_buf)
3436
0
        ps_ctl_op->u4_num_disp_bufs = 1;
3437
0
    else
3438
0
    {
3439
0
        if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3440
0
        {
3441
0
            if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3442
0
               (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3443
0
            {
3444
0
                ps_ctl_op->u4_num_disp_bufs =
3445
0
                                ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3446
0
            }
3447
0
            else
3448
0
            {
3449
                /*if VUI is not present assume maximum possible refrence frames for the level,
3450
                 * as max reorder frames*/
3451
0
                ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3452
0
            }
3453
3454
0
            ps_ctl_op->u4_num_disp_bufs +=
3455
0
                            ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3456
3457
0
        }
3458
0
        else
3459
0
        {
3460
0
            ps_ctl_op->u4_num_disp_bufs = 32;
3461
3462
0
        }
3463
3464
0
        ps_ctl_op->u4_num_disp_bufs = MAX(
3465
0
                        ps_ctl_op->u4_num_disp_bufs, 6);
3466
0
        ps_ctl_op->u4_num_disp_bufs = MIN(
3467
0
                        ps_ctl_op->u4_num_disp_bufs, 32);
3468
0
    }
3469
3470
0
    ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size(
3471
0
                    pic_wd, pic_ht, ps_dec->u1_chroma_format,
3472
0
                    &au4_min_out_buf_size[0]);
3473
3474
0
    for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++)
3475
0
    {
3476
0
        ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i];
3477
0
    }
3478
3479
0
    ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3480
3481
0
    return IV_SUCCESS;
3482
0
}
3483
3484
/*****************************************************************************/
3485
/*                                                                           */
3486
/*  Function Name : ih264d_set_params                                        */
3487
/*                                                                           */
3488
/*  Description   :                                                          */
3489
/*                                                                           */
3490
/*  Inputs        :iv_obj_t decoder handle                                   */
3491
/*                :pv_api_ip pointer to input structure                      */
3492
/*                :pv_api_op pointer to output structure                     */
3493
/*  Outputs       :                                                          */
3494
/*  Returns       : void                                                     */
3495
/*                                                                           */
3496
/*  Issues        : none                                                     */
3497
/*                                                                           */
3498
/*  Revision History:                                                        */
3499
/*                                                                           */
3500
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3501
/*         22 10 2008    100356         Draft                                */
3502
/*                                                                           */
3503
/*****************************************************************************/
3504
WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3505
0
{
3506
3507
0
    dec_struct_t * ps_dec;
3508
0
    WORD32 ret = IV_SUCCESS;
3509
3510
0
    ih264d_ctl_set_config_ip_t *ps_h264d_ctl_ip =
3511
0
                    (ih264d_ctl_set_config_ip_t *)pv_api_ip;
3512
0
    ih264d_ctl_set_config_op_t *ps_h264d_ctl_op =
3513
0
                    (ih264d_ctl_set_config_op_t *)pv_api_op;
3514
0
    ivd_ctl_set_config_ip_t *ps_ctl_ip =
3515
0
                    &ps_h264d_ctl_ip->s_ivd_ctl_set_config_ip_t;
3516
0
    ivd_ctl_set_config_op_t *ps_ctl_op =
3517
0
                    &ps_h264d_ctl_op->s_ivd_ctl_set_config_op_t;
3518
3519
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3520
3521
0
    ps_dec->u4_skip_frm_mask = 0;
3522
3523
0
    ps_ctl_op->u4_error_code = 0;
3524
3525
0
    if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE)
3526
0
    {
3527
0
        ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3528
0
        ret = IV_FAIL;
3529
0
    }
3530
3531
0
    if(ps_ctl_ip->u4_disp_wd >= ps_dec->u2_disp_width)
3532
0
    {
3533
0
        ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3534
0
    }
3535
0
    else if(0 == ps_dec->i4_header_decoded)
3536
0
    {
3537
0
        ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3538
0
    }
3539
0
    else if(ps_ctl_ip->u4_disp_wd == 0)
3540
0
    {
3541
0
        ps_dec->u4_app_disp_width = 0;
3542
0
    }
3543
0
    else
3544
0
    {
3545
        /*
3546
         * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF)
3547
         * does not propogate.
3548
         */
3549
0
        ps_dec->u4_app_disp_width = 0;
3550
0
        ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3551
0
        ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
3552
0
        ret = IV_FAIL;
3553
0
    }
3554
3555
0
    if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME)
3556
0
        ps_dec->i4_decode_header = 0;
3557
0
    else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER)
3558
0
        ps_dec->i4_decode_header = 1;
3559
0
    else
3560
0
    {
3561
0
        ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3562
0
        ps_dec->i4_decode_header = 1;
3563
0
        ret = IV_FAIL;
3564
0
    }
3565
0
    ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
3566
3567
0
    if((ps_ctl_ip->e_frm_out_mode != IVD_DECODE_FRAME_OUT) &&
3568
0
       (ps_ctl_ip->e_frm_out_mode != IVD_DISPLAY_FRAME_OUT))
3569
0
    {
3570
0
        ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3571
0
        ret = IV_FAIL;
3572
0
    }
3573
0
    ps_dec->e_frm_out_mode = ps_ctl_ip->e_frm_out_mode;
3574
0
    return ret;
3575
3576
0
}
3577
3578
/*****************************************************************************/
3579
/*                                                                           */
3580
/*  Function Name : ih264d_set_default_params                                */
3581
/*                                                                           */
3582
/*  Description   :                                                          */
3583
/*                                                                           */
3584
/*  Inputs        :iv_obj_t decoder handle                                   */
3585
/*                :pv_api_ip pointer to input structure                      */
3586
/*                :pv_api_op pointer to output structure                     */
3587
/*  Outputs       :                                                          */
3588
/*  Returns       : void                                                     */
3589
/*                                                                           */
3590
/*  Issues        : none                                                     */
3591
/*                                                                           */
3592
/*  Revision History:                                                        */
3593
/*                                                                           */
3594
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3595
/*         08 08 2011   100421          Copied from set_params               */
3596
/*                                                                           */
3597
/*****************************************************************************/
3598
WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl,
3599
                                 void *pv_api_ip,
3600
                                 void *pv_api_op)
3601
0
{
3602
3603
0
    dec_struct_t * ps_dec;
3604
0
    WORD32 ret = IV_SUCCESS;
3605
3606
0
    ivd_ctl_set_config_op_t *ps_ctl_op =
3607
0
                    (ivd_ctl_set_config_op_t *)pv_api_op;
3608
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3609
0
    UNUSED(pv_api_ip);
3610
3611
3612
0
    {
3613
0
        ps_dec->u4_app_disp_width = 0;
3614
0
        ps_dec->u4_skip_frm_mask = 0;
3615
0
        ps_dec->i4_decode_header = 1;
3616
3617
0
        ps_ctl_op->u4_error_code = 0;
3618
0
    }
3619
3620
3621
0
    return ret;
3622
0
}
3623
/*****************************************************************************/
3624
/*                                                                           */
3625
/*  Function Name :  ih264d_reset                                            */
3626
/*                                                                           */
3627
/*  Description   :                                                          */
3628
/*                                                                           */
3629
/*  Inputs        :iv_obj_t decoder handle                                   */
3630
/*                :pv_api_ip pointer to input structure                      */
3631
/*                :pv_api_op pointer to output structure                     */
3632
/*  Globals       : <Does it use any global variables?>                      */
3633
/*  Outputs       :                                                          */
3634
/*  Returns       : void                                                     */
3635
/*                                                                           */
3636
/*  Issues        : none                                                     */
3637
/*                                                                           */
3638
/*  Revision History:                                                        */
3639
/*                                                                           */
3640
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3641
/*         22 10 2008    100356         Draft                                */
3642
/*                                                                           */
3643
/*****************************************************************************/
3644
WORD32 ih264d_delete(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3645
0
{
3646
0
    dec_struct_t *ps_dec;
3647
0
    ih264d_delete_ip_t *ps_ip = (ih264d_delete_ip_t *)pv_api_ip;
3648
0
    ih264d_delete_op_t *ps_op = (ih264d_delete_op_t *)pv_api_op;
3649
3650
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3651
0
    UNUSED(ps_ip);
3652
0
    ps_op->s_ivd_delete_op_t.u4_error_code = 0;
3653
0
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_dynamic);
3654
0
    ih264d_free_dynamic_bufs(ps_dec);
3655
0
    ih264d_free_static_bufs(dec_hdl);
3656
0
    return IV_SUCCESS;
3657
0
}
3658
/*****************************************************************************/
3659
/*                                                                           */
3660
/*  Function Name :  ih264d_reset                                            */
3661
/*                                                                           */
3662
/*  Description   :                                                          */
3663
/*                                                                           */
3664
/*  Inputs        :iv_obj_t decoder handle                                   */
3665
/*                :pv_api_ip pointer to input structure                      */
3666
/*                :pv_api_op pointer to output structure                     */
3667
/*  Globals       : <Does it use any global variables?>                      */
3668
/*  Outputs       :                                                          */
3669
/*  Returns       : void                                                     */
3670
/*                                                                           */
3671
/*  Issues        : none                                                     */
3672
/*                                                                           */
3673
/*  Revision History:                                                        */
3674
/*                                                                           */
3675
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3676
/*         22 10 2008    100356         Draft                                */
3677
/*                                                                           */
3678
/*****************************************************************************/
3679
WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3680
0
{
3681
0
    dec_struct_t * ps_dec;
3682
0
    ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op;
3683
0
    UNUSED(pv_api_ip);
3684
0
    ps_ctl_op->u4_error_code = 0;
3685
3686
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3687
3688
0
    if(ps_dec != NULL)
3689
0
    {
3690
0
        ih264d_join_threads(ps_dec);
3691
0
        ih264d_init_decoder(ps_dec);
3692
0
    }
3693
0
    else
3694
0
    {
3695
0
        H264_DEC_DEBUG_PRINT(
3696
0
                        "\nReset called without Initializing the decoder\n");
3697
0
        ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE;
3698
0
    }
3699
3700
0
    return IV_SUCCESS;
3701
0
}
3702
3703
/*****************************************************************************/
3704
/*                                                                           */
3705
/*  Function Name :  ih264d_ctl                                              */
3706
/*                                                                           */
3707
/*  Description   :                                                          */
3708
/*                                                                           */
3709
/*  Inputs        :iv_obj_t decoder handle                                   */
3710
/*                :pv_api_ip pointer to input structure                      */
3711
/*                :pv_api_op pointer to output structure                     */
3712
/*  Outputs       :                                                          */
3713
/*  Returns       : void                                                     */
3714
/*                                                                           */
3715
/*  Issues        : none                                                     */
3716
/*                                                                           */
3717
/*  Revision History:                                                        */
3718
/*                                                                           */
3719
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3720
/*         22 10 2008    100356         Draft                                */
3721
/*                                                                           */
3722
/*****************************************************************************/
3723
WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3724
0
{
3725
0
    ivd_ctl_set_config_ip_t *ps_ctl_ip;
3726
0
    ivd_ctl_set_config_op_t *ps_ctl_op;
3727
0
    WORD32 ret = IV_SUCCESS;
3728
0
    UWORD32 subcommand;
3729
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3730
3731
0
    if(ps_dec->init_done != 1)
3732
0
    {
3733
        //Return proper Error Code
3734
0
        return IV_FAIL;
3735
0
    }
3736
0
    ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip;
3737
0
    ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op;
3738
0
    ps_ctl_op->u4_error_code = 0;
3739
0
    subcommand = ps_ctl_ip->e_sub_cmd;
3740
3741
0
    switch(subcommand)
3742
0
    {
3743
0
        case IVD_CMD_CTL_GETPARAMS:
3744
0
            ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip,
3745
0
                                    (void *)pv_api_op);
3746
0
            break;
3747
0
        case IVD_CMD_CTL_SETPARAMS:
3748
0
            ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip,
3749
0
                                    (void *)pv_api_op);
3750
0
            break;
3751
0
        case IVD_CMD_CTL_RESET:
3752
0
            ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op);
3753
0
            break;
3754
0
        case IVD_CMD_CTL_SETDEFAULT:
3755
0
            ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip,
3756
0
                                            (void *)pv_api_op);
3757
0
            break;
3758
0
        case IVD_CMD_CTL_FLUSH:
3759
0
            ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip,
3760
0
                                        (void *)pv_api_op);
3761
0
            break;
3762
0
        case IVD_CMD_CTL_GETBUFINFO:
3763
0
            ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip,
3764
0
                                      (void *)pv_api_op);
3765
0
            break;
3766
0
        case IVD_CMD_CTL_GETVERSION:
3767
0
            ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip,
3768
0
                                     (void *)pv_api_op);
3769
0
            break;
3770
0
        case IH264D_CMD_CTL_DEGRADE:
3771
0
            ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip,
3772
0
                                     (void *)pv_api_op);
3773
0
            break;
3774
3775
0
        case IH264D_CMD_CTL_SET_NUM_CORES:
3776
0
            ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip,
3777
0
                                       (void *)pv_api_op);
3778
0
            break;
3779
0
        case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
3780
0
            ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip,
3781
0
                                              (void *)pv_api_op);
3782
0
            break;
3783
0
        case IH264D_CMD_CTL_GET_VUI_PARAMS:
3784
0
            ret = ih264d_get_vui_params(dec_hdl, (void *)pv_api_ip,
3785
0
                                        (void *)pv_api_op);
3786
0
            break;
3787
0
        case IH264D_CMD_CTL_GET_SEI_MDCV_PARAMS:
3788
0
            ret = ih264d_get_sei_mdcv_params(dec_hdl, (void *)pv_api_ip,
3789
0
                                             (void *)pv_api_op);
3790
0
            break;
3791
0
        case IH264D_CMD_CTL_GET_SEI_CLL_PARAMS:
3792
0
            ret = ih264d_get_sei_cll_params(dec_hdl, (void *)pv_api_ip,
3793
0
                                            (void *)pv_api_op);
3794
0
            break;
3795
0
        case IH264D_CMD_CTL_GET_SEI_AVE_PARAMS:
3796
0
            ret = ih264d_get_sei_ave_params(dec_hdl, (void *)pv_api_ip,
3797
0
                                            (void *)pv_api_op);
3798
0
            break;
3799
0
        case IH264D_CMD_CTL_GET_SEI_CCV_PARAMS:
3800
0
            ret = ih264d_get_sei_ccv_params(dec_hdl, (void *)pv_api_ip,
3801
0
                                            (void *)pv_api_op);
3802
0
            break;
3803
0
        case IH264D_CMD_CTL_GET_SEI_SII_PARAMS:
3804
0
            ret = ih264d_get_sei_sii_params(dec_hdl, (void *) pv_api_ip, (void *) pv_api_op);
3805
0
            break;
3806
3807
0
        case IH264D_CMD_CTL_GET_SEI_FGC_PARAMS:
3808
0
            ret = ih264d_get_sei_fgc_params(dec_hdl, (void *) pv_api_ip, (void *) pv_api_op);
3809
0
            break;
3810
3811
0
        case IH264D_CMD_CTL_SET_PROCESSOR:
3812
0
            ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip,
3813
0
                                       (void *)pv_api_op);
3814
0
            break;
3815
0
        default:
3816
0
            H264_DEC_DEBUG_PRINT("\ndo nothing\n")
3817
0
            ;
3818
0
            break;
3819
0
    }
3820
3821
0
    return ret;
3822
0
}
3823
/*****************************************************************************/
3824
/*                                                                           */
3825
/*  Function Name :   ih264d_rel_display_frame                               */
3826
/*                                                                           */
3827
/*  Description   :                                                          */
3828
/*                                                                           */
3829
/*  Inputs        :iv_obj_t decoder handle                                   */
3830
/*                :pv_api_ip pointer to input structure                      */
3831
/*                :pv_api_op pointer to output structure                     */
3832
/*  Outputs       :                                                          */
3833
/*  Returns       : void                                                     */
3834
/*                                                                           */
3835
/*  Issues        : none                                                     */
3836
/*                                                                           */
3837
/*  Revision History:                                                        */
3838
/*                                                                           */
3839
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3840
/*         22 10 2008    100356         Draft                                */
3841
/*                                                                           */
3842
/*****************************************************************************/
3843
WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl,
3844
                                void *pv_api_ip,
3845
                                void *pv_api_op)
3846
0
{
3847
3848
0
    ivd_rel_display_frame_ip_t *ps_rel_ip;
3849
0
    ivd_rel_display_frame_op_t *ps_rel_op;
3850
0
    UWORD32 buf_released = 0;
3851
3852
0
    UWORD32 u4_ts = 0;
3853
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3854
3855
0
    ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
3856
0
    ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op;
3857
0
    ps_rel_op->u4_error_code = 0;
3858
0
    u4_ts = ps_rel_ip->u4_disp_buf_id;
3859
3860
0
    if(0 == ps_dec->u4_share_disp_buf)
3861
0
    {
3862
0
        ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3863
0
        ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0;
3864
0
        return IV_SUCCESS;
3865
0
    }
3866
3867
0
    if(ps_dec->pv_pic_buf_mgr != NULL)
3868
0
    {
3869
0
        if(1 == ps_dec->u4_disp_buf_mapping[u4_ts])
3870
0
        {
3871
0
            ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
3872
0
                                  ps_rel_ip->u4_disp_buf_id,
3873
0
                                  BUF_MGR_IO);
3874
0
            ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3875
0
            buf_released = 1;
3876
0
        }
3877
0
    }
3878
3879
0
    if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released))
3880
0
        ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1;
3881
3882
0
    return IV_SUCCESS;
3883
0
}
3884
3885
/**
3886
 *******************************************************************************
3887
 *
3888
 * @brief
3889
 *  Sets degrade params
3890
 *
3891
 * @par Description:
3892
 *  Sets degrade params.
3893
 *  Refer to ih264d_ctl_degrade_ip_t definition for details
3894
 *
3895
 * @param[in] ps_codec_obj
3896
 *  Pointer to codec object at API level
3897
 *
3898
 * @param[in] pv_api_ip
3899
 *  Pointer to input argument structure
3900
 *
3901
 * @param[out] pv_api_op
3902
 *  Pointer to output argument structure
3903
 *
3904
 * @returns  Status
3905
 *
3906
 * @remarks
3907
 *
3908
 *
3909
 *******************************************************************************
3910
 */
3911
3912
WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
3913
                          void *pv_api_ip,
3914
                          void *pv_api_op)
3915
0
{
3916
0
    ih264d_ctl_degrade_ip_t *ps_ip;
3917
0
    ih264d_ctl_degrade_op_t *ps_op;
3918
0
    dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle;
3919
3920
0
    ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
3921
0
    ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
3922
3923
0
    ps_codec->i4_degrade_type = ps_ip->i4_degrade_type;
3924
0
    ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
3925
0
    ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics;
3926
3927
0
    ps_op->u4_error_code = 0;
3928
0
    ps_codec->i4_degrade_pic_cnt = 0;
3929
3930
0
    return IV_SUCCESS;
3931
0
}
3932
3933
WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
3934
                                   void *pv_api_ip,
3935
                                   void *pv_api_op)
3936
0
{
3937
0
    ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
3938
0
    ih264d_ctl_get_frame_dimensions_op_t *ps_op;
3939
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3940
0
    UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
3941
3942
0
    ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
3943
3944
0
    ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
3945
0
    UNUSED(ps_ip);
3946
0
    if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3947
0
    {
3948
0
        disp_wd = ps_dec->u2_disp_width;
3949
0
        disp_ht = ps_dec->u2_disp_height;
3950
3951
0
        if(0 == ps_dec->u4_share_disp_buf)
3952
0
        {
3953
0
            buffer_wd = disp_wd;
3954
0
            buffer_ht = disp_ht;
3955
0
        }
3956
0
        else
3957
0
        {
3958
0
            buffer_wd = ps_dec->u2_frm_wd_y;
3959
0
            buffer_ht = ps_dec->u2_frm_ht_y;
3960
0
        }
3961
0
    }
3962
0
    else
3963
0
    {
3964
0
        disp_wd = 0;
3965
0
        disp_ht = 0;
3966
3967
0
        if(0 == ps_dec->u4_share_disp_buf)
3968
0
        {
3969
0
            buffer_wd = disp_wd;
3970
0
            buffer_ht = disp_ht;
3971
0
        }
3972
0
        else
3973
0
        {
3974
0
            buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1);
3975
0
            buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2);
3976
0
        }
3977
0
    }
3978
0
    if(ps_dec->u4_app_disp_width > buffer_wd)
3979
0
        buffer_wd = ps_dec->u4_app_disp_width;
3980
3981
0
    if(0 == ps_dec->u4_share_disp_buf)
3982
0
    {
3983
0
        x_offset = 0;
3984
0
        y_offset = 0;
3985
0
    }
3986
0
    else
3987
0
    {
3988
0
        y_offset = (PAD_LEN_Y_V << 1);
3989
0
        x_offset = PAD_LEN_Y_H;
3990
3991
0
        if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid))
3992
0
                        && (0 != ps_dec->u2_crop_offset_y))
3993
0
        {
3994
0
            y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y;
3995
0
            x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y;
3996
0
        }
3997
0
    }
3998
3999
0
    ps_op->u4_disp_wd[0] = disp_wd;
4000
0
    ps_op->u4_disp_ht[0] = disp_ht;
4001
0
    ps_op->u4_buffer_wd[0] = buffer_wd;
4002
0
    ps_op->u4_buffer_ht[0] = buffer_ht;
4003
0
    ps_op->u4_x_offset[0] = x_offset;
4004
0
    ps_op->u4_y_offset[0] = y_offset;
4005
4006
0
    ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
4007
0
                    >> 1);
4008
0
    ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
4009
0
                    >> 1);
4010
0
    ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
4011
0
                    >> 1);
4012
0
    ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
4013
0
                    >> 1);
4014
0
    ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] =
4015
0
                    (ps_op->u4_x_offset[0] >> 1);
4016
0
    ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] =
4017
0
                    (ps_op->u4_y_offset[0] >> 1);
4018
4019
0
    if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
4020
0
                    || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
4021
0
    {
4022
0
        ps_op->u4_disp_wd[2] = 0;
4023
0
        ps_op->u4_disp_ht[2] = 0;
4024
0
        ps_op->u4_buffer_wd[2] = 0;
4025
0
        ps_op->u4_buffer_ht[2] = 0;
4026
0
        ps_op->u4_x_offset[2] = 0;
4027
0
        ps_op->u4_y_offset[2] = 0;
4028
4029
0
        ps_op->u4_disp_wd[1] <<= 1;
4030
0
        ps_op->u4_buffer_wd[1] <<= 1;
4031
0
        ps_op->u4_x_offset[1] <<= 1;
4032
0
    }
4033
4034
0
    return IV_SUCCESS;
4035
4036
0
}
4037
4038
WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
4039
                             void *pv_api_ip,
4040
                             void *pv_api_op)
4041
0
{
4042
0
    ih264d_ctl_get_vui_params_ip_t *ps_ip;
4043
0
    ih264d_ctl_get_vui_params_op_t *ps_op;
4044
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4045
0
    dec_seq_params_t *ps_sps;
4046
0
    vui_t *ps_vui;
4047
0
    WORD32 i;
4048
0
    UWORD32 u4_size;
4049
4050
0
    ps_ip = (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
4051
0
    ps_op = (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
4052
0
    UNUSED(ps_ip);
4053
4054
0
    u4_size = ps_op->u4_size;
4055
0
    memset(ps_op, 0, sizeof(ih264d_ctl_get_vui_params_op_t));
4056
0
    ps_op->u4_size = u4_size;
4057
4058
0
    if(NULL == ps_dec->ps_cur_sps)
4059
0
    {
4060
0
        ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
4061
0
        return IV_FAIL;
4062
0
    }
4063
4064
0
    ps_sps = ps_dec->ps_cur_sps;
4065
0
    if((0 == ps_sps->u1_is_valid)
4066
0
                    || (0 == ps_sps->u1_vui_parameters_present_flag))
4067
0
    {
4068
0
        ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
4069
0
        return IV_FAIL;
4070
0
    }
4071
4072
0
    ps_vui = &ps_sps->s_vui;
4073
4074
0
    ps_op->u1_aspect_ratio_idc              = ps_vui->u1_aspect_ratio_idc;
4075
0
    ps_op->u2_sar_width                     = ps_vui->u2_sar_width;
4076
0
    ps_op->u2_sar_height                    = ps_vui->u2_sar_height;
4077
0
    ps_op->u1_overscan_appropriate_flag     = ps_vui->u1_overscan_appropriate_flag;
4078
0
    ps_op->u1_video_format                  = ps_vui->u1_video_format;
4079
0
    ps_op->u1_video_full_range_flag         = ps_vui->u1_video_full_range_flag;
4080
0
    ps_op->u1_colour_primaries              = ps_vui->u1_colour_primaries;
4081
0
    ps_op->u1_tfr_chars                     = ps_vui->u1_tfr_chars;
4082
0
    ps_op->u1_matrix_coeffs                 = ps_vui->u1_matrix_coeffs;
4083
0
    ps_op->u1_cr_top_field                  = ps_vui->u1_cr_top_field;
4084
0
    ps_op->u1_cr_bottom_field               = ps_vui->u1_cr_bottom_field;
4085
0
    ps_op->u4_num_units_in_tick             = ps_vui->u4_num_units_in_tick;
4086
0
    ps_op->u4_time_scale                    = ps_vui->u4_time_scale;
4087
0
    ps_op->u1_fixed_frame_rate_flag         = ps_vui->u1_fixed_frame_rate_flag;
4088
0
    ps_op->u1_nal_hrd_params_present        = ps_vui->u1_nal_hrd_params_present;
4089
0
    ps_op->u1_vcl_hrd_params_present        = ps_vui->u1_vcl_hrd_params_present;
4090
0
    ps_op->u1_low_delay_hrd_flag            = ps_vui->u1_low_delay_hrd_flag;
4091
0
    ps_op->u1_pic_struct_present_flag       = ps_vui->u1_pic_struct_present_flag;
4092
0
    ps_op->u1_bitstream_restriction_flag    = ps_vui->u1_bitstream_restriction_flag;
4093
0
    ps_op->u1_mv_over_pic_boundaries_flag   = ps_vui->u1_mv_over_pic_boundaries_flag;
4094
0
    ps_op->u4_max_bytes_per_pic_denom       = ps_vui->u4_max_bytes_per_pic_denom;
4095
0
    ps_op->u4_max_bits_per_mb_denom         = ps_vui->u4_max_bits_per_mb_denom;
4096
0
    ps_op->u4_log2_max_mv_length_horz       = ps_vui->u4_log2_max_mv_length_horz;
4097
0
    ps_op->u4_log2_max_mv_length_vert       = ps_vui->u4_log2_max_mv_length_vert;
4098
0
    ps_op->u4_num_reorder_frames            = ps_vui->u4_num_reorder_frames;
4099
0
    ps_op->u4_max_dec_frame_buffering       = ps_vui->u4_max_dec_frame_buffering;
4100
4101
0
    return IV_SUCCESS;
4102
0
}
4103
/*****************************************************************************/
4104
/*                                                                           */
4105
/*  Function Name : ih264d_get_sei_mdcv_params                               */
4106
/*                                                                           */
4107
/*  Description   : This function populates SEI mdcv message in              */
4108
/*                     output structure                                      */
4109
/*  Inputs        : iv_obj_t decoder handle                                  */
4110
/*                : pv_api_ip pointer to input structure                     */
4111
/*                : pv_api_op pointer to output structure                    */
4112
/*  Outputs       :                                                          */
4113
/*  Returns       : returns 0; 1 with error code when MDCV is not present    */
4114
/*                                                                           */
4115
/*  Issues        : none                                                     */
4116
/*                                                                           */
4117
/*  Revision History:                                                        */
4118
/*                                                                           */
4119
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4120
/*                                                                           */
4121
/*                                                                           */
4122
/*****************************************************************************/
4123
WORD32 ih264d_get_sei_mdcv_params(iv_obj_t *dec_hdl,
4124
                                  void *pv_api_ip,
4125
                                  void *pv_api_op)
4126
0
{
4127
0
    ih264d_ctl_get_sei_mdcv_params_ip_t *ps_ip;
4128
0
    ih264d_ctl_get_sei_mdcv_params_op_t *ps_op;
4129
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4130
0
    sei_mdcv_params_t *ps_sei_mdcv;
4131
0
    WORD32 i4_count;
4132
4133
0
    ps_ip = (ih264d_ctl_get_sei_mdcv_params_ip_t *)pv_api_ip;
4134
0
    ps_op = (ih264d_ctl_get_sei_mdcv_params_op_t *)pv_api_op;
4135
0
    UNUSED(ps_ip);
4136
4137
0
    if(0 == ps_dec->s_sei_export.u1_sei_mdcv_params_present_flag)
4138
0
    {
4139
0
        ps_op->u4_error_code = ERROR_SEI_MDCV_PARAMS_NOT_FOUND;
4140
0
        return IV_FAIL;
4141
0
    }
4142
4143
0
    ps_sei_mdcv = &ps_dec->s_sei_export.s_sei_mdcv_params;
4144
4145
0
    for(i4_count = 0; i4_count < NUM_SEI_MDCV_PRIMARIES; i4_count++)
4146
0
    {
4147
0
        ps_op->au2_display_primaries_x[i4_count] = ps_sei_mdcv->au2_display_primaries_x[i4_count];
4148
0
        ps_op->au2_display_primaries_y[i4_count] = ps_sei_mdcv->au2_display_primaries_y[i4_count];
4149
0
    }
4150
4151
0
    ps_op->u2_white_point_x = ps_sei_mdcv->u2_white_point_x;
4152
0
    ps_op->u2_white_point_y = ps_sei_mdcv->u2_white_point_y;
4153
0
    ps_op->u4_max_display_mastering_luminance = ps_sei_mdcv->u4_max_display_mastering_luminance;
4154
0
    ps_op->u4_min_display_mastering_luminance = ps_sei_mdcv->u4_min_display_mastering_luminance;
4155
4156
0
    return IV_SUCCESS;
4157
0
}
4158
4159
/*****************************************************************************/
4160
/*                                                                           */
4161
/*  Function Name : ih264d_get_sei_cll_params                                */
4162
/*                                                                           */
4163
/*  Description   : This function populates SEI cll message in               */
4164
/*                     output structure                                      */
4165
/*  Inputs        : iv_obj_t decoder handle                                  */
4166
/*                : pv_api_ip pointer to input structure                     */
4167
/*                : pv_api_op pointer to output structure                    */
4168
/*  Outputs       :                                                          */
4169
/*  Returns       : returns 0; 1 with error code when CLL is not present     */
4170
/*                                                                           */
4171
/*  Issues        : none                                                     */
4172
/*                                                                           */
4173
/*  Revision History:                                                        */
4174
/*                                                                           */
4175
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4176
/*                                                                           */
4177
/*                                                                           */
4178
/*****************************************************************************/
4179
WORD32 ih264d_get_sei_cll_params(iv_obj_t *dec_hdl,
4180
                                 void *pv_api_ip,
4181
                                 void *pv_api_op)
4182
0
{
4183
0
    ih264d_ctl_get_sei_cll_params_ip_t *ps_ip;
4184
0
    ih264d_ctl_get_sei_cll_params_op_t *ps_op;
4185
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4186
0
    sei_cll_params_t *ps_sei_cll;
4187
4188
0
    ps_ip = (ih264d_ctl_get_sei_cll_params_ip_t *)pv_api_ip;
4189
0
    ps_op = (ih264d_ctl_get_sei_cll_params_op_t *)pv_api_op;
4190
0
    UNUSED(ps_ip);
4191
4192
0
    if(0 == ps_dec->s_sei_export.u1_sei_cll_params_present_flag)
4193
0
    {
4194
0
        ps_op->u4_error_code = ERROR_SEI_CLL_PARAMS_NOT_FOUND;
4195
0
        return IV_FAIL;
4196
0
    }
4197
4198
0
    ps_sei_cll = &ps_dec->s_sei_export.s_sei_cll_params;
4199
4200
0
    ps_op->u2_max_content_light_level = ps_sei_cll->u2_max_content_light_level;
4201
0
    ps_op->u2_max_pic_average_light_level = ps_sei_cll->u2_max_pic_average_light_level;
4202
4203
0
    return IV_SUCCESS;
4204
0
}
4205
4206
/*****************************************************************************/
4207
/*                                                                           */
4208
/*  Function Name : ih264d_get_sei_ave_params                                */
4209
/*                                                                           */
4210
/*  Description   : This function populates SEI ave message in               */
4211
/*                     output structure                                      */
4212
/*  Inputs        : iv_obj_t decoder handle                                  */
4213
/*                : pv_api_ip pointer to input structure                     */
4214
/*                : pv_api_op pointer to output structure                    */
4215
/*  Outputs       :                                                          */
4216
/*  Returns       : returns 0; 1 with error code when AVE is not present     */
4217
/*                                                                           */
4218
/*  Issues        : none                                                     */
4219
/*                                                                           */
4220
/*  Revision History:                                                        */
4221
/*                                                                           */
4222
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4223
/*                                                                           */
4224
/*                                                                           */
4225
/*****************************************************************************/
4226
WORD32 ih264d_get_sei_ave_params(iv_obj_t *dec_hdl,
4227
                                 void *pv_api_ip,
4228
                                 void *pv_api_op)
4229
0
{
4230
0
    ih264d_ctl_get_sei_ave_params_ip_t *ps_ip;
4231
0
    ih264d_ctl_get_sei_ave_params_op_t *ps_op;
4232
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4233
0
    sei_ave_params_t *ps_sei_ave;
4234
4235
0
    ps_ip = (ih264d_ctl_get_sei_ave_params_ip_t *)pv_api_ip;
4236
0
    ps_op = (ih264d_ctl_get_sei_ave_params_op_t *)pv_api_op;
4237
0
    UNUSED(ps_ip);
4238
4239
0
    if(0 == ps_dec->s_sei_export.u1_sei_ave_params_present_flag)
4240
0
    {
4241
0
        ps_op->u4_error_code = ERROR_SEI_AVE_PARAMS_NOT_FOUND;
4242
0
        return IV_FAIL;
4243
0
    }
4244
4245
0
    ps_sei_ave = &ps_dec->s_sei_export.s_sei_ave_params;
4246
4247
0
    ps_op->u4_ambient_illuminance = ps_sei_ave->u4_ambient_illuminance;
4248
0
    ps_op->u2_ambient_light_x = ps_sei_ave->u2_ambient_light_x;
4249
0
    ps_op->u2_ambient_light_y = ps_sei_ave->u2_ambient_light_y;
4250
4251
0
    return IV_SUCCESS;
4252
0
}
4253
4254
/*****************************************************************************/
4255
/*                                                                           */
4256
/*  Function Name : ih264d_get_sei_ccv_params                                */
4257
/*                                                                           */
4258
/*  Description   : This function populates SEI mdcv message in              */
4259
/*                     output structure                                      */
4260
/*  Inputs        : iv_obj_t decoder handle                                  */
4261
/*                : pv_api_ip pointer to input structure                     */
4262
/*                : pv_api_op pointer to output structure                    */
4263
/*  Outputs       :                                                          */
4264
/*  Returns       : returns 0; 1 with error code when CCV is not present    */
4265
/*                                                                           */
4266
/*  Issues        : none                                                     */
4267
/*                                                                           */
4268
/*  Revision History:                                                        */
4269
/*                                                                           */
4270
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4271
/*                                                                           */
4272
/*                                                                           */
4273
/*****************************************************************************/
4274
WORD32 ih264d_get_sei_ccv_params(iv_obj_t *dec_hdl,
4275
                                 void *pv_api_ip,
4276
                                 void *pv_api_op)
4277
0
{
4278
0
    ih264d_ctl_get_sei_ccv_params_ip_t *ps_ip;
4279
0
    ih264d_ctl_get_sei_ccv_params_op_t *ps_op;
4280
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4281
0
    sei_ccv_params_t *ps_sei_ccv;
4282
0
    WORD32 i4_count;
4283
4284
0
    ps_ip = (ih264d_ctl_get_sei_ccv_params_ip_t *)pv_api_ip;
4285
0
    ps_op = (ih264d_ctl_get_sei_ccv_params_op_t *)pv_api_op;
4286
0
    UNUSED(ps_ip);
4287
4288
0
    if(0 == ps_dec->s_sei_export.u1_sei_ccv_params_present_flag)
4289
0
    {
4290
0
        ps_op->u4_error_code = ERROR_SEI_CCV_PARAMS_NOT_FOUND;
4291
0
        return IV_FAIL;
4292
0
    }
4293
4294
0
    ps_sei_ccv = &ps_dec->s_sei_export.s_sei_ccv_params;
4295
4296
0
    ps_op->u1_ccv_cancel_flag = ps_sei_ccv->u1_ccv_cancel_flag;
4297
4298
0
    if(0 == ps_op->u1_ccv_cancel_flag)
4299
0
    {
4300
0
        ps_op->u1_ccv_persistence_flag = ps_sei_ccv->u1_ccv_persistence_flag;
4301
0
        ps_op->u1_ccv_primaries_present_flag = ps_sei_ccv->u1_ccv_primaries_present_flag;
4302
0
        ps_op->u1_ccv_min_luminance_value_present_flag =
4303
0
                    ps_sei_ccv->u1_ccv_min_luminance_value_present_flag;
4304
0
        ps_op->u1_ccv_max_luminance_value_present_flag =
4305
0
                    ps_sei_ccv->u1_ccv_max_luminance_value_present_flag;
4306
0
        ps_op->u1_ccv_avg_luminance_value_present_flag =
4307
0
                    ps_sei_ccv->u1_ccv_avg_luminance_value_present_flag;
4308
0
        ps_op->u1_ccv_reserved_zero_2bits = ps_sei_ccv->u1_ccv_reserved_zero_2bits;
4309
4310
0
        if(1 == ps_sei_ccv->u1_ccv_primaries_present_flag)
4311
0
        {
4312
0
            for(i4_count = 0; i4_count < NUM_SEI_CCV_PRIMARIES; i4_count++)
4313
0
            {
4314
0
                ps_op->ai4_ccv_primaries_x[i4_count] = ps_sei_ccv->ai4_ccv_primaries_x[i4_count];
4315
0
                ps_op->ai4_ccv_primaries_y[i4_count] = ps_sei_ccv->ai4_ccv_primaries_y[i4_count];
4316
0
            }
4317
0
        }
4318
4319
0
        if(1 == ps_sei_ccv->u1_ccv_min_luminance_value_present_flag)
4320
0
        {
4321
0
            ps_op->u4_ccv_min_luminance_value = ps_sei_ccv->u4_ccv_min_luminance_value;
4322
0
        }
4323
0
        if(1 == ps_sei_ccv->u1_ccv_max_luminance_value_present_flag)
4324
0
        {
4325
0
            ps_op->u4_ccv_max_luminance_value = ps_sei_ccv->u4_ccv_max_luminance_value;
4326
0
        }
4327
0
        if(1 == ps_sei_ccv->u1_ccv_avg_luminance_value_present_flag)
4328
0
        {
4329
0
            ps_op->u4_ccv_avg_luminance_value = ps_sei_ccv->u4_ccv_avg_luminance_value;
4330
0
        }
4331
0
    }
4332
4333
0
    return IV_SUCCESS;
4334
0
}
4335
4336
/*****************************************************************************/
4337
/*                                                                           */
4338
/*  Function Name : ih264d_get_sei_sii_params                                */
4339
/*                                                                           */
4340
/*  Description   : This function populates SEI sii message in               */
4341
/*                     output structure                                      */
4342
/*  Inputs        : iv_obj_t decoder handle                                  */
4343
/*                : pv_api_ip pointer to input structure                     */
4344
/*                : pv_api_op pointer to output structure                    */
4345
/*  Outputs       :                                                          */
4346
/*  Returns       : returns 0; 1 with error code when SII is not present     */
4347
/*                                                                           */
4348
/*  Issues        : none                                                     */
4349
/*                                                                           */
4350
/*  Revision History:                                                        */
4351
/*                                                                           */
4352
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4353
/*                                                                           */
4354
/*                                                                           */
4355
/*****************************************************************************/
4356
WORD32 ih264d_get_sei_sii_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4357
0
{
4358
0
    ih264d_ctl_get_sei_sii_params_ip_t *ps_ip;
4359
0
    ih264d_ctl_get_sei_sii_params_op_t *ps_op;
4360
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4361
0
    sei_sii_params_t *ps_sei_sii;
4362
0
    int i;
4363
4364
0
    ps_ip = (ih264d_ctl_get_sei_sii_params_ip_t *) pv_api_ip;
4365
0
    ps_op = (ih264d_ctl_get_sei_sii_params_op_t *) pv_api_op;
4366
0
    UNUSED(ps_ip);
4367
4368
0
    if(0 == ps_dec->s_sei_export.u1_sei_sii_params_present_flag)
4369
0
    {
4370
0
        ps_op->u4_error_code = ERROR_SEI_SII_PARAMS_NOT_FOUND;
4371
0
        return IV_FAIL;
4372
0
    }
4373
4374
0
    ps_sei_sii = &ps_dec->s_sei_export.s_sei_sii_params;
4375
4376
0
    if((ps_sei_sii->u4_sii_sub_layer_idx > 0) &&
4377
0
       (ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag == 1))
4378
0
    {
4379
0
        ps_op->u4_error_code = ERROR_INV_SEI_SII_PARAMS;
4380
0
        return IV_FAIL;
4381
0
    }
4382
4383
0
    if((ps_sei_sii->u4_sii_sub_layer_idx > ps_sei_sii->u1_sii_max_sub_layers_minus1) &&
4384
0
       (ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag == 0))
4385
0
    {
4386
0
        ps_op->u4_error_code = ERROR_INV_SEI_SII_PARAMS;
4387
0
        return IV_FAIL;
4388
0
    }
4389
4390
0
    ps_op->u4_sii_sub_layer_idx = ps_sei_sii->u4_sii_sub_layer_idx;
4391
4392
0
    if(0 == ps_op->u4_sii_sub_layer_idx)
4393
0
    {
4394
0
        ps_op->u1_shutter_interval_info_present_flag =
4395
0
            ps_sei_sii->u1_shutter_interval_info_present_flag;
4396
4397
0
        if(1 == ps_sei_sii->u1_shutter_interval_info_present_flag)
4398
0
        {
4399
0
            ps_op->u4_sii_time_scale = ps_sei_sii->u4_sii_time_scale;
4400
0
            ps_op->u1_fixed_shutter_interval_within_cvs_flag =
4401
0
                ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag;
4402
4403
0
            if(1 == ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag)
4404
0
            {
4405
0
                ps_op->u4_sii_num_units_in_shutter_interval =
4406
0
                    ps_sei_sii->u4_sii_num_units_in_shutter_interval;
4407
0
            }
4408
0
            else
4409
0
            {
4410
0
                ps_op->u1_sii_max_sub_layers_minus1 = ps_sei_sii->u1_sii_max_sub_layers_minus1;
4411
0
                for(i = 0; i <= ps_sei_sii->u1_sii_max_sub_layers_minus1; i++)
4412
0
                {
4413
0
                    ps_op->au4_sub_layer_num_units_in_shutter_interval[i] =
4414
0
                        ps_sei_sii->au4_sub_layer_num_units_in_shutter_interval[i];
4415
0
                }
4416
0
            }
4417
0
        }
4418
0
    }
4419
4420
0
    return IV_SUCCESS;
4421
0
}
4422
4423
/*****************************************************************************/
4424
/*                                                                           */
4425
/*  Function Name : ih264d_get_sei_fgc_params                                */
4426
/*                                                                           */
4427
/*  Description   : This function populates SEI FGC message in               */
4428
/*                     output structure                                      */
4429
/*  Inputs        : iv_obj_t decoder handle                                  */
4430
/*                : pv_api_ip pointer to input structure                     */
4431
/*                : pv_api_op pointer to output structure                    */
4432
/*  Outputs       :                                                          */
4433
/*  Returns       : returns 0; 1 with error code when FGC is not present     */
4434
/*                                                                           */
4435
/*  Issues        : none                                                     */
4436
/*                                                                           */
4437
/*  Revision History:                                                        */
4438
/*                                                                           */
4439
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4440
/*                                                                           */
4441
/*                                                                           */
4442
/*****************************************************************************/
4443
WORD32 ih264d_get_sei_fgc_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4444
0
{
4445
0
    ih264d_ctl_get_sei_fgc_params_ip_t *ps_ip;
4446
0
    ih264d_ctl_get_sei_fgc_params_op_t *ps_op;
4447
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4448
0
    sei_fgc_params_t *ps_sei_fgc;
4449
0
    WORD32 i4_count;
4450
0
    UWORD32 c, i, j;
4451
4452
0
    ps_ip = (ih264d_ctl_get_sei_fgc_params_ip_t *) pv_api_ip;
4453
0
    ps_op = (ih264d_ctl_get_sei_fgc_params_op_t *) pv_api_op;
4454
0
    UNUSED(ps_ip);
4455
4456
0
    if(0 == ps_dec->s_sei_export.u1_sei_fgc_params_present_flag)
4457
0
    {
4458
0
        ps_op->u4_error_code = ERROR_SEI_FGC_PARAMS_NOT_FOUND;
4459
0
        return IV_FAIL;
4460
0
    }
4461
4462
0
    ps_sei_fgc = &ps_dec->s_sei_export.s_sei_fgc_params;
4463
4464
0
    ps_op->u1_film_grain_characteristics_cancel_flag =
4465
0
        ps_sei_fgc->u1_film_grain_characteristics_cancel_flag;
4466
4467
0
    if(0 == ps_op->u1_film_grain_characteristics_cancel_flag)
4468
0
    {
4469
0
        ps_op->i4_poc = ps_sei_fgc->i4_poc;
4470
0
        ps_op->u4_idr_pic_id = ps_sei_fgc->u4_idr_pic_id;
4471
0
        ps_op->u1_film_grain_model_id = ps_sei_fgc->u1_film_grain_model_id;
4472
0
        ps_op->u1_separate_colour_description_present_flag =
4473
0
            ps_sei_fgc->u1_separate_colour_description_present_flag;
4474
4475
0
        if(ps_op->u1_separate_colour_description_present_flag)
4476
0
        {
4477
0
            ps_op->u1_film_grain_bit_depth_luma_minus8 =
4478
0
                ps_sei_fgc->u1_film_grain_bit_depth_luma_minus8;
4479
0
            ps_op->u1_film_grain_bit_depth_chroma_minus8 =
4480
0
                ps_sei_fgc->u1_film_grain_bit_depth_chroma_minus8;
4481
0
            ps_op->u1_film_grain_full_range_flag = ps_sei_fgc->u1_film_grain_full_range_flag;
4482
0
            ps_op->u1_film_grain_colour_primaries = ps_sei_fgc->u1_film_grain_colour_primaries;
4483
0
            ps_op->u1_film_grain_transfer_characteristics =
4484
0
                ps_sei_fgc->u1_film_grain_transfer_characteristics;
4485
0
            ps_op->u1_film_grain_matrix_coefficients =
4486
0
                ps_sei_fgc->u1_film_grain_matrix_coefficients;
4487
0
        }
4488
0
        ps_op->u1_blending_mode_id = ps_sei_fgc->u1_blending_mode_id;
4489
0
        ps_op->u1_log2_scale_factor = ps_sei_fgc->u1_log2_scale_factor;
4490
4491
0
        for(c = 0; c < SEI_FGC_NUM_COLOUR_COMPONENTS; c++)
4492
0
        {
4493
0
            ps_op->au1_comp_model_present_flag[c] = ps_sei_fgc->au1_comp_model_present_flag[c];
4494
0
        }
4495
4496
0
        for(c = 0; c < SEI_FGC_NUM_COLOUR_COMPONENTS; c++)
4497
0
        {
4498
0
            if(ps_op->au1_comp_model_present_flag[c])
4499
0
            {
4500
0
                ps_op->au1_num_intensity_intervals_minus1[c] =
4501
0
                    ps_sei_fgc->au1_num_intensity_intervals_minus1[c];
4502
4503
0
                ps_op->au1_num_model_values_minus1[c] = ps_sei_fgc->au1_num_model_values_minus1[c];
4504
4505
0
                for(i = 0; i <= ps_op->au1_num_intensity_intervals_minus1[c]; i++)
4506
0
                {
4507
0
                    ps_op->au1_intensity_interval_lower_bound[c][i] =
4508
0
                        ps_sei_fgc->au1_intensity_interval_lower_bound[c][i];
4509
0
                    ps_op->au1_intensity_interval_upper_bound[c][i] =
4510
0
                        ps_sei_fgc->au1_intensity_interval_upper_bound[c][i];
4511
4512
0
                    for(j = 0; j <= ps_op->au1_num_model_values_minus1[c]; j++)
4513
0
                    {
4514
0
                        ps_op->ai4_comp_model_value[c][i][j] =
4515
0
                            ps_sei_fgc->ai4_comp_model_value[c][i][j];
4516
0
                    }
4517
0
                }
4518
0
            }
4519
0
        }
4520
0
        ps_op->u4_film_grain_characteristics_repetition_period =
4521
0
            ps_sei_fgc->u4_film_grain_characteristics_repetition_period;
4522
0
    }
4523
0
    return IV_SUCCESS;
4524
0
}
4525
4526
WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4527
0
{
4528
0
    ih264d_ctl_set_num_cores_ip_t *ps_ip;
4529
0
    ih264d_ctl_set_num_cores_op_t *ps_op;
4530
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4531
4532
0
    ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
4533
0
    ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
4534
0
    ps_op->u4_error_code = 0;
4535
0
    ps_dec->u4_num_cores = ps_ip->u4_num_cores;
4536
0
    if(ps_dec->u4_num_cores == 1)
4537
0
    {
4538
0
        ps_dec->u1_separate_parse = 0;
4539
0
    }
4540
0
    else
4541
0
    {
4542
0
        ps_dec->u1_separate_parse = 1;
4543
0
    }
4544
4545
    /*using only upto three threads currently*/
4546
0
    if(ps_dec->u4_num_cores > 3)
4547
0
        ps_dec->u4_num_cores = 3;
4548
4549
0
    return IV_SUCCESS;
4550
0
}
4551
4552
void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
4553
                                            ivd_video_decode_op_t *ps_dec_op)
4554
0
{
4555
0
    if((ps_dec_op->u4_error_code & 0xff)
4556
0
                    != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
4557
0
    {
4558
0
        ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
4559
0
        ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
4560
0
    }
4561
0
    ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
4562
0
    ps_dec_op->i4_display_index = ps_dec->i4_display_index;
4563
0
    ps_dec_op->e_pic_type = ps_dec->i4_frametype;
4564
4565
0
    ps_dec_op->u4_new_seq = 0;
4566
0
    ps_dec_op->u4_output_present = ps_dec->u4_output_present;
4567
0
    ps_dec_op->u4_progressive_frame_flag =
4568
0
                    ps_dec->s_disp_op.u4_progressive_frame_flag;
4569
4570
0
    ps_dec_op->u4_is_ref_flag = 1;
4571
0
    if(ps_dec_op->u4_frame_decoded_flag)
4572
0
    {
4573
0
        if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0)
4574
0
            ps_dec_op->u4_is_ref_flag = 0;
4575
0
    }
4576
4577
0
    ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format;
4578
0
    ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
4579
0
    ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
4580
0
    ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
4581
0
    ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
4582
4583
0
    ih264d_export_sei_params(&ps_dec_op->s_sei_decode_op, ps_dec);
4584
0
}
4585
4586
/*****************************************************************************/
4587
/*                                                                           */
4588
/*  Function Name : ih264d_api_function                                      */
4589
/*                                                                           */
4590
/*  Description   :                                                          */
4591
/*                                                                           */
4592
/*  Inputs        :iv_obj_t decoder handle                                   */
4593
/*                :pv_api_ip pointer to input structure                      */
4594
/*                :pv_api_op pointer to output structure                     */
4595
/*  Outputs       :                                                          */
4596
/*  Returns       : void                                                     */
4597
/*                                                                           */
4598
/*  Issues        : none                                                     */
4599
/*                                                                           */
4600
/*  Revision History:                                                        */
4601
/*                                                                           */
4602
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4603
/*         22 10 2008    100356         Draft                                */
4604
/*                                                                           */
4605
/*****************************************************************************/
4606
IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl,
4607
                                              void *pv_api_ip,
4608
                                              void *pv_api_op)
4609
0
{
4610
0
    UWORD32 command;
4611
0
    UWORD32 *pu2_ptr_cmd;
4612
0
    UWORD32 u4_api_ret;
4613
0
    IV_API_CALL_STATUS_T e_status;
4614
0
    e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op);
4615
4616
0
    if(e_status != IV_SUCCESS)
4617
0
    {
4618
0
        UWORD32 *ptr_err;
4619
4620
0
        ptr_err = (UWORD32 *)pv_api_op;
4621
0
        UNUSED(ptr_err);
4622
0
        H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1));
4623
0
        return IV_FAIL;
4624
0
    }
4625
4626
0
    pu2_ptr_cmd = (UWORD32 *)pv_api_ip;
4627
0
    pu2_ptr_cmd++;
4628
4629
0
    command = *pu2_ptr_cmd;
4630
//    H264_DEC_DEBUG_PRINT("inside lib = %d\n",command);
4631
0
    switch(command)
4632
0
    {
4633
4634
0
        case IVD_CMD_CREATE:
4635
0
            u4_api_ret = ih264d_create(dec_hdl, (void *)pv_api_ip,
4636
0
                                     (void *)pv_api_op);
4637
0
            break;
4638
0
        case IVD_CMD_DELETE:
4639
0
            u4_api_ret = ih264d_delete(dec_hdl, (void *)pv_api_ip,
4640
0
                                     (void *)pv_api_op);
4641
0
            break;
4642
4643
0
        case IVD_CMD_VIDEO_DECODE:
4644
0
            u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip,
4645
0
                                             (void *)pv_api_op);
4646
0
            break;
4647
4648
0
        case IVD_CMD_GET_DISPLAY_FRAME:
4649
0
            u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip,
4650
0
                                                  (void *)pv_api_op);
4651
4652
0
            break;
4653
4654
0
        case IVD_CMD_SET_DISPLAY_FRAME:
4655
0
            u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip,
4656
0
                                                  (void *)pv_api_op);
4657
4658
0
            break;
4659
4660
0
        case IVD_CMD_REL_DISPLAY_FRAME:
4661
0
            u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip,
4662
0
                                                  (void *)pv_api_op);
4663
0
            break;
4664
4665
0
        case IVD_CMD_VIDEO_CTL:
4666
0
            u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip,
4667
0
                                    (void *)pv_api_op);
4668
0
            break;
4669
0
        default:
4670
0
            u4_api_ret = IV_FAIL;
4671
0
            break;
4672
0
    }
4673
4674
0
    return u4_api_ret;
4675
0
}