Coverage Report

Created: 2025-11-24 06:53

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/libavc/decoder/mvc/imvcd_api.c
Line
Count
Source
1
/******************************************************************************
2
 *
3
 * Copyright (C) 2021 The Android Open Source Project
4
 *
5
 * Licensed under the Apache License, Version 2.0 (the "License");
6
 * you may not use this file except in compliance with the License.
7
 * You may obtain a copy of the License at:
8
 *
9
 * http://www.apache.org/licenses/LICENSE-2.0
10
 *
11
 * Unless required by applicable law or agreed to in writing, software
12
 * distributed under the License is distributed on an "AS IS" BASIS,
13
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14
 * See the License for the specific language governing permissions and
15
 * limitations under the License.
16
 *
17
 *****************************************************************************
18
 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19
 */
20
21
/*****************************************************************************/
22
/*                                                                           */
23
/*  File Name         : imvcd_api.c                                          */
24
/*                                                                           */
25
/*  Description       : Has all MVC API functions                            */
26
/*                                                                           */
27
/*                                                                           */
28
/*  List of Functions :                                                      */
29
/*                                                                           */
30
/*****************************************************************************/
31
#include <string.h>
32
33
#include "ih264_typedefs.h"
34
#include "iv.h"
35
#include "ivd.h"
36
#include "imvcd.h"
37
#include "ih264_debug.h"
38
#include "ih264_disp_mgr.h"
39
#include "ih264_error.h"
40
#include "ih264_buf_mgr.h"
41
#include "ih264_platform_macros.h"
42
#include "ih264d_inter_pred.h"
43
#include "ih264d_structs.h"
44
#include "ih264d_deblocking.h"
45
#include "ih264d_error_handler.h"
46
#include "ih264d_function_selector.h"
47
#include "ih264d_nal.h"
48
#include "ih264d_parse_cavlc.h"
49
#include "ih264d_parse_headers.h"
50
#include "ih264d_tables.h"
51
#include "ih264d_thread_compute_bs.h"
52
#include "ih264d_utils.h"
53
#include "ih264d_api_utils.h"
54
#include "ithread.h"
55
#include "imvcd_api_utils.h"
56
#include "imvcd_dpb_manager.h"
57
#include "imvcd_error_handler.h"
58
#include "imvcd_nalu_parser.h"
59
#include "imvcd_structs.h"
60
#include "imvcd_utils.h"
61
62
static void imvcd_free_static_bufs(iv_obj_t *ps_dec_hdl)
63
17.4k
{
64
17.4k
    mvc_dec_ctxt_t *ps_mvcd_ctxt;
65
17.4k
    dec_struct_t *ps_view_ctxt;
66
67
17.4k
    FT_ALIGNED_FREE *pf_aligned_free;
68
69
17.4k
    void *pv_mem_ctxt;
70
71
17.4k
    if(!ps_dec_hdl)
72
0
    {
73
0
        return;
74
0
    }
75
76
17.4k
    ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
77
78
17.4k
    if(!ps_mvcd_ctxt)
79
0
    {
80
0
        return;
81
0
    }
82
83
17.4k
    ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
84
17.4k
    pf_aligned_free = ps_view_ctxt->pf_aligned_free;
85
17.4k
    pv_mem_ctxt = ps_view_ctxt->pv_mem_ctxt;
86
87
17.4k
    imvcd_free_dynamic_bufs(ps_mvcd_ctxt);
88
89
17.4k
    imvcd_bitsteam_buf_free(ps_view_ctxt);
90
91
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_left_mvpred_addr);
92
93
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu4_wts_ofsts_mat);
94
95
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu4_mbaff_wt_mat);
96
97
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu1_init_dpb_base);
98
99
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu1_temp_mc_buffer);
100
101
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pi2_pred1);
102
103
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu1_ref_buff_base);
104
105
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_left_mb_ctxt_info);
106
107
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->p_cabac_ctxt_table_t);
108
109
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ppv_map_ref_idx_to_poc_base);
110
111
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu1_bits_buf_static);
112
113
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pv_scratch_sps_pps);
114
115
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_bitstrm);
116
117
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_dpb_cmds);
118
119
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_sei_parse);
120
121
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_sei);
122
123
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_dec_err_status);
124
125
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_pred);
126
127
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pv_bs_deblk_thread_handle);
128
129
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pv_dec_thread_handle);
130
131
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_pps);
132
133
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_sps);
134
135
17.4k
    ih264_buf_mgr_free(ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.pv_mem);
136
137
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.pv_mem);
138
139
17.4k
    ih264_buf_mgr_free(ps_mvcd_ctxt->s_mvc_au_buf_mgr.pv_mem);
140
141
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_mvcd_ctxt->s_mvc_au_buf_mgr.pv_mem);
142
143
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_mvcd_ctxt->ps_dpb_mgr);
144
145
17.4k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_mvcd_ctxt);
146
147
17.4k
    if(ps_dec_hdl)
148
17.4k
    {
149
17.4k
        pf_aligned_free(pv_mem_ctxt, ps_dec_hdl);
150
17.4k
    }
151
17.4k
}
152
153
static IV_API_CALL_STATUS_T imvcd_view_ctxt_init(imvcd_create_ip_t *ps_ip,
154
                                                 dec_struct_t *ps_view_ctxt)
155
17.4k
{
156
17.4k
    pocstruct_t *ps_prev_poc, *ps_cur_poc;
157
158
17.4k
    WORD32 i4_mem_size;
159
17.4k
    void *pv_buf;
160
161
17.4k
    FT_ALIGNED_ALLOC *pf_aligned_alloc = ps_ip->s_ivd_ip.pf_aligned_alloc;
162
163
17.4k
    void *pv_mem_ctxt = ps_ip->s_ivd_ip.pv_mem_ctxt;
164
17.4k
    const WORD32 i4_default_alignment = 128;
165
166
17.4k
    ps_view_ctxt->u4_share_disp_buf = 0;
167
17.4k
    ps_view_ctxt->u1_chroma_format = ps_ip->s_ivd_ip.e_output_format;
168
169
17.4k
    ps_view_ctxt->pf_aligned_alloc = pf_aligned_alloc;
170
17.4k
    ps_view_ctxt->pf_aligned_free = ps_ip->s_ivd_ip.pf_aligned_free;
171
17.4k
    ps_view_ctxt->pv_mem_ctxt = ps_ip->s_ivd_ip.pv_mem_ctxt;
172
173
17.4k
    i4_mem_size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS);
174
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
175
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
176
17.4k
    memset(pv_buf, 0, i4_mem_size);
177
17.4k
    ps_view_ctxt->ps_sps = pv_buf;
178
179
17.4k
    i4_mem_size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS;
180
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
181
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
182
17.4k
    memset(pv_buf, 0, i4_mem_size);
183
17.4k
    ps_view_ctxt->ps_pps = pv_buf;
184
185
17.4k
    i4_mem_size = ithread_get_handle_size();
186
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
187
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
188
17.4k
    memset(pv_buf, 0, i4_mem_size);
189
17.4k
    ps_view_ctxt->pv_dec_thread_handle = pv_buf;
190
191
17.4k
    i4_mem_size = ithread_get_handle_size();
192
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
193
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
194
17.4k
    memset(pv_buf, 0, i4_mem_size);
195
17.4k
    ps_view_ctxt->pv_bs_deblk_thread_handle = pv_buf;
196
197
17.4k
    i4_mem_size = sizeof(pred_info_t) * 2 * 32;
198
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
199
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
200
17.4k
    memset(pv_buf, 0, i4_mem_size);
201
17.4k
    ps_view_ctxt->ps_pred = pv_buf;
202
203
17.4k
    ps_view_ctxt->pv_disp_buf_mgr = NULL;
204
205
17.4k
    ps_view_ctxt->pv_pic_buf_mgr = NULL;
206
207
17.4k
    ps_view_ctxt->ps_pic_buf_base = NULL;
208
209
17.4k
    i4_mem_size = sizeof(dec_err_status_t);
210
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
211
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
212
17.4k
    memset(pv_buf, 0, i4_mem_size);
213
17.4k
    ps_view_ctxt->ps_dec_err_status = (dec_err_status_t *) pv_buf;
214
215
17.4k
    i4_mem_size = sizeof(sei);
216
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
217
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
218
17.4k
    memset(pv_buf, 0, i4_mem_size);
219
17.4k
    ps_view_ctxt->ps_sei = (sei *) pv_buf;
220
221
17.4k
    i4_mem_size = sizeof(sei);
222
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
223
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
224
17.4k
    memset(pv_buf, 0, i4_mem_size);
225
17.4k
    ps_view_ctxt->ps_sei_parse = (sei *) pv_buf;
226
227
17.4k
    i4_mem_size = sizeof(dpb_commands_t);
228
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
229
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
230
17.4k
    memset(pv_buf, 0, i4_mem_size);
231
17.4k
    ps_view_ctxt->ps_dpb_cmds = (dpb_commands_t *) pv_buf;
232
233
17.4k
    i4_mem_size = sizeof(dec_bit_stream_t);
234
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
235
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
236
17.4k
    memset(pv_buf, 0, i4_mem_size);
237
17.4k
    ps_view_ctxt->ps_bitstrm = (dec_bit_stream_t *) pv_buf;
238
239
17.4k
    i4_mem_size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
240
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
241
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
242
17.4k
    memset(pv_buf, 0, i4_mem_size);
243
17.4k
    ps_view_ctxt->pv_scratch_sps_pps = pv_buf;
244
245
17.4k
    ps_view_ctxt->u4_static_bits_buf_size = MIN_BITSTREAMS_BUF_SIZE;
246
17.4k
    pv_buf =
247
17.4k
        pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, ps_view_ctxt->u4_static_bits_buf_size);
248
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
249
17.4k
    memset(pv_buf, 0, ps_view_ctxt->u4_static_bits_buf_size);
250
17.4k
    ps_view_ctxt->pu1_bits_buf_static = pv_buf;
251
252
17.4k
    i4_mem_size = (TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) * sizeof(void *);
253
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
254
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
255
17.4k
    ps_view_ctxt->ppv_map_ref_idx_to_poc_base = pv_buf;
256
17.4k
    ps_view_ctxt->ppv_map_ref_idx_to_poc =
257
17.4k
        ps_view_ctxt->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC;
258
17.4k
    memset(ps_view_ctxt->ppv_map_ref_idx_to_poc_base, 0, i4_mem_size);
259
260
17.4k
    i4_mem_size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
261
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
262
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
263
17.4k
    memset(pv_buf, 0, i4_mem_size);
264
17.4k
    ps_view_ctxt->p_cabac_ctxt_table_t = pv_buf;
265
266
17.4k
    i4_mem_size = sizeof(ctxt_inc_mb_info_t);
267
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
268
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
269
17.4k
    memset(pv_buf, 0, i4_mem_size);
270
17.4k
    ps_view_ctxt->ps_left_mb_ctxt_info = pv_buf;
271
272
17.4k
    i4_mem_size = MAX_REF_BUF_SIZE * 2;
273
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
274
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
275
17.4k
    memset(pv_buf, 0, i4_mem_size);
276
17.4k
    ps_view_ctxt->pu1_ref_buff_base = pv_buf;
277
17.4k
    ps_view_ctxt->pu1_ref_buff = ps_view_ctxt->pu1_ref_buff_base + MAX_REF_BUF_SIZE;
278
279
17.4k
    i4_mem_size = sizeof(WORD16) * PRED_BUFFER_WIDTH * PRED_BUFFER_HEIGHT * 2;
280
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
281
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
282
17.4k
    memset(pv_buf, 0, i4_mem_size);
283
17.4k
    ps_view_ctxt->pi2_pred1 = pv_buf;
284
285
17.4k
    i4_mem_size = sizeof(UWORD8) * (MB_LUM_SIZE);
286
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
287
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
288
17.4k
    memset(pv_buf, 0, i4_mem_size);
289
17.4k
    ps_view_ctxt->pu1_temp_mc_buffer = pv_buf;
290
291
17.4k
    i4_mem_size = (sizeof(UWORD32) * 2 * 3 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)) * 2);
292
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
293
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
294
17.4k
    memset(pv_buf, 0, i4_mem_size);
295
17.4k
    ps_view_ctxt->pu4_mbaff_wt_mat = pv_buf;
296
297
17.4k
    i4_mem_size = sizeof(UWORD32) * 2 * 3 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1));
298
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
299
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
300
17.4k
    memset(pv_buf, 0, i4_mem_size);
301
17.4k
    ps_view_ctxt->pu4_wts_ofsts_mat = pv_buf;
302
303
17.4k
    i4_mem_size = (sizeof(neighbouradd_t) << 2);
304
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
305
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
306
17.4k
    memset(pv_buf, 0, i4_mem_size);
307
17.4k
    ps_view_ctxt->ps_left_mvpred_addr = pv_buf;
308
309
17.4k
    ps_view_ctxt->pv_mv_buf_mgr = NULL;
310
311
17.4k
    ps_view_ctxt->ps_col_mv_base = NULL;
312
313
17.4k
    ps_view_ctxt->init_done = 0;
314
17.4k
    ps_view_ctxt->u4_num_cores = 1;
315
17.4k
    ps_view_ctxt->u2_pic_ht = ps_view_ctxt->u2_pic_wd = 0;
316
17.4k
    ps_view_ctxt->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
317
17.4k
    ps_view_ctxt->u4_app_disable_deblk_frm = 0;
318
17.4k
    ps_view_ctxt->i4_degrade_type = 0;
319
17.4k
    ps_view_ctxt->i4_degrade_pics = 0;
320
321
17.4k
    memset(ps_view_ctxt->ps_pps, 0, ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
322
17.4k
    memset(ps_view_ctxt->ps_sps, 0, ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
323
324
17.4k
    ps_view_ctxt->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
325
17.4k
    ps_view_ctxt->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
326
17.4k
    ps_view_ctxt->s_cab_dec_env.pv_codec_handle = ps_view_ctxt;
327
17.4k
    ps_view_ctxt->u4_num_fld_in_frm = 0;
328
17.4k
    ps_view_ctxt->ps_sei->u1_is_valid = 0;
329
17.4k
    ps_view_ctxt->ps_cur_pps = NULL;
330
17.4k
    ps_view_ctxt->ps_cur_sps = NULL;
331
17.4k
    ps_view_ctxt->ps_cur_slice = NULL;
332
17.4k
    ps_view_ctxt->u1_init_dec_flag = 0;
333
17.4k
    ps_view_ctxt->u1_first_slice_in_stream = 1;
334
17.4k
    ps_view_ctxt->u1_last_pic_not_decoded = 0;
335
17.4k
    ps_view_ctxt->u4_app_disp_width = 0;
336
17.4k
    ps_view_ctxt->i4_header_decoded = 0;
337
17.4k
    ps_view_ctxt->u4_total_frames_decoded = 0;
338
17.4k
    ps_view_ctxt->i4_error_code = 0;
339
17.4k
    ps_view_ctxt->i4_content_type = IV_CONTENTTYPE_NA;
340
17.4k
    ps_view_ctxt->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS;
341
17.4k
    ps_view_ctxt->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
342
17.4k
    ps_view_ctxt->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
343
17.4k
    ps_view_ctxt->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
344
17.4k
    ps_view_ctxt->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
345
17.4k
    ps_view_ctxt->u1_pr_sl_type = 0xFF;
346
17.4k
    ps_view_ctxt->u2_mbx = 0xffff;
347
17.4k
    ps_view_ctxt->u2_mby = 0;
348
17.4k
    ps_view_ctxt->u4_total_mbs_coded = 0;
349
350
17.4k
    ps_prev_poc = &ps_view_ctxt->s_prev_pic_poc;
351
17.4k
    ps_cur_poc = &ps_view_ctxt->s_cur_pic_poc;
352
17.4k
    ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
353
17.4k
    ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
354
17.4k
    ps_prev_poc->i4_delta_pic_order_cnt_bottom = ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
355
17.4k
    ps_prev_poc->i4_delta_pic_order_cnt[0] = ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
356
17.4k
    ps_prev_poc->i4_delta_pic_order_cnt[1] = ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
357
17.4k
    ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
358
17.4k
    ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count = 0;
359
17.4k
    ps_prev_poc->i4_bottom_field_order_count = ps_cur_poc->i4_bottom_field_order_count = 0;
360
17.4k
    ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
361
17.4k
    ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
362
17.4k
    ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
363
364
17.4k
    ps_view_ctxt->i4_max_poc = 0;
365
17.4k
    ps_view_ctxt->i4_prev_max_display_seq = 0;
366
17.4k
    ps_view_ctxt->u4_recon_mb_grp = 4;
367
17.4k
    ps_view_ctxt->i4_reorder_depth = -1;
368
17.4k
    ps_view_ctxt->u1_second_field = 0;
369
17.4k
    ps_view_ctxt->s_prev_seq_params.u1_eoseq_pending = 0;
370
17.4k
    ps_view_ctxt->u2_crop_offset_y = 0;
371
17.4k
    ps_view_ctxt->u2_crop_offset_uv = 0;
372
17.4k
    ps_view_ctxt->i4_vui_frame_rate = -1;
373
17.4k
    ps_view_ctxt->i4_pic_type = NA_SLICE;
374
17.4k
    ps_view_ctxt->i4_frametype = IV_NA_FRAME;
375
17.4k
    ps_view_ctxt->i4_content_type = IV_CONTENTTYPE_NA;
376
17.4k
    ps_view_ctxt->u1_res_changed = 0;
377
17.4k
    ps_view_ctxt->u1_frame_decoded_flag = 0;
378
17.4k
    ps_view_ctxt->u4_skip_frm_mask = SKIP_NONE;
379
380
17.4k
    ps_view_ctxt->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
381
17.4k
    ps_view_ctxt->pf_cavlc_4x4res_block[1] = ih264d_cavlc_4x4res_block_totalcoeff_2to10;
382
17.4k
    ps_view_ctxt->pf_cavlc_4x4res_block[2] = ih264d_cavlc_4x4res_block_totalcoeff_11to16;
383
17.4k
    ps_view_ctxt->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
384
17.4k
    ps_view_ctxt->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
385
17.4k
    ps_view_ctxt->pf_cavlc_parse_8x8block[0] = ih264d_cavlc_parse_8x8block_none_available;
386
17.4k
    ps_view_ctxt->pf_cavlc_parse_8x8block[1] = ih264d_cavlc_parse_8x8block_left_available;
387
17.4k
    ps_view_ctxt->pf_cavlc_parse_8x8block[2] = ih264d_cavlc_parse_8x8block_top_available;
388
17.4k
    ps_view_ctxt->pf_cavlc_parse_8x8block[3] = ih264d_cavlc_parse_8x8block_both_available;
389
390
17.4k
    ps_view_ctxt->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
391
17.4k
    ps_view_ctxt->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
392
17.4k
    ps_view_ctxt->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
393
17.4k
    ps_view_ctxt->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
394
17.4k
    ps_view_ctxt->pf_fill_bs_xtra_left_edge[0] = ih264d_fill_bs_xtra_left_edge_cur_frm;
395
17.4k
    ps_view_ctxt->pf_fill_bs_xtra_left_edge[1] = ih264d_fill_bs_xtra_left_edge_cur_fld;
396
397
17.4k
    ps_view_ctxt->u2_prv_frame_num = 0;
398
17.4k
    ps_view_ctxt->u1_top_bottom_decoded = 0;
399
17.4k
    ps_view_ctxt->u1_dangling_field = 0;
400
17.4k
    ps_view_ctxt->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
401
17.4k
    ps_view_ctxt->pu1_left_mv_ctxt_inc = ps_view_ctxt->u1_left_mv_ctxt_inc_arr[0];
402
17.4k
    ps_view_ctxt->pi1_left_ref_idx_ctxt_inc = &ps_view_ctxt->i1_left_ref_idx_ctx_inc_arr[0][0];
403
17.4k
    ps_view_ctxt->pu1_left_yuv_dc_csbp = &ps_view_ctxt->u1_yuv_dc_csbp_topmb;
404
17.4k
    ps_view_ctxt->u1_flushfrm = 0;
405
17.4k
    ps_view_ctxt->s_cab_dec_env.pv_codec_handle = ps_view_ctxt;
406
17.4k
    ps_view_ctxt->ps_bitstrm->pv_codec_handle = ps_view_ctxt;
407
408
17.4k
    memset(ps_view_ctxt->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
409
17.4k
    memset(ps_view_ctxt->u4_disp_buf_mapping, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
410
17.4k
    memset(ps_view_ctxt->u4_disp_buf_to_be_freed, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
411
412
17.4k
    ih264d_init_arch(ps_view_ctxt);
413
17.4k
    ih264d_init_function_ptr(ps_view_ctxt);
414
17.4k
    ps_view_ctxt->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
415
17.4k
    ps_view_ctxt->init_done = 1;
416
417
17.4k
    return IV_SUCCESS;
418
17.4k
}
419
420
static IV_API_CALL_STATUS_T imvcd_ctxt_init(imvcd_create_ip_t *ps_ip, mvc_dec_ctxt_t *ps_mvcd_ctxt)
421
17.4k
{
422
17.4k
    WORD32 i4_mem_size;
423
17.4k
    void *pv_buf;
424
425
17.4k
    FT_ALIGNED_ALLOC *pf_aligned_alloc = ps_ip->s_ivd_ip.pf_aligned_alloc;
426
427
17.4k
    void *pv_mem_ctxt = ps_ip->s_ivd_ip.pv_mem_ctxt;
428
17.4k
    const WORD32 i4_default_alignment = 128;
429
430
17.4k
    memset(ps_mvcd_ctxt, 0, sizeof(ps_mvcd_ctxt[0]));
431
432
17.4k
    i4_mem_size = sizeof(mvc_dpb_manager_t);
433
17.4k
    ps_mvcd_ctxt->ps_dpb_mgr = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
434
17.4k
    RETURN_IF((NULL == ps_mvcd_ctxt->ps_dpb_mgr), IV_FAIL);
435
17.4k
    memset(ps_mvcd_ctxt->ps_dpb_mgr, 0, i4_mem_size);
436
437
17.4k
    imvcd_init_dpb_mgr(ps_mvcd_ctxt->ps_dpb_mgr, &ps_mvcd_ctxt->s_mvc_au_buf_mgr,
438
17.4k
                       &ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr, &ps_mvcd_ctxt->s_mvc_disp_buf_mgr);
439
440
17.4k
    ih264_disp_mgr_init(&ps_mvcd_ctxt->s_mvc_disp_buf_mgr);
441
442
17.4k
    i4_mem_size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
443
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
444
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
445
17.4k
    memset(pv_buf, 0, i4_mem_size);
446
17.4k
    ps_mvcd_ctxt->s_mvc_au_buf_mgr.pv_mem = pv_buf;
447
17.4k
    ps_mvcd_ctxt->s_mvc_au_buf_mgr.ps_buf_mgr_ctxt = pv_buf;
448
449
17.4k
    ih264_buf_mgr_init(ps_mvcd_ctxt->s_mvc_au_buf_mgr.pv_mem);
450
451
17.4k
    i4_mem_size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
452
17.4k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
453
17.4k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
454
17.4k
    memset(pv_buf, 0, i4_mem_size);
455
17.4k
    ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.pv_mem = pv_buf;
456
17.4k
    ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.ps_buf_mgr_ctxt = pv_buf;
457
458
17.4k
    ih264_buf_mgr_init(ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.pv_mem);
459
460
17.4k
    if(IV_SUCCESS != imvcd_view_ctxt_init(ps_ip, &ps_mvcd_ctxt->s_view_dec_ctxt))
461
0
    {
462
0
        return IV_FAIL;
463
0
    }
464
465
17.4k
    ps_mvcd_ctxt->u2_num_views = 0;
466
17.4k
    ps_mvcd_ctxt->u2_num_views_decoded = 0;
467
468
17.4k
    return IV_SUCCESS;
469
17.4k
}
470
471
static IV_API_CALL_STATUS_T imvcd_allocate_static_bufs(imvcd_create_ip_t *ps_ip,
472
                                                       imvcd_create_op_t *ps_op)
473
17.4k
{
474
17.4k
    iv_obj_t *ps_dec_hdl;
475
17.4k
    mvc_dec_ctxt_t *ps_mvcd_ctxt;
476
477
17.4k
    WORD32 i4_mem_size;
478
479
17.4k
    FT_ALIGNED_ALLOC *pf_aligned_alloc = ps_ip->s_ivd_ip.pf_aligned_alloc;
480
481
17.4k
    void *pv_mem_ctxt = ps_ip->s_ivd_ip.pv_mem_ctxt;
482
17.4k
    const WORD32 i4_default_alignment = 128;
483
484
17.4k
    i4_mem_size = sizeof(ps_dec_hdl[0]);
485
17.4k
    ps_op->s_ivd_op.pv_handle = ps_dec_hdl =
486
17.4k
        (iv_obj_t *) pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
487
488
17.4k
    if(NULL == ps_dec_hdl)
489
0
    {
490
0
        return IV_FAIL;
491
0
    }
492
493
17.4k
    i4_mem_size = sizeof(ps_mvcd_ctxt[0]);
494
17.4k
    ps_dec_hdl->pv_codec_handle = ps_mvcd_ctxt =
495
17.4k
        (mvc_dec_ctxt_t *) pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
496
497
17.4k
    if(NULL == ps_mvcd_ctxt)
498
0
    {
499
0
        return IV_FAIL;
500
0
    }
501
502
17.4k
    if(IV_SUCCESS != imvcd_ctxt_init(ps_ip, ps_mvcd_ctxt))
503
0
    {
504
0
        return IV_FAIL;
505
0
    }
506
507
17.4k
    return IV_SUCCESS;
508
17.4k
}
509
510
/* Description - 'Create' API for MVC Decoder */
511
static IV_API_CALL_STATUS_T imvcd_create(imvcd_create_ip_t *ps_ip, imvcd_create_op_t *ps_op)
512
17.4k
{
513
17.4k
    if(IV_SUCCESS != imvcd_check_create_structs(ps_ip, ps_op))
514
0
    {
515
0
        return IV_FAIL;
516
0
    }
517
518
17.4k
    if(IV_SUCCESS != imvcd_allocate_static_bufs(ps_ip, ps_op))
519
0
    {
520
0
        imvcd_free_static_bufs((iv_obj_t *) ps_op->s_ivd_op.pv_handle);
521
522
0
        return IV_FAIL;
523
0
    }
524
525
17.4k
    return IV_SUCCESS;
526
17.4k
}
527
528
/* Description - 'Delete' API for MVC Decoder */
529
static IV_API_CALL_STATUS_T imvcd_delete(iv_obj_t *ps_dec_hdl)
530
17.4k
{
531
17.4k
    if(IV_SUCCESS != imvcd_check_dec_handle(ps_dec_hdl))
532
0
    {
533
0
        return IV_FAIL;
534
0
    }
535
536
17.4k
    imvcd_free_static_bufs(ps_dec_hdl);
537
538
17.4k
    return IV_SUCCESS;
539
17.4k
}
540
541
static IV_API_CALL_STATUS_T imvcd_flush_mode_decode(mvc_dec_ctxt_t *ps_mvcd_ctxt,
542
                                                    imvcd_video_decode_op_t *ps_op)
543
0
{
544
0
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
545
546
0
    if(!ps_view_ctxt->u1_init_dec_flag)
547
0
    {
548
0
        ps_view_ctxt->u1_flushfrm = 0;
549
0
        ps_mvcd_ctxt->b_flush_enabled = false;
550
0
        ps_op->s_ivd_op.u4_output_present = 0;
551
552
0
        return IV_FAIL;
553
0
    }
554
555
0
    if(IV_SUCCESS != imvcd_get_next_display_au_buf(ps_mvcd_ctxt))
556
0
    {
557
0
        ps_view_ctxt->u1_flushfrm = 0;
558
0
        ps_mvcd_ctxt->b_flush_enabled = false;
559
0
        ps_op->s_ivd_op.u4_output_present = false;
560
561
0
        return IV_SUCCESS;
562
0
    }
563
564
0
    ih264d_export_sei_params(&ps_op->s_ivd_op.s_sei_decode_op, ps_view_ctxt);
565
566
0
    ps_op->s_ivd_op.u4_pic_wd = ps_view_ctxt->u2_disp_width;
567
0
    ps_op->s_ivd_op.u4_pic_ht = ps_view_ctxt->u2_disp_height;
568
0
    ps_op->s_ivd_op.u4_ts = ps_view_ctxt->s_disp_op.u4_ts;
569
0
    ps_op->s_ivd_op.u4_output_present = 1;
570
0
    ps_op->s_ivd_op.e_output_format = IV_YUV_420P;
571
572
0
    imvcd_convert_to_app_disp_buf(ps_mvcd_ctxt, ps_op->ps_view_disp_bufs);
573
574
0
    return IV_SUCCESS;
575
0
}
576
577
static void imvcd_fill_output_struct_from_context(mvc_dec_ctxt_t *ps_mvcd_ctxt,
578
                                                  imvcd_video_decode_op_t *ps_op)
579
11.8k
{
580
11.8k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
581
582
11.8k
    if((ps_op->s_ivd_op.u4_error_code & 0xff) != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
583
11.8k
    {
584
11.8k
        ps_op->s_ivd_op.u4_pic_wd = ps_view_ctxt->u2_disp_width;
585
11.8k
        ps_op->s_ivd_op.u4_pic_ht = ps_view_ctxt->u2_disp_height;
586
11.8k
    }
587
588
11.8k
    ps_op->s_ivd_op.u4_output_present = ps_view_ctxt->u4_output_present;
589
590
11.8k
    ps_op->s_ivd_op.e_output_format = IV_YUV_420P;
591
592
11.8k
    imvcd_convert_to_app_disp_buf(ps_mvcd_ctxt, ps_op->ps_view_disp_bufs);
593
594
11.8k
    ih264d_export_sei_params(&ps_op->s_ivd_op.s_sei_decode_op, ps_view_ctxt);
595
11.8k
}
596
597
static void imvcd_video_decode_clean_return(mvc_dec_ctxt_t *ps_mvcd_ctxt,
598
                                            imvcd_video_decode_ip_t *ps_ip,
599
                                            imvcd_video_decode_op_t *ps_op)
600
11.7k
{
601
11.7k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
602
603
11.7k
    ih264d_signal_decode_thread(ps_view_ctxt);
604
11.7k
    ih264d_signal_bs_deblk_thread(ps_view_ctxt);
605
606
11.7k
    imvcd_fill_output_struct_from_context(ps_mvcd_ctxt, ps_op);
607
608
11.7k
    ps_op->s_ivd_op.u4_frame_decoded_flag = 0;
609
11.7k
    ps_op->s_ivd_op.u4_num_bytes_consumed = ps_ip->s_ivd_ip.u4_num_Bytes;
610
11.7k
}
611
612
static FORCEINLINE void imvcd_update_num_pps(mvc_dec_ctxt_t *ps_mvcd_ctxt)
613
38.2k
{
614
38.2k
    WORD32 i;
615
616
38.2k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
617
618
38.2k
    ps_mvcd_ctxt->u1_num_pps = 0;
619
620
9.81M
    for(i = 0; i < MAX_NUM_PIC_PARAMS; i++)
621
9.78M
    {
622
9.78M
        if(ps_view_ctxt->ps_pps[i].u1_is_valid)
623
40.2k
        {
624
40.2k
            UWORD8 u1_sps_id = ps_view_ctxt->ps_pps[i].ps_sps->u1_seq_parameter_set_id;
625
626
40.2k
            if(ps_mvcd_ctxt->as_subset_sps[u1_sps_id].s_sps_data.u1_is_valid)
627
529
            {
628
529
                ps_mvcd_ctxt->aps_pps_id_to_subset_sps_map[i] =
629
529
                    &ps_mvcd_ctxt->as_subset_sps[u1_sps_id];
630
529
            }
631
632
40.2k
            ps_mvcd_ctxt->u1_num_pps++;
633
40.2k
        }
634
9.78M
    }
635
38.2k
}
636
637
static FORCEINLINE void imvcd_update_num_sps(mvc_dec_ctxt_t *ps_mvcd_ctxt)
638
40.3k
{
639
40.3k
    WORD32 i;
640
641
40.3k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
642
643
40.3k
    ps_mvcd_ctxt->u1_num_sps = 0;
644
645
1.33M
    for(i = 0; i < MAX_NUM_SEQ_PARAMS; i++)
646
1.29M
    {
647
1.29M
        if(ps_view_ctxt->ps_sps[i].u1_is_valid)
648
41.9k
        {
649
41.9k
            ps_mvcd_ctxt->u1_num_sps++;
650
41.9k
        }
651
1.29M
    }
652
40.3k
}
653
654
static FORCEINLINE void imvcd_update_num_subset_sps(mvc_dec_ctxt_t *ps_mvcd_ctxt)
655
4.81k
{
656
4.81k
    WORD32 i;
657
658
4.81k
    ps_mvcd_ctxt->u1_num_subset_sps = 0;
659
660
158k
    for(i = 0; i < MAX_NUM_SEQ_PARAMS; i++)
661
154k
    {
662
154k
        if(ps_mvcd_ctxt->as_subset_sps[i].s_sps_data.u1_is_valid)
663
5.78k
        {
664
5.78k
            ps_mvcd_ctxt->u1_num_subset_sps++;
665
5.78k
        }
666
154k
    }
667
4.81k
}
668
669
static IV_API_CALL_STATUS_T imvcd_view_decode(iv_obj_t *ps_dec_hdl, imvcd_video_decode_ip_t *ps_ip,
670
                                              imvcd_video_decode_op_t *ps_op)
671
139k
{
672
139k
    UWORD8 *pu1_input_buffer;
673
139k
    UWORD8 *pu1_bitstream_buf;
674
139k
    UWORD32 u4_bitstream_buf_size;
675
139k
    WORD32 i4_nalu_length;
676
139k
    UWORD32 u4_length_of_start_code;
677
139k
    WORD32 i4_error_code;
678
679
139k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
680
139k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
681
682
139k
    UWORD32 u4_num_bytes_consumed = 0;
683
139k
    UWORD32 u4_num_bytes_remaining = ps_ip->s_ivd_ip.u4_num_Bytes;
684
139k
    bool b_first_start_code_found = false;
685
139k
    bool b_frame_data_left = true;
686
139k
    bool b_header_data_left = true;
687
139k
    UWORD32 u4_next_is_aud = 0;
688
689
139k
    ASSERT(u4_num_bytes_remaining > 0);
690
691
139k
    imvcd_view_init(ps_mvcd_ctxt);
692
693
139k
    do
694
224k
    {
695
224k
        pu1_input_buffer = ((UWORD8 *) ps_ip->s_ivd_ip.pv_stream_buffer) + u4_num_bytes_consumed;
696
697
224k
        if(!ps_view_ctxt->pu1_bits_buf_dynamic &&
698
60.4k
           is_header_decoded(ps_view_ctxt->i4_header_decoded, PPS))
699
14.6k
        {
700
14.6k
            if(IV_SUCCESS !=
701
14.6k
               imvcd_bitstream_buf_alloc(
702
14.6k
                   ps_view_ctxt, is_header_decoded(ps_view_ctxt->i4_header_decoded, SUBSET_SPS)
703
14.6k
                                     ? ps_mvcd_ctxt->u2_num_views
704
14.6k
                                     : 1))
705
0
            {
706
0
                return IV_FAIL;
707
0
            }
708
14.6k
        }
709
710
224k
        if(ps_view_ctxt->pu1_bits_buf_dynamic)
711
178k
        {
712
178k
            pu1_bitstream_buf = ps_view_ctxt->pu1_bits_buf_dynamic;
713
178k
            u4_bitstream_buf_size = ps_view_ctxt->u4_dynamic_bits_buf_size;
714
178k
        }
715
45.7k
        else
716
45.7k
        {
717
45.7k
            pu1_bitstream_buf = ps_view_ctxt->pu1_bits_buf_static;
718
45.7k
            u4_bitstream_buf_size = ps_view_ctxt->u4_static_bits_buf_size;
719
45.7k
        }
720
721
224k
        i4_nalu_length = ih264d_find_start_code(pu1_input_buffer, 0, u4_num_bytes_remaining,
722
224k
                                                &u4_length_of_start_code, &u4_next_is_aud);
723
724
224k
        if(i4_nalu_length == -1)
725
0
        {
726
0
            i4_nalu_length = 0;
727
0
        }
728
729
224k
        if((0 != u4_next_is_aud) && (1 != u4_next_is_aud))
730
0
        {
731
0
            return IV_FAIL;
732
0
        }
733
734
224k
        if(i4_nalu_length)
735
223k
        {
736
            /* In some erroneous fuzzer bistreams, the slice data requires more
737
              parsing than what was implied by the distance between successive
738
              start codes.The primary culprit is the NEXTBITS macro which requires
739
              reading 4 additional bytes of the bitstream buffer.To alleviate
740
              this, 16 bytes per 4x4 TU have been additionally allocated to the
741
              bitstream buffer. Also, chroma bytes are added for 4:2:0/4:2:2 */
742
743
223k
            UWORD32 u4_nalu_buf_size = ((UWORD32) i4_nalu_length) + 8 + EXTRA_BS_OFFSET;
744
745
223k
            if(u4_nalu_buf_size > u4_bitstream_buf_size)
746
38
            {
747
                /* 64 extra bytes to account for OOB accesses during SEI parsing in */
748
                /* some fuzzer bitstreams */
749
38
                if(IV_SUCCESS != imvcd_bitstream_buf_realloc(ps_view_ctxt, u4_nalu_buf_size + 64))
750
0
                {
751
0
                    return IV_FAIL;
752
0
                }
753
754
38
                pu1_bitstream_buf = ps_view_ctxt->pu1_bits_buf_dynamic;
755
38
                u4_bitstream_buf_size = ps_view_ctxt->u4_dynamic_bits_buf_size;
756
38
            }
757
758
223k
            memcpy(pu1_bitstream_buf, pu1_input_buffer + u4_length_of_start_code, i4_nalu_length);
759
760
            /* Decoder may read extra 8 bytes near end of the frame */
761
223k
            if(u4_nalu_buf_size < u4_bitstream_buf_size)
762
223k
            {
763
223k
                memset(pu1_bitstream_buf + i4_nalu_length, 0, 8 * sizeof(pu1_bitstream_buf[0]));
764
223k
            }
765
766
223k
            b_first_start_code_found = true;
767
223k
        }
768
366
        else
769
366
        {
770
366
            if(!b_first_start_code_found)
771
54
            {
772
54
                ps_view_ctxt->i4_error_code = ERROR_START_CODE_NOT_FOUND;
773
54
                ps_op->s_ivd_op.u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
774
775
54
                if(ps_view_ctxt->u4_pic_buf_got == 0)
776
54
                {
777
54
                    imvcd_fill_output_struct_from_context(ps_mvcd_ctxt, ps_op);
778
779
54
                    ps_op->s_ivd_op.u4_error_code = ps_view_ctxt->i4_error_code;
780
781
54
                    imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
782
783
54
                    return IV_FAIL;
784
54
                }
785
0
                else
786
0
                {
787
0
                    ps_view_ctxt->u1_pic_decode_done = 1;
788
789
0
                    continue;
790
0
                }
791
54
            }
792
312
            else
793
312
            {
794
                /* a start code has already been found earlier in the same process
795
                 * call*/
796
312
                b_frame_data_left = false;
797
312
                b_header_data_left = false;
798
799
312
                if(!ps_view_ctxt->i4_decode_header && !ps_view_ctxt->u4_pic_buf_got)
800
0
                {
801
0
                    ps_op->s_ivd_op.u4_error_code = ih264d_map_error(ERROR_UNKNOWN_NAL);
802
803
0
                    imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
804
805
0
                    return IV_FAIL;
806
0
                }
807
808
312
                continue;
809
312
            }
810
366
        }
811
812
223k
        ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded] =
813
223k
            NAL_UNIT_TYPE(pu1_bitstream_buf[0]);
814
223k
        ps_mvcd_ctxt->au1_nal_ref_idc[ps_mvcd_ctxt->u2_num_views_decoded] =
815
223k
            NAL_REF_IDC(pu1_bitstream_buf[0]);
816
817
223k
        if(ps_view_ctxt->u4_dec_thread_created &&
818
85
           !is_slice_nalu_type(ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded]))
819
10
        {
820
10
            ps_op->s_ivd_op.u4_error_code = ERROR_FEATURE_UNAVAIL;
821
822
10
            imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
823
824
10
            return IV_FAIL;
825
10
        }
826
827
223k
        if(!is_mvc_nalu(ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded]))
828
94.4k
        {
829
94.4k
            ivd_video_decode_op_t s_avc_op;
830
831
94.4k
            i4_error_code =
832
94.4k
                ih264d_parse_nal_unit(ps_dec_hdl, &s_avc_op, pu1_bitstream_buf, i4_nalu_length);
833
94.4k
        }
834
129k
        else
835
129k
        {
836
129k
            i4_error_code = imvcd_nalu_parser(ps_mvcd_ctxt, pu1_bitstream_buf, i4_nalu_length);
837
129k
        }
838
839
223k
        if(OK != i4_error_code)
840
11.5k
        {
841
11.5k
            ps_op->s_ivd_op.u4_error_code = i4_error_code;
842
843
11.5k
            imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
844
845
11.5k
            return IV_FAIL;
846
11.5k
        }
847
212k
        else if(PPS == ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded])
848
38.2k
        {
849
38.2k
            imvcd_update_num_pps(ps_mvcd_ctxt);
850
38.2k
        }
851
174k
        else if(SPS == ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded])
852
40.3k
        {
853
40.3k
            imvcd_update_num_sps(ps_mvcd_ctxt);
854
40.3k
        }
855
133k
        else if(SUBSET_SPS == ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded])
856
4.81k
        {
857
4.81k
            imvcd_update_num_subset_sps(ps_mvcd_ctxt);
858
4.81k
        }
859
860
212k
        b_header_data_left = ps_view_ctxt->i4_decode_header &&
861
43.1k
                             (!is_header_decoded(ps_view_ctxt->i4_header_decoded, SPS) ||
862
40.6k
                              !is_header_decoded(ps_view_ctxt->i4_header_decoded, PPS)) &&
863
28.3k
                             (u4_num_bytes_consumed < ps_ip->s_ivd_ip.u4_num_Bytes);
864
212k
        b_frame_data_left = (!ps_view_ctxt->i4_decode_header &&
865
169k
                             (!ps_view_ctxt->u1_pic_decode_done || u4_next_is_aud)) &&
866
56.4k
                            (u4_num_bytes_consumed < ps_ip->s_ivd_ip.u4_num_Bytes);
867
868
212k
        u4_num_bytes_consumed += i4_nalu_length + u4_length_of_start_code;
869
212k
        u4_num_bytes_remaining -= i4_nalu_length + u4_length_of_start_code;
870
871
212k
    } while(b_header_data_left || b_frame_data_left);
872
873
127k
    if((i4_error_code == IVD_RES_CHANGED) || (i4_error_code == IVD_MEM_ALLOC_FAILED) ||
874
127k
       (i4_error_code == ERROR_UNAVAIL_PICBUF_T) || (i4_error_code == ERROR_UNAVAIL_MVBUF_T) ||
875
127k
       (i4_error_code == ERROR_INV_SPS_PPS_T))
876
0
    {
877
0
        ih264d_signal_decode_thread(ps_view_ctxt);
878
879
0
        if(ps_view_ctxt->u4_num_cores == 3)
880
0
        {
881
0
            ih264d_signal_bs_deblk_thread(ps_view_ctxt);
882
0
        }
883
884
        /* dont consume bitstream for change in resolution case */
885
0
        if(i4_error_code == IVD_RES_CHANGED)
886
0
        {
887
0
            ps_op->s_ivd_op.u4_num_bytes_consumed -= u4_num_bytes_consumed;
888
0
        }
889
890
0
        imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
891
892
0
        return IV_FAIL;
893
0
    }
894
895
127k
    if(ps_view_ctxt->u1_separate_parse)
896
76.7k
    {
897
76.7k
        if(ps_view_ctxt->u4_num_cores == 2)
898
36.8k
        {
899
36.8k
            if((ps_view_ctxt->u4_nmb_deblk == 0) && (ps_view_ctxt->u4_start_recon_deblk == 1))
900
31.2k
            {
901
31.2k
                tfr_ctxt_t s_tfr_ctxt;
902
903
31.2k
                UWORD32 u4_num_mbs, u4_max_addr;
904
905
31.2k
                tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
906
31.2k
                pad_mgr_t *ps_pad_mgr = &ps_view_ctxt->s_pad_mgr;
907
31.2k
                nalu_mvc_ext_t *ps_cur_nalu_mvc_ext = imvcd_get_cur_nalu_mvc_ext(ps_mvcd_ctxt);
908
909
                /*BS is done for all mbs while parsing*/
910
31.2k
                u4_max_addr = (ps_view_ctxt->u2_frm_wd_in_mbs * ps_view_ctxt->u2_frm_ht_in_mbs) - 1;
911
31.2k
                ps_view_ctxt->u4_cur_bs_mb_num = u4_max_addr + 1;
912
913
31.2k
                ps_view_ctxt->ps_cur_pic = &ps_view_ctxt->s_cur_pic;
914
31.2k
                imvcd_convert_au_buf_to_view_buf(ps_mvcd_ctxt->ps_cur_au, &ps_view_ctxt->s_cur_pic,
915
31.2k
                                                 ps_mvcd_ctxt->u2_num_views_decoded,
916
31.2k
                                                 ps_cur_nalu_mvc_ext->u2_view_id);
917
918
31.2k
                ih264d_init_deblk_tfr_ctxt(ps_view_ctxt, ps_pad_mgr, ps_tfr_cxt,
919
31.2k
                                           ps_view_ctxt->u2_frm_wd_in_mbs, 0);
920
921
31.2k
                u4_num_mbs = u4_max_addr - ps_view_ctxt->u4_cur_deblk_mb_num + 1;
922
923
31.2k
                if(u4_num_mbs != 0)
924
31.2k
                {
925
31.2k
                    ih264d_check_mb_map_deblk(ps_view_ctxt, u4_num_mbs, ps_tfr_cxt, 1);
926
31.2k
                }
927
928
31.2k
                ps_view_ctxt->u4_start_recon_deblk = 0;
929
31.2k
            }
930
36.8k
        }
931
932
76.7k
        ih264d_signal_decode_thread(ps_view_ctxt);
933
934
76.7k
        if(ps_view_ctxt->u4_num_cores == 3)
935
39.9k
        {
936
39.9k
            ih264d_signal_bs_deblk_thread(ps_view_ctxt);
937
39.9k
        }
938
76.7k
    }
939
940
127k
    DATA_SYNC();
941
942
    // Report if header (sps and pps) has not been decoded yet
943
127k
    if(ps_view_ctxt->i4_decode_header &&
944
15.0k
       (!is_header_decoded(ps_view_ctxt->i4_header_decoded, SPS) &&
945
102
        !is_header_decoded(ps_view_ctxt->i4_header_decoded, PPS)))
946
102
    {
947
102
        ps_op->s_ivd_op.u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
948
949
102
        imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
950
951
102
        return IV_FAIL;
952
102
    }
953
954
127k
    if(ps_view_ctxt->u4_pic_buf_got)
955
112k
    {
956
112k
        ps_view_ctxt->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY;
957
958
112k
        if(((ps_view_ctxt->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0) &&
959
112k
           ps_view_ctxt->u1_pic_decode_done)
960
112k
        {
961
112k
            nalu_mvc_ext_t *ps_cur_nalu_mvc_ext = imvcd_get_cur_nalu_mvc_ext(ps_mvcd_ctxt);
962
963
112k
            if(!ps_mvcd_ctxt->au1_nal_ref_idc[ps_mvcd_ctxt->u2_num_views_decoded] &&
964
27.3k
               ps_cur_nalu_mvc_ext->u1_inter_view_flag)
965
27.1k
            {
966
27.1k
                ps_view_ctxt->ps_cur_slice->u1_nal_ref_idc = 1;
967
27.1k
            }
968
969
            /* Padding only. Deblk has happened already. */
970
112k
            ih264d_deblock_picture_progressive(ps_view_ctxt);
971
972
112k
            if(!ps_mvcd_ctxt->au1_nal_ref_idc[ps_mvcd_ctxt->u2_num_views_decoded] &&
973
27.3k
               ps_cur_nalu_mvc_ext->u1_inter_view_flag)
974
27.1k
            {
975
27.1k
                ps_view_ctxt->ps_cur_slice->u1_nal_ref_idc = 0;
976
27.1k
            }
977
112k
        }
978
979
        /*Update the i4_frametype at the end of picture*/
980
112k
        if(imvcd_is_idr_au(ps_mvcd_ctxt))
981
32.7k
        {
982
32.7k
            ps_view_ctxt->i4_frametype = IV_IDR_FRAME;
983
32.7k
        }
984
79.8k
        else if(ps_view_ctxt->i4_pic_type == B_SLICE)
985
27.1k
        {
986
27.1k
            ps_view_ctxt->i4_frametype = IV_B_FRAME;
987
27.1k
        }
988
52.6k
        else if(ps_view_ctxt->i4_pic_type == P_SLICE)
989
46.0k
        {
990
46.0k
            ps_view_ctxt->i4_frametype = IV_P_FRAME;
991
46.0k
        }
992
6.64k
        else if(ps_view_ctxt->i4_pic_type == I_SLICE)
993
6.64k
        {
994
6.64k
            ps_view_ctxt->i4_frametype = IV_I_FRAME;
995
6.64k
        }
996
997
112k
        ps_view_ctxt->i4_content_type = ps_view_ctxt->ps_cur_slice->u1_field_pic_flag;
998
112k
    }
999
1000
    /* close deblock thread if it is not closed yet*/
1001
127k
    if(ps_view_ctxt->u4_num_cores == 3)
1002
39.9k
    {
1003
39.9k
        ih264d_signal_bs_deblk_thread(ps_view_ctxt);
1004
39.9k
    }
1005
1006
127k
    if(ps_view_ctxt->u4_dec_thread_created)
1007
0
    {
1008
0
        ih264d_signal_decode_thread(ps_view_ctxt);
1009
0
    }
1010
1011
127k
    if(ps_view_ctxt->u4_bs_deblk_thread_created)
1012
0
    {
1013
0
        ih264d_signal_bs_deblk_thread(ps_view_ctxt);
1014
0
    }
1015
1016
127k
    ps_op->s_ivd_op.u4_num_bytes_consumed = u4_num_bytes_consumed;
1017
1018
127k
    DATA_SYNC();
1019
1020
127k
    return IV_SUCCESS;
1021
127k
}
1022
1023
static IV_API_CALL_STATUS_T imvcd_finish_au_decode(mvc_dec_ctxt_t *ps_mvcd_ctxt,
1024
                                                   imvcd_video_decode_op_t *ps_op)
1025
110k
{
1026
110k
    WORD32 i4_error_code;
1027
1028
110k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1029
110k
    dec_slice_params_t *ps_cur_slice = ps_view_ctxt->ps_cur_slice;
1030
110k
    mvc_au_buffer_t *ps_cur_au = ps_mvcd_ctxt->ps_cur_au;
1031
110k
    mvc_dpb_manager_t *ps_dpb_mgr = ps_mvcd_ctxt->ps_dpb_mgr;
1032
1033
110k
    bool b_is_idr = imvcd_is_idr_au(ps_mvcd_ctxt);
1034
110k
    bool b_is_ref_au = !!ps_mvcd_ctxt->au1_nal_ref_idc[ps_mvcd_ctxt->u2_num_views - 1];
1035
110k
    WORD64 i8_display_poc =
1036
110k
        ((WORD64) ps_view_ctxt->i4_prev_max_display_seq) + ((WORD64) ps_cur_au->i4_poc);
1037
1038
110k
    imvcd_dpb_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1039
1040
110k
    if(ps_cur_slice->u1_mmco_equalto5 || b_is_idr)
1041
40.1k
    {
1042
40.1k
        ps_cur_au->i4_poc = 0;
1043
40.1k
        ps_cur_au->i4_avg_poc = 0;
1044
1045
40.1k
        if(ps_view_ctxt->u4_total_mbs_coded == (ps_view_ctxt->ps_cur_sps->u4_max_mb_addr + 1))
1046
40.1k
        {
1047
40.1k
            imvcd_reset_dpb(ps_dpb_mgr);
1048
40.1k
        }
1049
1050
40.1k
        imvcd_dpb_release_display_bufs(ps_dpb_mgr);
1051
40.1k
    }
1052
1053
110k
    if(IVD_DECODE_FRAME_OUT != ps_view_ctxt->e_frm_out_mode)
1054
110k
    {
1055
110k
        i4_error_code = imvcd_dpb_assign_display_seq(ps_dpb_mgr);
1056
1057
110k
        if(OK != i4_error_code)
1058
0
        {
1059
0
            return IV_FAIL;
1060
0
        }
1061
110k
    }
1062
1063
110k
    if(b_is_ref_au)
1064
83.5k
    {
1065
83.5k
        ih264_buf_mgr_set_status(ps_mvcd_ctxt->s_mvc_au_buf_mgr.ps_buf_mgr_ctxt,
1066
83.5k
                                 ps_cur_au->i4_pic_buf_id, BUF_MGR_REF);
1067
1068
83.5k
        ih264_buf_mgr_set_status(ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.ps_buf_mgr_ctxt,
1069
83.5k
                                 ps_cur_au->i4_mv_buf_id, BUF_MGR_REF);
1070
1071
83.5k
        ps_view_ctxt->au1_pic_buf_ref_flag[ps_cur_au->i4_pic_buf_id] = 1;
1072
83.5k
    }
1073
27.0k
    else
1074
27.0k
    {
1075
27.0k
        ih264_buf_mgr_release(ps_mvcd_ctxt->s_mvc_au_buf_mgr.ps_buf_mgr_ctxt,
1076
27.0k
                              ps_cur_au->i4_pic_buf_id, BUF_MGR_REF);
1077
1078
27.0k
        ih264_buf_mgr_release(ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.ps_buf_mgr_ctxt,
1079
27.0k
                              ps_cur_au->i4_mv_buf_id, BUF_MGR_REF | BUF_MGR_IO);
1080
1081
27.0k
        ps_view_ctxt->au1_pic_buf_ref_flag[ps_cur_au->i4_pic_buf_id] = 0;
1082
27.0k
    }
1083
1084
110k
    if((!ps_view_ctxt->u1_last_pic_not_decoded &&
1085
110k
        (0 == (ps_view_ctxt->ps_cur_pic->u4_pack_slc_typ & ps_view_ctxt->u4_skip_frm_mask))) ||
1086
0
       b_is_idr)
1087
110k
    {
1088
110k
        ih264_buf_mgr_set_status(ps_mvcd_ctxt->s_mvc_au_buf_mgr.ps_buf_mgr_ctxt,
1089
110k
                                 ps_cur_au->i4_pic_buf_id, BUF_MGR_IO);
1090
110k
    }
1091
1092
110k
    if(IS_OUT_OF_RANGE_S32(i8_display_poc))
1093
277
    {
1094
277
        ps_view_ctxt->i4_prev_max_display_seq = 0;
1095
277
    }
1096
1097
110k
    i4_error_code = imvcd_dpb_insert_pic_in_display_list(
1098
110k
        ps_dpb_mgr, i8_display_poc, ps_cur_au->i4_frame_num, ps_cur_au->i4_pic_buf_id);
1099
1100
110k
    if(i4_error_code != OK)
1101
1
    {
1102
1
        return IV_FAIL;
1103
1
    }
1104
1105
110k
    if(IVD_DECODE_FRAME_OUT == ps_view_ctxt->e_frm_out_mode)
1106
0
    {
1107
0
        i4_error_code = imvcd_dpb_assign_display_seq(ps_dpb_mgr);
1108
1109
0
        if(i4_error_code != OK)
1110
0
        {
1111
0
            return IV_FAIL;
1112
0
        }
1113
0
    }
1114
1115
110k
    ps_view_ctxt->u4_total_frames_decoded++;
1116
1117
    /* In case the decoder is configured to run in low delay mode,
1118
     * then get display buffer and then format convert.
1119
     * Note in this mode, format conversion does not run paralelly in a thread
1120
     * and adds to the codec cycles
1121
     */
1122
110k
    if((IVD_DECODE_FRAME_OUT == ps_view_ctxt->e_frm_out_mode) && ps_view_ctxt->u1_init_dec_flag)
1123
0
    {
1124
0
        i4_error_code = imvcd_get_next_display_au_buf(ps_mvcd_ctxt);
1125
1126
0
        if(i4_error_code != OK)
1127
0
        {
1128
0
            return IV_FAIL;
1129
0
        }
1130
1131
0
        ps_op->s_ivd_op.u4_output_present = 1;
1132
0
    }
1133
1134
110k
    ps_cur_au->u1_pic_type |= TOP_REF | BOT_REF;
1135
1136
110k
    if(ps_view_ctxt->u4_pic_buf_got)
1137
110k
    {
1138
110k
        if(ps_view_ctxt->u1_last_pic_not_decoded)
1139
0
        {
1140
0
            return IV_FAIL;
1141
0
        }
1142
110k
        else if(b_is_ref_au)
1143
83.5k
        {
1144
83.5k
            if(b_is_idr)
1145
26.0k
            {
1146
26.0k
                ps_dpb_mgr->u1_mmco_error_in_seq = 0;
1147
1148
26.0k
                if(!ps_view_ctxt->ps_dpb_cmds->u1_long_term_reference_flag)
1149
10.2k
                {
1150
10.2k
                    imvcd_reset_dpb(ps_dpb_mgr);
1151
1152
10.2k
                    i4_error_code = imvcd_dpb_insert_st_node(ps_dpb_mgr, ps_cur_au);
1153
1154
10.2k
                    if(i4_error_code != OK)
1155
0
                    {
1156
0
                        return IV_FAIL;
1157
0
                    }
1158
1159
10.2k
                    ps_dpb_mgr->u1_max_lt_frame_idx = NO_LONG_TERM_INDICIES;
1160
10.2k
                }
1161
15.8k
                else
1162
15.8k
                {
1163
15.8k
                    i4_error_code = imvcd_dpb_insert_st_node(ps_dpb_mgr, ps_cur_au);
1164
1165
15.8k
                    if(i4_error_code != OK)
1166
0
                    {
1167
0
                        return IV_FAIL;
1168
0
                    }
1169
1170
15.8k
                    imvcd_dpb_delete_st_node_or_make_lt(ps_dpb_mgr, ps_cur_au->i4_pic_num, 0);
1171
1172
15.8k
                    ps_dpb_mgr->u1_max_lt_frame_idx = 0;
1173
15.8k
                }
1174
26.0k
            }
1175
57.4k
            else if(!ps_dpb_mgr->u1_mmco_error_in_seq)
1176
56.5k
            {
1177
56.5k
                i4_error_code = imvcd_dpb_do_mmco(ps_view_ctxt->ps_dpb_cmds, ps_dpb_mgr, ps_cur_au,
1178
56.5k
                                                  ps_view_ctxt->ps_cur_sps->u1_num_ref_frames,
1179
56.5k
                                                  ps_view_ctxt->e_dec_status);
1180
1181
56.5k
                ps_dpb_mgr->u1_mmco_error_in_seq = i4_error_code != OK;
1182
56.5k
            }
1183
1184
83.5k
            i4_error_code = imvcd_dpb_update_default_index_list(ps_dpb_mgr);
1185
1186
83.5k
            if(i4_error_code != OK)
1187
0
            {
1188
0
                return IV_FAIL;
1189
0
            }
1190
83.5k
        }
1191
110k
    }
1192
1193
110k
    ps_op->s_ivd_op.u4_frame_decoded_flag = 1;
1194
1195
110k
    return IV_SUCCESS;
1196
110k
}
1197
1198
/* Description - 'AU Decode' API for MVC Decoder */
1199
static IV_API_CALL_STATUS_T imvcd_decode(iv_obj_t *ps_dec_hdl, imvcd_video_decode_ip_t *ps_ip,
1200
                                         imvcd_video_decode_op_t *ps_op)
1201
138k
{
1202
138k
    IV_API_CALL_STATUS_T e_retval;
1203
1204
138k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1205
138k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1206
138k
    imvcd_video_decode_ip_t s_view_ip = ps_ip[0];
1207
138k
    imvcd_video_decode_op_t s_view_op = ps_op[0];
1208
1209
138k
    UWORD16 u2_num_views_decoded = 0;
1210
138k
    UWORD16 u2_num_views = (ps_mvcd_ctxt->b_flush_enabled || ps_mvcd_ctxt->b_header_only_decode)
1211
138k
                               ? 1
1212
138k
                               : ps_mvcd_ctxt->u2_num_views;
1213
1214
138k
    ps_mvcd_ctxt->u2_num_views_decoded = 0;
1215
1216
138k
    if(IV_SUCCESS != imvcd_check_dec_handle(ps_dec_hdl))
1217
0
    {
1218
0
        return IV_FAIL;
1219
0
    }
1220
1221
138k
    if(IV_SUCCESS != imvcd_check_decode_structs(ps_dec_hdl, ps_ip, ps_op))
1222
0
    {
1223
0
        return IV_FAIL;
1224
0
    }
1225
1226
138k
    if(!ps_mvcd_ctxt->b_header_only_decode)
1227
120k
    {
1228
120k
        if(IV_SUCCESS != imvcd_au_error_checks(ps_mvcd_ctxt, ps_ip))
1229
1.16k
        {
1230
1.16k
            return IV_FAIL;
1231
1.16k
        }
1232
120k
    }
1233
1234
    /*Data memory barries instruction,so that bitstream write by the application
1235
     * is complete*/
1236
137k
    DATA_SYNC();
1237
1238
137k
    imvcd_au_init(ps_dec_hdl, ps_ip, ps_op);
1239
1240
137k
    if(ps_mvcd_ctxt->b_flush_enabled)
1241
0
    {
1242
0
        return imvcd_flush_mode_decode(ps_mvcd_ctxt, ps_op);
1243
0
    }
1244
1245
264k
    while(u2_num_views_decoded < u2_num_views)
1246
139k
    {
1247
139k
        e_retval = imvcd_view_decode(ps_dec_hdl, &s_view_ip, &s_view_op);
1248
1249
139k
        if(IV_SUCCESS != e_retval)
1250
11.7k
        {
1251
11.7k
            ps_op->s_ivd_op.u4_error_code = s_view_op.s_ivd_op.u4_error_code;
1252
1253
11.7k
            return IV_FAIL;
1254
11.7k
        }
1255
1256
127k
        s_view_ip.s_ivd_ip.pv_stream_buffer = ((UWORD8 *) s_view_ip.s_ivd_ip.pv_stream_buffer) +
1257
127k
                                              s_view_op.s_ivd_op.u4_num_bytes_consumed;
1258
127k
        s_view_ip.s_ivd_ip.u4_num_Bytes -= s_view_op.s_ivd_op.u4_num_bytes_consumed;
1259
127k
        ps_op->s_ivd_op.u4_num_bytes_consumed += s_view_op.s_ivd_op.u4_num_bytes_consumed;
1260
1261
127k
        u2_num_views_decoded++;
1262
127k
        ps_mvcd_ctxt->u2_num_views_decoded++;
1263
127k
    }
1264
1265
125k
    if(!ps_mvcd_ctxt->b_header_only_decode)
1266
110k
    {
1267
110k
        e_retval = imvcd_finish_au_decode(ps_mvcd_ctxt, ps_op);
1268
1269
110k
        if(IV_SUCCESS != e_retval)
1270
1
        {
1271
1
            return IV_FAIL;
1272
1
        }
1273
110k
    }
1274
1275
125k
    ps_op->s_ivd_op.u4_pic_wd = ps_view_ctxt->u2_disp_width;
1276
125k
    ps_op->s_ivd_op.u4_pic_ht = ps_view_ctxt->u2_disp_height;
1277
125k
    ps_op->s_ivd_op.u4_output_present = ps_view_ctxt->u4_output_present;
1278
125k
    ps_op->s_ivd_op.u4_ts = ps_view_ctxt->s_disp_op.u4_ts;
1279
125k
    ps_op->s_ivd_op.i4_reorder_depth = ps_view_ctxt->i4_reorder_depth;
1280
125k
    ps_op->s_ivd_op.e_output_format = IV_YUV_420P;
1281
1282
125k
    if(ps_op->s_ivd_op.u4_output_present)
1283
79.3k
    {
1284
79.3k
        imvcd_convert_to_app_disp_buf(ps_mvcd_ctxt, ps_op->ps_view_disp_bufs);
1285
79.3k
    }
1286
1287
125k
    return e_retval;
1288
125k
}
1289
1290
static IV_API_CALL_STATUS_T imvcd_ctl_set_dec_mode(iv_obj_t *ps_dec_hdl,
1291
                                                   imvcd_set_config_ip_t *ps_ip,
1292
                                                   imvcd_set_config_op_t *ps_op)
1293
138k
{
1294
138k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1295
138k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1296
1297
138k
    ps_view_ctxt->u4_skip_frm_mask = SKIP_NONE;
1298
1299
138k
    ps_op->s_ivd_op.u4_error_code = 0;
1300
1301
138k
    ps_view_ctxt->u4_app_disp_width = 0;
1302
1303
138k
    if(ps_ip->s_ivd_ip.e_frm_skip_mode != IVD_SKIP_NONE)
1304
0
    {
1305
0
        ps_op->s_ivd_op.u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
1306
1307
0
        return IV_FAIL;
1308
0
    }
1309
1310
138k
    if(ps_ip->s_ivd_ip.e_vid_dec_mode == IVD_DECODE_FRAME)
1311
120k
    {
1312
120k
        ps_view_ctxt->i4_decode_header = 0;
1313
120k
        ps_mvcd_ctxt->b_header_only_decode = false;
1314
120k
    }
1315
17.4k
    else if(ps_ip->s_ivd_ip.e_vid_dec_mode == IVD_DECODE_HEADER)
1316
17.4k
    {
1317
17.4k
        ps_view_ctxt->i4_decode_header = 1;
1318
17.4k
        ps_mvcd_ctxt->b_header_only_decode = true;
1319
17.4k
    }
1320
0
    else
1321
0
    {
1322
0
        ps_op->s_ivd_op.u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
1323
1324
0
        return IV_FAIL;
1325
0
    }
1326
1327
138k
    if((ps_ip->s_ivd_ip.e_frm_out_mode != IVD_DECODE_FRAME_OUT) &&
1328
138k
       (ps_ip->s_ivd_ip.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT))
1329
0
    {
1330
0
        ps_op->s_ivd_op.u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
1331
1332
0
        return IV_FAIL;
1333
0
    }
1334
1335
138k
    ps_mvcd_ctxt->b_flush_enabled = false;
1336
138k
    ps_view_ctxt->e_frm_out_mode = ps_ip->s_ivd_ip.e_frm_out_mode;
1337
1338
138k
    return IV_SUCCESS;
1339
138k
}
1340
1341
static IV_API_CALL_STATUS_T imvcd_ctl_set_num_cores(iv_obj_t *ps_dec_hdl,
1342
                                                    imvcd_set_num_cores_ip_t *ps_ip,
1343
                                                    imvcd_set_num_cores_op_t *ps_op)
1344
17.4k
{
1345
17.4k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1346
17.4k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1347
1348
17.4k
    ps_view_ctxt->u4_num_cores = ps_ip->u4_num_cores;
1349
1350
17.4k
    ps_op->u4_error_code = 0;
1351
1352
17.4k
    if(ps_view_ctxt->u4_num_cores == 1)
1353
4.46k
    {
1354
4.46k
        ps_view_ctxt->u1_separate_parse = 0;
1355
4.46k
    }
1356
12.9k
    else
1357
12.9k
    {
1358
12.9k
        ps_view_ctxt->u1_separate_parse = 1;
1359
12.9k
    }
1360
1361
    /*using only upto three threads currently*/
1362
17.4k
    if(ps_view_ctxt->u4_num_cores > 3)
1363
0
    {
1364
0
        ps_view_ctxt->u4_num_cores = 3;
1365
0
    }
1366
1367
17.4k
    return IV_SUCCESS;
1368
17.4k
}
1369
1370
static IV_API_CALL_STATUS_T imvcd_ctl_set_arch(iv_obj_t *ps_dec_hdl, imvcd_set_arch_ip_t *ps_ip,
1371
                                               imvcd_set_arch_op_t *ps_op)
1372
17.4k
{
1373
17.4k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1374
17.4k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1375
1376
17.4k
    ps_view_ctxt->e_processor_arch = ps_ip->e_arch;
1377
17.4k
    ps_view_ctxt->e_processor_soc = ps_ip->e_soc;
1378
1379
17.4k
    ps_op->u4_error_code = 0;
1380
1381
17.4k
    return IV_SUCCESS;
1382
17.4k
}
1383
1384
static IV_API_CALL_STATUS_T imvcd_ctl_set_degrade_mode(iv_obj_t *ps_dec_hdl,
1385
                                                       imvcd_set_degrade_mode_ip_t *ps_ip,
1386
                                                       imvcd_set_degrade_mode_op_t *ps_op)
1387
0
{
1388
0
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1389
0
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1390
1391
0
    ps_view_ctxt->i4_degrade_type = ps_ip->i4_degrade_type;
1392
0
    ps_view_ctxt->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
1393
0
    ps_view_ctxt->i4_degrade_pics = ps_ip->i4_degrade_pics;
1394
0
    ps_view_ctxt->i4_degrade_pic_cnt = 0;
1395
1396
0
    ps_op->u4_error_code = 0;
1397
1398
0
    return IV_SUCCESS;
1399
0
}
1400
1401
static IV_API_CALL_STATUS_T imvcd_ctl_flush_dec(iv_obj_t *ps_dec_hdl, imvcd_flush_dec_ip_t *ps_ip,
1402
                                                imvcd_flush_dec_op_t *ps_op)
1403
0
{
1404
0
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1405
0
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1406
1407
0
    UNUSED(ps_ip);
1408
1409
0
    ps_op->s_ivd_op.u4_error_code = 0;
1410
1411
0
    ps_mvcd_ctxt->b_flush_enabled = true;
1412
0
    ps_view_ctxt->u1_flushfrm = 1;
1413
1414
0
    if(ps_view_ctxt->u1_init_dec_flag)
1415
0
    {
1416
0
        imvcd_release_all_ref_bufs(ps_mvcd_ctxt, ps_view_ctxt->u1_pic_bufs);
1417
0
        imvcd_dpb_release_display_bufs(ps_mvcd_ctxt->ps_dpb_mgr);
1418
0
    }
1419
1420
    /* Ignore dangling fields during flush */
1421
0
    ps_view_ctxt->u1_top_bottom_decoded = 0;
1422
1423
0
    return IV_SUCCESS;
1424
0
}
1425
1426
static IV_API_CALL_STATUS_T imvcd_ctl_get_buf_info(iv_obj_t *ps_dec_hdl,
1427
                                                   imvcd_get_buf_info_ip_t *ps_ip,
1428
                                                   imvcd_get_buf_info_op_t *ps_op)
1429
14.9k
{
1430
14.9k
    UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
1431
14.9k
    UWORD32 u4_pic_wd, u4_pic_ht;
1432
14.9k
    UWORD32 i;
1433
1434
14.9k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1435
14.9k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1436
1437
14.9k
    UNUSED(ps_ip);
1438
1439
14.9k
    ps_op->s_ivd_op.u4_error_code = 0;
1440
1441
14.9k
    ps_op->s_ivd_op.u4_num_disp_bufs = 0;
1442
14.9k
    ps_op->s_ivd_op.u4_min_num_in_bufs = MIN_IN_BUFS;
1443
1444
14.9k
    u4_pic_wd = 0;
1445
14.9k
    u4_pic_ht = 0;
1446
1447
14.9k
    if(is_header_decoded(ps_view_ctxt->i4_header_decoded, SPS))
1448
14.9k
    {
1449
14.9k
        u4_pic_wd = ps_view_ctxt->u2_disp_width;
1450
14.9k
        u4_pic_ht = ps_view_ctxt->u2_disp_height;
1451
14.9k
    }
1452
1453
14.9k
    ps_op->s_mvc_buf_info.u2_num_views = ps_mvcd_ctxt->u2_num_views;
1454
1455
29.8k
    for(i = 0; i < ps_op->s_ivd_op.u4_min_num_in_bufs; i++)
1456
14.9k
    {
1457
14.9k
        ps_op->s_ivd_op.u4_min_in_buf_size[i] =
1458
14.9k
            MAX(256000, u4_pic_wd * u4_pic_ht * ps_mvcd_ctxt->u2_num_views * 3 / 2);
1459
14.9k
    }
1460
1461
14.9k
    ps_op->s_ivd_op.u4_min_num_out_bufs = ih264d_get_outbuf_size(
1462
14.9k
        u4_pic_wd, u4_pic_ht, ps_view_ctxt->u1_chroma_format, &au4_min_out_buf_size[0]);
1463
14.9k
    ps_op->s_ivd_op.u4_min_num_out_bufs *= ps_mvcd_ctxt->u2_num_views;
1464
1465
60.6k
    for(i = 0; i < ps_op->s_ivd_op.u4_min_num_out_bufs; i++)
1466
45.6k
    {
1467
45.6k
        ps_op->s_ivd_op.u4_min_out_buf_size[i] = au4_min_out_buf_size[i % NUM_COMPONENTS];
1468
45.6k
    }
1469
1470
14.9k
    return IV_SUCCESS;
1471
14.9k
}
1472
1473
static IV_API_CALL_STATUS_T imvcd_ctl_get_vui(iv_obj_t *ps_dec_hdl, imvcd_get_vui_ip_t *ps_ip,
1474
                                              imvcd_get_vui_op_t *ps_op)
1475
0
{
1476
0
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1477
0
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1478
1479
0
    UNUSED(ps_ip);
1480
1481
0
    ps_op->u4_error_code = 0;
1482
0
    ps_op->b_is_vui_available = false;
1483
1484
0
    if((ps_mvcd_ctxt->u1_num_sps > 0) && ps_view_ctxt->ps_cur_sps)
1485
0
    {
1486
0
        ps_op->b_is_vui_available = ps_view_ctxt->ps_cur_sps->u1_vui_parameters_present_flag;
1487
1488
0
        if(ps_op->b_is_vui_available)
1489
0
        {
1490
0
            ps_op->u1_aspect_ratio_idc = ps_view_ctxt->ps_cur_sps->s_vui.u1_aspect_ratio_idc;
1491
0
            ps_op->u2_sar_width = ps_view_ctxt->ps_cur_sps->s_vui.u2_sar_width;
1492
0
            ps_op->u2_sar_height = ps_view_ctxt->ps_cur_sps->s_vui.u2_sar_height;
1493
0
            ps_op->u1_overscan_appropriate_flag =
1494
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_overscan_appropriate_flag;
1495
0
            ps_op->u1_video_format = ps_view_ctxt->ps_cur_sps->s_vui.u1_video_format;
1496
0
            ps_op->u1_video_full_range_flag =
1497
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_video_full_range_flag;
1498
0
            ps_op->u1_colour_primaries = ps_view_ctxt->ps_cur_sps->s_vui.u1_colour_primaries;
1499
0
            ps_op->u1_tfr_chars = ps_view_ctxt->ps_cur_sps->s_vui.u1_tfr_chars;
1500
0
            ps_op->u1_matrix_coeffs = ps_view_ctxt->ps_cur_sps->s_vui.u1_matrix_coeffs;
1501
0
            ps_op->u1_cr_top_field = ps_view_ctxt->ps_cur_sps->s_vui.u1_cr_top_field;
1502
0
            ps_op->u1_cr_bottom_field = ps_view_ctxt->ps_cur_sps->s_vui.u1_cr_bottom_field;
1503
0
            ps_op->u4_num_units_in_tick = ps_view_ctxt->ps_cur_sps->s_vui.u4_num_units_in_tick;
1504
0
            ps_op->u4_time_scale = ps_view_ctxt->ps_cur_sps->s_vui.u4_time_scale;
1505
0
            ps_op->u1_fixed_frame_rate_flag =
1506
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_fixed_frame_rate_flag;
1507
0
            ps_op->u1_nal_hrd_params_present =
1508
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_nal_hrd_params_present;
1509
0
            ps_op->u1_vcl_hrd_params_present =
1510
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_vcl_hrd_params_present;
1511
0
            ps_op->u1_low_delay_hrd_flag = ps_view_ctxt->ps_cur_sps->s_vui.u1_low_delay_hrd_flag;
1512
0
            ps_op->u1_pic_struct_present_flag =
1513
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_pic_struct_present_flag;
1514
0
            ps_op->u1_bitstream_restriction_flag =
1515
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_bitstream_restriction_flag;
1516
0
            ps_op->u1_mv_over_pic_boundaries_flag =
1517
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_mv_over_pic_boundaries_flag;
1518
0
            ps_op->u4_max_bytes_per_pic_denom =
1519
0
                ps_view_ctxt->ps_cur_sps->s_vui.u4_max_bytes_per_pic_denom;
1520
0
            ps_op->u4_max_bits_per_mb_denom =
1521
0
                ps_view_ctxt->ps_cur_sps->s_vui.u4_max_bits_per_mb_denom;
1522
0
            ps_op->u4_log2_max_mv_length_horz =
1523
0
                ps_view_ctxt->ps_cur_sps->s_vui.u4_log2_max_mv_length_horz;
1524
0
            ps_op->u4_log2_max_mv_length_vert =
1525
0
                ps_view_ctxt->ps_cur_sps->s_vui.u4_log2_max_mv_length_vert;
1526
0
            ps_op->u4_num_reorder_frames = ps_view_ctxt->ps_cur_sps->s_vui.u4_num_reorder_frames;
1527
0
            ps_op->u4_max_dec_frame_buffering =
1528
0
                ps_view_ctxt->ps_cur_sps->s_vui.u4_max_dec_frame_buffering;
1529
0
        }
1530
0
    }
1531
1532
0
    return IV_SUCCESS;
1533
0
}
1534
1535
/* Description - 'Control Cmd' API for MVC Decoder */
1536
static IV_API_CALL_STATUS_T imvcd_ctl_cmd_handler(iv_obj_t *ps_dec_hdl, void *pv_ip, void *pv_op)
1537
188k
{
1538
188k
    ivd_ctl_set_config_ip_t *ps_ip = (ivd_ctl_set_config_ip_t *) pv_ip;
1539
1540
188k
    WORD32 i4_sub_cmd = ps_ip->e_sub_cmd;
1541
1542
188k
    if(IV_SUCCESS != imvcd_check_dec_handle(ps_dec_hdl))
1543
0
    {
1544
0
        return IV_FAIL;
1545
0
    }
1546
1547
188k
    if(IV_SUCCESS != imvcd_check_ctl_structs(pv_ip, pv_op))
1548
0
    {
1549
0
        return IV_FAIL;
1550
0
    }
1551
1552
188k
    switch(i4_sub_cmd)
1553
188k
    {
1554
138k
        case IVD_CMD_CTL_SETPARAMS:
1555
138k
        {
1556
138k
            return imvcd_ctl_set_dec_mode(ps_dec_hdl, pv_ip, pv_op);
1557
0
        }
1558
17.4k
        case IMVCD_CTL_SET_NUM_CORES:
1559
17.4k
        {
1560
17.4k
            return imvcd_ctl_set_num_cores(ps_dec_hdl, pv_ip, pv_op);
1561
0
        }
1562
17.4k
        case IMVCD_CTL_SET_PROCESSOR:
1563
17.4k
        {
1564
17.4k
            return imvcd_ctl_set_arch(ps_dec_hdl, pv_ip, pv_op);
1565
0
        }
1566
0
        case IMVCD_CTL_DEGRADE:
1567
0
        {
1568
0
            return imvcd_ctl_set_degrade_mode(ps_dec_hdl, pv_ip, pv_op);
1569
0
        }
1570
0
        case IVD_CMD_CTL_FLUSH:
1571
0
        {
1572
0
            return imvcd_ctl_flush_dec(ps_dec_hdl, pv_ip, pv_op);
1573
0
        }
1574
14.9k
        case IVD_CMD_CTL_GETBUFINFO:
1575
14.9k
        {
1576
14.9k
            return imvcd_ctl_get_buf_info(ps_dec_hdl, pv_ip, pv_op);
1577
0
        }
1578
0
        case IMVCD_CTL_GET_VUI_PARAMS:
1579
0
        {
1580
0
            return imvcd_ctl_get_vui(ps_dec_hdl, pv_ip, pv_op);
1581
0
        }
1582
0
        default:
1583
0
        {
1584
0
            return IV_FAIL;
1585
0
        }
1586
188k
    }
1587
188k
}
1588
1589
IV_API_CALL_STATUS_T imvcd_api_function(iv_obj_t *ps_dec_hdl, void *pv_ip, void *pv_op)
1590
361k
{
1591
361k
    IVD_API_COMMAND_TYPE_T e_cmd = ((WORD32 *) pv_ip)[1];
1592
1593
361k
    switch(e_cmd)
1594
361k
    {
1595
17.4k
        case IVD_CMD_CREATE:
1596
17.4k
        {
1597
17.4k
            return imvcd_create(pv_ip, pv_op);
1598
0
        }
1599
17.4k
        case IVD_CMD_DELETE:
1600
17.4k
        {
1601
17.4k
            return imvcd_delete(ps_dec_hdl);
1602
0
        }
1603
188k
        case IVD_CMD_VIDEO_CTL:
1604
188k
        {
1605
188k
            return imvcd_ctl_cmd_handler(ps_dec_hdl, pv_ip, pv_op);
1606
0
        }
1607
138k
        case IVD_CMD_VIDEO_DECODE:
1608
138k
        {
1609
138k
            return imvcd_decode(ps_dec_hdl, pv_ip, pv_op);
1610
0
        }
1611
0
        default:
1612
0
        {
1613
0
            return IV_FAIL;
1614
0
        }
1615
361k
    }
1616
361k
}