Coverage Report

Created: 2026-01-10 06:44

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/libavc/decoder/mvc/imvcd_api.c
Line
Count
Source
1
/******************************************************************************
2
 *
3
 * Copyright (C) 2021 The Android Open Source Project
4
 *
5
 * Licensed under the Apache License, Version 2.0 (the "License");
6
 * you may not use this file except in compliance with the License.
7
 * You may obtain a copy of the License at:
8
 *
9
 * http://www.apache.org/licenses/LICENSE-2.0
10
 *
11
 * Unless required by applicable law or agreed to in writing, software
12
 * distributed under the License is distributed on an "AS IS" BASIS,
13
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14
 * See the License for the specific language governing permissions and
15
 * limitations under the License.
16
 *
17
 *****************************************************************************
18
 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19
 */
20
21
/*****************************************************************************/
22
/*                                                                           */
23
/*  File Name         : imvcd_api.c                                          */
24
/*                                                                           */
25
/*  Description       : Has all MVC API functions                            */
26
/*                                                                           */
27
/*                                                                           */
28
/*  List of Functions :                                                      */
29
/*                                                                           */
30
/*****************************************************************************/
31
#include <string.h>
32
33
#include "ih264_typedefs.h"
34
#include "iv.h"
35
#include "ivd.h"
36
#include "imvcd.h"
37
#include "ih264_debug.h"
38
#include "ih264_disp_mgr.h"
39
#include "ih264_error.h"
40
#include "ih264_buf_mgr.h"
41
#include "ih264_platform_macros.h"
42
#include "ih264d_inter_pred.h"
43
#include "ih264d_structs.h"
44
#include "ih264d_deblocking.h"
45
#include "ih264d_error_handler.h"
46
#include "ih264d_function_selector.h"
47
#include "ih264d_nal.h"
48
#include "ih264d_parse_cavlc.h"
49
#include "ih264d_parse_headers.h"
50
#include "ih264d_tables.h"
51
#include "ih264d_thread_compute_bs.h"
52
#include "ih264d_utils.h"
53
#include "ih264d_api_utils.h"
54
#include "ithread.h"
55
#include "imvcd_api_utils.h"
56
#include "imvcd_dpb_manager.h"
57
#include "imvcd_error_handler.h"
58
#include "imvcd_nalu_parser.h"
59
#include "imvcd_structs.h"
60
#include "imvcd_utils.h"
61
62
static void imvcd_free_static_bufs(iv_obj_t *ps_dec_hdl)
63
3.73k
{
64
3.73k
    mvc_dec_ctxt_t *ps_mvcd_ctxt;
65
3.73k
    dec_struct_t *ps_view_ctxt;
66
67
3.73k
    FT_ALIGNED_FREE *pf_aligned_free;
68
69
3.73k
    void *pv_mem_ctxt;
70
71
3.73k
    if(!ps_dec_hdl)
72
0
    {
73
0
        return;
74
0
    }
75
76
3.73k
    ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
77
78
3.73k
    if(!ps_mvcd_ctxt)
79
0
    {
80
0
        return;
81
0
    }
82
83
3.73k
    ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
84
3.73k
    pf_aligned_free = ps_view_ctxt->pf_aligned_free;
85
3.73k
    pv_mem_ctxt = ps_view_ctxt->pv_mem_ctxt;
86
87
3.73k
    imvcd_free_dynamic_bufs(ps_mvcd_ctxt);
88
89
3.73k
    imvcd_bitsteam_buf_free(ps_view_ctxt);
90
91
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_left_mvpred_addr);
92
93
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu4_wts_ofsts_mat);
94
95
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu4_mbaff_wt_mat);
96
97
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu1_init_dpb_base);
98
99
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu1_temp_mc_buffer);
100
101
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pi2_pred1);
102
103
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu1_ref_buff_base);
104
105
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_left_mb_ctxt_info);
106
107
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->p_cabac_ctxt_table_t);
108
109
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ppv_map_ref_idx_to_poc_base);
110
111
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pu1_bits_buf_static);
112
113
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pv_scratch_sps_pps);
114
115
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_bitstrm);
116
117
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_dpb_cmds);
118
119
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_sei_parse);
120
121
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_sei);
122
123
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_dec_err_status);
124
125
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_pred);
126
127
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pv_bs_deblk_thread_handle);
128
129
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->pv_dec_thread_handle);
130
131
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_pps);
132
133
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_view_ctxt->ps_sps);
134
135
3.73k
    ih264_buf_mgr_free(ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.pv_mem);
136
137
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.pv_mem);
138
139
3.73k
    ih264_buf_mgr_free(ps_mvcd_ctxt->s_mvc_au_buf_mgr.pv_mem);
140
141
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_mvcd_ctxt->s_mvc_au_buf_mgr.pv_mem);
142
143
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_mvcd_ctxt->ps_dpb_mgr);
144
145
3.73k
    PS_DEC_ALIGNED_FREE(ps_view_ctxt, ps_mvcd_ctxt);
146
147
3.73k
    if(ps_dec_hdl)
148
3.73k
    {
149
3.73k
        pf_aligned_free(pv_mem_ctxt, ps_dec_hdl);
150
3.73k
    }
151
3.73k
}
152
153
static IV_API_CALL_STATUS_T imvcd_view_ctxt_init(imvcd_create_ip_t *ps_ip,
154
                                                 dec_struct_t *ps_view_ctxt)
155
3.73k
{
156
3.73k
    pocstruct_t *ps_prev_poc, *ps_cur_poc;
157
158
3.73k
    WORD32 i4_mem_size;
159
3.73k
    void *pv_buf;
160
161
3.73k
    FT_ALIGNED_ALLOC *pf_aligned_alloc = ps_ip->s_ivd_ip.pf_aligned_alloc;
162
163
3.73k
    void *pv_mem_ctxt = ps_ip->s_ivd_ip.pv_mem_ctxt;
164
3.73k
    const WORD32 i4_default_alignment = 128;
165
166
3.73k
    ps_view_ctxt->u4_share_disp_buf = 0;
167
3.73k
    ps_view_ctxt->u1_chroma_format = ps_ip->s_ivd_ip.e_output_format;
168
169
3.73k
    ps_view_ctxt->pf_aligned_alloc = pf_aligned_alloc;
170
3.73k
    ps_view_ctxt->pf_aligned_free = ps_ip->s_ivd_ip.pf_aligned_free;
171
3.73k
    ps_view_ctxt->pv_mem_ctxt = ps_ip->s_ivd_ip.pv_mem_ctxt;
172
173
3.73k
    i4_mem_size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS);
174
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
175
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
176
3.73k
    memset(pv_buf, 0, i4_mem_size);
177
3.73k
    ps_view_ctxt->ps_sps = pv_buf;
178
179
3.73k
    i4_mem_size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS;
180
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
181
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
182
3.73k
    memset(pv_buf, 0, i4_mem_size);
183
3.73k
    ps_view_ctxt->ps_pps = pv_buf;
184
185
3.73k
    i4_mem_size = ithread_get_handle_size();
186
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
187
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
188
3.73k
    memset(pv_buf, 0, i4_mem_size);
189
3.73k
    ps_view_ctxt->pv_dec_thread_handle = pv_buf;
190
191
3.73k
    i4_mem_size = ithread_get_handle_size();
192
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
193
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
194
3.73k
    memset(pv_buf, 0, i4_mem_size);
195
3.73k
    ps_view_ctxt->pv_bs_deblk_thread_handle = pv_buf;
196
197
3.73k
    i4_mem_size = sizeof(pred_info_t) * 2 * 32;
198
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
199
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
200
3.73k
    memset(pv_buf, 0, i4_mem_size);
201
3.73k
    ps_view_ctxt->ps_pred = pv_buf;
202
203
3.73k
    ps_view_ctxt->pv_disp_buf_mgr = NULL;
204
205
3.73k
    ps_view_ctxt->pv_pic_buf_mgr = NULL;
206
207
3.73k
    ps_view_ctxt->ps_pic_buf_base = NULL;
208
209
3.73k
    i4_mem_size = sizeof(dec_err_status_t);
210
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
211
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
212
3.73k
    memset(pv_buf, 0, i4_mem_size);
213
3.73k
    ps_view_ctxt->ps_dec_err_status = (dec_err_status_t *) pv_buf;
214
215
3.73k
    i4_mem_size = sizeof(sei);
216
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
217
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
218
3.73k
    memset(pv_buf, 0, i4_mem_size);
219
3.73k
    ps_view_ctxt->ps_sei = (sei *) pv_buf;
220
221
3.73k
    i4_mem_size = sizeof(sei);
222
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
223
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
224
3.73k
    memset(pv_buf, 0, i4_mem_size);
225
3.73k
    ps_view_ctxt->ps_sei_parse = (sei *) pv_buf;
226
227
3.73k
    i4_mem_size = sizeof(dpb_commands_t);
228
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
229
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
230
3.73k
    memset(pv_buf, 0, i4_mem_size);
231
3.73k
    ps_view_ctxt->ps_dpb_cmds = (dpb_commands_t *) pv_buf;
232
233
3.73k
    i4_mem_size = sizeof(dec_bit_stream_t);
234
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
235
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
236
3.73k
    memset(pv_buf, 0, i4_mem_size);
237
3.73k
    ps_view_ctxt->ps_bitstrm = (dec_bit_stream_t *) pv_buf;
238
239
3.73k
    i4_mem_size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
240
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
241
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
242
3.73k
    memset(pv_buf, 0, i4_mem_size);
243
3.73k
    ps_view_ctxt->pv_scratch_sps_pps = pv_buf;
244
245
3.73k
    ps_view_ctxt->u4_static_bits_buf_size = MIN_BITSTREAMS_BUF_SIZE;
246
3.73k
    pv_buf =
247
3.73k
        pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, ps_view_ctxt->u4_static_bits_buf_size);
248
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
249
3.73k
    memset(pv_buf, 0, ps_view_ctxt->u4_static_bits_buf_size);
250
3.73k
    ps_view_ctxt->pu1_bits_buf_static = pv_buf;
251
252
3.73k
    i4_mem_size = (TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC) * sizeof(void *);
253
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
254
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
255
3.73k
    ps_view_ctxt->ppv_map_ref_idx_to_poc_base = pv_buf;
256
3.73k
    ps_view_ctxt->ppv_map_ref_idx_to_poc =
257
3.73k
        ps_view_ctxt->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC;
258
3.73k
    memset(ps_view_ctxt->ppv_map_ref_idx_to_poc_base, 0, i4_mem_size);
259
260
3.73k
    i4_mem_size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
261
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
262
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
263
3.73k
    memset(pv_buf, 0, i4_mem_size);
264
3.73k
    ps_view_ctxt->p_cabac_ctxt_table_t = pv_buf;
265
266
3.73k
    i4_mem_size = sizeof(ctxt_inc_mb_info_t);
267
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
268
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
269
3.73k
    memset(pv_buf, 0, i4_mem_size);
270
3.73k
    ps_view_ctxt->ps_left_mb_ctxt_info = pv_buf;
271
272
3.73k
    i4_mem_size = MAX_REF_BUF_SIZE * 2;
273
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
274
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
275
3.73k
    memset(pv_buf, 0, i4_mem_size);
276
3.73k
    ps_view_ctxt->pu1_ref_buff_base = pv_buf;
277
3.73k
    ps_view_ctxt->pu1_ref_buff = ps_view_ctxt->pu1_ref_buff_base + MAX_REF_BUF_SIZE;
278
279
3.73k
    i4_mem_size = sizeof(WORD16) * PRED_BUFFER_WIDTH * PRED_BUFFER_HEIGHT * 2;
280
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
281
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
282
3.73k
    memset(pv_buf, 0, i4_mem_size);
283
3.73k
    ps_view_ctxt->pi2_pred1 = pv_buf;
284
285
3.73k
    i4_mem_size = sizeof(UWORD8) * (MB_LUM_SIZE);
286
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
287
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
288
3.73k
    memset(pv_buf, 0, i4_mem_size);
289
3.73k
    ps_view_ctxt->pu1_temp_mc_buffer = pv_buf;
290
291
3.73k
    i4_mem_size = (sizeof(UWORD32) * 2 * 3 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)) * 2);
292
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
293
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
294
3.73k
    memset(pv_buf, 0, i4_mem_size);
295
3.73k
    ps_view_ctxt->pu4_mbaff_wt_mat = pv_buf;
296
297
3.73k
    i4_mem_size = sizeof(UWORD32) * 2 * 3 * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1));
298
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
299
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
300
3.73k
    memset(pv_buf, 0, i4_mem_size);
301
3.73k
    ps_view_ctxt->pu4_wts_ofsts_mat = pv_buf;
302
303
3.73k
    i4_mem_size = (sizeof(neighbouradd_t) << 2);
304
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
305
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
306
3.73k
    memset(pv_buf, 0, i4_mem_size);
307
3.73k
    ps_view_ctxt->ps_left_mvpred_addr = pv_buf;
308
309
3.73k
    ps_view_ctxt->pv_mv_buf_mgr = NULL;
310
311
3.73k
    ps_view_ctxt->ps_col_mv_base = NULL;
312
313
3.73k
    ps_view_ctxt->init_done = 0;
314
3.73k
    ps_view_ctxt->u4_num_cores = 1;
315
3.73k
    ps_view_ctxt->u2_pic_ht = ps_view_ctxt->u2_pic_wd = 0;
316
3.73k
    ps_view_ctxt->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
317
3.73k
    ps_view_ctxt->u4_app_disable_deblk_frm = 0;
318
3.73k
    ps_view_ctxt->i4_degrade_type = 0;
319
3.73k
    ps_view_ctxt->i4_degrade_pics = 0;
320
321
3.73k
    memset(ps_view_ctxt->ps_pps, 0, ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
322
3.73k
    memset(ps_view_ctxt->ps_sps, 0, ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
323
324
3.73k
    ps_view_ctxt->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
325
3.73k
    ps_view_ctxt->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
326
3.73k
    ps_view_ctxt->s_cab_dec_env.pv_codec_handle = ps_view_ctxt;
327
3.73k
    ps_view_ctxt->u4_num_fld_in_frm = 0;
328
3.73k
    ps_view_ctxt->ps_sei->u1_is_valid = 0;
329
3.73k
    ps_view_ctxt->ps_cur_pps = NULL;
330
3.73k
    ps_view_ctxt->ps_cur_sps = NULL;
331
3.73k
    ps_view_ctxt->ps_cur_slice = NULL;
332
3.73k
    ps_view_ctxt->u1_init_dec_flag = 0;
333
3.73k
    ps_view_ctxt->u1_first_slice_in_stream = 1;
334
3.73k
    ps_view_ctxt->u1_last_pic_not_decoded = 0;
335
3.73k
    ps_view_ctxt->u4_app_disp_width = 0;
336
3.73k
    ps_view_ctxt->i4_header_decoded = 0;
337
3.73k
    ps_view_ctxt->u4_total_frames_decoded = 0;
338
3.73k
    ps_view_ctxt->i4_error_code = 0;
339
3.73k
    ps_view_ctxt->i4_content_type = IV_CONTENTTYPE_NA;
340
3.73k
    ps_view_ctxt->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS;
341
3.73k
    ps_view_ctxt->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
342
3.73k
    ps_view_ctxt->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
343
3.73k
    ps_view_ctxt->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
344
3.73k
    ps_view_ctxt->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
345
3.73k
    ps_view_ctxt->u1_pr_sl_type = 0xFF;
346
3.73k
    ps_view_ctxt->u2_mbx = 0xffff;
347
3.73k
    ps_view_ctxt->u2_mby = 0;
348
3.73k
    ps_view_ctxt->u4_total_mbs_coded = 0;
349
350
3.73k
    ps_prev_poc = &ps_view_ctxt->s_prev_pic_poc;
351
3.73k
    ps_cur_poc = &ps_view_ctxt->s_cur_pic_poc;
352
3.73k
    ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
353
3.73k
    ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
354
3.73k
    ps_prev_poc->i4_delta_pic_order_cnt_bottom = ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
355
3.73k
    ps_prev_poc->i4_delta_pic_order_cnt[0] = ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
356
3.73k
    ps_prev_poc->i4_delta_pic_order_cnt[1] = ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
357
3.73k
    ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
358
3.73k
    ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count = 0;
359
3.73k
    ps_prev_poc->i4_bottom_field_order_count = ps_cur_poc->i4_bottom_field_order_count = 0;
360
3.73k
    ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
361
3.73k
    ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
362
3.73k
    ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
363
364
3.73k
    ps_view_ctxt->i4_max_poc = 0;
365
3.73k
    ps_view_ctxt->i4_prev_max_display_seq = 0;
366
3.73k
    ps_view_ctxt->u4_recon_mb_grp = 4;
367
3.73k
    ps_view_ctxt->i4_reorder_depth = -1;
368
3.73k
    ps_view_ctxt->u1_second_field = 0;
369
3.73k
    ps_view_ctxt->s_prev_seq_params.u1_eoseq_pending = 0;
370
3.73k
    ps_view_ctxt->u2_crop_offset_y = 0;
371
3.73k
    ps_view_ctxt->u2_crop_offset_uv = 0;
372
3.73k
    ps_view_ctxt->i4_vui_frame_rate = -1;
373
3.73k
    ps_view_ctxt->i4_pic_type = NA_SLICE;
374
3.73k
    ps_view_ctxt->i4_frametype = IV_NA_FRAME;
375
3.73k
    ps_view_ctxt->i4_content_type = IV_CONTENTTYPE_NA;
376
3.73k
    ps_view_ctxt->u1_res_changed = 0;
377
3.73k
    ps_view_ctxt->u1_frame_decoded_flag = 0;
378
3.73k
    ps_view_ctxt->u4_skip_frm_mask = SKIP_NONE;
379
380
3.73k
    ps_view_ctxt->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
381
3.73k
    ps_view_ctxt->pf_cavlc_4x4res_block[1] = ih264d_cavlc_4x4res_block_totalcoeff_2to10;
382
3.73k
    ps_view_ctxt->pf_cavlc_4x4res_block[2] = ih264d_cavlc_4x4res_block_totalcoeff_11to16;
383
3.73k
    ps_view_ctxt->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
384
3.73k
    ps_view_ctxt->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
385
3.73k
    ps_view_ctxt->pf_cavlc_parse_8x8block[0] = ih264d_cavlc_parse_8x8block_none_available;
386
3.73k
    ps_view_ctxt->pf_cavlc_parse_8x8block[1] = ih264d_cavlc_parse_8x8block_left_available;
387
3.73k
    ps_view_ctxt->pf_cavlc_parse_8x8block[2] = ih264d_cavlc_parse_8x8block_top_available;
388
3.73k
    ps_view_ctxt->pf_cavlc_parse_8x8block[3] = ih264d_cavlc_parse_8x8block_both_available;
389
390
3.73k
    ps_view_ctxt->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
391
3.73k
    ps_view_ctxt->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
392
3.73k
    ps_view_ctxt->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
393
3.73k
    ps_view_ctxt->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
394
3.73k
    ps_view_ctxt->pf_fill_bs_xtra_left_edge[0] = ih264d_fill_bs_xtra_left_edge_cur_frm;
395
3.73k
    ps_view_ctxt->pf_fill_bs_xtra_left_edge[1] = ih264d_fill_bs_xtra_left_edge_cur_fld;
396
397
3.73k
    ps_view_ctxt->u2_prv_frame_num = 0;
398
3.73k
    ps_view_ctxt->u1_top_bottom_decoded = 0;
399
3.73k
    ps_view_ctxt->u1_dangling_field = 0;
400
3.73k
    ps_view_ctxt->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
401
3.73k
    ps_view_ctxt->pu1_left_mv_ctxt_inc = ps_view_ctxt->u1_left_mv_ctxt_inc_arr[0];
402
3.73k
    ps_view_ctxt->pi1_left_ref_idx_ctxt_inc = &ps_view_ctxt->i1_left_ref_idx_ctx_inc_arr[0][0];
403
3.73k
    ps_view_ctxt->pu1_left_yuv_dc_csbp = &ps_view_ctxt->u1_yuv_dc_csbp_topmb;
404
3.73k
    ps_view_ctxt->u1_flushfrm = 0;
405
3.73k
    ps_view_ctxt->s_cab_dec_env.pv_codec_handle = ps_view_ctxt;
406
3.73k
    ps_view_ctxt->ps_bitstrm->pv_codec_handle = ps_view_ctxt;
407
408
3.73k
    memset(ps_view_ctxt->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
409
3.73k
    memset(ps_view_ctxt->u4_disp_buf_mapping, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
410
3.73k
    memset(ps_view_ctxt->u4_disp_buf_to_be_freed, 0, (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
411
412
3.73k
    ih264d_init_arch(ps_view_ctxt);
413
3.73k
    ih264d_init_function_ptr(ps_view_ctxt);
414
3.73k
    ps_view_ctxt->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
415
3.73k
    ps_view_ctxt->init_done = 1;
416
417
3.73k
    return IV_SUCCESS;
418
3.73k
}
419
420
static IV_API_CALL_STATUS_T imvcd_ctxt_init(imvcd_create_ip_t *ps_ip, mvc_dec_ctxt_t *ps_mvcd_ctxt)
421
3.73k
{
422
3.73k
    WORD32 i4_mem_size;
423
3.73k
    void *pv_buf;
424
425
3.73k
    FT_ALIGNED_ALLOC *pf_aligned_alloc = ps_ip->s_ivd_ip.pf_aligned_alloc;
426
427
3.73k
    void *pv_mem_ctxt = ps_ip->s_ivd_ip.pv_mem_ctxt;
428
3.73k
    const WORD32 i4_default_alignment = 128;
429
430
3.73k
    memset(ps_mvcd_ctxt, 0, sizeof(ps_mvcd_ctxt[0]));
431
432
3.73k
    i4_mem_size = sizeof(mvc_dpb_manager_t);
433
3.73k
    ps_mvcd_ctxt->ps_dpb_mgr = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
434
3.73k
    RETURN_IF((NULL == ps_mvcd_ctxt->ps_dpb_mgr), IV_FAIL);
435
3.73k
    memset(ps_mvcd_ctxt->ps_dpb_mgr, 0, i4_mem_size);
436
437
3.73k
    imvcd_init_dpb_mgr(ps_mvcd_ctxt->ps_dpb_mgr, &ps_mvcd_ctxt->s_mvc_au_buf_mgr,
438
3.73k
                       &ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr, &ps_mvcd_ctxt->s_mvc_disp_buf_mgr);
439
440
3.73k
    ih264_disp_mgr_init(&ps_mvcd_ctxt->s_mvc_disp_buf_mgr);
441
442
3.73k
    i4_mem_size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
443
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
444
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
445
3.73k
    memset(pv_buf, 0, i4_mem_size);
446
3.73k
    ps_mvcd_ctxt->s_mvc_au_buf_mgr.pv_mem = pv_buf;
447
3.73k
    ps_mvcd_ctxt->s_mvc_au_buf_mgr.ps_buf_mgr_ctxt = pv_buf;
448
449
3.73k
    ih264_buf_mgr_init(ps_mvcd_ctxt->s_mvc_au_buf_mgr.pv_mem);
450
451
3.73k
    i4_mem_size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
452
3.73k
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
453
3.73k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
454
3.73k
    memset(pv_buf, 0, i4_mem_size);
455
3.73k
    ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.pv_mem = pv_buf;
456
3.73k
    ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.ps_buf_mgr_ctxt = pv_buf;
457
458
3.73k
    ih264_buf_mgr_init(ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.pv_mem);
459
460
3.73k
    if(IV_SUCCESS != imvcd_view_ctxt_init(ps_ip, &ps_mvcd_ctxt->s_view_dec_ctxt))
461
0
    {
462
0
        return IV_FAIL;
463
0
    }
464
465
3.73k
    ps_mvcd_ctxt->u2_num_views = 0;
466
3.73k
    ps_mvcd_ctxt->u2_num_views_decoded = 0;
467
468
3.73k
    return IV_SUCCESS;
469
3.73k
}
470
471
static IV_API_CALL_STATUS_T imvcd_allocate_static_bufs(imvcd_create_ip_t *ps_ip,
472
                                                       imvcd_create_op_t *ps_op)
473
3.73k
{
474
3.73k
    iv_obj_t *ps_dec_hdl;
475
3.73k
    mvc_dec_ctxt_t *ps_mvcd_ctxt;
476
477
3.73k
    WORD32 i4_mem_size;
478
479
3.73k
    FT_ALIGNED_ALLOC *pf_aligned_alloc = ps_ip->s_ivd_ip.pf_aligned_alloc;
480
481
3.73k
    void *pv_mem_ctxt = ps_ip->s_ivd_ip.pv_mem_ctxt;
482
3.73k
    const WORD32 i4_default_alignment = 128;
483
484
3.73k
    i4_mem_size = sizeof(ps_dec_hdl[0]);
485
3.73k
    ps_op->s_ivd_op.pv_handle = ps_dec_hdl =
486
3.73k
        (iv_obj_t *) pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
487
488
3.73k
    if(NULL == ps_dec_hdl)
489
0
    {
490
0
        return IV_FAIL;
491
0
    }
492
493
3.73k
    i4_mem_size = sizeof(ps_mvcd_ctxt[0]);
494
3.73k
    ps_dec_hdl->pv_codec_handle = ps_mvcd_ctxt =
495
3.73k
        (mvc_dec_ctxt_t *) pf_aligned_alloc(pv_mem_ctxt, i4_default_alignment, i4_mem_size);
496
497
3.73k
    if(NULL == ps_mvcd_ctxt)
498
0
    {
499
0
        return IV_FAIL;
500
0
    }
501
502
3.73k
    if(IV_SUCCESS != imvcd_ctxt_init(ps_ip, ps_mvcd_ctxt))
503
0
    {
504
0
        return IV_FAIL;
505
0
    }
506
507
3.73k
    return IV_SUCCESS;
508
3.73k
}
509
510
/* Description - 'Create' API for MVC Decoder */
511
static IV_API_CALL_STATUS_T imvcd_create(imvcd_create_ip_t *ps_ip, imvcd_create_op_t *ps_op)
512
3.73k
{
513
3.73k
    if(IV_SUCCESS != imvcd_check_create_structs(ps_ip, ps_op))
514
0
    {
515
0
        return IV_FAIL;
516
0
    }
517
518
3.73k
    if(IV_SUCCESS != imvcd_allocate_static_bufs(ps_ip, ps_op))
519
0
    {
520
0
        imvcd_free_static_bufs((iv_obj_t *) ps_op->s_ivd_op.pv_handle);
521
522
0
        return IV_FAIL;
523
0
    }
524
525
3.73k
    return IV_SUCCESS;
526
3.73k
}
527
528
/* Description - 'Delete' API for MVC Decoder */
529
static IV_API_CALL_STATUS_T imvcd_delete(iv_obj_t *ps_dec_hdl)
530
3.73k
{
531
3.73k
    if(IV_SUCCESS != imvcd_check_dec_handle(ps_dec_hdl))
532
0
    {
533
0
        return IV_FAIL;
534
0
    }
535
536
3.73k
    imvcd_free_static_bufs(ps_dec_hdl);
537
538
3.73k
    return IV_SUCCESS;
539
3.73k
}
540
541
static IV_API_CALL_STATUS_T imvcd_flush_mode_decode(mvc_dec_ctxt_t *ps_mvcd_ctxt,
542
                                                    imvcd_video_decode_op_t *ps_op)
543
0
{
544
0
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
545
546
0
    if(!ps_view_ctxt->u1_init_dec_flag)
547
0
    {
548
0
        ps_view_ctxt->u1_flushfrm = 0;
549
0
        ps_mvcd_ctxt->b_flush_enabled = false;
550
0
        ps_op->s_ivd_op.u4_output_present = 0;
551
552
0
        return IV_FAIL;
553
0
    }
554
555
0
    if(IV_SUCCESS != imvcd_get_next_display_au_buf(ps_mvcd_ctxt))
556
0
    {
557
0
        ps_view_ctxt->u1_flushfrm = 0;
558
0
        ps_mvcd_ctxt->b_flush_enabled = false;
559
0
        ps_op->s_ivd_op.u4_output_present = false;
560
561
0
        return IV_SUCCESS;
562
0
    }
563
564
0
    ih264d_export_sei_params(&ps_op->s_ivd_op.s_sei_decode_op, ps_view_ctxt);
565
566
0
    ps_op->s_ivd_op.u4_pic_wd = ps_view_ctxt->u2_disp_width;
567
0
    ps_op->s_ivd_op.u4_pic_ht = ps_view_ctxt->u2_disp_height;
568
0
    ps_op->s_ivd_op.u4_ts = ps_view_ctxt->s_disp_op.u4_ts;
569
0
    ps_op->s_ivd_op.u4_output_present = 1;
570
0
    ps_op->s_ivd_op.e_output_format = IV_YUV_420P;
571
572
0
    imvcd_convert_to_app_disp_buf(ps_mvcd_ctxt, ps_op->ps_view_disp_bufs);
573
574
0
    return IV_SUCCESS;
575
0
}
576
577
static void imvcd_fill_output_struct_from_context(mvc_dec_ctxt_t *ps_mvcd_ctxt,
578
                                                  imvcd_video_decode_op_t *ps_op)
579
2.32k
{
580
2.32k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
581
582
2.32k
    if((ps_op->s_ivd_op.u4_error_code & 0xff) != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
583
2.32k
    {
584
2.32k
        ps_op->s_ivd_op.u4_pic_wd = ps_view_ctxt->u2_disp_width;
585
2.32k
        ps_op->s_ivd_op.u4_pic_ht = ps_view_ctxt->u2_disp_height;
586
2.32k
    }
587
588
2.32k
    ps_op->s_ivd_op.u4_output_present = ps_view_ctxt->u4_output_present;
589
590
2.32k
    ps_op->s_ivd_op.e_output_format = IV_YUV_420P;
591
592
2.32k
    imvcd_convert_to_app_disp_buf(ps_mvcd_ctxt, ps_op->ps_view_disp_bufs);
593
594
2.32k
    ih264d_export_sei_params(&ps_op->s_ivd_op.s_sei_decode_op, ps_view_ctxt);
595
2.32k
}
596
597
static void imvcd_video_decode_clean_return(mvc_dec_ctxt_t *ps_mvcd_ctxt,
598
                                            imvcd_video_decode_ip_t *ps_ip,
599
                                            imvcd_video_decode_op_t *ps_op)
600
2.32k
{
601
2.32k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
602
603
2.32k
    ih264d_signal_decode_thread(ps_view_ctxt);
604
2.32k
    ih264d_signal_bs_deblk_thread(ps_view_ctxt);
605
606
2.32k
    imvcd_fill_output_struct_from_context(ps_mvcd_ctxt, ps_op);
607
608
2.32k
    ps_op->s_ivd_op.u4_frame_decoded_flag = 0;
609
2.32k
    ps_op->s_ivd_op.u4_num_bytes_consumed = ps_ip->s_ivd_ip.u4_num_Bytes;
610
2.32k
}
611
612
static FORCEINLINE void imvcd_update_num_pps(mvc_dec_ctxt_t *ps_mvcd_ctxt)
613
13.9k
{
614
13.9k
    WORD32 i;
615
616
13.9k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
617
618
13.9k
    ps_mvcd_ctxt->u1_num_pps = 0;
619
620
3.59M
    for(i = 0; i < MAX_NUM_PIC_PARAMS; i++)
621
3.58M
    {
622
3.58M
        if(ps_view_ctxt->ps_pps[i].u1_is_valid)
623
15.8k
        {
624
15.8k
            UWORD8 u1_sps_id = ps_view_ctxt->ps_pps[i].ps_sps->u1_seq_parameter_set_id;
625
626
15.8k
            if(ps_mvcd_ctxt->as_subset_sps[u1_sps_id].s_sps_data.u1_is_valid)
627
442
            {
628
442
                ps_mvcd_ctxt->aps_pps_id_to_subset_sps_map[i] =
629
442
                    &ps_mvcd_ctxt->as_subset_sps[u1_sps_id];
630
442
            }
631
632
15.8k
            ps_mvcd_ctxt->u1_num_pps++;
633
15.8k
        }
634
3.58M
    }
635
13.9k
}
636
637
static FORCEINLINE void imvcd_update_num_sps(mvc_dec_ctxt_t *ps_mvcd_ctxt)
638
16.6k
{
639
16.6k
    WORD32 i;
640
641
16.6k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
642
643
16.6k
    ps_mvcd_ctxt->u1_num_sps = 0;
644
645
547k
    for(i = 0; i < MAX_NUM_SEQ_PARAMS; i++)
646
531k
    {
647
531k
        if(ps_view_ctxt->ps_sps[i].u1_is_valid)
648
18.1k
        {
649
18.1k
            ps_mvcd_ctxt->u1_num_sps++;
650
18.1k
        }
651
531k
    }
652
16.6k
}
653
654
static FORCEINLINE void imvcd_update_num_subset_sps(mvc_dec_ctxt_t *ps_mvcd_ctxt)
655
4.83k
{
656
4.83k
    WORD32 i;
657
658
4.83k
    ps_mvcd_ctxt->u1_num_subset_sps = 0;
659
660
159k
    for(i = 0; i < MAX_NUM_SEQ_PARAMS; i++)
661
154k
    {
662
154k
        if(ps_mvcd_ctxt->as_subset_sps[i].s_sps_data.u1_is_valid)
663
5.42k
        {
664
5.42k
            ps_mvcd_ctxt->u1_num_subset_sps++;
665
5.42k
        }
666
154k
    }
667
4.83k
}
668
669
static IV_API_CALL_STATUS_T imvcd_view_decode(iv_obj_t *ps_dec_hdl, imvcd_video_decode_ip_t *ps_ip,
670
                                              imvcd_video_decode_op_t *ps_op)
671
96.0k
{
672
96.0k
    UWORD8 *pu1_input_buffer;
673
96.0k
    UWORD8 *pu1_bitstream_buf;
674
96.0k
    UWORD32 u4_bitstream_buf_size;
675
96.0k
    WORD32 i4_nalu_length;
676
96.0k
    UWORD32 u4_length_of_start_code;
677
96.0k
    WORD32 i4_error_code;
678
679
96.0k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
680
96.0k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
681
682
96.0k
    UWORD32 u4_num_bytes_consumed = 0;
683
96.0k
    UWORD32 u4_num_bytes_remaining = ps_ip->s_ivd_ip.u4_num_Bytes;
684
96.0k
    bool b_first_start_code_found = false;
685
96.0k
    bool b_frame_data_left = true;
686
96.0k
    bool b_header_data_left = true;
687
96.0k
    UWORD32 u4_next_is_aud = 0;
688
689
96.0k
    ASSERT(u4_num_bytes_remaining > 0);
690
691
96.0k
    imvcd_view_init(ps_mvcd_ctxt);
692
693
96.0k
    do
694
141k
    {
695
141k
        pu1_input_buffer = ((UWORD8 *) ps_ip->s_ivd_ip.pv_stream_buffer) + u4_num_bytes_consumed;
696
697
141k
        if(!ps_view_ctxt->pu1_bits_buf_dynamic &&
698
21.8k
           is_header_decoded(ps_view_ctxt->i4_header_decoded, PPS))
699
3.64k
        {
700
3.64k
            if(IV_SUCCESS !=
701
3.64k
               imvcd_bitstream_buf_alloc(
702
3.64k
                   ps_view_ctxt, is_header_decoded(ps_view_ctxt->i4_header_decoded, SUBSET_SPS)
703
3.64k
                                     ? ps_mvcd_ctxt->u2_num_views
704
3.64k
                                     : 1))
705
0
            {
706
0
                return IV_FAIL;
707
0
            }
708
3.64k
        }
709
710
141k
        if(ps_view_ctxt->pu1_bits_buf_dynamic)
711
123k
        {
712
123k
            pu1_bitstream_buf = ps_view_ctxt->pu1_bits_buf_dynamic;
713
123k
            u4_bitstream_buf_size = ps_view_ctxt->u4_dynamic_bits_buf_size;
714
123k
        }
715
18.1k
        else
716
18.1k
        {
717
18.1k
            pu1_bitstream_buf = ps_view_ctxt->pu1_bits_buf_static;
718
18.1k
            u4_bitstream_buf_size = ps_view_ctxt->u4_static_bits_buf_size;
719
18.1k
        }
720
721
141k
        i4_nalu_length = ih264d_find_start_code(pu1_input_buffer, 0, u4_num_bytes_remaining,
722
141k
                                                &u4_length_of_start_code, &u4_next_is_aud);
723
724
141k
        if(i4_nalu_length == -1)
725
0
        {
726
0
            i4_nalu_length = 0;
727
0
        }
728
729
141k
        if((0 != u4_next_is_aud) && (1 != u4_next_is_aud))
730
0
        {
731
0
            return IV_FAIL;
732
0
        }
733
734
141k
        if(i4_nalu_length)
735
141k
        {
736
            /* In some erroneous fuzzer bistreams, the slice data requires more
737
              parsing than what was implied by the distance between successive
738
              start codes.The primary culprit is the NEXTBITS macro which requires
739
              reading 4 additional bytes of the bitstream buffer.To alleviate
740
              this, 16 bytes per 4x4 TU have been additionally allocated to the
741
              bitstream buffer. Also, chroma bytes are added for 4:2:0/4:2:2 */
742
743
141k
            UWORD32 u4_nalu_buf_size = ((UWORD32) i4_nalu_length) + 8 + EXTRA_BS_OFFSET;
744
745
141k
            if(u4_nalu_buf_size > u4_bitstream_buf_size)
746
36
            {
747
                /* 64 extra bytes to account for OOB accesses during SEI parsing in */
748
                /* some fuzzer bitstreams */
749
36
                if(IV_SUCCESS != imvcd_bitstream_buf_realloc(ps_view_ctxt, u4_nalu_buf_size + 64))
750
0
                {
751
0
                    return IV_FAIL;
752
0
                }
753
754
36
                pu1_bitstream_buf = ps_view_ctxt->pu1_bits_buf_dynamic;
755
36
                u4_bitstream_buf_size = ps_view_ctxt->u4_dynamic_bits_buf_size;
756
36
            }
757
758
141k
            memcpy(pu1_bitstream_buf, pu1_input_buffer + u4_length_of_start_code, i4_nalu_length);
759
760
            /* Decoder may read extra 8 bytes near end of the frame */
761
141k
            if(u4_nalu_buf_size < u4_bitstream_buf_size)
762
141k
            {
763
141k
                memset(pu1_bitstream_buf + i4_nalu_length, 0, 8 * sizeof(pu1_bitstream_buf[0]));
764
141k
            }
765
766
141k
            b_first_start_code_found = true;
767
141k
        }
768
46
        else
769
46
        {
770
46
            if(!b_first_start_code_found)
771
2
            {
772
2
                ps_view_ctxt->i4_error_code = ERROR_START_CODE_NOT_FOUND;
773
2
                ps_op->s_ivd_op.u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
774
775
2
                if(ps_view_ctxt->u4_pic_buf_got == 0)
776
2
                {
777
2
                    imvcd_fill_output_struct_from_context(ps_mvcd_ctxt, ps_op);
778
779
2
                    ps_op->s_ivd_op.u4_error_code = ps_view_ctxt->i4_error_code;
780
781
2
                    imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
782
783
2
                    return IV_FAIL;
784
2
                }
785
0
                else
786
0
                {
787
0
                    ps_view_ctxt->u1_pic_decode_done = 1;
788
789
0
                    continue;
790
0
                }
791
2
            }
792
44
            else
793
44
            {
794
                /* a start code has already been found earlier in the same process
795
                 * call*/
796
44
                b_frame_data_left = false;
797
44
                b_header_data_left = false;
798
799
44
                if(!ps_view_ctxt->i4_decode_header && !ps_view_ctxt->u4_pic_buf_got)
800
0
                {
801
0
                    ps_op->s_ivd_op.u4_error_code = ih264d_map_error(ERROR_UNKNOWN_NAL);
802
803
0
                    imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
804
805
0
                    return IV_FAIL;
806
0
                }
807
808
44
                continue;
809
44
            }
810
46
        }
811
812
141k
        ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded] =
813
141k
            NAL_UNIT_TYPE(pu1_bitstream_buf[0]);
814
141k
        ps_mvcd_ctxt->au1_nal_ref_idc[ps_mvcd_ctxt->u2_num_views_decoded] =
815
141k
            NAL_REF_IDC(pu1_bitstream_buf[0]);
816
817
141k
        if(ps_view_ctxt->u4_dec_thread_created &&
818
73
           !is_slice_nalu_type(ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded]))
819
2
        {
820
2
            ps_op->s_ivd_op.u4_error_code = ERROR_FEATURE_UNAVAIL;
821
822
2
            imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
823
824
2
            return IV_FAIL;
825
2
        }
826
827
141k
        if(!is_mvc_nalu(ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded]))
828
42.0k
        {
829
42.0k
            ivd_video_decode_op_t s_avc_op;
830
831
42.0k
            i4_error_code =
832
42.0k
                ih264d_parse_nal_unit(ps_dec_hdl, &s_avc_op, pu1_bitstream_buf, i4_nalu_length);
833
42.0k
        }
834
99.5k
        else
835
99.5k
        {
836
99.5k
            i4_error_code = imvcd_nalu_parser(ps_mvcd_ctxt, pu1_bitstream_buf, i4_nalu_length);
837
99.5k
        }
838
839
141k
        if(OK != i4_error_code)
840
2.31k
        {
841
2.31k
            ps_op->s_ivd_op.u4_error_code = i4_error_code;
842
843
2.31k
            imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
844
845
2.31k
            return IV_FAIL;
846
2.31k
        }
847
139k
        else if(PPS == ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded])
848
13.9k
        {
849
13.9k
            imvcd_update_num_pps(ps_mvcd_ctxt);
850
13.9k
        }
851
125k
        else if(SPS == ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded])
852
16.6k
        {
853
16.6k
            imvcd_update_num_sps(ps_mvcd_ctxt);
854
16.6k
        }
855
108k
        else if(SUBSET_SPS == ps_mvcd_ctxt->ae_nalu_id[ps_mvcd_ctxt->u2_num_views_decoded])
856
4.83k
        {
857
4.83k
            imvcd_update_num_subset_sps(ps_mvcd_ctxt);
858
4.83k
        }
859
860
139k
        b_header_data_left = ps_view_ctxt->i4_decode_header &&
861
18.1k
                             (!is_header_decoded(ps_view_ctxt->i4_header_decoded, SPS) ||
862
15.6k
                              !is_header_decoded(ps_view_ctxt->i4_header_decoded, PPS)) &&
863
14.4k
                             (u4_num_bytes_consumed < ps_ip->s_ivd_ip.u4_num_Bytes);
864
139k
        b_frame_data_left = (!ps_view_ctxt->i4_decode_header &&
865
121k
                             (!ps_view_ctxt->u1_pic_decode_done || u4_next_is_aud)) &&
866
31.1k
                            (u4_num_bytes_consumed < ps_ip->s_ivd_ip.u4_num_Bytes);
867
868
139k
        u4_num_bytes_consumed += i4_nalu_length + u4_length_of_start_code;
869
139k
        u4_num_bytes_remaining -= i4_nalu_length + u4_length_of_start_code;
870
871
139k
    } while(b_header_data_left || b_frame_data_left);
872
873
93.7k
    if((i4_error_code == IVD_RES_CHANGED) || (i4_error_code == IVD_MEM_ALLOC_FAILED) ||
874
93.7k
       (i4_error_code == ERROR_UNAVAIL_PICBUF_T) || (i4_error_code == ERROR_UNAVAIL_MVBUF_T) ||
875
93.7k
       (i4_error_code == ERROR_INV_SPS_PPS_T))
876
0
    {
877
0
        ih264d_signal_decode_thread(ps_view_ctxt);
878
879
0
        if(ps_view_ctxt->u4_num_cores == 3)
880
0
        {
881
0
            ih264d_signal_bs_deblk_thread(ps_view_ctxt);
882
0
        }
883
884
        /* dont consume bitstream for change in resolution case */
885
0
        if(i4_error_code == IVD_RES_CHANGED)
886
0
        {
887
0
            ps_op->s_ivd_op.u4_num_bytes_consumed -= u4_num_bytes_consumed;
888
0
        }
889
890
0
        imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
891
892
0
        return IV_FAIL;
893
0
    }
894
895
93.7k
    if(ps_view_ctxt->u1_separate_parse)
896
52.8k
    {
897
52.8k
        if(ps_view_ctxt->u4_num_cores == 2)
898
24.6k
        {
899
24.6k
            if((ps_view_ctxt->u4_nmb_deblk == 0) && (ps_view_ctxt->u4_start_recon_deblk == 1))
900
23.2k
            {
901
23.2k
                tfr_ctxt_t s_tfr_ctxt;
902
903
23.2k
                UWORD32 u4_num_mbs, u4_max_addr;
904
905
23.2k
                tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
906
23.2k
                pad_mgr_t *ps_pad_mgr = &ps_view_ctxt->s_pad_mgr;
907
23.2k
                nalu_mvc_ext_t *ps_cur_nalu_mvc_ext = imvcd_get_cur_nalu_mvc_ext(ps_mvcd_ctxt);
908
909
                /*BS is done for all mbs while parsing*/
910
23.2k
                u4_max_addr = (ps_view_ctxt->u2_frm_wd_in_mbs * ps_view_ctxt->u2_frm_ht_in_mbs) - 1;
911
23.2k
                ps_view_ctxt->u4_cur_bs_mb_num = u4_max_addr + 1;
912
913
23.2k
                ps_view_ctxt->ps_cur_pic = &ps_view_ctxt->s_cur_pic;
914
23.2k
                imvcd_convert_au_buf_to_view_buf(ps_mvcd_ctxt->ps_cur_au, &ps_view_ctxt->s_cur_pic,
915
23.2k
                                                 ps_mvcd_ctxt->u2_num_views_decoded,
916
23.2k
                                                 ps_cur_nalu_mvc_ext->u2_view_id);
917
918
23.2k
                ih264d_init_deblk_tfr_ctxt(ps_view_ctxt, ps_pad_mgr, ps_tfr_cxt,
919
23.2k
                                           ps_view_ctxt->u2_frm_wd_in_mbs, 0);
920
921
23.2k
                u4_num_mbs = u4_max_addr - ps_view_ctxt->u4_cur_deblk_mb_num + 1;
922
923
23.2k
                if(u4_num_mbs != 0)
924
23.2k
                {
925
23.2k
                    ih264d_check_mb_map_deblk(ps_view_ctxt, u4_num_mbs, ps_tfr_cxt, 1);
926
23.2k
                }
927
928
23.2k
                ps_view_ctxt->u4_start_recon_deblk = 0;
929
23.2k
            }
930
24.6k
        }
931
932
52.8k
        ih264d_signal_decode_thread(ps_view_ctxt);
933
934
52.8k
        if(ps_view_ctxt->u4_num_cores == 3)
935
28.2k
        {
936
28.2k
            ih264d_signal_bs_deblk_thread(ps_view_ctxt);
937
28.2k
        }
938
52.8k
    }
939
940
93.7k
    DATA_SYNC();
941
942
    // Report if header (sps and pps) has not been decoded yet
943
93.7k
    if(ps_view_ctxt->i4_decode_header &&
944
3.69k
       (!is_header_decoded(ps_view_ctxt->i4_header_decoded, SPS) &&
945
11
        !is_header_decoded(ps_view_ctxt->i4_header_decoded, PPS)))
946
11
    {
947
11
        ps_op->s_ivd_op.u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
948
949
11
        imvcd_video_decode_clean_return(ps_mvcd_ctxt, ps_ip, ps_op);
950
951
11
        return IV_FAIL;
952
11
    }
953
954
93.7k
    if(ps_view_ctxt->u4_pic_buf_got)
955
90.0k
    {
956
90.0k
        ps_view_ctxt->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY;
957
958
90.0k
        if(((ps_view_ctxt->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0) &&
959
90.0k
           ps_view_ctxt->u1_pic_decode_done)
960
90.0k
        {
961
90.0k
            nalu_mvc_ext_t *ps_cur_nalu_mvc_ext = imvcd_get_cur_nalu_mvc_ext(ps_mvcd_ctxt);
962
963
90.0k
            if(!ps_mvcd_ctxt->au1_nal_ref_idc[ps_mvcd_ctxt->u2_num_views_decoded] &&
964
23.4k
               ps_cur_nalu_mvc_ext->u1_inter_view_flag)
965
23.2k
            {
966
23.2k
                ps_view_ctxt->ps_cur_slice->u1_nal_ref_idc = 1;
967
23.2k
            }
968
969
            /* Padding only. Deblk has happened already. */
970
90.0k
            ih264d_deblock_picture_progressive(ps_view_ctxt);
971
972
90.0k
            if(!ps_mvcd_ctxt->au1_nal_ref_idc[ps_mvcd_ctxt->u2_num_views_decoded] &&
973
23.4k
               ps_cur_nalu_mvc_ext->u1_inter_view_flag)
974
23.2k
            {
975
23.2k
                ps_view_ctxt->ps_cur_slice->u1_nal_ref_idc = 0;
976
23.2k
            }
977
90.0k
        }
978
979
        /*Update the i4_frametype at the end of picture*/
980
90.0k
        if(imvcd_is_idr_au(ps_mvcd_ctxt))
981
25.1k
        {
982
25.1k
            ps_view_ctxt->i4_frametype = IV_IDR_FRAME;
983
25.1k
        }
984
64.9k
        else if(ps_view_ctxt->i4_pic_type == B_SLICE)
985
20.2k
        {
986
20.2k
            ps_view_ctxt->i4_frametype = IV_B_FRAME;
987
20.2k
        }
988
44.6k
        else if(ps_view_ctxt->i4_pic_type == P_SLICE)
989
39.0k
        {
990
39.0k
            ps_view_ctxt->i4_frametype = IV_P_FRAME;
991
39.0k
        }
992
5.62k
        else if(ps_view_ctxt->i4_pic_type == I_SLICE)
993
5.62k
        {
994
5.62k
            ps_view_ctxt->i4_frametype = IV_I_FRAME;
995
5.62k
        }
996
997
90.0k
        ps_view_ctxt->i4_content_type = ps_view_ctxt->ps_cur_slice->u1_field_pic_flag;
998
90.0k
    }
999
1000
    /* close deblock thread if it is not closed yet*/
1001
93.7k
    if(ps_view_ctxt->u4_num_cores == 3)
1002
28.1k
    {
1003
28.1k
        ih264d_signal_bs_deblk_thread(ps_view_ctxt);
1004
28.1k
    }
1005
1006
93.7k
    if(ps_view_ctxt->u4_dec_thread_created)
1007
0
    {
1008
0
        ih264d_signal_decode_thread(ps_view_ctxt);
1009
0
    }
1010
1011
93.7k
    if(ps_view_ctxt->u4_bs_deblk_thread_created)
1012
0
    {
1013
0
        ih264d_signal_bs_deblk_thread(ps_view_ctxt);
1014
0
    }
1015
1016
93.7k
    ps_op->s_ivd_op.u4_num_bytes_consumed = u4_num_bytes_consumed;
1017
1018
93.7k
    DATA_SYNC();
1019
1020
93.7k
    return IV_SUCCESS;
1021
93.7k
}
1022
1023
static IV_API_CALL_STATUS_T imvcd_finish_au_decode(mvc_dec_ctxt_t *ps_mvcd_ctxt,
1024
                                                   imvcd_video_decode_op_t *ps_op)
1025
88.2k
{
1026
88.2k
    WORD32 i4_error_code;
1027
1028
88.2k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1029
88.2k
    dec_slice_params_t *ps_cur_slice = ps_view_ctxt->ps_cur_slice;
1030
88.2k
    mvc_au_buffer_t *ps_cur_au = ps_mvcd_ctxt->ps_cur_au;
1031
88.2k
    mvc_dpb_manager_t *ps_dpb_mgr = ps_mvcd_ctxt->ps_dpb_mgr;
1032
1033
88.2k
    bool b_is_idr = imvcd_is_idr_au(ps_mvcd_ctxt);
1034
88.2k
    bool b_is_ref_au = !!ps_mvcd_ctxt->au1_nal_ref_idc[ps_mvcd_ctxt->u2_num_views - 1];
1035
88.2k
    WORD64 i8_display_poc =
1036
88.2k
        ((WORD64) ps_view_ctxt->i4_prev_max_display_seq) + ((WORD64) ps_cur_au->i4_poc);
1037
1038
88.2k
    imvcd_dpb_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1039
1040
88.2k
    if(ps_cur_slice->u1_mmco_equalto5 || b_is_idr)
1041
31.0k
    {
1042
31.0k
        ps_cur_au->i4_poc = 0;
1043
31.0k
        ps_cur_au->i4_avg_poc = 0;
1044
1045
31.0k
        if(ps_view_ctxt->u4_total_mbs_coded == (ps_view_ctxt->ps_cur_sps->u4_max_mb_addr + 1))
1046
31.0k
        {
1047
31.0k
            imvcd_reset_dpb(ps_dpb_mgr);
1048
31.0k
        }
1049
1050
31.0k
        imvcd_dpb_release_display_bufs(ps_dpb_mgr);
1051
31.0k
    }
1052
1053
88.2k
    if(IVD_DECODE_FRAME_OUT != ps_view_ctxt->e_frm_out_mode)
1054
88.2k
    {
1055
88.2k
        i4_error_code = imvcd_dpb_assign_display_seq(ps_dpb_mgr);
1056
1057
88.2k
        if(OK != i4_error_code)
1058
0
        {
1059
0
            return IV_FAIL;
1060
0
        }
1061
88.2k
    }
1062
1063
88.2k
    if(b_is_ref_au)
1064
65.1k
    {
1065
65.1k
        ih264_buf_mgr_set_status(ps_mvcd_ctxt->s_mvc_au_buf_mgr.ps_buf_mgr_ctxt,
1066
65.1k
                                 ps_cur_au->i4_pic_buf_id, BUF_MGR_REF);
1067
1068
65.1k
        ih264_buf_mgr_set_status(ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.ps_buf_mgr_ctxt,
1069
65.1k
                                 ps_cur_au->i4_mv_buf_id, BUF_MGR_REF);
1070
1071
65.1k
        ps_view_ctxt->au1_pic_buf_ref_flag[ps_cur_au->i4_pic_buf_id] = 1;
1072
65.1k
    }
1073
23.1k
    else
1074
23.1k
    {
1075
23.1k
        ih264_buf_mgr_release(ps_mvcd_ctxt->s_mvc_au_buf_mgr.ps_buf_mgr_ctxt,
1076
23.1k
                              ps_cur_au->i4_pic_buf_id, BUF_MGR_REF);
1077
1078
23.1k
        ih264_buf_mgr_release(ps_mvcd_ctxt->s_mvc_au_mv_pred_buf_mgr.ps_buf_mgr_ctxt,
1079
23.1k
                              ps_cur_au->i4_mv_buf_id, BUF_MGR_REF | BUF_MGR_IO);
1080
1081
23.1k
        ps_view_ctxt->au1_pic_buf_ref_flag[ps_cur_au->i4_pic_buf_id] = 0;
1082
23.1k
    }
1083
1084
88.2k
    if((!ps_view_ctxt->u1_last_pic_not_decoded &&
1085
88.2k
        (0 == (ps_view_ctxt->ps_cur_pic->u4_pack_slc_typ & ps_view_ctxt->u4_skip_frm_mask))) ||
1086
0
       b_is_idr)
1087
88.2k
    {
1088
88.2k
        ih264_buf_mgr_set_status(ps_mvcd_ctxt->s_mvc_au_buf_mgr.ps_buf_mgr_ctxt,
1089
88.2k
                                 ps_cur_au->i4_pic_buf_id, BUF_MGR_IO);
1090
88.2k
    }
1091
1092
88.2k
    if(IS_OUT_OF_RANGE_S32(i8_display_poc))
1093
280
    {
1094
280
        ps_view_ctxt->i4_prev_max_display_seq = 0;
1095
280
    }
1096
1097
88.2k
    i4_error_code = imvcd_dpb_insert_pic_in_display_list(
1098
88.2k
        ps_dpb_mgr, i8_display_poc, ps_cur_au->i4_frame_num, ps_cur_au->i4_pic_buf_id);
1099
1100
88.2k
    if(i4_error_code != OK)
1101
0
    {
1102
0
        return IV_FAIL;
1103
0
    }
1104
1105
88.2k
    if(IVD_DECODE_FRAME_OUT == ps_view_ctxt->e_frm_out_mode)
1106
0
    {
1107
0
        i4_error_code = imvcd_dpb_assign_display_seq(ps_dpb_mgr);
1108
1109
0
        if(i4_error_code != OK)
1110
0
        {
1111
0
            return IV_FAIL;
1112
0
        }
1113
0
    }
1114
1115
88.2k
    ps_view_ctxt->u4_total_frames_decoded++;
1116
1117
    /* In case the decoder is configured to run in low delay mode,
1118
     * then get display buffer and then format convert.
1119
     * Note in this mode, format conversion does not run paralelly in a thread
1120
     * and adds to the codec cycles
1121
     */
1122
88.2k
    if((IVD_DECODE_FRAME_OUT == ps_view_ctxt->e_frm_out_mode) && ps_view_ctxt->u1_init_dec_flag)
1123
0
    {
1124
0
        i4_error_code = imvcd_get_next_display_au_buf(ps_mvcd_ctxt);
1125
1126
0
        if(i4_error_code != OK)
1127
0
        {
1128
0
            return IV_FAIL;
1129
0
        }
1130
1131
0
        ps_op->s_ivd_op.u4_output_present = 1;
1132
0
    }
1133
1134
88.2k
    ps_cur_au->u1_pic_type |= TOP_REF | BOT_REF;
1135
1136
88.2k
    if(ps_view_ctxt->u4_pic_buf_got)
1137
88.2k
    {
1138
88.2k
        if(ps_view_ctxt->u1_last_pic_not_decoded)
1139
0
        {
1140
0
            return IV_FAIL;
1141
0
        }
1142
88.2k
        else if(b_is_ref_au)
1143
65.1k
        {
1144
65.1k
            if(b_is_idr)
1145
18.5k
            {
1146
18.5k
                ps_dpb_mgr->u1_mmco_error_in_seq = 0;
1147
1148
18.5k
                if(!ps_view_ctxt->ps_dpb_cmds->u1_long_term_reference_flag)
1149
9.40k
                {
1150
9.40k
                    imvcd_reset_dpb(ps_dpb_mgr);
1151
1152
9.40k
                    i4_error_code = imvcd_dpb_insert_st_node(ps_dpb_mgr, ps_cur_au);
1153
1154
9.40k
                    if(i4_error_code != OK)
1155
0
                    {
1156
0
                        return IV_FAIL;
1157
0
                    }
1158
1159
9.40k
                    ps_dpb_mgr->u1_max_lt_frame_idx = NO_LONG_TERM_INDICIES;
1160
9.40k
                }
1161
9.16k
                else
1162
9.16k
                {
1163
9.16k
                    i4_error_code = imvcd_dpb_insert_st_node(ps_dpb_mgr, ps_cur_au);
1164
1165
9.16k
                    if(i4_error_code != OK)
1166
0
                    {
1167
0
                        return IV_FAIL;
1168
0
                    }
1169
1170
9.16k
                    imvcd_dpb_delete_st_node_or_make_lt(ps_dpb_mgr, ps_cur_au->i4_pic_num, 0);
1171
1172
9.16k
                    ps_dpb_mgr->u1_max_lt_frame_idx = 0;
1173
9.16k
                }
1174
18.5k
            }
1175
46.5k
            else if(!ps_dpb_mgr->u1_mmco_error_in_seq)
1176
45.7k
            {
1177
45.7k
                i4_error_code = imvcd_dpb_do_mmco(ps_view_ctxt->ps_dpb_cmds, ps_dpb_mgr, ps_cur_au,
1178
45.7k
                                                  ps_view_ctxt->ps_cur_sps->u1_num_ref_frames,
1179
45.7k
                                                  ps_view_ctxt->e_dec_status);
1180
1181
45.7k
                ps_dpb_mgr->u1_mmco_error_in_seq = i4_error_code != OK;
1182
45.7k
            }
1183
1184
65.1k
            i4_error_code = imvcd_dpb_update_default_index_list(ps_dpb_mgr);
1185
1186
65.1k
            if(i4_error_code != OK)
1187
0
            {
1188
0
                return IV_FAIL;
1189
0
            }
1190
65.1k
        }
1191
88.2k
    }
1192
1193
88.2k
    ps_op->s_ivd_op.u4_frame_decoded_flag = 1;
1194
1195
88.2k
    return IV_SUCCESS;
1196
88.2k
}
1197
1198
/* Description - 'AU Decode' API for MVC Decoder */
1199
static IV_API_CALL_STATUS_T imvcd_decode(iv_obj_t *ps_dec_hdl, imvcd_video_decode_ip_t *ps_ip,
1200
                                         imvcd_video_decode_op_t *ps_op)
1201
94.8k
{
1202
94.8k
    IV_API_CALL_STATUS_T e_retval;
1203
1204
94.8k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1205
94.8k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1206
94.8k
    imvcd_video_decode_ip_t s_view_ip = ps_ip[0];
1207
94.8k
    imvcd_video_decode_op_t s_view_op = ps_op[0];
1208
1209
94.8k
    UWORD16 u2_num_views_decoded = 0;
1210
94.8k
    UWORD16 u2_num_views = (ps_mvcd_ctxt->b_flush_enabled || ps_mvcd_ctxt->b_header_only_decode)
1211
94.8k
                               ? 1
1212
94.8k
                               : ps_mvcd_ctxt->u2_num_views;
1213
1214
94.8k
    ps_mvcd_ctxt->u2_num_views_decoded = 0;
1215
1216
94.8k
    if(IV_SUCCESS != imvcd_check_dec_handle(ps_dec_hdl))
1217
0
    {
1218
0
        return IV_FAIL;
1219
0
    }
1220
1221
94.8k
    if(IV_SUCCESS != imvcd_check_decode_structs(ps_dec_hdl, ps_ip, ps_op))
1222
0
    {
1223
0
        return IV_FAIL;
1224
0
    }
1225
1226
94.8k
    if(!ps_mvcd_ctxt->b_header_only_decode)
1227
91.0k
    {
1228
91.0k
        if(IV_SUCCESS != imvcd_au_error_checks(ps_mvcd_ctxt, ps_ip))
1229
510
        {
1230
510
            return IV_FAIL;
1231
510
        }
1232
91.0k
    }
1233
1234
    /*Data memory barries instruction,so that bitstream write by the application
1235
     * is complete*/
1236
94.3k
    DATA_SYNC();
1237
1238
94.3k
    imvcd_au_init(ps_dec_hdl, ps_ip, ps_op);
1239
1240
94.3k
    if(ps_mvcd_ctxt->b_flush_enabled)
1241
0
    {
1242
0
        return imvcd_flush_mode_decode(ps_mvcd_ctxt, ps_op);
1243
0
    }
1244
1245
188k
    while(u2_num_views_decoded < u2_num_views)
1246
96.0k
    {
1247
96.0k
        e_retval = imvcd_view_decode(ps_dec_hdl, &s_view_ip, &s_view_op);
1248
1249
96.0k
        if(IV_SUCCESS != e_retval)
1250
2.32k
        {
1251
2.32k
            ps_op->s_ivd_op.u4_error_code = s_view_op.s_ivd_op.u4_error_code;
1252
1253
2.32k
            return IV_FAIL;
1254
2.32k
        }
1255
1256
93.7k
        s_view_ip.s_ivd_ip.pv_stream_buffer = ((UWORD8 *) s_view_ip.s_ivd_ip.pv_stream_buffer) +
1257
93.7k
                                              s_view_op.s_ivd_op.u4_num_bytes_consumed;
1258
93.7k
        s_view_ip.s_ivd_ip.u4_num_Bytes -= s_view_op.s_ivd_op.u4_num_bytes_consumed;
1259
93.7k
        ps_op->s_ivd_op.u4_num_bytes_consumed += s_view_op.s_ivd_op.u4_num_bytes_consumed;
1260
1261
93.7k
        u2_num_views_decoded++;
1262
93.7k
        ps_mvcd_ctxt->u2_num_views_decoded++;
1263
93.7k
    }
1264
1265
91.9k
    if(!ps_mvcd_ctxt->b_header_only_decode)
1266
88.2k
    {
1267
88.2k
        e_retval = imvcd_finish_au_decode(ps_mvcd_ctxt, ps_op);
1268
1269
88.2k
        if(IV_SUCCESS != e_retval)
1270
0
        {
1271
0
            return IV_FAIL;
1272
0
        }
1273
88.2k
    }
1274
1275
91.9k
    ps_op->s_ivd_op.u4_pic_wd = ps_view_ctxt->u2_disp_width;
1276
91.9k
    ps_op->s_ivd_op.u4_pic_ht = ps_view_ctxt->u2_disp_height;
1277
91.9k
    ps_op->s_ivd_op.u4_output_present = ps_view_ctxt->u4_output_present;
1278
91.9k
    ps_op->s_ivd_op.u4_ts = ps_view_ctxt->s_disp_op.u4_ts;
1279
91.9k
    ps_op->s_ivd_op.i4_reorder_depth = ps_view_ctxt->i4_reorder_depth;
1280
91.9k
    ps_op->s_ivd_op.e_output_format = IV_YUV_420P;
1281
1282
91.9k
    if(ps_op->s_ivd_op.u4_output_present)
1283
71.1k
    {
1284
71.1k
        imvcd_convert_to_app_disp_buf(ps_mvcd_ctxt, ps_op->ps_view_disp_bufs);
1285
71.1k
    }
1286
1287
91.9k
    return e_retval;
1288
91.9k
}
1289
1290
static IV_API_CALL_STATUS_T imvcd_ctl_set_dec_mode(iv_obj_t *ps_dec_hdl,
1291
                                                   imvcd_set_config_ip_t *ps_ip,
1292
                                                   imvcd_set_config_op_t *ps_op)
1293
94.8k
{
1294
94.8k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1295
94.8k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1296
1297
94.8k
    ps_view_ctxt->u4_skip_frm_mask = SKIP_NONE;
1298
1299
94.8k
    ps_op->s_ivd_op.u4_error_code = 0;
1300
1301
94.8k
    ps_view_ctxt->u4_app_disp_width = 0;
1302
1303
94.8k
    if(ps_ip->s_ivd_ip.e_frm_skip_mode != IVD_SKIP_NONE)
1304
0
    {
1305
0
        ps_op->s_ivd_op.u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
1306
1307
0
        return IV_FAIL;
1308
0
    }
1309
1310
94.8k
    if(ps_ip->s_ivd_ip.e_vid_dec_mode == IVD_DECODE_FRAME)
1311
91.0k
    {
1312
91.0k
        ps_view_ctxt->i4_decode_header = 0;
1313
91.0k
        ps_mvcd_ctxt->b_header_only_decode = false;
1314
91.0k
    }
1315
3.73k
    else if(ps_ip->s_ivd_ip.e_vid_dec_mode == IVD_DECODE_HEADER)
1316
3.73k
    {
1317
3.73k
        ps_view_ctxt->i4_decode_header = 1;
1318
3.73k
        ps_mvcd_ctxt->b_header_only_decode = true;
1319
3.73k
    }
1320
0
    else
1321
0
    {
1322
0
        ps_op->s_ivd_op.u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
1323
1324
0
        return IV_FAIL;
1325
0
    }
1326
1327
94.8k
    if((ps_ip->s_ivd_ip.e_frm_out_mode != IVD_DECODE_FRAME_OUT) &&
1328
94.8k
       (ps_ip->s_ivd_ip.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT))
1329
0
    {
1330
0
        ps_op->s_ivd_op.u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
1331
1332
0
        return IV_FAIL;
1333
0
    }
1334
1335
94.8k
    ps_mvcd_ctxt->b_flush_enabled = false;
1336
94.8k
    ps_view_ctxt->e_frm_out_mode = ps_ip->s_ivd_ip.e_frm_out_mode;
1337
1338
94.8k
    return IV_SUCCESS;
1339
94.8k
}
1340
1341
static IV_API_CALL_STATUS_T imvcd_ctl_set_num_cores(iv_obj_t *ps_dec_hdl,
1342
                                                    imvcd_set_num_cores_ip_t *ps_ip,
1343
                                                    imvcd_set_num_cores_op_t *ps_op)
1344
3.73k
{
1345
3.73k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1346
3.73k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1347
1348
3.73k
    ps_view_ctxt->u4_num_cores = ps_ip->u4_num_cores;
1349
1350
3.73k
    ps_op->u4_error_code = 0;
1351
1352
3.73k
    if(ps_view_ctxt->u4_num_cores == 1)
1353
1.24k
    {
1354
1.24k
        ps_view_ctxt->u1_separate_parse = 0;
1355
1.24k
    }
1356
2.49k
    else
1357
2.49k
    {
1358
2.49k
        ps_view_ctxt->u1_separate_parse = 1;
1359
2.49k
    }
1360
1361
    /*using only upto three threads currently*/
1362
3.73k
    if(ps_view_ctxt->u4_num_cores > 3)
1363
0
    {
1364
0
        ps_view_ctxt->u4_num_cores = 3;
1365
0
    }
1366
1367
3.73k
    return IV_SUCCESS;
1368
3.73k
}
1369
1370
static IV_API_CALL_STATUS_T imvcd_ctl_set_arch(iv_obj_t *ps_dec_hdl, imvcd_set_arch_ip_t *ps_ip,
1371
                                               imvcd_set_arch_op_t *ps_op)
1372
3.73k
{
1373
3.73k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1374
3.73k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1375
1376
3.73k
    ps_view_ctxt->e_processor_arch = ps_ip->e_arch;
1377
3.73k
    ps_view_ctxt->e_processor_soc = ps_ip->e_soc;
1378
1379
3.73k
    ps_op->u4_error_code = 0;
1380
1381
3.73k
    return IV_SUCCESS;
1382
3.73k
}
1383
1384
static IV_API_CALL_STATUS_T imvcd_ctl_set_degrade_mode(iv_obj_t *ps_dec_hdl,
1385
                                                       imvcd_set_degrade_mode_ip_t *ps_ip,
1386
                                                       imvcd_set_degrade_mode_op_t *ps_op)
1387
0
{
1388
0
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1389
0
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1390
1391
0
    ps_view_ctxt->i4_degrade_type = ps_ip->i4_degrade_type;
1392
0
    ps_view_ctxt->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
1393
0
    ps_view_ctxt->i4_degrade_pics = ps_ip->i4_degrade_pics;
1394
0
    ps_view_ctxt->i4_degrade_pic_cnt = 0;
1395
1396
0
    ps_op->u4_error_code = 0;
1397
1398
0
    return IV_SUCCESS;
1399
0
}
1400
1401
static IV_API_CALL_STATUS_T imvcd_ctl_flush_dec(iv_obj_t *ps_dec_hdl, imvcd_flush_dec_ip_t *ps_ip,
1402
                                                imvcd_flush_dec_op_t *ps_op)
1403
0
{
1404
0
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1405
0
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1406
1407
0
    UNUSED(ps_ip);
1408
1409
0
    ps_op->s_ivd_op.u4_error_code = 0;
1410
1411
0
    ps_mvcd_ctxt->b_flush_enabled = true;
1412
0
    ps_view_ctxt->u1_flushfrm = 1;
1413
1414
0
    if(ps_view_ctxt->u1_init_dec_flag)
1415
0
    {
1416
0
        imvcd_release_all_ref_bufs(ps_mvcd_ctxt, ps_view_ctxt->u1_pic_bufs);
1417
0
        imvcd_dpb_release_display_bufs(ps_mvcd_ctxt->ps_dpb_mgr);
1418
0
    }
1419
1420
    /* Ignore dangling fields during flush */
1421
0
    ps_view_ctxt->u1_top_bottom_decoded = 0;
1422
1423
0
    return IV_SUCCESS;
1424
0
}
1425
1426
static IV_API_CALL_STATUS_T imvcd_ctl_get_buf_info(iv_obj_t *ps_dec_hdl,
1427
                                                   imvcd_get_buf_info_ip_t *ps_ip,
1428
                                                   imvcd_get_buf_info_op_t *ps_op)
1429
3.67k
{
1430
3.67k
    UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
1431
3.67k
    UWORD32 u4_pic_wd, u4_pic_ht;
1432
3.67k
    UWORD32 i;
1433
1434
3.67k
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1435
3.67k
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1436
1437
3.67k
    UNUSED(ps_ip);
1438
1439
3.67k
    ps_op->s_ivd_op.u4_error_code = 0;
1440
1441
3.67k
    ps_op->s_ivd_op.u4_num_disp_bufs = 0;
1442
3.67k
    ps_op->s_ivd_op.u4_min_num_in_bufs = MIN_IN_BUFS;
1443
1444
3.67k
    u4_pic_wd = 0;
1445
3.67k
    u4_pic_ht = 0;
1446
1447
3.67k
    if(is_header_decoded(ps_view_ctxt->i4_header_decoded, SPS))
1448
3.67k
    {
1449
3.67k
        u4_pic_wd = ps_view_ctxt->u2_disp_width;
1450
3.67k
        u4_pic_ht = ps_view_ctxt->u2_disp_height;
1451
3.67k
    }
1452
1453
3.67k
    ps_op->s_mvc_buf_info.u2_num_views = ps_mvcd_ctxt->u2_num_views;
1454
1455
7.35k
    for(i = 0; i < ps_op->s_ivd_op.u4_min_num_in_bufs; i++)
1456
3.67k
    {
1457
3.67k
        ps_op->s_ivd_op.u4_min_in_buf_size[i] =
1458
3.67k
            MAX(256000, u4_pic_wd * u4_pic_ht * ps_mvcd_ctxt->u2_num_views * 3 / 2);
1459
3.67k
    }
1460
1461
3.67k
    ps_op->s_ivd_op.u4_min_num_out_bufs = ih264d_get_outbuf_size(
1462
3.67k
        u4_pic_wd, u4_pic_ht, ps_view_ctxt->u1_chroma_format, &au4_min_out_buf_size[0]);
1463
3.67k
    ps_op->s_ivd_op.u4_min_num_out_bufs *= ps_mvcd_ctxt->u2_num_views;
1464
1465
15.3k
    for(i = 0; i < ps_op->s_ivd_op.u4_min_num_out_bufs; i++)
1466
11.6k
    {
1467
11.6k
        ps_op->s_ivd_op.u4_min_out_buf_size[i] = au4_min_out_buf_size[i % NUM_COMPONENTS];
1468
11.6k
    }
1469
1470
3.67k
    return IV_SUCCESS;
1471
3.67k
}
1472
1473
static IV_API_CALL_STATUS_T imvcd_ctl_get_vui(iv_obj_t *ps_dec_hdl, imvcd_get_vui_ip_t *ps_ip,
1474
                                              imvcd_get_vui_op_t *ps_op)
1475
0
{
1476
0
    mvc_dec_ctxt_t *ps_mvcd_ctxt = (mvc_dec_ctxt_t *) ps_dec_hdl->pv_codec_handle;
1477
0
    dec_struct_t *ps_view_ctxt = &ps_mvcd_ctxt->s_view_dec_ctxt;
1478
1479
0
    UNUSED(ps_ip);
1480
1481
0
    ps_op->u4_error_code = 0;
1482
0
    ps_op->b_is_vui_available = false;
1483
1484
0
    if((ps_mvcd_ctxt->u1_num_sps > 0) && ps_view_ctxt->ps_cur_sps)
1485
0
    {
1486
0
        ps_op->b_is_vui_available = ps_view_ctxt->ps_cur_sps->u1_vui_parameters_present_flag;
1487
1488
0
        if(ps_op->b_is_vui_available)
1489
0
        {
1490
0
            ps_op->u1_aspect_ratio_idc = ps_view_ctxt->ps_cur_sps->s_vui.u1_aspect_ratio_idc;
1491
0
            ps_op->u2_sar_width = ps_view_ctxt->ps_cur_sps->s_vui.u2_sar_width;
1492
0
            ps_op->u2_sar_height = ps_view_ctxt->ps_cur_sps->s_vui.u2_sar_height;
1493
0
            ps_op->u1_overscan_appropriate_flag =
1494
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_overscan_appropriate_flag;
1495
0
            ps_op->u1_video_format = ps_view_ctxt->ps_cur_sps->s_vui.u1_video_format;
1496
0
            ps_op->u1_video_full_range_flag =
1497
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_video_full_range_flag;
1498
0
            ps_op->u1_colour_primaries = ps_view_ctxt->ps_cur_sps->s_vui.u1_colour_primaries;
1499
0
            ps_op->u1_tfr_chars = ps_view_ctxt->ps_cur_sps->s_vui.u1_tfr_chars;
1500
0
            ps_op->u1_matrix_coeffs = ps_view_ctxt->ps_cur_sps->s_vui.u1_matrix_coeffs;
1501
0
            ps_op->u1_cr_top_field = ps_view_ctxt->ps_cur_sps->s_vui.u1_cr_top_field;
1502
0
            ps_op->u1_cr_bottom_field = ps_view_ctxt->ps_cur_sps->s_vui.u1_cr_bottom_field;
1503
0
            ps_op->u4_num_units_in_tick = ps_view_ctxt->ps_cur_sps->s_vui.u4_num_units_in_tick;
1504
0
            ps_op->u4_time_scale = ps_view_ctxt->ps_cur_sps->s_vui.u4_time_scale;
1505
0
            ps_op->u1_fixed_frame_rate_flag =
1506
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_fixed_frame_rate_flag;
1507
0
            ps_op->u1_nal_hrd_params_present =
1508
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_nal_hrd_params_present;
1509
0
            ps_op->u1_vcl_hrd_params_present =
1510
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_vcl_hrd_params_present;
1511
0
            ps_op->u1_low_delay_hrd_flag = ps_view_ctxt->ps_cur_sps->s_vui.u1_low_delay_hrd_flag;
1512
0
            ps_op->u1_pic_struct_present_flag =
1513
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_pic_struct_present_flag;
1514
0
            ps_op->u1_bitstream_restriction_flag =
1515
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_bitstream_restriction_flag;
1516
0
            ps_op->u1_mv_over_pic_boundaries_flag =
1517
0
                ps_view_ctxt->ps_cur_sps->s_vui.u1_mv_over_pic_boundaries_flag;
1518
0
            ps_op->u4_max_bytes_per_pic_denom =
1519
0
                ps_view_ctxt->ps_cur_sps->s_vui.u4_max_bytes_per_pic_denom;
1520
0
            ps_op->u4_max_bits_per_mb_denom =
1521
0
                ps_view_ctxt->ps_cur_sps->s_vui.u4_max_bits_per_mb_denom;
1522
0
            ps_op->u4_log2_max_mv_length_horz =
1523
0
                ps_view_ctxt->ps_cur_sps->s_vui.u4_log2_max_mv_length_horz;
1524
0
            ps_op->u4_log2_max_mv_length_vert =
1525
0
                ps_view_ctxt->ps_cur_sps->s_vui.u4_log2_max_mv_length_vert;
1526
0
            ps_op->u4_num_reorder_frames = ps_view_ctxt->ps_cur_sps->s_vui.u4_num_reorder_frames;
1527
0
            ps_op->u4_max_dec_frame_buffering =
1528
0
                ps_view_ctxt->ps_cur_sps->s_vui.u4_max_dec_frame_buffering;
1529
0
        }
1530
0
    }
1531
1532
0
    return IV_SUCCESS;
1533
0
}
1534
1535
/* Description - 'Control Cmd' API for MVC Decoder */
1536
static IV_API_CALL_STATUS_T imvcd_ctl_cmd_handler(iv_obj_t *ps_dec_hdl, void *pv_ip, void *pv_op)
1537
105k
{
1538
105k
    ivd_ctl_set_config_ip_t *ps_ip = (ivd_ctl_set_config_ip_t *) pv_ip;
1539
1540
105k
    WORD32 i4_sub_cmd = ps_ip->e_sub_cmd;
1541
1542
105k
    if(IV_SUCCESS != imvcd_check_dec_handle(ps_dec_hdl))
1543
0
    {
1544
0
        return IV_FAIL;
1545
0
    }
1546
1547
105k
    if(IV_SUCCESS != imvcd_check_ctl_structs(pv_ip, pv_op))
1548
0
    {
1549
0
        return IV_FAIL;
1550
0
    }
1551
1552
105k
    switch(i4_sub_cmd)
1553
105k
    {
1554
94.8k
        case IVD_CMD_CTL_SETPARAMS:
1555
94.8k
        {
1556
94.8k
            return imvcd_ctl_set_dec_mode(ps_dec_hdl, pv_ip, pv_op);
1557
0
        }
1558
3.73k
        case IMVCD_CTL_SET_NUM_CORES:
1559
3.73k
        {
1560
3.73k
            return imvcd_ctl_set_num_cores(ps_dec_hdl, pv_ip, pv_op);
1561
0
        }
1562
3.73k
        case IMVCD_CTL_SET_PROCESSOR:
1563
3.73k
        {
1564
3.73k
            return imvcd_ctl_set_arch(ps_dec_hdl, pv_ip, pv_op);
1565
0
        }
1566
0
        case IMVCD_CTL_DEGRADE:
1567
0
        {
1568
0
            return imvcd_ctl_set_degrade_mode(ps_dec_hdl, pv_ip, pv_op);
1569
0
        }
1570
0
        case IVD_CMD_CTL_FLUSH:
1571
0
        {
1572
0
            return imvcd_ctl_flush_dec(ps_dec_hdl, pv_ip, pv_op);
1573
0
        }
1574
3.67k
        case IVD_CMD_CTL_GETBUFINFO:
1575
3.67k
        {
1576
3.67k
            return imvcd_ctl_get_buf_info(ps_dec_hdl, pv_ip, pv_op);
1577
0
        }
1578
0
        case IMVCD_CTL_GET_VUI_PARAMS:
1579
0
        {
1580
0
            return imvcd_ctl_get_vui(ps_dec_hdl, pv_ip, pv_op);
1581
0
        }
1582
0
        default:
1583
0
        {
1584
0
            return IV_FAIL;
1585
0
        }
1586
105k
    }
1587
105k
}
1588
1589
IV_API_CALL_STATUS_T imvcd_api_function(iv_obj_t *ps_dec_hdl, void *pv_ip, void *pv_op)
1590
208k
{
1591
208k
    IVD_API_COMMAND_TYPE_T e_cmd = ((WORD32 *) pv_ip)[1];
1592
1593
208k
    switch(e_cmd)
1594
208k
    {
1595
3.73k
        case IVD_CMD_CREATE:
1596
3.73k
        {
1597
3.73k
            return imvcd_create(pv_ip, pv_op);
1598
0
        }
1599
3.73k
        case IVD_CMD_DELETE:
1600
3.73k
        {
1601
3.73k
            return imvcd_delete(ps_dec_hdl);
1602
0
        }
1603
105k
        case IVD_CMD_VIDEO_CTL:
1604
105k
        {
1605
105k
            return imvcd_ctl_cmd_handler(ps_dec_hdl, pv_ip, pv_op);
1606
0
        }
1607
94.8k
        case IVD_CMD_VIDEO_DECODE:
1608
94.8k
        {
1609
94.8k
            return imvcd_decode(ps_dec_hdl, pv_ip, pv_op);
1610
0
        }
1611
0
        default:
1612
0
        {
1613
0
            return IV_FAIL;
1614
0
        }
1615
208k
    }
1616
208k
}