Coverage Report

Created: 2026-01-17 06:18

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/libavc/decoder/ih264d_api.c
Line
Count
Source
1
/******************************************************************************
2
 *
3
 * Copyright (C) 2015 The Android Open Source Project
4
 *
5
 * Licensed under the Apache License, Version 2.0 (the "License");
6
 * you may not use this file except in compliance with the License.
7
 * You may obtain a copy of the License at:
8
 *
9
 * http://www.apache.org/licenses/LICENSE-2.0
10
 *
11
 * Unless required by applicable law or agreed to in writing, software
12
 * distributed under the License is distributed on an "AS IS" BASIS,
13
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14
 * See the License for the specific language governing permissions and
15
 * limitations under the License.
16
 *
17
 *****************************************************************************
18
 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19
*/
20
21
/*****************************************************************************/
22
/*                                                                           */
23
/*  File Name         : ih264d_api.c                                         */
24
/*                                                                           */
25
/*  Description       : Has all  API related functions                       */
26
/*                                                                           */
27
/*                                                                           */
28
/*  List of Functions : api_check_struct_sanity                              */
29
/*          ih264d_set_processor                                             */
30
/*          ih264d_create                                                    */
31
/*          ih264d_delete                                                    */
32
/*          ih264d_init                                                      */
33
/*          ih264d_map_error                                                 */
34
/*          ih264d_video_decode                                              */
35
/*          ih264d_get_version                                               */
36
/*          ih264d_get_display_frame                                         */
37
/*          ih264d_set_display_frame                                         */
38
/*          ih264d_set_flush_mode                                            */
39
/*          ih264d_get_status                                                */
40
/*          ih264d_get_buf_info                                              */
41
/*          ih264d_set_params                                                */
42
/*          ih264d_set_default_params                                        */
43
/*          ih264d_reset                                                     */
44
/*          ih264d_ctl                                                       */
45
/*          ih264d_rel_display_frame                                         */
46
/*          ih264d_set_degrade                                               */
47
/*          ih264d_get_frame_dimensions                                      */
48
/*          ih264d_set_num_cores                                             */
49
/*          ih264d_fill_output_struct_from_context                           */
50
/*          ih264d_api_function                                              */
51
/*                                                                           */
52
/*  Issues / Problems : None                                                 */
53
/*                                                                           */
54
/*  Revision History  :                                                      */
55
/*                                                                           */
56
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
57
/*         14 10 2008   100356(SKV)     Draft                                */
58
/*                                                                           */
59
/*****************************************************************************/
60
#include "ih264_typedefs.h"
61
#include "ih264_macros.h"
62
#include "ih264_platform_macros.h"
63
#include "ih264d_tables.h"
64
#include "iv.h"
65
#include "ivd.h"
66
#include "ih264d.h"
67
#include "ih264d_defs.h"
68
69
#include <string.h>
70
#include <limits.h>
71
#include <stddef.h>
72
73
#include "ih264d_inter_pred.h"
74
75
#include "ih264d_structs.h"
76
#include "ih264d_nal.h"
77
#include "ih264d_error_handler.h"
78
79
#include "ih264d_defs.h"
80
81
#include "ithread.h"
82
#include "ih264d_parse_slice.h"
83
#include "ih264d_function_selector.h"
84
#include "ih264_error.h"
85
#include "ih264_disp_mgr.h"
86
#include "ih264_buf_mgr.h"
87
#include "ih264d_deblocking.h"
88
#include "ih264d_parse_cavlc.h"
89
#include "ih264d_parse_cabac.h"
90
#include "ih264d_utils.h"
91
#include "ih264d_format_conv.h"
92
#include "ih264d_parse_headers.h"
93
#include "ih264d_thread_compute_bs.h"
94
#include <assert.h>
95
96
97
/*********************/
98
/* Codec Versioning  */
99
/*********************/
100
//Move this to where it is used
101
#define CODEC_NAME              "H264VDEC"
102
#define CODEC_RELEASE_TYPE      "production"
103
#define CODEC_RELEASE_VER       "05.00"
104
#define CODEC_VENDOR            "ITTIAM"
105
0
#define MAXVERSION_STRLEN       511
106
#ifdef ANDROID
107
#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor)    \
108
    snprintf(version_string, MAXVERSION_STRLEN,                                                     \
109
             "@(#)Id:%s_%s Ver:%s Released by %s",                                                  \
110
             codec_name, codec_release_type, codec_release_ver, codec_vendor)
111
#else
112
#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor)    \
113
0
    snprintf(version_string, MAXVERSION_STRLEN,                                                     \
114
0
             "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s",                                   \
115
0
             codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__)
116
#endif
117
118
119
0
#define MIN_IN_BUFS             1
120
76.8k
#define MIN_OUT_BUFS_420        3
121
2.30k
#define MIN_OUT_BUFS_422ILE     1
122
754
#define MIN_OUT_BUFS_RGB565     1
123
70.1k
#define MIN_OUT_BUFS_420SP      2
124
125
#define NUM_FRAMES_LIMIT_ENABLED 0
126
127
#if NUM_FRAMES_LIMIT_ENABLED
128
#define NUM_FRAMES_LIMIT 10000
129
#else
130
16.1k
#define NUM_FRAMES_LIMIT 0x7FFFFFFF
131
#endif
132
133
134
UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height);
135
WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
136
                                   void *pv_api_ip,
137
                                   void *pv_api_op);
138
WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
139
                             void *pv_api_ip,
140
                             void *pv_api_op);
141
142
WORD32 ih264d_get_sei_mdcv_params(iv_obj_t *dec_hdl,
143
                                  void *pv_api_ip,
144
                                  void *pv_api_op);
145
146
WORD32 ih264d_get_sei_cll_params(iv_obj_t *dec_hdl,
147
                                 void *pv_api_ip,
148
                                 void *pv_api_op);
149
150
WORD32 ih264d_get_sei_ave_params(iv_obj_t *dec_hdl,
151
                                 void *pv_api_ip,
152
                                 void *pv_api_op);
153
154
WORD32 ih264d_get_sei_ccv_params(iv_obj_t *dec_hdl,
155
                                 void *pv_api_ip,
156
                                 void *pv_api_op);
157
158
WORD32 ih264d_get_sei_sii_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
159
160
WORD32 ih264d_get_sei_fgc_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
161
162
WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
163
164
WORD32 ih264d_deblock_display(dec_struct_t *ps_dec);
165
166
void ih264d_signal_decode_thread(dec_struct_t *ps_dec);
167
168
void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec);
169
void ih264d_decode_picture_thread(dec_struct_t *ps_dec);
170
171
WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
172
                          void *pv_api_ip,
173
                          void *pv_api_op);
174
175
void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
176
                                            ivd_video_decode_op_t *ps_dec_op);
177
178
/*!
179
 **************************************************************************
180
 * \if Function name : ih264d_export_sei_params \endif
181
 *
182
 * \brief
183
 *    Exports sei params from decoder to application.
184
 *
185
 * \return
186
 *    0 on Success and error code otherwise
187
 **************************************************************************
188
 */
189
190
void ih264d_export_sei_params(ivd_sei_decode_op_t *ps_sei_decode_op, dec_struct_t *ps_dec)
191
217k
{
192
217k
    WORD32 i4_status = IV_SUCCESS;
193
217k
    sei *ps_sei = (sei *)ps_dec->pv_disp_sei_params;
194
195
217k
    i4_status = ih264d_export_sei_mdcv_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
196
217k
    i4_status = ih264d_export_sei_cll_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
197
217k
    i4_status = ih264d_export_sei_ave_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
198
217k
    i4_status = ih264d_export_sei_ccv_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
199
217k
    i4_status = ih264d_export_sei_sii_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
200
217k
    i4_status = ih264d_export_sei_fgc_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
201
202
217k
    UNUSED(i4_status);
203
217k
}
204
205
static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
206
                                                    void *pv_api_ip,
207
                                                    void *pv_api_op)
208
19.7k
{
209
19.7k
    IVD_API_COMMAND_TYPE_T e_cmd;
210
19.7k
    UWORD32 *pu4_api_ip;
211
19.7k
    UWORD32 *pu4_api_op;
212
19.7k
    UWORD32 i, j;
213
214
19.7k
    if(NULL == pv_api_op)
215
0
        return (IV_FAIL);
216
217
19.7k
    if(NULL == pv_api_ip)
218
0
        return (IV_FAIL);
219
220
19.7k
    pu4_api_ip = (UWORD32 *)pv_api_ip;
221
19.7k
    pu4_api_op = (UWORD32 *)pv_api_op;
222
19.7k
    e_cmd = *(pu4_api_ip + 1);
223
224
    /* error checks on handle */
225
19.7k
    switch((WORD32)e_cmd)
226
19.7k
    {
227
359
        case IVD_CMD_CREATE:
228
359
            break;
229
230
0
        case IVD_CMD_REL_DISPLAY_FRAME:
231
0
        case IVD_CMD_SET_DISPLAY_FRAME:
232
0
        case IVD_CMD_GET_DISPLAY_FRAME:
233
16.1k
        case IVD_CMD_VIDEO_DECODE:
234
16.5k
        case IVD_CMD_DELETE:
235
19.4k
        case IVD_CMD_VIDEO_CTL:
236
19.4k
            if(ps_handle == NULL)
237
0
            {
238
0
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
239
0
                *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
240
0
                return IV_FAIL;
241
0
            }
242
243
19.4k
            if(ps_handle->u4_size != sizeof(iv_obj_t))
244
0
            {
245
0
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
246
0
                *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
247
0
                return IV_FAIL;
248
0
            }
249
250
19.4k
            if(ps_handle->pv_fxns != ih264d_api_function)
251
0
            {
252
0
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
253
0
                *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
254
0
                return IV_FAIL;
255
0
            }
256
257
19.4k
            if(ps_handle->pv_codec_handle == NULL)
258
0
            {
259
0
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
260
0
                *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
261
0
                return IV_FAIL;
262
0
            }
263
19.4k
            break;
264
19.4k
        default:
265
0
            *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
266
0
            *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
267
0
            return IV_FAIL;
268
19.7k
    }
269
270
19.7k
    switch((WORD32)e_cmd)
271
19.7k
    {
272
359
        case IVD_CMD_CREATE:
273
359
        {
274
359
            ih264d_create_ip_t *ps_ip = (ih264d_create_ip_t *)pv_api_ip;
275
359
            ih264d_create_op_t *ps_op = (ih264d_create_op_t *)pv_api_op;
276
277
278
359
            ps_op->s_ivd_create_op_t.u4_error_code = 0;
279
280
359
            if((ps_ip->s_ivd_create_ip_t.u4_size > sizeof(ih264d_create_ip_t))
281
359
                            || (ps_ip->s_ivd_create_ip_t.u4_size
282
359
                                            < sizeof(ivd_create_ip_t)))
283
0
            {
284
0
                ps_op->s_ivd_create_op_t.u4_error_code |= 1
285
0
                                << IVD_UNSUPPORTEDPARAM;
286
0
                ps_op->s_ivd_create_op_t.u4_error_code |=
287
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
288
0
                H264_DEC_DEBUG_PRINT("\n");
289
0
                return (IV_FAIL);
290
0
            }
291
292
359
            if((ps_op->s_ivd_create_op_t.u4_size != sizeof(ih264d_create_op_t))
293
0
                            && (ps_op->s_ivd_create_op_t.u4_size
294
0
                                            != sizeof(ivd_create_op_t)))
295
0
            {
296
0
                ps_op->s_ivd_create_op_t.u4_error_code |= 1
297
0
                                << IVD_UNSUPPORTEDPARAM;
298
0
                ps_op->s_ivd_create_op_t.u4_error_code |=
299
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
300
0
                H264_DEC_DEBUG_PRINT("\n");
301
0
                return (IV_FAIL);
302
0
            }
303
304
305
359
            if((ps_ip->s_ivd_create_ip_t.e_output_format != IV_YUV_420P)
306
261
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
307
261
                                            != IV_YUV_422ILE)
308
168
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
309
168
                                            != IV_RGB_565)
310
131
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
311
131
                                            != IV_YUV_420SP_UV)
312
98
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
313
98
                                            != IV_YUV_420SP_VU))
314
0
            {
315
0
                ps_op->s_ivd_create_op_t.u4_error_code |= 1
316
0
                                << IVD_UNSUPPORTEDPARAM;
317
0
                ps_op->s_ivd_create_op_t.u4_error_code |=
318
0
                                IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
319
0
                H264_DEC_DEBUG_PRINT("\n");
320
0
                return (IV_FAIL);
321
0
            }
322
323
359
        }
324
359
            break;
325
326
359
        case IVD_CMD_GET_DISPLAY_FRAME:
327
0
        {
328
0
            ih264d_get_display_frame_ip_t *ps_ip =
329
0
                            (ih264d_get_display_frame_ip_t *)pv_api_ip;
330
0
            ih264d_get_display_frame_op_t *ps_op =
331
0
                            (ih264d_get_display_frame_op_t *)pv_api_op;
332
333
0
            ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
334
335
0
            if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size
336
0
                            != sizeof(ih264d_get_display_frame_ip_t))
337
0
                            && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size
338
0
                                            != sizeof(ivd_get_display_frame_ip_t)))
339
0
            {
340
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
341
0
                                << IVD_UNSUPPORTEDPARAM;
342
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
343
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
344
0
                return (IV_FAIL);
345
0
            }
346
347
0
            if((ps_op->s_ivd_get_display_frame_op_t.u4_size
348
0
                            != sizeof(ih264d_get_display_frame_op_t))
349
0
                            && (ps_op->s_ivd_get_display_frame_op_t.u4_size
350
0
                                            != sizeof(ivd_get_display_frame_op_t)))
351
0
            {
352
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
353
0
                                << IVD_UNSUPPORTEDPARAM;
354
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
355
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
356
0
                return (IV_FAIL);
357
0
            }
358
0
        }
359
0
            break;
360
361
0
        case IVD_CMD_REL_DISPLAY_FRAME:
362
0
        {
363
0
            ih264d_rel_display_frame_ip_t *ps_ip =
364
0
                            (ih264d_rel_display_frame_ip_t *)pv_api_ip;
365
0
            ih264d_rel_display_frame_op_t *ps_op =
366
0
                            (ih264d_rel_display_frame_op_t *)pv_api_op;
367
368
0
            ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
369
370
0
            if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
371
0
                            != sizeof(ih264d_rel_display_frame_ip_t))
372
0
                            && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
373
0
                                            != sizeof(ivd_rel_display_frame_ip_t)))
374
0
            {
375
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
376
0
                                << IVD_UNSUPPORTEDPARAM;
377
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
378
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
379
0
                return (IV_FAIL);
380
0
            }
381
382
0
            if((ps_op->s_ivd_rel_display_frame_op_t.u4_size
383
0
                            != sizeof(ih264d_rel_display_frame_op_t))
384
0
                            && (ps_op->s_ivd_rel_display_frame_op_t.u4_size
385
0
                                            != sizeof(ivd_rel_display_frame_op_t)))
386
0
            {
387
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
388
0
                                << IVD_UNSUPPORTEDPARAM;
389
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
390
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
391
0
                return (IV_FAIL);
392
0
            }
393
394
0
        }
395
0
            break;
396
397
0
        case IVD_CMD_SET_DISPLAY_FRAME:
398
0
        {
399
0
            ih264d_set_display_frame_ip_t *ps_ip =
400
0
                            (ih264d_set_display_frame_ip_t *)pv_api_ip;
401
0
            ih264d_set_display_frame_op_t *ps_op =
402
0
                            (ih264d_set_display_frame_op_t *)pv_api_op;
403
0
            UWORD32 j;
404
405
0
            ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
406
407
0
            if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size
408
0
                            != sizeof(ih264d_set_display_frame_ip_t))
409
0
                            && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size
410
0
                                            != sizeof(ivd_set_display_frame_ip_t)))
411
0
            {
412
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
413
0
                                << IVD_UNSUPPORTEDPARAM;
414
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
415
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
416
0
                return (IV_FAIL);
417
0
            }
418
419
0
            if((ps_op->s_ivd_set_display_frame_op_t.u4_size
420
0
                            != sizeof(ih264d_set_display_frame_op_t))
421
0
                            && (ps_op->s_ivd_set_display_frame_op_t.u4_size
422
0
                                            != sizeof(ivd_set_display_frame_op_t)))
423
0
            {
424
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
425
0
                                << IVD_UNSUPPORTEDPARAM;
426
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
427
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
428
0
                return (IV_FAIL);
429
0
            }
430
431
0
            if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
432
0
            {
433
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
434
0
                                << IVD_UNSUPPORTEDPARAM;
435
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
436
0
                                IVD_DISP_FRM_ZERO_OP_BUFS;
437
0
                return IV_FAIL;
438
0
            }
439
440
0
            for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs;
441
0
                            j++)
442
0
            {
443
0
                if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs
444
0
                                == 0)
445
0
                {
446
0
                    ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
447
0
                                    << IVD_UNSUPPORTEDPARAM;
448
0
                    ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
449
0
                                    IVD_DISP_FRM_ZERO_OP_BUFS;
450
0
                    return IV_FAIL;
451
0
                }
452
453
0
                for(i = 0;
454
0
                                i
455
0
                                                < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;
456
0
                                i++)
457
0
                {
458
0
                    if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i]
459
0
                                    == NULL)
460
0
                    {
461
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
462
0
                                        << IVD_UNSUPPORTEDPARAM;
463
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
464
0
                                        IVD_DISP_FRM_OP_BUF_NULL;
465
0
                        return IV_FAIL;
466
0
                    }
467
468
0
                    if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i]
469
0
                                    == 0)
470
0
                    {
471
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
472
0
                                        << IVD_UNSUPPORTEDPARAM;
473
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
474
0
                                        IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
475
0
                        return IV_FAIL;
476
0
                    }
477
0
                }
478
0
            }
479
0
        }
480
0
            break;
481
482
16.1k
        case IVD_CMD_VIDEO_DECODE:
483
16.1k
        {
484
16.1k
            ih264d_video_decode_ip_t *ps_ip =
485
16.1k
                            (ih264d_video_decode_ip_t *)pv_api_ip;
486
16.1k
            ih264d_video_decode_op_t *ps_op =
487
16.1k
                            (ih264d_video_decode_op_t *)pv_api_op;
488
489
16.1k
            H264_DEC_DEBUG_PRINT("The input bytes is: %d",
490
16.1k
                                 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes);
491
16.1k
            ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
492
493
16.1k
            if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(ih264d_video_decode_ip_t) &&
494
16.1k
               ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(ivd_video_decode_ip_t) &&
495
0
               ps_ip->s_ivd_video_decode_ip_t.u4_size !=
496
0
                   offsetof(ivd_video_decode_ip_t, s_out_buffer))
497
0
            {
498
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
499
0
                                << IVD_UNSUPPORTEDPARAM;
500
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |=
501
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
502
0
                return (IV_FAIL);
503
0
            }
504
505
16.1k
            if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(ih264d_video_decode_op_t) &&
506
16.1k
               ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(ivd_video_decode_op_t) &&
507
0
               ps_op->s_ivd_video_decode_op_t.u4_size !=
508
0
                   offsetof(ivd_video_decode_op_t, u4_output_present))
509
0
            {
510
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
511
0
                                << IVD_UNSUPPORTEDPARAM;
512
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |=
513
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
514
0
                return (IV_FAIL);
515
0
            }
516
517
16.1k
            {
518
16.1k
                dec_struct_t *ps_dec = (dec_struct_t *)(ps_handle->pv_codec_handle);
519
16.1k
                if(ps_dec->u1_enable_mb_info)
520
0
                {
521
0
                    if(!ps_ip->pu1_8x8_blk_qp_map && !ps_ip->pu1_8x8_blk_type_map)
522
0
                    {
523
0
                        ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
524
0
                                        << IVD_UNSUPPORTEDPARAM;
525
0
                        ps_op->s_ivd_video_decode_op_t.u4_error_code |=
526
0
                                        IH264D_FRAME_INFO_OP_BUF_NULL;
527
0
                        return IV_FAIL;
528
0
                    }
529
0
                }
530
16.1k
            }
531
16.1k
        }
532
16.1k
            break;
533
534
16.1k
        case IVD_CMD_DELETE:
535
359
        {
536
359
            ih264d_delete_ip_t *ps_ip =
537
359
                            (ih264d_delete_ip_t *)pv_api_ip;
538
359
            ih264d_delete_op_t *ps_op =
539
359
                            (ih264d_delete_op_t *)pv_api_op;
540
541
359
            ps_op->s_ivd_delete_op_t.u4_error_code = 0;
542
543
359
            if(ps_ip->s_ivd_delete_ip_t.u4_size
544
359
                            != sizeof(ih264d_delete_ip_t))
545
0
            {
546
0
                ps_op->s_ivd_delete_op_t.u4_error_code |= 1
547
0
                                << IVD_UNSUPPORTEDPARAM;
548
0
                ps_op->s_ivd_delete_op_t.u4_error_code |=
549
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
550
0
                return (IV_FAIL);
551
0
            }
552
553
359
            if(ps_op->s_ivd_delete_op_t.u4_size
554
359
                            != sizeof(ih264d_delete_op_t))
555
0
            {
556
0
                ps_op->s_ivd_delete_op_t.u4_error_code |= 1
557
0
                                << IVD_UNSUPPORTEDPARAM;
558
0
                ps_op->s_ivd_delete_op_t.u4_error_code |=
559
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
560
0
                return (IV_FAIL);
561
0
            }
562
563
359
        }
564
359
            break;
565
566
2.87k
        case IVD_CMD_VIDEO_CTL:
567
2.87k
        {
568
2.87k
            UWORD32 *pu4_ptr_cmd;
569
2.87k
            UWORD32 sub_command;
570
571
2.87k
            pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
572
2.87k
            pu4_ptr_cmd += 2;
573
2.87k
            sub_command = *pu4_ptr_cmd;
574
575
2.87k
            switch(sub_command)
576
2.87k
            {
577
718
                case IVD_CMD_CTL_SETPARAMS:
578
718
                {
579
718
                    ih264d_ctl_set_config_ip_t *ps_ip;
580
718
                    ih264d_ctl_set_config_op_t *ps_op;
581
718
                    ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip;
582
718
                    ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
583
584
718
                    if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size
585
718
                                    != sizeof(ih264d_ctl_set_config_ip_t))
586
0
                    {
587
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
588
0
                                        << IVD_UNSUPPORTEDPARAM;
589
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
590
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
591
0
                        return IV_FAIL;
592
0
                    }
593
718
                }
594
                    //no break; is needed here
595
718
                case IVD_CMD_CTL_SETDEFAULT:
596
718
                {
597
718
                    ih264d_ctl_set_config_op_t *ps_op;
598
718
                    ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
599
718
                    if(ps_op->s_ivd_ctl_set_config_op_t.u4_size
600
718
                                    != sizeof(ih264d_ctl_set_config_op_t))
601
0
                    {
602
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
603
0
                                        << IVD_UNSUPPORTEDPARAM;
604
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
605
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
606
0
                        return IV_FAIL;
607
0
                    }
608
718
                }
609
718
                    break;
610
611
718
                case IVD_CMD_CTL_GETPARAMS:
612
0
                {
613
0
                    ih264d_ctl_getstatus_ip_t *ps_ip;
614
0
                    ih264d_ctl_getstatus_op_t *ps_op;
615
616
0
                    ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip;
617
0
                    ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op;
618
0
                    if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size
619
0
                                    != sizeof(ih264d_ctl_getstatus_ip_t))
620
0
                    {
621
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
622
0
                                        << IVD_UNSUPPORTEDPARAM;
623
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
624
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
625
0
                        return IV_FAIL;
626
0
                    }
627
0
                    if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size
628
0
                                    != sizeof(ih264d_ctl_getstatus_op_t))
629
0
                    {
630
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
631
0
                                        << IVD_UNSUPPORTEDPARAM;
632
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
633
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
634
0
                        return IV_FAIL;
635
0
                    }
636
0
                }
637
0
                    break;
638
639
0
                case IVD_CMD_CTL_GETBUFINFO:
640
0
                {
641
0
                    ih264d_ctl_getbufinfo_ip_t *ps_ip;
642
0
                    ih264d_ctl_getbufinfo_op_t *ps_op;
643
0
                    ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip;
644
0
                    ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op;
645
646
0
                    if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size
647
0
                                    != sizeof(ih264d_ctl_getbufinfo_ip_t))
648
0
                    {
649
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
650
0
                                        << IVD_UNSUPPORTEDPARAM;
651
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
652
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
653
0
                        return IV_FAIL;
654
0
                    }
655
0
                    if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size
656
0
                                    != sizeof(ih264d_ctl_getbufinfo_op_t))
657
0
                    {
658
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
659
0
                                        << IVD_UNSUPPORTEDPARAM;
660
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
661
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
662
0
                        return IV_FAIL;
663
0
                    }
664
0
                }
665
0
                    break;
666
667
0
                case IVD_CMD_CTL_GETVERSION:
668
0
                {
669
0
                    ih264d_ctl_getversioninfo_ip_t *ps_ip;
670
0
                    ih264d_ctl_getversioninfo_op_t *ps_op;
671
0
                    ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip;
672
0
                    ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op;
673
0
                    if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size
674
0
                                    != sizeof(ih264d_ctl_getversioninfo_ip_t))
675
0
                    {
676
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
677
0
                                        << IVD_UNSUPPORTEDPARAM;
678
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
679
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
680
0
                        return IV_FAIL;
681
0
                    }
682
0
                    if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size
683
0
                                    != sizeof(ih264d_ctl_getversioninfo_op_t))
684
0
                    {
685
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
686
0
                                        << IVD_UNSUPPORTEDPARAM;
687
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
688
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
689
0
                        return IV_FAIL;
690
0
                    }
691
0
                }
692
0
                    break;
693
694
0
                case IVD_CMD_CTL_FLUSH:
695
0
                {
696
0
                    ih264d_ctl_flush_ip_t *ps_ip;
697
0
                    ih264d_ctl_flush_op_t *ps_op;
698
0
                    ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip;
699
0
                    ps_op = (ih264d_ctl_flush_op_t *)pv_api_op;
700
0
                    if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size
701
0
                                    != sizeof(ih264d_ctl_flush_ip_t))
702
0
                    {
703
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
704
0
                                        << IVD_UNSUPPORTEDPARAM;
705
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
706
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
707
0
                        return IV_FAIL;
708
0
                    }
709
0
                    if(ps_op->s_ivd_ctl_flush_op_t.u4_size
710
0
                                    != sizeof(ih264d_ctl_flush_op_t))
711
0
                    {
712
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
713
0
                                        << IVD_UNSUPPORTEDPARAM;
714
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
715
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
716
0
                        return IV_FAIL;
717
0
                    }
718
0
                }
719
0
                    break;
720
721
1.44k
                case IVD_CMD_CTL_RESET:
722
1.44k
                {
723
1.44k
                    ih264d_ctl_reset_ip_t *ps_ip;
724
1.44k
                    ih264d_ctl_reset_op_t *ps_op;
725
1.44k
                    ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip;
726
1.44k
                    ps_op = (ih264d_ctl_reset_op_t *)pv_api_op;
727
1.44k
                    if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size
728
1.44k
                                    != sizeof(ih264d_ctl_reset_ip_t))
729
0
                    {
730
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
731
0
                                        << IVD_UNSUPPORTEDPARAM;
732
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
733
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
734
0
                        return IV_FAIL;
735
0
                    }
736
1.44k
                    if(ps_op->s_ivd_ctl_reset_op_t.u4_size
737
1.44k
                                    != sizeof(ih264d_ctl_reset_op_t))
738
0
                    {
739
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
740
0
                                        << IVD_UNSUPPORTEDPARAM;
741
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
742
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
743
0
                        return IV_FAIL;
744
0
                    }
745
1.44k
                }
746
1.44k
                    break;
747
748
1.44k
                case IH264D_CMD_CTL_DEGRADE:
749
0
                {
750
0
                    ih264d_ctl_degrade_ip_t *ps_ip;
751
0
                    ih264d_ctl_degrade_op_t *ps_op;
752
753
0
                    ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
754
0
                    ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
755
756
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t))
757
0
                    {
758
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
759
0
                        ps_op->u4_error_code |=
760
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
761
0
                        return IV_FAIL;
762
0
                    }
763
764
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t))
765
0
                    {
766
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
767
0
                        ps_op->u4_error_code |=
768
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
769
0
                        return IV_FAIL;
770
0
                    }
771
772
0
                    if((ps_ip->i4_degrade_pics < 0)
773
0
                                    || (ps_ip->i4_degrade_pics > 4)
774
0
                                    || (ps_ip->i4_nondegrade_interval < 0)
775
0
                                    || (ps_ip->i4_degrade_type < 0)
776
0
                                    || (ps_ip->i4_degrade_type > 15))
777
0
                    {
778
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
779
0
                        return IV_FAIL;
780
0
                    }
781
782
0
                    break;
783
0
                }
784
785
0
                case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
786
0
                {
787
0
                    ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
788
0
                    ih264d_ctl_get_frame_dimensions_op_t *ps_op;
789
790
0
                    ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
791
0
                    ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
792
793
0
                    if(ps_ip->u4_size
794
0
                                    != sizeof(ih264d_ctl_get_frame_dimensions_ip_t))
795
0
                    {
796
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
797
0
                        ps_op->u4_error_code |=
798
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
799
0
                        return IV_FAIL;
800
0
                    }
801
802
0
                    if(ps_op->u4_size
803
0
                                    != sizeof(ih264d_ctl_get_frame_dimensions_op_t))
804
0
                    {
805
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
806
0
                        ps_op->u4_error_code |=
807
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
808
0
                        return IV_FAIL;
809
0
                    }
810
811
0
                    break;
812
0
                }
813
0
                case IH264D_CMD_CTL_GET_VUI_PARAMS:
814
0
                {
815
0
                    ih264d_ctl_get_vui_params_ip_t *ps_ip;
816
0
                    ih264d_ctl_get_vui_params_op_t *ps_op;
817
818
0
                    ps_ip =
819
0
                                    (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
820
0
                    ps_op =
821
0
                                    (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
822
823
0
                    if(ps_ip->u4_size
824
0
                                    != sizeof(ih264d_ctl_get_vui_params_ip_t))
825
0
                    {
826
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
827
0
                        ps_op->u4_error_code |=
828
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
829
0
                        return IV_FAIL;
830
0
                    }
831
832
0
                    if(ps_op->u4_size
833
0
                                    != sizeof(ih264d_ctl_get_vui_params_op_t))
834
0
                    {
835
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
836
0
                        ps_op->u4_error_code |=
837
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
838
0
                        return IV_FAIL;
839
0
                    }
840
841
0
                    break;
842
0
                }
843
0
                case IH264D_CMD_CTL_GET_SEI_MDCV_PARAMS:
844
0
                {
845
0
                    ih264d_ctl_get_sei_mdcv_params_ip_t *ps_ip;
846
0
                    ih264d_ctl_get_sei_mdcv_params_op_t *ps_op;
847
848
0
                    ps_ip = (ih264d_ctl_get_sei_mdcv_params_ip_t *)pv_api_ip;
849
0
                    ps_op = (ih264d_ctl_get_sei_mdcv_params_op_t *)pv_api_op;
850
851
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_mdcv_params_ip_t))
852
0
                    {
853
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
854
0
                        ps_op->u4_error_code |=
855
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
856
0
                        return IV_FAIL;
857
0
                    }
858
859
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_mdcv_params_op_t))
860
0
                    {
861
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
862
0
                        ps_op->u4_error_code |=
863
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
864
0
                        return IV_FAIL;
865
0
                    }
866
867
0
                    break;
868
0
                }
869
870
0
                case IH264D_CMD_CTL_GET_SEI_CLL_PARAMS:
871
0
                {
872
0
                    ih264d_ctl_get_sei_cll_params_ip_t *ps_ip;
873
0
                    ih264d_ctl_get_sei_cll_params_op_t *ps_op;
874
875
0
                    ps_ip = (ih264d_ctl_get_sei_cll_params_ip_t *)pv_api_ip;
876
0
                    ps_op = (ih264d_ctl_get_sei_cll_params_op_t *)pv_api_op;
877
878
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_cll_params_ip_t))
879
0
                    {
880
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
881
0
                        ps_op->u4_error_code |=
882
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
883
0
                        return IV_FAIL;
884
0
                    }
885
886
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_cll_params_op_t))
887
0
                    {
888
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
889
0
                        ps_op->u4_error_code |=
890
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
891
0
                        return IV_FAIL;
892
0
                    }
893
894
0
                    break;
895
0
                }
896
897
0
                case IH264D_CMD_CTL_GET_SEI_AVE_PARAMS:
898
0
                {
899
0
                    ih264d_ctl_get_sei_ave_params_ip_t *ps_ip;
900
0
                    ih264d_ctl_get_sei_ave_params_op_t *ps_op;
901
902
0
                    ps_ip = (ih264d_ctl_get_sei_ave_params_ip_t *)pv_api_ip;
903
0
                    ps_op = (ih264d_ctl_get_sei_ave_params_op_t *)pv_api_op;
904
905
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_ave_params_ip_t))
906
0
                    {
907
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
908
0
                        ps_op->u4_error_code |=
909
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
910
0
                        return IV_FAIL;
911
0
                    }
912
913
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_ave_params_op_t))
914
0
                    {
915
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
916
0
                        ps_op->u4_error_code |=
917
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
918
0
                        return IV_FAIL;
919
0
                    }
920
921
0
                    break;
922
0
                }
923
924
0
                case IH264D_CMD_CTL_GET_SEI_CCV_PARAMS:
925
0
                {
926
0
                    ih264d_ctl_get_sei_ccv_params_ip_t *ps_ip;
927
0
                    ih264d_ctl_get_sei_ccv_params_op_t *ps_op;
928
929
0
                    ps_ip = (ih264d_ctl_get_sei_ccv_params_ip_t *)pv_api_ip;
930
0
                    ps_op = (ih264d_ctl_get_sei_ccv_params_op_t *)pv_api_op;
931
932
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_ccv_params_ip_t))
933
0
                    {
934
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
935
0
                        ps_op->u4_error_code |=
936
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
937
0
                        return IV_FAIL;
938
0
                    }
939
940
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_ccv_params_op_t))
941
0
                    {
942
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
943
0
                        ps_op->u4_error_code |=
944
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
945
0
                        return IV_FAIL;
946
0
                    }
947
948
0
                    break;
949
0
                }
950
951
0
                case IH264D_CMD_CTL_GET_SEI_SII_PARAMS:
952
0
                {
953
0
                    ih264d_ctl_get_sei_sii_params_ip_t *ps_ip;
954
0
                    ih264d_ctl_get_sei_sii_params_op_t *ps_op;
955
956
0
                    ps_ip = (ih264d_ctl_get_sei_sii_params_ip_t *) pv_api_ip;
957
0
                    ps_op = (ih264d_ctl_get_sei_sii_params_op_t *) pv_api_op;
958
959
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_sii_params_ip_t))
960
0
                    {
961
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
962
0
                        ps_op->u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
963
0
                        return IV_FAIL;
964
0
                    }
965
966
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_sii_params_op_t))
967
0
                    {
968
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
969
0
                        ps_op->u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
970
0
                        return IV_FAIL;
971
0
                    }
972
973
0
                    break;
974
0
                }
975
976
0
                case IH264D_CMD_CTL_GET_SEI_FGC_PARAMS:
977
0
                {
978
0
                    ih264d_ctl_get_sei_fgc_params_ip_t *ps_ip;
979
0
                    ih264d_ctl_get_sei_fgc_params_op_t *ps_op;
980
981
0
                    ps_ip = (ih264d_ctl_get_sei_fgc_params_ip_t *) pv_api_ip;
982
0
                    ps_op = (ih264d_ctl_get_sei_fgc_params_op_t *) pv_api_op;
983
984
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_fgc_params_ip_t))
985
0
                    {
986
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
987
0
                        ps_op->u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
988
0
                        return IV_FAIL;
989
0
                    }
990
991
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_fgc_params_op_t))
992
0
                    {
993
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
994
0
                        ps_op->u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
995
0
                        return IV_FAIL;
996
0
                    }
997
998
0
                    break;
999
0
                }
1000
1001
359
                case IH264D_CMD_CTL_SET_NUM_CORES:
1002
359
                {
1003
359
                    ih264d_ctl_set_num_cores_ip_t *ps_ip;
1004
359
                    ih264d_ctl_set_num_cores_op_t *ps_op;
1005
1006
359
                    ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
1007
359
                    ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
1008
1009
359
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t))
1010
0
                    {
1011
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1012
0
                        ps_op->u4_error_code |=
1013
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
1014
0
                        return IV_FAIL;
1015
0
                    }
1016
1017
359
                    if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t))
1018
0
                    {
1019
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1020
0
                        ps_op->u4_error_code |=
1021
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
1022
0
                        return IV_FAIL;
1023
0
                    }
1024
1025
359
                    if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2)
1026
144
                                    && (ps_ip->u4_num_cores != 3)
1027
84
                                    && (ps_ip->u4_num_cores != 4))
1028
0
                    {
1029
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1030
0
                        return IV_FAIL;
1031
0
                    }
1032
359
                    break;
1033
359
                }
1034
359
                case IH264D_CMD_CTL_SET_PROCESSOR:
1035
359
                {
1036
359
                    ih264d_ctl_set_processor_ip_t *ps_ip;
1037
359
                    ih264d_ctl_set_processor_op_t *ps_op;
1038
1039
359
                    ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1040
359
                    ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1041
1042
359
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t))
1043
0
                    {
1044
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1045
0
                        ps_op->u4_error_code |=
1046
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
1047
0
                        return IV_FAIL;
1048
0
                    }
1049
1050
359
                    if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t))
1051
0
                    {
1052
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1053
0
                        ps_op->u4_error_code |=
1054
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
1055
0
                        return IV_FAIL;
1056
0
                    }
1057
1058
359
                    break;
1059
359
                }
1060
359
                default:
1061
0
                    *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
1062
0
                    *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
1063
0
                    return IV_FAIL;
1064
0
                    break;
1065
2.87k
            }
1066
2.87k
        }
1067
2.87k
            break;
1068
19.7k
    }
1069
1070
19.7k
    return IV_SUCCESS;
1071
19.7k
}
1072
1073
1074
/**
1075
 *******************************************************************************
1076
 *
1077
 * @brief
1078
 *  Sets Processor type
1079
 *
1080
 * @par Description:
1081
 *  Sets Processor type
1082
 *
1083
 * @param[in] ps_codec_obj
1084
 *  Pointer to codec object at API level
1085
 *
1086
 * @param[in] pv_api_ip
1087
 *  Pointer to input argument structure
1088
 *
1089
 * @param[out] pv_api_op
1090
 *  Pointer to output argument structure
1091
 *
1092
 * @returns  Status
1093
 *
1094
 * @remarks
1095
 *
1096
 *
1097
 *******************************************************************************
1098
 */
1099
1100
WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1101
359
{
1102
359
    ih264d_ctl_set_processor_ip_t *ps_ip;
1103
359
    ih264d_ctl_set_processor_op_t *ps_op;
1104
359
    dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1105
1106
359
    ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1107
359
    ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1108
1109
359
    ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
1110
359
    ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
1111
1112
359
    ih264d_init_function_ptr(ps_codec);
1113
1114
359
    ps_op->u4_error_code = 0;
1115
359
    return IV_SUCCESS;
1116
359
}
1117
1118
1119
/**************************************************************************
1120
 * \if Function name : ih264d_init_decoder \endif
1121
 *
1122
 *
1123
 * \brief
1124
 *    Initializes the decoder
1125
 *
1126
 * \param apiVersion               : Version of the api being used.
1127
 * \param errorHandlingMechanism   : Mechanism to be used for errror handling.
1128
 * \param postFilteringType: Type of post filtering operation to be used.
1129
 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0].
1130
 * \param uc_dispBufs: Number of Display Buffers.
1131
 * \param p_NALBufAPI: Pointer to NAL Buffer API.
1132
 * \param p_DispBufAPI: Pointer to Display Buffer API.
1133
 * \param ih264d_dec_mem_manager  :Pointer to the function that will be called by decoder
1134
 *                        for memory allocation and freeing.
1135
 *
1136
 * \return
1137
 *    0 on Success and -1 on error
1138
 *
1139
 **************************************************************************
1140
 */
1141
void ih264d_init_decoder(void * ps_dec_params)
1142
2.28k
{
1143
2.28k
    dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params;
1144
2.28k
    dec_slice_params_t *ps_cur_slice;
1145
2.28k
    pocstruct_t *ps_prev_poc, *ps_cur_poc;
1146
2.28k
    WORD32 size;
1147
1148
2.28k
    size = sizeof(pred_info_t) * 2 * 32;
1149
2.28k
    memset(ps_dec->ps_pred, 0 , size);
1150
1151
2.28k
    size = sizeof(disp_mgr_t);
1152
2.28k
    memset(ps_dec->pv_disp_buf_mgr, 0 , size);
1153
1154
2.28k
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1155
2.28k
    memset(ps_dec->pv_pic_buf_mgr, 0, size);
1156
1157
2.28k
    size = sizeof(dec_err_status_t);
1158
2.28k
    memset(ps_dec->ps_dec_err_status, 0, size);
1159
1160
2.28k
    size = sizeof(sei);
1161
2.28k
    memset(ps_dec->ps_sei, 0, size);
1162
1163
2.28k
    size = sizeof(sei);
1164
2.28k
    memset(ps_dec->ps_sei_parse, 0, size);
1165
1166
2.28k
    size = sizeof(dpb_commands_t);
1167
2.28k
    memset(ps_dec->ps_dpb_cmds, 0, size);
1168
1169
2.28k
    size = sizeof(dec_bit_stream_t);
1170
2.28k
    memset(ps_dec->ps_bitstrm, 0, size);
1171
1172
2.28k
    size = sizeof(dec_slice_params_t);
1173
2.28k
    memset(ps_dec->ps_cur_slice, 0, size);
1174
1175
2.28k
    size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1176
2.28k
    memset(ps_dec->pv_scratch_sps_pps, 0, size);
1177
1178
2.28k
    size = sizeof(ctxt_inc_mb_info_t);
1179
2.28k
    memset(ps_dec->ps_left_mb_ctxt_info, 0, size);
1180
1181
2.28k
    size = (sizeof(neighbouradd_t) << 2);
1182
2.28k
    memset(ps_dec->ps_left_mvpred_addr, 0 ,size);
1183
1184
2.28k
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1185
2.28k
    memset(ps_dec->pv_mv_buf_mgr, 0, size);
1186
1187
    /* Free any dynamic buffers that are allocated */
1188
2.28k
    ih264d_free_dynamic_bufs(ps_dec);
1189
1190
2.28k
    {
1191
2.28k
        UWORD8 i;
1192
2.28k
        struct pic_buffer_t *ps_init_dpb;
1193
2.28k
        ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0];
1194
148k
        for(i = 0; i < 2 * MAX_REF_BUFS; i++)
1195
145k
        {
1196
145k
            ps_init_dpb->pu1_buf1 = NULL;
1197
145k
            ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1198
145k
            ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb;
1199
145k
            ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb;
1200
145k
            ps_init_dpb++;
1201
145k
        }
1202
1203
2.28k
        ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0];
1204
148k
        for(i = 0; i < 2 * MAX_REF_BUFS; i++)
1205
145k
        {
1206
145k
            ps_init_dpb->pu1_buf1 = NULL;
1207
145k
            ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1208
145k
            ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb;
1209
145k
            ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb;
1210
145k
            ps_init_dpb++;
1211
145k
        }
1212
2.28k
    }
1213
1214
2.28k
    ps_cur_slice = ps_dec->ps_cur_slice;
1215
2.28k
    ps_dec->init_done = 0;
1216
1217
2.28k
    ps_dec->u4_num_cores = 1;
1218
1219
2.28k
    ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0;
1220
1221
2.28k
    ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
1222
2.28k
    ps_dec->u4_app_disable_deblk_frm = 0;
1223
2.28k
    ps_dec->i4_degrade_type = 0;
1224
2.28k
    ps_dec->i4_degrade_pics = 0;
1225
1226
2.28k
    memset(ps_dec->ps_pps, 0,
1227
2.28k
           ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
1228
2.28k
    memset(ps_dec->ps_sps, 0,
1229
2.28k
           ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
1230
1231
    /* Initialization of function pointers ih264d_deblock_picture function*/
1232
1233
2.28k
    ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
1234
2.28k
    ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
1235
1236
2.28k
    ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec;
1237
1238
2.28k
    ps_dec->u4_num_fld_in_frm = 0;
1239
1240
2.28k
    ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1241
1242
    /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/
1243
2.28k
    ps_dec->ps_sei->u1_is_valid = 0;
1244
1245
    /* decParams Initializations */
1246
2.28k
    ps_dec->ps_cur_pps = NULL;
1247
2.28k
    ps_dec->ps_cur_sps = NULL;
1248
2.28k
    ps_dec->u1_init_dec_flag = 0;
1249
2.28k
    ps_dec->u1_first_slice_in_stream = 1;
1250
2.28k
    ps_dec->u1_last_pic_not_decoded = 0;
1251
2.28k
    ps_dec->u4_app_disp_width = 0;
1252
2.28k
    ps_dec->i4_header_decoded = 0;
1253
2.28k
    ps_dec->u4_total_frames_decoded = 0;
1254
1255
2.28k
    ps_dec->i4_error_code = 0;
1256
2.28k
    ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1257
2.28k
    ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0;
1258
1259
2.28k
    ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS;
1260
2.28k
    ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
1261
2.28k
    ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
1262
2.28k
    ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
1263
2.28k
    ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
1264
1265
2.28k
    ps_dec->u1_pr_sl_type = 0xFF;
1266
2.28k
    ps_dec->u2_mbx = 0xffff;
1267
2.28k
    ps_dec->u2_mby = 0;
1268
2.28k
    ps_dec->u4_total_mbs_coded = 0;
1269
1270
    /* POC initializations */
1271
2.28k
    ps_prev_poc = &ps_dec->s_prev_pic_poc;
1272
2.28k
    ps_cur_poc = &ps_dec->s_cur_pic_poc;
1273
2.28k
    ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
1274
2.28k
    ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
1275
2.28k
    ps_prev_poc->i4_delta_pic_order_cnt_bottom =
1276
2.28k
                    ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
1277
2.28k
    ps_prev_poc->i4_delta_pic_order_cnt[0] =
1278
2.28k
                    ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
1279
2.28k
    ps_prev_poc->i4_delta_pic_order_cnt[1] =
1280
2.28k
                    ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
1281
2.28k
    ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1282
2.28k
    ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count =
1283
2.28k
                    0;
1284
2.28k
    ps_prev_poc->i4_bottom_field_order_count =
1285
2.28k
                    ps_cur_poc->i4_bottom_field_order_count = 0;
1286
2.28k
    ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
1287
2.28k
    ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1288
2.28k
    ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
1289
2.28k
    ps_cur_slice->u1_mmco_equalto5 = 0;
1290
2.28k
    ps_cur_slice->u2_frame_num = 0;
1291
1292
2.28k
    ps_dec->i4_max_poc = 0;
1293
2.28k
    ps_dec->i4_prev_max_display_seq = 0;
1294
2.28k
    ps_dec->u4_recon_mb_grp = 4;
1295
2.28k
    ps_dec->i4_reorder_depth = -1;
1296
1297
    /* Field PIC initializations */
1298
2.28k
    ps_dec->u1_second_field = 0;
1299
2.28k
    ps_dec->s_prev_seq_params.u1_eoseq_pending = 0;
1300
1301
    /* Set the cropping parameters as zero */
1302
2.28k
    ps_dec->u2_crop_offset_y = 0;
1303
2.28k
    ps_dec->u2_crop_offset_uv = 0;
1304
1305
    /* The Initial Frame Rate Info is not Present */
1306
2.28k
    ps_dec->i4_vui_frame_rate = -1;
1307
2.28k
    ps_dec->i4_pic_type = NA_SLICE;
1308
2.28k
    ps_dec->i4_frametype = IV_NA_FRAME;
1309
2.28k
    ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1310
1311
2.28k
    ps_dec->u1_res_changed = 0;
1312
1313
1314
2.28k
    ps_dec->u1_frame_decoded_flag = 0;
1315
1316
    /* Set the default frame seek mask mode */
1317
2.28k
    ps_dec->u4_skip_frm_mask = SKIP_NONE;
1318
1319
    /********************************************************/
1320
    /* Initialize CAVLC residual decoding function pointers */
1321
    /********************************************************/
1322
2.28k
    ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
1323
2.28k
    ps_dec->pf_cavlc_4x4res_block[1] =
1324
2.28k
                    ih264d_cavlc_4x4res_block_totalcoeff_2to10;
1325
2.28k
    ps_dec->pf_cavlc_4x4res_block[2] =
1326
2.28k
                    ih264d_cavlc_4x4res_block_totalcoeff_11to16;
1327
1328
2.28k
    ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
1329
2.28k
    ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
1330
1331
2.28k
    ps_dec->pf_cavlc_parse_8x8block[0] =
1332
2.28k
                    ih264d_cavlc_parse_8x8block_none_available;
1333
2.28k
    ps_dec->pf_cavlc_parse_8x8block[1] =
1334
2.28k
                    ih264d_cavlc_parse_8x8block_left_available;
1335
2.28k
    ps_dec->pf_cavlc_parse_8x8block[2] =
1336
2.28k
                    ih264d_cavlc_parse_8x8block_top_available;
1337
2.28k
    ps_dec->pf_cavlc_parse_8x8block[3] =
1338
2.28k
                    ih264d_cavlc_parse_8x8block_both_available;
1339
1340
    /***************************************************************************/
1341
    /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */
1342
    /***************************************************************************/
1343
2.28k
    ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
1344
2.28k
    ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
1345
1346
2.28k
    ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
1347
2.28k
    ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
1348
1349
2.28k
    ps_dec->pf_fill_bs_xtra_left_edge[0] =
1350
2.28k
                    ih264d_fill_bs_xtra_left_edge_cur_frm;
1351
2.28k
    ps_dec->pf_fill_bs_xtra_left_edge[1] =
1352
2.28k
                    ih264d_fill_bs_xtra_left_edge_cur_fld;
1353
1354
    /* Initialize Reference Pic Buffers */
1355
2.28k
    ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr);
1356
1357
2.28k
    ps_dec->u2_prv_frame_num = 0;
1358
2.28k
    ps_dec->u1_top_bottom_decoded = 0;
1359
2.28k
    ps_dec->u1_dangling_field = 0;
1360
1361
2.28k
    ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
1362
1363
2.28k
    ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0];
1364
2.28k
    ps_dec->pi1_left_ref_idx_ctxt_inc =
1365
2.28k
                    &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0];
1366
2.28k
    ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb;
1367
1368
    /* ! */
1369
    /* Initializing flush frame u4_flag */
1370
2.28k
    ps_dec->u1_flushfrm = 0;
1371
1372
2.28k
    {
1373
2.28k
        ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec;
1374
2.28k
        ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec;
1375
2.28k
        ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec;
1376
2.28k
        ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec;
1377
2.28k
    }
1378
1379
2.28k
    memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
1380
2.28k
    memset(ps_dec->u4_disp_buf_mapping, 0,
1381
2.28k
           (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1382
2.28k
    memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1383
2.28k
           (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1384
2.28k
    memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t));
1385
1386
2.28k
    ih264d_init_arch(ps_dec);
1387
2.28k
    ih264d_init_function_ptr(ps_dec);
1388
2.28k
    ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
1389
2.28k
    ps_dec->init_done = 1;
1390
1391
2.28k
}
1392
1393
WORD32 ih264d_join_threads(dec_struct_t *ps_dec)
1394
1.79k
{
1395
1.79k
    if(ps_dec->i4_threads_active)
1396
1.79k
    {
1397
        /* Wait for threads */
1398
1.79k
        ps_dec->i4_break_threads = 1;
1399
1.79k
        if(ps_dec->u4_dec_thread_created)
1400
141
        {
1401
141
            ithread_mutex_lock(ps_dec->apv_proc_start_mutex[0]);
1402
1403
141
            ps_dec->ai4_process_start[0] = PROC_START;
1404
1405
141
            ithread_cond_signal(ps_dec->apv_proc_start_condition[0]);
1406
1407
141
            ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[0]);
1408
1409
141
            ithread_join(ps_dec->pv_dec_thread_handle, NULL);
1410
1411
141
            ps_dec->u4_dec_thread_created = 0;
1412
141
        }
1413
1414
1.79k
        if(ps_dec->u4_bs_deblk_thread_created)
1415
68
        {
1416
68
            ithread_mutex_lock(ps_dec->apv_proc_start_mutex[1]);
1417
1418
68
            ps_dec->ai4_process_start[1] = PROC_START;
1419
1420
68
            ithread_cond_signal(ps_dec->apv_proc_start_condition[1]);
1421
1422
68
            ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[1]);
1423
1424
68
            ithread_join(ps_dec->pv_bs_deblk_thread_handle, NULL);
1425
1426
68
            ps_dec->u4_bs_deblk_thread_created = 0;
1427
68
        }
1428
1.79k
    }
1429
1.79k
    return IV_SUCCESS;
1430
1.79k
}
1431
1432
WORD32 ih264d_free_static_bufs(iv_obj_t *dec_hdl)
1433
359
{
1434
359
    dec_struct_t *ps_dec;
1435
1436
359
    void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1437
359
    void *pv_mem_ctxt;
1438
1439
359
    ps_dec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1440
359
    pf_aligned_free = ps_dec->pf_aligned_free;
1441
359
    pv_mem_ctxt = ps_dec->pv_mem_ctxt;
1442
1443
359
    if(ps_dec->i4_threads_active)
1444
359
    {
1445
1446
359
        ih264d_join_threads(ps_dec);
1447
1448
        // destroy mutex and condition variable for both the threads
1449
        // 1. ih264d_decode_picture_thread
1450
        // 2. ih264d_recon_deblk_thread
1451
359
        {
1452
359
            UWORD32 i;
1453
1.07k
            for(i = 0; i < 2; i++)
1454
718
            {
1455
718
                ithread_cond_destroy(ps_dec->apv_proc_start_condition[i]);
1456
718
                ithread_cond_destroy(ps_dec->apv_proc_done_condition[i]);
1457
1458
718
                ithread_mutex_destroy(ps_dec->apv_proc_start_mutex[i]);
1459
718
                ithread_mutex_destroy(ps_dec->apv_proc_done_mutex[i]);
1460
718
            }
1461
359
        }
1462
359
        PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->apv_proc_start_mutex[0]);
1463
359
        PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->apv_proc_start_condition[0]);
1464
359
    }
1465
1466
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sps);
1467
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pps);
1468
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_dec_thread_handle);
1469
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_bs_deblk_thread_handle);
1470
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_mgr);
1471
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred);
1472
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_disp_buf_mgr);
1473
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_pic_buf_mgr);
1474
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pic_buf_base);
1475
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_err_status);
1476
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei);
1477
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei_parse);
1478
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_cmds);
1479
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_bitstrm);
1480
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_cur_slice);
1481
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_scratch_sps_pps);
1482
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_static);
1483
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ppv_map_ref_idx_to_poc_base);
1484
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_cabac_ctxt_table_t);
1485
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mb_ctxt_info);
1486
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_ref_buff_base);
1487
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_pred1);
1488
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_temp_mc_buffer);
1489
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_init_dpb_base);
1490
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_mbaff_wt_mat);
1491
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_wts_ofsts_mat);
1492
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mvpred_addr);
1493
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_mv_buf_mgr);
1494
359
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_col_mv_base);
1495
359
    PS_DEC_ALIGNED_FREE(ps_dec, dec_hdl->pv_codec_handle);
1496
1497
359
    if(dec_hdl)
1498
359
    {
1499
359
        pf_aligned_free(pv_mem_ctxt, dec_hdl);
1500
359
    }
1501
359
    return IV_SUCCESS;
1502
359
}
1503
/*****************************************************************************/
1504
/*                                                                           */
1505
/*  Function Name : ih264d_create                                              */
1506
/*                                                                           */
1507
/*  Description   : creates decoder                                          */
1508
/*                                                                           */
1509
/*  Inputs        :iv_obj_t decoder handle                                   */
1510
/*                :pv_api_ip pointer to input structure                      */
1511
/*                :pv_api_op pointer to output structure                     */
1512
/*  Outputs       :                                                          */
1513
/*  Returns       : void                                                     */
1514
/*                                                                           */
1515
/*  Issues        : none                                                     */
1516
/*                                                                           */
1517
/*  Revision History:                                                        */
1518
/*                                                                           */
1519
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1520
/*         22 10 2008    100356         Draft                                */
1521
/*                                                                           */
1522
/*****************************************************************************/
1523
WORD32 ih264d_allocate_static_bufs(iv_obj_t **dec_hdl, void *pv_api_ip, void *pv_api_op)
1524
359
{
1525
359
    ih264d_create_ip_t *ps_create_ip;
1526
359
    ih264d_create_op_t *ps_create_op;
1527
359
    void *pv_buf;
1528
359
    UWORD8 *pu1_buf;
1529
359
    dec_struct_t *ps_dec;
1530
359
    void *(*pf_aligned_alloc)(void *pv_mem_ctxt, WORD32 alignment, WORD32 size);
1531
359
    void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1532
359
    void *pv_mem_ctxt;
1533
359
    WORD32 size;
1534
1535
359
    ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1536
359
    ps_create_op = (ih264d_create_op_t *)pv_api_op;
1537
1538
359
    ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1539
1540
359
    pf_aligned_alloc = ps_create_ip->s_ivd_create_ip_t.pf_aligned_alloc;
1541
359
    pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1542
359
    pv_mem_ctxt  = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1543
1544
    /* Initialize return handle to NULL */
1545
359
    ps_create_op->s_ivd_create_op_t.pv_handle = NULL;
1546
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(iv_obj_t));
1547
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1548
359
    memset(pv_buf, 0, sizeof(iv_obj_t));
1549
359
    *dec_hdl = (iv_obj_t *)pv_buf;
1550
359
    ps_create_op->s_ivd_create_op_t.pv_handle = *dec_hdl;
1551
1552
359
    (*dec_hdl)->pv_codec_handle = NULL;
1553
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(dec_struct_t));
1554
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1555
359
    (*dec_hdl)->pv_codec_handle = (dec_struct_t *)pv_buf;
1556
359
    ps_dec = (dec_struct_t *)pv_buf;
1557
1558
359
    memset(ps_dec, 0, sizeof(dec_struct_t));
1559
1560
359
#ifndef LOGO_EN
1561
359
    ps_dec->u4_share_disp_buf = ps_create_ip->s_ivd_create_ip_t.u4_share_disp_buf;
1562
#else
1563
    ps_dec->u4_share_disp_buf = 0;
1564
#endif
1565
1566
359
    ps_dec->u1_chroma_format =
1567
359
                    (UWORD8)(ps_create_ip->s_ivd_create_ip_t.e_output_format);
1568
1569
359
    if((ps_dec->u1_chroma_format != IV_YUV_420P)
1570
261
                    && (ps_dec->u1_chroma_format
1571
261
                                    != IV_YUV_420SP_UV)
1572
228
                    && (ps_dec->u1_chroma_format
1573
228
                                    != IV_YUV_420SP_VU))
1574
130
    {
1575
130
        ps_dec->u4_share_disp_buf = 0;
1576
130
    }
1577
1578
359
    ps_dec->u1_enable_mb_info = ps_create_ip->u4_enable_frame_info;
1579
359
    ps_dec->pf_aligned_alloc = pf_aligned_alloc;
1580
359
    ps_dec->pf_aligned_free = pf_aligned_free;
1581
359
    ps_dec->pv_mem_ctxt = pv_mem_ctxt;
1582
359
    ps_dec->i4_threads_active = ps_create_ip->u4_keep_threads_active;
1583
1584
1585
359
    size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS);
1586
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1587
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1588
359
    memset(pv_buf, 0, size);
1589
359
    ps_dec->ps_sps = pv_buf;
1590
1591
359
    size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS;
1592
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1593
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1594
359
    memset(pv_buf, 0, size);
1595
359
    ps_dec->ps_pps = pv_buf;
1596
1597
359
    size = ithread_get_handle_size();
1598
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1599
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1600
359
    memset(pv_buf, 0, size);
1601
359
    ps_dec->pv_dec_thread_handle = pv_buf;
1602
1603
359
    size = ithread_get_handle_size();
1604
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1605
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1606
359
    memset(pv_buf, 0, size);
1607
359
    ps_dec->pv_bs_deblk_thread_handle = pv_buf;
1608
1609
359
    if(ps_dec->i4_threads_active)
1610
359
    {
1611
359
        UWORD32 i;
1612
        /* Request memory to hold mutex (start/done) for both threads */
1613
359
        size = ithread_get_mutex_lock_size() << 2;
1614
359
        pv_buf = pf_aligned_alloc(pv_mem_ctxt, 8, size);
1615
359
        RETURN_IF((NULL == pv_buf), IV_FAIL);
1616
359
        memset(pv_buf, 0, size);
1617
1618
        // init mutex variable for both the threads
1619
        // 1. ih264d_decode_picture_thread
1620
        // 2. ih264d_recon_deblk_thread
1621
1.07k
        for(i = 0; i < 2; i++)
1622
718
        {
1623
718
            WORD32 ret;
1624
718
            WORD32 mutex_size = ithread_get_mutex_lock_size();
1625
1626
718
            ps_dec->apv_proc_start_mutex[i] =
1627
718
                            (UWORD8 *)pv_buf + (2 * i * mutex_size);
1628
718
            ps_dec->apv_proc_done_mutex[i] =
1629
718
                            (UWORD8 *)pv_buf + ((2 * i + 1) * mutex_size);
1630
1631
718
            ret = ithread_mutex_init(ps_dec->apv_proc_start_mutex[i]);
1632
718
            RETURN_IF((ret != IV_SUCCESS), ret);
1633
1634
718
            ret = ithread_mutex_init(ps_dec->apv_proc_done_mutex[i]);
1635
718
            RETURN_IF((ret != IV_SUCCESS), ret);
1636
718
        }
1637
1638
359
        size = ithread_get_cond_struct_size() << 2;
1639
359
        pv_buf = pf_aligned_alloc(pv_mem_ctxt, 8, size);
1640
359
        RETURN_IF((NULL == pv_buf), IV_FAIL);
1641
359
        memset(pv_buf, 0, size);
1642
1643
        // init condition variable for both the threads
1644
1.07k
        for(i = 0; i < 2; i++)
1645
718
        {
1646
718
            WORD32 ret;
1647
718
            WORD32 cond_size = ithread_get_cond_struct_size();
1648
718
            ps_dec->apv_proc_start_condition[i] =
1649
718
                            (UWORD8 *)pv_buf + (2 * i * cond_size);
1650
718
            ps_dec->apv_proc_done_condition[i] =
1651
718
                            (UWORD8 *)pv_buf + ((2 * i + 1) * cond_size);
1652
1653
718
            ret = ithread_cond_init(ps_dec->apv_proc_start_condition[i]);
1654
718
            RETURN_IF((ret != IV_SUCCESS), ret);
1655
1656
718
            ret = ithread_cond_init(ps_dec->apv_proc_done_condition[i]);
1657
718
            RETURN_IF((ret != IV_SUCCESS), ret);
1658
718
        }
1659
359
    }
1660
1661
359
    size = sizeof(dpb_manager_t);
1662
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1663
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1664
359
    memset(pv_buf, 0, size);
1665
359
    ps_dec->ps_dpb_mgr = pv_buf;
1666
1667
359
    size = sizeof(pred_info_t) * 2 * 32;
1668
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1669
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1670
359
    memset(pv_buf, 0, size);
1671
359
    ps_dec->ps_pred = pv_buf;
1672
1673
359
    size = sizeof(disp_mgr_t);
1674
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1675
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1676
359
    memset(pv_buf, 0, size);
1677
359
    ps_dec->pv_disp_buf_mgr = pv_buf;
1678
1679
359
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1680
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1681
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1682
359
    memset(pv_buf, 0, size);
1683
359
    ps_dec->pv_pic_buf_mgr = pv_buf;
1684
1685
359
    size = sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2);
1686
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1687
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1688
359
    memset(pv_buf, 0, size);
1689
359
    ps_dec->ps_pic_buf_base = pv_buf;
1690
1691
359
    size = sizeof(dec_err_status_t);
1692
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1693
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1694
359
    memset(pv_buf, 0, size);
1695
359
    ps_dec->ps_dec_err_status = (dec_err_status_t *)pv_buf;
1696
1697
359
    size = sizeof(sei);
1698
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1699
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1700
359
    memset(pv_buf, 0, size);
1701
359
    ps_dec->ps_sei = (sei *)pv_buf;
1702
1703
359
    size = sizeof(sei);
1704
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1705
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1706
359
    memset(pv_buf, 0, size);
1707
359
    ps_dec->ps_sei_parse = (sei *)pv_buf;
1708
1709
359
    size = sizeof(dpb_commands_t);
1710
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1711
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1712
359
    memset(pv_buf, 0, size);
1713
359
    ps_dec->ps_dpb_cmds = (dpb_commands_t *)pv_buf;
1714
1715
359
    size = sizeof(dec_bit_stream_t);
1716
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1717
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1718
359
    memset(pv_buf, 0, size);
1719
359
    ps_dec->ps_bitstrm = (dec_bit_stream_t *)pv_buf;
1720
1721
359
    size = sizeof(dec_slice_params_t);
1722
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1723
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1724
359
    memset(pv_buf, 0, size);
1725
359
    ps_dec->ps_cur_slice = (dec_slice_params_t *)pv_buf;
1726
1727
359
    size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1728
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1729
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1730
359
    memset(pv_buf, 0, size);
1731
359
    ps_dec->pv_scratch_sps_pps = pv_buf;
1732
1733
1734
359
    ps_dec->u4_static_bits_buf_size = 256000;
1735
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, ps_dec->u4_static_bits_buf_size);
1736
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1737
359
    memset(pv_buf, 0, ps_dec->u4_static_bits_buf_size);
1738
359
    ps_dec->pu1_bits_buf_static = pv_buf;
1739
1740
1741
359
    size = ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC)
1742
359
                        * sizeof(void *));
1743
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1744
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1745
359
    ps_dec->ppv_map_ref_idx_to_poc_base = pv_buf;
1746
359
    memset(ps_dec->ppv_map_ref_idx_to_poc_base, 0, size);
1747
1748
359
    ps_dec->ppv_map_ref_idx_to_poc = ps_dec->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC;
1749
1750
1751
359
    size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
1752
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1753
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1754
359
    memset(pv_buf, 0, size);
1755
359
    ps_dec->p_cabac_ctxt_table_t = pv_buf;
1756
1757
1758
1759
359
    size = sizeof(ctxt_inc_mb_info_t);
1760
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1761
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1762
359
    memset(pv_buf, 0, size);
1763
359
    ps_dec->ps_left_mb_ctxt_info = pv_buf;
1764
1765
1766
1767
359
    size = MAX_REF_BUF_SIZE * 2;
1768
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1769
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1770
359
    memset(pv_buf, 0, size);
1771
359
    ps_dec->pu1_ref_buff_base = pv_buf;
1772
359
    ps_dec->pu1_ref_buff = ps_dec->pu1_ref_buff_base + MAX_REF_BUF_SIZE;
1773
1774
1775
359
    size = ((sizeof(WORD16)) * PRED_BUFFER_WIDTH
1776
359
                        * PRED_BUFFER_HEIGHT * 2);
1777
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1778
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1779
359
    memset(pv_buf, 0, size);
1780
359
    ps_dec->pi2_pred1 = pv_buf;
1781
1782
1783
359
    size = sizeof(UWORD8) * (MB_LUM_SIZE);
1784
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1785
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1786
359
    memset(pv_buf, 0, size);
1787
359
    ps_dec->pu1_temp_mc_buffer = pv_buf;
1788
1789
1790
1791
1792
359
    size = 8 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
1793
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1794
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1795
359
    memset(pv_buf, 0, size);
1796
1797
359
    ps_dec->pu1_init_dpb_base = pv_buf;
1798
359
    pu1_buf = pv_buf;
1799
359
    ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = (struct pic_buffer_t *)pu1_buf;
1800
1801
359
    pu1_buf += size / 2;
1802
359
    ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = (struct pic_buffer_t *)pu1_buf;
1803
1804
359
    size = (sizeof(UWORD32) * 2 * 3
1805
359
                        * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)) * 2);
1806
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1807
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1808
359
    memset(pv_buf, 0, size);
1809
359
    ps_dec->pu4_mbaff_wt_mat = pv_buf;
1810
1811
359
    size = sizeof(UWORD32) * 2 * 3
1812
359
                        * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1));
1813
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1814
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1815
359
    memset(pv_buf, 0, size);
1816
359
    ps_dec->pu4_wts_ofsts_mat = pv_buf;
1817
1818
1819
359
    size = (sizeof(neighbouradd_t) << 2);
1820
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1821
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1822
359
    memset(pv_buf, 0, size);
1823
359
    ps_dec->ps_left_mvpred_addr = pv_buf;
1824
1825
1826
359
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1827
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1828
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1829
359
    memset(pv_buf, 0, size);
1830
359
    ps_dec->pv_mv_buf_mgr = pv_buf;
1831
1832
1833
359
    size =  sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2);
1834
359
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1835
359
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1836
359
    ps_dec->ps_col_mv_base = pv_buf;
1837
359
    memset(ps_dec->ps_col_mv_base, 0, size);
1838
1839
359
    ih264d_init_decoder(ps_dec);
1840
1841
359
    return IV_SUCCESS;
1842
359
}
1843
1844
1845
/*****************************************************************************/
1846
/*                                                                           */
1847
/*  Function Name : ih264d_create                                              */
1848
/*                                                                           */
1849
/*  Description   : creates decoder                                          */
1850
/*                                                                           */
1851
/*  Inputs        :iv_obj_t decoder handle                                   */
1852
/*                :pv_api_ip pointer to input structure                      */
1853
/*                :pv_api_op pointer to output structure                     */
1854
/*  Outputs       :                                                          */
1855
/*  Returns       : void                                                     */
1856
/*                                                                           */
1857
/*  Issues        : none                                                     */
1858
/*                                                                           */
1859
/*  Revision History:                                                        */
1860
/*                                                                           */
1861
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1862
/*         22 10 2008    100356         Draft                                */
1863
/*                                                                           */
1864
/*****************************************************************************/
1865
WORD32 ih264d_create(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1866
359
{
1867
359
    ih264d_create_ip_t *ps_create_ip;
1868
359
    ih264d_create_op_t *ps_create_op;
1869
1870
359
    WORD32 ret;
1871
1872
359
    ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1873
359
    ps_create_op = (ih264d_create_op_t *)pv_api_op;
1874
1875
359
    ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1876
359
    dec_hdl = NULL;
1877
359
    ret = ih264d_allocate_static_bufs(&dec_hdl, pv_api_ip, pv_api_op);
1878
1879
    /* If allocation of some buffer fails, then free buffers allocated till then */
1880
359
    if(IV_FAIL == ret)
1881
0
    {
1882
0
        if(dec_hdl)
1883
0
        {
1884
0
            if(dec_hdl->pv_codec_handle)
1885
0
            {
1886
0
                ih264d_free_static_bufs(dec_hdl);
1887
0
            }
1888
0
            else
1889
0
            {
1890
0
                void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1891
0
                void *pv_mem_ctxt;
1892
1893
0
                pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1894
0
                pv_mem_ctxt  = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1895
0
                pf_aligned_free(pv_mem_ctxt, dec_hdl);
1896
0
            }
1897
0
        }
1898
0
        ps_create_op->s_ivd_create_op_t.u4_error_code = IVD_MEM_ALLOC_FAILED;
1899
0
        ps_create_op->s_ivd_create_op_t.u4_error_code |= 1 << IVD_FATALERROR;
1900
1901
0
        return IV_FAIL;
1902
0
    }
1903
1904
359
    return IV_SUCCESS;
1905
359
}
1906
1907
/*****************************************************************************/
1908
/*                                                                           */
1909
/*  Function Name :  ih264d_map_error                                        */
1910
/*                                                                           */
1911
/*  Description   :  Maps error codes to IVD error groups                    */
1912
/*                                                                           */
1913
/*  Inputs        :                                                          */
1914
/*  Globals       : <Does it use any global variables?>                      */
1915
/*  Outputs       :                                                          */
1916
/*  Returns       : void                                                     */
1917
/*                                                                           */
1918
/*  Issues        : none                                                     */
1919
/*                                                                           */
1920
/*  Revision History:                                                        */
1921
/*                                                                           */
1922
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1923
/*         22 10 2008    100356         Draft                                */
1924
/*                                                                           */
1925
/*****************************************************************************/
1926
UWORD32 ih264d_map_error(UWORD32 i4_err_status)
1927
142k
{
1928
142k
    UWORD32 temp = 0;
1929
1930
142k
    switch(i4_err_status)
1931
142k
    {
1932
0
        case ERROR_MEM_ALLOC_ISRAM_T:
1933
0
        case ERROR_MEM_ALLOC_SDRAM_T:
1934
0
        case ERROR_BUF_MGR:
1935
0
        case ERROR_MB_GROUP_ASSGN_T:
1936
0
        case ERROR_FRAME_LIMIT_OVER:
1937
0
        case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT:
1938
0
        case ERROR_PROFILE_NOT_SUPPORTED:
1939
0
        case ERROR_INIT_NOT_DONE:
1940
0
        case IVD_MEM_ALLOC_FAILED:
1941
666
        case ERROR_FEATURE_UNAVAIL:
1942
1.27k
        case IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED:
1943
1.27k
            temp = 1 << IVD_FATALERROR;
1944
1.27k
            H264_DEC_DEBUG_PRINT("\nFatal Error\n");
1945
1.27k
            break;
1946
1947
4.22k
        case ERROR_DBP_MANAGER_T:
1948
4.22k
        case ERROR_GAPS_IN_FRM_NUM:
1949
4.22k
        case ERROR_UNKNOWN_NAL:
1950
4.22k
        case ERROR_INV_MB_SLC_GRP_T:
1951
4.22k
        case ERROR_MULTIPLE_SLC_GRP_T:
1952
4.22k
        case ERROR_UNKNOWN_LEVEL:
1953
4.50k
        case ERROR_UNAVAIL_PICBUF_T:
1954
4.68k
        case ERROR_UNAVAIL_MVBUF_T:
1955
4.68k
        case ERROR_UNAVAIL_DISPBUF_T:
1956
4.88k
        case ERROR_NUM_REF:
1957
4.88k
        case ERROR_REFIDX_ORDER_T:
1958
4.88k
        case ERROR_PIC0_NOT_FOUND_T:
1959
4.96k
        case ERROR_MB_TYPE:
1960
4.98k
        case ERROR_SUB_MB_TYPE:
1961
5.07k
        case ERROR_CBP:
1962
5.52k
        case ERROR_REF_IDX:
1963
5.52k
        case ERROR_NUM_MV:
1964
5.73k
        case ERROR_CHROMA_PRED_MODE:
1965
5.73k
        case ERROR_INTRAPRED:
1966
5.73k
        case ERROR_NEXT_MB_ADDRESS_T:
1967
5.73k
        case ERROR_MB_ADDRESS_T:
1968
5.73k
        case ERROR_PIC1_NOT_FOUND_T:
1969
6.06k
        case ERROR_CAVLC_NUM_COEFF_T:
1970
6.06k
        case ERROR_CAVLC_SCAN_POS_T:
1971
6.17k
        case ERROR_PRED_WEIGHT_TABLE_T:
1972
8.35k
        case ERROR_CORRUPTED_SLICE:
1973
8.35k
            temp = 1 << IVD_CORRUPTEDDATA;
1974
8.35k
            break;
1975
1976
0
        case ERROR_NOT_SUPP_RESOLUTION:
1977
0
        case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT:
1978
0
            temp = 1 << IVD_UNSUPPORTEDINPUT;
1979
0
            break;
1980
1981
0
        case ERROR_INVALID_PIC_PARAM:
1982
4
        case ERROR_INVALID_SEQ_PARAM:
1983
4
        case ERROR_EGC_EXCEED_32_1_T:
1984
4
        case ERROR_EGC_EXCEED_32_2_T:
1985
4
        case ERROR_INV_RANGE_TEV_T:
1986
390
        case ERROR_INV_SLC_TYPE_T:
1987
420
        case ERROR_INV_POC_TYPE_T:
1988
3.15k
        case ERROR_INV_RANGE_QP_T:
1989
7.29k
        case ERROR_INV_SPS_PPS_T:
1990
8.87k
        case ERROR_INV_SLICE_HDR_T:
1991
12.1k
        case ERROR_INV_SEI_MDCV_PARAMS:
1992
12.1k
        case ERROR_INV_SEI_CLL_PARAMS:
1993
12.2k
        case ERROR_INV_SEI_AVE_PARAMS:
1994
25.4k
        case ERROR_INV_SEI_CCV_PARAMS:
1995
25.4k
        case ERROR_INV_SEI_SII_PARAMS:
1996
1997
25.4k
            temp = 1 << IVD_CORRUPTEDHEADER;
1998
25.4k
            break;
1999
2000
270
        case ERROR_EOB_FLUSHBITS_T:
2001
6.07k
        case ERROR_EOB_GETBITS_T:
2002
6.07k
        case ERROR_EOB_GETBIT_T:
2003
6.07k
        case ERROR_EOB_BYPASS_T:
2004
6.07k
        case ERROR_EOB_DECISION_T:
2005
8.18k
        case ERROR_EOB_TERMINATE_T:
2006
8.18k
        case ERROR_EOB_READCOEFF4X4CAB_T:
2007
8.18k
            temp = 1 << IVD_INSUFFICIENTDATA;
2008
8.18k
            break;
2009
0
        case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED:
2010
0
        case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH:
2011
0
            temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR;
2012
0
            break;
2013
2014
470
        case ERROR_DANGLING_FIELD_IN_PIC:
2015
470
            temp = 1 << IVD_APPLIEDCONCEALMENT;
2016
470
            break;
2017
2018
142k
    }
2019
2020
142k
    return temp;
2021
2022
142k
}
2023
2024
UWORD32 ih264d_get_outbuf_size(WORD32 pic_wd,
2025
                               UWORD32 pic_ht,
2026
                               UWORD8 u1_chroma_format,
2027
                               UWORD32 *p_buf_size)
2028
149k
{
2029
149k
    UWORD32 u4_min_num_out_bufs = 0;
2030
2031
149k
    if(u1_chroma_format == IV_YUV_420P)
2032
76.8k
        u4_min_num_out_bufs = MIN_OUT_BUFS_420;
2033
73.1k
    else if(u1_chroma_format == IV_YUV_422ILE)
2034
2.30k
        u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
2035
70.8k
    else if(u1_chroma_format == IV_RGB_565)
2036
754
        u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
2037
70.1k
    else if((u1_chroma_format == IV_YUV_420SP_UV)
2038
31.0k
                    || (u1_chroma_format == IV_YUV_420SP_VU))
2039
70.1k
        u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
2040
2041
149k
    if(u1_chroma_format == IV_YUV_420P)
2042
76.8k
    {
2043
76.8k
        p_buf_size[0] = (pic_wd * pic_ht);
2044
76.8k
        p_buf_size[1] = (pic_wd * pic_ht) >> 2;
2045
76.8k
        p_buf_size[2] = (pic_wd * pic_ht) >> 2;
2046
76.8k
    }
2047
73.1k
    else if(u1_chroma_format == IV_YUV_422ILE)
2048
2.30k
    {
2049
2.30k
        p_buf_size[0] = (pic_wd * pic_ht) * 2;
2050
2.30k
        p_buf_size[1] = p_buf_size[2] = 0;
2051
2.30k
    }
2052
70.8k
    else if(u1_chroma_format == IV_RGB_565)
2053
754
    {
2054
754
        p_buf_size[0] = (pic_wd * pic_ht) * 2;
2055
754
        p_buf_size[1] = p_buf_size[2] = 0;
2056
754
    }
2057
70.1k
    else if((u1_chroma_format == IV_YUV_420SP_UV)
2058
31.0k
                    || (u1_chroma_format == IV_YUV_420SP_VU))
2059
70.1k
    {
2060
70.1k
        p_buf_size[0] = (pic_wd * pic_ht);
2061
70.1k
        p_buf_size[1] = (pic_wd * pic_ht) >> 1;
2062
70.1k
        p_buf_size[2] = 0;
2063
70.1k
    }
2064
2065
149k
    return u4_min_num_out_bufs;
2066
149k
}
2067
2068
WORD32 check_app_out_buf_size(dec_struct_t *ps_dec)
2069
146k
{
2070
146k
    UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
2071
146k
    UWORD32 u4_min_num_out_bufs, i;
2072
146k
    UWORD32 pic_wd, pic_ht;
2073
2074
146k
    if(0 == ps_dec->u4_share_disp_buf)
2075
146k
    {
2076
146k
        pic_wd = ps_dec->u2_disp_width;
2077
146k
        pic_ht = ps_dec->u2_disp_height;
2078
2079
146k
    }
2080
0
    else
2081
0
    {
2082
0
        pic_wd = ps_dec->u2_frm_wd_y;
2083
0
        pic_ht = ps_dec->u2_frm_ht_y;
2084
0
    }
2085
2086
146k
    if(ps_dec->u4_app_disp_width > pic_wd)
2087
0
        pic_wd = ps_dec->u4_app_disp_width;
2088
2089
146k
    u4_min_num_out_bufs = ih264d_get_outbuf_size(pic_wd, pic_ht,
2090
146k
                                                 ps_dec->u1_chroma_format,
2091
146k
                                                 &au4_min_out_buf_size[0]);
2092
2093
2094
146k
    if(0 == ps_dec->u4_share_disp_buf)
2095
146k
    {
2096
146k
        if(ps_dec->ps_out_buffer->u4_num_bufs < u4_min_num_out_bufs)
2097
0
            return IV_FAIL;
2098
2099
505k
        for(i = 0; i < u4_min_num_out_bufs; i++)
2100
360k
        {
2101
360k
            if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i]
2102
360k
                            < au4_min_out_buf_size[i])
2103
1.36k
                return (IV_FAIL);
2104
360k
        }
2105
146k
    }
2106
0
    else
2107
0
    {
2108
0
        if(ps_dec->disp_bufs[0].u4_num_bufs < u4_min_num_out_bufs)
2109
0
            return IV_FAIL;
2110
2111
0
        for(i = 0; i < u4_min_num_out_bufs; i++)
2112
0
        {
2113
            /* We need to check only with the disp_buffer[0], because we have
2114
             * already ensured that all the buffers are of the same size in
2115
             * ih264d_set_display_frame.
2116
             */
2117
0
            if(ps_dec->disp_bufs[0].u4_bufsize[i] < au4_min_out_buf_size[i])
2118
0
                return (IV_FAIL);
2119
0
        }
2120
2121
0
    }
2122
2123
145k
    return (IV_SUCCESS);
2124
146k
}
2125
2126
2127
/*****************************************************************************/
2128
/*                                                                           */
2129
/*  Function Name :  ih264d_video_decode                                     */
2130
/*                                                                           */
2131
/*  Description   :  handle video decode API command                         */
2132
/*                                                                           */
2133
/*  Inputs        :iv_obj_t decoder handle                                   */
2134
/*                :pv_api_ip pointer to input structure                      */
2135
/*                :pv_api_op pointer to output structure                     */
2136
/*  Outputs       :                                                          */
2137
/*  Returns       : void                                                     */
2138
/*                                                                           */
2139
/*  Issues        : none                                                     */
2140
/*                                                                           */
2141
/*  Revision History:                                                        */
2142
/*                                                                           */
2143
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
2144
/*         22 10 2008    100356         Draft                                */
2145
/*                                                                           */
2146
/*****************************************************************************/
2147
2148
WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2149
16.1k
{
2150
    /* ! */
2151
2152
16.1k
    dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2153
2154
16.1k
    WORD32 i4_err_status = 0;
2155
16.1k
    UWORD8 *pu1_buf = NULL;
2156
16.1k
    WORD32 buflen;
2157
16.1k
    UWORD32 u4_max_ofst, u4_length_of_start_code = 0;
2158
2159
16.1k
    UWORD32 bytes_consumed = 0;
2160
16.1k
    UWORD32 cur_slice_is_nonref = 0;
2161
16.1k
    UWORD32 u4_next_is_aud;
2162
16.1k
    UWORD32 u4_first_start_code_found = 0;
2163
16.1k
    WORD32 ret = 0,api_ret_value = IV_SUCCESS;
2164
16.1k
    WORD32 header_data_left = 0,frame_data_left = 0;
2165
16.1k
    UWORD8 *pu1_bitstrm_buf;
2166
16.1k
    ih264d_video_decode_ip_t *ps_h264d_dec_ip;
2167
16.1k
    ih264d_video_decode_op_t *ps_h264d_dec_op;
2168
16.1k
    ivd_video_decode_ip_t *ps_dec_ip;
2169
16.1k
    ivd_video_decode_op_t *ps_dec_op;
2170
2171
16.1k
    ithread_set_name((void*)"Parse_thread");
2172
2173
16.1k
    ps_h264d_dec_ip = (ih264d_video_decode_ip_t *)pv_api_ip;
2174
16.1k
    ps_h264d_dec_op = (ih264d_video_decode_op_t *)pv_api_op;
2175
16.1k
    ps_dec_ip = &ps_h264d_dec_ip->s_ivd_video_decode_ip_t;
2176
16.1k
    ps_dec_op = &ps_h264d_dec_op->s_ivd_video_decode_op_t;
2177
2178
16.1k
    {
2179
16.1k
        UWORD32 u4_size;
2180
16.1k
        u4_size = ps_dec_op->u4_size;
2181
16.1k
        memset(ps_h264d_dec_op, 0, ps_dec_op->u4_size);
2182
16.1k
        ps_dec_op->u4_size = u4_size;
2183
16.1k
    }
2184
2185
16.1k
    ps_dec->pv_dec_out = ps_dec_op;
2186
16.1k
    if(ps_dec->init_done != 1)
2187
0
    {
2188
0
        return IV_FAIL;
2189
0
    }
2190
2191
    /*Data memory barries instruction,so that bitstream write by the application is complete*/
2192
16.1k
    DATA_SYNC();
2193
2194
16.1k
    if(0 == ps_dec->u1_flushfrm)
2195
16.1k
    {
2196
16.1k
        if(ps_dec_ip->pv_stream_buffer == NULL)
2197
0
        {
2198
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2199
0
            ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
2200
0
            return IV_FAIL;
2201
0
        }
2202
16.1k
        if(ps_dec_ip->u4_num_Bytes <= 0)
2203
0
        {
2204
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2205
0
            ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV;
2206
0
            return IV_FAIL;
2207
2208
0
        }
2209
16.1k
    }
2210
16.1k
    ps_dec->u1_pic_decode_done = 0;
2211
2212
16.1k
    if(ps_dec->i4_threads_active)
2213
16.1k
    {
2214
16.1k
        UWORD32 i;
2215
16.1k
        ps_dec->i4_break_threads = 0;
2216
48.5k
        for (i = 0; i < 2; i++)
2217
32.3k
        {
2218
32.3k
            ret = ithread_mutex_lock(ps_dec->apv_proc_start_mutex[i]);
2219
32.3k
            RETURN_IF((ret != IV_SUCCESS), ret);
2220
2221
32.3k
            ps_dec->ai4_process_start[i] = PROC_INIT;
2222
2223
32.3k
            ret = ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[i]);
2224
32.3k
            RETURN_IF((ret != IV_SUCCESS), ret);
2225
32.3k
        }
2226
16.1k
    }
2227
0
    else {
2228
0
        ps_dec->u4_dec_thread_created = 0;
2229
0
        ps_dec->u4_bs_deblk_thread_created = 0;
2230
0
    }
2231
2232
16.1k
    ps_dec_op->u4_num_bytes_consumed = 0;
2233
16.1k
    ps_dec_op->i4_reorder_depth = -1;
2234
16.1k
    ps_dec_op->i4_display_index = DEFAULT_POC;
2235
16.1k
    ps_dec->ps_out_buffer = NULL;
2236
2237
16.1k
    if(ps_dec_ip->u4_size
2238
16.1k
                    >= offsetof(ivd_video_decode_ip_t, s_out_buffer))
2239
16.1k
        ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer;
2240
2241
16.1k
    ps_dec->u4_fmt_conv_cur_row = 0;
2242
2243
16.1k
    ps_dec->u4_output_present = 0;
2244
16.1k
    ps_dec->s_disp_op.u4_error_code = 1;
2245
16.1k
    ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS;
2246
16.1k
    if(0 == ps_dec->u4_share_disp_buf
2247
16.1k
                    && ps_dec->i4_decode_header == 0)
2248
13.1k
    {
2249
13.1k
        UWORD32 i;
2250
13.1k
        if((ps_dec->ps_out_buffer->u4_num_bufs == 0) ||
2251
13.1k
           (ps_dec->ps_out_buffer->u4_num_bufs > IVD_VIDDEC_MAX_IO_BUFFERS))
2252
0
        {
2253
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2254
0
            ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2255
0
            return IV_FAIL;
2256
0
        }
2257
2258
37.6k
        for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++)
2259
24.5k
        {
2260
24.5k
            if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL)
2261
0
            {
2262
0
                ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2263
0
                ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2264
0
                return IV_FAIL;
2265
0
            }
2266
2267
24.5k
            if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0)
2268
0
            {
2269
0
                ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2270
0
                ps_dec_op->u4_error_code |=
2271
0
                                IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2272
0
                return IV_FAIL;
2273
0
            }
2274
24.5k
        }
2275
13.1k
    }
2276
2277
16.1k
    if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT)
2278
0
    {
2279
0
        ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER;
2280
0
        return IV_FAIL;
2281
0
    }
2282
2283
    /* ! */
2284
16.1k
    ps_dec->u4_ts = ps_dec_ip->u4_ts;
2285
2286
16.1k
    ps_dec_op->u4_error_code = 0;
2287
16.1k
    ps_dec_op->e_pic_type = IV_NA_FRAME;
2288
16.1k
    ps_dec_op->u4_output_present = 0;
2289
16.1k
    ps_dec_op->u4_frame_decoded_flag = 0;
2290
2291
16.1k
    ps_dec->i4_frametype = IV_NA_FRAME;
2292
16.1k
    ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
2293
2294
16.1k
    ps_dec->u4_slice_start_code_found = 0;
2295
2296
    /* In case the decoder is not in flush mode(in shared mode),
2297
     then decoder has to pick up a buffer to write current frame.
2298
     Check if a frame is available in such cases */
2299
2300
16.1k
    if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1
2301
0
                    && ps_dec->u1_flushfrm == 0)
2302
0
    {
2303
0
        UWORD32 i;
2304
2305
0
        WORD32 disp_avail = 0, free_id;
2306
2307
        /* Check if at least one buffer is available with the codec */
2308
        /* If not then return to application with error */
2309
0
        for(i = 0; i < ps_dec->u1_pic_bufs; i++)
2310
0
        {
2311
0
            if(0 == ps_dec->u4_disp_buf_mapping[i]
2312
0
                            || 1 == ps_dec->u4_disp_buf_to_be_freed[i])
2313
0
            {
2314
0
                disp_avail = 1;
2315
0
                break;
2316
0
            }
2317
2318
0
        }
2319
2320
0
        if(0 == disp_avail)
2321
0
        {
2322
            /* If something is queued for display wait for that buffer to be returned */
2323
2324
0
            ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2325
0
            ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
2326
0
            return (IV_FAIL);
2327
0
        }
2328
2329
0
        while(1)
2330
0
        {
2331
0
            pic_buffer_t *ps_pic_buf;
2332
0
            ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free(
2333
0
                            (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id);
2334
2335
0
            if(ps_pic_buf == NULL)
2336
0
            {
2337
0
                UWORD32 display_queued = 0;
2338
2339
                /* check if any buffer was given for display which is not returned yet */
2340
0
                for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
2341
0
                {
2342
0
                    if(0 != ps_dec->u4_disp_buf_mapping[i])
2343
0
                    {
2344
0
                        display_queued = 1;
2345
0
                        break;
2346
0
                    }
2347
0
                }
2348
                /* If some buffer is queued for display, then codec has to singal an error and wait
2349
                 for that buffer to be returned.
2350
                 If nothing is queued for display then codec has ownership of all display buffers
2351
                 and it can reuse any of the existing buffers and continue decoding */
2352
2353
0
                if(1 == display_queued)
2354
0
                {
2355
                    /* If something is queued for display wait for that buffer to be returned */
2356
0
                    ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2357
0
                    ps_dec_op->u4_error_code |= (1
2358
0
                                    << IVD_UNSUPPORTEDPARAM);
2359
0
                    return (IV_FAIL);
2360
0
                }
2361
0
            }
2362
0
            else
2363
0
            {
2364
                /* If the buffer is with display, then mark it as in use and then look for a buffer again */
2365
0
                if(1 == ps_dec->u4_disp_buf_mapping[free_id])
2366
0
                {
2367
0
                    ih264_buf_mgr_set_status(
2368
0
                                    (buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2369
0
                                    free_id,
2370
0
                                    BUF_MGR_IO);
2371
0
                }
2372
0
                else
2373
0
                {
2374
                    /**
2375
                     *  Found a free buffer for present call. Release it now.
2376
                     *  Will be again obtained later.
2377
                     */
2378
0
                    ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2379
0
                                          free_id,
2380
0
                                          BUF_MGR_IO);
2381
0
                    break;
2382
0
                }
2383
0
            }
2384
0
        }
2385
2386
0
    }
2387
2388
16.1k
    if(ps_dec->u1_enable_mb_info && (ps_dec->i4_header_decoded & DECODED_SPS_MASK))
2389
0
    {
2390
0
        UWORD32 blk_qp_map_size = ps_h264d_dec_ip->u4_8x8_blk_qp_map_size;
2391
0
        UWORD32 blk_type_map_size = ps_h264d_dec_ip->u4_8x8_blk_type_map_size;
2392
0
        UWORD32 blk_8x8_map_size = ps_dec->u4_total_mbs << 2;
2393
0
        if ((ps_h264d_dec_ip->pu1_8x8_blk_qp_map && blk_qp_map_size < blk_8x8_map_size) ||
2394
0
            (ps_h264d_dec_ip->pu1_8x8_blk_type_map && blk_type_map_size < blk_8x8_map_size))
2395
0
        {
2396
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2397
0
            ps_dec_op->u4_error_code |= IH264D_INSUFFICIENT_METADATA_BUFFER;
2398
0
            return IV_FAIL;
2399
0
        }
2400
0
    }
2401
2402
16.1k
    if(ps_dec->u1_flushfrm)
2403
0
    {
2404
0
        if(ps_dec->u1_init_dec_flag == 0)
2405
0
        {
2406
            /*Come out of flush mode and return*/
2407
0
            ps_dec->u1_flushfrm = 0;
2408
0
            return (IV_FAIL);
2409
0
        }
2410
2411
2412
2413
0
        ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2414
0
                                      &(ps_dec->s_disp_op));
2415
0
        if(0 == ps_dec->s_disp_op.u4_error_code)
2416
0
        {
2417
            /* check output buffer size given by the application */
2418
0
            if(check_app_out_buf_size(ps_dec) != IV_SUCCESS)
2419
0
            {
2420
0
                ps_dec_op->u4_error_code= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2421
0
                return (IV_FAIL);
2422
0
            }
2423
2424
0
            ps_dec->u4_fmt_conv_cur_row = 0;
2425
0
            ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht;
2426
0
            ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2427
0
                                  ps_dec->u4_fmt_conv_cur_row,
2428
0
                                  ps_dec->u4_fmt_conv_num_rows);
2429
0
            ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2430
0
            ps_dec->u4_output_present = 1;
2431
2432
0
            if(ps_dec->u1_enable_mb_info)
2433
0
            {
2434
0
                UWORD32 disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2435
0
                if(ps_h264d_dec_ip->pu1_8x8_blk_qp_map)
2436
0
                {
2437
0
                    ps_h264d_dec_op->pu1_8x8_blk_qp_map = ps_h264d_dec_ip->pu1_8x8_blk_qp_map;
2438
0
                    ps_h264d_dec_op->u4_8x8_blk_qp_map_size = ps_dec->u4_total_mbs << 2;
2439
0
                    ih264_memcpy(ps_h264d_dec_op->pu1_8x8_blk_qp_map,
2440
0
                        ps_dec->as_buf_id_info_map[disp_buf_id].pu1_qp_map,
2441
0
                        ps_dec->u4_total_mbs << 2);
2442
0
                }
2443
0
                if(ps_h264d_dec_ip->pu1_8x8_blk_type_map)
2444
0
                {
2445
0
                    ps_h264d_dec_op->pu1_8x8_blk_type_map = ps_h264d_dec_ip->pu1_8x8_blk_type_map;
2446
0
                    ps_h264d_dec_op->u4_8x8_blk_type_map_size = ps_dec->u4_total_mbs << 2;
2447
0
                    ih264_memcpy(ps_h264d_dec_op->pu1_8x8_blk_type_map,
2448
0
                        ps_dec->as_buf_id_info_map[disp_buf_id].pu1_mb_type_map,
2449
0
                        ps_dec->u4_total_mbs << 2);
2450
0
                }
2451
0
            }
2452
0
        }
2453
0
        ih264d_export_sei_params(&ps_dec_op->s_sei_decode_op, ps_dec);
2454
2455
0
        ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2456
2457
0
        ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2458
0
        ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2459
0
        ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
2460
0
        ps_dec_op->i4_display_index = ps_dec->i4_display_index;
2461
2462
0
        ps_dec_op->u4_new_seq = 0;
2463
2464
0
        ps_dec_op->u4_output_present = ps_dec->u4_output_present;
2465
0
        ps_dec_op->u4_progressive_frame_flag =
2466
0
                        ps_dec->s_disp_op.u4_progressive_frame_flag;
2467
0
        ps_dec_op->e_output_format =
2468
0
                        ps_dec->s_disp_op.e_output_format;
2469
0
        ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
2470
0
        ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
2471
0
        ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
2472
0
        ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2473
2474
        /*In the case of flush ,since no frame is decoded set pic type as invalid*/
2475
0
        ps_dec_op->u4_is_ref_flag = -1;
2476
0
        ps_dec_op->e_pic_type = IV_NA_FRAME;
2477
0
        ps_dec_op->u4_frame_decoded_flag = 0;
2478
2479
0
        if(0 == ps_dec->s_disp_op.u4_error_code)
2480
0
        {
2481
0
            return (IV_SUCCESS);
2482
0
        }
2483
0
        else
2484
0
            return (IV_FAIL);
2485
2486
0
    }
2487
16.1k
    if(ps_dec->u1_res_changed == 1)
2488
481
    {
2489
        /*if resolution has changed and all buffers have been flushed, reset decoder*/
2490
481
        ih264d_init_decoder(ps_dec);
2491
481
    }
2492
2493
16.1k
    ps_dec->u4_cur_mb_addr = 0;
2494
16.1k
    ps_dec->u4_total_mbs_coded = 0;
2495
16.1k
    ps_dec->u2_cur_slice_num = 0;
2496
16.1k
    ps_dec->cur_dec_mb_num = 0;
2497
16.1k
    ps_dec->cur_recon_mb_num = 0;
2498
16.1k
    ps_dec->u4_first_slice_in_pic = 1;
2499
16.1k
    ps_dec->u1_slice_header_done = 0;
2500
16.1k
    ps_dec->u1_dangling_field = 0;
2501
16.1k
    ps_dec->u4_cur_bs_mb_num = 0;
2502
16.1k
    ps_dec->u4_start_recon_deblk  = 0;
2503
16.1k
    ps_dec->u4_sps_cnt_in_process = 0;
2504
2505
16.1k
    DEBUG_THREADS_PRINTF(" Starting process call\n");
2506
2507
2508
16.1k
    ps_dec->u4_pic_buf_got = 0;
2509
2510
16.1k
    do
2511
491k
    {
2512
491k
        WORD32 buf_size;
2513
2514
491k
        pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer
2515
491k
                        + ps_dec_op->u4_num_bytes_consumed;
2516
2517
491k
        u4_max_ofst = ps_dec_ip->u4_num_Bytes
2518
491k
                        - ps_dec_op->u4_num_bytes_consumed;
2519
2520
        /* If dynamic bitstream buffer is not allocated and
2521
         * header decode is done, then allocate dynamic bitstream buffer
2522
         */
2523
491k
        if((NULL == ps_dec->pu1_bits_buf_dynamic) &&
2524
402k
           (ps_dec->i4_header_decoded & 1))
2525
2.18k
        {
2526
2.18k
            WORD32 size;
2527
2528
2.18k
            void *pv_buf;
2529
2.18k
            void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
2530
2.18k
            size = MAX(256000, ps_dec->u2_pic_wd * ps_dec->u2_pic_ht * 3 / 2);
2531
2.18k
            pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128,
2532
2.18k
                                              size + EXTRA_BS_OFFSET);
2533
2.18k
            RETURN_IF((NULL == pv_buf), IV_FAIL);
2534
2.18k
            memset(pv_buf, 0, size + EXTRA_BS_OFFSET);
2535
2.18k
            ps_dec->pu1_bits_buf_dynamic = pv_buf;
2536
2.18k
            ps_dec->u4_dynamic_bits_buf_size = size;
2537
2.18k
        }
2538
2539
491k
        if(ps_dec->pu1_bits_buf_dynamic)
2540
91.6k
        {
2541
91.6k
            pu1_bitstrm_buf = ps_dec->pu1_bits_buf_dynamic;
2542
91.6k
            buf_size = ps_dec->u4_dynamic_bits_buf_size;
2543
91.6k
        }
2544
399k
        else
2545
399k
        {
2546
399k
            pu1_bitstrm_buf = ps_dec->pu1_bits_buf_static;
2547
399k
            buf_size = ps_dec->u4_static_bits_buf_size;
2548
399k
        }
2549
2550
491k
        u4_next_is_aud = 0;
2551
2552
491k
        buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst,
2553
491k
                                               &u4_length_of_start_code,
2554
491k
                                               &u4_next_is_aud);
2555
2556
491k
        if(buflen == -1)
2557
0
            buflen = 0;
2558
        /* Ignore bytes beyond the allocated size of intermediate buffer */
2559
        /* Since 8 bytes are read ahead, ensure 8 bytes are free at the
2560
        end of the buffer, which will be memset to 0 after emulation prevention */
2561
491k
        buflen = MIN(buflen, buf_size - 8);
2562
2563
491k
        bytes_consumed = buflen + u4_length_of_start_code;
2564
491k
        ps_dec_op->u4_num_bytes_consumed += bytes_consumed;
2565
2566
491k
        if(buflen)
2567
489k
        {
2568
489k
            memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code,
2569
489k
                   buflen);
2570
            /* Decoder may read extra 8 bytes near end of the frame */
2571
489k
            if((buflen + 8) < buf_size)
2572
489k
            {
2573
489k
                memset(pu1_bitstrm_buf + buflen, 0, 8);
2574
489k
            }
2575
489k
            u4_first_start_code_found = 1;
2576
2577
489k
        }
2578
1.99k
        else
2579
1.99k
        {
2580
            /*start code not found*/
2581
2582
1.99k
            if(u4_first_start_code_found == 0)
2583
327
            {
2584
                /*no start codes found in current process call*/
2585
2586
327
                ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND;
2587
327
                ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
2588
2589
327
                if(ps_dec->u4_pic_buf_got == 0)
2590
327
                {
2591
2592
327
                    ih264d_fill_output_struct_from_context(ps_dec,
2593
327
                                                           ps_dec_op);
2594
2595
327
                    ps_dec_op->u4_error_code = ps_dec->i4_error_code;
2596
327
                    ps_dec_op->u4_frame_decoded_flag = 0;
2597
2598
327
                    return (IV_FAIL);
2599
327
                }
2600
0
                else
2601
0
                {
2602
0
                    ps_dec->u1_pic_decode_done = 1;
2603
0
                    continue;
2604
0
                }
2605
327
            }
2606
1.66k
            else
2607
1.66k
            {
2608
                /* a start code has already been found earlier in the same process call*/
2609
1.66k
                frame_data_left = 0;
2610
1.66k
                header_data_left = 0;
2611
1.66k
                continue;
2612
1.66k
            }
2613
2614
1.99k
        }
2615
2616
489k
        ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op,
2617
489k
                              pu1_bitstrm_buf, buflen);
2618
489k
        if(ret != OK)
2619
52.7k
        {
2620
52.7k
            UWORD32 error =  ih264d_map_error(ret);
2621
52.7k
            ps_dec_op->u4_error_code = error | ret;
2622
52.7k
            api_ret_value = IV_FAIL;
2623
2624
52.7k
            if((ret == IVD_RES_CHANGED)
2625
50.7k
                            || (ret == IVD_MEM_ALLOC_FAILED)
2626
50.7k
                            || (ret == ERROR_UNAVAIL_PICBUF_T)
2627
50.5k
                            || (ret == ERROR_UNAVAIL_MVBUF_T)
2628
50.3k
                            || (ret == ERROR_INV_SPS_PPS_T)
2629
46.9k
                            || (ret == ERROR_FEATURE_UNAVAIL)
2630
46.6k
                            || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
2631
46.4k
                            || (ret == IVD_DISP_FRM_ZERO_OP_BUF_SIZE))
2632
6.40k
            {
2633
6.40k
                ps_dec->u4_slice_start_code_found = 0;
2634
6.40k
                break;
2635
6.40k
            }
2636
2637
46.2k
            if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC))
2638
6.51k
            {
2639
6.51k
                ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2640
6.51k
                api_ret_value = IV_FAIL;
2641
6.51k
                break;
2642
6.51k
            }
2643
2644
39.7k
            if(ret == ERROR_IN_LAST_SLICE_OF_PIC)
2645
14
            {
2646
14
                api_ret_value = IV_FAIL;
2647
14
                break;
2648
14
            }
2649
2650
39.7k
        }
2651
2652
476k
        header_data_left = ((ps_dec->i4_decode_header == 1)
2653
221k
                        && (ps_dec->i4_header_decoded != 3)
2654
221k
                        && (ps_dec_op->u4_num_bytes_consumed
2655
221k
                                        < ps_dec_ip->u4_num_Bytes));
2656
476k
        frame_data_left = (((ps_dec->i4_decode_header == 0)
2657
255k
                        && ((ps_dec->u1_pic_decode_done == 0)
2658
746
                                        || (u4_next_is_aud == 1)))
2659
254k
                        && (ps_dec_op->u4_num_bytes_consumed
2660
254k
                                        < ps_dec_ip->u4_num_Bytes));
2661
476k
    }
2662
478k
    while(( header_data_left == 1)||(frame_data_left == 1));
2663
2664
15.8k
    if((ps_dec->u4_pic_buf_got == 1)
2665
7.16k
            && (ret != IVD_MEM_ALLOC_FAILED)
2666
7.16k
            && ps_dec->u4_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2667
5.92k
    {
2668
        // last slice - missing/corruption
2669
5.92k
        WORD32 num_mb_skipped;
2670
5.92k
        WORD32 prev_slice_err;
2671
5.92k
        pocstruct_t temp_poc;
2672
5.92k
        WORD32 ret1;
2673
5.92k
        WORD32 ht_in_mbs;
2674
5.92k
        ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag);
2675
5.92k
        num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2676
5.92k
                            - ps_dec->u4_total_mbs_coded;
2677
2678
5.92k
        if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0))
2679
0
            prev_slice_err = 1;
2680
5.92k
        else
2681
5.92k
            prev_slice_err = 2;
2682
2683
5.92k
        if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_total_mbs_coded == 0))
2684
0
            prev_slice_err = 1;
2685
2686
5.92k
        ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num,
2687
5.92k
                                   &temp_poc, prev_slice_err);
2688
2689
5.92k
        if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) ||
2690
5.92k
                       (ret1 == ERROR_INV_SPS_PPS_T))
2691
0
        {
2692
0
            ret = ret1;
2693
0
        }
2694
5.92k
    }
2695
2696
15.8k
    if((ret == IVD_RES_CHANGED)
2697
13.9k
                    || (ret == IVD_MEM_ALLOC_FAILED)
2698
13.9k
                    || (ret == ERROR_UNAVAIL_PICBUF_T)
2699
13.6k
                    || (ret == ERROR_UNAVAIL_MVBUF_T)
2700
13.4k
                    || (ret == ERROR_INV_SPS_PPS_T))
2701
5.71k
    {
2702
2703
        /* signal the decode thread */
2704
5.71k
        ih264d_signal_decode_thread(ps_dec);
2705
        /* close deblock thread if it is not closed yet */
2706
5.71k
        if(ps_dec->u4_num_cores == 3)
2707
467
        {
2708
467
            ih264d_signal_bs_deblk_thread(ps_dec);
2709
467
        }
2710
        /* dont consume bitstream for change in resolution case */
2711
5.71k
        if(ret == IVD_RES_CHANGED)
2712
1.92k
        {
2713
1.92k
            ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2714
1.92k
        }
2715
5.71k
        return IV_FAIL;
2716
5.71k
    }
2717
2718
2719
10.1k
    if(ps_dec->u1_separate_parse)
2720
4.42k
    {
2721
        /* If Format conversion is not complete,
2722
         complete it here */
2723
4.42k
        if(ps_dec->u4_num_cores == 2)
2724
2.08k
        {
2725
2726
            /*do deblocking of all mbs*/
2727
2.08k
            if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0))
2728
382
            {
2729
382
                UWORD32 u4_num_mbs,u4_max_addr;
2730
382
                tfr_ctxt_t s_tfr_ctxt;
2731
382
                tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
2732
382
                pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr;
2733
2734
                /*BS is done for all mbs while parsing*/
2735
382
                u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1;
2736
382
                ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1;
2737
2738
2739
382
                ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt,
2740
382
                                           ps_dec->u2_frm_wd_in_mbs, 0);
2741
2742
2743
382
                u4_num_mbs = u4_max_addr
2744
382
                                - ps_dec->u4_cur_deblk_mb_num + 1;
2745
2746
382
                DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs);
2747
2748
382
                if(u4_num_mbs != 0)
2749
382
                    ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs,
2750
382
                                                   ps_tfr_cxt,1);
2751
2752
382
                ps_dec->u4_start_recon_deblk  = 0;
2753
2754
382
            }
2755
2756
2.08k
        }
2757
2758
        /*signal the decode thread*/
2759
4.42k
        ih264d_signal_decode_thread(ps_dec);
2760
        /* close deblock thread if it is not closed yet*/
2761
4.42k
        if(ps_dec->u4_num_cores == 3)
2762
2.34k
        {
2763
2.34k
            ih264d_signal_bs_deblk_thread(ps_dec);
2764
2.34k
        }
2765
4.42k
    }
2766
2767
2768
10.1k
    DATA_SYNC();
2769
2770
2771
10.1k
    if((ps_dec_op->u4_error_code & 0xff)
2772
10.1k
                    != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
2773
10.1k
    {
2774
10.1k
        ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2775
10.1k
        ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2776
10.1k
        ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
2777
10.1k
    }
2778
2779
//Report if header (sps and pps) has not been decoded yet
2780
10.1k
    if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3)
2781
683
    {
2782
683
        ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
2783
683
        api_ret_value = IV_FAIL;
2784
683
    }
2785
2786
10.1k
    if((ps_dec->u4_pic_buf_got == 1)
2787
7.16k
                    && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status))
2788
7.16k
    {
2789
        /*
2790
         * For field pictures, set the bottom and top picture decoded u4_flag correctly.
2791
         */
2792
2793
7.16k
        if(ps_dec->ps_cur_slice->u1_field_pic_flag)
2794
2.46k
        {
2795
2.46k
            if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag)
2796
878
            {
2797
878
                ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY;
2798
878
            }
2799
1.58k
            else
2800
1.58k
            {
2801
1.58k
                ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY;
2802
1.58k
            }
2803
2.46k
        }
2804
4.70k
        else
2805
4.70k
        {
2806
4.70k
                ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY;
2807
4.70k
        }
2808
2809
        /* if new frame in not found (if we are still getting slices from previous frame)
2810
         * ih264d_deblock_display is not called. Such frames will not be added to reference /display
2811
         */
2812
7.16k
        if ((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0)
2813
7.16k
        {
2814
            /* Calling Function to deblock Picture and Display */
2815
7.16k
            ret = ih264d_deblock_display(ps_dec);
2816
7.16k
        }
2817
2818
2819
        /*set to complete ,as we dont support partial frame decode*/
2820
7.16k
        if(ps_dec->i4_header_decoded == 3)
2821
7.16k
        {
2822
7.16k
            ps_dec->u4_total_mbs_coded = ps_dec->ps_cur_sps->u4_max_mb_addr + 1;
2823
7.16k
        }
2824
2825
        /*Update the i4_frametype at the end of picture*/
2826
7.16k
        if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
2827
3.13k
        {
2828
3.13k
            ps_dec->i4_frametype = IV_IDR_FRAME;
2829
3.13k
        }
2830
4.03k
        else if(ps_dec->i4_pic_type == B_SLICE)
2831
2.26k
        {
2832
2.26k
            ps_dec->i4_frametype = IV_B_FRAME;
2833
2.26k
        }
2834
1.76k
        else if(ps_dec->i4_pic_type == P_SLICE)
2835
1.00k
        {
2836
1.00k
            ps_dec->i4_frametype = IV_P_FRAME;
2837
1.00k
        }
2838
755
        else if(ps_dec->i4_pic_type == I_SLICE)
2839
266
        {
2840
266
            ps_dec->i4_frametype = IV_I_FRAME;
2841
266
        }
2842
489
        else
2843
489
        {
2844
489
            H264_DEC_DEBUG_PRINT("Shouldn't come here\n");
2845
489
        }
2846
2847
        //Update the content type
2848
7.16k
        ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag;
2849
2850
7.16k
        ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2;
2851
7.16k
        ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded
2852
7.16k
                        - ps_dec->ps_cur_slice->u1_field_pic_flag;
2853
2854
7.16k
    }
2855
2856
    /* close deblock thread if it is not closed yet*/
2857
10.1k
    if(!ps_dec->i4_threads_active)
2858
0
    {
2859
0
        if(ps_dec->u4_num_cores == 3)
2860
0
        {
2861
0
            ih264d_signal_bs_deblk_thread(ps_dec);
2862
0
        }
2863
0
    }
2864
2865
2866
10.1k
    {
2867
        /* In case the decoder is configured to run in low delay mode,
2868
         * then get display buffer and then format convert.
2869
         * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles
2870
         */
2871
2872
10.1k
        if((IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode)
2873
0
                        && ps_dec->u1_init_dec_flag)
2874
0
        {
2875
2876
0
            ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2877
0
                                          &(ps_dec->s_disp_op));
2878
0
            if(0 == ps_dec->s_disp_op.u4_error_code)
2879
0
            {
2880
0
                ps_dec->u4_fmt_conv_cur_row = 0;
2881
0
                ps_dec->u4_output_present = 1;
2882
0
            }
2883
0
        }
2884
2885
10.1k
        ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
2886
2887
        /* If Format conversion is not complete,
2888
         complete it here */
2889
10.1k
        if(ps_dec->u4_output_present &&
2890
4.77k
          (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht))
2891
2.06k
        {
2892
2.06k
            ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht
2893
2.06k
                            - ps_dec->u4_fmt_conv_cur_row;
2894
2.06k
            ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2895
2.06k
                                  ps_dec->u4_fmt_conv_cur_row,
2896
2.06k
                                  ps_dec->u4_fmt_conv_num_rows);
2897
2.06k
            ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2898
2.06k
        }
2899
2900
10.1k
        ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2901
10.1k
    }
2902
2903
10.1k
    if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1)
2904
283
    {
2905
283
        ps_dec_op->u4_progressive_frame_flag = 1;
2906
283
        if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2907
283
        {
2908
283
            if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag)
2909
192
                            && (0 == ps_dec->ps_sps->u1_mb_aff_flag))
2910
102
                ps_dec_op->u4_progressive_frame_flag = 0;
2911
2912
283
        }
2913
283
    }
2914
2915
10.1k
    if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded)
2916
5.18k
    {
2917
5.18k
        ps_dec->u1_top_bottom_decoded = 0;
2918
5.18k
    }
2919
    /*--------------------------------------------------------------------*/
2920
    /* Do End of Pic processing.                                          */
2921
    /* Should be called only if frame was decoded in previous process call*/
2922
    /*--------------------------------------------------------------------*/
2923
10.1k
    if(ps_dec->u4_pic_buf_got == 1)
2924
7.16k
    {
2925
7.16k
        if(1 == ps_dec->u1_last_pic_not_decoded)
2926
0
        {
2927
0
            ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec);
2928
2929
0
            if(ret != OK)
2930
0
                return ret;
2931
2932
0
            ret = ih264d_end_of_pic(ps_dec);
2933
0
            if(ret != OK)
2934
0
                return ret;
2935
0
        }
2936
7.16k
        else
2937
7.16k
        {
2938
7.16k
            ret = ih264d_end_of_pic(ps_dec);
2939
7.16k
            if(ret != OK)
2940
0
                return ret;
2941
7.16k
        }
2942
2943
7.16k
    }
2944
2945
10.1k
    if(ps_dec->u1_enable_mb_info && ps_dec->u4_output_present)
2946
0
    {
2947
0
        UWORD32 disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2948
0
        if(ps_h264d_dec_ip->pu1_8x8_blk_qp_map)
2949
0
        {
2950
0
            ps_h264d_dec_op->pu1_8x8_blk_qp_map = ps_h264d_dec_ip->pu1_8x8_blk_qp_map;
2951
0
            ps_h264d_dec_op->u4_8x8_blk_qp_map_size = ps_dec->u4_total_mbs << 2;
2952
0
            ih264_memcpy(ps_h264d_dec_op->pu1_8x8_blk_qp_map,
2953
0
                ps_dec->as_buf_id_info_map[disp_buf_id].pu1_qp_map,
2954
0
                ps_dec->u4_total_mbs << 2);
2955
0
        }
2956
0
        if(ps_h264d_dec_ip->pu1_8x8_blk_type_map)
2957
0
        {
2958
0
            ps_h264d_dec_op->pu1_8x8_blk_type_map = ps_h264d_dec_ip->pu1_8x8_blk_type_map;
2959
0
            ps_h264d_dec_op->u4_8x8_blk_type_map_size = ps_dec->u4_total_mbs << 2;
2960
0
            ih264_memcpy(ps_h264d_dec_op->pu1_8x8_blk_type_map,
2961
0
                ps_dec->as_buf_id_info_map[disp_buf_id].pu1_mb_type_map,
2962
0
                ps_dec->u4_total_mbs << 2);
2963
0
        }
2964
0
    }
2965
2966
    /*Data memory barrier instruction,so that yuv write by the library is complete*/
2967
10.1k
    DATA_SYNC();
2968
2969
10.1k
    H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n",
2970
10.1k
                         ps_dec_op->u4_num_bytes_consumed);
2971
10.1k
    return api_ret_value;
2972
10.1k
}
2973
2974
WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2975
0
{
2976
0
    char version_string[MAXVERSION_STRLEN + 1];
2977
0
    UWORD32 version_string_len;
2978
2979
0
    ivd_ctl_getversioninfo_ip_t *ps_ip;
2980
0
    ivd_ctl_getversioninfo_op_t *ps_op;
2981
2982
0
    ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip;
2983
0
    ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op;
2984
0
    UNUSED(dec_hdl);
2985
0
    ps_op->u4_error_code = IV_SUCCESS;
2986
2987
0
    VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
2988
0
            CODEC_VENDOR);
2989
2990
0
    if((WORD32)ps_ip->u4_version_buffer_size <= 0)
2991
0
    {
2992
0
        ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
2993
0
        return (IV_FAIL);
2994
0
    }
2995
2996
0
    version_string_len = strnlen(version_string, MAXVERSION_STRLEN) + 1;
2997
2998
0
    if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string)))
2999
0
    {
3000
0
        memcpy(ps_ip->pv_version_buffer, version_string, version_string_len);
3001
0
        ps_op->u4_error_code = IV_SUCCESS;
3002
0
    }
3003
0
    else
3004
0
    {
3005
0
        ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
3006
0
        return IV_FAIL;
3007
0
    }
3008
0
    return (IV_SUCCESS);
3009
0
}
3010
3011
/*****************************************************************************/
3012
/*                                                                           */
3013
/*  Function Name :   ih264d_get_display_frame                               */
3014
/*                                                                           */
3015
/*  Description   :                                                          */
3016
/*  Inputs        :iv_obj_t decoder handle                                   */
3017
/*                :pv_api_ip pointer to input structure                      */
3018
/*                :pv_api_op pointer to output structure                     */
3019
/*  Outputs       :                                                          */
3020
/*  Returns       : void                                                     */
3021
/*                                                                           */
3022
/*  Issues        : none                                                     */
3023
/*                                                                           */
3024
/*  Revision History:                                                        */
3025
/*                                                                           */
3026
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3027
/*         22 10 2008    100356         Draft                                */
3028
/*                                                                           */
3029
/*****************************************************************************/
3030
WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl,
3031
                                void *pv_api_ip,
3032
                                void *pv_api_op)
3033
0
{
3034
3035
0
    UNUSED(dec_hdl);
3036
0
    UNUSED(pv_api_ip);
3037
0
    UNUSED(pv_api_op);
3038
    // This function is no longer needed, output is returned in the process()
3039
0
    return IV_FAIL;
3040
0
}
3041
3042
/*****************************************************************************/
3043
/*                                                                           */
3044
/*  Function Name :  ih264d_set_display_frame                                */
3045
/*                                                                           */
3046
/*  Description   :                                                          */
3047
/*                                                                           */
3048
/*  Inputs        :iv_obj_t decoder handle                                   */
3049
/*                :pv_api_ip pointer to input structure                      */
3050
/*                :pv_api_op pointer to output structure                     */
3051
/*  Outputs       :                                                          */
3052
/*  Returns       : void                                                     */
3053
/*                                                                           */
3054
/*  Issues        : none                                                     */
3055
/*                                                                           */
3056
/*  Revision History:                                                        */
3057
/*                                                                           */
3058
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3059
/*         22 10 2008    100356         Draft                                */
3060
/*                                                                           */
3061
/*****************************************************************************/
3062
WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl,
3063
                                void *pv_api_ip,
3064
                                void *pv_api_op)
3065
0
{
3066
3067
0
    UWORD32 u4_disp_buf_size[3], u4_num_disp_bufs;
3068
0
    ivd_set_display_frame_ip_t *dec_disp_ip;
3069
0
    ivd_set_display_frame_op_t *dec_disp_op;
3070
3071
0
    UWORD32 i;
3072
0
    dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3073
3074
0
    dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
3075
0
    dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
3076
0
    dec_disp_op->u4_error_code = 0;
3077
3078
3079
0
    ps_dec->u4_num_disp_bufs = 0;
3080
0
    if(ps_dec->u4_share_disp_buf)
3081
0
    {
3082
0
        UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs;
3083
3084
0
        u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW);
3085
3086
0
        ps_dec->u4_num_disp_bufs = u4_num_bufs;
3087
3088
        /* Get the number and sizes of the first buffer. Compare this with the
3089
         * rest to make sure all the buffers are of the same size.
3090
         */
3091
0
        u4_num_disp_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs;
3092
3093
0
        u4_disp_buf_size[0] =
3094
0
          dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0];
3095
0
        u4_disp_buf_size[1] =
3096
0
          dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1];
3097
0
        u4_disp_buf_size[2] =
3098
0
          dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2];
3099
3100
0
        for(i = 0; i < u4_num_bufs; i++)
3101
0
        {
3102
0
            if(dec_disp_ip->s_disp_buffer[i].u4_num_bufs != u4_num_disp_bufs)
3103
0
            {
3104
0
                return IV_FAIL;
3105
0
            }
3106
3107
0
            if((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]
3108
0
                != u4_disp_buf_size[0])
3109
0
                || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]
3110
0
                    != u4_disp_buf_size[1])
3111
0
                || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]
3112
0
                    != u4_disp_buf_size[2]))
3113
0
            {
3114
0
                return IV_FAIL;
3115
0
            }
3116
3117
0
            ps_dec->disp_bufs[i].u4_num_bufs =
3118
0
                            dec_disp_ip->s_disp_buffer[i].u4_num_bufs;
3119
3120
0
            ps_dec->disp_bufs[i].buf[0] =
3121
0
                            dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
3122
0
            ps_dec->disp_bufs[i].buf[1] =
3123
0
                            dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
3124
0
            ps_dec->disp_bufs[i].buf[2] =
3125
0
                            dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
3126
3127
0
            ps_dec->disp_bufs[i].u4_bufsize[0] =
3128
0
                            dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0];
3129
0
            ps_dec->disp_bufs[i].u4_bufsize[1] =
3130
0
                            dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1];
3131
0
            ps_dec->disp_bufs[i].u4_bufsize[2] =
3132
0
                            dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2];
3133
3134
0
        }
3135
0
    }
3136
0
    return IV_SUCCESS;
3137
3138
0
}
3139
3140
/*****************************************************************************/
3141
/*                                                                           */
3142
/*  Function Name : ih264d_set_flush_mode                                    */
3143
/*                                                                           */
3144
/*  Description   :                                                          */
3145
/*                                                                           */
3146
/*  Inputs        :iv_obj_t decoder handle                                   */
3147
/*                :pv_api_ip pointer to input structure                      */
3148
/*                :pv_api_op pointer to output structure                     */
3149
/*  Globals       : <Does it use any global variables?>                      */
3150
/*  Outputs       :                                                          */
3151
/*  Returns       : void                                                     */
3152
/*                                                                           */
3153
/*  Issues        : none                                                     */
3154
/*                                                                           */
3155
/*  Revision History:                                                        */
3156
/*                                                                           */
3157
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3158
/*         22 10 2008    100356         Draft                                */
3159
/*                                                                           */
3160
/*****************************************************************************/
3161
WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3162
0
{
3163
0
    dec_struct_t * ps_dec;
3164
0
    ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op;
3165
0
    ps_ctl_op->u4_error_code = 0;
3166
3167
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3168
0
    ih264d_join_threads(ps_dec);
3169
0
    UNUSED(pv_api_ip);
3170
    /* ! */
3171
    /* Signal flush frame control call */
3172
0
    ps_dec->u1_flushfrm = 1;
3173
3174
0
    if(ps_dec->u1_init_dec_flag == 1)
3175
0
    {
3176
0
        ih264d_release_pics_in_dpb((void *)ps_dec, ps_dec->u1_pic_bufs);
3177
0
        ih264d_release_display_bufs(ps_dec);
3178
0
    }
3179
3180
0
    ps_ctl_op->u4_error_code = 0;
3181
3182
    /* Ignore dangling fields during flush */
3183
0
    ps_dec->u1_top_bottom_decoded = 0;
3184
3185
0
    return IV_SUCCESS;
3186
0
}
3187
3188
/*****************************************************************************/
3189
/*                                                                           */
3190
/*  Function Name : ih264d_get_status                                        */
3191
/*                                                                           */
3192
/*  Description   :                                                          */
3193
/*                                                                           */
3194
/*  Inputs        :iv_obj_t decoder handle                                   */
3195
/*                :pv_api_ip pointer to input structure                      */
3196
/*                :pv_api_op pointer to output structure                     */
3197
/*  Globals       : <Does it use any global variables?>                      */
3198
/*  Outputs       :                                                          */
3199
/*  Returns       : void                                                     */
3200
/*                                                                           */
3201
/*  Issues        : none                                                     */
3202
/*                                                                           */
3203
/*  Revision History:                                                        */
3204
/*                                                                           */
3205
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3206
/*         22 10 2008    100356         Draft                                */
3207
/*                                                                           */
3208
/*****************************************************************************/
3209
3210
WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3211
0
{
3212
3213
0
    UWORD32 i;
3214
0
    dec_struct_t * ps_dec;
3215
0
    UWORD32 pic_wd, pic_ht;
3216
0
    ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op;
3217
0
    UNUSED(pv_api_ip);
3218
0
    ps_ctl_op->u4_error_code = 0;
3219
3220
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3221
3222
3223
0
    if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3224
0
    {
3225
0
        ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height;
3226
0
        ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width;
3227
3228
0
        if(0 == ps_dec->u4_share_disp_buf)
3229
0
        {
3230
0
            pic_wd = ps_dec->u2_disp_width;
3231
0
            pic_ht = ps_dec->u2_disp_height;
3232
3233
0
        }
3234
0
        else
3235
0
        {
3236
0
            pic_wd = ps_dec->u2_frm_wd_y;
3237
0
            pic_ht = ps_dec->u2_frm_ht_y;
3238
0
        }
3239
0
    }
3240
0
    else
3241
0
    {
3242
0
        pic_wd = 0;
3243
0
        pic_ht = 0;
3244
3245
0
        ps_ctl_op->u4_pic_ht = pic_wd;
3246
0
        ps_ctl_op->u4_pic_wd = pic_ht;
3247
3248
0
        if(1 == ps_dec->u4_share_disp_buf)
3249
0
        {
3250
0
            pic_wd += (PAD_LEN_Y_H << 1);
3251
0
            pic_ht += (PAD_LEN_Y_V << 2);
3252
3253
0
        }
3254
3255
0
    }
3256
3257
0
    if(ps_dec->u4_app_disp_width > pic_wd)
3258
0
        pic_wd = ps_dec->u4_app_disp_width;
3259
0
    if(0 == ps_dec->u4_share_disp_buf)
3260
0
        ps_ctl_op->u4_num_disp_bufs = 1;
3261
0
    else
3262
0
    {
3263
0
        if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3264
0
        {
3265
0
            if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3266
0
               (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3267
0
            {
3268
0
                ps_ctl_op->u4_num_disp_bufs =
3269
0
                                ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3270
0
            }
3271
0
            else
3272
0
            {
3273
                /*if VUI is not present assume maximum possible refrence frames for the level,
3274
                 * as max reorder frames*/
3275
0
                ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3276
0
            }
3277
3278
0
            ps_ctl_op->u4_num_disp_bufs +=
3279
0
                            ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3280
0
        }
3281
0
        else
3282
0
        {
3283
0
            ps_ctl_op->u4_num_disp_bufs = 32;
3284
0
        }
3285
0
        ps_ctl_op->u4_num_disp_bufs = MAX(
3286
0
                        ps_ctl_op->u4_num_disp_bufs, 6);
3287
0
        ps_ctl_op->u4_num_disp_bufs = MIN(
3288
0
                        ps_ctl_op->u4_num_disp_bufs, 32);
3289
0
    }
3290
3291
0
    ps_ctl_op->u4_error_code = ps_dec->i4_error_code;
3292
3293
0
    ps_ctl_op->u4_frame_rate = 0; //make it proper
3294
0
    ps_ctl_op->u4_bit_rate = 0; //make it proper
3295
0
    ps_ctl_op->e_content_type = ps_dec->i4_content_type;
3296
0
    ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format;
3297
0
    ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3298
3299
0
    if(ps_dec->u1_chroma_format == IV_YUV_420P)
3300
0
    {
3301
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
3302
0
    }
3303
0
    else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3304
0
    {
3305
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
3306
0
    }
3307
0
    else if(ps_dec->u1_chroma_format == IV_RGB_565)
3308
0
    {
3309
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
3310
0
    }
3311
0
    else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3312
0
                    || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3313
0
    {
3314
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
3315
0
    }
3316
3317
0
    else
3318
0
    {
3319
        //Invalid chroma format; Error code may be updated, verify in testing if needed
3320
0
        ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL;
3321
0
        return IV_FAIL;
3322
0
    }
3323
3324
0
    for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3325
0
    {
3326
0
        ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
3327
0
    }
3328
3329
    /*!*/
3330
0
    if(ps_dec->u1_chroma_format == IV_YUV_420P)
3331
0
    {
3332
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3333
0
        ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3334
0
                        >> 2;
3335
0
        ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
3336
0
                        >> 2;
3337
0
    }
3338
0
    else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3339
0
    {
3340
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3341
0
                        * 2;
3342
0
        ps_ctl_op->u4_min_out_buf_size[1] =
3343
0
                        ps_ctl_op->u4_min_out_buf_size[2] = 0;
3344
0
    }
3345
0
    else if(ps_dec->u1_chroma_format == IV_RGB_565)
3346
0
    {
3347
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3348
0
                        * 2;
3349
0
        ps_ctl_op->u4_min_out_buf_size[1] =
3350
0
                        ps_ctl_op->u4_min_out_buf_size[2] = 0;
3351
0
    }
3352
0
    else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3353
0
                    || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3354
0
    {
3355
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3356
0
        ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3357
0
                        >> 1;
3358
0
        ps_ctl_op->u4_min_out_buf_size[2] = 0;
3359
0
    }
3360
3361
0
    ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3362
0
    return IV_SUCCESS;
3363
0
}
3364
3365
/*****************************************************************************/
3366
/*                                                                           */
3367
/*  Function Name :    ih264d_get_buf_info                                   */
3368
/*                                                                           */
3369
/*  Description   :                                                          */
3370
/*                                                                           */
3371
/*  Inputs        :iv_obj_t decoder handle                                   */
3372
/*                :pv_api_ip pointer to input structure                      */
3373
/*                :pv_api_op pointer to output structure                     */
3374
/*  Globals       : <Does it use any global variables?>                      */
3375
/*  Outputs       :                                                          */
3376
/*  Returns       : void                                                     */
3377
/*                                                                           */
3378
/*  Issues        : none                                                     */
3379
/*                                                                           */
3380
/*  Revision History:                                                        */
3381
/*                                                                           */
3382
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3383
/*         22 10 2008    100356         Draft                                */
3384
/*                                                                           */
3385
/*****************************************************************************/
3386
WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3387
0
{
3388
3389
0
    dec_struct_t * ps_dec;
3390
0
    UWORD8 i = 0; // Default for 420P format
3391
0
    UWORD16 pic_wd, pic_ht;
3392
0
    ivd_ctl_getbufinfo_op_t *ps_ctl_op =
3393
0
                    (ivd_ctl_getbufinfo_op_t*)pv_api_op;
3394
0
    UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
3395
0
    UNUSED(pv_api_ip);
3396
3397
0
    ps_ctl_op->u4_error_code = 0;
3398
3399
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3400
3401
0
    ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3402
3403
3404
0
    ps_ctl_op->u4_num_disp_bufs = 1;
3405
3406
3407
0
    pic_wd = 0;
3408
0
    pic_ht = 0;
3409
3410
0
    if(ps_dec->i4_header_decoded == 3)
3411
0
    {
3412
3413
0
        if(0 == ps_dec->u4_share_disp_buf)
3414
0
        {
3415
0
            pic_wd = ps_dec->u2_disp_width;
3416
0
            pic_ht = ps_dec->u2_disp_height;
3417
3418
0
        }
3419
0
        else
3420
0
        {
3421
0
            pic_wd = ps_dec->u2_frm_wd_y;
3422
0
            pic_ht = ps_dec->u2_frm_ht_y;
3423
0
        }
3424
3425
0
    }
3426
3427
0
    for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3428
0
    {
3429
0
        ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
3430
0
    }
3431
0
    if((WORD32)ps_dec->u4_app_disp_width > pic_wd)
3432
0
        pic_wd = ps_dec->u4_app_disp_width;
3433
3434
0
    if(0 == ps_dec->u4_share_disp_buf)
3435
0
        ps_ctl_op->u4_num_disp_bufs = 1;
3436
0
    else
3437
0
    {
3438
0
        if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3439
0
        {
3440
0
            if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3441
0
               (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3442
0
            {
3443
0
                ps_ctl_op->u4_num_disp_bufs =
3444
0
                                ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3445
0
            }
3446
0
            else
3447
0
            {
3448
                /*if VUI is not present assume maximum possible refrence frames for the level,
3449
                 * as max reorder frames*/
3450
0
                ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3451
0
            }
3452
3453
0
            ps_ctl_op->u4_num_disp_bufs +=
3454
0
                            ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3455
3456
0
        }
3457
0
        else
3458
0
        {
3459
0
            ps_ctl_op->u4_num_disp_bufs = 32;
3460
3461
0
        }
3462
3463
0
        ps_ctl_op->u4_num_disp_bufs = MAX(
3464
0
                        ps_ctl_op->u4_num_disp_bufs, 6);
3465
0
        ps_ctl_op->u4_num_disp_bufs = MIN(
3466
0
                        ps_ctl_op->u4_num_disp_bufs, 32);
3467
0
    }
3468
3469
0
    ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size(
3470
0
                    pic_wd, pic_ht, ps_dec->u1_chroma_format,
3471
0
                    &au4_min_out_buf_size[0]);
3472
3473
0
    for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++)
3474
0
    {
3475
0
        ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i];
3476
0
    }
3477
3478
0
    ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3479
3480
0
    return IV_SUCCESS;
3481
0
}
3482
3483
/*****************************************************************************/
3484
/*                                                                           */
3485
/*  Function Name : ih264d_set_params                                        */
3486
/*                                                                           */
3487
/*  Description   :                                                          */
3488
/*                                                                           */
3489
/*  Inputs        :iv_obj_t decoder handle                                   */
3490
/*                :pv_api_ip pointer to input structure                      */
3491
/*                :pv_api_op pointer to output structure                     */
3492
/*  Outputs       :                                                          */
3493
/*  Returns       : void                                                     */
3494
/*                                                                           */
3495
/*  Issues        : none                                                     */
3496
/*                                                                           */
3497
/*  Revision History:                                                        */
3498
/*                                                                           */
3499
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3500
/*         22 10 2008    100356         Draft                                */
3501
/*                                                                           */
3502
/*****************************************************************************/
3503
WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3504
718
{
3505
3506
718
    dec_struct_t * ps_dec;
3507
718
    WORD32 ret = IV_SUCCESS;
3508
3509
718
    ih264d_ctl_set_config_ip_t *ps_h264d_ctl_ip =
3510
718
                    (ih264d_ctl_set_config_ip_t *)pv_api_ip;
3511
718
    ih264d_ctl_set_config_op_t *ps_h264d_ctl_op =
3512
718
                    (ih264d_ctl_set_config_op_t *)pv_api_op;
3513
718
    ivd_ctl_set_config_ip_t *ps_ctl_ip =
3514
718
                    &ps_h264d_ctl_ip->s_ivd_ctl_set_config_ip_t;
3515
718
    ivd_ctl_set_config_op_t *ps_ctl_op =
3516
718
                    &ps_h264d_ctl_op->s_ivd_ctl_set_config_op_t;
3517
3518
718
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3519
3520
718
    ps_dec->u4_skip_frm_mask = 0;
3521
3522
718
    ps_ctl_op->u4_error_code = 0;
3523
3524
718
    if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE)
3525
0
    {
3526
0
        ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3527
0
        ret = IV_FAIL;
3528
0
    }
3529
3530
718
    if(ps_ctl_ip->u4_disp_wd >= ps_dec->u2_disp_width)
3531
415
    {
3532
415
        ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3533
415
    }
3534
303
    else if(0 == ps_dec->i4_header_decoded)
3535
4
    {
3536
4
        ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3537
4
    }
3538
299
    else if(ps_ctl_ip->u4_disp_wd == 0)
3539
299
    {
3540
299
        ps_dec->u4_app_disp_width = 0;
3541
299
    }
3542
0
    else
3543
0
    {
3544
        /*
3545
         * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF)
3546
         * does not propogate.
3547
         */
3548
0
        ps_dec->u4_app_disp_width = 0;
3549
0
        ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3550
0
        ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
3551
0
        ret = IV_FAIL;
3552
0
    }
3553
3554
718
    if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME)
3555
359
        ps_dec->i4_decode_header = 0;
3556
359
    else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER)
3557
359
        ps_dec->i4_decode_header = 1;
3558
0
    else
3559
0
    {
3560
0
        ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3561
0
        ps_dec->i4_decode_header = 1;
3562
0
        ret = IV_FAIL;
3563
0
    }
3564
718
    ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
3565
3566
718
    if((ps_ctl_ip->e_frm_out_mode != IVD_DECODE_FRAME_OUT) &&
3567
718
       (ps_ctl_ip->e_frm_out_mode != IVD_DISPLAY_FRAME_OUT))
3568
0
    {
3569
0
        ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3570
0
        ret = IV_FAIL;
3571
0
    }
3572
718
    ps_dec->e_frm_out_mode = ps_ctl_ip->e_frm_out_mode;
3573
718
    return ret;
3574
3575
718
}
3576
3577
/*****************************************************************************/
3578
/*                                                                           */
3579
/*  Function Name : ih264d_set_default_params                                */
3580
/*                                                                           */
3581
/*  Description   :                                                          */
3582
/*                                                                           */
3583
/*  Inputs        :iv_obj_t decoder handle                                   */
3584
/*                :pv_api_ip pointer to input structure                      */
3585
/*                :pv_api_op pointer to output structure                     */
3586
/*  Outputs       :                                                          */
3587
/*  Returns       : void                                                     */
3588
/*                                                                           */
3589
/*  Issues        : none                                                     */
3590
/*                                                                           */
3591
/*  Revision History:                                                        */
3592
/*                                                                           */
3593
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3594
/*         08 08 2011   100421          Copied from set_params               */
3595
/*                                                                           */
3596
/*****************************************************************************/
3597
WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl,
3598
                                 void *pv_api_ip,
3599
                                 void *pv_api_op)
3600
0
{
3601
3602
0
    dec_struct_t * ps_dec;
3603
0
    WORD32 ret = IV_SUCCESS;
3604
3605
0
    ivd_ctl_set_config_op_t *ps_ctl_op =
3606
0
                    (ivd_ctl_set_config_op_t *)pv_api_op;
3607
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3608
0
    UNUSED(pv_api_ip);
3609
3610
3611
0
    {
3612
0
        ps_dec->u4_app_disp_width = 0;
3613
0
        ps_dec->u4_skip_frm_mask = 0;
3614
0
        ps_dec->i4_decode_header = 1;
3615
3616
0
        ps_ctl_op->u4_error_code = 0;
3617
0
    }
3618
3619
3620
0
    return ret;
3621
0
}
3622
/*****************************************************************************/
3623
/*                                                                           */
3624
/*  Function Name :  ih264d_reset                                            */
3625
/*                                                                           */
3626
/*  Description   :                                                          */
3627
/*                                                                           */
3628
/*  Inputs        :iv_obj_t decoder handle                                   */
3629
/*                :pv_api_ip pointer to input structure                      */
3630
/*                :pv_api_op pointer to output structure                     */
3631
/*  Globals       : <Does it use any global variables?>                      */
3632
/*  Outputs       :                                                          */
3633
/*  Returns       : void                                                     */
3634
/*                                                                           */
3635
/*  Issues        : none                                                     */
3636
/*                                                                           */
3637
/*  Revision History:                                                        */
3638
/*                                                                           */
3639
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3640
/*         22 10 2008    100356         Draft                                */
3641
/*                                                                           */
3642
/*****************************************************************************/
3643
WORD32 ih264d_delete(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3644
359
{
3645
359
    dec_struct_t *ps_dec;
3646
359
    ih264d_delete_ip_t *ps_ip = (ih264d_delete_ip_t *)pv_api_ip;
3647
359
    ih264d_delete_op_t *ps_op = (ih264d_delete_op_t *)pv_api_op;
3648
3649
359
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3650
359
    UNUSED(ps_ip);
3651
359
    ps_op->s_ivd_delete_op_t.u4_error_code = 0;
3652
359
    ih264d_free_dynamic_bufs(ps_dec);
3653
359
    ih264d_free_static_bufs(dec_hdl);
3654
359
    return IV_SUCCESS;
3655
359
}
3656
/*****************************************************************************/
3657
/*                                                                           */
3658
/*  Function Name :  ih264d_reset                                            */
3659
/*                                                                           */
3660
/*  Description   :                                                          */
3661
/*                                                                           */
3662
/*  Inputs        :iv_obj_t decoder handle                                   */
3663
/*                :pv_api_ip pointer to input structure                      */
3664
/*                :pv_api_op pointer to output structure                     */
3665
/*  Globals       : <Does it use any global variables?>                      */
3666
/*  Outputs       :                                                          */
3667
/*  Returns       : void                                                     */
3668
/*                                                                           */
3669
/*  Issues        : none                                                     */
3670
/*                                                                           */
3671
/*  Revision History:                                                        */
3672
/*                                                                           */
3673
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3674
/*         22 10 2008    100356         Draft                                */
3675
/*                                                                           */
3676
/*****************************************************************************/
3677
WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3678
1.44k
{
3679
1.44k
    dec_struct_t * ps_dec;
3680
1.44k
    ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op;
3681
1.44k
    UNUSED(pv_api_ip);
3682
1.44k
    ps_ctl_op->u4_error_code = 0;
3683
3684
1.44k
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3685
3686
1.44k
    if(ps_dec != NULL)
3687
1.44k
    {
3688
1.44k
        ih264d_join_threads(ps_dec);
3689
1.44k
        ih264d_init_decoder(ps_dec);
3690
1.44k
    }
3691
0
    else
3692
0
    {
3693
0
        H264_DEC_DEBUG_PRINT(
3694
0
                        "\nReset called without Initializing the decoder\n");
3695
0
        ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE;
3696
0
    }
3697
3698
1.44k
    return IV_SUCCESS;
3699
1.44k
}
3700
3701
/*****************************************************************************/
3702
/*                                                                           */
3703
/*  Function Name :  ih264d_ctl                                              */
3704
/*                                                                           */
3705
/*  Description   :                                                          */
3706
/*                                                                           */
3707
/*  Inputs        :iv_obj_t decoder handle                                   */
3708
/*                :pv_api_ip pointer to input structure                      */
3709
/*                :pv_api_op pointer to output structure                     */
3710
/*  Outputs       :                                                          */
3711
/*  Returns       : void                                                     */
3712
/*                                                                           */
3713
/*  Issues        : none                                                     */
3714
/*                                                                           */
3715
/*  Revision History:                                                        */
3716
/*                                                                           */
3717
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3718
/*         22 10 2008    100356         Draft                                */
3719
/*                                                                           */
3720
/*****************************************************************************/
3721
WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3722
2.87k
{
3723
2.87k
    ivd_ctl_set_config_ip_t *ps_ctl_ip;
3724
2.87k
    ivd_ctl_set_config_op_t *ps_ctl_op;
3725
2.87k
    WORD32 ret = IV_SUCCESS;
3726
2.87k
    UWORD32 subcommand;
3727
2.87k
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3728
3729
2.87k
    if(ps_dec->init_done != 1)
3730
0
    {
3731
        //Return proper Error Code
3732
0
        return IV_FAIL;
3733
0
    }
3734
2.87k
    ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip;
3735
2.87k
    ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op;
3736
2.87k
    ps_ctl_op->u4_error_code = 0;
3737
2.87k
    subcommand = ps_ctl_ip->e_sub_cmd;
3738
3739
2.87k
    switch(subcommand)
3740
2.87k
    {
3741
0
        case IVD_CMD_CTL_GETPARAMS:
3742
0
            ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip,
3743
0
                                    (void *)pv_api_op);
3744
0
            break;
3745
718
        case IVD_CMD_CTL_SETPARAMS:
3746
718
            ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip,
3747
718
                                    (void *)pv_api_op);
3748
718
            break;
3749
1.44k
        case IVD_CMD_CTL_RESET:
3750
1.44k
            ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op);
3751
1.44k
            break;
3752
0
        case IVD_CMD_CTL_SETDEFAULT:
3753
0
            ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip,
3754
0
                                            (void *)pv_api_op);
3755
0
            break;
3756
0
        case IVD_CMD_CTL_FLUSH:
3757
0
            ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip,
3758
0
                                        (void *)pv_api_op);
3759
0
            break;
3760
0
        case IVD_CMD_CTL_GETBUFINFO:
3761
0
            ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip,
3762
0
                                      (void *)pv_api_op);
3763
0
            break;
3764
0
        case IVD_CMD_CTL_GETVERSION:
3765
0
            ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip,
3766
0
                                     (void *)pv_api_op);
3767
0
            break;
3768
0
        case IH264D_CMD_CTL_DEGRADE:
3769
0
            ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip,
3770
0
                                     (void *)pv_api_op);
3771
0
            break;
3772
3773
359
        case IH264D_CMD_CTL_SET_NUM_CORES:
3774
359
            ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip,
3775
359
                                       (void *)pv_api_op);
3776
359
            break;
3777
0
        case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
3778
0
            ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip,
3779
0
                                              (void *)pv_api_op);
3780
0
            break;
3781
0
        case IH264D_CMD_CTL_GET_VUI_PARAMS:
3782
0
            ret = ih264d_get_vui_params(dec_hdl, (void *)pv_api_ip,
3783
0
                                        (void *)pv_api_op);
3784
0
            break;
3785
0
        case IH264D_CMD_CTL_GET_SEI_MDCV_PARAMS:
3786
0
            ret = ih264d_get_sei_mdcv_params(dec_hdl, (void *)pv_api_ip,
3787
0
                                             (void *)pv_api_op);
3788
0
            break;
3789
0
        case IH264D_CMD_CTL_GET_SEI_CLL_PARAMS:
3790
0
            ret = ih264d_get_sei_cll_params(dec_hdl, (void *)pv_api_ip,
3791
0
                                            (void *)pv_api_op);
3792
0
            break;
3793
0
        case IH264D_CMD_CTL_GET_SEI_AVE_PARAMS:
3794
0
            ret = ih264d_get_sei_ave_params(dec_hdl, (void *)pv_api_ip,
3795
0
                                            (void *)pv_api_op);
3796
0
            break;
3797
0
        case IH264D_CMD_CTL_GET_SEI_CCV_PARAMS:
3798
0
            ret = ih264d_get_sei_ccv_params(dec_hdl, (void *)pv_api_ip,
3799
0
                                            (void *)pv_api_op);
3800
0
            break;
3801
0
        case IH264D_CMD_CTL_GET_SEI_SII_PARAMS:
3802
0
            ret = ih264d_get_sei_sii_params(dec_hdl, (void *) pv_api_ip, (void *) pv_api_op);
3803
0
            break;
3804
3805
0
        case IH264D_CMD_CTL_GET_SEI_FGC_PARAMS:
3806
0
            ret = ih264d_get_sei_fgc_params(dec_hdl, (void *) pv_api_ip, (void *) pv_api_op);
3807
0
            break;
3808
3809
359
        case IH264D_CMD_CTL_SET_PROCESSOR:
3810
359
            ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip,
3811
359
                                       (void *)pv_api_op);
3812
359
            break;
3813
0
        default:
3814
0
            H264_DEC_DEBUG_PRINT("\ndo nothing\n")
3815
0
            ;
3816
0
            break;
3817
2.87k
    }
3818
3819
2.87k
    return ret;
3820
2.87k
}
3821
/*****************************************************************************/
3822
/*                                                                           */
3823
/*  Function Name :   ih264d_rel_display_frame                               */
3824
/*                                                                           */
3825
/*  Description   :                                                          */
3826
/*                                                                           */
3827
/*  Inputs        :iv_obj_t decoder handle                                   */
3828
/*                :pv_api_ip pointer to input structure                      */
3829
/*                :pv_api_op pointer to output structure                     */
3830
/*  Outputs       :                                                          */
3831
/*  Returns       : void                                                     */
3832
/*                                                                           */
3833
/*  Issues        : none                                                     */
3834
/*                                                                           */
3835
/*  Revision History:                                                        */
3836
/*                                                                           */
3837
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3838
/*         22 10 2008    100356         Draft                                */
3839
/*                                                                           */
3840
/*****************************************************************************/
3841
WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl,
3842
                                void *pv_api_ip,
3843
                                void *pv_api_op)
3844
0
{
3845
3846
0
    ivd_rel_display_frame_ip_t *ps_rel_ip;
3847
0
    ivd_rel_display_frame_op_t *ps_rel_op;
3848
0
    UWORD32 buf_released = 0;
3849
3850
0
    UWORD32 u4_ts = 0;
3851
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3852
3853
0
    ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
3854
0
    ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op;
3855
0
    ps_rel_op->u4_error_code = 0;
3856
0
    u4_ts = ps_rel_ip->u4_disp_buf_id;
3857
3858
0
    if(0 == ps_dec->u4_share_disp_buf)
3859
0
    {
3860
0
        ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3861
0
        ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0;
3862
0
        return IV_SUCCESS;
3863
0
    }
3864
3865
0
    if(ps_dec->pv_pic_buf_mgr != NULL)
3866
0
    {
3867
0
        if(1 == ps_dec->u4_disp_buf_mapping[u4_ts])
3868
0
        {
3869
0
            ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
3870
0
                                  ps_rel_ip->u4_disp_buf_id,
3871
0
                                  BUF_MGR_IO);
3872
0
            ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3873
0
            buf_released = 1;
3874
0
        }
3875
0
    }
3876
3877
0
    if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released))
3878
0
        ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1;
3879
3880
0
    return IV_SUCCESS;
3881
0
}
3882
3883
/**
3884
 *******************************************************************************
3885
 *
3886
 * @brief
3887
 *  Sets degrade params
3888
 *
3889
 * @par Description:
3890
 *  Sets degrade params.
3891
 *  Refer to ih264d_ctl_degrade_ip_t definition for details
3892
 *
3893
 * @param[in] ps_codec_obj
3894
 *  Pointer to codec object at API level
3895
 *
3896
 * @param[in] pv_api_ip
3897
 *  Pointer to input argument structure
3898
 *
3899
 * @param[out] pv_api_op
3900
 *  Pointer to output argument structure
3901
 *
3902
 * @returns  Status
3903
 *
3904
 * @remarks
3905
 *
3906
 *
3907
 *******************************************************************************
3908
 */
3909
3910
WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
3911
                          void *pv_api_ip,
3912
                          void *pv_api_op)
3913
0
{
3914
0
    ih264d_ctl_degrade_ip_t *ps_ip;
3915
0
    ih264d_ctl_degrade_op_t *ps_op;
3916
0
    dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle;
3917
3918
0
    ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
3919
0
    ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
3920
3921
0
    ps_codec->i4_degrade_type = ps_ip->i4_degrade_type;
3922
0
    ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
3923
0
    ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics;
3924
3925
0
    ps_op->u4_error_code = 0;
3926
0
    ps_codec->i4_degrade_pic_cnt = 0;
3927
3928
0
    return IV_SUCCESS;
3929
0
}
3930
3931
WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
3932
                                   void *pv_api_ip,
3933
                                   void *pv_api_op)
3934
0
{
3935
0
    ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
3936
0
    ih264d_ctl_get_frame_dimensions_op_t *ps_op;
3937
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3938
0
    UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
3939
3940
0
    ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
3941
3942
0
    ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
3943
0
    UNUSED(ps_ip);
3944
0
    if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3945
0
    {
3946
0
        disp_wd = ps_dec->u2_disp_width;
3947
0
        disp_ht = ps_dec->u2_disp_height;
3948
3949
0
        if(0 == ps_dec->u4_share_disp_buf)
3950
0
        {
3951
0
            buffer_wd = disp_wd;
3952
0
            buffer_ht = disp_ht;
3953
0
        }
3954
0
        else
3955
0
        {
3956
0
            buffer_wd = ps_dec->u2_frm_wd_y;
3957
0
            buffer_ht = ps_dec->u2_frm_ht_y;
3958
0
        }
3959
0
    }
3960
0
    else
3961
0
    {
3962
0
        disp_wd = 0;
3963
0
        disp_ht = 0;
3964
3965
0
        if(0 == ps_dec->u4_share_disp_buf)
3966
0
        {
3967
0
            buffer_wd = disp_wd;
3968
0
            buffer_ht = disp_ht;
3969
0
        }
3970
0
        else
3971
0
        {
3972
0
            buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1);
3973
0
            buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2);
3974
0
        }
3975
0
    }
3976
0
    if(ps_dec->u4_app_disp_width > buffer_wd)
3977
0
        buffer_wd = ps_dec->u4_app_disp_width;
3978
3979
0
    if(0 == ps_dec->u4_share_disp_buf)
3980
0
    {
3981
0
        x_offset = 0;
3982
0
        y_offset = 0;
3983
0
    }
3984
0
    else
3985
0
    {
3986
0
        y_offset = (PAD_LEN_Y_V << 1);
3987
0
        x_offset = PAD_LEN_Y_H;
3988
3989
0
        if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid))
3990
0
                        && (0 != ps_dec->u2_crop_offset_y))
3991
0
        {
3992
0
            y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y;
3993
0
            x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y;
3994
0
        }
3995
0
    }
3996
3997
0
    ps_op->u4_disp_wd[0] = disp_wd;
3998
0
    ps_op->u4_disp_ht[0] = disp_ht;
3999
0
    ps_op->u4_buffer_wd[0] = buffer_wd;
4000
0
    ps_op->u4_buffer_ht[0] = buffer_ht;
4001
0
    ps_op->u4_x_offset[0] = x_offset;
4002
0
    ps_op->u4_y_offset[0] = y_offset;
4003
4004
0
    ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
4005
0
                    >> 1);
4006
0
    ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
4007
0
                    >> 1);
4008
0
    ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
4009
0
                    >> 1);
4010
0
    ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
4011
0
                    >> 1);
4012
0
    ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] =
4013
0
                    (ps_op->u4_x_offset[0] >> 1);
4014
0
    ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] =
4015
0
                    (ps_op->u4_y_offset[0] >> 1);
4016
4017
0
    if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
4018
0
                    || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
4019
0
    {
4020
0
        ps_op->u4_disp_wd[2] = 0;
4021
0
        ps_op->u4_disp_ht[2] = 0;
4022
0
        ps_op->u4_buffer_wd[2] = 0;
4023
0
        ps_op->u4_buffer_ht[2] = 0;
4024
0
        ps_op->u4_x_offset[2] = 0;
4025
0
        ps_op->u4_y_offset[2] = 0;
4026
4027
0
        ps_op->u4_disp_wd[1] <<= 1;
4028
0
        ps_op->u4_buffer_wd[1] <<= 1;
4029
0
        ps_op->u4_x_offset[1] <<= 1;
4030
0
    }
4031
4032
0
    return IV_SUCCESS;
4033
4034
0
}
4035
4036
WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
4037
                             void *pv_api_ip,
4038
                             void *pv_api_op)
4039
0
{
4040
0
    ih264d_ctl_get_vui_params_ip_t *ps_ip;
4041
0
    ih264d_ctl_get_vui_params_op_t *ps_op;
4042
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4043
0
    dec_seq_params_t *ps_sps;
4044
0
    vui_t *ps_vui;
4045
0
    WORD32 i;
4046
0
    UWORD32 u4_size;
4047
4048
0
    ps_ip = (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
4049
0
    ps_op = (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
4050
0
    UNUSED(ps_ip);
4051
4052
0
    u4_size = ps_op->u4_size;
4053
0
    memset(ps_op, 0, sizeof(ih264d_ctl_get_vui_params_op_t));
4054
0
    ps_op->u4_size = u4_size;
4055
4056
0
    if(NULL == ps_dec->ps_cur_sps)
4057
0
    {
4058
0
        ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
4059
0
        return IV_FAIL;
4060
0
    }
4061
4062
0
    ps_sps = ps_dec->ps_cur_sps;
4063
0
    if((0 == ps_sps->u1_is_valid)
4064
0
                    || (0 == ps_sps->u1_vui_parameters_present_flag))
4065
0
    {
4066
0
        ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
4067
0
        return IV_FAIL;
4068
0
    }
4069
4070
0
    ps_vui = &ps_sps->s_vui;
4071
4072
0
    ps_op->u1_aspect_ratio_idc              = ps_vui->u1_aspect_ratio_idc;
4073
0
    ps_op->u2_sar_width                     = ps_vui->u2_sar_width;
4074
0
    ps_op->u2_sar_height                    = ps_vui->u2_sar_height;
4075
0
    ps_op->u1_overscan_appropriate_flag     = ps_vui->u1_overscan_appropriate_flag;
4076
0
    ps_op->u1_video_format                  = ps_vui->u1_video_format;
4077
0
    ps_op->u1_video_full_range_flag         = ps_vui->u1_video_full_range_flag;
4078
0
    ps_op->u1_colour_primaries              = ps_vui->u1_colour_primaries;
4079
0
    ps_op->u1_tfr_chars                     = ps_vui->u1_tfr_chars;
4080
0
    ps_op->u1_matrix_coeffs                 = ps_vui->u1_matrix_coeffs;
4081
0
    ps_op->u1_cr_top_field                  = ps_vui->u1_cr_top_field;
4082
0
    ps_op->u1_cr_bottom_field               = ps_vui->u1_cr_bottom_field;
4083
0
    ps_op->u4_num_units_in_tick             = ps_vui->u4_num_units_in_tick;
4084
0
    ps_op->u4_time_scale                    = ps_vui->u4_time_scale;
4085
0
    ps_op->u1_fixed_frame_rate_flag         = ps_vui->u1_fixed_frame_rate_flag;
4086
0
    ps_op->u1_nal_hrd_params_present        = ps_vui->u1_nal_hrd_params_present;
4087
0
    ps_op->u1_vcl_hrd_params_present        = ps_vui->u1_vcl_hrd_params_present;
4088
0
    ps_op->u1_low_delay_hrd_flag            = ps_vui->u1_low_delay_hrd_flag;
4089
0
    ps_op->u1_pic_struct_present_flag       = ps_vui->u1_pic_struct_present_flag;
4090
0
    ps_op->u1_bitstream_restriction_flag    = ps_vui->u1_bitstream_restriction_flag;
4091
0
    ps_op->u1_mv_over_pic_boundaries_flag   = ps_vui->u1_mv_over_pic_boundaries_flag;
4092
0
    ps_op->u4_max_bytes_per_pic_denom       = ps_vui->u4_max_bytes_per_pic_denom;
4093
0
    ps_op->u4_max_bits_per_mb_denom         = ps_vui->u4_max_bits_per_mb_denom;
4094
0
    ps_op->u4_log2_max_mv_length_horz       = ps_vui->u4_log2_max_mv_length_horz;
4095
0
    ps_op->u4_log2_max_mv_length_vert       = ps_vui->u4_log2_max_mv_length_vert;
4096
0
    ps_op->u4_num_reorder_frames            = ps_vui->u4_num_reorder_frames;
4097
0
    ps_op->u4_max_dec_frame_buffering       = ps_vui->u4_max_dec_frame_buffering;
4098
4099
0
    return IV_SUCCESS;
4100
0
}
4101
/*****************************************************************************/
4102
/*                                                                           */
4103
/*  Function Name : ih264d_get_sei_mdcv_params                               */
4104
/*                                                                           */
4105
/*  Description   : This function populates SEI mdcv message in              */
4106
/*                     output structure                                      */
4107
/*  Inputs        : iv_obj_t decoder handle                                  */
4108
/*                : pv_api_ip pointer to input structure                     */
4109
/*                : pv_api_op pointer to output structure                    */
4110
/*  Outputs       :                                                          */
4111
/*  Returns       : returns 0; 1 with error code when MDCV is not present    */
4112
/*                                                                           */
4113
/*  Issues        : none                                                     */
4114
/*                                                                           */
4115
/*  Revision History:                                                        */
4116
/*                                                                           */
4117
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4118
/*                                                                           */
4119
/*                                                                           */
4120
/*****************************************************************************/
4121
WORD32 ih264d_get_sei_mdcv_params(iv_obj_t *dec_hdl,
4122
                                  void *pv_api_ip,
4123
                                  void *pv_api_op)
4124
0
{
4125
0
    ih264d_ctl_get_sei_mdcv_params_ip_t *ps_ip;
4126
0
    ih264d_ctl_get_sei_mdcv_params_op_t *ps_op;
4127
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4128
0
    sei_mdcv_params_t *ps_sei_mdcv;
4129
0
    WORD32 i4_count;
4130
4131
0
    ps_ip = (ih264d_ctl_get_sei_mdcv_params_ip_t *)pv_api_ip;
4132
0
    ps_op = (ih264d_ctl_get_sei_mdcv_params_op_t *)pv_api_op;
4133
0
    UNUSED(ps_ip);
4134
4135
0
    if(0 == ps_dec->s_sei_export.u1_sei_mdcv_params_present_flag)
4136
0
    {
4137
0
        ps_op->u4_error_code = ERROR_SEI_MDCV_PARAMS_NOT_FOUND;
4138
0
        return IV_FAIL;
4139
0
    }
4140
4141
0
    ps_sei_mdcv = &ps_dec->s_sei_export.s_sei_mdcv_params;
4142
4143
0
    for(i4_count = 0; i4_count < NUM_SEI_MDCV_PRIMARIES; i4_count++)
4144
0
    {
4145
0
        ps_op->au2_display_primaries_x[i4_count] = ps_sei_mdcv->au2_display_primaries_x[i4_count];
4146
0
        ps_op->au2_display_primaries_y[i4_count] = ps_sei_mdcv->au2_display_primaries_y[i4_count];
4147
0
    }
4148
4149
0
    ps_op->u2_white_point_x = ps_sei_mdcv->u2_white_point_x;
4150
0
    ps_op->u2_white_point_y = ps_sei_mdcv->u2_white_point_y;
4151
0
    ps_op->u4_max_display_mastering_luminance = ps_sei_mdcv->u4_max_display_mastering_luminance;
4152
0
    ps_op->u4_min_display_mastering_luminance = ps_sei_mdcv->u4_min_display_mastering_luminance;
4153
4154
0
    return IV_SUCCESS;
4155
0
}
4156
4157
/*****************************************************************************/
4158
/*                                                                           */
4159
/*  Function Name : ih264d_get_sei_cll_params                                */
4160
/*                                                                           */
4161
/*  Description   : This function populates SEI cll message in               */
4162
/*                     output structure                                      */
4163
/*  Inputs        : iv_obj_t decoder handle                                  */
4164
/*                : pv_api_ip pointer to input structure                     */
4165
/*                : pv_api_op pointer to output structure                    */
4166
/*  Outputs       :                                                          */
4167
/*  Returns       : returns 0; 1 with error code when CLL is not present     */
4168
/*                                                                           */
4169
/*  Issues        : none                                                     */
4170
/*                                                                           */
4171
/*  Revision History:                                                        */
4172
/*                                                                           */
4173
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4174
/*                                                                           */
4175
/*                                                                           */
4176
/*****************************************************************************/
4177
WORD32 ih264d_get_sei_cll_params(iv_obj_t *dec_hdl,
4178
                                 void *pv_api_ip,
4179
                                 void *pv_api_op)
4180
0
{
4181
0
    ih264d_ctl_get_sei_cll_params_ip_t *ps_ip;
4182
0
    ih264d_ctl_get_sei_cll_params_op_t *ps_op;
4183
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4184
0
    sei_cll_params_t *ps_sei_cll;
4185
4186
0
    ps_ip = (ih264d_ctl_get_sei_cll_params_ip_t *)pv_api_ip;
4187
0
    ps_op = (ih264d_ctl_get_sei_cll_params_op_t *)pv_api_op;
4188
0
    UNUSED(ps_ip);
4189
4190
0
    if(0 == ps_dec->s_sei_export.u1_sei_cll_params_present_flag)
4191
0
    {
4192
0
        ps_op->u4_error_code = ERROR_SEI_CLL_PARAMS_NOT_FOUND;
4193
0
        return IV_FAIL;
4194
0
    }
4195
4196
0
    ps_sei_cll = &ps_dec->s_sei_export.s_sei_cll_params;
4197
4198
0
    ps_op->u2_max_content_light_level = ps_sei_cll->u2_max_content_light_level;
4199
0
    ps_op->u2_max_pic_average_light_level = ps_sei_cll->u2_max_pic_average_light_level;
4200
4201
0
    return IV_SUCCESS;
4202
0
}
4203
4204
/*****************************************************************************/
4205
/*                                                                           */
4206
/*  Function Name : ih264d_get_sei_ave_params                                */
4207
/*                                                                           */
4208
/*  Description   : This function populates SEI ave message in               */
4209
/*                     output structure                                      */
4210
/*  Inputs        : iv_obj_t decoder handle                                  */
4211
/*                : pv_api_ip pointer to input structure                     */
4212
/*                : pv_api_op pointer to output structure                    */
4213
/*  Outputs       :                                                          */
4214
/*  Returns       : returns 0; 1 with error code when AVE is not present     */
4215
/*                                                                           */
4216
/*  Issues        : none                                                     */
4217
/*                                                                           */
4218
/*  Revision History:                                                        */
4219
/*                                                                           */
4220
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4221
/*                                                                           */
4222
/*                                                                           */
4223
/*****************************************************************************/
4224
WORD32 ih264d_get_sei_ave_params(iv_obj_t *dec_hdl,
4225
                                 void *pv_api_ip,
4226
                                 void *pv_api_op)
4227
0
{
4228
0
    ih264d_ctl_get_sei_ave_params_ip_t *ps_ip;
4229
0
    ih264d_ctl_get_sei_ave_params_op_t *ps_op;
4230
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4231
0
    sei_ave_params_t *ps_sei_ave;
4232
4233
0
    ps_ip = (ih264d_ctl_get_sei_ave_params_ip_t *)pv_api_ip;
4234
0
    ps_op = (ih264d_ctl_get_sei_ave_params_op_t *)pv_api_op;
4235
0
    UNUSED(ps_ip);
4236
4237
0
    if(0 == ps_dec->s_sei_export.u1_sei_ave_params_present_flag)
4238
0
    {
4239
0
        ps_op->u4_error_code = ERROR_SEI_AVE_PARAMS_NOT_FOUND;
4240
0
        return IV_FAIL;
4241
0
    }
4242
4243
0
    ps_sei_ave = &ps_dec->s_sei_export.s_sei_ave_params;
4244
4245
0
    ps_op->u4_ambient_illuminance = ps_sei_ave->u4_ambient_illuminance;
4246
0
    ps_op->u2_ambient_light_x = ps_sei_ave->u2_ambient_light_x;
4247
0
    ps_op->u2_ambient_light_y = ps_sei_ave->u2_ambient_light_y;
4248
4249
0
    return IV_SUCCESS;
4250
0
}
4251
4252
/*****************************************************************************/
4253
/*                                                                           */
4254
/*  Function Name : ih264d_get_sei_ccv_params                                */
4255
/*                                                                           */
4256
/*  Description   : This function populates SEI mdcv message in              */
4257
/*                     output structure                                      */
4258
/*  Inputs        : iv_obj_t decoder handle                                  */
4259
/*                : pv_api_ip pointer to input structure                     */
4260
/*                : pv_api_op pointer to output structure                    */
4261
/*  Outputs       :                                                          */
4262
/*  Returns       : returns 0; 1 with error code when CCV is not present    */
4263
/*                                                                           */
4264
/*  Issues        : none                                                     */
4265
/*                                                                           */
4266
/*  Revision History:                                                        */
4267
/*                                                                           */
4268
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4269
/*                                                                           */
4270
/*                                                                           */
4271
/*****************************************************************************/
4272
WORD32 ih264d_get_sei_ccv_params(iv_obj_t *dec_hdl,
4273
                                 void *pv_api_ip,
4274
                                 void *pv_api_op)
4275
0
{
4276
0
    ih264d_ctl_get_sei_ccv_params_ip_t *ps_ip;
4277
0
    ih264d_ctl_get_sei_ccv_params_op_t *ps_op;
4278
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4279
0
    sei_ccv_params_t *ps_sei_ccv;
4280
0
    WORD32 i4_count;
4281
4282
0
    ps_ip = (ih264d_ctl_get_sei_ccv_params_ip_t *)pv_api_ip;
4283
0
    ps_op = (ih264d_ctl_get_sei_ccv_params_op_t *)pv_api_op;
4284
0
    UNUSED(ps_ip);
4285
4286
0
    if(0 == ps_dec->s_sei_export.u1_sei_ccv_params_present_flag)
4287
0
    {
4288
0
        ps_op->u4_error_code = ERROR_SEI_CCV_PARAMS_NOT_FOUND;
4289
0
        return IV_FAIL;
4290
0
    }
4291
4292
0
    ps_sei_ccv = &ps_dec->s_sei_export.s_sei_ccv_params;
4293
4294
0
    ps_op->u1_ccv_cancel_flag = ps_sei_ccv->u1_ccv_cancel_flag;
4295
4296
0
    if(0 == ps_op->u1_ccv_cancel_flag)
4297
0
    {
4298
0
        ps_op->u1_ccv_persistence_flag = ps_sei_ccv->u1_ccv_persistence_flag;
4299
0
        ps_op->u1_ccv_primaries_present_flag = ps_sei_ccv->u1_ccv_primaries_present_flag;
4300
0
        ps_op->u1_ccv_min_luminance_value_present_flag =
4301
0
                    ps_sei_ccv->u1_ccv_min_luminance_value_present_flag;
4302
0
        ps_op->u1_ccv_max_luminance_value_present_flag =
4303
0
                    ps_sei_ccv->u1_ccv_max_luminance_value_present_flag;
4304
0
        ps_op->u1_ccv_avg_luminance_value_present_flag =
4305
0
                    ps_sei_ccv->u1_ccv_avg_luminance_value_present_flag;
4306
0
        ps_op->u1_ccv_reserved_zero_2bits = ps_sei_ccv->u1_ccv_reserved_zero_2bits;
4307
4308
0
        if(1 == ps_sei_ccv->u1_ccv_primaries_present_flag)
4309
0
        {
4310
0
            for(i4_count = 0; i4_count < NUM_SEI_CCV_PRIMARIES; i4_count++)
4311
0
            {
4312
0
                ps_op->ai4_ccv_primaries_x[i4_count] = ps_sei_ccv->ai4_ccv_primaries_x[i4_count];
4313
0
                ps_op->ai4_ccv_primaries_y[i4_count] = ps_sei_ccv->ai4_ccv_primaries_y[i4_count];
4314
0
            }
4315
0
        }
4316
4317
0
        if(1 == ps_sei_ccv->u1_ccv_min_luminance_value_present_flag)
4318
0
        {
4319
0
            ps_op->u4_ccv_min_luminance_value = ps_sei_ccv->u4_ccv_min_luminance_value;
4320
0
        }
4321
0
        if(1 == ps_sei_ccv->u1_ccv_max_luminance_value_present_flag)
4322
0
        {
4323
0
            ps_op->u4_ccv_max_luminance_value = ps_sei_ccv->u4_ccv_max_luminance_value;
4324
0
        }
4325
0
        if(1 == ps_sei_ccv->u1_ccv_avg_luminance_value_present_flag)
4326
0
        {
4327
0
            ps_op->u4_ccv_avg_luminance_value = ps_sei_ccv->u4_ccv_avg_luminance_value;
4328
0
        }
4329
0
    }
4330
4331
0
    return IV_SUCCESS;
4332
0
}
4333
4334
/*****************************************************************************/
4335
/*                                                                           */
4336
/*  Function Name : ih264d_get_sei_sii_params                                */
4337
/*                                                                           */
4338
/*  Description   : This function populates SEI sii message in               */
4339
/*                     output structure                                      */
4340
/*  Inputs        : iv_obj_t decoder handle                                  */
4341
/*                : pv_api_ip pointer to input structure                     */
4342
/*                : pv_api_op pointer to output structure                    */
4343
/*  Outputs       :                                                          */
4344
/*  Returns       : returns 0; 1 with error code when SII is not present     */
4345
/*                                                                           */
4346
/*  Issues        : none                                                     */
4347
/*                                                                           */
4348
/*  Revision History:                                                        */
4349
/*                                                                           */
4350
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4351
/*                                                                           */
4352
/*                                                                           */
4353
/*****************************************************************************/
4354
WORD32 ih264d_get_sei_sii_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4355
0
{
4356
0
    ih264d_ctl_get_sei_sii_params_ip_t *ps_ip;
4357
0
    ih264d_ctl_get_sei_sii_params_op_t *ps_op;
4358
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4359
0
    sei_sii_params_t *ps_sei_sii;
4360
0
    int i;
4361
4362
0
    ps_ip = (ih264d_ctl_get_sei_sii_params_ip_t *) pv_api_ip;
4363
0
    ps_op = (ih264d_ctl_get_sei_sii_params_op_t *) pv_api_op;
4364
0
    UNUSED(ps_ip);
4365
4366
0
    if(0 == ps_dec->s_sei_export.u1_sei_sii_params_present_flag)
4367
0
    {
4368
0
        ps_op->u4_error_code = ERROR_SEI_SII_PARAMS_NOT_FOUND;
4369
0
        return IV_FAIL;
4370
0
    }
4371
4372
0
    ps_sei_sii = &ps_dec->s_sei_export.s_sei_sii_params;
4373
4374
0
    if((ps_sei_sii->u4_sii_sub_layer_idx > 0) &&
4375
0
       (ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag == 1))
4376
0
    {
4377
0
        ps_op->u4_error_code = ERROR_INV_SEI_SII_PARAMS;
4378
0
        return IV_FAIL;
4379
0
    }
4380
4381
0
    if((ps_sei_sii->u4_sii_sub_layer_idx > ps_sei_sii->u1_sii_max_sub_layers_minus1) &&
4382
0
       (ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag == 0))
4383
0
    {
4384
0
        ps_op->u4_error_code = ERROR_INV_SEI_SII_PARAMS;
4385
0
        return IV_FAIL;
4386
0
    }
4387
4388
0
    ps_op->u4_sii_sub_layer_idx = ps_sei_sii->u4_sii_sub_layer_idx;
4389
4390
0
    if(0 == ps_op->u4_sii_sub_layer_idx)
4391
0
    {
4392
0
        ps_op->u1_shutter_interval_info_present_flag =
4393
0
            ps_sei_sii->u1_shutter_interval_info_present_flag;
4394
4395
0
        if(1 == ps_sei_sii->u1_shutter_interval_info_present_flag)
4396
0
        {
4397
0
            ps_op->u4_sii_time_scale = ps_sei_sii->u4_sii_time_scale;
4398
0
            ps_op->u1_fixed_shutter_interval_within_cvs_flag =
4399
0
                ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag;
4400
4401
0
            if(1 == ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag)
4402
0
            {
4403
0
                ps_op->u4_sii_num_units_in_shutter_interval =
4404
0
                    ps_sei_sii->u4_sii_num_units_in_shutter_interval;
4405
0
            }
4406
0
            else
4407
0
            {
4408
0
                ps_op->u1_sii_max_sub_layers_minus1 = ps_sei_sii->u1_sii_max_sub_layers_minus1;
4409
0
                for(i = 0; i <= ps_sei_sii->u1_sii_max_sub_layers_minus1; i++)
4410
0
                {
4411
0
                    ps_op->au4_sub_layer_num_units_in_shutter_interval[i] =
4412
0
                        ps_sei_sii->au4_sub_layer_num_units_in_shutter_interval[i];
4413
0
                }
4414
0
            }
4415
0
        }
4416
0
    }
4417
4418
0
    return IV_SUCCESS;
4419
0
}
4420
4421
/*****************************************************************************/
4422
/*                                                                           */
4423
/*  Function Name : ih264d_get_sei_fgc_params                                */
4424
/*                                                                           */
4425
/*  Description   : This function populates SEI FGC message in               */
4426
/*                     output structure                                      */
4427
/*  Inputs        : iv_obj_t decoder handle                                  */
4428
/*                : pv_api_ip pointer to input structure                     */
4429
/*                : pv_api_op pointer to output structure                    */
4430
/*  Outputs       :                                                          */
4431
/*  Returns       : returns 0; 1 with error code when FGC is not present     */
4432
/*                                                                           */
4433
/*  Issues        : none                                                     */
4434
/*                                                                           */
4435
/*  Revision History:                                                        */
4436
/*                                                                           */
4437
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4438
/*                                                                           */
4439
/*                                                                           */
4440
/*****************************************************************************/
4441
WORD32 ih264d_get_sei_fgc_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4442
0
{
4443
0
    ih264d_ctl_get_sei_fgc_params_ip_t *ps_ip;
4444
0
    ih264d_ctl_get_sei_fgc_params_op_t *ps_op;
4445
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4446
0
    sei_fgc_params_t *ps_sei_fgc;
4447
0
    WORD32 i4_count;
4448
0
    UWORD32 c, i, j;
4449
4450
0
    ps_ip = (ih264d_ctl_get_sei_fgc_params_ip_t *) pv_api_ip;
4451
0
    ps_op = (ih264d_ctl_get_sei_fgc_params_op_t *) pv_api_op;
4452
0
    UNUSED(ps_ip);
4453
4454
0
    if(0 == ps_dec->s_sei_export.u1_sei_fgc_params_present_flag)
4455
0
    {
4456
0
        ps_op->u4_error_code = ERROR_SEI_FGC_PARAMS_NOT_FOUND;
4457
0
        return IV_FAIL;
4458
0
    }
4459
4460
0
    ps_sei_fgc = &ps_dec->s_sei_export.s_sei_fgc_params;
4461
4462
0
    ps_op->u1_film_grain_characteristics_cancel_flag =
4463
0
        ps_sei_fgc->u1_film_grain_characteristics_cancel_flag;
4464
4465
0
    if(0 == ps_op->u1_film_grain_characteristics_cancel_flag)
4466
0
    {
4467
0
        ps_op->i4_poc = ps_sei_fgc->i4_poc;
4468
0
        ps_op->u4_idr_pic_id = ps_sei_fgc->u4_idr_pic_id;
4469
0
        ps_op->u1_film_grain_model_id = ps_sei_fgc->u1_film_grain_model_id;
4470
0
        ps_op->u1_separate_colour_description_present_flag =
4471
0
            ps_sei_fgc->u1_separate_colour_description_present_flag;
4472
4473
0
        if(ps_op->u1_separate_colour_description_present_flag)
4474
0
        {
4475
0
            ps_op->u1_film_grain_bit_depth_luma_minus8 =
4476
0
                ps_sei_fgc->u1_film_grain_bit_depth_luma_minus8;
4477
0
            ps_op->u1_film_grain_bit_depth_chroma_minus8 =
4478
0
                ps_sei_fgc->u1_film_grain_bit_depth_chroma_minus8;
4479
0
            ps_op->u1_film_grain_full_range_flag = ps_sei_fgc->u1_film_grain_full_range_flag;
4480
0
            ps_op->u1_film_grain_colour_primaries = ps_sei_fgc->u1_film_grain_colour_primaries;
4481
0
            ps_op->u1_film_grain_transfer_characteristics =
4482
0
                ps_sei_fgc->u1_film_grain_transfer_characteristics;
4483
0
            ps_op->u1_film_grain_matrix_coefficients =
4484
0
                ps_sei_fgc->u1_film_grain_matrix_coefficients;
4485
0
        }
4486
0
        ps_op->u1_blending_mode_id = ps_sei_fgc->u1_blending_mode_id;
4487
0
        ps_op->u1_log2_scale_factor = ps_sei_fgc->u1_log2_scale_factor;
4488
4489
0
        for(c = 0; c < SEI_FGC_NUM_COLOUR_COMPONENTS; c++)
4490
0
        {
4491
0
            ps_op->au1_comp_model_present_flag[c] = ps_sei_fgc->au1_comp_model_present_flag[c];
4492
0
        }
4493
4494
0
        for(c = 0; c < SEI_FGC_NUM_COLOUR_COMPONENTS; c++)
4495
0
        {
4496
0
            if(ps_op->au1_comp_model_present_flag[c])
4497
0
            {
4498
0
                ps_op->au1_num_intensity_intervals_minus1[c] =
4499
0
                    ps_sei_fgc->au1_num_intensity_intervals_minus1[c];
4500
4501
0
                ps_op->au1_num_model_values_minus1[c] = ps_sei_fgc->au1_num_model_values_minus1[c];
4502
4503
0
                for(i = 0; i <= ps_op->au1_num_intensity_intervals_minus1[c]; i++)
4504
0
                {
4505
0
                    ps_op->au1_intensity_interval_lower_bound[c][i] =
4506
0
                        ps_sei_fgc->au1_intensity_interval_lower_bound[c][i];
4507
0
                    ps_op->au1_intensity_interval_upper_bound[c][i] =
4508
0
                        ps_sei_fgc->au1_intensity_interval_upper_bound[c][i];
4509
4510
0
                    for(j = 0; j <= ps_op->au1_num_model_values_minus1[c]; j++)
4511
0
                    {
4512
0
                        ps_op->ai4_comp_model_value[c][i][j] =
4513
0
                            ps_sei_fgc->ai4_comp_model_value[c][i][j];
4514
0
                    }
4515
0
                }
4516
0
            }
4517
0
        }
4518
0
        ps_op->u4_film_grain_characteristics_repetition_period =
4519
0
            ps_sei_fgc->u4_film_grain_characteristics_repetition_period;
4520
0
    }
4521
0
    return IV_SUCCESS;
4522
0
}
4523
4524
WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4525
359
{
4526
359
    ih264d_ctl_set_num_cores_ip_t *ps_ip;
4527
359
    ih264d_ctl_set_num_cores_op_t *ps_op;
4528
359
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4529
4530
359
    ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
4531
359
    ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
4532
359
    ps_op->u4_error_code = 0;
4533
359
    ps_dec->u4_num_cores = ps_ip->u4_num_cores;
4534
359
    if(ps_dec->u4_num_cores == 1)
4535
159
    {
4536
159
        ps_dec->u1_separate_parse = 0;
4537
159
    }
4538
200
    else
4539
200
    {
4540
200
        ps_dec->u1_separate_parse = 1;
4541
200
    }
4542
4543
    /*using only upto three threads currently*/
4544
359
    if(ps_dec->u4_num_cores > 3)
4545
84
        ps_dec->u4_num_cores = 3;
4546
4547
359
    return IV_SUCCESS;
4548
359
}
4549
4550
void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
4551
                                            ivd_video_decode_op_t *ps_dec_op)
4552
10.4k
{
4553
10.4k
    if((ps_dec_op->u4_error_code & 0xff)
4554
10.4k
                    != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
4555
10.4k
    {
4556
10.4k
        ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
4557
10.4k
        ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
4558
10.4k
    }
4559
10.4k
    ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
4560
10.4k
    ps_dec_op->i4_display_index = ps_dec->i4_display_index;
4561
10.4k
    ps_dec_op->e_pic_type = ps_dec->i4_frametype;
4562
4563
10.4k
    ps_dec_op->u4_new_seq = 0;
4564
10.4k
    ps_dec_op->u4_output_present = ps_dec->u4_output_present;
4565
10.4k
    ps_dec_op->u4_progressive_frame_flag =
4566
10.4k
                    ps_dec->s_disp_op.u4_progressive_frame_flag;
4567
4568
10.4k
    ps_dec_op->u4_is_ref_flag = 1;
4569
10.4k
    if(ps_dec_op->u4_frame_decoded_flag)
4570
6.66k
    {
4571
6.66k
        if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0)
4572
3.66k
            ps_dec_op->u4_is_ref_flag = 0;
4573
6.66k
    }
4574
4575
10.4k
    ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format;
4576
10.4k
    ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
4577
10.4k
    ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
4578
10.4k
    ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
4579
10.4k
    ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
4580
4581
10.4k
    ih264d_export_sei_params(&ps_dec_op->s_sei_decode_op, ps_dec);
4582
10.4k
}
4583
4584
/*****************************************************************************/
4585
/*                                                                           */
4586
/*  Function Name : ih264d_api_function                                      */
4587
/*                                                                           */
4588
/*  Description   :                                                          */
4589
/*                                                                           */
4590
/*  Inputs        :iv_obj_t decoder handle                                   */
4591
/*                :pv_api_ip pointer to input structure                      */
4592
/*                :pv_api_op pointer to output structure                     */
4593
/*  Outputs       :                                                          */
4594
/*  Returns       : void                                                     */
4595
/*                                                                           */
4596
/*  Issues        : none                                                     */
4597
/*                                                                           */
4598
/*  Revision History:                                                        */
4599
/*                                                                           */
4600
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4601
/*         22 10 2008    100356         Draft                                */
4602
/*                                                                           */
4603
/*****************************************************************************/
4604
IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl,
4605
                                              void *pv_api_ip,
4606
                                              void *pv_api_op)
4607
19.7k
{
4608
19.7k
    UWORD32 command;
4609
19.7k
    UWORD32 *pu2_ptr_cmd;
4610
19.7k
    UWORD32 u4_api_ret;
4611
19.7k
    IV_API_CALL_STATUS_T e_status;
4612
19.7k
    e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op);
4613
4614
19.7k
    if(e_status != IV_SUCCESS)
4615
0
    {
4616
0
        UWORD32 *ptr_err;
4617
4618
0
        ptr_err = (UWORD32 *)pv_api_op;
4619
0
        UNUSED(ptr_err);
4620
0
        H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1));
4621
0
        return IV_FAIL;
4622
0
    }
4623
4624
19.7k
    pu2_ptr_cmd = (UWORD32 *)pv_api_ip;
4625
19.7k
    pu2_ptr_cmd++;
4626
4627
19.7k
    command = *pu2_ptr_cmd;
4628
//    H264_DEC_DEBUG_PRINT("inside lib = %d\n",command);
4629
19.7k
    switch(command)
4630
19.7k
    {
4631
4632
359
        case IVD_CMD_CREATE:
4633
359
            u4_api_ret = ih264d_create(dec_hdl, (void *)pv_api_ip,
4634
359
                                     (void *)pv_api_op);
4635
359
            break;
4636
359
        case IVD_CMD_DELETE:
4637
359
            u4_api_ret = ih264d_delete(dec_hdl, (void *)pv_api_ip,
4638
359
                                     (void *)pv_api_op);
4639
359
            break;
4640
4641
16.1k
        case IVD_CMD_VIDEO_DECODE:
4642
16.1k
            u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip,
4643
16.1k
                                             (void *)pv_api_op);
4644
16.1k
            break;
4645
4646
0
        case IVD_CMD_GET_DISPLAY_FRAME:
4647
0
            u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip,
4648
0
                                                  (void *)pv_api_op);
4649
4650
0
            break;
4651
4652
0
        case IVD_CMD_SET_DISPLAY_FRAME:
4653
0
            u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip,
4654
0
                                                  (void *)pv_api_op);
4655
4656
0
            break;
4657
4658
0
        case IVD_CMD_REL_DISPLAY_FRAME:
4659
0
            u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip,
4660
0
                                                  (void *)pv_api_op);
4661
0
            break;
4662
4663
2.87k
        case IVD_CMD_VIDEO_CTL:
4664
2.87k
            u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip,
4665
2.87k
                                    (void *)pv_api_op);
4666
2.87k
            break;
4667
0
        default:
4668
0
            u4_api_ret = IV_FAIL;
4669
0
            break;
4670
19.7k
    }
4671
4672
19.7k
    return u4_api_ret;
4673
19.7k
}