Coverage Report

Created: 2026-10-17 07:28

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/libavc/decoder/ih264d_api.c
Line
Count
Source
1
/******************************************************************************
2
 *
3
 * Copyright (C) 2015 The Android Open Source Project
4
 *
5
 * Licensed under the Apache License, Version 2.0 (the "License");
6
 * you may not use this file except in compliance with the License.
7
 * You may obtain a copy of the License at:
8
 *
9
 * http://www.apache.org/licenses/LICENSE-2.0
10
 *
11
 * Unless required by applicable law or agreed to in writing, software
12
 * distributed under the License is distributed on an "AS IS" BASIS,
13
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14
 * See the License for the specific language governing permissions and
15
 * limitations under the License.
16
 *
17
 *****************************************************************************
18
 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19
*/
20
21
/*****************************************************************************/
22
/*                                                                           */
23
/*  File Name         : ih264d_api.c                                         */
24
/*                                                                           */
25
/*  Description       : Has all  API related functions                       */
26
/*                                                                           */
27
/*                                                                           */
28
/*  List of Functions : api_check_struct_sanity                              */
29
/*          ih264d_set_processor                                             */
30
/*          ih264d_create                                                    */
31
/*          ih264d_delete                                                    */
32
/*          ih264d_init                                                      */
33
/*          ih264d_map_error                                                 */
34
/*          ih264d_video_decode                                              */
35
/*          ih264d_get_version                                               */
36
/*          ih264d_get_display_frame                                         */
37
/*          ih264d_set_display_frame                                         */
38
/*          ih264d_set_flush_mode                                            */
39
/*          ih264d_get_status                                                */
40
/*          ih264d_get_buf_info                                              */
41
/*          ih264d_set_params                                                */
42
/*          ih264d_set_default_params                                        */
43
/*          ih264d_reset                                                     */
44
/*          ih264d_ctl                                                       */
45
/*          ih264d_rel_display_frame                                         */
46
/*          ih264d_set_degrade                                               */
47
/*          ih264d_get_frame_dimensions                                      */
48
/*          ih264d_set_num_cores                                             */
49
/*          ih264d_fill_output_struct_from_context                           */
50
/*          ih264d_api_function                                              */
51
/*                                                                           */
52
/*  Issues / Problems : None                                                 */
53
/*                                                                           */
54
/*  Revision History  :                                                      */
55
/*                                                                           */
56
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
57
/*         14 10 2008   100356(SKV)     Draft                                */
58
/*                                                                           */
59
/*****************************************************************************/
60
#include "ih264_typedefs.h"
61
#include "ih264_macros.h"
62
#include "ih264_platform_macros.h"
63
#include "ih264d_tables.h"
64
#include "iv.h"
65
#include "ivd.h"
66
#include "ih264d.h"
67
#include "ih264d_defs.h"
68
69
#include <string.h>
70
#include <limits.h>
71
#include <stddef.h>
72
73
#include "ih264d_inter_pred.h"
74
75
#include "ih264d_structs.h"
76
#include "ih264d_nal.h"
77
#include "ih264d_error_handler.h"
78
79
#include "ih264d_defs.h"
80
81
#include "ithread.h"
82
#include "ih264d_parse_slice.h"
83
#include "ih264d_function_selector.h"
84
#include "ih264_error.h"
85
#include "ih264_disp_mgr.h"
86
#include "ih264_buf_mgr.h"
87
#include "ih264d_deblocking.h"
88
#include "ih264d_parse_cavlc.h"
89
#include "ih264d_parse_cabac.h"
90
#include "ih264d_utils.h"
91
#include "ih264d_format_conv.h"
92
#include "ih264d_parse_headers.h"
93
#include "ih264d_thread_compute_bs.h"
94
#include <assert.h>
95
96
97
/*********************/
98
/* Codec Versioning  */
99
/*********************/
100
//Move this to where it is used
101
#define CODEC_NAME              "H264VDEC"
102
#define CODEC_RELEASE_TYPE      "production"
103
#define CODEC_RELEASE_VER       "05.00"
104
#define CODEC_VENDOR            "ITTIAM"
105
0
#define MAXVERSION_STRLEN       511
106
#ifdef ANDROID
107
#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor)    \
108
    snprintf(version_string, MAXVERSION_STRLEN,                                                     \
109
             "@(#)Id:%s_%s Ver:%s Released by %s",                                                  \
110
             codec_name, codec_release_type, codec_release_ver, codec_vendor)
111
#else
112
#define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor)    \
113
0
    snprintf(version_string, MAXVERSION_STRLEN,                                                     \
114
0
             "@(#)Id:%s_%s Ver:%s Released by %s Build: %s @ %s",                                   \
115
0
             codec_name, codec_release_type, codec_release_ver, codec_vendor, __DATE__, __TIME__)
116
#endif
117
118
119
0
#define MIN_IN_BUFS             1
120
7.17k
#define MIN_OUT_BUFS_420        3
121
2.14k
#define MIN_OUT_BUFS_422ILE     1
122
1.01k
#define MIN_OUT_BUFS_RGB565     1
123
5.63k
#define MIN_OUT_BUFS_420SP      2
124
125
#define NUM_FRAMES_LIMIT_ENABLED 0
126
127
#if NUM_FRAMES_LIMIT_ENABLED
128
#define NUM_FRAMES_LIMIT 10000
129
#else
130
14.1k
#define NUM_FRAMES_LIMIT 0x7FFFFFFF
131
#endif
132
133
134
UWORD32 ih264d_get_extra_mem_external(UWORD32 width, UWORD32 height);
135
WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
136
                                   void *pv_api_ip,
137
                                   void *pv_api_op);
138
WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
139
                             void *pv_api_ip,
140
                             void *pv_api_op);
141
142
WORD32 ih264d_get_sei_mdcv_params(iv_obj_t *dec_hdl,
143
                                  void *pv_api_ip,
144
                                  void *pv_api_op);
145
146
WORD32 ih264d_get_sei_cll_params(iv_obj_t *dec_hdl,
147
                                 void *pv_api_ip,
148
                                 void *pv_api_op);
149
150
WORD32 ih264d_get_sei_ave_params(iv_obj_t *dec_hdl,
151
                                 void *pv_api_ip,
152
                                 void *pv_api_op);
153
154
WORD32 ih264d_get_sei_ccv_params(iv_obj_t *dec_hdl,
155
                                 void *pv_api_ip,
156
                                 void *pv_api_op);
157
158
WORD32 ih264d_get_sei_sii_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
159
160
WORD32 ih264d_get_sei_fgc_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
161
162
WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op);
163
164
WORD32 ih264d_deblock_display(dec_struct_t *ps_dec);
165
166
void ih264d_signal_decode_thread(dec_struct_t *ps_dec);
167
168
void ih264d_signal_bs_deblk_thread(dec_struct_t *ps_dec);
169
void ih264d_decode_picture_thread(dec_struct_t *ps_dec);
170
171
WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
172
                          void *pv_api_ip,
173
                          void *pv_api_op);
174
175
void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
176
                                            ivd_video_decode_op_t *ps_dec_op);
177
178
/*!
179
 **************************************************************************
180
 * \if Function name : ih264d_export_sei_params \endif
181
 *
182
 * \brief
183
 *    Exports sei params from decoder to application.
184
 *
185
 * \return
186
 *    0 on Success and error code otherwise
187
 **************************************************************************
188
 */
189
190
void ih264d_export_sei_params(ivd_sei_decode_op_t *ps_sei_decode_op, dec_struct_t *ps_dec)
191
17.3k
{
192
17.3k
    WORD32 i4_status = IV_SUCCESS;
193
17.3k
    sei *ps_sei = (sei *)ps_dec->pv_disp_sei_params;
194
195
17.3k
    i4_status = ih264d_export_sei_mdcv_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
196
17.3k
    i4_status = ih264d_export_sei_cll_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
197
17.3k
    i4_status = ih264d_export_sei_ave_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
198
17.3k
    i4_status = ih264d_export_sei_ccv_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
199
17.3k
    i4_status = ih264d_export_sei_sii_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
200
17.3k
    i4_status = ih264d_export_sei_fgc_params(ps_sei_decode_op, ps_sei, &ps_dec->s_sei_export);
201
202
17.3k
    UNUSED(i4_status);
203
17.3k
}
204
205
static IV_API_CALL_STATUS_T api_check_struct_sanity(iv_obj_t *ps_handle,
206
                                                    void *pv_api_ip,
207
                                                    void *pv_api_op)
208
17.6k
{
209
17.6k
    IVD_API_COMMAND_TYPE_T e_cmd;
210
17.6k
    UWORD32 *pu4_api_ip;
211
17.6k
    UWORD32 *pu4_api_op;
212
17.6k
    UWORD32 i, j;
213
214
17.6k
    if(NULL == pv_api_op)
215
0
        return (IV_FAIL);
216
217
17.6k
    if(NULL == pv_api_ip)
218
0
        return (IV_FAIL);
219
220
17.6k
    pu4_api_ip = (UWORD32 *)pv_api_ip;
221
17.6k
    pu4_api_op = (UWORD32 *)pv_api_op;
222
17.6k
    e_cmd = *(pu4_api_ip + 1);
223
224
    /* error checks on handle */
225
17.6k
    switch((WORD32)e_cmd)
226
17.6k
    {
227
308
        case IVD_CMD_CREATE:
228
308
            break;
229
230
0
        case IVD_CMD_REL_DISPLAY_FRAME:
231
0
        case IVD_CMD_SET_DISPLAY_FRAME:
232
0
        case IVD_CMD_GET_DISPLAY_FRAME:
233
14.3k
        case IVD_CMD_VIDEO_DECODE:
234
14.6k
        case IVD_CMD_DELETE:
235
17.3k
        case IVD_CMD_VIDEO_CTL:
236
17.3k
            if(ps_handle == NULL)
237
205
            {
238
205
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
239
205
                *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
240
205
                return IV_FAIL;
241
205
            }
242
243
17.1k
            if(ps_handle->u4_size != sizeof(iv_obj_t))
244
0
            {
245
0
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
246
0
                *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
247
0
                return IV_FAIL;
248
0
            }
249
250
17.1k
            if(ps_handle->pv_fxns != ih264d_api_function)
251
0
            {
252
0
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
253
0
                *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
254
0
                return IV_FAIL;
255
0
            }
256
257
17.1k
            if(ps_handle->pv_codec_handle == NULL)
258
0
            {
259
0
                *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
260
0
                *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
261
0
                return IV_FAIL;
262
0
            }
263
17.1k
            break;
264
17.1k
        default:
265
0
            *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
266
0
            *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
267
0
            return IV_FAIL;
268
17.6k
    }
269
270
17.4k
    switch((WORD32)e_cmd)
271
17.4k
    {
272
308
        case IVD_CMD_CREATE:
273
308
        {
274
308
            ih264d_create_ip_t *ps_ip = (ih264d_create_ip_t *)pv_api_ip;
275
308
            ih264d_create_op_t *ps_op = (ih264d_create_op_t *)pv_api_op;
276
277
278
308
            ps_op->s_ivd_create_op_t.u4_error_code = 0;
279
280
308
            if((ps_ip->s_ivd_create_ip_t.u4_size > sizeof(ih264d_create_ip_t))
281
308
                            || (ps_ip->s_ivd_create_ip_t.u4_size
282
308
                                            < sizeof(ivd_create_ip_t)))
283
0
            {
284
0
                ps_op->s_ivd_create_op_t.u4_error_code |= 1
285
0
                                << IVD_UNSUPPORTEDPARAM;
286
0
                ps_op->s_ivd_create_op_t.u4_error_code |=
287
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
288
0
                H264_DEC_DEBUG_PRINT("\n");
289
0
                return (IV_FAIL);
290
0
            }
291
292
308
            if((ps_op->s_ivd_create_op_t.u4_size != sizeof(ih264d_create_op_t))
293
0
                            && (ps_op->s_ivd_create_op_t.u4_size
294
0
                                            != sizeof(ivd_create_op_t)))
295
0
            {
296
0
                ps_op->s_ivd_create_op_t.u4_error_code |= 1
297
0
                                << IVD_UNSUPPORTEDPARAM;
298
0
                ps_op->s_ivd_create_op_t.u4_error_code |=
299
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
300
0
                H264_DEC_DEBUG_PRINT("\n");
301
0
                return (IV_FAIL);
302
0
            }
303
304
305
308
            if((ps_ip->s_ivd_create_ip_t.e_output_format != IV_YUV_420P)
306
236
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
307
236
                                            != IV_YUV_422ILE)
308
166
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
309
166
                                            != IV_RGB_565)
310
113
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
311
113
                                            != IV_YUV_420SP_UV)
312
59
                            && (ps_ip->s_ivd_create_ip_t.e_output_format
313
59
                                            != IV_YUV_420SP_VU))
314
1
            {
315
1
                ps_op->s_ivd_create_op_t.u4_error_code |= 1
316
1
                                << IVD_UNSUPPORTEDPARAM;
317
1
                ps_op->s_ivd_create_op_t.u4_error_code |=
318
1
                                IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
319
1
                H264_DEC_DEBUG_PRINT("\n");
320
1
                return (IV_FAIL);
321
1
            }
322
323
308
        }
324
307
            break;
325
326
307
        case IVD_CMD_GET_DISPLAY_FRAME:
327
0
        {
328
0
            ih264d_get_display_frame_ip_t *ps_ip =
329
0
                            (ih264d_get_display_frame_ip_t *)pv_api_ip;
330
0
            ih264d_get_display_frame_op_t *ps_op =
331
0
                            (ih264d_get_display_frame_op_t *)pv_api_op;
332
333
0
            ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
334
335
0
            if((ps_ip->s_ivd_get_display_frame_ip_t.u4_size
336
0
                            != sizeof(ih264d_get_display_frame_ip_t))
337
0
                            && (ps_ip->s_ivd_get_display_frame_ip_t.u4_size
338
0
                                            != sizeof(ivd_get_display_frame_ip_t)))
339
0
            {
340
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
341
0
                                << IVD_UNSUPPORTEDPARAM;
342
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
343
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
344
0
                return (IV_FAIL);
345
0
            }
346
347
0
            if((ps_op->s_ivd_get_display_frame_op_t.u4_size
348
0
                            != sizeof(ih264d_get_display_frame_op_t))
349
0
                            && (ps_op->s_ivd_get_display_frame_op_t.u4_size
350
0
                                            != sizeof(ivd_get_display_frame_op_t)))
351
0
            {
352
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1
353
0
                                << IVD_UNSUPPORTEDPARAM;
354
0
                ps_op->s_ivd_get_display_frame_op_t.u4_error_code |=
355
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
356
0
                return (IV_FAIL);
357
0
            }
358
0
        }
359
0
            break;
360
361
0
        case IVD_CMD_REL_DISPLAY_FRAME:
362
0
        {
363
0
            ih264d_rel_display_frame_ip_t *ps_ip =
364
0
                            (ih264d_rel_display_frame_ip_t *)pv_api_ip;
365
0
            ih264d_rel_display_frame_op_t *ps_op =
366
0
                            (ih264d_rel_display_frame_op_t *)pv_api_op;
367
368
0
            ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
369
370
0
            if((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
371
0
                            != sizeof(ih264d_rel_display_frame_ip_t))
372
0
                            && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size
373
0
                                            != sizeof(ivd_rel_display_frame_ip_t)))
374
0
            {
375
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
376
0
                                << IVD_UNSUPPORTEDPARAM;
377
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
378
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
379
0
                return (IV_FAIL);
380
0
            }
381
382
0
            if((ps_op->s_ivd_rel_display_frame_op_t.u4_size
383
0
                            != sizeof(ih264d_rel_display_frame_op_t))
384
0
                            && (ps_op->s_ivd_rel_display_frame_op_t.u4_size
385
0
                                            != sizeof(ivd_rel_display_frame_op_t)))
386
0
            {
387
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1
388
0
                                << IVD_UNSUPPORTEDPARAM;
389
0
                ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |=
390
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
391
0
                return (IV_FAIL);
392
0
            }
393
394
0
        }
395
0
            break;
396
397
0
        case IVD_CMD_SET_DISPLAY_FRAME:
398
0
        {
399
0
            ih264d_set_display_frame_ip_t *ps_ip =
400
0
                            (ih264d_set_display_frame_ip_t *)pv_api_ip;
401
0
            ih264d_set_display_frame_op_t *ps_op =
402
0
                            (ih264d_set_display_frame_op_t *)pv_api_op;
403
0
            UWORD32 j;
404
405
0
            ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
406
407
0
            if((ps_ip->s_ivd_set_display_frame_ip_t.u4_size
408
0
                            != sizeof(ih264d_set_display_frame_ip_t))
409
0
                            && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size
410
0
                                            != sizeof(ivd_set_display_frame_ip_t)))
411
0
            {
412
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
413
0
                                << IVD_UNSUPPORTEDPARAM;
414
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
415
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
416
0
                return (IV_FAIL);
417
0
            }
418
419
0
            if((ps_op->s_ivd_set_display_frame_op_t.u4_size
420
0
                            != sizeof(ih264d_set_display_frame_op_t))
421
0
                            && (ps_op->s_ivd_set_display_frame_op_t.u4_size
422
0
                                            != sizeof(ivd_set_display_frame_op_t)))
423
0
            {
424
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
425
0
                                << IVD_UNSUPPORTEDPARAM;
426
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
427
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
428
0
                return (IV_FAIL);
429
0
            }
430
431
0
            if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
432
0
            {
433
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
434
0
                                << IVD_UNSUPPORTEDPARAM;
435
0
                ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
436
0
                                IVD_DISP_FRM_ZERO_OP_BUFS;
437
0
                return IV_FAIL;
438
0
            }
439
440
0
            for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs;
441
0
                            j++)
442
0
            {
443
0
                if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs
444
0
                                == 0)
445
0
                {
446
0
                    ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
447
0
                                    << IVD_UNSUPPORTEDPARAM;
448
0
                    ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
449
0
                                    IVD_DISP_FRM_ZERO_OP_BUFS;
450
0
                    return IV_FAIL;
451
0
                }
452
453
0
                for(i = 0;
454
0
                                i
455
0
                                                < ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;
456
0
                                i++)
457
0
                {
458
0
                    if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i]
459
0
                                    == NULL)
460
0
                    {
461
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
462
0
                                        << IVD_UNSUPPORTEDPARAM;
463
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
464
0
                                        IVD_DISP_FRM_OP_BUF_NULL;
465
0
                        return IV_FAIL;
466
0
                    }
467
468
0
                    if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i]
469
0
                                    == 0)
470
0
                    {
471
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1
472
0
                                        << IVD_UNSUPPORTEDPARAM;
473
0
                        ps_op->s_ivd_set_display_frame_op_t.u4_error_code |=
474
0
                                        IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
475
0
                        return IV_FAIL;
476
0
                    }
477
0
                }
478
0
            }
479
0
        }
480
0
            break;
481
482
14.1k
        case IVD_CMD_VIDEO_DECODE:
483
14.1k
        {
484
14.1k
            ih264d_video_decode_ip_t *ps_ip =
485
14.1k
                            (ih264d_video_decode_ip_t *)pv_api_ip;
486
14.1k
            ih264d_video_decode_op_t *ps_op =
487
14.1k
                            (ih264d_video_decode_op_t *)pv_api_op;
488
489
14.1k
            H264_DEC_DEBUG_PRINT("The input bytes is: %d",
490
14.1k
                                 ps_ip->s_ivd_video_decode_ip_t.u4_num_Bytes);
491
14.1k
            ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
492
493
14.1k
            if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(ih264d_video_decode_ip_t) &&
494
14.1k
               ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(ivd_video_decode_ip_t) &&
495
0
               ps_ip->s_ivd_video_decode_ip_t.u4_size !=
496
0
                   offsetof(ivd_video_decode_ip_t, s_out_buffer))
497
0
            {
498
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
499
0
                                << IVD_UNSUPPORTEDPARAM;
500
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |=
501
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
502
0
                return (IV_FAIL);
503
0
            }
504
505
14.1k
            if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(ih264d_video_decode_op_t) &&
506
14.1k
               ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(ivd_video_decode_op_t) &&
507
0
               ps_op->s_ivd_video_decode_op_t.u4_size !=
508
0
                   offsetof(ivd_video_decode_op_t, u4_output_present))
509
0
            {
510
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
511
0
                                << IVD_UNSUPPORTEDPARAM;
512
0
                ps_op->s_ivd_video_decode_op_t.u4_error_code |=
513
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
514
0
                return (IV_FAIL);
515
0
            }
516
517
14.1k
            {
518
14.1k
                dec_struct_t *ps_dec = (dec_struct_t *)(ps_handle->pv_codec_handle);
519
14.1k
                if(ps_dec->u1_enable_mb_info)
520
0
                {
521
0
                    if(!ps_ip->pu1_8x8_blk_qp_map && !ps_ip->pu1_8x8_blk_type_map)
522
0
                    {
523
0
                        ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1
524
0
                                        << IVD_UNSUPPORTEDPARAM;
525
0
                        ps_op->s_ivd_video_decode_op_t.u4_error_code |=
526
0
                                        IH264D_FRAME_INFO_OP_BUF_NULL;
527
0
                        return IV_FAIL;
528
0
                    }
529
0
                }
530
14.1k
            }
531
14.1k
        }
532
14.1k
            break;
533
534
14.1k
        case IVD_CMD_DELETE:
535
307
        {
536
307
            ih264d_delete_ip_t *ps_ip =
537
307
                            (ih264d_delete_ip_t *)pv_api_ip;
538
307
            ih264d_delete_op_t *ps_op =
539
307
                            (ih264d_delete_op_t *)pv_api_op;
540
541
307
            ps_op->s_ivd_delete_op_t.u4_error_code = 0;
542
543
307
            if(ps_ip->s_ivd_delete_ip_t.u4_size
544
307
                            != sizeof(ih264d_delete_ip_t))
545
0
            {
546
0
                ps_op->s_ivd_delete_op_t.u4_error_code |= 1
547
0
                                << IVD_UNSUPPORTEDPARAM;
548
0
                ps_op->s_ivd_delete_op_t.u4_error_code |=
549
0
                                IVD_IP_API_STRUCT_SIZE_INCORRECT;
550
0
                return (IV_FAIL);
551
0
            }
552
553
307
            if(ps_op->s_ivd_delete_op_t.u4_size
554
307
                            != sizeof(ih264d_delete_op_t))
555
0
            {
556
0
                ps_op->s_ivd_delete_op_t.u4_error_code |= 1
557
0
                                << IVD_UNSUPPORTEDPARAM;
558
0
                ps_op->s_ivd_delete_op_t.u4_error_code |=
559
0
                                IVD_OP_API_STRUCT_SIZE_INCORRECT;
560
0
                return (IV_FAIL);
561
0
            }
562
563
307
        }
564
307
            break;
565
566
2.66k
        case IVD_CMD_VIDEO_CTL:
567
2.66k
        {
568
2.66k
            UWORD32 *pu4_ptr_cmd;
569
2.66k
            UWORD32 sub_command;
570
571
2.66k
            pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
572
2.66k
            pu4_ptr_cmd += 2;
573
2.66k
            sub_command = *pu4_ptr_cmd;
574
575
2.66k
            switch(sub_command)
576
2.66k
            {
577
614
                case IVD_CMD_CTL_SETPARAMS:
578
614
                {
579
614
                    ih264d_ctl_set_config_ip_t *ps_ip;
580
614
                    ih264d_ctl_set_config_op_t *ps_op;
581
614
                    ps_ip = (ih264d_ctl_set_config_ip_t *)pv_api_ip;
582
614
                    ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
583
584
614
                    if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size
585
614
                                    != sizeof(ih264d_ctl_set_config_ip_t))
586
0
                    {
587
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
588
0
                                        << IVD_UNSUPPORTEDPARAM;
589
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
590
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
591
0
                        return IV_FAIL;
592
0
                    }
593
614
                }
594
                    //no break; is needed here
595
614
                case IVD_CMD_CTL_SETDEFAULT:
596
614
                {
597
614
                    ih264d_ctl_set_config_op_t *ps_op;
598
614
                    ps_op = (ih264d_ctl_set_config_op_t *)pv_api_op;
599
614
                    if(ps_op->s_ivd_ctl_set_config_op_t.u4_size
600
614
                                    != sizeof(ih264d_ctl_set_config_op_t))
601
0
                    {
602
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1
603
0
                                        << IVD_UNSUPPORTEDPARAM;
604
0
                        ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |=
605
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
606
0
                        return IV_FAIL;
607
0
                    }
608
614
                }
609
614
                    break;
610
611
614
                case IVD_CMD_CTL_GETPARAMS:
612
0
                {
613
0
                    ih264d_ctl_getstatus_ip_t *ps_ip;
614
0
                    ih264d_ctl_getstatus_op_t *ps_op;
615
616
0
                    ps_ip = (ih264d_ctl_getstatus_ip_t *)pv_api_ip;
617
0
                    ps_op = (ih264d_ctl_getstatus_op_t *)pv_api_op;
618
0
                    if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size
619
0
                                    != sizeof(ih264d_ctl_getstatus_ip_t))
620
0
                    {
621
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
622
0
                                        << IVD_UNSUPPORTEDPARAM;
623
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
624
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
625
0
                        return IV_FAIL;
626
0
                    }
627
0
                    if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size
628
0
                                    != sizeof(ih264d_ctl_getstatus_op_t))
629
0
                    {
630
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1
631
0
                                        << IVD_UNSUPPORTEDPARAM;
632
0
                        ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |=
633
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
634
0
                        return IV_FAIL;
635
0
                    }
636
0
                }
637
0
                    break;
638
639
0
                case IVD_CMD_CTL_GETBUFINFO:
640
0
                {
641
0
                    ih264d_ctl_getbufinfo_ip_t *ps_ip;
642
0
                    ih264d_ctl_getbufinfo_op_t *ps_op;
643
0
                    ps_ip = (ih264d_ctl_getbufinfo_ip_t *)pv_api_ip;
644
0
                    ps_op = (ih264d_ctl_getbufinfo_op_t *)pv_api_op;
645
646
0
                    if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size
647
0
                                    != sizeof(ih264d_ctl_getbufinfo_ip_t))
648
0
                    {
649
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
650
0
                                        << IVD_UNSUPPORTEDPARAM;
651
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
652
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
653
0
                        return IV_FAIL;
654
0
                    }
655
0
                    if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size
656
0
                                    != sizeof(ih264d_ctl_getbufinfo_op_t))
657
0
                    {
658
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1
659
0
                                        << IVD_UNSUPPORTEDPARAM;
660
0
                        ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |=
661
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
662
0
                        return IV_FAIL;
663
0
                    }
664
0
                }
665
0
                    break;
666
667
0
                case IVD_CMD_CTL_GETVERSION:
668
0
                {
669
0
                    ih264d_ctl_getversioninfo_ip_t *ps_ip;
670
0
                    ih264d_ctl_getversioninfo_op_t *ps_op;
671
0
                    ps_ip = (ih264d_ctl_getversioninfo_ip_t *)pv_api_ip;
672
0
                    ps_op = (ih264d_ctl_getversioninfo_op_t *)pv_api_op;
673
0
                    if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size
674
0
                                    != sizeof(ih264d_ctl_getversioninfo_ip_t))
675
0
                    {
676
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
677
0
                                        << IVD_UNSUPPORTEDPARAM;
678
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
679
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
680
0
                        return IV_FAIL;
681
0
                    }
682
0
                    if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size
683
0
                                    != sizeof(ih264d_ctl_getversioninfo_op_t))
684
0
                    {
685
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1
686
0
                                        << IVD_UNSUPPORTEDPARAM;
687
0
                        ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |=
688
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
689
0
                        return IV_FAIL;
690
0
                    }
691
0
                }
692
0
                    break;
693
694
0
                case IVD_CMD_CTL_FLUSH:
695
0
                {
696
0
                    ih264d_ctl_flush_ip_t *ps_ip;
697
0
                    ih264d_ctl_flush_op_t *ps_op;
698
0
                    ps_ip = (ih264d_ctl_flush_ip_t *)pv_api_ip;
699
0
                    ps_op = (ih264d_ctl_flush_op_t *)pv_api_op;
700
0
                    if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size
701
0
                                    != sizeof(ih264d_ctl_flush_ip_t))
702
0
                    {
703
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
704
0
                                        << IVD_UNSUPPORTEDPARAM;
705
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
706
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
707
0
                        return IV_FAIL;
708
0
                    }
709
0
                    if(ps_op->s_ivd_ctl_flush_op_t.u4_size
710
0
                                    != sizeof(ih264d_ctl_flush_op_t))
711
0
                    {
712
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1
713
0
                                        << IVD_UNSUPPORTEDPARAM;
714
0
                        ps_op->s_ivd_ctl_flush_op_t.u4_error_code |=
715
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
716
0
                        return IV_FAIL;
717
0
                    }
718
0
                }
719
0
                    break;
720
721
1.43k
                case IVD_CMD_CTL_RESET:
722
1.43k
                {
723
1.43k
                    ih264d_ctl_reset_ip_t *ps_ip;
724
1.43k
                    ih264d_ctl_reset_op_t *ps_op;
725
1.43k
                    ps_ip = (ih264d_ctl_reset_ip_t *)pv_api_ip;
726
1.43k
                    ps_op = (ih264d_ctl_reset_op_t *)pv_api_op;
727
1.43k
                    if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size
728
1.43k
                                    != sizeof(ih264d_ctl_reset_ip_t))
729
0
                    {
730
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
731
0
                                        << IVD_UNSUPPORTEDPARAM;
732
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
733
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
734
0
                        return IV_FAIL;
735
0
                    }
736
1.43k
                    if(ps_op->s_ivd_ctl_reset_op_t.u4_size
737
1.43k
                                    != sizeof(ih264d_ctl_reset_op_t))
738
0
                    {
739
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1
740
0
                                        << IVD_UNSUPPORTEDPARAM;
741
0
                        ps_op->s_ivd_ctl_reset_op_t.u4_error_code |=
742
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
743
0
                        return IV_FAIL;
744
0
                    }
745
1.43k
                }
746
1.43k
                    break;
747
748
1.43k
                case IH264D_CMD_CTL_DEGRADE:
749
0
                {
750
0
                    ih264d_ctl_degrade_ip_t *ps_ip;
751
0
                    ih264d_ctl_degrade_op_t *ps_op;
752
753
0
                    ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
754
0
                    ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
755
756
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_degrade_ip_t))
757
0
                    {
758
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
759
0
                        ps_op->u4_error_code |=
760
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
761
0
                        return IV_FAIL;
762
0
                    }
763
764
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_degrade_op_t))
765
0
                    {
766
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
767
0
                        ps_op->u4_error_code |=
768
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
769
0
                        return IV_FAIL;
770
0
                    }
771
772
0
                    if((ps_ip->i4_degrade_pics < 0)
773
0
                                    || (ps_ip->i4_degrade_pics > 4)
774
0
                                    || (ps_ip->i4_nondegrade_interval < 0)
775
0
                                    || (ps_ip->i4_degrade_type < 0)
776
0
                                    || (ps_ip->i4_degrade_type > 15))
777
0
                    {
778
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
779
0
                        return IV_FAIL;
780
0
                    }
781
782
0
                    break;
783
0
                }
784
785
0
                case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
786
0
                {
787
0
                    ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
788
0
                    ih264d_ctl_get_frame_dimensions_op_t *ps_op;
789
790
0
                    ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
791
0
                    ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
792
793
0
                    if(ps_ip->u4_size
794
0
                                    != sizeof(ih264d_ctl_get_frame_dimensions_ip_t))
795
0
                    {
796
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
797
0
                        ps_op->u4_error_code |=
798
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
799
0
                        return IV_FAIL;
800
0
                    }
801
802
0
                    if(ps_op->u4_size
803
0
                                    != sizeof(ih264d_ctl_get_frame_dimensions_op_t))
804
0
                    {
805
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
806
0
                        ps_op->u4_error_code |=
807
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
808
0
                        return IV_FAIL;
809
0
                    }
810
811
0
                    break;
812
0
                }
813
0
                case IH264D_CMD_CTL_GET_VUI_PARAMS:
814
0
                {
815
0
                    ih264d_ctl_get_vui_params_ip_t *ps_ip;
816
0
                    ih264d_ctl_get_vui_params_op_t *ps_op;
817
818
0
                    ps_ip =
819
0
                                    (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
820
0
                    ps_op =
821
0
                                    (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
822
823
0
                    if(ps_ip->u4_size
824
0
                                    != sizeof(ih264d_ctl_get_vui_params_ip_t))
825
0
                    {
826
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
827
0
                        ps_op->u4_error_code |=
828
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
829
0
                        return IV_FAIL;
830
0
                    }
831
832
0
                    if(ps_op->u4_size
833
0
                                    != sizeof(ih264d_ctl_get_vui_params_op_t))
834
0
                    {
835
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
836
0
                        ps_op->u4_error_code |=
837
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
838
0
                        return IV_FAIL;
839
0
                    }
840
841
0
                    break;
842
0
                }
843
0
                case IH264D_CMD_CTL_GET_SEI_MDCV_PARAMS:
844
0
                {
845
0
                    ih264d_ctl_get_sei_mdcv_params_ip_t *ps_ip;
846
0
                    ih264d_ctl_get_sei_mdcv_params_op_t *ps_op;
847
848
0
                    ps_ip = (ih264d_ctl_get_sei_mdcv_params_ip_t *)pv_api_ip;
849
0
                    ps_op = (ih264d_ctl_get_sei_mdcv_params_op_t *)pv_api_op;
850
851
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_mdcv_params_ip_t))
852
0
                    {
853
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
854
0
                        ps_op->u4_error_code |=
855
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
856
0
                        return IV_FAIL;
857
0
                    }
858
859
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_mdcv_params_op_t))
860
0
                    {
861
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
862
0
                        ps_op->u4_error_code |=
863
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
864
0
                        return IV_FAIL;
865
0
                    }
866
867
0
                    break;
868
0
                }
869
870
0
                case IH264D_CMD_CTL_GET_SEI_CLL_PARAMS:
871
0
                {
872
0
                    ih264d_ctl_get_sei_cll_params_ip_t *ps_ip;
873
0
                    ih264d_ctl_get_sei_cll_params_op_t *ps_op;
874
875
0
                    ps_ip = (ih264d_ctl_get_sei_cll_params_ip_t *)pv_api_ip;
876
0
                    ps_op = (ih264d_ctl_get_sei_cll_params_op_t *)pv_api_op;
877
878
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_cll_params_ip_t))
879
0
                    {
880
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
881
0
                        ps_op->u4_error_code |=
882
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
883
0
                        return IV_FAIL;
884
0
                    }
885
886
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_cll_params_op_t))
887
0
                    {
888
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
889
0
                        ps_op->u4_error_code |=
890
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
891
0
                        return IV_FAIL;
892
0
                    }
893
894
0
                    break;
895
0
                }
896
897
0
                case IH264D_CMD_CTL_GET_SEI_AVE_PARAMS:
898
0
                {
899
0
                    ih264d_ctl_get_sei_ave_params_ip_t *ps_ip;
900
0
                    ih264d_ctl_get_sei_ave_params_op_t *ps_op;
901
902
0
                    ps_ip = (ih264d_ctl_get_sei_ave_params_ip_t *)pv_api_ip;
903
0
                    ps_op = (ih264d_ctl_get_sei_ave_params_op_t *)pv_api_op;
904
905
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_ave_params_ip_t))
906
0
                    {
907
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
908
0
                        ps_op->u4_error_code |=
909
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
910
0
                        return IV_FAIL;
911
0
                    }
912
913
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_ave_params_op_t))
914
0
                    {
915
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
916
0
                        ps_op->u4_error_code |=
917
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
918
0
                        return IV_FAIL;
919
0
                    }
920
921
0
                    break;
922
0
                }
923
924
0
                case IH264D_CMD_CTL_GET_SEI_CCV_PARAMS:
925
0
                {
926
0
                    ih264d_ctl_get_sei_ccv_params_ip_t *ps_ip;
927
0
                    ih264d_ctl_get_sei_ccv_params_op_t *ps_op;
928
929
0
                    ps_ip = (ih264d_ctl_get_sei_ccv_params_ip_t *)pv_api_ip;
930
0
                    ps_op = (ih264d_ctl_get_sei_ccv_params_op_t *)pv_api_op;
931
932
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_ccv_params_ip_t))
933
0
                    {
934
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
935
0
                        ps_op->u4_error_code |=
936
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
937
0
                        return IV_FAIL;
938
0
                    }
939
940
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_ccv_params_op_t))
941
0
                    {
942
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
943
0
                        ps_op->u4_error_code |=
944
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
945
0
                        return IV_FAIL;
946
0
                    }
947
948
0
                    break;
949
0
                }
950
951
0
                case IH264D_CMD_CTL_GET_SEI_SII_PARAMS:
952
0
                {
953
0
                    ih264d_ctl_get_sei_sii_params_ip_t *ps_ip;
954
0
                    ih264d_ctl_get_sei_sii_params_op_t *ps_op;
955
956
0
                    ps_ip = (ih264d_ctl_get_sei_sii_params_ip_t *) pv_api_ip;
957
0
                    ps_op = (ih264d_ctl_get_sei_sii_params_op_t *) pv_api_op;
958
959
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_sii_params_ip_t))
960
0
                    {
961
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
962
0
                        ps_op->u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
963
0
                        return IV_FAIL;
964
0
                    }
965
966
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_sii_params_op_t))
967
0
                    {
968
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
969
0
                        ps_op->u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
970
0
                        return IV_FAIL;
971
0
                    }
972
973
0
                    break;
974
0
                }
975
976
0
                case IH264D_CMD_CTL_GET_SEI_FGC_PARAMS:
977
0
                {
978
0
                    ih264d_ctl_get_sei_fgc_params_ip_t *ps_ip;
979
0
                    ih264d_ctl_get_sei_fgc_params_op_t *ps_op;
980
981
0
                    ps_ip = (ih264d_ctl_get_sei_fgc_params_ip_t *) pv_api_ip;
982
0
                    ps_op = (ih264d_ctl_get_sei_fgc_params_op_t *) pv_api_op;
983
984
0
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_get_sei_fgc_params_ip_t))
985
0
                    {
986
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
987
0
                        ps_op->u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
988
0
                        return IV_FAIL;
989
0
                    }
990
991
0
                    if(ps_op->u4_size != sizeof(ih264d_ctl_get_sei_fgc_params_op_t))
992
0
                    {
993
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
994
0
                        ps_op->u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
995
0
                        return IV_FAIL;
996
0
                    }
997
998
0
                    break;
999
0
                }
1000
1001
307
                case IH264D_CMD_CTL_SET_NUM_CORES:
1002
307
                {
1003
307
                    ih264d_ctl_set_num_cores_ip_t *ps_ip;
1004
307
                    ih264d_ctl_set_num_cores_op_t *ps_op;
1005
1006
307
                    ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
1007
307
                    ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
1008
1009
307
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_set_num_cores_ip_t))
1010
0
                    {
1011
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1012
0
                        ps_op->u4_error_code |=
1013
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
1014
0
                        return IV_FAIL;
1015
0
                    }
1016
1017
307
                    if(ps_op->u4_size != sizeof(ih264d_ctl_set_num_cores_op_t))
1018
0
                    {
1019
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1020
0
                        ps_op->u4_error_code |=
1021
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
1022
0
                        return IV_FAIL;
1023
0
                    }
1024
1025
307
                    if((ps_ip->u4_num_cores != 1) && (ps_ip->u4_num_cores != 2)
1026
154
                                    && (ps_ip->u4_num_cores != 3)
1027
106
                                    && (ps_ip->u4_num_cores != 4))
1028
0
                    {
1029
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1030
0
                        return IV_FAIL;
1031
0
                    }
1032
307
                    break;
1033
307
                }
1034
307
                case IH264D_CMD_CTL_SET_PROCESSOR:
1035
307
                {
1036
307
                    ih264d_ctl_set_processor_ip_t *ps_ip;
1037
307
                    ih264d_ctl_set_processor_op_t *ps_op;
1038
1039
307
                    ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1040
307
                    ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1041
1042
307
                    if(ps_ip->u4_size != sizeof(ih264d_ctl_set_processor_ip_t))
1043
0
                    {
1044
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1045
0
                        ps_op->u4_error_code |=
1046
0
                                        IVD_IP_API_STRUCT_SIZE_INCORRECT;
1047
0
                        return IV_FAIL;
1048
0
                    }
1049
1050
307
                    if(ps_op->u4_size != sizeof(ih264d_ctl_set_processor_op_t))
1051
0
                    {
1052
0
                        ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
1053
0
                        ps_op->u4_error_code |=
1054
0
                                        IVD_OP_API_STRUCT_SIZE_INCORRECT;
1055
0
                        return IV_FAIL;
1056
0
                    }
1057
1058
307
                    break;
1059
307
                }
1060
307
                default:
1061
0
                    *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
1062
0
                    *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
1063
0
                    return IV_FAIL;
1064
0
                    break;
1065
2.66k
            }
1066
2.66k
        }
1067
2.66k
            break;
1068
17.4k
    }
1069
1070
17.4k
    return IV_SUCCESS;
1071
17.4k
}
1072
1073
1074
/**
1075
 *******************************************************************************
1076
 *
1077
 * @brief
1078
 *  Sets Processor type
1079
 *
1080
 * @par Description:
1081
 *  Sets Processor type
1082
 *
1083
 * @param[in] ps_codec_obj
1084
 *  Pointer to codec object at API level
1085
 *
1086
 * @param[in] pv_api_ip
1087
 *  Pointer to input argument structure
1088
 *
1089
 * @param[out] pv_api_op
1090
 *  Pointer to output argument structure
1091
 *
1092
 * @returns  Status
1093
 *
1094
 * @remarks
1095
 *
1096
 *
1097
 *******************************************************************************
1098
 */
1099
1100
WORD32 ih264d_set_processor(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1101
307
{
1102
307
    ih264d_ctl_set_processor_ip_t *ps_ip;
1103
307
    ih264d_ctl_set_processor_op_t *ps_op;
1104
307
    dec_struct_t *ps_codec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1105
1106
307
    ps_ip = (ih264d_ctl_set_processor_ip_t *)pv_api_ip;
1107
307
    ps_op = (ih264d_ctl_set_processor_op_t *)pv_api_op;
1108
1109
307
    ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
1110
307
    ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
1111
1112
307
    ih264d_init_function_ptr(ps_codec);
1113
1114
307
    ps_op->u4_error_code = 0;
1115
307
    return IV_SUCCESS;
1116
307
}
1117
1118
1119
/**************************************************************************
1120
 * \if Function name : ih264d_init_decoder \endif
1121
 *
1122
 *
1123
 * \brief
1124
 *    Initializes the decoder
1125
 *
1126
 * \param apiVersion               : Version of the api being used.
1127
 * \param errorHandlingMechanism   : Mechanism to be used for errror handling.
1128
 * \param postFilteringType: Type of post filtering operation to be used.
1129
 * \param uc_outputFormat: Format of the decoded picture [default 4:2:0].
1130
 * \param uc_dispBufs: Number of Display Buffers.
1131
 * \param p_NALBufAPI: Pointer to NAL Buffer API.
1132
 * \param p_DispBufAPI: Pointer to Display Buffer API.
1133
 * \param ih264d_dec_mem_manager  :Pointer to the function that will be called by decoder
1134
 *                        for memory allocation and freeing.
1135
 *
1136
 * \return
1137
 *    0 on Success and -1 on error
1138
 *
1139
 **************************************************************************
1140
 */
1141
void ih264d_init_decoder(void * ps_dec_params)
1142
2.26k
{
1143
2.26k
    dec_struct_t * ps_dec = (dec_struct_t *)ps_dec_params;
1144
2.26k
    dec_slice_params_t *ps_cur_slice;
1145
2.26k
    pocstruct_t *ps_prev_poc, *ps_cur_poc;
1146
2.26k
    WORD32 size;
1147
1148
2.26k
    size = sizeof(pred_info_t) * 2 * 32;
1149
2.26k
    memset(ps_dec->ps_pred, 0 , size);
1150
1151
2.26k
    size = sizeof(disp_mgr_t);
1152
2.26k
    memset(ps_dec->pv_disp_buf_mgr, 0 , size);
1153
1154
2.26k
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1155
2.26k
    memset(ps_dec->pv_pic_buf_mgr, 0, size);
1156
1157
2.26k
    size = sizeof(dec_err_status_t);
1158
2.26k
    memset(ps_dec->ps_dec_err_status, 0, size);
1159
1160
2.26k
    size = sizeof(sei);
1161
2.26k
    memset(ps_dec->ps_sei, 0, size);
1162
1163
2.26k
    size = sizeof(sei);
1164
2.26k
    memset(ps_dec->ps_sei_parse, 0, size);
1165
1166
2.26k
    size = sizeof(dpb_commands_t);
1167
2.26k
    memset(ps_dec->ps_dpb_cmds, 0, size);
1168
1169
2.26k
    size = sizeof(dec_bit_stream_t);
1170
2.26k
    memset(ps_dec->ps_bitstrm, 0, size);
1171
1172
2.26k
    size = sizeof(dec_slice_params_t);
1173
2.26k
    memset(ps_dec->ps_cur_slice, 0, size);
1174
1175
2.26k
    size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1176
2.26k
    memset(ps_dec->pv_scratch_sps_pps, 0, size);
1177
1178
2.26k
    size = sizeof(ctxt_inc_mb_info_t);
1179
2.26k
    memset(ps_dec->ps_left_mb_ctxt_info, 0, size);
1180
1181
2.26k
    size = (sizeof(neighbouradd_t) << 2);
1182
2.26k
    memset(ps_dec->ps_left_mvpred_addr, 0 ,size);
1183
1184
2.26k
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1185
2.26k
    memset(ps_dec->pv_mv_buf_mgr, 0, size);
1186
1187
    /* Free any dynamic buffers that are allocated */
1188
2.26k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_dynamic);
1189
2.26k
    ih264d_free_dynamic_bufs(ps_dec);
1190
1191
2.26k
    {
1192
2.26k
        UWORD8 i;
1193
2.26k
        struct pic_buffer_t *ps_init_dpb;
1194
2.26k
        ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[0][0];
1195
147k
        for(i = 0; i < 2 * MAX_REF_BUFS; i++)
1196
145k
        {
1197
145k
            ps_init_dpb->pu1_buf1 = NULL;
1198
145k
            ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1199
145k
            ps_dec->ps_dpb_mgr->ps_init_dpb[0][i] = ps_init_dpb;
1200
145k
            ps_dec->ps_dpb_mgr->ps_mod_dpb[0][i] = ps_init_dpb;
1201
145k
            ps_init_dpb++;
1202
145k
        }
1203
1204
2.26k
        ps_init_dpb = ps_dec->ps_dpb_mgr->ps_init_dpb[1][0];
1205
147k
        for(i = 0; i < 2 * MAX_REF_BUFS; i++)
1206
145k
        {
1207
145k
            ps_init_dpb->pu1_buf1 = NULL;
1208
145k
            ps_init_dpb->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1209
145k
            ps_dec->ps_dpb_mgr->ps_init_dpb[1][i] = ps_init_dpb;
1210
145k
            ps_dec->ps_dpb_mgr->ps_mod_dpb[1][i] = ps_init_dpb;
1211
145k
            ps_init_dpb++;
1212
145k
        }
1213
2.26k
    }
1214
1215
2.26k
    ps_cur_slice = ps_dec->ps_cur_slice;
1216
2.26k
    ps_dec->init_done = 0;
1217
1218
2.26k
    ps_dec->u4_num_cores = 1;
1219
1220
2.26k
    ps_dec->u2_pic_ht = ps_dec->u2_pic_wd = 0;
1221
1222
2.26k
    ps_dec->u1_separate_parse = DEFAULT_SEPARATE_PARSE;
1223
2.26k
    ps_dec->u4_app_disable_deblk_frm = 0;
1224
2.26k
    ps_dec->i4_degrade_type = 0;
1225
2.26k
    ps_dec->i4_degrade_pics = 0;
1226
1227
2.26k
    memset(ps_dec->ps_pps, 0,
1228
2.26k
           ((sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS));
1229
2.26k
    memset(ps_dec->ps_sps, 0,
1230
2.26k
           ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS));
1231
1232
    /* Initialization of function pointers ih264d_deblock_picture function*/
1233
1234
2.26k
    ps_dec->p_DeblockPicture[0] = ih264d_deblock_picture_non_mbaff;
1235
2.26k
    ps_dec->p_DeblockPicture[1] = ih264d_deblock_picture_mbaff;
1236
1237
2.26k
    ps_dec->s_cab_dec_env.pv_codec_handle = ps_dec;
1238
1239
2.26k
    ps_dec->u4_num_fld_in_frm = 0;
1240
1241
2.26k
    ps_dec->ps_dpb_mgr->pv_codec_handle = ps_dec;
1242
1243
    /* Initialize the sei validity u4_flag with zero indiacting sei is not valid*/
1244
2.26k
    ps_dec->ps_sei->u1_is_valid = 0;
1245
1246
    /* decParams Initializations */
1247
2.26k
    ps_dec->ps_cur_pps = NULL;
1248
2.26k
    ps_dec->ps_cur_sps = NULL;
1249
2.26k
    ps_dec->u1_init_dec_flag = 0;
1250
2.26k
    ps_dec->u1_first_slice_in_stream = 1;
1251
2.26k
    ps_dec->u1_last_pic_not_decoded = 0;
1252
2.26k
    ps_dec->u4_app_disp_width = 0;
1253
2.26k
    ps_dec->i4_header_decoded = 0;
1254
2.26k
    ps_dec->u4_total_frames_decoded = 0;
1255
1256
2.26k
    ps_dec->i4_error_code = 0;
1257
2.26k
    ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1258
2.26k
    ps_dec->ps_cur_slice->u1_mbaff_frame_flag = 0;
1259
1260
2.26k
    ps_dec->ps_dec_err_status->u1_err_flag = ACCEPT_ALL_PICS; //REJECT_PB_PICS;
1261
2.26k
    ps_dec->ps_dec_err_status->u1_cur_pic_type = PIC_TYPE_UNKNOWN;
1262
2.26k
    ps_dec->ps_dec_err_status->u4_frm_sei_sync = SYNC_FRM_DEFAULT;
1263
2.26k
    ps_dec->ps_dec_err_status->u4_cur_frm = INIT_FRAME;
1264
2.26k
    ps_dec->ps_dec_err_status->u1_pic_aud_i = PIC_TYPE_UNKNOWN;
1265
1266
2.26k
    ps_dec->u1_pr_sl_type = 0xFF;
1267
2.26k
    ps_dec->u2_mbx = 0xffff;
1268
2.26k
    ps_dec->u2_mby = 0;
1269
2.26k
    ps_dec->u4_total_mbs_coded = 0;
1270
1271
    /* POC initializations */
1272
2.26k
    ps_prev_poc = &ps_dec->s_prev_pic_poc;
1273
2.26k
    ps_cur_poc = &ps_dec->s_cur_pic_poc;
1274
2.26k
    ps_prev_poc->i4_pic_order_cnt_lsb = ps_cur_poc->i4_pic_order_cnt_lsb = 0;
1275
2.26k
    ps_prev_poc->i4_pic_order_cnt_msb = ps_cur_poc->i4_pic_order_cnt_msb = 0;
1276
2.26k
    ps_prev_poc->i4_delta_pic_order_cnt_bottom =
1277
2.26k
                    ps_cur_poc->i4_delta_pic_order_cnt_bottom = 0;
1278
2.26k
    ps_prev_poc->i4_delta_pic_order_cnt[0] =
1279
2.26k
                    ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
1280
2.26k
    ps_prev_poc->i4_delta_pic_order_cnt[1] =
1281
2.26k
                    ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
1282
2.26k
    ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1283
2.26k
    ps_prev_poc->i4_top_field_order_count = ps_cur_poc->i4_top_field_order_count =
1284
2.26k
                    0;
1285
2.26k
    ps_prev_poc->i4_bottom_field_order_count =
1286
2.26k
                    ps_cur_poc->i4_bottom_field_order_count = 0;
1287
2.26k
    ps_prev_poc->u1_bot_field = ps_cur_poc->u1_bot_field = 0;
1288
2.26k
    ps_prev_poc->u1_mmco_equalto5 = ps_cur_poc->u1_mmco_equalto5 = 0;
1289
2.26k
    ps_prev_poc->i4_prev_frame_num_ofst = ps_cur_poc->i4_prev_frame_num_ofst = 0;
1290
2.26k
    ps_cur_slice->u1_mmco_equalto5 = 0;
1291
2.26k
    ps_cur_slice->u2_frame_num = 0;
1292
1293
2.26k
    ps_dec->i4_max_poc = 0;
1294
2.26k
    ps_dec->i4_prev_max_display_seq = 0;
1295
2.26k
    ps_dec->u4_recon_mb_grp = 4;
1296
2.26k
    ps_dec->i4_reorder_depth = -1;
1297
1298
    /* Field PIC initializations */
1299
2.26k
    ps_dec->u1_second_field = 0;
1300
2.26k
    ps_dec->s_prev_seq_params.u1_eoseq_pending = 0;
1301
1302
    /* Set the cropping parameters as zero */
1303
2.26k
    ps_dec->u2_crop_offset_y = 0;
1304
2.26k
    ps_dec->u2_crop_offset_uv = 0;
1305
1306
    /* The Initial Frame Rate Info is not Present */
1307
2.26k
    ps_dec->i4_vui_frame_rate = -1;
1308
2.26k
    ps_dec->i4_pic_type = NA_SLICE;
1309
2.26k
    ps_dec->i4_frametype = IV_NA_FRAME;
1310
2.26k
    ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
1311
1312
2.26k
    ps_dec->u1_res_changed = 0;
1313
1314
1315
2.26k
    ps_dec->u1_frame_decoded_flag = 0;
1316
1317
    /* Set the default frame seek mask mode */
1318
2.26k
    ps_dec->u4_skip_frm_mask = SKIP_NONE;
1319
1320
    /********************************************************/
1321
    /* Initialize CAVLC residual decoding function pointers */
1322
    /********************************************************/
1323
2.26k
    ps_dec->pf_cavlc_4x4res_block[0] = ih264d_cavlc_4x4res_block_totalcoeff_1;
1324
2.26k
    ps_dec->pf_cavlc_4x4res_block[1] =
1325
2.26k
                    ih264d_cavlc_4x4res_block_totalcoeff_2to10;
1326
2.26k
    ps_dec->pf_cavlc_4x4res_block[2] =
1327
2.26k
                    ih264d_cavlc_4x4res_block_totalcoeff_11to16;
1328
1329
2.26k
    ps_dec->pf_cavlc_parse4x4coeff[0] = ih264d_cavlc_parse4x4coeff_n0to7;
1330
2.26k
    ps_dec->pf_cavlc_parse4x4coeff[1] = ih264d_cavlc_parse4x4coeff_n8;
1331
1332
2.26k
    ps_dec->pf_cavlc_parse_8x8block[0] =
1333
2.26k
                    ih264d_cavlc_parse_8x8block_none_available;
1334
2.26k
    ps_dec->pf_cavlc_parse_8x8block[1] =
1335
2.26k
                    ih264d_cavlc_parse_8x8block_left_available;
1336
2.26k
    ps_dec->pf_cavlc_parse_8x8block[2] =
1337
2.26k
                    ih264d_cavlc_parse_8x8block_top_available;
1338
2.26k
    ps_dec->pf_cavlc_parse_8x8block[3] =
1339
2.26k
                    ih264d_cavlc_parse_8x8block_both_available;
1340
1341
    /***************************************************************************/
1342
    /* Initialize Bs calculation function pointers for P and B, 16x16/non16x16 */
1343
    /***************************************************************************/
1344
2.26k
    ps_dec->pf_fill_bs1[0][0] = ih264d_fill_bs1_16x16mb_pslice;
1345
2.26k
    ps_dec->pf_fill_bs1[0][1] = ih264d_fill_bs1_non16x16mb_pslice;
1346
1347
2.26k
    ps_dec->pf_fill_bs1[1][0] = ih264d_fill_bs1_16x16mb_bslice;
1348
2.26k
    ps_dec->pf_fill_bs1[1][1] = ih264d_fill_bs1_non16x16mb_bslice;
1349
1350
2.26k
    ps_dec->pf_fill_bs_xtra_left_edge[0] =
1351
2.26k
                    ih264d_fill_bs_xtra_left_edge_cur_frm;
1352
2.26k
    ps_dec->pf_fill_bs_xtra_left_edge[1] =
1353
2.26k
                    ih264d_fill_bs_xtra_left_edge_cur_fld;
1354
1355
    /* Initialize Reference Pic Buffers */
1356
2.26k
    ih264d_init_ref_bufs(ps_dec->ps_dpb_mgr);
1357
1358
2.26k
    ps_dec->u2_prv_frame_num = 0;
1359
2.26k
    ps_dec->u1_top_bottom_decoded = 0;
1360
2.26k
    ps_dec->u1_dangling_field = 0;
1361
1362
2.26k
    ps_dec->s_cab_dec_env.cabac_table = gau4_ih264d_cabac_table;
1363
1364
2.26k
    ps_dec->pu1_left_mv_ctxt_inc = ps_dec->u1_left_mv_ctxt_inc_arr[0];
1365
2.26k
    ps_dec->pi1_left_ref_idx_ctxt_inc =
1366
2.26k
                    &ps_dec->i1_left_ref_idx_ctx_inc_arr[0][0];
1367
2.26k
    ps_dec->pu1_left_yuv_dc_csbp = &ps_dec->u1_yuv_dc_csbp_topmb;
1368
1369
    /* ! */
1370
    /* Initializing flush frame u4_flag */
1371
2.26k
    ps_dec->u1_flushfrm = 0;
1372
1373
2.26k
    {
1374
2.26k
        ps_dec->s_cab_dec_env.pv_codec_handle = (void*)ps_dec;
1375
2.26k
        ps_dec->ps_bitstrm->pv_codec_handle = (void*)ps_dec;
1376
2.26k
        ps_dec->ps_cur_slice->pv_codec_handle = (void*)ps_dec;
1377
2.26k
        ps_dec->ps_dpb_mgr->pv_codec_handle = (void*)ps_dec;
1378
2.26k
    }
1379
1380
2.26k
    memset(ps_dec->disp_bufs, 0, (MAX_DISP_BUFS_NEW) * sizeof(disp_buf_t));
1381
2.26k
    memset(ps_dec->u4_disp_buf_mapping, 0,
1382
2.26k
           (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1383
2.26k
    memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1384
2.26k
           (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1385
2.26k
    memset(ps_dec->ps_cur_slice, 0, sizeof(dec_slice_params_t));
1386
1387
2.26k
    ih264d_init_arch(ps_dec);
1388
2.26k
    ih264d_init_function_ptr(ps_dec);
1389
2.26k
    ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
1390
2.26k
    ps_dec->init_done = 1;
1391
1392
2.26k
}
1393
1394
WORD32 ih264d_join_threads(dec_struct_t *ps_dec)
1395
1.74k
{
1396
1.74k
    if(ps_dec->i4_threads_active)
1397
1.74k
    {
1398
        /* Wait for threads */
1399
1.74k
        ps_dec->i4_break_threads = 1;
1400
1.74k
        if(ps_dec->u4_dec_thread_created)
1401
134
        {
1402
134
            ithread_mutex_lock(ps_dec->apv_proc_start_mutex[0]);
1403
1404
134
            ps_dec->ai4_process_start[0] = PROC_START;
1405
1406
134
            ithread_cond_signal(ps_dec->apv_proc_start_condition[0]);
1407
1408
134
            ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[0]);
1409
1410
134
            ithread_join(ps_dec->pv_dec_thread_handle, NULL);
1411
1412
134
            ps_dec->u4_dec_thread_created = 0;
1413
134
        }
1414
1415
1.74k
        if(ps_dec->u4_bs_deblk_thread_created)
1416
66
        {
1417
66
            ithread_mutex_lock(ps_dec->apv_proc_start_mutex[1]);
1418
1419
66
            ps_dec->ai4_process_start[1] = PROC_START;
1420
1421
66
            ithread_cond_signal(ps_dec->apv_proc_start_condition[1]);
1422
1423
66
            ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[1]);
1424
1425
66
            ithread_join(ps_dec->pv_bs_deblk_thread_handle, NULL);
1426
1427
66
            ps_dec->u4_bs_deblk_thread_created = 0;
1428
66
        }
1429
1.74k
    }
1430
1.74k
    return IV_SUCCESS;
1431
1.74k
}
1432
1433
WORD32 ih264d_free_static_bufs(iv_obj_t *dec_hdl)
1434
307
{
1435
307
    dec_struct_t *ps_dec;
1436
1437
307
    void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1438
307
    void *pv_mem_ctxt;
1439
1440
307
    ps_dec = (dec_struct_t *)dec_hdl->pv_codec_handle;
1441
307
    pf_aligned_free = ps_dec->pf_aligned_free;
1442
307
    pv_mem_ctxt = ps_dec->pv_mem_ctxt;
1443
1444
307
    if(ps_dec->i4_threads_active)
1445
307
    {
1446
1447
307
        ih264d_join_threads(ps_dec);
1448
1449
        // destroy mutex and condition variable for both the threads
1450
        // 1. ih264d_decode_picture_thread
1451
        // 2. ih264d_recon_deblk_thread
1452
307
        {
1453
307
            UWORD32 i;
1454
921
            for(i = 0; i < 2; i++)
1455
614
            {
1456
614
                ithread_cond_destroy(ps_dec->apv_proc_start_condition[i]);
1457
614
                ithread_cond_destroy(ps_dec->apv_proc_done_condition[i]);
1458
1459
614
                ithread_mutex_destroy(ps_dec->apv_proc_start_mutex[i]);
1460
614
                ithread_mutex_destroy(ps_dec->apv_proc_done_mutex[i]);
1461
614
            }
1462
307
        }
1463
307
        PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->apv_proc_start_mutex[0]);
1464
307
        PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->apv_proc_start_condition[0]);
1465
307
    }
1466
1467
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sps);
1468
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pps);
1469
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_dec_thread_handle);
1470
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_bs_deblk_thread_handle);
1471
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_mgr);
1472
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred);
1473
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_disp_buf_mgr);
1474
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_pic_buf_mgr);
1475
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pic_buf_base);
1476
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_err_status);
1477
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei);
1478
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_sei_parse);
1479
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dpb_cmds);
1480
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_bitstrm);
1481
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_cur_slice);
1482
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_scratch_sps_pps);
1483
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_static);
1484
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ppv_map_ref_idx_to_poc_base);
1485
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_cabac_ctxt_table_t);
1486
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mb_ctxt_info);
1487
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_ref_buff_base);
1488
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_pred1);
1489
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_temp_mc_buffer);
1490
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_init_dpb_base);
1491
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_mbaff_wt_mat);
1492
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu4_wts_ofsts_mat);
1493
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_left_mvpred_addr);
1494
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pv_mv_buf_mgr);
1495
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_col_mv_base);
1496
307
    PS_DEC_ALIGNED_FREE(ps_dec, dec_hdl->pv_codec_handle);
1497
1498
307
    if(dec_hdl)
1499
307
    {
1500
307
        pf_aligned_free(pv_mem_ctxt, dec_hdl);
1501
307
    }
1502
307
    return IV_SUCCESS;
1503
307
}
1504
/*****************************************************************************/
1505
/*                                                                           */
1506
/*  Function Name : ih264d_create                                              */
1507
/*                                                                           */
1508
/*  Description   : creates decoder                                          */
1509
/*                                                                           */
1510
/*  Inputs        :iv_obj_t decoder handle                                   */
1511
/*                :pv_api_ip pointer to input structure                      */
1512
/*                :pv_api_op pointer to output structure                     */
1513
/*  Outputs       :                                                          */
1514
/*  Returns       : void                                                     */
1515
/*                                                                           */
1516
/*  Issues        : none                                                     */
1517
/*                                                                           */
1518
/*  Revision History:                                                        */
1519
/*                                                                           */
1520
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1521
/*         22 10 2008    100356         Draft                                */
1522
/*                                                                           */
1523
/*****************************************************************************/
1524
WORD32 ih264d_allocate_static_bufs(iv_obj_t **dec_hdl, void *pv_api_ip, void *pv_api_op)
1525
307
{
1526
307
    ih264d_create_ip_t *ps_create_ip;
1527
307
    ih264d_create_op_t *ps_create_op;
1528
307
    void *pv_buf;
1529
307
    UWORD8 *pu1_buf;
1530
307
    dec_struct_t *ps_dec;
1531
307
    void *(*pf_aligned_alloc)(void *pv_mem_ctxt, WORD32 alignment, WORD32 size);
1532
307
    void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1533
307
    void *pv_mem_ctxt;
1534
307
    WORD32 size;
1535
1536
307
    ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1537
307
    ps_create_op = (ih264d_create_op_t *)pv_api_op;
1538
1539
307
    ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1540
1541
307
    pf_aligned_alloc = ps_create_ip->s_ivd_create_ip_t.pf_aligned_alloc;
1542
307
    pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1543
307
    pv_mem_ctxt  = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1544
1545
    /* Initialize return handle to NULL */
1546
307
    ps_create_op->s_ivd_create_op_t.pv_handle = NULL;
1547
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(iv_obj_t));
1548
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1549
307
    memset(pv_buf, 0, sizeof(iv_obj_t));
1550
307
    *dec_hdl = (iv_obj_t *)pv_buf;
1551
307
    ps_create_op->s_ivd_create_op_t.pv_handle = *dec_hdl;
1552
1553
307
    (*dec_hdl)->pv_codec_handle = NULL;
1554
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, sizeof(dec_struct_t));
1555
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1556
307
    (*dec_hdl)->pv_codec_handle = (dec_struct_t *)pv_buf;
1557
307
    ps_dec = (dec_struct_t *)pv_buf;
1558
1559
307
    memset(ps_dec, 0, sizeof(dec_struct_t));
1560
1561
307
#ifndef LOGO_EN
1562
307
    ps_dec->u4_share_disp_buf = ps_create_ip->s_ivd_create_ip_t.u4_share_disp_buf;
1563
#else
1564
    ps_dec->u4_share_disp_buf = 0;
1565
#endif
1566
1567
307
    ps_dec->u1_chroma_format =
1568
307
                    (UWORD8)(ps_create_ip->s_ivd_create_ip_t.e_output_format);
1569
1570
307
    if((ps_dec->u1_chroma_format != IV_YUV_420P)
1571
235
                    && (ps_dec->u1_chroma_format
1572
235
                                    != IV_YUV_420SP_UV)
1573
181
                    && (ps_dec->u1_chroma_format
1574
181
                                    != IV_YUV_420SP_VU))
1575
123
    {
1576
123
        ps_dec->u4_share_disp_buf = 0;
1577
123
    }
1578
1579
307
    ps_dec->u1_enable_mb_info = ps_create_ip->u4_enable_frame_info;
1580
307
    ps_dec->pf_aligned_alloc = pf_aligned_alloc;
1581
307
    ps_dec->pf_aligned_free = pf_aligned_free;
1582
307
    ps_dec->pv_mem_ctxt = pv_mem_ctxt;
1583
307
    ps_dec->i4_threads_active = ps_create_ip->u4_keep_threads_active;
1584
1585
1586
307
    size = ((sizeof(dec_seq_params_t)) * MAX_NUM_SEQ_PARAMS);
1587
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1588
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1589
307
    memset(pv_buf, 0, size);
1590
307
    ps_dec->ps_sps = pv_buf;
1591
1592
307
    size = (sizeof(dec_pic_params_t)) * MAX_NUM_PIC_PARAMS;
1593
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1594
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1595
307
    memset(pv_buf, 0, size);
1596
307
    ps_dec->ps_pps = pv_buf;
1597
1598
307
    size = ithread_get_handle_size();
1599
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1600
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1601
307
    memset(pv_buf, 0, size);
1602
307
    ps_dec->pv_dec_thread_handle = pv_buf;
1603
1604
307
    size = ithread_get_handle_size();
1605
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1606
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1607
307
    memset(pv_buf, 0, size);
1608
307
    ps_dec->pv_bs_deblk_thread_handle = pv_buf;
1609
1610
307
    if(ps_dec->i4_threads_active)
1611
307
    {
1612
307
        UWORD32 i;
1613
        /* Request memory to hold mutex (start/done) for both threads */
1614
307
        size = ithread_get_mutex_lock_size() << 2;
1615
307
        pv_buf = pf_aligned_alloc(pv_mem_ctxt, 8, size);
1616
307
        RETURN_IF((NULL == pv_buf), IV_FAIL);
1617
307
        memset(pv_buf, 0, size);
1618
1619
        // init mutex variable for both the threads
1620
        // 1. ih264d_decode_picture_thread
1621
        // 2. ih264d_recon_deblk_thread
1622
921
        for(i = 0; i < 2; i++)
1623
614
        {
1624
614
            WORD32 ret;
1625
614
            WORD32 mutex_size = ithread_get_mutex_lock_size();
1626
1627
614
            ps_dec->apv_proc_start_mutex[i] =
1628
614
                            (UWORD8 *)pv_buf + (2 * i * mutex_size);
1629
614
            ps_dec->apv_proc_done_mutex[i] =
1630
614
                            (UWORD8 *)pv_buf + ((2 * i + 1) * mutex_size);
1631
1632
614
            ret = ithread_mutex_init(ps_dec->apv_proc_start_mutex[i]);
1633
614
            RETURN_IF((ret != IV_SUCCESS), ret);
1634
1635
614
            ret = ithread_mutex_init(ps_dec->apv_proc_done_mutex[i]);
1636
614
            RETURN_IF((ret != IV_SUCCESS), ret);
1637
614
        }
1638
1639
307
        size = ithread_get_cond_struct_size() << 2;
1640
307
        pv_buf = pf_aligned_alloc(pv_mem_ctxt, 8, size);
1641
307
        RETURN_IF((NULL == pv_buf), IV_FAIL);
1642
307
        memset(pv_buf, 0, size);
1643
1644
        // init condition variable for both the threads
1645
921
        for(i = 0; i < 2; i++)
1646
614
        {
1647
614
            WORD32 ret;
1648
614
            WORD32 cond_size = ithread_get_cond_struct_size();
1649
614
            ps_dec->apv_proc_start_condition[i] =
1650
614
                            (UWORD8 *)pv_buf + (2 * i * cond_size);
1651
614
            ps_dec->apv_proc_done_condition[i] =
1652
614
                            (UWORD8 *)pv_buf + ((2 * i + 1) * cond_size);
1653
1654
614
            ret = ithread_cond_init(ps_dec->apv_proc_start_condition[i]);
1655
614
            RETURN_IF((ret != IV_SUCCESS), ret);
1656
1657
614
            ret = ithread_cond_init(ps_dec->apv_proc_done_condition[i]);
1658
614
            RETURN_IF((ret != IV_SUCCESS), ret);
1659
614
        }
1660
307
    }
1661
1662
307
    size = sizeof(dpb_manager_t);
1663
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1664
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1665
307
    memset(pv_buf, 0, size);
1666
307
    ps_dec->ps_dpb_mgr = pv_buf;
1667
1668
307
    size = sizeof(pred_info_t) * 2 * 32;
1669
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1670
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1671
307
    memset(pv_buf, 0, size);
1672
307
    ps_dec->ps_pred = pv_buf;
1673
1674
307
    size = sizeof(disp_mgr_t);
1675
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1676
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1677
307
    memset(pv_buf, 0, size);
1678
307
    ps_dec->pv_disp_buf_mgr = pv_buf;
1679
1680
307
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1681
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1682
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1683
307
    memset(pv_buf, 0, size);
1684
307
    ps_dec->pv_pic_buf_mgr = pv_buf;
1685
1686
307
    size = sizeof(struct pic_buffer_t) * (H264_MAX_REF_PICS * 2);
1687
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1688
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1689
307
    memset(pv_buf, 0, size);
1690
307
    ps_dec->ps_pic_buf_base = pv_buf;
1691
1692
307
    size = sizeof(dec_err_status_t);
1693
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1694
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1695
307
    memset(pv_buf, 0, size);
1696
307
    ps_dec->ps_dec_err_status = (dec_err_status_t *)pv_buf;
1697
1698
307
    size = sizeof(sei);
1699
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1700
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1701
307
    memset(pv_buf, 0, size);
1702
307
    ps_dec->ps_sei = (sei *)pv_buf;
1703
1704
307
    size = sizeof(sei);
1705
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1706
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1707
307
    memset(pv_buf, 0, size);
1708
307
    ps_dec->ps_sei_parse = (sei *)pv_buf;
1709
1710
307
    size = sizeof(dpb_commands_t);
1711
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1712
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1713
307
    memset(pv_buf, 0, size);
1714
307
    ps_dec->ps_dpb_cmds = (dpb_commands_t *)pv_buf;
1715
1716
307
    size = sizeof(dec_bit_stream_t);
1717
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1718
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1719
307
    memset(pv_buf, 0, size);
1720
307
    ps_dec->ps_bitstrm = (dec_bit_stream_t *)pv_buf;
1721
1722
307
    size = sizeof(dec_slice_params_t);
1723
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1724
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1725
307
    memset(pv_buf, 0, size);
1726
307
    ps_dec->ps_cur_slice = (dec_slice_params_t *)pv_buf;
1727
1728
307
    size = MAX(sizeof(dec_seq_params_t), sizeof(dec_pic_params_t));
1729
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1730
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1731
307
    memset(pv_buf, 0, size);
1732
307
    ps_dec->pv_scratch_sps_pps = pv_buf;
1733
1734
1735
307
    ps_dec->u4_static_bits_buf_size = 256000;
1736
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, ps_dec->u4_static_bits_buf_size);
1737
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1738
307
    memset(pv_buf, 0, ps_dec->u4_static_bits_buf_size);
1739
307
    ps_dec->pu1_bits_buf_static = pv_buf;
1740
1741
1742
307
    size = ((TOTAL_LIST_ENTRIES + PAD_MAP_IDX_POC)
1743
307
                        * sizeof(void *));
1744
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1745
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1746
307
    ps_dec->ppv_map_ref_idx_to_poc_base = pv_buf;
1747
307
    memset(ps_dec->ppv_map_ref_idx_to_poc_base, 0, size);
1748
1749
307
    ps_dec->ppv_map_ref_idx_to_poc = ps_dec->ppv_map_ref_idx_to_poc_base + OFFSET_MAP_IDX_POC;
1750
1751
1752
307
    size = (sizeof(bin_ctxt_model_t) * NUM_CABAC_CTXTS);
1753
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1754
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1755
307
    memset(pv_buf, 0, size);
1756
307
    ps_dec->p_cabac_ctxt_table_t = pv_buf;
1757
1758
1759
1760
307
    size = sizeof(ctxt_inc_mb_info_t);
1761
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1762
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1763
307
    memset(pv_buf, 0, size);
1764
307
    ps_dec->ps_left_mb_ctxt_info = pv_buf;
1765
1766
1767
1768
307
    size = MAX_REF_BUF_SIZE * 2;
1769
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1770
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1771
307
    memset(pv_buf, 0, size);
1772
307
    ps_dec->pu1_ref_buff_base = pv_buf;
1773
307
    ps_dec->pu1_ref_buff = ps_dec->pu1_ref_buff_base + MAX_REF_BUF_SIZE;
1774
1775
1776
307
    size = ((sizeof(WORD16)) * PRED_BUFFER_WIDTH
1777
307
                        * PRED_BUFFER_HEIGHT * 2);
1778
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1779
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1780
307
    memset(pv_buf, 0, size);
1781
307
    ps_dec->pi2_pred1 = pv_buf;
1782
1783
1784
307
    size = sizeof(UWORD8) * (MB_LUM_SIZE);
1785
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1786
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1787
307
    memset(pv_buf, 0, size);
1788
307
    ps_dec->pu1_temp_mc_buffer = pv_buf;
1789
1790
1791
1792
1793
307
    size = 8 * MAX_REF_BUFS * sizeof(struct pic_buffer_t);
1794
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1795
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1796
307
    memset(pv_buf, 0, size);
1797
1798
307
    ps_dec->pu1_init_dpb_base = pv_buf;
1799
307
    pu1_buf = pv_buf;
1800
307
    ps_dec->ps_dpb_mgr->ps_init_dpb[0][0] = (struct pic_buffer_t *)pu1_buf;
1801
1802
307
    pu1_buf += size / 2;
1803
307
    ps_dec->ps_dpb_mgr->ps_init_dpb[1][0] = (struct pic_buffer_t *)pu1_buf;
1804
1805
307
    size = (sizeof(UWORD32) * 2 * 3
1806
307
                        * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1)) * 2);
1807
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1808
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1809
307
    memset(pv_buf, 0, size);
1810
307
    ps_dec->pu4_mbaff_wt_mat = pv_buf;
1811
1812
307
    size = sizeof(UWORD32) * 2 * 3
1813
307
                        * ((MAX_FRAMES << 1) * (MAX_FRAMES << 1));
1814
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1815
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1816
307
    memset(pv_buf, 0, size);
1817
307
    ps_dec->pu4_wts_ofsts_mat = pv_buf;
1818
1819
1820
307
    size = (sizeof(neighbouradd_t) << 2);
1821
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1822
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1823
307
    memset(pv_buf, 0, size);
1824
307
    ps_dec->ps_left_mvpred_addr = pv_buf;
1825
1826
1827
307
    size = sizeof(buf_mgr_t) + ithread_get_mutex_lock_size();
1828
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1829
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1830
307
    memset(pv_buf, 0, size);
1831
307
    ps_dec->pv_mv_buf_mgr = pv_buf;
1832
1833
1834
307
    size =  sizeof(col_mv_buf_t) * (H264_MAX_REF_PICS * 2);
1835
307
    pv_buf = pf_aligned_alloc(pv_mem_ctxt, 128, size);
1836
307
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1837
307
    ps_dec->ps_col_mv_base = pv_buf;
1838
307
    memset(ps_dec->ps_col_mv_base, 0, size);
1839
1840
307
    ih264d_init_decoder(ps_dec);
1841
1842
307
    return IV_SUCCESS;
1843
307
}
1844
1845
1846
/*****************************************************************************/
1847
/*                                                                           */
1848
/*  Function Name : ih264d_create                                              */
1849
/*                                                                           */
1850
/*  Description   : creates decoder                                          */
1851
/*                                                                           */
1852
/*  Inputs        :iv_obj_t decoder handle                                   */
1853
/*                :pv_api_ip pointer to input structure                      */
1854
/*                :pv_api_op pointer to output structure                     */
1855
/*  Outputs       :                                                          */
1856
/*  Returns       : void                                                     */
1857
/*                                                                           */
1858
/*  Issues        : none                                                     */
1859
/*                                                                           */
1860
/*  Revision History:                                                        */
1861
/*                                                                           */
1862
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1863
/*         22 10 2008    100356         Draft                                */
1864
/*                                                                           */
1865
/*****************************************************************************/
1866
WORD32 ih264d_create(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
1867
307
{
1868
307
    ih264d_create_ip_t *ps_create_ip;
1869
307
    ih264d_create_op_t *ps_create_op;
1870
1871
307
    WORD32 ret;
1872
1873
307
    ps_create_ip = (ih264d_create_ip_t *)pv_api_ip;
1874
307
    ps_create_op = (ih264d_create_op_t *)pv_api_op;
1875
1876
307
    ps_create_op->s_ivd_create_op_t.u4_error_code = 0;
1877
307
    dec_hdl = NULL;
1878
307
    ret = ih264d_allocate_static_bufs(&dec_hdl, pv_api_ip, pv_api_op);
1879
1880
    /* If allocation of some buffer fails, then free buffers allocated till then */
1881
307
    if(IV_FAIL == ret)
1882
0
    {
1883
0
        if(dec_hdl)
1884
0
        {
1885
0
            if(dec_hdl->pv_codec_handle)
1886
0
            {
1887
0
                ih264d_free_static_bufs(dec_hdl);
1888
0
            }
1889
0
            else
1890
0
            {
1891
0
                void (*pf_aligned_free)(void *pv_mem_ctxt, void *pv_buf);
1892
0
                void *pv_mem_ctxt;
1893
1894
0
                pf_aligned_free = ps_create_ip->s_ivd_create_ip_t.pf_aligned_free;
1895
0
                pv_mem_ctxt  = ps_create_ip->s_ivd_create_ip_t.pv_mem_ctxt;
1896
0
                pf_aligned_free(pv_mem_ctxt, dec_hdl);
1897
0
            }
1898
0
        }
1899
0
        ps_create_op->s_ivd_create_op_t.u4_error_code = IVD_MEM_ALLOC_FAILED;
1900
0
        ps_create_op->s_ivd_create_op_t.u4_error_code |= 1 << IVD_FATALERROR;
1901
1902
0
        return IV_FAIL;
1903
0
    }
1904
1905
307
    return IV_SUCCESS;
1906
307
}
1907
1908
/*****************************************************************************/
1909
/*                                                                           */
1910
/*  Function Name :  ih264d_map_error                                        */
1911
/*                                                                           */
1912
/*  Description   :  Maps error codes to IVD error groups                    */
1913
/*                                                                           */
1914
/*  Inputs        :                                                          */
1915
/*  Globals       : <Does it use any global variables?>                      */
1916
/*  Outputs       :                                                          */
1917
/*  Returns       : void                                                     */
1918
/*                                                                           */
1919
/*  Issues        : none                                                     */
1920
/*                                                                           */
1921
/*  Revision History:                                                        */
1922
/*                                                                           */
1923
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1924
/*         22 10 2008    100356         Draft                                */
1925
/*                                                                           */
1926
/*****************************************************************************/
1927
UWORD32 ih264d_map_error(UWORD32 i4_err_status)
1928
30.9k
{
1929
30.9k
    UWORD32 temp = 0;
1930
1931
30.9k
    switch(i4_err_status)
1932
30.9k
    {
1933
0
        case ERROR_MEM_ALLOC_ISRAM_T:
1934
0
        case ERROR_MEM_ALLOC_SDRAM_T:
1935
0
        case ERROR_BUF_MGR:
1936
0
        case ERROR_MB_GROUP_ASSGN_T:
1937
0
        case ERROR_FRAME_LIMIT_OVER:
1938
0
        case ERROR_ACTUAL_RESOLUTION_GREATER_THAN_INIT:
1939
0
        case ERROR_PROFILE_NOT_SUPPORTED:
1940
0
        case ERROR_INIT_NOT_DONE:
1941
0
        case IVD_MEM_ALLOC_FAILED:
1942
191
        case ERROR_FEATURE_UNAVAIL:
1943
316
        case IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED:
1944
316
            temp = 1 << IVD_FATALERROR;
1945
316
            H264_DEC_DEBUG_PRINT("\nFatal Error\n");
1946
316
            break;
1947
1948
433
        case ERROR_DBP_MANAGER_T:
1949
433
        case ERROR_GAPS_IN_FRM_NUM:
1950
433
        case ERROR_UNKNOWN_NAL:
1951
433
        case ERROR_INV_MB_SLC_GRP_T:
1952
433
        case ERROR_MULTIPLE_SLC_GRP_T:
1953
433
        case ERROR_UNKNOWN_LEVEL:
1954
612
        case ERROR_UNAVAIL_PICBUF_T:
1955
799
        case ERROR_UNAVAIL_MVBUF_T:
1956
799
        case ERROR_UNAVAIL_DISPBUF_T:
1957
847
        case ERROR_NUM_REF:
1958
847
        case ERROR_REFIDX_ORDER_T:
1959
847
        case ERROR_PIC0_NOT_FOUND_T:
1960
961
        case ERROR_MB_TYPE:
1961
977
        case ERROR_SUB_MB_TYPE:
1962
1.11k
        case ERROR_CBP:
1963
1.51k
        case ERROR_REF_IDX:
1964
1.51k
        case ERROR_NUM_MV:
1965
1.65k
        case ERROR_CHROMA_PRED_MODE:
1966
1.65k
        case ERROR_INTRAPRED:
1967
1.65k
        case ERROR_NEXT_MB_ADDRESS_T:
1968
1.65k
        case ERROR_MB_ADDRESS_T:
1969
1.65k
        case ERROR_PIC1_NOT_FOUND_T:
1970
1.82k
        case ERROR_CAVLC_NUM_COEFF_T:
1971
1.82k
        case ERROR_CAVLC_SCAN_POS_T:
1972
1.97k
        case ERROR_PRED_WEIGHT_TABLE_T:
1973
4.73k
        case ERROR_CORRUPTED_SLICE:
1974
4.73k
            temp = 1 << IVD_CORRUPTEDDATA;
1975
4.73k
            break;
1976
1977
0
        case ERROR_NOT_SUPP_RESOLUTION:
1978
0
        case ERROR_ACTUAL_LEVEL_GREATER_THAN_INIT:
1979
0
            temp = 1 << IVD_UNSUPPORTEDINPUT;
1980
0
            break;
1981
1982
0
        case ERROR_INVALID_PIC_PARAM:
1983
5
        case ERROR_INVALID_SEQ_PARAM:
1984
5
        case ERROR_EGC_EXCEED_32_1_T:
1985
5
        case ERROR_EGC_EXCEED_32_2_T:
1986
5
        case ERROR_INV_RANGE_TEV_T:
1987
296
        case ERROR_INV_SLC_TYPE_T:
1988
346
        case ERROR_INV_POC_TYPE_T:
1989
1.73k
        case ERROR_INV_RANGE_QP_T:
1990
4.79k
        case ERROR_INV_SPS_PPS_T:
1991
5.50k
        case ERROR_INV_SLICE_HDR_T:
1992
7.49k
        case ERROR_INV_SEI_MDCV_PARAMS:
1993
7.49k
        case ERROR_INV_SEI_CLL_PARAMS:
1994
7.51k
        case ERROR_INV_SEI_AVE_PARAMS:
1995
7.72k
        case ERROR_INV_SEI_CCV_PARAMS:
1996
7.73k
        case ERROR_INV_SEI_SII_PARAMS:
1997
1998
7.73k
            temp = 1 << IVD_CORRUPTEDHEADER;
1999
7.73k
            break;
2000
2001
297
        case ERROR_EOB_FLUSHBITS_T:
2002
1.45k
        case ERROR_EOB_GETBITS_T:
2003
1.45k
        case ERROR_EOB_GETBIT_T:
2004
1.45k
        case ERROR_EOB_BYPASS_T:
2005
1.45k
        case ERROR_EOB_DECISION_T:
2006
3.27k
        case ERROR_EOB_TERMINATE_T:
2007
3.27k
        case ERROR_EOB_READCOEFF4X4CAB_T:
2008
3.27k
            temp = 1 << IVD_INSUFFICIENTDATA;
2009
3.27k
            break;
2010
0
        case ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED:
2011
0
        case ERROR_DISP_WIDTH_RESET_TO_PIC_WIDTH:
2012
0
            temp = 1 << IVD_UNSUPPORTEDPARAM | 1 << IVD_FATALERROR;
2013
0
            break;
2014
2015
368
        case ERROR_DANGLING_FIELD_IN_PIC:
2016
368
            temp = 1 << IVD_APPLIEDCONCEALMENT;
2017
368
            break;
2018
2019
30.9k
    }
2020
2021
30.9k
    return temp;
2022
2023
30.9k
}
2024
2025
UWORD32 ih264d_get_outbuf_size(WORD32 pic_wd,
2026
                               UWORD32 pic_ht,
2027
                               UWORD8 u1_chroma_format,
2028
                               UWORD32 *p_buf_size)
2029
15.9k
{
2030
15.9k
    UWORD32 u4_min_num_out_bufs = 0;
2031
2032
15.9k
    if(u1_chroma_format == IV_YUV_420P)
2033
7.17k
        u4_min_num_out_bufs = MIN_OUT_BUFS_420;
2034
8.79k
    else if(u1_chroma_format == IV_YUV_422ILE)
2035
2.14k
        u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
2036
6.64k
    else if(u1_chroma_format == IV_RGB_565)
2037
1.01k
        u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
2038
5.63k
    else if((u1_chroma_format == IV_YUV_420SP_UV)
2039
2.30k
                    || (u1_chroma_format == IV_YUV_420SP_VU))
2040
5.63k
        u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
2041
2042
15.9k
    if(u1_chroma_format == IV_YUV_420P)
2043
7.17k
    {
2044
7.17k
        p_buf_size[0] = (pic_wd * pic_ht);
2045
7.17k
        p_buf_size[1] = (pic_wd * pic_ht) >> 2;
2046
7.17k
        p_buf_size[2] = (pic_wd * pic_ht) >> 2;
2047
7.17k
    }
2048
8.79k
    else if(u1_chroma_format == IV_YUV_422ILE)
2049
2.14k
    {
2050
2.14k
        p_buf_size[0] = (pic_wd * pic_ht) * 2;
2051
2.14k
        p_buf_size[1] = p_buf_size[2] = 0;
2052
2.14k
    }
2053
6.64k
    else if(u1_chroma_format == IV_RGB_565)
2054
1.01k
    {
2055
1.01k
        p_buf_size[0] = (pic_wd * pic_ht) * 2;
2056
1.01k
        p_buf_size[1] = p_buf_size[2] = 0;
2057
1.01k
    }
2058
5.63k
    else if((u1_chroma_format == IV_YUV_420SP_UV)
2059
2.30k
                    || (u1_chroma_format == IV_YUV_420SP_VU))
2060
5.63k
    {
2061
5.63k
        p_buf_size[0] = (pic_wd * pic_ht);
2062
5.63k
        p_buf_size[1] = (pic_wd * pic_ht) >> 1;
2063
5.63k
        p_buf_size[2] = 0;
2064
5.63k
    }
2065
2066
15.9k
    return u4_min_num_out_bufs;
2067
15.9k
}
2068
2069
WORD32 check_app_out_buf_size(dec_struct_t *ps_dec)
2070
12.1k
{
2071
12.1k
    UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
2072
12.1k
    UWORD32 u4_min_num_out_bufs, i;
2073
12.1k
    UWORD32 pic_wd, pic_ht;
2074
2075
12.1k
    if(0 == ps_dec->u4_share_disp_buf)
2076
12.1k
    {
2077
12.1k
        pic_wd = ps_dec->u2_disp_width;
2078
12.1k
        pic_ht = ps_dec->u2_disp_height;
2079
2080
12.1k
    }
2081
0
    else
2082
0
    {
2083
0
        pic_wd = ps_dec->u2_frm_wd_y;
2084
0
        pic_ht = ps_dec->u2_frm_ht_y;
2085
0
    }
2086
2087
12.1k
    if(ps_dec->u4_app_disp_width > pic_wd)
2088
0
        pic_wd = ps_dec->u4_app_disp_width;
2089
2090
12.1k
    u4_min_num_out_bufs = ih264d_get_outbuf_size(pic_wd, pic_ht,
2091
12.1k
                                                 ps_dec->u1_chroma_format,
2092
12.1k
                                                 &au4_min_out_buf_size[0]);
2093
2094
2095
12.1k
    if(0 == ps_dec->u4_share_disp_buf)
2096
12.1k
    {
2097
12.1k
        if(ps_dec->ps_out_buffer->u4_num_bufs < u4_min_num_out_bufs)
2098
0
            return IV_FAIL;
2099
2100
36.0k
        for(i = 0; i < u4_min_num_out_bufs; i++)
2101
24.2k
        {
2102
24.2k
            if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i]
2103
24.2k
                            < au4_min_out_buf_size[i])
2104
291
                return (IV_FAIL);
2105
24.2k
        }
2106
12.1k
    }
2107
0
    else
2108
0
    {
2109
0
        if(ps_dec->disp_bufs[0].u4_num_bufs < u4_min_num_out_bufs)
2110
0
            return IV_FAIL;
2111
2112
0
        for(i = 0; i < u4_min_num_out_bufs; i++)
2113
0
        {
2114
            /* We need to check only with the disp_buffer[0], because we have
2115
             * already ensured that all the buffers are of the same size in
2116
             * ih264d_set_display_frame.
2117
             */
2118
0
            if(ps_dec->disp_bufs[0].u4_bufsize[i] < au4_min_out_buf_size[i])
2119
0
                return (IV_FAIL);
2120
0
        }
2121
2122
0
    }
2123
2124
11.8k
    return (IV_SUCCESS);
2125
12.1k
}
2126
2127
2128
/*****************************************************************************/
2129
/*                                                                           */
2130
/*  Function Name :  ih264d_video_decode                                     */
2131
/*                                                                           */
2132
/*  Description   :  handle video decode API command                         */
2133
/*                                                                           */
2134
/*  Inputs        :iv_obj_t decoder handle                                   */
2135
/*                :pv_api_ip pointer to input structure                      */
2136
/*                :pv_api_op pointer to output structure                     */
2137
/*  Outputs       :                                                          */
2138
/*  Returns       : void                                                     */
2139
/*                                                                           */
2140
/*  Issues        : none                                                     */
2141
/*                                                                           */
2142
/*  Revision History:                                                        */
2143
/*                                                                           */
2144
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
2145
/*         22 10 2008    100356         Draft                                */
2146
/*                                                                           */
2147
/*****************************************************************************/
2148
2149
WORD32 ih264d_video_decode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2150
14.1k
{
2151
    /* ! */
2152
2153
14.1k
    dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
2154
2155
14.1k
    WORD32 i4_err_status = 0;
2156
14.1k
    UWORD8 *pu1_buf = NULL;
2157
14.1k
    WORD32 buflen;
2158
14.1k
    UWORD32 u4_max_ofst, u4_length_of_start_code = 0;
2159
2160
14.1k
    UWORD32 bytes_consumed = 0;
2161
14.1k
    UWORD32 cur_slice_is_nonref = 0;
2162
14.1k
    UWORD32 u4_next_is_aud;
2163
14.1k
    UWORD32 u4_first_start_code_found = 0;
2164
14.1k
    WORD32 ret = 0,api_ret_value = IV_SUCCESS;
2165
14.1k
    WORD32 header_data_left = 0,frame_data_left = 0;
2166
14.1k
    UWORD8 *pu1_bitstrm_buf;
2167
14.1k
    ih264d_video_decode_ip_t *ps_h264d_dec_ip;
2168
14.1k
    ih264d_video_decode_op_t *ps_h264d_dec_op;
2169
14.1k
    ivd_video_decode_ip_t *ps_dec_ip;
2170
14.1k
    ivd_video_decode_op_t *ps_dec_op;
2171
2172
14.1k
    ithread_set_name((void*)"Parse_thread");
2173
2174
14.1k
    ps_h264d_dec_ip = (ih264d_video_decode_ip_t *)pv_api_ip;
2175
14.1k
    ps_h264d_dec_op = (ih264d_video_decode_op_t *)pv_api_op;
2176
14.1k
    ps_dec_ip = &ps_h264d_dec_ip->s_ivd_video_decode_ip_t;
2177
14.1k
    ps_dec_op = &ps_h264d_dec_op->s_ivd_video_decode_op_t;
2178
2179
14.1k
    {
2180
14.1k
        UWORD32 u4_size;
2181
14.1k
        u4_size = ps_dec_op->u4_size;
2182
14.1k
        memset(ps_h264d_dec_op, 0, ps_dec_op->u4_size);
2183
14.1k
        ps_dec_op->u4_size = u4_size;
2184
14.1k
    }
2185
2186
14.1k
    ps_dec->pv_dec_out = ps_dec_op;
2187
14.1k
    if(ps_dec->init_done != 1)
2188
0
    {
2189
0
        return IV_FAIL;
2190
0
    }
2191
2192
    /*Data memory barries instruction,so that bitstream write by the application is complete*/
2193
14.1k
    DATA_SYNC();
2194
2195
14.1k
    if(0 == ps_dec->u1_flushfrm)
2196
14.1k
    {
2197
14.1k
        if(ps_dec_ip->pv_stream_buffer == NULL)
2198
0
        {
2199
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2200
0
            ps_dec_op->u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
2201
0
            return IV_FAIL;
2202
0
        }
2203
14.1k
        if(ps_dec_ip->u4_num_Bytes <= 0)
2204
0
        {
2205
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2206
0
            ps_dec_op->u4_error_code |= IVD_DEC_NUMBYTES_INV;
2207
0
            return IV_FAIL;
2208
2209
0
        }
2210
14.1k
    }
2211
14.1k
    ps_dec->u1_pic_decode_done = 0;
2212
2213
14.1k
    if(ps_dec->i4_threads_active)
2214
14.1k
    {
2215
14.1k
        UWORD32 i;
2216
14.1k
        ps_dec->i4_break_threads = 0;
2217
42.5k
        for (i = 0; i < 2; i++)
2218
28.3k
        {
2219
28.3k
            ret = ithread_mutex_lock(ps_dec->apv_proc_start_mutex[i]);
2220
28.3k
            RETURN_IF((ret != IV_SUCCESS), ret);
2221
2222
28.3k
            ps_dec->ai4_process_start[i] = PROC_INIT;
2223
2224
28.3k
            ret = ithread_mutex_unlock(ps_dec->apv_proc_start_mutex[i]);
2225
28.3k
            RETURN_IF((ret != IV_SUCCESS), ret);
2226
28.3k
        }
2227
14.1k
    }
2228
0
    else {
2229
0
        ps_dec->u4_dec_thread_created = 0;
2230
0
        ps_dec->u4_bs_deblk_thread_created = 0;
2231
0
    }
2232
2233
14.1k
    ps_dec_op->u4_num_bytes_consumed = 0;
2234
14.1k
    ps_dec_op->i4_reorder_depth = -1;
2235
14.1k
    ps_dec_op->i4_display_index = DEFAULT_POC;
2236
14.1k
    ps_dec->ps_out_buffer = NULL;
2237
2238
14.1k
    if(ps_dec_ip->u4_size
2239
14.1k
                    >= offsetof(ivd_video_decode_ip_t, s_out_buffer))
2240
14.1k
        ps_dec->ps_out_buffer = &ps_dec_ip->s_out_buffer;
2241
2242
14.1k
    ps_dec->u4_fmt_conv_cur_row = 0;
2243
2244
14.1k
    ps_dec->u4_output_present = 0;
2245
14.1k
    ps_dec->s_disp_op.u4_error_code = 1;
2246
14.1k
    ps_dec->u4_fmt_conv_num_rows = FMT_CONV_NUM_ROWS;
2247
14.1k
    if(0 == ps_dec->u4_share_disp_buf
2248
14.1k
                    && ps_dec->i4_decode_header == 0)
2249
11.6k
    {
2250
11.6k
        UWORD32 i;
2251
11.6k
        if((ps_dec->ps_out_buffer->u4_num_bufs == 0) ||
2252
11.6k
           (ps_dec->ps_out_buffer->u4_num_bufs > IVD_VIDDEC_MAX_IO_BUFFERS))
2253
0
        {
2254
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2255
0
            ps_dec_op->u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2256
0
            return IV_FAIL;
2257
0
        }
2258
2259
32.8k
        for(i = 0; i < ps_dec->ps_out_buffer->u4_num_bufs; i++)
2260
21.1k
        {
2261
21.1k
            if(ps_dec->ps_out_buffer->pu1_bufs[i] == NULL)
2262
0
            {
2263
0
                ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2264
0
                ps_dec_op->u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2265
0
                return IV_FAIL;
2266
0
            }
2267
2268
21.1k
            if(ps_dec->ps_out_buffer->u4_min_out_buf_size[i] == 0)
2269
0
            {
2270
0
                ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2271
0
                ps_dec_op->u4_error_code |=
2272
0
                                IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2273
0
                return IV_FAIL;
2274
0
            }
2275
21.1k
        }
2276
11.6k
    }
2277
2278
14.1k
    if(ps_dec->u4_total_frames_decoded >= NUM_FRAMES_LIMIT)
2279
0
    {
2280
0
        ps_dec_op->u4_error_code = ERROR_FRAME_LIMIT_OVER;
2281
0
        return IV_FAIL;
2282
0
    }
2283
2284
    /* ! */
2285
14.1k
    ps_dec->u4_ts = ps_dec_ip->u4_ts;
2286
14.1k
    ps_dec->i4_error_code = 0;
2287
2288
14.1k
    ps_dec_op->u4_error_code = 0;
2289
14.1k
    ps_dec_op->e_pic_type = IV_NA_FRAME;
2290
14.1k
    ps_dec_op->u4_output_present = 0;
2291
14.1k
    ps_dec_op->u4_frame_decoded_flag = 0;
2292
2293
14.1k
    ps_dec->i4_frametype = IV_NA_FRAME;
2294
14.1k
    ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
2295
2296
14.1k
    ps_dec->u4_slice_start_code_found = 0;
2297
2298
    /* In case the decoder is not in flush mode(in shared mode),
2299
     then decoder has to pick up a buffer to write current frame.
2300
     Check if a frame is available in such cases */
2301
2302
14.1k
    if(ps_dec->u1_init_dec_flag == 1 && ps_dec->u4_share_disp_buf == 1
2303
0
                    && ps_dec->u1_flushfrm == 0)
2304
0
    {
2305
0
        UWORD32 i;
2306
2307
0
        WORD32 disp_avail = 0, free_id;
2308
2309
        /* Check if at least one buffer is available with the codec */
2310
        /* If not then return to application with error */
2311
0
        for(i = 0; i < ps_dec->u1_pic_bufs; i++)
2312
0
        {
2313
0
            if(0 == ps_dec->u4_disp_buf_mapping[i]
2314
0
                            || 1 == ps_dec->u4_disp_buf_to_be_freed[i])
2315
0
            {
2316
0
                disp_avail = 1;
2317
0
                break;
2318
0
            }
2319
2320
0
        }
2321
2322
0
        if(0 == disp_avail)
2323
0
        {
2324
            /* If something is queued for display wait for that buffer to be returned */
2325
2326
0
            ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2327
0
            ps_dec_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
2328
0
            return (IV_FAIL);
2329
0
        }
2330
2331
0
        while(1)
2332
0
        {
2333
0
            pic_buffer_t *ps_pic_buf;
2334
0
            ps_pic_buf = (pic_buffer_t *)ih264_buf_mgr_get_next_free(
2335
0
                            (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, &free_id);
2336
2337
0
            if(ps_pic_buf == NULL)
2338
0
            {
2339
0
                UWORD32 display_queued = 0;
2340
2341
                /* check if any buffer was given for display which is not returned yet */
2342
0
                for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
2343
0
                {
2344
0
                    if(0 != ps_dec->u4_disp_buf_mapping[i])
2345
0
                    {
2346
0
                        display_queued = 1;
2347
0
                        break;
2348
0
                    }
2349
0
                }
2350
                /* If some buffer is queued for display, then codec has to singal an error and wait
2351
                 for that buffer to be returned.
2352
                 If nothing is queued for display then codec has ownership of all display buffers
2353
                 and it can reuse any of the existing buffers and continue decoding */
2354
2355
0
                if(1 == display_queued)
2356
0
                {
2357
                    /* If something is queued for display wait for that buffer to be returned */
2358
0
                    ps_dec_op->u4_error_code = IVD_DEC_REF_BUF_NULL;
2359
0
                    ps_dec_op->u4_error_code |= (1
2360
0
                                    << IVD_UNSUPPORTEDPARAM);
2361
0
                    return (IV_FAIL);
2362
0
                }
2363
0
            }
2364
0
            else
2365
0
            {
2366
                /* If the buffer is with display, then mark it as in use and then look for a buffer again */
2367
0
                if(1 == ps_dec->u4_disp_buf_mapping[free_id])
2368
0
                {
2369
0
                    ih264_buf_mgr_set_status(
2370
0
                                    (buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2371
0
                                    free_id,
2372
0
                                    BUF_MGR_IO);
2373
0
                }
2374
0
                else
2375
0
                {
2376
                    /**
2377
                     *  Found a free buffer for present call. Release it now.
2378
                     *  Will be again obtained later.
2379
                     */
2380
0
                    ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
2381
0
                                          free_id,
2382
0
                                          BUF_MGR_IO);
2383
0
                    break;
2384
0
                }
2385
0
            }
2386
0
        }
2387
2388
0
    }
2389
2390
14.1k
    if(ps_dec->u1_enable_mb_info && (ps_dec->i4_header_decoded & DECODED_SPS_MASK))
2391
0
    {
2392
0
        UWORD32 blk_qp_map_size = ps_h264d_dec_ip->u4_8x8_blk_qp_map_size;
2393
0
        UWORD32 blk_type_map_size = ps_h264d_dec_ip->u4_8x8_blk_type_map_size;
2394
0
        UWORD32 blk_8x8_map_size = ps_dec->u4_total_mbs << 2;
2395
0
        if ((ps_h264d_dec_ip->pu1_8x8_blk_qp_map && blk_qp_map_size < blk_8x8_map_size) ||
2396
0
            (ps_h264d_dec_ip->pu1_8x8_blk_type_map && blk_type_map_size < blk_8x8_map_size))
2397
0
        {
2398
0
            ps_dec_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2399
0
            ps_dec_op->u4_error_code |= IH264D_INSUFFICIENT_METADATA_BUFFER;
2400
0
            return IV_FAIL;
2401
0
        }
2402
0
    }
2403
2404
14.1k
    if(ps_dec->u1_flushfrm)
2405
0
    {
2406
0
        if(ps_dec->u1_init_dec_flag == 0)
2407
0
        {
2408
            /*Come out of flush mode and return*/
2409
0
            ps_dec->u1_flushfrm = 0;
2410
0
            return (IV_FAIL);
2411
0
        }
2412
2413
2414
2415
0
        ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2416
0
                                      &(ps_dec->s_disp_op));
2417
0
        if(0 == ps_dec->s_disp_op.u4_error_code)
2418
0
        {
2419
            /* check output buffer size given by the application */
2420
0
            if(check_app_out_buf_size(ps_dec) != IV_SUCCESS)
2421
0
            {
2422
0
                ps_dec_op->u4_error_code= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2423
0
                return (IV_FAIL);
2424
0
            }
2425
2426
0
            ps_dec->u4_fmt_conv_cur_row = 0;
2427
0
            ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht;
2428
0
            ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2429
0
                                  ps_dec->u4_fmt_conv_cur_row,
2430
0
                                  ps_dec->u4_fmt_conv_num_rows);
2431
0
            ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2432
0
            ps_dec->u4_output_present = 1;
2433
2434
0
            if(ps_dec->u1_enable_mb_info)
2435
0
            {
2436
0
                UWORD32 disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2437
0
                if(ps_h264d_dec_ip->pu1_8x8_blk_qp_map)
2438
0
                {
2439
0
                    ps_h264d_dec_op->pu1_8x8_blk_qp_map = ps_h264d_dec_ip->pu1_8x8_blk_qp_map;
2440
0
                    ps_h264d_dec_op->u4_8x8_blk_qp_map_size = ps_dec->u4_total_mbs << 2;
2441
0
                    memcpy(ps_h264d_dec_op->pu1_8x8_blk_qp_map,
2442
0
                        ps_dec->as_buf_id_info_map[disp_buf_id].pu1_qp_map,
2443
0
                        ps_dec->u4_total_mbs << 2);
2444
0
                }
2445
0
                if(ps_h264d_dec_ip->pu1_8x8_blk_type_map)
2446
0
                {
2447
0
                    ps_h264d_dec_op->pu1_8x8_blk_type_map = ps_h264d_dec_ip->pu1_8x8_blk_type_map;
2448
0
                    ps_h264d_dec_op->u4_8x8_blk_type_map_size = ps_dec->u4_total_mbs << 2;
2449
0
                    memcpy(ps_h264d_dec_op->pu1_8x8_blk_type_map,
2450
0
                        ps_dec->as_buf_id_info_map[disp_buf_id].pu1_mb_type_map,
2451
0
                        ps_dec->u4_total_mbs << 2);
2452
0
                }
2453
0
            }
2454
0
        }
2455
0
        ih264d_export_sei_params(&ps_dec_op->s_sei_decode_op, ps_dec);
2456
2457
0
        ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2458
2459
0
        ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2460
0
        ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2461
0
        ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
2462
0
        ps_dec_op->i4_display_index = ps_dec->i4_display_index;
2463
2464
0
        ps_dec_op->u4_new_seq = 0;
2465
2466
0
        ps_dec_op->u4_output_present = ps_dec->u4_output_present;
2467
0
        ps_dec_op->u4_progressive_frame_flag =
2468
0
                        ps_dec->s_disp_op.u4_progressive_frame_flag;
2469
0
        ps_dec_op->e_output_format =
2470
0
                        ps_dec->s_disp_op.e_output_format;
2471
0
        ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
2472
0
        ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
2473
0
        ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
2474
0
        ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2475
2476
        /*In the case of flush ,since no frame is decoded set pic type as invalid*/
2477
0
        ps_dec_op->u4_is_ref_flag = -1;
2478
0
        ps_dec_op->e_pic_type = IV_NA_FRAME;
2479
0
        ps_dec_op->u4_frame_decoded_flag = 0;
2480
2481
0
        if(0 == ps_dec->s_disp_op.u4_error_code)
2482
0
        {
2483
0
            return (IV_SUCCESS);
2484
0
        }
2485
0
        else
2486
0
            return (IV_FAIL);
2487
2488
0
    }
2489
14.1k
    if(ps_dec->u1_res_changed == 1)
2490
524
    {
2491
        /*if resolution has changed and all buffers have been flushed, reset decoder*/
2492
524
        ih264d_init_decoder(ps_dec);
2493
524
    }
2494
2495
14.1k
    ps_dec->u4_cur_mb_addr = 0;
2496
14.1k
    ps_dec->u4_total_mbs_coded = 0;
2497
14.1k
    ps_dec->u2_cur_slice_num = 0;
2498
14.1k
    ps_dec->cur_dec_mb_num = 0;
2499
14.1k
    ps_dec->cur_recon_mb_num = 0;
2500
14.1k
    ps_dec->u4_first_slice_in_pic = 1;
2501
14.1k
    ps_dec->u1_slice_header_done = 0;
2502
14.1k
    ps_dec->u1_dangling_field = 0;
2503
14.1k
    ps_dec->u4_cur_bs_mb_num = 0;
2504
14.1k
    ps_dec->u4_start_recon_deblk  = 0;
2505
14.1k
    ps_dec->u4_sps_cnt_in_process = 0;
2506
2507
14.1k
    DEBUG_THREADS_PRINTF(" Starting process call\n");
2508
2509
2510
14.1k
    ps_dec->u4_pic_buf_got = 0;
2511
2512
14.1k
    do
2513
246k
    {
2514
246k
        WORD32 buf_size;
2515
2516
246k
        pu1_buf = (UWORD8*)ps_dec_ip->pv_stream_buffer
2517
246k
                        + ps_dec_op->u4_num_bytes_consumed;
2518
2519
246k
        u4_max_ofst = ps_dec_ip->u4_num_Bytes
2520
246k
                        - ps_dec_op->u4_num_bytes_consumed;
2521
2522
        /* If dynamic bitstream buffer is not allocated and
2523
         * header decode is done, then allocate dynamic bitstream buffer
2524
         */
2525
246k
        if((NULL == ps_dec->pu1_bits_buf_dynamic) &&
2526
163k
           (ps_dec->i4_header_decoded & 1))
2527
2.20k
        {
2528
2.20k
            WORD32 size;
2529
2530
2.20k
            void *pv_buf;
2531
2.20k
            void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
2532
2.20k
            size = MAX(256000, ps_dec->u2_pic_wd * ps_dec->u2_pic_ht * 3 / 2);
2533
2.20k
            pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128,
2534
2.20k
                                              size + EXTRA_BS_OFFSET);
2535
2.20k
            RETURN_IF((NULL == pv_buf), IV_FAIL);
2536
2.20k
            memset(pv_buf, 0, size + EXTRA_BS_OFFSET);
2537
2.20k
            ps_dec->pu1_bits_buf_dynamic = pv_buf;
2538
2.20k
            ps_dec->u4_dynamic_bits_buf_size = size;
2539
2.20k
        }
2540
2541
246k
        if(ps_dec->pu1_bits_buf_dynamic)
2542
84.7k
        {
2543
84.7k
            pu1_bitstrm_buf = ps_dec->pu1_bits_buf_dynamic;
2544
84.7k
            buf_size = ps_dec->u4_dynamic_bits_buf_size;
2545
84.7k
        }
2546
161k
        else
2547
161k
        {
2548
161k
            pu1_bitstrm_buf = ps_dec->pu1_bits_buf_static;
2549
161k
            buf_size = ps_dec->u4_static_bits_buf_size;
2550
161k
        }
2551
2552
246k
        u4_next_is_aud = 0;
2553
2554
246k
        buflen = ih264d_find_start_code(pu1_buf, 0, u4_max_ofst,
2555
246k
                                               &u4_length_of_start_code,
2556
246k
                                               &u4_next_is_aud);
2557
2558
246k
        if(buflen == -1)
2559
0
            buflen = 0;
2560
        /* Ignore bytes beyond the allocated size of intermediate buffer */
2561
        /* Since 8 bytes are read ahead, ensure 8 bytes are free at the
2562
        end of the buffer, which will be memset to 0 after emulation prevention */
2563
246k
        buflen = MIN(buflen, buf_size - 8);
2564
2565
246k
        bytes_consumed = buflen + u4_length_of_start_code;
2566
246k
        ps_dec_op->u4_num_bytes_consumed += bytes_consumed;
2567
2568
246k
        if(buflen)
2569
245k
        {
2570
245k
            memcpy(pu1_bitstrm_buf, pu1_buf + u4_length_of_start_code,
2571
245k
                   buflen);
2572
            /* Decoder may read extra 8 bytes near end of the frame */
2573
245k
            if((buflen + 8) < buf_size)
2574
245k
            {
2575
245k
                memset(pu1_bitstrm_buf + buflen, 0, 8);
2576
245k
            }
2577
245k
            u4_first_start_code_found = 1;
2578
2579
245k
        }
2580
1.26k
        else
2581
1.26k
        {
2582
            /*start code not found*/
2583
2584
1.26k
            if(u4_first_start_code_found == 0)
2585
123
            {
2586
                /*no start codes found in current process call*/
2587
2588
123
                ps_dec->i4_error_code = ERROR_START_CODE_NOT_FOUND;
2589
123
                ps_dec_op->u4_error_code |= 1 << IVD_INSUFFICIENTDATA;
2590
2591
123
                if(ps_dec->u4_pic_buf_got == 0)
2592
123
                {
2593
2594
123
                    ih264d_fill_output_struct_from_context(ps_dec,
2595
123
                                                           ps_dec_op);
2596
2597
123
                    ps_dec_op->u4_error_code = ps_dec->i4_error_code;
2598
123
                    ps_dec_op->u4_frame_decoded_flag = 0;
2599
2600
123
                    return (IV_FAIL);
2601
123
                }
2602
0
                else
2603
0
                {
2604
0
                    ps_dec->u1_pic_decode_done = 1;
2605
0
                    continue;
2606
0
                }
2607
123
            }
2608
1.14k
            else
2609
1.14k
            {
2610
                /* a start code has already been found earlier in the same process call*/
2611
1.14k
                frame_data_left = 0;
2612
1.14k
                header_data_left = 0;
2613
1.14k
                continue;
2614
1.14k
            }
2615
2616
1.26k
        }
2617
2618
245k
        ret = ih264d_parse_nal_unit(dec_hdl, ps_dec_op,
2619
245k
                              pu1_bitstrm_buf, buflen);
2620
245k
        if(ret != OK)
2621
26.7k
        {
2622
26.7k
            UWORD32 error =  ih264d_map_error(ret);
2623
26.7k
            ps_dec_op->u4_error_code = error | ret;
2624
26.7k
            api_ret_value = IV_FAIL;
2625
2626
26.7k
            if((ret == IVD_RES_CHANGED)
2627
24.7k
                            || (ret == IVD_MEM_ALLOC_FAILED)
2628
24.7k
                            || (ret == ERROR_UNAVAIL_PICBUF_T)
2629
24.5k
                            || (ret == ERROR_UNAVAIL_MVBUF_T)
2630
24.3k
                            || (ret == ERROR_INV_SPS_PPS_T)
2631
21.3k
                            || (ret == ERROR_FEATURE_UNAVAIL)
2632
21.1k
                            || (ret == IVD_STREAM_WIDTH_HEIGHT_NOT_SUPPORTED)
2633
21.0k
                            || (ret == IVD_DISP_FRM_ZERO_OP_BUF_SIZE))
2634
5.73k
            {
2635
5.73k
                ps_dec->u4_slice_start_code_found = 0;
2636
5.73k
                break;
2637
5.73k
            }
2638
2639
20.9k
            if((ret == ERROR_INCOMPLETE_FRAME) || (ret == ERROR_DANGLING_FIELD_IN_PIC))
2640
5.80k
            {
2641
5.80k
                ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2642
5.80k
                api_ret_value = IV_FAIL;
2643
5.80k
                break;
2644
5.80k
            }
2645
2646
15.1k
            if(ret == ERROR_IN_LAST_SLICE_OF_PIC)
2647
13
            {
2648
13
                api_ret_value = IV_FAIL;
2649
13
                break;
2650
13
            }
2651
2652
15.1k
        }
2653
2654
233k
        header_data_left = ((ps_dec->i4_decode_header == 1)
2655
100k
                        && (ps_dec->i4_header_decoded != 3)
2656
100k
                        && (ps_dec_op->u4_num_bytes_consumed
2657
100k
                                        < ps_dec_ip->u4_num_Bytes));
2658
233k
        frame_data_left = (((ps_dec->i4_decode_header == 0)
2659
132k
                        && ((ps_dec->u1_pic_decode_done == 0)
2660
935
                                        || (u4_next_is_aud == 1)))
2661
131k
                        && (ps_dec_op->u4_num_bytes_consumed
2662
131k
                                        < ps_dec_ip->u4_num_Bytes));
2663
233k
    }
2664
234k
    while(( header_data_left == 1)||(frame_data_left == 1));
2665
2666
14.0k
    if((ps_dec->u4_pic_buf_got == 1)
2667
7.14k
            && (ret != IVD_MEM_ALLOC_FAILED)
2668
7.14k
            && ps_dec->u4_total_mbs_coded < ps_dec->u2_frm_ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2669
5.84k
    {
2670
        // last slice - missing/corruption
2671
5.84k
        WORD32 num_mb_skipped;
2672
5.84k
        WORD32 prev_slice_err;
2673
5.84k
        pocstruct_t temp_poc;
2674
5.84k
        WORD32 ret1;
2675
5.84k
        WORD32 ht_in_mbs;
2676
5.84k
        ht_in_mbs = ps_dec->u2_pic_ht >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag);
2677
5.84k
        num_mb_skipped = (ht_in_mbs * ps_dec->u2_frm_wd_in_mbs)
2678
5.84k
                            - ps_dec->u4_total_mbs_coded;
2679
2680
5.84k
        if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_pic_buf_got == 0))
2681
0
            prev_slice_err = 1;
2682
5.84k
        else
2683
5.84k
            prev_slice_err = 2;
2684
2685
5.84k
        if(ps_dec->u4_first_slice_in_pic && (ps_dec->u4_total_mbs_coded == 0))
2686
0
            prev_slice_err = 1;
2687
2688
5.84k
        ret1 = ih264d_mark_err_slice_skip(ps_dec, num_mb_skipped, ps_dec->u1_nal_unit_type == IDR_SLICE_NAL, ps_dec->ps_cur_slice->u2_frame_num,
2689
5.84k
                                   &temp_poc, prev_slice_err);
2690
2691
5.84k
        if((ret1 == ERROR_UNAVAIL_PICBUF_T) || (ret1 == ERROR_UNAVAIL_MVBUF_T) ||
2692
5.84k
                       (ret1 == ERROR_INV_SPS_PPS_T))
2693
0
        {
2694
0
            ret = ret1;
2695
0
        }
2696
5.84k
    }
2697
2698
14.0k
    if((ret == IVD_RES_CHANGED)
2699
12.0k
                    || (ret == IVD_MEM_ALLOC_FAILED)
2700
12.0k
                    || (ret == ERROR_UNAVAIL_PICBUF_T)
2701
11.9k
                    || (ret == ERROR_UNAVAIL_MVBUF_T)
2702
11.7k
                    || (ret == ERROR_INV_SPS_PPS_T))
2703
5.34k
    {
2704
2705
        /* signal the decode thread */
2706
5.34k
        ih264d_signal_decode_thread(ps_dec);
2707
        /* close deblock thread if it is not closed yet */
2708
5.34k
        if(ps_dec->u4_num_cores == 3)
2709
662
        {
2710
662
            ih264d_signal_bs_deblk_thread(ps_dec);
2711
662
        }
2712
        /* dont consume bitstream for change in resolution case */
2713
5.34k
        if(ret == IVD_RES_CHANGED)
2714
1.96k
        {
2715
1.96k
            ps_dec_op->u4_num_bytes_consumed -= bytes_consumed;
2716
1.96k
        }
2717
5.34k
        return IV_FAIL;
2718
5.34k
    }
2719
2720
2721
8.71k
    if(ps_dec->u1_separate_parse)
2722
4.76k
    {
2723
        /* If Format conversion is not complete,
2724
         complete it here */
2725
4.76k
        if(ps_dec->u4_num_cores == 2)
2726
2.75k
        {
2727
2728
            /*do deblocking of all mbs*/
2729
2.75k
            if((ps_dec->u4_nmb_deblk == 0) &&(ps_dec->u4_start_recon_deblk == 1) && (ps_dec->ps_cur_sps->u1_mb_aff_flag == 0))
2730
517
            {
2731
517
                UWORD32 u4_num_mbs,u4_max_addr;
2732
517
                tfr_ctxt_t s_tfr_ctxt;
2733
517
                tfr_ctxt_t *ps_tfr_cxt = &s_tfr_ctxt;
2734
517
                pad_mgr_t *ps_pad_mgr = &ps_dec->s_pad_mgr;
2735
2736
                /*BS is done for all mbs while parsing*/
2737
517
                u4_max_addr = (ps_dec->u2_frm_wd_in_mbs * ps_dec->u2_frm_ht_in_mbs) - 1;
2738
517
                ps_dec->u4_cur_bs_mb_num = u4_max_addr + 1;
2739
2740
2741
517
                ih264d_init_deblk_tfr_ctxt(ps_dec, ps_pad_mgr, ps_tfr_cxt,
2742
517
                                           ps_dec->u2_frm_wd_in_mbs, 0);
2743
2744
2745
517
                u4_num_mbs = u4_max_addr
2746
517
                                - ps_dec->u4_cur_deblk_mb_num + 1;
2747
2748
517
                DEBUG_PERF_PRINTF("mbs left for deblocking= %d \n",u4_num_mbs);
2749
2750
517
                if(u4_num_mbs != 0)
2751
517
                    ih264d_check_mb_map_deblk(ps_dec, u4_num_mbs,
2752
517
                                                   ps_tfr_cxt,1);
2753
2754
517
                ps_dec->u4_start_recon_deblk  = 0;
2755
2756
517
            }
2757
2758
2.75k
        }
2759
2760
        /*signal the decode thread*/
2761
4.76k
        ih264d_signal_decode_thread(ps_dec);
2762
        /* close deblock thread if it is not closed yet*/
2763
4.76k
        if(ps_dec->u4_num_cores == 3)
2764
2.00k
        {
2765
2.00k
            ih264d_signal_bs_deblk_thread(ps_dec);
2766
2.00k
        }
2767
4.76k
    }
2768
2769
2770
8.71k
    DATA_SYNC();
2771
2772
2773
8.71k
    if((ps_dec_op->u4_error_code & 0xff)
2774
8.71k
                    != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
2775
8.71k
    {
2776
8.71k
        ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
2777
8.71k
        ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
2778
8.71k
        ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
2779
8.71k
    }
2780
2781
//Report if header (sps and pps) has not been decoded yet
2782
8.71k
    if(ps_dec->i4_decode_header == 1 && ps_dec->i4_header_decoded != 3)
2783
406
    {
2784
406
        ps_dec_op->u4_error_code |= (1 << IVD_INSUFFICIENTDATA);
2785
406
        api_ret_value = IV_FAIL;
2786
406
    }
2787
2788
8.71k
    if((ps_dec->u4_pic_buf_got == 1)
2789
7.14k
                    && (ERROR_DANGLING_FIELD_IN_PIC != i4_err_status))
2790
7.14k
    {
2791
        /*
2792
         * For field pictures, set the bottom and top picture decoded u4_flag correctly.
2793
         */
2794
2795
7.14k
        if(ps_dec->ps_cur_slice->u1_field_pic_flag)
2796
2.99k
        {
2797
2.99k
            if(1 == ps_dec->ps_cur_slice->u1_bottom_field_flag)
2798
736
            {
2799
736
                ps_dec->u1_top_bottom_decoded |= BOT_FIELD_ONLY;
2800
736
            }
2801
2.25k
            else
2802
2.25k
            {
2803
2.25k
                ps_dec->u1_top_bottom_decoded |= TOP_FIELD_ONLY;
2804
2.25k
            }
2805
2.99k
        }
2806
4.15k
        else
2807
4.15k
        {
2808
4.15k
                ps_dec->u1_top_bottom_decoded = TOP_FIELD_ONLY | BOT_FIELD_ONLY;
2809
4.15k
        }
2810
2811
        /* if new frame in not found (if we are still getting slices from previous frame)
2812
         * ih264d_deblock_display is not called. Such frames will not be added to reference /display
2813
         */
2814
7.14k
        if ((ps_dec->ps_dec_err_status->u1_err_flag & REJECT_CUR_PIC) == 0)
2815
7.14k
        {
2816
            /* Calling Function to deblock Picture and Display */
2817
7.14k
            ret = ih264d_deblock_display(ps_dec);
2818
7.14k
        }
2819
2820
2821
        /*set to complete ,as we dont support partial frame decode*/
2822
7.14k
        if(ps_dec->i4_header_decoded == 3)
2823
7.14k
        {
2824
7.14k
            ps_dec->u4_total_mbs_coded = ps_dec->ps_cur_sps->u4_max_mb_addr + 1;
2825
7.14k
        }
2826
2827
        /*Update the i4_frametype at the end of picture*/
2828
7.14k
        if(ps_dec->ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
2829
2.53k
        {
2830
2.53k
            ps_dec->i4_frametype = IV_IDR_FRAME;
2831
2.53k
        }
2832
4.61k
        else if(ps_dec->i4_pic_type == B_SLICE)
2833
2.50k
        {
2834
2.50k
            ps_dec->i4_frametype = IV_B_FRAME;
2835
2.50k
        }
2836
2.10k
        else if(ps_dec->i4_pic_type == P_SLICE)
2837
1.40k
        {
2838
1.40k
            ps_dec->i4_frametype = IV_P_FRAME;
2839
1.40k
        }
2840
704
        else if(ps_dec->i4_pic_type == I_SLICE)
2841
322
        {
2842
322
            ps_dec->i4_frametype = IV_I_FRAME;
2843
322
        }
2844
382
        else
2845
382
        {
2846
382
            H264_DEC_DEBUG_PRINT("Shouldn't come here\n");
2847
382
        }
2848
2849
        //Update the content type
2850
7.14k
        ps_dec->i4_content_type = ps_dec->ps_cur_slice->u1_field_pic_flag;
2851
2852
7.14k
        ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded + 2;
2853
7.14k
        ps_dec->u4_total_frames_decoded = ps_dec->u4_total_frames_decoded
2854
7.14k
                        - ps_dec->ps_cur_slice->u1_field_pic_flag;
2855
2856
7.14k
    }
2857
2858
    /* close deblock thread if it is not closed yet*/
2859
8.71k
    if(!ps_dec->i4_threads_active)
2860
0
    {
2861
0
        if(ps_dec->u4_num_cores == 3)
2862
0
        {
2863
0
            ih264d_signal_bs_deblk_thread(ps_dec);
2864
0
        }
2865
0
    }
2866
2867
2868
8.71k
    {
2869
        /* In case the decoder is configured to run in low delay mode,
2870
         * then get display buffer and then format convert.
2871
         * Note in this mode, format conversion does not run paralelly in a thread and adds to the codec cycles
2872
         */
2873
2874
8.71k
        if((IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode)
2875
0
                        && ps_dec->u1_init_dec_flag)
2876
0
        {
2877
2878
0
            ih264d_get_next_display_field(ps_dec, ps_dec->ps_out_buffer,
2879
0
                                          &(ps_dec->s_disp_op));
2880
0
            if(0 == ps_dec->s_disp_op.u4_error_code)
2881
0
            {
2882
0
                ps_dec->u4_fmt_conv_cur_row = 0;
2883
0
                ps_dec->u4_output_present = 1;
2884
0
            }
2885
0
        }
2886
2887
8.71k
        ih264d_fill_output_struct_from_context(ps_dec, ps_dec_op);
2888
2889
        /* If Format conversion is not complete,
2890
         complete it here */
2891
8.71k
        if(ps_dec->u4_output_present &&
2892
5.06k
          (ps_dec->u4_fmt_conv_cur_row < ps_dec->s_disp_frame_info.u4_y_ht))
2893
1.74k
        {
2894
1.74k
            ps_dec->u4_fmt_conv_num_rows = ps_dec->s_disp_frame_info.u4_y_ht
2895
1.74k
                            - ps_dec->u4_fmt_conv_cur_row;
2896
1.74k
            ih264d_format_convert(ps_dec, &(ps_dec->s_disp_op),
2897
1.74k
                                  ps_dec->u4_fmt_conv_cur_row,
2898
1.74k
                                  ps_dec->u4_fmt_conv_num_rows);
2899
1.74k
            ps_dec->u4_fmt_conv_cur_row += ps_dec->u4_fmt_conv_num_rows;
2900
1.74k
        }
2901
2902
8.71k
        ih264d_release_display_field(ps_dec, &(ps_dec->s_disp_op));
2903
8.71k
    }
2904
2905
8.71k
    if(ps_dec->i4_decode_header == 1 && (ps_dec->i4_header_decoded & 1) == 1)
2906
254
    {
2907
254
        ps_dec_op->u4_progressive_frame_flag = 1;
2908
254
        if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
2909
254
        {
2910
254
            if((0 == ps_dec->ps_sps->u1_frame_mbs_only_flag)
2911
185
                            && (0 == ps_dec->ps_sps->u1_mb_aff_flag))
2912
77
                ps_dec_op->u4_progressive_frame_flag = 0;
2913
2914
254
        }
2915
254
    }
2916
2917
8.71k
    if((TOP_FIELD_ONLY | BOT_FIELD_ONLY) == ps_dec->u1_top_bottom_decoded)
2918
4.52k
    {
2919
4.52k
        ps_dec->u1_top_bottom_decoded = 0;
2920
4.52k
    }
2921
    /*--------------------------------------------------------------------*/
2922
    /* Do End of Pic processing.                                          */
2923
    /* Should be called only if frame was decoded in previous process call*/
2924
    /*--------------------------------------------------------------------*/
2925
8.71k
    if(ps_dec->u4_pic_buf_got == 1)
2926
7.14k
    {
2927
7.14k
        if(1 == ps_dec->u1_last_pic_not_decoded)
2928
0
        {
2929
0
            ret = ih264d_end_of_pic_dispbuf_mgr(ps_dec);
2930
2931
0
            if(ret != OK)
2932
0
                return ret;
2933
2934
0
            ret = ih264d_end_of_pic(ps_dec);
2935
0
            if(ret != OK)
2936
0
                return ret;
2937
0
        }
2938
7.14k
        else
2939
7.14k
        {
2940
7.14k
            ret = ih264d_end_of_pic(ps_dec);
2941
7.14k
            if(ret != OK)
2942
0
                return ret;
2943
7.14k
        }
2944
2945
7.14k
    }
2946
2947
8.71k
    if(ps_dec->u1_enable_mb_info && ps_dec->u4_output_present)
2948
0
    {
2949
0
        UWORD32 disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
2950
0
        if(ps_h264d_dec_ip->pu1_8x8_blk_qp_map)
2951
0
        {
2952
0
            ps_h264d_dec_op->pu1_8x8_blk_qp_map = ps_h264d_dec_ip->pu1_8x8_blk_qp_map;
2953
0
            ps_h264d_dec_op->u4_8x8_blk_qp_map_size = ps_dec->u4_total_mbs << 2;
2954
0
            memcpy(ps_h264d_dec_op->pu1_8x8_blk_qp_map,
2955
0
                ps_dec->as_buf_id_info_map[disp_buf_id].pu1_qp_map,
2956
0
                ps_dec->u4_total_mbs << 2);
2957
0
        }
2958
0
        if(ps_h264d_dec_ip->pu1_8x8_blk_type_map)
2959
0
        {
2960
0
            ps_h264d_dec_op->pu1_8x8_blk_type_map = ps_h264d_dec_ip->pu1_8x8_blk_type_map;
2961
0
            ps_h264d_dec_op->u4_8x8_blk_type_map_size = ps_dec->u4_total_mbs << 2;
2962
0
            memcpy(ps_h264d_dec_op->pu1_8x8_blk_type_map,
2963
0
                ps_dec->as_buf_id_info_map[disp_buf_id].pu1_mb_type_map,
2964
0
                ps_dec->u4_total_mbs << 2);
2965
0
        }
2966
0
    }
2967
2968
    /*Data memory barrier instruction,so that yuv write by the library is complete*/
2969
8.71k
    DATA_SYNC();
2970
2971
8.71k
    H264_DEC_DEBUG_PRINT("The num bytes consumed: %d\n",
2972
8.71k
                         ps_dec_op->u4_num_bytes_consumed);
2973
8.71k
    return api_ret_value;
2974
8.71k
}
2975
2976
WORD32 ih264d_get_version(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
2977
0
{
2978
0
    char version_string[MAXVERSION_STRLEN + 1];
2979
0
    UWORD32 version_string_len;
2980
2981
0
    ivd_ctl_getversioninfo_ip_t *ps_ip;
2982
0
    ivd_ctl_getversioninfo_op_t *ps_op;
2983
2984
0
    ps_ip = (ivd_ctl_getversioninfo_ip_t *)pv_api_ip;
2985
0
    ps_op = (ivd_ctl_getversioninfo_op_t *)pv_api_op;
2986
0
    UNUSED(dec_hdl);
2987
0
    ps_op->u4_error_code = IV_SUCCESS;
2988
2989
0
    VERSION(version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
2990
0
            CODEC_VENDOR);
2991
2992
0
    if((WORD32)ps_ip->u4_version_buffer_size <= 0)
2993
0
    {
2994
0
        ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
2995
0
        return (IV_FAIL);
2996
0
    }
2997
2998
0
    version_string_len = strnlen(version_string, MAXVERSION_STRLEN) + 1;
2999
3000
0
    if(ps_ip->u4_version_buffer_size >= version_string_len) //(WORD32)sizeof(sizeof(version_string)))
3001
0
    {
3002
0
        memcpy(ps_ip->pv_version_buffer, version_string, version_string_len);
3003
0
        ps_op->u4_error_code = IV_SUCCESS;
3004
0
    }
3005
0
    else
3006
0
    {
3007
0
        ps_op->u4_error_code = IH264D_VERS_BUF_INSUFFICIENT;
3008
0
        return IV_FAIL;
3009
0
    }
3010
0
    return (IV_SUCCESS);
3011
0
}
3012
3013
/*****************************************************************************/
3014
/*                                                                           */
3015
/*  Function Name :   ih264d_get_display_frame                               */
3016
/*                                                                           */
3017
/*  Description   :                                                          */
3018
/*  Inputs        :iv_obj_t decoder handle                                   */
3019
/*                :pv_api_ip pointer to input structure                      */
3020
/*                :pv_api_op pointer to output structure                     */
3021
/*  Outputs       :                                                          */
3022
/*  Returns       : void                                                     */
3023
/*                                                                           */
3024
/*  Issues        : none                                                     */
3025
/*                                                                           */
3026
/*  Revision History:                                                        */
3027
/*                                                                           */
3028
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3029
/*         22 10 2008    100356         Draft                                */
3030
/*                                                                           */
3031
/*****************************************************************************/
3032
WORD32 ih264d_get_display_frame(iv_obj_t *dec_hdl,
3033
                                void *pv_api_ip,
3034
                                void *pv_api_op)
3035
0
{
3036
3037
0
    UNUSED(dec_hdl);
3038
0
    UNUSED(pv_api_ip);
3039
0
    UNUSED(pv_api_op);
3040
    // This function is no longer needed, output is returned in the process()
3041
0
    return IV_FAIL;
3042
0
}
3043
3044
/*****************************************************************************/
3045
/*                                                                           */
3046
/*  Function Name :  ih264d_set_display_frame                                */
3047
/*                                                                           */
3048
/*  Description   :                                                          */
3049
/*                                                                           */
3050
/*  Inputs        :iv_obj_t decoder handle                                   */
3051
/*                :pv_api_ip pointer to input structure                      */
3052
/*                :pv_api_op pointer to output structure                     */
3053
/*  Outputs       :                                                          */
3054
/*  Returns       : void                                                     */
3055
/*                                                                           */
3056
/*  Issues        : none                                                     */
3057
/*                                                                           */
3058
/*  Revision History:                                                        */
3059
/*                                                                           */
3060
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3061
/*         22 10 2008    100356         Draft                                */
3062
/*                                                                           */
3063
/*****************************************************************************/
3064
WORD32 ih264d_set_display_frame(iv_obj_t *dec_hdl,
3065
                                void *pv_api_ip,
3066
                                void *pv_api_op)
3067
0
{
3068
3069
0
    UWORD32 u4_disp_buf_size[3], u4_num_disp_bufs;
3070
0
    ivd_set_display_frame_ip_t *dec_disp_ip;
3071
0
    ivd_set_display_frame_op_t *dec_disp_op;
3072
3073
0
    UWORD32 i;
3074
0
    dec_struct_t * ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3075
3076
0
    dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
3077
0
    dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
3078
0
    dec_disp_op->u4_error_code = 0;
3079
3080
3081
0
    ps_dec->u4_num_disp_bufs = 0;
3082
0
    if(ps_dec->u4_share_disp_buf)
3083
0
    {
3084
0
        UWORD32 u4_num_bufs = dec_disp_ip->num_disp_bufs;
3085
3086
0
        u4_num_bufs = MIN(u4_num_bufs, MAX_DISP_BUFS_NEW);
3087
3088
0
        ps_dec->u4_num_disp_bufs = u4_num_bufs;
3089
3090
        /* Get the number and sizes of the first buffer. Compare this with the
3091
         * rest to make sure all the buffers are of the same size.
3092
         */
3093
0
        u4_num_disp_bufs = dec_disp_ip->s_disp_buffer[0].u4_num_bufs;
3094
3095
0
        u4_disp_buf_size[0] =
3096
0
          dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[0];
3097
0
        u4_disp_buf_size[1] =
3098
0
          dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[1];
3099
0
        u4_disp_buf_size[2] =
3100
0
          dec_disp_ip->s_disp_buffer[0].u4_min_out_buf_size[2];
3101
3102
0
        for(i = 0; i < u4_num_bufs; i++)
3103
0
        {
3104
0
            if(dec_disp_ip->s_disp_buffer[i].u4_num_bufs != u4_num_disp_bufs)
3105
0
            {
3106
0
                return IV_FAIL;
3107
0
            }
3108
3109
0
            if((dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0]
3110
0
                != u4_disp_buf_size[0])
3111
0
                || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1]
3112
0
                    != u4_disp_buf_size[1])
3113
0
                || (dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2]
3114
0
                    != u4_disp_buf_size[2]))
3115
0
            {
3116
0
                return IV_FAIL;
3117
0
            }
3118
3119
0
            ps_dec->disp_bufs[i].u4_num_bufs =
3120
0
                            dec_disp_ip->s_disp_buffer[i].u4_num_bufs;
3121
3122
0
            ps_dec->disp_bufs[i].buf[0] =
3123
0
                            dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
3124
0
            ps_dec->disp_bufs[i].buf[1] =
3125
0
                            dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
3126
0
            ps_dec->disp_bufs[i].buf[2] =
3127
0
                            dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
3128
3129
0
            ps_dec->disp_bufs[i].u4_bufsize[0] =
3130
0
                            dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[0];
3131
0
            ps_dec->disp_bufs[i].u4_bufsize[1] =
3132
0
                            dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[1];
3133
0
            ps_dec->disp_bufs[i].u4_bufsize[2] =
3134
0
                            dec_disp_ip->s_disp_buffer[i].u4_min_out_buf_size[2];
3135
3136
0
        }
3137
0
    }
3138
0
    return IV_SUCCESS;
3139
3140
0
}
3141
3142
/*****************************************************************************/
3143
/*                                                                           */
3144
/*  Function Name : ih264d_set_flush_mode                                    */
3145
/*                                                                           */
3146
/*  Description   :                                                          */
3147
/*                                                                           */
3148
/*  Inputs        :iv_obj_t decoder handle                                   */
3149
/*                :pv_api_ip pointer to input structure                      */
3150
/*                :pv_api_op pointer to output structure                     */
3151
/*  Globals       : <Does it use any global variables?>                      */
3152
/*  Outputs       :                                                          */
3153
/*  Returns       : void                                                     */
3154
/*                                                                           */
3155
/*  Issues        : none                                                     */
3156
/*                                                                           */
3157
/*  Revision History:                                                        */
3158
/*                                                                           */
3159
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3160
/*         22 10 2008    100356         Draft                                */
3161
/*                                                                           */
3162
/*****************************************************************************/
3163
WORD32 ih264d_set_flush_mode(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3164
0
{
3165
0
    dec_struct_t * ps_dec;
3166
0
    ivd_ctl_flush_op_t *ps_ctl_op = (ivd_ctl_flush_op_t*)pv_api_op;
3167
0
    ps_ctl_op->u4_error_code = 0;
3168
3169
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3170
0
    ih264d_join_threads(ps_dec);
3171
0
    UNUSED(pv_api_ip);
3172
    /* ! */
3173
    /* Signal flush frame control call */
3174
0
    ps_dec->u1_flushfrm = 1;
3175
3176
0
    if(ps_dec->u1_init_dec_flag == 1)
3177
0
    {
3178
0
        ih264d_release_pics_in_dpb((void *)ps_dec, ps_dec->u1_pic_bufs);
3179
0
        ih264d_release_display_bufs(ps_dec);
3180
0
    }
3181
3182
0
    ps_ctl_op->u4_error_code = 0;
3183
3184
    /* Ignore dangling fields during flush */
3185
0
    ps_dec->u1_top_bottom_decoded = 0;
3186
3187
0
    return IV_SUCCESS;
3188
0
}
3189
3190
/*****************************************************************************/
3191
/*                                                                           */
3192
/*  Function Name : ih264d_get_status                                        */
3193
/*                                                                           */
3194
/*  Description   :                                                          */
3195
/*                                                                           */
3196
/*  Inputs        :iv_obj_t decoder handle                                   */
3197
/*                :pv_api_ip pointer to input structure                      */
3198
/*                :pv_api_op pointer to output structure                     */
3199
/*  Globals       : <Does it use any global variables?>                      */
3200
/*  Outputs       :                                                          */
3201
/*  Returns       : void                                                     */
3202
/*                                                                           */
3203
/*  Issues        : none                                                     */
3204
/*                                                                           */
3205
/*  Revision History:                                                        */
3206
/*                                                                           */
3207
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3208
/*         22 10 2008    100356         Draft                                */
3209
/*                                                                           */
3210
/*****************************************************************************/
3211
3212
WORD32 ih264d_get_status(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3213
0
{
3214
3215
0
    UWORD32 i;
3216
0
    dec_struct_t * ps_dec;
3217
0
    UWORD32 pic_wd, pic_ht;
3218
0
    ivd_ctl_getstatus_op_t *ps_ctl_op = (ivd_ctl_getstatus_op_t*)pv_api_op;
3219
0
    UNUSED(pv_api_ip);
3220
0
    ps_ctl_op->u4_error_code = 0;
3221
3222
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3223
3224
3225
0
    if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3226
0
    {
3227
0
        ps_ctl_op->u4_pic_ht = ps_dec->u2_disp_height;
3228
0
        ps_ctl_op->u4_pic_wd = ps_dec->u2_disp_width;
3229
3230
0
        if(0 == ps_dec->u4_share_disp_buf)
3231
0
        {
3232
0
            pic_wd = ps_dec->u2_disp_width;
3233
0
            pic_ht = ps_dec->u2_disp_height;
3234
3235
0
        }
3236
0
        else
3237
0
        {
3238
0
            pic_wd = ps_dec->u2_frm_wd_y;
3239
0
            pic_ht = ps_dec->u2_frm_ht_y;
3240
0
        }
3241
0
    }
3242
0
    else
3243
0
    {
3244
0
        pic_wd = 0;
3245
0
        pic_ht = 0;
3246
3247
0
        ps_ctl_op->u4_pic_ht = pic_wd;
3248
0
        ps_ctl_op->u4_pic_wd = pic_ht;
3249
3250
0
        if(1 == ps_dec->u4_share_disp_buf)
3251
0
        {
3252
0
            pic_wd += (PAD_LEN_Y_H << 1);
3253
0
            pic_ht += (PAD_LEN_Y_V << 2);
3254
3255
0
        }
3256
3257
0
    }
3258
3259
0
    if(ps_dec->u4_app_disp_width > pic_wd)
3260
0
        pic_wd = ps_dec->u4_app_disp_width;
3261
0
    if(0 == ps_dec->u4_share_disp_buf)
3262
0
        ps_ctl_op->u4_num_disp_bufs = 1;
3263
0
    else
3264
0
    {
3265
0
        if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3266
0
        {
3267
0
            if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3268
0
               (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3269
0
            {
3270
0
                ps_ctl_op->u4_num_disp_bufs =
3271
0
                                ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3272
0
            }
3273
0
            else
3274
0
            {
3275
                /*if VUI is not present assume maximum possible refrence frames for the level,
3276
                 * as max reorder frames*/
3277
0
                ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3278
0
            }
3279
3280
0
            ps_ctl_op->u4_num_disp_bufs +=
3281
0
                            ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3282
0
        }
3283
0
        else
3284
0
        {
3285
0
            ps_ctl_op->u4_num_disp_bufs = 32;
3286
0
        }
3287
0
        ps_ctl_op->u4_num_disp_bufs = MAX(
3288
0
                        ps_ctl_op->u4_num_disp_bufs, 6);
3289
0
        ps_ctl_op->u4_num_disp_bufs = MIN(
3290
0
                        ps_ctl_op->u4_num_disp_bufs, 32);
3291
0
    }
3292
3293
0
    ps_ctl_op->u4_error_code = ps_dec->i4_error_code;
3294
3295
0
    ps_ctl_op->u4_frame_rate = 0; //make it proper
3296
0
    ps_ctl_op->u4_bit_rate = 0; //make it proper
3297
0
    ps_ctl_op->e_content_type = ps_dec->i4_content_type;
3298
0
    ps_ctl_op->e_output_chroma_format = ps_dec->u1_chroma_format;
3299
0
    ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3300
3301
0
    if(ps_dec->u1_chroma_format == IV_YUV_420P)
3302
0
    {
3303
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420;
3304
0
    }
3305
0
    else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3306
0
    {
3307
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
3308
0
    }
3309
0
    else if(ps_dec->u1_chroma_format == IV_RGB_565)
3310
0
    {
3311
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
3312
0
    }
3313
0
    else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3314
0
                    || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3315
0
    {
3316
0
        ps_ctl_op->u4_min_num_out_bufs = MIN_OUT_BUFS_420SP;
3317
0
    }
3318
3319
0
    else
3320
0
    {
3321
        //Invalid chroma format; Error code may be updated, verify in testing if needed
3322
0
        ps_ctl_op->u4_error_code = ERROR_FEATURE_UNAVAIL;
3323
0
        return IV_FAIL;
3324
0
    }
3325
3326
0
    for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3327
0
    {
3328
0
        ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
3329
0
    }
3330
3331
    /*!*/
3332
0
    if(ps_dec->u1_chroma_format == IV_YUV_420P)
3333
0
    {
3334
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3335
0
        ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3336
0
                        >> 2;
3337
0
        ps_ctl_op->u4_min_out_buf_size[2] = (pic_wd * pic_ht)
3338
0
                        >> 2;
3339
0
    }
3340
0
    else if(ps_dec->u1_chroma_format == IV_YUV_422ILE)
3341
0
    {
3342
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3343
0
                        * 2;
3344
0
        ps_ctl_op->u4_min_out_buf_size[1] =
3345
0
                        ps_ctl_op->u4_min_out_buf_size[2] = 0;
3346
0
    }
3347
0
    else if(ps_dec->u1_chroma_format == IV_RGB_565)
3348
0
    {
3349
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht)
3350
0
                        * 2;
3351
0
        ps_ctl_op->u4_min_out_buf_size[1] =
3352
0
                        ps_ctl_op->u4_min_out_buf_size[2] = 0;
3353
0
    }
3354
0
    else if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
3355
0
                    || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
3356
0
    {
3357
0
        ps_ctl_op->u4_min_out_buf_size[0] = (pic_wd * pic_ht);
3358
0
        ps_ctl_op->u4_min_out_buf_size[1] = (pic_wd * pic_ht)
3359
0
                        >> 1;
3360
0
        ps_ctl_op->u4_min_out_buf_size[2] = 0;
3361
0
    }
3362
3363
0
    ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3364
0
    return IV_SUCCESS;
3365
0
}
3366
3367
/*****************************************************************************/
3368
/*                                                                           */
3369
/*  Function Name :    ih264d_get_buf_info                                   */
3370
/*                                                                           */
3371
/*  Description   :                                                          */
3372
/*                                                                           */
3373
/*  Inputs        :iv_obj_t decoder handle                                   */
3374
/*                :pv_api_ip pointer to input structure                      */
3375
/*                :pv_api_op pointer to output structure                     */
3376
/*  Globals       : <Does it use any global variables?>                      */
3377
/*  Outputs       :                                                          */
3378
/*  Returns       : void                                                     */
3379
/*                                                                           */
3380
/*  Issues        : none                                                     */
3381
/*                                                                           */
3382
/*  Revision History:                                                        */
3383
/*                                                                           */
3384
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3385
/*         22 10 2008    100356         Draft                                */
3386
/*                                                                           */
3387
/*****************************************************************************/
3388
WORD32 ih264d_get_buf_info(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3389
0
{
3390
3391
0
    dec_struct_t * ps_dec;
3392
0
    UWORD8 i = 0; // Default for 420P format
3393
0
    UWORD16 pic_wd, pic_ht;
3394
0
    ivd_ctl_getbufinfo_op_t *ps_ctl_op =
3395
0
                    (ivd_ctl_getbufinfo_op_t*)pv_api_op;
3396
0
    UWORD32 au4_min_out_buf_size[IVD_VIDDEC_MAX_IO_BUFFERS];
3397
0
    UNUSED(pv_api_ip);
3398
3399
0
    ps_ctl_op->u4_error_code = 0;
3400
3401
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3402
3403
0
    ps_ctl_op->u4_min_num_in_bufs = MIN_IN_BUFS;
3404
3405
3406
0
    ps_ctl_op->u4_num_disp_bufs = 1;
3407
3408
3409
0
    pic_wd = 0;
3410
0
    pic_ht = 0;
3411
3412
0
    if(ps_dec->i4_header_decoded == 3)
3413
0
    {
3414
3415
0
        if(0 == ps_dec->u4_share_disp_buf)
3416
0
        {
3417
0
            pic_wd = ps_dec->u2_disp_width;
3418
0
            pic_ht = ps_dec->u2_disp_height;
3419
3420
0
        }
3421
0
        else
3422
0
        {
3423
0
            pic_wd = ps_dec->u2_frm_wd_y;
3424
0
            pic_ht = ps_dec->u2_frm_ht_y;
3425
0
        }
3426
3427
0
    }
3428
3429
0
    for(i = 0; i < ps_ctl_op->u4_min_num_in_bufs; i++)
3430
0
    {
3431
0
        ps_ctl_op->u4_min_in_buf_size[i] = MAX(256000, pic_wd * pic_ht * 3 / 2);
3432
0
    }
3433
0
    if((WORD32)ps_dec->u4_app_disp_width > pic_wd)
3434
0
        pic_wd = ps_dec->u4_app_disp_width;
3435
3436
0
    if(0 == ps_dec->u4_share_disp_buf)
3437
0
        ps_ctl_op->u4_num_disp_bufs = 1;
3438
0
    else
3439
0
    {
3440
0
        if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3441
0
        {
3442
0
            if((ps_dec->ps_cur_sps->u1_vui_parameters_present_flag == 1) &&
3443
0
               (1 == ps_dec->ps_cur_sps->s_vui.u1_bitstream_restriction_flag))
3444
0
            {
3445
0
                ps_ctl_op->u4_num_disp_bufs =
3446
0
                                ps_dec->ps_cur_sps->s_vui.u4_num_reorder_frames + 1;
3447
0
            }
3448
0
            else
3449
0
            {
3450
                /*if VUI is not present assume maximum possible refrence frames for the level,
3451
                 * as max reorder frames*/
3452
0
                ps_ctl_op->u4_num_disp_bufs = ih264d_get_dpb_size(ps_dec->ps_cur_sps);
3453
0
            }
3454
3455
0
            ps_ctl_op->u4_num_disp_bufs +=
3456
0
                            ps_dec->ps_cur_sps->u1_num_ref_frames + 1;
3457
3458
0
        }
3459
0
        else
3460
0
        {
3461
0
            ps_ctl_op->u4_num_disp_bufs = 32;
3462
3463
0
        }
3464
3465
0
        ps_ctl_op->u4_num_disp_bufs = MAX(
3466
0
                        ps_ctl_op->u4_num_disp_bufs, 6);
3467
0
        ps_ctl_op->u4_num_disp_bufs = MIN(
3468
0
                        ps_ctl_op->u4_num_disp_bufs, 32);
3469
0
    }
3470
3471
0
    ps_ctl_op->u4_min_num_out_bufs = ih264d_get_outbuf_size(
3472
0
                    pic_wd, pic_ht, ps_dec->u1_chroma_format,
3473
0
                    &au4_min_out_buf_size[0]);
3474
3475
0
    for(i = 0; i < ps_ctl_op->u4_min_num_out_bufs; i++)
3476
0
    {
3477
0
        ps_ctl_op->u4_min_out_buf_size[i] = au4_min_out_buf_size[i];
3478
0
    }
3479
3480
0
    ps_dec->u4_num_disp_bufs_requested = ps_ctl_op->u4_num_disp_bufs;
3481
3482
0
    return IV_SUCCESS;
3483
0
}
3484
3485
/*****************************************************************************/
3486
/*                                                                           */
3487
/*  Function Name : ih264d_set_params                                        */
3488
/*                                                                           */
3489
/*  Description   :                                                          */
3490
/*                                                                           */
3491
/*  Inputs        :iv_obj_t decoder handle                                   */
3492
/*                :pv_api_ip pointer to input structure                      */
3493
/*                :pv_api_op pointer to output structure                     */
3494
/*  Outputs       :                                                          */
3495
/*  Returns       : void                                                     */
3496
/*                                                                           */
3497
/*  Issues        : none                                                     */
3498
/*                                                                           */
3499
/*  Revision History:                                                        */
3500
/*                                                                           */
3501
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3502
/*         22 10 2008    100356         Draft                                */
3503
/*                                                                           */
3504
/*****************************************************************************/
3505
WORD32 ih264d_set_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3506
614
{
3507
3508
614
    dec_struct_t * ps_dec;
3509
614
    WORD32 ret = IV_SUCCESS;
3510
3511
614
    ih264d_ctl_set_config_ip_t *ps_h264d_ctl_ip =
3512
614
                    (ih264d_ctl_set_config_ip_t *)pv_api_ip;
3513
614
    ih264d_ctl_set_config_op_t *ps_h264d_ctl_op =
3514
614
                    (ih264d_ctl_set_config_op_t *)pv_api_op;
3515
614
    ivd_ctl_set_config_ip_t *ps_ctl_ip =
3516
614
                    &ps_h264d_ctl_ip->s_ivd_ctl_set_config_ip_t;
3517
614
    ivd_ctl_set_config_op_t *ps_ctl_op =
3518
614
                    &ps_h264d_ctl_op->s_ivd_ctl_set_config_op_t;
3519
3520
614
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3521
3522
614
    ps_dec->u4_skip_frm_mask = 0;
3523
3524
614
    ps_ctl_op->u4_error_code = 0;
3525
3526
614
    if(ps_ctl_ip->e_frm_skip_mode != IVD_SKIP_NONE)
3527
0
    {
3528
0
        ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3529
0
        ret = IV_FAIL;
3530
0
    }
3531
3532
614
    if(ps_ctl_ip->u4_disp_wd >= ps_dec->u2_disp_width)
3533
344
    {
3534
344
        ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3535
344
    }
3536
270
    else if(0 == ps_dec->i4_header_decoded)
3537
7
    {
3538
7
        ps_dec->u4_app_disp_width = ps_ctl_ip->u4_disp_wd;
3539
7
    }
3540
263
    else if(ps_ctl_ip->u4_disp_wd == 0)
3541
263
    {
3542
263
        ps_dec->u4_app_disp_width = 0;
3543
263
    }
3544
0
    else
3545
0
    {
3546
        /*
3547
         * Set the display width to zero. This will ensure that the wrong value we had stored (0xFFFFFFFF)
3548
         * does not propogate.
3549
         */
3550
0
        ps_dec->u4_app_disp_width = 0;
3551
0
        ps_ctl_op->u4_error_code |= (1 << IVD_UNSUPPORTEDPARAM);
3552
0
        ps_ctl_op->u4_error_code |= ERROR_DISP_WIDTH_INVALID;
3553
0
        ret = IV_FAIL;
3554
0
    }
3555
3556
614
    if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_FRAME)
3557
307
        ps_dec->i4_decode_header = 0;
3558
307
    else if(ps_ctl_ip->e_vid_dec_mode == IVD_DECODE_HEADER)
3559
307
        ps_dec->i4_decode_header = 1;
3560
0
    else
3561
0
    {
3562
0
        ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3563
0
        ps_dec->i4_decode_header = 1;
3564
0
        ret = IV_FAIL;
3565
0
    }
3566
614
    ps_dec->e_frm_out_mode = IVD_DISPLAY_FRAME_OUT;
3567
3568
614
    if((ps_ctl_ip->e_frm_out_mode != IVD_DECODE_FRAME_OUT) &&
3569
614
       (ps_ctl_ip->e_frm_out_mode != IVD_DISPLAY_FRAME_OUT))
3570
0
    {
3571
0
        ps_ctl_op->u4_error_code = (1 << IVD_UNSUPPORTEDPARAM);
3572
0
        ret = IV_FAIL;
3573
0
    }
3574
614
    ps_dec->e_frm_out_mode = ps_ctl_ip->e_frm_out_mode;
3575
614
    return ret;
3576
3577
614
}
3578
3579
/*****************************************************************************/
3580
/*                                                                           */
3581
/*  Function Name : ih264d_set_default_params                                */
3582
/*                                                                           */
3583
/*  Description   :                                                          */
3584
/*                                                                           */
3585
/*  Inputs        :iv_obj_t decoder handle                                   */
3586
/*                :pv_api_ip pointer to input structure                      */
3587
/*                :pv_api_op pointer to output structure                     */
3588
/*  Outputs       :                                                          */
3589
/*  Returns       : void                                                     */
3590
/*                                                                           */
3591
/*  Issues        : none                                                     */
3592
/*                                                                           */
3593
/*  Revision History:                                                        */
3594
/*                                                                           */
3595
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3596
/*         08 08 2011   100421          Copied from set_params               */
3597
/*                                                                           */
3598
/*****************************************************************************/
3599
WORD32 ih264d_set_default_params(iv_obj_t *dec_hdl,
3600
                                 void *pv_api_ip,
3601
                                 void *pv_api_op)
3602
0
{
3603
3604
0
    dec_struct_t * ps_dec;
3605
0
    WORD32 ret = IV_SUCCESS;
3606
3607
0
    ivd_ctl_set_config_op_t *ps_ctl_op =
3608
0
                    (ivd_ctl_set_config_op_t *)pv_api_op;
3609
0
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3610
0
    UNUSED(pv_api_ip);
3611
3612
3613
0
    {
3614
0
        ps_dec->u4_app_disp_width = 0;
3615
0
        ps_dec->u4_skip_frm_mask = 0;
3616
0
        ps_dec->i4_decode_header = 1;
3617
3618
0
        ps_ctl_op->u4_error_code = 0;
3619
0
    }
3620
3621
3622
0
    return ret;
3623
0
}
3624
/*****************************************************************************/
3625
/*                                                                           */
3626
/*  Function Name :  ih264d_reset                                            */
3627
/*                                                                           */
3628
/*  Description   :                                                          */
3629
/*                                                                           */
3630
/*  Inputs        :iv_obj_t decoder handle                                   */
3631
/*                :pv_api_ip pointer to input structure                      */
3632
/*                :pv_api_op pointer to output structure                     */
3633
/*  Globals       : <Does it use any global variables?>                      */
3634
/*  Outputs       :                                                          */
3635
/*  Returns       : void                                                     */
3636
/*                                                                           */
3637
/*  Issues        : none                                                     */
3638
/*                                                                           */
3639
/*  Revision History:                                                        */
3640
/*                                                                           */
3641
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3642
/*         22 10 2008    100356         Draft                                */
3643
/*                                                                           */
3644
/*****************************************************************************/
3645
WORD32 ih264d_delete(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3646
307
{
3647
307
    dec_struct_t *ps_dec;
3648
307
    ih264d_delete_ip_t *ps_ip = (ih264d_delete_ip_t *)pv_api_ip;
3649
307
    ih264d_delete_op_t *ps_op = (ih264d_delete_op_t *)pv_api_op;
3650
3651
307
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3652
307
    UNUSED(ps_ip);
3653
307
    ps_op->s_ivd_delete_op_t.u4_error_code = 0;
3654
307
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_bits_buf_dynamic);
3655
307
    ih264d_free_dynamic_bufs(ps_dec);
3656
307
    ih264d_free_static_bufs(dec_hdl);
3657
307
    return IV_SUCCESS;
3658
307
}
3659
/*****************************************************************************/
3660
/*                                                                           */
3661
/*  Function Name :  ih264d_reset                                            */
3662
/*                                                                           */
3663
/*  Description   :                                                          */
3664
/*                                                                           */
3665
/*  Inputs        :iv_obj_t decoder handle                                   */
3666
/*                :pv_api_ip pointer to input structure                      */
3667
/*                :pv_api_op pointer to output structure                     */
3668
/*  Globals       : <Does it use any global variables?>                      */
3669
/*  Outputs       :                                                          */
3670
/*  Returns       : void                                                     */
3671
/*                                                                           */
3672
/*  Issues        : none                                                     */
3673
/*                                                                           */
3674
/*  Revision History:                                                        */
3675
/*                                                                           */
3676
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3677
/*         22 10 2008    100356         Draft                                */
3678
/*                                                                           */
3679
/*****************************************************************************/
3680
WORD32 ih264d_reset(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3681
1.43k
{
3682
1.43k
    dec_struct_t * ps_dec;
3683
1.43k
    ivd_ctl_reset_op_t *ps_ctl_op = (ivd_ctl_reset_op_t *)pv_api_op;
3684
1.43k
    UNUSED(pv_api_ip);
3685
1.43k
    ps_ctl_op->u4_error_code = 0;
3686
3687
1.43k
    ps_dec = (dec_struct_t *)(dec_hdl->pv_codec_handle);
3688
3689
1.43k
    if(ps_dec != NULL)
3690
1.43k
    {
3691
1.43k
        ih264d_join_threads(ps_dec);
3692
1.43k
        ih264d_init_decoder(ps_dec);
3693
1.43k
    }
3694
0
    else
3695
0
    {
3696
0
        H264_DEC_DEBUG_PRINT(
3697
0
                        "\nReset called without Initializing the decoder\n");
3698
0
        ps_ctl_op->u4_error_code = ERROR_INIT_NOT_DONE;
3699
0
    }
3700
3701
1.43k
    return IV_SUCCESS;
3702
1.43k
}
3703
3704
/*****************************************************************************/
3705
/*                                                                           */
3706
/*  Function Name :  ih264d_ctl                                              */
3707
/*                                                                           */
3708
/*  Description   :                                                          */
3709
/*                                                                           */
3710
/*  Inputs        :iv_obj_t decoder handle                                   */
3711
/*                :pv_api_ip pointer to input structure                      */
3712
/*                :pv_api_op pointer to output structure                     */
3713
/*  Outputs       :                                                          */
3714
/*  Returns       : void                                                     */
3715
/*                                                                           */
3716
/*  Issues        : none                                                     */
3717
/*                                                                           */
3718
/*  Revision History:                                                        */
3719
/*                                                                           */
3720
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3721
/*         22 10 2008    100356         Draft                                */
3722
/*                                                                           */
3723
/*****************************************************************************/
3724
WORD32 ih264d_ctl(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
3725
2.66k
{
3726
2.66k
    ivd_ctl_set_config_ip_t *ps_ctl_ip;
3727
2.66k
    ivd_ctl_set_config_op_t *ps_ctl_op;
3728
2.66k
    WORD32 ret = IV_SUCCESS;
3729
2.66k
    UWORD32 subcommand;
3730
2.66k
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3731
3732
2.66k
    if(ps_dec->init_done != 1)
3733
0
    {
3734
        //Return proper Error Code
3735
0
        return IV_FAIL;
3736
0
    }
3737
2.66k
    ps_ctl_ip = (ivd_ctl_set_config_ip_t*)pv_api_ip;
3738
2.66k
    ps_ctl_op = (ivd_ctl_set_config_op_t*)pv_api_op;
3739
2.66k
    ps_ctl_op->u4_error_code = 0;
3740
2.66k
    subcommand = ps_ctl_ip->e_sub_cmd;
3741
3742
2.66k
    switch(subcommand)
3743
2.66k
    {
3744
0
        case IVD_CMD_CTL_GETPARAMS:
3745
0
            ret = ih264d_get_status(dec_hdl, (void *)pv_api_ip,
3746
0
                                    (void *)pv_api_op);
3747
0
            break;
3748
614
        case IVD_CMD_CTL_SETPARAMS:
3749
614
            ret = ih264d_set_params(dec_hdl, (void *)pv_api_ip,
3750
614
                                    (void *)pv_api_op);
3751
614
            break;
3752
1.43k
        case IVD_CMD_CTL_RESET:
3753
1.43k
            ret = ih264d_reset(dec_hdl, (void *)pv_api_ip, (void *)pv_api_op);
3754
1.43k
            break;
3755
0
        case IVD_CMD_CTL_SETDEFAULT:
3756
0
            ret = ih264d_set_default_params(dec_hdl, (void *)pv_api_ip,
3757
0
                                            (void *)pv_api_op);
3758
0
            break;
3759
0
        case IVD_CMD_CTL_FLUSH:
3760
0
            ret = ih264d_set_flush_mode(dec_hdl, (void *)pv_api_ip,
3761
0
                                        (void *)pv_api_op);
3762
0
            break;
3763
0
        case IVD_CMD_CTL_GETBUFINFO:
3764
0
            ret = ih264d_get_buf_info(dec_hdl, (void *)pv_api_ip,
3765
0
                                      (void *)pv_api_op);
3766
0
            break;
3767
0
        case IVD_CMD_CTL_GETVERSION:
3768
0
            ret = ih264d_get_version(dec_hdl, (void *)pv_api_ip,
3769
0
                                     (void *)pv_api_op);
3770
0
            break;
3771
0
        case IH264D_CMD_CTL_DEGRADE:
3772
0
            ret = ih264d_set_degrade(dec_hdl, (void *)pv_api_ip,
3773
0
                                     (void *)pv_api_op);
3774
0
            break;
3775
3776
307
        case IH264D_CMD_CTL_SET_NUM_CORES:
3777
307
            ret = ih264d_set_num_cores(dec_hdl, (void *)pv_api_ip,
3778
307
                                       (void *)pv_api_op);
3779
307
            break;
3780
0
        case IH264D_CMD_CTL_GET_BUFFER_DIMENSIONS:
3781
0
            ret = ih264d_get_frame_dimensions(dec_hdl, (void *)pv_api_ip,
3782
0
                                              (void *)pv_api_op);
3783
0
            break;
3784
0
        case IH264D_CMD_CTL_GET_VUI_PARAMS:
3785
0
            ret = ih264d_get_vui_params(dec_hdl, (void *)pv_api_ip,
3786
0
                                        (void *)pv_api_op);
3787
0
            break;
3788
0
        case IH264D_CMD_CTL_GET_SEI_MDCV_PARAMS:
3789
0
            ret = ih264d_get_sei_mdcv_params(dec_hdl, (void *)pv_api_ip,
3790
0
                                             (void *)pv_api_op);
3791
0
            break;
3792
0
        case IH264D_CMD_CTL_GET_SEI_CLL_PARAMS:
3793
0
            ret = ih264d_get_sei_cll_params(dec_hdl, (void *)pv_api_ip,
3794
0
                                            (void *)pv_api_op);
3795
0
            break;
3796
0
        case IH264D_CMD_CTL_GET_SEI_AVE_PARAMS:
3797
0
            ret = ih264d_get_sei_ave_params(dec_hdl, (void *)pv_api_ip,
3798
0
                                            (void *)pv_api_op);
3799
0
            break;
3800
0
        case IH264D_CMD_CTL_GET_SEI_CCV_PARAMS:
3801
0
            ret = ih264d_get_sei_ccv_params(dec_hdl, (void *)pv_api_ip,
3802
0
                                            (void *)pv_api_op);
3803
0
            break;
3804
0
        case IH264D_CMD_CTL_GET_SEI_SII_PARAMS:
3805
0
            ret = ih264d_get_sei_sii_params(dec_hdl, (void *) pv_api_ip, (void *) pv_api_op);
3806
0
            break;
3807
3808
0
        case IH264D_CMD_CTL_GET_SEI_FGC_PARAMS:
3809
0
            ret = ih264d_get_sei_fgc_params(dec_hdl, (void *) pv_api_ip, (void *) pv_api_op);
3810
0
            break;
3811
3812
307
        case IH264D_CMD_CTL_SET_PROCESSOR:
3813
307
            ret = ih264d_set_processor(dec_hdl, (void *)pv_api_ip,
3814
307
                                       (void *)pv_api_op);
3815
307
            break;
3816
0
        default:
3817
0
            H264_DEC_DEBUG_PRINT("\ndo nothing\n")
3818
0
            ;
3819
0
            break;
3820
2.66k
    }
3821
3822
2.66k
    return ret;
3823
2.66k
}
3824
/*****************************************************************************/
3825
/*                                                                           */
3826
/*  Function Name :   ih264d_rel_display_frame                               */
3827
/*                                                                           */
3828
/*  Description   :                                                          */
3829
/*                                                                           */
3830
/*  Inputs        :iv_obj_t decoder handle                                   */
3831
/*                :pv_api_ip pointer to input structure                      */
3832
/*                :pv_api_op pointer to output structure                     */
3833
/*  Outputs       :                                                          */
3834
/*  Returns       : void                                                     */
3835
/*                                                                           */
3836
/*  Issues        : none                                                     */
3837
/*                                                                           */
3838
/*  Revision History:                                                        */
3839
/*                                                                           */
3840
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
3841
/*         22 10 2008    100356         Draft                                */
3842
/*                                                                           */
3843
/*****************************************************************************/
3844
WORD32 ih264d_rel_display_frame(iv_obj_t *dec_hdl,
3845
                                void *pv_api_ip,
3846
                                void *pv_api_op)
3847
0
{
3848
3849
0
    ivd_rel_display_frame_ip_t *ps_rel_ip;
3850
0
    ivd_rel_display_frame_op_t *ps_rel_op;
3851
0
    UWORD32 buf_released = 0;
3852
3853
0
    UWORD32 u4_ts = 0;
3854
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3855
3856
0
    ps_rel_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
3857
0
    ps_rel_op = (ivd_rel_display_frame_op_t *)pv_api_op;
3858
0
    ps_rel_op->u4_error_code = 0;
3859
0
    u4_ts = ps_rel_ip->u4_disp_buf_id;
3860
3861
0
    if(0 == ps_dec->u4_share_disp_buf)
3862
0
    {
3863
0
        ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3864
0
        ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 0;
3865
0
        return IV_SUCCESS;
3866
0
    }
3867
3868
0
    if(ps_dec->pv_pic_buf_mgr != NULL)
3869
0
    {
3870
0
        if(1 == ps_dec->u4_disp_buf_mapping[u4_ts])
3871
0
        {
3872
0
            ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
3873
0
                                  ps_rel_ip->u4_disp_buf_id,
3874
0
                                  BUF_MGR_IO);
3875
0
            ps_dec->u4_disp_buf_mapping[u4_ts] = 0;
3876
0
            buf_released = 1;
3877
0
        }
3878
0
    }
3879
3880
0
    if((1 == ps_dec->u4_share_disp_buf) && (0 == buf_released))
3881
0
        ps_dec->u4_disp_buf_to_be_freed[u4_ts] = 1;
3882
3883
0
    return IV_SUCCESS;
3884
0
}
3885
3886
/**
3887
 *******************************************************************************
3888
 *
3889
 * @brief
3890
 *  Sets degrade params
3891
 *
3892
 * @par Description:
3893
 *  Sets degrade params.
3894
 *  Refer to ih264d_ctl_degrade_ip_t definition for details
3895
 *
3896
 * @param[in] ps_codec_obj
3897
 *  Pointer to codec object at API level
3898
 *
3899
 * @param[in] pv_api_ip
3900
 *  Pointer to input argument structure
3901
 *
3902
 * @param[out] pv_api_op
3903
 *  Pointer to output argument structure
3904
 *
3905
 * @returns  Status
3906
 *
3907
 * @remarks
3908
 *
3909
 *
3910
 *******************************************************************************
3911
 */
3912
3913
WORD32 ih264d_set_degrade(iv_obj_t *ps_codec_obj,
3914
                          void *pv_api_ip,
3915
                          void *pv_api_op)
3916
0
{
3917
0
    ih264d_ctl_degrade_ip_t *ps_ip;
3918
0
    ih264d_ctl_degrade_op_t *ps_op;
3919
0
    dec_struct_t *ps_codec = (dec_struct_t *)ps_codec_obj->pv_codec_handle;
3920
3921
0
    ps_ip = (ih264d_ctl_degrade_ip_t *)pv_api_ip;
3922
0
    ps_op = (ih264d_ctl_degrade_op_t *)pv_api_op;
3923
3924
0
    ps_codec->i4_degrade_type = ps_ip->i4_degrade_type;
3925
0
    ps_codec->i4_nondegrade_interval = ps_ip->i4_nondegrade_interval;
3926
0
    ps_codec->i4_degrade_pics = ps_ip->i4_degrade_pics;
3927
3928
0
    ps_op->u4_error_code = 0;
3929
0
    ps_codec->i4_degrade_pic_cnt = 0;
3930
3931
0
    return IV_SUCCESS;
3932
0
}
3933
3934
WORD32 ih264d_get_frame_dimensions(iv_obj_t *dec_hdl,
3935
                                   void *pv_api_ip,
3936
                                   void *pv_api_op)
3937
0
{
3938
0
    ih264d_ctl_get_frame_dimensions_ip_t *ps_ip;
3939
0
    ih264d_ctl_get_frame_dimensions_op_t *ps_op;
3940
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
3941
0
    UWORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
3942
3943
0
    ps_ip = (ih264d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
3944
3945
0
    ps_op = (ih264d_ctl_get_frame_dimensions_op_t *)pv_api_op;
3946
0
    UNUSED(ps_ip);
3947
0
    if((NULL != ps_dec->ps_cur_sps) && (1 == (ps_dec->ps_cur_sps->u1_is_valid)))
3948
0
    {
3949
0
        disp_wd = ps_dec->u2_disp_width;
3950
0
        disp_ht = ps_dec->u2_disp_height;
3951
3952
0
        if(0 == ps_dec->u4_share_disp_buf)
3953
0
        {
3954
0
            buffer_wd = disp_wd;
3955
0
            buffer_ht = disp_ht;
3956
0
        }
3957
0
        else
3958
0
        {
3959
0
            buffer_wd = ps_dec->u2_frm_wd_y;
3960
0
            buffer_ht = ps_dec->u2_frm_ht_y;
3961
0
        }
3962
0
    }
3963
0
    else
3964
0
    {
3965
0
        disp_wd = 0;
3966
0
        disp_ht = 0;
3967
3968
0
        if(0 == ps_dec->u4_share_disp_buf)
3969
0
        {
3970
0
            buffer_wd = disp_wd;
3971
0
            buffer_ht = disp_ht;
3972
0
        }
3973
0
        else
3974
0
        {
3975
0
            buffer_wd = ALIGN16(disp_wd) + (PAD_LEN_Y_H << 1);
3976
0
            buffer_ht = ALIGN16(disp_ht) + (PAD_LEN_Y_V << 2);
3977
0
        }
3978
0
    }
3979
0
    if(ps_dec->u4_app_disp_width > buffer_wd)
3980
0
        buffer_wd = ps_dec->u4_app_disp_width;
3981
3982
0
    if(0 == ps_dec->u4_share_disp_buf)
3983
0
    {
3984
0
        x_offset = 0;
3985
0
        y_offset = 0;
3986
0
    }
3987
0
    else
3988
0
    {
3989
0
        y_offset = (PAD_LEN_Y_V << 1);
3990
0
        x_offset = PAD_LEN_Y_H;
3991
3992
0
        if((NULL != ps_dec->ps_sps) && (1 == (ps_dec->ps_sps->u1_is_valid))
3993
0
                        && (0 != ps_dec->u2_crop_offset_y))
3994
0
        {
3995
0
            y_offset += ps_dec->u2_crop_offset_y / ps_dec->u2_frm_wd_y;
3996
0
            x_offset += ps_dec->u2_crop_offset_y % ps_dec->u2_frm_wd_y;
3997
0
        }
3998
0
    }
3999
4000
0
    ps_op->u4_disp_wd[0] = disp_wd;
4001
0
    ps_op->u4_disp_ht[0] = disp_ht;
4002
0
    ps_op->u4_buffer_wd[0] = buffer_wd;
4003
0
    ps_op->u4_buffer_ht[0] = buffer_ht;
4004
0
    ps_op->u4_x_offset[0] = x_offset;
4005
0
    ps_op->u4_y_offset[0] = y_offset;
4006
4007
0
    ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
4008
0
                    >> 1);
4009
0
    ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
4010
0
                    >> 1);
4011
0
    ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
4012
0
                    >> 1);
4013
0
    ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
4014
0
                    >> 1);
4015
0
    ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] =
4016
0
                    (ps_op->u4_x_offset[0] >> 1);
4017
0
    ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] =
4018
0
                    (ps_op->u4_y_offset[0] >> 1);
4019
4020
0
    if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
4021
0
                    || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU))
4022
0
    {
4023
0
        ps_op->u4_disp_wd[2] = 0;
4024
0
        ps_op->u4_disp_ht[2] = 0;
4025
0
        ps_op->u4_buffer_wd[2] = 0;
4026
0
        ps_op->u4_buffer_ht[2] = 0;
4027
0
        ps_op->u4_x_offset[2] = 0;
4028
0
        ps_op->u4_y_offset[2] = 0;
4029
4030
0
        ps_op->u4_disp_wd[1] <<= 1;
4031
0
        ps_op->u4_buffer_wd[1] <<= 1;
4032
0
        ps_op->u4_x_offset[1] <<= 1;
4033
0
    }
4034
4035
0
    return IV_SUCCESS;
4036
4037
0
}
4038
4039
WORD32 ih264d_get_vui_params(iv_obj_t *dec_hdl,
4040
                             void *pv_api_ip,
4041
                             void *pv_api_op)
4042
0
{
4043
0
    ih264d_ctl_get_vui_params_ip_t *ps_ip;
4044
0
    ih264d_ctl_get_vui_params_op_t *ps_op;
4045
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4046
0
    dec_seq_params_t *ps_sps;
4047
0
    vui_t *ps_vui;
4048
0
    WORD32 i;
4049
0
    UWORD32 u4_size;
4050
4051
0
    ps_ip = (ih264d_ctl_get_vui_params_ip_t *)pv_api_ip;
4052
0
    ps_op = (ih264d_ctl_get_vui_params_op_t *)pv_api_op;
4053
0
    UNUSED(ps_ip);
4054
4055
0
    u4_size = ps_op->u4_size;
4056
0
    memset(ps_op, 0, sizeof(ih264d_ctl_get_vui_params_op_t));
4057
0
    ps_op->u4_size = u4_size;
4058
4059
0
    if(NULL == ps_dec->ps_cur_sps)
4060
0
    {
4061
0
        ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
4062
0
        return IV_FAIL;
4063
0
    }
4064
4065
0
    ps_sps = ps_dec->ps_cur_sps;
4066
0
    if((0 == ps_sps->u1_is_valid)
4067
0
                    || (0 == ps_sps->u1_vui_parameters_present_flag))
4068
0
    {
4069
0
        ps_op->u4_error_code = ERROR_VUI_PARAMS_NOT_FOUND;
4070
0
        return IV_FAIL;
4071
0
    }
4072
4073
0
    ps_vui = &ps_sps->s_vui;
4074
4075
0
    ps_op->u1_aspect_ratio_idc              = ps_vui->u1_aspect_ratio_idc;
4076
0
    ps_op->u2_sar_width                     = ps_vui->u2_sar_width;
4077
0
    ps_op->u2_sar_height                    = ps_vui->u2_sar_height;
4078
0
    ps_op->u1_overscan_appropriate_flag     = ps_vui->u1_overscan_appropriate_flag;
4079
0
    ps_op->u1_video_format                  = ps_vui->u1_video_format;
4080
0
    ps_op->u1_video_full_range_flag         = ps_vui->u1_video_full_range_flag;
4081
0
    ps_op->u1_colour_primaries              = ps_vui->u1_colour_primaries;
4082
0
    ps_op->u1_tfr_chars                     = ps_vui->u1_tfr_chars;
4083
0
    ps_op->u1_matrix_coeffs                 = ps_vui->u1_matrix_coeffs;
4084
0
    ps_op->u1_cr_top_field                  = ps_vui->u1_cr_top_field;
4085
0
    ps_op->u1_cr_bottom_field               = ps_vui->u1_cr_bottom_field;
4086
0
    ps_op->u4_num_units_in_tick             = ps_vui->u4_num_units_in_tick;
4087
0
    ps_op->u4_time_scale                    = ps_vui->u4_time_scale;
4088
0
    ps_op->u1_fixed_frame_rate_flag         = ps_vui->u1_fixed_frame_rate_flag;
4089
0
    ps_op->u1_nal_hrd_params_present        = ps_vui->u1_nal_hrd_params_present;
4090
0
    ps_op->u1_vcl_hrd_params_present        = ps_vui->u1_vcl_hrd_params_present;
4091
0
    ps_op->u1_low_delay_hrd_flag            = ps_vui->u1_low_delay_hrd_flag;
4092
0
    ps_op->u1_pic_struct_present_flag       = ps_vui->u1_pic_struct_present_flag;
4093
0
    ps_op->u1_bitstream_restriction_flag    = ps_vui->u1_bitstream_restriction_flag;
4094
0
    ps_op->u1_mv_over_pic_boundaries_flag   = ps_vui->u1_mv_over_pic_boundaries_flag;
4095
0
    ps_op->u4_max_bytes_per_pic_denom       = ps_vui->u4_max_bytes_per_pic_denom;
4096
0
    ps_op->u4_max_bits_per_mb_denom         = ps_vui->u4_max_bits_per_mb_denom;
4097
0
    ps_op->u4_log2_max_mv_length_horz       = ps_vui->u4_log2_max_mv_length_horz;
4098
0
    ps_op->u4_log2_max_mv_length_vert       = ps_vui->u4_log2_max_mv_length_vert;
4099
0
    ps_op->u4_num_reorder_frames            = ps_vui->u4_num_reorder_frames;
4100
0
    ps_op->u4_max_dec_frame_buffering       = ps_vui->u4_max_dec_frame_buffering;
4101
4102
0
    return IV_SUCCESS;
4103
0
}
4104
/*****************************************************************************/
4105
/*                                                                           */
4106
/*  Function Name : ih264d_get_sei_mdcv_params                               */
4107
/*                                                                           */
4108
/*  Description   : This function populates SEI mdcv message in              */
4109
/*                     output structure                                      */
4110
/*  Inputs        : iv_obj_t decoder handle                                  */
4111
/*                : pv_api_ip pointer to input structure                     */
4112
/*                : pv_api_op pointer to output structure                    */
4113
/*  Outputs       :                                                          */
4114
/*  Returns       : returns 0; 1 with error code when MDCV is not present    */
4115
/*                                                                           */
4116
/*  Issues        : none                                                     */
4117
/*                                                                           */
4118
/*  Revision History:                                                        */
4119
/*                                                                           */
4120
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4121
/*                                                                           */
4122
/*                                                                           */
4123
/*****************************************************************************/
4124
WORD32 ih264d_get_sei_mdcv_params(iv_obj_t *dec_hdl,
4125
                                  void *pv_api_ip,
4126
                                  void *pv_api_op)
4127
0
{
4128
0
    ih264d_ctl_get_sei_mdcv_params_ip_t *ps_ip;
4129
0
    ih264d_ctl_get_sei_mdcv_params_op_t *ps_op;
4130
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4131
0
    sei_mdcv_params_t *ps_sei_mdcv;
4132
0
    WORD32 i4_count;
4133
4134
0
    ps_ip = (ih264d_ctl_get_sei_mdcv_params_ip_t *)pv_api_ip;
4135
0
    ps_op = (ih264d_ctl_get_sei_mdcv_params_op_t *)pv_api_op;
4136
0
    UNUSED(ps_ip);
4137
4138
0
    if(0 == ps_dec->s_sei_export.u1_sei_mdcv_params_present_flag)
4139
0
    {
4140
0
        ps_op->u4_error_code = ERROR_SEI_MDCV_PARAMS_NOT_FOUND;
4141
0
        return IV_FAIL;
4142
0
    }
4143
4144
0
    ps_sei_mdcv = &ps_dec->s_sei_export.s_sei_mdcv_params;
4145
4146
0
    for(i4_count = 0; i4_count < NUM_SEI_MDCV_PRIMARIES; i4_count++)
4147
0
    {
4148
0
        ps_op->au2_display_primaries_x[i4_count] = ps_sei_mdcv->au2_display_primaries_x[i4_count];
4149
0
        ps_op->au2_display_primaries_y[i4_count] = ps_sei_mdcv->au2_display_primaries_y[i4_count];
4150
0
    }
4151
4152
0
    ps_op->u2_white_point_x = ps_sei_mdcv->u2_white_point_x;
4153
0
    ps_op->u2_white_point_y = ps_sei_mdcv->u2_white_point_y;
4154
0
    ps_op->u4_max_display_mastering_luminance = ps_sei_mdcv->u4_max_display_mastering_luminance;
4155
0
    ps_op->u4_min_display_mastering_luminance = ps_sei_mdcv->u4_min_display_mastering_luminance;
4156
4157
0
    return IV_SUCCESS;
4158
0
}
4159
4160
/*****************************************************************************/
4161
/*                                                                           */
4162
/*  Function Name : ih264d_get_sei_cll_params                                */
4163
/*                                                                           */
4164
/*  Description   : This function populates SEI cll message in               */
4165
/*                     output structure                                      */
4166
/*  Inputs        : iv_obj_t decoder handle                                  */
4167
/*                : pv_api_ip pointer to input structure                     */
4168
/*                : pv_api_op pointer to output structure                    */
4169
/*  Outputs       :                                                          */
4170
/*  Returns       : returns 0; 1 with error code when CLL is not present     */
4171
/*                                                                           */
4172
/*  Issues        : none                                                     */
4173
/*                                                                           */
4174
/*  Revision History:                                                        */
4175
/*                                                                           */
4176
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4177
/*                                                                           */
4178
/*                                                                           */
4179
/*****************************************************************************/
4180
WORD32 ih264d_get_sei_cll_params(iv_obj_t *dec_hdl,
4181
                                 void *pv_api_ip,
4182
                                 void *pv_api_op)
4183
0
{
4184
0
    ih264d_ctl_get_sei_cll_params_ip_t *ps_ip;
4185
0
    ih264d_ctl_get_sei_cll_params_op_t *ps_op;
4186
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4187
0
    sei_cll_params_t *ps_sei_cll;
4188
4189
0
    ps_ip = (ih264d_ctl_get_sei_cll_params_ip_t *)pv_api_ip;
4190
0
    ps_op = (ih264d_ctl_get_sei_cll_params_op_t *)pv_api_op;
4191
0
    UNUSED(ps_ip);
4192
4193
0
    if(0 == ps_dec->s_sei_export.u1_sei_cll_params_present_flag)
4194
0
    {
4195
0
        ps_op->u4_error_code = ERROR_SEI_CLL_PARAMS_NOT_FOUND;
4196
0
        return IV_FAIL;
4197
0
    }
4198
4199
0
    ps_sei_cll = &ps_dec->s_sei_export.s_sei_cll_params;
4200
4201
0
    ps_op->u2_max_content_light_level = ps_sei_cll->u2_max_content_light_level;
4202
0
    ps_op->u2_max_pic_average_light_level = ps_sei_cll->u2_max_pic_average_light_level;
4203
4204
0
    return IV_SUCCESS;
4205
0
}
4206
4207
/*****************************************************************************/
4208
/*                                                                           */
4209
/*  Function Name : ih264d_get_sei_ave_params                                */
4210
/*                                                                           */
4211
/*  Description   : This function populates SEI ave message in               */
4212
/*                     output structure                                      */
4213
/*  Inputs        : iv_obj_t decoder handle                                  */
4214
/*                : pv_api_ip pointer to input structure                     */
4215
/*                : pv_api_op pointer to output structure                    */
4216
/*  Outputs       :                                                          */
4217
/*  Returns       : returns 0; 1 with error code when AVE is not present     */
4218
/*                                                                           */
4219
/*  Issues        : none                                                     */
4220
/*                                                                           */
4221
/*  Revision History:                                                        */
4222
/*                                                                           */
4223
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4224
/*                                                                           */
4225
/*                                                                           */
4226
/*****************************************************************************/
4227
WORD32 ih264d_get_sei_ave_params(iv_obj_t *dec_hdl,
4228
                                 void *pv_api_ip,
4229
                                 void *pv_api_op)
4230
0
{
4231
0
    ih264d_ctl_get_sei_ave_params_ip_t *ps_ip;
4232
0
    ih264d_ctl_get_sei_ave_params_op_t *ps_op;
4233
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4234
0
    sei_ave_params_t *ps_sei_ave;
4235
4236
0
    ps_ip = (ih264d_ctl_get_sei_ave_params_ip_t *)pv_api_ip;
4237
0
    ps_op = (ih264d_ctl_get_sei_ave_params_op_t *)pv_api_op;
4238
0
    UNUSED(ps_ip);
4239
4240
0
    if(0 == ps_dec->s_sei_export.u1_sei_ave_params_present_flag)
4241
0
    {
4242
0
        ps_op->u4_error_code = ERROR_SEI_AVE_PARAMS_NOT_FOUND;
4243
0
        return IV_FAIL;
4244
0
    }
4245
4246
0
    ps_sei_ave = &ps_dec->s_sei_export.s_sei_ave_params;
4247
4248
0
    ps_op->u4_ambient_illuminance = ps_sei_ave->u4_ambient_illuminance;
4249
0
    ps_op->u2_ambient_light_x = ps_sei_ave->u2_ambient_light_x;
4250
0
    ps_op->u2_ambient_light_y = ps_sei_ave->u2_ambient_light_y;
4251
4252
0
    return IV_SUCCESS;
4253
0
}
4254
4255
/*****************************************************************************/
4256
/*                                                                           */
4257
/*  Function Name : ih264d_get_sei_ccv_params                                */
4258
/*                                                                           */
4259
/*  Description   : This function populates SEI mdcv message in              */
4260
/*                     output structure                                      */
4261
/*  Inputs        : iv_obj_t decoder handle                                  */
4262
/*                : pv_api_ip pointer to input structure                     */
4263
/*                : pv_api_op pointer to output structure                    */
4264
/*  Outputs       :                                                          */
4265
/*  Returns       : returns 0; 1 with error code when CCV is not present    */
4266
/*                                                                           */
4267
/*  Issues        : none                                                     */
4268
/*                                                                           */
4269
/*  Revision History:                                                        */
4270
/*                                                                           */
4271
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4272
/*                                                                           */
4273
/*                                                                           */
4274
/*****************************************************************************/
4275
WORD32 ih264d_get_sei_ccv_params(iv_obj_t *dec_hdl,
4276
                                 void *pv_api_ip,
4277
                                 void *pv_api_op)
4278
0
{
4279
0
    ih264d_ctl_get_sei_ccv_params_ip_t *ps_ip;
4280
0
    ih264d_ctl_get_sei_ccv_params_op_t *ps_op;
4281
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4282
0
    sei_ccv_params_t *ps_sei_ccv;
4283
0
    WORD32 i4_count;
4284
4285
0
    ps_ip = (ih264d_ctl_get_sei_ccv_params_ip_t *)pv_api_ip;
4286
0
    ps_op = (ih264d_ctl_get_sei_ccv_params_op_t *)pv_api_op;
4287
0
    UNUSED(ps_ip);
4288
4289
0
    if(0 == ps_dec->s_sei_export.u1_sei_ccv_params_present_flag)
4290
0
    {
4291
0
        ps_op->u4_error_code = ERROR_SEI_CCV_PARAMS_NOT_FOUND;
4292
0
        return IV_FAIL;
4293
0
    }
4294
4295
0
    ps_sei_ccv = &ps_dec->s_sei_export.s_sei_ccv_params;
4296
4297
0
    ps_op->u1_ccv_cancel_flag = ps_sei_ccv->u1_ccv_cancel_flag;
4298
4299
0
    if(0 == ps_op->u1_ccv_cancel_flag)
4300
0
    {
4301
0
        ps_op->u1_ccv_persistence_flag = ps_sei_ccv->u1_ccv_persistence_flag;
4302
0
        ps_op->u1_ccv_primaries_present_flag = ps_sei_ccv->u1_ccv_primaries_present_flag;
4303
0
        ps_op->u1_ccv_min_luminance_value_present_flag =
4304
0
                    ps_sei_ccv->u1_ccv_min_luminance_value_present_flag;
4305
0
        ps_op->u1_ccv_max_luminance_value_present_flag =
4306
0
                    ps_sei_ccv->u1_ccv_max_luminance_value_present_flag;
4307
0
        ps_op->u1_ccv_avg_luminance_value_present_flag =
4308
0
                    ps_sei_ccv->u1_ccv_avg_luminance_value_present_flag;
4309
0
        ps_op->u1_ccv_reserved_zero_2bits = ps_sei_ccv->u1_ccv_reserved_zero_2bits;
4310
4311
0
        if(1 == ps_sei_ccv->u1_ccv_primaries_present_flag)
4312
0
        {
4313
0
            for(i4_count = 0; i4_count < NUM_SEI_CCV_PRIMARIES; i4_count++)
4314
0
            {
4315
0
                ps_op->ai4_ccv_primaries_x[i4_count] = ps_sei_ccv->ai4_ccv_primaries_x[i4_count];
4316
0
                ps_op->ai4_ccv_primaries_y[i4_count] = ps_sei_ccv->ai4_ccv_primaries_y[i4_count];
4317
0
            }
4318
0
        }
4319
4320
0
        if(1 == ps_sei_ccv->u1_ccv_min_luminance_value_present_flag)
4321
0
        {
4322
0
            ps_op->u4_ccv_min_luminance_value = ps_sei_ccv->u4_ccv_min_luminance_value;
4323
0
        }
4324
0
        if(1 == ps_sei_ccv->u1_ccv_max_luminance_value_present_flag)
4325
0
        {
4326
0
            ps_op->u4_ccv_max_luminance_value = ps_sei_ccv->u4_ccv_max_luminance_value;
4327
0
        }
4328
0
        if(1 == ps_sei_ccv->u1_ccv_avg_luminance_value_present_flag)
4329
0
        {
4330
0
            ps_op->u4_ccv_avg_luminance_value = ps_sei_ccv->u4_ccv_avg_luminance_value;
4331
0
        }
4332
0
    }
4333
4334
0
    return IV_SUCCESS;
4335
0
}
4336
4337
/*****************************************************************************/
4338
/*                                                                           */
4339
/*  Function Name : ih264d_get_sei_sii_params                                */
4340
/*                                                                           */
4341
/*  Description   : This function populates SEI sii message in               */
4342
/*                     output structure                                      */
4343
/*  Inputs        : iv_obj_t decoder handle                                  */
4344
/*                : pv_api_ip pointer to input structure                     */
4345
/*                : pv_api_op pointer to output structure                    */
4346
/*  Outputs       :                                                          */
4347
/*  Returns       : returns 0; 1 with error code when SII is not present     */
4348
/*                                                                           */
4349
/*  Issues        : none                                                     */
4350
/*                                                                           */
4351
/*  Revision History:                                                        */
4352
/*                                                                           */
4353
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4354
/*                                                                           */
4355
/*                                                                           */
4356
/*****************************************************************************/
4357
WORD32 ih264d_get_sei_sii_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4358
0
{
4359
0
    ih264d_ctl_get_sei_sii_params_ip_t *ps_ip;
4360
0
    ih264d_ctl_get_sei_sii_params_op_t *ps_op;
4361
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4362
0
    sei_sii_params_t *ps_sei_sii;
4363
0
    int i;
4364
4365
0
    ps_ip = (ih264d_ctl_get_sei_sii_params_ip_t *) pv_api_ip;
4366
0
    ps_op = (ih264d_ctl_get_sei_sii_params_op_t *) pv_api_op;
4367
0
    UNUSED(ps_ip);
4368
4369
0
    if(0 == ps_dec->s_sei_export.u1_sei_sii_params_present_flag)
4370
0
    {
4371
0
        ps_op->u4_error_code = ERROR_SEI_SII_PARAMS_NOT_FOUND;
4372
0
        return IV_FAIL;
4373
0
    }
4374
4375
0
    ps_sei_sii = &ps_dec->s_sei_export.s_sei_sii_params;
4376
4377
0
    if((ps_sei_sii->u4_sii_sub_layer_idx > 0) &&
4378
0
       (ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag == 1))
4379
0
    {
4380
0
        ps_op->u4_error_code = ERROR_INV_SEI_SII_PARAMS;
4381
0
        return IV_FAIL;
4382
0
    }
4383
4384
0
    if((ps_sei_sii->u4_sii_sub_layer_idx > ps_sei_sii->u1_sii_max_sub_layers_minus1) &&
4385
0
       (ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag == 0))
4386
0
    {
4387
0
        ps_op->u4_error_code = ERROR_INV_SEI_SII_PARAMS;
4388
0
        return IV_FAIL;
4389
0
    }
4390
4391
0
    ps_op->u4_sii_sub_layer_idx = ps_sei_sii->u4_sii_sub_layer_idx;
4392
4393
0
    if(0 == ps_op->u4_sii_sub_layer_idx)
4394
0
    {
4395
0
        ps_op->u1_shutter_interval_info_present_flag =
4396
0
            ps_sei_sii->u1_shutter_interval_info_present_flag;
4397
4398
0
        if(1 == ps_sei_sii->u1_shutter_interval_info_present_flag)
4399
0
        {
4400
0
            ps_op->u4_sii_time_scale = ps_sei_sii->u4_sii_time_scale;
4401
0
            ps_op->u1_fixed_shutter_interval_within_cvs_flag =
4402
0
                ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag;
4403
4404
0
            if(1 == ps_sei_sii->u1_fixed_shutter_interval_within_cvs_flag)
4405
0
            {
4406
0
                ps_op->u4_sii_num_units_in_shutter_interval =
4407
0
                    ps_sei_sii->u4_sii_num_units_in_shutter_interval;
4408
0
            }
4409
0
            else
4410
0
            {
4411
0
                ps_op->u1_sii_max_sub_layers_minus1 = ps_sei_sii->u1_sii_max_sub_layers_minus1;
4412
0
                for(i = 0; i <= ps_sei_sii->u1_sii_max_sub_layers_minus1; i++)
4413
0
                {
4414
0
                    ps_op->au4_sub_layer_num_units_in_shutter_interval[i] =
4415
0
                        ps_sei_sii->au4_sub_layer_num_units_in_shutter_interval[i];
4416
0
                }
4417
0
            }
4418
0
        }
4419
0
    }
4420
4421
0
    return IV_SUCCESS;
4422
0
}
4423
4424
/*****************************************************************************/
4425
/*                                                                           */
4426
/*  Function Name : ih264d_get_sei_fgc_params                                */
4427
/*                                                                           */
4428
/*  Description   : This function populates SEI FGC message in               */
4429
/*                     output structure                                      */
4430
/*  Inputs        : iv_obj_t decoder handle                                  */
4431
/*                : pv_api_ip pointer to input structure                     */
4432
/*                : pv_api_op pointer to output structure                    */
4433
/*  Outputs       :                                                          */
4434
/*  Returns       : returns 0; 1 with error code when FGC is not present     */
4435
/*                                                                           */
4436
/*  Issues        : none                                                     */
4437
/*                                                                           */
4438
/*  Revision History:                                                        */
4439
/*                                                                           */
4440
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4441
/*                                                                           */
4442
/*                                                                           */
4443
/*****************************************************************************/
4444
WORD32 ih264d_get_sei_fgc_params(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4445
0
{
4446
0
    ih264d_ctl_get_sei_fgc_params_ip_t *ps_ip;
4447
0
    ih264d_ctl_get_sei_fgc_params_op_t *ps_op;
4448
0
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4449
0
    sei_fgc_params_t *ps_sei_fgc;
4450
0
    WORD32 i4_count;
4451
0
    UWORD32 c, i, j;
4452
4453
0
    ps_ip = (ih264d_ctl_get_sei_fgc_params_ip_t *) pv_api_ip;
4454
0
    ps_op = (ih264d_ctl_get_sei_fgc_params_op_t *) pv_api_op;
4455
0
    UNUSED(ps_ip);
4456
4457
0
    if(0 == ps_dec->s_sei_export.u1_sei_fgc_params_present_flag)
4458
0
    {
4459
0
        ps_op->u4_error_code = ERROR_SEI_FGC_PARAMS_NOT_FOUND;
4460
0
        return IV_FAIL;
4461
0
    }
4462
4463
0
    ps_sei_fgc = &ps_dec->s_sei_export.s_sei_fgc_params;
4464
4465
0
    ps_op->u1_film_grain_characteristics_cancel_flag =
4466
0
        ps_sei_fgc->u1_film_grain_characteristics_cancel_flag;
4467
4468
0
    if(0 == ps_op->u1_film_grain_characteristics_cancel_flag)
4469
0
    {
4470
0
        ps_op->i4_poc = ps_sei_fgc->i4_poc;
4471
0
        ps_op->u4_idr_pic_id = ps_sei_fgc->u4_idr_pic_id;
4472
0
        ps_op->u1_film_grain_model_id = ps_sei_fgc->u1_film_grain_model_id;
4473
0
        ps_op->u1_separate_colour_description_present_flag =
4474
0
            ps_sei_fgc->u1_separate_colour_description_present_flag;
4475
4476
0
        if(ps_op->u1_separate_colour_description_present_flag)
4477
0
        {
4478
0
            ps_op->u1_film_grain_bit_depth_luma_minus8 =
4479
0
                ps_sei_fgc->u1_film_grain_bit_depth_luma_minus8;
4480
0
            ps_op->u1_film_grain_bit_depth_chroma_minus8 =
4481
0
                ps_sei_fgc->u1_film_grain_bit_depth_chroma_minus8;
4482
0
            ps_op->u1_film_grain_full_range_flag = ps_sei_fgc->u1_film_grain_full_range_flag;
4483
0
            ps_op->u1_film_grain_colour_primaries = ps_sei_fgc->u1_film_grain_colour_primaries;
4484
0
            ps_op->u1_film_grain_transfer_characteristics =
4485
0
                ps_sei_fgc->u1_film_grain_transfer_characteristics;
4486
0
            ps_op->u1_film_grain_matrix_coefficients =
4487
0
                ps_sei_fgc->u1_film_grain_matrix_coefficients;
4488
0
        }
4489
0
        ps_op->u1_blending_mode_id = ps_sei_fgc->u1_blending_mode_id;
4490
0
        ps_op->u1_log2_scale_factor = ps_sei_fgc->u1_log2_scale_factor;
4491
4492
0
        for(c = 0; c < SEI_FGC_NUM_COLOUR_COMPONENTS; c++)
4493
0
        {
4494
0
            ps_op->au1_comp_model_present_flag[c] = ps_sei_fgc->au1_comp_model_present_flag[c];
4495
0
        }
4496
4497
0
        for(c = 0; c < SEI_FGC_NUM_COLOUR_COMPONENTS; c++)
4498
0
        {
4499
0
            if(ps_op->au1_comp_model_present_flag[c])
4500
0
            {
4501
0
                ps_op->au1_num_intensity_intervals_minus1[c] =
4502
0
                    ps_sei_fgc->au1_num_intensity_intervals_minus1[c];
4503
4504
0
                ps_op->au1_num_model_values_minus1[c] = ps_sei_fgc->au1_num_model_values_minus1[c];
4505
4506
0
                for(i = 0; i <= ps_op->au1_num_intensity_intervals_minus1[c]; i++)
4507
0
                {
4508
0
                    ps_op->au1_intensity_interval_lower_bound[c][i] =
4509
0
                        ps_sei_fgc->au1_intensity_interval_lower_bound[c][i];
4510
0
                    ps_op->au1_intensity_interval_upper_bound[c][i] =
4511
0
                        ps_sei_fgc->au1_intensity_interval_upper_bound[c][i];
4512
4513
0
                    for(j = 0; j <= ps_op->au1_num_model_values_minus1[c]; j++)
4514
0
                    {
4515
0
                        ps_op->ai4_comp_model_value[c][i][j] =
4516
0
                            ps_sei_fgc->ai4_comp_model_value[c][i][j];
4517
0
                    }
4518
0
                }
4519
0
            }
4520
0
        }
4521
0
        ps_op->u4_film_grain_characteristics_repetition_period =
4522
0
            ps_sei_fgc->u4_film_grain_characteristics_repetition_period;
4523
0
    }
4524
0
    return IV_SUCCESS;
4525
0
}
4526
4527
WORD32 ih264d_set_num_cores(iv_obj_t *dec_hdl, void *pv_api_ip, void *pv_api_op)
4528
307
{
4529
307
    ih264d_ctl_set_num_cores_ip_t *ps_ip;
4530
307
    ih264d_ctl_set_num_cores_op_t *ps_op;
4531
307
    dec_struct_t *ps_dec = dec_hdl->pv_codec_handle;
4532
4533
307
    ps_ip = (ih264d_ctl_set_num_cores_ip_t *)pv_api_ip;
4534
307
    ps_op = (ih264d_ctl_set_num_cores_op_t *)pv_api_op;
4535
307
    ps_op->u4_error_code = 0;
4536
307
    ps_dec->u4_num_cores = ps_ip->u4_num_cores;
4537
307
    if(ps_dec->u4_num_cores == 1)
4538
96
    {
4539
96
        ps_dec->u1_separate_parse = 0;
4540
96
    }
4541
211
    else
4542
211
    {
4543
211
        ps_dec->u1_separate_parse = 1;
4544
211
    }
4545
4546
    /*using only upto three threads currently*/
4547
307
    if(ps_dec->u4_num_cores > 3)
4548
106
        ps_dec->u4_num_cores = 3;
4549
4550
307
    return IV_SUCCESS;
4551
307
}
4552
4553
void ih264d_fill_output_struct_from_context(dec_struct_t *ps_dec,
4554
                                            ivd_video_decode_op_t *ps_dec_op)
4555
8.83k
{
4556
8.83k
    if((ps_dec_op->u4_error_code & 0xff)
4557
8.83k
                    != ERROR_DYNAMIC_RESOLUTION_NOT_SUPPORTED)
4558
8.83k
    {
4559
8.83k
        ps_dec_op->u4_pic_wd = (UWORD32)ps_dec->u2_disp_width;
4560
8.83k
        ps_dec_op->u4_pic_ht = (UWORD32)ps_dec->u2_disp_height;
4561
8.83k
    }
4562
8.83k
    ps_dec_op->i4_reorder_depth = ps_dec->i4_reorder_depth;
4563
8.83k
    ps_dec_op->i4_display_index = ps_dec->i4_display_index;
4564
8.83k
    ps_dec_op->e_pic_type = ps_dec->i4_frametype;
4565
4566
8.83k
    ps_dec_op->u4_new_seq = 0;
4567
8.83k
    ps_dec_op->u4_output_present = ps_dec->u4_output_present;
4568
8.83k
    ps_dec_op->u4_progressive_frame_flag =
4569
8.83k
                    ps_dec->s_disp_op.u4_progressive_frame_flag;
4570
4571
8.83k
    ps_dec_op->u4_is_ref_flag = 1;
4572
8.83k
    if(ps_dec_op->u4_frame_decoded_flag)
4573
6.77k
    {
4574
6.77k
        if(ps_dec->ps_cur_slice->u1_nal_ref_idc == 0)
4575
3.47k
            ps_dec_op->u4_is_ref_flag = 0;
4576
6.77k
    }
4577
4578
8.83k
    ps_dec_op->e_output_format = ps_dec->s_disp_op.e_output_format;
4579
8.83k
    ps_dec_op->s_disp_frm_buf = ps_dec->s_disp_op.s_disp_frm_buf;
4580
8.83k
    ps_dec_op->e4_fld_type = ps_dec->s_disp_op.e4_fld_type;
4581
8.83k
    ps_dec_op->u4_ts = ps_dec->s_disp_op.u4_ts;
4582
8.83k
    ps_dec_op->u4_disp_buf_id = ps_dec->s_disp_op.u4_disp_buf_id;
4583
4584
8.83k
    ih264d_export_sei_params(&ps_dec_op->s_sei_decode_op, ps_dec);
4585
8.83k
}
4586
4587
/*****************************************************************************/
4588
/*                                                                           */
4589
/*  Function Name : ih264d_api_function                                      */
4590
/*                                                                           */
4591
/*  Description   :                                                          */
4592
/*                                                                           */
4593
/*  Inputs        :iv_obj_t decoder handle                                   */
4594
/*                :pv_api_ip pointer to input structure                      */
4595
/*                :pv_api_op pointer to output structure                     */
4596
/*  Outputs       :                                                          */
4597
/*  Returns       : void                                                     */
4598
/*                                                                           */
4599
/*  Issues        : none                                                     */
4600
/*                                                                           */
4601
/*  Revision History:                                                        */
4602
/*                                                                           */
4603
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
4604
/*         22 10 2008    100356         Draft                                */
4605
/*                                                                           */
4606
/*****************************************************************************/
4607
IV_API_CALL_STATUS_T ih264d_api_function(iv_obj_t *dec_hdl,
4608
                                              void *pv_api_ip,
4609
                                              void *pv_api_op)
4610
17.6k
{
4611
17.6k
    UWORD32 command;
4612
17.6k
    UWORD32 *pu2_ptr_cmd;
4613
17.6k
    UWORD32 u4_api_ret;
4614
17.6k
    IV_API_CALL_STATUS_T e_status;
4615
17.6k
    e_status = api_check_struct_sanity(dec_hdl, pv_api_ip, pv_api_op);
4616
4617
17.6k
    if(e_status != IV_SUCCESS)
4618
206
    {
4619
206
        UWORD32 *ptr_err;
4620
4621
206
        ptr_err = (UWORD32 *)pv_api_op;
4622
206
        UNUSED(ptr_err);
4623
206
        H264_DEC_DEBUG_PRINT("error code = %d\n", *(ptr_err + 1));
4624
206
        return IV_FAIL;
4625
206
    }
4626
4627
17.4k
    pu2_ptr_cmd = (UWORD32 *)pv_api_ip;
4628
17.4k
    pu2_ptr_cmd++;
4629
4630
17.4k
    command = *pu2_ptr_cmd;
4631
//    H264_DEC_DEBUG_PRINT("inside lib = %d\n",command);
4632
17.4k
    switch(command)
4633
17.4k
    {
4634
4635
307
        case IVD_CMD_CREATE:
4636
307
            u4_api_ret = ih264d_create(dec_hdl, (void *)pv_api_ip,
4637
307
                                     (void *)pv_api_op);
4638
307
            break;
4639
307
        case IVD_CMD_DELETE:
4640
307
            u4_api_ret = ih264d_delete(dec_hdl, (void *)pv_api_ip,
4641
307
                                     (void *)pv_api_op);
4642
307
            break;
4643
4644
14.1k
        case IVD_CMD_VIDEO_DECODE:
4645
14.1k
            u4_api_ret = ih264d_video_decode(dec_hdl, (void *)pv_api_ip,
4646
14.1k
                                             (void *)pv_api_op);
4647
14.1k
            break;
4648
4649
0
        case IVD_CMD_GET_DISPLAY_FRAME:
4650
0
            u4_api_ret = ih264d_get_display_frame(dec_hdl, (void *)pv_api_ip,
4651
0
                                                  (void *)pv_api_op);
4652
4653
0
            break;
4654
4655
0
        case IVD_CMD_SET_DISPLAY_FRAME:
4656
0
            u4_api_ret = ih264d_set_display_frame(dec_hdl, (void *)pv_api_ip,
4657
0
                                                  (void *)pv_api_op);
4658
4659
0
            break;
4660
4661
0
        case IVD_CMD_REL_DISPLAY_FRAME:
4662
0
            u4_api_ret = ih264d_rel_display_frame(dec_hdl, (void *)pv_api_ip,
4663
0
                                                  (void *)pv_api_op);
4664
0
            break;
4665
4666
2.66k
        case IVD_CMD_VIDEO_CTL:
4667
2.66k
            u4_api_ret = ih264d_ctl(dec_hdl, (void *)pv_api_ip,
4668
2.66k
                                    (void *)pv_api_op);
4669
2.66k
            break;
4670
0
        default:
4671
0
            u4_api_ret = IV_FAIL;
4672
0
            break;
4673
17.4k
    }
4674
4675
17.4k
    return u4_api_ret;
4676
17.4k
}