Coverage Report

Created: 2026-11-12 06:33

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/libavc/decoder/ih264d_utils.c
Line
Count
Source
1
/******************************************************************************
2
 *
3
 * Copyright (C) 2015 The Android Open Source Project
4
 *
5
 * Licensed under the Apache License, Version 2.0 (the "License");
6
 * you may not use this file except in compliance with the License.
7
 * You may obtain a copy of the License at:
8
 *
9
 * http://www.apache.org/licenses/LICENSE-2.0
10
 *
11
 * Unless required by applicable law or agreed to in writing, software
12
 * distributed under the License is distributed on an "AS IS" BASIS,
13
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14
 * See the License for the specific language governing permissions and
15
 * limitations under the License.
16
 *
17
 *****************************************************************************
18
 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19
*/
20
/*!
21
 **************************************************************************
22
 * \file ih264d_utils.c
23
 *
24
 * \brief
25
 *    Contains routines that handle of start and end of pic processing
26
 *
27
 * \date
28
 *    19/12/2002
29
 *
30
 * \author  AI
31
 **************************************************************************
32
 */
33
34
#include <string.h>
35
#include "ih264_typedefs.h"
36
#include "ithread.h"
37
#include "ih264d_deblocking.h"
38
#include "ih264d_parse_slice.h"
39
#include "ih264d_parse_cavlc.h"
40
#include "ih264d_dpb_manager.h"
41
#include "ih264d_defs.h"
42
#include "ih264d_structs.h"
43
#include "ih264d_mem_request.h"
44
#include "ih264_typedefs.h"
45
#include "ih264_macros.h"
46
#include "ih264_platform_macros.h"
47
#include "ih264d_tables.h"
48
#include "ih264d_debug.h"
49
#include "ih264d_mb_utils.h"
50
#include "ih264d_error_handler.h"
51
#include "ih264d_dpb_manager.h"
52
#include "ih264d_utils.h"
53
#include "ih264d_defs.h"
54
#include "ih264d_tables.h"
55
#include "ih264d_inter_pred.h"
56
#include "ih264d_dpb_manager.h"
57
#include "iv.h"
58
#include "ivd.h"
59
#include "ih264d_format_conv.h"
60
#include "ih264_error.h"
61
#include "ih264_disp_mgr.h"
62
#include "ih264_buf_mgr.h"
63
#include "ih264d_utils.h"
64
65
/*!
66
 **************************************************************************
67
 * \if Function name : ih264d_is_end_of_pic \endif
68
 *
69
 * \brief
70
 *    Determines whether current slice is first slice of a new picture as
71
 *    defined in 7.4.1.2.4 of 14496-10.
72
 *
73
 * \return
74
 *    Return 1 if current slice is first slice of a new picture
75
 *    Otherwise it returns 0
76
 **************************************************************************
77
 */
78
UWORD8 ih264d_is_end_of_pic(UWORD16 u2_frame_num,
79
                            UWORD8 u1_nal_ref_idc,
80
                            pocstruct_t *ps_cur_poc,
81
                            pocstruct_t *ps_prev_poc,
82
                            dec_slice_params_t * ps_prev_slice, /*!< Previous slice parameters*/
83
                            UWORD8 u1_pic_order_cnt_type,
84
                            UWORD8 u1_nal_unit_type,
85
                            UWORD32 u4_idr_pic_id,
86
                            UWORD8 u1_field_pic_flag,
87
                            UWORD8 u1_bottom_field_flag)
88
10.6k
{
89
10.6k
    WORD8 i1_is_end_of_pic;
90
10.6k
    WORD8 a, b, c, d, e, f, g, h;
91
92
10.6k
    a = b = c = d = e = f = g = h = 0;
93
10.6k
    a = (ps_prev_slice->u2_frame_num != u2_frame_num);
94
10.6k
    b = (ps_prev_slice->u1_field_pic_flag != u1_field_pic_flag);
95
10.6k
    if(u1_field_pic_flag && ps_prev_slice->u1_field_pic_flag)
96
1.87k
        c = (u1_bottom_field_flag != ps_prev_slice->u1_bottom_field_flag);
97
10.6k
    d =
98
10.6k
                    (u1_nal_ref_idc == 0 && ps_prev_slice->u1_nal_ref_idc != 0)
99
10.5k
                                    || (u1_nal_ref_idc != 0
100
7.21k
                                                    && ps_prev_slice->u1_nal_ref_idc
101
7.21k
                                                                    == 0);
102
10.6k
    if(!a)
103
10.2k
    {
104
10.2k
        if((u1_pic_order_cnt_type == 0)
105
8.63k
                        && (ps_prev_slice->u1_pic_order_cnt_type == 0))
106
8.63k
        {
107
8.63k
            e =
108
8.63k
                            ((ps_cur_poc->i4_pic_order_cnt_lsb
109
8.63k
                                            != ps_prev_poc->i4_pic_order_cnt_lsb)
110
8.16k
                                            || (ps_cur_poc->i4_delta_pic_order_cnt_bottom
111
8.16k
                                                            != ps_prev_poc->i4_delta_pic_order_cnt_bottom));
112
8.63k
        }
113
114
10.2k
        if((u1_pic_order_cnt_type == 1)
115
256
                        && (ps_prev_slice->u1_pic_order_cnt_type == 1))
116
256
        {
117
256
            f =
118
256
                            ((ps_cur_poc->i4_delta_pic_order_cnt[0]
119
256
                                            != ps_prev_poc->i4_delta_pic_order_cnt[0])
120
137
                                            || (ps_cur_poc->i4_delta_pic_order_cnt[1]
121
137
                                                            != ps_prev_poc->i4_delta_pic_order_cnt[1]));
122
256
        }
123
10.2k
    }
124
125
10.6k
    if((u1_nal_unit_type == IDR_SLICE_NAL)
126
4.06k
                    && (ps_prev_slice->u1_nal_unit_type == IDR_SLICE_NAL))
127
4.04k
    {
128
4.04k
        g = (u4_idr_pic_id != ps_prev_slice->u4_idr_pic_id);
129
4.04k
    }
130
131
10.6k
    if((u1_nal_unit_type == IDR_SLICE_NAL)
132
4.06k
                    && (ps_prev_slice->u1_nal_unit_type != IDR_SLICE_NAL))
133
18
    {
134
18
        h = 1;
135
18
    }
136
10.6k
    i1_is_end_of_pic = a + b + c + d + e + f + g + h;
137
10.6k
    return (i1_is_end_of_pic);
138
10.6k
}
139
140
/*!
141
 **************************************************************************
142
 * \if Function name : ih264d_decode_pic_order_cnt \endif
143
 *
144
 * \brief
145
 *    Calculates picture order count of picture.
146
 *
147
 * \return
148
 *    Returns the pic order count of the picture to which current
149
 *    Slice belongs.
150
 *
151
 **************************************************************************
152
 */
153
WORD32 ih264d_decode_pic_order_cnt(UWORD8 u1_is_idr_slice,
154
                                   UWORD32 u2_frame_num,
155
                                   pocstruct_t *ps_prev_poc,
156
                                   pocstruct_t *ps_cur_poc,
157
                                   dec_slice_params_t *ps_cur_slice, /*!< Pointer to current slice Params*/
158
                                   dec_pic_params_t * ps_pps,
159
                                   UWORD8 u1_nal_ref_idc,
160
                                   UWORD8 u1_bottom_field_flag,
161
                                   UWORD8 u1_field_pic_flag,
162
                                   WORD32 *pi4_poc)
163
2.56M
{
164
2.56M
    WORD64 i8_pic_msb;
165
2.56M
    WORD32 i4_top_field_order_cnt = 0, i4_bottom_field_order_cnt = 0;
166
2.56M
    dec_seq_params_t *ps_seq = ps_pps->ps_sps;
167
2.56M
    WORD32 i4_prev_frame_num_ofst;
168
169
2.56M
    switch(ps_seq->u1_pic_order_cnt_type)
170
2.56M
    {
171
34.6k
        case 0:
172
            /* POC TYPE 0 */
173
34.6k
            if(u1_is_idr_slice)
174
9.99k
            {
175
9.99k
                ps_cur_poc->i4_pic_order_cnt_msb = 0;
176
9.99k
                ps_cur_poc->i4_pic_order_cnt_lsb = 0;
177
9.99k
            }
178
34.6k
            if(ps_prev_poc->u1_mmco_equalto5)
179
134
            {
180
134
                if(ps_prev_poc->u1_bot_field != 1)
181
134
                {
182
134
                    ps_prev_poc->i4_pic_order_cnt_msb = 0;
183
134
                    ps_prev_poc->i4_pic_order_cnt_lsb =
184
134
                                    ps_prev_poc->i4_top_field_order_count;
185
134
                }
186
0
                else
187
0
                {
188
0
                    ps_prev_poc->i4_pic_order_cnt_msb = 0;
189
0
                    ps_prev_poc->i4_pic_order_cnt_lsb = 0;
190
0
                }
191
134
            }
192
193
34.6k
            if((ps_cur_poc->i4_pic_order_cnt_lsb
194
34.6k
                            < ps_prev_poc->i4_pic_order_cnt_lsb)
195
5.80k
                            && ((ps_prev_poc->i4_pic_order_cnt_lsb
196
5.80k
                                            - ps_cur_poc->i4_pic_order_cnt_lsb)
197
5.80k
                                            >= (ps_seq->i4_max_pic_order_cntLsb
198
5.80k
                                                            >> 1)))
199
3.34k
            {
200
3.34k
                i8_pic_msb = (WORD64)ps_prev_poc->i4_pic_order_cnt_msb
201
3.34k
                                + ps_seq->i4_max_pic_order_cntLsb;
202
3.34k
            }
203
31.3k
            else if((ps_cur_poc->i4_pic_order_cnt_lsb
204
31.3k
                            > ps_prev_poc->i4_pic_order_cnt_lsb)
205
9.93k
                            && ((ps_cur_poc->i4_pic_order_cnt_lsb
206
9.93k
                                            - ps_prev_poc->i4_pic_order_cnt_lsb)
207
9.93k
                                            >= (ps_seq->i4_max_pic_order_cntLsb
208
9.93k
                                                            >> 1)))
209
3.53k
            {
210
3.53k
                i8_pic_msb = (WORD64)ps_prev_poc->i4_pic_order_cnt_msb
211
3.53k
                                - ps_seq->i4_max_pic_order_cntLsb;
212
3.53k
            }
213
27.8k
            else
214
27.8k
            {
215
27.8k
                i8_pic_msb = ps_prev_poc->i4_pic_order_cnt_msb;
216
27.8k
            }
217
218
34.6k
            if(!u1_field_pic_flag || !u1_bottom_field_flag)
219
34.3k
            {
220
34.3k
                WORD64 i8_result = i8_pic_msb + ps_cur_poc->i4_pic_order_cnt_lsb;
221
34.3k
                if(IS_OUT_OF_RANGE_S32(i8_result))
222
0
                {
223
0
                    return ERROR_INV_POC;
224
0
                }
225
34.3k
                i4_top_field_order_cnt = i8_result;
226
34.3k
            }
227
228
34.6k
            if(!u1_field_pic_flag)
229
34.2k
            {
230
34.2k
                WORD64 i8_result = (WORD64)i4_top_field_order_cnt
231
34.2k
                                     + ps_cur_poc->i4_delta_pic_order_cnt_bottom;
232
34.2k
                if(IS_OUT_OF_RANGE_S32(i8_result))
233
373
                {
234
373
                    return ERROR_INV_POC;
235
373
                }
236
33.8k
                i4_bottom_field_order_cnt = i8_result;
237
33.8k
            }
238
461
            else if(u1_bottom_field_flag)
239
337
            {
240
337
                WORD64 i8_result = i8_pic_msb + ps_cur_poc->i4_pic_order_cnt_lsb;
241
337
                if(IS_OUT_OF_RANGE_S32(i8_result))
242
0
                {
243
0
                    return ERROR_INV_POC;
244
0
                }
245
337
                i4_bottom_field_order_cnt = i8_result;
246
337
            }
247
248
34.3k
            if(IS_OUT_OF_RANGE_S32(i8_pic_msb))
249
0
            {
250
0
                return ERROR_INV_POC;
251
0
            }
252
34.3k
            ps_cur_poc->i4_pic_order_cnt_msb = i8_pic_msb;
253
34.3k
            break;
254
255
2.46M
        case 1:
256
2.46M
        {
257
            /* POC TYPE 1 */
258
2.46M
            UWORD8 i;
259
2.46M
            WORD32 prev_frame_num;
260
2.46M
            WORD32 frame_num_ofst;
261
2.46M
            WORD32 abs_frm_num;
262
2.46M
            WORD32 poc_cycle_cnt, frame_num_in_poc_cycle;
263
2.46M
            WORD64 i8_expected_delta_poc_cycle;
264
2.46M
            WORD32 expected_poc;
265
2.46M
            WORD64 i8_result;
266
267
2.46M
            prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num;
268
2.46M
            if(!u1_is_idr_slice)
269
2.45M
            {
270
2.45M
                if(ps_cur_slice->u1_mmco_equalto5)
271
3.16k
                {
272
3.16k
                    prev_frame_num = 0;
273
3.16k
                    i4_prev_frame_num_ofst = 0;
274
3.16k
                }
275
2.45M
                else
276
2.45M
                {
277
2.45M
                    i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst;
278
2.45M
                }
279
2.45M
            }
280
8.25k
            else
281
8.25k
                i4_prev_frame_num_ofst = 0;
282
283
            /* 1. Derivation for FrameNumOffset */
284
2.46M
            if(u1_is_idr_slice)
285
8.25k
            {
286
8.25k
                frame_num_ofst = 0;
287
8.25k
                ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
288
8.25k
                ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
289
8.25k
            }
290
2.45M
            else if(prev_frame_num > ((WORD32)u2_frame_num))
291
8.86k
            {
292
8.86k
                WORD64 i8_result = i4_prev_frame_num_ofst
293
8.86k
                                + (WORD64)ps_seq->u2_u4_max_pic_num_minus1 + 1;
294
8.86k
                if(IS_OUT_OF_RANGE_S32(i8_result))
295
0
                {
296
0
                    return ERROR_INV_FRAME_NUM;
297
0
                }
298
8.86k
                frame_num_ofst = i8_result;
299
8.86k
            }
300
2.45M
            else
301
2.45M
                frame_num_ofst = i4_prev_frame_num_ofst;
302
303
            /* 2. Derivation for absFrameNum */
304
2.46M
            if(0 != ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle)
305
2.36M
            {
306
2.36M
                WORD64 i8_result = frame_num_ofst + (WORD64)u2_frame_num;
307
2.36M
                if(IS_OUT_OF_RANGE_S32(i8_result))
308
0
                {
309
0
                    return ERROR_INV_FRAME_NUM;
310
0
                }
311
2.36M
                abs_frm_num = i8_result;
312
2.36M
            }
313
105k
            else
314
105k
                abs_frm_num = 0;
315
2.46M
            if((u1_nal_ref_idc == 0) && (abs_frm_num > 0))
316
1.29k
                abs_frm_num = abs_frm_num - 1;
317
318
            /* 4. expectedDeltaPerPicOrderCntCycle is derived as */
319
2.46M
            i8_expected_delta_poc_cycle = 0;
320
14.3M
            for(i = 0; i < ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle;
321
11.8M
                            i++)
322
11.8M
            {
323
11.8M
                i8_expected_delta_poc_cycle +=
324
11.8M
                                ps_seq->i4_ofst_for_ref_frame[i];
325
11.8M
            }
326
327
            /* 3. When absFrameNum > 0, picOrderCntCycleCnt and
328
             frame_num_in_poc_cycle are derived as : */
329
            /* 5. expectedPicOrderCnt is derived as : */
330
2.46M
            if(abs_frm_num > 0)
331
2.36M
            {
332
2.36M
                poc_cycle_cnt =
333
2.36M
                                DIV((abs_frm_num - 1),
334
2.36M
                                    ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle);
335
2.36M
                frame_num_in_poc_cycle =
336
2.36M
                                MOD((abs_frm_num - 1),
337
2.36M
                                    ps_seq->u1_num_ref_frames_in_pic_order_cnt_cycle);
338
339
2.36M
                i8_result = poc_cycle_cnt
340
2.36M
                                * i8_expected_delta_poc_cycle;
341
342
9.45M
                for(i = 0; i <= frame_num_in_poc_cycle; i++)
343
7.09M
                {
344
7.09M
                    i8_result = i8_result
345
7.09M
                                    + ps_seq->i4_ofst_for_ref_frame[i];
346
7.09M
                }
347
348
2.36M
                if(IS_OUT_OF_RANGE_S32(i8_result))
349
162
                    return ERROR_INV_POC;
350
351
2.36M
                expected_poc = (WORD32)i8_result;
352
353
2.36M
            }
354
106k
            else
355
106k
                expected_poc = 0;
356
357
2.46M
            if(u1_nal_ref_idc == 0)
358
8.97k
            {
359
8.97k
                i8_result = (WORD64)expected_poc
360
8.97k
                                + ps_seq->i4_ofst_for_non_ref_pic;
361
362
8.97k
                if(IS_OUT_OF_RANGE_S32(i8_result))
363
200
                    return ERROR_INV_POC;
364
365
8.77k
                expected_poc = (WORD32)i8_result;
366
8.77k
            }
367
368
            /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */
369
2.46M
            if(!u1_field_pic_flag)
370
2.46M
            {
371
2.46M
                i8_result = (WORD64)expected_poc
372
2.46M
                                + ps_cur_poc->i4_delta_pic_order_cnt[0];
373
374
2.46M
                if(IS_OUT_OF_RANGE_S32(i8_result))
375
132
                    return ERROR_INV_POC;
376
2.46M
                i4_top_field_order_cnt = (WORD32)i8_result;
377
378
2.46M
                i8_result = (WORD64)i4_top_field_order_cnt
379
2.46M
                                + ps_seq->i4_ofst_for_top_to_bottom_field
380
2.46M
                                + ps_cur_poc->i4_delta_pic_order_cnt[1];
381
382
2.46M
                if(IS_OUT_OF_RANGE_S32(i8_result))
383
342
                    return ERROR_INV_POC;
384
2.46M
                i4_bottom_field_order_cnt = (WORD32)i8_result;
385
2.46M
            }
386
102
            else if(!u1_bottom_field_flag)
387
65
            {
388
65
                i8_result = (WORD64)expected_poc
389
65
                                + ps_cur_poc->i4_delta_pic_order_cnt[0];
390
391
65
                if(IS_OUT_OF_RANGE_S32(i8_result))
392
33
                    return ERROR_INV_POC;
393
32
                i4_top_field_order_cnt = (WORD32)i8_result;
394
32
            }
395
37
            else
396
37
            {
397
37
                i8_result = (WORD64)expected_poc
398
37
                                + ps_seq->i4_ofst_for_top_to_bottom_field
399
37
                                + ps_cur_poc->i4_delta_pic_order_cnt[0];
400
401
37
                if(IS_OUT_OF_RANGE_S32(i8_result))
402
0
                    return ERROR_INV_POC;
403
37
                i4_bottom_field_order_cnt = (WORD32)i8_result;
404
37
            }
405
            /* Copy the current POC info into Previous POC structure */
406
2.46M
            ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst;
407
2.46M
        }
408
409
0
            break;
410
59.8k
        case 2:
411
59.8k
        {
412
            /* POC TYPE 2 */
413
59.8k
            WORD32 prev_frame_num;
414
59.8k
            WORD32 frame_num_ofst;
415
59.8k
            WORD32 tmp_poc;
416
417
59.8k
            prev_frame_num = (WORD32)ps_cur_slice->u2_frame_num;
418
59.8k
            if(!u1_is_idr_slice)
419
50.3k
            {
420
50.3k
                if(ps_cur_slice->u1_mmco_equalto5)
421
247
                {
422
247
                    prev_frame_num = 0;
423
247
                    i4_prev_frame_num_ofst = 0;
424
247
                }
425
50.1k
                else
426
50.1k
                    i4_prev_frame_num_ofst = ps_prev_poc->i4_prev_frame_num_ofst;
427
50.3k
            }
428
9.47k
            else
429
9.47k
                i4_prev_frame_num_ofst = 0;
430
431
            /* 1. Derivation for FrameNumOffset */
432
59.8k
            if(u1_is_idr_slice)
433
9.47k
            {
434
9.47k
                frame_num_ofst = 0;
435
9.47k
                ps_cur_poc->i4_delta_pic_order_cnt[0] = 0;
436
9.47k
                ps_cur_poc->i4_delta_pic_order_cnt[1] = 0;
437
9.47k
            }
438
50.3k
            else if(prev_frame_num > ((WORD32)u2_frame_num))
439
3.06k
            {
440
3.06k
                WORD64 i8_result = i4_prev_frame_num_ofst
441
3.06k
                                + (WORD64)ps_seq->u2_u4_max_pic_num_minus1 + 1;
442
3.06k
                if(IS_OUT_OF_RANGE_S32(i8_result))
443
0
                {
444
0
                    return ERROR_INV_FRAME_NUM;
445
0
                }
446
3.06k
                frame_num_ofst = i8_result;
447
3.06k
            }
448
47.2k
            else
449
47.2k
                frame_num_ofst = i4_prev_frame_num_ofst;
450
451
            /* 2. Derivation for tempPicOrderCnt */
452
59.8k
            if(u1_is_idr_slice)
453
9.47k
                tmp_poc = 0;
454
50.3k
            else if(u1_nal_ref_idc == 0)
455
3.39k
            {
456
3.39k
                WORD64 i8_result = ((frame_num_ofst + (WORD64)u2_frame_num) << 1) - 1;
457
3.39k
                if(IS_OUT_OF_RANGE_S32(i8_result))
458
0
                {
459
0
                    return ERROR_INV_POC;
460
0
                }
461
3.39k
                tmp_poc = i8_result;
462
3.39k
            }
463
46.9k
            else
464
46.9k
            {
465
46.9k
                WORD64 i8_result = (frame_num_ofst + (WORD64)u2_frame_num) << 1;
466
46.9k
                if(IS_OUT_OF_RANGE_S32(i8_result))
467
0
                {
468
0
                    return ERROR_INV_POC;
469
0
                }
470
46.9k
                tmp_poc = i8_result;
471
46.9k
            }
472
473
            /* 6. TopFieldOrderCnt or BottomFieldOrderCnt are derived as */
474
59.8k
            if(!u1_field_pic_flag)
475
59.6k
            {
476
59.6k
                i4_top_field_order_cnt = tmp_poc;
477
59.6k
                i4_bottom_field_order_cnt = tmp_poc;
478
59.6k
            }
479
156
            else if(!u1_bottom_field_flag)
480
40
                i4_top_field_order_cnt = tmp_poc;
481
116
            else
482
116
                i4_bottom_field_order_cnt = tmp_poc;
483
484
            /* Copy the current POC info into Previous POC structure */
485
59.8k
            ps_prev_poc->i4_prev_frame_num_ofst = frame_num_ofst;
486
59.8k
            ps_cur_poc->i4_prev_frame_num_ofst = frame_num_ofst;
487
59.8k
        }
488
0
            break;
489
0
        default:
490
0
            return ERROR_INV_POC_TYPE_T;
491
0
            break;
492
2.56M
    }
493
494
2.56M
    if(!u1_field_pic_flag) // or a complementary field pair
495
2.56M
    {
496
2.56M
        *pi4_poc = MIN(i4_top_field_order_cnt, i4_bottom_field_order_cnt);
497
2.56M
        ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt;
498
2.56M
        ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt;
499
2.56M
    }
500
686
    else if(!u1_bottom_field_flag)
501
196
    {
502
196
        *pi4_poc = i4_top_field_order_cnt;
503
196
        ps_pps->i4_top_field_order_cnt = i4_top_field_order_cnt;
504
196
    }
505
490
    else
506
490
    {
507
490
        *pi4_poc = i4_bottom_field_order_cnt;
508
490
        ps_pps->i4_bottom_field_order_cnt = i4_bottom_field_order_cnt;
509
490
    }
510
511
2.56M
    ps_pps->i4_avg_poc = *pi4_poc;
512
513
2.56M
    return OK;
514
2.56M
}
515
516
/*!
517
 **************************************************************************
518
 * \if Function name : ih264d_end_of_pic_processing \endif
519
 *
520
 * \brief
521
 *    Performs the end of picture processing.
522
 *
523
 * It performs deblocking on the current picture and sets the i4_status of
524
 * current picture as decoded.
525
 *
526
 * \return
527
 *    0 on Success and Error code otherwise.
528
 **************************************************************************
529
 */
530
WORD32 ih264d_end_of_pic_processing(dec_struct_t *ps_dec)
531
184k
{
532
184k
    UWORD8 u1_pic_type, u1_nal_ref_idc;
533
184k
    dec_slice_params_t *ps_cur_slice = ps_dec->ps_cur_slice;
534
535
    /* If nal_ref_idc is equal to 0 for one slice or slice data partition NAL
536
     unit of a particular picture, it shall be equal to 0 for all slice and
537
     slice data partition NAL units of the picture. nal_ref_idc greater
538
     than 0 indicates that the content of the NAL unit belongs to a decoded
539
     picture that is stored and marked for use as a reference picture in the
540
     decoded picture buffer. */
541
542
    /* 1. Do MMCO
543
     2. Add Cur Pic to list of reference pics.
544
     */
545
546
    /* Call MMCO */
547
184k
    u1_pic_type = 0;
548
184k
    u1_nal_ref_idc = ps_cur_slice->u1_nal_ref_idc;
549
550
184k
    if(u1_nal_ref_idc)
551
160k
    {
552
160k
        if(ps_cur_slice->u1_nal_unit_type == IDR_SLICE_NAL)
553
135k
        {
554
135k
            ps_dec->ps_dpb_mgr->u1_mmco_error_in_seq = 0;
555
135k
            if(ps_dec->ps_dpb_cmds->u1_long_term_reference_flag == 0)
556
114k
            {
557
114k
                ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr);
558
                /* ignore DPB errors */
559
114k
                ih264d_insert_st_node(ps_dec->ps_dpb_mgr,
560
114k
                                      ps_dec->ps_cur_pic,
561
114k
                                      ps_dec->u1_pic_buf_id,
562
114k
                                      ps_cur_slice->u2_frame_num);
563
114k
                ps_dec->ps_dpb_mgr->u1_max_lt_frame_idx = NO_LONG_TERM_INDICIES;
564
114k
            }
565
20.7k
            else
566
20.7k
            {
567
                /* Equivalent of inserting a pic directly as longterm Pic */
568
569
20.7k
                {
570
                    /* ignore DPB errors */
571
20.7k
                    ih264d_insert_st_node(ps_dec->ps_dpb_mgr,
572
20.7k
                                          ps_dec->ps_cur_pic,
573
20.7k
                                          ps_dec->u1_pic_buf_id,
574
20.7k
                                          ps_cur_slice->u2_frame_num);
575
576
                    /* Set longTermIdx = 0, MaxLongTermFrameIdx = 0 */
577
20.7k
                    ih264d_delete_st_node_or_make_lt(
578
20.7k
                                    ps_dec->ps_dpb_mgr,
579
20.7k
                                    ps_cur_slice->u2_frame_num, 0,
580
20.7k
                                    ps_cur_slice->u1_field_pic_flag);
581
582
20.7k
                    ps_dec->ps_dpb_mgr->u1_max_lt_frame_idx = 0;
583
20.7k
                }
584
20.7k
            }
585
135k
        }
586
25.4k
        else
587
25.4k
        {
588
589
25.4k
            {
590
25.4k
                UWORD16 u2_pic_num = ps_cur_slice->u2_frame_num;
591
592
25.4k
                if(!ps_dec->ps_dpb_mgr->u1_mmco_error_in_seq)
593
21.9k
                {
594
21.9k
                    WORD32 ret = ih264d_do_mmco_buffer(ps_dec->ps_dpb_cmds, ps_dec->ps_dpb_mgr,
595
21.9k
                                               ps_dec->ps_cur_sps->u1_num_ref_frames, u2_pic_num,
596
21.9k
                                               (ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1),
597
21.9k
                                               ps_dec->u1_nal_unit_type, ps_dec->ps_cur_pic,
598
21.9k
                                               ps_dec->u1_pic_buf_id,
599
21.9k
                                               ps_cur_slice->u1_field_pic_flag,
600
21.9k
                                               ps_dec->e_dec_status);
601
21.9k
                    ps_dec->ps_dpb_mgr->u1_mmco_error_in_seq = ret != OK;
602
21.9k
                }
603
25.4k
            }
604
25.4k
        }
605
160k
        ih264d_update_default_index_list(ps_dec->ps_dpb_mgr);
606
160k
    }
607
608
184k
    if(ps_cur_slice->u1_field_pic_flag)
609
2.66k
    {
610
2.66k
        if(ps_cur_slice->u1_bottom_field_flag)
611
879
        {
612
879
            if(u1_nal_ref_idc)
613
758
                u1_pic_type = u1_pic_type | BOT_REF;
614
879
            u1_pic_type = u1_pic_type | BOT_FLD;
615
879
        }
616
1.78k
        else
617
1.78k
        {
618
1.78k
            if(u1_nal_ref_idc)
619
1.03k
                u1_pic_type = u1_pic_type | TOP_REF;
620
1.78k
            u1_pic_type = u1_pic_type | TOP_FLD;
621
1.78k
        }
622
2.66k
    }
623
181k
    else
624
181k
        u1_pic_type = TOP_REF | BOT_REF;
625
184k
    ps_dec->ps_cur_pic->u1_pic_type |= u1_pic_type;
626
627
628
184k
    if(ps_cur_slice->u1_field_pic_flag)
629
2.66k
    {
630
2.66k
        H264_DEC_DEBUG_PRINT("Toggling secondField\n");
631
2.66k
        ps_dec->u1_second_field = 1 - ps_dec->u1_second_field;
632
2.66k
    }
633
634
184k
    return OK;
635
184k
}
636
637
/*****************************************************************************/
638
/*                                                                           */
639
/*  Function Name : init_dpb_size                                            */
640
/*                                                                           */
641
/*  Description   : This function calculates the DBP i4_size in frames          */
642
/*  Inputs        : ps_seq - current sequence params                         */
643
/*                                                                           */
644
/*  Globals       : None                                                     */
645
/*                                                                           */
646
/*  Outputs       : None                                                     */
647
/*                                                                           */
648
/*  Returns       : DPB in frames                                            */
649
/*                                                                           */
650
/*  Issues        : None                                                     */
651
/*                                                                           */
652
/*  Revision History:                                                        */
653
/*                                                                           */
654
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
655
/*         28 04 2005   NS              Draft                                */
656
/*                                                                           */
657
/*****************************************************************************/
658
WORD32 ih264d_get_dpb_size(dec_seq_params_t *ps_seq)
659
139k
{
660
139k
    WORD32 i4_size;
661
139k
    UWORD8 u1_level_idc;
662
663
139k
    u1_level_idc = ps_seq->u1_level_idc;
664
665
139k
    switch(u1_level_idc)
666
139k
    {
667
1.07k
        case 10:
668
1.07k
            i4_size = 152064;
669
1.07k
            break;
670
26.5k
        case 11:
671
26.5k
            i4_size = 345600;
672
26.5k
            break;
673
2.22k
        case 12:
674
2.22k
            i4_size = 912384;
675
2.22k
            break;
676
1.74k
        case 13:
677
1.74k
            i4_size = 912384;
678
1.74k
            break;
679
32.6k
        case 20:
680
32.6k
            i4_size = 912384;
681
32.6k
            break;
682
4.06k
        case 21:
683
4.06k
            i4_size = 1824768;
684
4.06k
            break;
685
1.15k
        case 22:
686
1.15k
            i4_size = 3110400;
687
1.15k
            break;
688
1.12k
        case 30:
689
1.12k
            i4_size = 3110400;
690
1.12k
            break;
691
8.61k
        case 31:
692
8.61k
            i4_size = 6912000;
693
8.61k
            break;
694
10.5k
        case 32:
695
10.5k
            i4_size = 7864320;
696
10.5k
            break;
697
5.21k
        case 40:
698
5.21k
            i4_size = 12582912;
699
5.21k
            break;
700
2.22k
        case 41:
701
2.22k
            i4_size = 12582912;
702
2.22k
            break;
703
3.03k
        case 42:
704
3.03k
            i4_size = 12582912;
705
3.03k
            break;
706
583
        case 50:
707
583
            i4_size = 42393600;
708
583
            break;
709
464
        case 51:
710
464
            i4_size = 70778880;
711
464
            break;
712
24
        case 52:
713
24
            i4_size = 70778880;
714
24
            break;
715
38.5k
        default:
716
38.5k
            i4_size = 70778880;
717
38.5k
            break;
718
139k
    }
719
720
139k
    i4_size /= (ps_seq->u2_frm_wd_in_mbs * (ps_seq->u2_frm_ht_in_mbs << (1 - ps_seq->u1_frame_mbs_only_flag)));
721
139k
    i4_size /= 384;
722
139k
    i4_size = MIN(i4_size, 16);
723
139k
    i4_size = MAX(i4_size, 1);
724
139k
    return (i4_size);
725
139k
}
726
727
/**************************************************************************/
728
/* This function initialises the value of ps_dec->u4_recon_mb_grp         */
729
/* ps_dec->u4_recon_mb_grp must satisfy the following criteria            */
730
/*  - multiple of 2 (required for N/2 parse-mvpred design)                */
731
/*  - multiple of 4 (if it is not a frame_mbs_only sequence),             */
732
/*         in this case N/2 itself needs to be even for mbpair processing */
733
/*  - lesser than ps_dec->u2_frm_wd_in_mbs/2 (at least 3 N-Chunks       */
734
/*         should make a row to ensure proper MvTop transferring)         */
735
/**************************************************************************/
736
WORD32 ih264d_init_dec_mb_grp(dec_struct_t *ps_dec)
737
24.9k
{
738
24.9k
    dec_seq_params_t *ps_seq = ps_dec->ps_cur_sps;
739
24.9k
    UWORD8 u1_frm = ps_seq->u1_frame_mbs_only_flag;
740
741
24.9k
    ps_dec->u4_recon_mb_grp = ps_dec->u2_frm_wd_in_mbs << ps_seq->u1_mb_aff_flag;
742
743
24.9k
    ps_dec->u4_recon_mb_grp_pair = ps_dec->u4_recon_mb_grp >> 1;
744
745
24.9k
    if(!ps_dec->u4_recon_mb_grp)
746
0
    {
747
0
        return ERROR_MB_GROUP_ASSGN_T;
748
0
    }
749
750
24.9k
    ps_dec->u4_num_mbs_prev_nmb = ps_dec->u4_recon_mb_grp;
751
752
24.9k
    return OK;
753
24.9k
}
754
755
756
/*!
757
 **************************************************************************
758
 * \if Function name : ih264d_init_pic \endif
759
 *
760
 * \brief
761
 *    Initializes the picture.
762
 *
763
 * \return
764
 *    0 on Success and Error code otherwise
765
 *
766
 * \note
767
 *    This function is called when first slice of the
768
 *    NON -IDR picture is encountered.
769
 **************************************************************************
770
 */
771
WORD32 ih264d_init_pic(dec_struct_t *ps_dec,
772
                       UWORD16 u2_frame_num,
773
                       WORD32 i4_poc,
774
                       dec_pic_params_t *ps_pps)
775
8.53k
{
776
8.53k
    dec_seq_params_t *ps_seq = ps_pps->ps_sps;
777
8.53k
    prev_seq_params_t * ps_prev_seq_params = &ps_dec->s_prev_seq_params;
778
8.53k
    WORD32 i4_pic_bufs;
779
8.53k
    WORD32 ret;
780
781
8.53k
    ps_dec->ps_cur_slice->u2_frame_num = u2_frame_num;
782
8.53k
    ps_dec->ps_cur_slice->i4_poc = i4_poc;
783
8.53k
    ps_dec->ps_cur_pps = ps_pps;
784
8.53k
    ps_dec->ps_cur_pps->pv_codec_handle = ps_dec;
785
786
8.53k
    ps_dec->ps_cur_sps = ps_seq;
787
8.53k
    ps_dec->ps_dpb_mgr->i4_max_frm_num = ps_seq->u2_u4_max_pic_num_minus1
788
8.53k
                    + 1;
789
790
8.53k
    ps_dec->ps_dpb_mgr->u2_pic_ht = ps_dec->u2_pic_ht;
791
8.53k
    ps_dec->ps_dpb_mgr->u2_pic_wd = ps_dec->u2_pic_wd;
792
8.53k
    ps_dec->i4_pic_type = NA_SLICE;
793
8.53k
    ps_dec->i4_frametype = IV_NA_FRAME;
794
8.53k
    ps_dec->i4_content_type = IV_CONTENTTYPE_NA;
795
796
    /*--------------------------------------------------------------------*/
797
    /* Get the value of MaxMbAddress and frmheight in Mbs                 */
798
    /*--------------------------------------------------------------------*/
799
8.53k
    ps_seq->u4_max_mb_addr =
800
8.53k
                    ((UWORD32)ps_seq->u2_frm_wd_in_mbs
801
8.53k
                                    * ((UWORD32)ps_dec->u2_pic_ht
802
8.53k
                                                    >> (4
803
8.53k
                                                                    + ps_dec->ps_cur_slice->u1_field_pic_flag)))
804
8.53k
                                    - 1;
805
8.53k
    ps_dec->u2_frm_ht_in_mbs = (ps_dec->u2_pic_ht
806
8.53k
                    >> (4 + ps_dec->ps_cur_slice->u1_field_pic_flag));
807
808
    /***************************************************************************/
809
    /* If change in Level or the required PicBuffers i4_size is more than the  */
810
    /* current one FREE the current PicBuffers and allocate affresh            */
811
    /***************************************************************************/
812
8.53k
    if(!ps_dec->u1_init_dec_flag)
813
629
    {
814
629
        ps_dec->u1_max_dec_frame_buffering = ih264d_get_dpb_size(ps_seq);
815
816
629
        ps_dec->i4_display_delay = ps_dec->u1_max_dec_frame_buffering;
817
629
        if((1 == ps_seq->u1_vui_parameters_present_flag) &&
818
145
           (1 == ps_seq->s_vui.u1_bitstream_restriction_flag))
819
125
        {
820
125
            if(ps_seq->u1_frame_mbs_only_flag == 1)
821
121
                ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames + 1;
822
4
            else
823
4
                ps_dec->i4_display_delay = ps_seq->s_vui.u4_num_reorder_frames * 2 + 2;
824
125
        }
825
826
629
        if(IVD_DECODE_FRAME_OUT == ps_dec->e_frm_out_mode)
827
0
            ps_dec->i4_display_delay = 0;
828
829
629
        if(ps_dec->u4_share_disp_buf == 0)
830
629
        {
831
629
            UWORD8 u1_num_ref_frames = ps_dec->u4_thumbnail_mode ? 0 : ps_seq->u1_num_ref_frames;
832
629
            if(ps_seq->u1_frame_mbs_only_flag == 1)
833
358
                ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + u1_num_ref_frames + 1;
834
271
            else
835
271
                ps_dec->u1_pic_bufs = ps_dec->i4_display_delay + u1_num_ref_frames * 2 + 2;
836
629
        }
837
0
        else
838
0
        {
839
0
            ps_dec->u1_pic_bufs = (WORD32)ps_dec->u4_num_disp_bufs;
840
0
        }
841
842
629
        if(!ps_dec->u4_thumbnail_mode)
843
629
        {
844
            /* Ensure at least two buffers are allocated */
845
629
            ps_dec->u1_pic_bufs = MAX(ps_dec->u1_pic_bufs, 2);
846
629
        }
847
848
629
        if(ps_dec->u4_share_disp_buf == 0)
849
629
            ps_dec->u1_pic_bufs = MIN(ps_dec->u1_pic_bufs,
850
629
                                      (H264_MAX_REF_PICS * 2));
851
852
629
        ps_dec->u1_max_dec_frame_buffering = MIN(
853
629
                        ps_dec->u1_max_dec_frame_buffering,
854
629
                        ps_dec->u1_pic_bufs);
855
856
        /* Temporary hack to run Tractor Cav/Cab/MbAff Profiler streams  also for CAFI1_SVA_C.264 in conformance*/
857
629
        if(ps_dec->u1_init_dec_flag)
858
0
        {
859
0
            ih264d_release_pics_in_dpb((void *)ps_dec,
860
0
                                       ps_dec->u1_pic_bufs);
861
0
            ih264d_release_display_bufs(ps_dec);
862
0
            ih264d_reset_ref_bufs(ps_dec->ps_dpb_mgr);
863
0
        }
864
865
        /*********************************************************************/
866
        /* Configuring decoder parameters based on level and then            */
867
        /* fresh pointer initialisation in decoder scratch and state buffers */
868
        /*********************************************************************/
869
629
        if(!ps_dec->u1_init_dec_flag ||
870
0
                ((ps_seq->u1_level_idc < H264_LEVEL_3_0) ^ (ps_prev_seq_params->u1_level_idc < H264_LEVEL_3_0)))
871
629
        {
872
629
            ret = ih264d_init_dec_mb_grp(ps_dec);
873
629
            if(ret != OK)
874
0
                return ret;
875
629
        }
876
877
629
        ret = ih264d_allocate_dynamic_bufs(ps_dec);
878
629
        if(ret != OK)
879
0
        {
880
            /* Free any dynamic buffers that are allocated */
881
0
            ih264d_free_dynamic_bufs(ps_dec);
882
0
            ps_dec->i4_error_code = IVD_MEM_ALLOC_FAILED;
883
0
            return IVD_MEM_ALLOC_FAILED;
884
0
        }
885
886
629
        ret = ih264d_create_pic_buffers(ps_dec->u1_pic_bufs,
887
629
                                        ps_dec);
888
629
        if(ret != OK)
889
0
            return ret;
890
891
892
893
629
        ret = ih264d_create_mv_bank(ps_dec, ps_dec->u2_pic_wd,
894
629
                                    ps_dec->u2_pic_ht);
895
629
        if(ret != OK)
896
0
            return ret;
897
898
        /* In shared mode, set all of them as used by display */
899
629
        if(ps_dec->u4_share_disp_buf == 1)
900
0
        {
901
0
            WORD32 i;
902
903
0
            for(i = 0; i < ps_dec->u1_pic_bufs; i++)
904
0
            {
905
0
                ih264_buf_mgr_set_status((buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i,
906
0
                                         BUF_MGR_IO);
907
0
            }
908
0
        }
909
910
629
        ps_dec->u1_init_dec_flag = 1;
911
629
        ps_prev_seq_params->u2_frm_wd_in_mbs = ps_seq->u2_frm_wd_in_mbs;
912
629
        ps_prev_seq_params->u1_level_idc = ps_seq->u1_level_idc;
913
629
        ps_prev_seq_params->u1_profile_idc = ps_seq->u1_profile_idc;
914
629
        ps_prev_seq_params->u2_frm_ht_in_mbs = ps_seq->u2_frm_ht_in_mbs;
915
629
        ps_prev_seq_params->u1_frame_mbs_only_flag =
916
629
                        ps_seq->u1_frame_mbs_only_flag;
917
629
        ps_prev_seq_params->u1_direct_8x8_inference_flag =
918
629
                        ps_seq->u1_direct_8x8_inference_flag;
919
920
629
        ps_dec->i4_cur_display_seq = 0;
921
629
        ps_dec->i4_prev_max_display_seq = 0;
922
629
        ps_dec->i4_max_poc = 0;
923
924
629
        {
925
            /* 0th entry of CtxtIncMbMap will be always be containing default values
926
             for CABAC context representing MB not available */
927
629
            ctxt_inc_mb_info_t *p_DefCtxt = ps_dec->p_ctxt_inc_mb_map - 1;
928
629
            UWORD8 *pu1_temp;
929
629
            WORD8 i;
930
629
            p_DefCtxt->u1_mb_type = CAB_SKIP;
931
932
629
            p_DefCtxt->u1_cbp = 0x0f;
933
629
            p_DefCtxt->u1_intra_chroma_pred_mode = 0;
934
935
629
            p_DefCtxt->u1_yuv_dc_csbp = 0x7;
936
937
629
            p_DefCtxt->u1_transform8x8_ctxt = 0;
938
939
629
            pu1_temp = (UWORD8*)p_DefCtxt->i1_ref_idx;
940
3.14k
            for(i = 0; i < 4; i++, pu1_temp++)
941
2.51k
                (*pu1_temp) = 0;
942
629
            pu1_temp = (UWORD8*)p_DefCtxt->u1_mv;
943
10.6k
            for(i = 0; i < 16; i++, pu1_temp++)
944
10.0k
                (*pu1_temp) = 0;
945
629
            ps_dec->ps_def_ctxt_mb_info = p_DefCtxt;
946
629
        }
947
948
629
    }
949
    /* reset DBP commands read u4_flag */
950
8.53k
    ps_dec->ps_dpb_cmds->u1_dpb_commands_read = 0;
951
952
8.53k
    return OK;
953
8.53k
}
954
955
/*****************************************************************************/
956
/*                                                                           */
957
/*  Function Name : ih264d_get_next_display_field                                   */
958
/*                                                                           */
959
/*  Description   : Application calls this module to get the next field      */
960
/*                  to be displayed                                          */
961
/*                                                                           */
962
/*  Inputs        : 1.   IBUFAPI_Handle Hnadle to the Display buffer         */
963
/*                  2.   IH264DEC_DispUnit    Pointer to the display struct  */
964
/*                                                                           */
965
/*  Globals       :                                                          */
966
/*                                                                           */
967
/*                                                                           */
968
/*  Processing    : None                                                     */
969
/*  Outputs       : None                                                     */
970
/*  Returns       : None                                                     */
971
/*  Issues        : None                                                     */
972
/*                                                                           */
973
/*  Revision History:                                                        */
974
/*                                                                           */
975
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
976
/*         27 05 2005   Ittiam          Draft                                */
977
/*                                                                           */
978
/*****************************************************************************/
979
980
WORD32 ih264d_get_next_display_field(dec_struct_t * ps_dec,
981
                                  ivd_out_bufdesc_t *ps_out_buffer,
982
                                  ivd_get_display_frame_op_t *pv_disp_op)
983
273k
{
984
273k
    pic_buffer_t *pic_buf;
985
986
273k
    UWORD8 i1_cur_fld;
987
273k
    WORD32 u4_api_ret = -1;
988
273k
    WORD32 i4_disp_buf_id;
989
273k
    iv_yuv_buf_t *ps_op_frm;
990
991
992
993
273k
    ps_op_frm = &(ps_dec->s_disp_frame_info);
994
273k
    H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
995
273k
    pic_buf = (pic_buffer_t *)ih264_disp_mgr_get(
996
273k
                    (disp_mgr_t *)ps_dec->pv_disp_buf_mgr, &i4_disp_buf_id);
997
273k
    ps_dec->u4_num_fld_in_frm = 0;
998
273k
    u4_api_ret = -1;
999
273k
    pv_disp_op->u4_ts = 0;
1000
273k
    pv_disp_op->e_output_format = ps_dec->u1_chroma_format;
1001
1002
273k
    pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_out_buffer->pu1_bufs[0];
1003
273k
    pv_disp_op->s_disp_frm_buf.pv_u_buf = ps_out_buffer->pu1_bufs[1];
1004
273k
    pv_disp_op->s_disp_frm_buf.pv_v_buf = ps_out_buffer->pu1_bufs[2];
1005
273k
    ps_dec->i4_display_index  = DEFAULT_POC;
1006
273k
    if(pic_buf != NULL)
1007
138k
    {
1008
138k
        ps_dec->pv_disp_sei_params = &pic_buf->s_sei_pic;
1009
138k
        pv_disp_op->e4_fld_type = 0;
1010
138k
        pv_disp_op->u4_disp_buf_id = i4_disp_buf_id;
1011
1012
138k
        ps_op_frm->u4_y_ht = pic_buf->u2_disp_height << 1;
1013
138k
        ps_op_frm->u4_u_ht = ps_op_frm->u4_v_ht = ps_op_frm->u4_y_ht >> 1;
1014
138k
        ps_op_frm->u4_y_wd = pic_buf->u2_disp_width;
1015
1016
138k
        ps_op_frm->u4_u_wd = ps_op_frm->u4_v_wd = ps_op_frm->u4_y_wd >> 1;
1017
1018
138k
        ps_op_frm->u4_y_strd = pic_buf->u2_frm_wd_y;
1019
138k
        ps_op_frm->u4_u_strd = ps_op_frm->u4_v_strd = pic_buf->u2_frm_wd_uv;
1020
1021
        /* ! */
1022
138k
        pv_disp_op->u4_ts = pic_buf->u4_ts;
1023
138k
        ps_dec->i4_display_index = pic_buf->i4_poc;
1024
1025
        /* set the start of the Y, U and V buffer pointer for display    */
1026
138k
        ps_op_frm->pv_y_buf = pic_buf->pu1_buf1 + pic_buf->u2_crop_offset_y;
1027
138k
        ps_op_frm->pv_u_buf = pic_buf->pu1_buf2 + pic_buf->u2_crop_offset_uv;
1028
138k
        ps_op_frm->pv_v_buf = pic_buf->pu1_buf3 + pic_buf->u2_crop_offset_uv;
1029
138k
        ps_dec->u4_num_fld_in_frm++;
1030
138k
        ps_dec->u4_num_fld_in_frm++;
1031
138k
        u4_api_ret = 0;
1032
1033
138k
        if(pic_buf->u1_picturetype == 0)
1034
136k
            pv_disp_op->u4_progressive_frame_flag = 1;
1035
1.44k
        else
1036
1.44k
            pv_disp_op->u4_progressive_frame_flag = 0;
1037
1038
138k
    } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
1039
273k
    pv_disp_op->u4_error_code = u4_api_ret;
1040
273k
    pv_disp_op->e_pic_type = 0xFFFFFFFF; //Junk;
1041
1042
273k
    if(u4_api_ret)
1043
135k
    {
1044
135k
        pv_disp_op->u4_error_code = 1; //put a proper error code here
1045
135k
    }
1046
138k
    else
1047
138k
    {
1048
1049
        //Release the buffer if being sent for display
1050
138k
        UWORD32 temp;
1051
138k
        UWORD32 dest_inc_Y = 0, dest_inc_UV = 0;
1052
1053
138k
        pv_disp_op->s_disp_frm_buf.u4_y_wd = temp = MIN(ps_op_frm->u4_y_wd,
1054
138k
                                                        ps_op_frm->u4_y_strd);
1055
138k
        pv_disp_op->s_disp_frm_buf.u4_u_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd
1056
138k
                        >> 1;
1057
138k
        pv_disp_op->s_disp_frm_buf.u4_v_wd = pv_disp_op->s_disp_frm_buf.u4_y_wd
1058
138k
                        >> 1;
1059
1060
138k
        pv_disp_op->s_disp_frm_buf.u4_y_ht = ps_op_frm->u4_y_ht;
1061
138k
        pv_disp_op->s_disp_frm_buf.u4_u_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht
1062
138k
                        >> 1;
1063
138k
        pv_disp_op->s_disp_frm_buf.u4_v_ht = pv_disp_op->s_disp_frm_buf.u4_y_ht
1064
138k
                        >> 1;
1065
138k
        if(0 == ps_dec->u4_share_disp_buf)
1066
138k
        {
1067
138k
            pv_disp_op->s_disp_frm_buf.u4_y_strd =
1068
138k
                            pv_disp_op->s_disp_frm_buf.u4_y_wd;
1069
138k
            pv_disp_op->s_disp_frm_buf.u4_u_strd =
1070
138k
                            pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1;
1071
138k
            pv_disp_op->s_disp_frm_buf.u4_v_strd =
1072
138k
                            pv_disp_op->s_disp_frm_buf.u4_y_wd >> 1;
1073
1074
138k
        }
1075
0
        else
1076
0
        {
1077
0
            pv_disp_op->s_disp_frm_buf.u4_y_strd = ps_op_frm->u4_y_strd;
1078
0
        }
1079
1080
138k
        if(ps_dec->u4_app_disp_width)
1081
0
        {
1082
0
            pv_disp_op->s_disp_frm_buf.u4_y_strd = MAX(
1083
0
                            ps_dec->u4_app_disp_width,
1084
0
                            pv_disp_op->s_disp_frm_buf.u4_y_strd);
1085
0
        }
1086
1087
138k
        pv_disp_op->u4_error_code = 0;
1088
138k
        if(pv_disp_op->e_output_format == IV_YUV_420P)
1089
67.5k
        {
1090
67.5k
            UWORD32 i;
1091
67.5k
            pv_disp_op->s_disp_frm_buf.u4_u_strd =
1092
67.5k
                            pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1;
1093
67.5k
            pv_disp_op->s_disp_frm_buf.u4_v_strd =
1094
67.5k
                            pv_disp_op->s_disp_frm_buf.u4_y_strd >> 1;
1095
1096
67.5k
            pv_disp_op->s_disp_frm_buf.u4_u_wd = ps_op_frm->u4_y_wd >> 1;
1097
67.5k
            pv_disp_op->s_disp_frm_buf.u4_v_wd = ps_op_frm->u4_y_wd >> 1;
1098
1099
67.5k
            if(1 == ps_dec->u4_share_disp_buf)
1100
0
            {
1101
0
                pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf;
1102
1103
0
                for(i = 0; i < MAX_DISP_BUFS_NEW; i++)
1104
0
                {
1105
0
                    UWORD8 *buf = ps_dec->disp_bufs[i].buf[0];
1106
0
                    buf += ps_dec->disp_bufs[i].u4_ofst[0];
1107
0
                    if(((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf
1108
0
                                    - pic_buf->u2_crop_offset_y) == buf)
1109
0
                    {
1110
0
                        buf = ps_dec->disp_bufs[i].buf[1];
1111
0
                        buf += ps_dec->disp_bufs[i].u4_ofst[1];
1112
0
                        pv_disp_op->s_disp_frm_buf.pv_u_buf = buf
1113
0
                                        + (pic_buf->u2_crop_offset_uv
1114
0
                                           / YUV420SP_FACTOR);
1115
1116
0
                        buf = ps_dec->disp_bufs[i].buf[2];
1117
0
                        buf += ps_dec->disp_bufs[i].u4_ofst[2];
1118
0
                        pv_disp_op->s_disp_frm_buf.pv_v_buf = buf
1119
0
                                        + (pic_buf->u2_crop_offset_uv
1120
0
                                           / YUV420SP_FACTOR);
1121
1122
0
                    }
1123
0
                }
1124
0
            }
1125
1126
67.5k
        }
1127
70.7k
        else if((pv_disp_op->e_output_format == IV_YUV_420SP_UV)
1128
26.6k
                        || (pv_disp_op->e_output_format == IV_YUV_420SP_VU))
1129
69.1k
        {
1130
69.1k
            pv_disp_op->s_disp_frm_buf.u4_u_strd =
1131
69.1k
                            pv_disp_op->s_disp_frm_buf.u4_y_strd;
1132
69.1k
            pv_disp_op->s_disp_frm_buf.u4_v_strd = 0;
1133
1134
69.1k
            if(1 == ps_dec->u4_share_disp_buf)
1135
0
            {
1136
0
                UWORD32 i;
1137
1138
0
                pv_disp_op->s_disp_frm_buf.pv_y_buf = ps_op_frm->pv_y_buf;
1139
1140
0
                for(i = 0; i < MAX_DISP_BUFS_NEW; i++)
1141
0
                {
1142
0
                    UWORD8 *buf = ps_dec->disp_bufs[i].buf[0];
1143
0
                    buf += ps_dec->disp_bufs[i].u4_ofst[0];
1144
0
                    if((UWORD8 *)pv_disp_op->s_disp_frm_buf.pv_y_buf
1145
0
                                    - pic_buf->u2_crop_offset_y == buf)
1146
0
                    {
1147
0
                        buf = ps_dec->disp_bufs[i].buf[1];
1148
0
                        buf += ps_dec->disp_bufs[i].u4_ofst[1];
1149
0
                        pv_disp_op->s_disp_frm_buf.pv_u_buf = buf
1150
0
                                        + pic_buf->u2_crop_offset_uv;
1151
0
                        ;
1152
1153
0
                        buf = ps_dec->disp_bufs[i].buf[2];
1154
0
                        buf += ps_dec->disp_bufs[i].u4_ofst[2];
1155
0
                        pv_disp_op->s_disp_frm_buf.pv_v_buf = buf
1156
0
                                        + pic_buf->u2_crop_offset_uv;
1157
0
                        ;
1158
0
                    }
1159
0
                }
1160
0
            }
1161
69.1k
            pv_disp_op->s_disp_frm_buf.u4_u_wd =
1162
69.1k
                            pv_disp_op->s_disp_frm_buf.u4_y_wd;
1163
69.1k
            pv_disp_op->s_disp_frm_buf.u4_v_wd = 0;
1164
1165
69.1k
        }
1166
1.60k
        else if((pv_disp_op->e_output_format == IV_RGB_565)
1167
962
                        || (pv_disp_op->e_output_format == IV_YUV_422ILE))
1168
1.60k
        {
1169
1170
1.60k
            pv_disp_op->s_disp_frm_buf.u4_u_strd = 0;
1171
1.60k
            pv_disp_op->s_disp_frm_buf.u4_v_strd = 0;
1172
1.60k
            pv_disp_op->s_disp_frm_buf.u4_u_wd = 0;
1173
1.60k
            pv_disp_op->s_disp_frm_buf.u4_v_wd = 0;
1174
1.60k
            pv_disp_op->s_disp_frm_buf.u4_u_ht = 0;
1175
1.60k
            pv_disp_op->s_disp_frm_buf.u4_v_ht = 0;
1176
1177
1.60k
        }
1178
1179
1180
138k
    }
1181
1182
273k
    return u4_api_ret;
1183
273k
}
1184
1185
1186
/*****************************************************************************/
1187
/*  Function Name : ih264d_release_display_field                                         */
1188
/*                                                                           */
1189
/*  Description   : This function releases the display field that was returned   */
1190
/*                  here.                                                    */
1191
/*  Inputs        : ps_dec - Decoder parameters                              */
1192
/*  Globals       : None                                                     */
1193
/*  Processing    : Refer bumping process in the standard                    */
1194
/*  Outputs       : Assigns display sequence number.                         */
1195
/*  Returns       : None                                                     */
1196
/*                                                                           */
1197
/*  Issues        : None                                                     */
1198
/*                                                                           */
1199
/*  Revision History:                                                        */
1200
/*                                                                           */
1201
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1202
/*         27 04 2005   NS              Draft                                */
1203
/*                                                                           */
1204
/*****************************************************************************/
1205
void ih264d_release_display_field(dec_struct_t *ps_dec,
1206
                                  ivd_get_display_frame_op_t *pv_disp_op)
1207
186k
{
1208
186k
    if(1 == pv_disp_op->u4_error_code)
1209
105k
    {
1210
105k
        if(1 == ps_dec->u1_flushfrm)
1211
0
        {
1212
0
            UWORD32 i;
1213
1214
0
            if(1 == ps_dec->u4_share_disp_buf)
1215
0
            {
1216
0
                H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
1217
0
                for(i = 0; i < (MAX_DISP_BUFS_NEW); i++)
1218
0
                {
1219
0
                    if(1 == ps_dec->u4_disp_buf_mapping[i])
1220
0
                    {
1221
0
                        ih264_buf_mgr_release(
1222
0
                                        (buf_mgr_t *)ps_dec->pv_pic_buf_mgr, i,
1223
0
                                        BUF_MGR_IO);
1224
0
                        ps_dec->u4_disp_buf_mapping[i] = 0;
1225
0
                    }
1226
0
                } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
1227
1228
0
                memset(ps_dec->u4_disp_buf_to_be_freed, 0,
1229
0
                       (MAX_DISP_BUFS_NEW) * sizeof(UWORD32));
1230
0
                for(i = 0; i < ps_dec->u1_pic_bufs; i++)
1231
0
                    ps_dec->u4_disp_buf_mapping[i] = 1;
1232
0
            }
1233
0
            ps_dec->u1_flushfrm = 0;
1234
1235
0
        }
1236
105k
    }
1237
81.0k
    else
1238
81.0k
    {
1239
81.0k
        H264_MUTEX_LOCK(&ps_dec->process_disp_mutex);
1240
1241
81.0k
        if(0 == ps_dec->u4_share_disp_buf)
1242
81.0k
        {
1243
81.0k
            ih264_buf_mgr_release((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1244
81.0k
                                  pv_disp_op->u4_disp_buf_id,
1245
81.0k
                                  BUF_MGR_IO);
1246
1247
81.0k
        }
1248
0
        else
1249
0
        {
1250
0
            ps_dec->u4_disp_buf_mapping[pv_disp_op->u4_disp_buf_id] = 1;
1251
0
        } H264_MUTEX_UNLOCK(&ps_dec->process_disp_mutex);
1252
1253
81.0k
    }
1254
186k
}
1255
/*****************************************************************************/
1256
/*  Function Name : ih264d_assign_display_seq                                         */
1257
/*                                                                           */
1258
/*  Description   : This function implments bumping process. Every outgoing  */
1259
/*                  frame from DPB is assigned a display sequence number     */
1260
/*                  which increases monotonically. System looks for this     */
1261
/*                  number to display a frame.                              */
1262
/*                  here.                                                    */
1263
/*  Inputs        : ps_dec - Decoder parameters                              */
1264
/*  Globals       : None                                                     */
1265
/*  Processing    : Refer bumping process in the standard                    */
1266
/*  Outputs       : Assigns display sequence number.                         */
1267
/*  Returns       : None                                                     */
1268
/*                                                                           */
1269
/*  Issues        : None                                                     */
1270
/*                                                                           */
1271
/*  Revision History:                                                        */
1272
/*                                                                           */
1273
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1274
/*         27 04 2005   NS              Draft                                */
1275
/*                                                                           */
1276
/*****************************************************************************/
1277
WORD32 ih264d_assign_display_seq(dec_struct_t *ps_dec)
1278
182k
{
1279
182k
    WORD32 i;
1280
182k
    WORD32 i4_min_poc;
1281
182k
    WORD32 i4_min_poc_buf_id;
1282
182k
    WORD32 i4_min_index;
1283
182k
    dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1284
182k
    WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map;
1285
1286
182k
    i4_min_poc = 0x7fffffff;
1287
182k
    i4_min_poc_buf_id = -1;
1288
182k
    i4_min_index = -1;
1289
1290
182k
    if(ps_dpb_mgr->i1_poc_buf_id_entries >= ps_dec->i4_display_delay)
1291
8.94k
    {
1292
161k
        for(i = 0; i < MAX_BUF_ID_MAP_ENTRIES; i++)
1293
152k
        {
1294
152k
            if((i4_poc_buf_id_map[i][0] != -1)
1295
85.4k
                            && (DO_NOT_DISP
1296
85.4k
                                            != ps_dpb_mgr->ai4_poc_buf_id_map[i][0]))
1297
82.1k
            {
1298
                /* Checking for <= is necessary to handle cases where there is one
1299
                   valid buffer with poc set to 0x7FFFFFFF. */
1300
82.1k
                if(i4_poc_buf_id_map[i][1] <= i4_min_poc)
1301
32.5k
                {
1302
32.5k
                    i4_min_poc = i4_poc_buf_id_map[i][1];
1303
32.5k
                    i4_min_poc_buf_id = i4_poc_buf_id_map[i][0];
1304
32.5k
                    i4_min_index = i;
1305
32.5k
                }
1306
82.1k
            }
1307
152k
        }
1308
1309
8.94k
        if((i4_min_index != -1) && (DO_NOT_DISP != i4_min_poc_buf_id))
1310
8.89k
        {
1311
8.89k
            ps_dec->i4_cur_display_seq++;
1312
8.89k
            ih264_disp_mgr_add(
1313
8.89k
                            (disp_mgr_t *)ps_dec->pv_disp_buf_mgr,
1314
8.89k
                            i4_min_poc_buf_id, ps_dec->i4_cur_display_seq,
1315
8.89k
                            ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]);
1316
8.89k
            i4_poc_buf_id_map[i4_min_index][0] = -1;
1317
8.89k
            i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1318
8.89k
            ps_dpb_mgr->i1_poc_buf_id_entries--;
1319
8.89k
        }
1320
59
        else if(DO_NOT_DISP == i4_min_poc_buf_id)
1321
0
        {
1322
0
            WORD32 i4_error_code;
1323
0
            i4_error_code = ERROR_GAPS_IN_FRM_NUM;
1324
//          i4_error_code |= 1<<IVD_CORRUPTEDDATA;
1325
0
            return i4_error_code;
1326
0
        }
1327
8.94k
    }
1328
182k
    return OK;
1329
182k
}
1330
1331
/*****************************************************************************/
1332
/*                                                                           */
1333
/*  Function Name : ih264d_release_display_bufs                                       */
1334
/*                                                                           */
1335
/*  Description   : This function implments bumping process when mmco = 5.   */
1336
/*                  Each outgoing frame from DPB is assigned a display       */
1337
/*                  sequence number which increases monotonically. System    */
1338
/*                  looks for this number to display a frame.                */
1339
/*  Inputs        : ps_dec - Decoder parameters                              */
1340
/*  Globals       : None                                                     */
1341
/*  Processing    : Refer bumping process in the standard for mmco = 5       */
1342
/*  Outputs       : Assigns display sequence number.                         */
1343
/*  Returns       : None                                                     */
1344
/*                                                                           */
1345
/*  Issues        : None                                                     */
1346
/*                                                                           */
1347
/*  Revision History:                                                        */
1348
/*                                                                           */
1349
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1350
/*         27 04 2005   NS              Draft                                */
1351
/*                                                                           */
1352
/*****************************************************************************/
1353
void ih264d_release_display_bufs(dec_struct_t *ps_dec)
1354
148k
{
1355
148k
    WORD32 i, j;
1356
148k
    WORD32 i4_min_poc;
1357
148k
    WORD32 i4_min_poc_buf_id;
1358
148k
    WORD32 i4_min_index;
1359
148k
    WORD64 i8_temp;
1360
148k
    dpb_manager_t *ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1361
148k
    WORD32 (*i4_poc_buf_id_map)[3] = ps_dpb_mgr->ai4_poc_buf_id_map;
1362
1363
148k
    i4_min_poc = 0x7fffffff;
1364
148k
    i4_min_poc_buf_id = 0;
1365
148k
    i4_min_index = 0;
1366
1367
148k
    ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1368
1369
293k
    for(j = 0; j < ps_dpb_mgr->i1_poc_buf_id_entries; j++)
1370
145k
    {
1371
145k
        i4_min_poc = 0x7fffffff;
1372
2.62M
        for(i = 0; i < MAX_BUF_ID_MAP_ENTRIES; i++)
1373
2.47M
        {
1374
2.47M
            if(i4_poc_buf_id_map[i][0] != -1)
1375
215k
            {
1376
                /* Checking for <= is necessary to handle cases where there is one
1377
                   valid buffer with poc set to 0x7FFFFFFF. */
1378
215k
                if(i4_poc_buf_id_map[i][1] <= i4_min_poc)
1379
181k
                {
1380
181k
                    i4_min_poc = i4_poc_buf_id_map[i][1];
1381
181k
                    i4_min_poc_buf_id = i4_poc_buf_id_map[i][0];
1382
181k
                    i4_min_index = i;
1383
181k
                }
1384
215k
            }
1385
2.47M
        }
1386
1387
145k
        if(DO_NOT_DISP != i4_min_poc_buf_id)
1388
142k
        {
1389
142k
            ps_dec->i4_cur_display_seq++;
1390
142k
            ih264_disp_mgr_add(
1391
142k
                            (disp_mgr_t *)ps_dec->pv_disp_buf_mgr,
1392
142k
                            i4_min_poc_buf_id, ps_dec->i4_cur_display_seq,
1393
142k
                            ps_dec->apv_buf_id_pic_buf_map[i4_min_poc_buf_id]);
1394
142k
            i4_poc_buf_id_map[i4_min_index][0] = -1;
1395
142k
            i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1396
142k
            ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0;
1397
142k
        }
1398
3.35k
        else
1399
3.35k
        {
1400
3.35k
            i4_poc_buf_id_map[i4_min_index][0] = -1;
1401
3.35k
            i4_poc_buf_id_map[i4_min_index][1] = 0x7fffffff;
1402
3.35k
            ps_dpb_mgr->ai4_poc_buf_id_map[i4_min_index][2] = 0;
1403
3.35k
        }
1404
145k
    }
1405
148k
    ps_dpb_mgr->i1_poc_buf_id_entries = 0;
1406
148k
    i8_temp = (WORD64)ps_dec->i4_prev_max_display_seq + ps_dec->i4_max_poc
1407
148k
              + ps_dec->u1_max_dec_frame_buffering + 1;
1408
    /*If i4_prev_max_display_seq overflows integer range, reset it */
1409
148k
    ps_dec->i4_prev_max_display_seq = IS_OUT_OF_RANGE_S32(i8_temp)?
1410
147k
                                      0 : i8_temp;
1411
148k
    ps_dec->i4_max_poc = 0;
1412
148k
}
1413
1414
/*****************************************************************************/
1415
/*                                                                           */
1416
/*  Function Name : ih264d_assign_pic_num                                           */
1417
/*                                                                           */
1418
/*  Description   : This function assigns pic num to each reference frame    */
1419
/*                  depending on the cur_frame_num as speified in section    */
1420
/*                  8.2.4.1                                                  */
1421
/*                                                                           */
1422
/*  Inputs        : ps_dec                                                   */
1423
/*                                                                           */
1424
/*  Globals       : NO globals used                                          */
1425
/*                                                                           */
1426
/*  Processing    : for all ST pictures                                      */
1427
/*                    if( FrameNum > cur_frame_num)                          */
1428
/*                    PicNum = FrameNum - MaxFrameNum                        */
1429
/*                    else                                                   */
1430
/*                    PicNum = FrameNum                                      */
1431
/*                                                                           */
1432
/*  Returns       : void                                                     */
1433
/*                                                                           */
1434
/*  Issues        : NO                                                       */
1435
/*                                                                           */
1436
/*  Revision History:                                                        */
1437
/*                                                                           */
1438
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1439
/*         13 07 2002   Jay             Draft                                */
1440
/*                                                                           */
1441
/*****************************************************************************/
1442
1443
void ih264d_assign_pic_num(dec_struct_t *ps_dec)
1444
199k
{
1445
199k
    dpb_manager_t *ps_dpb_mgr;
1446
199k
    struct dpb_info_t *ps_next_dpb;
1447
199k
    WORD8 i;
1448
199k
    WORD32 i4_cur_frame_num, i4_max_frame_num;
1449
199k
    WORD32 i4_ref_frame_num;
1450
199k
    UWORD8 u1_fld_pic_flag = ps_dec->ps_cur_slice->u1_field_pic_flag;
1451
1452
199k
    i4_max_frame_num = ps_dec->ps_cur_sps->u2_u4_max_pic_num_minus1 + 1;
1453
199k
    i4_cur_frame_num = ps_dec->ps_cur_pic->i4_frame_num;
1454
199k
    ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1455
1456
    /* Start from ST head */
1457
199k
    ps_next_dpb = ps_dpb_mgr->ps_dpb_st_head;
1458
368k
    for(i = 0; i < ps_dpb_mgr->u1_num_st_ref_bufs; i++)
1459
169k
    {
1460
169k
        WORD32 i4_pic_num;
1461
1462
169k
        i4_ref_frame_num = ps_next_dpb->ps_pic_buf->i4_frame_num;
1463
169k
        if(i4_ref_frame_num > i4_cur_frame_num)
1464
42.7k
        {
1465
            /* RefPic Buf frame_num is before Current frame_num in decode order */
1466
42.7k
            i4_pic_num = i4_ref_frame_num - i4_max_frame_num;
1467
42.7k
        }
1468
126k
        else
1469
126k
        {
1470
            /* RefPic Buf frame_num is after Current frame_num in decode order */
1471
126k
            i4_pic_num = i4_ref_frame_num;
1472
126k
        }
1473
1474
169k
        ps_next_dpb->ps_pic_buf->i4_pic_num = i4_pic_num;
1475
169k
        ps_next_dpb->i4_frame_num = i4_pic_num;
1476
169k
        ps_next_dpb->ps_pic_buf->u1_long_term_frm_idx = MAX_REF_BUFS + 1;
1477
169k
        if(u1_fld_pic_flag)
1478
3.30k
        {
1479
            /* Assign the pic num to top fields and bot fields */
1480
1481
3.30k
            ps_next_dpb->s_top_field.i4_pic_num = i4_pic_num * 2
1482
3.30k
                            + !(ps_dec->ps_cur_slice->u1_bottom_field_flag);
1483
3.30k
            ps_next_dpb->s_bot_field.i4_pic_num = i4_pic_num * 2
1484
3.30k
                            + ps_dec->ps_cur_slice->u1_bottom_field_flag;
1485
3.30k
        }
1486
        /* Chase the next link */
1487
169k
        ps_next_dpb = ps_next_dpb->ps_prev_short;
1488
169k
    }
1489
1490
199k
    if(ps_dec->ps_cur_sps->u1_gaps_in_frame_num_value_allowed_flag
1491
1.67k
                    && ps_dpb_mgr->u1_num_gaps)
1492
1.06k
    {
1493
1.06k
        WORD32 i4_start_frm, i4_end_frm;
1494
        /* Assign pic numbers for gaps */
1495
19.2k
        for(i = 0; i < MAX_BUF_ID_MAP_ENTRIES; i++)
1496
18.1k
        {
1497
18.1k
            i4_start_frm = ps_dpb_mgr->ai4_gaps_start_frm_num[i];
1498
18.1k
            if(i4_start_frm != INVALID_FRAME_NUM)
1499
1.75k
            {
1500
1.75k
                if(i4_start_frm > i4_cur_frame_num)
1501
323
                {
1502
                    /* gap's frame_num is before Current frame_num in
1503
                     decode order */
1504
323
                    i4_start_frm -= i4_max_frame_num;
1505
323
                }
1506
1.75k
                ps_dpb_mgr->ai4_gaps_start_frm_num[i] = i4_start_frm;
1507
1.75k
                i4_end_frm = ps_dpb_mgr->ai4_gaps_end_frm_num[i];
1508
1509
1.75k
                if(i4_end_frm > i4_cur_frame_num)
1510
136
                {
1511
                    /* gap's frame_num is before Current frame_num in
1512
                     decode order */
1513
136
                    i4_end_frm -= i4_max_frame_num;
1514
136
                }
1515
1.75k
                ps_dpb_mgr->ai4_gaps_end_frm_num[i] = i4_end_frm;
1516
1.75k
            }
1517
18.1k
        }
1518
1.06k
    }
1519
199k
}
1520
1521
/*!
1522
 **************************************************************************
1523
 * \if Function name : ih264d_update_qp \endif
1524
 *
1525
 * \brief
1526
 *    Updates the values of QP and its related entities
1527
 *
1528
 * \return
1529
 *    0 on Success and Error code otherwise
1530
 *
1531
 **************************************************************************
1532
 */
1533
WORD32 ih264d_update_qp(dec_struct_t * ps_dec, const WORD8 i1_qp)
1534
971k
{
1535
971k
    WORD32 i_temp;
1536
971k
    i_temp = (ps_dec->u1_qp + i1_qp + 52) % 52;
1537
1538
971k
    if((i_temp < 0) || (i_temp > 51) || (i1_qp < -26) || (i1_qp > 25))
1539
0
        return ERROR_INV_RANGE_QP_T;
1540
1541
971k
    ps_dec->u1_qp = i_temp;
1542
971k
    ps_dec->u1_qp_y_rem6 = ps_dec->u1_qp % 6;
1543
971k
    ps_dec->u1_qp_y_div6 = ps_dec->u1_qp / 6;
1544
971k
    i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_chroma_qp_index_offset);
1545
971k
    ps_dec->u1_qp_u_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1546
971k
    ps_dec->u1_qp_u_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1547
1548
971k
    i_temp = CLIP3(0, 51, ps_dec->u1_qp + ps_dec->ps_cur_pps->i1_second_chroma_qp_index_offset);
1549
971k
    ps_dec->u1_qp_v_rem6 = MOD(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1550
971k
    ps_dec->u1_qp_v_div6 = DIV(gau1_ih264d_qp_scale_cr[12 + i_temp], 6);
1551
1552
971k
    ps_dec->pu2_quant_scale_y =
1553
971k
                    gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_y_rem6];
1554
971k
    ps_dec->pu2_quant_scale_u =
1555
971k
                    gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_u_rem6];
1556
971k
    ps_dec->pu2_quant_scale_v =
1557
971k
                    gau2_ih264_iquant_scale_4x4[ps_dec->u1_qp_v_rem6];
1558
971k
    return OK;
1559
971k
}
1560
1561
/*****************************************************************************/
1562
/*                                                                           */
1563
/*  Function Name : ih264d_decode_gaps_in_frame_num                                 */
1564
/*                                                                           */
1565
/*  Description   : This function decodes gaps in frame number               */
1566
/*                                                                           */
1567
/*  Inputs        : ps_dec          Decoder parameters                       */
1568
/*                  u2_frame_num   current frame number                     */
1569
/*                                                                           */
1570
/*  Globals       : None                                                     */
1571
/*  Processing    : This functionality needs to be implemented               */
1572
/*  Outputs       : None                                                     */
1573
/*  Returns       : None                                                     */
1574
/*                                                                           */
1575
/*  Issues        : Not implemented                                          */
1576
/*                                                                           */
1577
/*  Revision History:                                                        */
1578
/*                                                                           */
1579
/*         DD MM YYYY   Author(s)       Changes (Describe the changes made)  */
1580
/*         06 05 2002   NS              Draft                                */
1581
/*                                                                           */
1582
/*****************************************************************************/
1583
WORD32 ih264d_decode_gaps_in_frame_num(dec_struct_t *ps_dec,
1584
                                       UWORD16 u2_frame_num)
1585
2.14k
{
1586
2.14k
    UWORD32 u4_next_frm_num, u4_start_frm_num;
1587
2.14k
    UWORD32 u4_max_frm_num;
1588
2.14k
    pocstruct_t s_tmp_poc;
1589
2.14k
    WORD32 i4_poc;
1590
2.14k
    dec_slice_params_t *ps_cur_slice;
1591
1592
2.14k
    dec_pic_params_t *ps_pic_params;
1593
2.14k
    WORD8 i1_gap_idx;
1594
2.14k
    WORD32 *i4_gaps_start_frm_num;
1595
2.14k
    dpb_manager_t *ps_dpb_mgr;
1596
2.14k
    WORD32 i4_frame_gaps;
1597
2.14k
    WORD8 *pi1_gaps_per_seq;
1598
2.14k
    WORD32 ret;
1599
1600
2.14k
    ps_cur_slice = ps_dec->ps_cur_slice;
1601
2.14k
    if(ps_cur_slice->u1_field_pic_flag)
1602
750
    {
1603
750
        if(ps_dec->u2_prev_ref_frame_num == u2_frame_num)
1604
164
            return 0;
1605
750
    }
1606
1.98k
    ps_pic_params = ps_dec->ps_cur_pps;
1607
1608
1.98k
    u4_next_frm_num = ps_dec->u2_prev_ref_frame_num + 1;
1609
1.98k
    u4_max_frm_num = ps_pic_params->ps_sps->u2_u4_max_pic_num_minus1 + 1;
1610
1611
    // check
1612
1.98k
    if(u4_next_frm_num >= u4_max_frm_num)
1613
12
    {
1614
12
        u4_next_frm_num -= u4_max_frm_num;
1615
12
    }
1616
1617
1.98k
    if(u4_next_frm_num == u2_frame_num)
1618
151
    {
1619
151
        return (0);
1620
151
    }
1621
1622
    // check
1623
1.83k
    if((ps_dec->u1_nal_unit_type == IDR_SLICE_NAL)
1624
732
                    && (u4_next_frm_num >= u2_frame_num))
1625
4
    {
1626
4
        return (0);
1627
4
    }
1628
1.83k
    u4_start_frm_num = u4_next_frm_num;
1629
1630
1.83k
    s_tmp_poc.i4_pic_order_cnt_lsb = 0;
1631
1.83k
    s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0;
1632
1.83k
    s_tmp_poc.i4_pic_order_cnt_lsb = 0;
1633
1.83k
    s_tmp_poc.i4_delta_pic_order_cnt_bottom = 0;
1634
1.83k
    s_tmp_poc.i4_delta_pic_order_cnt[0] = 0;
1635
1.83k
    s_tmp_poc.i4_delta_pic_order_cnt[1] = 0;
1636
1637
1.83k
    ps_cur_slice = ps_dec->ps_cur_slice;
1638
1639
1.83k
    i4_frame_gaps = 0;
1640
1.83k
    ps_dpb_mgr = ps_dec->ps_dpb_mgr;
1641
1642
    /* Find a empty slot to store gap seqn info */
1643
1.83k
    i4_gaps_start_frm_num = ps_dpb_mgr->ai4_gaps_start_frm_num;
1644
8.03k
    for(i1_gap_idx = 0; i1_gap_idx < MAX_BUF_ID_MAP_ENTRIES; i1_gap_idx++)
1645
7.79k
    {
1646
7.79k
        if(INVALID_FRAME_NUM == i4_gaps_start_frm_num[i1_gap_idx])
1647
1.59k
            break;
1648
7.79k
    }
1649
1.83k
    if(MAX_BUF_ID_MAP_ENTRIES == i1_gap_idx)
1650
240
    {
1651
240
        UWORD32 i4_error_code;
1652
240
        i4_error_code = ERROR_DBP_MANAGER_T;
1653
//          i4_error_code |= 1<<IVD_CORRUPTEDDATA;
1654
240
        return i4_error_code;
1655
240
    }
1656
1657
1.59k
    i4_poc = 0;
1658
1.59k
    i4_gaps_start_frm_num[i1_gap_idx] = u4_start_frm_num;
1659
1.59k
    ps_dpb_mgr->ai4_gaps_end_frm_num[i1_gap_idx] = u2_frame_num - 1;
1660
1.59k
    pi1_gaps_per_seq = ps_dpb_mgr->ai1_gaps_per_seq;
1661
1.59k
    pi1_gaps_per_seq[i1_gap_idx] = 0;
1662
2.36M
    while(u4_next_frm_num != u2_frame_num)
1663
2.36M
    {
1664
2.36M
        ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1665
2.36M
        if(ps_pic_params->ps_sps->u1_pic_order_cnt_type)
1666
2.35M
        {
1667
            /* allocate a picture buffer and insert it as ST node */
1668
2.35M
            ret = ih264d_decode_pic_order_cnt(0, u4_next_frm_num,
1669
2.35M
                                              &ps_dec->s_prev_pic_poc,
1670
2.35M
                                              &s_tmp_poc, ps_cur_slice,
1671
2.35M
                                              ps_pic_params, 1, 0, 0,
1672
2.35M
                                              &i4_poc);
1673
2.35M
            if(ret != OK)
1674
136
                return ret;
1675
1676
            /* Display seq no calculations */
1677
2.35M
            if(i4_poc >= ps_dec->i4_max_poc)
1678
1.38k
                ps_dec->i4_max_poc = i4_poc;
1679
            /* IDR Picture or POC wrap around */
1680
2.35M
            if(i4_poc == 0)
1681
63
            {
1682
63
                WORD64 i8_temp;
1683
63
                i8_temp = (WORD64)ps_dec->i4_prev_max_display_seq
1684
63
                          + ps_dec->i4_max_poc
1685
63
                          + ps_dec->u1_max_dec_frame_buffering + 1;
1686
                /*If i4_prev_max_display_seq overflows integer range, reset it */
1687
63
                ps_dec->i4_prev_max_display_seq = IS_OUT_OF_RANGE_S32(i8_temp)?
1688
38
                                                  0 : i8_temp;
1689
63
                ps_dec->i4_max_poc = 0;
1690
63
            }
1691
1692
2.35M
            ps_cur_slice->u1_mmco_equalto5 = 0;
1693
2.35M
            ps_cur_slice->u2_frame_num = u4_next_frm_num;
1694
2.35M
        }
1695
1696
        // check
1697
2.36M
        if(ps_dpb_mgr->i1_poc_buf_id_entries
1698
2.36M
                        >= ps_dec->u1_max_dec_frame_buffering)
1699
114
        {
1700
114
            ret = ih264d_assign_display_seq(ps_dec);
1701
114
            if(ret != OK)
1702
0
                return ret;
1703
114
        }
1704
1705
2.36M
        {
1706
2.36M
            WORD64 i8_display_poc;
1707
2.36M
            i8_display_poc = (WORD64)ps_dec->i4_prev_max_display_seq +
1708
2.36M
                        i4_poc;
1709
2.36M
            if(IS_OUT_OF_RANGE_S32(i8_display_poc))
1710
30
            {
1711
30
                ps_dec->i4_prev_max_display_seq = 0;
1712
30
            }
1713
2.36M
        }
1714
2.36M
        ret = ih264d_insert_pic_in_display_list(
1715
2.36M
                        ps_dec->ps_dpb_mgr, (WORD8) DO_NOT_DISP,
1716
2.36M
                        (WORD32)(ps_dec->i4_prev_max_display_seq + i4_poc),
1717
2.36M
                        u4_next_frm_num);
1718
2.36M
        if(ret != OK)
1719
11
            return ret;
1720
1721
2.36M
        pi1_gaps_per_seq[i1_gap_idx]++;
1722
2.36M
        ret = ih264d_do_mmco_for_gaps(ps_dpb_mgr,
1723
2.36M
                                ps_dec->ps_cur_sps->u1_num_ref_frames);
1724
2.36M
        if(ret != OK)
1725
396
            return ret;
1726
1727
2.36M
        ih264d_delete_nonref_nondisplay_pics(ps_dpb_mgr);
1728
1729
2.36M
        u4_next_frm_num++;
1730
2.36M
        if(u4_next_frm_num >= u4_max_frm_num)
1731
109
        {
1732
109
            u4_next_frm_num -= u4_max_frm_num;
1733
109
        }
1734
1735
2.36M
        i4_frame_gaps++;
1736
2.36M
    }
1737
1738
1.04k
    return OK;
1739
1.59k
}
1740
1741
/*!
1742
 **************************************************************************
1743
 * \if Function name : ih264d_create_pic_buffers \endif
1744
 *
1745
 * \brief
1746
 *    This function creates Picture Buffers.
1747
 *
1748
 * \return
1749
 *    0 on Success and -1 on error
1750
 **************************************************************************
1751
 */
1752
WORD32 ih264d_create_pic_buffers(UWORD8 u1_num_of_buf,
1753
                               dec_struct_t *ps_dec)
1754
21.5k
{
1755
21.5k
    struct pic_buffer_t *ps_pic_buf;
1756
21.5k
    UWORD8 i;
1757
21.5k
    UWORD32 u4_luma_size, u4_chroma_size;
1758
21.5k
    UWORD8 u1_frm = ps_dec->ps_cur_sps->u1_frame_mbs_only_flag;
1759
21.5k
    WORD32 j;
1760
21.5k
    UWORD8 *pu1_buf;
1761
1762
21.5k
    ps_pic_buf = ps_dec->ps_pic_buf_base;
1763
21.5k
    ih264_disp_mgr_init((disp_mgr_t *)ps_dec->pv_disp_buf_mgr);
1764
21.5k
    ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_pic_buf_mgr);
1765
21.5k
    u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y;
1766
21.5k
    u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv;
1767
1768
21.5k
    {
1769
21.5k
        if(ps_dec->u4_share_disp_buf == 1)
1770
0
        {
1771
            /* In case of buffers getting shared between application and library
1772
             there is no need of reference memtabs. Instead of setting the i4_size
1773
             to zero, it is reduced to a small i4_size to ensure that changes
1774
             in the code are minimal */
1775
0
            if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
1776
0
                            || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)
1777
0
                            || (ps_dec->u1_chroma_format == IV_YUV_420P))
1778
0
            {
1779
0
                u4_luma_size = 64;
1780
0
            }
1781
1782
0
            if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
1783
0
            {
1784
0
                u4_chroma_size = 64;
1785
0
            }
1786
1787
0
        }
1788
21.5k
    }
1789
1790
21.5k
    pu1_buf = ps_dec->pu1_pic_buf_base;
1791
1792
    /* Allocate memory for refernce buffers */
1793
397k
    for(i = 0; i < u1_num_of_buf; i++)
1794
375k
    {
1795
375k
        UWORD32 u4_offset;
1796
375k
        WORD32 buf_ret;
1797
375k
        UWORD8 *pu1_luma, *pu1_chroma;
1798
375k
        void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
1799
1800
375k
        pu1_luma = pu1_buf;
1801
375k
        pu1_buf += ALIGN64(u4_luma_size);
1802
375k
        pu1_chroma = pu1_buf;
1803
375k
        pu1_buf += ALIGN64(u4_chroma_size);
1804
1805
        /* Offset to the start of the pic from the top left corner of the frame
1806
         buffer */
1807
1808
375k
        if((0 == ps_dec->u4_share_disp_buf)
1809
0
                        || (NULL == ps_dec->disp_bufs[i].buf[0]))
1810
375k
        {
1811
375k
            UWORD32 pad_len_h, pad_len_v;
1812
1813
375k
            u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H;
1814
375k
            ps_pic_buf->pu1_buf1 = (UWORD8 *)(pu1_luma) + u4_offset;
1815
1816
375k
            pad_len_h = MAX(PAD_LEN_UV_H, (PAD_LEN_Y_H >> 1));
1817
375k
            pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1818
1819
375k
            u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1820
1821
375k
            ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset;
1822
375k
            ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset;
1823
1824
375k
        }
1825
0
        else
1826
0
        {
1827
0
            UWORD32 pad_len_h, pad_len_v;
1828
0
            u4_offset = ps_dec->u2_frm_wd_y * (PAD_LEN_Y_V << 1) + PAD_LEN_Y_H;
1829
0
            ps_pic_buf->pu1_buf1 = (UWORD8 *)ps_dec->disp_bufs[i].buf[0]
1830
0
                            + u4_offset;
1831
1832
0
            ps_dec->disp_bufs[i].u4_ofst[0] = u4_offset;
1833
1834
0
            if(ps_dec->u1_chroma_format == IV_YUV_420P)
1835
0
            {
1836
0
                pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR,
1837
0
                                (PAD_LEN_Y_H >> 1));
1838
0
                pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1839
1840
0
                u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1841
0
                ps_pic_buf->pu1_buf2 = (UWORD8 *)(pu1_chroma) + u4_offset;
1842
0
                ps_pic_buf->pu1_buf3 = (UWORD8 *)(NULL) + u4_offset;
1843
1844
0
                ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset;
1845
0
                ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset;
1846
1847
0
            }
1848
0
            else
1849
0
            {
1850
0
                pad_len_h = MAX(PAD_LEN_UV_H * YUV420SP_FACTOR,
1851
0
                                (PAD_LEN_Y_H >> 1));
1852
0
                pad_len_v = MAX(PAD_LEN_UV_V, PAD_LEN_Y_V);
1853
1854
0
                u4_offset = ps_dec->u2_frm_wd_uv * pad_len_v + pad_len_h;
1855
0
                ps_pic_buf->pu1_buf2 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1])
1856
0
                                + u4_offset;
1857
0
                ps_pic_buf->pu1_buf3 = (UWORD8 *)(ps_dec->disp_bufs[i].buf[1])
1858
0
                                + u4_offset;
1859
1860
0
                ps_dec->disp_bufs[i].u4_ofst[1] = u4_offset;
1861
0
                ps_dec->disp_bufs[i].u4_ofst[2] = u4_offset;
1862
0
            }
1863
0
        }
1864
1865
375k
        ps_pic_buf->u2_frm_ht_y = ps_dec->u2_frm_ht_y;
1866
375k
        ps_pic_buf->u2_frm_ht_uv = ps_dec->u2_frm_ht_uv;
1867
375k
        ps_pic_buf->u2_frm_wd_y = ps_dec->u2_frm_wd_y;
1868
375k
        ps_pic_buf->u2_frm_wd_uv = ps_dec->u2_frm_wd_uv;
1869
1870
375k
        ps_pic_buf->u1_pic_buf_id = i;
1871
1872
375k
        buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_pic_buf_mgr,
1873
375k
                                    ps_pic_buf, i);
1874
375k
        if(0 != buf_ret)
1875
0
        {
1876
0
            ps_dec->i4_error_code = ERROR_BUF_MGR;
1877
0
            return ERROR_BUF_MGR;
1878
0
        }
1879
1880
375k
        ps_dec->apv_buf_id_pic_buf_map[i] = (void *)ps_pic_buf;
1881
375k
        ps_pic_buf++;
1882
375k
    }
1883
1884
21.5k
    if(1 == ps_dec->u4_share_disp_buf)
1885
0
    {
1886
0
        for(i = 0; i < u1_num_of_buf; i++)
1887
0
            ps_dec->u4_disp_buf_mapping[i] = 1;
1888
0
    }
1889
21.5k
    return OK;
1890
21.5k
}
1891
1892
/*!
1893
 **************************************************************************
1894
 * \if Function name : ih264d_allocate_dynamic_bufs \endif
1895
 *
1896
 * \brief
1897
 *    This function allocates memory required by Decoder.
1898
 *
1899
 * \param ps_dec: Pointer to dec_struct_t.
1900
 *
1901
 * \return
1902
 *    Returns i4_status as returned by MemManager.
1903
 *
1904
 **************************************************************************
1905
 */
1906
WORD16 ih264d_allocate_dynamic_bufs(dec_struct_t * ps_dec)
1907
21.5k
{
1908
21.5k
    struct MemReq s_MemReq;
1909
21.5k
    struct MemBlock *p_MemBlock;
1910
1911
21.5k
    pred_info_t *ps_pred_frame;
1912
21.5k
    dec_mb_info_t *ps_frm_mb_info;
1913
21.5k
    dec_slice_struct_t *ps_dec_slice_buf;
1914
21.5k
    UWORD8 *pu1_dec_mb_map, *pu1_recon_mb_map;
1915
21.5k
    UWORD16 *pu2_slice_num_map;
1916
1917
21.5k
    WORD16 *pi16_res_coeff;
1918
21.5k
    WORD16 i16_status = 0;
1919
21.5k
    UWORD8 uc_frmOrFld = (1 - ps_dec->ps_cur_sps->u1_frame_mbs_only_flag);
1920
21.5k
    UWORD16 u4_luma_wd = ps_dec->u2_frm_wd_y;
1921
21.5k
    UWORD16 u4_chroma_wd = ps_dec->u2_frm_wd_uv;
1922
21.5k
    WORD8 c_i = 0;
1923
21.5k
    dec_seq_params_t *ps_sps = ps_dec->ps_cur_sps;
1924
21.5k
    UWORD32 u4_total_mbs = ps_sps->u4_total_num_of_mbs << uc_frmOrFld;
1925
21.5k
    UWORD32 u4_wd_mbs = ps_dec->u2_frm_wd_in_mbs;
1926
21.5k
    UWORD32 u4_ht_mbs = ps_dec->u2_frm_ht_in_mbs;
1927
21.5k
    UWORD32 u4_blk_wd;
1928
21.5k
    UWORD32 ui_size = 0;
1929
21.5k
    UWORD32 u4_int_scratch_size = 0, u4_ref_pred_size = 0;
1930
21.5k
    UWORD8 *pu1_buf;
1931
21.5k
    WORD32 num_entries;
1932
21.5k
    WORD32 size;
1933
21.5k
    void *pv_buf;
1934
21.5k
    UWORD32 u4_num_bufs;
1935
21.5k
    UWORD32 u4_luma_size, u4_chroma_size;
1936
21.5k
    void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
1937
1938
    /* Free any dynamic buffers that are allocated earlier. As ps_dec is memset to zero  */
1939
    /* at the beginning, it is safe to call this even if no memory was allocated earlier */
1940
21.5k
    ih264d_free_dynamic_bufs(ps_dec);
1941
1942
21.5k
    size = u4_total_mbs;
1943
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1944
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1945
21.5k
    memset(pv_buf, 0, size);
1946
21.5k
    ps_dec->pu1_dec_mb_map = pv_buf;
1947
1948
21.5k
    size = u4_total_mbs;
1949
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1950
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1951
21.5k
    memset(pv_buf, 0, size);
1952
21.5k
    ps_dec->pu1_recon_mb_map = pv_buf;
1953
1954
21.5k
    size = u4_total_mbs * sizeof(UWORD16);
1955
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1956
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1957
21.5k
    memset(pv_buf, 0, size);
1958
21.5k
    ps_dec->pu2_slice_num_map = pv_buf;
1959
1960
    /************************************************************/
1961
    /* Post allocation Initialisations                          */
1962
    /************************************************************/
1963
21.5k
    ps_dec->ps_parse_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
1964
21.5k
    ps_dec->ps_decode_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
1965
21.5k
    ps_dec->ps_computebs_cur_slice = &(ps_dec->ps_dec_slice_buf[0]);
1966
1967
21.5k
    ps_dec->ps_pred_start = ps_dec->ps_pred;
1968
1969
21.5k
    size = sizeof(parse_pmbarams_t) * (ps_dec->u4_recon_mb_grp);
1970
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1971
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1972
21.5k
    memset(pv_buf, 0, size);
1973
21.5k
    ps_dec->ps_parse_mb_data = pv_buf;
1974
1975
21.5k
    size = sizeof(parse_part_params_t)
1976
21.5k
                        * ((ps_dec->u4_recon_mb_grp) << 4);
1977
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1978
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1979
21.5k
    memset(pv_buf, 0, size);
1980
21.5k
    ps_dec->ps_parse_part_params = pv_buf;
1981
1982
21.5k
    size = ((u4_wd_mbs * sizeof(deblkmb_neighbour_t)) << uc_frmOrFld);
1983
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1984
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1985
21.5k
    memset(pv_buf, 0, size);
1986
21.5k
    ps_dec->ps_deblk_top_mb = pv_buf;
1987
1988
21.5k
    size = ((sizeof(ctxt_inc_mb_info_t))
1989
21.5k
                        * (((u4_wd_mbs + 1) << uc_frmOrFld) + 1));
1990
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
1991
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
1992
21.5k
    memset(pv_buf, 0, size);
1993
21.5k
    ps_dec->p_ctxt_inc_mb_map = pv_buf;
1994
1995
    /* 0th entry of CtxtIncMbMap will be always be containing default values
1996
     for CABAC context representing MB not available */
1997
21.5k
    ps_dec->p_ctxt_inc_mb_map += 1;
1998
1999
21.5k
    size = (sizeof(mv_pred_t) * ps_dec->u4_recon_mb_grp
2000
21.5k
                        * 16);
2001
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2002
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2003
21.5k
    memset(pv_buf, 0, size);
2004
21.5k
    ps_dec->ps_mv_p[0] = pv_buf;
2005
2006
21.5k
    size = (sizeof(mv_pred_t) * ps_dec->u4_recon_mb_grp
2007
21.5k
                        * 16);
2008
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2009
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2010
21.5k
    memset(pv_buf, 0, size);
2011
21.5k
    ps_dec->ps_mv_p[1] = pv_buf;
2012
2013
21.5k
    {
2014
21.5k
        UWORD8 i;
2015
107k
        for(i = 0; i < MV_SCRATCH_BUFS; i++)
2016
86.2k
        {
2017
86.2k
            size = (sizeof(mv_pred_t)
2018
86.2k
                            * ps_dec->u4_recon_mb_grp * 4);
2019
86.2k
            pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2020
86.2k
            RETURN_IF((NULL == pv_buf), IV_FAIL);
2021
86.2k
            memset(pv_buf, 0, size);
2022
86.2k
            ps_dec->ps_mv_top_p[i] = pv_buf;
2023
86.2k
        }
2024
21.5k
    }
2025
2026
21.5k
    size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
2027
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2028
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2029
21.5k
    ps_dec->pu1_y_intra_pred_line = pv_buf;
2030
21.5k
    memset(ps_dec->pu1_y_intra_pred_line, 0, size);
2031
21.5k
    ps_dec->pu1_y_intra_pred_line += MB_SIZE;
2032
2033
21.5k
    size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
2034
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2035
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2036
21.5k
    ps_dec->pu1_u_intra_pred_line = pv_buf;
2037
21.5k
    memset(ps_dec->pu1_u_intra_pred_line, 0, size);
2038
21.5k
    ps_dec->pu1_u_intra_pred_line += MB_SIZE;
2039
2040
21.5k
    size = sizeof(UWORD8) * ((u4_wd_mbs + 2) * MB_SIZE) * 2;
2041
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2042
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2043
21.5k
    ps_dec->pu1_v_intra_pred_line = pv_buf;
2044
21.5k
    memset(ps_dec->pu1_v_intra_pred_line, 0, size);
2045
21.5k
    ps_dec->pu1_v_intra_pred_line += MB_SIZE;
2046
2047
21.5k
    if(ps_dec->u1_separate_parse)
2048
6.42k
    {
2049
        /* Needs one extra row of info, to hold top row data */
2050
6.42k
        size = sizeof(mb_neigbour_params_t)
2051
6.42k
                        * 2 * ((u4_wd_mbs + 2) * (u4_ht_mbs + 1));
2052
6.42k
    }
2053
15.1k
    else
2054
15.1k
    {
2055
15.1k
        size = sizeof(mb_neigbour_params_t)
2056
15.1k
                        * 2 * ((u4_wd_mbs + 2) << uc_frmOrFld);
2057
15.1k
    }
2058
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2059
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2060
2061
21.5k
    ps_dec->ps_nbr_mb_row = pv_buf;
2062
21.5k
    memset(ps_dec->ps_nbr_mb_row, 0, size);
2063
2064
    /* Allocate deblock MB info */
2065
21.5k
    size = (u4_total_mbs + u4_wd_mbs) * sizeof(deblk_mb_t);
2066
2067
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2068
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2069
21.5k
    ps_dec->ps_deblk_pic = pv_buf;
2070
2071
21.5k
    memset(ps_dec->ps_deblk_pic, 0, size);
2072
2073
    /* Allocate frame level mb info */
2074
21.5k
    size = sizeof(dec_mb_info_t) * u4_total_mbs;
2075
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2076
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2077
21.5k
    ps_dec->ps_frm_mb_info = pv_buf;
2078
21.5k
    memset(ps_dec->ps_frm_mb_info, 0, size);
2079
2080
    /* Allocate memory for slice headers dec_slice_struct_t */
2081
21.5k
    num_entries = MAX_FRAMES;
2082
21.5k
    if((1 >= ps_dec->ps_cur_sps->u1_num_ref_frames) &&
2083
16.5k
        (0 == ps_dec->i4_display_delay))
2084
0
    {
2085
0
        num_entries = 1;
2086
0
    }
2087
21.5k
    num_entries = ((2 * num_entries) + 1);
2088
21.5k
    num_entries *= 2;
2089
2090
21.5k
    size = num_entries * sizeof(void *);
2091
21.5k
    size += PAD_MAP_IDX_POC * sizeof(void *);
2092
21.5k
    size *= u4_total_mbs;
2093
21.5k
    size += sizeof(dec_slice_struct_t) * u4_total_mbs;
2094
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2095
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2096
2097
21.5k
    ps_dec->ps_dec_slice_buf = pv_buf;
2098
21.5k
    memset(ps_dec->ps_dec_slice_buf, 0, size);
2099
21.5k
    pu1_buf = (UWORD8 *)ps_dec->ps_dec_slice_buf;
2100
21.5k
    pu1_buf += sizeof(dec_slice_struct_t) * u4_total_mbs;
2101
21.5k
    ps_dec->pv_map_ref_idx_to_poc_buf = (void *)pu1_buf;
2102
2103
    /* Allocate memory for packed pred info */
2104
21.5k
    num_entries = u4_total_mbs;
2105
21.5k
    num_entries *= 16 * 2;
2106
2107
21.5k
    size = sizeof(pred_info_pkd_t) * num_entries;
2108
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2109
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2110
21.5k
    memset(pv_buf, 0, size);
2111
21.5k
    ps_dec->ps_pred_pkd = pv_buf;
2112
2113
    /* Allocate memory for coeff data */
2114
21.5k
    size = MB_LUM_SIZE * sizeof(WORD16);
2115
    /*For I16x16 MBs, 16 4x4 AC coeffs and 1 4x4 DC coeff TU blocks will be sent
2116
    For all MBs along with 8 4x4 AC coeffs 2 2x2 DC coeff TU blocks will be sent
2117
    So use 17 4x4 TU blocks for luma and 9 4x4 TU blocks for chroma */
2118
21.5k
    size += u4_total_mbs * (MAX(17 * sizeof(tu_sblk4x4_coeff_data_t),4 * sizeof(tu_blk8x8_coeff_data_t))
2119
21.5k
                                            + 9 * sizeof(tu_sblk4x4_coeff_data_t));
2120
    //32 bytes for each mb to store u1_prev_intra4x4_pred_mode and u1_rem_intra4x4_pred_mode data
2121
21.5k
    size += u4_total_mbs * 32;
2122
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2123
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2124
21.5k
    memset(pv_buf, 0, size);
2125
2126
21.5k
    ps_dec->pi2_coeff_data = pv_buf;
2127
2128
21.5k
    ps_dec->pv_pic_tu_coeff_data = (void *)(ps_dec->pi2_coeff_data + MB_LUM_SIZE);
2129
2130
    /* Allocate MV bank buffer */
2131
21.5k
    {
2132
21.5k
        UWORD32 col_flag_buffer_size, mvpred_buffer_size;
2133
21.5k
        UWORD8 u1_num_ref_frames = ps_dec->u4_thumbnail_mode ?
2134
0
                        !ps_dec->ps_cur_sps->u1_frame_mbs_only_flag :
2135
21.5k
                        ps_dec->ps_cur_sps->u1_num_ref_frames;
2136
2137
21.5k
        col_flag_buffer_size = ((ps_dec->u2_pic_wd * ps_dec->u2_pic_ht) >> 4);
2138
21.5k
        mvpred_buffer_size = sizeof(mv_pred_t)
2139
21.5k
                        * ((ps_dec->u2_pic_wd * (ps_dec->u2_pic_ht + PAD_MV_BANK_ROW)) >> 4);
2140
2141
21.5k
        u4_num_bufs = u1_num_ref_frames + 1;
2142
2143
21.5k
        u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs);
2144
21.5k
        if(!ps_dec->u4_thumbnail_mode)
2145
21.5k
        {
2146
21.5k
            u4_num_bufs = MAX(u4_num_bufs, 2);
2147
21.5k
        }
2148
21.5k
        size = ALIGN64(mvpred_buffer_size) + ALIGN64(col_flag_buffer_size);
2149
21.5k
        size *= u4_num_bufs;
2150
21.5k
        pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2151
21.5k
        RETURN_IF((NULL == pv_buf), IV_FAIL);
2152
21.5k
        memset(pv_buf, 0, size);
2153
21.5k
        ps_dec->pu1_mv_bank_buf_base = pv_buf;
2154
21.5k
    }
2155
2156
    /* Allocate Pic buffer */
2157
0
    u4_luma_size = ps_dec->u2_frm_wd_y * ps_dec->u2_frm_ht_y;
2158
21.5k
    u4_chroma_size = ps_dec->u2_frm_wd_uv * ps_dec->u2_frm_ht_uv;
2159
2160
21.5k
    {
2161
21.5k
        if(ps_dec->u4_share_disp_buf == 1)
2162
0
        {
2163
            /* In case of buffers getting shared between application and library
2164
             there is no need of reference memtabs. Instead of setting the i4_size
2165
             to zero, it is reduced to a small i4_size to ensure that changes
2166
             in the code are minimal */
2167
0
            if((ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
2168
0
                            || (ps_dec->u1_chroma_format == IV_YUV_420SP_VU)
2169
0
                            || (ps_dec->u1_chroma_format == IV_YUV_420P))
2170
0
            {
2171
0
                u4_luma_size = 64;
2172
0
            }
2173
2174
0
            if(ps_dec->u1_chroma_format == IV_YUV_420SP_UV)
2175
0
            {
2176
0
                u4_chroma_size = 64;
2177
0
            }
2178
2179
0
        }
2180
21.5k
    }
2181
2182
21.5k
    size = ALIGN64(u4_luma_size) + ALIGN64(u4_chroma_size);
2183
21.5k
    size *= ps_dec->u1_pic_bufs;
2184
21.5k
    pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2185
21.5k
    RETURN_IF((NULL == pv_buf), IV_FAIL);
2186
21.5k
    memset(pv_buf, 0, size);
2187
21.5k
    ps_dec->pu1_pic_buf_base = pv_buf;
2188
2189
    /* Allocate memory for mb_info maps */
2190
21.5k
    if(ps_dec->u1_enable_mb_info)
2191
0
    {
2192
0
        size = (u4_total_mbs << 2) * MAX_DISP_BUFS_NEW;
2193
2194
0
        pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2195
0
        RETURN_IF((NULL == pv_buf), IV_FAIL);
2196
0
        memset(pv_buf, 0, size);
2197
0
        ps_dec->pu1_qp_map_base = pv_buf;
2198
2199
0
        pv_buf = ps_dec->pf_aligned_alloc(pv_mem_ctxt, 128, size);
2200
0
        RETURN_IF((NULL == pv_buf), IV_FAIL);
2201
0
        memset(pv_buf, 0, size);
2202
0
        ps_dec->pu1_mb_type_map_base = pv_buf;
2203
0
    }
2204
2205
    /* Post allocation Increment Actions */
2206
2207
    /***************************************************************************/
2208
    /*Initialize cabac context pointers for every SE that has fixed contextIdx */
2209
    /***************************************************************************/
2210
21.5k
    {
2211
21.5k
        bin_ctxt_model_t * const p_cabac_ctxt_table_t =
2212
21.5k
                        ps_dec->p_cabac_ctxt_table_t;
2213
21.5k
        bin_ctxt_model_t * * p_coeff_abs_level_minus1_t =
2214
21.5k
                        ps_dec->p_coeff_abs_level_minus1_t;
2215
21.5k
        bin_ctxt_model_t * * p_cbf_t = ps_dec->p_cbf_t;
2216
2217
21.5k
        ps_dec->p_mb_field_dec_flag_t = p_cabac_ctxt_table_t
2218
21.5k
                        + MB_FIELD_DECODING_FLAG;
2219
21.5k
        ps_dec->p_prev_intra4x4_pred_mode_flag_t = p_cabac_ctxt_table_t
2220
21.5k
                        + PREV_INTRA4X4_PRED_MODE_FLAG;
2221
21.5k
        ps_dec->p_rem_intra4x4_pred_mode_t = p_cabac_ctxt_table_t
2222
21.5k
                        + REM_INTRA4X4_PRED_MODE;
2223
21.5k
        ps_dec->p_intra_chroma_pred_mode_t = p_cabac_ctxt_table_t
2224
21.5k
                        + INTRA_CHROMA_PRED_MODE;
2225
21.5k
        ps_dec->p_mb_qp_delta_t = p_cabac_ctxt_table_t + MB_QP_DELTA;
2226
21.5k
        ps_dec->p_ref_idx_t = p_cabac_ctxt_table_t + REF_IDX;
2227
21.5k
        ps_dec->p_mvd_x_t = p_cabac_ctxt_table_t + MVD_X;
2228
21.5k
        ps_dec->p_mvd_y_t = p_cabac_ctxt_table_t + MVD_Y;
2229
21.5k
        p_cbf_t[0] = p_cabac_ctxt_table_t + CBF + 0;
2230
21.5k
        p_cbf_t[1] = p_cabac_ctxt_table_t + CBF + 4;
2231
21.5k
        p_cbf_t[2] = p_cabac_ctxt_table_t + CBF + 8;
2232
21.5k
        p_cbf_t[3] = p_cabac_ctxt_table_t + CBF + 12;
2233
21.5k
        p_cbf_t[4] = p_cabac_ctxt_table_t + CBF + 16;
2234
21.5k
        ps_dec->p_cbp_luma_t = p_cabac_ctxt_table_t + CBP_LUMA;
2235
21.5k
        ps_dec->p_cbp_chroma_t = p_cabac_ctxt_table_t + CBP_CHROMA;
2236
2237
21.5k
        p_coeff_abs_level_minus1_t[LUMA_DC_CTXCAT] = p_cabac_ctxt_table_t
2238
21.5k
                        + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_0_OFFSET;
2239
2240
21.5k
        p_coeff_abs_level_minus1_t[LUMA_AC_CTXCAT] = p_cabac_ctxt_table_t
2241
21.5k
                        + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_1_OFFSET;
2242
2243
21.5k
        p_coeff_abs_level_minus1_t[LUMA_4X4_CTXCAT] = p_cabac_ctxt_table_t
2244
21.5k
                        + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_2_OFFSET;
2245
2246
21.5k
        p_coeff_abs_level_minus1_t[CHROMA_DC_CTXCAT] = p_cabac_ctxt_table_t
2247
21.5k
                        + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_3_OFFSET;
2248
2249
21.5k
        p_coeff_abs_level_minus1_t[CHROMA_AC_CTXCAT] = p_cabac_ctxt_table_t
2250
21.5k
                        + COEFF_ABS_LEVEL_MINUS1 + COEFF_ABS_LEVEL_CAT_4_OFFSET;
2251
2252
21.5k
        p_coeff_abs_level_minus1_t[LUMA_8X8_CTXCAT] = p_cabac_ctxt_table_t
2253
21.5k
                        + COEFF_ABS_LEVEL_MINUS1_8X8
2254
21.5k
                        + COEFF_ABS_LEVEL_CAT_5_OFFSET;
2255
2256
        /********************************************************/
2257
        /* context for the high profile related syntax elements */
2258
        /* This is maintained seperately in s_high_profile     */
2259
        /********************************************************/
2260
21.5k
        {
2261
2262
21.5k
            ps_dec->s_high_profile.ps_transform8x8_flag = p_cabac_ctxt_table_t
2263
21.5k
                            + TRANSFORM_SIZE_8X8_FLAG;
2264
2265
21.5k
            ps_dec->s_high_profile.ps_sigcoeff_8x8_frame = p_cabac_ctxt_table_t
2266
21.5k
                            + SIGNIFICANT_COEFF_FLAG_8X8_FRAME;
2267
2268
21.5k
            ps_dec->s_high_profile.ps_last_sigcoeff_8x8_frame =
2269
21.5k
                            p_cabac_ctxt_table_t
2270
21.5k
                                            + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FRAME;
2271
2272
21.5k
            ps_dec->s_high_profile.ps_coeff_abs_levelminus1 =
2273
21.5k
                            p_cabac_ctxt_table_t + COEFF_ABS_LEVEL_MINUS1_8X8;
2274
2275
21.5k
            ps_dec->s_high_profile.ps_sigcoeff_8x8_field = p_cabac_ctxt_table_t
2276
21.5k
                            + SIGNIFICANT_COEFF_FLAG_8X8_FIELD;
2277
2278
21.5k
            ps_dec->s_high_profile.ps_last_sigcoeff_8x8_field =
2279
21.5k
                            p_cabac_ctxt_table_t
2280
21.5k
                                            + LAST_SIGNIFICANT_COEFF_FLAG_8X8_FIELD;
2281
21.5k
        }
2282
21.5k
    }
2283
21.5k
    return (i16_status);
2284
21.5k
}
2285
2286
/*!
2287
 **************************************************************************
2288
 * \if Function name : ih264d_free_dynamic_bufs \endif
2289
 *
2290
 * \brief
2291
 *    This function frees dynamic memory allocated by Decoder.
2292
 *
2293
 * \param ps_dec: Pointer to dec_struct_t.
2294
 *
2295
 * \return
2296
 *    Returns i4_status as returned by MemManager.
2297
 *
2298
 **************************************************************************
2299
 */
2300
WORD16 ih264d_free_dynamic_bufs(dec_struct_t * ps_dec)
2301
146k
{
2302
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_pic);
2303
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_dec_mb_map);
2304
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_recon_mb_map);
2305
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu2_slice_num_map);
2306
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_dec_slice_buf);
2307
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_frm_mb_info);
2308
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pi2_coeff_data);
2309
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_mb_data);
2310
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_parse_part_params);
2311
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_deblk_top_mb);
2312
2313
146k
    if(ps_dec->p_ctxt_inc_mb_map)
2314
21.5k
    {
2315
21.5k
        ps_dec->p_ctxt_inc_mb_map -= 1;
2316
21.5k
        PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->p_ctxt_inc_mb_map);
2317
21.5k
    }
2318
2319
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[0]);
2320
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_p[1]);
2321
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_pred_pkd);
2322
146k
    {
2323
146k
        UWORD8 i;
2324
730k
        for(i = 0; i < MV_SCRATCH_BUFS; i++)
2325
584k
        {
2326
584k
            PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_mv_top_p[i]);
2327
584k
        }
2328
146k
    }
2329
2330
146k
    if(ps_dec->pu1_y_intra_pred_line)
2331
21.5k
    {
2332
21.5k
        ps_dec->pu1_y_intra_pred_line -= MB_SIZE;
2333
21.5k
    }
2334
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_y_intra_pred_line);
2335
2336
146k
    if(ps_dec->pu1_u_intra_pred_line)
2337
21.5k
    {
2338
21.5k
        ps_dec->pu1_u_intra_pred_line -= MB_SIZE;
2339
21.5k
    }
2340
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_u_intra_pred_line);
2341
2342
146k
    if(ps_dec->pu1_v_intra_pred_line)
2343
21.5k
    {
2344
21.5k
        ps_dec->pu1_v_intra_pred_line -= MB_SIZE;
2345
21.5k
    }
2346
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_v_intra_pred_line);
2347
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->ps_nbr_mb_row);
2348
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_mv_bank_buf_base);
2349
146k
    PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_pic_buf_base);
2350
2351
    /* Free memory for mb_info maps */
2352
146k
    if(ps_dec->u1_enable_mb_info)
2353
0
    {
2354
0
        PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_qp_map_base);
2355
0
        PS_DEC_ALIGNED_FREE(ps_dec, ps_dec->pu1_mb_type_map_base);
2356
0
    }
2357
146k
    return 0;
2358
146k
}
2359
2360
/*!
2361
 **************************************************************************
2362
 * \if Function name : ih264d_create_mv_bank \endif
2363
 *
2364
 * \brief
2365
 *    This function creates MV bank.
2366
 *
2367
 * \param memType  : Type of memory being handled
2368
 *                   0: Display Buffer
2369
 *                   1: Decoder Buffer
2370
 *                   2: Internal Buffer
2371
 * \param u1_num_of_buf: Number of decode or display buffers.
2372
 * \param u4_wd : Frame width.
2373
 * \param u4_ht : Frame Height.
2374
 * \param ps_pic_buf_api : Pointer to Picture Buffer API.
2375
 * \param ih264d_dec_mem_manager  : Memory manager utility supplied by system.
2376
 *
2377
 * \return
2378
 *    0 on Success and -1 on error
2379
 *
2380
 **************************************************************************
2381
 */
2382
WORD32 ih264d_create_mv_bank(void *pv_dec,
2383
                             UWORD32 ui_width,
2384
                             UWORD32 ui_height)
2385
21.5k
{
2386
21.5k
    UWORD8  i;
2387
21.5k
    UWORD32 col_flag_buffer_size, mvpred_buffer_size;
2388
21.5k
    UWORD8 *pu1_mv_buf_mgr_base, *pu1_mv_bank_base;
2389
21.5k
    col_mv_buf_t *ps_col_mv;
2390
21.5k
    mv_pred_t *ps_mv;
2391
21.5k
    UWORD8 *pu1_col_zero_flag_buf;
2392
21.5k
    dec_struct_t *ps_dec = (dec_struct_t *)pv_dec;
2393
21.5k
    WORD32 buf_ret;
2394
21.5k
    UWORD32 u4_num_bufs;
2395
21.5k
    UWORD8 *pu1_buf;
2396
21.5k
    WORD32 size;
2397
21.5k
    void *pv_mem_ctxt = ps_dec->pv_mem_ctxt;
2398
2399
21.5k
    col_flag_buffer_size = ((ui_width * ui_height) >> 4);
2400
21.5k
    mvpred_buffer_size = sizeof(mv_pred_t)
2401
21.5k
                    * ((ui_width * (ui_height + PAD_MV_BANK_ROW)) >> 4);
2402
2403
21.5k
    ih264_buf_mgr_init((buf_mgr_t *)ps_dec->pv_mv_buf_mgr);
2404
2405
21.5k
    ps_col_mv = ps_dec->ps_col_mv_base;
2406
2407
21.5k
    {
2408
21.5k
        UWORD8 u1_num_ref_frames = ps_dec->u4_thumbnail_mode ?
2409
0
                        !ps_dec->ps_cur_sps->u1_frame_mbs_only_flag :
2410
21.5k
                        ps_dec->ps_cur_sps->u1_num_ref_frames;
2411
21.5k
        u4_num_bufs = u1_num_ref_frames + 1;
2412
21.5k
    }
2413
2414
21.5k
    u4_num_bufs = MIN(u4_num_bufs, ps_dec->u1_pic_bufs);
2415
21.5k
    if(!ps_dec->u4_thumbnail_mode)
2416
21.5k
    {
2417
21.5k
        u4_num_bufs = MAX(u4_num_bufs, 2);
2418
21.5k
    }
2419
21.5k
    pu1_buf = ps_dec->pu1_mv_bank_buf_base;
2420
90.3k
    for(i = 0 ; i < u4_num_bufs ; i++)
2421
68.8k
    {
2422
68.8k
        pu1_col_zero_flag_buf = pu1_buf;
2423
68.8k
        pu1_buf += ALIGN64(col_flag_buffer_size);
2424
2425
68.8k
        ps_mv = (mv_pred_t *)pu1_buf;
2426
68.8k
        pu1_buf += ALIGN64(mvpred_buffer_size);
2427
2428
68.8k
        memset(ps_mv, 0, ((ui_width * OFFSET_MV_BANK_ROW) >> 4) * sizeof(mv_pred_t));
2429
68.8k
        ps_mv += (ui_width*OFFSET_MV_BANK_ROW) >> 4;
2430
2431
68.8k
        ps_col_mv->pv_col_zero_flag = (void *)pu1_col_zero_flag_buf;
2432
68.8k
        ps_col_mv->pv_mv = (void *)ps_mv;
2433
68.8k
        buf_ret = ih264_buf_mgr_add((buf_mgr_t *)ps_dec->pv_mv_buf_mgr, ps_col_mv, i);
2434
68.8k
        if(0 != buf_ret)
2435
0
        {
2436
0
            ps_dec->i4_error_code = ERROR_BUF_MGR;
2437
0
            return ERROR_BUF_MGR;
2438
0
        }
2439
68.8k
        ps_col_mv++;
2440
68.8k
    }
2441
21.5k
    return OK;
2442
21.5k
}
2443
2444
void ih264d_unpack_coeff4x4_dc_4x4blk(tu_sblk4x4_coeff_data_t *ps_tu_4x4,
2445
                                      WORD16 *pi2_out_coeff_data,
2446
                                      UWORD8 *pu1_inv_scan)
2447
586k
{
2448
586k
    UWORD16 u2_sig_coeff_map = ps_tu_4x4->u2_sig_coeff_map;
2449
586k
    WORD32 idx;
2450
586k
    WORD16 *pi2_coeff_data = &ps_tu_4x4->ai2_level[0];
2451
2452
1.51M
    while(u2_sig_coeff_map)
2453
925k
    {
2454
925k
        idx = CLZ(u2_sig_coeff_map);
2455
2456
925k
        idx = 31 - idx;
2457
925k
        RESET_BIT(u2_sig_coeff_map,idx);
2458
2459
925k
        idx = pu1_inv_scan[idx];
2460
925k
        pi2_out_coeff_data[idx] = *pi2_coeff_data++;
2461
2462
925k
    }
2463
586k
}