/*

* Copyright(c) 2019 Intel Corporation

*

* This source code is subject to the terms of the BSD 3-Clause Clear License and

* the Alliance for Open Media Patent License 1.0. If the BSD 3-Clause Clear License

* was not distributed with this source code in the LICENSE file, you can

* obtain it at https://www.aomedia.org/license. If the Alliance for Open

* Media Patent License 1.0 was not distributed with this source code in the

* PATENTS file, you can obtain it at https://www.aomedia.org/license/patent-license.

*/

// SUMMARY

//   Contains the API component functions

/**************************************

 * Includes

 **************************************/

#include <stdlib.h>

#include <stdio.h>

#include <stdint.h>

#include "EbVersion.h"

#include "svt_threads.h"

#include "utility.h"

#include "enc_handle.h"

#include "enc_settings.h"

#include "pcs.h"

#include "pic_operators.h"

#include "reference_object.h"

#include "resource_coordination_process.h"

#include "pic_analysis_process.h"

#include "pd_process.h"

#include "me_process.h"

#include "initial_rc_process.h"

#include "src_ops_process.h"

#include "pic_manager_process.h"

#include "rc_process.h"

#include "md_config_process.h"

#include "enc_dec_process.h"

#include "ec_process.h"

#include "packetization_process.h"

#include "resource_coordination_results.h"

#include "pic_analysis_results.h"

#include "pd_results.h"

#include "me_results.h"

#include "initial_rc_results.h"

#include "pic_demux_results.h"

#include "rc_tasks.h"

#include "enc_dec_tasks.h"

#include "enc_dec_results.h"

#include "ec_results.h"

#include "pred_structure.h"

#include "rest_process.h"

#include "cdef_process.h"

#include "dlf_process.h"

#include "rc_results.h"

#include "definitions.h"

#include "metadata_handle.h"

#include "pack_unpack_c.h"

#include "enc_mode_config.h"

#include "hash.h"

#ifdef ARCH_X86_64

#include <immintrin.h>

#endif

#include "svt_log.h"

#ifdef _WIN32

#include <windows.h>

#else

#include <errno.h>

#include <unistd.h>

#endif

#include "aom_dsp_rtcd.h"

#include "common_dsp_rtcd.h"

/**************************************

  * Defines

  **************************************/

// clang-format off

// Config Set Initial Count

#define EB_SequenceControlSetPoolInitCount              10

// Process Instantiation Initial Counts

#define EB_ResourceCoordinationProcessInitCount         1

#define EB_PictureDecisionProcessInitCount              1

#define EB_InitialRateControlProcessInitCount           1

#define EB_PictureManagerProcessInitCount               1

#define EB_RateControlProcessInitCount                  1

#define EB_PacketizationProcessInitCount                1

// Output Buffer Transfer Parameters

#define TPL_INPUT_PORT_SOP                              0

#define TPL_INPUT_PORT_TPL                              1

#define TPL_INPUT_PORT_INVALID                          -1

#define ENCDEC_INPUT_PORT_MDC                           0

#define ENCDEC_INPUT_PORT_ENCDEC                        1

#define ENCDEC_INPUT_PORT_INVALID                       -1

#define ENCODE_FIRST_PASS                               1

// clang-format on

uint8_t svt_aom_get_tpl_synthesizer_block_size(int8_t tpl_level, uint32_t picture_width, uint32_t picture_height);

/* count number of refs in a steady state MG*/

static uint16_t get_num_refs_in_one_mg(uint32_t hierarchical_levels, uint32_t referencing_scheme) {

    if (hierarchical_levels == 0) {

        return 1;

    }

    // All internal layer pics will be used as references.  Only top layer pics can be

    // not used as refs.

    uint16_t tot_refs = 1 << (hierarchical_levels - 1);

    // Top layer pics start at pic_idx 0 and every second pic is a top layer pic

    for (uint16_t pic_idx = 0; pic_idx < (uint32_t)(1 << hierarchical_levels); pic_idx += 2) {

        tot_refs += svt_aom_is_pic_used_as_ref(

            hierarchical_levels, hierarchical_levels, pic_idx, referencing_scheme, 0);

    }

    return tot_refs;

}

static const char* get_asm_level_name_str(EbCpuFlags cpu_flags) {

    // clang-format off

    static const struct {

        const char *name;

        EbCpuFlags  flags;

    } param_maps[] = {

        {"c",            0},

#ifdef ARCH_X86_64

        {"mmx",          EB_CPU_FLAGS_MMX},

        {"sse",          EB_CPU_FLAGS_SSE},

        {"sse2",         EB_CPU_FLAGS_SSE2},

        {"sse3",         EB_CPU_FLAGS_SSE3},

        {"ssse3",        EB_CPU_FLAGS_SSSE3},

        {"sse4_1",       EB_CPU_FLAGS_SSE4_1},

        {"sse4_2",       EB_CPU_FLAGS_SSE4_2},

        {"avx",          EB_CPU_FLAGS_AVX},

        {"avx2",         EB_CPU_FLAGS_AVX2},

        {"avx512",       EB_CPU_FLAGS_AVX512F},

        {"avx512icl",    EB_CPU_FLAGS_AVX512ICL},

#elif defined(ARCH_AARCH64)

        {"neon",         EB_CPU_FLAGS_NEON},

        {"crc32",        EB_CPU_FLAGS_ARM_CRC32},

        {"neon_dotprod", EB_CPU_FLAGS_NEON_DOTPROD},

        {"neon_i8mm",    EB_CPU_FLAGS_NEON_I8MM},

        {"sve",          EB_CPU_FLAGS_SVE},

        {"sve2",         EB_CPU_FLAGS_SVE2}

#endif

    };

    // clang-format on

    static const uint32_t para_map_size = sizeof(param_maps) / sizeof(param_maps[0]);

    for (int32_t i = para_map_size - 1; i >= 0; --i) {

        if (param_maps[i].flags & cpu_flags) {

            return param_maps[i].name;

        }

    }

    return "c";

}

//Get Number of logical processors

static uint32_t get_num_processors() {

#ifdef _WIN32

    return GetActiveProcessorCount(ALL_PROCESSOR_GROUPS);

#else

    return sysconf(_SC_NPROCESSORS_ONLN);

#endif

}

void    svt_aom_asm_set_convolve_asm_table(void);

void    svt_aom_asm_set_convolve_hbd_asm_table(void);

void    svt_aom_init_intra_dc_predictors_c_internal(void);

void    svt_aom_init_intra_predictors_internal(void);

void    svt_av1_init_me_luts(void);

uint8_t svt_aom_get_tpl_group_level(uint8_t tpl, int8_t enc_mode);

uint8_t svt_aom_set_tpl_group(PictureParentControlSet* pcs, uint8_t tpl_group_level, uint32_t source_width,

                              uint32_t source_height);

static void enc_switch_to_real_time() {

#if !defined(_WIN32) && !defined(__EMSCRIPTEN__)

    if (!geteuid()) {

        (void)pthread_setschedparam(pthread_self(), SCHED_FIFO, &(struct sched_param){.sched_priority = 99});

    }

#endif

}

typedef enum ParallelLevel {

    PARALLEL_LEVEL_1     = 1,

    PARALLEL_LEVEL_2     = 2,

    PARALLEL_LEVEL_3     = 3,

    PARALLEL_LEVEL_4     = 4,

    PARALLEL_LEVEL_5     = 5,

    PARALLEL_LEVEL_6     = 6,

    PARALLEL_LEVEL_COUNT = 7

} ParallelLevel;

// When level of parallelism is not specified, the level will be determined

// based on the core count of the machine

#define PARALLEL_LEVEL_1_RANGE 1 // single core count

#define PARALLEL_LEVEL_2_RANGE 2

#define PARALLEL_LEVEL_3_RANGE 5

#define PARALLEL_LEVEL_4_RANGE 11

#define PARALLEL_LEVEL_5_RANGE 23

#define PARALLEL_LEVEL_6_RANGE 47

// Map a machine core count to the default level of parallelism used when the

// user leaves lp unset (lp == 0).

static uint32_t get_default_level_of_parallelism(uint32_t core_count) {

    if (core_count <= PARALLEL_LEVEL_1_RANGE) {

        return PARALLEL_LEVEL_1;

    } else if (core_count <= PARALLEL_LEVEL_2_RANGE) {

        return PARALLEL_LEVEL_2;

    } else if (core_count <= PARALLEL_LEVEL_3_RANGE) {

        return PARALLEL_LEVEL_3;

    } else if (core_count <= PARALLEL_LEVEL_4_RANGE) {

        return PARALLEL_LEVEL_4;

    } else if (core_count <= PARALLEL_LEVEL_5_RANGE) {

        return PARALLEL_LEVEL_5;

    }

    return PARALLEL_LEVEL_6;

}

//return max wavefronts in a given picture

static uint32_t get_max_wavefronts(uint32_t width, uint32_t height, uint32_t blk_size) {

    assert(width > 0 && height > 0);

    return (MIN(width, height) + (blk_size - 1)) / blk_size;

}

/*

* When the picture dimension is a single SB, must use a single segment (EncDec segments

* assume a width of at least 2 SBs)

*

* Return true if the pic dimension is a single SB width

*/

static bool is_pic_dimension_single_sb(uint32_t sb_size, uint16_t pic_dimension) {

    return ((pic_dimension + sb_size - 1) / sb_size) == 1;

}

/*********************************************************************************

* set_segments_numbers: Set the segment numbers for difference processes

***********************************************************************************/

void set_segments_numbers(SequenceControlSet* scs) {

    const uint32_t lp = scs->lp;

    scs->enc_dec_segment_row_count_array =

        (lp == PARALLEL_LEVEL_1 || is_pic_dimension_single_sb(scs->super_block_size, scs->max_input_luma_width)) ? 1

        : (scs->super_block_size == 128) ? MAX((int32_t)((scs->max_input_luma_height + 64) / 128), 1)

                                         : MAX((int32_t)((scs->max_input_luma_height + 32) / 64), 1);

    scs->enc_dec_segment_col_count_array =

        (lp == PARALLEL_LEVEL_1 || is_pic_dimension_single_sb(scs->super_block_size, scs->max_input_luma_height)) ? 1

        : (scs->super_block_size == 128) ? MAX((int32_t)((scs->max_input_luma_width + 64) / 128), 1)

                                         : MAX((int32_t)((scs->max_input_luma_width + 32) / 64), 1);

    scs->me_segment_row_count_array = scs->tf_segment_row_count = (lp == PARALLEL_LEVEL_1) ? 1

        : (((scs->max_input_luma_height + 32) / BLOCK_SIZE_64) < 6)                        ? 1

                                                                                           : 8;

    scs->me_segment_col_count_array = scs->tf_segment_column_count = (lp == PARALLEL_LEVEL_1) ? 1

        : (((scs->max_input_luma_width + 32) / BLOCK_SIZE_64) < 10)                           ? 1

                                                                                              : 6;

    // Jing:

    // A tile group can be consisted by 1 tile or NxM tiles.

    // Segments will be parallelized within a tile group

    // We can use tile group to control the threads/parallelism in ED stage

    // NOTE:1 col will have better perf for segments for large resolutions

    if (scs->static_config.pred_structure == LOW_DELAY) {

        // Low-delay is picture-serial, so tiles are the only intra-frame parallelism:

        // map one tile-group per tile (RA keeps a single tile-group).

        scs->tile_group_col_count_array = 1 << scs->static_config.tile_columns;

        scs->tile_group_row_count_array = 1 << scs->static_config.tile_rows;

    } else {

        // by default, do not use tile parallel. to enable, one can set one tile-group per tile.

        scs->tile_group_col_count_array = 1;

        scs->tile_group_row_count_array = 1;

    }

    // TPL processed in 64x64 blocks, so check width against 64x64 block size (even if SB is 128x128)

    scs->tpl_segment_row_count_array = (lp == PARALLEL_LEVEL_1 ||

                                        is_pic_dimension_single_sb(64, scs->max_input_luma_width))

        ? 1

        : MAX((int32_t)((scs->max_input_luma_height + 32) / 64), 1);

    scs->tpl_segment_col_count_array = (lp == PARALLEL_LEVEL_1)

        ? 1

        : MAX((int32_t)((scs->max_input_luma_width + 32) / 64), 1);

    scs->cdef_segment_row_count    = (lp == PARALLEL_LEVEL_1)       ? 1

        : (((scs->max_input_luma_height + 32) / BLOCK_SIZE_64) < 6) ? 1

        : (scs->input_resolution <= INPUT_SIZE_1080p_RANGE)         ? 2

                                                                    : 4;

    scs->cdef_segment_column_count = (lp == PARALLEL_LEVEL_1)       ? 1

        : (((scs->max_input_luma_width + 32) / BLOCK_SIZE_64) < 10) ? 1

        : (scs->input_resolution <= INPUT_SIZE_1080p_RANGE)         ? 3

                                                                    : 6;

    //since restoration unit size is same for Luma and Chroma, Luma segments and chroma segments do not correspond to the same area!

    //to keep proper processing, segments have to be configured based on chroma resolution.

    const uint32_t unit_size       = RESTORATION_UNITSIZE_MAX;

    const uint32_t rest_seg_w      = MAX((scs->max_input_luma_width / 2 + (unit_size >> 1)) / unit_size, 1);

    const uint32_t rest_seg_h      = MAX((scs->max_input_luma_height / 2 + (unit_size >> 1)) / unit_size, 1);

    scs->rest_segment_column_count = (lp == PARALLEL_LEVEL_1) ? 1

        : scs->input_resolution <= INPUT_SIZE_1080p_RANGE     ? MIN(rest_seg_w, 6)

                                                              : MIN(rest_seg_w, 9);

    scs->rest_segment_row_count    = (lp == PARALLEL_LEVEL_1) ? 1

        : scs->input_resolution <= INPUT_SIZE_1080p_RANGE     ? MIN(rest_seg_h, 4)

                                                              : MIN(rest_seg_h, 6);

    // Low-delay ME segment right-sizing, gated to <=540p (INPUT_SIZE_480p_RANGE).

    //

    // The ME grid set above is resolution-blind: it is a flat 8x6 = 48 segments for every

    // resolution >= 640x360, which at 360p is only ~1.25 superblocks of work per segment. In

    // low delay n_extra_mg is 0, so max_me == 1 and max_me_proc == tot_me_segs (see below):

    // the ME segment count *is* the ME worker pool, and with a single picture in flight a

    // segment's cost lands directly on the frame's critical path. Segments beyond what the

    // configured parallelism can consume are therefore pure per-segment overhead.

    //

    // Trim towards whichever floor binds first, and never below it:

    //   - two segments per core that this parallelism level represents, so the ME pool keeps

    //     slack to absorb the cost variance between segments, and

    //   - a bound on the work per segment, so a large frame is never reduced to a handful of

    //     coarse segments that serialize the ME stage.

    // Both floors err towards more segments: getting them wrong costs some of the saving, it

    // does not cost throughput. 720p and above stay on the stock 8x6: pinned 4-core 720p lp3

    // regresses when the grid is reduced. VOD/RA, lp1, lp5+, and 1x1 grids (CIF and below)

    // are also untouched.

    if (scs->static_config.pred_structure == LOW_DELAY && lp != PARALLEL_LEVEL_1 && lp <= PARALLEL_LEVEL_4 &&

        scs->input_resolution <= INPUT_SIZE_480p_RANGE) {

        const uint32_t max_sbs_per_seg = 20;

        const uint32_t lp_cores        = (lp == PARALLEL_LEVEL_2) ? PARALLEL_LEVEL_2_RANGE

            : (lp == PARALLEL_LEVEL_3)                            ? PARALLEL_LEVEL_3_RANGE

                                                                  : PARALLEL_LEVEL_4_RANGE;

        const uint32_t sb_total        = ((scs->max_input_luma_width + BLOCK_SIZE_64 - 1) / BLOCK_SIZE_64) *

            ((scs->max_input_luma_height + BLOCK_SIZE_64 - 1) / BLOCK_SIZE_64);

        const uint32_t min_segs = MAX(2 * lp_cores, (sb_total + max_sbs_per_seg - 1) / max_sbs_per_seg);

        uint32_t rows = scs->me_segment_row_count_array;

        uint32_t cols = scs->me_segment_col_count_array;

        // Shrink the longer axis one step at a time while staying at or above the floor. Only

        // ever shrinks, so a grid that is already at or below the floor is left alone.

        for (;;) {

            const uint32_t next_rows = (rows >= cols && rows > 1) ? rows - 1 : rows;

            const uint32_t next_cols = (next_rows == rows && cols > 1) ? cols - 1 : cols;

            if ((next_rows == rows && next_cols == cols) || next_rows * next_cols < min_segs) {

                break;

            }

            rows = next_rows;

            cols = next_cols;

        }

        scs->me_segment_row_count_array = scs->tf_segment_row_count = rows;

        scs->me_segment_col_count_array = scs->tf_segment_column_count = cols;

    }

}

static EbErrorType load_default_buffer_configuration_settings(SequenceControlSet* scs) {

    EbErrorType return_error = EB_ErrorNone;

    uint32_t    core_count   = get_num_processors();

    uint32_t lp = scs->static_config.level_of_parallelism;

    if (lp == 0) {

        // In the default config (lp == 0) the core count will determine the

        // amount of parallelism used

        lp = get_default_level_of_parallelism(core_count);

    }

    scs->lp = lp;

    set_segments_numbers(scs);

    const bool is_low_delay = (scs->static_config.pred_structure == LOW_DELAY);

    // adjust buffer count for superres

    uint32_t superres_count = (scs->static_config.superres_mode == SUPERRES_AUTO &&

                               (scs->static_config.superres_auto_search_type == SUPERRES_AUTO_DUAL ||

                                scs->static_config.superres_auto_search_type == SUPERRES_AUTO_ALL))

        ? 1

        : 0;

    //#====================== Data Structures and Picture Buffers ======================

    uint32_t min_input, min_parent, min_child, min_paref, min_ref, min_tpl_ref, min_overlay, min_recon, min_me;

    uint32_t max_input, max_parent, max_child, max_paref, max_me, max_recon;

    /*Look-Ahead. Picture-Decision outputs pictures by group of mini-gops so

        the needed pictures for a certain look-ahead distance (LAD) should be rounded up to the next multiple of MiniGopSize.*/

    uint32_t      mg_size = 1 << scs->static_config.hierarchical_levels;

    const uint8_t overlay = scs->static_config.enable_overlays ? 1 : 0;

    /*To accomodate FFMPEG EOS, 1 frame delay is needed in Resource coordination for RA (for the low delay mode, buffering for receiving EOS does not happen).

      Note that we have the option to not add 1 frame delay of Resource Coordination. In this case we have wait for first I frame

      to be released back to be able to start first base(16). Anyway poc16 needs to wait for poc0 to finish.*/

    const uint8_t eos_delay = is_low_delay || scs->allintra ? 0 : 1;

    //Minimum input pictures needed in the pipeline

    uint16_t lad_mg_pictures = (1 + mg_size + overlay) *

        scs->lad_mg; //Unit= 1(provision for a potential delayI) + prediction struct + potential overlay        return_ppcs = (1 + mg_size) * (scs->lad_mg + 1)  + scs->scd_delay + eos_delay;

    uint32_t return_ppcs = (1 + mg_size) * (scs->lad_mg + 1) + scs->scd_delay + eos_delay;

    //scs->input_buffer_fifo_init_count = return_ppcs;

    min_input = return_ppcs;

    min_parent = return_ppcs;

    // If overlay frames are used, each input will be assigned 2 ppcs: one for the regular frame, and one for the potential alt-ref frame

    if (scs->static_config.enable_overlays) {

        min_parent *= 2;

    }

    //Pic-Manager will inject one child at a time.

    min_child                          = 1;

    const uint16_t num_ref_from_cur_mg = get_num_refs_in_one_mg(scs->static_config.hierarchical_levels,

                                                                scs->mrp_ctrls.referencing_scheme) +

        1; //+1: to accomodate one for a delayed-I

    const uint16_t num_ref_lad_mgs = num_ref_from_cur_mg * scs->lad_mg;

    const uint8_t  dpb_frames =

        REF_FRAMES; // up to dpb_frame refs from prev MGs can be used (AV1 spec allows holding up to 8 frames for references)

    min_ref     = (scs->enable_dec_order) ? dpb_frames + 1 : num_ref_from_cur_mg + num_ref_lad_mgs + dpb_frames;

    min_tpl_ref = scs->tpl ? dpb_frames + 1 : 0; // TPL pictures are processed in decode order

    if (scs->tpl) {

        // PictureDecisionContext.mg_size = mg_size + overlay; see EbPictureDecisionProcess.c line 5680

        min_me = 1 + // potential delay I

            lad_mg_pictures + // 16 + 1 ME data used in store_tpl_pictures() at line 5717

            (mg_size + overlay); // 16 + 1 ME data used in store_tpl_pictures() at line 5729

    } else {

        min_me = 1;

    }

    //PA REF

    const uint16_t num_pa_ref_from_cur_mg =

        mg_size; //ref+nref; nRef PA buffers are processed in PicAnalysis and used in TF

    min_paref = num_pa_ref_from_cur_mg + lad_mg_pictures + scs->scd_delay + eos_delay + dpb_frames;

    if (scs->static_config.enable_overlays) {

        // Need an extra PA ref buffer for each overlay picture. Overlay pics use the same DPB as

        // regular pics, so no need to allocate an extra dpb_frames buffers for the ref pics

        min_paref += num_pa_ref_from_cur_mg + lad_mg_pictures + scs->scd_delay + eos_delay;

    }

    //Overlays

    // Each input pic will assign a ppcs and for each potential overlay, will assign a buffer to store the unfiltered input picture

    min_overlay = scs->static_config.enable_overlays ? return_ppcs : 0;

    min_recon   = min_ref;

    if (is_low_delay) {

        uint32_t low_delay_tf_frames = scs->tf_params_per_type[1].max_num_past_pics;

        min_input = min_parent = 1 + low_delay_tf_frames + scs->scd_delay + eos_delay;

        min_child              = 1; // max_child is 1 for LD

        uint8_t max_refs       = dpb_frames;

        // For special, known, RPS structures and ref frame counts, we can reduce the number of ref buffers

        // A session declaring max_hierarchical_levels may raise its MG size later

        // via MG_SIZE_CHANGE_EVENT, so the flat-IPP shortcut would size the pools

        // for layers it no longer has. Keep the full sizing for those sessions.

        const bool mg_size_may_change = scs->static_config.max_hierarchical_levels > 0;

        if (!mg_size_may_change && scs->static_config.rtc && scs->static_config.hierarchical_levels == 0) {

            max_refs = scs->mrp_ctrls.flat_max_refs;

            // For flat IPP the previous frame is always used as a reference. Therefore, that picture does

            // not require a special buffer for use as a TF ref.

            if (low_delay_tf_frames) {

                low_delay_tf_frames -= 1;

            }

        } else if (scs->mrp_ctrls.ld_reduce_ref_buffs == 1) {

            max_refs = 4;

        } else if (scs->mrp_ctrls.ld_reduce_ref_buffs == 2) {

            max_refs = 2;

        }

        // Set flat_max_refs in case we switch MG size

        scs->mrp_ctrls.flat_max_refs = max_refs;

        min_ref = 1 /*current pic*/ + max_refs;

        // Ref-frame management: app may hold up to max_managed_refs anchors

        // simultaneously; grow the ref-buffer pool by that many entries.

        // When max_managed_refs == 0 (default), this adds 0 and the legacy

        // memory footprint is preserved bit-exactly.

        min_ref += scs->static_config.max_managed_refs;

        min_me    = 1;

        min_paref = 1 /*current pic*/ + low_delay_tf_frames + max_refs + scs->scd_delay + eos_delay;

        // Same rationale for the PA-ref pool.

        min_paref += scs->static_config.max_managed_refs;

    }

    //Configure max needed buffers to process 1+n_extra_mg Mini-Gops in the pipeline. n extra MGs to feed to picMgr on top of current one.

    // Low delay mode has no extra minigops to process.

    uint32_t n_extra_mg;

    if (lp <= PARALLEL_LEVEL_3 || is_low_delay) {

        n_extra_mg = 0;

    } else if (lp <= PARALLEL_LEVEL_4) {

        n_extra_mg = 1;

    } else if (lp <= PARALLEL_LEVEL_5) {

        n_extra_mg = 2;

    } else {

        n_extra_mg = scs->input_resolution <= INPUT_SIZE_4K_RANGE ? 7

            : scs->input_resolution <= INPUT_SIZE_8K_RANGE        ? 5

                                                                  : 0;

    }

    max_input  = min_input + (1 + mg_size) * n_extra_mg;

    max_parent = max_input;

    max_child  = (mg_size / 2) * (n_extra_mg + 1);

    max_child  = MAX(max_child, 1); //have at least one child for mg_size<2

    // In low delay mode, will only have one picture at a time to process

    if (is_low_delay) {

        max_child = 1;

    }

    // max_ref defines here to avoid cppcheck warning

    uint32_t max_ref = min_ref + num_ref_from_cur_mg * n_extra_mg;

    max_paref        = min_paref + (1 + mg_size) * n_extra_mg;

    max_me           = min_me + (1 + mg_size) * n_extra_mg;

    max_recon        = max_ref;

    // if tpl_la is disabled when super-res fix/random, input speed is much faster than recon output speed,

    // recon_output_fifo might be full and freeze at svt_aom_recon_output()

    if (!scs->tpl && scs->static_config.recon_enabled) {

        max_recon = min_recon = MAX(max_ref, 30);

    }

    //#====================== Process Buffers ======================

    scs->input_buffer_fifo_init_count            = clamp(max_input, min_input, max_input);

    scs->picture_control_set_pool_init_count     = clamp(max_parent, min_parent, max_parent);

    scs->pa_reference_picture_buffer_init_count  = clamp(max_paref, min_paref, max_paref);

    scs->tpl_reference_picture_buffer_init_count = min_tpl_ref;

    scs->output_recon_buffer_fifo_init_count = scs->reference_picture_buffer_init_count = clamp(

        max_recon, min_recon, max_recon);

    scs->me_pool_init_count                      = clamp(max_me, min_me, max_me);

    scs->overlay_input_picture_buffer_init_count = min_overlay;

    if (lp <= PARALLEL_LEVEL_1 || MIN_PIC_PARALLELIZATION) {

        scs->input_buffer_fifo_init_count              = min_input;

        scs->picture_control_set_pool_init_count       = min_parent;

        scs->pa_reference_picture_buffer_init_count    = min_paref;

        scs->tpl_reference_picture_buffer_init_count   = min_tpl_ref;

        scs->reference_picture_buffer_init_count       = min_ref;

        scs->picture_control_set_pool_init_count_child = min_child;

        scs->enc_dec_pool_init_count                   = min_child;

        scs->me_pool_init_count                        = min_me;

        scs->overlay_input_picture_buffer_init_count   = min_overlay;

        scs->output_recon_buffer_fifo_init_count = MAX(scs->reference_picture_buffer_init_count, min_recon);

#if CONFIG_SINGLE_THREAD_KERNEL

        // In ST mode the dispatcher processes a full mini-GOP before returning

        // to the app.  svt_aom_recon_output() is called from both REST and

        // Packetization for each non-alt-ref frame, consuming 2 buffers per

        // frame.  The pool must hold enough for the full mini-GOP.

        if (scs->static_config.recon_enabled) {

            scs->output_recon_buffer_fifo_init_count = MAX(scs->output_recon_buffer_fifo_init_count, return_ppcs);

        }

#endif

    } else if (lp <= PARALLEL_LEVEL_2) {

        scs->picture_control_set_pool_init_count_child = scs->enc_dec_pool_init_count = clamp(2, min_child, max_child) +

            superres_count;

    } else if (lp <= PARALLEL_LEVEL_3) {

        scs->picture_control_set_pool_init_count_child = scs->enc_dec_pool_init_count = clamp(8, min_child, max_child) +

            superres_count;

    } else if (lp <= PARALLEL_LEVEL_4) {

        scs->picture_control_set_pool_init_count_child = scs->enc_dec_pool_init_count = clamp(

                                                                                            12, min_child, max_child) +

            superres_count;

    } else if (lp <= PARALLEL_LEVEL_5) {

        scs->picture_control_set_pool_init_count_child = scs->enc_dec_pool_init_count = clamp(

                                                                                            16, min_child, max_child) +

            superres_count;

    } else {

        const uint8_t pcs_processes                    = scs->static_config.rate_control_mode == SVT_AV1_RC_MODE_VBR &&

                scs->static_config.pass == ENC_SECOND_PASS

            ? 24

            : 20;

        scs->picture_control_set_pool_init_count_child = scs->enc_dec_pool_init_count =

            clamp(pcs_processes, min_child, max_child) + superres_count;

    }

    if (scs->static_config.avif) {

        scs->input_buffer_fifo_init_count              = 4;

        scs->picture_control_set_pool_init_count       = 4;

        scs->pa_reference_picture_buffer_init_count    = 4;

        scs->tpl_reference_picture_buffer_init_count   = 0;

        scs->output_recon_buffer_fifo_init_count       = 1;

        scs->reference_picture_buffer_init_count       = 2;

        scs->picture_control_set_pool_init_count_child = 1;

        scs->enc_dec_pool_init_count                   = 1;

        scs->me_pool_init_count                        = 1;

        scs->overlay_input_picture_buffer_init_count   = 0;

        scs->allintra                                  = true;

        scs->static_config.intra_period_length         = 0;

    }

    //#====================== Inter process Fifos ======================

    const uint32_t tot_tf_segs  = scs->tf_segment_column_count * scs->tf_segment_row_count;

    const uint32_t tot_me_segs  = scs->me_segment_col_count_array * scs->me_segment_row_count_array;

    const uint32_t tot_tpl_segs = scs->tpl_segment_col_count_array * scs->tpl_segment_row_count_array;

    // For VBR/Capped-CRF and superres, we may use a recode loop, in which case, the enc dec fifo queue should be increased

    // to account for the extra potential calls.

    const bool     allow_recode     = scs->static_config.recode_loop != DISALLOW_RECODE;

    const bool     is_superres      = scs->static_config.superres_mode != SUPERRES_NONE;

    const uint32_t tot_enc_dec_segs = scs->enc_dec_segment_col_count_array * scs->enc_dec_segment_row_count_array;

    const uint32_t tot_cdef_segs    = scs->cdef_segment_column_count * scs->cdef_segment_row_count;

    const uint32_t tot_rest_segs    = scs->rest_segment_column_count * scs->rest_segment_row_count;

    const uint32_t tot_tiles = MIN(64, (1 << scs->static_config.tile_columns) * (1 << scs->static_config.tile_rows));

    const uint32_t max_fifo  = 300;

    // Open loop

    scs->resource_coordination_fifo_init_count = MIN(

        max_fifo, scs->picture_control_set_pool_init_count); // outputs one pic @ a time to pic analysis (no segments)

    scs->picture_analysis_fifo_init_count = MIN(

        max_fifo, scs->picture_control_set_pool_init_count); // output from pic analysis to PD process (single threaded)

    // +1 b/c release_prev_picture_from_reorder_queue keeps the entry behind the head for the scd

    // histogram until the next pass, so the window is one wider than the ppcs pool

    scs->enc_ctx->picture_decision_reorder_queue_size = scs->picture_control_set_pool_init_count + 1;

    scs->picture_decision_fifo_init_count             = MIN(

        max_fifo, scs->picture_control_set_pool_init_count * MAX(tot_me_segs, tot_tf_segs));

    scs->motion_estimation_fifo_init_count = MIN(

        max_fifo, scs->picture_control_set_pool_init_count); // output from ME to init_rc_process (single threaded)

    scs->initial_rate_control_fifo_init_count = MIN(

        max_fifo, scs->picture_control_set_pool_init_count); // output from irc to src_ops (single threaded)

    scs->tpl_disp_fifo_init_count = MIN(max_fifo,

                                        scs->picture_control_set_pool_init_count * tot_tpl_segs); // TPL dispenser

    // Pic manager (pass through from open loop to closed loop)

    scs->picture_demux_fifo_init_count = MIN(

        max_fifo,

        scs->picture_control_set_pool_init_count +

            2 * scs->picture_control_set_pool_init_count_child); // input to pic mgr from src ops, rest, and packetization

    scs->enc_ctx->pic_mgr_input_pic_list_size = scs->picture_control_set_pool_init_count;

    // Closed loop

    scs->rate_control_tasks_fifo_init_count = MIN(

        max_fifo,

        2 * scs->picture_control_set_pool_init_count_child); // inputs to rc form pic manager and EC/packetization

    scs->rate_control_fifo_init_count = MIN(max_fifo,

                                            scs->picture_control_set_pool_init_count_child); // inputs to MDC from rc

    scs->mode_decision_configuration_fifo_init_count = MIN(

        max_fifo,

        scs->picture_control_set_pool_init_count_child * tot_tiles * tot_enc_dec_segs *

            (1 + allow_recode + is_superres)); // input to MD from MDC

    scs->enc_dec_fifo_init_count = MIN(max_fifo,

                                       scs->picture_control_set_pool_init_count_child); // TODO: Add DLF segments

    scs->dlf_fifo_init_count     = MIN(

        max_fifo, scs->picture_control_set_pool_init_count_child * tot_cdef_segs); // input to CDEF from DLF

    scs->cdef_fifo_init_count = MIN(

        max_fifo, scs->picture_control_set_pool_init_count_child * tot_rest_segs); // input to rest from CDEF

    scs->rest_fifo_init_count = MIN(

        max_fifo, scs->picture_control_set_pool_init_count_child * tot_tiles); // input to EC from rest

    scs->entropy_coding_fifo_init_count = MIN(

        max_fifo, scs->picture_control_set_pool_init_count_child); // EC outputs to packetization (single threaded)

    scs->enc_ctx->packetization_reorder_queue_size = scs->picture_control_set_pool_init_count;

    // bistream buffer will be allocated at run time. app will free the buffer once written to file.

    //

    // release_frames frees the reorder slot and its ppcs, but not the output buffer, which only the

    // app frees. Holder: 1 per undrained reorder

    // slot (<= ppcs pool), 1 per frame parked in the undisplayed queue

    // (<= UNDISP_QUEUE_SIZE), +2 to signal EOS @ resource coord

    // Upperbound matters. Packetization can block in svt_get_empty_object without a slot.

    scs->output_stream_buffer_fifo_init_count = scs->picture_control_set_pool_init_count + UNDISP_QUEUE_SIZE + 2;

    //#====================== Processes number ======================

    scs->total_process_init_count = 0;

    uint32_t max_pa_proc, max_me_proc, max_tpl_proc, max_mdc_proc, max_md_proc, max_ec_proc, max_dlf_proc,

        max_cdef_proc, max_rest_proc;

    max_pa_proc  = max_input;

    max_me_proc  = max_me * tot_me_segs;

    max_tpl_proc = scs->tpl ? get_max_wavefronts(scs->max_input_luma_width, scs->max_input_luma_height, 64) : 1;

    max_mdc_proc = scs->picture_control_set_pool_init_count_child;

    max_md_proc  = scs->picture_control_set_pool_init_count_child *

        get_max_wavefronts(scs->max_input_luma_width, scs->max_input_luma_height, scs->super_block_size);

    max_ec_proc = scs->picture_control_set_pool_init_count_child;

    // Low-delay is picture-serial, so MD/EC parallelize only across tiles. Raise

    // their ceilings to the tile count and target ld_workers below, which doubles

    // per --lp level (matching the core-count brackets) so the thread count

    // scales with --lp instead of being pinned to 1 (EC) or flat.

    uint32_t ld_workers = 1;

    if (is_low_delay) {

        // Each tile has its own segment wavefront, so the MD ceiling is the sum

        // of per-tile wavefronts (not the single frame-wide one), and EC can run

        // one worker per tile.

        uint32_t per_tile_wf = get_max_wavefronts(MAX(scs->max_input_luma_width / scs->tile_group_col_count_array, 1u),

                                                  MAX(scs->max_input_luma_height / scs->tile_group_row_count_array, 1u),

                                                  scs->super_block_size);

        max_md_proc = MAX(max_md_proc, tot_tiles * per_tile_wf);

        max_ec_proc = MAX(max_ec_proc, tot_tiles);

        ld_workers  = 1u << (lp - 1);

    }

    max_dlf_proc  = scs->picture_control_set_pool_init_count_child;

    max_cdef_proc = scs->picture_control_set_pool_init_count_child * scs->cdef_segment_column_count *

        scs->cdef_segment_row_count;

    max_rest_proc = scs->picture_control_set_pool_init_count_child * scs->rest_segment_column_count *

        scs->rest_segment_row_count;

#define WORKERS_COUNT(x) (is_low_delay ? ld_workers : (x))

    if (lp <= PARALLEL_LEVEL_1) {

        scs->total_process_init_count += (scs->picture_analysis_process_init_count = 1);

        scs->total_process_init_count += (scs->motion_estimation_process_init_count = 1);

        scs->total_process_init_count += (scs->source_based_operations_process_init_count = 1);

        scs->total_process_init_count += (scs->tpl_disp_process_init_count = 1);

        scs->total_process_init_count += (scs->mode_decision_configuration_process_init_count = 1);

        scs->total_process_init_count += (scs->enc_dec_process_init_count = 1);

        scs->total_process_init_count += (scs->entropy_coding_process_init_count = 1);

        scs->total_process_init_count += (scs->dlf_process_init_count = 1);

        scs->total_process_init_count += (scs->cdef_process_init_count = 1);

        scs->total_process_init_count += (scs->rest_process_init_count = 1);

    } else if (lp <= PARALLEL_LEVEL_2) {

        const uint8_t pa_processes = scs->static_config.film_grain_denoise_strength ? 16 : 1;

        scs->total_process_init_count += (scs->source_based_operations_process_init_count = 1);

        scs->total_process_init_count += (scs->picture_analysis_process_init_count = clamp(

                                              pa_processes, 1, max_pa_proc));

        scs->total_process_init_count += (scs->motion_estimation_process_init_count = clamp(20, 1, max_me_proc));

        scs->total_process_init_count += (scs->tpl_disp_process_init_count = clamp(6, 1, max_tpl_proc));

        scs->total_process_init_count += (scs->mode_decision_configuration_process_init_count = clamp(

                                              1, 1, max_mdc_proc));

        scs->total_process_init_count +=

            (scs->enc_dec_process_init_count = clamp(

                 WORKERS_COUNT(3), scs->picture_control_set_pool_init_count_child, max_md_proc));

        scs->total_process_init_count += (scs->entropy_coding_process_init_count = clamp(

                                              WORKERS_COUNT(1), 1, max_ec_proc));

        scs->total_process_init_count += (scs->dlf_process_init_count = clamp(1, 1, max_dlf_proc));

        scs->total_process_init_count += (scs->cdef_process_init_count = clamp(6, 1, max_cdef_proc));

        scs->total_process_init_count += (scs->rest_process_init_count = clamp(1, 1, max_rest_proc));

    } else if (lp <= PARALLEL_LEVEL_3) {

        const uint8_t pa_processes = scs->static_config.film_grain_denoise_strength ? 16 : 1;

        scs->total_process_init_count += (scs->source_based_operations_process_init_count = 1);

        scs->total_process_init_count += (scs->picture_analysis_process_init_count = clamp(

                                              pa_processes, 1, max_pa_proc));

        scs->total_process_init_count += (scs->motion_estimation_process_init_count = clamp(25, 1, max_me_proc));

        scs->total_process_init_count += (scs->tpl_disp_process_init_count = clamp(6, 1, max_tpl_proc));

        scs->total_process_init_count += (scs->mode_decision_configuration_process_init_count = clamp(

                                              2, 1, max_mdc_proc));

        scs->total_process_init_count +=

            (scs->enc_dec_process_init_count = clamp(

                 WORKERS_COUNT(5), scs->picture_control_set_pool_init_count_child, max_md_proc));

        scs->total_process_init_count += (scs->entropy_coding_process_init_count = clamp(

                                              WORKERS_COUNT(2), 1, max_ec_proc));

        scs->total_process_init_count += (scs->dlf_process_init_count = clamp(2, 1, max_dlf_proc));

        scs->total_process_init_count += (scs->cdef_process_init_count = clamp(6, 1, max_cdef_proc));

        scs->total_process_init_count += (scs->rest_process_init_count = clamp(2, 1, max_rest_proc));

    } else if (lp <= PARALLEL_LEVEL_5 || scs->input_resolution <= INPUT_SIZE_1080p_RANGE) {

        uint8_t pa_processes = scs->static_config.film_grain_denoise_strength ? 20 : 4;

        if (scs->static_config.pass == ENC_FIRST_PASS) {

            pa_processes = lp <= PARALLEL_LEVEL_5 ? 12 : 20;

        }

        scs->total_process_init_count += (scs->source_based_operations_process_init_count = 1);

        scs->total_process_init_count += (scs->picture_analysis_process_init_count = clamp(

                                              pa_processes, 1, max_pa_proc));

        scs->total_process_init_count += (scs->motion_estimation_process_init_count = clamp(25, 1, max_me_proc));

        scs->total_process_init_count += (scs->tpl_disp_process_init_count = clamp(6, 1, max_tpl_proc));

        scs->total_process_init_count += (scs->mode_decision_configuration_process_init_count = clamp(

                                              3, 1, max_mdc_proc));

        scs->total_process_init_count +=

            (scs->enc_dec_process_init_count = clamp(

                 WORKERS_COUNT(6), scs->picture_control_set_pool_init_count_child, max_md_proc));

        scs->total_process_init_count += (scs->entropy_coding_process_init_count = clamp(

                                              WORKERS_COUNT(4), 1, max_ec_proc));

        scs->total_process_init_count += (scs->dlf_process_init_count = clamp(3, 1, max_dlf_proc));

        scs->total_process_init_count += (scs->cdef_process_init_count = clamp(6, 1, max_cdef_proc));

        scs->total_process_init_count += (scs->rest_process_init_count = clamp(4, 1, max_rest_proc));

    } else {

        const uint8_t pa_processes = (scs->static_config.pass == ENC_FIRST_PASS ||

                                      scs->static_config.film_grain_denoise_strength)

            ? 20

            : 16;

        scs->total_process_init_count += (scs->source_based_operations_process_init_count = 1);

        scs->total_process_init_count += (scs->picture_analysis_process_init_count = clamp(

                                              pa_processes, 1, max_pa_proc));

        scs->total_process_init_count += (scs->motion_estimation_process_init_count = clamp(25, 1, max_me_proc));

        scs->total_process_init_count += (scs->tpl_disp_process_init_count = clamp(12, 1, max_tpl_proc));

        scs->total_process_init_count += (scs->mode_decision_configuration_process_init_count = clamp(

                                              8, 1, max_mdc_proc));

        scs->total_process_init_count +=

            (scs->enc_dec_process_init_count = clamp(

                 WORKERS_COUNT(8), scs->picture_control_set_pool_init_count_child, max_md_proc));

        scs->total_process_init_count += (scs->entropy_coding_process_init_count = clamp(

                                              WORKERS_COUNT(10), 1, max_ec_proc));

        scs->total_process_init_count += (scs->dlf_process_init_count = clamp(8, 1, max_dlf_proc));

        scs->total_process_init_count += (scs->cdef_process_init_count = clamp(8, 1, max_cdef_proc));

        scs->total_process_init_count += (scs->rest_process_init_count = clamp(10, 1, max_rest_proc));

    }

#undef WORKERS_COUNT

    scs->total_process_init_count += 6; // single processes count

    if (scs->static_config.pass == 0 || scs->static_config.pass == 2) {

        SVT_INFO("Level of Parallelism: %u\n", lp);

        SVT_INFO("Number of PPCS %u\n", scs->picture_control_set_pool_init_count);

        /******************************************************************

        * Platform detection, limit cpu flags to hardware available CPU

        ******************************************************************/

#if defined ARCH_X86_64 || defined ARCH_AARCH64

        const EbCpuFlags cpu_flags        = svt_aom_get_cpu_flags();

        const EbCpuFlags cpu_flags_to_use = svt_aom_get_cpu_flags_to_use();

        scs->static_config.use_cpu_flags &= cpu_flags_to_use;

        SVT_INFO("[asm level on system : up to %s]\n", get_asm_level_name_str(cpu_flags));

        SVT_INFO("[asm level selected : up to %s]\n", get_asm_level_name_str(scs->static_config.use_cpu_flags));

#else

        scs->static_config.use_cpu_flags &= 0;

        SVT_INFO("[asm level on system : up to %s]\n", get_asm_level_name_str(0));

        SVT_INFO("[asm level selected : up to %s]\n", get_asm_level_name_str(scs->static_config.use_cpu_flags));

#endif

    }

    return return_error;

}

typedef struct {

    int32_t  type;

    uint32_t count;

} EncDecPorts_t;

// The port-count arrays are built per-instance as locals in svt_av1_enc_init()

// and passed to the lookup/total_count helpers below. They must not be

// file-scope globals: the .count fields are derived from per-instance,

// preset-dependent process counts, so concurrent svt_av1_enc_init() calls at

// different presets would race on them (see #2381).

// Rate Control

static uint32_t rate_control_port_lookup(const RateControlPorts* rate_control_ports, RateControlInputPortTypes type,

                                         uint32_t port_type_index) {

    uint32_t port_index = 0;

    uint32_t port_count = 0;

    while ((type != rate_control_ports[port_index].type) && (type != RATE_CONTROL_INPUT_PORT_INVALID)) {

        port_count += rate_control_ports[port_index++].count;

    }

    return (port_count + port_type_index);

}

// Rate Control

static uint32_t rate_control_port_total_count(const RateControlPorts* rate_control_ports) {

    uint32_t port_index  = 0;

    uint32_t total_count = 0;

    while (rate_control_ports[port_index].type != RATE_CONTROL_INPUT_PORT_INVALID) {

        total_count += rate_control_ports[port_index++].count;

    }

    return total_count;

}

static uint32_t pic_mgr_port_lookup(const PicMgrPorts* pic_mgr_ports, PicMgrInputPortTypes type,

                                    uint32_t port_type_index) {

    uint32_t port_index = 0;

    uint32_t port_count = 0;

    while ((type != pic_mgr_ports[port_index].type) && (type != PIC_MGR_INPUT_PORT_INVALID)) {

        port_count += pic_mgr_ports[port_index++].count;

    }

    return (port_count + port_type_index);

}

static uint32_t pic_mgr_port_total_count(const PicMgrPorts* pic_mgr_ports) {

    uint32_t port_index  = 0;

    uint32_t total_count = 0;

    while (pic_mgr_ports[port_index].type != PIC_MGR_INPUT_PORT_INVALID) {

        total_count += pic_mgr_ports[port_index++].count;

    }

    return total_count;

}

// TPL

static uint32_t tpl_port_lookup(const EncDecPorts_t* tpl_ports, int32_t type, uint32_t port_type_index) {

    uint32_t port_index = 0;

    uint32_t port_count = 0;

    while ((type != tpl_ports[port_index].type) && (type != TPL_INPUT_PORT_INVALID)) {

        port_count += tpl_ports[port_index++].count;

    }

    return (port_count + port_type_index);

}

static uint32_t tpl_port_total_count(const EncDecPorts_t* tpl_ports) {

    uint32_t port_index  = 0;

    uint32_t total_count = 0;

    while (tpl_ports[port_index].type != TPL_INPUT_PORT_INVALID) {

        total_count += tpl_ports[port_index++].count;

    }

    return total_count;

}

/*****************************************

 * Input Port Lookup

 *****************************************/

// EncDec

static uint32_t enc_dec_port_lookup(const EncDecPorts_t* enc_dec_ports, int32_t type, uint32_t port_type_index) {

    uint32_t port_index = 0;

    uint32_t port_count = 0;

    while ((type != enc_dec_ports[port_index].type) && (type != ENCDEC_INPUT_PORT_INVALID)) {

        port_count += enc_dec_ports[port_index++].count;

    }

    return (port_count + port_type_index);

}

// EncDec

static uint32_t enc_dec_port_total_count(const EncDecPorts_t* enc_dec_ports) {

    uint32_t port_index  = 0;

    uint32_t total_count = 0;

    while (enc_dec_ports[port_index].type != ENCDEC_INPUT_PORT_INVALID) {

        total_count += enc_dec_ports[port_index++].count;

    }

    return total_count;

}

/*****************************************

 * Input Port Total Count

 *****************************************/

static void lib_svt_encoder_send_error_exit(EbPtr hComponent, uint32_t error_code);

static void svt_enc_handle_stop_threads(EbEncHandle* enc_handle_ptr) {

    SequenceControlSet* scs = enc_handle_ptr->scs_instance->scs;

    // Resource Coordination

    EB_DESTROY_THREAD(enc_handle_ptr->resource_coordination_thread_handle);

    EB_DESTROY_THREAD_ARRAY(enc_handle_ptr->picture_analysis_thread_handle_array,

                            scs->picture_analysis_process_init_count);

    // Picture Decision

    EB_DESTROY_THREAD(enc_handle_ptr->picture_decision_thread_handle);

    // Motion Estimation

    EB_DESTROY_THREAD_ARRAY(enc_handle_ptr->motion_estimation_thread_handle_array,

                            scs->motion_estimation_process_init_count);

    // Initial Rate Control

    EB_DESTROY_THREAD(enc_handle_ptr->initial_rate_control_thread_handle);

    // Source Based Oprations

    EB_DESTROY_THREAD_ARRAY(enc_handle_ptr->source_based_operations_thread_handle_array,

                            scs->source_based_operations_process_init_count);

    // TPL dispenser ME

    EB_DESTROY_THREAD_ARRAY(enc_handle_ptr->tpl_disp_thread_handle_array, scs->tpl_disp_process_init_count);

    // Picture Manager

    EB_DESTROY_THREAD(enc_handle_ptr->picture_manager_thread_handle);

    // Rate Control

    EB_DESTROY_THREAD(enc_handle_ptr->rate_control_thread_handle);

    // Mode Decision Configuration Process

    EB_DESTROY_THREAD_ARRAY(enc_handle_ptr->mode_decision_configuration_thread_handle_array,

                            scs->mode_decision_configuration_process_init_count);

    // EncDec Process

    EB_DESTROY_THREAD_ARRAY(enc_handle_ptr->enc_dec_thread_handle_array, scs->enc_dec_process_init_count);

    // Dlf Process

    EB_DESTROY_THREAD_ARRAY(enc_handle_ptr->dlf_thread_handle_array, scs->dlf_process_init_count);

    // Cdef Process

    EB_DESTROY_THREAD_ARRAY(enc_handle_ptr->cdef_thread_handle_array, scs->cdef_process_init_count);

    // Rest Process

    EB_DESTROY_THREAD_ARRAY(enc_handle_ptr->rest_thread_handle_array, scs->rest_process_init_count);

    // Entropy Coding Process

    EB_DESTROY_THREAD_ARRAY(enc_handle_ptr->entropy_coding_thread_handle_array, scs->entropy_coding_process_init_count);

    // Packetization

    EB_DESTROY_THREAD(enc_handle_ptr->packetization_thread_handle);

}

/**********************************

* Encoder Library Handle Deonstructor

**********************************/

static void svt_enc_handle_dctor(EbPtr p) {

    EbEncHandle* enc_handle_ptr = (EbEncHandle*)p;

    svt_enc_handle_stop_threads(enc_handle_ptr);

    EB_FREE(enc_handle_ptr->app_callback_ptr);

    EB_DELETE(enc_handle_ptr->scs_pool_ptr);

    EB_DELETE(enc_handle_ptr->picture_parent_control_set_pool_ptr);

    EB_DELETE(enc_handle_ptr->me_pool_ptr);

    EB_DELETE(enc_handle_ptr->picture_control_set_pool_ptr);

    EB_DELETE(enc_handle_ptr->enc_dec_pool_ptr);

    EB_DELETE(enc_handle_ptr->pa_reference_picture_pool_ptr);

    EB_DELETE(enc_handle_ptr->tpl_reference_picture_pool_ptr);

    EB_DELETE(enc_handle_ptr->overlay_input_picture_pool_ptr);

    EB_DELETE(enc_handle_ptr->reference_picture_pool_ptr);

    EB_DELETE(enc_handle_ptr->input_cmd_resource_ptr);

    EB_DELETE(enc_handle_ptr->input_y8b_buffer_resource_ptr);

    //all y_buffer have been redirected to y8b location that just got released.

    //to prevent releasing twice, we need to reset the buffer back to NULL

    if (enc_handle_ptr->input_buffer_resource_ptr) {

        for (uint32_t w_i = 0; w_i < enc_handle_ptr->input_buffer_resource_ptr->object_total_count; ++w_i) {

            EbObjectWrapper*     wrp  = enc_handle_ptr->input_buffer_resource_ptr->wrapper_ptr_pool[w_i];

            EbBufferHeaderType*  obj  = (EbBufferHeaderType*)wrp->object_ptr;

            EbPictureBufferDesc* desc = (EbPictureBufferDesc*)obj->p_buffer;

            desc->y_buffer            = 0;

        }

    }

    EB_DELETE(enc_handle_ptr->input_buffer_resource_ptr);

    EB_DELETE(enc_handle_ptr->output_stream_buffer_resource_ptr);

    EB_DELETE(enc_handle_ptr->output_recon_buffer_resource_ptr);

    EB_DELETE(enc_handle_ptr->resource_coordination_results_resource_ptr);

    EB_DELETE(enc_handle_ptr->picture_analysis_results_resource_ptr);