Coverage Report

Created: 2025-07-18 06:38

/src/libxaac/decoder/ixheaacd_ld_mps_config.c
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Source (jump to first uncovered line)
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/******************************************************************************
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*                                                                            *
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* Copyright (C) 2018 The Android Open Source Project
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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*****************************************************************************
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* Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
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*/
20
#include "ixheaac_type_def.h"
21
#include "ixheaac_constants.h"
22
#include "ixheaac_error_standards.h"
23
24
#include "ixheaacd_bitbuffer.h"
25
#include "ixheaacd_config.h"
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27
#include <assert.h>
28
29
#ifndef sign
30
#define sign(a) (((a) > 0) ? 1 : ((a) < 0) ? -1 : 0)
31
#endif
32
33
typedef struct {
34
  WORD32 num_input_chan;
35
  WORD32 num_output_chan;
36
  WORD32 num_ott_boxes;
37
  WORD32 num_ttt_boxes;
38
  WORD32 ott_mode_lfe[MAX_NUM_OTT];
39
} ia_ld_mps_dec_tree_properties_struct;
40
41
static WORD32 ixheaacd_freq_res_table[] = {0, 23, 15, 12, 9, 7, 5, 4};
42
43
static WORD32 ixheaacd_hrtf_freq_res_table[][8] = {{0, 28, 20, 14, 10, 7, 5, 4},
44
                                          {0, 13, 13, 8, 7, 4, 3, 3}};
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46
static ia_ld_mps_dec_tree_properties_struct ixheaacd_tree_property_table[] = {
47
    {1, 6, 5, 0, {0, 0, 0, 0, 1}}, {1, 6, 5, 0, {0, 0, 1, 0, 0}}, {2, 6, 3, 1, {1, 0, 0, 0, 0}},
48
    {2, 8, 5, 1, {1, 0, 0, 0, 0}}, {2, 8, 5, 1, {1, 0, 0, 0, 0}}, {6, 8, 2, 0, {0, 0, 0, 0, 0}},
49
    {6, 8, 2, 0, {0, 0, 0, 0, 0}}, {1, 2, 1, 0, {0, 0, 0, 0, 0}}};
50
51
static IA_ERRORCODE ixheaacd_ld_spatial_extension_config(
52
    ia_bit_buf_struct *it_bit_buff, ia_usac_dec_mps_config_struct *config,
53
1.44k
    WORD32 bits_available) {
54
1.44k
  WORD32 j, ch, idx, tmp, tmp_open, sac_ext_len, bits_read, n_fill_bits;
55
1.44k
  UWORD32 i;
56
1.44k
  WORD32 ba = bits_available;
57
58
1.44k
  config->sac_ext_cnt = 0;
59
60
1.44k
  tmp = it_bit_buff->cnt_bits;
61
62
9.95k
  while (ba >= 8) {
63
8.56k
    if (config->sac_ext_cnt >= MAX_NUM_EXT_TYPES) return IA_FATAL_ERROR;
64
65
8.56k
    config->bs_sac_ext_type[config->sac_ext_cnt] =
66
8.56k
        ixheaacd_read_bits_buf(it_bit_buff, 4);
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8.56k
    ba -= 4;
68
69
8.56k
    sac_ext_len = ixheaacd_read_bits_buf(it_bit_buff, 4);
70
8.56k
    ba -= 4;
71
72
8.56k
    if ((ba >= 6) && (sac_ext_len > 0)) {
73
5.23k
      if (sac_ext_len == 15) {
74
2.81k
        sac_ext_len += ixheaacd_read_bits_buf(it_bit_buff, 8);
75
2.81k
        ba -= 8;
76
2.81k
        if (sac_ext_len == 15 + 255) {
77
915
          sac_ext_len += ixheaacd_read_bits_buf(it_bit_buff, 16);
78
915
          ba -= 16;
79
915
        }
80
2.81k
      }
81
82
5.23k
      switch (config->bs_sac_ext_type[config->sac_ext_cnt]) {
83
65
        case 0:
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65
          config->bs_residual_coding = 1;
85
86
65
          config->bs_residual_sampling_freq_index =
87
65
              ixheaacd_read_bits_buf(it_bit_buff, 4);
88
65
          if (config->bs_residual_sampling_freq_index > MAX_RES_SAMP_FREQ_IDX) {
89
3
            return IA_FATAL_ERROR;
90
3
          }
91
62
          config->bs_residual_frames_per_spatial_frame =
92
62
              ixheaacd_read_bits_buf(it_bit_buff, 2);
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94
62
          if ((config->num_ott_boxes + config->num_ttt_boxes) >
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62
              MAX_RESIDUAL_CHANNELS)
96
2
            return IA_FATAL_ERROR;
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146
          for (j = 0; j < config->num_ott_boxes + config->num_ttt_boxes; j++) {
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87
            config->bs_residual_present[j] =
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87
                ixheaacd_read_bits_buf(it_bit_buff, 1);
100
87
            if (config->bs_residual_present[j]) {
101
30
              config->bs_residual_bands_ld_mps[j] =
102
30
                  ixheaacd_read_bits_buf(it_bit_buff, 5);
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30
              if (config->bs_residual_bands_ld_mps[j] > MAX_PARAMETER_BANDS)
104
1
              {
105
1
                return IA_FATAL_ERROR;
106
1
              }
107
30
            }
108
87
          }
109
59
          break;
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111
59
        case 1:
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47
          config->bs_arbitrary_downmix = 2;
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114
47
          config->bs_arbitrary_downmix_residual_sampling_freq_index =
115
47
              ixheaacd_read_bits_buf(it_bit_buff, 4);
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47
          if (config->bs_arbitrary_downmix_residual_sampling_freq_index > MAX_RES_SAMP_FREQ_IDX) {
117
1
            return IA_FATAL_ERROR;
118
1
          }
119
46
          config->bs_arbitrary_downmix_residual_frames_per_spatial_frame =
120
46
              ixheaacd_read_bits_buf(it_bit_buff, 2);
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46
          config->bs_arbitrary_downmix_residual_bands =
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46
              ixheaacd_read_bits_buf(it_bit_buff, 5);
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46
          if (config->bs_arbitrary_downmix_residual_bands >=
124
46
              ixheaacd_freq_res_table[config->bs_freq_res]) {
125
4
            return IA_FATAL_ERROR;
126
4
          }
127
128
42
          break;
129
130
253
        case 2:
131
253
          config->num_out_chan_AT = 0;
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253
          config->num_ott_boxes_AT = 0;
133
253
          if (config->num_output_channels > MAX_OUTPUT_CHANNELS)
134
1
            return IA_FATAL_ERROR;
135
1.50k
          for (ch = 0; ch < config->num_output_channels; ch++) {
136
1.24k
            tmp_open = 1;
137
1.24k
            idx = 0;
138
5.57k
            while ((tmp_open > 0) && (idx < MAX_ARBITRARY_TREE_INDEX)) {
139
4.32k
              config->bs_ott_box_present_AT[ch][idx] =
140
4.32k
                  ixheaacd_read_bits_buf(it_bit_buff, 1);
141
4.32k
              if (config->bs_ott_box_present_AT[ch][idx]) {
142
3.12k
                config->num_ott_boxes_AT++;
143
3.12k
                tmp_open++;
144
3.12k
              } else {
145
1.20k
                config->num_out_chan_AT++;
146
1.20k
                tmp_open--;
147
1.20k
              }
148
4.32k
              idx++;
149
4.32k
            }
150
1.24k
          }
151
152
3.20k
          for (i = 0; i < config->num_ott_boxes_AT; i++) {
153
2.95k
            config->bs_ott_default_cld_AT[i] =
154
2.95k
                ixheaacd_read_bits_buf(it_bit_buff, 1);
155
2.95k
            config->bs_ott_mode_lfe_AT[i] =
156
2.95k
                ixheaacd_read_bits_buf(it_bit_buff, 1);
157
2.95k
            if (config->bs_ott_mode_lfe_AT[i]) {
158
1.09k
              config->bs_ott_bands_AT[i] =
159
1.09k
                  ixheaacd_read_bits_buf(it_bit_buff, 5);
160
1.85k
            } else {
161
1.85k
              config->bs_ott_bands_AT[i] = ixheaacd_freq_res_table[config->bs_freq_res];
162
1.85k
            }
163
2.95k
          }
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1.32k
          for (i = 0; i < config->num_out_chan_AT; i++) {
166
1.07k
            config->bs_output_channel_pos_AT[i] =
167
1.07k
                ixheaacd_read_bits_buf(it_bit_buff, 5);
168
1.07k
          }
169
170
252
          break;
171
172
4.86k
        default:;
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5.23k
      }
174
5.23k
    }
175
176
8.51k
    bits_read = tmp - it_bit_buff->cnt_bits;
177
8.51k
    n_fill_bits = 8 * sac_ext_len - bits_read;
178
179
1.83M
    while (n_fill_bits > 7) {
180
1.82M
      ixheaacd_read_bits_buf(it_bit_buff, 8);
181
1.82M
      n_fill_bits -= 8;
182
1.82M
    }
183
8.51k
    if (n_fill_bits > 0) {
184
197
      ixheaacd_read_bits_buf(it_bit_buff, n_fill_bits);
185
197
    }
186
187
8.51k
    ba -= 8 * sac_ext_len;
188
8.51k
    config->sac_ext_cnt++;
189
8.51k
  }
190
1.39k
  return IA_NO_ERROR;
191
1.44k
}
192
193
IA_ERRORCODE ixheaacd_ld_spatial_specific_config(
194
1.52k
    ia_usac_dec_mps_config_struct *config, ia_bit_buf_struct *it_bit_buff) {
195
1.52k
  WORD32 i, num_header_bits;
196
1.52k
  UWORD32 hc, hb;
197
1.52k
  WORD32 sac_header_len;
198
1.52k
  WORD32 bits_available;
199
1.52k
  WORD32 tmp = it_bit_buff->cnt_bits;
200
1.52k
  WORD32 err = 0;
201
202
1.52k
  sac_header_len = tmp;
203
204
1.52k
  bits_available = sac_header_len;
205
1.52k
  config->bs_sampling_freq_index = ixheaacd_read_bits_buf(it_bit_buff, 4);
206
1.52k
  if (config->bs_sampling_freq_index == 15) {
207
22
    config->bs_fampling_frequency = ixheaacd_read_bits_buf(it_bit_buff, 24);
208
22
  }
209
210
1.52k
  config->bs_frame_length = ixheaacd_read_bits_buf(it_bit_buff, 5);
211
1.52k
  config->bs_freq_res = ixheaacd_read_bits_buf(it_bit_buff, 3);
212
1.52k
  config->bs_tree_config = ixheaacd_read_bits_buf(it_bit_buff, 4);
213
214
1.52k
  if (config->bs_tree_config > 7) return IA_FATAL_ERROR;
215
216
1.51k
  if (config->bs_tree_config != 15) {
217
1.51k
    config->num_ott_boxes =
218
1.51k
        ixheaacd_tree_property_table[config->bs_tree_config].num_ott_boxes;
219
1.51k
    config->num_ttt_boxes =
220
1.51k
        ixheaacd_tree_property_table[config->bs_tree_config].num_ttt_boxes;
221
1.51k
    config->num_input_channels =
222
1.51k
        ixheaacd_tree_property_table[config->bs_tree_config].num_input_chan;
223
1.51k
    config->num_output_channels =
224
1.51k
        ixheaacd_tree_property_table[config->bs_tree_config].num_output_chan;
225
9.06k
    for (i = 0; i < MAX_NUM_OTT; i++) {
226
7.55k
      config->ott_mode_lfe[i] =
227
7.55k
          ixheaacd_tree_property_table[config->bs_tree_config].ott_mode_lfe[i];
228
7.55k
    }
229
1.51k
  }
230
1.51k
  config->bs_quant_mode = ixheaacd_read_bits_buf(it_bit_buff, 2);
231
1.51k
  if (config->bs_tree_config != 7) {
232
1.19k
    config->bs_one_icc = ixheaacd_read_bits_buf(it_bit_buff, 1);
233
1.19k
  }
234
1.51k
  config->bs_arbitrary_downmix = ixheaacd_read_bits_buf(it_bit_buff, 1);
235
1.51k
  if (config->bs_tree_config != 7) {
236
1.19k
    config->bs_fixed_gain_sur = ixheaacd_read_bits_buf(it_bit_buff, 3);
237
1.19k
    config->bs_fixed_gain_LFE = ixheaacd_read_bits_buf(it_bit_buff, 3);
238
1.19k
  }
239
1.51k
  config->bs_fixed_gain_dmx = ixheaacd_read_bits_buf(it_bit_buff, 3);
240
1.51k
  if (config->bs_tree_config != 7) {
241
1.19k
    config->bs_matrix_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
242
1.19k
  }
243
1.51k
  config->bs_temp_shape_config = ixheaacd_read_bits_buf(it_bit_buff, 2);
244
1.51k
  config->bs_decorr_config = ixheaacd_read_bits_buf(it_bit_buff, 2);
245
1.51k
  if (config->bs_tree_config != 7) {
246
1.19k
    config->bs_3D_audio_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
247
1.19k
  } else {
248
321
    config->bs_3D_audio_mode = 0;
249
321
  }
250
251
  // ott_config
252
6.22k
  for (i = 0; i < config->num_ott_boxes; i++) {
253
4.71k
    if (config->ott_mode_lfe[i]) {
254
795
      config->bs_ott_bands[i] = ixheaacd_read_bits_buf(it_bit_buff, 5);
255
3.92k
    } else {
256
3.92k
      config->bs_ott_bands[i] = ixheaacd_freq_res_table[config->bs_freq_res];
257
3.92k
    }
258
4.71k
  }
259
260
  // ttt_config
261
1.71k
  for (i = 0; i < config->num_ttt_boxes; i++) {
262
203
    config->bs_ttt_dual_mode[i] = ixheaacd_read_bits_buf(it_bit_buff, 1);
263
203
    config->bs_ttt_mode_low[i] = ixheaacd_read_bits_buf(it_bit_buff, 3);
264
203
    if (config->bs_ttt_dual_mode[i]) {
265
14
      config->bs_ttt_mode_high[i] = ixheaacd_read_bits_buf(it_bit_buff, 3);
266
14
      config->bs_ttt_bands_low[i] = ixheaacd_read_bits_buf(it_bit_buff, 5);
267
14
      config->bs_ttt_bands_high[i] = ixheaacd_freq_res_table[config->bs_freq_res];
268
189
    } else {
269
189
      config->bs_ttt_bands_low[i] = ixheaacd_freq_res_table[config->bs_freq_res];
270
189
    }
271
203
  }
272
273
1.51k
  if (config->bs_temp_shape_config == 2) {
274
409
    config->bs_env_quant_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
275
409
  }
276
277
1.51k
  if (config->bs_3D_audio_mode) {
278
203
    config->bs_3D_audio_HRTF_set = ixheaacd_read_bits_buf(it_bit_buff, 2);
279
    // param_HRTF_set
280
203
    if (config->bs_3D_audio_HRTF_set == 0) {
281
79
      config->bs_HRTF_freq_res = ixheaacd_read_bits_buf(it_bit_buff, 3);
282
79
      config->bs_HRTF_num_chan = 5;
283
79
      config->bs_HRTF_asymmetric = ixheaacd_read_bits_buf(it_bit_buff, 1);
284
285
79
      config->HRTF_num_band = ixheaacd_hrtf_freq_res_table[0][config->bs_HRTF_freq_res];
286
79
      config->HRTF_num_phase = ixheaacd_hrtf_freq_res_table[1][config->bs_HRTF_freq_res];
287
288
327
      for (hc = 0; hc < config->bs_HRTF_num_chan; hc++) {
289
1.75k
        for (hb = 0; hb < config->HRTF_num_band; hb++) {
290
1.50k
          config->bs_HRTF_level_left[hc][hb] =
291
1.50k
              ixheaacd_read_bits_buf(it_bit_buff, 6);
292
1.50k
        }
293
1.65k
        for (hb = 0; hb < config->HRTF_num_band; hb++) {
294
1.40k
          config->bs_HRTF_level_right[hc][hb] =
295
1.40k
              config->bs_HRTF_asymmetric
296
1.40k
                  ? ixheaacd_read_bits_buf(it_bit_buff, 6)
297
1.40k
                  : config->bs_HRTF_level_left[hc][hb];
298
1.40k
        }
299
248
        config->bs_HRTF_phase[hc] = ixheaacd_read_bits_buf(it_bit_buff, 1);
300
1.06k
        for (hb = 0; hb < config->HRTF_num_phase; hb++) {
301
817
          config->bs_HRTF_phase_LR[hc][hb] =
302
817
              config->bs_HRTF_phase[hc] ? ixheaacd_read_bits_buf(it_bit_buff, 6)
303
817
                                        : 0;
304
817
        }
305
248
        config->bs_HRTF_icc[hc] = ixheaacd_read_bits_buf(it_bit_buff, 1);
306
248
        if (config->bs_HRTF_icc[hc]) {
307
454
          for (hb = 0; hb < config->HRTF_num_band; hb++)
308
377
            config->bs_HRTF_icc_LR[hc][hb] =
309
377
                ixheaacd_read_bits_buf(it_bit_buff, 3);
310
77
        }
311
248
      }
312
79
    }
313
203
  }
314
315
  // byte_align
316
1.51k
  i = (it_bit_buff->cnt_bits & 0x7);
317
1.51k
  ixheaacd_read_bits_buf(it_bit_buff, i);
318
319
1.51k
  num_header_bits = tmp - (it_bit_buff->cnt_bits);
320
1.51k
  bits_available -= num_header_bits;
321
322
1.51k
  err =
323
1.51k
      ixheaacd_ld_spatial_extension_config(it_bit_buff, config, bits_available);
324
1.51k
  return err;
325
1.52k
}