Coverage Report

Created: 2025-11-24 06:48

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/libxaac/decoder/ixheaacd_ld_mps_config.c
Line
Count
Source
1
/******************************************************************************
2
*                                                                            *
3
* Copyright (C) 2018 The Android Open Source Project
4
*
5
* Licensed under the Apache License, Version 2.0 (the "License");
6
* you may not use this file except in compliance with the License.
7
* You may obtain a copy of the License at:
8
*
9
* http://www.apache.org/licenses/LICENSE-2.0
10
*
11
* Unless required by applicable law or agreed to in writing, software
12
* distributed under the License is distributed on an "AS IS" BASIS,
13
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14
* See the License for the specific language governing permissions and
15
* limitations under the License.
16
*
17
*****************************************************************************
18
* Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19
*/
20
#include "ixheaac_type_def.h"
21
#include "ixheaac_constants.h"
22
#include "ixheaac_error_standards.h"
23
24
#include "ixheaacd_bitbuffer.h"
25
#include "ixheaacd_config.h"
26
27
#include <assert.h>
28
29
#ifndef sign
30
#define sign(a) (((a) > 0) ? 1 : ((a) < 0) ? -1 : 0)
31
#endif
32
33
typedef struct {
34
  WORD32 num_input_chan;
35
  WORD32 num_output_chan;
36
  WORD32 num_ott_boxes;
37
  WORD32 num_ttt_boxes;
38
  WORD32 ott_mode_lfe[MAX_NUM_OTT];
39
} ia_ld_mps_dec_tree_properties_struct;
40
41
static WORD32 ixheaacd_freq_res_table[] = {0, 23, 15, 12, 9, 7, 5, 4};
42
43
static WORD32 ixheaacd_hrtf_freq_res_table[][8] = {{0, 28, 20, 14, 10, 7, 5, 4},
44
                                          {0, 13, 13, 8, 7, 4, 3, 3}};
45
46
static ia_ld_mps_dec_tree_properties_struct ixheaacd_tree_property_table[] = {
47
    {1, 6, 5, 0, {0, 0, 0, 0, 1}}, {1, 6, 5, 0, {0, 0, 1, 0, 0}}, {2, 6, 3, 1, {1, 0, 0, 0, 0}},
48
    {2, 8, 5, 1, {1, 0, 0, 0, 0}}, {2, 8, 5, 1, {1, 0, 0, 0, 0}}, {6, 8, 2, 0, {0, 0, 0, 0, 0}},
49
    {6, 8, 2, 0, {0, 0, 0, 0, 0}}, {1, 2, 1, 0, {0, 0, 0, 0, 0}}};
50
51
static IA_ERRORCODE ixheaacd_ld_spatial_extension_config(
52
    ia_bit_buf_struct *it_bit_buff, ia_usac_dec_mps_config_struct *config,
53
1.44k
    WORD32 bits_available) {
54
1.44k
  WORD32 j, ch, idx, tmp, tmp_open, sac_ext_len, bits_read, n_fill_bits;
55
1.44k
  UWORD32 i;
56
1.44k
  WORD32 ba = bits_available;
57
58
1.44k
  config->sac_ext_cnt = 0;
59
60
1.44k
  tmp = it_bit_buff->cnt_bits;
61
62
10.0k
  while (ba >= 8) {
63
8.66k
    if (config->sac_ext_cnt >= MAX_NUM_EXT_TYPES) return IA_FATAL_ERROR;
64
65
8.65k
    config->bs_sac_ext_type[config->sac_ext_cnt] =
66
8.65k
        ixheaacd_read_bits_buf(it_bit_buff, 4);
67
8.65k
    ba -= 4;
68
69
8.65k
    sac_ext_len = ixheaacd_read_bits_buf(it_bit_buff, 4);
70
8.65k
    ba -= 4;
71
72
8.65k
    if ((ba >= 6) && (sac_ext_len > 0)) {
73
5.18k
      if (sac_ext_len == 15) {
74
2.81k
        sac_ext_len += ixheaacd_read_bits_buf(it_bit_buff, 8);
75
2.81k
        ba -= 8;
76
2.81k
        if (sac_ext_len == 15 + 255) {
77
953
          sac_ext_len += ixheaacd_read_bits_buf(it_bit_buff, 16);
78
953
          ba -= 16;
79
953
        }
80
2.81k
      }
81
82
5.18k
      switch (config->bs_sac_ext_type[config->sac_ext_cnt]) {
83
50
        case 0:
84
50
          config->bs_residual_coding = 1;
85
86
50
          config->bs_residual_sampling_freq_index =
87
50
              ixheaacd_read_bits_buf(it_bit_buff, 4);
88
50
          if (config->bs_residual_sampling_freq_index > MAX_RES_SAMP_FREQ_IDX) {
89
2
            return IA_FATAL_ERROR;
90
2
          }
91
48
          config->bs_residual_frames_per_spatial_frame =
92
48
              ixheaacd_read_bits_buf(it_bit_buff, 2);
93
94
48
          if ((config->num_ott_boxes + config->num_ttt_boxes) >
95
48
              MAX_RESIDUAL_CHANNELS)
96
4
            return IA_FATAL_ERROR;
97
114
          for (j = 0; j < config->num_ott_boxes + config->num_ttt_boxes; j++) {
98
72
            config->bs_residual_present[j] =
99
72
                ixheaacd_read_bits_buf(it_bit_buff, 1);
100
72
            if (config->bs_residual_present[j]) {
101
23
              config->bs_residual_bands_ld_mps[j] =
102
23
                  ixheaacd_read_bits_buf(it_bit_buff, 5);
103
23
              if (config->bs_residual_bands_ld_mps[j] > MAX_PARAMETER_BANDS)
104
2
              {
105
2
                return IA_FATAL_ERROR;
106
2
              }
107
23
            }
108
72
          }
109
42
          break;
110
111
54
        case 1:
112
54
          config->bs_arbitrary_downmix = 2;
113
114
54
          config->bs_arbitrary_downmix_residual_sampling_freq_index =
115
54
              ixheaacd_read_bits_buf(it_bit_buff, 4);
116
54
          if (config->bs_arbitrary_downmix_residual_sampling_freq_index > MAX_RES_SAMP_FREQ_IDX) {
117
1
            return IA_FATAL_ERROR;
118
1
          }
119
53
          config->bs_arbitrary_downmix_residual_frames_per_spatial_frame =
120
53
              ixheaacd_read_bits_buf(it_bit_buff, 2);
121
53
          config->bs_arbitrary_downmix_residual_bands =
122
53
              ixheaacd_read_bits_buf(it_bit_buff, 5);
123
53
          if (config->bs_arbitrary_downmix_residual_bands >=
124
53
              ixheaacd_freq_res_table[config->bs_freq_res]) {
125
1
            return IA_FATAL_ERROR;
126
1
          }
127
128
52
          break;
129
130
250
        case 2:
131
250
          config->num_out_chan_AT = 0;
132
250
          config->num_ott_boxes_AT = 0;
133
250
          if (config->num_output_channels > MAX_OUTPUT_CHANNELS)
134
1
            return IA_FATAL_ERROR;
135
1.58k
          for (ch = 0; ch < config->num_output_channels; ch++) {
136
1.33k
            tmp_open = 1;
137
1.33k
            idx = 0;
138
5.55k
            while ((tmp_open > 0) && (idx < MAX_ARBITRARY_TREE_INDEX)) {
139
4.21k
              config->bs_ott_box_present_AT[ch][idx] =
140
4.21k
                  ixheaacd_read_bits_buf(it_bit_buff, 1);
141
4.21k
              if (config->bs_ott_box_present_AT[ch][idx]) {
142
2.93k
                config->num_ott_boxes_AT++;
143
2.93k
                tmp_open++;
144
2.93k
              } else {
145
1.28k
                config->num_out_chan_AT++;
146
1.28k
                tmp_open--;
147
1.28k
              }
148
4.21k
              idx++;
149
4.21k
            }
150
1.33k
          }
151
152
3.07k
          for (i = 0; i < config->num_ott_boxes_AT; i++) {
153
2.82k
            config->bs_ott_default_cld_AT[i] =
154
2.82k
                ixheaacd_read_bits_buf(it_bit_buff, 1);
155
2.82k
            config->bs_ott_mode_lfe_AT[i] =
156
2.82k
                ixheaacd_read_bits_buf(it_bit_buff, 1);
157
2.82k
            if (config->bs_ott_mode_lfe_AT[i]) {
158
1.15k
              config->bs_ott_bands_AT[i] =
159
1.15k
                  ixheaacd_read_bits_buf(it_bit_buff, 5);
160
1.67k
            } else {
161
1.67k
              config->bs_ott_bands_AT[i] = ixheaacd_freq_res_table[config->bs_freq_res];
162
1.67k
            }
163
2.82k
          }
164
165
1.44k
          for (i = 0; i < config->num_out_chan_AT; i++) {
166
1.19k
            config->bs_output_channel_pos_AT[i] =
167
1.19k
                ixheaacd_read_bits_buf(it_bit_buff, 5);
168
1.19k
          }
169
170
249
          break;
171
172
4.83k
        default:;
173
5.18k
      }
174
5.18k
    }
175
176
8.62k
    bits_read = tmp - it_bit_buff->cnt_bits;
177
8.62k
    n_fill_bits = 8 * sac_ext_len - bits_read;
178
179
1.86M
    while (n_fill_bits > 7) {
180
1.85M
      ixheaacd_read_bits_buf(it_bit_buff, 8);
181
1.85M
      n_fill_bits -= 8;
182
1.85M
    }
183
8.62k
    if (n_fill_bits > 0) {
184
229
      ixheaacd_read_bits_buf(it_bit_buff, n_fill_bits);
185
229
    }
186
187
8.62k
    ba -= 8 * sac_ext_len;
188
8.62k
    config->sac_ext_cnt++;
189
8.62k
  }
190
1.39k
  return IA_NO_ERROR;
191
1.44k
}
192
193
IA_ERRORCODE ixheaacd_ld_spatial_specific_config(
194
1.49k
    ia_usac_dec_mps_config_struct *config, ia_bit_buf_struct *it_bit_buff) {
195
1.49k
  WORD32 i, num_header_bits;
196
1.49k
  UWORD32 hc, hb;
197
1.49k
  WORD32 sac_header_len;
198
1.49k
  WORD32 bits_available;
199
1.49k
  WORD32 tmp = it_bit_buff->cnt_bits;
200
1.49k
  WORD32 err = 0;
201
202
1.49k
  sac_header_len = tmp;
203
204
1.49k
  bits_available = sac_header_len;
205
1.49k
  config->bs_sampling_freq_index = ixheaacd_read_bits_buf(it_bit_buff, 4);
206
1.49k
  if (config->bs_sampling_freq_index == 15) {
207
11
    config->bs_fampling_frequency = ixheaacd_read_bits_buf(it_bit_buff, 24);
208
11
  }
209
210
1.49k
  config->bs_frame_length = ixheaacd_read_bits_buf(it_bit_buff, 5);
211
1.49k
  config->bs_freq_res = ixheaacd_read_bits_buf(it_bit_buff, 3);
212
1.49k
  config->bs_tree_config = ixheaacd_read_bits_buf(it_bit_buff, 4);
213
214
1.49k
  if (config->bs_tree_config > 7) return IA_FATAL_ERROR;
215
216
1.49k
  if (config->bs_tree_config != 15) {
217
1.49k
    config->num_ott_boxes =
218
1.49k
        ixheaacd_tree_property_table[config->bs_tree_config].num_ott_boxes;
219
1.49k
    config->num_ttt_boxes =
220
1.49k
        ixheaacd_tree_property_table[config->bs_tree_config].num_ttt_boxes;
221
1.49k
    config->num_input_channels =
222
1.49k
        ixheaacd_tree_property_table[config->bs_tree_config].num_input_chan;
223
1.49k
    config->num_output_channels =
224
1.49k
        ixheaacd_tree_property_table[config->bs_tree_config].num_output_chan;
225
8.94k
    for (i = 0; i < MAX_NUM_OTT; i++) {
226
7.45k
      config->ott_mode_lfe[i] =
227
7.45k
          ixheaacd_tree_property_table[config->bs_tree_config].ott_mode_lfe[i];
228
7.45k
    }
229
1.49k
  }
230
1.49k
  config->bs_quant_mode = ixheaacd_read_bits_buf(it_bit_buff, 2);
231
1.49k
  if (config->bs_tree_config != 7) {
232
1.25k
    config->bs_one_icc = ixheaacd_read_bits_buf(it_bit_buff, 1);
233
1.25k
  }
234
1.49k
  config->bs_arbitrary_downmix = ixheaacd_read_bits_buf(it_bit_buff, 1);
235
1.49k
  if (config->bs_tree_config != 7) {
236
1.25k
    config->bs_fixed_gain_sur = ixheaacd_read_bits_buf(it_bit_buff, 3);
237
1.25k
    config->bs_fixed_gain_LFE = ixheaacd_read_bits_buf(it_bit_buff, 3);
238
1.25k
  }
239
1.49k
  config->bs_fixed_gain_dmx = ixheaacd_read_bits_buf(it_bit_buff, 3);
240
1.49k
  if (config->bs_tree_config != 7) {
241
1.25k
    config->bs_matrix_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
242
1.25k
  }
243
1.49k
  config->bs_temp_shape_config = ixheaacd_read_bits_buf(it_bit_buff, 2);
244
1.49k
  config->bs_decorr_config = ixheaacd_read_bits_buf(it_bit_buff, 2);
245
1.49k
  if (config->bs_tree_config != 7) {
246
1.25k
    config->bs_3D_audio_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
247
1.25k
  } else {
248
244
    config->bs_3D_audio_mode = 0;
249
244
  }
250
251
  // ott_config
252
6.45k
  for (i = 0; i < config->num_ott_boxes; i++) {
253
4.96k
    if (config->ott_mode_lfe[i]) {
254
869
      config->bs_ott_bands[i] = ixheaacd_read_bits_buf(it_bit_buff, 5);
255
4.09k
    } else {
256
4.09k
      config->bs_ott_bands[i] = ixheaacd_freq_res_table[config->bs_freq_res];
257
4.09k
    }
258
4.96k
  }
259
260
  // ttt_config
261
1.69k
  for (i = 0; i < config->num_ttt_boxes; i++) {
262
199
    config->bs_ttt_dual_mode[i] = ixheaacd_read_bits_buf(it_bit_buff, 1);
263
199
    config->bs_ttt_mode_low[i] = ixheaacd_read_bits_buf(it_bit_buff, 3);
264
199
    if (config->bs_ttt_dual_mode[i]) {
265
7
      config->bs_ttt_mode_high[i] = ixheaacd_read_bits_buf(it_bit_buff, 3);
266
7
      config->bs_ttt_bands_low[i] = ixheaacd_read_bits_buf(it_bit_buff, 5);
267
7
      config->bs_ttt_bands_high[i] = ixheaacd_freq_res_table[config->bs_freq_res];
268
192
    } else {
269
192
      config->bs_ttt_bands_low[i] = ixheaacd_freq_res_table[config->bs_freq_res];
270
192
    }
271
199
  }
272
273
1.49k
  if (config->bs_temp_shape_config == 2) {
274
318
    config->bs_env_quant_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
275
318
  }
276
277
1.49k
  if (config->bs_3D_audio_mode) {
278
242
    config->bs_3D_audio_HRTF_set = ixheaacd_read_bits_buf(it_bit_buff, 2);
279
    // param_HRTF_set
280
242
    if (config->bs_3D_audio_HRTF_set == 0) {
281
71
      config->bs_HRTF_freq_res = ixheaacd_read_bits_buf(it_bit_buff, 3);
282
71
      config->bs_HRTF_num_chan = 5;
283
71
      config->bs_HRTF_asymmetric = ixheaacd_read_bits_buf(it_bit_buff, 1);
284
285
71
      config->HRTF_num_band = ixheaacd_hrtf_freq_res_table[0][config->bs_HRTF_freq_res];
286
71
      config->HRTF_num_phase = ixheaacd_hrtf_freq_res_table[1][config->bs_HRTF_freq_res];
287
288
303
      for (hc = 0; hc < config->bs_HRTF_num_chan; hc++) {
289
1.86k
        for (hb = 0; hb < config->HRTF_num_band; hb++) {
290
1.63k
          config->bs_HRTF_level_left[hc][hb] =
291
1.63k
              ixheaacd_read_bits_buf(it_bit_buff, 6);
292
1.63k
        }
293
1.77k
        for (hb = 0; hb < config->HRTF_num_band; hb++) {
294
1.54k
          config->bs_HRTF_level_right[hc][hb] =
295
1.54k
              config->bs_HRTF_asymmetric
296
1.54k
                  ? ixheaacd_read_bits_buf(it_bit_buff, 6)
297
1.54k
                  : config->bs_HRTF_level_left[hc][hb];
298
1.54k
        }
299
232
        config->bs_HRTF_phase[hc] = ixheaacd_read_bits_buf(it_bit_buff, 1);
300
1.11k
        for (hb = 0; hb < config->HRTF_num_phase; hb++) {
301
886
          config->bs_HRTF_phase_LR[hc][hb] =
302
886
              config->bs_HRTF_phase[hc] ? ixheaacd_read_bits_buf(it_bit_buff, 6)
303
886
                                        : 0;
304
886
        }
305
232
        config->bs_HRTF_icc[hc] = ixheaacd_read_bits_buf(it_bit_buff, 1);
306
232
        if (config->bs_HRTF_icc[hc]) {
307
577
          for (hb = 0; hb < config->HRTF_num_band; hb++)
308
505
            config->bs_HRTF_icc_LR[hc][hb] =
309
505
                ixheaacd_read_bits_buf(it_bit_buff, 3);
310
72
        }
311
232
      }
312
71
    }
313
242
  }
314
315
  // byte_align
316
1.49k
  i = (it_bit_buff->cnt_bits & 0x7);
317
1.49k
  ixheaacd_read_bits_buf(it_bit_buff, i);
318
319
1.49k
  num_header_bits = tmp - (it_bit_buff->cnt_bits);
320
1.49k
  bits_available -= num_header_bits;
321
322
1.49k
  err =
323
1.49k
      ixheaacd_ld_spatial_extension_config(it_bit_buff, config, bits_available);
324
1.49k
  return err;
325
1.49k
}