Coverage Report

Created: 2026-01-25 06:51

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/libxaac/decoder/ixheaacd_ld_mps_config.c
Line
Count
Source
1
/******************************************************************************
2
*                                                                            *
3
* Copyright (C) 2018 The Android Open Source Project
4
*
5
* Licensed under the Apache License, Version 2.0 (the "License");
6
* you may not use this file except in compliance with the License.
7
* You may obtain a copy of the License at:
8
*
9
* http://www.apache.org/licenses/LICENSE-2.0
10
*
11
* Unless required by applicable law or agreed to in writing, software
12
* distributed under the License is distributed on an "AS IS" BASIS,
13
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14
* See the License for the specific language governing permissions and
15
* limitations under the License.
16
*
17
*****************************************************************************
18
* Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19
*/
20
#include "ixheaac_type_def.h"
21
#include "ixheaac_constants.h"
22
#include "ixheaac_error_standards.h"
23
24
#include "ixheaacd_bitbuffer.h"
25
#include "ixheaacd_config.h"
26
27
#include <assert.h>
28
29
#ifndef sign
30
#define sign(a) (((a) > 0) ? 1 : ((a) < 0) ? -1 : 0)
31
#endif
32
33
typedef struct {
34
  WORD32 num_input_chan;
35
  WORD32 num_output_chan;
36
  WORD32 num_ott_boxes;
37
  WORD32 num_ttt_boxes;
38
  WORD32 ott_mode_lfe[MAX_NUM_OTT];
39
} ia_ld_mps_dec_tree_properties_struct;
40
41
static WORD32 ixheaacd_freq_res_table[] = {0, 23, 15, 12, 9, 7, 5, 4};
42
43
static WORD32 ixheaacd_hrtf_freq_res_table[][8] = {{0, 28, 20, 14, 10, 7, 5, 4},
44
                                          {0, 13, 13, 8, 7, 4, 3, 3}};
45
46
static ia_ld_mps_dec_tree_properties_struct ixheaacd_tree_property_table[] = {
47
    {1, 6, 5, 0, {0, 0, 0, 0, 1}}, {1, 6, 5, 0, {0, 0, 1, 0, 0}}, {2, 6, 3, 1, {1, 0, 0, 0, 0}},
48
    {2, 8, 5, 1, {1, 0, 0, 0, 0}}, {2, 8, 5, 1, {1, 0, 0, 0, 0}}, {6, 8, 2, 0, {0, 0, 0, 0, 0}},
49
    {6, 8, 2, 0, {0, 0, 0, 0, 0}}, {1, 2, 1, 0, {0, 0, 0, 0, 0}}};
50
51
static IA_ERRORCODE ixheaacd_ld_spatial_extension_config(
52
    ia_bit_buf_struct *it_bit_buff, ia_usac_dec_mps_config_struct *config,
53
1.21k
    WORD32 bits_available) {
54
1.21k
  WORD32 j, ch, idx, tmp, tmp_open, sac_ext_len, bits_read, n_fill_bits;
55
1.21k
  UWORD32 i;
56
1.21k
  WORD32 ba = bits_available;
57
58
1.21k
  config->sac_ext_cnt = 0;
59
60
1.21k
  tmp = it_bit_buff->cnt_bits;
61
62
8.44k
  while (ba >= 8) {
63
7.27k
    if (config->sac_ext_cnt >= MAX_NUM_EXT_TYPES) return IA_FATAL_ERROR;
64
65
7.26k
    config->bs_sac_ext_type[config->sac_ext_cnt] =
66
7.26k
        ixheaacd_read_bits_buf(it_bit_buff, 4);
67
7.26k
    ba -= 4;
68
69
7.26k
    sac_ext_len = ixheaacd_read_bits_buf(it_bit_buff, 4);
70
7.26k
    ba -= 4;
71
72
7.26k
    if ((ba >= 6) && (sac_ext_len > 0)) {
73
4.30k
      if (sac_ext_len == 15) {
74
2.32k
        sac_ext_len += ixheaacd_read_bits_buf(it_bit_buff, 8);
75
2.32k
        ba -= 8;
76
2.32k
        if (sac_ext_len == 15 + 255) {
77
784
          sac_ext_len += ixheaacd_read_bits_buf(it_bit_buff, 16);
78
784
          ba -= 16;
79
784
        }
80
2.32k
      }
81
82
4.30k
      switch (config->bs_sac_ext_type[config->sac_ext_cnt]) {
83
54
        case 0:
84
54
          config->bs_residual_coding = 1;
85
86
54
          config->bs_residual_sampling_freq_index =
87
54
              ixheaacd_read_bits_buf(it_bit_buff, 4);
88
54
          if (config->bs_residual_sampling_freq_index > MAX_RES_SAMP_FREQ_IDX) {
89
4
            return IA_FATAL_ERROR;
90
4
          }
91
50
          config->bs_residual_frames_per_spatial_frame =
92
50
              ixheaacd_read_bits_buf(it_bit_buff, 2);
93
94
50
          if ((config->num_ott_boxes + config->num_ttt_boxes) >
95
50
              MAX_RESIDUAL_CHANNELS)
96
2
            return IA_FATAL_ERROR;
97
118
          for (j = 0; j < config->num_ott_boxes + config->num_ttt_boxes; j++) {
98
71
            config->bs_residual_present[j] =
99
71
                ixheaacd_read_bits_buf(it_bit_buff, 1);
100
71
            if (config->bs_residual_present[j]) {
101
20
              config->bs_residual_bands_ld_mps[j] =
102
20
                  ixheaacd_read_bits_buf(it_bit_buff, 5);
103
20
              if (config->bs_residual_bands_ld_mps[j] > MAX_PARAMETER_BANDS)
104
1
              {
105
1
                return IA_FATAL_ERROR;
106
1
              }
107
20
            }
108
71
          }
109
47
          break;
110
111
47
        case 1:
112
38
          config->bs_arbitrary_downmix = 2;
113
114
38
          config->bs_arbitrary_downmix_residual_sampling_freq_index =
115
38
              ixheaacd_read_bits_buf(it_bit_buff, 4);
116
38
          if (config->bs_arbitrary_downmix_residual_sampling_freq_index > MAX_RES_SAMP_FREQ_IDX) {
117
1
            return IA_FATAL_ERROR;
118
1
          }
119
37
          config->bs_arbitrary_downmix_residual_frames_per_spatial_frame =
120
37
              ixheaacd_read_bits_buf(it_bit_buff, 2);
121
37
          config->bs_arbitrary_downmix_residual_bands =
122
37
              ixheaacd_read_bits_buf(it_bit_buff, 5);
123
37
          if (config->bs_arbitrary_downmix_residual_bands >=
124
37
              ixheaacd_freq_res_table[config->bs_freq_res]) {
125
2
            return IA_FATAL_ERROR;
126
2
          }
127
128
35
          break;
129
130
218
        case 2:
131
218
          config->num_out_chan_AT = 0;
132
218
          config->num_ott_boxes_AT = 0;
133
218
          if (config->num_output_channels > MAX_OUTPUT_CHANNELS)
134
1
            return IA_FATAL_ERROR;
135
1.38k
          for (ch = 0; ch < config->num_output_channels; ch++) {
136
1.17k
            tmp_open = 1;
137
1.17k
            idx = 0;
138
5.16k
            while ((tmp_open > 0) && (idx < MAX_ARBITRARY_TREE_INDEX)) {
139
3.99k
              config->bs_ott_box_present_AT[ch][idx] =
140
3.99k
                  ixheaacd_read_bits_buf(it_bit_buff, 1);
141
3.99k
              if (config->bs_ott_box_present_AT[ch][idx]) {
142
2.92k
                config->num_ott_boxes_AT++;
143
2.92k
                tmp_open++;
144
2.92k
              } else {
145
1.06k
                config->num_out_chan_AT++;
146
1.06k
                tmp_open--;
147
1.06k
              }
148
3.99k
              idx++;
149
3.99k
            }
150
1.17k
          }
151
152
3.05k
          for (i = 0; i < config->num_ott_boxes_AT; i++) {
153
2.83k
            config->bs_ott_default_cld_AT[i] =
154
2.83k
                ixheaacd_read_bits_buf(it_bit_buff, 1);
155
2.83k
            config->bs_ott_mode_lfe_AT[i] =
156
2.83k
                ixheaacd_read_bits_buf(it_bit_buff, 1);
157
2.83k
            if (config->bs_ott_mode_lfe_AT[i]) {
158
1.11k
              config->bs_ott_bands_AT[i] =
159
1.11k
                  ixheaacd_read_bits_buf(it_bit_buff, 5);
160
1.72k
            } else {
161
1.72k
              config->bs_ott_bands_AT[i] = ixheaacd_freq_res_table[config->bs_freq_res];
162
1.72k
            }
163
2.83k
          }
164
165
1.20k
          for (i = 0; i < config->num_out_chan_AT; i++) {
166
992
            config->bs_output_channel_pos_AT[i] =
167
992
                ixheaacd_read_bits_buf(it_bit_buff, 5);
168
992
          }
169
170
217
          break;
171
172
3.99k
        default:;
173
4.30k
      }
174
4.30k
    }
175
176
7.23k
    bits_read = tmp - it_bit_buff->cnt_bits;
177
7.23k
    n_fill_bits = 8 * sac_ext_len - bits_read;
178
179
1.34M
    while (n_fill_bits > 7) {
180
1.34M
      ixheaacd_read_bits_buf(it_bit_buff, 8);
181
1.34M
      n_fill_bits -= 8;
182
1.34M
    }
183
7.23k
    if (n_fill_bits > 0) {
184
198
      ixheaacd_read_bits_buf(it_bit_buff, n_fill_bits);
185
198
    }
186
187
7.23k
    ba -= 8 * sac_ext_len;
188
7.23k
    config->sac_ext_cnt++;
189
7.23k
  }
190
1.16k
  return IA_NO_ERROR;
191
1.21k
}
192
193
IA_ERRORCODE ixheaacd_ld_spatial_specific_config(
194
1.26k
    ia_usac_dec_mps_config_struct *config, ia_bit_buf_struct *it_bit_buff) {
195
1.26k
  WORD32 i, num_header_bits;
196
1.26k
  UWORD32 hc, hb;
197
1.26k
  WORD32 sac_header_len;
198
1.26k
  WORD32 bits_available;
199
1.26k
  WORD32 tmp = it_bit_buff->cnt_bits;
200
1.26k
  WORD32 err = 0;
201
202
1.26k
  sac_header_len = tmp;
203
204
1.26k
  bits_available = sac_header_len;
205
1.26k
  config->bs_sampling_freq_index = ixheaacd_read_bits_buf(it_bit_buff, 4);
206
1.26k
  if (config->bs_sampling_freq_index == 15) {
207
12
    config->bs_fampling_frequency = ixheaacd_read_bits_buf(it_bit_buff, 24);
208
12
  }
209
210
1.26k
  config->bs_frame_length = ixheaacd_read_bits_buf(it_bit_buff, 5);
211
1.26k
  config->bs_freq_res = ixheaacd_read_bits_buf(it_bit_buff, 3);
212
1.26k
  config->bs_tree_config = ixheaacd_read_bits_buf(it_bit_buff, 4);
213
214
1.26k
  if (config->bs_tree_config > 7) return IA_FATAL_ERROR;
215
216
1.26k
  if (config->bs_tree_config != 15) {
217
1.26k
    config->num_ott_boxes =
218
1.26k
        ixheaacd_tree_property_table[config->bs_tree_config].num_ott_boxes;
219
1.26k
    config->num_ttt_boxes =
220
1.26k
        ixheaacd_tree_property_table[config->bs_tree_config].num_ttt_boxes;
221
1.26k
    config->num_input_channels =
222
1.26k
        ixheaacd_tree_property_table[config->bs_tree_config].num_input_chan;
223
1.26k
    config->num_output_channels =
224
1.26k
        ixheaacd_tree_property_table[config->bs_tree_config].num_output_chan;
225
7.58k
    for (i = 0; i < MAX_NUM_OTT; i++) {
226
6.32k
      config->ott_mode_lfe[i] =
227
6.32k
          ixheaacd_tree_property_table[config->bs_tree_config].ott_mode_lfe[i];
228
6.32k
    }
229
1.26k
  }
230
1.26k
  config->bs_quant_mode = ixheaacd_read_bits_buf(it_bit_buff, 2);
231
1.26k
  if (config->bs_tree_config != 7) {
232
1.05k
    config->bs_one_icc = ixheaacd_read_bits_buf(it_bit_buff, 1);
233
1.05k
  }
234
1.26k
  config->bs_arbitrary_downmix = ixheaacd_read_bits_buf(it_bit_buff, 1);
235
1.26k
  if (config->bs_tree_config != 7) {
236
1.05k
    config->bs_fixed_gain_sur = ixheaacd_read_bits_buf(it_bit_buff, 3);
237
1.05k
    config->bs_fixed_gain_LFE = ixheaacd_read_bits_buf(it_bit_buff, 3);
238
1.05k
  }
239
1.26k
  config->bs_fixed_gain_dmx = ixheaacd_read_bits_buf(it_bit_buff, 3);
240
1.26k
  if (config->bs_tree_config != 7) {
241
1.05k
    config->bs_matrix_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
242
1.05k
  }
243
1.26k
  config->bs_temp_shape_config = ixheaacd_read_bits_buf(it_bit_buff, 2);
244
1.26k
  config->bs_decorr_config = ixheaacd_read_bits_buf(it_bit_buff, 2);
245
1.26k
  if (config->bs_tree_config != 7) {
246
1.05k
    config->bs_3D_audio_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
247
1.05k
  } else {
248
215
    config->bs_3D_audio_mode = 0;
249
215
  }
250
251
  // ott_config
252
5.39k
  for (i = 0; i < config->num_ott_boxes; i++) {
253
4.12k
    if (config->ott_mode_lfe[i]) {
254
701
      config->bs_ott_bands[i] = ixheaacd_read_bits_buf(it_bit_buff, 5);
255
3.42k
    } else {
256
3.42k
      config->bs_ott_bands[i] = ixheaacd_freq_res_table[config->bs_freq_res];
257
3.42k
    }
258
4.12k
  }
259
260
  // ttt_config
261
1.43k
  for (i = 0; i < config->num_ttt_boxes; i++) {
262
165
    config->bs_ttt_dual_mode[i] = ixheaacd_read_bits_buf(it_bit_buff, 1);
263
165
    config->bs_ttt_mode_low[i] = ixheaacd_read_bits_buf(it_bit_buff, 3);
264
165
    if (config->bs_ttt_dual_mode[i]) {
265
9
      config->bs_ttt_mode_high[i] = ixheaacd_read_bits_buf(it_bit_buff, 3);
266
9
      config->bs_ttt_bands_low[i] = ixheaacd_read_bits_buf(it_bit_buff, 5);
267
9
      config->bs_ttt_bands_high[i] = ixheaacd_freq_res_table[config->bs_freq_res];
268
156
    } else {
269
156
      config->bs_ttt_bands_low[i] = ixheaacd_freq_res_table[config->bs_freq_res];
270
156
    }
271
165
  }
272
273
1.26k
  if (config->bs_temp_shape_config == 2) {
274
301
    config->bs_env_quant_mode = ixheaacd_read_bits_buf(it_bit_buff, 1);
275
301
  }
276
277
1.26k
  if (config->bs_3D_audio_mode) {
278
207
    config->bs_3D_audio_HRTF_set = ixheaacd_read_bits_buf(it_bit_buff, 2);
279
    // param_HRTF_set
280
207
    if (config->bs_3D_audio_HRTF_set == 0) {
281
80
      config->bs_HRTF_freq_res = ixheaacd_read_bits_buf(it_bit_buff, 3);
282
80
      config->bs_HRTF_num_chan = 5;
283
80
      config->bs_HRTF_asymmetric = ixheaacd_read_bits_buf(it_bit_buff, 1);
284
285
80
      config->HRTF_num_band = ixheaacd_hrtf_freq_res_table[0][config->bs_HRTF_freq_res];
286
80
      config->HRTF_num_phase = ixheaacd_hrtf_freq_res_table[1][config->bs_HRTF_freq_res];
287
288
343
      for (hc = 0; hc < config->bs_HRTF_num_chan; hc++) {
289
1.93k
        for (hb = 0; hb < config->HRTF_num_band; hb++) {
290
1.66k
          config->bs_HRTF_level_left[hc][hb] =
291
1.66k
              ixheaacd_read_bits_buf(it_bit_buff, 6);
292
1.66k
        }
293
1.86k
        for (hb = 0; hb < config->HRTF_num_band; hb++) {
294
1.59k
          config->bs_HRTF_level_right[hc][hb] =
295
1.59k
              config->bs_HRTF_asymmetric
296
1.59k
                  ? ixheaacd_read_bits_buf(it_bit_buff, 6)
297
1.59k
                  : config->bs_HRTF_level_left[hc][hb];
298
1.59k
        }
299
263
        config->bs_HRTF_phase[hc] = ixheaacd_read_bits_buf(it_bit_buff, 1);
300
1.19k
        for (hb = 0; hb < config->HRTF_num_phase; hb++) {
301
928
          config->bs_HRTF_phase_LR[hc][hb] =
302
928
              config->bs_HRTF_phase[hc] ? ixheaacd_read_bits_buf(it_bit_buff, 6)
303
928
                                        : 0;
304
928
        }
305
263
        config->bs_HRTF_icc[hc] = ixheaacd_read_bits_buf(it_bit_buff, 1);
306
263
        if (config->bs_HRTF_icc[hc]) {
307
586
          for (hb = 0; hb < config->HRTF_num_band; hb++)
308
510
            config->bs_HRTF_icc_LR[hc][hb] =
309
510
                ixheaacd_read_bits_buf(it_bit_buff, 3);
310
76
        }
311
263
      }
312
80
    }
313
207
  }
314
315
  // byte_align
316
1.26k
  i = (it_bit_buff->cnt_bits & 0x7);
317
1.26k
  ixheaacd_read_bits_buf(it_bit_buff, i);
318
319
1.26k
  num_header_bits = tmp - (it_bit_buff->cnt_bits);
320
1.26k
  bits_available -= num_header_bits;
321
322
1.26k
  err =
323
1.26k
      ixheaacd_ld_spatial_extension_config(it_bit_buff, config, bits_available);
324
1.26k
  return err;
325
1.26k
}