Coverage Report

Created: 2026-03-21 07:02

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/libxaac/decoder/ixheaacd_mps_reshape_bb_env.c
Line
Count
Source
1
/******************************************************************************
2
 *
3
 * Copyright (C) 2023 The Android Open Source Project
4
 *
5
 * Licensed under the Apache License, Version 2.0 (the "License");
6
 * you may not use this file except in compliance with the License.
7
 * You may obtain a copy of the License at:
8
 *
9
 * http://www.apache.org/licenses/LICENSE-2.0
10
 *
11
 * Unless required by applicable law or agreed to in writing, software
12
 * distributed under the License is distributed on an "AS IS" BASIS,
13
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14
 * See the License for the specific language governing permissions and
15
 * limitations under the License.
16
 *
17
 *****************************************************************************
18
 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19
*/
20
#include "ixheaac_type_def.h"
21
#include "ixheaacd_mps_struct_def.h"
22
#include "ixheaacd_mps_res_rom.h"
23
#include "ixheaacd_mps_aac_struct.h"
24
#include "ixheaac_constants.h"
25
#include "ixheaac_basic_ops32.h"
26
#include "ixheaac_basic_ops40.h"
27
#include "ixheaacd_bitbuffer.h"
28
#include "ixheaacd_error_codes.h"
29
#include "ixheaacd_common_rom.h"
30
#include "ixheaacd_sbrdecsettings.h"
31
#include "ixheaacd_sbr_scale.h"
32
#include "ixheaacd_env_extr_part.h"
33
#include "ixheaacd_sbr_rom.h"
34
#include "ixheaacd_hybrid.h"
35
#include "ixheaacd_ps_dec.h"
36
#include "ixheaacd_mps_polyphase.h"
37
#include "ixheaacd_config.h"
38
#include "ixheaacd_qmf_dec.h"
39
#include "ixheaacd_mps_dec.h"
40
#include "ixheaacd_mps_bitdec.h"
41
#include "ixheaacd_mps_macro_def.h"
42
#include "ixheaacd_mps_basic_op.h"
43
#include "ixheaacd_mps_reshape_bb_env.h"
44
#include "ixheaac_error_standards.h"
45
46
#define ALIGN_SIZE64(x) ((((x) + 7) >> 3) << 3)
47
48
1.11k
VOID ixheaacd_init_bb_env(ia_heaac_mps_state_struct *pstr_mps_state) {
49
1.11k
  WORD32 k, j;
50
1.11k
  ia_mps_dec_reshape_bb_env_state_struct *reshape_bb_env_state =
51
1.11k
      pstr_mps_state->mps_persistent_mem.reshape_bb_env_state;
52
53
25.6k
  for (k = 0; k < 2 * MAX_OUTPUT_CHANNELS_MPS + MAX_INPUT_CHANNELS_MPS; k++) {
54
24.5k
    reshape_bb_env_state->norm_nrg_prev[k] = ONE_IN_Q30;
55
24.5k
    reshape_bb_env_state->frame_nrg_prev[k] = 0;
56
24.5k
    reshape_bb_env_state->q_frame_nrg_prev[k] = 30;
57
24.5k
    reshape_bb_env_state->q_norm_nrg_prev[k] = 30;
58
710k
    for (j = 0; j < MAX_PARAMETER_BANDS; j++) {
59
686k
      reshape_bb_env_state->part_nrg_prev[k][j] = 0;
60
686k
      reshape_bb_env_state->q_part_nrg_prev[k][j] = 30;
61
686k
    }
62
24.5k
  }
63
1.11k
}
64
65
static VOID ixheaacd_extract_bb_env(ia_heaac_mps_state_struct *pstr_mps_state, WORD32 inp,
66
39.5k
                                            WORD32 ch, WORD32 *env, VOID *scratch, WORD32 flag) {
67
39.5k
  ia_mps_dec_reshape_bb_env_state_struct *reshape_bb_env_state =
68
39.5k
      pstr_mps_state->mps_persistent_mem.reshape_bb_env_state;
69
39.5k
  WORD64 *slot_nrg_fix, *slot_nrg;
70
39.5k
  WORD16 *q_slot_nrg_fix, *q_slot_nrg;
71
39.5k
  WORD32 *part_nrg_fix;
72
39.5k
  WORD16 *q_part_nrg_fix;
73
74
39.5k
  WORD32 *p_buffer_real, *p_buffer_imag, *p_buffer_re, *p_buffer_im;
75
39.5k
  WORD32 ts, qs, pb;
76
77
39.5k
  WORD32 start_p = 10;
78
39.5k
  WORD32 end_p = 18;
79
39.5k
  WORD32 env_fix_l;
80
39.5k
  WORD16 q_env_fix_l;
81
82
39.5k
  WORD16 alpha_fix = ALPHA_Q15;
83
39.5k
  WORD16 beta_fix = BETA_Q15;
84
85
39.5k
  WORD16 one_min_alpha_fix = ONE_MINUS_ALPHA_Q16;
86
39.5k
  WORD16 one_min_beta_fix = ONE_MINUS_BETA_Q16;
87
39.5k
  WORD16 one_by_nine = ONE_BY_NINE_Q16;
88
39.5k
  WORD32 frame_nrg_fix = 0;
89
39.5k
  WORD32 *norm_nrg_fix;
90
39.5k
  WORD16 q_frame_nrg_fix = 0;
91
39.5k
  WORD16 *q_norm_nrg_fix;
92
39.5k
  WORD32 temp_1, temp4;
93
39.5k
  WORD16 qtemp1, q_env;
94
95
39.5k
  WORD32 prev_ch_offs;
96
39.5k
  WORD32 cnt = min(42, pstr_mps_state->hybrid_bands);
97
39.5k
  WORD32 time_slots = pstr_mps_state->time_slots;
98
39.5k
  const WORD32 *sqrt_tab = pstr_mps_state->ia_mps_dec_mps_table.common_table_ptr->sqrt_tab;
99
39.5k
  WORD32 *hyb_output_real_dry, *n_slot_nrg;
100
39.5k
  WORD32 *hyb_output_imag_dry;
101
102
39.5k
  const WORD32 *bb_env_kernels =
103
39.5k
      pstr_mps_state->ia_mps_dec_mps_table.bitdec_table_ptr->kernel_table.bb_env_kernels;
104
105
39.5k
  q_slot_nrg_fix = (WORD16 *)scratch;
106
39.5k
  n_slot_nrg =
107
39.5k
      (WORD32 *)((WORD8 *)scratch + IXHEAAC_GET_SIZE_ALIGNED(RESHAPE_OFFSET_1, BYTE_ALIGN_8));
108
39.5k
  slot_nrg_fix =
109
39.5k
      (WORD64 *)((WORD8 *)scratch + IXHEAAC_GET_SIZE_ALIGNED(RESHAPE_OFFSET_2, BYTE_ALIGN_8));
110
39.5k
  switch (inp) {
111
0
    WORD32 frame_nrg_prev;
112
0
    WORD16 q_frame_nrg_prev;
113
0
    WORD32 *p_hyb_out_dry_real, *p_hyb_out_dry_imag;
114
115
26.6k
    case INP_DRY_WET:
116
26.6k
      frame_nrg_prev = reshape_bb_env_state->frame_nrg_prev[ch];
117
26.6k
      q_frame_nrg_prev = reshape_bb_env_state->q_frame_nrg_prev[ch];
118
119
26.6k
      part_nrg_fix = &reshape_bb_env_state->part_nrg_prev[ch][0];
120
26.6k
      q_part_nrg_fix = &reshape_bb_env_state->q_part_nrg_prev[ch][0];
121
122
26.6k
      norm_nrg_fix = &reshape_bb_env_state->norm_nrg_prev[ch];
123
26.6k
      q_norm_nrg_fix = &reshape_bb_env_state->q_norm_nrg_prev[ch];
124
125
26.6k
      p_buffer_real = pstr_mps_state->array_struct->buf_real + ch * TSXHB + 12;
126
26.6k
      p_buffer_imag = pstr_mps_state->array_struct->buf_imag + ch * TSXHB + 12;
127
128
26.6k
      p_hyb_out_dry_real = pstr_mps_state->array_struct->hyb_output_real_dry + ch * TSXHB + 12;
129
26.6k
      p_hyb_out_dry_imag = pstr_mps_state->array_struct->hyb_output_imag_dry + ch * TSXHB + 12;
130
131
788k
      for (ts = 0; ts < time_slots; ts++) {
132
761k
        WORD32 prev_idx = 10;
133
134
761k
        slot_nrg = slot_nrg_fix + 4;
135
4.56M
        for (pb = 14; pb <= end_p; pb++) *slot_nrg++ = 0;
136
137
761k
        slot_nrg = slot_nrg_fix;
138
139
761k
        p_buffer_re = p_buffer_real;
140
761k
        p_buffer_im = p_buffer_imag;
141
142
761k
        hyb_output_real_dry = p_hyb_out_dry_real;
143
761k
        hyb_output_imag_dry = p_hyb_out_dry_imag;
144
145
3.80M
        for (qs = 12; qs < 16; qs++) {
146
3.04M
          temp_1 = ixheaac_add32_sat(*hyb_output_real_dry, *p_buffer_re);
147
3.04M
          temp4 = ixheaac_add32_sat(*hyb_output_imag_dry, *p_buffer_im);
148
149
3.04M
          *slot_nrg++ = ixheaac_add64_sat(ixheaac_mult32x32in64(temp_1, temp_1), 
150
3.04M
                    ixheaac_mult32x32in64(temp4, temp4));
151
152
3.04M
          p_buffer_re++;
153
3.04M
          p_buffer_im++;
154
3.04M
          hyb_output_real_dry++;
155
3.04M
          hyb_output_imag_dry++;
156
3.04M
        }
157
761k
        prev_idx = 14;
158
11.4M
        for (; qs < 30; qs++) {
159
10.6M
          WORD32 idx = bb_env_kernels[qs];
160
10.6M
          if (prev_idx != idx) {
161
2.28M
            slot_nrg++;
162
2.28M
            prev_idx = idx;
163
2.28M
          }
164
10.6M
          temp_1 = ixheaac_add32_sat(*hyb_output_real_dry, *p_buffer_re);
165
10.6M
          temp4 = ixheaac_add32_sat(*hyb_output_imag_dry, *p_buffer_im);
166
167
10.6M
      *slot_nrg = ixheaac_add64_sat(*slot_nrg, ixheaac_mult32x32in64(temp_1, temp_1));
168
10.6M
      *slot_nrg = ixheaac_add64_sat(*slot_nrg, ixheaac_mult32x32in64(temp4, temp4));
169
170
10.6M
          p_buffer_re++;
171
10.6M
          p_buffer_im++;
172
10.6M
          hyb_output_real_dry++;
173
10.6M
          hyb_output_imag_dry++;
174
10.6M
        }
175
761k
        slot_nrg++;
176
9.71M
        for (; qs < cnt; qs++) {
177
8.95M
          temp_1 = ixheaac_add32_sat(*hyb_output_real_dry, *p_buffer_re);
178
8.95M
          temp4 = ixheaac_add32_sat(*hyb_output_imag_dry, *p_buffer_im);
179
180
8.95M
      *slot_nrg = ixheaac_add64_sat(*slot_nrg, ixheaac_mult32x32in64(temp_1, temp_1));
181
8.95M
      *slot_nrg = ixheaac_add64_sat(*slot_nrg, ixheaac_mult32x32in64(temp4, temp4));
182
183
8.95M
          p_buffer_re++;
184
8.95M
          p_buffer_im++;
185
8.95M
          hyb_output_real_dry++;
186
8.95M
          hyb_output_imag_dry++;
187
8.95M
        }
188
189
761k
        slot_nrg = slot_nrg_fix;
190
761k
        q_slot_nrg = q_slot_nrg_fix;
191
192
761k
        frame_nrg_fix = 0;
193
761k
        q_frame_nrg_fix = 30;
194
7.61M
        for (pb = start_p; pb <= end_p; pb++) {
195
6.85M
          *n_slot_nrg = ixheaacd_mps_narrow(*slot_nrg, q_slot_nrg);
196
6.85M
          slot_nrg++;
197
6.85M
          temp_1 = ixheaac_mult32x16in32(*n_slot_nrg, one_min_alpha_fix);
198
6.85M
          temp4 = ixheaac_mult32x16in32((part_nrg_fix[pb]) << 1, alpha_fix);
199
6.85M
          part_nrg_fix[pb] =
200
6.85M
              ixheaacd_mps_reshape_add32(temp4, temp_1, &q_part_nrg_fix[pb], *q_slot_nrg);
201
202
6.85M
          frame_nrg_fix = ixheaacd_mps_reshape_add32(frame_nrg_fix, *n_slot_nrg++,
203
6.85M
                                                     &q_frame_nrg_fix, *q_slot_nrg++);
204
6.85M
        }
205
206
761k
        frame_nrg_fix = ixheaac_mult32x16in32(frame_nrg_fix, one_by_nine);
207
208
761k
        temp_1 = ixheaac_mult32x16in32(frame_nrg_fix, one_min_alpha_fix);
209
761k
        temp4 = ixheaac_mult32x16in32((frame_nrg_prev) << 1, alpha_fix);
210
761k
        frame_nrg_fix =
211
761k
            ixheaacd_mps_reshape_add32(temp_1, temp4, &q_frame_nrg_fix, q_frame_nrg_prev);
212
213
761k
        frame_nrg_prev = frame_nrg_fix;
214
761k
        q_frame_nrg_prev = q_frame_nrg_fix;
215
216
761k
        env_fix_l = 0;
217
761k
        q_env_fix_l = 30;
218
761k
        q_slot_nrg = q_slot_nrg_fix;
219
220
761k
        n_slot_nrg -= PB_OFFSET;
221
7.61M
        for (pb = start_p; pb <= end_p; pb++) {
222
6.85M
          temp_1 = ixheaacd_mps_div_32(*n_slot_nrg++, part_nrg_fix[pb], &qtemp1);
223
6.85M
          qtemp1 = *q_slot_nrg++ + qtemp1 - q_part_nrg_fix[pb];
224
6.85M
          env_fix_l = ixheaacd_mps_reshape_add32(env_fix_l, temp_1, &q_env_fix_l, qtemp1);
225
6.85M
        }
226
761k
        n_slot_nrg -= PB_OFFSET;
227
228
761k
        env_fix_l =
229
761k
            ixheaacd_mps_mult32x32(env_fix_l, frame_nrg_fix, &q_env_fix_l, q_frame_nrg_fix);
230
231
761k
        temp_1 = ixheaac_mult32x16in32(env_fix_l, one_min_beta_fix);
232
761k
        temp4 = ixheaac_mult32x16in32((*norm_nrg_fix) << 1, beta_fix);
233
761k
        *norm_nrg_fix = ixheaacd_mps_reshape_add32(temp4, temp_1, q_norm_nrg_fix, q_env_fix_l);
234
235
761k
        if (flag) {
236
26.9k
          temp_1 = ixheaacd_mps_div_32(env_fix_l, *norm_nrg_fix, &qtemp1);
237
26.9k
          q_env = q_env_fix_l + qtemp1 - *q_norm_nrg_fix;
238
26.9k
          env[ts] = ixheaacd_mps_sqrt(temp_1, &(q_env), sqrt_tab);
239
26.9k
          env[ts] = ixheaacd_mps_convert_to_qn(env[ts], q_env, 15);
240
26.9k
        }
241
242
761k
        p_buffer_real += MAX_HYBRID_BANDS;
243
761k
        p_buffer_imag += MAX_HYBRID_BANDS;
244
245
761k
        p_hyb_out_dry_real += MAX_HYBRID_BANDS;
246
761k
        p_hyb_out_dry_imag += MAX_HYBRID_BANDS;
247
761k
      }
248
26.6k
      reshape_bb_env_state->frame_nrg_prev[ch] = frame_nrg_prev;
249
26.6k
      reshape_bb_env_state->q_frame_nrg_prev[ch] = q_frame_nrg_prev;
250
251
26.6k
      break;
252
12.8k
    case INP_DMX:
253
12.8k
      prev_ch_offs = ch + pstr_mps_state->num_output_channels;
254
255
12.8k
      frame_nrg_prev = reshape_bb_env_state->frame_nrg_prev[prev_ch_offs];
256
12.8k
      q_frame_nrg_prev = reshape_bb_env_state->q_frame_nrg_prev[prev_ch_offs];
257
258
12.8k
      part_nrg_fix = &reshape_bb_env_state->part_nrg_prev[prev_ch_offs][0];
259
12.8k
      q_part_nrg_fix = &reshape_bb_env_state->q_part_nrg_prev[prev_ch_offs][0];
260
261
12.8k
      norm_nrg_fix = &reshape_bb_env_state->norm_nrg_prev[prev_ch_offs];
262
12.8k
      q_norm_nrg_fix = &reshape_bb_env_state->q_norm_nrg_prev[prev_ch_offs];
263
264
12.8k
      p_buffer_real = pstr_mps_state->array_struct->x_real + ch * TSXHB + 12;
265
12.8k
      p_buffer_imag = pstr_mps_state->array_struct->x_imag + ch * TSXHB + 12;
266
382k
      for (ts = 0; ts < time_slots; ts++) {
267
369k
        WORD32 prev_idx;
268
269
369k
        slot_nrg = slot_nrg_fix + 4;
270
2.21M
        for (pb = 14; pb <= end_p; pb++) *slot_nrg++ = 0;
271
272
369k
        slot_nrg = slot_nrg_fix;
273
274
369k
        hyb_output_real_dry = p_buffer_real;
275
369k
        hyb_output_imag_dry = p_buffer_imag;
276
277
1.84M
        for (qs = 12; qs < 16; qs++) {
278
1.47M
          *slot_nrg++ = ixheaac_add64_sat(ixheaac_mult32x32in64(*hyb_output_real_dry, *hyb_output_real_dry), 
279
1.47M
                    ixheaac_mult32x32in64(*hyb_output_imag_dry, *hyb_output_imag_dry));
280
281
1.47M
          hyb_output_real_dry++;
282
1.47M
          hyb_output_imag_dry++;
283
1.47M
        }
284
369k
        prev_idx = 14;
285
5.54M
        for (; qs < 30; qs++) {
286
5.17M
          WORD32 idx = bb_env_kernels[qs];
287
5.17M
          if (prev_idx != idx) {
288
1.10M
            slot_nrg++;
289
1.10M
            prev_idx = idx;
290
1.10M
          }
291
292
5.17M
      *slot_nrg = ixheaac_add64_sat(*slot_nrg, ixheaac_mult32x32in64(*hyb_output_real_dry, *hyb_output_real_dry));
293
5.17M
      *slot_nrg = ixheaac_add64_sat(*slot_nrg, ixheaac_mult32x32in64(*hyb_output_imag_dry, *hyb_output_imag_dry));
294
295
5.17M
          hyb_output_real_dry++;
296
5.17M
          hyb_output_imag_dry++;
297
5.17M
        }
298
369k
        slot_nrg++;
299
4.74M
        for (; qs < cnt; qs++) {
300
4.37M
      *slot_nrg = ixheaac_add64_sat(*slot_nrg, ixheaac_mult32x32in64(*hyb_output_real_dry, *hyb_output_real_dry));
301
4.37M
      *slot_nrg = ixheaac_add64_sat(*slot_nrg, ixheaac_mult32x32in64(*hyb_output_imag_dry, *hyb_output_imag_dry));
302
303
4.37M
          hyb_output_real_dry++;
304
4.37M
          hyb_output_imag_dry++;
305
4.37M
        }
306
307
369k
        slot_nrg = slot_nrg_fix;
308
369k
        q_slot_nrg = q_slot_nrg_fix;
309
310
369k
        frame_nrg_fix = 0;
311
369k
        q_frame_nrg_fix = 30;
312
3.69M
        for (pb = start_p; pb <= end_p; pb++) {
313
3.32M
          *n_slot_nrg = ixheaacd_mps_narrow(*slot_nrg, q_slot_nrg);
314
3.32M
          slot_nrg++;
315
3.32M
          temp_1 = ixheaac_mult32x16in32(*n_slot_nrg, one_min_alpha_fix);
316
3.32M
          temp4 = ixheaac_mult32x16in32((part_nrg_fix[pb]) << 1, alpha_fix);
317
3.32M
          part_nrg_fix[pb] =
318
3.32M
              ixheaacd_mps_reshape_add32(temp4, temp_1, &q_part_nrg_fix[pb], *q_slot_nrg);
319
3.32M
          frame_nrg_fix = ixheaacd_mps_reshape_add32(frame_nrg_fix, *n_slot_nrg++,
320
3.32M
                                                     &q_frame_nrg_fix, *q_slot_nrg++);
321
3.32M
        }
322
323
369k
        frame_nrg_fix = ixheaac_mult32x16in32(frame_nrg_fix, one_by_nine);
324
325
369k
        temp_1 = ixheaac_mult32x16in32(frame_nrg_fix, one_min_alpha_fix);
326
369k
        temp4 = ixheaac_mult32x16in32((frame_nrg_prev) << 1, alpha_fix);
327
369k
        frame_nrg_fix =
328
369k
            ixheaacd_mps_reshape_add32(temp_1, temp4, &q_frame_nrg_fix, q_frame_nrg_prev);
329
330
369k
        frame_nrg_prev = frame_nrg_fix;
331
369k
        q_frame_nrg_prev = q_frame_nrg_fix;
332
333
369k
        env_fix_l = 0;
334
369k
        q_env_fix_l = 30;
335
336
369k
        q_slot_nrg = q_slot_nrg_fix;
337
369k
        n_slot_nrg -= PB_OFFSET;
338
3.69M
        for (pb = start_p; pb <= end_p; pb++) {
339
3.32M
          temp_1 = ixheaacd_mps_div_32(*n_slot_nrg++, part_nrg_fix[pb], &qtemp1);
340
3.32M
          qtemp1 = *q_slot_nrg++ + qtemp1 - q_part_nrg_fix[pb];
341
3.32M
          env_fix_l = ixheaacd_mps_reshape_add32(env_fix_l, temp_1, &q_env_fix_l, qtemp1);
342
3.32M
        }
343
369k
        n_slot_nrg -= PB_OFFSET;
344
345
369k
        env_fix_l =
346
369k
            ixheaacd_mps_mult32x32(env_fix_l, frame_nrg_fix, &q_env_fix_l, q_frame_nrg_fix);
347
348
369k
        temp_1 = ixheaac_mult32x16in32(env_fix_l, one_min_beta_fix);
349
369k
        temp4 = ixheaac_mult32x16in32((*norm_nrg_fix) << 1, beta_fix);
350
369k
        *norm_nrg_fix = ixheaacd_mps_reshape_add32(temp4, temp_1, q_norm_nrg_fix, q_env_fix_l);
351
352
369k
        temp_1 = ixheaacd_mps_div_32(env_fix_l, *norm_nrg_fix, &qtemp1);
353
369k
        q_env = q_env_fix_l + qtemp1 - *q_norm_nrg_fix;
354
369k
        env[ts] = ixheaacd_mps_sqrt(temp_1, &(q_env), sqrt_tab);
355
369k
        env[ts] = ixheaacd_mps_convert_to_qn(env[ts], q_env, 15);
356
357
369k
        p_buffer_real += MAX_HYBRID_BANDS;
358
369k
        p_buffer_imag += MAX_HYBRID_BANDS;
359
369k
      }
360
12.8k
      reshape_bb_env_state->frame_nrg_prev[prev_ch_offs] = frame_nrg_prev;
361
12.8k
      reshape_bb_env_state->q_frame_nrg_prev[prev_ch_offs] = q_frame_nrg_prev;
362
363
12.8k
      break;
364
0
    default:
365
0
      break;
366
39.5k
  }
367
39.5k
  return;
368
39.5k
}
369
370
6.49k
VOID ixheaacd_reshape_bb_env(ia_heaac_mps_state_struct *pstr_mps_state) {
371
6.49k
  WORD32 *env_dry;
372
6.49k
  WORD32 *env_dmx_0, *env_dmx_1;
373
374
6.49k
  WORD32 *p_buffer_real, *p_buffer_imag, *p_buffer_re, *p_buffer_im;
375
6.49k
  WORD32 *hyb_output_real_wet, *hyb_output_imag_wet;
376
377
6.49k
  WORD32 temp_1, temp_2;
378
6.49k
  WORD16 qtemp1, qtemp2;
379
6.49k
  WORD32 tmp, dry_fac, slot_amp_dry, slot_amp_wet;
380
6.49k
  WORD16 q_dry_fac, q_slot_amp_dry, q_slot_amp_wet;
381
382
6.49k
  WORD32 slot_amp_ratio;
383
6.49k
  WORD16 q_slot_amp_ratio;
384
6.49k
  WORD32 ch, ch2, ts, qs;
385
6.49k
  WORD32 *hyb_output_real_dry, *hyb_out_dry_real;
386
6.49k
  WORD32 *hyb_output_imag_dry, *hyb_out_dry_imag;
387
6.49k
  WORD64 *inter;
388
389
6.49k
  VOID *free_scratch;
390
6.49k
  const WORD32 *sqrt_tab = pstr_mps_state->ia_mps_dec_mps_table.common_table_ptr->sqrt_tab;
391
6.49k
  ia_mps_dec_auxilary_struct *p_aux_struct = pstr_mps_state->aux_struct;
392
6.49k
  WORD32 *temp_shape_enable_channel_ges = p_aux_struct->temp_shape_enable_channel_ges;
393
394
6.49k
  WORD32 start_hsb;
395
6.49k
  WORD32 time_slots = pstr_mps_state->time_slots;
396
6.49k
  WORD32 num_output_channels = pstr_mps_state->num_output_channels;
397
6.49k
  WORD32 tree_config = pstr_mps_state->tree_config;
398
6.49k
  WORD32 hybrid_bands = pstr_mps_state->hybrid_bands;
399
400
6.49k
  const WORD32 *ch_idx = &pstr_mps_state->ia_mps_dec_mps_table.m1_m2_table_ptr->idx_table
401
6.49k
                              .row_2_channel_ges[tree_config][0];
402
6.49k
  WORD64 acc, acc2;
403
6.49k
  start_hsb = 6;
404
405
6.49k
  free_scratch = pstr_mps_state->mps_scratch_mem_v;
406
6.49k
  env_dry = free_scratch;
407
6.49k
  env_dmx_0 = pstr_mps_state->array_struct->env_dmx_0;
408
6.49k
  env_dmx_1 = pstr_mps_state->array_struct->env_dmx_1;
409
6.49k
  inter = (WORD64 *)((WORD8 *)free_scratch +
410
6.49k
                     IXHEAAC_GET_SIZE_ALIGNED(MAX_TIME_SLOTSX12, BYTE_ALIGN_8));
411
6.49k
  free_scratch =
412
6.49k
      inter + IXHEAAC_GET_SIZE_ALIGNED_TYPE(MAX_TIME_SLOTS, sizeof(*inter), BYTE_ALIGN_8);
413
414
6.49k
  p_buffer_real = pstr_mps_state->array_struct->buf_real + start_hsb;
415
6.49k
  p_buffer_imag = pstr_mps_state->array_struct->buf_imag + start_hsb;
416
417
57.8k
  for (ch = 0; ch < num_output_channels; ch++) {
418
51.3k
    ch2 = ch_idx[ch];
419
420
51.3k
    if (ch2 == -1) continue;
421
422
26.6k
    p_buffer_re = p_buffer_real;
423
26.6k
    p_buffer_im = p_buffer_imag;
424
425
26.6k
    ixheaacd_extract_bb_env(pstr_mps_state, INP_DRY_WET, ch, env_dry, free_scratch,
426
26.6k
                                         temp_shape_enable_channel_ges[ch2]);
427
428
26.6k
    if (temp_shape_enable_channel_ges[ch2]) {
429
927
      WORD32 *env = &p_aux_struct->env_shape_data[ch2][0];
430
927
      switch (tree_config) {
431
39
        case TREE_5151:
432
132
        case TREE_5152:
433
3.58k
          for (ts = 0; ts < time_slots; ts++) {
434
3.45k
            inter[ts] = (WORD64)((WORD64)*env++ * (WORD64)env_dmx_0[ts]);
435
3.45k
          }
436
132
          break;
437
438
125
        case TREE_525:
439
290
        case TREE_7271:
440
330
        case TREE_7272:
441
442
330
          switch (ch2) {
443
107
            case 0:
444
144
            case 3:
445
175
            case 5:
446
447
5.59k
              for (ts = 0; ts < time_slots; ts++) {
448
5.42k
                inter[ts] = (WORD64)((WORD64)*env++ * (WORD64)env_dmx_0[ts]);
449
5.42k
              }
450
175
              break;
451
40
            case 1:
452
85
            case 4:
453
113
            case 6:
454
455
3.60k
              for (ts = 0; ts < time_slots; ts++) {
456
3.48k
                inter[ts] = (WORD64)((WORD64)*env++ * (WORD64)env_dmx_1[ts]);
457
3.48k
              }
458
113
              break;
459
42
            case 2:
460
461
1.32k
              for (ts = 0; ts < time_slots; ts++) {
462
1.28k
                temp_2 = ((WORD64)env_dmx_0[ts] + (WORD64)env_dmx_1[ts]) >> 1;
463
1.28k
                inter[ts] = (WORD64)((WORD64)*env++ * (WORD64)temp_2);
464
1.28k
              }
465
42
              break;
466
0
            default:
467
0
              break;
468
330
          }
469
330
          break;
470
471
330
        case TREE_7571:
472
465
        case TREE_7572:
473
465
          switch (ch2) {
474
152
            case 0:
475
278
            case 2:
476
8.35k
              for (ts = 0; ts < time_slots; ts++) {
477
8.07k
                inter[ts] = (WORD64)((WORD64)*env++ * (WORD64)env_dmx_0[ts]);
478
8.07k
              }
479
480
278
              break;
481
133
            case 1:
482
187
            case 3:
483
5.38k
              for (ts = 0; ts < time_slots; ts++) {
484
5.20k
                inter[ts] = (WORD64)((WORD64)*env++ * (WORD64)env_dmx_1[ts]);
485
5.20k
              }
486
187
              break;
487
0
            default:
488
0
              break;
489
465
          }
490
465
        default:
491
465
          break;
492
927
      }
493
494
927
      hyb_out_dry_real =
495
927
          pstr_mps_state->array_struct->hyb_output_real_dry + ch * TSXHB + start_hsb;
496
927
      hyb_out_dry_imag =
497
927
          pstr_mps_state->array_struct->hyb_output_imag_dry + ch * TSXHB + start_hsb;
498
499
27.8k
      for (ts = 0; ts < time_slots; ts++) {
500
26.9k
        tmp = ixheaacd_mps_narrow(inter[ts], &qtemp1);
501
502
26.9k
        if (env_dry[ts] == 0) {
503
11.4k
          q_dry_fac = 0;
504
11.4k
          dry_fac = MAX_32;
505
15.4k
        } else {
506
15.4k
          dry_fac = ixheaacd_mps_div_32(tmp, env_dry[ts], &q_dry_fac);
507
15.4k
          q_dry_fac += qtemp1 - 5;
508
15.4k
        }
509
510
26.9k
        hyb_output_real_wet = p_buffer_re;
511
26.9k
        hyb_output_imag_wet = p_buffer_im;
512
513
26.9k
        hyb_output_real_dry = hyb_out_dry_real;
514
26.9k
        hyb_output_imag_dry = hyb_out_dry_imag;
515
26.9k
        acc = 0;
516
26.9k
        acc2 = 0;
517
518
1.36M
        for (qs = start_hsb; qs < hybrid_bands; qs++) {
519
1.34M
          acc = ixheaac_add64_sat(acc, ixheaac_mult32x32in64(*hyb_output_real_dry, *hyb_output_real_dry));
520
1.34M
          hyb_output_real_dry++;
521
1.34M
          acc = ixheaac_add64_sat(acc, ixheaac_mult32x32in64(*hyb_output_imag_dry, *hyb_output_imag_dry));
522
1.34M
          hyb_output_imag_dry++;
523
524
1.34M
          acc2 = ixheaac_add64_sat(acc2, ixheaac_mult32x32in64(*hyb_output_real_wet, *hyb_output_real_wet));
525
1.34M
          hyb_output_real_wet++;
526
1.34M
          acc2 = ixheaac_add64_sat(acc2, ixheaac_mult32x32in64(*hyb_output_imag_wet, *hyb_output_imag_wet));
527
1.34M
          hyb_output_imag_wet++;
528
1.34M
        }
529
26.9k
        slot_amp_dry = ixheaacd_mps_narrow(acc, &q_slot_amp_dry);
530
26.9k
        slot_amp_wet = ixheaacd_mps_narrow(acc2, &q_slot_amp_wet);
531
532
26.9k
        qtemp1 = q_slot_amp_dry;
533
534
26.9k
        temp_1 = ixheaacd_mps_add32(slot_amp_dry, ABS_THR_FIX, &qtemp1, 15);
535
26.9k
        temp_2 = ixheaacd_mps_div_32(slot_amp_wet, temp_1, &qtemp2);
536
26.9k
        q_slot_amp_ratio = qtemp2 + q_slot_amp_wet - qtemp1;
537
26.9k
        slot_amp_ratio = ixheaacd_mps_sqrt(temp_2, &q_slot_amp_ratio, sqrt_tab);
538
539
26.9k
        temp_1 = ixheaacd_mps_convert_to_qn(dry_fac, q_dry_fac, 15);
540
26.9k
        temp_1 -= ONE_IN_Q15;
541
26.9k
        temp_1 = ixheaacd_mps_mult32_shr_16(temp_1, slot_amp_ratio);
542
26.9k
        q_slot_amp_ratio -= 1;
543
544
26.9k
        temp_1 = ixheaacd_mps_add32(temp_1, dry_fac, &q_slot_amp_ratio, q_dry_fac);
545
546
26.9k
        temp_1 = ixheaacd_mps_convert_to_qn(temp_1, q_slot_amp_ratio, 15);
547
26.9k
        temp_1 = max(ONE_IN_Q13, temp_1);
548
26.9k
        dry_fac = min(FOUR_IN_Q15, temp_1);
549
550
26.9k
        hyb_output_real_dry = hyb_out_dry_real;
551
26.9k
        hyb_output_imag_dry = hyb_out_dry_imag;
552
553
1.36M
        for (qs = start_hsb; qs < hybrid_bands; qs++) {
554
1.34M
          *hyb_output_real_dry = ixheaacd_mps_mult32_shr_15(*hyb_output_real_dry, dry_fac);
555
1.34M
          hyb_output_real_dry++;
556
1.34M
          *hyb_output_imag_dry = ixheaacd_mps_mult32_shr_15(*hyb_output_imag_dry, dry_fac);
557
1.34M
          hyb_output_imag_dry++;
558
1.34M
        }
559
26.9k
        p_buffer_re += MAX_HYBRID_BANDS;
560
26.9k
        p_buffer_im += MAX_HYBRID_BANDS;
561
26.9k
        hyb_out_dry_real += MAX_HYBRID_BANDS;
562
26.9k
        hyb_out_dry_imag += MAX_HYBRID_BANDS;
563
26.9k
      }
564
927
    }
565
26.6k
    p_buffer_real += TSXHB;
566
26.6k
    p_buffer_imag += TSXHB;
567
26.6k
  }
568
6.49k
  return;
569
6.49k
}
570
571
6.49k
VOID ixheaacd_pre_reshape_bb_env(ia_heaac_mps_state_struct *pstr_mps_state) {
572
6.49k
  WORD32 *env_dmx_0, *env_dmx_1;
573
574
6.49k
  VOID *free_scratch;
575
576
6.49k
  WORD32 tree_config = pstr_mps_state->tree_config;
577
578
6.49k
  free_scratch = pstr_mps_state->mps_scratch_mem_v;
579
6.49k
  env_dmx_0 = pstr_mps_state->array_struct->env_dmx_0;
580
6.49k
  env_dmx_1 = pstr_mps_state->array_struct->env_dmx_1;
581
582
6.49k
  switch (tree_config) {
583
5.98k
    case TREE_7572:
584
5.98k
      ixheaacd_extract_bb_env(pstr_mps_state, INP_DMX, 0 + 4, env_dmx_0, free_scratch, 0);
585
5.98k
      ixheaacd_extract_bb_env(pstr_mps_state, INP_DMX, 1 + 4, env_dmx_1, free_scratch, 0);
586
5.98k
      break;
587
515
    default:
588
515
      ixheaacd_extract_bb_env(pstr_mps_state, INP_DMX, 0, env_dmx_0, free_scratch, 0);
589
515
      if (min(pstr_mps_state->num_input_channels, 2) == 2) {
590
406
        ixheaacd_extract_bb_env(pstr_mps_state, INP_DMX, 1, env_dmx_1, free_scratch, 0);
591
406
      }
592
6.49k
  }
593
6.49k
  return;
594
6.49k
}