Coverage Report

Created: 2026-08-13 06:34

next uncovered line (L), next uncovered region (R), next uncovered branch (B)
/src/libxaac/decoder/ixheaacd_mps_apply_m2.c
Line
Count
Source
1
/******************************************************************************
2
 *
3
 * Copyright (C) 2023 The Android Open Source Project
4
 *
5
 * Licensed under the Apache License, Version 2.0 (the "License");
6
 * you may not use this file except in compliance with the License.
7
 * You may obtain a copy of the License at:
8
 *
9
 * http://www.apache.org/licenses/LICENSE-2.0
10
 *
11
 * Unless required by applicable law or agreed to in writing, software
12
 * distributed under the License is distributed on an "AS IS" BASIS,
13
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14
 * See the License for the specific language governing permissions and
15
 * limitations under the License.
16
 *
17
 *****************************************************************************
18
 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19
*/
20
#include <string.h>
21
#include "ixheaac_type_def.h"
22
#include "ixheaacd_mps_struct_def.h"
23
#include "ixheaacd_mps_res_rom.h"
24
#include "ixheaacd_mps_aac_struct.h"
25
#include "ixheaac_constants.h"
26
#include "ixheaac_basic_ops32.h"
27
#include "ixheaac_basic_ops40.h"
28
#include "ixheaacd_bitbuffer.h"
29
#include "ixheaacd_common_rom.h"
30
#include "ixheaacd_sbrdecsettings.h"
31
#include "ixheaacd_sbr_scale.h"
32
#include "ixheaacd_env_extr_part.h"
33
#include "ixheaacd_sbr_rom.h"
34
#include "ixheaacd_hybrid.h"
35
#include "ixheaacd_ps_dec.h"
36
#include "ixheaacd_mps_polyphase.h"
37
#include "ixheaacd_config.h"
38
#include "ixheaacd_qmf_dec.h"
39
#include "ixheaacd_mps_dec.h"
40
#include "ixheaacd_mps_macro_def.h"
41
#include "ixheaacd_mps_apply_common.h"
42
#include "ixheaacd_mps_basic_op.h"
43
#include "ixheaacd_mps_get_index.h"
44
45
17.2k
VOID ixheaacd_apply_m2(ia_heaac_mps_state_struct *pstr_mps_state) {
46
17.2k
  WORD32 ts, qs, row, col;
47
17.2k
  ia_heaac_mps_state_struct *curr_state = pstr_mps_state;
48
17.2k
  ia_mps_persistent_mem *persistent_mem = &curr_state->mps_persistent_mem;
49
17.2k
  ia_mps_dec_reuse_array_struct *p_array_struct = pstr_mps_state->array_struct;
50
17.2k
  ia_mps_dec_m2_param_struct *p_m2_param = pstr_mps_state->aux_struct->m2_param;
51
52
17.2k
  WORD32 num_direct_signals = curr_state->num_direct_signals;
53
17.2k
  WORD32 temp_1, loop_counter, col_counter = num_direct_signals + curr_state->num_decor_signals;
54
55
17.2k
  WORD32 *rout_ptr, *rout_kernel_ptr;
56
57
17.2k
  WORD32 *hyb_output_real_dry, *hyb_output_imag_dry, *hyb_output_real_wet, *hyb_output_imag_wet;
58
59
17.2k
  WORD32 *p_hyb_out_dry_real, *p_hyb_out_dry_imag, *p_hyb_out_dry_re, *p_hyb_out_dry_im;
60
61
17.2k
  WORD32 *w_wet_real, *w_wet_imag, *w_dry_real, *w_dry_imag;
62
63
17.2k
  WORD32 *m2_decor_real_prev = persistent_mem->m2_decor_real_prev;
64
17.2k
  WORD32 *m2_decor_imag_prev = persistent_mem->m2_decor_imag_prev;
65
66
17.2k
  WORD32 *p_buffer_real, *p_buffer_imag, *p_buffer_re, *p_buffer_im;
67
17.2k
  WORD32 *p_buf_real, *p_buf_imag, *p_buf_re, *p_buf_im;
68
69
17.2k
  WORD32 *m2_resid_real_prev = persistent_mem->m2_resid_real_prev;
70
17.2k
  WORD32 *m2_resid_imag_prev = persistent_mem->m2_resid_imag_prev;
71
72
17.2k
  WORD32 idx = 0;
73
17.2k
  WORD32 w_wet_offset = num_direct_signals * TSXHB;
74
75
17.2k
  WORD32 num_output_channels = curr_state->num_output_channels;
76
17.2k
  WORD32 time_slots = curr_state->time_slots;
77
17.2k
  WORD32 hybrid_bands = curr_state->hybrid_bands;
78
17.2k
  WORD32 m2_param_imag_present = curr_state->m2_param_imag_present;
79
17.2k
  WORD32 num_parameter_bands = curr_state->num_parameter_bands;
80
17.2k
  WORD32 up_mix_type = curr_state->up_mix_type;
81
17.2k
  WORD32 residual_coding = curr_state->residual_coding;
82
17.2k
  WORD32 *index_ptr = curr_state->index;
83
84
17.2k
  SIZE_T params[4];
85
86
17.2k
  params[0] = (SIZE_T)(&curr_state->kernels[0]);
87
17.2k
  params[1] = time_slots;
88
17.2k
  params[2] = num_parameter_bands;
89
17.2k
  params[3] = hybrid_bands;
90
91
17.2k
  rout_ptr = pstr_mps_state->mps_scratch_mem_v;
92
17.2k
  rout_kernel_ptr =
93
17.2k
      rout_ptr + IXHEAAC_GET_SIZE_ALIGNED_TYPE(TSXHB, sizeof(*rout_kernel_ptr), BYTE_ALIGN_8);
94
95
17.2k
  p_hyb_out_dry_real = p_array_struct->hyb_output_real_dry;
96
17.2k
  p_hyb_out_dry_imag = p_array_struct->hyb_output_imag_dry;
97
98
151k
  for (row = 0; row < num_output_channels; row++) {
99
133k
    hyb_output_real_dry = p_hyb_out_dry_real;
100
133k
    hyb_output_imag_dry = p_hyb_out_dry_imag;
101
102
3.77M
    for (ts = 0; ts < time_slots; ts++) {
103
3.64M
      memset(hyb_output_real_dry, 0, (hybrid_bands) * sizeof(hyb_output_real_dry[0]));
104
3.64M
      memset(hyb_output_imag_dry, 0, (hybrid_bands) * sizeof(hyb_output_imag_dry[0]));
105
106
3.64M
      hyb_output_real_dry += MAX_HYBRID_BANDS;
107
3.64M
      hyb_output_imag_dry += MAX_HYBRID_BANDS;
108
3.64M
    }
109
110
133k
    p_hyb_out_dry_real += TSXHB;
111
133k
    p_hyb_out_dry_imag += TSXHB;
112
133k
  }
113
114
17.2k
  if (residual_coding)
115
481
    loop_counter = col_counter;
116
16.7k
  else
117
16.7k
    loop_counter = num_direct_signals;
118
119
17.2k
  idx = 0;
120
121
17.2k
  p_hyb_out_dry_real = p_array_struct->hyb_output_real_dry;
122
17.2k
  p_hyb_out_dry_imag = p_array_struct->hyb_output_imag_dry;
123
124
151k
  for (row = 0; row < num_output_channels; row++) {
125
133k
    p_buffer_real = p_array_struct->buf_real;
126
133k
    p_buffer_imag = p_array_struct->buf_imag;
127
128
857k
    for (col = 0; col < num_direct_signals; col++) {
129
723k
      p_buffer_re = p_buffer_real;
130
723k
      p_buffer_im = p_buffer_imag;
131
132
723k
      if (curr_state->m2_param_present[row][col] & 2) {
133
133k
        ixheaacd_dec_interp_umx(p_m2_param->m2_resid_real[idx++], rout_ptr, m2_resid_real_prev,
134
133k
                                pstr_mps_state);
135
133k
        ixheaacd_apply_abs_kernels(rout_ptr, rout_kernel_ptr, params);
136
137
133k
        p_hyb_out_dry_re = p_hyb_out_dry_real;
138
133k
        p_hyb_out_dry_im = p_hyb_out_dry_imag;
139
140
3.77M
        for (ts = 0; ts < time_slots; ts++) {
141
3.64M
          hyb_output_real_dry = p_hyb_out_dry_re;
142
3.64M
          hyb_output_imag_dry = p_hyb_out_dry_im;
143
144
3.64M
          w_dry_real = p_buffer_re;
145
3.64M
          w_dry_imag = p_buffer_im;
146
147
215M
          for (qs = 0; qs < hybrid_bands; qs++) {
148
211M
            temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_real, *rout_kernel_ptr);
149
211M
            w_dry_real++;
150
211M
            *hyb_output_real_dry = ixheaac_add32_sat(*hyb_output_real_dry, temp_1);
151
211M
            hyb_output_real_dry++;
152
153
211M
            temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_imag, *rout_kernel_ptr);
154
211M
            w_dry_imag++;
155
211M
            rout_kernel_ptr++;
156
211M
            *hyb_output_imag_dry = ixheaac_add32_sat(*hyb_output_imag_dry, temp_1);
157
211M
            hyb_output_imag_dry++;
158
211M
          }
159
3.64M
          p_buffer_re += MAX_HYBRID_BANDS;
160
3.64M
          p_buffer_im += MAX_HYBRID_BANDS;
161
162
3.64M
          p_hyb_out_dry_re += MAX_HYBRID_BANDS;
163
3.64M
          p_hyb_out_dry_im += MAX_HYBRID_BANDS;
164
3.64M
        }
165
133k
        m2_resid_real_prev += num_parameter_bands;
166
133k
      }
167
723k
      p_buffer_real += TSXHB;
168
723k
      p_buffer_imag += TSXHB;
169
723k
    }
170
171
142k
    for (; col < loop_counter; col++) {
172
8.26k
      WORD32 index;
173
8.26k
      WORD32 res = ixheaacd_get_res_idx(pstr_mps_state, col);
174
8.26k
      index = index_ptr[res];
175
176
8.26k
      if (curr_state->m2_param_present[row][col] & 2) {
177
3.10k
        WORD32 *p_dry_real = p_array_struct->w_dry_real + res * TSXHB;
178
3.10k
        WORD32 *p_dry_imag = p_array_struct->w_dry_imag + res * TSXHB;
179
180
3.10k
        ixheaacd_dec_interp_umx(p_m2_param->m2_resid_real[idx++], rout_ptr, m2_resid_real_prev,
181
3.10k
                                pstr_mps_state);
182
3.10k
        ixheaacd_apply_abs_kernels(rout_ptr, rout_kernel_ptr, params);
183
184
3.10k
        p_hyb_out_dry_re = p_hyb_out_dry_real;
185
3.10k
        p_hyb_out_dry_im = p_hyb_out_dry_imag;
186
187
82.5k
        for (ts = 0; ts < time_slots; ts++) {
188
79.4k
          hyb_output_real_dry = p_hyb_out_dry_re;
189
79.4k
          hyb_output_imag_dry = p_hyb_out_dry_im;
190
191
79.4k
          w_dry_real = p_dry_real;
192
79.4k
          w_dry_imag = p_dry_imag;
193
194
1.06M
          for (qs = 0; qs < index; qs++) {
195
987k
            temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_real, *rout_kernel_ptr);
196
987k
            w_dry_real++;
197
987k
            *hyb_output_real_dry = ixheaac_add32_sat(*hyb_output_real_dry, temp_1);
198
987k
            hyb_output_real_dry++;
199
200
987k
            temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_imag, *rout_kernel_ptr);
201
987k
            w_dry_imag++;
202
987k
            rout_kernel_ptr++;
203
987k
            *hyb_output_imag_dry = ixheaac_add32_sat(*hyb_output_imag_dry, temp_1);
204
987k
            hyb_output_imag_dry++;
205
987k
          }
206
79.4k
          rout_kernel_ptr += hybrid_bands - index;
207
208
79.4k
          p_hyb_out_dry_re += MAX_HYBRID_BANDS;
209
79.4k
          p_hyb_out_dry_im += MAX_HYBRID_BANDS;
210
211
79.4k
          p_dry_real += MAX_HYBRID_BANDS;
212
79.4k
          p_dry_imag += MAX_HYBRID_BANDS;
213
79.4k
        }
214
3.10k
        m2_resid_real_prev += num_parameter_bands;
215
3.10k
      }
216
8.26k
    }
217
218
133k
    p_hyb_out_dry_real += TSXHB;
219
133k
    p_hyb_out_dry_imag += TSXHB;
220
133k
  }
221
222
17.2k
  if (up_mix_type == 2) {
223
0
    if (m2_param_imag_present) {
224
0
      if (residual_coding)
225
0
        loop_counter = col_counter;
226
0
      else
227
0
        loop_counter = num_direct_signals;
228
229
0
      idx = 0;
230
231
0
      p_hyb_out_dry_real = p_array_struct->hyb_output_real_dry;
232
0
      p_hyb_out_dry_imag = p_array_struct->hyb_output_imag_dry;
233
234
0
      for (row = 0; row < num_output_channels; row++) {
235
0
        p_buffer_real = p_array_struct->buf_real;
236
0
        p_buffer_imag = p_array_struct->buf_imag;
237
238
0
        for (col = 0; col < num_direct_signals; col++) {
239
0
          p_buffer_re = p_buffer_real;
240
0
          p_buffer_im = p_buffer_imag;
241
242
0
          if (curr_state->m2_param_present[row][col] & 2) {
243
0
            ixheaacd_dec_interp_umx(p_m2_param->m2_resid_imag[idx++], rout_ptr,
244
0
                                    m2_resid_imag_prev, pstr_mps_state);
245
0
            ixheaacd_apply_abs_kernels(rout_ptr, rout_kernel_ptr, params);
246
247
0
            p_hyb_out_dry_re = p_hyb_out_dry_real;
248
0
            p_hyb_out_dry_im = p_hyb_out_dry_imag;
249
250
0
            for (ts = 0; ts < time_slots; ts++) {
251
0
              hyb_output_real_dry = p_hyb_out_dry_re;
252
0
              hyb_output_imag_dry = p_hyb_out_dry_im;
253
254
0
              w_dry_real = p_buffer_re;
255
0
              w_dry_imag = p_buffer_im;
256
257
0
              for (qs = 0; qs < 2; qs++) {
258
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_imag, *rout_kernel_ptr);
259
0
                w_dry_imag++;
260
0
                *hyb_output_real_dry = ixheaac_add32_sat(*hyb_output_real_dry, temp_1);
261
0
                hyb_output_real_dry++;
262
263
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_real, *rout_kernel_ptr);
264
0
                w_dry_real++;
265
0
                rout_kernel_ptr++;
266
0
                *hyb_output_imag_dry = ixheaac_sub32_sat(*hyb_output_imag_dry, temp_1);
267
0
                hyb_output_imag_dry++;
268
0
              }
269
270
0
              for (; qs < hybrid_bands; qs++) {
271
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_imag, *rout_kernel_ptr);
272
0
                w_dry_imag++;
273
0
                *hyb_output_real_dry = ixheaac_sub32_sat(*hyb_output_real_dry, temp_1);
274
0
                hyb_output_real_dry++;
275
276
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_real, *rout_kernel_ptr);
277
0
                w_dry_real++;
278
0
                rout_kernel_ptr++;
279
0
                *hyb_output_imag_dry = ixheaac_add32_sat(*hyb_output_imag_dry, temp_1);
280
0
                hyb_output_imag_dry++;
281
0
              }
282
0
              p_buffer_re += MAX_HYBRID_BANDS;
283
0
              p_buffer_im += MAX_HYBRID_BANDS;
284
285
0
              p_hyb_out_dry_re += MAX_HYBRID_BANDS;
286
0
              p_hyb_out_dry_im += MAX_HYBRID_BANDS;
287
0
            }
288
0
            m2_resid_imag_prev += num_parameter_bands;
289
0
          }
290
0
          p_buffer_real += TSXHB;
291
0
          p_buffer_imag += TSXHB;
292
0
        }
293
294
0
        for (; col < loop_counter; col++) {
295
0
          WORD32 index;
296
0
          WORD32 res = ixheaacd_get_res_idx(pstr_mps_state, col);
297
0
          index = index_ptr[res];
298
299
0
          if (curr_state->m2_param_present[row][col] & 2) {
300
0
            WORD32 *p_dry_real = p_array_struct->w_dry_real + res * TSXHB;
301
0
            WORD32 *p_dry_imag = p_array_struct->w_dry_imag + res * TSXHB;
302
0
            ixheaacd_dec_interp_umx(p_m2_param->m2_resid_imag[idx++], rout_ptr,
303
0
                                    m2_resid_imag_prev, pstr_mps_state);
304
0
            ixheaacd_apply_abs_kernels(rout_ptr, rout_kernel_ptr, params);
305
306
0
            p_hyb_out_dry_re = p_hyb_out_dry_real;
307
0
            p_hyb_out_dry_im = p_hyb_out_dry_imag;
308
309
0
            for (ts = 0; ts < time_slots; ts++) {
310
0
              hyb_output_real_dry = p_hyb_out_dry_re;
311
0
              hyb_output_imag_dry = p_hyb_out_dry_im;
312
313
0
              w_dry_real = p_dry_real;
314
0
              w_dry_imag = p_dry_imag;
315
316
0
              for (qs = 0; qs < 2; qs++) {
317
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_imag, *rout_kernel_ptr);
318
0
                w_dry_imag++;
319
0
                *hyb_output_real_dry = ixheaac_add32_sat(*hyb_output_real_dry, temp_1);
320
0
                hyb_output_real_dry++;
321
322
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_real, *rout_kernel_ptr);
323
0
                w_dry_real++;
324
0
                rout_kernel_ptr++;
325
0
                *hyb_output_imag_dry = ixheaac_sub32_sat(*hyb_output_imag_dry, temp_1);
326
0
                hyb_output_imag_dry++;
327
0
              }
328
329
0
              for (; qs < index; qs++) {
330
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_imag, *rout_kernel_ptr);
331
0
                w_dry_imag++;
332
0
                *hyb_output_real_dry = ixheaac_sub32_sat(*hyb_output_real_dry, temp_1);
333
0
                hyb_output_real_dry++;
334
335
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_dry_real, *rout_kernel_ptr);
336
0
                w_dry_real++;
337
0
                rout_kernel_ptr++;
338
0
                *hyb_output_imag_dry = ixheaac_add32_sat(*hyb_output_imag_dry, temp_1);
339
0
                hyb_output_imag_dry++;
340
0
              }
341
0
              rout_kernel_ptr += hybrid_bands - index;
342
343
0
              p_hyb_out_dry_re += MAX_HYBRID_BANDS;
344
0
              p_hyb_out_dry_im += MAX_HYBRID_BANDS;
345
346
0
              p_dry_real += MAX_HYBRID_BANDS;
347
0
              p_dry_imag += MAX_HYBRID_BANDS;
348
0
            }
349
0
            m2_resid_imag_prev += num_parameter_bands;
350
0
          }
351
0
        }
352
0
        p_hyb_out_dry_real += TSXHB;
353
0
        p_hyb_out_dry_imag += TSXHB;
354
0
      }
355
0
    }
356
0
  }
357
17.2k
  p_buffer_real = p_array_struct->buf_real;
358
17.2k
  p_buffer_imag = p_array_struct->buf_imag;
359
360
151k
  for (row = 0; row < num_output_channels; row++) {
361
133k
    hyb_output_real_wet = p_buffer_real;
362
133k
    hyb_output_imag_wet = p_buffer_imag;
363
364
3.77M
    for (ts = 0; ts < time_slots; ts++) {
365
3.64M
      memset(hyb_output_real_wet, 0, (hybrid_bands) * sizeof(*hyb_output_real_wet));
366
3.64M
      memset(hyb_output_imag_wet, 0, (hybrid_bands) * sizeof(*hyb_output_imag_wet));
367
368
3.64M
      hyb_output_real_wet += MAX_HYBRID_BANDS;
369
3.64M
      hyb_output_imag_wet += MAX_HYBRID_BANDS;
370
3.64M
    }
371
133k
    p_buffer_real += TSXHB;
372
133k
    p_buffer_imag += TSXHB;
373
133k
  }
374
17.2k
  idx = 0;
375
376
17.2k
  p_buffer_real = p_array_struct->buf_real;
377
17.2k
  p_buffer_imag = p_array_struct->buf_imag;
378
379
151k
  for (row = 0; row < num_output_channels; row++) {
380
133k
    p_buf_real = p_array_struct->buffer_real + w_wet_offset;
381
133k
    p_buf_imag = p_array_struct->buffer_imag + w_wet_offset;
382
434k
    for (col = num_direct_signals; col < col_counter; col++) {
383
300k
      if (curr_state->m2_param_present[row][col] & 1) {
384
83.7k
        ixheaacd_dec_interp_umx(p_m2_param->m2_decor_real[idx++], rout_ptr, m2_decor_real_prev,
385
83.7k
                                pstr_mps_state);
386
387
83.7k
        ixheaacd_apply_abs_kernels(rout_ptr, rout_kernel_ptr, params);
388
83.7k
        p_buffer_re = p_buffer_real;
389
83.7k
        p_buffer_im = p_buffer_imag;
390
391
83.7k
        p_buf_re = p_buf_real;
392
83.7k
        p_buf_im = p_buf_imag;
393
2.32M
        for (ts = 0; ts < time_slots; ts++) {
394
2.24M
          hyb_output_real_wet = p_buffer_re;
395
2.24M
          hyb_output_imag_wet = p_buffer_im;
396
397
2.24M
          w_wet_real = p_buf_re;
398
2.24M
          w_wet_imag = p_buf_im;
399
400
125M
          for (qs = 0; qs < hybrid_bands; qs++) {
401
123M
            temp_1 = ixheaacd_mps_mult32_shr_15(*w_wet_real, *rout_kernel_ptr);
402
123M
            w_wet_real++;
403
123M
            *hyb_output_real_wet = ixheaac_add32_sat(*hyb_output_real_wet, temp_1);
404
123M
            hyb_output_real_wet++;
405
406
123M
            temp_1 = ixheaacd_mps_mult32_shr_15(*w_wet_imag, *rout_kernel_ptr);
407
123M
            w_wet_imag++;
408
123M
            rout_kernel_ptr++;
409
123M
            *hyb_output_imag_wet = ixheaac_add32_sat(*hyb_output_imag_wet, temp_1);
410
123M
            hyb_output_imag_wet++;
411
123M
          }
412
2.24M
          p_buffer_re += MAX_HYBRID_BANDS;
413
2.24M
          p_buffer_im += MAX_HYBRID_BANDS;
414
415
2.24M
          p_buf_re += MAX_HYBRID_BANDS;
416
2.24M
          p_buf_im += MAX_HYBRID_BANDS;
417
2.24M
        }
418
83.7k
        m2_decor_real_prev += num_parameter_bands;
419
83.7k
      }
420
300k
      p_buf_real += TSXHB;
421
300k
      p_buf_imag += TSXHB;
422
300k
    }
423
133k
    p_buffer_real += TSXHB;
424
133k
    p_buffer_imag += TSXHB;
425
133k
  }
426
427
17.2k
  if (up_mix_type == 2) {
428
0
    if (m2_param_imag_present) {
429
0
      idx = 0;
430
431
0
      p_buffer_real = p_array_struct->buf_real;
432
0
      p_buffer_imag = p_array_struct->buf_imag;
433
434
0
      for (row = 0; row < num_output_channels; row++) {
435
0
        m2_decor_imag_prev += num_parameter_bands * num_direct_signals;
436
0
        p_buf_real = p_array_struct->buffer_real + w_wet_offset;
437
0
        p_buf_imag = p_array_struct->buffer_imag + w_wet_offset;
438
0
        for (col = num_direct_signals; col < col_counter; col++) {
439
0
          if (curr_state->m2_param_present[row][col] & 1) {
440
0
            ixheaacd_dec_interp_umx(p_m2_param->m2_decor_imag[idx++], rout_ptr,
441
0
                                    m2_decor_imag_prev, pstr_mps_state);
442
0
            ixheaacd_apply_abs_kernels(rout_ptr, rout_kernel_ptr, params);
443
444
0
            p_buffer_re = p_buffer_real;
445
0
            p_buffer_im = p_buffer_imag;
446
447
0
            p_buf_re = p_buf_real;
448
0
            p_buf_im = p_buf_imag;
449
0
            for (ts = 0; ts < time_slots; ts++) {
450
0
              hyb_output_real_wet = p_buffer_re;
451
0
              hyb_output_imag_wet = p_buffer_im;
452
453
0
              w_wet_real = p_buf_re;
454
0
              w_wet_imag = p_buf_im;
455
456
0
              for (qs = 0; qs < 2; qs++) {
457
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_wet_imag, *rout_kernel_ptr);
458
0
                w_wet_imag++;
459
0
                *hyb_output_real_wet = ixheaac_add32_sat(*hyb_output_real_wet, temp_1);
460
0
                hyb_output_real_wet++;
461
462
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_wet_real, *rout_kernel_ptr);
463
0
                w_wet_real++;
464
0
                rout_kernel_ptr++;
465
0
                *hyb_output_imag_wet = ixheaac_sub32_sat(*hyb_output_imag_wet, temp_1);
466
0
                hyb_output_imag_wet++;
467
0
              }
468
469
0
              for (; qs < hybrid_bands; qs++) {
470
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_wet_imag, *rout_kernel_ptr);
471
0
                w_wet_imag++;
472
0
                *hyb_output_real_wet = ixheaac_sub32_sat(*hyb_output_real_wet, temp_1);
473
0
                hyb_output_real_wet++;
474
475
0
                temp_1 = ixheaacd_mps_mult32_shr_15(*w_wet_real, *rout_kernel_ptr);
476
0
                w_wet_real++;
477
0
                rout_kernel_ptr++;
478
0
                *hyb_output_imag_wet = ixheaac_add32_sat(*hyb_output_imag_wet, temp_1);
479
0
                hyb_output_imag_wet++;
480
0
              }
481
0
              p_buffer_re += MAX_HYBRID_BANDS;
482
0
              p_buffer_im += MAX_HYBRID_BANDS;
483
484
0
              p_buf_re += MAX_HYBRID_BANDS;
485
0
              p_buf_im += MAX_HYBRID_BANDS;
486
0
            }
487
0
            m2_decor_imag_prev += num_parameter_bands;
488
0
          }
489
0
          p_buf_real += TSXHB;
490
0
          p_buf_imag += TSXHB;
491
0
        }
492
0
        p_buffer_real += TSXHB;
493
0
        p_buffer_imag += TSXHB;
494
0
      }
495
0
    }
496
0
  }
497
17.2k
  return;
498
17.2k
}