/src/build/lib/Target/AArch64/AArch64GenCallingConv.inc
Line | Count | Source (jump to first uncovered line) |
1 | | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
2 | | |* *| |
3 | | |* Calling Convention Implementation Fragment *| |
4 | | |* *| |
5 | | |* Automatically generated file, do not edit! *| |
6 | | |* *| |
7 | | \*===----------------------------------------------------------------------===*/ |
8 | | |
9 | | #ifndef GET_CC_REGISTER_LISTS |
10 | | |
11 | | bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, |
12 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
13 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
14 | | bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT, |
15 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
16 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
17 | | bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, |
18 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
19 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
20 | | bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT, |
21 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
22 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
23 | | bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, |
24 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
25 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
26 | | bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT, |
27 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
28 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
29 | | bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT, |
30 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
31 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
32 | | bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT, |
33 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
34 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
35 | | bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, |
36 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
37 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
38 | | bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, |
39 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
40 | | ISD::ArgFlagsTy ArgFlags, CCState &State); |
41 | | |
42 | | |
43 | | bool llvm::CC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, |
44 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
45 | 105k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
46 | | |
47 | 105k | if (ArgFlags.isNest()) { |
48 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X18)) { |
49 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
50 | 0 | return false; |
51 | 0 | } |
52 | 0 | } |
53 | | |
54 | 105k | if (LocVT == MVT::iPTR) { |
55 | 0 | LocVT = MVT::i64; |
56 | 0 | LocInfo = CCValAssign::BCvt; |
57 | 0 | } |
58 | | |
59 | 105k | if (LocVT == MVT::v2f32) { |
60 | 897 | LocVT = MVT::v2i32; |
61 | 897 | LocInfo = CCValAssign::BCvt; |
62 | 897 | } |
63 | | |
64 | 105k | if (LocVT == MVT::v2f64 || |
65 | 105k | LocVT == MVT::v4f32) { |
66 | 8.17k | LocVT = MVT::v2i64; |
67 | 8.17k | LocInfo = CCValAssign::BCvt; |
68 | 8.17k | } |
69 | | |
70 | 105k | if (State.getMachineFunction().getDataLayout().isBigEndian()) { |
71 | 0 | if (LocVT == MVT::v2i32 || |
72 | 0 | LocVT == MVT::v2f32 || |
73 | 0 | LocVT == MVT::v4i16 || |
74 | 0 | LocVT == MVT::v4f16 || |
75 | 0 | LocVT == MVT::v4bf16 || |
76 | 0 | LocVT == MVT::v8i8) { |
77 | 0 | LocVT = MVT::f64; |
78 | 0 | LocInfo = CCValAssign::BCvt; |
79 | 0 | } |
80 | 0 | } |
81 | | |
82 | 105k | if (State.getMachineFunction().getDataLayout().isBigEndian()) { |
83 | 0 | if (LocVT == MVT::v2i64 || |
84 | 0 | LocVT == MVT::v2f64 || |
85 | 0 | LocVT == MVT::v4i32 || |
86 | 0 | LocVT == MVT::v4f32 || |
87 | 0 | LocVT == MVT::v8i16 || |
88 | 0 | LocVT == MVT::v8f16 || |
89 | 0 | LocVT == MVT::v8bf16 || |
90 | 0 | LocVT == MVT::v16i8) { |
91 | 0 | LocVT = MVT::f128; |
92 | 0 | LocInfo = CCValAssign::BCvt; |
93 | 0 | } |
94 | 0 | } |
95 | | |
96 | 105k | if (ArgFlags.isInReg()) { |
97 | 0 | if (LocVT == MVT::i64) { |
98 | 0 | if (ArgFlags.isSRet()) { |
99 | 0 | if (LocVT == MVT::i64) { |
100 | 0 | static const MCPhysReg RegList1[] = { |
101 | 0 | AArch64::X0, AArch64::X1 |
102 | 0 | }; |
103 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
104 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
105 | 0 | return false; |
106 | 0 | } |
107 | 0 | } |
108 | 0 | } |
109 | 0 | } |
110 | 0 | } |
111 | | |
112 | 105k | if (ArgFlags.isSRet()) { |
113 | 152 | if (LocVT == MVT::i64) { |
114 | 152 | if (unsigned Reg = State.AllocateReg(AArch64::X8)) { |
115 | 152 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
116 | 152 | return false; |
117 | 152 | } |
118 | 152 | } |
119 | 152 | } |
120 | | |
121 | 104k | if (ArgFlags.isByVal()) { |
122 | 10 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags); |
123 | 10 | return false; |
124 | 10 | } |
125 | | |
126 | 104k | if (ArgFlags.isSwiftSelf()) { |
127 | 0 | if (LocVT == MVT::i64) { |
128 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X20)) { |
129 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
130 | 0 | return false; |
131 | 0 | } |
132 | 0 | } |
133 | 0 | } |
134 | | |
135 | 104k | if (ArgFlags.isSwiftError()) { |
136 | 8 | if (LocVT == MVT::i64) { |
137 | 8 | if (unsigned Reg = State.AllocateReg(AArch64::X21)) { |
138 | 8 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
139 | 8 | return false; |
140 | 8 | } |
141 | 8 | } |
142 | 8 | } |
143 | | |
144 | 104k | if (ArgFlags.isSwiftAsync()) { |
145 | 0 | if (LocVT == MVT::i64) { |
146 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X22)) { |
147 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
148 | 0 | return false; |
149 | 0 | } |
150 | 0 | } |
151 | 0 | } |
152 | | |
153 | 104k | if (ArgFlags.isInConsecutiveRegs()) { |
154 | 367 | if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
155 | 362 | return false; |
156 | 367 | } |
157 | | |
158 | 104k | if (LocVT == MVT::nxv16i8 || |
159 | 104k | LocVT == MVT::nxv8i16 || |
160 | 104k | LocVT == MVT::nxv4i32 || |
161 | 104k | LocVT == MVT::nxv2i64 || |
162 | 104k | LocVT == MVT::nxv2f16 || |
163 | 104k | LocVT == MVT::nxv4f16 || |
164 | 104k | LocVT == MVT::nxv8f16 || |
165 | 104k | LocVT == MVT::nxv2bf16 || |
166 | 104k | LocVT == MVT::nxv4bf16 || |
167 | 104k | LocVT == MVT::nxv8bf16 || |
168 | 104k | LocVT == MVT::nxv2f32 || |
169 | 104k | LocVT == MVT::nxv4f32 || |
170 | 104k | LocVT == MVT::nxv2f64) { |
171 | 0 | static const MCPhysReg RegList2[] = { |
172 | 0 | AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 |
173 | 0 | }; |
174 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
175 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
176 | 0 | return false; |
177 | 0 | } |
178 | 0 | } |
179 | | |
180 | 104k | if (LocVT == MVT::nxv16i8 || |
181 | 104k | LocVT == MVT::nxv8i16 || |
182 | 104k | LocVT == MVT::nxv4i32 || |
183 | 104k | LocVT == MVT::nxv2i64 || |
184 | 104k | LocVT == MVT::nxv2f16 || |
185 | 104k | LocVT == MVT::nxv4f16 || |
186 | 104k | LocVT == MVT::nxv8f16 || |
187 | 104k | LocVT == MVT::nxv2bf16 || |
188 | 104k | LocVT == MVT::nxv4bf16 || |
189 | 104k | LocVT == MVT::nxv8bf16 || |
190 | 104k | LocVT == MVT::nxv2f32 || |
191 | 104k | LocVT == MVT::nxv4f32 || |
192 | 104k | LocVT == MVT::nxv2f64) { |
193 | 0 | LocVT = MVT::i64; |
194 | 0 | LocInfo = CCValAssign::Indirect; |
195 | 0 | } |
196 | | |
197 | 104k | if (LocVT == MVT::nxv1i1 || |
198 | 104k | LocVT == MVT::nxv2i1 || |
199 | 104k | LocVT == MVT::nxv4i1 || |
200 | 104k | LocVT == MVT::nxv8i1 || |
201 | 104k | LocVT == MVT::nxv16i1 || |
202 | 104k | LocVT == MVT::aarch64svcount) { |
203 | 0 | static const MCPhysReg RegList3[] = { |
204 | 0 | AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3 |
205 | 0 | }; |
206 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
207 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
208 | 0 | return false; |
209 | 0 | } |
210 | 0 | } |
211 | | |
212 | 104k | if (LocVT == MVT::nxv1i1 || |
213 | 104k | LocVT == MVT::nxv2i1 || |
214 | 104k | LocVT == MVT::nxv4i1 || |
215 | 104k | LocVT == MVT::nxv8i1 || |
216 | 104k | LocVT == MVT::nxv16i1 || |
217 | 104k | LocVT == MVT::aarch64svcount) { |
218 | 0 | LocVT = MVT::i64; |
219 | 0 | LocInfo = CCValAssign::Indirect; |
220 | 0 | } |
221 | | |
222 | 104k | if (LocVT == MVT::i1 || |
223 | 104k | LocVT == MVT::i8 || |
224 | 104k | LocVT == MVT::i16) { |
225 | 8.16k | LocVT = MVT::i32; |
226 | 8.16k | if (ArgFlags.isSExt()) |
227 | 84 | LocInfo = CCValAssign::SExt; |
228 | 8.08k | else if (ArgFlags.isZExt()) |
229 | 615 | LocInfo = CCValAssign::ZExt; |
230 | 7.46k | else |
231 | 7.46k | LocInfo = CCValAssign::AExt; |
232 | 8.16k | } |
233 | | |
234 | 104k | if (LocVT == MVT::i32) { |
235 | 33.1k | static const MCPhysReg RegList4[] = { |
236 | 33.1k | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
237 | 33.1k | }; |
238 | 33.1k | if (unsigned Reg = State.AllocateReg(RegList4)) { |
239 | 32.4k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
240 | 32.4k | return false; |
241 | 32.4k | } |
242 | 33.1k | } |
243 | | |
244 | 72.1k | if (LocVT == MVT::i64) { |
245 | 29.9k | if (ArgFlags.isSplit()) { |
246 | 3.52k | static const MCPhysReg RegList5[] = { |
247 | 3.52k | AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6 |
248 | 3.52k | }; |
249 | 3.52k | static const MCPhysReg RegList6[] = { |
250 | 3.52k | AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5 |
251 | 3.52k | }; |
252 | 3.52k | if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) { |
253 | 3.51k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
254 | 3.51k | return false; |
255 | 3.51k | } |
256 | 3.52k | } |
257 | 29.9k | } |
258 | | |
259 | 68.6k | if (LocVT == MVT::i64) { |
260 | 26.4k | if (ArgFlags.isSplit()) { |
261 | 14 | static const MCPhysReg ShadowRegList7[] = { |
262 | 14 | AArch64::X7 |
263 | 14 | }; |
264 | 14 | int64_t Offset8 = State.AllocateStack(8, Align(16), ShadowRegList7); |
265 | 14 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); |
266 | 14 | return false; |
267 | 14 | } |
268 | 26.4k | } |
269 | | |
270 | 68.6k | if (LocVT == MVT::i64) { |
271 | 26.3k | static const MCPhysReg RegList9[] = { |
272 | 26.3k | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
273 | 26.3k | }; |
274 | 26.3k | if (unsigned Reg = State.AllocateReg(RegList9)) { |
275 | 24.5k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
276 | 24.5k | return false; |
277 | 24.5k | } |
278 | 26.3k | } |
279 | | |
280 | 44.0k | if (LocVT == MVT::f16) { |
281 | 249 | static const MCPhysReg RegList10[] = { |
282 | 249 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 |
283 | 249 | }; |
284 | 249 | if (unsigned Reg = State.AllocateReg(RegList10)) { |
285 | 249 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
286 | 249 | return false; |
287 | 249 | } |
288 | 249 | } |
289 | | |
290 | 43.7k | if (LocVT == MVT::bf16) { |
291 | 0 | static const MCPhysReg RegList11[] = { |
292 | 0 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 |
293 | 0 | }; |
294 | 0 | if (unsigned Reg = State.AllocateReg(RegList11)) { |
295 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
296 | 0 | return false; |
297 | 0 | } |
298 | 0 | } |
299 | | |
300 | 43.7k | if (LocVT == MVT::f32) { |
301 | 8.04k | static const MCPhysReg RegList12[] = { |
302 | 8.04k | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 |
303 | 8.04k | }; |
304 | 8.04k | if (unsigned Reg = State.AllocateReg(RegList12)) { |
305 | 8.04k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
306 | 8.04k | return false; |
307 | 8.04k | } |
308 | 8.04k | } |
309 | | |
310 | 35.7k | if (LocVT == MVT::f64) { |
311 | 5.34k | static const MCPhysReg RegList13[] = { |
312 | 5.34k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
313 | 5.34k | }; |
314 | 5.34k | if (unsigned Reg = State.AllocateReg(RegList13)) { |
315 | 5.34k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
316 | 5.34k | return false; |
317 | 5.34k | } |
318 | 5.34k | } |
319 | | |
320 | 30.3k | if (LocVT == MVT::v1i64 || |
321 | 30.3k | LocVT == MVT::v2i32 || |
322 | 30.3k | LocVT == MVT::v4i16 || |
323 | 30.3k | LocVT == MVT::v8i8 || |
324 | 30.3k | LocVT == MVT::v1f64 || |
325 | 30.3k | LocVT == MVT::v2f32 || |
326 | 30.3k | LocVT == MVT::v4f16 || |
327 | 30.3k | LocVT == MVT::v4bf16) { |
328 | 5.73k | static const MCPhysReg RegList14[] = { |
329 | 5.73k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
330 | 5.73k | }; |
331 | 5.73k | if (unsigned Reg = State.AllocateReg(RegList14)) { |
332 | 5.73k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
333 | 5.73k | return false; |
334 | 5.73k | } |
335 | 5.73k | } |
336 | | |
337 | 24.6k | if (LocVT == MVT::f128 || |
338 | 24.6k | LocVT == MVT::v2i64 || |
339 | 24.6k | LocVT == MVT::v4i32 || |
340 | 24.6k | LocVT == MVT::v8i16 || |
341 | 24.6k | LocVT == MVT::v16i8 || |
342 | 24.6k | LocVT == MVT::v4f32 || |
343 | 24.6k | LocVT == MVT::v2f64 || |
344 | 24.6k | LocVT == MVT::v8f16 || |
345 | 24.6k | LocVT == MVT::v8bf16) { |
346 | 22.1k | static const MCPhysReg RegList15[] = { |
347 | 22.1k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
348 | 22.1k | }; |
349 | 22.1k | if (unsigned Reg = State.AllocateReg(RegList15)) { |
350 | 21.6k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
351 | 21.6k | return false; |
352 | 21.6k | } |
353 | 22.1k | } |
354 | | |
355 | 2.98k | if (LocVT == MVT::i1 || |
356 | 2.98k | LocVT == MVT::i8 || |
357 | 2.98k | LocVT == MVT::i16 || |
358 | 2.98k | LocVT == MVT::f16 || |
359 | 2.98k | LocVT == MVT::bf16) { |
360 | 0 | int64_t Offset16 = State.AllocateStack(8, Align(8)); |
361 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo)); |
362 | 0 | return false; |
363 | 0 | } |
364 | | |
365 | 2.98k | if (LocVT == MVT::i32 || |
366 | 2.98k | LocVT == MVT::f32) { |
367 | 738 | int64_t Offset17 = State.AllocateStack(8, Align(8)); |
368 | 738 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset17, LocVT, LocInfo)); |
369 | 738 | return false; |
370 | 738 | } |
371 | | |
372 | 2.24k | if (LocVT == MVT::i64 || |
373 | 2.24k | LocVT == MVT::f64 || |
374 | 2.24k | LocVT == MVT::v1f64 || |
375 | 2.24k | LocVT == MVT::v2f32 || |
376 | 2.24k | LocVT == MVT::v1i64 || |
377 | 2.24k | LocVT == MVT::v2i32 || |
378 | 2.24k | LocVT == MVT::v4i16 || |
379 | 2.24k | LocVT == MVT::v8i8 || |
380 | 2.24k | LocVT == MVT::v4f16 || |
381 | 2.24k | LocVT == MVT::v4bf16) { |
382 | 1.80k | int64_t Offset18 = State.AllocateStack(8, Align(8)); |
383 | 1.80k | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo)); |
384 | 1.80k | return false; |
385 | 1.80k | } |
386 | | |
387 | 436 | if (LocVT == MVT::f128 || |
388 | 436 | LocVT == MVT::v2i64 || |
389 | 436 | LocVT == MVT::v4i32 || |
390 | 436 | LocVT == MVT::v8i16 || |
391 | 436 | LocVT == MVT::v16i8 || |
392 | 436 | LocVT == MVT::v4f32 || |
393 | 436 | LocVT == MVT::v2f64 || |
394 | 436 | LocVT == MVT::v8f16 || |
395 | 436 | LocVT == MVT::v8bf16) { |
396 | 436 | int64_t Offset19 = State.AllocateStack(16, Align(16)); |
397 | 436 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo)); |
398 | 436 | return false; |
399 | 436 | } |
400 | | |
401 | 0 | return true; // CC didn't match. |
402 | 436 | } |
403 | | |
404 | | |
405 | | bool llvm::CC_AArch64_Arm64EC_VarArg(unsigned ValNo, MVT ValVT, |
406 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
407 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
408 | |
|
409 | 0 | if (LocVT == MVT::f16 || |
410 | 0 | LocVT == MVT::bf16) { |
411 | 0 | LocVT = MVT::i16; |
412 | 0 | LocInfo = CCValAssign::BCvt; |
413 | 0 | } |
414 | |
|
415 | 0 | if (LocVT == MVT::f32) { |
416 | 0 | LocVT = MVT::i32; |
417 | 0 | LocInfo = CCValAssign::BCvt; |
418 | 0 | } |
419 | |
|
420 | 0 | if (LocVT == MVT::f64 || |
421 | 0 | LocVT == MVT::v1f64 || |
422 | 0 | LocVT == MVT::v1i64 || |
423 | 0 | LocVT == MVT::v2f32 || |
424 | 0 | LocVT == MVT::v2i32 || |
425 | 0 | LocVT == MVT::v4i16 || |
426 | 0 | LocVT == MVT::v4f16 || |
427 | 0 | LocVT == MVT::v4bf16 || |
428 | 0 | LocVT == MVT::v8i8 || |
429 | 0 | LocVT == MVT::iPTR) { |
430 | 0 | LocVT = MVT::i64; |
431 | 0 | LocInfo = CCValAssign::BCvt; |
432 | 0 | } |
433 | |
|
434 | 0 | if (LocVT == MVT::f128 || |
435 | 0 | LocVT == MVT::v2f64 || |
436 | 0 | LocVT == MVT::v2i64 || |
437 | 0 | LocVT == MVT::v4i32 || |
438 | 0 | LocVT == MVT::v4f32 || |
439 | 0 | LocVT == MVT::v8i16 || |
440 | 0 | LocVT == MVT::v8f16 || |
441 | 0 | LocVT == MVT::v8bf16 || |
442 | 0 | LocVT == MVT::v16i8) { |
443 | 0 | LocVT = MVT::i64; |
444 | 0 | LocInfo = CCValAssign::Indirect; |
445 | 0 | } |
446 | |
|
447 | 0 | if (LocVT == MVT::nxv16i8 || |
448 | 0 | LocVT == MVT::nxv8i16 || |
449 | 0 | LocVT == MVT::nxv4i32 || |
450 | 0 | LocVT == MVT::nxv2i64 || |
451 | 0 | LocVT == MVT::nxv2f16 || |
452 | 0 | LocVT == MVT::nxv4f16 || |
453 | 0 | LocVT == MVT::nxv8f16 || |
454 | 0 | LocVT == MVT::nxv2bf16 || |
455 | 0 | LocVT == MVT::nxv4bf16 || |
456 | 0 | LocVT == MVT::nxv8bf16 || |
457 | 0 | LocVT == MVT::nxv2f32 || |
458 | 0 | LocVT == MVT::nxv4f32 || |
459 | 0 | LocVT == MVT::nxv2f64) { |
460 | 0 | LocVT = MVT::i64; |
461 | 0 | LocInfo = CCValAssign::Indirect; |
462 | 0 | } |
463 | |
|
464 | 0 | if (LocVT == MVT::nxv2i1 || |
465 | 0 | LocVT == MVT::nxv4i1 || |
466 | 0 | LocVT == MVT::nxv8i1 || |
467 | 0 | LocVT == MVT::nxv16i1) { |
468 | 0 | LocVT = MVT::i64; |
469 | 0 | LocInfo = CCValAssign::Indirect; |
470 | 0 | } |
471 | |
|
472 | 0 | if (ArgFlags.isInReg()) { |
473 | 0 | if (LocVT == MVT::i64) { |
474 | 0 | if (ArgFlags.isSRet()) { |
475 | 0 | if (LocVT == MVT::i64) { |
476 | 0 | static const MCPhysReg RegList1[] = { |
477 | 0 | AArch64::X0, AArch64::X1 |
478 | 0 | }; |
479 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
480 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
481 | 0 | return false; |
482 | 0 | } |
483 | 0 | } |
484 | 0 | } |
485 | 0 | } |
486 | 0 | } |
487 | | |
488 | 0 | if (ArgFlags.isSRet()) { |
489 | 0 | if (LocVT == MVT::i64) { |
490 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X8)) { |
491 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
492 | 0 | return false; |
493 | 0 | } |
494 | 0 | } |
495 | 0 | } |
496 | | |
497 | 0 | if (ArgFlags.isByVal()) { |
498 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags); |
499 | 0 | return false; |
500 | 0 | } |
501 | | |
502 | 0 | if (LocVT == MVT::i1 || |
503 | 0 | LocVT == MVT::i8 || |
504 | 0 | LocVT == MVT::i16) { |
505 | 0 | LocVT = MVT::i32; |
506 | 0 | if (ArgFlags.isSExt()) |
507 | 0 | LocInfo = CCValAssign::SExt; |
508 | 0 | else if (ArgFlags.isZExt()) |
509 | 0 | LocInfo = CCValAssign::ZExt; |
510 | 0 | else |
511 | 0 | LocInfo = CCValAssign::AExt; |
512 | 0 | } |
513 | |
|
514 | 0 | if (LocVT == MVT::i32) { |
515 | 0 | static const MCPhysReg RegList2[] = { |
516 | 0 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3 |
517 | 0 | }; |
518 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
519 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
520 | 0 | return false; |
521 | 0 | } |
522 | 0 | } |
523 | | |
524 | 0 | if (LocVT == MVT::i64) { |
525 | 0 | static const MCPhysReg RegList3[] = { |
526 | 0 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3 |
527 | 0 | }; |
528 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
529 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
530 | 0 | return false; |
531 | 0 | } |
532 | 0 | } |
533 | | |
534 | 0 | if (LocVT == MVT::i32 || |
535 | 0 | LocVT == MVT::i64) { |
536 | 0 | int64_t Offset4 = State.AllocateStack(8, Align(8)); |
537 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); |
538 | 0 | return false; |
539 | 0 | } |
540 | | |
541 | 0 | return true; // CC didn't match. |
542 | 0 | } |
543 | | |
544 | | |
545 | | bool llvm::CC_AArch64_DarwinPCS(unsigned ValNo, MVT ValVT, |
546 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
547 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
548 | |
|
549 | 0 | if (LocVT == MVT::iPTR) { |
550 | 0 | LocVT = MVT::i64; |
551 | 0 | LocInfo = CCValAssign::BCvt; |
552 | 0 | } |
553 | |
|
554 | 0 | if (LocVT == MVT::v2f32) { |
555 | 0 | LocVT = MVT::v2i32; |
556 | 0 | LocInfo = CCValAssign::BCvt; |
557 | 0 | } |
558 | |
|
559 | 0 | if (LocVT == MVT::v2f64 || |
560 | 0 | LocVT == MVT::v4f32 || |
561 | 0 | LocVT == MVT::f128) { |
562 | 0 | LocVT = MVT::v2i64; |
563 | 0 | LocInfo = CCValAssign::BCvt; |
564 | 0 | } |
565 | |
|
566 | 0 | if (ArgFlags.isSRet()) { |
567 | 0 | if (LocVT == MVT::i64) { |
568 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X8)) { |
569 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
570 | 0 | return false; |
571 | 0 | } |
572 | 0 | } |
573 | 0 | } |
574 | | |
575 | 0 | if (ArgFlags.isByVal()) { |
576 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags); |
577 | 0 | return false; |
578 | 0 | } |
579 | | |
580 | 0 | if (ArgFlags.isSwiftSelf()) { |
581 | 0 | if (LocVT == MVT::i64) { |
582 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X20)) { |
583 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
584 | 0 | return false; |
585 | 0 | } |
586 | 0 | } |
587 | 0 | } |
588 | | |
589 | 0 | if (ArgFlags.isSwiftError()) { |
590 | 0 | if (LocVT == MVT::i64) { |
591 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X21)) { |
592 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
593 | 0 | return false; |
594 | 0 | } |
595 | 0 | } |
596 | 0 | } |
597 | | |
598 | 0 | if (ArgFlags.isSwiftAsync()) { |
599 | 0 | if (LocVT == MVT::i64) { |
600 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X22)) { |
601 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
602 | 0 | return false; |
603 | 0 | } |
604 | 0 | } |
605 | 0 | } |
606 | | |
607 | 0 | if (ArgFlags.isInConsecutiveRegs()) { |
608 | 0 | if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
609 | 0 | return false; |
610 | 0 | } |
611 | | |
612 | 0 | if (LocVT == MVT::i1 || |
613 | 0 | LocVT == MVT::i8 || |
614 | 0 | LocVT == MVT::i16) { |
615 | 0 | LocVT = MVT::i32; |
616 | 0 | if (ArgFlags.isSExt()) |
617 | 0 | LocInfo = CCValAssign::SExt; |
618 | 0 | else if (ArgFlags.isZExt()) |
619 | 0 | LocInfo = CCValAssign::ZExt; |
620 | 0 | else |
621 | 0 | LocInfo = CCValAssign::AExt; |
622 | 0 | } |
623 | |
|
624 | 0 | if (LocVT == MVT::i32) { |
625 | 0 | static const MCPhysReg RegList1[] = { |
626 | 0 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
627 | 0 | }; |
628 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
629 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
630 | 0 | return false; |
631 | 0 | } |
632 | 0 | } |
633 | | |
634 | 0 | if (LocVT == MVT::i64) { |
635 | 0 | if (ArgFlags.isSplit()) { |
636 | 0 | static const MCPhysReg RegList2[] = { |
637 | 0 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6 |
638 | 0 | }; |
639 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
640 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
641 | 0 | return false; |
642 | 0 | } |
643 | 0 | } |
644 | 0 | } |
645 | | |
646 | 0 | if (LocVT == MVT::i64) { |
647 | 0 | if (ArgFlags.isSplit()) { |
648 | 0 | static const MCPhysReg ShadowRegList3[] = { |
649 | 0 | AArch64::X7 |
650 | 0 | }; |
651 | 0 | int64_t Offset4 = State.AllocateStack(8, Align(16), ShadowRegList3); |
652 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); |
653 | 0 | return false; |
654 | 0 | } |
655 | 0 | } |
656 | | |
657 | 0 | if (LocVT == MVT::i64) { |
658 | 0 | static const MCPhysReg RegList5[] = { |
659 | 0 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
660 | 0 | }; |
661 | 0 | if (unsigned Reg = State.AllocateReg(RegList5)) { |
662 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
663 | 0 | return false; |
664 | 0 | } |
665 | 0 | } |
666 | | |
667 | 0 | if (LocVT == MVT::f16) { |
668 | 0 | static const MCPhysReg RegList6[] = { |
669 | 0 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 |
670 | 0 | }; |
671 | 0 | if (unsigned Reg = State.AllocateReg(RegList6)) { |
672 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
673 | 0 | return false; |
674 | 0 | } |
675 | 0 | } |
676 | | |
677 | 0 | if (LocVT == MVT::bf16) { |
678 | 0 | static const MCPhysReg RegList7[] = { |
679 | 0 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 |
680 | 0 | }; |
681 | 0 | if (unsigned Reg = State.AllocateReg(RegList7)) { |
682 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
683 | 0 | return false; |
684 | 0 | } |
685 | 0 | } |
686 | | |
687 | 0 | if (LocVT == MVT::f32) { |
688 | 0 | static const MCPhysReg RegList8[] = { |
689 | 0 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 |
690 | 0 | }; |
691 | 0 | if (unsigned Reg = State.AllocateReg(RegList8)) { |
692 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
693 | 0 | return false; |
694 | 0 | } |
695 | 0 | } |
696 | | |
697 | 0 | if (LocVT == MVT::f64) { |
698 | 0 | static const MCPhysReg RegList9[] = { |
699 | 0 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
700 | 0 | }; |
701 | 0 | if (unsigned Reg = State.AllocateReg(RegList9)) { |
702 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
703 | 0 | return false; |
704 | 0 | } |
705 | 0 | } |
706 | | |
707 | 0 | if (LocVT == MVT::v1i64 || |
708 | 0 | LocVT == MVT::v2i32 || |
709 | 0 | LocVT == MVT::v4i16 || |
710 | 0 | LocVT == MVT::v8i8 || |
711 | 0 | LocVT == MVT::v1f64 || |
712 | 0 | LocVT == MVT::v2f32 || |
713 | 0 | LocVT == MVT::v4f16 || |
714 | 0 | LocVT == MVT::v4bf16) { |
715 | 0 | static const MCPhysReg RegList10[] = { |
716 | 0 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
717 | 0 | }; |
718 | 0 | if (unsigned Reg = State.AllocateReg(RegList10)) { |
719 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
720 | 0 | return false; |
721 | 0 | } |
722 | 0 | } |
723 | | |
724 | 0 | if (LocVT == MVT::v2i64 || |
725 | 0 | LocVT == MVT::v4i32 || |
726 | 0 | LocVT == MVT::v8i16 || |
727 | 0 | LocVT == MVT::v16i8 || |
728 | 0 | LocVT == MVT::v4f32 || |
729 | 0 | LocVT == MVT::v2f64 || |
730 | 0 | LocVT == MVT::v8f16 || |
731 | 0 | LocVT == MVT::v8bf16) { |
732 | 0 | static const MCPhysReg RegList11[] = { |
733 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
734 | 0 | }; |
735 | 0 | if (unsigned Reg = State.AllocateReg(RegList11)) { |
736 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
737 | 0 | return false; |
738 | 0 | } |
739 | 0 | } |
740 | | |
741 | 0 | if (ValVT == MVT::i1 || ValVT == MVT::i8) { |
742 | 0 | int64_t Offset12 = State.AllocateStack(1, Align(1)); |
743 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset12, LocVT, LocInfo)); |
744 | 0 | return false; |
745 | 0 | } |
746 | | |
747 | 0 | if (ValVT == MVT::i16 || ValVT == MVT::f16 || ValVT == MVT::bf16) { |
748 | 0 | int64_t Offset13 = State.AllocateStack(2, Align(2)); |
749 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset13, LocVT, LocInfo)); |
750 | 0 | return false; |
751 | 0 | } |
752 | | |
753 | 0 | if (LocVT == MVT::i32 || |
754 | 0 | LocVT == MVT::f32) { |
755 | 0 | int64_t Offset14 = State.AllocateStack(4, Align(4)); |
756 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset14, LocVT, LocInfo)); |
757 | 0 | return false; |
758 | 0 | } |
759 | | |
760 | 0 | if (ArgFlags.isPointer()) { |
761 | 0 | if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) { |
762 | 0 | LocVT = MVT::i32; |
763 | 0 | LocInfo = CCValAssign::Trunc; |
764 | 0 | } |
765 | 0 | } |
766 | |
|
767 | 0 | if (ArgFlags.isPointer()) { |
768 | 0 | if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) { |
769 | 0 | int64_t Offset15 = State.AllocateStack(4, Align(4)); |
770 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset15, LocVT, LocInfo)); |
771 | 0 | return false; |
772 | 0 | } |
773 | 0 | } |
774 | | |
775 | 0 | if (LocVT == MVT::i64 || |
776 | 0 | LocVT == MVT::f64 || |
777 | 0 | LocVT == MVT::v1f64 || |
778 | 0 | LocVT == MVT::v2f32 || |
779 | 0 | LocVT == MVT::v1i64 || |
780 | 0 | LocVT == MVT::v2i32 || |
781 | 0 | LocVT == MVT::v4i16 || |
782 | 0 | LocVT == MVT::v8i8 || |
783 | 0 | LocVT == MVT::v4f16 || |
784 | 0 | LocVT == MVT::v4bf16) { |
785 | 0 | int64_t Offset16 = State.AllocateStack(8, Align(8)); |
786 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo)); |
787 | 0 | return false; |
788 | 0 | } |
789 | | |
790 | 0 | if (LocVT == MVT::v2i64 || |
791 | 0 | LocVT == MVT::v4i32 || |
792 | 0 | LocVT == MVT::v8i16 || |
793 | 0 | LocVT == MVT::v16i8 || |
794 | 0 | LocVT == MVT::v4f32 || |
795 | 0 | LocVT == MVT::v2f64 || |
796 | 0 | LocVT == MVT::v8f16 || |
797 | 0 | LocVT == MVT::v8bf16) { |
798 | 0 | int64_t Offset17 = State.AllocateStack(16, Align(16)); |
799 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset17, LocVT, LocInfo)); |
800 | 0 | return false; |
801 | 0 | } |
802 | | |
803 | 0 | return true; // CC didn't match. |
804 | 0 | } |
805 | | |
806 | | |
807 | | bool llvm::CC_AArch64_DarwinPCS_ILP32_VarArg(unsigned ValNo, MVT ValVT, |
808 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
809 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
810 | |
|
811 | 0 | if (LocVT == MVT::v2f32) { |
812 | 0 | LocVT = MVT::v2i32; |
813 | 0 | LocInfo = CCValAssign::BCvt; |
814 | 0 | } |
815 | |
|
816 | 0 | if (LocVT == MVT::v2f64 || |
817 | 0 | LocVT == MVT::v4f32 || |
818 | 0 | LocVT == MVT::f128) { |
819 | 0 | LocVT = MVT::v2i64; |
820 | 0 | LocInfo = CCValAssign::BCvt; |
821 | 0 | } |
822 | |
|
823 | 0 | if (LocVT == MVT::i8 || |
824 | 0 | LocVT == MVT::i16) { |
825 | 0 | LocVT = MVT::i32; |
826 | 0 | if (ArgFlags.isSExt()) |
827 | 0 | LocInfo = CCValAssign::SExt; |
828 | 0 | else if (ArgFlags.isZExt()) |
829 | 0 | LocInfo = CCValAssign::ZExt; |
830 | 0 | else |
831 | 0 | LocInfo = CCValAssign::AExt; |
832 | 0 | } |
833 | |
|
834 | 0 | if (LocVT == MVT::f16 || |
835 | 0 | LocVT == MVT::bf16) { |
836 | 0 | LocVT = MVT::f32; |
837 | 0 | LocInfo = CCValAssign::FPExt; |
838 | 0 | } |
839 | |
|
840 | 0 | if (ArgFlags.isPointer()) { |
841 | 0 | if (State.getMachineFunction().getDataLayout().getPointerSize() == 4) { |
842 | 0 | LocVT = MVT::i32; |
843 | 0 | LocInfo = CCValAssign::Trunc; |
844 | 0 | } |
845 | 0 | } |
846 | |
|
847 | 0 | if (LocVT == MVT::i32 || |
848 | 0 | LocVT == MVT::f32) { |
849 | 0 | int64_t Offset1 = State.AllocateStack(4, Align(4)); |
850 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); |
851 | 0 | return false; |
852 | 0 | } |
853 | | |
854 | 0 | if (LocVT == MVT::i64) { |
855 | 0 | if (ArgFlags.isSplit()) { |
856 | 0 | int64_t Offset2 = State.AllocateStack(8, Align(16)); |
857 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); |
858 | 0 | return false; |
859 | 0 | } |
860 | 0 | } |
861 | | |
862 | 0 | if (LocVT == MVT::i64 || |
863 | 0 | LocVT == MVT::f64 || |
864 | 0 | LocVT == MVT::v1i64 || |
865 | 0 | LocVT == MVT::v2i32 || |
866 | 0 | LocVT == MVT::v4i16 || |
867 | 0 | LocVT == MVT::v8i8 || |
868 | 0 | LocVT == MVT::v1f64 || |
869 | 0 | LocVT == MVT::v2f32 || |
870 | 0 | LocVT == MVT::v4f16 || |
871 | 0 | LocVT == MVT::v4bf16) { |
872 | 0 | int64_t Offset3 = State.AllocateStack(8, Align(8)); |
873 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); |
874 | 0 | return false; |
875 | 0 | } |
876 | | |
877 | 0 | if (LocVT == MVT::v2i64 || |
878 | 0 | LocVT == MVT::v4i32 || |
879 | 0 | LocVT == MVT::v8i16 || |
880 | 0 | LocVT == MVT::v16i8 || |
881 | 0 | LocVT == MVT::v4f32 || |
882 | 0 | LocVT == MVT::v2f64 || |
883 | 0 | LocVT == MVT::v8f16 || |
884 | 0 | LocVT == MVT::v8bf16) { |
885 | 0 | int64_t Offset4 = State.AllocateStack(16, Align(16)); |
886 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset4, LocVT, LocInfo)); |
887 | 0 | return false; |
888 | 0 | } |
889 | | |
890 | 0 | return true; // CC didn't match. |
891 | 0 | } |
892 | | |
893 | | |
894 | | bool llvm::CC_AArch64_DarwinPCS_VarArg(unsigned ValNo, MVT ValVT, |
895 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
896 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
897 | |
|
898 | 0 | if (LocVT == MVT::iPTR) { |
899 | 0 | LocVT = MVT::i64; |
900 | 0 | LocInfo = CCValAssign::BCvt; |
901 | 0 | } |
902 | |
|
903 | 0 | if (LocVT == MVT::v2f32) { |
904 | 0 | LocVT = MVT::v2i32; |
905 | 0 | LocInfo = CCValAssign::BCvt; |
906 | 0 | } |
907 | |
|
908 | 0 | if (LocVT == MVT::v2f64 || |
909 | 0 | LocVT == MVT::v4f32 || |
910 | 0 | LocVT == MVT::f128) { |
911 | 0 | LocVT = MVT::v2i64; |
912 | 0 | LocInfo = CCValAssign::BCvt; |
913 | 0 | } |
914 | |
|
915 | 0 | if (ArgFlags.isInConsecutiveRegs()) { |
916 | 0 | if (CC_AArch64_Custom_Stack_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
917 | 0 | return false; |
918 | 0 | } |
919 | | |
920 | 0 | if (LocVT == MVT::i8 || |
921 | 0 | LocVT == MVT::i16 || |
922 | 0 | LocVT == MVT::i32) { |
923 | 0 | LocVT = MVT::i64; |
924 | 0 | if (ArgFlags.isSExt()) |
925 | 0 | LocInfo = CCValAssign::SExt; |
926 | 0 | else if (ArgFlags.isZExt()) |
927 | 0 | LocInfo = CCValAssign::ZExt; |
928 | 0 | else |
929 | 0 | LocInfo = CCValAssign::AExt; |
930 | 0 | } |
931 | |
|
932 | 0 | if (LocVT == MVT::f16 || |
933 | 0 | LocVT == MVT::bf16 || |
934 | 0 | LocVT == MVT::f32) { |
935 | 0 | LocVT = MVT::f64; |
936 | 0 | LocInfo = CCValAssign::FPExt; |
937 | 0 | } |
938 | |
|
939 | 0 | if (LocVT == MVT::i64) { |
940 | 0 | if (ArgFlags.isSplit()) { |
941 | 0 | int64_t Offset1 = State.AllocateStack(8, Align(16)); |
942 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset1, LocVT, LocInfo)); |
943 | 0 | return false; |
944 | 0 | } |
945 | 0 | } |
946 | | |
947 | 0 | if (LocVT == MVT::i64 || |
948 | 0 | LocVT == MVT::f64 || |
949 | 0 | LocVT == MVT::v1i64 || |
950 | 0 | LocVT == MVT::v2i32 || |
951 | 0 | LocVT == MVT::v4i16 || |
952 | 0 | LocVT == MVT::v8i8 || |
953 | 0 | LocVT == MVT::v1f64 || |
954 | 0 | LocVT == MVT::v2f32 || |
955 | 0 | LocVT == MVT::v4f16 || |
956 | 0 | LocVT == MVT::v4bf16) { |
957 | 0 | int64_t Offset2 = State.AllocateStack(8, Align(8)); |
958 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset2, LocVT, LocInfo)); |
959 | 0 | return false; |
960 | 0 | } |
961 | | |
962 | 0 | if (LocVT == MVT::v2i64 || |
963 | 0 | LocVT == MVT::v4i32 || |
964 | 0 | LocVT == MVT::v8i16 || |
965 | 0 | LocVT == MVT::v16i8 || |
966 | 0 | LocVT == MVT::v4f32 || |
967 | 0 | LocVT == MVT::v2f64 || |
968 | 0 | LocVT == MVT::v8f16 || |
969 | 0 | LocVT == MVT::v8bf16) { |
970 | 0 | int64_t Offset3 = State.AllocateStack(16, Align(16)); |
971 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset3, LocVT, LocInfo)); |
972 | 0 | return false; |
973 | 0 | } |
974 | | |
975 | 0 | return true; // CC didn't match. |
976 | 0 | } |
977 | | |
978 | | |
979 | | bool llvm::CC_AArch64_GHC(unsigned ValNo, MVT ValVT, |
980 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
981 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
982 | |
|
983 | 0 | if (LocVT == MVT::iPTR) { |
984 | 0 | LocVT = MVT::i64; |
985 | 0 | LocInfo = CCValAssign::BCvt; |
986 | 0 | } |
987 | |
|
988 | 0 | if (LocVT == MVT::v1i64 || |
989 | 0 | LocVT == MVT::v2i32 || |
990 | 0 | LocVT == MVT::v4i16 || |
991 | 0 | LocVT == MVT::v8i8 || |
992 | 0 | LocVT == MVT::v2f32) { |
993 | 0 | LocVT = MVT::f64; |
994 | 0 | LocInfo = CCValAssign::BCvt; |
995 | 0 | } |
996 | |
|
997 | 0 | if (LocVT == MVT::v2i64 || |
998 | 0 | LocVT == MVT::v4i32 || |
999 | 0 | LocVT == MVT::v8i16 || |
1000 | 0 | LocVT == MVT::v16i8 || |
1001 | 0 | LocVT == MVT::v4f32 || |
1002 | 0 | LocVT == MVT::f128) { |
1003 | 0 | LocVT = MVT::v2f64; |
1004 | 0 | LocInfo = CCValAssign::BCvt; |
1005 | 0 | } |
1006 | |
|
1007 | 0 | if (LocVT == MVT::v2f64) { |
1008 | 0 | static const MCPhysReg RegList1[] = { |
1009 | 0 | AArch64::Q4, AArch64::Q5 |
1010 | 0 | }; |
1011 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
1012 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1013 | 0 | return false; |
1014 | 0 | } |
1015 | 0 | } |
1016 | | |
1017 | 0 | if (LocVT == MVT::f32) { |
1018 | 0 | static const MCPhysReg RegList2[] = { |
1019 | 0 | AArch64::S8, AArch64::S9, AArch64::S10, AArch64::S11 |
1020 | 0 | }; |
1021 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
1022 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1023 | 0 | return false; |
1024 | 0 | } |
1025 | 0 | } |
1026 | | |
1027 | 0 | if (LocVT == MVT::f64) { |
1028 | 0 | static const MCPhysReg RegList3[] = { |
1029 | 0 | AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15 |
1030 | 0 | }; |
1031 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
1032 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1033 | 0 | return false; |
1034 | 0 | } |
1035 | 0 | } |
1036 | | |
1037 | 0 | if (LocVT == MVT::i8 || |
1038 | 0 | LocVT == MVT::i16 || |
1039 | 0 | LocVT == MVT::i32) { |
1040 | 0 | LocVT = MVT::i64; |
1041 | 0 | if (ArgFlags.isSExt()) |
1042 | 0 | LocInfo = CCValAssign::SExt; |
1043 | 0 | else if (ArgFlags.isZExt()) |
1044 | 0 | LocInfo = CCValAssign::ZExt; |
1045 | 0 | else |
1046 | 0 | LocInfo = CCValAssign::AExt; |
1047 | 0 | } |
1048 | |
|
1049 | 0 | if (LocVT == MVT::i64) { |
1050 | 0 | static const MCPhysReg RegList4[] = { |
1051 | 0 | AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28 |
1052 | 0 | }; |
1053 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
1054 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1055 | 0 | return false; |
1056 | 0 | } |
1057 | 0 | } |
1058 | | |
1059 | 0 | return true; // CC didn't match. |
1060 | 0 | } |
1061 | | |
1062 | | |
1063 | | bool llvm::CC_AArch64_Win64PCS(unsigned ValNo, MVT ValVT, |
1064 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1065 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1066 | |
|
1067 | 0 | if (LocVT == MVT::iPTR) { |
1068 | 0 | LocVT = MVT::i64; |
1069 | 0 | LocInfo = CCValAssign::BCvt; |
1070 | 0 | } |
1071 | |
|
1072 | 0 | if (LocVT == MVT::v2f32) { |
1073 | 0 | LocVT = MVT::v2i32; |
1074 | 0 | LocInfo = CCValAssign::BCvt; |
1075 | 0 | } |
1076 | |
|
1077 | 0 | if (LocVT == MVT::v2f64 || |
1078 | 0 | LocVT == MVT::v4f32) { |
1079 | 0 | LocVT = MVT::v2i64; |
1080 | 0 | LocInfo = CCValAssign::BCvt; |
1081 | 0 | } |
1082 | |
|
1083 | 0 | if (State.getMachineFunction().getDataLayout().isBigEndian()) { |
1084 | 0 | if (LocVT == MVT::v2i32 || |
1085 | 0 | LocVT == MVT::v2f32 || |
1086 | 0 | LocVT == MVT::v4i16 || |
1087 | 0 | LocVT == MVT::v4f16 || |
1088 | 0 | LocVT == MVT::v4bf16 || |
1089 | 0 | LocVT == MVT::v8i8) { |
1090 | 0 | LocVT = MVT::f64; |
1091 | 0 | LocInfo = CCValAssign::BCvt; |
1092 | 0 | } |
1093 | 0 | } |
1094 | |
|
1095 | 0 | if (State.getMachineFunction().getDataLayout().isBigEndian()) { |
1096 | 0 | if (LocVT == MVT::v2i64 || |
1097 | 0 | LocVT == MVT::v2f64 || |
1098 | 0 | LocVT == MVT::v4i32 || |
1099 | 0 | LocVT == MVT::v4f32 || |
1100 | 0 | LocVT == MVT::v8i16 || |
1101 | 0 | LocVT == MVT::v8f16 || |
1102 | 0 | LocVT == MVT::v8bf16 || |
1103 | 0 | LocVT == MVT::v16i8) { |
1104 | 0 | LocVT = MVT::f128; |
1105 | 0 | LocInfo = CCValAssign::BCvt; |
1106 | 0 | } |
1107 | 0 | } |
1108 | |
|
1109 | 0 | if (ArgFlags.isInReg()) { |
1110 | 0 | if (LocVT == MVT::i64) { |
1111 | 0 | if (ArgFlags.isSRet()) { |
1112 | 0 | if (LocVT == MVT::i64) { |
1113 | 0 | static const MCPhysReg RegList1[] = { |
1114 | 0 | AArch64::X0, AArch64::X1 |
1115 | 0 | }; |
1116 | 0 | if (unsigned Reg = State.AllocateReg(RegList1)) { |
1117 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1118 | 0 | return false; |
1119 | 0 | } |
1120 | 0 | } |
1121 | 0 | } |
1122 | 0 | } |
1123 | 0 | } |
1124 | | |
1125 | 0 | if (ArgFlags.isSRet()) { |
1126 | 0 | if (LocVT == MVT::i64) { |
1127 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X8)) { |
1128 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1129 | 0 | return false; |
1130 | 0 | } |
1131 | 0 | } |
1132 | 0 | } |
1133 | | |
1134 | 0 | if (ArgFlags.isByVal()) { |
1135 | 0 | State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 8, Align(8), ArgFlags); |
1136 | 0 | return false; |
1137 | 0 | } |
1138 | | |
1139 | 0 | if (ArgFlags.isSwiftSelf()) { |
1140 | 0 | if (LocVT == MVT::i64) { |
1141 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X20)) { |
1142 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1143 | 0 | return false; |
1144 | 0 | } |
1145 | 0 | } |
1146 | 0 | } |
1147 | | |
1148 | 0 | if (ArgFlags.isSwiftError()) { |
1149 | 0 | if (LocVT == MVT::i64) { |
1150 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X21)) { |
1151 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1152 | 0 | return false; |
1153 | 0 | } |
1154 | 0 | } |
1155 | 0 | } |
1156 | | |
1157 | 0 | if (ArgFlags.isSwiftAsync()) { |
1158 | 0 | if (LocVT == MVT::i64) { |
1159 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X22)) { |
1160 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1161 | 0 | return false; |
1162 | 0 | } |
1163 | 0 | } |
1164 | 0 | } |
1165 | | |
1166 | 0 | if (ArgFlags.isInConsecutiveRegs()) { |
1167 | 0 | if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1168 | 0 | return false; |
1169 | 0 | } |
1170 | | |
1171 | 0 | if (LocVT == MVT::nxv16i8 || |
1172 | 0 | LocVT == MVT::nxv8i16 || |
1173 | 0 | LocVT == MVT::nxv4i32 || |
1174 | 0 | LocVT == MVT::nxv2i64 || |
1175 | 0 | LocVT == MVT::nxv2f16 || |
1176 | 0 | LocVT == MVT::nxv4f16 || |
1177 | 0 | LocVT == MVT::nxv8f16 || |
1178 | 0 | LocVT == MVT::nxv2bf16 || |
1179 | 0 | LocVT == MVT::nxv4bf16 || |
1180 | 0 | LocVT == MVT::nxv8bf16 || |
1181 | 0 | LocVT == MVT::nxv2f32 || |
1182 | 0 | LocVT == MVT::nxv4f32 || |
1183 | 0 | LocVT == MVT::nxv2f64) { |
1184 | 0 | static const MCPhysReg RegList2[] = { |
1185 | 0 | AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 |
1186 | 0 | }; |
1187 | 0 | if (unsigned Reg = State.AllocateReg(RegList2)) { |
1188 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1189 | 0 | return false; |
1190 | 0 | } |
1191 | 0 | } |
1192 | | |
1193 | 0 | if (LocVT == MVT::nxv16i8 || |
1194 | 0 | LocVT == MVT::nxv8i16 || |
1195 | 0 | LocVT == MVT::nxv4i32 || |
1196 | 0 | LocVT == MVT::nxv2i64 || |
1197 | 0 | LocVT == MVT::nxv2f16 || |
1198 | 0 | LocVT == MVT::nxv4f16 || |
1199 | 0 | LocVT == MVT::nxv8f16 || |
1200 | 0 | LocVT == MVT::nxv2bf16 || |
1201 | 0 | LocVT == MVT::nxv4bf16 || |
1202 | 0 | LocVT == MVT::nxv8bf16 || |
1203 | 0 | LocVT == MVT::nxv2f32 || |
1204 | 0 | LocVT == MVT::nxv4f32 || |
1205 | 0 | LocVT == MVT::nxv2f64) { |
1206 | 0 | LocVT = MVT::i64; |
1207 | 0 | LocInfo = CCValAssign::Indirect; |
1208 | 0 | } |
1209 | |
|
1210 | 0 | if (LocVT == MVT::nxv1i1 || |
1211 | 0 | LocVT == MVT::nxv2i1 || |
1212 | 0 | LocVT == MVT::nxv4i1 || |
1213 | 0 | LocVT == MVT::nxv8i1 || |
1214 | 0 | LocVT == MVT::nxv16i1 || |
1215 | 0 | LocVT == MVT::aarch64svcount) { |
1216 | 0 | static const MCPhysReg RegList3[] = { |
1217 | 0 | AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3 |
1218 | 0 | }; |
1219 | 0 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
1220 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1221 | 0 | return false; |
1222 | 0 | } |
1223 | 0 | } |
1224 | | |
1225 | 0 | if (LocVT == MVT::nxv1i1 || |
1226 | 0 | LocVT == MVT::nxv2i1 || |
1227 | 0 | LocVT == MVT::nxv4i1 || |
1228 | 0 | LocVT == MVT::nxv8i1 || |
1229 | 0 | LocVT == MVT::nxv16i1 || |
1230 | 0 | LocVT == MVT::aarch64svcount) { |
1231 | 0 | LocVT = MVT::i64; |
1232 | 0 | LocInfo = CCValAssign::Indirect; |
1233 | 0 | } |
1234 | |
|
1235 | 0 | if (LocVT == MVT::i1 || |
1236 | 0 | LocVT == MVT::i8 || |
1237 | 0 | LocVT == MVT::i16) { |
1238 | 0 | LocVT = MVT::i32; |
1239 | 0 | if (ArgFlags.isSExt()) |
1240 | 0 | LocInfo = CCValAssign::SExt; |
1241 | 0 | else if (ArgFlags.isZExt()) |
1242 | 0 | LocInfo = CCValAssign::ZExt; |
1243 | 0 | else |
1244 | 0 | LocInfo = CCValAssign::AExt; |
1245 | 0 | } |
1246 | |
|
1247 | 0 | if (LocVT == MVT::i32) { |
1248 | 0 | static const MCPhysReg RegList4[] = { |
1249 | 0 | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
1250 | 0 | }; |
1251 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
1252 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1253 | 0 | return false; |
1254 | 0 | } |
1255 | 0 | } |
1256 | | |
1257 | 0 | if (LocVT == MVT::i64) { |
1258 | 0 | if (ArgFlags.isSplit()) { |
1259 | 0 | static const MCPhysReg RegList5[] = { |
1260 | 0 | AArch64::X0, AArch64::X2, AArch64::X4, AArch64::X6 |
1261 | 0 | }; |
1262 | 0 | static const MCPhysReg RegList6[] = { |
1263 | 0 | AArch64::X0, AArch64::X1, AArch64::X3, AArch64::X5 |
1264 | 0 | }; |
1265 | 0 | if (unsigned Reg = State.AllocateReg(RegList5, RegList6)) { |
1266 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1267 | 0 | return false; |
1268 | 0 | } |
1269 | 0 | } |
1270 | 0 | } |
1271 | | |
1272 | 0 | if (LocVT == MVT::i64) { |
1273 | 0 | if (ArgFlags.isSplit()) { |
1274 | 0 | static const MCPhysReg ShadowRegList7[] = { |
1275 | 0 | AArch64::X7 |
1276 | 0 | }; |
1277 | 0 | int64_t Offset8 = State.AllocateStack(8, Align(16), ShadowRegList7); |
1278 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset8, LocVT, LocInfo)); |
1279 | 0 | return false; |
1280 | 0 | } |
1281 | 0 | } |
1282 | | |
1283 | 0 | if (LocVT == MVT::i64) { |
1284 | 0 | static const MCPhysReg RegList9[] = { |
1285 | 0 | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
1286 | 0 | }; |
1287 | 0 | if (unsigned Reg = State.AllocateReg(RegList9)) { |
1288 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1289 | 0 | return false; |
1290 | 0 | } |
1291 | 0 | } |
1292 | | |
1293 | 0 | if (LocVT == MVT::f16) { |
1294 | 0 | static const MCPhysReg RegList10[] = { |
1295 | 0 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 |
1296 | 0 | }; |
1297 | 0 | if (unsigned Reg = State.AllocateReg(RegList10)) { |
1298 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1299 | 0 | return false; |
1300 | 0 | } |
1301 | 0 | } |
1302 | | |
1303 | 0 | if (LocVT == MVT::bf16) { |
1304 | 0 | static const MCPhysReg RegList11[] = { |
1305 | 0 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 |
1306 | 0 | }; |
1307 | 0 | if (unsigned Reg = State.AllocateReg(RegList11)) { |
1308 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1309 | 0 | return false; |
1310 | 0 | } |
1311 | 0 | } |
1312 | | |
1313 | 0 | if (LocVT == MVT::f32) { |
1314 | 0 | static const MCPhysReg RegList12[] = { |
1315 | 0 | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 |
1316 | 0 | }; |
1317 | 0 | if (unsigned Reg = State.AllocateReg(RegList12)) { |
1318 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1319 | 0 | return false; |
1320 | 0 | } |
1321 | 0 | } |
1322 | | |
1323 | 0 | if (LocVT == MVT::f64) { |
1324 | 0 | static const MCPhysReg RegList13[] = { |
1325 | 0 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
1326 | 0 | }; |
1327 | 0 | if (unsigned Reg = State.AllocateReg(RegList13)) { |
1328 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1329 | 0 | return false; |
1330 | 0 | } |
1331 | 0 | } |
1332 | | |
1333 | 0 | if (LocVT == MVT::v1i64 || |
1334 | 0 | LocVT == MVT::v2i32 || |
1335 | 0 | LocVT == MVT::v4i16 || |
1336 | 0 | LocVT == MVT::v8i8 || |
1337 | 0 | LocVT == MVT::v1f64 || |
1338 | 0 | LocVT == MVT::v2f32 || |
1339 | 0 | LocVT == MVT::v4f16 || |
1340 | 0 | LocVT == MVT::v4bf16) { |
1341 | 0 | static const MCPhysReg RegList14[] = { |
1342 | 0 | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
1343 | 0 | }; |
1344 | 0 | if (unsigned Reg = State.AllocateReg(RegList14)) { |
1345 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1346 | 0 | return false; |
1347 | 0 | } |
1348 | 0 | } |
1349 | | |
1350 | 0 | if (LocVT == MVT::f128 || |
1351 | 0 | LocVT == MVT::v2i64 || |
1352 | 0 | LocVT == MVT::v4i32 || |
1353 | 0 | LocVT == MVT::v8i16 || |
1354 | 0 | LocVT == MVT::v16i8 || |
1355 | 0 | LocVT == MVT::v4f32 || |
1356 | 0 | LocVT == MVT::v2f64 || |
1357 | 0 | LocVT == MVT::v8f16 || |
1358 | 0 | LocVT == MVT::v8bf16) { |
1359 | 0 | static const MCPhysReg RegList15[] = { |
1360 | 0 | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
1361 | 0 | }; |
1362 | 0 | if (unsigned Reg = State.AllocateReg(RegList15)) { |
1363 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1364 | 0 | return false; |
1365 | 0 | } |
1366 | 0 | } |
1367 | | |
1368 | 0 | if (LocVT == MVT::i1 || |
1369 | 0 | LocVT == MVT::i8 || |
1370 | 0 | LocVT == MVT::i16 || |
1371 | 0 | LocVT == MVT::f16 || |
1372 | 0 | LocVT == MVT::bf16) { |
1373 | 0 | int64_t Offset16 = State.AllocateStack(8, Align(8)); |
1374 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset16, LocVT, LocInfo)); |
1375 | 0 | return false; |
1376 | 0 | } |
1377 | | |
1378 | 0 | if (LocVT == MVT::i32 || |
1379 | 0 | LocVT == MVT::f32) { |
1380 | 0 | int64_t Offset17 = State.AllocateStack(8, Align(8)); |
1381 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset17, LocVT, LocInfo)); |
1382 | 0 | return false; |
1383 | 0 | } |
1384 | | |
1385 | 0 | if (LocVT == MVT::i64 || |
1386 | 0 | LocVT == MVT::f64 || |
1387 | 0 | LocVT == MVT::v1f64 || |
1388 | 0 | LocVT == MVT::v2f32 || |
1389 | 0 | LocVT == MVT::v1i64 || |
1390 | 0 | LocVT == MVT::v2i32 || |
1391 | 0 | LocVT == MVT::v4i16 || |
1392 | 0 | LocVT == MVT::v8i8 || |
1393 | 0 | LocVT == MVT::v4f16 || |
1394 | 0 | LocVT == MVT::v4bf16) { |
1395 | 0 | int64_t Offset18 = State.AllocateStack(8, Align(8)); |
1396 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset18, LocVT, LocInfo)); |
1397 | 0 | return false; |
1398 | 0 | } |
1399 | | |
1400 | 0 | if (LocVT == MVT::f128 || |
1401 | 0 | LocVT == MVT::v2i64 || |
1402 | 0 | LocVT == MVT::v4i32 || |
1403 | 0 | LocVT == MVT::v8i16 || |
1404 | 0 | LocVT == MVT::v16i8 || |
1405 | 0 | LocVT == MVT::v4f32 || |
1406 | 0 | LocVT == MVT::v2f64 || |
1407 | 0 | LocVT == MVT::v8f16 || |
1408 | 0 | LocVT == MVT::v8bf16) { |
1409 | 0 | int64_t Offset19 = State.AllocateStack(16, Align(16)); |
1410 | 0 | State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset19, LocVT, LocInfo)); |
1411 | 0 | return false; |
1412 | 0 | } |
1413 | | |
1414 | 0 | return true; // CC didn't match. |
1415 | 0 | } |
1416 | | |
1417 | | |
1418 | | bool llvm::CC_AArch64_Win64_CFGuard_Check(unsigned ValNo, MVT ValVT, |
1419 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1420 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1421 | |
|
1422 | 0 | if (LocVT == MVT::i64) { |
1423 | 0 | if (unsigned Reg = State.AllocateReg(AArch64::X15)) { |
1424 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1425 | 0 | return false; |
1426 | 0 | } |
1427 | 0 | } |
1428 | | |
1429 | 0 | return true; // CC didn't match. |
1430 | 0 | } |
1431 | | |
1432 | | |
1433 | | bool llvm::CC_AArch64_Win64_VarArg(unsigned ValNo, MVT ValVT, |
1434 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1435 | 0 | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1436 | |
|
1437 | 0 | if (LocVT == MVT::f16 || |
1438 | 0 | LocVT == MVT::bf16) { |
1439 | 0 | LocVT = MVT::i16; |
1440 | 0 | LocInfo = CCValAssign::BCvt; |
1441 | 0 | } |
1442 | |
|
1443 | 0 | if (LocVT == MVT::f32) { |
1444 | 0 | LocVT = MVT::i32; |
1445 | 0 | LocInfo = CCValAssign::BCvt; |
1446 | 0 | } |
1447 | |
|
1448 | 0 | if (LocVT == MVT::f64) { |
1449 | 0 | LocVT = MVT::i64; |
1450 | 0 | LocInfo = CCValAssign::BCvt; |
1451 | 0 | } |
1452 | |
|
1453 | 0 | if (!CC_AArch64_Win64PCS(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1454 | 0 | return false; |
1455 | | |
1456 | 0 | return true; // CC didn't match. |
1457 | 0 | } |
1458 | | |
1459 | | |
1460 | | bool llvm::RetCC_AArch64_AAPCS(unsigned ValNo, MVT ValVT, |
1461 | | MVT LocVT, CCValAssign::LocInfo LocInfo, |
1462 | 114k | ISD::ArgFlagsTy ArgFlags, CCState &State) { |
1463 | | |
1464 | 114k | if (LocVT == MVT::iPTR) { |
1465 | 0 | LocVT = MVT::i64; |
1466 | 0 | LocInfo = CCValAssign::BCvt; |
1467 | 0 | } |
1468 | | |
1469 | 114k | if (LocVT == MVT::v2f32) { |
1470 | 1.24k | LocVT = MVT::v2i32; |
1471 | 1.24k | LocInfo = CCValAssign::BCvt; |
1472 | 1.24k | } |
1473 | | |
1474 | 114k | if (LocVT == MVT::v2f64 || |
1475 | 114k | LocVT == MVT::v4f32) { |
1476 | 6.59k | LocVT = MVT::v2i64; |
1477 | 6.59k | LocInfo = CCValAssign::BCvt; |
1478 | 6.59k | } |
1479 | | |
1480 | 114k | if (ArgFlags.isInConsecutiveRegs()) { |
1481 | 5 | if (CC_AArch64_Custom_Block(ValNo, ValVT, LocVT, LocInfo, ArgFlags, State)) |
1482 | 0 | return false; |
1483 | 5 | } |
1484 | | |
1485 | 114k | if (ArgFlags.isSwiftError()) { |
1486 | 8 | if (LocVT == MVT::i64) { |
1487 | 8 | if (unsigned Reg = State.AllocateReg(AArch64::X21)) { |
1488 | 8 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1489 | 8 | return false; |
1490 | 8 | } |
1491 | 8 | } |
1492 | 8 | } |
1493 | | |
1494 | 114k | if (State.getMachineFunction().getDataLayout().isBigEndian()) { |
1495 | 0 | if (LocVT == MVT::v2i32 || |
1496 | 0 | LocVT == MVT::v2f32 || |
1497 | 0 | LocVT == MVT::v4i16 || |
1498 | 0 | LocVT == MVT::v4f16 || |
1499 | 0 | LocVT == MVT::v4bf16 || |
1500 | 0 | LocVT == MVT::v8i8) { |
1501 | 0 | LocVT = MVT::f64; |
1502 | 0 | LocInfo = CCValAssign::BCvt; |
1503 | 0 | } |
1504 | 0 | } |
1505 | | |
1506 | 114k | if (State.getMachineFunction().getDataLayout().isBigEndian()) { |
1507 | 0 | if (LocVT == MVT::v2i64 || |
1508 | 0 | LocVT == MVT::v2f64 || |
1509 | 0 | LocVT == MVT::v4i32 || |
1510 | 0 | LocVT == MVT::v4f32 || |
1511 | 0 | LocVT == MVT::v8i16 || |
1512 | 0 | LocVT == MVT::v8f16 || |
1513 | 0 | LocVT == MVT::v8bf16 || |
1514 | 0 | LocVT == MVT::v16i8) { |
1515 | 0 | LocVT = MVT::f128; |
1516 | 0 | LocInfo = CCValAssign::BCvt; |
1517 | 0 | } |
1518 | 0 | } |
1519 | | |
1520 | 114k | if (LocVT == MVT::i1 || |
1521 | 114k | LocVT == MVT::i8 || |
1522 | 114k | LocVT == MVT::i16) { |
1523 | 36 | LocVT = MVT::i32; |
1524 | 36 | if (ArgFlags.isSExt()) |
1525 | 0 | LocInfo = CCValAssign::SExt; |
1526 | 36 | else if (ArgFlags.isZExt()) |
1527 | 0 | LocInfo = CCValAssign::ZExt; |
1528 | 36 | else |
1529 | 36 | LocInfo = CCValAssign::AExt; |
1530 | 36 | } |
1531 | | |
1532 | 114k | if (LocVT == MVT::i32) { |
1533 | 42.3k | static const MCPhysReg RegList1[] = { |
1534 | 42.3k | AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7 |
1535 | 42.3k | }; |
1536 | 42.3k | if (unsigned Reg = State.AllocateReg(RegList1)) { |
1537 | 42.2k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1538 | 42.2k | return false; |
1539 | 42.2k | } |
1540 | 42.3k | } |
1541 | | |
1542 | 72.2k | if (LocVT == MVT::i64) { |
1543 | 13.0k | static const MCPhysReg RegList2[] = { |
1544 | 13.0k | AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7 |
1545 | 13.0k | }; |
1546 | 13.0k | if (unsigned Reg = State.AllocateReg(RegList2)) { |
1547 | 12.9k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1548 | 12.9k | return false; |
1549 | 12.9k | } |
1550 | 13.0k | } |
1551 | | |
1552 | 59.3k | if (LocVT == MVT::f16) { |
1553 | 482 | static const MCPhysReg RegList3[] = { |
1554 | 482 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 |
1555 | 482 | }; |
1556 | 482 | if (unsigned Reg = State.AllocateReg(RegList3)) { |
1557 | 482 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1558 | 482 | return false; |
1559 | 482 | } |
1560 | 482 | } |
1561 | | |
1562 | 58.8k | if (LocVT == MVT::bf16) { |
1563 | 0 | static const MCPhysReg RegList4[] = { |
1564 | 0 | AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7 |
1565 | 0 | }; |
1566 | 0 | if (unsigned Reg = State.AllocateReg(RegList4)) { |
1567 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1568 | 0 | return false; |
1569 | 0 | } |
1570 | 0 | } |
1571 | | |
1572 | 58.8k | if (LocVT == MVT::f32) { |
1573 | 9.81k | static const MCPhysReg RegList5[] = { |
1574 | 9.81k | AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7 |
1575 | 9.81k | }; |
1576 | 9.81k | if (unsigned Reg = State.AllocateReg(RegList5)) { |
1577 | 9.81k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1578 | 9.81k | return false; |
1579 | 9.81k | } |
1580 | 9.81k | } |
1581 | | |
1582 | 49.0k | if (LocVT == MVT::f64) { |
1583 | 5.75k | static const MCPhysReg RegList6[] = { |
1584 | 5.75k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
1585 | 5.75k | }; |
1586 | 5.75k | if (unsigned Reg = State.AllocateReg(RegList6)) { |
1587 | 5.75k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1588 | 5.75k | return false; |
1589 | 5.75k | } |
1590 | 5.75k | } |
1591 | | |
1592 | 43.2k | if (LocVT == MVT::v1i64 || |
1593 | 43.2k | LocVT == MVT::v2i32 || |
1594 | 43.2k | LocVT == MVT::v4i16 || |
1595 | 43.2k | LocVT == MVT::v8i8 || |
1596 | 43.2k | LocVT == MVT::v1f64 || |
1597 | 43.2k | LocVT == MVT::v2f32 || |
1598 | 43.2k | LocVT == MVT::v4f16 || |
1599 | 43.2k | LocVT == MVT::v4bf16) { |
1600 | 7.15k | static const MCPhysReg RegList7[] = { |
1601 | 7.15k | AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7 |
1602 | 7.15k | }; |
1603 | 7.15k | if (unsigned Reg = State.AllocateReg(RegList7)) { |
1604 | 7.15k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1605 | 7.15k | return false; |
1606 | 7.15k | } |
1607 | 7.15k | } |
1608 | | |
1609 | 36.1k | if (LocVT == MVT::f128 || |
1610 | 36.1k | LocVT == MVT::v2i64 || |
1611 | 36.1k | LocVT == MVT::v4i32 || |
1612 | 36.1k | LocVT == MVT::v8i16 || |
1613 | 36.1k | LocVT == MVT::v16i8 || |
1614 | 36.1k | LocVT == MVT::v4f32 || |
1615 | 36.1k | LocVT == MVT::v2f64 || |
1616 | 36.1k | LocVT == MVT::v8f16 || |
1617 | 36.1k | LocVT == MVT::v8bf16) { |
1618 | 36.0k | static const MCPhysReg RegList8[] = { |
1619 | 36.0k | AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7 |
1620 | 36.0k | }; |
1621 | 36.0k | if (unsigned Reg = State.AllocateReg(RegList8)) { |
1622 | 36.0k | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1623 | 36.0k | return false; |
1624 | 36.0k | } |
1625 | 36.0k | } |
1626 | | |
1627 | 109 | if (LocVT == MVT::nxv16i8 || |
1628 | 109 | LocVT == MVT::nxv8i16 || |
1629 | 109 | LocVT == MVT::nxv4i32 || |
1630 | 109 | LocVT == MVT::nxv2i64 || |
1631 | 109 | LocVT == MVT::nxv2f16 || |
1632 | 109 | LocVT == MVT::nxv4f16 || |
1633 | 109 | LocVT == MVT::nxv8f16 || |
1634 | 109 | LocVT == MVT::nxv2bf16 || |
1635 | 109 | LocVT == MVT::nxv4bf16 || |
1636 | 109 | LocVT == MVT::nxv8bf16 || |
1637 | 109 | LocVT == MVT::nxv2f32 || |
1638 | 109 | LocVT == MVT::nxv4f32 || |
1639 | 109 | LocVT == MVT::nxv2f64) { |
1640 | 0 | static const MCPhysReg RegList9[] = { |
1641 | 0 | AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 |
1642 | 0 | }; |
1643 | 0 | if (unsigned Reg = State.AllocateReg(RegList9)) { |
1644 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1645 | 0 | return false; |
1646 | 0 | } |
1647 | 0 | } |
1648 | | |
1649 | 109 | if (LocVT == MVT::nxv1i1 || |
1650 | 109 | LocVT == MVT::nxv2i1 || |
1651 | 109 | LocVT == MVT::nxv4i1 || |
1652 | 109 | LocVT == MVT::nxv8i1 || |
1653 | 109 | LocVT == MVT::nxv16i1 || |
1654 | 109 | LocVT == MVT::aarch64svcount) { |
1655 | 0 | static const MCPhysReg RegList10[] = { |
1656 | 0 | AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3 |
1657 | 0 | }; |
1658 | 0 | if (unsigned Reg = State.AllocateReg(RegList10)) { |
1659 | 0 | State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); |
1660 | 0 | return false; |
1661 | 0 | } |
1662 | 0 | } |
1663 | | |
1664 | 109 | return true; // CC didn't match. |
1665 | 109 | } |
1666 | | |
1667 | | #else |
1668 | | |
1669 | | const MCRegister CC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X18, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 }; |
1670 | | const MCRegister CC_AArch64_Arm64EC_VarArg_ArgRegs[] = { AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X8 }; |
1671 | | const MCRegister CC_AArch64_DarwinPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8 }; |
1672 | | const MCRegister CC_AArch64_DarwinPCS_ILP32_VarArg_ArgRegs[] = { 0 }; |
1673 | | const MCRegister CC_AArch64_DarwinPCS_VarArg_ArgRegs[] = { 0 }; |
1674 | | const MCRegister CC_AArch64_GHC_ArgRegs[] = { AArch64::D12, AArch64::D13, AArch64::D14, AArch64::D15, AArch64::Q4, AArch64::Q5, AArch64::S10, AArch64::S11, AArch64::S8, AArch64::S9, AArch64::X19, AArch64::X20, AArch64::X21, AArch64::X22, AArch64::X23, AArch64::X24, AArch64::X25, AArch64::X26, AArch64::X27, AArch64::X28 }; |
1675 | | const MCRegister CC_AArch64_Win64PCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::X8, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 }; |
1676 | | const MCRegister CC_AArch64_Win64_CFGuard_Check_ArgRegs[] = { AArch64::X15 }; |
1677 | | const MCRegister CC_AArch64_Win64_VarArg_ArgRegs[] = { 0 }; |
1678 | | const MCRegister RetCC_AArch64_AAPCS_ArgRegs[] = { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4, AArch64::D5, AArch64::D6, AArch64::D7, AArch64::H0, AArch64::H1, AArch64::H2, AArch64::H3, AArch64::H4, AArch64::H5, AArch64::H6, AArch64::H7, AArch64::P0, AArch64::P1, AArch64::P2, AArch64::P3, AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64::Q7, AArch64::S0, AArch64::S1, AArch64::S2, AArch64::S3, AArch64::S4, AArch64::S5, AArch64::S6, AArch64::S7, AArch64::W0, AArch64::W1, AArch64::W2, AArch64::W3, AArch64::W4, AArch64::W5, AArch64::W6, AArch64::W7, AArch64::X0, AArch64::X1, AArch64::X2, AArch64::X3, AArch64::X4, AArch64::X5, AArch64::X6, AArch64::X7, AArch64::Z0, AArch64::Z1, AArch64::Z2, AArch64::Z3, AArch64::Z4, AArch64::Z5, AArch64::Z6, AArch64::Z7 }; |
1679 | | |
1680 | | // Registers used by Swift. |
1681 | | const MCRegister CC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 }; |
1682 | | const MCRegister CC_AArch64_DarwinPCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 }; |
1683 | | const MCRegister CC_AArch64_Win64PCS_Swift_ArgRegs[] = { AArch64::X20, AArch64::X21, AArch64::X22 }; |
1684 | | const MCRegister RetCC_AArch64_AAPCS_Swift_ArgRegs[] = { AArch64::X21 }; |
1685 | | |
1686 | | #endif // CC_REGISTER_LIST |